diff --git a/FPGA_firmware/hit20v3.qar b/FPGA_firmware/hit20v3.qar new file mode 100644 index 0000000..29a9d90 Binary files /dev/null and b/FPGA_firmware/hit20v3.qar differ diff --git a/FPGA_nios/.gitignore b/FPGA_nios/.gitignore new file mode 100644 index 0000000..3171365 --- /dev/null +++ b/FPGA_nios/.gitignore @@ -0,0 +1,37 @@ +# Eclipse project files +.classpath +.project +.settings/ + +# Build output +Debug/ +Release/ +*.o +*.elf +*.bin +*.hex +*.srec +*.map +*.lst +*.d + +# Other generated files +*.log +*.tmp +*.swp +*.bak + +# Temporary files +*.tmp +*.user + +# Eclipse metadata +.metadata/ + +# OS-specific files +.DS_Store +Thumbs.db + +# Other +*.lst +*.pt diff --git a/FPGA_nios/hit_pat/.cproject b/FPGA_nios/hit_pat/.cproject new file mode 100644 index 0000000..49ceae4 --- /dev/null +++ b/FPGA_nios/hit_pat/.cproject @@ -0,0 +1,91 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + wsl + make + mem_init_install + true + false + false + + + wsl + make + mem_init_generate + true + false + false + + + wsl + make + help + true + false + false + + + + + + + + + + diff --git a/FPGA_nios/hit_pat/.force_relink b/FPGA_nios/hit_pat/.force_relink new file mode 100644 index 0000000..e69de29 diff --git a/FPGA_nios/hit_pat/create-this-app b/FPGA_nios/hit_pat/create-this-app new file mode 100644 index 0000000..0bd09c1 --- /dev/null +++ b/FPGA_nios/hit_pat/create-this-app @@ -0,0 +1,131 @@ +#!/bin/bash +# +# This script creates the simple_socket_server application in this directory. + + +BSP_DIR=../hit_pat_bsp +QUARTUS_PROJECT_DIR=../../ +NIOS2_APP_GEN_ARGS="--elf-name hit_pat.elf --set OBJDUMP_INCLUDE_SOURCE 1 --src-files alt_error_handler.c iniche_init.c led.c network_utilities.c simple_socket_server.c tse_my_system.c" + +# If script is launched from Windows through Windows Subsystem for Linux (WSL). +# The adjust-path macro converts absolute windows +# paths into unix style paths (Example: c:/dir -> /c/dir). This will ensure +# paths are readable. +uname=$(uname -r) +if [[ $uname =~ "Microsoft" ]]; then + _IS_WSL=1 + windows_exe=.exe +fi + +adjust_path() { + if [ "${_IS_WSL}" = "1" ] && [[ ! $1 =~ ^\/mnt\/* ]]; then + echo "$(wslpath -u "$1")" + else + echo "$1" + fi +} + +# First, check to see if $SOPC_KIT_NIOS2 environmental variable is set. +# This variable is required for the command line tools to execute correctly. +if [ -z "${SOPC_KIT_NIOS2}" ] +then + echo Required \$SOPC_KIT_NIOS2 Environmental Variable is not set! + exit 1 +fi + + +# Also make sure that the APP has not been created already. Check for +# existence of Makefile in the app directory +if [ -f ./Makefile ] +then + echo Application has already been created! Delete Makefile if you want to create a new application makefile + exit 1 +fi + + +# We are selecting ucosii_net bsp because it supports this application. +# Check to see if the ucosii_net has already been generated by checking for +# existence of the public.mk file. If not, we need to run +# create-this-bsp file to generate the bsp. +if [ ! -f ${BSP_DIR}/public.mk ]; then + # Since BSP doesn't exist, create the BSP + # Pass any command line arguments passed to this script to the BSP. + pushd "$(adjust_path ${BSP_DIR})" >> /dev/null + ./create-this-bsp "$@" || { + echo "create-this-bsp failed" + exit 1 + } + popd >> /dev/null +fi + + +# Don't run make if create-this-app script is called with --no-make arg +SKIP_MAKE= +while [ $# -gt 0 ] +do + case "$1" in + --no-make) + SKIP_MAKE=1 + ;; + esac + shift +done + + +# Now we also need to go copy the sources for this application to the +# local directory. +find "${SOPC_KIT_NIOS2}/examples/software/simple_socket_server/" -name '*.c' -or -name '*.h' -or -name 'hostfs*' | xargs -i cp -L {} ./ || { + echo "failed during copying example source files" + exit 1 +} + +find "${SOPC_KIT_NIOS2}/examples/software/simple_socket_server/" -name 'readme.txt' -or -name 'Readme.txt' | xargs -i cp -L {} ./ || { + echo "failed copying readme file" +} + +if [ -d "${SOPC_KIT_NIOS2}/examples/software/simple_socket_server/system" ] +then + cp -RL "${SOPC_KIT_NIOS2}/examples/software/simple_socket_server/system" . || { + echo "failed during copying project support files" + exit 1 + } +fi + +chmod -R +w . || { + echo "failed during changing file permissions" + exit 1 +} + +cmd="nios2-app-generate-makefile$windows_exe --bsp-dir ${BSP_DIR} --set QUARTUS_PROJECT_DIR=${QUARTUS_PROJECT_DIR} ${NIOS2_APP_GEN_ARGS}" + +echo "create-this-app: Running \"${cmd}\"" +$cmd || { + echo "nios2-app-generate-makefile failed" + exit 1 +} + +if [ -z "$SKIP_MAKE" ]; then + cmd="make" + + echo "create-this-app: Running \"$cmd\"" + $cmd || { + echo "make failed" + exit 1 + } + + echo + echo "To download and run the application:" + echo " 1. Make sure the board is connected to the system." + echo " 2. Run 'nios2-configure-sof ' to configure the FPGA with the hardware design." + echo " 3. If you have a stdio device, run 'nios2-terminal' in a different shell." + echo " 4. Run 'make download-elf' from the application directory." + echo + echo "To debug the application:" + echo " Import the project into Nios II Software Build Tools for Eclipse." + echo " Refer to Nios II Software Build Tools for Eclipse Documentation for more information." + echo + echo -e "" +fi + + +exit 0 diff --git a/FPGA_nios/hit_pat/hit_pat.objdump b/FPGA_nios/hit_pat/hit_pat.objdump new file mode 100644 index 0000000..ae87d1e --- /dev/null +++ b/FPGA_nios/hit_pat/hit_pat.objdump @@ -0,0 +1,106020 @@ + +hit_pat.elf: file format elf32-littlenios2 +hit_pat.elf +architecture: nios2:r1, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x08000338 + +Program Header: + LOAD off 0x00000000 vaddr 0x08000000 paddr 0x08000000 align 2**12 + filesz 0x0004cb8c memsz 0x0005e59c flags rwx + LOAD off 0x0004d000 vaddr 0x14000000 paddr 0x14000000 align 2**12 + filesz 0x00000020 memsz 0x00000020 flags r-x + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .entry 00000020 14000000 14000000 0004d000 2**5 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .exceptions 00000218 08000120 08000120 00000120 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .text 00046670 08000338 08000338 00000338 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 3 .rodata 00004f6c 080469a8 080469a8 000469a8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .rwdata 0000126c 0804b920 0804b920 0004b920 2**4 + CONTENTS, ALLOC, LOAD, DATA, SMALL_DATA + 5 .bss 00011a10 0804cb8c 0804cb8c 0004cb8c 2**2 + ALLOC, SMALL_DATA + 6 .ddr3_ram 00000000 0805e59c 0805e59c 0004d020 2**0 + CONTENTS + 7 .ext_flash_avl_mem 00000000 14000020 14000020 0004d020 2**0 + CONTENTS + 8 .onchip_flash_data 00000000 18200000 18200000 0004d020 2**0 + CONTENTS + 9 .descriptor_memory 00000000 18400000 18400000 0004d020 2**0 + CONTENTS + 10 .calibration_ram 00000000 18403400 18403400 0004d020 2**0 + CONTENTS + 11 .comment 0000002c 00000000 00000000 0004d020 2**0 + CONTENTS, READONLY + 12 .debug_aranges 00001c78 00000000 00000000 0004d050 2**3 + CONTENTS, READONLY, DEBUGGING + 13 .debug_info 0010e51e 00000000 00000000 0004ecc8 2**0 + CONTENTS, READONLY, DEBUGGING + 14 .debug_abbrev 00021537 00000000 00000000 0015d1e6 2**0 + CONTENTS, READONLY, DEBUGGING + 15 .debug_line 0003ca4d 00000000 00000000 0017e71d 2**0 + CONTENTS, READONLY, DEBUGGING + 16 .debug_frame 00008900 00000000 00000000 001bb16c 2**2 + CONTENTS, READONLY, DEBUGGING + 17 .debug_str 0000c2e6 00000000 00000000 001c3a6c 2**0 + CONTENTS, READONLY, DEBUGGING + 18 .debug_loc 00022905 00000000 00000000 001cfd52 2**0 + CONTENTS, READONLY, DEBUGGING + 19 .debug_alt_sim_info 00000060 00000000 00000000 001f2658 2**2 + CONTENTS, READONLY, DEBUGGING + 20 .debug_ranges 000021b8 00000000 00000000 001f26b8 2**3 + CONTENTS, READONLY, DEBUGGING + 21 .thread_model 00000006 00000000 00000000 001fec83 2**0 + CONTENTS, READONLY + 22 .cpu 00000003 00000000 00000000 001fec89 2**0 + CONTENTS, READONLY + 23 .qsys 00000001 00000000 00000000 001fec8c 2**0 + CONTENTS, READONLY + 24 .simulation_enabled 00000001 00000000 00000000 001fec8d 2**0 + CONTENTS, READONLY + 25 .sysid_hash 00000004 00000000 00000000 001fec8e 2**0 + CONTENTS, READONLY + 26 .sysid_base 00000004 00000000 00000000 001fec92 2**0 + CONTENTS, READONLY + 27 .sysid_time 00000004 00000000 00000000 001fec96 2**0 + CONTENTS, READONLY + 28 .stderr_dev 0000000a 00000000 00000000 001fec9a 2**0 + CONTENTS, READONLY + 29 .stdin_dev 0000000a 00000000 00000000 001feca4 2**0 + CONTENTS, READONLY + 30 .stdout_dev 0000000a 00000000 00000000 001fecae 2**0 + CONTENTS, READONLY + 31 .thread_model 00000006 00000000 00000000 001fecb8 2**0 + CONTENTS, READONLY + 32 .cpu 00000003 00000000 00000000 001fecbe 2**0 + CONTENTS, READONLY + 33 .qsys 00000001 00000000 00000000 001fecc1 2**0 + CONTENTS, READONLY + 34 .simulation_enabled 00000001 00000000 00000000 001fecc2 2**0 + CONTENTS, READONLY + 35 .sysid_hash 00000004 00000000 00000000 001fecc3 2**0 + CONTENTS, READONLY + 36 .sysid_base 00000004 00000000 00000000 001fecc7 2**0 + CONTENTS, READONLY + 37 .sysid_time 00000004 00000000 00000000 001feccb 2**0 + CONTENTS, READONLY + 38 .stderr_dev 0000000a 00000000 00000000 001feccf 2**0 + CONTENTS, READONLY + 39 .stdin_dev 0000000a 00000000 00000000 001fecd9 2**0 + CONTENTS, READONLY + 40 .stdout_dev 0000000a 00000000 00000000 001fece3 2**0 + CONTENTS, READONLY + 41 .sopc_system_name 00000005 00000000 00000000 001feced 2**0 + CONTENTS, READONLY + 42 .quartus_project_dir 0000001b 00000000 00000000 001fecf2 2**0 + CONTENTS, READONLY +SYMBOL TABLE: +14000000 l d .entry 00000000 .entry +08000120 l d .exceptions 00000000 .exceptions +08000338 l d .text 00000000 .text +080469a8 l d .rodata 00000000 .rodata +0804b920 l d .rwdata 00000000 .rwdata +0804cb8c l d .bss 00000000 .bss +0805e59c l d .ddr3_ram 00000000 .ddr3_ram +14000020 l d .ext_flash_avl_mem 00000000 .ext_flash_avl_mem +18200000 l d .onchip_flash_data 00000000 .onchip_flash_data +18400000 l d .descriptor_memory 00000000 .descriptor_memory +18403400 l d .calibration_ram 00000000 .calibration_ram +00000000 l d .comment 00000000 .comment +00000000 l d .debug_aranges 00000000 .debug_aranges +00000000 l d .debug_info 00000000 .debug_info +00000000 l d .debug_abbrev 00000000 .debug_abbrev +00000000 l d .debug_line 00000000 .debug_line +00000000 l d .debug_frame 00000000 .debug_frame +00000000 l d .debug_str 00000000 .debug_str +00000000 l d .debug_loc 00000000 .debug_loc +00000000 l d .debug_alt_sim_info 00000000 .debug_alt_sim_info +00000000 l d .debug_ranges 00000000 .debug_ranges +00000000 l df *ABS* 00000000 d:/hit20v3/software/hit_pat/software/hit_pat_bsp//obj/HAL/src/crt0.o +0800037c l .text 00000000 alt_after_alt_main +00000000 l df *ABS* 00000000 alt_irq_handler.c +00000000 l df *ABS* 00000000 alt_instruction_exception_entry.c +00000000 l df *ABS* 00000000 control.c +0804cb8c l O .bss 00000004 bytes_received.5850 +0804cb90 l O .bss 00000006 header.5849 +0804cb98 l O .bss 00000004 bytes_received.5856 +0804cd60 l O .bss 00000020 packet_data.5855 +00000000 l df *ABS* 00000000 main.c +00000000 l df *ABS* 00000000 network_utilities.c +00000000 l df *ABS* 00000000 sensor.c +00000000 l df *ABS* 00000000 socket_server.c +0804cba8 l O .bss 00000004 mutex +0804cd80 l O .bss 00000010 connections +00000000 l df *ABS* 00000000 tse_my_system.c +00000000 l df *ABS* 00000000 udpgen.c +00000000 l df *ABS* 00000000 utils.c +00000000 l df *ABS* 00000000 ctype_.c +00000000 l df *ABS* 00000000 getchar.c +00000000 l df *ABS* 00000000 impure.c +0804ba80 l O .rwdata 00000424 impure_data +00000000 l df *ABS* 00000000 printf.c +00000000 l df *ABS* 00000000 putchar.c +00000000 l df *ABS* 00000000 puts.c +00000000 l df *ABS* 00000000 strlen.c +00000000 l df *ABS* 00000000 vfprintf.c +08004fbc l F .text 000000c0 __sbprintf +080474ae l O .rodata 00000010 blanks.5226 +0804749e l O .rodata 00000010 zeroes.5227 +00000000 l df *ABS* 00000000 wsetup.c +00000000 l df *ABS* 00000000 dtoa.c +080051dc l F .text 00000210 quorem +00000000 l df *ABS* 00000000 fflush.c +00000000 l df *ABS* 00000000 findfp.c +08006d64 l F .text 00000008 __fp_lock +08006d78 l F .text 00000168 __sinit.part.0 +08006ee0 l F .text 00000008 __fp_unlock +00000000 l df *ABS* 00000000 mallocr.c +00000000 l df *ABS* 00000000 fvwrite.c +00000000 l df *ABS* 00000000 fwalk.c +00000000 l df *ABS* 00000000 getc.c +00000000 l df *ABS* 00000000 localeconv.c +00000000 l df *ABS* 00000000 makebuf.c +00000000 l df *ABS* 00000000 mallocr.c +00000000 l df *ABS* 00000000 memchr.c +00000000 l df *ABS* 00000000 memcpy.c +00000000 l df *ABS* 00000000 memmove.c +00000000 l df *ABS* 00000000 memset.c +00000000 l df *ABS* 00000000 mprec.c +080474d0 l O .rodata 0000000c p05.4024 +00000000 l df *ABS* 00000000 putc.c +00000000 l df *ABS* 00000000 mallocr.c +00000000 l df *ABS* 00000000 rget.c +00000000 l df *ABS* 00000000 sbrkr.c +00000000 l df *ABS* 00000000 stdio.c +00000000 l df *ABS* 00000000 vfprintf.c +0800a304 l F .text 000000f4 __sprint_r.part.0 +0800b754 l F .text 000000c0 __sbprintf +08047604 l O .rodata 00000010 blanks.5203 +080475f4 l O .rodata 00000010 zeroes.5204 +00000000 l df *ABS* 00000000 wbuf.c +00000000 l df *ABS* 00000000 writer.c +00000000 l df *ABS* 00000000 closer.c +00000000 l df *ABS* 00000000 mallocr.c +00000000 l df *ABS* 00000000 fclose.c +00000000 l df *ABS* 00000000 fputwc.c +00000000 l df *ABS* 00000000 fstatr.c +00000000 l df *ABS* 00000000 int_errno.c +00000000 l df *ABS* 00000000 isattyr.c +00000000 l df *ABS* 00000000 locale.c +00000000 l df *ABS* 00000000 lseekr.c +00000000 l df *ABS* 00000000 mbtowc_r.c +00000000 l df *ABS* 00000000 readr.c +00000000 l df *ABS* 00000000 refill.c +0800c03c l F .text 0000001c lflush +00000000 l df *ABS* 00000000 strcmp.c +00000000 l df *ABS* 00000000 wcrtomb.c +00000000 l df *ABS* 00000000 wctomb_r.c +00000000 l df *ABS* 00000000 libgcc2.c +00000000 l df *ABS* 00000000 libgcc2.c +00000000 l df *ABS* 00000000 lib2-divmod.c +00000000 l df *ABS* 00000000 adddf3.c +00000000 l df *ABS* 00000000 divdf3.c +00000000 l df *ABS* 00000000 eqdf2.c +00000000 l df *ABS* 00000000 gedf2.c +00000000 l df *ABS* 00000000 ledf2.c +00000000 l df *ABS* 00000000 muldf3.c +00000000 l df *ABS* 00000000 subdf3.c +00000000 l df *ABS* 00000000 unorddf2.c +00000000 l df *ABS* 00000000 fixdfsi.c +00000000 l df *ABS* 00000000 floatsidf.c +00000000 l df *ABS* 00000000 floatunsidf.c +00000000 l df *ABS* 00000000 libgcc2.c +00000000 l df *ABS* 00000000 libgcc2.c +00000000 l df *ABS* 00000000 alt_flash_dev.c +00000000 l df *ABS* 00000000 alt_fstat.c +0800f8a0 l F .text 0000003c alt_get_errno +00000000 l df *ABS* 00000000 alt_isatty.c +0800f98c l F .text 0000003c alt_get_errno +00000000 l df *ABS* 00000000 alt_lseek.c +0800fa6c l F .text 0000003c alt_get_errno +00000000 l df *ABS* 00000000 alt_main.c +00000000 l df *ABS* 00000000 alt_sbrk.c +0804cad0 l O .rwdata 00000004 heap_end +00000000 l df *ABS* 00000000 alt_env_lock.c +0804cad4 l O .rwdata 00000004 lockid +0804cbd4 l O .bss 00000004 locks +00000000 l df *ABS* 00000000 alt_malloc_lock.c +0804cad8 l O .rwdata 00000004 lockid +0804cbdc l O .bss 00000004 locks +00000000 l df *ABS* 00000000 os_core.c +080113a0 l F .text 0000003c OS_InitMisc +080113dc l F .text 0000006c OS_InitRdyList +080114cc l F .text 000000e4 OS_InitTCBList +080112c0 l F .text 000000e0 OS_InitEventList +08011448 l F .text 00000084 OS_InitTaskIdle +08011734 l F .text 0000006c OS_SchedNew +00000000 l df *ABS* 00000000 os_flag.c +08012fb8 l F .text 000000f4 OS_FlagTaskRdy +08012d74 l F .text 00000164 OS_FlagBlock +00000000 l df *ABS* 00000000 os_mem.c +00000000 l df *ABS* 00000000 os_mutex.c +0801457c l F .text 00000188 OSMutex_RdyAtPrio +00000000 l df *ABS* 00000000 os_q.c +00000000 l df *ABS* 00000000 os_sem.c +00000000 l df *ABS* 00000000 os_task.c +00000000 l df *ABS* 00000000 os_time.c +00000000 l df *ABS* 00000000 alt_sys_init.c +08017794 l F .text 00000034 alt_dev_reg +0804c420 l O .rwdata 000000d0 debug_uart +0804c4f0 l O .rwdata 000000dc ext_flash +0804c5d0 l O .rwdata 00000070 msgdma_rx +0804c640 l O .rwdata 00000070 msgdma_tx +0804c6b0 l O .rwdata 00000100 onchip_flash +00000000 l df *ABS* 00000000 altera_avalon_timer_sc.c +08017a2c l F .text 00000078 alt_avalon_timer_sc_irq +00000000 l df *ABS* 00000000 altera_avalon_tse.c +0804cc26 l O .bss 00000001 tse_system_count.5331 +0804cc27 l O .bss 00000001 is_init.5413 +00000000 l df *ABS* 00000000 altera_avalon_uart_fd.c +00000000 l df *ABS* 00000000 altera_avalon_uart_init.c +0801ccb0 l F .text 0000009c altera_avalon_uart_irq +0801cd4c l F .text 00000134 altera_avalon_uart_rxirq +0801ce80 l F .text 000001a0 altera_avalon_uart_txirq +00000000 l df *ABS* 00000000 altera_avalon_uart_read.c +0801d074 l F .text 0000003c alt_get_errno +00000000 l df *ABS* 00000000 altera_avalon_uart_write.c +0801d318 l F .text 0000003c alt_get_errno +00000000 l df *ABS* 00000000 altera_generic_quad_spi_controller.c +0801d588 l F .text 00000034 alt_flash_device_register +0801e010 l F .text 0000008c alt_qspi_poll_for_write_in_progress +0801df74 l F .text 0000009c alt_qspi_validate_read_write_arguments +00000000 l df *ABS* 00000000 altera_msgdma.c +0801e09c l F .text 0000003c alt_get_errno +0801e0d8 l F .text 00000094 alt_msgdma_write_standard_descriptor +0801e16c l F .text 0000012c alt_msgdma_write_extended_descriptor +0801e298 l F .text 00000184 alt_msgdma_irq +0801e41c l F .text 0000008c alt_msgdma_construct_standard_descriptor +0801e4a8 l F .text 00000154 alt_msgdma_construct_extended_descriptor +0801e5fc l F .text 0000033c alt_msgdma_descriptor_async_transfer +0801e938 l F .text 00000408 alt_msgdma_descriptor_sync_transfer +0801f010 l F .text 000000a4 alt_msgdma_construct_prefetcher_standard_descriptor +0801f0b4 l F .text 00000194 alt_msgdma_construct_prefetcher_extended_descriptor +00000000 l df *ABS* 00000000 altera_onchip_flash.c +080201d8 l F .text 00000034 alt_flash_device_register +00000000 l df *ABS* 00000000 ins_tse_mac.c +00000000 l df *ABS* 00000000 alt_iniche_close.c +00000000 l df *ABS* 00000000 alt_iniche_dev.c +00000000 l df *ABS* 00000000 alt_iniche_read.c +00000000 l df *ABS* 00000000 alt_iniche_write.c +00000000 l df *ABS* 00000000 et_arp.c +0804cc2c l O .bss 00000004 arp_timer +0804cc34 l O .bss 00000004 cachetime +00000000 l df *ABS* 00000000 iface.c +00000000 l df *ABS* 00000000 ipnet.c +00000000 l df *ABS* 00000000 ipstart.c +0804cdb8 l O .bss 0000003c closers +0804cc58 l O .bss 00000004 nclosers +00000000 l df *ABS* 00000000 igmp_cmn.c +00000000 l df *ABS* 00000000 bsdsock.c +00000000 l df *ABS* 00000000 cksum.c +0804cb04 l O .rwdata 00000004 cksum_select +00000000 l df *ABS* 00000000 in_utils.c +0804cdf4 l O .bss 00000018 tistring +00000000 l df *ABS* 00000000 netmain.c +00000000 l df *ABS* 00000000 tk_crnos.c +00000000 l df *ABS* 00000000 ping.c +00000000 l df *ABS* 00000000 pktalloc.c +00000000 l df *ABS* 00000000 q.c +00000000 l df *ABS* 00000000 asm_cksum.o +08028cd0 l .text 00000000 done +08028b60 l .text 00000000 asm1 +08028c8c l .text 00000000 loop0 +08028b88 l .text 00000000 loop +08028ca8 l .text 00000000 fold +00000000 l df *ABS* 00000000 brdutils.c +0804cc8c l O .bss 00000004 kbd_init.4507 +0804cc88 l O .bss 00000004 cpu_statusreg +00000000 l df *ABS* 00000000 osportco.c +00000000 l df *ABS* 00000000 targnios.c +00000000 l df *ABS* 00000000 nptcp.c +0804ccc0 l O .bss 00000004 in_tcptick +00000000 l df *ABS* 00000000 rawsock.c +00000000 l df *ABS* 00000000 sockcall.c +0802cf30 l F .text 0000008c sockargs +0802c26c l F .text 000001e0 t_getname +00000000 l df *ABS* 00000000 socket.c +00000000 l df *ABS* 00000000 socket2.c +00000000 l df *ABS* 00000000 soselect.c +00000000 l df *ABS* 00000000 tcp_in.c +00000000 l df *ABS* 00000000 tcp_out.c +0803492c l F .text 000000cc bld_options +00000000 l df *ABS* 00000000 tcp_subr.c +00000000 l df *ABS* 00000000 tcp_timr.c +00000000 l df *ABS* 00000000 tcp_usr.c +00000000 l df *ABS* 00000000 tcpport.c +00000000 l df *ABS* 00000000 udpsock.c +00000000 l df *ABS* 00000000 alt_busy_sleep.c +00000000 l df *ABS* 00000000 alt_close.c +080370b4 l F .text 0000003c alt_get_errno +00000000 l df *ABS* 00000000 alt_dcache_flush.c +00000000 l df *ABS* 00000000 alt_dev.c +08037238 l F .text 0000002c alt_dev_null_write +00000000 l df *ABS* 00000000 alt_dev_llist_insert.c +08037264 l F .text 0000003c alt_get_errno +00000000 l df *ABS* 00000000 alt_do_ctors.c +00000000 l df *ABS* 00000000 alt_do_dtors.c +00000000 l df *ABS* 00000000 alt_errno.c +00000000 l df *ABS* 00000000 alt_find_dev.c +00000000 l df *ABS* 00000000 alt_iic.c +00000000 l df *ABS* 00000000 alt_iic_isr_register.c +00000000 l df *ABS* 00000000 alt_io_redirect.c +08037728 l F .text 000000b0 alt_open_fd +00000000 l df *ABS* 00000000 alt_irq_vars.c +00000000 l df *ABS* 00000000 alt_open.c +08037854 l F .text 0000003c alt_get_errno +08037890 l F .text 000000b8 alt_file_locked +00000000 l df *ABS* 00000000 alt_printf.c +00000000 l df *ABS* 00000000 alt_putchar.c +00000000 l df *ABS* 00000000 alt_read.c +08037cf8 l F .text 0000003c alt_get_errno +00000000 l df *ABS* 00000000 alt_release_fd.c +00000000 l df *ABS* 00000000 alt_remap_cached.c +00000000 l df *ABS* 00000000 alt_tick.c +00000000 l df *ABS* 00000000 alt_uncached_free.c +00000000 l df *ABS* 00000000 alt_uncached_malloc.c +00000000 l df *ABS* 00000000 alt_usleep.c +00000000 l df *ABS* 00000000 alt_write.c +08038230 l F .text 0000003c alt_get_errno +00000000 l df *ABS* 00000000 altera_nios2_gen2_irq.c +00000000 l df *ABS* 00000000 os_cpu_a.o +00000040 l *ABS* 00000000 OSCtxSw_SWITCH_PC +00000000 l df *ABS* 00000000 os_cpu_c.c +00000014 l *ABS* 00000000 OSTCBNext_OFFSET +00000032 l *ABS* 00000000 OSTCBPrio_OFFSET +00000000 l *ABS* 00000000 OSTCBStkPtr_OFFSET +00000000 l df *ABS* 00000000 allports.c +0804ccf8 l O .bss 00000004 inside_pktdemux +00000000 l df *ABS* 00000000 timeouts.c +08038b28 l F .text 0000014c check_interval_timers +0804cd04 l O .bss 00000004 numtimers +00000000 l df *ABS* 00000000 tk_misc.c +00000000 l df *ABS* 00000000 alt_iniche_fcntl.c +00000000 l df *ABS* 00000000 icmp.c +0804c940 l O .rwdata 00000018 dsts +00000000 l df *ABS* 00000000 ip.c +0804cb74 l O .rwdata 00000004 uid +00000000 l df *ABS* 00000000 ipdemux.c +00000000 l df *ABS* 00000000 ipmc.c +00000000 l df *ABS* 00000000 ipport.c +00000000 l df *ABS* 00000000 ipraw.c +00000000 l df *ABS* 00000000 iproute.c +00000000 l df *ABS* 00000000 udp.c +0804cd2c l O .bss 00000002 usocket +00000000 l df *ABS* 00000000 igmp.c +00000000 l df *ABS* 00000000 igmp2.c +00000000 l df *ABS* 00000000 ipopt.c +00000000 l df *ABS* 00000000 u_mctest.c +0804cb7c l O .rwdata 00000004 iCounter.5304 +00000000 l df *ABS* 00000000 memdev.c +00000000 l df *ABS* 00000000 parseip.c +0804ce0c l O .bss 0000001e nearBuf.4931 +00000000 l df *ABS* 00000000 tcpcksum.c +00000000 l df *ABS* 00000000 udp_open.c +00000000 l df *ABS* 00000000 in_pcb.c +00000000 l df *ABS* 00000000 vfsfiles.c +00000000 l df *ABS* 00000000 vfsport.c +00000000 l df *ABS* 00000000 alt_fcntl.c +080426b8 l F .text 0000003c alt_get_errno +00000000 l df *ABS* 00000000 alt_find_file.c +00000000 l df *ABS* 00000000 alt_get_fd.c +00000000 l df *ABS* 00000000 atexit.c +00000000 l df *ABS* 00000000 atoi.c +00000000 l df *ABS* 00000000 exit.c +00000000 l df *ABS* 00000000 malign.c +00000000 l df *ABS* 00000000 mallocr.c +00000000 l df *ABS* 00000000 malloc.c +00000000 l df *ABS* 00000000 memcmp.c +00000000 l df *ABS* 00000000 sprintf.c +00000000 l df *ABS* 00000000 strchr.c +00000000 l df *ABS* 00000000 strcpy.c +00000000 l df *ABS* 00000000 strncmp.c +00000000 l df *ABS* 00000000 strtol.c +080430e8 l F .text 00000224 _strtol_l.isra.0 +00000000 l df *ABS* 00000000 vfprintf.c +0804b8e1 l O .rodata 00000010 blanks.5207 +0804b8d1 l O .rodata 00000010 zeroes.5208 +00000000 l df *ABS* 00000000 vprintf.c +00000000 l df *ABS* 00000000 vsprintf.c +00000000 l df *ABS* 00000000 __atexit.c +00000000 l df *ABS* 00000000 __call_atexit.c +00000000 l df *ABS* 00000000 vfprintf.c +0804b901 l O .rodata 00000010 blanks.5187 +0804b8f1 l O .rodata 00000010 zeroes.5188 +00000000 l df *ABS* 00000000 vfprintfr_1.c +00000000 l df *ABS* 00000000 alt_exit.c +0804cd5c g O .bss 00000004 alt_instruction_exception_handler +080200e8 g F .text 0000003c alt_msgdma_standard_descriptor_async_transfer +08002cb8 g F .text 00000018 putchar +0805e1c4 g O .bss 00000014 soq +18200000 g *ABS* 00000000 __alt_mem_onchip_flash_data +080097bc g F .text 00000074 _mprec_log10 +0804cbac g O .bss 00000001 to_sslistenertask +08018c1c g F .text 000000cc alt_tse_get_mac_info +0800989c g F .text 00000074 __any_on +0800be3c g F .text 00000058 _isatty_r +080474dc g O .rodata 00000028 __mprec_tinytens +0803a2d4 g F .text 00000714 ip_write_internal +0800fb7c g F .text 000000bc alt_main +08042f60 g F .text 0000008c strcpy +08028748 g F .text 000000ac pk_free +08002cd0 g F .text 000000cc _puts_r +08000380 g F .text 00000030 control_delay +0805e370 g O .bss 00000100 alt_irq +08002a14 g F .text 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g O .bss 00000004 _PathLocale +0804cb0c g O .rwdata 00000004 pingdata +0804cc98 g O .bss 00000004 tcp_sleep_count +0802a334 g F .text 0000007c insque +08042a90 g F .text 00000014 atexit +0804cd44 g O .bss 00000004 vfsfiles +0800b970 g F .text 00000064 _write_r +08045484 g F .text 0000004c _vsprintf_r +0803d8a0 g F .text 00000294 udp_send +08010908 g F .text 0000008c OSSchedLock +0802565c g F .text 0000027c igmp_send +0800bf10 g F .text 00000014 setlocale +0801f3f0 g F .text 00000098 alt_msgdma_construct_prefetcher_extended_mm_to_st_descriptor +08011e78 g F .text 000000f8 OSFlagCreate +08028ef4 g F .text 00000044 irq_Unmask +0802bc50 g F .text 000000d4 t_listen +0801c9a0 g F .text 000000a0 PEF7071_link_status_read +0804cabc g O .rwdata 00000004 _impure_ptr +08000950 g F .text 00000714 control_step +0804cbc8 g O .bss 00000004 alt_argc +08035a14 g F .text 000006b8 tcp_usrreq +080365b8 g F .text 00000238 udp_usrreq +080298a0 g F .text 00000034 ncpalloc +08006ab4 g F .text 00000228 __sflush_r +080373a4 g F .text 00000060 _do_dtors +0804cb6c g O .rwdata 00000004 pingdelay +08022ef4 g F .text 00000074 arp_send_pending +0803ddfc g F .text 00000268 igmpv1_input +0800c058 g F .text 000001cc __srefill_r +0802959c g F .text 0000004c pre_task_setup +0804ccb8 g O .bss 00000004 rcvdq_sem_ptr +08026454 g F .text 00000120 bsd_getsockname +08001a54 g F .text 0000012c FindLastFlashSectorOffset +08011f70 g F .text 0000021c OSFlagDel +0804cc10 g O .bss 00000004 OSEventFreeList +08000120 g .exceptions 00000000 alt_irq_entry +0804cc30 g O .bss 00000004 arpcache +08039a54 g F .text 000002d8 icmp_destun +0800bf94 g F .text 00000044 __ascii_mbtowc +0803c504 g F .text 00000064 lookup_mcast +0804232c g F .text 00000048 vfslookup +0803bf08 g F .text 000003a4 ip_demux +0800946c g F .text 0000005c __ulp +0804cc9c g O .bss 00000004 tcp_wakeup_count +08012378 g F .text 00000598 OSFlagPend +08007094 g F .text 00000014 __fp_unlock_all +080292b4 g F .text 000000b4 wait_app_sem +0804cb00 g O .rwdata 00000004 ipmcfail_str +0804ccb0 g O .bss 00000004 memtrapsize +08029d40 g F .text 000002d8 m_copy +0804cb40 g O .rwdata 00000008 alt_fs_list +0805e228 g O .bss 00000014 mfreeq +080204dc g F .text 000002d8 alt_onchip_flash_write_block +0801d758 g F .text 00000124 alt_qspi_controller_erase_block +080117a0 g F .text 00000074 OS_StrCopy +0802d1f8 g F .text 0000005c sobind +0804cadc g O .rwdata 00000004 eth_tse_name +0803f598 g F .text 00000050 init_memdev +0802a3b0 g F .text 000000f4 nptcp_init +08002abc g F .text 0000004c led_clear +0805e07c g O .bss 000000f0 global_TCPwakeup_set +08038678 g F .text 00000020 OSInitHookEnd +0802f384 g F .text 000000c4 soisdisconnected +08022e6c g F .text 00000088 arp_free_pending +08007bfc g F .text 0000000c localeconv +0802d434 g F .text 000002c8 soclose +0805df6c g O .bss 00000014 bigfreeq +08007c08 g F .text 00000098 __swhatbuf_r +0804cb68 g O .rwdata 00000004 prompt +0804cb30 g O .rwdata 00000004 tcp_keepidle +0801bc08 g F .text 000001a8 alt_tse_phy_set_adv_10 +0802b124 g F .text 000001c4 rawip_soinput +08037494 g F .text 00000050 alt_ic_isr_register +08041e08 g F .text 00000060 vfwrite +0802f640 g F .text 000000ac soqinsque +0804cd1c g O .bss 00000004 so_evtmap_delete +0804cb8c g *ABS* 00000000 _edata +0801ca40 g F .text 00000060 altera_avalon_uart_read_fd +08022aa8 g F .text 00000124 iniche_devices_init +080207b4 g F .text 000002cc alt_onchip_flash_write +0805e23c g O .bss 00000028 tcp_saveti +08027544 g F .text 000000d8 con_page +0805e59c g *ABS* 00000000 _end +0802ec0c g F .text 00000520 sogetopt +08001064 g F .text 0000008c ControlTask +0800f7e4 g F .text 00000068 alt_flash_open_dev +0804cc14 g O .bss 00000001 OSIntNesting +08002c30 g F .text 00000008 _getchar_r +0801aaa4 g F .text 00000240 alt_tse_mac_associate_phy +0804c7b0 g O .rwdata 00000030 nettasks +080287f4 g F .text 00000020 pk_get_max_intrsafe_buf_len +0800bbec g F .text 00000150 __fputwc +0803b370 g F .text 000001cc iproute +0802ac18 g F .text 000000f0 np_stripoptions +0804cd20 g O .bss 00000001 so_evtmap +0801750c g F .text 000001cc OSTimeDlyResume +0803cc7c g F .text 000003a4 add_route +0801226c g F .text 0000010c OSFlagNameSet +08024d64 g F .text 00000090 c_older +0803002c g F .text 00000084 sbflush +0803f610 g F .text 00000024 md_fclose +08027ce4 g F .text 00000030 tk_yield +0803756c g F .text 0000008c alt_ic_irq_disable +0802d934 g F .text 00000560 sosend +0803b028 g F .text 000000a4 ip_mymach +0800a220 g F .text 00000080 __swrite +08002840 g F .text 000000c4 swap_quad +0804cc80 g O .bss 00000004 cticks_initialized +0804cb70 g O .rwdata 00000004 deflength +0802c9ac g F .text 000001f0 t_sendto +0804cac4 g O .rwdata 00000004 __malloc_trim_threshold +0804cc18 g O .bss 00000004 OSTCBCur +0802d050 g F .text 000001a8 socreate +08042abc g F .text 00000034 exit +0805d998 g O .bss 00000100 arp_table +08001b80 g F .text 00000088 sensor_command_bit +08014238 g F .text 000001f8 OSMutexPost +0804cd08 g O .bss 00000004 icmpdu_hook +08007a28 g F .text 000000b4 _fwalk_reent +0801f7c8 g F .text 00000110 alt_msgdma_prefetcher_set_std_list_own_by_hw_bits +08038e38 g F .text 00000024 create_apptasks +0804cb2c g O .rwdata 00000004 tcp_ttl +080092b0 g F .text 000001bc __mdiff +0800f84c g F .text 00000054 alt_flash_close_dev +080298d4 g F .text 00000040 ncpfree +0800cf80 g F .text 00000078 .hidden __modsi3 +08042b04 g F .text 00000194 _memalign_r +0804cc48 g O .bss 00000004 MaxLnh +08017e34 g F .text 00000050 tse_mac_setGMIImode +0803fd7c g F .text 00000084 inet_ntop +0803dd94 g F .text 00000024 udp_maxalloc +0801c614 g F .text 000000e4 marvell_cfg_gmii +10000000 g *ABS* 00000000 __alt_data_end +08000120 g F .exceptions 00000000 alt_exception +08007074 g F .text 00000004 __sfp_lock_release +0801077c g F .text 00000050 OSInit +0801ef68 g F .text 000000a8 alt_msgdma_construct_extended_mm_to_mm_descriptor +0801ace4 g F .text 00000128 alt_tse_phy_cfg_pcs +08017220 g F .text 000000ec OSTaskQuery +080387c4 g F .text 0000008c icmp_port_du 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+08015f74 g F .text 000000d8 OSSemSet +0804cb88 g O .rwdata 00000004 http_root_path +0804cb9c g O .bss 00000001 to_controltask +0801da8c g F .text 000001e8 alt_qspi_controller_write +0800a3f8 g F .text 00000018 __sprint_r +08017c78 g F .text 00000070 tse_mac_aRxRead +08042dfc g F .text 00000164 strchr +0805de46 g O .bss 00000012 ipreturn +0804cd10 g O .bss 00000004 port_prep +0804c833 g O .rwdata 0000000d tcp_backoff +0802f178 g F .text 00000070 soisconnecting +080226c0 g F .text 00000138 allocate_rx_descriptor_chain +0804cb58 g O .rwdata 00000004 alt_priority_mask +0803e284 g F .text 000001c0 igmpv2_process_query +080303f8 g F .text 000001d0 t_select +08002b7c g F .text 0000004c led4_blink_enable +0801584c g F .text 00000214 OSSemDel +08000418 g F .text 00000060 control_process_snapshot +08036e34 g F .text 00000128 udp4_sockaddr +0804cc20 g O .bss 00000004 OSFlagFreeList +0804081c g F .text 000001e0 in_pcbconnect +0804ccd4 g O .bss 00000004 dropline +080374e4 g F .text 00000088 alt_ic_irq_enable +08004fa4 g F .text 00000018 __vfprintf_internal +080278f4 g F .text 00000078 tk_netmain +080409fc g F .text 0000005c in_pcbdisconnect +0805d574 g O .bss 00000054 OSTCBPrioTbl +0801d0b0 g F .text 00000268 altera_avalon_uart_read +0800c3ec g F .text 0000000c _wctomb_r +0800fce8 g F .text 000000c4 __env_lock +0804c964 g O .rwdata 00000024 mdio +08018ce8 g F .text 000000e0 alt_tse_mac_set_speed +08026214 g F .text 00000120 bsd_accept +0804cb3c g O .rwdata 00000004 tcp_recvspace +0800ebec g F .text 0000096c .hidden __subdf3 +08046970 g F .text 00000004 _vfprintf_r +0803637c g F .text 00000040 tcpinit +0804cc68 g O .bss 00000004 igmp_all_rtrs_group +0802b0c8 g F .text 0000005c rawip_lookup +08038ed8 g F .text 000000a0 fcntl +080008a4 g F .text 000000ac control_get_data +08008d24 g F .text 000000b0 __lo0bits +0802fe50 g F .text 000001dc sbcompress +0804cb5c g O .rwdata 00000008 alt_alarm_list +0803504c g F .text 0000009c tcp_drop +08037344 g F .text 00000060 _do_ctors +0801b9b4 g F .text 00000254 alt_tse_phy_set_adv_100 +080355c0 g F .text 00000454 tcp_timers +080252fc g F .text 00000080 if_netnumber +0803ee74 g F .text 00000084 ip_freemoptions +0802f12c g F .text 0000004c sohasoutofband +0800c368 g F .text 00000084 wcrtomb +08031050 g F .text 00002214 tcp_input +08026334 g F .text 00000120 bsd_getpeername +08026930 g F .text 00000144 bsd_recvfrom +08022a60 g F .text 00000048 close +0804cbd8 g O .bss 00000004 alt_envsem +0804c2ac g O .rwdata 0000016c __global_locale +08010c98 g F .text 00000020 OSVersion +08040db4 g F .text 0000002c set_vfopen_error +08022408 g F .text 000002b8 tse_msgdma_read_init +08018ac8 g F .text 0000006c alt_tse_get_system_index +0804c810 g O .rwdata 00000018 rawip_protosw +08001d58 g F .text 00000050 ss_initialize_connection +0802f8e0 g F .text 0000006c sbwait +08011258 g F .text 00000068 OS_EventWaitListInit +0804cd00 g O .bss 00000004 port_1s_callout +0800bd60 g F .text 0000007c fputwc +08038698 g F .text 00000020 OSTaskIdleHook +08042ca8 g F .text 00000010 free +08007078 g F .text 00000004 __sinit_lock_acquire +0804cc28 g O .bss 00000001 number_of_tse_mac +08008a9c g F .text 00000114 __multadd +08017078 g F .text 000001a8 OSTaskSuspend +08008a78 g F .text 00000024 _Bfree +08017b20 g F .text 00000030 no_printf +0802f448 g F .text 000001f8 sonewconn +08038f78 g F .text 00000adc icmprcv +080299a4 g F .text 000000cc pffindproto +08011868 g F .text 0000005c OS_TaskIdle +080154f0 g F .text 0000013c OSQQuery + + + +Disassembly of section .entry: + +14000000 <__reset>: +#if NIOS2_ICACHE_SIZE > 0 && defined(ALT_ALLOW_CODE_AT_RESET) && (!defined(ALT_SIM_OPTIMIZE) || defined(NIOS2_ECC_PRESENT)) + /* Assume the instruction cache size is always a power of two. */ +#if NIOS2_ICACHE_SIZE > 0x8000 + movhi r2, %hi(NIOS2_ICACHE_SIZE) +#else + movui r2, NIOS2_ICACHE_SIZE +14000000: 00820014 movui r2,2048 +#endif + +0: + initi r2 +14000004: 1001483a initi r2 + addi r2, r2, -NIOS2_ICACHE_LINE_SIZE +14000008: 10bff804 addi r2,r2,-32 + bgt r2, zero, 0b +1400000c: 00bffd16 blt zero,r2,14000004 <__reset+0x4> + * Jump to the _start entry point in the .text section if reset code + * is allowed or if optimizing for RTL simulation. + */ +#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE) + /* Jump to the _start entry point in the .text section. */ + movhi r1, %hi(_start) +14000010: 00420034 movhi at,2048 + ori r1, r1, %lo(_start) +14000014: 0840ce14 ori at,at,824 + jmp r1 +14000018: 0800683a jmp at +1400001c: 00000000 call 10000000 <__alt_data_end> + +Disassembly of section .exceptions: + +08000120 : + +#else /* ALT_EXCEPTION_STACK disabled */ + /* + * Reserve space on normal stack for registers about to be pushed. + */ + addi sp, sp, -76 + 8000120: deffed04 addi sp,sp,-76 + * documentation for details). + * + * Leave a gap in the stack frame at 4(sp) for the muldiv handler to + * store zero into. + */ + stw ra, 0(sp) + 8000124: dfc00015 stw ra,0(sp) + stw r1, 8(sp) + 8000128: d8400215 stw at,8(sp) + stw r2, 12(sp) + 800012c: d8800315 stw r2,12(sp) + stw r3, 16(sp) + 8000130: d8c00415 stw r3,16(sp) + stw r4, 20(sp) + 8000134: d9000515 stw r4,20(sp) + stw r5, 24(sp) + 8000138: d9400615 stw r5,24(sp) + stw r6, 28(sp) + 800013c: d9800715 stw r6,28(sp) + stw r7, 32(sp) + 8000140: d9c00815 stw r7,32(sp) + rdctl r5, estatus /* Read early to avoid usage stall */ + 8000144: 000b307a rdctl r5,estatus + stw r8, 36(sp) + 8000148: da000915 stw r8,36(sp) + stw r9, 40(sp) + 800014c: da400a15 stw r9,40(sp) + stw r10, 44(sp) + 8000150: da800b15 stw r10,44(sp) + stw r11, 48(sp) + 8000154: dac00c15 stw r11,48(sp) + stw r12, 52(sp) + 8000158: db000d15 stw r12,52(sp) + stw r13, 56(sp) + 800015c: db400e15 stw r13,56(sp) + stw r14, 60(sp) + 8000160: db800f15 stw r14,60(sp) + stw r15, 64(sp) + 8000164: dbc01015 stw r15,64(sp) + /* + * ea-4 contains the address of the instruction being executed + * when the exception occured. For interrupt exceptions, we will + * will be re-issue the isntruction. Store it in 72(sp) + */ + stw r5, 68(sp) /* estatus */ + 8000168: d9401115 stw r5,68(sp) + addi r15, ea, -4 /* instruction that caused exception */ + 800016c: ebffff04 addi r15,ea,-4 + stw r15, 72(sp) + 8000170: dbc01215 stw r15,72(sp) +#else + /* + * Test to see if the exception was a software exception or caused + * by an external interrupt, and vector accordingly. + */ + rdctl r4, ipending + 8000174: 0009313a rdctl r4,ipending + andi r2, r5, 1 + 8000178: 2880004c andi r2,r5,1 + beq r2, zero, .Lnot_irq + 800017c: 10000326 beq r2,zero,800018c + beq r4, zero, .Lnot_irq + 8000180: 20000226 beq r4,zero,800018c + /* + * Now that all necessary registers have been preserved, call + * alt_irq_handler() to process the interrupts. + */ + + call alt_irq_handler + 8000184: 80001fc0 call 80001fc + + .section .exceptions.irqreturn, "xa" + + br .Lexception_exit + 8000188: 00000706 br 80001a8 + * upon completion, so we write ea (address of instruction *after* + * the one where the exception occured) into 72(sp). The actual + * instruction that caused the exception is written in r2, which these + * handlers will utilize. + */ + stw ea, 72(sp) /* EA is PC+4 so will skip over instruction causing exception */ + 800018c: df401215 stw ea,72(sp) +.Lunknown_16bit: + addi.n r4, r4, 2 /* Need PC+2 to skip over instruction causing exception */ + stw r4, 72(sp) + +#else /* CDX is not Enabled and all instructions are 32bits */ + ldw r2, -4(ea) /* Instruction value that caused exception */ + 8000190: e8bfff17 ldw r2,-4(ea) + * debugger is present) or go into an infinite loop since the + * handling behavior is undefined; in that case we will not return here. + */ + + /* Load exception-causing address as first argument (r4) */ + addi r4, ea, -4 + 8000194: e93fff04 addi r4,ea,-4 + + /* Call the instruction-exception entry */ + call alt_instruction_exception_entry + 8000198: 80002c40 call 80002c4 + * instruction + * + * Return code was 0: Skip. The instruction after the exception is + * already stored in 72(sp). + */ + bne r2, r0, .Lexception_exit + 800019c: 1000021e bne r2,zero,80001a8 + + /* + * Otherwise, modify 72(sp) to re-issue the instruction that caused the + * exception. + */ + addi r15, ea, -4 /* instruction that caused exception */ + 80001a0: ebffff04 addi r15,ea,-4 + stw r15, 72(sp) + 80001a4: dbc01215 stw r15,72(sp) + /* + * Restore the saved registers, so that all general purpose registers + * have been restored to their state at the time the interrupt occured. + */ + + ldw r5, 68(sp) + 80001a8: d9401117 ldw r5,68(sp) + ldw ea, 72(sp) /* This becomes the PC once eret is executed */ + 80001ac: df401217 ldw ea,72(sp) + ldw ra, 0(sp) + 80001b0: dfc00017 ldw ra,0(sp) + + wrctl estatus, r5 + 80001b4: 2801707a wrctl estatus,r5 + + ldw r1, 8(sp) + 80001b8: d8400217 ldw at,8(sp) + ldw r2, 12(sp) + 80001bc: d8800317 ldw r2,12(sp) + ldw r3, 16(sp) + 80001c0: d8c00417 ldw r3,16(sp) + ldw r4, 20(sp) + 80001c4: d9000517 ldw r4,20(sp) + ldw r5, 24(sp) + 80001c8: d9400617 ldw r5,24(sp) + ldw r6, 28(sp) + 80001cc: d9800717 ldw r6,28(sp) + ldw r7, 32(sp) + 80001d0: d9c00817 ldw r7,32(sp) + +#if defined(ALT_EXCEPTION_STACK) && defined(ALT_STACK_CHECK) + ldw et, %gprel(alt_exception_old_stack_limit)(gp) +#endif + + ldw r8, 36(sp) + 80001d4: da000917 ldw r8,36(sp) + ldw r9, 40(sp) + 80001d8: da400a17 ldw r9,40(sp) + ldw r10, 44(sp) + 80001dc: da800b17 ldw r10,44(sp) + ldw r11, 48(sp) + 80001e0: dac00c17 ldw r11,48(sp) + ldw r12, 52(sp) + 80001e4: db000d17 ldw r12,52(sp) + ldw r13, 56(sp) + 80001e8: db400e17 ldw r13,56(sp) + ldw r14, 60(sp) + 80001ec: db800f17 ldw r14,60(sp) + ldw r15, 64(sp) + 80001f0: dbc01017 ldw r15,64(sp) + stw et, %gprel(alt_stack_limit_value)(gp) + stw zero, %gprel(alt_exception_old_stack_limit)(gp) +#endif /* ALT_STACK_CHECK */ + ldw sp, 76(sp) +#else /* ALT_EXCEPTION_STACK disabled */ + addi sp, sp, 76 + 80001f4: dec01304 addi sp,sp,76 + + /* + * Return to the interrupted instruction. + */ + + eret + 80001f8: ef80083a eret + +080001fc : + * instruction is present if the macro ALT_CI_INTERRUPT_VECTOR defined. + */ + +void alt_irq_handler (void) __attribute__ ((section (".exceptions"))); +void alt_irq_handler (void) +{ + 80001fc: defff904 addi sp,sp,-28 + 8000200: dfc00615 stw ra,24(sp) + 8000204: df000515 stw fp,20(sp) + 8000208: df000504 addi fp,sp,20 + + /* + * Notify the operating system that we are at interrupt level. + */ + + ALT_OS_INT_ENTER(); + 800020c: 80107cc0 call 80107cc +#ifndef NIOS2_EIC_PRESENT +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void) +{ + alt_u32 active; + + NIOS2_READ_IPENDING (active); + 8000210: 0005313a rdctl r2,ipending + 8000214: e0bffc15 stw r2,-16(fp) + + return active; + 8000218: e0bffc17 ldw r2,-16(fp) + * Consider the case where the high priority interupt is asserted during + * the interrupt entry sequence for a lower priority interrupt to see why + * this is the case. + */ + + active = alt_irq_pending (); + 800021c: e0bfff15 stw r2,-4(fp) + + do + { + i = 0; + 8000220: e03ffd15 stw zero,-12(fp) + mask = 1; + 8000224: 00800044 movi r2,1 + 8000228: e0bffe15 stw r2,-8(fp) + * called to clear the interrupt condition. + */ + + do + { + if (active & mask) + 800022c: e0ffff17 ldw r3,-4(fp) + 8000230: e0bffe17 ldw r2,-8(fp) + 8000234: 1884703a and r2,r3,r2 + 8000238: 10001126 beq r2,zero,8000280 + { +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_irq[i].handler(alt_irq[i].context); + 800023c: e0bffd17 ldw r2,-12(fp) + 8000240: 100690fa slli r3,r2,3 + 8000244: 008201b4 movhi r2,2054 + 8000248: 1885883a add r2,r3,r2 + 800024c: 10f8dc17 ldw r3,-7312(r2) + 8000250: e0bffd17 ldw r2,-12(fp) + 8000254: 100890fa slli r4,r2,3 + 8000258: 008201b4 movhi r2,2054 + 800025c: 2085883a add r2,r4,r2 + 8000260: 10b8dd17 ldw r2,-7308(r2) + 8000264: 1009883a mov r4,r2 + 8000268: 183ee83a callr r3 +#else + alt_irq[i].handler(alt_irq[i].context, i); +#endif + break; + 800026c: 0001883a nop + NIOS2_READ_IPENDING (active); + 8000270: 0005313a rdctl r2,ipending + 8000274: e0bffb15 stw r2,-20(fp) + return active; + 8000278: e0bffb17 ldw r2,-20(fp) + 800027c: 00000706 br 800029c + } + mask <<= 1; + 8000280: e0bffe17 ldw r2,-8(fp) + 8000284: 1085883a add r2,r2,r2 + 8000288: e0bffe15 stw r2,-8(fp) + i++; + 800028c: e0bffd17 ldw r2,-12(fp) + 8000290: 10800044 addi r2,r2,1 + 8000294: e0bffd15 stw r2,-12(fp) + if (active & mask) + 8000298: 003fe406 br 800022c + + } while (1); + + active = alt_irq_pending (); + 800029c: e0bfff15 stw r2,-4(fp) + + } while (active); + 80002a0: e0bfff17 ldw r2,-4(fp) + 80002a4: 103fde1e bne r2,zero,8000220 + + /* + * Notify the operating system that interrupt processing is complete. + */ + + ALT_OS_INT_EXIT(); + 80002a8: 80108180 call 8010818 +} + 80002ac: 0001883a nop + 80002b0: e037883a mov sp,fp + 80002b4: dfc00117 ldw ra,4(sp) + 80002b8: df000017 ldw fp,0(sp) + 80002bc: dec00204 addi sp,sp,8 + 80002c0: f800283a ret + +080002c4 : + * that handler if it has been registered. Absent a handler, it will + * break break or hang as discussed below. + */ +int +alt_instruction_exception_entry (alt_u32 exception_pc) +{ + 80002c4: defffb04 addi sp,sp,-20 + 80002c8: dfc00415 stw ra,16(sp) + 80002cc: df000315 stw fp,12(sp) + 80002d0: df000304 addi fp,sp,12 + 80002d4: e13ffd15 stw r4,-12(fp) + * NIOS2_EXCEPTION_CAUSE_NOT_PRESENT. Your handling routine should + * check the validity of the cause argument before proceeding. + */ +#ifdef NIOS2_HAS_EXTRA_EXCEPTION_INFO + /* Get exception cause & "badaddr" */ + NIOS2_READ_EXCEPTION(cause); + 80002d8: 000531fa rdctl r2,exception + 80002dc: e0bfff15 stw r2,-4(fp) + cause = ( (cause & NIOS2_EXCEPTION_REG_CAUSE_MASK) >> + 80002e0: e0bfff17 ldw r2,-4(fp) + 80002e4: 1004d0ba srli r2,r2,2 + 80002e8: 108007cc andi r2,r2,31 + 80002ec: e0bfff15 stw r2,-4(fp) + NIOS2_EXCEPTION_REG_CAUSE_OFST ); + + NIOS2_READ_BADADDR(badaddr); + 80002f0: 0005333a rdctl r2,badaddr + 80002f4: e0bffe15 stw r2,-8(fp) +#else + cause = NIOS2_EXCEPTION_CAUSE_NOT_PRESENT; + badaddr = 0; +#endif /* NIOS2_HAS_EXTRA_EXCEPTION_INFO */ + + if(alt_instruction_exception_handler) { + 80002f8: d0a0a917 ldw r2,-32092(gp) + 80002fc: 10000726 beq r2,zero,800031c + * Call handler. Its return value indicates whether the exception-causing + * instruction should be re-issued. The code that called us, + * alt_eceptions_entry.S, will look at this value and adjust the ea + * register as necessary + */ + return alt_instruction_exception_handler(cause, exception_pc, badaddr); + 8000300: d0a0a917 ldw r2,-32092(gp) + 8000304: e0ffff17 ldw r3,-4(fp) + 8000308: e1bffe17 ldw r6,-8(fp) + 800030c: e17ffd17 ldw r5,-12(fp) + 8000310: 1809883a mov r4,r3 + 8000314: 103ee83a callr r2 + 8000318: 00000206 br 8000324 + * (a peripheral which negates its interrupt output before its + * interrupt handler has been executed will cause spurious interrupts) + */ + else { +#ifdef NIOS2_HAS_DEBUG_STUB + NIOS2_BREAK(); + 800031c: 003da03a break 0 + ; +#endif /* NIOS2_HAS_DEBUG_STUB */ + } + + /* We should not get here. Remove compiler warning. */ + return NIOS2_EXCEPTION_RETURN_REISSUE_INST; + 8000320: 0005883a mov r2,zero +} + 8000324: e037883a mov sp,fp + 8000328: dfc00117 ldw ra,4(sp) + 800032c: df000017 ldw fp,0(sp) + 8000330: dec00204 addi sp,sp,8 + 8000334: f800283a ret + +Disassembly of section .text: + +08000338 <_start>: + + /* Assume the data cache size is always a power of two. */ +#if NIOS2_DCACHE_SIZE > 0x8000 + movhi r2, %hi(NIOS2_DCACHE_SIZE) +#else + movui r2, NIOS2_DCACHE_SIZE + 8000338: 00820014 movui r2,2048 +#endif + +0: + initd 0(r2) + 800033c: 10000033 initd 0(r2) +#ifdef NIOS2_ECC_PRESENT + addi r2, r2, -4 +#else + addi r2, r2, -NIOS2_DCACHE_LINE_SIZE + 8000340: 10bff804 addi r2,r2,-32 +#endif + bgt r2, zero, 0b + 8000344: 00bffd16 blt zero,r2,800033c <_start+0x4> + + /* + * Now that the caches are initialized, set up the stack pointer and global pointer. + * The values provided by the linker are assumed to be correctly aligned. + */ + movhi sp, %hi(__alt_stack_pointer) + 8000348: 06c40034 movhi sp,4096 + ori sp, sp, %lo(__alt_stack_pointer) + 800034c: dec00014 ori sp,sp,0 + movhi gp, %hi(_gp) + 8000350: 06820174 movhi gp,2053 + ori gp, gp, %lo(_gp) + 8000354: d692ae14 ori gp,gp,19128 + */ +#ifndef ALT_SIM_OPTIMIZE + /* Log that the BSS is about to be cleared. */ + ALT_LOG_PUTS(alt_log_msg_bss) + + movhi r2, %hi(__bss_start) + 8000358: 00820134 movhi r2,2052 + ori r2, r2, %lo(__bss_start) + 800035c: 10b2e314 ori r2,r2,52108 + + movhi r3, %hi(__bss_end) + 8000360: 00c20174 movhi r3,2053 + ori r3, r3, %lo(__bss_end) + 8000364: 18f96714 ori r3,r3,58780 + + beq r2, r3, 1f + 8000368: 10c00326 beq r2,r3,8000378 <_start+0x40> + +0: + stw zero, (r2) + 800036c: 10000015 stw zero,0(r2) + addi r2, r2, 4 + 8000370: 10800104 addi r2,r2,4 + bltu r2, r3, 0b + 8000374: 10fffd36 bltu r2,r3,800036c <_start+0x34> + + /* Log that alt_main is about to be called. */ + ALT_LOG_PUTS(alt_log_msg_alt_main) + + /* Call the C entry point. It should never return. */ + call alt_main + 8000378: 800fb7c0 call 800fb7c + +0800037c : + + /* Wait in infinite loop in case alt_main does return. */ +alt_after_alt_main: + br alt_after_alt_main + 800037c: 003fff06 br 800037c + +08000380 : +extern NET nets[MAXNETS]; /* pointers to the static network structs */ + +// **************************** + +void control_delay() +{ + 8000380: defffe04 addi sp,sp,-8 + 8000384: dfc00115 stw ra,4(sp) + 8000388: df000015 stw fp,0(sp) + 800038c: d839883a mov fp,sp + TK_SLEEP(1); + 8000390: 01000084 movi r4,2 + 8000394: 801730c0 call 801730c +} + 8000398: 0001883a nop + 800039c: e037883a mov sp,fp + 80003a0: dfc00117 ldw ra,4(sp) + 80003a4: df000017 ldw fp,0(sp) + 80003a8: dec00204 addi sp,sp,8 + 80003ac: f800283a ret + +080003b0 : + +// **************************** + + //simple reply +void control_pong(command_header* header) +{ + 80003b0: defffb04 addi sp,sp,-20 + 80003b4: dfc00415 stw ra,16(sp) + 80003b8: df000315 stw fp,12(sp) + 80003bc: df000304 addi fp,sp,12 + 80003c0: e13ffd15 stw r4,-12(fp) + command_header tmp; + tmp = *header; + 80003c4: e0bffd17 ldw r2,-12(fp) + 80003c8: 10c0000b ldhu r3,0(r2) + 80003cc: e0fffe8d sth r3,-6(fp) + 80003d0: 10c0008b ldhu r3,2(r2) + 80003d4: e0ffff0d sth r3,-4(fp) + 80003d8: 1080010b ldhu r2,4(r2) + 80003dc: e0bfff8d sth r2,-2(fp) + swap_bytes((char*)(void*)(&tmp), sizeof(tmp)); + 80003e0: e0bffe84 addi r2,fp,-6 + 80003e4: 01400184 movi r5,6 + 80003e8: 1009883a mov r4,r2 + 80003ec: 80027a80 call 80027a8 + ethernet_write(0, sizeof(command_header), (unsigned char*)(header)); + 80003f0: e1bffd17 ldw r6,-12(fp) + 80003f4: 01400184 movi r5,6 + 80003f8: 0009883a mov r4,zero + 80003fc: 800220c0 call 800220c +} + 8000400: 0001883a nop + 8000404: e037883a mov sp,fp + 8000408: dfc00117 ldw ra,4(sp) + 800040c: df000017 ldw fp,0(sp) + 8000410: dec00204 addi sp,sp,8 + 8000414: f800283a ret + +08000418 : + +void control_process_snapshot() +{ + 8000418: defffc04 addi sp,sp,-16 + 800041c: dfc00315 stw ra,12(sp) + 8000420: df000215 stw fp,8(sp) + 8000424: df000204 addi fp,sp,8 + command_header header = {.marker = 0x5555, .command = COMMAND_SLOWCTRL_SNAPSHOT, + 8000428: 00955544 movi r2,21845 + 800042c: e0bffe8d sth r2,-6(fp) + 8000430: 00810404 movi r2,1040 + 8000434: e0bfff0d sth r2,-4(fp) + 8000438: e03fff8d sth zero,-2(fp) + .length = 0}; //SLOWCTRL_ADC_CHANNEL_COUNT * sizeof(SLOWCTRL_ADC_DATA_TYPE) / sizeof(unsigned short)}; + swap_bytes((char*)(void*)(&header), sizeof(header)); + 800043c: e0bffe84 addi r2,fp,-6 + 8000440: 01400184 movi r5,6 + 8000444: 1009883a mov r4,r2 + 8000448: 80027a80 call 80027a8 + ethernet_write(0, sizeof(command_header), (unsigned char*)(&header)); + 800044c: e0bffe84 addi r2,fp,-6 + 8000450: 100d883a mov r6,r2 + 8000454: 01400184 movi r5,6 + 8000458: 0009883a mov r4,zero + 800045c: 800220c0 call 800220c + //ethernet_write(0, SLOWCTRL_ADC_CHANNEL_COUNT*sizeof(SLOWCTRL_ADC_DATA_TYPE), (unsigned char*)slowctrl_adc_buffer); +} + 8000460: 0001883a nop + 8000464: e037883a mov sp,fp + 8000468: dfc00117 ldw ra,4(sp) + 800046c: df000017 ldw fp,0(sp) + 8000470: dec00204 addi sp,sp,8 + 8000474: f800283a ret + +08000478 : + + //helper for the one below +int check_arp(struct arptabent * arp_entry, ip_addr ip) +{ + 8000478: defffc04 addi sp,sp,-16 + 800047c: df000315 stw fp,12(sp) + 8000480: df000304 addi fp,sp,12 + 8000484: e13ffe15 stw r4,-8(fp) + 8000488: e17ffd15 stw r5,-12(fp) + if (arp_entry->t_pro_addr != ip) + 800048c: e0bffe17 ldw r2,-8(fp) + 8000490: 10800017 ldw r2,0(r2) + 8000494: e0fffd17 ldw r3,-12(fp) + 8000498: 18800226 beq r3,r2,80004a4 + return 0; //bad IP + 800049c: 0005883a mov r2,zero + 80004a0: 00001106 br 80004e8 + + for (int i = 0; i < 6; i++) + 80004a4: e03fff15 stw zero,-4(fp) + 80004a8: 00000b06 br 80004d8 + if (arp_entry->t_phy_addr[i] != 0) + 80004ac: e0fffe17 ldw r3,-8(fp) + 80004b0: e0bfff17 ldw r2,-4(fp) + 80004b4: 1885883a add r2,r3,r2 + 80004b8: 10800103 ldbu r2,4(r2) + 80004bc: 10803fcc andi r2,r2,255 + 80004c0: 10000226 beq r2,zero,80004cc + return 1; //non-zero MAC + 80004c4: 00800044 movi r2,1 + 80004c8: 00000706 br 80004e8 + for (int i = 0; i < 6; i++) + 80004cc: e0bfff17 ldw r2,-4(fp) + 80004d0: 10800044 addi r2,r2,1 + 80004d4: e0bfff15 stw r2,-4(fp) + 80004d8: e0bfff17 ldw r2,-4(fp) + 80004dc: 10800190 cmplti r2,r2,6 + 80004e0: 103ff21e bne r2,zero,80004ac + + return 0; + 80004e4: 0005883a mov r2,zero +} + 80004e8: e037883a mov sp,fp + 80004ec: df000017 ldw fp,0(sp) + 80004f0: dec00104 addi sp,sp,4 + 80004f4: f800283a ret + +080004f8 : + +void control_process_config_peer(unsigned short* data) +{ + 80004f8: defff104 addi sp,sp,-60 + 80004fc: dfc00e15 stw ra,56(sp) + 8000500: df000d15 stw fp,52(sp) + 8000504: df000d04 addi fp,sp,52 + 8000508: e13ff615 stw r4,-40(fp) + ip_addr ip = 0; + 800050c: e03ffa15 stw zero,-24(fp) + ip_addr srcip = 0; + 8000510: e03ff915 stw zero,-28(fp) + int i; + command_header header = {.marker = 0x5555, .command = COMMAND_DAQ_CONFIG_PEER, .length = 0}; + 8000514: 00955544 movi r2,21845 + 8000518: e0bff78d sth r2,-34(fp) + 800051c: 0080cc44 movi r2,817 + 8000520: e0bff80d sth r2,-32(fp) + 8000524: e03ff88d sth zero,-30(fp) + + for (i = 0; i < 4; i++) + 8000528: e03fff15 stw zero,-4(fp) + 800052c: 00001006 br 8000570 + ip = (ip << 8) | (unsigned char)(data[3-i] & 0x00FF); + 8000530: e0bffa17 ldw r2,-24(fp) + 8000534: 1006923a slli r3,r2,8 + 8000538: 010000c4 movi r4,3 + 800053c: e0bfff17 ldw r2,-4(fp) + 8000540: 2085c83a sub r2,r4,r2 + 8000544: 1085883a add r2,r2,r2 + 8000548: 1009883a mov r4,r2 + 800054c: e0bff617 ldw r2,-40(fp) + 8000550: 1105883a add r2,r2,r4 + 8000554: 1080000b ldhu r2,0(r2) + 8000558: 10803fcc andi r2,r2,255 + 800055c: 1884b03a or r2,r3,r2 + 8000560: e0bffa15 stw r2,-24(fp) + for (i = 0; i < 4; i++) + 8000564: e0bfff17 ldw r2,-4(fp) + 8000568: 10800044 addi r2,r2,1 + 800056c: e0bfff15 stw r2,-4(fp) + 8000570: e0bfff17 ldw r2,-4(fp) + 8000574: 10800110 cmplti r2,r2,4 + 8000578: 103fed1e bne r2,zero,8000530 + + //daq_configure_peer_addr(ip, data[4]); + + printf("Querying ARP for %d.%d.%d.%d ...\n",data[0],data[1],data[2],data[3]); + 800057c: e0bff617 ldw r2,-40(fp) + 8000580: 1080000b ldhu r2,0(r2) + 8000584: 10ffffcc andi r3,r2,65535 + 8000588: e0bff617 ldw r2,-40(fp) + 800058c: 10800084 addi r2,r2,2 + 8000590: 1080000b ldhu r2,0(r2) + 8000594: 113fffcc andi r4,r2,65535 + 8000598: e0bff617 ldw r2,-40(fp) + 800059c: 10800104 addi r2,r2,4 + 80005a0: 1080000b ldhu r2,0(r2) + 80005a4: 117fffcc andi r5,r2,65535 + 80005a8: e0bff617 ldw r2,-40(fp) + 80005ac: 10800184 addi r2,r2,6 + 80005b0: 1080000b ldhu r2,0(r2) + 80005b4: 10bfffcc andi r2,r2,65535 + 80005b8: d8800015 stw r2,0(sp) + 80005bc: 280f883a mov r7,r5 + 80005c0: 200d883a mov r6,r4 + 80005c4: 180b883a mov r5,r3 + 80005c8: 01020134 movhi r4,2052 + 80005cc: 211a6a04 addi r4,r4,27048 + 80005d0: 8002c780 call 8002c78 + + struct arptabent * arp_entry = find_oldest_arp(ip); + 80005d4: e0bffa17 ldw r2,-24(fp) + 80005d8: 1009883a mov r4,r2 + 80005dc: 80233bc0 call 80233bc + 80005e0: e0bffe15 stw r2,-8(fp) + + int pingseq = 0; + 80005e4: e03ffd15 stw zero,-12(fp) + while (!check_arp(arp_entry, ip)) //big loop for pinging 10 times + 80005e8: 00002606 br 8000684 + { + printf("ARP entry could not be found, pinging!\n"); + 80005ec: 01020134 movhi r4,2052 + 80005f0: 211a7304 addi r4,r4,27084 + 80005f4: 8002d9c0 call 8002d9c + //ping the peer to ARP it. + icmpEcho(ip, NULL, 8, pingseq++); + 80005f8: e13ffa17 ldw r4,-24(fp) + 80005fc: e0bffd17 ldw r2,-12(fp) + 8000600: 10c00044 addi r3,r2,1 + 8000604: e0fffd15 stw r3,-12(fp) + 8000608: 10bfffcc andi r2,r2,65535 + 800060c: 100f883a mov r7,r2 + 8000610: 01800204 movi r6,8 + 8000614: 000b883a mov r5,zero + 8000618: 8027f0c0 call 8027f0c + + for (int i = 0; (i < 5) && (!check_arp(arp_entry, ip)); i++) //small loop for waiting 5 times after each ping + 800061c: e03ffc15 stw zero,-16(fp) + 8000620: 00000906 br 8000648 + { + TK_SLEEP(10); + 8000624: 010002c4 movi r4,11 + 8000628: 801730c0 call 801730c + arp_entry = find_oldest_arp(ip); + 800062c: e0bffa17 ldw r2,-24(fp) + 8000630: 1009883a mov r4,r2 + 8000634: 80233bc0 call 80233bc + 8000638: e0bffe15 stw r2,-8(fp) + for (int i = 0; (i < 5) && (!check_arp(arp_entry, ip)); i++) //small loop for waiting 5 times after each ping + 800063c: e0bffc17 ldw r2,-16(fp) + 8000640: 10800044 addi r2,r2,1 + 8000644: e0bffc15 stw r2,-16(fp) + 8000648: e0bffc17 ldw r2,-16(fp) + 800064c: 10800148 cmpgei r2,r2,5 + 8000650: 1000051e bne r2,zero,8000668 + 8000654: e0bffa17 ldw r2,-24(fp) + 8000658: 100b883a mov r5,r2 + 800065c: e13ffe17 ldw r4,-8(fp) + 8000660: 80004780 call 8000478 + 8000664: 103fef26 beq r2,zero,8000624 + } + + if (pingseq > 10) + 8000668: e0bffd17 ldw r2,-12(fp) + 800066c: 108002d0 cmplti r2,r2,11 + 8000670: 1000041e bne r2,zero,8000684 + { + printf("Could not resolve MAC! The result below is random!\n"); + 8000674: 01020134 movhi r4,2052 + 8000678: 211a7d04 addi r4,r4,27124 + 800067c: 8002d9c0 call 8002d9c + break; + 8000680: 00000506 br 8000698 + while (!check_arp(arp_entry, ip)) //big loop for pinging 10 times + 8000684: e0bffa17 ldw r2,-24(fp) + 8000688: 100b883a mov r5,r2 + 800068c: e13ffe17 ldw r4,-8(fp) + 8000690: 80004780 call 8000478 + 8000694: 103fd526 beq r2,zero,80005ec + } + } + + printf("Peer MAC is %02x %02x %02x %02x %02x %02x\n", + arp_entry->t_phy_addr[0], arp_entry->t_phy_addr[1], arp_entry->t_phy_addr[2], + 8000698: e0bffe17 ldw r2,-8(fp) + 800069c: 10800103 ldbu r2,4(r2) + printf("Peer MAC is %02x %02x %02x %02x %02x %02x\n", + 80006a0: 11403fcc andi r5,r2,255 + arp_entry->t_phy_addr[0], arp_entry->t_phy_addr[1], arp_entry->t_phy_addr[2], + 80006a4: e0bffe17 ldw r2,-8(fp) + 80006a8: 10800143 ldbu r2,5(r2) + printf("Peer MAC is %02x %02x %02x %02x %02x %02x\n", + 80006ac: 11803fcc andi r6,r2,255 + arp_entry->t_phy_addr[0], arp_entry->t_phy_addr[1], arp_entry->t_phy_addr[2], + 80006b0: e0bffe17 ldw r2,-8(fp) + 80006b4: 10800183 ldbu r2,6(r2) + printf("Peer MAC is %02x %02x %02x %02x %02x %02x\n", + 80006b8: 11c03fcc andi r7,r2,255 + arp_entry->t_phy_addr[3], arp_entry->t_phy_addr[4], arp_entry->t_phy_addr[5]); + 80006bc: e0bffe17 ldw r2,-8(fp) + 80006c0: 108001c3 ldbu r2,7(r2) + printf("Peer MAC is %02x %02x %02x %02x %02x %02x\n", + 80006c4: 10803fcc andi r2,r2,255 + arp_entry->t_phy_addr[3], arp_entry->t_phy_addr[4], arp_entry->t_phy_addr[5]); + 80006c8: e0fffe17 ldw r3,-8(fp) + 80006cc: 18c00203 ldbu r3,8(r3) + printf("Peer MAC is %02x %02x %02x %02x %02x %02x\n", + 80006d0: 18c03fcc andi r3,r3,255 + arp_entry->t_phy_addr[3], arp_entry->t_phy_addr[4], arp_entry->t_phy_addr[5]); + 80006d4: e13ffe17 ldw r4,-8(fp) + 80006d8: 21000243 ldbu r4,9(r4) + printf("Peer MAC is %02x %02x %02x %02x %02x %02x\n", + 80006dc: 21003fcc andi r4,r4,255 + 80006e0: d9000215 stw r4,8(sp) + 80006e4: d8c00115 stw r3,4(sp) + 80006e8: d8800015 stw r2,0(sp) + 80006ec: 01020134 movhi r4,2052 + 80006f0: 211a8a04 addi r4,r4,27176 + 80006f4: 8002c780 call 8002c78 + + srcip = nets[0]->n_ipaddr; + 80006f8: 008201b4 movhi r2,2054 + 80006fc: 10b77017 ldw r2,-8768(r2) + 8000700: 10800a17 ldw r2,40(r2) + 8000704: e0bff915 stw r2,-28(fp) + swap_quad((unsigned char*)(void*)(&srcip), 4); //UDP generator needs such a format + 8000708: e0bff904 addi r2,fp,-28 + 800070c: 01400104 movi r5,4 + 8000710: 1009883a mov r4,r2 + 8000714: 80028400 call 8002840 + swap_quad((unsigned char*)(void*)(&ip), 4); + 8000718: e0bffa04 addi r2,fp,-24 + 800071c: 01400104 movi r5,4 + 8000720: 1009883a mov r4,r2 + 8000724: 80028400 call 8002840 + + //set up udpgen with correct values + udpgen_set_size(UDP_GENERATOR_BASE, 167); //sensor_interface.v:39 + 8000728: 00c029c4 movi r3,167 + 800072c: 00861034 movhi r2,6208 + 8000730: 10cf30ad sthio r3,15554(r2) + udpgen_set_srcip(UDP_GENERATOR_BASE, srcip); + 8000734: e0bff917 ldw r2,-28(fp) + 8000738: 1007883a mov r3,r2 + 800073c: 00861034 movhi r2,6208 + 8000740: 10cf3135 stwio r3,15556(r2) + udpgen_set_dstip(UDP_GENERATOR_BASE, ip); + 8000744: e0bffa17 ldw r2,-24(fp) + 8000748: 1007883a mov r3,r2 + 800074c: 00861034 movhi r2,6208 + 8000750: 10cf3235 stwio r3,15560(r2) + udpgen_set_srcport(UDP_GENERATOR_BASE, DATA_PORT); + 8000754: 00c3e844 movi r3,4001 + 8000758: 00861034 movhi r2,6208 + 800075c: 10cf33ad sthio r3,15566(r2) + udpgen_set_dstport(UDP_GENERATOR_BASE, data[4]); + 8000760: e0bff617 ldw r2,-40(fp) + 8000764: 10800204 addi r2,r2,8 + 8000768: 1080000b ldhu r2,0(r2) + 800076c: 10ffffcc andi r3,r2,65535 + 8000770: 00861034 movhi r2,6208 + 8000774: 10cf332d sthio r3,15564(r2) + udpgen_set_dstmac_a(UDP_GENERATOR_BASE, arp_entry->t_phy_addr); + 8000778: e03ffb15 stw zero,-20(fp) + 800077c: 00001106 br 80007c4 + 8000780: e0bffb17 ldw r2,-20(fp) + 8000784: 10800404 addi r2,r2,16 + 8000788: 1007883a mov r3,r2 + 800078c: 00861034 movhi r2,6208 + 8000790: 108f3004 addi r2,r2,15552 + 8000794: 1885883a add r2,r3,r2 + 8000798: 01000144 movi r4,5 + 800079c: e0fffb17 ldw r3,-20(fp) + 80007a0: 20c7c83a sub r3,r4,r3 + 80007a4: e13ffe17 ldw r4,-8(fp) + 80007a8: 20c7883a add r3,r4,r3 + 80007ac: 18c00103 ldbu r3,4(r3) + 80007b0: 18c03fcc andi r3,r3,255 + 80007b4: 10c00025 stbio r3,0(r2) + 80007b8: e0bffb17 ldw r2,-20(fp) + 80007bc: 10800044 addi r2,r2,1 + 80007c0: e0bffb15 stw r2,-20(fp) + 80007c4: e0bffb17 ldw r2,-20(fp) + 80007c8: 10800190 cmplti r2,r2,6 + 80007cc: 103fec1e bne r2,zero,8000780 + + swap_bytes((unsigned char*)(void*)(&header), sizeof(header)); + 80007d0: e0bff784 addi r2,fp,-34 + 80007d4: 01400184 movi r5,6 + 80007d8: 1009883a mov r4,r2 + 80007dc: 80027a80 call 80027a8 + ethernet_write(0, sizeof(command_header), (unsigned char*)(&header)); + 80007e0: e0bff784 addi r2,fp,-34 + 80007e4: 100d883a mov r6,r2 + 80007e8: 01400184 movi r5,6 + 80007ec: 0009883a mov r4,zero + 80007f0: 800220c0 call 800220c +} + 80007f4: 0001883a nop + 80007f8: e037883a mov sp,fp + 80007fc: dfc00117 ldw ra,4(sp) + 8000800: df000017 ldw fp,0(sp) + 8000804: dec00204 addi sp,sp,8 + 8000808: f800283a ret + +0800080c : + +// **************************** + + //Receive command header. Return (without loosing data!) if number of received bytes is insufficient. +unsigned char control_get_header(command_header** result) +{ + 800080c: defffd04 addi sp,sp,-12 + 8000810: dfc00215 stw ra,8(sp) + 8000814: df000115 stw fp,4(sp) + 8000818: df000104 addi fp,sp,4 + 800081c: e13fff15 stw r4,-4(fp) + static command_header header; + static unsigned int bytes_received = 0; + + bytes_received += ethernet_read(0, sizeof(command_header)-bytes_received, (unsigned char*)(&header) + bytes_received); + 8000820: d0a03517 ldw r2,-32556(gp) + 8000824: 00c00184 movi r3,6 + 8000828: 1885c83a sub r2,r3,r2 + 800082c: 1009883a mov r4,r2 + 8000830: d0e03517 ldw r3,-32556(gp) + 8000834: d0a03604 addi r2,gp,-32552 + 8000838: 1885883a add r2,r3,r2 + 800083c: 100d883a mov r6,r2 + 8000840: 200b883a mov r5,r4 + 8000844: 0009883a mov r4,zero + 8000848: 80023140 call 8002314 + 800084c: 1007883a mov r3,r2 + 8000850: d0a03517 ldw r2,-32556(gp) + 8000854: 1885883a add r2,r3,r2 + 8000858: d0a03515 stw r2,-32556(gp) + + if (bytes_received < sizeof(command_header)) + 800085c: d0a03517 ldw r2,-32556(gp) + 8000860: 108001a8 cmpgeui r2,r2,6 + 8000864: 1000021e bne r2,zero,8000870 + return 0; + 8000868: 0005883a mov r2,zero + 800086c: 00000806 br 8000890 + + swap_bytes((unsigned char*)(void*)(&header),sizeof(header)); //if the header is complete, swap bytes and return it + 8000870: 01400184 movi r5,6 + 8000874: d1203604 addi r4,gp,-32552 + 8000878: 80027a80 call 80027a8 + *result = &header; + 800087c: e0bfff17 ldw r2,-4(fp) + 8000880: d0e03604 addi r3,gp,-32552 + 8000884: 10c00015 stw r3,0(r2) + bytes_received = 0; + 8000888: d0203515 stw zero,-32556(gp) + return 1; + 800088c: 00800044 movi r2,1 +} + 8000890: e037883a mov sp,fp + 8000894: dfc00117 ldw ra,4(sp) + 8000898: df000017 ldw fp,0(sp) + 800089c: dec00204 addi sp,sp,8 + 80008a0: f800283a ret + +080008a4 : + + //Receive command data. Return (without loosing data!) if number of received bytes is insufficient. + //Expected data length is given in words! +unsigned char control_get_data(unsigned short expected_length, unsigned short** data) +{ + 80008a4: defffc04 addi sp,sp,-16 + 80008a8: dfc00315 stw ra,12(sp) + 80008ac: df000215 stw fp,8(sp) + 80008b0: df000204 addi fp,sp,8 + 80008b4: 2005883a mov r2,r4 + 80008b8: e17ffe15 stw r5,-8(fp) + 80008bc: e0bfff0d sth r2,-4(fp) + static unsigned short packet_data[CONTROL_MAX_DATA_LENGTH]; + static unsigned int bytes_received = 0; + + bytes_received += ethernet_read(0, 2*expected_length - bytes_received, (unsigned char*)(&packet_data) + bytes_received); + 80008c0: e0bfff0b ldhu r2,-4(fp) + 80008c4: 1085883a add r2,r2,r2 + 80008c8: 1007883a mov r3,r2 + 80008cc: d0a03817 ldw r2,-32544(gp) + 80008d0: 1885c83a sub r2,r3,r2 + 80008d4: 1009883a mov r4,r2 + 80008d8: d0e03817 ldw r3,-32544(gp) + 80008dc: 00820174 movhi r2,2053 + 80008e0: 10b35804 addi r2,r2,-12960 + 80008e4: 1885883a add r2,r3,r2 + 80008e8: 100d883a mov r6,r2 + 80008ec: 200b883a mov r5,r4 + 80008f0: 0009883a mov r4,zero + 80008f4: 80023140 call 8002314 + 80008f8: 1007883a mov r3,r2 + 80008fc: d0a03817 ldw r2,-32544(gp) + 8000900: 1885883a add r2,r3,r2 + 8000904: d0a03815 stw r2,-32544(gp) + + if (bytes_received < (2*expected_length)) + 8000908: e0bfff0b ldhu r2,-4(fp) + 800090c: 1085883a add r2,r2,r2 + 8000910: 1007883a mov r3,r2 + 8000914: d0a03817 ldw r2,-32544(gp) + 8000918: 10c0022e bgeu r2,r3,8000924 + return 0; + 800091c: 0005883a mov r2,zero + 8000920: 00000606 br 800093c + + *data = packet_data; + 8000924: e0fffe17 ldw r3,-8(fp) + 8000928: 00820174 movhi r2,2053 + 800092c: 10b35804 addi r2,r2,-12960 + 8000930: 18800015 stw r2,0(r3) + bytes_received = 0; + 8000934: d0203815 stw zero,-32544(gp) + return 1; + 8000938: 00800044 movi r2,1 +} + 800093c: e037883a mov sp,fp + 8000940: dfc00117 ldw ra,4(sp) + 8000944: df000017 ldw fp,0(sp) + 8000948: dec00204 addi sp,sp,8 + 800094c: f800283a ret + +08000950 : + +// **************************** + +void control_step() +{ + 8000950: defffb04 addi sp,sp,-20 + 8000954: dfc00415 stw ra,16(sp) + 8000958: df000315 stw fp,12(sp) + 800095c: df000304 addi fp,sp,12 + command_header* header; + unsigned short* data; + unsigned int loop_ctr = 0; + 8000960: e03fff15 stw zero,-4(fp) + + + //get header - at this moment this is blocking! + while (!control_get_header(&header)) + 8000964: 00000706 br 8000984 + { + control_delay(); + 8000968: 80003800 call 8000380 + + if (++loop_ctr > CONTROL_TIMEOUT) + 800096c: e0bfff17 ldw r2,-4(fp) + 8000970: 10800044 addi r2,r2,1 + 8000974: e0bfff15 stw r2,-4(fp) + 8000978: e0bfff17 ldw r2,-4(fp) + 800097c: 1080fa70 cmpltui r2,r2,1001 + 8000980: 1001ae26 beq r2,zero,800103c + while (!control_get_header(&header)) + 8000984: e0bffe04 addi r2,fp,-8 + 8000988: 1009883a mov r4,r2 + 800098c: 800080c0 call 800080c + 8000990: 10803fcc andi r2,r2,255 + 8000994: 103ff426 beq r2,zero,8000968 + return; + } + } + + //check start marker + if (header->marker != 0x5555) + 8000998: e0bffe17 ldw r2,-8(fp) + 800099c: 1080000b ldhu r2,0(r2) + 80009a0: 10bfffcc andi r2,r2,65535 + 80009a4: 10955560 cmpeqi r2,r2,21845 + 80009a8: 1001a626 beq r2,zero,8001044 + return; + + + //get packet data - at this moment this is blocking! + while (!control_get_data(header->length, &data)) + 80009ac: 00000706 br 80009cc + { + control_delay(); + 80009b0: 80003800 call 8000380 + + if (++loop_ctr > CONTROL_TIMEOUT) + 80009b4: e0bfff17 ldw r2,-4(fp) + 80009b8: 10800044 addi r2,r2,1 + 80009bc: e0bfff15 stw r2,-4(fp) + 80009c0: e0bfff17 ldw r2,-4(fp) + 80009c4: 1080fa70 cmpltui r2,r2,1001 + 80009c8: 1001a026 beq r2,zero,800104c + while (!control_get_data(header->length, &data)) + 80009cc: e0bffe17 ldw r2,-8(fp) + 80009d0: 1080010b ldhu r2,4(r2) + 80009d4: 10bfffcc andi r2,r2,65535 + 80009d8: e0fffd04 addi r3,fp,-12 + 80009dc: 180b883a mov r5,r3 + 80009e0: 1009883a mov r4,r2 + 80009e4: 80008a40 call 80008a4 + 80009e8: 10803fcc andi r2,r2,255 + 80009ec: 103ff026 beq r2,zero,80009b0 + { + return; + } + } + //swap data bytes + swap_bytes((unsigned char*)(void*)data, header->length*2); + 80009f0: e0fffd17 ldw r3,-12(fp) + 80009f4: e0bffe17 ldw r2,-8(fp) + 80009f8: 1080010b ldhu r2,4(r2) + 80009fc: 10bfffcc andi r2,r2,65535 + 8000a00: 1085883a add r2,r2,r2 + 8000a04: 100b883a mov r5,r2 + 8000a08: 1809883a mov r4,r3 + 8000a0c: 80027a80 call 80027a8 + + switch(header->command) + 8000a10: e0bffe17 ldw r2,-8(fp) + 8000a14: 1080008b ldhu r2,2(r2) + 8000a18: 10bfffcc andi r2,r2,65535 + 8000a1c: 10c09420 cmpeqi r3,r2,592 + 8000a20: 1800b51e bne r3,zero,8000cf8 + 8000a24: 10c09448 cmpgei r3,r2,593 + 8000a28: 1800201e bne r3,zero,8000aac + 8000a2c: 10c08420 cmpeqi r3,r2,528 + 8000a30: 1800691e bne r3,zero,8000bd8 + 8000a34: 10c08448 cmpgei r3,r2,529 + 8000a38: 18000e1e bne r3,zero,8000a74 + 8000a3c: 10c00460 cmpeqi r3,r2,17 + 8000a40: 18004a1e bne r3,zero,8000b6c + 8000a44: 10c00488 cmpgei r3,r2,18 + 8000a48: 1800051e bne r3,zero,8000a60 + 8000a4c: 10c00060 cmpeqi r3,r2,1 + 8000a50: 1800361e bne r3,zero,8000b2c + 8000a54: 10800420 cmpeqi r2,r2,16 + 8000a58: 10003b1e bne r2,zero,8000b48 + control_pong(header); + break; + + + default: + break; + 8000a5c: 00017c06 br 8001050 + switch(header->command) + 8000a60: 10c04420 cmpeqi r3,r2,272 + 8000a64: 18004a1e bne r3,zero,8000b90 + 8000a68: 10804460 cmpeqi r2,r2,273 + 8000a6c: 1000511e bne r2,zero,8000bb4 + break; + 8000a70: 00017706 br 8001050 + switch(header->command) + 8000a74: 10c08860 cmpeqi r3,r2,545 + 8000a78: 1800721e bne r3,zero,8000c44 + 8000a7c: 10c08888 cmpgei r3,r2,546 + 8000a80: 1800051e bne r3,zero,8000a98 + 8000a84: 10c08460 cmpeqi r3,r2,529 + 8000a88: 18005c1e bne r3,zero,8000bfc + 8000a8c: 10808820 cmpeqi r2,r2,544 + 8000a90: 1000631e bne r2,zero,8000c20 + break; + 8000a94: 00016e06 br 8001050 + switch(header->command) + 8000a98: 10c08c20 cmpeqi r3,r2,560 + 8000a9c: 1800721e bne r3,zero,8000c68 + 8000aa0: 10809020 cmpeqi r2,r2,576 + 8000aa4: 1000821e bne r2,zero,8000cb0 + break; + 8000aa8: 00016906 br 8001050 + switch(header->command) + 8000aac: 10c0c8a0 cmpeqi r3,r2,802 + 8000ab0: 1800ff1e bne r3,zero,8000eb0 + 8000ab4: 10c0c8c8 cmpgei r3,r2,803 + 8000ab8: 18000e1e bne r3,zero,8000af4 + 8000abc: 10c0c420 cmpeqi r3,r2,784 + 8000ac0: 1800c81e bne r3,zero,8000de4 + 8000ac4: 10c0c448 cmpgei r3,r2,785 + 8000ac8: 1800051e bne r3,zero,8000ae0 + 8000acc: 10c09820 cmpeqi r3,r2,608 + 8000ad0: 18009e1e bne r3,zero,8000d4c + 8000ad4: 10809c20 cmpeqi r2,r2,624 + 8000ad8: 1000af1e bne r2,zero,8000d98 + break; + 8000adc: 00015c06 br 8001050 + switch(header->command) + 8000ae0: 10c0c460 cmpeqi r3,r2,785 + 8000ae4: 1800d01e bne r3,zero,8000e28 + 8000ae8: 1080c860 cmpeqi r2,r2,801 + 8000aec: 1000df1e bne r2,zero,8000e6c + break; + 8000af0: 00015706 br 8001050 + switch(header->command) + 8000af4: 10d00060 cmpeqi r3,r2,16385 + 8000af8: 1801001e bne r3,zero,8000efc + 8000afc: 10d00088 cmpgei r3,r2,16386 + 8000b00: 1800051e bne r3,zero,8000b18 + 8000b04: 10c0cc60 cmpeqi r3,r2,817 + 8000b08: 1800f01e bne r3,zero,8000ecc + 8000b0c: 10810420 cmpeqi r2,r2,1040 + 8000b10: 1000f51e bne r2,zero,8000ee8 + break; + 8000b14: 00014e06 br 8001050 + switch(header->command) + 8000b18: 10d000a0 cmpeqi r3,r2,16386 + 8000b1c: 1801091e bne r3,zero,8000f44 + 8000b20: 109000e0 cmpeqi r2,r2,16387 + 8000b24: 1001191e bne r2,zero,8000f8c + break; + 8000b28: 00014906 br 8001050 + printf("COMMAND_PING\n"); + 8000b2c: 01020134 movhi r4,2052 + 8000b30: 211a9504 addi r4,r4,27220 + 8000b34: 8002d9c0 call 8002d9c + control_pong(header); + 8000b38: e0bffe17 ldw r2,-8(fp) + 8000b3c: 1009883a mov r4,r2 + 8000b40: 80003b00 call 80003b0 + break; + 8000b44: 00014206 br 8001050 + printf("COMMAND_DEBUG_LED_OFF\n"); + 8000b48: 01020134 movhi r4,2052 + 8000b4c: 211a9904 addi r4,r4,27236 + 8000b50: 8002d9c0 call 8002d9c + led_clear(0); + 8000b54: 0009883a mov r4,zero + 8000b58: 8002abc0 call 8002abc + control_pong(header); + 8000b5c: e0bffe17 ldw r2,-8(fp) + 8000b60: 1009883a mov r4,r2 + 8000b64: 80003b00 call 80003b0 + break; + 8000b68: 00013906 br 8001050 + printf("COMMAND_DEBUG_LED_ON\n"); + 8000b6c: 01020134 movhi r4,2052 + 8000b70: 211a9f04 addi r4,r4,27260 + 8000b74: 8002d9c0 call 8002d9c + led_set(0); + 8000b78: 0009883a mov r4,zero + 8000b7c: 8002a700 call 8002a70 + control_pong(header); + 8000b80: e0bffe17 ldw r2,-8(fp) + 8000b84: 1009883a mov r4,r2 + 8000b88: 80003b00 call 80003b0 + break; + 8000b8c: 00013006 br 8001050 + printf("COMMAND_LEDS_DISABLE\n"); + 8000b90: 01020134 movhi r4,2052 + 8000b94: 211aa504 addi r4,r4,27284 + 8000b98: 8002d9c0 call 8002d9c + led4_blink_enable(0); + 8000b9c: 0009883a mov r4,zero + 8000ba0: 8002b7c0 call 8002b7c + control_pong(header); + 8000ba4: e0bffe17 ldw r2,-8(fp) + 8000ba8: 1009883a mov r4,r2 + 8000bac: 80003b00 call 80003b0 + break; + 8000bb0: 00012706 br 8001050 + printf("COMMAND_LEDS_ENABLE\n"); + 8000bb4: 01020134 movhi r4,2052 + 8000bb8: 211aab04 addi r4,r4,27308 + 8000bbc: 8002d9c0 call 8002d9c + led4_blink_enable(1); + 8000bc0: 01000044 movi r4,1 + 8000bc4: 8002b7c0 call 8002b7c + control_pong(header); + 8000bc8: e0bffe17 ldw r2,-8(fp) + 8000bcc: 1009883a mov r4,r2 + 8000bd0: 80003b00 call 80003b0 + break; + 8000bd4: 00011e06 br 8001050 + printf("COMMAND_TRIGGER_DISABLE\n"); + 8000bd8: 01020134 movhi r4,2052 + 8000bdc: 211ab004 addi r4,r4,27328 + 8000be0: 8002d9c0 call 8002d9c + master_clock_enable(0); + 8000be4: 0009883a mov r4,zero + 8000be8: 8002a140 call 8002a14 + control_pong(header); + 8000bec: e0bffe17 ldw r2,-8(fp) + 8000bf0: 1009883a mov r4,r2 + 8000bf4: 80003b00 call 80003b0 + break; + 8000bf8: 00011506 br 8001050 + printf("COMMAND_TRIGGER_ENABLE\n"); + 8000bfc: 01020134 movhi r4,2052 + 8000c00: 211ab604 addi r4,r4,27352 + 8000c04: 8002d9c0 call 8002d9c + master_clock_enable(1); + 8000c08: 01000044 movi r4,1 + 8000c0c: 8002a140 call 8002a14 + control_pong(header); + 8000c10: e0bffe17 ldw r2,-8(fp) + 8000c14: 1009883a mov r4,r2 + 8000c18: 80003b00 call 80003b0 + break; + 8000c1c: 00010c06 br 8001050 + printf("COMMAND_TRIGGER_SET_SLAVE\n"); + 8000c20: 01020134 movhi r4,2052 + 8000c24: 211abc04 addi r4,r4,27376 + 8000c28: 8002d9c0 call 8002d9c + masterslave(TRIGGER_SLAVE); + 8000c2c: 0009883a mov r4,zero + 8000c30: 80029440 call 8002944 + control_pong(header); + 8000c34: e0bffe17 ldw r2,-8(fp) + 8000c38: 1009883a mov r4,r2 + 8000c3c: 80003b00 call 80003b0 + break; + 8000c40: 00010306 br 8001050 + printf("COMMAND_TRIGGER_SET_MASTER\n"); + 8000c44: 01020134 movhi r4,2052 + 8000c48: 211ac304 addi r4,r4,27404 + 8000c4c: 8002d9c0 call 8002d9c + masterslave(TRIGGER_MASTER); + 8000c50: 01000044 movi r4,1 + 8000c54: 80029440 call 8002944 + control_pong(header); + 8000c58: e0bffe17 ldw r2,-8(fp) + 8000c5c: 1009883a mov r4,r2 + 8000c60: 80003b00 call 80003b0 + break; + 8000c64: 0000fa06 br 8001050 + printf("COMMAND_TRIGGER_SET_PERIOD: %d\n", data[0]); + 8000c68: e0bffd17 ldw r2,-12(fp) + 8000c6c: 1080000b ldhu r2,0(r2) + 8000c70: 10bfffcc andi r2,r2,65535 + 8000c74: 100b883a mov r5,r2 + 8000c78: 01020134 movhi r4,2052 + 8000c7c: 211aca04 addi r4,r4,27432 + 8000c80: 8002c780 call 8002c78 + master_clock_period((alt_u32)data[0]); //we set only 16 lsbs! + 8000c84: e0bffd17 ldw r2,-12(fp) + 8000c88: 1080000b ldhu r2,0(r2) + 8000c8c: 10bfffcc andi r2,r2,65535 + 8000c90: 1009883a mov r4,r2 + 8000c94: 80029cc0 call 80029cc + header->length = 0; + 8000c98: e0bffe17 ldw r2,-8(fp) + 8000c9c: 1000010d sth zero,4(r2) + control_pong(header); + 8000ca0: e0bffe17 ldw r2,-8(fp) + 8000ca4: 1009883a mov r4,r2 + 8000ca8: 80003b00 call 80003b0 + break; + 8000cac: 0000e806 br 8001050 + printf("COMMAND_TRIGGER_SET_TINT: %d\n", data[0]); + 8000cb0: e0bffd17 ldw r2,-12(fp) + 8000cb4: 1080000b ldhu r2,0(r2) + 8000cb8: 10bfffcc andi r2,r2,65535 + 8000cbc: 100b883a mov r5,r2 + 8000cc0: 01020134 movhi r4,2052 + 8000cc4: 211ad204 addi r4,r4,27464 + 8000cc8: 8002c780 call 8002c78 + sensor_set_shutter(SENSOR_INTERFACE_BASE, data[0]); + 8000ccc: e0bffd17 ldw r2,-12(fp) + 8000cd0: 1080000b ldhu r2,0(r2) + 8000cd4: 10ffffcc andi r3,r2,65535 + 8000cd8: 00861034 movhi r2,6208 + 8000cdc: 10cf55ad sthio r3,15702(r2) + header->length = 0; + 8000ce0: e0bffe17 ldw r2,-8(fp) + 8000ce4: 1000010d sth zero,4(r2) + control_pong(header); + 8000ce8: e0bffe17 ldw r2,-8(fp) + 8000cec: 1009883a mov r4,r2 + 8000cf0: 80003b00 call 80003b0 + break; + 8000cf4: 0000d606 br 8001050 + printf("COMMAND_SET_GAIN: %d\n", data[0]); + 8000cf8: e0bffd17 ldw r2,-12(fp) + 8000cfc: 1080000b ldhu r2,0(r2) + 8000d00: 10bfffcc andi r2,r2,65535 + 8000d04: 100b883a mov r5,r2 + 8000d08: 01020134 movhi r4,2052 + 8000d0c: 211ada04 addi r4,r4,27496 + 8000d10: 8002c780 call 8002c78 + sensor_set_gain(SENSOR_INTERFACE_BASE, data[0]); + 8000d14: e0bffd17 ldw r2,-12(fp) + 8000d18: 1080000b ldhu r2,0(r2) + 8000d1c: 10803fcc andi r2,r2,255 + 8000d20: 100d883a mov r6,r2 + 8000d24: 01400084 movi r5,2 + 8000d28: 01061034 movhi r4,6208 + 8000d2c: 210f5404 addi r4,r4,15696 + 8000d30: 8001b800 call 8001b80 + header->length = 0; + 8000d34: e0bffe17 ldw r2,-8(fp) + 8000d38: 1000010d sth zero,4(r2) + control_pong(header); + 8000d3c: e0bffe17 ldw r2,-8(fp) + 8000d40: 1009883a mov r4,r2 + 8000d44: 80003b00 call 80003b0 + break; + 8000d48: 0000c106 br 8001050 + printf("COMMAND_TRIGGER_SET_MASTER_DELAY: %d\n", data[0]); + 8000d4c: e0bffd17 ldw r2,-12(fp) + 8000d50: 1080000b ldhu r2,0(r2) + 8000d54: 10bfffcc andi r2,r2,65535 + 8000d58: 100b883a mov r5,r2 + 8000d5c: 01020134 movhi r4,2052 + 8000d60: 211ae004 addi r4,r4,27520 + 8000d64: 8002c780 call 8002c78 + set_delay(TRIGGER_MASTER, data[0]); + 8000d68: e0bffd17 ldw r2,-12(fp) + 8000d6c: 1080000b ldhu r2,0(r2) + 8000d70: 10bfffcc andi r2,r2,65535 + 8000d74: 100b883a mov r5,r2 + 8000d78: 01000044 movi r4,1 + 8000d7c: 8002bc80 call 8002bc8 + header->length = 0; + 8000d80: e0bffe17 ldw r2,-8(fp) + 8000d84: 1000010d sth zero,4(r2) + control_pong(header); + 8000d88: e0bffe17 ldw r2,-8(fp) + 8000d8c: 1009883a mov r4,r2 + 8000d90: 80003b00 call 80003b0 + break; + 8000d94: 0000ae06 br 8001050 + printf("COMMAND_TRIGGER_SET_SLAVE_DELAY: %d\n", data[0]); + 8000d98: e0bffd17 ldw r2,-12(fp) + 8000d9c: 1080000b ldhu r2,0(r2) + 8000da0: 10bfffcc andi r2,r2,65535 + 8000da4: 100b883a mov r5,r2 + 8000da8: 01020134 movhi r4,2052 + 8000dac: 211aea04 addi r4,r4,27560 + 8000db0: 8002c780 call 8002c78 + set_delay(TRIGGER_SLAVE, data[0]); + 8000db4: e0bffd17 ldw r2,-12(fp) + 8000db8: 1080000b ldhu r2,0(r2) + 8000dbc: 10bfffcc andi r2,r2,65535 + 8000dc0: 100b883a mov r5,r2 + 8000dc4: 0009883a mov r4,zero + 8000dc8: 8002bc80 call 8002bc8 + header->length = 0; + 8000dcc: e0bffe17 ldw r2,-8(fp) + 8000dd0: 1000010d sth zero,4(r2) + control_pong(header); + 8000dd4: e0bffe17 ldw r2,-8(fp) + 8000dd8: 1009883a mov r4,r2 + 8000ddc: 80003b00 call 80003b0 + break; + 8000de0: 00009b06 br 8001050 + printf("COMMAND_DAQ_DISABLE\n"); + 8000de4: 01020134 movhi r4,2052 + 8000de8: 211af404 addi r4,r4,27600 + 8000dec: 8002d9c0 call 8002d9c + sensor_set_enable(SENSOR_INTERFACE_BASE, 0); + 8000df0: 000d883a mov r6,zero + 8000df4: 01400044 movi r5,1 + 8000df8: 01061034 movhi r4,6208 + 8000dfc: 210f5404 addi r4,r4,15696 + 8000e00: 8001b800 call 8001b80 + udpgen_command_bit(UDP_GENERATOR_BASE, UDPGEN_CSR_EN_BITMASK,0); + 8000e04: 000d883a mov r6,zero + 8000e08: 01400044 movi r5,1 + 8000e0c: 01061034 movhi r4,6208 + 8000e10: 210f3004 addi r4,r4,15552 + 8000e14: 80025540 call 8002554 + control_pong(header); + 8000e18: e0bffe17 ldw r2,-8(fp) + 8000e1c: 1009883a mov r4,r2 + 8000e20: 80003b00 call 80003b0 + break; + 8000e24: 00008a06 br 8001050 + printf("COMMAND_DAQ_ENABLE\n"); + 8000e28: 01020134 movhi r4,2052 + 8000e2c: 211af904 addi r4,r4,27620 + 8000e30: 8002d9c0 call 8002d9c + udpgen_command_bit(UDP_GENERATOR_BASE, UDPGEN_CSR_EN_BITMASK,1); + 8000e34: 01800044 movi r6,1 + 8000e38: 01400044 movi r5,1 + 8000e3c: 01061034 movhi r4,6208 + 8000e40: 210f3004 addi r4,r4,15552 + 8000e44: 80025540 call 8002554 + sensor_set_enable(SENSOR_INTERFACE_BASE, 1); + 8000e48: 01800044 movi r6,1 + 8000e4c: 01400044 movi r5,1 + 8000e50: 01061034 movhi r4,6208 + 8000e54: 210f5404 addi r4,r4,15696 + 8000e58: 8001b800 call 8001b80 + control_pong(header); + 8000e5c: e0bffe17 ldw r2,-8(fp) + 8000e60: 1009883a mov r4,r2 + 8000e64: 80003b00 call 80003b0 + break; + 8000e68: 00007906 br 8001050 + printf("COMMAND_DAQ_RESET_COUNTERS\n"); + 8000e6c: 01020134 movhi r4,2052 + 8000e70: 211afe04 addi r4,r4,27640 + 8000e74: 8002d9c0 call 8002d9c + sensor_reset(SENSOR_INTERFACE_BASE); + 8000e78: 01800044 movi r6,1 + 8000e7c: 01400204 movi r5,8 + 8000e80: 01061034 movhi r4,6208 + 8000e84: 210f5404 addi r4,r4,15696 + 8000e88: 8001b800 call 8001b80 + 8000e8c: 000d883a mov r6,zero + 8000e90: 01400204 movi r5,8 + 8000e94: 01061034 movhi r4,6208 + 8000e98: 210f5404 addi r4,r4,15696 + 8000e9c: 8001b800 call 8001b80 + control_pong(header); + 8000ea0: e0bffe17 ldw r2,-8(fp) + 8000ea4: 1009883a mov r4,r2 + 8000ea8: 80003b00 call 80003b0 + break; + 8000eac: 00006806 br 8001050 + printf("COMMAND_DAQ_FLUSH_DATA\n"); + 8000eb0: 01020134 movhi r4,2052 + 8000eb4: 211b0504 addi r4,r4,27668 + 8000eb8: 8002d9c0 call 8002d9c + control_pong(header); + 8000ebc: e0bffe17 ldw r2,-8(fp) + 8000ec0: 1009883a mov r4,r2 + 8000ec4: 80003b00 call 80003b0 + break; + 8000ec8: 00006106 br 8001050 + printf("COMMAND_DAQ_CONFIG_PEER\n"); + 8000ecc: 01020134 movhi r4,2052 + 8000ed0: 211b0b04 addi r4,r4,27692 + 8000ed4: 8002d9c0 call 8002d9c + control_process_config_peer(data); + 8000ed8: e0bffd17 ldw r2,-12(fp) + 8000edc: 1009883a mov r4,r2 + 8000ee0: 80004f80 call 80004f8 + break; + 8000ee4: 00005a06 br 8001050 + printf("COMMAND_SLOWCTRL_SNAPSHOT\n"); + 8000ee8: 01020134 movhi r4,2052 + 8000eec: 211b1104 addi r4,r4,27716 + 8000ef0: 8002d9c0 call 8002d9c + control_process_snapshot(); + 8000ef4: 80004180 call 8000418 + break; + 8000ef8: 00005506 br 8001050 + printf("COMMAND_SET_CLUSTER_THRESHOLD: %d\n", data[0]); + 8000efc: e0bffd17 ldw r2,-12(fp) + 8000f00: 1080000b ldhu r2,0(r2) + 8000f04: 10bfffcc andi r2,r2,65535 + 8000f08: 100b883a mov r5,r2 + 8000f0c: 01020134 movhi r4,2052 + 8000f10: 211b1804 addi r4,r4,27744 + 8000f14: 8002c780 call 8002c78 + sensor_set_cluster_threshold(SENSOR_INTERFACE_BASE,data[0]); + 8000f18: e0bffd17 ldw r2,-12(fp) + 8000f1c: 1080000b ldhu r2,0(r2) + 8000f20: 10ffffcc andi r3,r2,65535 + 8000f24: 00861034 movhi r2,6208 + 8000f28: 10cf5725 stbio r3,15708(r2) + header->length = 0; + 8000f2c: e0bffe17 ldw r2,-8(fp) + 8000f30: 1000010d sth zero,4(r2) + control_pong(header); + 8000f34: e0bffe17 ldw r2,-8(fp) + 8000f38: 1009883a mov r4,r2 + 8000f3c: 80003b00 call 80003b0 + break; + 8000f40: 00004306 br 8001050 + printf("COMMAND_SET_CLUSTER_SIZE: %d\n", data[0]); + 8000f44: e0bffd17 ldw r2,-12(fp) + 8000f48: 1080000b ldhu r2,0(r2) + 8000f4c: 10bfffcc andi r2,r2,65535 + 8000f50: 100b883a mov r5,r2 + 8000f54: 01020134 movhi r4,2052 + 8000f58: 211b2104 addi r4,r4,27780 + 8000f5c: 8002c780 call 8002c78 + sensor_set_cluster_size(SENSOR_INTERFACE_BASE,data[0]); + 8000f60: e0bffd17 ldw r2,-12(fp) + 8000f64: 1080000b ldhu r2,0(r2) + 8000f68: 10ffffcc andi r3,r2,65535 + 8000f6c: 00861034 movhi r2,6208 + 8000f70: 10cf5765 stbio r3,15709(r2) + header->length = 0; + 8000f74: e0bffe17 ldw r2,-8(fp) + 8000f78: 1000010d sth zero,4(r2) + control_pong(header); + 8000f7c: e0bffe17 ldw r2,-8(fp) + 8000f80: 1009883a mov r4,r2 + 8000f84: 80003b00 call 80003b0 + break; + 8000f88: 00003106 br 8001050 + if (header->length>=2){ + 8000f8c: e0bffe17 ldw r2,-8(fp) + 8000f90: 1080010b ldhu r2,4(r2) + 8000f94: 10bfffcc andi r2,r2,65535 + 8000f98: 108000b0 cmpltui r2,r2,2 + 8000f9c: 10001a1e bne r2,zero,8001008 + calibration_ram_set_factor(CALIBRATION_RAM_BASE,data[0],data[1]); //i is channelID + 8000fa0: e0bffd17 ldw r2,-12(fp) + 8000fa4: 1080000b ldhu r2,0(r2) + 8000fa8: 10bfffcc andi r2,r2,65535 + 8000fac: 1085883a add r2,r2,r2 + 8000fb0: 1007883a mov r3,r2 + 8000fb4: 00861034 movhi r2,6208 + 8000fb8: 108d0004 addi r2,r2,13312 + 8000fbc: 1885883a add r2,r3,r2 + 8000fc0: e0fffd17 ldw r3,-12(fp) + 8000fc4: 18c00084 addi r3,r3,2 + 8000fc8: 18c0000b ldhu r3,0(r3) + 8000fcc: 18ffffcc andi r3,r3,65535 + 8000fd0: 10c0002d sthio r3,0(r2) + printf("COMMAND_SET_CALIBRATION_FACTOR ChannelIP%d : %d\n", data[0],data[1]); + 8000fd4: e0bffd17 ldw r2,-12(fp) + 8000fd8: 1080000b ldhu r2,0(r2) + 8000fdc: 10ffffcc andi r3,r2,65535 + 8000fe0: e0bffd17 ldw r2,-12(fp) + 8000fe4: 10800084 addi r2,r2,2 + 8000fe8: 1080000b ldhu r2,0(r2) + 8000fec: 10bfffcc andi r2,r2,65535 + 8000ff0: 100d883a mov r6,r2 + 8000ff4: 180b883a mov r5,r3 + 8000ff8: 01020134 movhi r4,2052 + 8000ffc: 211b2904 addi r4,r4,27812 + 8001000: 8002c780 call 8002c78 + 8001004: 00000706 br 8001024 + printf("COMMAND_SET_CALIBRATION_FACTOR length: %d\n", header->length); + 8001008: e0bffe17 ldw r2,-8(fp) + 800100c: 1080010b ldhu r2,4(r2) + 8001010: 10bfffcc andi r2,r2,65535 + 8001014: 100b883a mov r5,r2 + 8001018: 01020134 movhi r4,2052 + 800101c: 211b3604 addi r4,r4,27864 + 8001020: 8002c780 call 8002c78 + header->length = 0; + 8001024: e0bffe17 ldw r2,-8(fp) + 8001028: 1000010d sth zero,4(r2) + control_pong(header); + 800102c: e0bffe17 ldw r2,-8(fp) + 8001030: 1009883a mov r4,r2 + 8001034: 80003b00 call 80003b0 + break; + 8001038: 00000506 br 8001050 + return; + 800103c: 0001883a nop + 8001040: 00000306 br 8001050 + return; + 8001044: 0001883a nop + 8001048: 00000106 br 8001050 + return; + 800104c: 0001883a nop + } + +} + 8001050: e037883a mov sp,fp + 8001054: dfc00117 ldw ra,4(sp) + 8001058: df000017 ldw fp,0(sp) + 800105c: dec00204 addi sp,sp,8 + 8001060: f800283a ret + +08001064 : + CONTROL_STACK_SIZE, +}; + + +void ControlTask(void* param) +{ + 8001064: defffc04 addi sp,sp,-16 + 8001068: dfc00315 stw ra,12(sp) + 800106c: df000215 stw fp,8(sp) + 8001070: df000204 addi fp,sp,8 + 8001074: e13ffe15 stw r4,-8(fp) + printf ("::: Control task started ::: \n"); + 8001078: 01020134 movhi r4,2052 + 800107c: 211b4504 addi r4,r4,27924 + 8001080: 8002d9c0 call 8002d9c + ethernet_listen(0, CONTROL_PORT); + 8001084: 0143e804 movi r5,4000 + 8001088: 0009883a mov r4,zero + 800108c: 80020d00 call 80020d0 + + sensor_preconfigure(SENSOR_INTERFACE_BASE); + 8001090: 01061034 movhi r4,6208 + 8001094: 210f5404 addi r4,r4,15696 + 8001098: 8001c080 call 8001c08 + + //initial calibration factor here + printf("Initiate Calibration Factor 1 to 320 from channel1 to channel320 \n"); + 800109c: 01020134 movhi r4,2052 + 80010a0: 211b4d04 addi r4,r4,27956 + 80010a4: 8002d9c0 call 8002d9c + + + for (alt_u32 i = 0; i < 320; i++) { + 80010a8: e03fff15 stw zero,-4(fp) + 80010ac: 00000b06 br 80010dc + //pow(2,13)=8192. represent calibration factor 1; range[0.00012,8) + //default calibration factor is 1. + calibration_ram_set_factor(CALIBRATION_RAM_BASE,i,8192); //i is channelID + 80010b0: e0bfff17 ldw r2,-4(fp) + 80010b4: 1085883a add r2,r2,r2 + 80010b8: 1007883a mov r3,r2 + 80010bc: 00861034 movhi r2,6208 + 80010c0: 108d0004 addi r2,r2,13312 + 80010c4: 1885883a add r2,r3,r2 + 80010c8: 00c80004 movi r3,8192 + 80010cc: 10c0002d sthio r3,0(r2) + for (alt_u32 i = 0; i < 320; i++) { + 80010d0: e0bfff17 ldw r2,-4(fp) + 80010d4: 10800044 addi r2,r2,1 + 80010d8: e0bfff15 stw r2,-4(fp) + 80010dc: e0bfff17 ldw r2,-4(fp) + 80010e0: 10805030 cmpltui r2,r2,320 + 80010e4: 103ff21e bne r2,zero,80010b0 + } + + while(1) + control_step(); + 80010e8: 80009500 call 8000950 + 80010ec: 003ffe06 br 80010e8 + +080010f0 : +} + +void control_init() +{ + 80010f0: defffe04 addi sp,sp,-8 + 80010f4: dfc00115 stw ra,4(sp) + 80010f8: df000015 stw fp,0(sp) + 80010fc: d839883a mov fp,sp + TK_NEWTASK(&controltask); + 8001100: 01020174 movhi r4,2053 + 8001104: 212e4804 addi r4,r4,-18144 + 8001108: 80290740 call 8029074 +} + 800110c: 0001883a nop + 8001110: e037883a mov sp,fp + 8001114: dfc00117 ldw ra,4(sp) + 8001118: df000017 ldw fp,0(sp) + 800111c: dec00204 addi sp,sp,8 + 8001120: f800283a ret + +08001124 : +/* InitialTask will initialize the NicheStack + * TCP/IP Stack and then initialize the rest of the Simple Socket Server example + * RTOS structures and tasks. + */ +void InitialTask(void *task_data) +{ + 8001124: defffc04 addi sp,sp,-16 + 8001128: dfc00315 stw ra,12(sp) + 800112c: df000215 stw fp,8(sp) + 8001130: df000204 addi fp,sp,8 + 8001134: e13ffe15 stw r4,-8(fp) + * I/O drivers are available. Two tasks are created: + * "Inet main" task with priority 2 + * "clock tick" task with priority 3 + */ + + alt_iniche_init(); + 8001138: 80293dc0 call 80293dc + netmain(); + 800113c: 80278140 call 8027814 + + /* Wait for the network stack to be ready before proceeding. + * iniche_net_ready indicates that TCP/IP stack is ready, and IP address is obtained. + */ + while (!iniche_net_ready){ + 8001140: 00000206 br 800114c + TK_SLEEP(1); + 8001144: 01000084 movi r4,2 + 8001148: 801730c0 call 801730c + while (!iniche_net_ready){ + 800114c: d0a06f17 ldw r2,-32324(gp) + 8001150: 103ffc26 beq r2,zero,8001144 + + /* Now that the stack is running, perform the application initialization steps */ + + /* Application Specific Task Launching Code Block Begin */ + + printf("\nSocket Server starting up\n"); + 8001154: 01020134 movhi r4,2052 + 8001158: 211b5e04 addi r4,r4,28024 + 800115c: 8002d9c0 call 8002d9c + + /* Create tasks */ + ethernet_init(); + 8001160: 80020500 call 8002050 + control_init(); + 8001164: 80010f00 call 80010f0 + //TK_NEWTASK(&ssconntask); + + /* Application Specific Task Launching Code Block End */ + + /*This task is deleted because there is no need for it to run again */ + error_code = OSTaskDel(OS_PRIO_SELF); + 8001168: 01003fc4 movi r4,255 + 800116c: 80167f00 call 80167f0 + 8001170: e0bfffc5 stb r2,-1(fp) + //alt_uCOSIIErrorHandler(error_code, 0); + + while (1); /* Correct Program Flow should never get here */ + 8001174: 003fff06 br 8001174 + +08001178
: + +/* Main creates a single task, SSSInitialTask, and starts task scheduler. + */ + +int main (int argc, char* argv[], char* envp[]) +{ + 8001178: defff504 addi sp,sp,-44 + 800117c: dfc00a15 stw ra,40(sp) + 8001180: df000915 stw fp,36(sp) + 8001184: df000904 addi fp,sp,36 + 8001188: e13ffe15 stw r4,-8(fp) + 800118c: e17ffd15 stw r5,-12(fp) + 8001190: e1bffc15 stw r6,-16(fp) + + INT8U error_code; + + /* Clear the RTOS timer */ + OSTimeSet(0); + 8001194: 0009883a mov r4,zero + 8001198: 80177340 call 8017734 + + /* SSSInitialTask will initialize the NicheStack + * TCP/IP Stack and then initialize the rest of the Simple Socket Server example + * RTOS structures and tasks. + */ + error_code = OSTaskCreateExt(InitialTask, + 800119c: d8000415 stw zero,16(sp) + 80011a0: d8000315 stw zero,12(sp) + 80011a4: 008e0004 movi r2,14336 + 80011a8: d8800215 stw r2,8(sp) + 80011ac: 00820174 movhi r2,2053 + 80011b0: 10b38b04 addi r2,r2,-12756 + 80011b4: d8800115 stw r2,4(sp) + 80011b8: 00800144 movi r2,5 + 80011bc: d8800015 stw r2,0(sp) + 80011c0: 01c00144 movi r7,5 + 80011c4: 018201b4 movhi r6,2054 + 80011c8: 31ab8b04 addi r6,r6,-20948 + 80011cc: 000b883a mov r5,zero + 80011d0: 01020034 movhi r4,2048 + 80011d4: 21044904 addi r4,r4,4388 + 80011d8: 801664c0 call 801664c + 80011dc: e0bfffc5 stb r2,-1(fp) + + /* + * As with all MicroC/OS-II designs, once the initial thread(s) and + * associated RTOS resources are declared, we start the RTOS. That's it! + */ + OSStart(); + 80011e0: 8010a700 call 8010a70 + + + + while(1); /* Correct Program Flow never gets here. */ + 80011e4: 003fff06 br 80011e4 + +080011e8 : +* Read the MAC address in a board specific way. Prompt user to enter serial +* number to generate MAC address if failed to read from flash. +* +*/ +int get_mac_addr(NET net, unsigned char mac_addr[6]) +{ + 80011e8: defffb04 addi sp,sp,-20 + 80011ec: dfc00415 stw ra,16(sp) + 80011f0: df000315 stw fp,12(sp) + 80011f4: df000304 addi fp,sp,12 + 80011f8: e13ffe15 stw r4,-8(fp) + 80011fc: e17ffd15 stw r5,-12(fp) + error_t error = 0; + 8001200: e03fff15 stw zero,-4(fp) + + error = get_board_mac_addr(mac_addr); + 8001204: e13ffd17 ldw r4,-12(fp) + 8001208: 80018b40 call 80018b4 + 800120c: e0bfff15 stw r2,-4(fp) + + if(error) + 8001210: e0bfff17 ldw r2,-4(fp) + 8001214: 10000326 beq r2,zero,8001224 + { + /* Failed read MAC address from flash, prompt user to enter serial + number to generate MAC address. */ + error = generate_mac_addr(mac_addr); + 8001218: e13ffd17 ldw r4,-12(fp) + 800121c: 80017800 call 8001780 + 8001220: e0bfff15 stw r2,-4(fp) + } + return error; + 8001224: e0bfff17 ldw r2,-4(fp) +} + 8001228: e037883a mov sp,fp + 800122c: dfc00117 ldw ra,4(sp) + 8001230: df000017 ldw fp,0(sp) + 8001234: dec00204 addi sp,sp,8 + 8001238: f800283a ret + +0800123c : +int get_ip_addr(alt_iniche_dev *p_dev, + ip_addr* ipaddr, + ip_addr* netmask, + ip_addr* gw, + int* use_dhcp) +{ + 800123c: defff804 addi sp,sp,-32 + 8001240: dfc00715 stw ra,28(sp) + 8001244: df000615 stw fp,24(sp) + 8001248: df000604 addi fp,sp,24 + 800124c: e13ffe15 stw r4,-8(fp) + 8001250: e17ffd15 stw r5,-12(fp) + 8001254: e1bffc15 stw r6,-16(fp) + 8001258: e1fffb15 stw r7,-20(fp) + + alt_u32 sw_state = ~(IORD_ALTERA_AVALON_PIO_DATA(BUTTON_PIO_BASE)); + 800125c: 00861034 movhi r2,6208 + 8001260: 108f5037 ldwio r2,15680(r2) + 8001264: 0084303a nor r2,zero,r2 + 8001268: e0bfff15 stw r2,-4(fp) + + printf("Input state: 0x%08lx\n", sw_state); + 800126c: e17fff17 ldw r5,-4(fp) + 8001270: 01020134 movhi r4,2052 + 8001274: 211b6504 addi r4,r4,28052 + 8001278: 8002c780 call 8002c78 + IP4_ADDR(*netmask, 0, 0, 0, 0); + printf("DHCP enabled.\n"); + } + else + {*/ + *use_dhcp = 0; + 800127c: e0800217 ldw r2,8(fp) + 8001280: 10000015 stw zero,0(r2) + IP4_ADDR(*ipaddr, IPADDR0, IPADDR1, IPADDR2, IPADDR3+((sw_state>>4)&0x0F)); + 8001284: e0bfff17 ldw r2,-4(fp) + 8001288: 1004d13a srli r2,r2,4 + 800128c: 108003cc andi r2,r2,15 + 8001290: 10800404 addi r2,r2,16 + 8001294: 1006963a slli r3,r2,24 + 8001298: 008001f4 movhi r2,7 + 800129c: 10800284 addi r2,r2,10 + 80012a0: 1886b03a or r3,r3,r2 + 80012a4: e0bffd17 ldw r2,-12(fp) + 80012a8: 10c00015 stw r3,0(r2) + IP4_ADDR(*gw, GWADDR0, GWADDR1, GWADDR2, GWADDR3); + 80012ac: e0fffb17 ldw r3,-20(fp) + 80012b0: 008041f4 movhi r2,263 + 80012b4: 10800284 addi r2,r2,10 + 80012b8: 18800015 stw r2,0(r3) + IP4_ADDR(*netmask, MSKADDR0, MSKADDR1, MSKADDR2, MSKADDR3); + 80012bc: e0fffc17 ldw r3,-16(fp) + 80012c0: 00804034 movhi r2,256 + 80012c4: 10bfffc4 addi r2,r2,-1 + 80012c8: 18800015 stw r2,0(r3) + printf("DHCP disabled.\n"); + 80012cc: 01020134 movhi r4,2052 + 80012d0: 211b6b04 addi r4,r4,28076 + 80012d4: 8002d9c0 call 8002d9c + printf("Static IP Address is %d.%d.%d.%d\n", + ip4_addr1(*ipaddr), + 80012d8: e0bffd17 ldw r2,-12(fp) + 80012dc: 10800017 ldw r2,0(r2) + 80012e0: 1006d63a srli r3,r2,24 + 80012e4: e0bffd17 ldw r2,-12(fp) + 80012e8: 10800017 ldw r2,0(r2) + 80012ec: 1004d23a srli r2,r2,8 + 80012f0: 10bfc00c andi r2,r2,65280 + 80012f4: 1886b03a or r3,r3,r2 + 80012f8: e0bffd17 ldw r2,-12(fp) + 80012fc: 10800017 ldw r2,0(r2) + 8001300: 1004923a slli r2,r2,8 + 8001304: 10803fec andhi r2,r2,255 + 8001308: 1886b03a or r3,r3,r2 + 800130c: e0bffd17 ldw r2,-12(fp) + 8001310: 10800017 ldw r2,0(r2) + 8001314: 1004963a slli r2,r2,24 + 8001318: 1884b03a or r2,r3,r2 + 800131c: 1008d63a srli r4,r2,24 + ip4_addr2(*ipaddr), + 8001320: e0bffd17 ldw r2,-12(fp) + 8001324: 10800017 ldw r2,0(r2) + 8001328: 1006d63a srli r3,r2,24 + 800132c: e0bffd17 ldw r2,-12(fp) + 8001330: 10800017 ldw r2,0(r2) + 8001334: 1004d23a srli r2,r2,8 + 8001338: 10bfc00c andi r2,r2,65280 + 800133c: 1886b03a or r3,r3,r2 + 8001340: e0bffd17 ldw r2,-12(fp) + 8001344: 10800017 ldw r2,0(r2) + 8001348: 1004923a slli r2,r2,8 + 800134c: 10803fec andhi r2,r2,255 + 8001350: 1886b03a or r3,r3,r2 + 8001354: e0bffd17 ldw r2,-12(fp) + 8001358: 10800017 ldw r2,0(r2) + 800135c: 1004963a slli r2,r2,24 + 8001360: 1884b03a or r2,r3,r2 + 8001364: 1004d43a srli r2,r2,16 + printf("Static IP Address is %d.%d.%d.%d\n", + 8001368: 11403fcc andi r5,r2,255 + ip4_addr3(*ipaddr), + 800136c: e0bffd17 ldw r2,-12(fp) + 8001370: 10800017 ldw r2,0(r2) + 8001374: 1006d63a srli r3,r2,24 + 8001378: e0bffd17 ldw r2,-12(fp) + 800137c: 10800017 ldw r2,0(r2) + 8001380: 1004d23a srli r2,r2,8 + 8001384: 10bfc00c andi r2,r2,65280 + 8001388: 1886b03a or r3,r3,r2 + 800138c: e0bffd17 ldw r2,-12(fp) + 8001390: 10800017 ldw r2,0(r2) + 8001394: 1004923a slli r2,r2,8 + 8001398: 10803fec andhi r2,r2,255 + 800139c: 1886b03a or r3,r3,r2 + 80013a0: e0bffd17 ldw r2,-12(fp) + 80013a4: 10800017 ldw r2,0(r2) + 80013a8: 1004963a slli r2,r2,24 + 80013ac: 1884b03a or r2,r3,r2 + 80013b0: 1004d23a srli r2,r2,8 + printf("Static IP Address is %d.%d.%d.%d\n", + 80013b4: 11803fcc andi r6,r2,255 + ip4_addr4(*ipaddr)); + 80013b8: e0bffd17 ldw r2,-12(fp) + 80013bc: 10800017 ldw r2,0(r2) + 80013c0: 1006d63a srli r3,r2,24 + 80013c4: e0bffd17 ldw r2,-12(fp) + 80013c8: 10800017 ldw r2,0(r2) + 80013cc: 1004d23a srli r2,r2,8 + 80013d0: 10bfc00c andi r2,r2,65280 + 80013d4: 1886b03a or r3,r3,r2 + 80013d8: e0bffd17 ldw r2,-12(fp) + 80013dc: 10800017 ldw r2,0(r2) + 80013e0: 1004923a slli r2,r2,8 + 80013e4: 10803fec andhi r2,r2,255 + 80013e8: 1886b03a or r3,r3,r2 + 80013ec: e0bffd17 ldw r2,-12(fp) + 80013f0: 10800017 ldw r2,0(r2) + 80013f4: 1004963a slli r2,r2,24 + 80013f8: 1884b03a or r2,r3,r2 + printf("Static IP Address is %d.%d.%d.%d\n", + 80013fc: 10803fcc andi r2,r2,255 + 8001400: d8800015 stw r2,0(sp) + 8001404: 300f883a mov r7,r6 + 8001408: 280d883a mov r6,r5 + 800140c: 200b883a mov r5,r4 + 8001410: 01020134 movhi r4,2052 + 8001414: 211b6f04 addi r4,r4,28092 + 8001418: 8002c780 call 8002c78 + //} + + + /* Non-standard API: return 1 for success */ + return 1; + 800141c: 00800044 movi r2,1 +} + 8001420: e037883a mov sp,fp + 8001424: dfc00117 ldw ra,4(sp) + 8001428: df000017 ldw fp,0(sp) + 800142c: dec00204 addi sp,sp,8 + 8001430: f800283a ret + +08001434 : +* +* Prompt user to enter 9-digit serial number. +* +*/ +alt_u32 get_serial_number (void) +{ + 8001434: defff904 addi sp,sp,-28 + 8001438: dfc00615 stw ra,24(sp) + 800143c: df000515 stw fp,20(sp) + 8001440: df000504 addi fp,sp,20 + alt_u32 ser_num = 0; + 8001444: e03fff15 stw zero,-4(fp) + char serial_number[9]; + int i = 0; + 8001448: e03ffe15 stw zero,-8(fp) + + while(!ser_num) + 800144c: 00005606 br 80015a8 + { + printf("Please enter your 9-digit serial number. This is printed on a \n"); + 8001450: 01020134 movhi r4,2052 + 8001454: 211b7804 addi r4,r4,28128 + 8001458: 8002d9c0 call 8002d9c + printf("label under your Nios dev. board. The first 3 digits of the \n"); + 800145c: 01020134 movhi r4,2052 + 8001460: 211b8804 addi r4,r4,28192 + 8001464: 8002d9c0 call 8002d9c + printf("label are ASJ and the serial number follows this.\n -->"); + 8001468: 01020134 movhi r4,2052 + 800146c: 211b9804 addi r4,r4,28256 + 8001470: 8002c780 call 8002c78 + + for(i=0; i<9; i++) + 8001474: e03ffe15 stw zero,-8(fp) + 8001478: 00001d06 br 80014f0 + { + serial_number[i] = getchar(); + 800147c: 8002c380 call 8002c38 + 8001480: 1007883a mov r3,r2 + 8001484: e0bffe17 ldw r2,-8(fp) + 8001488: e085883a add r2,fp,r2 + 800148c: 10fffbc5 stb r3,-17(r2) + putchar(serial_number[i]); + 8001490: e0bffe17 ldw r2,-8(fp) + 8001494: e085883a add r2,fp,r2 + 8001498: 10bffbc3 ldbu r2,-17(r2) + 800149c: 10803fcc andi r2,r2,255 + 80014a0: 1080201c xori r2,r2,128 + 80014a4: 10bfe004 addi r2,r2,-128 + 80014a8: 1009883a mov r4,r2 + 80014ac: 8002cb80 call 8002cb8 + + /* Handle backspaces. How civilized. */ + if ((serial_number[i] == 0x08) && (i >= 0)) + 80014b0: e0bffe17 ldw r2,-8(fp) + 80014b4: e085883a add r2,fp,r2 + 80014b8: 10bffbc3 ldbu r2,-17(r2) + 80014bc: 10803fcc andi r2,r2,255 + 80014c0: 1080201c xori r2,r2,128 + 80014c4: 10bfe004 addi r2,r2,-128 + 80014c8: 10800218 cmpnei r2,r2,8 + 80014cc: 1000051e bne r2,zero,80014e4 + 80014d0: e0bffe17 ldw r2,-8(fp) + 80014d4: 10000316 blt r2,zero,80014e4 + { + i--; + 80014d8: e0bffe17 ldw r2,-8(fp) + 80014dc: 10bfffc4 addi r2,r2,-1 + 80014e0: e0bffe15 stw r2,-8(fp) + for(i=0; i<9; i++) + 80014e4: e0bffe17 ldw r2,-8(fp) + 80014e8: 10800044 addi r2,r2,1 + 80014ec: e0bffe15 stw r2,-8(fp) + 80014f0: e0bffe17 ldw r2,-8(fp) + 80014f4: 10800250 cmplti r2,r2,9 + 80014f8: 103fe01e bne r2,zero,800147c + } + } + printf("\n"); + 80014fc: 01000284 movi r4,10 + 8001500: 8002cb80 call 8002cb8 + + for(i=0; i<9; i++) + 8001504: e03ffe15 stw zero,-8(fp) + 8001508: 00002406 br 800159c + { + if (isdigit(serial_number[i])) + 800150c: e0bffe17 ldw r2,-8(fp) + 8001510: e085883a add r2,fp,r2 + 8001514: 10bffbc3 ldbu r2,-17(r2) + 8001518: 10803fcc andi r2,r2,255 + 800151c: 1080201c xori r2,r2,128 + 8001520: 10bfe004 addi r2,r2,-128 + 8001524: 10c00044 addi r3,r2,1 + 8001528: 00820134 movhi r2,2052 + 800152c: 109c7584 addi r2,r2,29142 + 8001530: 1885883a add r2,r3,r2 + 8001534: 10800003 ldbu r2,0(r2) + 8001538: 10803fcc andi r2,r2,255 + 800153c: 1080010c andi r2,r2,4 + 8001540: 10000e26 beq r2,zero,800157c + { + ser_num *= 10; + 8001544: e0bfff17 ldw r2,-4(fp) + 8001548: 108002a4 muli r2,r2,10 + 800154c: e0bfff15 stw r2,-4(fp) + ser_num += serial_number[i] - '0'; + 8001550: e0bffe17 ldw r2,-8(fp) + 8001554: e085883a add r2,fp,r2 + 8001558: 10bffbc3 ldbu r2,-17(r2) + 800155c: 10c03fcc andi r3,r2,255 + 8001560: 18c0201c xori r3,r3,128 + 8001564: 18ffe004 addi r3,r3,-128 + 8001568: e0bfff17 ldw r2,-4(fp) + 800156c: 1885883a add r2,r3,r2 + 8001570: 10bff404 addi r2,r2,-48 + 8001574: e0bfff15 stw r2,-4(fp) + 8001578: 00000506 br 8001590 + } + else + { + ser_num = 0; + 800157c: e03fff15 stw zero,-4(fp) + printf("Serial number only contains decimal digits and is non-zero\n"); + 8001580: 01020134 movhi r4,2052 + 8001584: 211ba604 addi r4,r4,28312 + 8001588: 8002d9c0 call 8002d9c + break; + 800158c: 00000606 br 80015a8 + for(i=0; i<9; i++) + 8001590: e0bffe17 ldw r2,-8(fp) + 8001594: 10800044 addi r2,r2,1 + 8001598: e0bffe15 stw r2,-8(fp) + 800159c: e0bffe17 ldw r2,-8(fp) + 80015a0: 10800250 cmplti r2,r2,9 + 80015a4: 103fd91e bne r2,zero,800150c + while(!ser_num) + 80015a8: e0bfff17 ldw r2,-4(fp) + 80015ac: 103fa826 beq r2,zero,8001450 + } + } + } + + return ser_num; + 80015b0: e0bfff17 ldw r2,-4(fp) +} + 80015b4: e037883a mov sp,fp + 80015b8: dfc00117 ldw ra,4(sp) + 80015bc: df000017 ldw fp,0(sp) + 80015c0: dec00204 addi sp,sp,8 + 80015c4: f800283a ret + +080015c8 : + * sections. These fail-safe static settings are compatible with previous + * Nios Ethernet designs, and allow the "factory-safe" design to behave + * as expected if the last flash sector is erased. + */ +error_t generate_and_store_mac_addr() +{ + 80015c8: deffef04 addi sp,sp,-68 + 80015cc: dfc01015 stw ra,64(sp) + 80015d0: df000f15 stw fp,60(sp) + 80015d4: df000f04 addi fp,sp,60 + error_t error = -1; + 80015d8: 00bfffc4 movi r2,-1 + 80015dc: e0bfff15 stw r2,-4(fp) + alt_u32 ser_num = 0; + 80015e0: e03ffe15 stw zero,-8(fp) + char flash_content[32]; + alt_flash_fd* flash_handle; + + printf("Can't read the MAC address from your board (this probably means\n"); + 80015e4: 01020134 movhi r4,2052 + 80015e8: 211bb504 addi r4,r4,28372 + 80015ec: 8002d9c0 call 8002d9c + printf("that your flash was erased). We will assign you a MAC address and\n"); + 80015f0: 01020134 movhi r4,2052 + 80015f4: 211bc504 addi r4,r4,28436 + 80015f8: 8002d9c0 call 8002d9c + printf("static network settings\n\n"); + 80015fc: 01020134 movhi r4,2052 + 8001600: 211bd604 addi r4,r4,28504 + 8001604: 8002d9c0 call 8002d9c + + ser_num = get_serial_number(); + 8001608: 80014340 call 8001434 + 800160c: e0bffe15 stw r2,-8(fp) + + if (ser_num) + 8001610: e0bffe17 ldw r2,-8(fp) + 8001614: 10005426 beq r2,zero,8001768 + { + /* This says the image is safe */ + flash_content[0] = 0xfe; + 8001618: 00bfff84 movi r2,-2 + 800161c: e0bff105 stb r2,-60(fp) + flash_content[1] = 0x5a; + 8001620: 00801684 movi r2,90 + 8001624: e0bff145 stb r2,-59(fp) + flash_content[2] = 0x0; + 8001628: e03ff185 stb zero,-58(fp) + flash_content[3] = 0x0; + 800162c: e03ff1c5 stb zero,-57(fp) + + /* This is the Altera Vendor ID */ + flash_content[4] = 0x0; + 8001630: e03ff205 stb zero,-56(fp) + flash_content[5] = 0x7; + 8001634: 008001c4 movi r2,7 + 8001638: e0bff245 stb r2,-55(fp) + flash_content[6] = 0xed; + 800163c: 00bffb44 movi r2,-19 + 8001640: e0bff285 stb r2,-54(fp) + + /* Reserverd Board identifier for erase boards */ + flash_content[7] = 0xFF; + 8001644: 00bfffc4 movi r2,-1 + 8001648: e0bff2c5 stb r2,-53(fp) + flash_content[8] = (ser_num & 0xff00) >> 8; + 800164c: e0bffe17 ldw r2,-8(fp) + 8001650: 1004d23a srli r2,r2,8 + 8001654: e0bff305 stb r2,-52(fp) + flash_content[9] = ser_num & 0xff; + 8001658: e0bffe17 ldw r2,-8(fp) + 800165c: e0bff345 stb r2,-51(fp) + + /* Then comes a 16-bit "flags" field */ + flash_content[10] = 0xFF; + 8001660: 00bfffc4 movi r2,-1 + 8001664: e0bff385 stb r2,-50(fp) + flash_content[11] = 0xFF; + 8001668: 00bfffc4 movi r2,-1 + 800166c: e0bff3c5 stb r2,-49(fp) + + /* Then comes the static IP address */ + flash_content[12] = IPADDR0; + 8001670: 00800284 movi r2,10 + 8001674: e0bff405 stb r2,-48(fp) + flash_content[13] = IPADDR1; + 8001678: e03ff445 stb zero,-47(fp) + flash_content[14] = IPADDR2; + 800167c: 008001c4 movi r2,7 + 8001680: e0bff485 stb r2,-46(fp) + flash_content[15] = IPADDR3; + 8001684: 00800404 movi r2,16 + 8001688: e0bff4c5 stb r2,-45(fp) + + /* Then comes the static nameserver address */ + flash_content[16] = 0xFF; + 800168c: 00bfffc4 movi r2,-1 + 8001690: e0bff505 stb r2,-44(fp) + flash_content[17] = 0xFF; + 8001694: 00bfffc4 movi r2,-1 + 8001698: e0bff545 stb r2,-43(fp) + flash_content[18] = 0xFF; + 800169c: 00bfffc4 movi r2,-1 + 80016a0: e0bff585 stb r2,-42(fp) + flash_content[19] = 0xFF; + 80016a4: 00bfffc4 movi r2,-1 + 80016a8: e0bff5c5 stb r2,-41(fp) + + /* Then comes the static subnet mask */ + flash_content[20] = MSKADDR0; + 80016ac: 00bfffc4 movi r2,-1 + 80016b0: e0bff605 stb r2,-40(fp) + flash_content[21] = MSKADDR1; + 80016b4: 00bfffc4 movi r2,-1 + 80016b8: e0bff645 stb r2,-39(fp) + flash_content[22] = MSKADDR2; + 80016bc: 00bfffc4 movi r2,-1 + 80016c0: e0bff685 stb r2,-38(fp) + flash_content[23] = MSKADDR3; + 80016c4: e03ff6c5 stb zero,-37(fp) + + /* Then comes the static gateway address */ + flash_content[24] = GWADDR0; + 80016c8: 00800284 movi r2,10 + 80016cc: e0bff705 stb r2,-36(fp) + flash_content[25] = GWADDR1; + 80016d0: e03ff745 stb zero,-35(fp) + flash_content[26] = GWADDR2; + 80016d4: 008001c4 movi r2,7 + 80016d8: e0bff785 stb r2,-34(fp) + flash_content[27] = GWADDR3; + 80016dc: 00800044 movi r2,1 + 80016e0: e0bff7c5 stb r2,-33(fp) + + /* And finally whether to use DHCP - set all bits to be safe */ + flash_content[28] = 0xFF; + 80016e4: 00bfffc4 movi r2,-1 + 80016e8: e0bff805 stb r2,-32(fp) + flash_content[29] = 0xFF; + 80016ec: 00bfffc4 movi r2,-1 + 80016f0: e0bff845 stb r2,-31(fp) + flash_content[30] = 0xFF; + 80016f4: 00bfffc4 movi r2,-1 + 80016f8: e0bff885 stb r2,-30(fp) + flash_content[31] = 0xFF; + 80016fc: 00bfffc4 movi r2,-1 + 8001700: e0bff8c5 stb r2,-29(fp) + + /* Write the MAC address to flash */ + flash_handle = alt_flash_open_dev(EXT_FLASH_AVL_MEM_NAME); + 8001704: 01020134 movhi r4,2052 + 8001708: 211bdd04 addi r4,r4,28532 + 800170c: 800f7e40 call 800f7e4 + 8001710: e0bffd15 stw r2,-12(fp) + if (flash_handle) + 8001714: e0bffd17 ldw r2,-12(fp) + 8001718: 10001326 beq r2,zero,8001768 + { + alt_write_flash(flash_handle, + 800171c: d0a03a17 ldw r2,-32536(gp) + 8001720: 1007883a mov r3,r2 + 8001724: e0bffd17 ldw r2,-12(fp) + 8001728: e0bffc15 stw r2,-16(fp) + 800172c: e0fffb15 stw r3,-20(fp) + 8001730: e0bff104 addi r2,fp,-60 + 8001734: e0bffa15 stw r2,-24(fp) + 8001738: 00800804 movi r2,32 + 800173c: e0bff915 stw r2,-28(fp) + alt_flash_fd* fd, + int offset, + const void* src_addr, + int length ) +{ + return fd->write( fd, offset, src_addr, length ); + 8001740: e0bffc17 ldw r2,-16(fp) + 8001744: 10800517 ldw r2,20(r2) + 8001748: e1fff917 ldw r7,-28(fp) + 800174c: e1bffa17 ldw r6,-24(fp) + 8001750: e17ffb17 ldw r5,-20(fp) + 8001754: e13ffc17 ldw r4,-16(fp) + 8001758: 103ee83a callr r2 + last_flash_sector_offset, + flash_content, + 32); + alt_flash_close_dev(flash_handle); + 800175c: e13ffd17 ldw r4,-12(fp) + 8001760: 800f84c0 call 800f84c + error = 0; + 8001764: e03fff15 stw zero,-4(fp) + } + } + + return error; + 8001768: e0bfff17 ldw r2,-4(fp) +} + 800176c: e037883a mov sp,fp + 8001770: dfc00117 ldw ra,4(sp) + 8001774: df000017 ldw fp,0(sp) + 8001778: dec00204 addi sp,sp,8 + 800177c: f800283a ret + +08001780 : + * Development Board serial number is 040800017, the corresponding ethernet + * number generated will be 00:07:ED:FF:8F:11. + * + */ +error_t generate_mac_addr(unsigned char mac_addr[6]) +{ + 8001780: defff804 addi sp,sp,-32 + 8001784: dfc00715 stw ra,28(sp) + 8001788: df000615 stw fp,24(sp) + 800178c: df000604 addi fp,sp,24 + 8001790: e13ffd15 stw r4,-12(fp) + error_t error = -1; + 8001794: 00bfffc4 movi r2,-1 + 8001798: e0bfff15 stw r2,-4(fp) + alt_u32 ser_num = 0; + 800179c: e03ffe15 stw zero,-8(fp) + + printf("\nCan't read the MAC address from your board. We will assign you\n"); + 80017a0: 01020134 movhi r4,2052 + 80017a4: 211be304 addi r4,r4,28556 + 80017a8: 8002d9c0 call 8002d9c + printf("a MAC address.\n\n"); + 80017ac: 01020134 movhi r4,2052 + 80017b0: 211bf304 addi r4,r4,28620 + 80017b4: 8002d9c0 call 8002d9c + + ser_num = get_serial_number(); + 80017b8: 80014340 call 8001434 + 80017bc: e0bffe15 stw r2,-8(fp) + + if (ser_num) + 80017c0: e0bffe17 ldw r2,-8(fp) + 80017c4: 10003526 beq r2,zero,800189c + { + /* This is the Altera Vendor ID */ + mac_addr[0] = 0x0; + 80017c8: e0bffd17 ldw r2,-12(fp) + 80017cc: 10000005 stb zero,0(r2) + mac_addr[1] = 0x7; + 80017d0: e0bffd17 ldw r2,-12(fp) + 80017d4: 10800044 addi r2,r2,1 + 80017d8: 00c001c4 movi r3,7 + 80017dc: 10c00005 stb r3,0(r2) + mac_addr[2] = 0xed; + 80017e0: e0bffd17 ldw r2,-12(fp) + 80017e4: 10800084 addi r2,r2,2 + 80017e8: 00fffb44 movi r3,-19 + 80017ec: 10c00005 stb r3,0(r2) + + /* Reserverd Board identifier */ + mac_addr[3] = 0xFF; + 80017f0: e0bffd17 ldw r2,-12(fp) + 80017f4: 108000c4 addi r2,r2,3 + 80017f8: 00ffffc4 movi r3,-1 + 80017fc: 10c00005 stb r3,0(r2) + mac_addr[4] = (ser_num & 0xff00) >> 8; + 8001800: e0bffe17 ldw r2,-8(fp) + 8001804: 1006d23a srli r3,r2,8 + 8001808: e0bffd17 ldw r2,-12(fp) + 800180c: 10800104 addi r2,r2,4 + 8001810: 10c00005 stb r3,0(r2) + mac_addr[5] = ser_num & 0xff; + 8001814: e0bffd17 ldw r2,-12(fp) + 8001818: 10800144 addi r2,r2,5 + 800181c: e0fffe17 ldw r3,-8(fp) + 8001820: 10c00005 stb r3,0(r2) + + printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", + mac_addr[0], + 8001824: e0bffd17 ldw r2,-12(fp) + 8001828: 10800003 ldbu r2,0(r2) + printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", + 800182c: 11403fcc andi r5,r2,255 + mac_addr[1], + 8001830: e0bffd17 ldw r2,-12(fp) + 8001834: 10800044 addi r2,r2,1 + 8001838: 10800003 ldbu r2,0(r2) + printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", + 800183c: 11803fcc andi r6,r2,255 + mac_addr[2], + 8001840: e0bffd17 ldw r2,-12(fp) + 8001844: 10800084 addi r2,r2,2 + 8001848: 10800003 ldbu r2,0(r2) + printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", + 800184c: 11c03fcc andi r7,r2,255 + mac_addr[3], + 8001850: e0bffd17 ldw r2,-12(fp) + 8001854: 108000c4 addi r2,r2,3 + 8001858: 10800003 ldbu r2,0(r2) + printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", + 800185c: 10803fcc andi r2,r2,255 + mac_addr[4], + 8001860: e0fffd17 ldw r3,-12(fp) + 8001864: 18c00104 addi r3,r3,4 + 8001868: 18c00003 ldbu r3,0(r3) + printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", + 800186c: 18c03fcc andi r3,r3,255 + mac_addr[5]); + 8001870: e13ffd17 ldw r4,-12(fp) + 8001874: 21000144 addi r4,r4,5 + 8001878: 21000003 ldbu r4,0(r4) + printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", + 800187c: 21003fcc andi r4,r4,255 + 8001880: d9000215 stw r4,8(sp) + 8001884: d8c00115 stw r3,4(sp) + 8001888: d8800015 stw r2,0(sp) + 800188c: 01020134 movhi r4,2052 + 8001890: 211bf704 addi r4,r4,28636 + 8001894: 8002c780 call 8002c78 + + error = 0; + 8001898: e03fff15 stw zero,-4(fp) + } + + return error; + 800189c: e0bfff17 ldw r2,-4(fp) +} + 80018a0: e037883a mov sp,fp + 80018a4: dfc00117 ldw ra,4(sp) + 80018a8: df000017 ldw fp,0(sp) + 80018ac: dec00204 addi sp,sp,8 + 80018b0: f800283a ret + +080018b4 : +* +* Read the MAC address in a board specific way +* +*/ +error_t get_board_mac_addr(unsigned char mac_addr[6]) +{ + 80018b4: defff804 addi sp,sp,-32 + 80018b8: dfc00715 stw ra,28(sp) + 80018bc: df000615 stw fp,24(sp) + 80018c0: df000604 addi fp,sp,24 + 80018c4: e13ffd15 stw r4,-12(fp) + error_t error = 0; + 80018c8: e03fff15 stw zero,-4(fp) + alt_u32 signature; + + /* Get the flash sector with the MAC address. */ + error = FindLastFlashSectorOffset(&last_flash_sector_offset); + 80018cc: d1203a04 addi r4,gp,-32536 + 80018d0: 8001a540 call 8001a54 + 80018d4: e0bfff15 stw r2,-4(fp) + if (!error) + 80018d8: e0bfff17 ldw r2,-4(fp) + 80018dc: 1000041e bne r2,zero,80018f0 + last_flash_sector = EXT_FLASH_AVL_MEM_BASE + last_flash_sector_offset; + 80018e0: d0e03a17 ldw r3,-32536(gp) + 80018e4: 00850034 movhi r2,5120 + 80018e8: 1885883a add r2,r3,r2 + 80018ec: d0a03b15 stw r2,-32532(gp) + * valid network settings are present, indicated by a signature of 0x00005afe at + * the first address of the last flash sector. This hex value is chosen as the + * signature since it looks like the english word "SAFE", meaning that it is + * safe to use these network address values. + */ + if (!error) + 80018f0: e0bfff17 ldw r2,-4(fp) + 80018f4: 1000081e bne r2,zero,8001918 + { + signature = IORD_32DIRECT(last_flash_sector, 0); + 80018f8: d0a03b17 ldw r2,-32532(gp) + 80018fc: 10800037 ldwio r2,0(r2) + 8001900: e0bffe15 stw r2,-8(fp) + if (signature != 0x00005afe) + 8001904: e0bffe17 ldw r2,-8(fp) + 8001908: 1096bfa0 cmpeqi r2,r2,23294 + 800190c: 1000021e bne r2,zero,8001918 + { + error = generate_and_store_mac_addr(); + 8001910: 80015c80 call 80015c8 + 8001914: e0bfff15 stw r2,-4(fp) + } + } + + if (!error) + 8001918: e0bfff17 ldw r2,-4(fp) + 800191c: 1000471e bne r2,zero,8001a3c + { + mac_addr[0] = IORD_8DIRECT(last_flash_sector, 4); + 8001920: d0a03b17 ldw r2,-32532(gp) + 8001924: 10800104 addi r2,r2,4 + 8001928: 10800023 ldbuio r2,0(r2) + 800192c: 10803fcc andi r2,r2,255 + 8001930: 1007883a mov r3,r2 + 8001934: e0bffd17 ldw r2,-12(fp) + 8001938: 10c00005 stb r3,0(r2) + mac_addr[1] = IORD_8DIRECT(last_flash_sector, 5); + 800193c: d0a03b17 ldw r2,-32532(gp) + 8001940: 10800144 addi r2,r2,5 + 8001944: 10800023 ldbuio r2,0(r2) + 8001948: 10c03fcc andi r3,r2,255 + 800194c: e0bffd17 ldw r2,-12(fp) + 8001950: 10800044 addi r2,r2,1 + 8001954: 10c00005 stb r3,0(r2) + mac_addr[2] = IORD_8DIRECT(last_flash_sector, 6); + 8001958: d0a03b17 ldw r2,-32532(gp) + 800195c: 10800184 addi r2,r2,6 + 8001960: 10800023 ldbuio r2,0(r2) + 8001964: 10c03fcc andi r3,r2,255 + 8001968: e0bffd17 ldw r2,-12(fp) + 800196c: 10800084 addi r2,r2,2 + 8001970: 10c00005 stb r3,0(r2) + mac_addr[3] = IORD_8DIRECT(last_flash_sector, 7); + 8001974: d0a03b17 ldw r2,-32532(gp) + 8001978: 108001c4 addi r2,r2,7 + 800197c: 10800023 ldbuio r2,0(r2) + 8001980: 10c03fcc andi r3,r2,255 + 8001984: e0bffd17 ldw r2,-12(fp) + 8001988: 108000c4 addi r2,r2,3 + 800198c: 10c00005 stb r3,0(r2) + mac_addr[4] = IORD_8DIRECT(last_flash_sector, 8); + 8001990: d0a03b17 ldw r2,-32532(gp) + 8001994: 10800204 addi r2,r2,8 + 8001998: 10800023 ldbuio r2,0(r2) + 800199c: 10c03fcc andi r3,r2,255 + 80019a0: e0bffd17 ldw r2,-12(fp) + 80019a4: 10800104 addi r2,r2,4 + 80019a8: 10c00005 stb r3,0(r2) + mac_addr[5] = IORD_8DIRECT(last_flash_sector, 9); + 80019ac: d0a03b17 ldw r2,-32532(gp) + 80019b0: 10800244 addi r2,r2,9 + 80019b4: 10800023 ldbuio r2,0(r2) + 80019b8: 10c03fcc andi r3,r2,255 + 80019bc: e0bffd17 ldw r2,-12(fp) + 80019c0: 10800144 addi r2,r2,5 + 80019c4: 10c00005 stb r3,0(r2) + + printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", + mac_addr[0], + 80019c8: e0bffd17 ldw r2,-12(fp) + 80019cc: 10800003 ldbu r2,0(r2) + printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", + 80019d0: 11403fcc andi r5,r2,255 + mac_addr[1], + 80019d4: e0bffd17 ldw r2,-12(fp) + 80019d8: 10800044 addi r2,r2,1 + 80019dc: 10800003 ldbu r2,0(r2) + printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", + 80019e0: 11803fcc andi r6,r2,255 + mac_addr[2], + 80019e4: e0bffd17 ldw r2,-12(fp) + 80019e8: 10800084 addi r2,r2,2 + 80019ec: 10800003 ldbu r2,0(r2) + printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", + 80019f0: 11c03fcc andi r7,r2,255 + mac_addr[3], + 80019f4: e0bffd17 ldw r2,-12(fp) + 80019f8: 108000c4 addi r2,r2,3 + 80019fc: 10800003 ldbu r2,0(r2) + printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", + 8001a00: 10803fcc andi r2,r2,255 + mac_addr[4], + 8001a04: e0fffd17 ldw r3,-12(fp) + 8001a08: 18c00104 addi r3,r3,4 + 8001a0c: 18c00003 ldbu r3,0(r3) + printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", + 8001a10: 18c03fcc andi r3,r3,255 + mac_addr[5]); + 8001a14: e13ffd17 ldw r4,-12(fp) + 8001a18: 21000144 addi r4,r4,5 + 8001a1c: 21000003 ldbu r4,0(r4) + printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", + 8001a20: 21003fcc andi r4,r4,255 + 8001a24: d9000215 stw r4,8(sp) + 8001a28: d8c00115 stw r3,4(sp) + 8001a2c: d8800015 stw r2,0(sp) + 8001a30: 01020134 movhi r4,2052 + 8001a34: 211bf704 addi r4,r4,28636 + 8001a38: 8002c780 call 8002c78 + + } + + return error; + 8001a3c: e0bfff17 ldw r2,-4(fp) +} + 8001a40: e037883a mov sp,fp + 8001a44: dfc00117 ldw ra,4(sp) + 8001a48: df000017 ldw fp,0(sp) + 8001a4c: dec00204 addi sp,sp,8 + 8001a50: f800283a ret + +08001a54 : + * in pLastFlashSectorOffset. + */ + +int FindLastFlashSectorOffset( + alt_u32 *pLastFlashSectorOffset) +{ + 8001a54: defff304 addi sp,sp,-52 + 8001a58: dfc00c15 stw ra,48(sp) + 8001a5c: df000b15 stw fp,44(sp) + 8001a60: df000b04 addi fp,sp,44 + 8001a64: e13ff515 stw r4,-44(fp) + flash_region *regions; + int numRegions; + flash_region *pLastRegion; + int lastFlashSectorOffset; + int n; + int error = 0; + 8001a68: e03ffc15 stw zero,-16(fp) + + /* Open the flash device. */ + fd = alt_flash_open_dev(EXT_FLASH_AVL_MEM_NAME); + 8001a6c: 01020134 movhi r4,2052 + 8001a70: 211bdd04 addi r4,r4,28532 + 8001a74: 800f7e40 call 800f7e4 + 8001a78: e0bffb15 stw r2,-20(fp) + if (fd <= 0) + 8001a7c: e0bffb17 ldw r2,-20(fp) + 8001a80: 1000021e bne r2,zero,8001a8c + error = -1; + 8001a84: 00bfffc4 movi r2,-1 + 8001a88: e0bffc15 stw r2,-16(fp) + + /* Get the flash info. */ + if (!error) + 8001a8c: e0bffc17 ldw r2,-16(fp) + 8001a90: 10000d1e bne r2,zero,8001ac8 + 8001a94: e0bffb17 ldw r2,-20(fp) + 8001a98: e0bffa15 stw r2,-24(fp) + 8001a9c: e0bff704 addi r2,fp,-36 + 8001aa0: e0bff915 stw r2,-28(fp) + 8001aa4: e0bff604 addi r2,fp,-40 + 8001aa8: e0bff815 stw r2,-32(fp) + */ +static __inline__ int __attribute__ ((always_inline)) alt_get_flash_info( + alt_flash_fd* fd, flash_region** info, + int* number_of_regions) +{ + return fd->get_info( fd, info, number_of_regions); + 8001aac: e0bffa17 ldw r2,-24(fp) + 8001ab0: 10800717 ldw r2,28(r2) + 8001ab4: e1bff817 ldw r6,-32(fp) + 8001ab8: e17ff917 ldw r5,-28(fp) + 8001abc: e13ffa17 ldw r4,-24(fp) + 8001ac0: 103ee83a callr r2 + error = alt_get_flash_info(fd, ®ions, &numRegions); + 8001ac4: e0bffc15 stw r2,-16(fp) + + /* Find the last flash sector. */ + if (!error) + 8001ac8: e0bffc17 ldw r2,-16(fp) + 8001acc: 1000211e bne r2,zero,8001b54 + { + pLastRegion = &(regions[0]); + 8001ad0: e0bff717 ldw r2,-36(fp) + 8001ad4: e0bfff15 stw r2,-4(fp) + for (n = 1; n < numRegions; n++) + 8001ad8: 00800044 movi r2,1 + 8001adc: e0bffd15 stw r2,-12(fp) + 8001ae0: 00001006 br 8001b24 + { + if (regions[n].offset > pLastRegion->offset) + 8001ae4: e0fff717 ldw r3,-36(fp) + 8001ae8: e0bffd17 ldw r2,-12(fp) + 8001aec: 1004913a slli r2,r2,4 + 8001af0: 1885883a add r2,r3,r2 + 8001af4: 10800017 ldw r2,0(r2) + 8001af8: e0ffff17 ldw r3,-4(fp) + 8001afc: 18c00017 ldw r3,0(r3) + 8001b00: 1880050e bge r3,r2,8001b18 + pLastRegion = &(regions[n]); + 8001b04: e0fff717 ldw r3,-36(fp) + 8001b08: e0bffd17 ldw r2,-12(fp) + 8001b0c: 1004913a slli r2,r2,4 + 8001b10: 1885883a add r2,r3,r2 + 8001b14: e0bfff15 stw r2,-4(fp) + for (n = 1; n < numRegions; n++) + 8001b18: e0bffd17 ldw r2,-12(fp) + 8001b1c: 10800044 addi r2,r2,1 + 8001b20: e0bffd15 stw r2,-12(fp) + 8001b24: e0bff617 ldw r2,-40(fp) + 8001b28: e0fffd17 ldw r3,-12(fp) + 8001b2c: 18bfed16 blt r3,r2,8001ae4 + } + lastFlashSectorOffset = pLastRegion->offset + 8001b30: e0bfff17 ldw r2,-4(fp) + 8001b34: 10c00017 ldw r3,0(r2) + + pLastRegion->region_size + 8001b38: e0bfff17 ldw r2,-4(fp) + 8001b3c: 10800117 ldw r2,4(r2) + 8001b40: 1887883a add r3,r3,r2 + - pLastRegion->block_size; + 8001b44: e0bfff17 ldw r2,-4(fp) + 8001b48: 10800317 ldw r2,12(r2) + lastFlashSectorOffset = pLastRegion->offset + 8001b4c: 1885c83a sub r2,r3,r2 + 8001b50: e0bffe15 stw r2,-8(fp) + } + + /* Return results. */ + if (!error) + 8001b54: e0bffc17 ldw r2,-16(fp) + 8001b58: 1000031e bne r2,zero,8001b68 + *pLastFlashSectorOffset = lastFlashSectorOffset; + 8001b5c: e0fffe17 ldw r3,-8(fp) + 8001b60: e0bff517 ldw r2,-44(fp) + 8001b64: 10c00015 stw r3,0(r2) + + return (error); + 8001b68: e0bffc17 ldw r2,-16(fp) +} + 8001b6c: e037883a mov sp,fp + 8001b70: dfc00117 ldw ra,4(sp) + 8001b74: df000017 ldw fp,0(sp) + 8001b78: dec00204 addi sp,sp,8 + 8001b7c: f800283a ret + +08001b80 : +#include "dev_commands.h" +#include "sensor.h" + + +void sensor_command_bit(alt_u32 base, alt_u8 bitmask, alt_u8 state) +{ + 8001b80: defffb04 addi sp,sp,-20 + 8001b84: df000415 stw fp,16(sp) + 8001b88: df000404 addi fp,sp,16 + 8001b8c: e13ffe15 stw r4,-8(fp) + 8001b90: 2805883a mov r2,r5 + 8001b94: 3007883a mov r3,r6 + 8001b98: e0bffd05 stb r2,-12(fp) + 8001b9c: 1805883a mov r2,r3 + 8001ba0: e0bffc05 stb r2,-16(fp) + alt_u8 tmp = IORD_8DIRECT(base, SENSOR_REG_COMMAND); + 8001ba4: e0bffe17 ldw r2,-8(fp) + 8001ba8: 10800023 ldbuio r2,0(r2) + 8001bac: 10803fcc andi r2,r2,255 + 8001bb0: e0bfffc5 stb r2,-1(fp) + if (state) + 8001bb4: e0bffc03 ldbu r2,-16(fp) + 8001bb8: 10000526 beq r2,zero,8001bd0 + tmp |= bitmask; + 8001bbc: e0ffffc3 ldbu r3,-1(fp) + 8001bc0: e0bffd03 ldbu r2,-12(fp) + 8001bc4: 1884b03a or r2,r3,r2 + 8001bc8: e0bfffc5 stb r2,-1(fp) + 8001bcc: 00000606 br 8001be8 + else + tmp &= ~bitmask; + 8001bd0: e0bffd03 ldbu r2,-12(fp) + 8001bd4: 0084303a nor r2,zero,r2 + 8001bd8: 1007883a mov r3,r2 + 8001bdc: e0bfffc3 ldbu r2,-1(fp) + 8001be0: 1884703a and r2,r3,r2 + 8001be4: e0bfffc5 stb r2,-1(fp) + IOWR_8DIRECT(base, SENSOR_REG_COMMAND, tmp); + 8001be8: e0bffe17 ldw r2,-8(fp) + 8001bec: e0ffffc3 ldbu r3,-1(fp) + 8001bf0: 10c00025 stbio r3,0(r2) +} + 8001bf4: 0001883a nop + 8001bf8: e037883a mov sp,fp + 8001bfc: df000017 ldw fp,0(sp) + 8001c00: dec00104 addi sp,sp,4 + 8001c04: f800283a ret + +08001c08 : + + +void sensor_preconfigure(alt_u32 base) +{ + 8001c08: defffd04 addi sp,sp,-12 + 8001c0c: dfc00215 stw ra,8(sp) + 8001c10: df000115 stw fp,4(sp) + 8001c14: df000104 addi fp,sp,4 + 8001c18: e13fff15 stw r4,-4(fp) + printf(" *** Preconfiguring sensor module... \n"); + 8001c1c: 01020134 movhi r4,2052 + 8001c20: 211c0604 addi r4,r4,28696 + 8001c24: 8002d9c0 call 8002d9c + + sensor_command(base, 0); //disable + 8001c28: e0bfff17 ldw r2,-4(fp) + 8001c2c: 0007883a mov r3,zero + 8001c30: 10c00025 stbio r3,0(r2) + sensor_set_sensorclk(base, 6); //sensor clock - 3.57 MHz + 8001c34: e0bfff17 ldw r2,-4(fp) + 8001c38: 10800084 addi r2,r2,2 + 8001c3c: 1007883a mov r3,r2 + 8001c40: 00800184 movi r2,6 + 8001c44: 18800025 stbio r2,0(r3) + sensor_set_adccnv(base, 31); //conversion delay - default + 8001c48: e0bfff17 ldw r2,-4(fp) + 8001c4c: 108000c4 addi r2,r2,3 + 8001c50: 1007883a mov r3,r2 + 8001c54: 008007c4 movi r2,31 + 8001c58: 18800025 stbio r2,0(r3) + sensor_set_delay(base, 1); //trigger delay - default + 8001c5c: e0bfff17 ldw r2,-4(fp) + 8001c60: 10800104 addi r2,r2,4 + 8001c64: 1007883a mov r3,r2 + 8001c68: 00800044 movi r2,1 + 8001c6c: 1880002d sthio r2,0(r3) + sensor_set_shutter(base, 100); //integration time - dummy default + 8001c70: e0bfff17 ldw r2,-4(fp) + 8001c74: 10800184 addi r2,r2,6 + 8001c78: 1007883a mov r3,r2 + 8001c7c: 00801904 movi r2,100 + 8001c80: 1880002d sthio r2,0(r3) + sensor_set_serspeed(base, 50); //synchro serial port - 1 Mbps + 8001c84: e0bfff17 ldw r2,-4(fp) + 8001c88: 10800204 addi r2,r2,8 + 8001c8c: 1007883a mov r3,r2 + 8001c90: 00800c84 movi r2,50 + 8001c94: 18800025 stbio r2,0(r3) + sensor_set_header_anydata(base, 0x00); //should be 0 + 8001c98: e0bfff17 ldw r2,-4(fp) + 8001c9c: 10800244 addi r2,r2,9 + 8001ca0: 0007883a mov r3,zero + 8001ca4: 10c00025 stbio r3,0(r2) + sensor_set_header_cmd(base, COMMAND_DATA_TRANSFER); //command header, must be this one + 8001ca8: e0bfff17 ldw r2,-4(fp) + 8001cac: 10800284 addi r2,r2,10 + 8001cb0: 1007883a mov r3,r2 + 8001cb4: 00a00004 movi r2,-32768 + 8001cb8: 1880002d sthio r2,0(r3) + sensor_command(base, 1); //enable, gain low, SCLK full + 8001cbc: e0bfff17 ldw r2,-4(fp) + 8001cc0: 00c00044 movi r3,1 + 8001cc4: 10c00025 stbio r3,0(r2) + + sensor_set_cluster_threshold(base, 10); //default cluster threshold 10 + 8001cc8: e0bfff17 ldw r2,-4(fp) + 8001ccc: 10800304 addi r2,r2,12 + 8001cd0: 1007883a mov r3,r2 + 8001cd4: 00800284 movi r2,10 + 8001cd8: 18800025 stbio r2,0(r3) + sensor_set_cluster_size(base, 4); //default cluster size 4 + 8001cdc: e0bfff17 ldw r2,-4(fp) + 8001ce0: 10800344 addi r2,r2,13 + 8001ce4: 1007883a mov r3,r2 + 8001ce8: 00800104 movi r2,4 + 8001cec: 18800025 stbio r2,0(r3) + sensor_set_in_algo_threshold(base, 4); //default algo threshold 4 + 8001cf0: e0bfff17 ldw r2,-4(fp) + 8001cf4: 10800384 addi r2,r2,14 + 8001cf8: 1007883a mov r3,r2 + 8001cfc: 00800104 movi r2,4 + 8001d00: 18800025 stbio r2,0(r3) + +} + 8001d04: 0001883a nop + 8001d08: e037883a mov sp,fp + 8001d0c: dfc00117 ldw ra,4(sp) + 8001d10: df000017 ldw fp,0(sp) + 8001d14: dec00204 addi sp,sp,8 + 8001d18: f800283a ret + +08001d1c : +// ******************************************************** + + + +void ss_reset_connection(SSConn* conn) //called e.g. after closing a socket +{ + 8001d1c: defffe04 addi sp,sp,-8 + 8001d20: df000115 stw fp,4(sp) + 8001d24: df000104 addi fp,sp,4 + 8001d28: e13fff15 stw r4,-4(fp) + conn->fd_conn = -1; + 8001d2c: e0bfff17 ldw r2,-4(fp) + 8001d30: 00ffffc4 movi r3,-1 + 8001d34: 10c00215 stw r3,8(r2) + conn->state = LISTENING; + 8001d38: e0bfff17 ldw r2,-4(fp) + 8001d3c: 00c00044 movi r3,1 + 8001d40: 10c00015 stw r3,0(r2) + return; + 8001d44: 0001883a nop +} + 8001d48: e037883a mov sp,fp + 8001d4c: df000017 ldw fp,0(sp) + 8001d50: dec00104 addi sp,sp,4 + 8001d54: f800283a ret + +08001d58 : + +void ss_initialize_connection(SSConn* conn) //called only at initialization +{ + 8001d58: defffe04 addi sp,sp,-8 + 8001d5c: df000115 stw fp,4(sp) + 8001d60: df000104 addi fp,sp,4 + 8001d64: e13fff15 stw r4,-4(fp) + conn->fd_conn = -1; + 8001d68: e0bfff17 ldw r2,-4(fp) + 8001d6c: 00ffffc4 movi r3,-1 + 8001d70: 10c00215 stw r3,8(r2) + conn->fd_listen = -1; + 8001d74: e0bfff17 ldw r2,-4(fp) + 8001d78: 00ffffc4 movi r3,-1 + 8001d7c: 10c00115 stw r3,4(r2) + conn->listenport = -1; + 8001d80: e0bfff17 ldw r2,-4(fp) + 8001d84: 00ffffc4 movi r3,-1 + 8001d88: 10c00315 stw r3,12(r2) + conn->state = FREE; + 8001d8c: e0bfff17 ldw r2,-4(fp) + 8001d90: 10000015 stw zero,0(r2) + return; + 8001d94: 0001883a nop +} + 8001d98: e037883a mov sp,fp + 8001d9c: df000017 ldw fp,0(sp) + 8001da0: dec00104 addi sp,sp,4 + 8001da4: f800283a ret + +08001da8 : + +void ss_handle_accept(SSConn* conn) +{ + 8001da8: defff604 addi sp,sp,-40 + 8001dac: dfc00915 stw ra,36(sp) + 8001db0: df000815 stw fp,32(sp) + 8001db4: df000804 addi fp,sp,32 + 8001db8: e13ff815 stw r4,-32(fp) + int socket; + int len; + struct sockaddr_in incoming_addr; + + INT8U err; + OSMutexPend(mutex, 0, &err); + 8001dbc: d0a03c17 ldw r2,-32528(gp) + 8001dc0: e0fff9c4 addi r3,fp,-25 + 8001dc4: 180d883a mov r6,r3 + 8001dc8: 000b883a mov r5,zero + 8001dcc: 1009883a mov r4,r2 + 8001dd0: 8013cdc0 call 8013cdc + + len = sizeof(incoming_addr); + 8001dd4: 00800404 movi r2,16 + 8001dd8: e0bffe15 stw r2,-8(fp) + + //Close old connection if needed + if ((conn)->fd_conn != -1) + 8001ddc: e0bff817 ldw r2,-32(fp) + 8001de0: 10800217 ldw r2,8(r2) + 8001de4: 10bfffe0 cmpeqi r2,r2,-1 + 8001de8: 1000091e bne r2,zero,8001e10 + { + printf("[ss_handle_accept] closing old connection\n"); + 8001dec: 01020134 movhi r4,2052 + 8001df0: 211c1604 addi r4,r4,28760 + 8001df4: 8002d9c0 call 8002d9c + close(conn->fd_conn); + 8001df8: e0bff817 ldw r2,-32(fp) + 8001dfc: 10800217 ldw r2,8(r2) + 8001e00: 1009883a mov r4,r2 + 8001e04: 8022a600 call 8022a60 + ss_reset_connection(conn); + 8001e08: e13ff817 ldw r4,-32(fp) + 8001e0c: 8001d1c0 call 8001d1c + } + + if((socket=accept(conn->fd_listen,(struct sockaddr*)&incoming_addr,&len))<0) + 8001e10: e0bff817 ldw r2,-32(fp) + 8001e14: 10800117 ldw r2,4(r2) + 8001e18: e13ffe04 addi r4,fp,-8 + 8001e1c: e0fffa04 addi r3,fp,-24 + 8001e20: 200d883a mov r6,r4 + 8001e24: 180b883a mov r5,r3 + 8001e28: 1009883a mov r4,r2 + 8001e2c: 80262140 call 8026214 + 8001e30: e0bfff15 stw r2,-4(fp) + 8001e34: e0bfff17 ldw r2,-4(fp) + 8001e38: 10000c16 blt r2,zero,8001e6c + //alt_NetworkErrorHandler(EXPANDED_DIAGNOSIS_CODE, + // "[ss_handle_accept] accept failed"); + } + else + { + (conn)->fd_conn = socket; + 8001e3c: e0bff817 ldw r2,-32(fp) + 8001e40: e0ffff17 ldw r3,-4(fp) + 8001e44: 10c00215 stw r3,8(r2) + (conn)->state = CONNECTED; + 8001e48: e0bff817 ldw r2,-32(fp) + 8001e4c: 00c00084 movi r3,2 + 8001e50: 10c00015 stw r3,0(r2) + printf("[ss_handle_accept] accepted connection request from %s\n", + 8001e54: e13ffb17 ldw r4,-20(fp) + 8001e58: 80268fc0 call 80268fc + 8001e5c: 100b883a mov r5,r2 + 8001e60: 01020134 movhi r4,2052 + 8001e64: 211c2104 addi r4,r4,28804 + 8001e68: 8002c780 call 8002c78 + inet_ntoa(incoming_addr.sin_addr)); + } + + OSMutexPost(mutex); + 8001e6c: d0a03c17 ldw r2,-32528(gp) + 8001e70: 1009883a mov r4,r2 + 8001e74: 80142380 call 8014238 + return; + 8001e78: 0001883a nop +} + 8001e7c: e037883a mov sp,fp + 8001e80: dfc00117 ldw ra,4(sp) + 8001e84: df000017 ldw fp,0(sp) + 8001e88: dec00204 addi sp,sp,8 + 8001e8c: f800283a ret + +08001e90 : + +/* + * Listener Task() + */ +void SSListenerTask(void* param) +{ + 8001e90: deffb304 addi sp,sp,-308 + 8001e94: dfc04c15 stw ra,304(sp) + 8001e98: df004b15 stw fp,300(sp) + 8001e9c: df004b04 addi fp,sp,300 + 8001ea0: e13fb615 stw r4,-296(fp) + + int max_socket = 0; + 8001ea4: e03fff15 stw zero,-4(fp) + BSD_TIMEVAL_T timeout; + + INT8U err; + OSMutexPend(mutex, 0, &err); //wrap initialization in a mutex - just in case... + 8001ea8: d0a03c17 ldw r2,-32528(gp) + 8001eac: e0fff8c4 addi r3,fp,-29 + 8001eb0: 180d883a mov r6,r3 + 8001eb4: 000b883a mov r5,zero + 8001eb8: 1009883a mov r4,r2 + 8001ebc: 8013cdc0 call 8013cdc + + timeout.tv_sec = 0; + 8001ec0: e03ff915 stw zero,-28(fp) + 8001ec4: e03ffa15 stw zero,-24(fp) + timeout.tv_usec = 100000; + 8001ec8: 008000b4 movhi r2,2 + 8001ecc: 10a1a804 addi r2,r2,-31072 + 8001ed0: e0bffb15 stw r2,-20(fp) + + fd_set readfds; //set of descriptors + + for (int ch = 0; ch < NR_CHANNELS; ch++) + 8001ed4: e03ffe15 stw zero,-8(fp) + 8001ed8: 00000d06 br 8001f10 + if ((connections[ch].fd_listen = socket(AF_INET, SOCK_STREAM, 0)) < 0) + 8001edc: 000d883a mov r6,zero + 8001ee0: 01400044 movi r5,1 + 8001ee4: 01000084 movi r4,2 + 8001ee8: 802ba700 call 802ba70 + 8001eec: 1009883a mov r4,r2 + 8001ef0: e0bffe17 ldw r2,-8(fp) + 8001ef4: 1006913a slli r3,r2,4 + 8001ef8: 00820174 movhi r2,2053 + 8001efc: 1885883a add r2,r3,r2 + 8001f00: 11336115 stw r4,-12924(r2) + for (int ch = 0; ch < NR_CHANNELS; ch++) + 8001f04: e0bffe17 ldw r2,-8(fp) + 8001f08: 10800044 addi r2,r2,1 + 8001f0c: e0bffe15 stw r2,-8(fp) + 8001f10: e0bffe17 ldw r2,-8(fp) + 8001f14: 00bff10e bge zero,r2,8001edc + //alt_NetworkErrorHandler(EXPANDED_DIAGNOSIS_CODE,"[sss_task] Socket creation failed"); + } + + //Binding etc. is done by ethernet_listen() + + OSMutexPost(mutex); + 8001f18: d0a03c17 ldw r2,-32528(gp) + 8001f1c: 1009883a mov r4,r2 + 8001f20: 80142380 call 8014238 + + //Now run in loop to handle incoming requests on all listening ports + while(1) + { + FD_ZERO(&readfds); + 8001f24: e03fb715 stw zero,-292(fp) + + for (int ch = 0; ch < NR_CHANNELS; ch++) + 8001f28: e03ffd15 stw zero,-12(fp) + 8001f2c: 00002006 br 8001fb0 + if (connections[ch].listenport >= 0) + 8001f30: e0bffd17 ldw r2,-12(fp) + 8001f34: 1006913a slli r3,r2,4 + 8001f38: 00820174 movhi r2,2053 + 8001f3c: 1885883a add r2,r3,r2 + 8001f40: 10b36317 ldw r2,-12916(r2) + 8001f44: 10001716 blt r2,zero,8001fa4 + { + FD_SET(connections[ch].fd_listen, &readfds); + 8001f48: e0bffd17 ldw r2,-12(fp) + 8001f4c: 1006913a slli r3,r2,4 + 8001f50: 00820174 movhi r2,2053 + 8001f54: 1885883a add r2,r3,r2 + 8001f58: 10b36117 ldw r2,-12924(r2) + 8001f5c: e0ffb704 addi r3,fp,-292 + 8001f60: 180b883a mov r5,r3 + 8001f64: 1009883a mov r4,r2 + 8001f68: 8030b180 call 8030b18 + if (connections[ch].fd_listen >= max_socket) + 8001f6c: e0bffd17 ldw r2,-12(fp) + 8001f70: 1006913a slli r3,r2,4 + 8001f74: 00820174 movhi r2,2053 + 8001f78: 1885883a add r2,r3,r2 + 8001f7c: 10f36117 ldw r3,-12924(r2) + 8001f80: e0bfff17 ldw r2,-4(fp) + 8001f84: 18800716 blt r3,r2,8001fa4 + max_socket = connections[ch].fd_listen+1; + 8001f88: e0bffd17 ldw r2,-12(fp) + 8001f8c: 1006913a slli r3,r2,4 + 8001f90: 00820174 movhi r2,2053 + 8001f94: 1885883a add r2,r3,r2 + 8001f98: 10b36117 ldw r2,-12924(r2) + 8001f9c: 10800044 addi r2,r2,1 + 8001fa0: e0bfff15 stw r2,-4(fp) + for (int ch = 0; ch < NR_CHANNELS; ch++) + 8001fa4: e0bffd17 ldw r2,-12(fp) + 8001fa8: 10800044 addi r2,r2,1 + 8001fac: e0bffd15 stw r2,-12(fp) + 8001fb0: e0bffd17 ldw r2,-12(fp) + 8001fb4: 00bfde0e bge zero,r2,8001f30 + } + + if (max_socket == 0) + 8001fb8: e0bfff17 ldw r2,-4(fp) + 8001fbc: 1000031e bne r2,zero,8001fcc + TK_SLEEP(10); //just sleep a bit if nothing to do + 8001fc0: 010002c4 movi r4,11 + 8001fc4: 801730c0 call 801730c + 8001fc8: 003fd606 br 8001f24 + else + { + select(max_socket, &readfds, NULL, NULL, &timeout); //we must timeout from time to time to find newly set-up channels + 8001fcc: e0ffb704 addi r3,fp,-292 + 8001fd0: e0bff904 addi r2,fp,-28 + 8001fd4: d8800015 stw r2,0(sp) + 8001fd8: 000f883a mov r7,zero + 8001fdc: 000d883a mov r6,zero + 8001fe0: 180b883a mov r5,r3 + 8001fe4: e13fff17 ldw r4,-4(fp) + 8001fe8: 8026a740 call 8026a74 + + for (int ch = 0; ch < NR_CHANNELS; ch++) + 8001fec: e03ffc15 stw zero,-16(fp) + 8001ff0: 00001406 br 8002044 + if (FD_ISSET(connections[ch].fd_listen, &readfds)) + 8001ff4: e0bffc17 ldw r2,-16(fp) + 8001ff8: 1006913a slli r3,r2,4 + 8001ffc: 00820174 movhi r2,2053 + 8002000: 1885883a add r2,r3,r2 + 8002004: 10b36117 ldw r2,-12924(r2) + 8002008: e0ffb704 addi r3,fp,-292 + 800200c: 180b883a mov r5,r3 + 8002010: 1009883a mov r4,r2 + 8002014: 8030b8c0 call 8030b8c + 8002018: 10000726 beq r2,zero,8002038 + ss_handle_accept(&(connections[ch])); + 800201c: e0bffc17 ldw r2,-16(fp) + 8002020: 1006913a slli r3,r2,4 + 8002024: 00820174 movhi r2,2053 + 8002028: 10b36004 addi r2,r2,-12928 + 800202c: 1885883a add r2,r3,r2 + 8002030: 1009883a mov r4,r2 + 8002034: 8001da80 call 8001da8 + for (int ch = 0; ch < NR_CHANNELS; ch++) + 8002038: e0bffc17 ldw r2,-16(fp) + 800203c: 10800044 addi r2,r2,1 + 8002040: e0bffc15 stw r2,-16(fp) + 8002044: e0bffc17 ldw r2,-16(fp) + 8002048: 00bfea0e bge zero,r2,8001ff4 + FD_ZERO(&readfds); + 800204c: 003fb506 br 8001f24 + +08002050 : + + +// ****************** User interface ******************** + +int ethernet_init() +{ + 8002050: defffc04 addi sp,sp,-16 + 8002054: dfc00315 stw ra,12(sp) + 8002058: df000215 stw fp,8(sp) + 800205c: df000204 addi fp,sp,8 + INT8U err; + mutex = OSMutexCreate(SS_LISTENER_TASK_PRIORITY-1, &err); + 8002060: e0bffec4 addi r2,fp,-5 + 8002064: 100b883a mov r5,r2 + 8002068: 01000204 movi r4,8 + 800206c: 801389c0 call 801389c + 8002070: d0a03c15 stw r2,-32528(gp) + + + for (int ch = 0; ch < NR_CHANNELS; ch++) + 8002074: e03fff15 stw zero,-4(fp) + 8002078: 00000a06 br 80020a4 + ss_initialize_connection(&(connections[ch])); + 800207c: e0bfff17 ldw r2,-4(fp) + 8002080: 1006913a slli r3,r2,4 + 8002084: 00820174 movhi r2,2053 + 8002088: 10b36004 addi r2,r2,-12928 + 800208c: 1885883a add r2,r3,r2 + 8002090: 1009883a mov r4,r2 + 8002094: 8001d580 call 8001d58 + for (int ch = 0; ch < NR_CHANNELS; ch++) + 8002098: e0bfff17 ldw r2,-4(fp) + 800209c: 10800044 addi r2,r2,1 + 80020a0: e0bfff15 stw r2,-4(fp) + 80020a4: e0bfff17 ldw r2,-4(fp) + 80020a8: 00bff40e bge zero,r2,800207c + + TK_NEWTASK(&sslistenertask); + 80020ac: 01020174 movhi r4,2053 + 80020b0: 212e4e04 addi r4,r4,-18120 + 80020b4: 80290740 call 8029074 + return 0; + 80020b8: 0005883a mov r2,zero +} + 80020bc: e037883a mov sp,fp + 80020c0: dfc00117 ldw ra,4(sp) + 80020c4: df000017 ldw fp,0(sp) + 80020c8: dec00204 addi sp,sp,8 + 80020cc: f800283a ret + +080020d0 : + +int ethernet_listen(int channel, int port) +{ + 80020d0: defff704 addi sp,sp,-36 + 80020d4: dfc00815 stw ra,32(sp) + 80020d8: df000715 stw fp,28(sp) + 80020dc: df000704 addi fp,sp,28 + 80020e0: e13ffa15 stw r4,-24(fp) + 80020e4: e17ff915 stw r5,-28(fp) + struct sockaddr_in addr; + + INT8U err; + OSMutexPend(mutex, 0, &err); + 80020e8: d0a03c17 ldw r2,-32528(gp) + 80020ec: e0fffbc4 addi r3,fp,-17 + 80020f0: 180d883a mov r6,r3 + 80020f4: 000b883a mov r5,zero + 80020f8: 1009883a mov r4,r2 + 80020fc: 8013cdc0 call 8013cdc + + addr.sin_family = AF_INET; + 8002100: 00800084 movi r2,2 + 8002104: e0bffc0d sth r2,-16(fp) + addr.sin_port = htons(port); + 8002108: e0bff917 ldw r2,-28(fp) + 800210c: 1005d23a srai r2,r2,8 + 8002110: 10803fcc andi r2,r2,255 + 8002114: 1007883a mov r3,r2 + 8002118: e0bff917 ldw r2,-28(fp) + 800211c: 1004923a slli r2,r2,8 + 8002120: 1884b03a or r2,r3,r2 + 8002124: e0bffc8d sth r2,-14(fp) + addr.sin_addr.s_addr = INADDR_ANY; + 8002128: e03ffd15 stw zero,-12(fp) + + if (bind(connections[channel].fd_listen,(struct sockaddr *)&addr,sizeof(addr)) < 0) + 800212c: e0bffa17 ldw r2,-24(fp) + 8002130: 1006913a slli r3,r2,4 + 8002134: 00820174 movhi r2,2053 + 8002138: 1885883a add r2,r3,r2 + 800213c: 10b36117 ldw r2,-12924(r2) + 8002140: e0fffc04 addi r3,fp,-16 + 8002144: 01800404 movi r6,16 + 8002148: 180b883a mov r5,r3 + 800214c: 1009883a mov r4,r2 + 8002150: 802baf00 call 802baf0 + 8002154: 1000050e bge r2,zero,800216c + { + //alt_NetworkErrorHandler(EXPANDED_DIAGNOSIS_CODE,"[sss_task] Bind failed"); + OSMutexPost(mutex); + 8002158: d0a03c17 ldw r2,-32528(gp) + 800215c: 1009883a mov r4,r2 + 8002160: 80142380 call 8014238 + return -1; + 8002164: 00bfffc4 movi r2,-1 + 8002168: 00002306 br 80021f8 + } + + if (listen(connections[channel].fd_listen,1) < 0) + 800216c: e0bffa17 ldw r2,-24(fp) + 8002170: 1006913a slli r3,r2,4 + 8002174: 00820174 movhi r2,2053 + 8002178: 1885883a add r2,r3,r2 + 800217c: 10b36117 ldw r2,-12924(r2) + 8002180: 01400044 movi r5,1 + 8002184: 1009883a mov r4,r2 + 8002188: 802bc500 call 802bc50 + 800218c: 1000050e bge r2,zero,80021a4 + { + //alt_NetworkErrorHandler(EXPANDED_DIAGNOSIS_CODE,"[sss_task] Listen failed"); + OSMutexPost(mutex); + 8002190: d0a03c17 ldw r2,-32528(gp) + 8002194: 1009883a mov r4,r2 + 8002198: 80142380 call 8014238 + return -2; + 800219c: 00bfff84 movi r2,-2 + 80021a0: 00001506 br 80021f8 + } + + ss_reset_connection(&(connections[channel])); + 80021a4: e0bffa17 ldw r2,-24(fp) + 80021a8: 1006913a slli r3,r2,4 + 80021ac: 00820174 movhi r2,2053 + 80021b0: 10b36004 addi r2,r2,-12928 + 80021b4: 1885883a add r2,r3,r2 + 80021b8: 1009883a mov r4,r2 + 80021bc: 8001d1c0 call 8001d1c + connections[channel].listenport = port; + 80021c0: e0bffa17 ldw r2,-24(fp) + 80021c4: 1008913a slli r4,r2,4 + 80021c8: e0fff917 ldw r3,-28(fp) + 80021cc: 00820174 movhi r2,2053 + 80021d0: 2085883a add r2,r4,r2 + 80021d4: 10f36315 stw r3,-12916(r2) + printf("[sss_task] Simple Socket Server listening on port %d\n", port); + 80021d8: e17ff917 ldw r5,-28(fp) + 80021dc: 01020134 movhi r4,2052 + 80021e0: 211c2f04 addi r4,r4,28860 + 80021e4: 8002c780 call 8002c78 + + OSMutexPost(mutex); + 80021e8: d0a03c17 ldw r2,-32528(gp) + 80021ec: 1009883a mov r4,r2 + 80021f0: 80142380 call 8014238 + return 0; + 80021f4: 0005883a mov r2,zero +} + 80021f8: e037883a mov sp,fp + 80021fc: dfc00117 ldw ra,4(sp) + 8002200: df000017 ldw fp,0(sp) + 8002204: dec00204 addi sp,sp,8 + 8002208: f800283a ret + +0800220c : + +int ethernet_write(int channel, int size, unsigned char* data) +{ + 800220c: defff904 addi sp,sp,-28 + 8002210: dfc00615 stw ra,24(sp) + 8002214: df000515 stw fp,20(sp) + 8002218: df000504 addi fp,sp,20 + 800221c: e13ffd15 stw r4,-12(fp) + 8002220: e17ffc15 stw r5,-16(fp) + 8002224: e1bffb15 stw r6,-20(fp) + int result; + + INT8U err; + OSMutexPend(mutex, 0, &err); + 8002228: d0a03c17 ldw r2,-32528(gp) + 800222c: e0fffec4 addi r3,fp,-5 + 8002230: 180d883a mov r6,r3 + 8002234: 000b883a mov r5,zero + 8002238: 1009883a mov r4,r2 + 800223c: 8013cdc0 call 8013cdc + + if (connections[channel].fd_conn == -1) //socket is closed or channel unconfigured + 8002240: e0bffd17 ldw r2,-12(fp) + 8002244: 1006913a slli r3,r2,4 + 8002248: 00820174 movhi r2,2053 + 800224c: 1885883a add r2,r3,r2 + 8002250: 10b36217 ldw r2,-12920(r2) + 8002254: 10bfffd8 cmpnei r2,r2,-1 + 8002258: 1000051e bne r2,zero,8002270 + { + OSMutexPost(mutex); + 800225c: d0a03c17 ldw r2,-32528(gp) + 8002260: 1009883a mov r4,r2 + 8002264: 80142380 call 8014238 + return 0; + 8002268: 0005883a mov r2,zero + 800226c: 00002406 br 8002300 + } + + result = (int)send(connections[channel].fd_conn, data, size, 0); + 8002270: e0bffd17 ldw r2,-12(fp) + 8002274: 1006913a slli r3,r2,4 + 8002278: 00820174 movhi r2,2053 + 800227c: 1885883a add r2,r3,r2 + 8002280: 10b36217 ldw r2,-12920(r2) + 8002284: 000f883a mov r7,zero + 8002288: e1bffc17 ldw r6,-16(fp) + 800228c: e17ffb17 ldw r5,-20(fp) + 8002290: 1009883a mov r4,r2 + 8002294: 802cb9c0 call 802cb9c + 8002298: e0bfff15 stw r2,-4(fp) + if (result == -1) + 800229c: e0bfff17 ldw r2,-4(fp) + 80022a0: 10bfffd8 cmpnei r2,r2,-1 + 80022a4: 1000121e bne r2,zero,80022f0 + { + printf("[ethernet_write] closing connection due to error\n"); + 80022a8: 01020134 movhi r4,2052 + 80022ac: 211c3d04 addi r4,r4,28916 + 80022b0: 8002d9c0 call 8002d9c + close(connections[channel].fd_conn); //close connection on error + 80022b4: e0bffd17 ldw r2,-12(fp) + 80022b8: 1006913a slli r3,r2,4 + 80022bc: 00820174 movhi r2,2053 + 80022c0: 1885883a add r2,r3,r2 + 80022c4: 10b36217 ldw r2,-12920(r2) + 80022c8: 1009883a mov r4,r2 + 80022cc: 8022a600 call 8022a60 + ss_reset_connection(&(connections[channel])); + 80022d0: e0bffd17 ldw r2,-12(fp) + 80022d4: 1006913a slli r3,r2,4 + 80022d8: 00820174 movhi r2,2053 + 80022dc: 10b36004 addi r2,r2,-12928 + 80022e0: 1885883a add r2,r3,r2 + 80022e4: 1009883a mov r4,r2 + 80022e8: 8001d1c0 call 8001d1c + result = 0; + 80022ec: e03fff15 stw zero,-4(fp) + } + + OSMutexPost(mutex); + 80022f0: d0a03c17 ldw r2,-32528(gp) + 80022f4: 1009883a mov r4,r2 + 80022f8: 80142380 call 8014238 + return result; + 80022fc: e0bfff17 ldw r2,-4(fp) +} + 8002300: e037883a mov sp,fp + 8002304: dfc00117 ldw ra,4(sp) + 8002308: df000017 ldw fp,0(sp) + 800230c: dec00204 addi sp,sp,8 + 8002310: f800283a ret + +08002314 : + +int ethernet_read(int channel, int size, unsigned char* data) +{ + 8002314: deffb304 addi sp,sp,-308 + 8002318: dfc04c15 stw ra,304(sp) + 800231c: df004b15 stw fp,300(sp) + 8002320: df004b04 addi fp,sp,300 + 8002324: e13fb815 stw r4,-288(fp) + 8002328: e17fb715 stw r5,-292(fp) + 800232c: e1bfb615 stw r6,-296(fp) + int max_socket; + BSD_TIMEVAL_T timeout; + int result; + + INT8U err; + OSMutexPend(mutex, 0, &err); + 8002330: d0a03c17 ldw r2,-32528(gp) + 8002334: e0ffb9c4 addi r3,fp,-281 + 8002338: 180d883a mov r6,r3 + 800233c: 000b883a mov r5,zero + 8002340: 1009883a mov r4,r2 + 8002344: 8013cdc0 call 8013cdc + + if (connections[channel].fd_conn == -1) //socket is closed or channel unconfigured + 8002348: e0bfb817 ldw r2,-288(fp) + 800234c: 1006913a slli r3,r2,4 + 8002350: 00820174 movhi r2,2053 + 8002354: 1885883a add r2,r3,r2 + 8002358: 10b36217 ldw r2,-12920(r2) + 800235c: 10bfffd8 cmpnei r2,r2,-1 + 8002360: 1000051e bne r2,zero,8002378 + { + OSMutexPost(mutex); + 8002364: d0a03c17 ldw r2,-32528(gp) + 8002368: 1009883a mov r4,r2 + 800236c: 80142380 call 8014238 + return 0; + 8002370: 0005883a mov r2,zero + 8002374: 00005006 br 80024b8 + } + + //prepare call parameters + FD_ZERO(&readfds); + 8002378: e03fbd15 stw zero,-268(fp) + FD_SET(connections[channel].fd_conn, &readfds); + 800237c: e0bfb817 ldw r2,-288(fp) + 8002380: 1006913a slli r3,r2,4 + 8002384: 00820174 movhi r2,2053 + 8002388: 1885883a add r2,r3,r2 + 800238c: 10b36217 ldw r2,-12920(r2) + 8002390: e0ffbd04 addi r3,fp,-268 + 8002394: 180b883a mov r5,r3 + 8002398: 1009883a mov r4,r2 + 800239c: 8030b180 call 8030b18 + max_socket = connections[channel].fd_conn+1; + 80023a0: e0bfb817 ldw r2,-288(fp) + 80023a4: 1006913a slli r3,r2,4 + 80023a8: 00820174 movhi r2,2053 + 80023ac: 1885883a add r2,r3,r2 + 80023b0: 10b36217 ldw r2,-12920(r2) + 80023b4: 10800044 addi r2,r2,1 + 80023b8: e0bffe15 stw r2,-8(fp) + timeout.tv_sec = 0; + 80023bc: e03fba15 stw zero,-280(fp) + 80023c0: e03fbb15 stw zero,-276(fp) + timeout.tv_usec = 0; + 80023c4: e03fbc15 stw zero,-272(fp) + + //check for data + if (select(max_socket, &readfds, NULL, NULL, &timeout)) + 80023c8: e0ffbd04 addi r3,fp,-268 + 80023cc: e0bfba04 addi r2,fp,-280 + 80023d0: d8800015 stw r2,0(sp) + 80023d4: 000f883a mov r7,zero + 80023d8: 000d883a mov r6,zero + 80023dc: 180b883a mov r5,r3 + 80023e0: e13ffe17 ldw r4,-8(fp) + 80023e4: 8026a740 call 8026a74 + 80023e8: 10002f26 beq r2,zero,80024a8 + if (FD_ISSET(connections[channel].fd_conn, &readfds)) + 80023ec: e0bfb817 ldw r2,-288(fp) + 80023f0: 1006913a slli r3,r2,4 + 80023f4: 00820174 movhi r2,2053 + 80023f8: 1885883a add r2,r3,r2 + 80023fc: 10b36217 ldw r2,-12920(r2) + 8002400: e0ffbd04 addi r3,fp,-268 + 8002404: 180b883a mov r5,r3 + 8002408: 1009883a mov r4,r2 + 800240c: 8030b8c0 call 8030b8c + 8002410: 10002526 beq r2,zero,80024a8 + { + result = (int)recv(connections[channel].fd_conn, data, size, 0); + 8002414: e0bfb817 ldw r2,-288(fp) + 8002418: 1006913a slli r3,r2,4 + 800241c: 00820174 movhi r2,2053 + 8002420: 1885883a add r2,r3,r2 + 8002424: 10b36217 ldw r2,-12920(r2) + 8002428: 000f883a mov r7,zero + 800242c: e1bfb717 ldw r6,-292(fp) + 8002430: e17fb617 ldw r5,-296(fp) + 8002434: 1009883a mov r4,r2 + 8002438: 802c7940 call 802c794 + 800243c: e0bfff15 stw r2,-4(fp) + if (result == -1) + 8002440: e0bfff17 ldw r2,-4(fp) + 8002444: 10bfffd8 cmpnei r2,r2,-1 + 8002448: 1000121e bne r2,zero,8002494 + { + printf("[ethernet_read] closing connection due to error\n"); + 800244c: 01020134 movhi r4,2052 + 8002450: 211c4a04 addi r4,r4,28968 + 8002454: 8002d9c0 call 8002d9c + close(connections[channel].fd_conn); //close connection on error + 8002458: e0bfb817 ldw r2,-288(fp) + 800245c: 1006913a slli r3,r2,4 + 8002460: 00820174 movhi r2,2053 + 8002464: 1885883a add r2,r3,r2 + 8002468: 10b36217 ldw r2,-12920(r2) + 800246c: 1009883a mov r4,r2 + 8002470: 8022a600 call 8022a60 + ss_reset_connection(&(connections[channel])); + 8002474: e0bfb817 ldw r2,-288(fp) + 8002478: 1006913a slli r3,r2,4 + 800247c: 00820174 movhi r2,2053 + 8002480: 10b36004 addi r2,r2,-12928 + 8002484: 1885883a add r2,r3,r2 + 8002488: 1009883a mov r4,r2 + 800248c: 8001d1c0 call 8001d1c + result = 0; + 8002490: e03fff15 stw zero,-4(fp) + } + OSMutexPost(mutex); + 8002494: d0a03c17 ldw r2,-32528(gp) + 8002498: 1009883a mov r4,r2 + 800249c: 80142380 call 8014238 + return result; + 80024a0: e0bfff17 ldw r2,-4(fp) + 80024a4: 00000406 br 80024b8 + } + + OSMutexPost(mutex); + 80024a8: d0a03c17 ldw r2,-32528(gp) + 80024ac: 1009883a mov r4,r2 + 80024b0: 80142380 call 8014238 + return 0; + 80024b4: 0005883a mov r2,zero +} + 80024b8: e037883a mov sp,fp + 80024bc: dfc00117 ldw ra,4(sp) + 80024c0: df000017 ldw fp,0(sp) + 80024c4: dec00204 addi sp,sp,8 + 80024c8: f800283a ret + +080024cc : + +int ethernet_close(int channel) +{ + 80024cc: defffc04 addi sp,sp,-16 + 80024d0: dfc00315 stw ra,12(sp) + 80024d4: df000215 stw fp,8(sp) + 80024d8: df000204 addi fp,sp,8 + 80024dc: e13ffe15 stw r4,-8(fp) + INT8U err; + OSMutexPend(mutex, 0, &err); + 80024e0: d0a03c17 ldw r2,-32528(gp) + 80024e4: e0ffffc4 addi r3,fp,-1 + 80024e8: 180d883a mov r6,r3 + 80024ec: 000b883a mov r5,zero + 80024f0: 1009883a mov r4,r2 + 80024f4: 8013cdc0 call 8013cdc + + close(connections[channel].fd_conn); + 80024f8: e0bffe17 ldw r2,-8(fp) + 80024fc: 1006913a slli r3,r2,4 + 8002500: 00820174 movhi r2,2053 + 8002504: 1885883a add r2,r3,r2 + 8002508: 10b36217 ldw r2,-12920(r2) + 800250c: 1009883a mov r4,r2 + 8002510: 8022a600 call 8022a60 + ss_reset_connection(&(connections[channel])); + 8002514: e0bffe17 ldw r2,-8(fp) + 8002518: 1006913a slli r3,r2,4 + 800251c: 00820174 movhi r2,2053 + 8002520: 10b36004 addi r2,r2,-12928 + 8002524: 1885883a add r2,r3,r2 + 8002528: 1009883a mov r4,r2 + 800252c: 8001d1c0 call 8001d1c + + OSMutexPost(mutex); + 8002530: d0a03c17 ldw r2,-32528(gp) + 8002534: 1009883a mov r4,r2 + 8002538: 80142380 call 8014238 + return 0; + 800253c: 0005883a mov r2,zero +} + 8002540: e037883a mov sp,fp + 8002544: dfc00117 ldw ra,4(sp) + 8002548: df000017 ldw fp,0(sp) + 800254c: dec00204 addi sp,sp,8 + 8002550: f800283a ret + +08002554 : + +//******************************************************************* + + +void udpgen_command_bit(alt_u32 base, alt_u8 bitmask, alt_u8 state) +{ + 8002554: defffb04 addi sp,sp,-20 + 8002558: df000415 stw fp,16(sp) + 800255c: df000404 addi fp,sp,16 + 8002560: e13ffe15 stw r4,-8(fp) + 8002564: 2805883a mov r2,r5 + 8002568: 3007883a mov r3,r6 + 800256c: e0bffd05 stb r2,-12(fp) + 8002570: 1805883a mov r2,r3 + 8002574: e0bffc05 stb r2,-16(fp) + alt_u8 tmp = IORD_8DIRECT(base, UDPGEN_REG_CSR); + 8002578: e0bffe17 ldw r2,-8(fp) + 800257c: 10800023 ldbuio r2,0(r2) + 8002580: 10803fcc andi r2,r2,255 + 8002584: e0bfffc5 stb r2,-1(fp) + if (state) + 8002588: e0bffc03 ldbu r2,-16(fp) + 800258c: 10000526 beq r2,zero,80025a4 + tmp |= bitmask; + 8002590: e0ffffc3 ldbu r3,-1(fp) + 8002594: e0bffd03 ldbu r2,-12(fp) + 8002598: 1884b03a or r2,r3,r2 + 800259c: e0bfffc5 stb r2,-1(fp) + 80025a0: 00000606 br 80025bc + else + tmp &= ~bitmask; + 80025a4: e0bffd03 ldbu r2,-12(fp) + 80025a8: 0084303a nor r2,zero,r2 + 80025ac: 1007883a mov r3,r2 + 80025b0: e0bfffc3 ldbu r2,-1(fp) + 80025b4: 1884703a and r2,r3,r2 + 80025b8: e0bfffc5 stb r2,-1(fp) + IOWR_8DIRECT(base, UDPGEN_REG_CSR, tmp); + 80025bc: e0bffe17 ldw r2,-8(fp) + 80025c0: e0ffffc3 ldbu r3,-1(fp) + 80025c4: 10c00025 stbio r3,0(r2) +} + 80025c8: 0001883a nop + 80025cc: e037883a mov sp,fp + 80025d0: df000017 ldw fp,0(sp) + 80025d4: dec00104 addi sp,sp,4 + 80025d8: f800283a ret + +080025dc : + +void udpgen_test(alt_u32 base) +{ + 80025dc: defff604 addi sp,sp,-40 + 80025e0: dfc00915 stw ra,36(sp) + 80025e4: df000815 stw fp,32(sp) + 80025e8: df000804 addi fp,sp,32 + 80025ec: e13ff815 stw r4,-32(fp) + printf (" *** Setting up UDP generator... \n"); + 80025f0: 01020134 movhi r4,2052 + 80025f4: 211c6004 addi r4,r4,29056 + 80025f8: 8002d9c0 call 8002d9c + + unsigned char dstmac[] = {0x18, 0xd6, 0xc7, 0x05, 0xaa, 0x63}; + 80025fc: 00800604 movi r2,24 + 8002600: e0bffb85 stb r2,-18(fp) + 8002604: 00bff584 movi r2,-42 + 8002608: e0bffbc5 stb r2,-17(fp) + 800260c: 00bff1c4 movi r2,-57 + 8002610: e0bffc05 stb r2,-16(fp) + 8002614: 00800144 movi r2,5 + 8002618: e0bffc45 stb r2,-15(fp) + 800261c: 00bfea84 movi r2,-86 + 8002620: e0bffc85 stb r2,-14(fp) + 8002624: 008018c4 movi r2,99 + 8002628: e0bffcc5 stb r2,-13(fp) + unsigned char srcip[] = {10,0,7,17}; + 800262c: 00800284 movi r2,10 + 8002630: e0bffa85 stb r2,-22(fp) + 8002634: e03ffac5 stb zero,-21(fp) + 8002638: 008001c4 movi r2,7 + 800263c: e0bffb05 stb r2,-20(fp) + 8002640: 00800444 movi r2,17 + 8002644: e0bffb45 stb r2,-19(fp) + unsigned char dstip[] = {10,0,7,1}; + 8002648: 00800284 movi r2,10 + 800264c: e0bff985 stb r2,-26(fp) + 8002650: e03ff9c5 stb zero,-25(fp) + 8002654: 008001c4 movi r2,7 + 8002658: e0bffa05 stb r2,-24(fp) + 800265c: 00800044 movi r2,1 + 8002660: e0bffa45 stb r2,-23(fp) + + udpgen_command(UDP_GENERATOR_BASE, 0x01); + 8002664: 00c00044 movi r3,1 + 8002668: 00861034 movhi r2,6208 + 800266c: 10cf3025 stbio r3,15552(r2) + udpgen_set_size(UDP_GENERATOR_BASE, 16); + 8002670: 00c00404 movi r3,16 + 8002674: 00861034 movhi r2,6208 + 8002678: 10cf30ad sthio r3,15554(r2) + udpgen_set_srcip_a(UDP_GENERATOR_BASE, srcip); + 800267c: e03fff15 stw zero,-4(fp) + 8002680: 00001006 br 80026c4 + 8002684: e0bfff17 ldw r2,-4(fp) + 8002688: 10800104 addi r2,r2,4 + 800268c: 1007883a mov r3,r2 + 8002690: 00861034 movhi r2,6208 + 8002694: 108f3004 addi r2,r2,15552 + 8002698: 1885883a add r2,r3,r2 + 800269c: 010000c4 movi r4,3 + 80026a0: e0ffff17 ldw r3,-4(fp) + 80026a4: 20c7c83a sub r3,r4,r3 + 80026a8: e0c7883a add r3,fp,r3 + 80026ac: 18fffa83 ldbu r3,-22(r3) + 80026b0: 18c03fcc andi r3,r3,255 + 80026b4: 10c00025 stbio r3,0(r2) + 80026b8: e0bfff17 ldw r2,-4(fp) + 80026bc: 10800044 addi r2,r2,1 + 80026c0: e0bfff15 stw r2,-4(fp) + 80026c4: e0bfff17 ldw r2,-4(fp) + 80026c8: 10800110 cmplti r2,r2,4 + 80026cc: 103fed1e bne r2,zero,8002684 + udpgen_set_dstip_a(UDP_GENERATOR_BASE, dstip); + 80026d0: e03ffe15 stw zero,-8(fp) + 80026d4: 00001006 br 8002718 + 80026d8: e0bffe17 ldw r2,-8(fp) + 80026dc: 10800204 addi r2,r2,8 + 80026e0: 1007883a mov r3,r2 + 80026e4: 00861034 movhi r2,6208 + 80026e8: 108f3004 addi r2,r2,15552 + 80026ec: 1885883a add r2,r3,r2 + 80026f0: 010000c4 movi r4,3 + 80026f4: e0fffe17 ldw r3,-8(fp) + 80026f8: 20c7c83a sub r3,r4,r3 + 80026fc: e0c7883a add r3,fp,r3 + 8002700: 18fff983 ldbu r3,-26(r3) + 8002704: 18c03fcc andi r3,r3,255 + 8002708: 10c00025 stbio r3,0(r2) + 800270c: e0bffe17 ldw r2,-8(fp) + 8002710: 10800044 addi r2,r2,1 + 8002714: e0bffe15 stw r2,-8(fp) + 8002718: e0bffe17 ldw r2,-8(fp) + 800271c: 10800110 cmplti r2,r2,4 + 8002720: 103fed1e bne r2,zero,80026d8 + udpgen_set_srcport(UDP_GENERATOR_BASE, 4096); + 8002724: 00c40004 movi r3,4096 + 8002728: 00861034 movhi r2,6208 + 800272c: 10cf33ad sthio r3,15566(r2) + udpgen_set_dstport(UDP_GENERATOR_BASE, 4097); + 8002730: 00c40044 movi r3,4097 + 8002734: 00861034 movhi r2,6208 + 8002738: 10cf332d sthio r3,15564(r2) + udpgen_set_dstmac_a(UDP_GENERATOR_BASE, dstmac); + 800273c: e03ffd15 stw zero,-12(fp) + 8002740: 00001006 br 8002784 + 8002744: e0bffd17 ldw r2,-12(fp) + 8002748: 10800404 addi r2,r2,16 + 800274c: 1007883a mov r3,r2 + 8002750: 00861034 movhi r2,6208 + 8002754: 108f3004 addi r2,r2,15552 + 8002758: 1885883a add r2,r3,r2 + 800275c: 01000144 movi r4,5 + 8002760: e0fffd17 ldw r3,-12(fp) + 8002764: 20c7c83a sub r3,r4,r3 + 8002768: e0c7883a add r3,fp,r3 + 800276c: 18fffb83 ldbu r3,-18(r3) + 8002770: 18c03fcc andi r3,r3,255 + 8002774: 10c00025 stbio r3,0(r2) + 8002778: e0bffd17 ldw r2,-12(fp) + 800277c: 10800044 addi r2,r2,1 + 8002780: e0bffd15 stw r2,-12(fp) + 8002784: e0bffd17 ldw r2,-12(fp) + 8002788: 10800190 cmplti r2,r2,6 + 800278c: 103fed1e bne r2,zero,8002744 +} + 8002790: 0001883a nop + 8002794: e037883a mov sp,fp + 8002798: dfc00117 ldw ra,4(sp) + 800279c: df000017 ldw fp,0(sp) + 80027a0: dec00204 addi sp,sp,8 + 80027a4: f800283a ret + +080027a8 : + +//****************************************************** + +//Swap odd/even bytes in a bunch of data to align endianness of shorts +void swap_bytes(unsigned char* array, int size_bytes) +{ + 80027a8: defffb04 addi sp,sp,-20 + 80027ac: df000415 stw fp,16(sp) + 80027b0: df000404 addi fp,sp,16 + 80027b4: e13ffd15 stw r4,-12(fp) + 80027b8: e17ffc15 stw r5,-16(fp) + for (int i = 0; i < size_bytes; i+= 2) + 80027bc: e03fff15 stw zero,-4(fp) + 80027c0: 00001706 br 8002820 + { + unsigned char tmp = array[i]; + 80027c4: e0bfff17 ldw r2,-4(fp) + 80027c8: e0fffd17 ldw r3,-12(fp) + 80027cc: 1885883a add r2,r3,r2 + 80027d0: 10800003 ldbu r2,0(r2) + 80027d4: e0bffec5 stb r2,-5(fp) + array[i] = array[i+1]; + 80027d8: e0bfff17 ldw r2,-4(fp) + 80027dc: 10800044 addi r2,r2,1 + 80027e0: e0fffd17 ldw r3,-12(fp) + 80027e4: 1887883a add r3,r3,r2 + 80027e8: e0bfff17 ldw r2,-4(fp) + 80027ec: e13ffd17 ldw r4,-12(fp) + 80027f0: 2085883a add r2,r4,r2 + 80027f4: 18c00003 ldbu r3,0(r3) + 80027f8: 10c00005 stb r3,0(r2) + array[i+1] = tmp; + 80027fc: e0bfff17 ldw r2,-4(fp) + 8002800: 10800044 addi r2,r2,1 + 8002804: e0fffd17 ldw r3,-12(fp) + 8002808: 1885883a add r2,r3,r2 + 800280c: e0fffec3 ldbu r3,-5(fp) + 8002810: 10c00005 stb r3,0(r2) + for (int i = 0; i < size_bytes; i+= 2) + 8002814: e0bfff17 ldw r2,-4(fp) + 8002818: 10800084 addi r2,r2,2 + 800281c: e0bfff15 stw r2,-4(fp) + 8002820: e0ffff17 ldw r3,-4(fp) + 8002824: e0bffc17 ldw r2,-16(fp) + 8002828: 18bfe616 blt r3,r2,80027c4 + } +} + 800282c: 0001883a nop + 8002830: e037883a mov sp,fp + 8002834: df000017 ldw fp,0(sp) + 8002838: dec00104 addi sp,sp,4 + 800283c: f800283a ret + +08002840 : +//The same, but four-byte-wise +void swap_quad(unsigned char* array, int size_bytes) +{ + 8002840: defffa04 addi sp,sp,-24 + 8002844: df000515 stw fp,20(sp) + 8002848: df000504 addi fp,sp,20 + 800284c: e13ffc15 stw r4,-16(fp) + 8002850: e17ffb15 stw r5,-20(fp) + unsigned char buf[4]; + + for (int i = 0; i < size_bytes; i+= 4) + 8002854: e03fff15 stw zero,-4(fp) + 8002858: 00002206 br 80028e4 + { + memcpy(buf, array+i, 4); + 800285c: e0bfff17 ldw r2,-4(fp) + 8002860: e0fffc17 ldw r3,-16(fp) + 8002864: 1885883a add r2,r3,r2 + 8002868: 10c00003 ldbu r3,0(r2) + 800286c: e0fffd05 stb r3,-12(fp) + 8002870: 10c00043 ldbu r3,1(r2) + 8002874: e0fffd45 stb r3,-11(fp) + 8002878: 10c00083 ldbu r3,2(r2) + 800287c: e0fffd85 stb r3,-10(fp) + 8002880: 108000c3 ldbu r2,3(r2) + 8002884: e0bffdc5 stb r2,-9(fp) + for (int j = 0; j < 4; j++) + 8002888: e03ffe15 stw zero,-8(fp) + 800288c: 00000f06 br 80028cc + array[i+j] = buf[3-j]; + 8002890: 00c000c4 movi r3,3 + 8002894: e0bffe17 ldw r2,-8(fp) + 8002898: 1887c83a sub r3,r3,r2 + 800289c: e13fff17 ldw r4,-4(fp) + 80028a0: e0bffe17 ldw r2,-8(fp) + 80028a4: 2085883a add r2,r4,r2 + 80028a8: 1009883a mov r4,r2 + 80028ac: e0bffc17 ldw r2,-16(fp) + 80028b0: 1105883a add r2,r2,r4 + 80028b4: e0c7883a add r3,fp,r3 + 80028b8: 18fffd03 ldbu r3,-12(r3) + 80028bc: 10c00005 stb r3,0(r2) + for (int j = 0; j < 4; j++) + 80028c0: e0bffe17 ldw r2,-8(fp) + 80028c4: 10800044 addi r2,r2,1 + 80028c8: e0bffe15 stw r2,-8(fp) + 80028cc: e0bffe17 ldw r2,-8(fp) + 80028d0: 10800110 cmplti r2,r2,4 + 80028d4: 103fee1e bne r2,zero,8002890 + for (int i = 0; i < size_bytes; i+= 4) + 80028d8: e0bfff17 ldw r2,-4(fp) + 80028dc: 10800104 addi r2,r2,4 + 80028e0: e0bfff15 stw r2,-4(fp) + 80028e4: e0ffff17 ldw r3,-4(fp) + 80028e8: e0bffb17 ldw r2,-20(fp) + 80028ec: 18bfdb16 blt r3,r2,800285c + } +} + 80028f0: 0001883a nop + 80028f4: e037883a mov sp,fp + 80028f8: df000017 ldw fp,0(sp) + 80028fc: dec00104 addi sp,sp,4 + 8002900: f800283a ret + +08002904 : + + //trigger FPGA reload +void reload_fpga() +{ + 8002904: defffe04 addi sp,sp,-8 + 8002908: dfc00115 stw ra,4(sp) + 800290c: df000015 stw fp,0(sp) + 8002910: d839883a mov fp,sp + printf("$$$$ RECONFIGURING FPGA!!! $$$$\n"); + 8002914: 01020134 movhi r4,2052 + 8002918: 211c6904 addi r4,r4,29092 + 800291c: 8002d9c0 call 8002d9c + //TK_SLEEP(100); //let it print the message before dying + //IOWR(DUAL_BOOT_BASE, 0, 0x1); + printf("*** DISABLED! ***\n"); + 8002920: 01020134 movhi r4,2052 + 8002924: 211c7104 addi r4,r4,29124 + 8002928: 8002d9c0 call 8002d9c +} + 800292c: 0001883a nop + 8002930: e037883a mov sp,fp + 8002934: dfc00117 ldw ra,4(sp) + 8002938: df000017 ldw fp,0(sp) + 800293c: dec00204 addi sp,sp,8 + 8002940: f800283a ret + +08002944 : + +void masterslave(alt_u8 master) +{ + 8002944: defffd04 addi sp,sp,-12 + 8002948: dfc00215 stw ra,8(sp) + 800294c: df000115 stw fp,4(sp) + 8002950: df000104 addi fp,sp,4 + 8002954: 2005883a mov r2,r4 + 8002958: e0bfff05 stb r2,-4(fp) + if (master) + 800295c: e0bfff03 ldbu r2,-4(fp) + 8002960: 10000426 beq r2,zero,8002974 + IOWR_ALTERA_AVALON_PIO_SET_BITS(OUTPUT_PIO_BASE, 0x80); + 8002964: 00c02004 movi r3,128 + 8002968: 00861034 movhi r2,6208 + 800296c: 10cf1435 stwio r3,15440(r2) + 8002970: 00000306 br 8002980 + else + IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(OUTPUT_PIO_BASE, 0x80); + 8002974: 00c02004 movi r3,128 + 8002978: 00861034 movhi r2,6208 + 800297c: 10cf1535 stwio r3,15444(r2) + mastermode = master; + 8002980: e0bfff03 ldbu r2,-4(fp) + 8002984: d0a03d85 stb r2,-32522(gp) + set_delay(mastermode, delays[mastermode]); //update sensor delay setting + 8002988: d0a03d83 ldbu r2,-32522(gp) + 800298c: 11003fcc andi r4,r2,255 + 8002990: d0a03d83 ldbu r2,-32522(gp) + 8002994: 10803fcc andi r2,r2,255 + 8002998: 1087883a add r3,r2,r2 + 800299c: d0a03e04 addi r2,gp,-32520 + 80029a0: 1885883a add r2,r3,r2 + 80029a4: 1080000b ldhu r2,0(r2) + 80029a8: 10bfffcc andi r2,r2,65535 + 80029ac: 100b883a mov r5,r2 + 80029b0: 8002bc80 call 8002bc8 +} + 80029b4: 0001883a nop + 80029b8: e037883a mov sp,fp + 80029bc: dfc00117 ldw ra,4(sp) + 80029c0: df000017 ldw fp,0(sp) + 80029c4: dec00204 addi sp,sp,8 + 80029c8: f800283a ret + +080029cc : + +void master_clock_period(alt_u32 period) +{ + 80029cc: defffe04 addi sp,sp,-8 + 80029d0: df000115 stw fp,4(sp) + 80029d4: df000104 addi fp,sp,4 + 80029d8: e13fff15 stw r4,-4(fp) + //set period + IOWR_ALTERA_AVALON_TIMER_PERIODL(FRAME_TIMER_BASE, (alt_u16)(period & 0xFFFF)); + 80029dc: e0bfff17 ldw r2,-4(fp) + 80029e0: 10ffffcc andi r3,r2,65535 + 80029e4: 00861034 movhi r2,6208 + 80029e8: 10cf0235 stwio r3,15368(r2) + IOWR_ALTERA_AVALON_TIMER_PERIODH(FRAME_TIMER_BASE, (alt_u16)((period>>16) & 0xFFFF)); + 80029ec: e0bfff17 ldw r2,-4(fp) + 80029f0: 1004d43a srli r2,r2,16 + 80029f4: 10ffffcc andi r3,r2,65535 + 80029f8: 00861034 movhi r2,6208 + 80029fc: 10cf0335 stwio r3,15372(r2) + //start timer in continuous mode + //IOWR_ALTERA_AVALON_TIMER_CONTROL(FRAME_TIMER_BASE, + // ALTERA_AVALON_TIMER_CONTROL_CONT_MSK); +} + 8002a00: 0001883a nop + 8002a04: e037883a mov sp,fp + 8002a08: df000017 ldw fp,0(sp) + 8002a0c: dec00104 addi sp,sp,4 + 8002a10: f800283a ret + +08002a14 : + +void master_clock_enable(alt_u8 en) +{ + 8002a14: defffd04 addi sp,sp,-12 + 8002a18: df000215 stw fp,8(sp) + 8002a1c: df000204 addi fp,sp,8 + 8002a20: 2005883a mov r2,r4 + 8002a24: e0bffe05 stb r2,-8(fp) + alt_u16 tmp = 0; // = IORD_ALTERA_AVALON_TIMER_CONTROL(FRAME_TIMER_BASE); + 8002a28: e03fff8d sth zero,-2(fp) + + if (en) + 8002a2c: e0bffe03 ldbu r2,-8(fp) + 8002a30: 10000426 beq r2,zero,8002a44 + tmp |= ALTERA_AVALON_TIMER_CONTROL_START_MSK | ALTERA_AVALON_TIMER_CONTROL_CONT_MSK; + 8002a34: e0bfff8b ldhu r2,-2(fp) + 8002a38: 10800194 ori r2,r2,6 + 8002a3c: e0bfff8d sth r2,-2(fp) + 8002a40: 00000306 br 8002a50 + else + tmp |= ALTERA_AVALON_TIMER_CONTROL_STOP_MSK; + 8002a44: e0bfff8b ldhu r2,-2(fp) + 8002a48: 10800214 ori r2,r2,8 + 8002a4c: e0bfff8d sth r2,-2(fp) + + IOWR_ALTERA_AVALON_TIMER_CONTROL(FRAME_TIMER_BASE,tmp); + 8002a50: e0ffff8b ldhu r3,-2(fp) + 8002a54: 00861034 movhi r2,6208 + 8002a58: 10cf0135 stwio r3,15364(r2) +} + 8002a5c: 0001883a nop + 8002a60: e037883a mov sp,fp + 8002a64: df000017 ldw fp,0(sp) + 8002a68: dec00104 addi sp,sp,4 + 8002a6c: f800283a ret + +08002a70 : + +void led_set(alt_u8 led_nr) +{ + 8002a70: defffe04 addi sp,sp,-8 + 8002a74: df000115 stw fp,4(sp) + 8002a78: df000104 addi fp,sp,4 + 8002a7c: 2005883a mov r2,r4 + 8002a80: e0bfff05 stb r2,-4(fp) + if (led_nr > 4) + 8002a84: e0bfff03 ldbu r2,-4(fp) + 8002a88: 10800170 cmpltui r2,r2,5 + 8002a8c: 10000626 beq r2,zero,8002aa8 + return; + IOWR_ALTERA_AVALON_PIO_SET_BITS(OUTPUT_PIO_BASE, 1< + return; + 8002aa8: 0001883a nop +} + 8002aac: e037883a mov sp,fp + 8002ab0: df000017 ldw fp,0(sp) + 8002ab4: dec00104 addi sp,sp,4 + 8002ab8: f800283a ret + +08002abc : + +void led_clear(alt_u8 led_nr) +{ + 8002abc: defffe04 addi sp,sp,-8 + 8002ac0: df000115 stw fp,4(sp) + 8002ac4: df000104 addi fp,sp,4 + 8002ac8: 2005883a mov r2,r4 + 8002acc: e0bfff05 stb r2,-4(fp) + if (led_nr > 4) + 8002ad0: e0bfff03 ldbu r2,-4(fp) + 8002ad4: 10800170 cmpltui r2,r2,5 + 8002ad8: 10000626 beq r2,zero,8002af4 + return; + IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(OUTPUT_PIO_BASE, 1< + return; + 8002af4: 0001883a nop +} + 8002af8: e037883a mov sp,fp + 8002afc: df000017 ldw fp,0(sp) + 8002b00: dec00104 addi sp,sp,4 + 8002b04: f800283a ret + +08002b08 : + +void led_toggle(alt_u8 led_nr) +{ + 8002b08: defffd04 addi sp,sp,-12 + 8002b0c: df000215 stw fp,8(sp) + 8002b10: df000204 addi fp,sp,8 + 8002b14: 2005883a mov r2,r4 + 8002b18: e0bffe05 stb r2,-8(fp) + if (led_nr > 4) + 8002b1c: e0bffe03 ldbu r2,-8(fp) + 8002b20: 10800170 cmpltui r2,r2,5 + 8002b24: 10001026 beq r2,zero,8002b68 + return; + alt_u32 tmp = IORD_ALTERA_AVALON_PIO_DATA(OUTPUT_PIO_BASE); + 8002b28: 00861034 movhi r2,6208 + 8002b2c: 108f1037 ldwio r2,15424(r2) + 8002b30: e0bfff15 stw r2,-4(fp) + tmp ^= (1< + return; + 8002b68: 0001883a nop +} + 8002b6c: e037883a mov sp,fp + 8002b70: df000017 ldw fp,0(sp) + 8002b74: dec00104 addi sp,sp,4 + 8002b78: f800283a ret + +08002b7c : + +void led4_blink_enable(alt_u8 en) +{ + 8002b7c: defffe04 addi sp,sp,-8 + 8002b80: df000115 stw fp,4(sp) + 8002b84: df000104 addi fp,sp,4 + 8002b88: 2005883a mov r2,r4 + 8002b8c: e0bfff05 stb r2,-4(fp) + if (en) + 8002b90: e0bfff03 ldbu r2,-4(fp) + 8002b94: 10000426 beq r2,zero,8002ba8 + IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(OUTPUT_PIO_BASE, 1<<5); + 8002b98: 00c00804 movi r3,32 + 8002b9c: 00861034 movhi r2,6208 + 8002ba0: 10cf1535 stwio r3,15444(r2) + else + IOWR_ALTERA_AVALON_PIO_SET_BITS(OUTPUT_PIO_BASE, 1<<5); +} + 8002ba4: 00000306 br 8002bb4 + IOWR_ALTERA_AVALON_PIO_SET_BITS(OUTPUT_PIO_BASE, 1<<5); + 8002ba8: 00c00804 movi r3,32 + 8002bac: 00861034 movhi r2,6208 + 8002bb0: 10cf1435 stwio r3,15440(r2) +} + 8002bb4: 0001883a nop + 8002bb8: e037883a mov sp,fp + 8002bbc: df000017 ldw fp,0(sp) + 8002bc0: dec00104 addi sp,sp,4 + 8002bc4: f800283a ret + +08002bc8 : + +void set_delay(alt_u8 master, alt_u16 value) +{ + 8002bc8: defffd04 addi sp,sp,-12 + 8002bcc: df000215 stw fp,8(sp) + 8002bd0: df000204 addi fp,sp,8 + 8002bd4: 2005883a mov r2,r4 + 8002bd8: 2807883a mov r3,r5 + 8002bdc: e0bfff05 stb r2,-4(fp) + 8002be0: 1805883a mov r2,r3 + 8002be4: e0bffe0d sth r2,-8(fp) + delays[master] = value; + 8002be8: e0bfff03 ldbu r2,-4(fp) + 8002bec: 1087883a add r3,r2,r2 + 8002bf0: d0a03e04 addi r2,gp,-32520 + 8002bf4: 1885883a add r2,r3,r2 + 8002bf8: e0fffe0b ldhu r3,-8(fp) + 8002bfc: 10c0000d sth r3,0(r2) + if (master == mastermode) + 8002c00: d0a03d83 ldbu r2,-32522(gp) + 8002c04: e0ffff03 ldbu r3,-4(fp) + 8002c08: 10803fcc andi r2,r2,255 + 8002c0c: 1880031e bne r3,r2,8002c1c + sensor_set_delay(SENSOR_INTERFACE_BASE, value); //update sensor setting only if right mode + 8002c10: e0fffe0b ldhu r3,-8(fp) + 8002c14: 00861034 movhi r2,6208 + 8002c18: 10cf552d sthio r3,15700(r2) +} + 8002c1c: 0001883a nop + 8002c20: e037883a mov sp,fp + 8002c24: df000017 ldw fp,0(sp) + 8002c28: dec00104 addi sp,sp,4 + 8002c2c: f800283a ret + +08002c30 <_getchar_r>: + 8002c30: 21400117 ldw r5,4(r4) + 8002c34: 8007adc1 jmpi 8007adc <_getc_r> + +08002c38 : + 8002c38: 00820174 movhi r2,2053 + 8002c3c: 1132af17 ldw r4,-13636(r2) + 8002c40: 21400117 ldw r5,4(r4) + 8002c44: 8007adc1 jmpi 8007adc <_getc_r> + +08002c48 <_printf_r>: + 8002c48: defffd04 addi sp,sp,-12 + 8002c4c: 2805883a mov r2,r5 + 8002c50: dfc00015 stw ra,0(sp) + 8002c54: d9800115 stw r6,4(sp) + 8002c58: d9c00215 stw r7,8(sp) + 8002c5c: 21400217 ldw r5,8(r4) + 8002c60: d9c00104 addi r7,sp,4 + 8002c64: 100d883a mov r6,r2 + 8002c68: 8002e440 call 8002e44 <___vfprintf_internal_r> + 8002c6c: dfc00017 ldw ra,0(sp) + 8002c70: dec00304 addi sp,sp,12 + 8002c74: f800283a ret + +08002c78 : + 8002c78: defffc04 addi sp,sp,-16 + 8002c7c: dfc00015 stw ra,0(sp) + 8002c80: d9400115 stw r5,4(sp) + 8002c84: d9800215 stw r6,8(sp) + 8002c88: d9c00315 stw r7,12(sp) + 8002c8c: 00820174 movhi r2,2053 + 8002c90: 10b2af17 ldw r2,-13636(r2) + 8002c94: 200b883a mov r5,r4 + 8002c98: d9800104 addi r6,sp,4 + 8002c9c: 11000217 ldw r4,8(r2) + 8002ca0: 8004fa40 call 8004fa4 <__vfprintf_internal> + 8002ca4: dfc00017 ldw ra,0(sp) + 8002ca8: dec00404 addi sp,sp,16 + 8002cac: f800283a ret + +08002cb0 <_putchar_r>: + 8002cb0: 21800217 ldw r6,8(r4) + 8002cb4: 80099101 jmpi 8009910 <_putc_r> + +08002cb8 : + 8002cb8: 00820174 movhi r2,2053 + 8002cbc: 10b2af17 ldw r2,-13636(r2) + 8002cc0: 200b883a mov r5,r4 + 8002cc4: 11800217 ldw r6,8(r2) + 8002cc8: 1009883a mov r4,r2 + 8002ccc: 80099101 jmpi 8009910 <_putc_r> + +08002cd0 <_puts_r>: + 8002cd0: defff504 addi sp,sp,-44 + 8002cd4: dc000815 stw r16,32(sp) + 8002cd8: 2021883a mov r16,r4 + 8002cdc: 2809883a mov r4,r5 + 8002ce0: dc400915 stw r17,36(sp) + 8002ce4: dfc00a15 stw ra,40(sp) + 8002ce8: 2823883a mov r17,r5 + 8002cec: 8002dac0 call 8002dac + 8002cf0: 11000044 addi r4,r2,1 + 8002cf4: d8800515 stw r2,20(sp) + 8002cf8: 00800044 movi r2,1 + 8002cfc: 00c20134 movhi r3,2052 + 8002d00: d8800715 stw r2,28(sp) + 8002d04: d8800404 addi r2,sp,16 + 8002d08: 18dd1604 addi r3,r3,29784 + 8002d0c: d8800115 stw r2,4(sp) + 8002d10: 00800084 movi r2,2 + 8002d14: dc400415 stw r17,16(sp) + 8002d18: d8c00615 stw r3,24(sp) + 8002d1c: d9000315 stw r4,12(sp) + 8002d20: d8800215 stw r2,8(sp) + 8002d24: 81400217 ldw r5,8(r16) + 8002d28: 80000226 beq r16,zero,8002d34 <_puts_r+0x64> + 8002d2c: 80800e17 ldw r2,56(r16) + 8002d30: 10001326 beq r2,zero,8002d80 <_puts_r+0xb0> + 8002d34: 2880030b ldhu r2,12(r5) + 8002d38: 10c8000c andi r3,r2,8192 + 8002d3c: 1800061e bne r3,zero,8002d58 <_puts_r+0x88> + 8002d40: 28c01917 ldw r3,100(r5) + 8002d44: 0137ffc4 movi r4,-8193 + 8002d48: 10880014 ori r2,r2,8192 + 8002d4c: 1906703a and r3,r3,r4 + 8002d50: 2880030d sth r2,12(r5) + 8002d54: 28c01915 stw r3,100(r5) + 8002d58: d9800104 addi r6,sp,4 + 8002d5c: 8009883a mov r4,r16 + 8002d60: 80074c00 call 80074c0 <__sfvwrite_r> + 8002d64: 10000b1e bne r2,zero,8002d94 <_puts_r+0xc4> + 8002d68: 00800284 movi r2,10 + 8002d6c: dfc00a17 ldw ra,40(sp) + 8002d70: dc400917 ldw r17,36(sp) + 8002d74: dc000817 ldw r16,32(sp) + 8002d78: dec00b04 addi sp,sp,44 + 8002d7c: f800283a ret + 8002d80: 8009883a mov r4,r16 + 8002d84: d9400015 stw r5,0(sp) + 8002d88: 80070600 call 8007060 <__sinit> + 8002d8c: d9400017 ldw r5,0(sp) + 8002d90: 003fe806 br 8002d34 <_puts_r+0x64> + 8002d94: 00bfffc4 movi r2,-1 + 8002d98: 003ff406 br 8002d6c <_puts_r+0x9c> + +08002d9c : + 8002d9c: 00820174 movhi r2,2053 + 8002da0: 200b883a mov r5,r4 + 8002da4: 1132af17 ldw r4,-13636(r2) + 8002da8: 8002cd01 jmpi 8002cd0 <_puts_r> + +08002dac : + 8002dac: 208000cc andi r2,r4,3 + 8002db0: 10002026 beq r2,zero,8002e34 + 8002db4: 20800007 ldb r2,0(r4) + 8002db8: 10002026 beq r2,zero,8002e3c + 8002dbc: 2005883a mov r2,r4 + 8002dc0: 00000206 br 8002dcc + 8002dc4: 10c00007 ldb r3,0(r2) + 8002dc8: 18001826 beq r3,zero,8002e2c + 8002dcc: 10800044 addi r2,r2,1 + 8002dd0: 10c000cc andi r3,r2,3 + 8002dd4: 183ffb1e bne r3,zero,8002dc4 + 8002dd8: 11400017 ldw r5,0(r2) + 8002ddc: 01ffbff4 movhi r7,65279 + 8002de0: 39ffbfc4 addi r7,r7,-257 + 8002de4: 29c7883a add r3,r5,r7 + 8002de8: 01a02074 movhi r6,32897 + 8002dec: 014a303a nor r5,zero,r5 + 8002df0: 1946703a and r3,r3,r5 + 8002df4: 31a02004 addi r6,r6,-32640 + 8002df8: 1986703a and r3,r3,r6 + 8002dfc: 1800091e bne r3,zero,8002e24 + 8002e00: 10800104 addi r2,r2,4 + 8002e04: 11400017 ldw r5,0(r2) + 8002e08: 29c7883a add r3,r5,r7 + 8002e0c: 014a303a nor r5,zero,r5 + 8002e10: 1946703a and r3,r3,r5 + 8002e14: 1986703a and r3,r3,r6 + 8002e18: 183ff926 beq r3,zero,8002e00 + 8002e1c: 00000106 br 8002e24 + 8002e20: 10800044 addi r2,r2,1 + 8002e24: 10c00007 ldb r3,0(r2) + 8002e28: 183ffd1e bne r3,zero,8002e20 + 8002e2c: 1105c83a sub r2,r2,r4 + 8002e30: f800283a ret + 8002e34: 2005883a mov r2,r4 + 8002e38: 003fe706 br 8002dd8 + 8002e3c: 0005883a mov r2,zero + 8002e40: f800283a ret + +08002e44 <___vfprintf_internal_r>: + 8002e44: deffbd04 addi sp,sp,-268 + 8002e48: dfc04215 stw ra,264(sp) + 8002e4c: dd003d15 stw r20,244(sp) + 8002e50: dcc03c15 stw r19,240(sp) + 8002e54: dc003915 stw r16,228(sp) + 8002e58: d9000515 stw r4,20(sp) + 8002e5c: 2021883a mov r16,r4 + 8002e60: 2827883a mov r19,r5 + 8002e64: 3029883a mov r20,r6 + 8002e68: d9c00615 stw r7,24(sp) + 8002e6c: df004115 stw fp,260(sp) + 8002e70: ddc04015 stw r23,256(sp) + 8002e74: dd803f15 stw r22,252(sp) + 8002e78: dd403e15 stw r21,248(sp) + 8002e7c: dc803b15 stw r18,236(sp) + 8002e80: dc403a15 stw r17,232(sp) + 8002e84: 8007bf00 call 8007bf0 <_localeconv_r> + 8002e88: 10800017 ldw r2,0(r2) + 8002e8c: 1009883a mov r4,r2 + 8002e90: d8800d15 stw r2,52(sp) + 8002e94: 8002dac0 call 8002dac + 8002e98: d8800b15 stw r2,44(sp) + 8002e9c: 80000226 beq r16,zero,8002ea8 <___vfprintf_internal_r+0x64> + 8002ea0: 80800e17 ldw r2,56(r16) + 8002ea4: 1002da26 beq r2,zero,8003a10 <___vfprintf_internal_r+0xbcc> + 8002ea8: 9880030b ldhu r2,12(r19) + 8002eac: 10c8000c andi r3,r2,8192 + 8002eb0: 1800061e bne r3,zero,8002ecc <___vfprintf_internal_r+0x88> + 8002eb4: 98c01917 ldw r3,100(r19) + 8002eb8: 0137ffc4 movi r4,-8193 + 8002ebc: 10880014 ori r2,r2,8192 + 8002ec0: 1906703a and r3,r3,r4 + 8002ec4: 9880030d sth r2,12(r19) + 8002ec8: 98c01915 stw r3,100(r19) + 8002ecc: 10c0020c andi r3,r2,8 + 8002ed0: 18009a26 beq r3,zero,800313c <___vfprintf_internal_r+0x2f8> + 8002ed4: 98c00417 ldw r3,16(r19) + 8002ed8: 18009826 beq r3,zero,800313c <___vfprintf_internal_r+0x2f8> + 8002edc: 1080068c andi r2,r2,26 + 8002ee0: 10800298 cmpnei r2,r2,10 + 8002ee4: 10009d26 beq r2,zero,800315c <___vfprintf_internal_r+0x318> + 8002ee8: ddc02904 addi r23,sp,164 + 8002eec: ddc01c15 stw r23,112(sp) + 8002ef0: d8001e15 stw zero,120(sp) + 8002ef4: d8001d15 stw zero,116(sp) + 8002ef8: d8000815 stw zero,32(sp) + 8002efc: d8000915 stw zero,36(sp) + 8002f00: d8000a15 stw zero,40(sp) + 8002f04: b811883a mov r8,r23 + 8002f08: d8000c15 stw zero,48(sp) + 8002f0c: d8001115 stw zero,68(sp) + 8002f10: d8000415 stw zero,16(sp) + 8002f14: a02d883a mov r22,r20 + 8002f18: b0800007 ldb r2,0(r22) + 8002f1c: 1000a226 beq r2,zero,80031a8 <___vfprintf_internal_r+0x364> + 8002f20: 10800960 cmpeqi r2,r2,37 + 8002f24: 10052e1e bne r2,zero,80043e0 <___vfprintf_internal_r+0x159c> + 8002f28: b021883a mov r16,r22 + 8002f2c: 00000206 br 8002f38 <___vfprintf_internal_r+0xf4> + 8002f30: 18009326 beq r3,zero,8003180 <___vfprintf_internal_r+0x33c> + 8002f34: 9021883a mov r16,r18 + 8002f38: 80800047 ldb r2,1(r16) + 8002f3c: 84800044 addi r18,r16,1 + 8002f40: 10c00958 cmpnei r3,r2,37 + 8002f44: 103ffa1e bne r2,zero,8002f30 <___vfprintf_internal_r+0xec> + 8002f48: 95a3c83a sub r17,r18,r22 + 8002f4c: 88009626 beq r17,zero,80031a8 <___vfprintf_internal_r+0x364> + 8002f50: d8c01e17 ldw r3,120(sp) + 8002f54: d8801d17 ldw r2,116(sp) + 8002f58: 45800015 stw r22,0(r8) + 8002f5c: 1c47883a add r3,r3,r17 + 8002f60: 10800044 addi r2,r2,1 + 8002f64: d8801d15 stw r2,116(sp) + 8002f68: 44400115 stw r17,4(r8) + 8002f6c: d8c01e15 stw r3,120(sp) + 8002f70: 10800208 cmpgei r2,r2,8 + 8002f74: 1000851e bne r2,zero,800318c <___vfprintf_internal_r+0x348> + 8002f78: 42000204 addi r8,r8,8 + 8002f7c: d8c00417 ldw r3,16(sp) + 8002f80: 80800047 ldb r2,1(r16) + 8002f84: 1c47883a add r3,r3,r17 + 8002f88: d8c00415 stw r3,16(sp) + 8002f8c: 10008626 beq r2,zero,80031a8 <___vfprintf_internal_r+0x364> + 8002f90: 92800047 ldb r10,1(r18) + 8002f94: 95800044 addi r22,r18,1 + 8002f98: d8001545 stb zero,85(sp) + 8002f9c: 0009883a mov r4,zero + 8002fa0: 000b883a mov r5,zero + 8002fa4: 02ffffc4 movi r11,-1 + 8002fa8: 0023883a mov r17,zero + 8002fac: 0019883a mov r12,zero + 8002fb0: b5800044 addi r22,r22,1 + 8002fb4: 5039883a mov fp,r10 + 8002fb8: e0bff804 addi r2,fp,-32 + 8002fbc: 10c01668 cmpgeui r3,r2,89 + 8002fc0: 18009b1e bne r3,zero,8003230 <___vfprintf_internal_r+0x3ec> + 8002fc4: 100490ba slli r2,r2,2 + 8002fc8: 00c20034 movhi r3,2048 + 8002fcc: 10c7883a add r3,r2,r3 + 8002fd0: 188bf617 ldw r2,12248(r3) + 8002fd4: 1000683a jmp r2 + 8002fd8: 08003300 call 800330 + 8002fdc: 08003230 cmpltui zero,at,200 + 8002fe0: 08003230 cmpltui zero,at,200 + 8002fe4: 080032f4 orhi zero,at,203 + 8002fe8: 08003230 cmpltui zero,at,200 + 8002fec: 08003230 cmpltui zero,at,200 + 8002ff0: 08003230 cmpltui zero,at,200 + 8002ff4: 08003230 cmpltui zero,at,200 + 8002ff8: 08003230 cmpltui zero,at,200 + 8002ffc: 08003230 cmpltui zero,at,200 + 8003000: 080032cc andi zero,at,203 + 8003004: 080032bc xorhi zero,at,202 + 8003008: 08003230 cmpltui zero,at,200 + 800300c: 080032a4 muli zero,at,202 + 8003010: 08003260 cmpeqi zero,at,201 + 8003014: 08003230 cmpltui zero,at,200 + 8003018: 08003254 ori zero,at,201 + 800301c: 08003200 call 800320 + 8003020: 08003200 call 800320 + 8003024: 08003200 call 800320 + 8003028: 08003200 call 800320 + 800302c: 08003200 call 800320 + 8003030: 08003200 call 800320 + 8003034: 08003200 call 800320 + 8003038: 08003200 call 800320 + 800303c: 08003200 call 800320 + 8003040: 08003230 cmpltui zero,at,200 + 8003044: 08003230 cmpltui zero,at,200 + 8003048: 08003230 cmpltui zero,at,200 + 800304c: 08003230 cmpltui zero,at,200 + 8003050: 08003230 cmpltui zero,at,200 + 8003054: 08003230 cmpltui zero,at,200 + 8003058: 08003230 cmpltui zero,at,200 + 800305c: 08003230 cmpltui zero,at,200 + 8003060: 08003230 cmpltui zero,at,200 + 8003064: 08003230 cmpltui zero,at,200 + 8003068: 08003814 ori zero,at,224 + 800306c: 08003734 orhi zero,at,220 + 8003070: 08003230 cmpltui zero,at,200 + 8003074: 08003734 orhi zero,at,220 + 8003078: 08003230 cmpltui zero,at,200 + 800307c: 08003230 cmpltui zero,at,200 + 8003080: 08003230 cmpltui zero,at,200 + 8003084: 08003230 cmpltui zero,at,200 + 8003088: 08003728 cmpgeui zero,at,220 + 800308c: 08003230 cmpltui zero,at,200 + 8003090: 08003230 cmpltui zero,at,200 + 8003094: 080036f4 orhi zero,at,219 + 8003098: 08003230 cmpltui zero,at,200 + 800309c: 08003230 cmpltui zero,at,200 + 80030a0: 08003230 cmpltui zero,at,200 + 80030a4: 08003230 cmpltui zero,at,200 + 80030a8: 08003230 cmpltui zero,at,200 + 80030ac: 08003934 orhi zero,at,228 + 80030b0: 08003230 cmpltui zero,at,200 + 80030b4: 08003230 cmpltui zero,at,200 + 80030b8: 080038ec andhi zero,at,227 + 80030bc: 08003230 cmpltui zero,at,200 + 80030c0: 08003230 cmpltui zero,at,200 + 80030c4: 08003230 cmpltui zero,at,200 + 80030c8: 08003230 cmpltui zero,at,200 + 80030cc: 08003230 cmpltui zero,at,200 + 80030d0: 08003230 cmpltui zero,at,200 + 80030d4: 08003230 cmpltui zero,at,200 + 80030d8: 08003230 cmpltui zero,at,200 + 80030dc: 08003230 cmpltui zero,at,200 + 80030e0: 08003230 cmpltui zero,at,200 + 80030e4: 08003484 addi zero,at,210 + 80030e8: 08003410 cmplti zero,at,208 + 80030ec: 08003734 orhi zero,at,220 + 80030f0: 08003734 orhi zero,at,220 + 80030f4: 08003734 orhi zero,at,220 + 80030f8: 08003a04 addi zero,at,232 + 80030fc: 08003410 cmplti zero,at,208 + 8003100: 08003230 cmpltui zero,at,200 + 8003104: 08003230 cmpltui zero,at,200 + 8003108: 080039f0 cmpltui zero,at,231 + 800310c: 08003230 cmpltui zero,at,200 + 8003110: 080036b4 orhi zero,at,218 + 8003114: 08003674 orhi zero,at,217 + 8003118: 08003974 orhi zero,at,229 + 800311c: 08003968 cmpgeui zero,at,229 + 8003120: 08003230 cmpltui zero,at,200 + 8003124: 080033b4 orhi zero,at,206 + 8003128: 08003230 cmpltui zero,at,200 + 800312c: 08003374 orhi zero,at,205 + 8003130: 08003230 cmpltui zero,at,200 + 8003134: 08003230 cmpltui zero,at,200 + 8003138: 0800332c andhi zero,at,204 + 800313c: d9000517 ldw r4,20(sp) + 8003140: 980b883a mov r5,r19 + 8003144: 800507c0 call 800507c <__swsetup_r> + 8003148: 10074c1e bne r2,zero,8004e7c <___vfprintf_internal_r+0x2038> + 800314c: 9880030b ldhu r2,12(r19) + 8003150: 1080068c andi r2,r2,26 + 8003154: 10800298 cmpnei r2,r2,10 + 8003158: 103f631e bne r2,zero,8002ee8 <___vfprintf_internal_r+0xa4> + 800315c: 9880038f ldh r2,14(r19) + 8003160: 103f6116 blt r2,zero,8002ee8 <___vfprintf_internal_r+0xa4> + 8003164: d9c00617 ldw r7,24(sp) + 8003168: d9000517 ldw r4,20(sp) + 800316c: a00d883a mov r6,r20 + 8003170: 980b883a mov r5,r19 + 8003174: 8004fbc0 call 8004fbc <__sbprintf> + 8003178: d8800415 stw r2,16(sp) + 800317c: 00001306 br 80031cc <___vfprintf_internal_r+0x388> + 8003180: 95a3c83a sub r17,r18,r22 + 8003184: 883f8226 beq r17,zero,8002f90 <___vfprintf_internal_r+0x14c> + 8003188: 003f7106 br 8002f50 <___vfprintf_internal_r+0x10c> + 800318c: d9000517 ldw r4,20(sp) + 8003190: d9801c04 addi r6,sp,112 + 8003194: 980b883a mov r5,r19 + 8003198: 800a3f80 call 800a3f8 <__sprint_r> + 800319c: 1000081e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 80031a0: b811883a mov r8,r23 + 80031a4: 003f7506 br 8002f7c <___vfprintf_internal_r+0x138> + 80031a8: d8801e17 ldw r2,120(sp) + 80031ac: 10000426 beq r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 80031b0: d9000517 ldw r4,20(sp) + 80031b4: d9801c04 addi r6,sp,112 + 80031b8: 980b883a mov r5,r19 + 80031bc: 800a3f80 call 800a3f8 <__sprint_r> + 80031c0: 9880030b ldhu r2,12(r19) + 80031c4: 1080100c andi r2,r2,64 + 80031c8: 10072c1e bne r2,zero,8004e7c <___vfprintf_internal_r+0x2038> + 80031cc: d8800417 ldw r2,16(sp) + 80031d0: dfc04217 ldw ra,264(sp) + 80031d4: df004117 ldw fp,260(sp) + 80031d8: ddc04017 ldw r23,256(sp) + 80031dc: dd803f17 ldw r22,252(sp) + 80031e0: dd403e17 ldw r21,248(sp) + 80031e4: dd003d17 ldw r20,244(sp) + 80031e8: dcc03c17 ldw r19,240(sp) + 80031ec: dc803b17 ldw r18,236(sp) + 80031f0: dc403a17 ldw r17,232(sp) + 80031f4: dc003917 ldw r16,228(sp) + 80031f8: dec04304 addi sp,sp,268 + 80031fc: f800283a ret + 8003200: 0023883a mov r17,zero + 8003204: e0bff404 addi r2,fp,-48 + 8003208: b5800044 addi r22,r22,1 + 800320c: 8c4002a4 muli r17,r17,10 + 8003210: b73fffc7 ldb fp,-1(r22) + 8003214: 1463883a add r17,r2,r17 + 8003218: e0bff404 addi r2,fp,-48 + 800321c: 10c002b0 cmpltui r3,r2,10 + 8003220: 183ff91e bne r3,zero,8003208 <___vfprintf_internal_r+0x3c4> + 8003224: e0bff804 addi r2,fp,-32 + 8003228: 10c01668 cmpgeui r3,r2,89 + 800322c: 183f6526 beq r3,zero,8002fc4 <___vfprintf_internal_r+0x180> + 8003230: 21003fcc andi r4,r4,255 + 8003234: 20066d1e bne r4,zero,8004bec <___vfprintf_internal_r+0x1da8> + 8003238: e03fdb26 beq fp,zero,80031a8 <___vfprintf_internal_r+0x364> + 800323c: df001f05 stb fp,124(sp) + 8003240: d8001545 stb zero,85(sp) + 8003244: 05400044 movi r21,1 + 8003248: 05000044 movi r20,1 + 800324c: dc001f04 addi r16,sp,124 + 8003250: 00009506 br 80034a8 <___vfprintf_internal_r+0x664> + 8003254: 63002014 ori r12,r12,128 + 8003258: b2800007 ldb r10,0(r22) + 800325c: 003f5406 br 8002fb0 <___vfprintf_internal_r+0x16c> + 8003260: b7000007 ldb fp,0(r22) + 8003264: b0c00044 addi r3,r22,1 + 8003268: e0800aa0 cmpeqi r2,fp,42 + 800326c: 1007411e bne r2,zero,8004f74 <___vfprintf_internal_r+0x2130> + 8003270: e0bff404 addi r2,fp,-48 + 8003274: 118002b0 cmpltui r6,r2,10 + 8003278: 182d883a mov r22,r3 + 800327c: 0017883a mov r11,zero + 8003280: 303f4d26 beq r6,zero,8002fb8 <___vfprintf_internal_r+0x174> + 8003284: b5800044 addi r22,r22,1 + 8003288: 5ac002a4 muli r11,r11,10 + 800328c: b73fffc7 ldb fp,-1(r22) + 8003290: 5897883a add r11,r11,r2 + 8003294: e0bff404 addi r2,fp,-48 + 8003298: 10c002b0 cmpltui r3,r2,10 + 800329c: 183ff91e bne r3,zero,8003284 <___vfprintf_internal_r+0x440> + 80032a0: 003f4506 br 8002fb8 <___vfprintf_internal_r+0x174> + 80032a4: b7000003 ldbu fp,0(r22) + 80032a8: e2803fcc andi r10,fp,255 + 80032ac: 5280201c xori r10,r10,128 + 80032b0: 63000114 ori r12,r12,4 + 80032b4: 52bfe004 addi r10,r10,-128 + 80032b8: 003f3d06 br 8002fb0 <___vfprintf_internal_r+0x16c> + 80032bc: 01000044 movi r4,1 + 80032c0: 01400ac4 movi r5,43 + 80032c4: b2800007 ldb r10,0(r22) + 80032c8: 003f3906 br 8002fb0 <___vfprintf_internal_r+0x16c> + 80032cc: d8800617 ldw r2,24(sp) + 80032d0: b7000003 ldbu fp,0(r22) + 80032d4: 14400017 ldw r17,0(r2) + 80032d8: 10800104 addi r2,r2,4 + 80032dc: 8804d716 blt r17,zero,800463c <___vfprintf_internal_r+0x17f8> + 80032e0: d8800615 stw r2,24(sp) + 80032e4: e2803fcc andi r10,fp,255 + 80032e8: 5280201c xori r10,r10,128 + 80032ec: 52bfe004 addi r10,r10,-128 + 80032f0: 003f2f06 br 8002fb0 <___vfprintf_internal_r+0x16c> + 80032f4: 63000054 ori r12,r12,1 + 80032f8: b2800007 ldb r10,0(r22) + 80032fc: 003f2c06 br 8002fb0 <___vfprintf_internal_r+0x16c> + 8003300: 28803fcc andi r2,r5,255 + 8003304: 1080201c xori r2,r2,128 + 8003308: 10bfe004 addi r2,r2,-128 + 800330c: b7000003 ldbu fp,0(r22) + 8003310: 103ff41e bne r2,zero,80032e4 <___vfprintf_internal_r+0x4a0> + 8003314: e2803fcc andi r10,fp,255 + 8003318: 5280201c xori r10,r10,128 + 800331c: 01000044 movi r4,1 + 8003320: 01400804 movi r5,32 + 8003324: 52bfe004 addi r10,r10,-128 + 8003328: 003f2106 br 8002fb0 <___vfprintf_internal_r+0x16c> + 800332c: 21003fcc andi r4,r4,255 + 8003330: 2006b31e bne r4,zero,8004e00 <___vfprintf_internal_r+0x1fbc> + 8003334: 00820134 movhi r2,2052 + 8003338: 109d2004 addi r2,r2,29824 + 800333c: d8800c15 stw r2,48(sp) + 8003340: 6080080c andi r2,r12,32 + 8003344: 10017026 beq r2,zero,8003908 <___vfprintf_internal_r+0xac4> + 8003348: d8800617 ldw r2,24(sp) + 800334c: 15400017 ldw r21,0(r2) + 8003350: 15000117 ldw r20,4(r2) + 8003354: 10800204 addi r2,r2,8 + 8003358: d8800615 stw r2,24(sp) + 800335c: 6080004c andi r2,r12,1 + 8003360: 10000226 beq r2,zero,800336c <___vfprintf_internal_r+0x528> + 8003364: ad04b03a or r2,r21,r20 + 8003368: 1004a71e bne r2,zero,8004608 <___vfprintf_internal_r+0x17c4> + 800336c: 00800084 movi r2,2 + 8003370: 00018f06 br 80039b0 <___vfprintf_internal_r+0xb6c> + 8003374: 21003fcc andi r4,r4,255 + 8003378: 20069f1e bne r4,zero,8004df8 <___vfprintf_internal_r+0x1fb4> + 800337c: 6080080c andi r2,r12,32 + 8003380: 1001b41e bne r2,zero,8003a54 <___vfprintf_internal_r+0xc10> + 8003384: d8800617 ldw r2,24(sp) + 8003388: 60c0040c andi r3,r12,16 + 800338c: 15400017 ldw r21,0(r2) + 8003390: 10800104 addi r2,r2,4 + 8003394: 18016e1e bne r3,zero,8003950 <___vfprintf_internal_r+0xb0c> + 8003398: 60c0100c andi r3,r12,64 + 800339c: 18059f26 beq r3,zero,8004a1c <___vfprintf_internal_r+0x1bd8> + 80033a0: d8800615 stw r2,24(sp) + 80033a4: ad7fffcc andi r21,r21,65535 + 80033a8: 0029883a mov r20,zero + 80033ac: 00800044 movi r2,1 + 80033b0: 00017f06 br 80039b0 <___vfprintf_internal_r+0xb6c> + 80033b4: d8800617 ldw r2,24(sp) + 80033b8: d8001545 stb zero,85(sp) + 80033bc: 14000017 ldw r16,0(r2) + 80033c0: 14800104 addi r18,r2,4 + 80033c4: 8004c726 beq r16,zero,80046e4 <___vfprintf_internal_r+0x18a0> + 80033c8: da000e15 stw r8,56(sp) + 80033cc: db000715 stw r12,28(sp) + 80033d0: 58bfffe0 cmpeqi r2,r11,-1 + 80033d4: 1005691e bne r2,zero,800497c <___vfprintf_internal_r+0x1b38> + 80033d8: 580d883a mov r6,r11 + 80033dc: 000b883a mov r5,zero + 80033e0: 8009883a mov r4,r16 + 80033e4: dac00615 stw r11,24(sp) + 80033e8: 80085d00 call 80085d0 + 80033ec: dac00617 ldw r11,24(sp) + 80033f0: db000717 ldw r12,28(sp) + 80033f4: da000e17 ldw r8,56(sp) + 80033f8: 10066726 beq r2,zero,8004d98 <___vfprintf_internal_r+0x1f54> + 80033fc: 1429c83a sub r20,r2,r16 + 8003400: a02b883a mov r21,r20 + 8003404: a005f716 blt r20,zero,8004be4 <___vfprintf_internal_r+0x1da0> + 8003408: dc800615 stw r18,24(sp) + 800340c: 00002606 br 80034a8 <___vfprintf_internal_r+0x664> + 8003410: 21003fcc andi r4,r4,255 + 8003414: 2006761e bne r4,zero,8004df0 <___vfprintf_internal_r+0x1fac> + 8003418: 6080080c andi r2,r12,32 + 800341c: 10017f1e bne r2,zero,8003a1c <___vfprintf_internal_r+0xbd8> + 8003420: d8800617 ldw r2,24(sp) + 8003424: 60c0040c andi r3,r12,16 + 8003428: 10800104 addi r2,r2,4 + 800342c: 1801001e bne r3,zero,8003830 <___vfprintf_internal_r+0x9ec> + 8003430: 60c0100c andi r3,r12,64 + 8003434: 1800fe26 beq r3,zero,8003830 <___vfprintf_internal_r+0x9ec> + 8003438: d8c00617 ldw r3,24(sp) + 800343c: d8800615 stw r2,24(sp) + 8003440: 1d40000f ldh r21,0(r3) + 8003444: a829d7fa srai r20,r21,31 + 8003448: a005883a mov r2,r20 + 800344c: 1000fe16 blt r2,zero,8003848 <___vfprintf_internal_r+0xa04> + 8003450: 58bfffd8 cmpnei r2,r11,-1 + 8003454: db401543 ldbu r13,85(sp) + 8003458: 10018526 beq r2,zero,8003a70 <___vfprintf_internal_r+0xc2c> + 800345c: 00ffdfc4 movi r3,-129 + 8003460: ad04b03a or r2,r21,r20 + 8003464: 60d8703a and r12,r12,r3 + 8003468: 1001811e bne r2,zero,8003a70 <___vfprintf_internal_r+0xc2c> + 800346c: 5801831e bne r11,zero,8003a7c <___vfprintf_internal_r+0xc38> + 8003470: 6025883a mov r18,r12 + 8003474: 0017883a mov r11,zero + 8003478: 0029883a mov r20,zero + 800347c: b821883a mov r16,r23 + 8003480: 00018306 br 8003a90 <___vfprintf_internal_r+0xc4c> + 8003484: d8c00617 ldw r3,24(sp) + 8003488: d8001545 stb zero,85(sp) + 800348c: 05400044 movi r21,1 + 8003490: 18800017 ldw r2,0(r3) + 8003494: 18c00104 addi r3,r3,4 + 8003498: d8c00615 stw r3,24(sp) + 800349c: d8801f05 stb r2,124(sp) + 80034a0: 05000044 movi r20,1 + 80034a4: dc001f04 addi r16,sp,124 + 80034a8: 6025883a mov r18,r12 + 80034ac: 0017883a mov r11,zero + 80034b0: d8000715 stw zero,28(sp) + 80034b4: 9380008c andi r14,r18,2 + 80034b8: 70000126 beq r14,zero,80034c0 <___vfprintf_internal_r+0x67c> + 80034bc: ad400084 addi r21,r21,2 + 80034c0: 9340210c andi r13,r18,132 + 80034c4: d8c01e17 ldw r3,120(sp) + 80034c8: 6800021e bne r13,zero,80034d4 <___vfprintf_internal_r+0x690> + 80034cc: 8d4fc83a sub r7,r17,r21 + 80034d0: 01c2ce16 blt zero,r7,800400c <___vfprintf_internal_r+0x11c8> + 80034d4: d8801547 ldb r2,85(sp) + 80034d8: 10000c26 beq r2,zero,800350c <___vfprintf_internal_r+0x6c8> + 80034dc: d8801d17 ldw r2,116(sp) + 80034e0: d9001544 addi r4,sp,85 + 80034e4: 18c00044 addi r3,r3,1 + 80034e8: 10800044 addi r2,r2,1 + 80034ec: 41000015 stw r4,0(r8) + 80034f0: 01000044 movi r4,1 + 80034f4: d8801d15 stw r2,116(sp) + 80034f8: 41000115 stw r4,4(r8) + 80034fc: d8c01e15 stw r3,120(sp) + 8003500: 10800208 cmpgei r2,r2,8 + 8003504: 1002fb1e bne r2,zero,80040f4 <___vfprintf_internal_r+0x12b0> + 8003508: 42000204 addi r8,r8,8 + 800350c: 70000c26 beq r14,zero,8003540 <___vfprintf_internal_r+0x6fc> + 8003510: d8801d17 ldw r2,116(sp) + 8003514: d9001584 addi r4,sp,86 + 8003518: 18c00084 addi r3,r3,2 + 800351c: 10800044 addi r2,r2,1 + 8003520: 41000015 stw r4,0(r8) + 8003524: 01000084 movi r4,2 + 8003528: d8801d15 stw r2,116(sp) + 800352c: 41000115 stw r4,4(r8) + 8003530: d8c01e15 stw r3,120(sp) + 8003534: 10800208 cmpgei r2,r2,8 + 8003538: 1002fc1e bne r2,zero,800412c <___vfprintf_internal_r+0x12e8> + 800353c: 42000204 addi r8,r8,8 + 8003540: 6b402018 cmpnei r13,r13,128 + 8003544: 6801cf26 beq r13,zero,8003c84 <___vfprintf_internal_r+0xe40> + 8003548: 5d0fc83a sub r7,r11,r20 + 800354c: 01c20616 blt zero,r7,8003d68 <___vfprintf_internal_r+0xf24> + 8003550: 9080400c andi r2,r18,256 + 8003554: 10017c1e bne r2,zero,8003b48 <___vfprintf_internal_r+0xd04> + 8003558: d8801d17 ldw r2,116(sp) + 800355c: 1d07883a add r3,r3,r20 + 8003560: 44000015 stw r16,0(r8) + 8003564: 10800044 addi r2,r2,1 + 8003568: d8801d15 stw r2,116(sp) + 800356c: 45000115 stw r20,4(r8) + 8003570: d8c01e15 stw r3,120(sp) + 8003574: 10800208 cmpgei r2,r2,8 + 8003578: 1002571e bne r2,zero,8003ed8 <___vfprintf_internal_r+0x1094> + 800357c: 42000204 addi r8,r8,8 + 8003580: 9480010c andi r18,r18,4 + 8003584: 90000226 beq r18,zero,8003590 <___vfprintf_internal_r+0x74c> + 8003588: 8d61c83a sub r16,r17,r21 + 800358c: 04000916 blt zero,r16,80035b4 <___vfprintf_internal_r+0x770> + 8003590: 8d40010e bge r17,r21,8003598 <___vfprintf_internal_r+0x754> + 8003594: a823883a mov r17,r21 + 8003598: d8800417 ldw r2,16(sp) + 800359c: 1445883a add r2,r2,r17 + 80035a0: d8800415 stw r2,16(sp) + 80035a4: 1802241e bne r3,zero,8003e38 <___vfprintf_internal_r+0xff4> + 80035a8: d8001d15 stw zero,116(sp) + 80035ac: b811883a mov r8,r23 + 80035b0: 003e5906 br 8002f18 <___vfprintf_internal_r+0xd4> + 80035b4: 03020134 movhi r12,2052 + 80035b8: 81000450 cmplti r4,r16,17 + 80035bc: 631d2b84 addi r12,r12,29870 + 80035c0: d8801d17 ldw r2,116(sp) + 80035c4: 20001c1e bne r4,zero,8003638 <___vfprintf_internal_r+0x7f4> + 80035c8: 04800404 movi r18,16 + 80035cc: dd000517 ldw r20,20(sp) + 80035d0: 6039883a mov fp,r12 + 80035d4: 00000406 br 80035e8 <___vfprintf_internal_r+0x7a4> + 80035d8: 843ffc04 addi r16,r16,-16 + 80035dc: 81000448 cmpgei r4,r16,17 + 80035e0: 42000204 addi r8,r8,8 + 80035e4: 20001326 beq r4,zero,8003634 <___vfprintf_internal_r+0x7f0> + 80035e8: 10800044 addi r2,r2,1 + 80035ec: 18c00404 addi r3,r3,16 + 80035f0: 47000015 stw fp,0(r8) + 80035f4: 44800115 stw r18,4(r8) + 80035f8: d8c01e15 stw r3,120(sp) + 80035fc: d8801d15 stw r2,116(sp) + 8003600: 11000208 cmpgei r4,r2,8 + 8003604: 203ff426 beq r4,zero,80035d8 <___vfprintf_internal_r+0x794> + 8003608: d9801c04 addi r6,sp,112 + 800360c: 980b883a mov r5,r19 + 8003610: a009883a mov r4,r20 + 8003614: 800a3f80 call 800a3f8 <__sprint_r> + 8003618: 103ee91e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 800361c: 843ffc04 addi r16,r16,-16 + 8003620: 81000448 cmpgei r4,r16,17 + 8003624: d8c01e17 ldw r3,120(sp) + 8003628: d8801d17 ldw r2,116(sp) + 800362c: b811883a mov r8,r23 + 8003630: 203fed1e bne r4,zero,80035e8 <___vfprintf_internal_r+0x7a4> + 8003634: e019883a mov r12,fp + 8003638: 10800044 addi r2,r2,1 + 800363c: 1c07883a add r3,r3,r16 + 8003640: d8801d15 stw r2,116(sp) + 8003644: 43000015 stw r12,0(r8) + 8003648: 44000115 stw r16,4(r8) + 800364c: d8c01e15 stw r3,120(sp) + 8003650: 10800210 cmplti r2,r2,8 + 8003654: 103fce1e bne r2,zero,8003590 <___vfprintf_internal_r+0x74c> + 8003658: d9000517 ldw r4,20(sp) + 800365c: d9801c04 addi r6,sp,112 + 8003660: 980b883a mov r5,r19 + 8003664: 800a3f80 call 800a3f8 <__sprint_r> + 8003668: 103ed51e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 800366c: d8c01e17 ldw r3,120(sp) + 8003670: 003fc706 br 8003590 <___vfprintf_internal_r+0x74c> + 8003674: 21003fcc andi r4,r4,255 + 8003678: 2005d91e bne r4,zero,8004de0 <___vfprintf_internal_r+0x1f9c> + 800367c: 6080080c andi r2,r12,32 + 8003680: 1000ed1e bne r2,zero,8003a38 <___vfprintf_internal_r+0xbf4> + 8003684: d8800617 ldw r2,24(sp) + 8003688: 60c0040c andi r3,r12,16 + 800368c: 15400017 ldw r21,0(r2) + 8003690: 10800104 addi r2,r2,4 + 8003694: 18001e1e bne r3,zero,8003710 <___vfprintf_internal_r+0x8cc> + 8003698: 60c0100c andi r3,r12,64 + 800369c: 1804db26 beq r3,zero,8004a0c <___vfprintf_internal_r+0x1bc8> + 80036a0: d8800615 stw r2,24(sp) + 80036a4: ad7fffcc andi r21,r21,65535 + 80036a8: 0029883a mov r20,zero + 80036ac: 0005883a mov r2,zero + 80036b0: 0000bf06 br 80039b0 <___vfprintf_internal_r+0xb6c> + 80036b4: 21003fcc andi r4,r4,255 + 80036b8: 2005cb1e bne r4,zero,8004de8 <___vfprintf_internal_r+0x1fa4> + 80036bc: d9000617 ldw r4,24(sp) + 80036c0: 6080080c andi r2,r12,32 + 80036c4: 20c00104 addi r3,r4,4 + 80036c8: 1003d51e bne r2,zero,8004620 <___vfprintf_internal_r+0x17dc> + 80036cc: 6080040c andi r2,r12,16 + 80036d0: 1004301e bne r2,zero,8004794 <___vfprintf_internal_r+0x1950> + 80036d4: 6300100c andi r12,r12,64 + 80036d8: 60042e26 beq r12,zero,8004794 <___vfprintf_internal_r+0x1950> + 80036dc: d8800617 ldw r2,24(sp) + 80036e0: d8c00615 stw r3,24(sp) + 80036e4: d8c00417 ldw r3,16(sp) + 80036e8: 10800017 ldw r2,0(r2) + 80036ec: 10c0000d sth r3,0(r2) + 80036f0: 003e0906 br 8002f18 <___vfprintf_internal_r+0xd4> + 80036f4: 21003fcc andi r4,r4,255 + 80036f8: 2005c31e bne r4,zero,8004e08 <___vfprintf_internal_r+0x1fc4> + 80036fc: 6080080c andi r2,r12,32 + 8003700: 63000414 ori r12,r12,16 + 8003704: 1000cc1e bne r2,zero,8003a38 <___vfprintf_internal_r+0xbf4> + 8003708: d8800617 ldw r2,24(sp) + 800370c: 10800104 addi r2,r2,4 + 8003710: d8c00617 ldw r3,24(sp) + 8003714: 0029883a mov r20,zero + 8003718: d8800615 stw r2,24(sp) + 800371c: 1d400017 ldw r21,0(r3) + 8003720: 0005883a mov r2,zero + 8003724: 0000a206 br 80039b0 <___vfprintf_internal_r+0xb6c> + 8003728: 63000214 ori r12,r12,8 + 800372c: b2800007 ldb r10,0(r22) + 8003730: 003e1f06 br 8002fb0 <___vfprintf_internal_r+0x16c> + 8003734: 21003fcc andi r4,r4,255 + 8003738: 2005b71e bne r4,zero,8004e18 <___vfprintf_internal_r+0x1fd4> + 800373c: d8c00617 ldw r3,24(sp) + 8003740: 00a00034 movhi r2,32768 + 8003744: 10bfffc4 addi r2,r2,-1 + 8003748: 1d000117 ldw r20,4(r3) + 800374c: 1c800017 ldw r18,0(r3) + 8003750: 01dffc34 movhi r7,32752 + 8003754: a0a0703a and r16,r20,r2 + 8003758: 01bfffc4 movi r6,-1 + 800375c: 18800204 addi r2,r3,8 + 8003760: 39ffffc4 addi r7,r7,-1 + 8003764: 9009883a mov r4,r18 + 8003768: 800b883a mov r5,r16 + 800376c: da000f15 stw r8,60(sp) + 8003770: dac00e15 stw r11,56(sp) + 8003774: db000715 stw r12,28(sp) + 8003778: dd000a15 stw r20,40(sp) + 800377c: dc800915 stw r18,36(sp) + 8003780: d8800615 stw r2,24(sp) + 8003784: 800f5580 call 800f558 <__unorddf2> + 8003788: db000717 ldw r12,28(sp) + 800378c: dac00e17 ldw r11,56(sp) + 8003790: da000f17 ldw r8,60(sp) + 8003794: 1003161e bne r2,zero,80043f0 <___vfprintf_internal_r+0x15ac> + 8003798: 01dffc34 movhi r7,32752 + 800379c: 01bfffc4 movi r6,-1 + 80037a0: 39ffffc4 addi r7,r7,-1 + 80037a4: 9009883a mov r4,r18 + 80037a8: 800b883a mov r5,r16 + 80037ac: 800e4700 call 800e470 <__ledf2> + 80037b0: db000717 ldw r12,28(sp) + 80037b4: dac00e17 ldw r11,56(sp) + 80037b8: da000f17 ldw r8,60(sp) + 80037bc: 00830c0e bge zero,r2,80043f0 <___vfprintf_internal_r+0x15ac> + 80037c0: 000d883a mov r6,zero + 80037c4: 000f883a mov r7,zero + 80037c8: 9009883a mov r4,r18 + 80037cc: a00b883a mov r5,r20 + 80037d0: da000e15 stw r8,56(sp) + 80037d4: 800e4700 call 800e470 <__ledf2> + 80037d8: db000717 ldw r12,28(sp) + 80037dc: da000e17 ldw r8,56(sp) + 80037e0: 1004e216 blt r2,zero,8004b6c <___vfprintf_internal_r+0x1d28> + 80037e4: db401543 ldbu r13,85(sp) + 80037e8: e0801210 cmplti r2,fp,72 + 80037ec: 1004cb1e bne r2,zero,8004b1c <___vfprintf_internal_r+0x1cd8> + 80037f0: 04020134 movhi r16,2052 + 80037f4: 841d1804 addi r16,r16,29792 + 80037f8: 04bfdfc4 movi r18,-129 + 80037fc: 64a4703a and r18,r12,r18 + 8003800: 054000c4 movi r21,3 + 8003804: 050000c4 movi r20,3 + 8003808: 0017883a mov r11,zero + 800380c: d8000715 stw zero,28(sp) + 8003810: 0000a306 br 8003aa0 <___vfprintf_internal_r+0xc5c> + 8003814: 21003fcc andi r4,r4,255 + 8003818: 20057d1e bne r4,zero,8004e10 <___vfprintf_internal_r+0x1fcc> + 800381c: 6080080c andi r2,r12,32 + 8003820: 63000414 ori r12,r12,16 + 8003824: 10007d1e bne r2,zero,8003a1c <___vfprintf_internal_r+0xbd8> + 8003828: d8800617 ldw r2,24(sp) + 800382c: 10800104 addi r2,r2,4 + 8003830: d8c00617 ldw r3,24(sp) + 8003834: 1d400017 ldw r21,0(r3) + 8003838: d8800615 stw r2,24(sp) + 800383c: a829d7fa srai r20,r21,31 + 8003840: a005883a mov r2,r20 + 8003844: 103f020e bge r2,zero,8003450 <___vfprintf_internal_r+0x60c> + 8003848: 056bc83a sub r21,zero,r21 + 800384c: a804c03a cmpne r2,r21,zero + 8003850: 0529c83a sub r20,zero,r20 + 8003854: a0a9c83a sub r20,r20,r2 + 8003858: 00800b44 movi r2,45 + 800385c: d8801545 stb r2,85(sp) + 8003860: 58ffffe0 cmpeqi r3,r11,-1 + 8003864: 03400b44 movi r13,45 + 8003868: 00800044 movi r2,1 + 800386c: 18005426 beq r3,zero,80039c0 <___vfprintf_internal_r+0xb7c> + 8003870: 10c00060 cmpeqi r3,r2,1 + 8003874: 18007e1e bne r3,zero,8003a70 <___vfprintf_internal_r+0xc2c> + 8003878: 108000a0 cmpeqi r2,r2,2 + 800387c: 1002371e bne r2,zero,800415c <___vfprintf_internal_r+0x1318> + 8003880: b807883a mov r3,r23 + 8003884: 00000106 br 800388c <___vfprintf_internal_r+0xa48> + 8003888: 8007883a mov r3,r16 + 800388c: a808d0fa srli r4,r21,3 + 8003890: a00a977a slli r5,r20,29 + 8003894: a028d0fa srli r20,r20,3 + 8003898: ad4001cc andi r21,r21,7 + 800389c: a8800c04 addi r2,r21,48 + 80038a0: 292ab03a or r21,r5,r4 + 80038a4: 18bfffc5 stb r2,-1(r3) + 80038a8: ad08b03a or r4,r21,r20 + 80038ac: 1c3fffc4 addi r16,r3,-1 + 80038b0: 203ff51e bne r4,zero,8003888 <___vfprintf_internal_r+0xa44> + 80038b4: 6100004c andi r4,r12,1 + 80038b8: 2000a026 beq r4,zero,8003b3c <___vfprintf_internal_r+0xcf8> + 80038bc: 10803fcc andi r2,r2,255 + 80038c0: 1080201c xori r2,r2,128 + 80038c4: 10bfe004 addi r2,r2,-128 + 80038c8: 10800c18 cmpnei r2,r2,48 + 80038cc: 10009b26 beq r2,zero,8003b3c <___vfprintf_internal_r+0xcf8> + 80038d0: 18ffff84 addi r3,r3,-2 + 80038d4: 00800c04 movi r2,48 + 80038d8: 80bfffc5 stb r2,-1(r16) + 80038dc: b8e9c83a sub r20,r23,r3 + 80038e0: 6025883a mov r18,r12 + 80038e4: 1821883a mov r16,r3 + 80038e8: 00006906 br 8003a90 <___vfprintf_internal_r+0xc4c> + 80038ec: 21003fcc andi r4,r4,255 + 80038f0: 2005391e bne r4,zero,8004dd8 <___vfprintf_internal_r+0x1f94> + 80038f4: 00820134 movhi r2,2052 + 80038f8: 109d1b04 addi r2,r2,29804 + 80038fc: d8800c15 stw r2,48(sp) + 8003900: 6080080c andi r2,r12,32 + 8003904: 103e901e bne r2,zero,8003348 <___vfprintf_internal_r+0x504> + 8003908: d8c00617 ldw r3,24(sp) + 800390c: 6080040c andi r2,r12,16 + 8003910: 1d400017 ldw r21,0(r3) + 8003914: 18c00104 addi r3,r3,4 + 8003918: d8c00615 stw r3,24(sp) + 800391c: 1002ae1e bne r2,zero,80043d8 <___vfprintf_internal_r+0x1594> + 8003920: 6080100c andi r2,r12,64 + 8003924: 1002ac26 beq r2,zero,80043d8 <___vfprintf_internal_r+0x1594> + 8003928: ad7fffcc andi r21,r21,65535 + 800392c: 0029883a mov r20,zero + 8003930: 003e8a06 br 800335c <___vfprintf_internal_r+0x518> + 8003934: 21003fcc andi r4,r4,255 + 8003938: 2005391e bne r4,zero,8004e20 <___vfprintf_internal_r+0x1fdc> + 800393c: 6080080c andi r2,r12,32 + 8003940: 63000414 ori r12,r12,16 + 8003944: 1000431e bne r2,zero,8003a54 <___vfprintf_internal_r+0xc10> + 8003948: d8800617 ldw r2,24(sp) + 800394c: 10800104 addi r2,r2,4 + 8003950: d8c00617 ldw r3,24(sp) + 8003954: 0029883a mov r20,zero + 8003958: d8800615 stw r2,24(sp) + 800395c: 1d400017 ldw r21,0(r3) + 8003960: 00800044 movi r2,1 + 8003964: 00001206 br 80039b0 <___vfprintf_internal_r+0xb6c> + 8003968: 63000814 ori r12,r12,32 + 800396c: b2800007 ldb r10,0(r22) + 8003970: 003d8f06 br 8002fb0 <___vfprintf_internal_r+0x16c> + 8003974: d8c00617 ldw r3,24(sp) + 8003978: 00800c04 movi r2,48 + 800397c: d8801585 stb r2,86(sp) + 8003980: 00801e04 movi r2,120 + 8003984: 01020134 movhi r4,2052 + 8003988: d88015c5 stb r2,87(sp) + 800398c: 1d400017 ldw r21,0(r3) + 8003990: 18800104 addi r2,r3,4 + 8003994: d8800615 stw r2,24(sp) + 8003998: 209d2004 addi r2,r4,29824 + 800399c: d8800c15 stw r2,48(sp) + 80039a0: 0029883a mov r20,zero + 80039a4: 63000094 ori r12,r12,2 + 80039a8: 00800084 movi r2,2 + 80039ac: 07001e04 movi fp,120 + 80039b0: d8001545 stb zero,85(sp) + 80039b4: 58ffffe0 cmpeqi r3,r11,-1 + 80039b8: 001b883a mov r13,zero + 80039bc: 183fac1e bne r3,zero,8003870 <___vfprintf_internal_r+0xa2c> + 80039c0: 04bfdfc4 movi r18,-129 + 80039c4: ad06b03a or r3,r21,r20 + 80039c8: 64a4703a and r18,r12,r18 + 80039cc: 18018d1e bne r3,zero,8004004 <___vfprintf_internal_r+0x11c0> + 80039d0: 5803b91e bne r11,zero,80048b8 <___vfprintf_internal_r+0x1a74> + 80039d4: 103ea71e bne r2,zero,8003474 <___vfprintf_internal_r+0x630> + 80039d8: 6500004c andi r20,r12,1 + 80039dc: a0028226 beq r20,zero,80043e8 <___vfprintf_internal_r+0x15a4> + 80039e0: 00800c04 movi r2,48 + 80039e4: d88028c5 stb r2,163(sp) + 80039e8: dc0028c4 addi r16,sp,163 + 80039ec: 00002806 br 8003a90 <___vfprintf_internal_r+0xc4c> + 80039f0: b2800007 ldb r10,0(r22) + 80039f4: 50801b18 cmpnei r2,r10,108 + 80039f8: 10032926 beq r2,zero,80046a0 <___vfprintf_internal_r+0x185c> + 80039fc: 63000414 ori r12,r12,16 + 8003a00: 003d6b06 br 8002fb0 <___vfprintf_internal_r+0x16c> + 8003a04: 63001014 ori r12,r12,64 + 8003a08: b2800007 ldb r10,0(r22) + 8003a0c: 003d6806 br 8002fb0 <___vfprintf_internal_r+0x16c> + 8003a10: d9000517 ldw r4,20(sp) + 8003a14: 80070600 call 8007060 <__sinit> + 8003a18: 003d2306 br 8002ea8 <___vfprintf_internal_r+0x64> + 8003a1c: d8c00617 ldw r3,24(sp) + 8003a20: 18800117 ldw r2,4(r3) + 8003a24: 1d400017 ldw r21,0(r3) + 8003a28: 18c00204 addi r3,r3,8 + 8003a2c: d8c00615 stw r3,24(sp) + 8003a30: 1029883a mov r20,r2 + 8003a34: 003e8506 br 800344c <___vfprintf_internal_r+0x608> + 8003a38: d8c00617 ldw r3,24(sp) + 8003a3c: 0005883a mov r2,zero + 8003a40: 1d400017 ldw r21,0(r3) + 8003a44: 1d000117 ldw r20,4(r3) + 8003a48: 18c00204 addi r3,r3,8 + 8003a4c: d8c00615 stw r3,24(sp) + 8003a50: 003fd706 br 80039b0 <___vfprintf_internal_r+0xb6c> + 8003a54: d8c00617 ldw r3,24(sp) + 8003a58: 00800044 movi r2,1 + 8003a5c: 1d400017 ldw r21,0(r3) + 8003a60: 1d000117 ldw r20,4(r3) + 8003a64: 18c00204 addi r3,r3,8 + 8003a68: d8c00615 stw r3,24(sp) + 8003a6c: 003fd006 br 80039b0 <___vfprintf_internal_r+0xb6c> + 8003a70: a000111e bne r20,zero,8003ab8 <___vfprintf_internal_r+0xc74> + 8003a74: a88002a8 cmpgeui r2,r21,10 + 8003a78: 10000f1e bne r2,zero,8003ab8 <___vfprintf_internal_r+0xc74> + 8003a7c: ad400c04 addi r21,r21,48 + 8003a80: dd4028c5 stb r21,163(sp) + 8003a84: 6025883a mov r18,r12 + 8003a88: 05000044 movi r20,1 + 8003a8c: dc0028c4 addi r16,sp,163 + 8003a90: 582b883a mov r21,r11 + 8003a94: 5d00010e bge r11,r20,8003a9c <___vfprintf_internal_r+0xc58> + 8003a98: a02b883a mov r21,r20 + 8003a9c: d8000715 stw zero,28(sp) + 8003aa0: 6b403fcc andi r13,r13,255 + 8003aa4: 6b40201c xori r13,r13,128 + 8003aa8: 6b7fe004 addi r13,r13,-128 + 8003aac: 683e8126 beq r13,zero,80034b4 <___vfprintf_internal_r+0x670> + 8003ab0: ad400044 addi r21,r21,1 + 8003ab4: 003e7f06 br 80034b4 <___vfprintf_internal_r+0x670> + 8003ab8: dc400e15 stw r17,56(sp) + 8003abc: b821883a mov r16,r23 + 8003ac0: a023883a mov r17,r20 + 8003ac4: db000715 stw r12,28(sp) + 8003ac8: 9829883a mov r20,r19 + 8003acc: dac00f15 stw r11,60(sp) + 8003ad0: 4025883a mov r18,r8 + 8003ad4: 6827883a mov r19,r13 + 8003ad8: 00000206 br 8003ae4 <___vfprintf_internal_r+0xca0> + 8003adc: 102b883a mov r21,r2 + 8003ae0: 1823883a mov r17,r3 + 8003ae4: a809883a mov r4,r21 + 8003ae8: 880b883a mov r5,r17 + 8003aec: 01800284 movi r6,10 + 8003af0: 000f883a mov r7,zero + 8003af4: 800c9c00 call 800c9c0 <__umoddi3> + 8003af8: 10800c04 addi r2,r2,48 + 8003afc: 843fffc4 addi r16,r16,-1 + 8003b00: a809883a mov r4,r21 + 8003b04: 880b883a mov r5,r17 + 8003b08: 80800005 stb r2,0(r16) + 8003b0c: 01800284 movi r6,10 + 8003b10: 000f883a mov r7,zero + 8003b14: 800c4280 call 800c428 <__udivdi3> + 8003b18: 883ff01e bne r17,zero,8003adc <___vfprintf_internal_r+0xc98> + 8003b1c: ad4002a8 cmpgeui r21,r21,10 + 8003b20: a83fee1e bne r21,zero,8003adc <___vfprintf_internal_r+0xc98> + 8003b24: db000717 ldw r12,28(sp) + 8003b28: dc400e17 ldw r17,56(sp) + 8003b2c: dac00f17 ldw r11,60(sp) + 8003b30: 981b883a mov r13,r19 + 8003b34: 9011883a mov r8,r18 + 8003b38: a027883a mov r19,r20 + 8003b3c: bc29c83a sub r20,r23,r16 + 8003b40: 6025883a mov r18,r12 + 8003b44: 003fd206 br 8003a90 <___vfprintf_internal_r+0xc4c> + 8003b48: e2801990 cmplti r10,fp,102 + 8003b4c: 5000ea1e bne r10,zero,8003ef8 <___vfprintf_internal_r+0x10b4> + 8003b50: d9000917 ldw r4,36(sp) + 8003b54: d9400a17 ldw r5,40(sp) + 8003b58: 000d883a mov r6,zero + 8003b5c: 000f883a mov r7,zero + 8003b60: da000f15 stw r8,60(sp) + 8003b64: d8c00e15 stw r3,56(sp) + 8003b68: 800e3000 call 800e300 <__eqdf2> + 8003b6c: d8c00e17 ldw r3,56(sp) + 8003b70: da000f17 ldw r8,60(sp) + 8003b74: 1001891e bne r2,zero,800419c <___vfprintf_internal_r+0x1358> + 8003b78: d8801d17 ldw r2,116(sp) + 8003b7c: 01020134 movhi r4,2052 + 8003b80: 211d2704 addi r4,r4,29852 + 8003b84: 10800044 addi r2,r2,1 + 8003b88: 18c00044 addi r3,r3,1 + 8003b8c: 41000015 stw r4,0(r8) + 8003b90: 01000044 movi r4,1 + 8003b94: d8801d15 stw r2,116(sp) + 8003b98: 41000115 stw r4,4(r8) + 8003b9c: d8c01e15 stw r3,120(sp) + 8003ba0: 10800208 cmpgei r2,r2,8 + 8003ba4: 1003331e bne r2,zero,8004874 <___vfprintf_internal_r+0x1a30> + 8003ba8: 42000204 addi r8,r8,8 + 8003bac: d8801617 ldw r2,88(sp) + 8003bb0: d8c00817 ldw r3,32(sp) + 8003bb4: 10c00416 blt r2,r3,8003bc8 <___vfprintf_internal_r+0xd84> + 8003bb8: 9080004c andi r2,r18,1 + 8003bbc: 1000021e bne r2,zero,8003bc8 <___vfprintf_internal_r+0xd84> + 8003bc0: d8c01e17 ldw r3,120(sp) + 8003bc4: 003e6e06 br 8003580 <___vfprintf_internal_r+0x73c> + 8003bc8: d8800d17 ldw r2,52(sp) + 8003bcc: d8c01e17 ldw r3,120(sp) + 8003bd0: d9000b17 ldw r4,44(sp) + 8003bd4: 40800015 stw r2,0(r8) + 8003bd8: d8801d17 ldw r2,116(sp) + 8003bdc: 20c7883a add r3,r4,r3 + 8003be0: 41000115 stw r4,4(r8) + 8003be4: 10800044 addi r2,r2,1 + 8003be8: d8801d15 stw r2,116(sp) + 8003bec: d8c01e15 stw r3,120(sp) + 8003bf0: 10800208 cmpgei r2,r2,8 + 8003bf4: 1002b11e bne r2,zero,80046bc <___vfprintf_internal_r+0x1878> + 8003bf8: 42000204 addi r8,r8,8 + 8003bfc: d8800817 ldw r2,32(sp) + 8003c00: 143fffc4 addi r16,r2,-1 + 8003c04: 043e5e0e bge zero,r16,8003580 <___vfprintf_internal_r+0x73c> + 8003c08: 03020134 movhi r12,2052 + 8003c0c: 81000450 cmplti r4,r16,17 + 8003c10: 631d2784 addi r12,r12,29854 + 8003c14: d8801d17 ldw r2,116(sp) + 8003c18: 2003731e bne r4,zero,80049e8 <___vfprintf_internal_r+0x1ba4> + 8003c1c: dc400715 stw r17,28(sp) + 8003c20: 05000404 movi r20,16 + 8003c24: df000517 ldw fp,20(sp) + 8003c28: 6023883a mov r17,r12 + 8003c2c: 00000406 br 8003c40 <___vfprintf_internal_r+0xdfc> + 8003c30: 42000204 addi r8,r8,8 + 8003c34: 843ffc04 addi r16,r16,-16 + 8003c38: 81000448 cmpgei r4,r16,17 + 8003c3c: 20036826 beq r4,zero,80049e0 <___vfprintf_internal_r+0x1b9c> + 8003c40: 10800044 addi r2,r2,1 + 8003c44: 18c00404 addi r3,r3,16 + 8003c48: 44400015 stw r17,0(r8) + 8003c4c: 45000115 stw r20,4(r8) + 8003c50: d8c01e15 stw r3,120(sp) + 8003c54: d8801d15 stw r2,116(sp) + 8003c58: 11000208 cmpgei r4,r2,8 + 8003c5c: 203ff426 beq r4,zero,8003c30 <___vfprintf_internal_r+0xdec> + 8003c60: d9801c04 addi r6,sp,112 + 8003c64: 980b883a mov r5,r19 + 8003c68: e009883a mov r4,fp + 8003c6c: 800a3f80 call 800a3f8 <__sprint_r> + 8003c70: 103d531e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 8003c74: d8c01e17 ldw r3,120(sp) + 8003c78: d8801d17 ldw r2,116(sp) + 8003c7c: b811883a mov r8,r23 + 8003c80: 003fec06 br 8003c34 <___vfprintf_internal_r+0xdf0> + 8003c84: 8d4fc83a sub r7,r17,r21 + 8003c88: 01fe2f0e bge zero,r7,8003548 <___vfprintf_internal_r+0x704> + 8003c8c: 03020134 movhi r12,2052 + 8003c90: 39000450 cmplti r4,r7,17 + 8003c94: 631d2784 addi r12,r12,29854 + 8003c98: d8801d17 ldw r2,116(sp) + 8003c9c: 2000271e bne r4,zero,8003d3c <___vfprintf_internal_r+0xef8> + 8003ca0: dc000e15 stw r16,56(sp) + 8003ca4: dc800f15 stw r18,60(sp) + 8003ca8: dc401015 stw r17,64(sp) + 8003cac: 03400404 movi r13,16 + 8003cb0: 3821883a mov r16,r7 + 8003cb4: dac01215 stw r11,72(sp) + 8003cb8: dc400517 ldw r17,20(sp) + 8003cbc: 6025883a mov r18,r12 + 8003cc0: 00000406 br 8003cd4 <___vfprintf_internal_r+0xe90> + 8003cc4: 843ffc04 addi r16,r16,-16 + 8003cc8: 81000448 cmpgei r4,r16,17 + 8003ccc: 42000204 addi r8,r8,8 + 8003cd0: 20001426 beq r4,zero,8003d24 <___vfprintf_internal_r+0xee0> + 8003cd4: 10800044 addi r2,r2,1 + 8003cd8: 18c00404 addi r3,r3,16 + 8003cdc: 44800015 stw r18,0(r8) + 8003ce0: 43400115 stw r13,4(r8) + 8003ce4: d8c01e15 stw r3,120(sp) + 8003ce8: d8801d15 stw r2,116(sp) + 8003cec: 11000208 cmpgei r4,r2,8 + 8003cf0: 203ff426 beq r4,zero,8003cc4 <___vfprintf_internal_r+0xe80> + 8003cf4: d9801c04 addi r6,sp,112 + 8003cf8: 980b883a mov r5,r19 + 8003cfc: 8809883a mov r4,r17 + 8003d00: 800a3f80 call 800a3f8 <__sprint_r> + 8003d04: 103d2e1e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 8003d08: 843ffc04 addi r16,r16,-16 + 8003d0c: 81000448 cmpgei r4,r16,17 + 8003d10: d8c01e17 ldw r3,120(sp) + 8003d14: d8801d17 ldw r2,116(sp) + 8003d18: b811883a mov r8,r23 + 8003d1c: 03400404 movi r13,16 + 8003d20: 203fec1e bne r4,zero,8003cd4 <___vfprintf_internal_r+0xe90> + 8003d24: 800f883a mov r7,r16 + 8003d28: 9019883a mov r12,r18 + 8003d2c: dc000e17 ldw r16,56(sp) + 8003d30: dc401017 ldw r17,64(sp) + 8003d34: dac01217 ldw r11,72(sp) + 8003d38: dc800f17 ldw r18,60(sp) + 8003d3c: 10800044 addi r2,r2,1 + 8003d40: 19c7883a add r3,r3,r7 + 8003d44: d8801d15 stw r2,116(sp) + 8003d48: 43000015 stw r12,0(r8) + 8003d4c: 41c00115 stw r7,4(r8) + 8003d50: d8c01e15 stw r3,120(sp) + 8003d54: 10800208 cmpgei r2,r2,8 + 8003d58: 1002cd1e bne r2,zero,8004890 <___vfprintf_internal_r+0x1a4c> + 8003d5c: 5d0fc83a sub r7,r11,r20 + 8003d60: 42000204 addi r8,r8,8 + 8003d64: 01fdfa0e bge zero,r7,8003550 <___vfprintf_internal_r+0x70c> + 8003d68: 03020134 movhi r12,2052 + 8003d6c: 39000450 cmplti r4,r7,17 + 8003d70: 631d2784 addi r12,r12,29854 + 8003d74: d8801d17 ldw r2,116(sp) + 8003d78: 2000251e bne r4,zero,8003e10 <___vfprintf_internal_r+0xfcc> + 8003d7c: dc000e15 stw r16,56(sp) + 8003d80: dc800f15 stw r18,60(sp) + 8003d84: dc401015 stw r17,64(sp) + 8003d88: 02c00404 movi r11,16 + 8003d8c: 3821883a mov r16,r7 + 8003d90: dc400517 ldw r17,20(sp) + 8003d94: 6025883a mov r18,r12 + 8003d98: 00000406 br 8003dac <___vfprintf_internal_r+0xf68> + 8003d9c: 843ffc04 addi r16,r16,-16 + 8003da0: 81000448 cmpgei r4,r16,17 + 8003da4: 42000204 addi r8,r8,8 + 8003da8: 20001426 beq r4,zero,8003dfc <___vfprintf_internal_r+0xfb8> + 8003dac: 10800044 addi r2,r2,1 + 8003db0: 18c00404 addi r3,r3,16 + 8003db4: 44800015 stw r18,0(r8) + 8003db8: 42c00115 stw r11,4(r8) + 8003dbc: d8c01e15 stw r3,120(sp) + 8003dc0: d8801d15 stw r2,116(sp) + 8003dc4: 11000208 cmpgei r4,r2,8 + 8003dc8: 203ff426 beq r4,zero,8003d9c <___vfprintf_internal_r+0xf58> + 8003dcc: d9801c04 addi r6,sp,112 + 8003dd0: 980b883a mov r5,r19 + 8003dd4: 8809883a mov r4,r17 + 8003dd8: 800a3f80 call 800a3f8 <__sprint_r> + 8003ddc: 103cf81e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 8003de0: 843ffc04 addi r16,r16,-16 + 8003de4: 81000448 cmpgei r4,r16,17 + 8003de8: d8c01e17 ldw r3,120(sp) + 8003dec: d8801d17 ldw r2,116(sp) + 8003df0: b811883a mov r8,r23 + 8003df4: 02c00404 movi r11,16 + 8003df8: 203fec1e bne r4,zero,8003dac <___vfprintf_internal_r+0xf68> + 8003dfc: 800f883a mov r7,r16 + 8003e00: 9019883a mov r12,r18 + 8003e04: dc401017 ldw r17,64(sp) + 8003e08: dc000e17 ldw r16,56(sp) + 8003e0c: dc800f17 ldw r18,60(sp) + 8003e10: 10800044 addi r2,r2,1 + 8003e14: 19c7883a add r3,r3,r7 + 8003e18: d8801d15 stw r2,116(sp) + 8003e1c: 43000015 stw r12,0(r8) + 8003e20: 41c00115 stw r7,4(r8) + 8003e24: d8c01e15 stw r3,120(sp) + 8003e28: 10800208 cmpgei r2,r2,8 + 8003e2c: 1001621e bne r2,zero,80043b8 <___vfprintf_internal_r+0x1574> + 8003e30: 42000204 addi r8,r8,8 + 8003e34: 003dc606 br 8003550 <___vfprintf_internal_r+0x70c> + 8003e38: d9000517 ldw r4,20(sp) + 8003e3c: d9801c04 addi r6,sp,112 + 8003e40: 980b883a mov r5,r19 + 8003e44: 800a3f80 call 800a3f8 <__sprint_r> + 8003e48: 103dd726 beq r2,zero,80035a8 <___vfprintf_internal_r+0x764> + 8003e4c: 003cdc06 br 80031c0 <___vfprintf_internal_r+0x37c> + 8003e50: d9000517 ldw r4,20(sp) + 8003e54: d9801c04 addi r6,sp,112 + 8003e58: 980b883a mov r5,r19 + 8003e5c: 800a3f80 call 800a3f8 <__sprint_r> + 8003e60: 103cd71e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 8003e64: d9001617 ldw r4,88(sp) + 8003e68: d8c01e17 ldw r3,120(sp) + 8003e6c: b811883a mov r8,r23 + 8003e70: 2002951e bne r4,zero,80048c8 <___vfprintf_internal_r+0x1a84> + 8003e74: d9000817 ldw r4,32(sp) + 8003e78: 9080004c andi r2,r18,1 + 8003e7c: 1104b03a or r2,r2,r4 + 8003e80: 103dbf26 beq r2,zero,8003580 <___vfprintf_internal_r+0x73c> + 8003e84: d8800d17 ldw r2,52(sp) + 8003e88: d9000b17 ldw r4,44(sp) + 8003e8c: 40800015 stw r2,0(r8) + 8003e90: d8801d17 ldw r2,116(sp) + 8003e94: 20c7883a add r3,r4,r3 + 8003e98: 41000115 stw r4,4(r8) + 8003e9c: 10800044 addi r2,r2,1 + 8003ea0: d8c01e15 stw r3,120(sp) + 8003ea4: d8801d15 stw r2,116(sp) + 8003ea8: 11000208 cmpgei r4,r2,8 + 8003eac: 2003641e bne r4,zero,8004c40 <___vfprintf_internal_r+0x1dfc> + 8003eb0: 42000204 addi r8,r8,8 + 8003eb4: d9000817 ldw r4,32(sp) + 8003eb8: 10800044 addi r2,r2,1 + 8003ebc: d8801d15 stw r2,116(sp) + 8003ec0: 20c7883a add r3,r4,r3 + 8003ec4: 44000015 stw r16,0(r8) + 8003ec8: 41000115 stw r4,4(r8) + 8003ecc: d8c01e15 stw r3,120(sp) + 8003ed0: 10800208 cmpgei r2,r2,8 + 8003ed4: 103da926 beq r2,zero,800357c <___vfprintf_internal_r+0x738> + 8003ed8: d9000517 ldw r4,20(sp) + 8003edc: d9801c04 addi r6,sp,112 + 8003ee0: 980b883a mov r5,r19 + 8003ee4: 800a3f80 call 800a3f8 <__sprint_r> + 8003ee8: 103cb51e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 8003eec: d8c01e17 ldw r3,120(sp) + 8003ef0: b811883a mov r8,r23 + 8003ef4: 003da206 br 8003580 <___vfprintf_internal_r+0x73c> + 8003ef8: d8800817 ldw r2,32(sp) + 8003efc: df001d17 ldw fp,116(sp) + 8003f00: 18c00044 addi r3,r3,1 + 8003f04: 10800088 cmpgei r2,r2,2 + 8003f08: e5000044 addi r20,fp,1 + 8003f0c: 42800204 addi r10,r8,8 + 8003f10: 1000fb26 beq r2,zero,8004300 <___vfprintf_internal_r+0x14bc> + 8003f14: 00800044 movi r2,1 + 8003f18: 40800115 stw r2,4(r8) + 8003f1c: 44000015 stw r16,0(r8) + 8003f20: d8c01e15 stw r3,120(sp) + 8003f24: dd001d15 stw r20,116(sp) + 8003f28: a0800210 cmplti r2,r20,8 + 8003f2c: 10022c26 beq r2,zero,80047e0 <___vfprintf_internal_r+0x199c> + 8003f30: d8800b17 ldw r2,44(sp) + 8003f34: d9000d17 ldw r4,52(sp) + 8003f38: a5000044 addi r20,r20,1 + 8003f3c: 1887883a add r3,r3,r2 + 8003f40: 50800115 stw r2,4(r10) + 8003f44: 51000015 stw r4,0(r10) + 8003f48: d8c01e15 stw r3,120(sp) + 8003f4c: dd001d15 stw r20,116(sp) + 8003f50: a0800208 cmpgei r2,r20,8 + 8003f54: 1002191e bne r2,zero,80047bc <___vfprintf_internal_r+0x1978> + 8003f58: 52800204 addi r10,r10,8 + 8003f5c: d8800817 ldw r2,32(sp) + 8003f60: d9000917 ldw r4,36(sp) + 8003f64: d9400a17 ldw r5,40(sp) + 8003f68: 52000204 addi r8,r10,8 + 8003f6c: 12ffffc4 addi r11,r2,-1 + 8003f70: a7000044 addi fp,r20,1 + 8003f74: 000d883a mov r6,zero + 8003f78: 000f883a mov r7,zero + 8003f7c: d8c01215 stw r3,72(sp) + 8003f80: da800f15 stw r10,60(sp) + 8003f84: da000e15 stw r8,56(sp) + 8003f88: dac00715 stw r11,28(sp) + 8003f8c: df001015 stw fp,64(sp) + 8003f90: 800e3000 call 800e300 <__eqdf2> + 8003f94: dac00717 ldw r11,28(sp) + 8003f98: da000e17 ldw r8,56(sp) + 8003f9c: da800f17 ldw r10,60(sp) + 8003fa0: db401017 ldw r13,64(sp) + 8003fa4: d8c01217 ldw r3,72(sp) + 8003fa8: 1000e126 beq r2,zero,8004330 <___vfprintf_internal_r+0x14ec> + 8003fac: 84000044 addi r16,r16,1 + 8003fb0: 1ac7883a add r3,r3,r11 + 8003fb4: df001d15 stw fp,116(sp) + 8003fb8: 54000015 stw r16,0(r10) + 8003fbc: 52c00115 stw r11,4(r10) + 8003fc0: d8c01e15 stw r3,120(sp) + 8003fc4: e7000208 cmpgei fp,fp,8 + 8003fc8: e001aa1e bne fp,zero,8004674 <___vfprintf_internal_r+0x1830> + 8003fcc: 50800404 addi r2,r10,16 + 8003fd0: a7000084 addi fp,r20,2 + 8003fd4: 4015883a mov r10,r8 + 8003fd8: 1011883a mov r8,r2 + 8003fdc: d9001117 ldw r4,68(sp) + 8003fe0: d8801844 addi r2,sp,97 + 8003fe4: df001d15 stw fp,116(sp) + 8003fe8: 20c7883a add r3,r4,r3 + 8003fec: 50800015 stw r2,0(r10) + 8003ff0: 51000115 stw r4,4(r10) + 8003ff4: d8c01e15 stw r3,120(sp) + 8003ff8: e7000210 cmplti fp,fp,8 + 8003ffc: e03d601e bne fp,zero,8003580 <___vfprintf_internal_r+0x73c> + 8004000: 003fb506 br 8003ed8 <___vfprintf_internal_r+0x1094> + 8004004: 9019883a mov r12,r18 + 8004008: 003e1906 br 8003870 <___vfprintf_internal_r+0xa2c> + 800400c: 03020134 movhi r12,2052 + 8004010: 39000450 cmplti r4,r7,17 + 8004014: 631d2b84 addi r12,r12,29870 + 8004018: d8801d17 ldw r2,116(sp) + 800401c: 20002b1e bne r4,zero,80040cc <___vfprintf_internal_r+0x1288> + 8004020: dc001015 stw r16,64(sp) + 8004024: dc801215 stw r18,72(sp) + 8004028: dc401315 stw r17,76(sp) + 800402c: 03c00404 movi r15,16 + 8004030: db800e15 stw r14,56(sp) + 8004034: db400f15 stw r13,60(sp) + 8004038: dac01415 stw r11,80(sp) + 800403c: 3821883a mov r16,r7 + 8004040: dc400517 ldw r17,20(sp) + 8004044: 6025883a mov r18,r12 + 8004048: 00000406 br 800405c <___vfprintf_internal_r+0x1218> + 800404c: 843ffc04 addi r16,r16,-16 + 8004050: 81000448 cmpgei r4,r16,17 + 8004054: 42000204 addi r8,r8,8 + 8004058: 20001426 beq r4,zero,80040ac <___vfprintf_internal_r+0x1268> + 800405c: 10800044 addi r2,r2,1 + 8004060: 18c00404 addi r3,r3,16 + 8004064: 44800015 stw r18,0(r8) + 8004068: 43c00115 stw r15,4(r8) + 800406c: d8c01e15 stw r3,120(sp) + 8004070: d8801d15 stw r2,116(sp) + 8004074: 11000208 cmpgei r4,r2,8 + 8004078: 203ff426 beq r4,zero,800404c <___vfprintf_internal_r+0x1208> + 800407c: d9801c04 addi r6,sp,112 + 8004080: 980b883a mov r5,r19 + 8004084: 8809883a mov r4,r17 + 8004088: 800a3f80 call 800a3f8 <__sprint_r> + 800408c: 103c4c1e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 8004090: 843ffc04 addi r16,r16,-16 + 8004094: 81000448 cmpgei r4,r16,17 + 8004098: d8c01e17 ldw r3,120(sp) + 800409c: d8801d17 ldw r2,116(sp) + 80040a0: b811883a mov r8,r23 + 80040a4: 03c00404 movi r15,16 + 80040a8: 203fec1e bne r4,zero,800405c <___vfprintf_internal_r+0x1218> + 80040ac: 800f883a mov r7,r16 + 80040b0: 9019883a mov r12,r18 + 80040b4: db800e17 ldw r14,56(sp) + 80040b8: db400f17 ldw r13,60(sp) + 80040bc: dc401317 ldw r17,76(sp) + 80040c0: dac01417 ldw r11,80(sp) + 80040c4: dc001017 ldw r16,64(sp) + 80040c8: dc801217 ldw r18,72(sp) + 80040cc: 10800044 addi r2,r2,1 + 80040d0: 19c7883a add r3,r3,r7 + 80040d4: d8801d15 stw r2,116(sp) + 80040d8: 43000015 stw r12,0(r8) + 80040dc: 41c00115 stw r7,4(r8) + 80040e0: d8c01e15 stw r3,120(sp) + 80040e4: 10800208 cmpgei r2,r2,8 + 80040e8: 1001d41e bne r2,zero,800483c <___vfprintf_internal_r+0x19f8> + 80040ec: 42000204 addi r8,r8,8 + 80040f0: 003cf806 br 80034d4 <___vfprintf_internal_r+0x690> + 80040f4: d9000517 ldw r4,20(sp) + 80040f8: d9801c04 addi r6,sp,112 + 80040fc: 980b883a mov r5,r19 + 8004100: dac01015 stw r11,64(sp) + 8004104: db400f15 stw r13,60(sp) + 8004108: db800e15 stw r14,56(sp) + 800410c: 800a3f80 call 800a3f8 <__sprint_r> + 8004110: 103c2b1e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 8004114: d8c01e17 ldw r3,120(sp) + 8004118: b811883a mov r8,r23 + 800411c: dac01017 ldw r11,64(sp) + 8004120: db400f17 ldw r13,60(sp) + 8004124: db800e17 ldw r14,56(sp) + 8004128: 003cf806 br 800350c <___vfprintf_internal_r+0x6c8> + 800412c: d9000517 ldw r4,20(sp) + 8004130: d9801c04 addi r6,sp,112 + 8004134: 980b883a mov r5,r19 + 8004138: dac00f15 stw r11,60(sp) + 800413c: db400e15 stw r13,56(sp) + 8004140: 800a3f80 call 800a3f8 <__sprint_r> + 8004144: 103c1e1e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 8004148: d8c01e17 ldw r3,120(sp) + 800414c: b811883a mov r8,r23 + 8004150: dac00f17 ldw r11,60(sp) + 8004154: db400e17 ldw r13,56(sp) + 8004158: 003cf906 br 8003540 <___vfprintf_internal_r+0x6fc> + 800415c: d9000c17 ldw r4,48(sp) + 8004160: b821883a mov r16,r23 + 8004164: a88003cc andi r2,r21,15 + 8004168: a006973a slli r3,r20,28 + 800416c: 2085883a add r2,r4,r2 + 8004170: a82ad13a srli r21,r21,4 + 8004174: 10800003 ldbu r2,0(r2) + 8004178: a028d13a srli r20,r20,4 + 800417c: 843fffc4 addi r16,r16,-1 + 8004180: 1d6ab03a or r21,r3,r21 + 8004184: 80800005 stb r2,0(r16) + 8004188: ad04b03a or r2,r21,r20 + 800418c: 103ff51e bne r2,zero,8004164 <___vfprintf_internal_r+0x1320> + 8004190: bc29c83a sub r20,r23,r16 + 8004194: 6025883a mov r18,r12 + 8004198: 003e3d06 br 8003a90 <___vfprintf_internal_r+0xc4c> + 800419c: d9001617 ldw r4,88(sp) + 80041a0: 0101980e bge zero,r4,8004804 <___vfprintf_internal_r+0x19c0> + 80041a4: d8800717 ldw r2,28(sp) + 80041a8: d9000817 ldw r4,32(sp) + 80041ac: 1039883a mov fp,r2 + 80041b0: 20812516 blt r4,r2,8004648 <___vfprintf_internal_r+0x1804> + 80041b4: 07000a0e bge zero,fp,80041e0 <___vfprintf_internal_r+0x139c> + 80041b8: d8801d17 ldw r2,116(sp) + 80041bc: 1f07883a add r3,r3,fp + 80041c0: 44000015 stw r16,0(r8) + 80041c4: 10800044 addi r2,r2,1 + 80041c8: d8801d15 stw r2,116(sp) + 80041cc: 47000115 stw fp,4(r8) + 80041d0: d8c01e15 stw r3,120(sp) + 80041d4: 10800208 cmpgei r2,r2,8 + 80041d8: 1002d91e bne r2,zero,8004d40 <___vfprintf_internal_r+0x1efc> + 80041dc: 42000204 addi r8,r8,8 + 80041e0: e0013e16 blt fp,zero,80046dc <___vfprintf_internal_r+0x1898> + 80041e4: d8800717 ldw r2,28(sp) + 80041e8: 1739c83a sub fp,r2,fp + 80041ec: 07014516 blt zero,fp,8004704 <___vfprintf_internal_r+0x18c0> + 80041f0: d9001617 ldw r4,88(sp) + 80041f4: d8800817 ldw r2,32(sp) + 80041f8: 2081160e bge r4,r2,8004654 <___vfprintf_internal_r+0x1810> + 80041fc: d8800d17 ldw r2,52(sp) + 8004200: d9400b17 ldw r5,44(sp) + 8004204: 40800015 stw r2,0(r8) + 8004208: d8801d17 ldw r2,116(sp) + 800420c: 1947883a add r3,r3,r5 + 8004210: 41400115 stw r5,4(r8) + 8004214: 10800044 addi r2,r2,1 + 8004218: d8801d15 stw r2,116(sp) + 800421c: d8c01e15 stw r3,120(sp) + 8004220: 10800208 cmpgei r2,r2,8 + 8004224: 1002601e bne r2,zero,8004ba8 <___vfprintf_internal_r+0x1d64> + 8004228: 42000204 addi r8,r8,8 + 800422c: d8800817 ldw r2,32(sp) + 8004230: d9400717 ldw r5,28(sp) + 8004234: 1105c83a sub r2,r2,r4 + 8004238: 29015c0e bge r5,r4,80047ac <___vfprintf_internal_r+0x1968> + 800423c: 1039883a mov fp,r2 + 8004240: 07000c0e bge zero,fp,8004274 <___vfprintf_internal_r+0x1430> + 8004244: d9000717 ldw r4,28(sp) + 8004248: 1f07883a add r3,r3,fp + 800424c: 47000115 stw fp,4(r8) + 8004250: 8121883a add r16,r16,r4 + 8004254: d9001d17 ldw r4,116(sp) + 8004258: 44000015 stw r16,0(r8) + 800425c: d8c01e15 stw r3,120(sp) + 8004260: 21000044 addi r4,r4,1 + 8004264: d9001d15 stw r4,116(sp) + 8004268: 21000208 cmpgei r4,r4,8 + 800426c: 2002bf1e bne r4,zero,8004d6c <___vfprintf_internal_r+0x1f28> + 8004270: 42000204 addi r8,r8,8 + 8004274: e000010e bge fp,zero,800427c <___vfprintf_internal_r+0x1438> + 8004278: 0039883a mov fp,zero + 800427c: 1739c83a sub fp,r2,fp + 8004280: 073cbf0e bge zero,fp,8003580 <___vfprintf_internal_r+0x73c> + 8004284: 03020134 movhi r12,2052 + 8004288: e1000450 cmplti r4,fp,17 + 800428c: 631d2784 addi r12,r12,29854 + 8004290: d8801d17 ldw r2,116(sp) + 8004294: 20023b1e bne r4,zero,8004b84 <___vfprintf_internal_r+0x1d40> + 8004298: dc400715 stw r17,28(sp) + 800429c: 05000404 movi r20,16 + 80042a0: dc000517 ldw r16,20(sp) + 80042a4: 6023883a mov r17,r12 + 80042a8: 00000406 br 80042bc <___vfprintf_internal_r+0x1478> + 80042ac: 42000204 addi r8,r8,8 + 80042b0: e73ffc04 addi fp,fp,-16 + 80042b4: e1000448 cmpgei r4,fp,17 + 80042b8: 20023026 beq r4,zero,8004b7c <___vfprintf_internal_r+0x1d38> + 80042bc: 10800044 addi r2,r2,1 + 80042c0: 18c00404 addi r3,r3,16 + 80042c4: 44400015 stw r17,0(r8) + 80042c8: 45000115 stw r20,4(r8) + 80042cc: d8c01e15 stw r3,120(sp) + 80042d0: d8801d15 stw r2,116(sp) + 80042d4: 11000208 cmpgei r4,r2,8 + 80042d8: 203ff426 beq r4,zero,80042ac <___vfprintf_internal_r+0x1468> + 80042dc: d9801c04 addi r6,sp,112 + 80042e0: 980b883a mov r5,r19 + 80042e4: 8009883a mov r4,r16 + 80042e8: 800a3f80 call 800a3f8 <__sprint_r> + 80042ec: 103bb41e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 80042f0: d8c01e17 ldw r3,120(sp) + 80042f4: d8801d17 ldw r2,116(sp) + 80042f8: b811883a mov r8,r23 + 80042fc: 003fec06 br 80042b0 <___vfprintf_internal_r+0x146c> + 8004300: 9080004c andi r2,r18,1 + 8004304: 103f031e bne r2,zero,8003f14 <___vfprintf_internal_r+0x10d0> + 8004308: 00800044 movi r2,1 + 800430c: dd001d15 stw r20,116(sp) + 8004310: 44000015 stw r16,0(r8) + 8004314: 40800115 stw r2,4(r8) + 8004318: d8c01e15 stw r3,120(sp) + 800431c: a5000208 cmpgei r20,r20,8 + 8004320: a000d41e bne r20,zero,8004674 <___vfprintf_internal_r+0x1830> + 8004324: e7000084 addi fp,fp,2 + 8004328: 42000404 addi r8,r8,16 + 800432c: 003f2b06 br 8003fdc <___vfprintf_internal_r+0x1198> + 8004330: 02ff2a0e bge zero,r11,8003fdc <___vfprintf_internal_r+0x1198> + 8004334: 58800450 cmplti r2,r11,17 + 8004338: 03020134 movhi r12,2052 + 800433c: 1002f81e bne r2,zero,8004f20 <___vfprintf_internal_r+0x20dc> + 8004340: 631d2784 addi r12,r12,29854 + 8004344: dc800715 stw r18,28(sp) + 8004348: dc400e15 stw r17,56(sp) + 800434c: 04000404 movi r16,16 + 8004350: 5823883a mov r17,r11 + 8004354: df000517 ldw fp,20(sp) + 8004358: 6025883a mov r18,r12 + 800435c: 6829883a mov r20,r13 + 8004360: 00000506 br 8004378 <___vfprintf_internal_r+0x1534> + 8004364: 52800204 addi r10,r10,8 + 8004368: 8c7ffc04 addi r17,r17,-16 + 800436c: 88800448 cmpgei r2,r17,17 + 8004370: 10018a26 beq r2,zero,800499c <___vfprintf_internal_r+0x1b58> + 8004374: a5000044 addi r20,r20,1 + 8004378: 18c00404 addi r3,r3,16 + 800437c: 54800015 stw r18,0(r10) + 8004380: 54000115 stw r16,4(r10) + 8004384: d8c01e15 stw r3,120(sp) + 8004388: dd001d15 stw r20,116(sp) + 800438c: a0800208 cmpgei r2,r20,8 + 8004390: 103ff426 beq r2,zero,8004364 <___vfprintf_internal_r+0x1520> + 8004394: d9801c04 addi r6,sp,112 + 8004398: 980b883a mov r5,r19 + 800439c: e009883a mov r4,fp + 80043a0: 800a3f80 call 800a3f8 <__sprint_r> + 80043a4: 103b861e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 80043a8: dd001d17 ldw r20,116(sp) + 80043ac: d8c01e17 ldw r3,120(sp) + 80043b0: b815883a mov r10,r23 + 80043b4: 003fec06 br 8004368 <___vfprintf_internal_r+0x1524> + 80043b8: d9000517 ldw r4,20(sp) + 80043bc: d9801c04 addi r6,sp,112 + 80043c0: 980b883a mov r5,r19 + 80043c4: 800a3f80 call 800a3f8 <__sprint_r> + 80043c8: 103b7d1e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 80043cc: d8c01e17 ldw r3,120(sp) + 80043d0: b811883a mov r8,r23 + 80043d4: 003c5e06 br 8003550 <___vfprintf_internal_r+0x70c> + 80043d8: 0029883a mov r20,zero + 80043dc: 003bdf06 br 800335c <___vfprintf_internal_r+0x518> + 80043e0: b025883a mov r18,r22 + 80043e4: 003aea06 br 8002f90 <___vfprintf_internal_r+0x14c> + 80043e8: b821883a mov r16,r23 + 80043ec: 003da806 br 8003a90 <___vfprintf_internal_r+0xc4c> + 80043f0: d9000917 ldw r4,36(sp) + 80043f4: d9400a17 ldw r5,40(sp) + 80043f8: da000f15 stw r8,60(sp) + 80043fc: 200d883a mov r6,r4 + 8004400: 280f883a mov r7,r5 + 8004404: dac00e15 stw r11,56(sp) + 8004408: db000715 stw r12,28(sp) + 800440c: 800f5580 call 800f558 <__unorddf2> + 8004410: db000717 ldw r12,28(sp) + 8004414: dac00e17 ldw r11,56(sp) + 8004418: da000f17 ldw r8,60(sp) + 800441c: 1002af1e bne r2,zero,8004edc <___vfprintf_internal_r+0x2098> + 8004420: 00fff7c4 movi r3,-33 + 8004424: e0c6703a and r3,fp,r3 + 8004428: 58bfffe0 cmpeqi r2,r11,-1 + 800442c: d8c00715 stw r3,28(sp) + 8004430: 10024c1e bne r2,zero,8004d64 <___vfprintf_internal_r+0x1f20> + 8004434: 188011d8 cmpnei r2,r3,71 + 8004438: 1001fe26 beq r2,zero,8004c34 <___vfprintf_internal_r+0x1df0> + 800443c: d8800a17 ldw r2,40(sp) + 8004440: 64804014 ori r18,r12,256 + 8004444: 1001e116 blt r2,zero,8004bcc <___vfprintf_internal_r+0x1d88> + 8004448: dd400a17 ldw r21,40(sp) + 800444c: d8000e05 stb zero,56(sp) + 8004450: e08019a0 cmpeqi r2,fp,102 + 8004454: d8800f15 stw r2,60(sp) + 8004458: 1001741e bne r2,zero,8004a2c <___vfprintf_internal_r+0x1be8> + 800445c: e08011a0 cmpeqi r2,fp,70 + 8004460: 1001721e bne r2,zero,8004a2c <___vfprintf_internal_r+0x1be8> + 8004464: d8800717 ldw r2,28(sp) + 8004468: da001215 stw r8,72(sp) + 800446c: db001015 stw r12,64(sp) + 8004470: 10801158 cmpnei r2,r2,69 + 8004474: 10020526 beq r2,zero,8004c8c <___vfprintf_internal_r+0x1e48> + 8004478: d8801a04 addi r2,sp,104 + 800447c: d8800315 stw r2,12(sp) + 8004480: d9400917 ldw r5,36(sp) + 8004484: d8801704 addi r2,sp,92 + 8004488: d9000517 ldw r4,20(sp) + 800448c: d8800215 stw r2,8(sp) + 8004490: d8801604 addi r2,sp,88 + 8004494: dac00015 stw r11,0(sp) + 8004498: d8800115 stw r2,4(sp) + 800449c: 01c00084 movi r7,2 + 80044a0: a80d883a mov r6,r21 + 80044a4: dac00815 stw r11,32(sp) + 80044a8: 80053ec0 call 80053ec <_dtoa_r> + 80044ac: dac00817 ldw r11,32(sp) + 80044b0: 1021883a mov r16,r2 + 80044b4: e08019d8 cmpnei r2,fp,103 + 80044b8: db001017 ldw r12,64(sp) + 80044bc: da001217 ldw r8,72(sp) + 80044c0: 5829883a mov r20,r11 + 80044c4: 1002031e bne r2,zero,8004cd4 <___vfprintf_internal_r+0x1e90> + 80044c8: 6080004c andi r2,r12,1 + 80044cc: 1002031e bne r2,zero,8004cdc <___vfprintf_internal_r+0x1e98> + 80044d0: d8c01617 ldw r3,88(sp) + 80044d4: d8800717 ldw r2,28(sp) + 80044d8: d8c00715 stw r3,28(sp) + 80044dc: d8c01a17 ldw r3,104(sp) + 80044e0: 108011e0 cmpeqi r2,r2,71 + 80044e4: 1c07c83a sub r3,r3,r16 + 80044e8: d8c00815 stw r3,32(sp) + 80044ec: 10000526 beq r2,zero,8004504 <___vfprintf_internal_r+0x16c0> + 80044f0: d8c00717 ldw r3,28(sp) + 80044f4: 18bfff50 cmplti r2,r3,-3 + 80044f8: 1000011e bne r2,zero,8004500 <___vfprintf_internal_r+0x16bc> + 80044fc: 58c2050e bge r11,r3,8004d14 <___vfprintf_internal_r+0x1ed0> + 8004500: e73fff84 addi fp,fp,-2 + 8004504: d8800717 ldw r2,28(sp) + 8004508: df001845 stb fp,97(sp) + 800450c: 153fffc4 addi r20,r2,-1 + 8004510: dd001615 stw r20,88(sp) + 8004514: a0027916 blt r20,zero,8004efc <___vfprintf_internal_r+0x20b8> + 8004518: 00800ac4 movi r2,43 + 800451c: d8801885 stb r2,98(sp) + 8004520: a0800290 cmplti r2,r20,10 + 8004524: 1002581e bne r2,zero,8004e88 <___vfprintf_internal_r+0x2044> + 8004528: dc000715 stw r16,28(sp) + 800452c: dd401bc4 addi r21,sp,111 + 8004530: a021883a mov r16,r20 + 8004534: db000f15 stw r12,60(sp) + 8004538: 9829883a mov r20,r19 + 800453c: 4027883a mov r19,r8 + 8004540: 00000206 br 800454c <___vfprintf_internal_r+0x1708> + 8004544: 202b883a mov r21,r4 + 8004548: 1021883a mov r16,r2 + 800454c: 8009883a mov r4,r16 + 8004550: 01400284 movi r5,10 + 8004554: 800cf800 call 800cf80 <__modsi3> + 8004558: 10800c04 addi r2,r2,48 + 800455c: 8009883a mov r4,r16 + 8004560: a8bfffc5 stb r2,-1(r21) + 8004564: 01400284 movi r5,10 + 8004568: 800cf000 call 800cf00 <__divsi3> + 800456c: 80c01908 cmpgei r3,r16,100 + 8004570: a93fffc4 addi r4,r21,-1 + 8004574: 183ff31e bne r3,zero,8004544 <___vfprintf_internal_r+0x1700> + 8004578: 10800c04 addi r2,r2,48 + 800457c: 20bfffc5 stb r2,-1(r4) + 8004580: a8ffff84 addi r3,r21,-2 + 8004584: d9001bc4 addi r4,sp,111 + 8004588: 9811883a mov r8,r19 + 800458c: dc000717 ldw r16,28(sp) + 8004590: db000f17 ldw r12,60(sp) + 8004594: a027883a mov r19,r20 + 8004598: 1902732e bgeu r3,r4,8004f68 <___vfprintf_internal_r+0x2124> + 800459c: d90018c4 addi r4,sp,99 + 80045a0: 00000106 br 80045a8 <___vfprintf_internal_r+0x1764> + 80045a4: 18800003 ldbu r2,0(r3) + 80045a8: 21000044 addi r4,r4,1 + 80045ac: 20bfffc5 stb r2,-1(r4) + 80045b0: 18c00044 addi r3,r3,1 + 80045b4: d8801bc4 addi r2,sp,111 + 80045b8: 18bffa1e bne r3,r2,80045a4 <___vfprintf_internal_r+0x1760> + 80045bc: d8801c44 addi r2,sp,113 + 80045c0: d8c018c4 addi r3,sp,99 + 80045c4: 1545c83a sub r2,r2,r21 + 80045c8: 1885883a add r2,r3,r2 + 80045cc: d8c01844 addi r3,sp,97 + 80045d0: 10c5c83a sub r2,r2,r3 + 80045d4: d8801115 stw r2,68(sp) + 80045d8: d8c00817 ldw r3,32(sp) + 80045dc: d9001117 ldw r4,68(sp) + 80045e0: 18800088 cmpgei r2,r3,2 + 80045e4: 1929883a add r20,r3,r4 + 80045e8: 10024926 beq r2,zero,8004f10 <___vfprintf_internal_r+0x20cc> + 80045ec: d8800b17 ldw r2,44(sp) + 80045f0: a0a9883a add r20,r20,r2 + 80045f4: a02b883a mov r21,r20 + 80045f8: a000010e bge r20,zero,8004600 <___vfprintf_internal_r+0x17bc> + 80045fc: 002b883a mov r21,zero + 8004600: d8000715 stw zero,28(sp) + 8004604: 00013f06 br 8004b04 <___vfprintf_internal_r+0x1cc0> + 8004608: 00800c04 movi r2,48 + 800460c: d8801585 stb r2,86(sp) + 8004610: df0015c5 stb fp,87(sp) + 8004614: 63000094 ori r12,r12,2 + 8004618: 00800084 movi r2,2 + 800461c: 003ce406 br 80039b0 <___vfprintf_internal_r+0xb6c> + 8004620: d9400417 ldw r5,16(sp) + 8004624: 20800017 ldw r2,0(r4) + 8004628: d8c00615 stw r3,24(sp) + 800462c: 2809d7fa srai r4,r5,31 + 8004630: 11400015 stw r5,0(r2) + 8004634: 11000115 stw r4,4(r2) + 8004638: 003a3706 br 8002f18 <___vfprintf_internal_r+0xd4> + 800463c: 0463c83a sub r17,zero,r17 + 8004640: d8800615 stw r2,24(sp) + 8004644: 003b1806 br 80032a8 <___vfprintf_internal_r+0x464> + 8004648: 2039883a mov fp,r4 + 800464c: 073eda16 blt zero,fp,80041b8 <___vfprintf_internal_r+0x1374> + 8004650: 003ee306 br 80041e0 <___vfprintf_internal_r+0x139c> + 8004654: 9080004c andi r2,r18,1 + 8004658: 103ee81e bne r2,zero,80041fc <___vfprintf_internal_r+0x13b8> + 800465c: d8800817 ldw r2,32(sp) + 8004660: d9400717 ldw r5,28(sp) + 8004664: 1105c83a sub r2,r2,r4 + 8004668: 2900500e bge r5,r4,80047ac <___vfprintf_internal_r+0x1968> + 800466c: 1039883a mov fp,r2 + 8004670: 003f0006 br 8004274 <___vfprintf_internal_r+0x1430> + 8004674: d9000517 ldw r4,20(sp) + 8004678: d9801c04 addi r6,sp,112 + 800467c: 980b883a mov r5,r19 + 8004680: 800a3f80 call 800a3f8 <__sprint_r> + 8004684: 103ace1e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 8004688: df001d17 ldw fp,116(sp) + 800468c: d8c01e17 ldw r3,120(sp) + 8004690: da002b04 addi r8,sp,172 + 8004694: e7000044 addi fp,fp,1 + 8004698: b815883a mov r10,r23 + 800469c: 003e4f06 br 8003fdc <___vfprintf_internal_r+0x1198> + 80046a0: b7000043 ldbu fp,1(r22) + 80046a4: 63000814 ori r12,r12,32 + 80046a8: b5800044 addi r22,r22,1 + 80046ac: e2803fcc andi r10,fp,255 + 80046b0: 5280201c xori r10,r10,128 + 80046b4: 52bfe004 addi r10,r10,-128 + 80046b8: 003a3d06 br 8002fb0 <___vfprintf_internal_r+0x16c> + 80046bc: d9000517 ldw r4,20(sp) + 80046c0: d9801c04 addi r6,sp,112 + 80046c4: 980b883a mov r5,r19 + 80046c8: 800a3f80 call 800a3f8 <__sprint_r> + 80046cc: 103abc1e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 80046d0: d8c01e17 ldw r3,120(sp) + 80046d4: b811883a mov r8,r23 + 80046d8: 003d4806 br 8003bfc <___vfprintf_internal_r+0xdb8> + 80046dc: 0039883a mov fp,zero + 80046e0: 003ec006 br 80041e4 <___vfprintf_internal_r+0x13a0> + 80046e4: 588001f0 cmpltui r2,r11,7 + 80046e8: 5829883a mov r20,r11 + 80046ec: 10013b26 beq r2,zero,8004bdc <___vfprintf_internal_r+0x1d98> + 80046f0: 04020134 movhi r16,2052 + 80046f4: a02b883a mov r21,r20 + 80046f8: dc800615 stw r18,24(sp) + 80046fc: 841d2504 addi r16,r16,29844 + 8004700: 003b6906 br 80034a8 <___vfprintf_internal_r+0x664> + 8004704: 03020134 movhi r12,2052 + 8004708: e1000450 cmplti r4,fp,17 + 800470c: 631d2784 addi r12,r12,29854 + 8004710: d8801d17 ldw r2,116(sp) + 8004714: 20010b1e bne r4,zero,8004b44 <___vfprintf_internal_r+0x1d00> + 8004718: b009883a mov r4,r22 + 800471c: dc000e15 stw r16,56(sp) + 8004720: dc800f15 stw r18,60(sp) + 8004724: 882d883a mov r22,r17 + 8004728: 05000404 movi r20,16 + 800472c: e023883a mov r17,fp + 8004730: dc000517 ldw r16,20(sp) + 8004734: 6025883a mov r18,r12 + 8004738: 2039883a mov fp,r4 + 800473c: 00000406 br 8004750 <___vfprintf_internal_r+0x190c> + 8004740: 42000204 addi r8,r8,8 + 8004744: 8c7ffc04 addi r17,r17,-16 + 8004748: 89000448 cmpgei r4,r17,17 + 800474c: 2000f626 beq r4,zero,8004b28 <___vfprintf_internal_r+0x1ce4> + 8004750: 10800044 addi r2,r2,1 + 8004754: 18c00404 addi r3,r3,16 + 8004758: 44800015 stw r18,0(r8) + 800475c: 45000115 stw r20,4(r8) + 8004760: d8c01e15 stw r3,120(sp) + 8004764: d8801d15 stw r2,116(sp) + 8004768: 11000208 cmpgei r4,r2,8 + 800476c: 203ff426 beq r4,zero,8004740 <___vfprintf_internal_r+0x18fc> + 8004770: d9801c04 addi r6,sp,112 + 8004774: 980b883a mov r5,r19 + 8004778: 8009883a mov r4,r16 + 800477c: 800a3f80 call 800a3f8 <__sprint_r> + 8004780: 103a8f1e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 8004784: d8c01e17 ldw r3,120(sp) + 8004788: d8801d17 ldw r2,116(sp) + 800478c: b811883a mov r8,r23 + 8004790: 003fec06 br 8004744 <___vfprintf_internal_r+0x1900> + 8004794: d8800617 ldw r2,24(sp) + 8004798: 10800017 ldw r2,0(r2) + 800479c: d8c00615 stw r3,24(sp) + 80047a0: d8c00417 ldw r3,16(sp) + 80047a4: 10c00015 stw r3,0(r2) + 80047a8: 0039db06 br 8002f18 <___vfprintf_internal_r+0xd4> + 80047ac: d9000817 ldw r4,32(sp) + 80047b0: d9400717 ldw r5,28(sp) + 80047b4: 2179c83a sub fp,r4,r5 + 80047b8: 003ea106 br 8004240 <___vfprintf_internal_r+0x13fc> + 80047bc: d9000517 ldw r4,20(sp) + 80047c0: d9801c04 addi r6,sp,112 + 80047c4: 980b883a mov r5,r19 + 80047c8: 800a3f80 call 800a3f8 <__sprint_r> + 80047cc: 103a7c1e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 80047d0: d8c01e17 ldw r3,120(sp) + 80047d4: dd001d17 ldw r20,116(sp) + 80047d8: b815883a mov r10,r23 + 80047dc: 003ddf06 br 8003f5c <___vfprintf_internal_r+0x1118> + 80047e0: d9000517 ldw r4,20(sp) + 80047e4: d9801c04 addi r6,sp,112 + 80047e8: 980b883a mov r5,r19 + 80047ec: 800a3f80 call 800a3f8 <__sprint_r> + 80047f0: 103a731e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 80047f4: d8c01e17 ldw r3,120(sp) + 80047f8: dd001d17 ldw r20,116(sp) + 80047fc: b815883a mov r10,r23 + 8004800: 003dcb06 br 8003f30 <___vfprintf_internal_r+0x10ec> + 8004804: d8801d17 ldw r2,116(sp) + 8004808: 01420134 movhi r5,2052 + 800480c: 295d2704 addi r5,r5,29852 + 8004810: 10800044 addi r2,r2,1 + 8004814: 18c00044 addi r3,r3,1 + 8004818: 41400015 stw r5,0(r8) + 800481c: 01400044 movi r5,1 + 8004820: d8801d15 stw r2,116(sp) + 8004824: 41400115 stw r5,4(r8) + 8004828: d8c01e15 stw r3,120(sp) + 800482c: 10800208 cmpgei r2,r2,8 + 8004830: 103d871e bne r2,zero,8003e50 <___vfprintf_internal_r+0x100c> + 8004834: 42000204 addi r8,r8,8 + 8004838: 003d8d06 br 8003e70 <___vfprintf_internal_r+0x102c> + 800483c: d9000517 ldw r4,20(sp) + 8004840: d9801c04 addi r6,sp,112 + 8004844: 980b883a mov r5,r19 + 8004848: dac01015 stw r11,64(sp) + 800484c: db400f15 stw r13,60(sp) + 8004850: db800e15 stw r14,56(sp) + 8004854: 800a3f80 call 800a3f8 <__sprint_r> + 8004858: 103a591e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 800485c: d8c01e17 ldw r3,120(sp) + 8004860: b811883a mov r8,r23 + 8004864: dac01017 ldw r11,64(sp) + 8004868: db400f17 ldw r13,60(sp) + 800486c: db800e17 ldw r14,56(sp) + 8004870: 003b1806 br 80034d4 <___vfprintf_internal_r+0x690> + 8004874: d9000517 ldw r4,20(sp) + 8004878: d9801c04 addi r6,sp,112 + 800487c: 980b883a mov r5,r19 + 8004880: 800a3f80 call 800a3f8 <__sprint_r> + 8004884: 103a4e1e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 8004888: b811883a mov r8,r23 + 800488c: 003cc706 br 8003bac <___vfprintf_internal_r+0xd68> + 8004890: d9000517 ldw r4,20(sp) + 8004894: d9801c04 addi r6,sp,112 + 8004898: 980b883a mov r5,r19 + 800489c: dac00e15 stw r11,56(sp) + 80048a0: 800a3f80 call 800a3f8 <__sprint_r> + 80048a4: 103a461e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 80048a8: d8c01e17 ldw r3,120(sp) + 80048ac: b811883a mov r8,r23 + 80048b0: dac00e17 ldw r11,56(sp) + 80048b4: 003b2406 br 8003548 <___vfprintf_internal_r+0x704> + 80048b8: 10c00060 cmpeqi r3,r2,1 + 80048bc: 9019883a mov r12,r18 + 80048c0: 183bed26 beq r3,zero,8003878 <___vfprintf_internal_r+0xa34> + 80048c4: 003c6d06 br 8003a7c <___vfprintf_internal_r+0xc38> + 80048c8: d8800d17 ldw r2,52(sp) + 80048cc: d9400b17 ldw r5,44(sp) + 80048d0: 40800015 stw r2,0(r8) + 80048d4: d8801d17 ldw r2,116(sp) + 80048d8: 28c7883a add r3,r5,r3 + 80048dc: 41400115 stw r5,4(r8) + 80048e0: 10800044 addi r2,r2,1 + 80048e4: d8c01e15 stw r3,120(sp) + 80048e8: d8801d15 stw r2,116(sp) + 80048ec: 11400208 cmpgei r5,r2,8 + 80048f0: 2800d31e bne r5,zero,8004c40 <___vfprintf_internal_r+0x1dfc> + 80048f4: 42000204 addi r8,r8,8 + 80048f8: 203d6e0e bge r4,zero,8003eb4 <___vfprintf_internal_r+0x1070> + 80048fc: 03020134 movhi r12,2052 + 8004900: 217ffc08 cmpgei r5,r4,-16 + 8004904: 631d2784 addi r12,r12,29854 + 8004908: 0129c83a sub r20,zero,r4 + 800490c: 28014a1e bne r5,zero,8004e38 <___vfprintf_internal_r+0x1ff4> + 8004910: dc000715 stw r16,28(sp) + 8004914: 07000404 movi fp,16 + 8004918: a021883a mov r16,r20 + 800491c: 8829883a mov r20,r17 + 8004920: 6023883a mov r17,r12 + 8004924: 00000406 br 8004938 <___vfprintf_internal_r+0x1af4> + 8004928: 42000204 addi r8,r8,8 + 800492c: 843ffc04 addi r16,r16,-16 + 8004930: 81000448 cmpgei r4,r16,17 + 8004934: 20013c26 beq r4,zero,8004e28 <___vfprintf_internal_r+0x1fe4> + 8004938: 10800044 addi r2,r2,1 + 800493c: 18c00404 addi r3,r3,16 + 8004940: 44400015 stw r17,0(r8) + 8004944: 47000115 stw fp,4(r8) + 8004948: d8c01e15 stw r3,120(sp) + 800494c: d8801d15 stw r2,116(sp) + 8004950: 11000208 cmpgei r4,r2,8 + 8004954: 203ff426 beq r4,zero,8004928 <___vfprintf_internal_r+0x1ae4> + 8004958: d9000517 ldw r4,20(sp) + 800495c: d9801c04 addi r6,sp,112 + 8004960: 980b883a mov r5,r19 + 8004964: 800a3f80 call 800a3f8 <__sprint_r> + 8004968: 103a151e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 800496c: d8c01e17 ldw r3,120(sp) + 8004970: d8801d17 ldw r2,116(sp) + 8004974: b811883a mov r8,r23 + 8004978: 003fec06 br 800492c <___vfprintf_internal_r+0x1ae8> + 800497c: 8009883a mov r4,r16 + 8004980: 8002dac0 call 8002dac + 8004984: 1029883a mov r20,r2 + 8004988: 102b883a mov r21,r2 + 800498c: dc800615 stw r18,24(sp) + 8004990: db000717 ldw r12,28(sp) + 8004994: da000e17 ldw r8,56(sp) + 8004998: 003ac306 br 80034a8 <___vfprintf_internal_r+0x664> + 800499c: 8817883a mov r11,r17 + 80049a0: 9019883a mov r12,r18 + 80049a4: dc400e17 ldw r17,56(sp) + 80049a8: dc800717 ldw r18,28(sp) + 80049ac: a7000044 addi fp,r20,1 + 80049b0: 50800204 addi r2,r10,8 + 80049b4: 1ac7883a add r3,r3,r11 + 80049b8: 53000015 stw r12,0(r10) + 80049bc: 52c00115 stw r11,4(r10) + 80049c0: d8c01e15 stw r3,120(sp) + 80049c4: df001d15 stw fp,116(sp) + 80049c8: e1000208 cmpgei r4,fp,8 + 80049cc: 203f291e bne r4,zero,8004674 <___vfprintf_internal_r+0x1830> + 80049d0: e7000044 addi fp,fp,1 + 80049d4: 12000204 addi r8,r2,8 + 80049d8: 1015883a mov r10,r2 + 80049dc: 003d7f06 br 8003fdc <___vfprintf_internal_r+0x1198> + 80049e0: 8819883a mov r12,r17 + 80049e4: dc400717 ldw r17,28(sp) + 80049e8: 10800044 addi r2,r2,1 + 80049ec: 1c07883a add r3,r3,r16 + 80049f0: d8801d15 stw r2,116(sp) + 80049f4: 43000015 stw r12,0(r8) + 80049f8: 44000115 stw r16,4(r8) + 80049fc: d8c01e15 stw r3,120(sp) + 8004a00: 10800208 cmpgei r2,r2,8 + 8004a04: 103add26 beq r2,zero,800357c <___vfprintf_internal_r+0x738> + 8004a08: 003d3306 br 8003ed8 <___vfprintf_internal_r+0x1094> + 8004a0c: d8800615 stw r2,24(sp) + 8004a10: 0029883a mov r20,zero + 8004a14: 0005883a mov r2,zero + 8004a18: 003be506 br 80039b0 <___vfprintf_internal_r+0xb6c> + 8004a1c: d8800615 stw r2,24(sp) + 8004a20: 0029883a mov r20,zero + 8004a24: 00800044 movi r2,1 + 8004a28: 003be106 br 80039b0 <___vfprintf_internal_r+0xb6c> + 8004a2c: d8801a04 addi r2,sp,104 + 8004a30: d8800315 stw r2,12(sp) + 8004a34: d9400917 ldw r5,36(sp) + 8004a38: d8801704 addi r2,sp,92 + 8004a3c: d9000517 ldw r4,20(sp) + 8004a40: d8800215 stw r2,8(sp) + 8004a44: d8801604 addi r2,sp,88 + 8004a48: dac00015 stw r11,0(sp) + 8004a4c: d8800115 stw r2,4(sp) + 8004a50: 01c000c4 movi r7,3 + 8004a54: a80d883a mov r6,r21 + 8004a58: da001215 stw r8,72(sp) + 8004a5c: db001015 stw r12,64(sp) + 8004a60: dac00815 stw r11,32(sp) + 8004a64: 80053ec0 call 80053ec <_dtoa_r> + 8004a68: dac00817 ldw r11,32(sp) + 8004a6c: 1021883a mov r16,r2 + 8004a70: db001017 ldw r12,64(sp) + 8004a74: 12e9883a add r20,r2,r11 + 8004a78: 80800007 ldb r2,0(r16) + 8004a7c: da001217 ldw r8,72(sp) + 8004a80: 10800c20 cmpeqi r2,r2,48 + 8004a84: 10005b1e bne r2,zero,8004bf4 <___vfprintf_internal_r+0x1db0> + 8004a88: d8801617 ldw r2,88(sp) + 8004a8c: a0a9883a add r20,r20,r2 + 8004a90: d9000917 ldw r4,36(sp) + 8004a94: 000d883a mov r6,zero + 8004a98: 000f883a mov r7,zero + 8004a9c: a80b883a mov r5,r21 + 8004aa0: da001215 stw r8,72(sp) + 8004aa4: dac01015 stw r11,64(sp) + 8004aa8: db000815 stw r12,32(sp) + 8004aac: 800e3000 call 800e300 <__eqdf2> + 8004ab0: db000817 ldw r12,32(sp) + 8004ab4: dac01017 ldw r11,64(sp) + 8004ab8: da001217 ldw r8,72(sp) + 8004abc: 1000891e bne r2,zero,8004ce4 <___vfprintf_internal_r+0x1ea0> + 8004ac0: a005883a mov r2,r20 + 8004ac4: 1405c83a sub r2,r2,r16 + 8004ac8: d8c00717 ldw r3,28(sp) + 8004acc: d8800815 stw r2,32(sp) + 8004ad0: d8801617 ldw r2,88(sp) + 8004ad4: 18c011d8 cmpnei r3,r3,71 + 8004ad8: d8800715 stw r2,28(sp) + 8004adc: 183e8426 beq r3,zero,80044f0 <___vfprintf_internal_r+0x16ac> + 8004ae0: d8800f17 ldw r2,60(sp) + 8004ae4: 103e8726 beq r2,zero,8004504 <___vfprintf_internal_r+0x16c0> + 8004ae8: d8c00717 ldw r3,28(sp) + 8004aec: 6080004c andi r2,r12,1 + 8004af0: 12c4b03a or r2,r2,r11 + 8004af4: 00c10d0e bge zero,r3,8004f2c <___vfprintf_internal_r+0x20e8> + 8004af8: 1000f11e bne r2,zero,8004ec0 <___vfprintf_internal_r+0x207c> + 8004afc: dd000717 ldw r20,28(sp) + 8004b00: a02b883a mov r21,r20 + 8004b04: d8800e07 ldb r2,56(sp) + 8004b08: 10007f26 beq r2,zero,8004d08 <___vfprintf_internal_r+0x1ec4> + 8004b0c: 00800b44 movi r2,45 + 8004b10: d8801545 stb r2,85(sp) + 8004b14: 0017883a mov r11,zero + 8004b18: 003be506 br 8003ab0 <___vfprintf_internal_r+0xc6c> + 8004b1c: 04020134 movhi r16,2052 + 8004b20: 841d1704 addi r16,r16,29788 + 8004b24: 003b3406 br 80037f8 <___vfprintf_internal_r+0x9b4> + 8004b28: 9019883a mov r12,r18 + 8004b2c: dc000e17 ldw r16,56(sp) + 8004b30: dc800f17 ldw r18,60(sp) + 8004b34: e009883a mov r4,fp + 8004b38: 8839883a mov fp,r17 + 8004b3c: b023883a mov r17,r22 + 8004b40: 202d883a mov r22,r4 + 8004b44: 10800044 addi r2,r2,1 + 8004b48: 1f07883a add r3,r3,fp + 8004b4c: d8801d15 stw r2,116(sp) + 8004b50: 43000015 stw r12,0(r8) + 8004b54: 47000115 stw fp,4(r8) + 8004b58: d8c01e15 stw r3,120(sp) + 8004b5c: 10800208 cmpgei r2,r2,8 + 8004b60: 1000421e bne r2,zero,8004c6c <___vfprintf_internal_r+0x1e28> + 8004b64: 42000204 addi r8,r8,8 + 8004b68: 003da106 br 80041f0 <___vfprintf_internal_r+0x13ac> + 8004b6c: 00800b44 movi r2,45 + 8004b70: d8801545 stb r2,85(sp) + 8004b74: 03400b44 movi r13,45 + 8004b78: 003b1b06 br 80037e8 <___vfprintf_internal_r+0x9a4> + 8004b7c: 8819883a mov r12,r17 + 8004b80: dc400717 ldw r17,28(sp) + 8004b84: 10800044 addi r2,r2,1 + 8004b88: 1f07883a add r3,r3,fp + 8004b8c: d8801d15 stw r2,116(sp) + 8004b90: 43000015 stw r12,0(r8) + 8004b94: 47000115 stw fp,4(r8) + 8004b98: d8c01e15 stw r3,120(sp) + 8004b9c: 10800208 cmpgei r2,r2,8 + 8004ba0: 103a7626 beq r2,zero,800357c <___vfprintf_internal_r+0x738> + 8004ba4: 003ccc06 br 8003ed8 <___vfprintf_internal_r+0x1094> + 8004ba8: d9000517 ldw r4,20(sp) + 8004bac: d9801c04 addi r6,sp,112 + 8004bb0: 980b883a mov r5,r19 + 8004bb4: 800a3f80 call 800a3f8 <__sprint_r> + 8004bb8: 1039811e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 8004bbc: d9001617 ldw r4,88(sp) + 8004bc0: d8c01e17 ldw r3,120(sp) + 8004bc4: b811883a mov r8,r23 + 8004bc8: 003d9806 br 800422c <___vfprintf_internal_r+0x13e8> + 8004bcc: 1560003c xorhi r21,r2,32768 + 8004bd0: 00800b44 movi r2,45 + 8004bd4: d8800e05 stb r2,56(sp) + 8004bd8: 003e1d06 br 8004450 <___vfprintf_internal_r+0x160c> + 8004bdc: 05000184 movi r20,6 + 8004be0: 003ec306 br 80046f0 <___vfprintf_internal_r+0x18ac> + 8004be4: 002b883a mov r21,zero + 8004be8: 003a0706 br 8003408 <___vfprintf_internal_r+0x5c4> + 8004bec: d9401545 stb r5,85(sp) + 8004bf0: 00399106 br 8003238 <___vfprintf_internal_r+0x3f4> + 8004bf4: d9000917 ldw r4,36(sp) + 8004bf8: 000d883a mov r6,zero + 8004bfc: 000f883a mov r7,zero + 8004c00: a80b883a mov r5,r21 + 8004c04: da001215 stw r8,72(sp) + 8004c08: dac01015 stw r11,64(sp) + 8004c0c: db000815 stw r12,32(sp) + 8004c10: 800e3000 call 800e300 <__eqdf2> + 8004c14: db000817 ldw r12,32(sp) + 8004c18: dac01017 ldw r11,64(sp) + 8004c1c: da001217 ldw r8,72(sp) + 8004c20: 103f9926 beq r2,zero,8004a88 <___vfprintf_internal_r+0x1c44> + 8004c24: 00800044 movi r2,1 + 8004c28: 12c5c83a sub r2,r2,r11 + 8004c2c: d8801615 stw r2,88(sp) + 8004c30: 003f9606 br 8004a8c <___vfprintf_internal_r+0x1c48> + 8004c34: 583e011e bne r11,zero,800443c <___vfprintf_internal_r+0x15f8> + 8004c38: 02c00044 movi r11,1 + 8004c3c: 003dff06 br 800443c <___vfprintf_internal_r+0x15f8> + 8004c40: d9000517 ldw r4,20(sp) + 8004c44: d9801c04 addi r6,sp,112 + 8004c48: 980b883a mov r5,r19 + 8004c4c: 800a3f80 call 800a3f8 <__sprint_r> + 8004c50: 10395b1e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 8004c54: d9001617 ldw r4,88(sp) + 8004c58: d8c01e17 ldw r3,120(sp) + 8004c5c: d8801d17 ldw r2,116(sp) + 8004c60: b811883a mov r8,r23 + 8004c64: 203c930e bge r4,zero,8003eb4 <___vfprintf_internal_r+0x1070> + 8004c68: 003f2406 br 80048fc <___vfprintf_internal_r+0x1ab8> + 8004c6c: d9000517 ldw r4,20(sp) + 8004c70: d9801c04 addi r6,sp,112 + 8004c74: 980b883a mov r5,r19 + 8004c78: 800a3f80 call 800a3f8 <__sprint_r> + 8004c7c: 1039501e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 8004c80: d8c01e17 ldw r3,120(sp) + 8004c84: b811883a mov r8,r23 + 8004c88: 003d5906 br 80041f0 <___vfprintf_internal_r+0x13ac> + 8004c8c: d8801a04 addi r2,sp,104 + 8004c90: d8800315 stw r2,12(sp) + 8004c94: d9400917 ldw r5,36(sp) + 8004c98: d8801704 addi r2,sp,92 + 8004c9c: d9000517 ldw r4,20(sp) + 8004ca0: 5d000044 addi r20,r11,1 + 8004ca4: d8800215 stw r2,8(sp) + 8004ca8: d8801604 addi r2,sp,88 + 8004cac: d8800115 stw r2,4(sp) + 8004cb0: dd000015 stw r20,0(sp) + 8004cb4: 01c00084 movi r7,2 + 8004cb8: a80d883a mov r6,r21 + 8004cbc: dac00815 stw r11,32(sp) + 8004cc0: 80053ec0 call 80053ec <_dtoa_r> + 8004cc4: dac00817 ldw r11,32(sp) + 8004cc8: db001017 ldw r12,64(sp) + 8004ccc: da001217 ldw r8,72(sp) + 8004cd0: 1021883a mov r16,r2 + 8004cd4: e08011d8 cmpnei r2,fp,71 + 8004cd8: 103dfb26 beq r2,zero,80044c8 <___vfprintf_internal_r+0x1684> + 8004cdc: 8529883a add r20,r16,r20 + 8004ce0: 003f6b06 br 8004a90 <___vfprintf_internal_r+0x1c4c> + 8004ce4: d8801a17 ldw r2,104(sp) + 8004ce8: 01000c04 movi r4,48 + 8004cec: 153f752e bgeu r2,r20,8004ac4 <___vfprintf_internal_r+0x1c80> + 8004cf0: 10c00044 addi r3,r2,1 + 8004cf4: d8c01a15 stw r3,104(sp) + 8004cf8: 11000005 stb r4,0(r2) + 8004cfc: d8801a17 ldw r2,104(sp) + 8004d00: 153ffb36 bltu r2,r20,8004cf0 <___vfprintf_internal_r+0x1eac> + 8004d04: 003f6f06 br 8004ac4 <___vfprintf_internal_r+0x1c80> + 8004d08: db401543 ldbu r13,85(sp) + 8004d0c: 0017883a mov r11,zero + 8004d10: 003b6306 br 8003aa0 <___vfprintf_internal_r+0xc5c> + 8004d14: d8800717 ldw r2,28(sp) + 8004d18: d8c00817 ldw r3,32(sp) + 8004d1c: 10c02216 blt r2,r3,8004da8 <___vfprintf_internal_r+0x1f64> + 8004d20: 6300004c andi r12,r12,1 + 8004d24: 60005f1e bne r12,zero,8004ea4 <___vfprintf_internal_r+0x2060> + 8004d28: 102b883a mov r21,r2 + 8004d2c: 1000010e bge r2,zero,8004d34 <___vfprintf_internal_r+0x1ef0> + 8004d30: 002b883a mov r21,zero + 8004d34: dd000717 ldw r20,28(sp) + 8004d38: 070019c4 movi fp,103 + 8004d3c: 003f7106 br 8004b04 <___vfprintf_internal_r+0x1cc0> + 8004d40: d9000517 ldw r4,20(sp) + 8004d44: d9801c04 addi r6,sp,112 + 8004d48: 980b883a mov r5,r19 + 8004d4c: 800a3f80 call 800a3f8 <__sprint_r> + 8004d50: 10391b1e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 8004d54: d8c01e17 ldw r3,120(sp) + 8004d58: b811883a mov r8,r23 + 8004d5c: e03d210e bge fp,zero,80041e4 <___vfprintf_internal_r+0x13a0> + 8004d60: 003e5e06 br 80046dc <___vfprintf_internal_r+0x1898> + 8004d64: 02c00184 movi r11,6 + 8004d68: 003db406 br 800443c <___vfprintf_internal_r+0x15f8> + 8004d6c: d9000517 ldw r4,20(sp) + 8004d70: d9801c04 addi r6,sp,112 + 8004d74: 980b883a mov r5,r19 + 8004d78: 800a3f80 call 800a3f8 <__sprint_r> + 8004d7c: 1039101e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 8004d80: d8801617 ldw r2,88(sp) + 8004d84: d9000817 ldw r4,32(sp) + 8004d88: d8c01e17 ldw r3,120(sp) + 8004d8c: b811883a mov r8,r23 + 8004d90: 2085c83a sub r2,r4,r2 + 8004d94: 003d3706 br 8004274 <___vfprintf_internal_r+0x1430> + 8004d98: 582b883a mov r21,r11 + 8004d9c: dc800615 stw r18,24(sp) + 8004da0: 5829883a mov r20,r11 + 8004da4: 0039c006 br 80034a8 <___vfprintf_internal_r+0x664> + 8004da8: d8800817 ldw r2,32(sp) + 8004dac: d8c00b17 ldw r3,44(sp) + 8004db0: 10e9883a add r20,r2,r3 + 8004db4: d8800717 ldw r2,28(sp) + 8004db8: 00800316 blt zero,r2,8004dc8 <___vfprintf_internal_r+0x1f84> + 8004dbc: d8800717 ldw r2,28(sp) + 8004dc0: a0b9c83a sub fp,r20,r2 + 8004dc4: e5000044 addi r20,fp,1 + 8004dc8: a02b883a mov r21,r20 + 8004dcc: a0003a16 blt r20,zero,8004eb8 <___vfprintf_internal_r+0x2074> + 8004dd0: 070019c4 movi fp,103 + 8004dd4: 003f4b06 br 8004b04 <___vfprintf_internal_r+0x1cc0> + 8004dd8: d9401545 stb r5,85(sp) + 8004ddc: 003ac506 br 80038f4 <___vfprintf_internal_r+0xab0> + 8004de0: d9401545 stb r5,85(sp) + 8004de4: 003a2506 br 800367c <___vfprintf_internal_r+0x838> + 8004de8: d9401545 stb r5,85(sp) + 8004dec: 003a3306 br 80036bc <___vfprintf_internal_r+0x878> + 8004df0: d9401545 stb r5,85(sp) + 8004df4: 00398806 br 8003418 <___vfprintf_internal_r+0x5d4> + 8004df8: d9401545 stb r5,85(sp) + 8004dfc: 00395f06 br 800337c <___vfprintf_internal_r+0x538> + 8004e00: d9401545 stb r5,85(sp) + 8004e04: 00394b06 br 8003334 <___vfprintf_internal_r+0x4f0> + 8004e08: d9401545 stb r5,85(sp) + 8004e0c: 003a3b06 br 80036fc <___vfprintf_internal_r+0x8b8> + 8004e10: d9401545 stb r5,85(sp) + 8004e14: 003a8106 br 800381c <___vfprintf_internal_r+0x9d8> + 8004e18: d9401545 stb r5,85(sp) + 8004e1c: 003a4706 br 800373c <___vfprintf_internal_r+0x8f8> + 8004e20: d9401545 stb r5,85(sp) + 8004e24: 003ac506 br 800393c <___vfprintf_internal_r+0xaf8> + 8004e28: 8819883a mov r12,r17 + 8004e2c: a023883a mov r17,r20 + 8004e30: 8029883a mov r20,r16 + 8004e34: dc000717 ldw r16,28(sp) + 8004e38: 10800044 addi r2,r2,1 + 8004e3c: 1d07883a add r3,r3,r20 + 8004e40: 43000015 stw r12,0(r8) + 8004e44: 45000115 stw r20,4(r8) + 8004e48: d8c01e15 stw r3,120(sp) + 8004e4c: d8801d15 stw r2,116(sp) + 8004e50: 11000208 cmpgei r4,r2,8 + 8004e54: 203c1626 beq r4,zero,8003eb0 <___vfprintf_internal_r+0x106c> + 8004e58: d9000517 ldw r4,20(sp) + 8004e5c: d9801c04 addi r6,sp,112 + 8004e60: 980b883a mov r5,r19 + 8004e64: 800a3f80 call 800a3f8 <__sprint_r> + 8004e68: 1038d51e bne r2,zero,80031c0 <___vfprintf_internal_r+0x37c> + 8004e6c: d8c01e17 ldw r3,120(sp) + 8004e70: d8801d17 ldw r2,116(sp) + 8004e74: b811883a mov r8,r23 + 8004e78: 003c0e06 br 8003eb4 <___vfprintf_internal_r+0x1070> + 8004e7c: 00bfffc4 movi r2,-1 + 8004e80: d8800415 stw r2,16(sp) + 8004e84: 0038d106 br 80031cc <___vfprintf_internal_r+0x388> + 8004e88: 00800c04 movi r2,48 + 8004e8c: a0c00c04 addi r3,r20,48 + 8004e90: d88018c5 stb r2,99(sp) + 8004e94: 00800104 movi r2,4 + 8004e98: d8c01905 stb r3,100(sp) + 8004e9c: d8801115 stw r2,68(sp) + 8004ea0: 003dcd06 br 80045d8 <___vfprintf_internal_r+0x1794> + 8004ea4: d8800717 ldw r2,28(sp) + 8004ea8: d8c00b17 ldw r3,44(sp) + 8004eac: 10e9883a add r20,r2,r3 + 8004eb0: a02b883a mov r21,r20 + 8004eb4: a03fc60e bge r20,zero,8004dd0 <___vfprintf_internal_r+0x1f8c> + 8004eb8: 002b883a mov r21,zero + 8004ebc: 003fc406 br 8004dd0 <___vfprintf_internal_r+0x1f8c> + 8004ec0: d8800b17 ldw r2,44(sp) + 8004ec4: 1885883a add r2,r3,r2 + 8004ec8: 12e9883a add r20,r2,r11 + 8004ecc: a02b883a mov r21,r20 + 8004ed0: a03f0c0e bge r20,zero,8004b04 <___vfprintf_internal_r+0x1cc0> + 8004ed4: 002b883a mov r21,zero + 8004ed8: 003f0a06 br 8004b04 <___vfprintf_internal_r+0x1cc0> + 8004edc: d8800a17 ldw r2,40(sp) + 8004ee0: 10001d16 blt r2,zero,8004f58 <___vfprintf_internal_r+0x2114> + 8004ee4: db401543 ldbu r13,85(sp) + 8004ee8: e0801210 cmplti r2,fp,72 + 8004eec: 1000171e bne r2,zero,8004f4c <___vfprintf_internal_r+0x2108> + 8004ef0: 04020134 movhi r16,2052 + 8004ef4: 841d1a04 addi r16,r16,29800 + 8004ef8: 003a3f06 br 80037f8 <___vfprintf_internal_r+0x9b4> + 8004efc: 00c00044 movi r3,1 + 8004f00: 18a9c83a sub r20,r3,r2 + 8004f04: 00800b44 movi r2,45 + 8004f08: d8801885 stb r2,98(sp) + 8004f0c: 003d8406 br 8004520 <___vfprintf_internal_r+0x16dc> + 8004f10: 6080004c andi r2,r12,1 + 8004f14: d8800715 stw r2,28(sp) + 8004f18: 103db41e bne r2,zero,80045ec <___vfprintf_internal_r+0x17a8> + 8004f1c: 003feb06 br 8004ecc <___vfprintf_internal_r+0x2088> + 8004f20: 4005883a mov r2,r8 + 8004f24: 631d2784 addi r12,r12,29854 + 8004f28: 003ea206 br 80049b4 <___vfprintf_internal_r+0x1b70> + 8004f2c: 1000031e bne r2,zero,8004f3c <___vfprintf_internal_r+0x20f8> + 8004f30: 05400044 movi r21,1 + 8004f34: 05000044 movi r20,1 + 8004f38: 003ef206 br 8004b04 <___vfprintf_internal_r+0x1cc0> + 8004f3c: d8800b17 ldw r2,44(sp) + 8004f40: 10800044 addi r2,r2,1 + 8004f44: 12e9883a add r20,r2,r11 + 8004f48: 003fe006 br 8004ecc <___vfprintf_internal_r+0x2088> + 8004f4c: 04020134 movhi r16,2052 + 8004f50: 841d1904 addi r16,r16,29796 + 8004f54: 003a2806 br 80037f8 <___vfprintf_internal_r+0x9b4> + 8004f58: 00800b44 movi r2,45 + 8004f5c: d8801545 stb r2,85(sp) + 8004f60: 03400b44 movi r13,45 + 8004f64: 003fe006 br 8004ee8 <___vfprintf_internal_r+0x20a4> + 8004f68: 00800084 movi r2,2 + 8004f6c: d8801115 stw r2,68(sp) + 8004f70: 003d9906 br 80045d8 <___vfprintf_internal_r+0x1794> + 8004f74: d8800617 ldw r2,24(sp) + 8004f78: 12c00017 ldw r11,0(r2) + 8004f7c: 10800104 addi r2,r2,4 + 8004f80: 5800010e bge r11,zero,8004f88 <___vfprintf_internal_r+0x2144> + 8004f84: 02ffffc4 movi r11,-1 + 8004f88: b7000043 ldbu fp,1(r22) + 8004f8c: d8800615 stw r2,24(sp) + 8004f90: 182d883a mov r22,r3 + 8004f94: e2803fcc andi r10,fp,255 + 8004f98: 5280201c xori r10,r10,128 + 8004f9c: 52bfe004 addi r10,r10,-128 + 8004fa0: 00380306 br 8002fb0 <___vfprintf_internal_r+0x16c> + +08004fa4 <__vfprintf_internal>: + 8004fa4: 00820174 movhi r2,2053 + 8004fa8: 300f883a mov r7,r6 + 8004fac: 280d883a mov r6,r5 + 8004fb0: 200b883a mov r5,r4 + 8004fb4: 1132af17 ldw r4,-13636(r2) + 8004fb8: 8002e441 jmpi 8002e44 <___vfprintf_internal_r> + +08004fbc <__sbprintf>: + 8004fbc: 2880030b ldhu r2,12(r5) + 8004fc0: 2b001917 ldw r12,100(r5) + 8004fc4: 2ac0038b ldhu r11,14(r5) + 8004fc8: 2a800717 ldw r10,28(r5) + 8004fcc: 2a400917 ldw r9,36(r5) + 8004fd0: defee204 addi sp,sp,-1144 + 8004fd4: da001a04 addi r8,sp,104 + 8004fd8: 00c10004 movi r3,1024 + 8004fdc: dc011a15 stw r16,1128(sp) + 8004fe0: 10bfff4c andi r2,r2,65533 + 8004fe4: 2821883a mov r16,r5 + 8004fe8: d80b883a mov r5,sp + 8004fec: dc811c15 stw r18,1136(sp) + 8004ff0: dc411b15 stw r17,1132(sp) + 8004ff4: dfc11d15 stw ra,1140(sp) + 8004ff8: 2025883a mov r18,r4 + 8004ffc: d880030d sth r2,12(sp) + 8005000: db001915 stw r12,100(sp) + 8005004: dac0038d sth r11,14(sp) + 8005008: da800715 stw r10,28(sp) + 800500c: da400915 stw r9,36(sp) + 8005010: da000015 stw r8,0(sp) + 8005014: da000415 stw r8,16(sp) + 8005018: d8c00215 stw r3,8(sp) + 800501c: d8c00515 stw r3,20(sp) + 8005020: d8000615 stw zero,24(sp) + 8005024: 8002e440 call 8002e44 <___vfprintf_internal_r> + 8005028: 1023883a mov r17,r2 + 800502c: 10000d0e bge r2,zero,8005064 <__sbprintf+0xa8> + 8005030: d880030b ldhu r2,12(sp) + 8005034: 1080100c andi r2,r2,64 + 8005038: 10000326 beq r2,zero,8005048 <__sbprintf+0x8c> + 800503c: 8080030b ldhu r2,12(r16) + 8005040: 10801014 ori r2,r2,64 + 8005044: 8080030d sth r2,12(r16) + 8005048: 8805883a mov r2,r17 + 800504c: dfc11d17 ldw ra,1140(sp) + 8005050: dc811c17 ldw r18,1136(sp) + 8005054: dc411b17 ldw r17,1132(sp) + 8005058: dc011a17 ldw r16,1128(sp) + 800505c: dec11e04 addi sp,sp,1144 + 8005060: f800283a ret + 8005064: d80b883a mov r5,sp + 8005068: 9009883a mov r4,r18 + 800506c: 8006cdc0 call 8006cdc <_fflush_r> + 8005070: 103fef26 beq r2,zero,8005030 <__sbprintf+0x74> + 8005074: 047fffc4 movi r17,-1 + 8005078: 003fed06 br 8005030 <__sbprintf+0x74> + +0800507c <__swsetup_r>: + 800507c: 00820174 movhi r2,2053 + 8005080: 10b2af17 ldw r2,-13636(r2) + 8005084: defffd04 addi sp,sp,-12 + 8005088: dc400115 stw r17,4(sp) + 800508c: dc000015 stw r16,0(sp) + 8005090: dfc00215 stw ra,8(sp) + 8005094: 2023883a mov r17,r4 + 8005098: 2821883a mov r16,r5 + 800509c: 10000226 beq r2,zero,80050a8 <__swsetup_r+0x2c> + 80050a0: 10c00e17 ldw r3,56(r2) + 80050a4: 18002026 beq r3,zero,8005128 <__swsetup_r+0xac> + 80050a8: 8080030b ldhu r2,12(r16) + 80050ac: 10c0020c andi r3,r2,8 + 80050b0: 1009883a mov r4,r2 + 80050b4: 18002226 beq r3,zero,8005140 <__swsetup_r+0xc4> + 80050b8: 80c00417 ldw r3,16(r16) + 80050bc: 18002826 beq r3,zero,8005160 <__swsetup_r+0xe4> + 80050c0: 1100004c andi r4,r2,1 + 80050c4: 20000b1e bne r4,zero,80050f4 <__swsetup_r+0x78> + 80050c8: 1080008c andi r2,r2,2 + 80050cc: 10002d1e bne r2,zero,8005184 <__swsetup_r+0x108> + 80050d0: 80800517 ldw r2,20(r16) + 80050d4: 80800215 stw r2,8(r16) + 80050d8: 18000b26 beq r3,zero,8005108 <__swsetup_r+0x8c> + 80050dc: 0005883a mov r2,zero + 80050e0: dfc00217 ldw ra,8(sp) + 80050e4: dc400117 ldw r17,4(sp) + 80050e8: dc000017 ldw r16,0(sp) + 80050ec: dec00304 addi sp,sp,12 + 80050f0: f800283a ret + 80050f4: 80800517 ldw r2,20(r16) + 80050f8: 80000215 stw zero,8(r16) + 80050fc: 0085c83a sub r2,zero,r2 + 8005100: 80800615 stw r2,24(r16) + 8005104: 183ff51e bne r3,zero,80050dc <__swsetup_r+0x60> + 8005108: 80c0030b ldhu r3,12(r16) + 800510c: 0005883a mov r2,zero + 8005110: 1900200c andi r4,r3,128 + 8005114: 203ff226 beq r4,zero,80050e0 <__swsetup_r+0x64> + 8005118: 18c01014 ori r3,r3,64 + 800511c: 80c0030d sth r3,12(r16) + 8005120: 00bfffc4 movi r2,-1 + 8005124: 003fee06 br 80050e0 <__swsetup_r+0x64> + 8005128: 1009883a mov r4,r2 + 800512c: 80070600 call 8007060 <__sinit> + 8005130: 8080030b ldhu r2,12(r16) + 8005134: 10c0020c andi r3,r2,8 + 8005138: 1009883a mov r4,r2 + 800513c: 183fde1e bne r3,zero,80050b8 <__swsetup_r+0x3c> + 8005140: 2080040c andi r2,r4,16 + 8005144: 10001f26 beq r2,zero,80051c4 <__swsetup_r+0x148> + 8005148: 2080010c andi r2,r4,4 + 800514c: 10000f1e bne r2,zero,800518c <__swsetup_r+0x110> + 8005150: 80c00417 ldw r3,16(r16) + 8005154: 20800214 ori r2,r4,8 + 8005158: 8080030d sth r2,12(r16) + 800515c: 183fd81e bne r3,zero,80050c0 <__swsetup_r+0x44> + 8005160: 1100a00c andi r4,r2,640 + 8005164: 21008020 cmpeqi r4,r4,512 + 8005168: 203fd51e bne r4,zero,80050c0 <__swsetup_r+0x44> + 800516c: 800b883a mov r5,r16 + 8005170: 8809883a mov r4,r17 + 8005174: 8007ca00 call 8007ca0 <__smakebuf_r> + 8005178: 8080030b ldhu r2,12(r16) + 800517c: 80c00417 ldw r3,16(r16) + 8005180: 003fcf06 br 80050c0 <__swsetup_r+0x44> + 8005184: 0005883a mov r2,zero + 8005188: 003fd206 br 80050d4 <__swsetup_r+0x58> + 800518c: 81400c17 ldw r5,48(r16) + 8005190: 28000626 beq r5,zero,80051ac <__swsetup_r+0x130> + 8005194: 80801004 addi r2,r16,64 + 8005198: 28800326 beq r5,r2,80051a8 <__swsetup_r+0x12c> + 800519c: 8809883a mov r4,r17 + 80051a0: 80071c40 call 80071c4 <_free_r> + 80051a4: 8100030b ldhu r4,12(r16) + 80051a8: 80000c15 stw zero,48(r16) + 80051ac: 80c00417 ldw r3,16(r16) + 80051b0: 00bff6c4 movi r2,-37 + 80051b4: 1108703a and r4,r2,r4 + 80051b8: 80000115 stw zero,4(r16) + 80051bc: 80c00015 stw r3,0(r16) + 80051c0: 003fe406 br 8005154 <__swsetup_r+0xd8> + 80051c4: 00800244 movi r2,9 + 80051c8: 88800015 stw r2,0(r17) + 80051cc: 20801014 ori r2,r4,64 + 80051d0: 8080030d sth r2,12(r16) + 80051d4: 00bfffc4 movi r2,-1 + 80051d8: 003fc106 br 80050e0 <__swsetup_r+0x64> + +080051dc : + 80051dc: defff504 addi sp,sp,-44 + 80051e0: dc800315 stw r18,12(sp) + 80051e4: 20800417 ldw r2,16(r4) + 80051e8: 2c800417 ldw r18,16(r5) + 80051ec: dfc00a15 stw ra,40(sp) + 80051f0: df000915 stw fp,36(sp) + 80051f4: ddc00815 stw r23,32(sp) + 80051f8: dd800715 stw r22,28(sp) + 80051fc: dd400615 stw r21,24(sp) + 8005200: dd000515 stw r20,20(sp) + 8005204: dcc00415 stw r19,16(sp) + 8005208: dc400215 stw r17,8(sp) + 800520c: dc000115 stw r16,4(sp) + 8005210: 14807416 blt r2,r18,80053e4 + 8005214: 94bfffc4 addi r18,r18,-1 + 8005218: 902e90ba slli r23,r18,2 + 800521c: 2c400504 addi r17,r5,20 + 8005220: 25400504 addi r21,r4,20 + 8005224: 8de9883a add r20,r17,r23 + 8005228: a7000017 ldw fp,0(r20) + 800522c: adef883a add r23,r21,r23 + 8005230: b8c00017 ldw r3,0(r23) + 8005234: e7000044 addi fp,fp,1 + 8005238: 282d883a mov r22,r5 + 800523c: 2021883a mov r16,r4 + 8005240: e00b883a mov r5,fp + 8005244: 1809883a mov r4,r3 + 8005248: d8c00015 stw r3,0(sp) + 800524c: 800cff80 call 800cff8 <__udivsi3> + 8005250: d8c00017 ldw r3,0(sp) + 8005254: 1027883a mov r19,r2 + 8005258: 1f002c36 bltu r3,fp,800530c + 800525c: 8811883a mov r8,r17 + 8005260: a80b883a mov r5,r21 + 8005264: 0013883a mov r9,zero + 8005268: 0007883a mov r3,zero + 800526c: 42000104 addi r8,r8,4 + 8005270: 41ffff17 ldw r7,-4(r8) + 8005274: 29800017 ldw r6,0(r5) + 8005278: 29400104 addi r5,r5,4 + 800527c: 38bfffcc andi r2,r7,65535 + 8005280: 14c5383a mul r2,r2,r19 + 8005284: 3808d43a srli r4,r7,16 + 8005288: 32bfffcc andi r10,r6,65535 + 800528c: 1245883a add r2,r2,r9 + 8005290: 1012d43a srli r9,r2,16 + 8005294: 11ffffcc andi r7,r2,65535 + 8005298: 24c9383a mul r4,r4,r19 + 800529c: 19c7c83a sub r3,r3,r7 + 80052a0: 1a8f883a add r7,r3,r10 + 80052a4: 3006d43a srli r3,r6,16 + 80052a8: 2249883a add r4,r4,r9 + 80052ac: 3805d43a srai r2,r7,16 + 80052b0: 21bfffcc andi r6,r4,65535 + 80052b4: 1987c83a sub r3,r3,r6 + 80052b8: 1887883a add r3,r3,r2 + 80052bc: 180c943a slli r6,r3,16 + 80052c0: 39ffffcc andi r7,r7,65535 + 80052c4: 2012d43a srli r9,r4,16 + 80052c8: 31ceb03a or r7,r6,r7 + 80052cc: 29ffff15 stw r7,-4(r5) + 80052d0: 1807d43a srai r3,r3,16 + 80052d4: a23fe52e bgeu r20,r8,800526c + 80052d8: b8800017 ldw r2,0(r23) + 80052dc: 10000b1e bne r2,zero,800530c + 80052e0: b8bfff04 addi r2,r23,-4 + 80052e4: a880082e bgeu r21,r2,8005308 + 80052e8: b8ffff17 ldw r3,-4(r23) + 80052ec: 18000326 beq r3,zero,80052fc + 80052f0: 00000506 br 8005308 + 80052f4: 10c00017 ldw r3,0(r2) + 80052f8: 1800031e bne r3,zero,8005308 + 80052fc: 10bfff04 addi r2,r2,-4 + 8005300: 94bfffc4 addi r18,r18,-1 + 8005304: a8bffb36 bltu r21,r2,80052f4 + 8005308: 84800415 stw r18,16(r16) + 800530c: b00b883a mov r5,r22 + 8005310: 8009883a mov r4,r16 + 8005314: 80092580 call 8009258 <__mcmp> + 8005318: 10002516 blt r2,zero,80053b0 + 800531c: 9cc00044 addi r19,r19,1 + 8005320: a80d883a mov r6,r21 + 8005324: 0007883a mov r3,zero + 8005328: 8c400104 addi r17,r17,4 + 800532c: 893fff17 ldw r4,-4(r17) + 8005330: 31400017 ldw r5,0(r6) + 8005334: 31800104 addi r6,r6,4 + 8005338: 20bfffcc andi r2,r4,65535 + 800533c: 1887c83a sub r3,r3,r2 + 8005340: 28bfffcc andi r2,r5,65535 + 8005344: 1885883a add r2,r3,r2 + 8005348: 2008d43a srli r4,r4,16 + 800534c: 2806d43a srli r3,r5,16 + 8005350: 100fd43a srai r7,r2,16 + 8005354: 117fffcc andi r5,r2,65535 + 8005358: 1907c83a sub r3,r3,r4 + 800535c: 19c7883a add r3,r3,r7 + 8005360: 1804943a slli r2,r3,16 + 8005364: 1807d43a srai r3,r3,16 + 8005368: 1144b03a or r2,r2,r5 + 800536c: 30bfff15 stw r2,-4(r6) + 8005370: a47fed2e bgeu r20,r17,8005328 + 8005374: 900690ba slli r3,r18,2 + 8005378: a8c7883a add r3,r21,r3 + 800537c: 18800017 ldw r2,0(r3) + 8005380: 10000b1e bne r2,zero,80053b0 + 8005384: 18bfff04 addi r2,r3,-4 + 8005388: a880082e bgeu r21,r2,80053ac + 800538c: 18ffff17 ldw r3,-4(r3) + 8005390: 18000326 beq r3,zero,80053a0 + 8005394: 00000506 br 80053ac + 8005398: 10c00017 ldw r3,0(r2) + 800539c: 1800031e bne r3,zero,80053ac + 80053a0: 10bfff04 addi r2,r2,-4 + 80053a4: 94bfffc4 addi r18,r18,-1 + 80053a8: a8bffb36 bltu r21,r2,8005398 + 80053ac: 84800415 stw r18,16(r16) + 80053b0: 9805883a mov r2,r19 + 80053b4: dfc00a17 ldw ra,40(sp) + 80053b8: df000917 ldw fp,36(sp) + 80053bc: ddc00817 ldw r23,32(sp) + 80053c0: dd800717 ldw r22,28(sp) + 80053c4: dd400617 ldw r21,24(sp) + 80053c8: dd000517 ldw r20,20(sp) + 80053cc: dcc00417 ldw r19,16(sp) + 80053d0: dc800317 ldw r18,12(sp) + 80053d4: dc400217 ldw r17,8(sp) + 80053d8: dc000117 ldw r16,4(sp) + 80053dc: dec00b04 addi sp,sp,44 + 80053e0: f800283a ret + 80053e4: 0005883a mov r2,zero + 80053e8: 003ff206 br 80053b4 + +080053ec <_dtoa_r>: + 80053ec: 20801017 ldw r2,64(r4) + 80053f0: deffe204 addi sp,sp,-120 + 80053f4: df001c15 stw fp,112(sp) + 80053f8: dcc01715 stw r19,92(sp) + 80053fc: dc401515 stw r17,84(sp) + 8005400: dc001415 stw r16,80(sp) + 8005404: dfc01d15 stw ra,116(sp) + 8005408: ddc01b15 stw r23,108(sp) + 800540c: dd801a15 stw r22,104(sp) + 8005410: dd401915 stw r21,100(sp) + 8005414: dd001815 stw r20,96(sp) + 8005418: dc801615 stw r18,88(sp) + 800541c: d9400115 stw r5,4(sp) + 8005420: d9c00215 stw r7,8(sp) + 8005424: 2039883a mov fp,r4 + 8005428: 3027883a mov r19,r6 + 800542c: dc002017 ldw r16,128(sp) + 8005430: 3023883a mov r17,r6 + 8005434: 10000826 beq r2,zero,8005458 <_dtoa_r+0x6c> + 8005438: 21801117 ldw r6,68(r4) + 800543c: 00c00044 movi r3,1 + 8005440: 100b883a mov r5,r2 + 8005444: 1986983a sll r3,r3,r6 + 8005448: 11800115 stw r6,4(r2) + 800544c: 10c00215 stw r3,8(r2) + 8005450: 8008a780 call 8008a78 <_Bfree> + 8005454: e0001015 stw zero,64(fp) + 8005458: 98018116 blt r19,zero,8005a60 <_dtoa_r+0x674> + 800545c: 80000015 stw zero,0(r16) + 8005460: 989ffc2c andhi r2,r19,32752 + 8005464: 00dffc34 movhi r3,32752 + 8005468: 10c18626 beq r2,r3,8005a84 <_dtoa_r+0x698> + 800546c: d9000117 ldw r4,4(sp) + 8005470: 000d883a mov r6,zero + 8005474: 000f883a mov r7,zero + 8005478: 880b883a mov r5,r17 + 800547c: 800e3000 call 800e300 <__eqdf2> + 8005480: 1000191e bne r2,zero,80054e8 <_dtoa_r+0xfc> + 8005484: d8c01f17 ldw r3,124(sp) + 8005488: 00800044 movi r2,1 + 800548c: 18800015 stw r2,0(r3) + 8005490: d8802117 ldw r2,132(sp) + 8005494: 10032426 beq r2,zero,8006128 <_dtoa_r+0xd3c> + 8005498: d9002117 ldw r4,132(sp) + 800549c: 00820134 movhi r2,2052 + 80054a0: 109d2744 addi r2,r2,29853 + 80054a4: 00c20134 movhi r3,2052 + 80054a8: 20800015 stw r2,0(r4) + 80054ac: 189d2704 addi r2,r3,29852 + 80054b0: d8800315 stw r2,12(sp) + 80054b4: d8800317 ldw r2,12(sp) + 80054b8: dfc01d17 ldw ra,116(sp) + 80054bc: df001c17 ldw fp,112(sp) + 80054c0: ddc01b17 ldw r23,108(sp) + 80054c4: dd801a17 ldw r22,104(sp) + 80054c8: dd401917 ldw r21,100(sp) + 80054cc: dd001817 ldw r20,96(sp) + 80054d0: dcc01717 ldw r19,92(sp) + 80054d4: dc801617 ldw r18,88(sp) + 80054d8: dc401517 ldw r17,84(sp) + 80054dc: dc001417 ldw r16,80(sp) + 80054e0: dec01e04 addi sp,sp,120 + 80054e4: f800283a ret + 80054e8: dc800117 ldw r18,4(sp) + 80054ec: d8801204 addi r2,sp,72 + 80054f0: 9820d53a srli r16,r19,20 + 80054f4: d8800015 stw r2,0(sp) + 80054f8: d9c01304 addi r7,sp,76 + 80054fc: 900b883a mov r5,r18 + 8005500: 880d883a mov r6,r17 + 8005504: e009883a mov r4,fp + 8005508: 80095cc0 call 80095cc <__d2b> + 800550c: 102b883a mov r21,r2 + 8005510: 8001701e bne r16,zero,8005ad4 <_dtoa_r+0x6e8> + 8005514: dc801217 ldw r18,72(sp) + 8005518: dc001317 ldw r16,76(sp) + 800551c: 9421883a add r16,r18,r16 + 8005520: 80810c84 addi r2,r16,1074 + 8005524: 10c00850 cmplti r3,r2,33 + 8005528: 18030f1e bne r3,zero,8006168 <_dtoa_r+0xd7c> + 800552c: 01001004 movi r4,64 + 8005530: 2085c83a sub r2,r4,r2 + 8005534: 98a6983a sll r19,r19,r2 + 8005538: d8800117 ldw r2,4(sp) + 800553c: 81010484 addi r4,r16,1042 + 8005540: 1108d83a srl r4,r2,r4 + 8005544: 9908b03a or r4,r19,r4 + 8005548: 800f6f40 call 800f6f4 <__floatunsidf> + 800554c: 1009883a mov r4,r2 + 8005550: 017f8434 movhi r5,65040 + 8005554: 00800044 movi r2,1 + 8005558: 194b883a add r5,r3,r5 + 800555c: 843fffc4 addi r16,r16,-1 + 8005560: d8800a15 stw r2,40(sp) + 8005564: 000d883a mov r6,zero + 8005568: 01cffe34 movhi r7,16376 + 800556c: 800ebec0 call 800ebec <__subdf3> + 8005570: 0198dbf4 movhi r6,25455 + 8005574: 01cff4f4 movhi r7,16339 + 8005578: 3190d844 addi r6,r6,17249 + 800557c: 39e1e9c4 addi r7,r7,-30809 + 8005580: 1009883a mov r4,r2 + 8005584: 180b883a mov r5,r3 + 8005588: 800e5600 call 800e560 <__muldf3> + 800558c: 01a2d874 movhi r6,35681 + 8005590: 01cff1f4 movhi r7,16327 + 8005594: 31b22cc4 addi r6,r6,-14157 + 8005598: 39e28a04 addi r7,r7,-30168 + 800559c: 180b883a mov r5,r3 + 80055a0: 1009883a mov r4,r2 + 80055a4: 800d0b80 call 800d0b8 <__adddf3> + 80055a8: 8009883a mov r4,r16 + 80055ac: 1029883a mov r20,r2 + 80055b0: 1827883a mov r19,r3 + 80055b4: 800f62c0 call 800f62c <__floatsidf> + 80055b8: 019427f4 movhi r6,20639 + 80055bc: 01cff4f4 movhi r7,16339 + 80055c0: 319e7ec4 addi r6,r6,31227 + 80055c4: 39d104c4 addi r7,r7,17427 + 80055c8: 1009883a mov r4,r2 + 80055cc: 180b883a mov r5,r3 + 80055d0: 800e5600 call 800e560 <__muldf3> + 80055d4: 100d883a mov r6,r2 + 80055d8: 180f883a mov r7,r3 + 80055dc: a009883a mov r4,r20 + 80055e0: 980b883a mov r5,r19 + 80055e4: 800d0b80 call 800d0b8 <__adddf3> + 80055e8: 1009883a mov r4,r2 + 80055ec: 180b883a mov r5,r3 + 80055f0: 1029883a mov r20,r2 + 80055f4: 1827883a mov r19,r3 + 80055f8: 800f5ac0 call 800f5ac <__fixdfsi> + 80055fc: 000d883a mov r6,zero + 8005600: 000f883a mov r7,zero + 8005604: a009883a mov r4,r20 + 8005608: 980b883a mov r5,r19 + 800560c: 102d883a mov r22,r2 + 8005610: 800e4700 call 800e470 <__ledf2> + 8005614: 1002ba16 blt r2,zero,8006100 <_dtoa_r+0xd14> + 8005618: 9421c83a sub r16,r18,r16 + 800561c: b08005e8 cmpgeui r2,r22,23 + 8005620: 853fffc4 addi r20,r16,-1 + 8005624: 1002ae1e bne r2,zero,80060e0 <_dtoa_r+0xcf4> + 8005628: b00690fa slli r3,r22,3 + 800562c: 00820134 movhi r2,2052 + 8005630: 109d4b04 addi r2,r2,29996 + 8005634: 10c5883a add r2,r2,r3 + 8005638: 11800017 ldw r6,0(r2) + 800563c: 11c00117 ldw r7,4(r2) + 8005640: d9000117 ldw r4,4(sp) + 8005644: 880b883a mov r5,r17 + 8005648: 800e4700 call 800e470 <__ledf2> + 800564c: 10026f0e bge r2,zero,800600c <_dtoa_r+0xc20> + 8005650: d8000915 stw zero,36(sp) + 8005654: b5bfffc4 addi r22,r22,-1 + 8005658: a002a416 blt r20,zero,80060ec <_dtoa_r+0xd00> + 800565c: d8000515 stw zero,20(sp) + 8005660: b0026d0e bge r22,zero,8006018 <_dtoa_r+0xc2c> + 8005664: d8800517 ldw r2,20(sp) + 8005668: d8c00217 ldw r3,8(sp) + 800566c: dd800415 stw r22,16(sp) + 8005670: 1585c83a sub r2,r2,r22 + 8005674: d8800515 stw r2,20(sp) + 8005678: 0585c83a sub r2,zero,r22 + 800567c: d8800815 stw r2,32(sp) + 8005680: 188002a8 cmpgeui r2,r3,10 + 8005684: 002d883a mov r22,zero + 8005688: 1002691e bne r2,zero,8006030 <_dtoa_r+0xc44> + 800568c: 18800190 cmplti r2,r3,6 + 8005690: 1002ba1e bne r2,zero,800617c <_dtoa_r+0xd90> + 8005694: 18bfff04 addi r2,r3,-4 + 8005698: d8800215 stw r2,8(sp) + 800569c: 0021883a mov r16,zero + 80056a0: d8c00217 ldw r3,8(sp) + 80056a4: 188000e0 cmpeqi r2,r3,3 + 80056a8: 10039d1e bne r2,zero,8006520 <_dtoa_r+0x1134> + 80056ac: 18800108 cmpgei r2,r3,4 + 80056b0: 10027a26 beq r2,zero,800609c <_dtoa_r+0xcb0> + 80056b4: d8c00217 ldw r3,8(sp) + 80056b8: 18800120 cmpeqi r2,r3,4 + 80056bc: 10026926 beq r2,zero,8006064 <_dtoa_r+0xc78> + 80056c0: 00800044 movi r2,1 + 80056c4: d8800715 stw r2,28(sp) + 80056c8: d8801e17 ldw r2,120(sp) + 80056cc: 0083670e bge zero,r2,800646c <_dtoa_r+0x1080> + 80056d0: d8800b15 stw r2,44(sp) + 80056d4: d8800615 stw r2,24(sp) + 80056d8: 100d883a mov r6,r2 + 80056dc: e0001115 stw zero,68(fp) + 80056e0: 30800610 cmplti r2,r6,24 + 80056e4: dc800617 ldw r18,24(sp) + 80056e8: 1004eb1e bne r2,zero,8006a98 <_dtoa_r+0x16ac> + 80056ec: 00c00044 movi r3,1 + 80056f0: 00800104 movi r2,4 + 80056f4: 1085883a add r2,r2,r2 + 80056f8: 11000504 addi r4,r2,20 + 80056fc: 180b883a mov r5,r3 + 8005700: 18c00044 addi r3,r3,1 + 8005704: 313ffb2e bgeu r6,r4,80056f4 <_dtoa_r+0x308> + 8005708: e1401115 stw r5,68(fp) + 800570c: e009883a mov r4,fp + 8005710: 80089d40 call 80089d4 <_Balloc> + 8005714: d8800315 stw r2,12(sp) + 8005718: e0801015 stw r2,64(fp) + 800571c: 948003e8 cmpgeui r18,r18,15 + 8005720: 9000fe1e bne r18,zero,8005b1c <_dtoa_r+0x730> + 8005724: 8000fd26 beq r16,zero,8005b1c <_dtoa_r+0x730> + 8005728: d9000417 ldw r4,16(sp) + 800572c: 0103c60e bge zero,r4,8006648 <_dtoa_r+0x125c> + 8005730: 208003cc andi r2,r4,15 + 8005734: 100690fa slli r3,r2,3 + 8005738: 202fd13a srai r23,r4,4 + 800573c: 00820134 movhi r2,2052 + 8005740: 109d4b04 addi r2,r2,29996 + 8005744: 10c5883a add r2,r2,r3 + 8005748: b8c0040c andi r3,r23,16 + 800574c: 12800017 ldw r10,0(r2) + 8005750: 12400117 ldw r9,4(r2) + 8005754: 1803621e bne r3,zero,80064e0 <_dtoa_r+0x10f4> + 8005758: d8800117 ldw r2,4(sp) + 800575c: 8827883a mov r19,r17 + 8005760: 04000084 movi r16,2 + 8005764: d8800c15 stw r2,48(sp) + 8005768: 04820134 movhi r18,2052 + 800576c: 949d4104 addi r18,r18,29956 + 8005770: b8000f26 beq r23,zero,80057b0 <_dtoa_r+0x3c4> + 8005774: 5005883a mov r2,r10 + 8005778: 4807883a mov r3,r9 + 800577c: b980004c andi r6,r23,1 + 8005780: 1009883a mov r4,r2 + 8005784: b82fd07a srai r23,r23,1 + 8005788: 180b883a mov r5,r3 + 800578c: 30000426 beq r6,zero,80057a0 <_dtoa_r+0x3b4> + 8005790: 91800017 ldw r6,0(r18) + 8005794: 91c00117 ldw r7,4(r18) + 8005798: 84000044 addi r16,r16,1 + 800579c: 800e5600 call 800e560 <__muldf3> + 80057a0: 94800204 addi r18,r18,8 + 80057a4: b83ff51e bne r23,zero,800577c <_dtoa_r+0x390> + 80057a8: 1015883a mov r10,r2 + 80057ac: 1813883a mov r9,r3 + 80057b0: d9000c17 ldw r4,48(sp) + 80057b4: 980b883a mov r5,r19 + 80057b8: 500d883a mov r6,r10 + 80057bc: 480f883a mov r7,r9 + 80057c0: 800da580 call 800da58 <__divdf3> + 80057c4: 1025883a mov r18,r2 + 80057c8: 1827883a mov r19,r3 + 80057cc: d8800917 ldw r2,36(sp) + 80057d0: 10000626 beq r2,zero,80057ec <_dtoa_r+0x400> + 80057d4: 000d883a mov r6,zero + 80057d8: 01cffc34 movhi r7,16368 + 80057dc: 9009883a mov r4,r18 + 80057e0: 980b883a mov r5,r19 + 80057e4: 800e4700 call 800e470 <__ledf2> + 80057e8: 10042616 blt r2,zero,8006884 <_dtoa_r+0x1498> + 80057ec: 8009883a mov r4,r16 + 80057f0: 800f62c0 call 800f62c <__floatsidf> + 80057f4: 900d883a mov r6,r18 + 80057f8: 980f883a mov r7,r19 + 80057fc: 1009883a mov r4,r2 + 8005800: 180b883a mov r5,r3 + 8005804: 800e5600 call 800e560 <__muldf3> + 8005808: 000d883a mov r6,zero + 800580c: 01d00734 movhi r7,16412 + 8005810: 1009883a mov r4,r2 + 8005814: 180b883a mov r5,r3 + 8005818: 800d0b80 call 800d0b8 <__adddf3> + 800581c: d8800c15 stw r2,48(sp) + 8005820: 00bf3034 movhi r2,64704 + 8005824: 1885883a add r2,r3,r2 + 8005828: d8800d15 stw r2,52(sp) + 800582c: d8800617 ldw r2,24(sp) + 8005830: 10036d26 beq r2,zero,80065e8 <_dtoa_r+0x11fc> + 8005834: d8800417 ldw r2,16(sp) + 8005838: d8800f15 stw r2,60(sp) + 800583c: d8800617 ldw r2,24(sp) + 8005840: d8800e15 stw r2,56(sp) + 8005844: 980b883a mov r5,r19 + 8005848: 9009883a mov r4,r18 + 800584c: 800f5ac0 call 800f5ac <__fixdfsi> + 8005850: 1009883a mov r4,r2 + 8005854: 102f883a mov r23,r2 + 8005858: 800f62c0 call 800f62c <__floatsidf> + 800585c: 100d883a mov r6,r2 + 8005860: 180f883a mov r7,r3 + 8005864: 9009883a mov r4,r18 + 8005868: 980b883a mov r5,r19 + 800586c: 800ebec0 call 800ebec <__subdf3> + 8005870: 1025883a mov r18,r2 + 8005874: d8800e17 ldw r2,56(sp) + 8005878: 1821883a mov r16,r3 + 800587c: ba400c04 addi r9,r23,48 + 8005880: 10bfffc4 addi r2,r2,-1 + 8005884: 100690fa slli r3,r2,3 + 8005888: 00820134 movhi r2,2052 + 800588c: 109d4b04 addi r2,r2,29996 + 8005890: 10c5883a add r2,r2,r3 + 8005894: 11800017 ldw r6,0(r2) + 8005898: d8c00317 ldw r3,12(sp) + 800589c: 11c00117 ldw r7,4(r2) + 80058a0: d8800717 ldw r2,28(sp) + 80058a4: 4811883a mov r8,r9 + 80058a8: da001015 stw r8,64(sp) + 80058ac: 1dc00044 addi r23,r3,1 + 80058b0: 1003a226 beq r2,zero,800673c <_dtoa_r+0x1350> + 80058b4: 0009883a mov r4,zero + 80058b8: 014ff834 movhi r5,16352 + 80058bc: da401115 stw r9,68(sp) + 80058c0: 800da580 call 800da58 <__divdf3> + 80058c4: d9800c17 ldw r6,48(sp) + 80058c8: d9c00d17 ldw r7,52(sp) + 80058cc: 1009883a mov r4,r2 + 80058d0: 180b883a mov r5,r3 + 80058d4: 800ebec0 call 800ebec <__subdf3> + 80058d8: 1827883a mov r19,r3 + 80058dc: da401117 ldw r9,68(sp) + 80058e0: d8c00317 ldw r3,12(sp) + 80058e4: 900d883a mov r6,r18 + 80058e8: 800f883a mov r7,r16 + 80058ec: 1a400005 stb r9,0(r3) + 80058f0: 1009883a mov r4,r2 + 80058f4: 980b883a mov r5,r19 + 80058f8: d8800c15 stw r2,48(sp) + 80058fc: 800e3800 call 800e380 <__gedf2> + 8005900: da001017 ldw r8,64(sp) + 8005904: 00804816 blt zero,r2,8005a28 <_dtoa_r+0x63c> + 8005908: 900d883a mov r6,r18 + 800590c: 800f883a mov r7,r16 + 8005910: 0009883a mov r4,zero + 8005914: 014ffc34 movhi r5,16368 + 8005918: da000d15 stw r8,52(sp) + 800591c: 800ebec0 call 800ebec <__subdf3> + 8005920: d9000c17 ldw r4,48(sp) + 8005924: 100d883a mov r6,r2 + 8005928: 180f883a mov r7,r3 + 800592c: 980b883a mov r5,r19 + 8005930: 800e3800 call 800e380 <__gedf2> + 8005934: da000d17 ldw r8,52(sp) + 8005938: 00844e16 blt zero,r2,8006a74 <_dtoa_r+0x1688> + 800593c: d8c00e17 ldw r3,56(sp) + 8005940: 18800060 cmpeqi r2,r3,1 + 8005944: 1000751e bne r2,zero,8005b1c <_dtoa_r+0x730> + 8005948: d8800317 ldw r2,12(sp) + 800594c: dd800d15 stw r22,52(sp) + 8005950: dd000e15 stw r20,56(sp) + 8005954: 10c5883a add r2,r2,r3 + 8005958: dd000c17 ldw r20,48(sp) + 800595c: 102d883a mov r22,r2 + 8005960: dc400c15 stw r17,48(sp) + 8005964: 00000806 br 8005988 <_dtoa_r+0x59c> + 8005968: 800ebec0 call 800ebec <__subdf3> + 800596c: a00d883a mov r6,r20 + 8005970: 980f883a mov r7,r19 + 8005974: 1009883a mov r4,r2 + 8005978: 180b883a mov r5,r3 + 800597c: 800e4700 call 800e470 <__ledf2> + 8005980: 10042316 blt r2,zero,8006a10 <_dtoa_r+0x1624> + 8005984: bd806226 beq r23,r22,8005b10 <_dtoa_r+0x724> + 8005988: a009883a mov r4,r20 + 800598c: 980b883a mov r5,r19 + 8005990: 000d883a mov r6,zero + 8005994: 01d00934 movhi r7,16420 + 8005998: 800e5600 call 800e560 <__muldf3> + 800599c: 000d883a mov r6,zero + 80059a0: 01d00934 movhi r7,16420 + 80059a4: 9009883a mov r4,r18 + 80059a8: 800b883a mov r5,r16 + 80059ac: 1029883a mov r20,r2 + 80059b0: 1827883a mov r19,r3 + 80059b4: 800e5600 call 800e560 <__muldf3> + 80059b8: 180b883a mov r5,r3 + 80059bc: 1009883a mov r4,r2 + 80059c0: 1821883a mov r16,r3 + 80059c4: 1025883a mov r18,r2 + 80059c8: 800f5ac0 call 800f5ac <__fixdfsi> + 80059cc: 1009883a mov r4,r2 + 80059d0: 1023883a mov r17,r2 + 80059d4: 800f62c0 call 800f62c <__floatsidf> + 80059d8: 9009883a mov r4,r18 + 80059dc: 800b883a mov r5,r16 + 80059e0: 100d883a mov r6,r2 + 80059e4: 180f883a mov r7,r3 + 80059e8: 800ebec0 call 800ebec <__subdf3> + 80059ec: bdc00044 addi r23,r23,1 + 80059f0: 8c400c04 addi r17,r17,48 + 80059f4: a00d883a mov r6,r20 + 80059f8: 980f883a mov r7,r19 + 80059fc: 1009883a mov r4,r2 + 8005a00: 180b883a mov r5,r3 + 8005a04: bc7fffc5 stb r17,-1(r23) + 8005a08: 1025883a mov r18,r2 + 8005a0c: 1821883a mov r16,r3 + 8005a10: 800e4700 call 800e470 <__ledf2> + 8005a14: 900d883a mov r6,r18 + 8005a18: 800f883a mov r7,r16 + 8005a1c: 0009883a mov r4,zero + 8005a20: 014ffc34 movhi r5,16368 + 8005a24: 103fd00e bge r2,zero,8005968 <_dtoa_r+0x57c> + 8005a28: d8800f17 ldw r2,60(sp) + 8005a2c: 10800044 addi r2,r2,1 + 8005a30: d8800415 stw r2,16(sp) + 8005a34: a80b883a mov r5,r21 + 8005a38: e009883a mov r4,fp + 8005a3c: 8008a780 call 8008a78 <_Bfree> + 8005a40: d8801f17 ldw r2,124(sp) + 8005a44: d8c00417 ldw r3,16(sp) + 8005a48: b8000005 stb zero,0(r23) + 8005a4c: 10c00015 stw r3,0(r2) + 8005a50: d8802117 ldw r2,132(sp) + 8005a54: 103e9726 beq r2,zero,80054b4 <_dtoa_r+0xc8> + 8005a58: 15c00015 stw r23,0(r2) + 8005a5c: 003e9506 br 80054b4 <_dtoa_r+0xc8> + 8005a60: 04600034 movhi r17,32768 + 8005a64: 8c7fffc4 addi r17,r17,-1 + 8005a68: 9c62703a and r17,r19,r17 + 8005a6c: 00800044 movi r2,1 + 8005a70: 8827883a mov r19,r17 + 8005a74: 80800015 stw r2,0(r16) + 8005a78: 00dffc34 movhi r3,32752 + 8005a7c: 989ffc2c andhi r2,r19,32752 + 8005a80: 10fe7a1e bne r2,r3,800546c <_dtoa_r+0x80> + 8005a84: 00800434 movhi r2,16 + 8005a88: d8c01f17 ldw r3,124(sp) + 8005a8c: 10bfffc4 addi r2,r2,-1 + 8005a90: 98a6703a and r19,r19,r2 + 8005a94: 0089c3c4 movi r2,9999 + 8005a98: 18800015 stw r2,0(r3) + 8005a9c: d8800117 ldw r2,4(sp) + 8005aa0: 98aab03a or r21,r19,r2 + 8005aa4: a800141e bne r21,zero,8005af8 <_dtoa_r+0x70c> + 8005aa8: d8802117 ldw r2,132(sp) + 8005aac: 1003f626 beq r2,zero,8006a88 <_dtoa_r+0x169c> + 8005ab0: 00820134 movhi r2,2052 + 8005ab4: 1007883a mov r3,r2 + 8005ab8: 18dd3104 addi r3,r3,29892 + 8005abc: 00820134 movhi r2,2052 + 8005ac0: d8c00315 stw r3,12(sp) + 8005ac4: 109d3304 addi r2,r2,29900 + 8005ac8: d8c02117 ldw r3,132(sp) + 8005acc: 18800015 stw r2,0(r3) + 8005ad0: 003e7806 br 80054b4 <_dtoa_r+0xc8> + 8005ad4: 01400434 movhi r5,16 + 8005ad8: 297fffc4 addi r5,r5,-1 + 8005adc: 894a703a and r5,r17,r5 + 8005ae0: 9009883a mov r4,r18 + 8005ae4: 294ffc34 orhi r5,r5,16368 + 8005ae8: 843f0044 addi r16,r16,-1023 + 8005aec: dc801217 ldw r18,72(sp) + 8005af0: d8000a15 stw zero,40(sp) + 8005af4: 003e9b06 br 8005564 <_dtoa_r+0x178> + 8005af8: d8802117 ldw r2,132(sp) + 8005afc: 1002461e bne r2,zero,8006418 <_dtoa_r+0x102c> + 8005b00: 00820134 movhi r2,2052 + 8005b04: 109d3004 addi r2,r2,29888 + 8005b08: d8800315 stw r2,12(sp) + 8005b0c: 003e6906 br 80054b4 <_dtoa_r+0xc8> + 8005b10: dd800d17 ldw r22,52(sp) + 8005b14: dd000e17 ldw r20,56(sp) + 8005b18: dc400c17 ldw r17,48(sp) + 8005b1c: d8801317 ldw r2,76(sp) + 8005b20: 10009f16 blt r2,zero,8005da0 <_dtoa_r+0x9b4> + 8005b24: d9000417 ldw r4,16(sp) + 8005b28: 20c003c8 cmpgei r3,r4,15 + 8005b2c: 18009c1e bne r3,zero,8005da0 <_dtoa_r+0x9b4> + 8005b30: 200690fa slli r3,r4,3 + 8005b34: 00820134 movhi r2,2052 + 8005b38: 109d4b04 addi r2,r2,29996 + 8005b3c: 10c5883a add r2,r2,r3 + 8005b40: 14000017 ldw r16,0(r2) + 8005b44: 14800117 ldw r18,4(r2) + 8005b48: d8801e17 ldw r2,120(sp) + 8005b4c: 1000140e bge r2,zero,8005ba0 <_dtoa_r+0x7b4> + 8005b50: d8800617 ldw r2,24(sp) + 8005b54: 00801216 blt zero,r2,8005ba0 <_dtoa_r+0x7b4> + 8005b58: 1002b81e bne r2,zero,800663c <_dtoa_r+0x1250> + 8005b5c: 8009883a mov r4,r16 + 8005b60: 900b883a mov r5,r18 + 8005b64: 000d883a mov r6,zero + 8005b68: 01d00534 movhi r7,16404 + 8005b6c: 800e5600 call 800e560 <__muldf3> + 8005b70: d9800117 ldw r6,4(sp) + 8005b74: 880f883a mov r7,r17 + 8005b78: 1009883a mov r4,r2 + 8005b7c: 180b883a mov r5,r3 + 8005b80: 800e3800 call 800e380 <__gedf2> + 8005b84: 0025883a mov r18,zero + 8005b88: 0021883a mov r16,zero + 8005b8c: 1001fd16 blt r2,zero,8006384 <_dtoa_r+0xf98> + 8005b90: d8801e17 ldw r2,120(sp) + 8005b94: ddc00317 ldw r23,12(sp) + 8005b98: 00a2303a nor r17,zero,r2 + 8005b9c: 0001ff06 br 800639c <_dtoa_r+0xfb0> + 8005ba0: dcc00117 ldw r19,4(sp) + 8005ba4: 800d883a mov r6,r16 + 8005ba8: 900f883a mov r7,r18 + 8005bac: 880b883a mov r5,r17 + 8005bb0: 9809883a mov r4,r19 + 8005bb4: 800da580 call 800da58 <__divdf3> + 8005bb8: 180b883a mov r5,r3 + 8005bbc: 1009883a mov r4,r2 + 8005bc0: 800f5ac0 call 800f5ac <__fixdfsi> + 8005bc4: 1009883a mov r4,r2 + 8005bc8: 102d883a mov r22,r2 + 8005bcc: 800f62c0 call 800f62c <__floatsidf> + 8005bd0: 800d883a mov r6,r16 + 8005bd4: 900f883a mov r7,r18 + 8005bd8: 1009883a mov r4,r2 + 8005bdc: 180b883a mov r5,r3 + 8005be0: 800e5600 call 800e560 <__muldf3> + 8005be4: 880b883a mov r5,r17 + 8005be8: 100d883a mov r6,r2 + 8005bec: 180f883a mov r7,r3 + 8005bf0: 9809883a mov r4,r19 + 8005bf4: 800ebec0 call 800ebec <__subdf3> + 8005bf8: dc400317 ldw r17,12(sp) + 8005bfc: 1009883a mov r4,r2 + 8005c00: d9c00417 ldw r7,16(sp) + 8005c04: b0800c04 addi r2,r22,48 + 8005c08: 88800005 stb r2,0(r17) + 8005c0c: d8800617 ldw r2,24(sp) + 8005c10: 39c00044 addi r7,r7,1 + 8005c14: d9c00415 stw r7,16(sp) + 8005c18: 11800060 cmpeqi r6,r2,1 + 8005c1c: 180b883a mov r5,r3 + 8005c20: 2005883a mov r2,r4 + 8005c24: 8dc00044 addi r23,r17,1 + 8005c28: 3000391e bne r6,zero,8005d10 <_dtoa_r+0x924> + 8005c2c: 01d00934 movhi r7,16420 + 8005c30: 800e5600 call 800e560 <__muldf3> + 8005c34: 000d883a mov r6,zero + 8005c38: 000f883a mov r7,zero + 8005c3c: 1009883a mov r4,r2 + 8005c40: 180b883a mov r5,r3 + 8005c44: 1027883a mov r19,r2 + 8005c48: 1829883a mov r20,r3 + 8005c4c: 800e3000 call 800e300 <__eqdf2> + 8005c50: 103f7826 beq r2,zero,8005a34 <_dtoa_r+0x648> + 8005c54: d8c00617 ldw r3,24(sp) + 8005c58: 8805883a mov r2,r17 + 8005c5c: dd400115 stw r21,4(sp) + 8005c60: 8c400084 addi r17,r17,2 + 8005c64: 10ed883a add r22,r2,r3 + 8005c68: 00000a06 br 8005c94 <_dtoa_r+0x8a8> + 8005c6c: 800e5600 call 800e560 <__muldf3> + 8005c70: 000d883a mov r6,zero + 8005c74: 000f883a mov r7,zero + 8005c78: 1009883a mov r4,r2 + 8005c7c: 180b883a mov r5,r3 + 8005c80: 1027883a mov r19,r2 + 8005c84: 1829883a mov r20,r3 + 8005c88: 8c400044 addi r17,r17,1 + 8005c8c: 800e3000 call 800e300 <__eqdf2> + 8005c90: 10029d26 beq r2,zero,8006708 <_dtoa_r+0x131c> + 8005c94: 800d883a mov r6,r16 + 8005c98: 900f883a mov r7,r18 + 8005c9c: 9809883a mov r4,r19 + 8005ca0: a00b883a mov r5,r20 + 8005ca4: 800da580 call 800da58 <__divdf3> + 8005ca8: 180b883a mov r5,r3 + 8005cac: 1009883a mov r4,r2 + 8005cb0: 800f5ac0 call 800f5ac <__fixdfsi> + 8005cb4: 1009883a mov r4,r2 + 8005cb8: 102b883a mov r21,r2 + 8005cbc: 800f62c0 call 800f62c <__floatsidf> + 8005cc0: 800d883a mov r6,r16 + 8005cc4: 900f883a mov r7,r18 + 8005cc8: 1009883a mov r4,r2 + 8005ccc: 180b883a mov r5,r3 + 8005cd0: 800e5600 call 800e560 <__muldf3> + 8005cd4: 100d883a mov r6,r2 + 8005cd8: 180f883a mov r7,r3 + 8005cdc: 9809883a mov r4,r19 + 8005ce0: a00b883a mov r5,r20 + 8005ce4: 800ebec0 call 800ebec <__subdf3> + 8005ce8: aa400c04 addi r9,r21,48 + 8005cec: 8a7fffc5 stb r9,-1(r17) + 8005cf0: 000d883a mov r6,zero + 8005cf4: 01d00934 movhi r7,16420 + 8005cf8: 1009883a mov r4,r2 + 8005cfc: 180b883a mov r5,r3 + 8005d00: 882f883a mov r23,r17 + 8005d04: b47fd91e bne r22,r17,8005c6c <_dtoa_r+0x880> + 8005d08: a82d883a mov r22,r21 + 8005d0c: dd400117 ldw r21,4(sp) + 8005d10: 100d883a mov r6,r2 + 8005d14: 180f883a mov r7,r3 + 8005d18: 1009883a mov r4,r2 + 8005d1c: 180b883a mov r5,r3 + 8005d20: 800d0b80 call 800d0b8 <__adddf3> + 8005d24: 800d883a mov r6,r16 + 8005d28: 900f883a mov r7,r18 + 8005d2c: 1009883a mov r4,r2 + 8005d30: 180b883a mov r5,r3 + 8005d34: 1027883a mov r19,r2 + 8005d38: 1823883a mov r17,r3 + 8005d3c: 800e3800 call 800e380 <__gedf2> + 8005d40: 00800816 blt zero,r2,8005d64 <_dtoa_r+0x978> + 8005d44: 800d883a mov r6,r16 + 8005d48: 900f883a mov r7,r18 + 8005d4c: 9809883a mov r4,r19 + 8005d50: 880b883a mov r5,r17 + 8005d54: 800e3000 call 800e300 <__eqdf2> + 8005d58: 103f361e bne r2,zero,8005a34 <_dtoa_r+0x648> + 8005d5c: b580004c andi r22,r22,1 + 8005d60: b03f3426 beq r22,zero,8005a34 <_dtoa_r+0x648> + 8005d64: ba3fffc3 ldbu r8,-1(r23) + 8005d68: d9000317 ldw r4,12(sp) + 8005d6c: 00000306 br 8005d7c <_dtoa_r+0x990> + 8005d70: 20c30e26 beq r4,r3,80069ac <_dtoa_r+0x15c0> + 8005d74: 1a3fffc3 ldbu r8,-1(r3) + 8005d78: 182f883a mov r23,r3 + 8005d7c: 40803fcc andi r2,r8,255 + 8005d80: 1080201c xori r2,r2,128 + 8005d84: 10bfe004 addi r2,r2,-128 + 8005d88: 10800e60 cmpeqi r2,r2,57 + 8005d8c: b8ffffc4 addi r3,r23,-1 + 8005d90: 103ff71e bne r2,zero,8005d70 <_dtoa_r+0x984> + 8005d94: 42000044 addi r8,r8,1 + 8005d98: 1a000005 stb r8,0(r3) + 8005d9c: 003f2506 br 8005a34 <_dtoa_r+0x648> + 8005da0: d8c00717 ldw r3,28(sp) + 8005da4: 1800e426 beq r3,zero,8006138 <_dtoa_r+0xd4c> + 8005da8: d8c00217 ldw r3,8(sp) + 8005dac: 18c00088 cmpgei r3,r3,2 + 8005db0: 1801ec26 beq r3,zero,8006564 <_dtoa_r+0x1178> + 8005db4: d8800617 ldw r2,24(sp) + 8005db8: 14bfffc4 addi r18,r2,-1 + 8005dbc: d8800817 ldw r2,32(sp) + 8005dc0: 1481c50e bge r2,r18,80064d8 <_dtoa_r+0x10ec> + 8005dc4: d8800817 ldw r2,32(sp) + 8005dc8: dc800815 stw r18,32(sp) + 8005dcc: 9085c83a sub r2,r18,r2 + 8005dd0: b0ad883a add r22,r22,r2 + 8005dd4: 0025883a mov r18,zero + 8005dd8: d8800617 ldw r2,24(sp) + 8005ddc: 10024c16 blt r2,zero,8006710 <_dtoa_r+0x1324> + 8005de0: d8c00517 ldw r3,20(sp) + 8005de4: a0a9883a add r20,r20,r2 + 8005de8: 1885883a add r2,r3,r2 + 8005dec: 1827883a mov r19,r3 + 8005df0: d8800515 stw r2,20(sp) + 8005df4: 01400044 movi r5,1 + 8005df8: e009883a mov r4,fp + 8005dfc: 8008dd40 call 8008dd4 <__i2b> + 8005e00: 1021883a mov r16,r2 + 8005e04: 04c0080e bge zero,r19,8005e28 <_dtoa_r+0xa3c> + 8005e08: 0500070e bge zero,r20,8005e28 <_dtoa_r+0xa3c> + 8005e0c: 9805883a mov r2,r19 + 8005e10: a4c1a916 blt r20,r19,80064b8 <_dtoa_r+0x10cc> + 8005e14: d8c00517 ldw r3,20(sp) + 8005e18: 98a7c83a sub r19,r19,r2 + 8005e1c: a0a9c83a sub r20,r20,r2 + 8005e20: 1887c83a sub r3,r3,r2 + 8005e24: d8c00515 stw r3,20(sp) + 8005e28: d8800817 ldw r2,32(sp) + 8005e2c: 10001426 beq r2,zero,8005e80 <_dtoa_r+0xa94> + 8005e30: d8800717 ldw r2,28(sp) + 8005e34: 10017226 beq r2,zero,8006400 <_dtoa_r+0x1014> + 8005e38: 04800e0e bge zero,r18,8005e74 <_dtoa_r+0xa88> + 8005e3c: 800b883a mov r5,r16 + 8005e40: 900d883a mov r6,r18 + 8005e44: e009883a mov r4,fp + 8005e48: 8008ff40 call 8008ff4 <__pow5mult> + 8005e4c: a80d883a mov r6,r21 + 8005e50: 100b883a mov r5,r2 + 8005e54: e009883a mov r4,fp + 8005e58: 1021883a mov r16,r2 + 8005e5c: 8008e080 call 8008e08 <__multiply> + 8005e60: 102f883a mov r23,r2 + 8005e64: a80b883a mov r5,r21 + 8005e68: e009883a mov r4,fp + 8005e6c: 8008a780 call 8008a78 <_Bfree> + 8005e70: b82b883a mov r21,r23 + 8005e74: d8800817 ldw r2,32(sp) + 8005e78: 148dc83a sub r6,r2,r18 + 8005e7c: 3001611e bne r6,zero,8006404 <_dtoa_r+0x1018> + 8005e80: 01400044 movi r5,1 + 8005e84: e009883a mov r4,fp + 8005e88: 8008dd40 call 8008dd4 <__i2b> + 8005e8c: 1025883a mov r18,r2 + 8005e90: 0580bc16 blt zero,r22,8006184 <_dtoa_r+0xd98> + 8005e94: d8800217 ldw r2,8(sp) + 8005e98: 10800088 cmpgei r2,r2,2 + 8005e9c: 10016526 beq r2,zero,8006434 <_dtoa_r+0x1048> + 8005ea0: 0023883a mov r17,zero + 8005ea4: 00800044 movi r2,1 + 8005ea8: b000bf1e bne r22,zero,80061a8 <_dtoa_r+0xdbc> + 8005eac: 1505883a add r2,r2,r20 + 8005eb0: 108007cc andi r2,r2,31 + 8005eb4: 1000aa26 beq r2,zero,8006160 <_dtoa_r+0xd74> + 8005eb8: 00c00804 movi r3,32 + 8005ebc: 1887c83a sub r3,r3,r2 + 8005ec0: 19000150 cmplti r4,r3,5 + 8005ec4: 2002f61e bne r4,zero,8006aa0 <_dtoa_r+0x16b4> + 8005ec8: 00c00704 movi r3,28 + 8005ecc: 1885c83a sub r2,r3,r2 + 8005ed0: d8c00517 ldw r3,20(sp) + 8005ed4: 98a7883a add r19,r19,r2 + 8005ed8: a0a9883a add r20,r20,r2 + 8005edc: 1887883a add r3,r3,r2 + 8005ee0: d8c00515 stw r3,20(sp) + 8005ee4: d8800517 ldw r2,20(sp) + 8005ee8: 00809716 blt zero,r2,8006148 <_dtoa_r+0xd5c> + 8005eec: 0500050e bge zero,r20,8005f04 <_dtoa_r+0xb18> + 8005ef0: 900b883a mov r5,r18 + 8005ef4: a00d883a mov r6,r20 + 8005ef8: e009883a mov r4,fp + 8005efc: 800911c0 call 800911c <__lshift> + 8005f00: 1025883a mov r18,r2 + 8005f04: d8800917 ldw r2,36(sp) + 8005f08: 10012b1e bne r2,zero,80063b8 <_dtoa_r+0xfcc> + 8005f0c: d8800617 ldw r2,24(sp) + 8005f10: 00810d0e bge zero,r2,8006348 <_dtoa_r+0xf5c> + 8005f14: d8800417 ldw r2,16(sp) + 8005f18: 10800044 addi r2,r2,1 + 8005f1c: d8800415 stw r2,16(sp) + 8005f20: d8800717 ldw r2,28(sp) + 8005f24: 1000b21e bne r2,zero,80061f0 <_dtoa_r+0xe04> + 8005f28: ddc00317 ldw r23,12(sp) + 8005f2c: 04400044 movi r17,1 + 8005f30: dcc00617 ldw r19,24(sp) + 8005f34: 00000306 br 8005f44 <_dtoa_r+0xb58> + 8005f38: 8008a9c0 call 8008a9c <__multadd> + 8005f3c: 102b883a mov r21,r2 + 8005f40: 8c400044 addi r17,r17,1 + 8005f44: 900b883a mov r5,r18 + 8005f48: a809883a mov r4,r21 + 8005f4c: 80051dc0 call 80051dc + 8005f50: 10800c04 addi r2,r2,48 + 8005f54: bdc00044 addi r23,r23,1 + 8005f58: b8bfffc5 stb r2,-1(r23) + 8005f5c: 000f883a mov r7,zero + 8005f60: 01800284 movi r6,10 + 8005f64: a80b883a mov r5,r21 + 8005f68: e009883a mov r4,fp + 8005f6c: 8cfff216 blt r17,r19,8005f38 <_dtoa_r+0xb4c> + 8005f70: 1011883a mov r8,r2 + 8005f74: 0029883a mov r20,zero + 8005f78: a80b883a mov r5,r21 + 8005f7c: 01800044 movi r6,1 + 8005f80: e009883a mov r4,fp + 8005f84: da000115 stw r8,4(sp) + 8005f88: 800911c0 call 800911c <__lshift> + 8005f8c: 900b883a mov r5,r18 + 8005f90: 1009883a mov r4,r2 + 8005f94: 102b883a mov r21,r2 + 8005f98: 80092580 call 8009258 <__mcmp> + 8005f9c: b8ffffc3 ldbu r3,-1(r23) + 8005fa0: 0081610e bge zero,r2,8006528 <_dtoa_r+0x113c> + 8005fa4: d9400317 ldw r5,12(sp) + 8005fa8: 00000306 br 8005fb8 <_dtoa_r+0xbcc> + 8005fac: 29017726 beq r5,r4,800658c <_dtoa_r+0x11a0> + 8005fb0: 20ffffc3 ldbu r3,-1(r4) + 8005fb4: 202f883a mov r23,r4 + 8005fb8: 18803fcc andi r2,r3,255 + 8005fbc: 1080201c xori r2,r2,128 + 8005fc0: 10bfe004 addi r2,r2,-128 + 8005fc4: 10800e60 cmpeqi r2,r2,57 + 8005fc8: b93fffc4 addi r4,r23,-1 + 8005fcc: 103ff71e bne r2,zero,8005fac <_dtoa_r+0xbc0> + 8005fd0: 18c00044 addi r3,r3,1 + 8005fd4: 20c00005 stb r3,0(r4) + 8005fd8: 900b883a mov r5,r18 + 8005fdc: e009883a mov r4,fp + 8005fe0: 8008a780 call 8008a78 <_Bfree> + 8005fe4: 803e9326 beq r16,zero,8005a34 <_dtoa_r+0x648> + 8005fe8: a0000426 beq r20,zero,8005ffc <_dtoa_r+0xc10> + 8005fec: a4000326 beq r20,r16,8005ffc <_dtoa_r+0xc10> + 8005ff0: a00b883a mov r5,r20 + 8005ff4: e009883a mov r4,fp + 8005ff8: 8008a780 call 8008a78 <_Bfree> + 8005ffc: 800b883a mov r5,r16 + 8006000: e009883a mov r4,fp + 8006004: 8008a780 call 8008a78 <_Bfree> + 8006008: 003e8a06 br 8005a34 <_dtoa_r+0x648> + 800600c: d8000915 stw zero,36(sp) + 8006010: a0003616 blt r20,zero,80060ec <_dtoa_r+0xd00> + 8006014: d8000515 stw zero,20(sp) + 8006018: d8c00217 ldw r3,8(sp) + 800601c: dd800415 stw r22,16(sp) + 8006020: d8000815 stw zero,32(sp) + 8006024: 188002a8 cmpgeui r2,r3,10 + 8006028: a5a9883a add r20,r20,r22 + 800602c: 103d9726 beq r2,zero,800568c <_dtoa_r+0x2a0> + 8006030: 00800044 movi r2,1 + 8006034: d8800715 stw r2,28(sp) + 8006038: 00bfffc4 movi r2,-1 + 800603c: 04bfffc4 movi r18,-1 + 8006040: 04000044 movi r16,1 + 8006044: d8000215 stw zero,8(sp) + 8006048: d8800615 stw r2,24(sp) + 800604c: d8001e15 stw zero,120(sp) + 8006050: d8800617 ldw r2,24(sp) + 8006054: e0001115 stw zero,68(fp) + 8006058: 000b883a mov r5,zero + 800605c: d8800b15 stw r2,44(sp) + 8006060: 003daa06 br 800570c <_dtoa_r+0x320> + 8006064: 18800160 cmpeqi r2,r3,5 + 8006068: 00c00044 movi r3,1 + 800606c: d8c00715 stw r3,28(sp) + 8006070: 10000d26 beq r2,zero,80060a8 <_dtoa_r+0xcbc> + 8006074: d8801e17 ldw r2,120(sp) + 8006078: d8c00417 ldw r3,16(sp) + 800607c: 10c5883a add r2,r2,r3 + 8006080: d8800b15 stw r2,44(sp) + 8006084: 10800044 addi r2,r2,1 + 8006088: d8800615 stw r2,24(sp) + 800608c: 100d883a mov r6,r2 + 8006090: 00bd9216 blt zero,r2,80056dc <_dtoa_r+0x2f0> + 8006094: 01800044 movi r6,1 + 8006098: 003d9006 br 80056dc <_dtoa_r+0x2f0> + 800609c: 188000a0 cmpeqi r2,r3,2 + 80060a0: d8000715 stw zero,28(sp) + 80060a4: 103d881e bne r2,zero,80056c8 <_dtoa_r+0x2dc> + 80060a8: e0001115 stw zero,68(fp) + 80060ac: 000b883a mov r5,zero + 80060b0: e009883a mov r4,fp + 80060b4: 80089d40 call 80089d4 <_Balloc> + 80060b8: d8800315 stw r2,12(sp) + 80060bc: e0801015 stw r2,64(fp) + 80060c0: 00bfffc4 movi r2,-1 + 80060c4: d8800b15 stw r2,44(sp) + 80060c8: 00800044 movi r2,1 + 80060cc: d8800715 stw r2,28(sp) + 80060d0: 00bfffc4 movi r2,-1 + 80060d4: d8001e15 stw zero,120(sp) + 80060d8: d8800615 stw r2,24(sp) + 80060dc: 003e8f06 br 8005b1c <_dtoa_r+0x730> + 80060e0: 00800044 movi r2,1 + 80060e4: d8800915 stw r2,36(sp) + 80060e8: a03d5c0e bge r20,zero,800565c <_dtoa_r+0x270> + 80060ec: 04800044 movi r18,1 + 80060f0: 9405c83a sub r2,r18,r16 + 80060f4: d8800515 stw r2,20(sp) + 80060f8: 0029883a mov r20,zero + 80060fc: 003d5806 br 8005660 <_dtoa_r+0x274> + 8006100: b009883a mov r4,r22 + 8006104: 800f62c0 call 800f62c <__floatsidf> + 8006108: a00d883a mov r6,r20 + 800610c: 980f883a mov r7,r19 + 8006110: 1009883a mov r4,r2 + 8006114: 180b883a mov r5,r3 + 8006118: 800e3000 call 800e300 <__eqdf2> + 800611c: 103d3e26 beq r2,zero,8005618 <_dtoa_r+0x22c> + 8006120: b5bfffc4 addi r22,r22,-1 + 8006124: 003d3c06 br 8005618 <_dtoa_r+0x22c> + 8006128: 00820134 movhi r2,2052 + 800612c: 109d2704 addi r2,r2,29852 + 8006130: d8800315 stw r2,12(sp) + 8006134: 003cdf06 br 80054b4 <_dtoa_r+0xc8> + 8006138: dc800817 ldw r18,32(sp) + 800613c: dcc00517 ldw r19,20(sp) + 8006140: 0021883a mov r16,zero + 8006144: 003f2f06 br 8005e04 <_dtoa_r+0xa18> + 8006148: a80b883a mov r5,r21 + 800614c: 100d883a mov r6,r2 + 8006150: e009883a mov r4,fp + 8006154: 800911c0 call 800911c <__lshift> + 8006158: 102b883a mov r21,r2 + 800615c: 003f6306 br 8005eec <_dtoa_r+0xb00> + 8006160: 00800704 movi r2,28 + 8006164: 003f5a06 br 8005ed0 <_dtoa_r+0xae4> + 8006168: 01000804 movi r4,32 + 800616c: 2089c83a sub r4,r4,r2 + 8006170: d8800117 ldw r2,4(sp) + 8006174: 1108983a sll r4,r2,r4 + 8006178: 003cf306 br 8005548 <_dtoa_r+0x15c> + 800617c: 04000044 movi r16,1 + 8006180: 003d4706 br 80056a0 <_dtoa_r+0x2b4> + 8006184: b00d883a mov r6,r22 + 8006188: 100b883a mov r5,r2 + 800618c: e009883a mov r4,fp + 8006190: 8008ff40 call 8008ff4 <__pow5mult> + 8006194: 1025883a mov r18,r2 + 8006198: d8800217 ldw r2,8(sp) + 800619c: 10800090 cmplti r2,r2,2 + 80061a0: 10012f1e bne r2,zero,8006660 <_dtoa_r+0x1274> + 80061a4: 0023883a mov r17,zero + 80061a8: 90800417 ldw r2,16(r18) + 80061ac: 10800104 addi r2,r2,4 + 80061b0: 100490ba slli r2,r2,2 + 80061b4: 9085883a add r2,r18,r2 + 80061b8: 11000017 ldw r4,0(r2) + 80061bc: 8008cc00 call 8008cc0 <__hi0bits> + 80061c0: 00c00804 movi r3,32 + 80061c4: 1885c83a sub r2,r3,r2 + 80061c8: 003f3806 br 8005eac <_dtoa_r+0xac0> + 80061cc: 800b883a mov r5,r16 + 80061d0: 000f883a mov r7,zero + 80061d4: 01800284 movi r6,10 + 80061d8: e009883a mov r4,fp + 80061dc: 8008a9c0 call 8008a9c <__multadd> + 80061e0: 1021883a mov r16,r2 + 80061e4: d8800b17 ldw r2,44(sp) + 80061e8: 00821b0e bge zero,r2,8006a58 <_dtoa_r+0x166c> + 80061ec: d8800615 stw r2,24(sp) + 80061f0: 04c0b316 blt zero,r19,80064c0 <_dtoa_r+0x10d4> + 80061f4: 8801341e bne r17,zero,80066c8 <_dtoa_r+0x12dc> + 80061f8: 8027883a mov r19,r16 + 80061fc: dc400317 ldw r17,12(sp) + 8006200: d8c00617 ldw r3,24(sp) + 8006204: d8800117 ldw r2,4(sp) + 8006208: 8dffffc4 addi r23,r17,-1 + 800620c: b8c7883a add r3,r23,r3 + 8006210: d8c00615 stw r3,24(sp) + 8006214: d8c00217 ldw r3,8(sp) + 8006218: 1080004c andi r2,r2,1 + 800621c: d8800815 stw r2,32(sp) + 8006220: 10c4b03a or r2,r2,r3 + 8006224: d8800715 stw r2,28(sp) + 8006228: 00002c06 br 80062dc <_dtoa_r+0xef0> + 800622c: b80b883a mov r5,r23 + 8006230: a809883a mov r4,r21 + 8006234: da000515 stw r8,20(sp) + 8006238: 80092580 call 8009258 <__mcmp> + 800623c: b80b883a mov r5,r23 + 8006240: e009883a mov r4,fp + 8006244: d8800115 stw r2,4(sp) + 8006248: 8008a780 call 8008a78 <_Bfree> + 800624c: d8800117 ldw r2,4(sp) + 8006250: da000517 ldw r8,20(sp) + 8006254: 1000021e bne r2,zero,8006260 <_dtoa_r+0xe74> + 8006258: d8c00717 ldw r3,28(sp) + 800625c: 1801f226 beq r3,zero,8006a28 <_dtoa_r+0x163c> + 8006260: 8dc00044 addi r23,r17,1 + 8006264: a0010516 blt r20,zero,800667c <_dtoa_r+0x1290> + 8006268: d8c00217 ldw r3,8(sp) + 800626c: a0e8b03a or r20,r20,r3 + 8006270: d8c00817 ldw r3,32(sp) + 8006274: 1d28b03a or r20,r3,r20 + 8006278: a0010026 beq r20,zero,800667c <_dtoa_r+0x1290> + 800627c: 00812816 blt zero,r2,8006720 <_dtoa_r+0x1334> + 8006280: d8800617 ldw r2,24(sp) + 8006284: 8a000005 stb r8,0(r17) + 8006288: 14412926 beq r2,r17,8006730 <_dtoa_r+0x1344> + 800628c: a80b883a mov r5,r21 + 8006290: 000f883a mov r7,zero + 8006294: 01800284 movi r6,10 + 8006298: e009883a mov r4,fp + 800629c: 8008a9c0 call 8008a9c <__multadd> + 80062a0: 102b883a mov r21,r2 + 80062a4: 000f883a mov r7,zero + 80062a8: 01800284 movi r6,10 + 80062ac: 800b883a mov r5,r16 + 80062b0: e009883a mov r4,fp + 80062b4: 84c02026 beq r16,r19,8006338 <_dtoa_r+0xf4c> + 80062b8: 8008a9c0 call 8008a9c <__multadd> + 80062bc: 980b883a mov r5,r19 + 80062c0: 000f883a mov r7,zero + 80062c4: 01800284 movi r6,10 + 80062c8: e009883a mov r4,fp + 80062cc: 1021883a mov r16,r2 + 80062d0: 8008a9c0 call 8008a9c <__multadd> + 80062d4: 1027883a mov r19,r2 + 80062d8: b823883a mov r17,r23 + 80062dc: 900b883a mov r5,r18 + 80062e0: a809883a mov r4,r21 + 80062e4: 80051dc0 call 80051dc + 80062e8: 800b883a mov r5,r16 + 80062ec: a809883a mov r4,r21 + 80062f0: 102d883a mov r22,r2 + 80062f4: 80092580 call 8009258 <__mcmp> + 80062f8: 980d883a mov r6,r19 + 80062fc: 900b883a mov r5,r18 + 8006300: e009883a mov r4,fp + 8006304: 1029883a mov r20,r2 + 8006308: 80092b00 call 80092b0 <__mdiff> + 800630c: 102f883a mov r23,r2 + 8006310: 10800317 ldw r2,12(r2) + 8006314: b2000c04 addi r8,r22,48 + 8006318: 103fc426 beq r2,zero,800622c <_dtoa_r+0xe40> + 800631c: b80b883a mov r5,r23 + 8006320: e009883a mov r4,fp + 8006324: da000115 stw r8,4(sp) + 8006328: 8008a780 call 8008a78 <_Bfree> + 800632c: 00800044 movi r2,1 + 8006330: da000117 ldw r8,4(sp) + 8006334: 003fca06 br 8006260 <_dtoa_r+0xe74> + 8006338: 8008a9c0 call 8008a9c <__multadd> + 800633c: 1021883a mov r16,r2 + 8006340: 1027883a mov r19,r2 + 8006344: 003fe406 br 80062d8 <_dtoa_r+0xeec> + 8006348: d8800217 ldw r2,8(sp) + 800634c: 108000d0 cmplti r2,r2,3 + 8006350: 10004b1e bne r2,zero,8006480 <_dtoa_r+0x1094> + 8006354: d8800617 ldw r2,24(sp) + 8006358: 103e0d1e bne r2,zero,8005b90 <_dtoa_r+0x7a4> + 800635c: 900b883a mov r5,r18 + 8006360: e009883a mov r4,fp + 8006364: 000f883a mov r7,zero + 8006368: 01800144 movi r6,5 + 800636c: 8008a9c0 call 8008a9c <__multadd> + 8006370: 100b883a mov r5,r2 + 8006374: a809883a mov r4,r21 + 8006378: 1025883a mov r18,r2 + 800637c: 80092580 call 8009258 <__mcmp> + 8006380: 00be030e bge zero,r2,8005b90 <_dtoa_r+0x7a4> + 8006384: d8c00317 ldw r3,12(sp) + 8006388: 00800c44 movi r2,49 + 800638c: 18800005 stb r2,0(r3) + 8006390: d8800417 ldw r2,16(sp) + 8006394: 1dc00044 addi r23,r3,1 + 8006398: 14400044 addi r17,r2,1 + 800639c: 900b883a mov r5,r18 + 80063a0: e009883a mov r4,fp + 80063a4: 8008a780 call 8008a78 <_Bfree> + 80063a8: 88800044 addi r2,r17,1 + 80063ac: d8800415 stw r2,16(sp) + 80063b0: 803f121e bne r16,zero,8005ffc <_dtoa_r+0xc10> + 80063b4: 003d9f06 br 8005a34 <_dtoa_r+0x648> + 80063b8: 900b883a mov r5,r18 + 80063bc: a809883a mov r4,r21 + 80063c0: 80092580 call 8009258 <__mcmp> + 80063c4: 103ed10e bge r2,zero,8005f0c <_dtoa_r+0xb20> + 80063c8: a80b883a mov r5,r21 + 80063cc: 000f883a mov r7,zero + 80063d0: 01800284 movi r6,10 + 80063d4: e009883a mov r4,fp + 80063d8: 8008a9c0 call 8008a9c <__multadd> + 80063dc: 102b883a mov r21,r2 + 80063e0: d8800417 ldw r2,16(sp) + 80063e4: 153fffc4 addi r20,r2,-1 + 80063e8: d8800717 ldw r2,28(sp) + 80063ec: 103f771e bne r2,zero,80061cc <_dtoa_r+0xde0> + 80063f0: d8800b17 ldw r2,44(sp) + 80063f4: 0081910e bge zero,r2,8006a3c <_dtoa_r+0x1650> + 80063f8: d8800615 stw r2,24(sp) + 80063fc: 003eca06 br 8005f28 <_dtoa_r+0xb3c> + 8006400: d9800817 ldw r6,32(sp) + 8006404: a80b883a mov r5,r21 + 8006408: e009883a mov r4,fp + 800640c: 8008ff40 call 8008ff4 <__pow5mult> + 8006410: 102b883a mov r21,r2 + 8006414: 003e9a06 br 8005e80 <_dtoa_r+0xa94> + 8006418: 00820134 movhi r2,2052 + 800641c: 1007883a mov r3,r2 + 8006420: 18dd3004 addi r3,r3,29888 + 8006424: 00820134 movhi r2,2052 + 8006428: d8c00315 stw r3,12(sp) + 800642c: 109d30c4 addi r2,r2,29891 + 8006430: 003da506 br 8005ac8 <_dtoa_r+0x6dc> + 8006434: d8800117 ldw r2,4(sp) + 8006438: 103e991e bne r2,zero,8005ea0 <_dtoa_r+0xab4> + 800643c: 00800434 movhi r2,16 + 8006440: 10bfffc4 addi r2,r2,-1 + 8006444: 8884703a and r2,r17,r2 + 8006448: 103e951e bne r2,zero,8005ea0 <_dtoa_r+0xab4> + 800644c: 8c5ffc2c andhi r17,r17,32752 + 8006450: 883e9326 beq r17,zero,8005ea0 <_dtoa_r+0xab4> + 8006454: d8800517 ldw r2,20(sp) + 8006458: a5000044 addi r20,r20,1 + 800645c: 04400044 movi r17,1 + 8006460: 10800044 addi r2,r2,1 + 8006464: d8800515 stw r2,20(sp) + 8006468: 003e8e06 br 8005ea4 <_dtoa_r+0xab8> + 800646c: 00800044 movi r2,1 + 8006470: 04800044 movi r18,1 + 8006474: d8800615 stw r2,24(sp) + 8006478: d8801e15 stw r2,120(sp) + 800647c: 003ef406 br 8006050 <_dtoa_r+0xc64> + 8006480: d8800417 ldw r2,16(sp) + 8006484: 10800044 addi r2,r2,1 + 8006488: d8800415 stw r2,16(sp) + 800648c: d8800717 ldw r2,28(sp) + 8006490: 103f571e bne r2,zero,80061f0 <_dtoa_r+0xe04> + 8006494: 900b883a mov r5,r18 + 8006498: a809883a mov r4,r21 + 800649c: 80051dc0 call 80051dc + 80064a0: 12000c04 addi r8,r2,48 + 80064a4: d8800317 ldw r2,12(sp) + 80064a8: 0029883a mov r20,zero + 80064ac: 15c00044 addi r23,r2,1 + 80064b0: 12000005 stb r8,0(r2) + 80064b4: 003eb006 br 8005f78 <_dtoa_r+0xb8c> + 80064b8: a005883a mov r2,r20 + 80064bc: 003e5506 br 8005e14 <_dtoa_r+0xa28> + 80064c0: 800b883a mov r5,r16 + 80064c4: 980d883a mov r6,r19 + 80064c8: e009883a mov r4,fp + 80064cc: 800911c0 call 800911c <__lshift> + 80064d0: 1021883a mov r16,r2 + 80064d4: 003f4706 br 80061f4 <_dtoa_r+0xe08> + 80064d8: 14a5c83a sub r18,r2,r18 + 80064dc: 003e3e06 br 8005dd8 <_dtoa_r+0x9ec> + 80064e0: 00820134 movhi r2,2052 + 80064e4: 109d4104 addi r2,r2,29956 + 80064e8: 11800817 ldw r6,32(r2) + 80064ec: 11c00917 ldw r7,36(r2) + 80064f0: d9000117 ldw r4,4(sp) + 80064f4: 880b883a mov r5,r17 + 80064f8: da400e15 stw r9,56(sp) + 80064fc: da800d15 stw r10,52(sp) + 8006500: 800da580 call 800da58 <__divdf3> + 8006504: d8800c15 stw r2,48(sp) + 8006508: 1827883a mov r19,r3 + 800650c: bdc003cc andi r23,r23,15 + 8006510: 040000c4 movi r16,3 + 8006514: da800d17 ldw r10,52(sp) + 8006518: da400e17 ldw r9,56(sp) + 800651c: 003c9206 br 8005768 <_dtoa_r+0x37c> + 8006520: d8000715 stw zero,28(sp) + 8006524: 003ed306 br 8006074 <_dtoa_r+0xc88> + 8006528: 1000031e bne r2,zero,8006538 <_dtoa_r+0x114c> + 800652c: da000117 ldw r8,4(sp) + 8006530: 4200004c andi r8,r8,1 + 8006534: 403e9b1e bne r8,zero,8005fa4 <_dtoa_r+0xbb8> + 8006538: 1805883a mov r2,r3 + 800653c: 00000206 br 8006548 <_dtoa_r+0x115c> + 8006540: b8bfff83 ldbu r2,-2(r23) + 8006544: 182f883a mov r23,r3 + 8006548: 10803fcc andi r2,r2,255 + 800654c: 1080201c xori r2,r2,128 + 8006550: 10bfe004 addi r2,r2,-128 + 8006554: 10800c18 cmpnei r2,r2,48 + 8006558: b8ffffc4 addi r3,r23,-1 + 800655c: 103ff826 beq r2,zero,8006540 <_dtoa_r+0x1154> + 8006560: 003e9d06 br 8005fd8 <_dtoa_r+0xbec> + 8006564: d8c00a17 ldw r3,40(sp) + 8006568: 1800bc26 beq r3,zero,800685c <_dtoa_r+0x1470> + 800656c: d8c00517 ldw r3,20(sp) + 8006570: 10810cc4 addi r2,r2,1075 + 8006574: a0a9883a add r20,r20,r2 + 8006578: 1885883a add r2,r3,r2 + 800657c: 1827883a mov r19,r3 + 8006580: dc800817 ldw r18,32(sp) + 8006584: d8800515 stw r2,20(sp) + 8006588: 003e1a06 br 8005df4 <_dtoa_r+0xa08> + 800658c: d8c00317 ldw r3,12(sp) + 8006590: 00800c44 movi r2,49 + 8006594: 18800005 stb r2,0(r3) + 8006598: d8800417 ldw r2,16(sp) + 800659c: 10800044 addi r2,r2,1 + 80065a0: d8800415 stw r2,16(sp) + 80065a4: 003e8c06 br 8005fd8 <_dtoa_r+0xbec> + 80065a8: 8009883a mov r4,r16 + 80065ac: 800f62c0 call 800f62c <__floatsidf> + 80065b0: 900d883a mov r6,r18 + 80065b4: 980f883a mov r7,r19 + 80065b8: 1009883a mov r4,r2 + 80065bc: 180b883a mov r5,r3 + 80065c0: 800e5600 call 800e560 <__muldf3> + 80065c4: 000d883a mov r6,zero + 80065c8: 01d00734 movhi r7,16412 + 80065cc: 1009883a mov r4,r2 + 80065d0: 180b883a mov r5,r3 + 80065d4: 800d0b80 call 800d0b8 <__adddf3> + 80065d8: d8800c15 stw r2,48(sp) + 80065dc: 00bf3034 movhi r2,64704 + 80065e0: 1885883a add r2,r3,r2 + 80065e4: d8800d15 stw r2,52(sp) + 80065e8: 9009883a mov r4,r18 + 80065ec: 980b883a mov r5,r19 + 80065f0: 000d883a mov r6,zero + 80065f4: 01d00534 movhi r7,16404 + 80065f8: 800ebec0 call 800ebec <__subdf3> + 80065fc: ddc00c17 ldw r23,48(sp) + 8006600: dcc00d17 ldw r19,52(sp) + 8006604: 1009883a mov r4,r2 + 8006608: b80d883a mov r6,r23 + 800660c: 980f883a mov r7,r19 + 8006610: 180b883a mov r5,r3 + 8006614: 1025883a mov r18,r2 + 8006618: 1821883a mov r16,r3 + 800661c: 800e3800 call 800e380 <__gedf2> + 8006620: 0080ee16 blt zero,r2,80069dc <_dtoa_r+0x15f0> + 8006624: 99e0003c xorhi r7,r19,32768 + 8006628: b80d883a mov r6,r23 + 800662c: 9009883a mov r4,r18 + 8006630: 800b883a mov r5,r16 + 8006634: 800e4700 call 800e470 <__ledf2> + 8006638: 103d380e bge r2,zero,8005b1c <_dtoa_r+0x730> + 800663c: 0025883a mov r18,zero + 8006640: 0021883a mov r16,zero + 8006644: 003d5206 br 8005b90 <_dtoa_r+0x7a4> + 8006648: d8800417 ldw r2,16(sp) + 800664c: 1000ad1e bne r2,zero,8006904 <_dtoa_r+0x1518> + 8006650: dc800117 ldw r18,4(sp) + 8006654: 8827883a mov r19,r17 + 8006658: 04000084 movi r16,2 + 800665c: 003c5b06 br 80057cc <_dtoa_r+0x3e0> + 8006660: d8800117 ldw r2,4(sp) + 8006664: 103ecf1e bne r2,zero,80061a4 <_dtoa_r+0xdb8> + 8006668: 00800434 movhi r2,16 + 800666c: 10bfffc4 addi r2,r2,-1 + 8006670: 8884703a and r2,r17,r2 + 8006674: 103f7526 beq r2,zero,800644c <_dtoa_r+0x1060> + 8006678: 003eca06 br 80061a4 <_dtoa_r+0xdb8> + 800667c: 00800e0e bge zero,r2,80066b8 <_dtoa_r+0x12cc> + 8006680: a80b883a mov r5,r21 + 8006684: 01800044 movi r6,1 + 8006688: e009883a mov r4,fp + 800668c: da000115 stw r8,4(sp) + 8006690: 800911c0 call 800911c <__lshift> + 8006694: 900b883a mov r5,r18 + 8006698: 1009883a mov r4,r2 + 800669c: 102b883a mov r21,r2 + 80066a0: 80092580 call 8009258 <__mcmp> + 80066a4: da000117 ldw r8,4(sp) + 80066a8: 0080d50e bge zero,r2,8006a00 <_dtoa_r+0x1614> + 80066ac: 42000e60 cmpeqi r8,r8,57 + 80066b0: 4000c31e bne r8,zero,80069c0 <_dtoa_r+0x15d4> + 80066b4: b2000c44 addi r8,r22,49 + 80066b8: 8029883a mov r20,r16 + 80066bc: 8a000005 stb r8,0(r17) + 80066c0: 9821883a mov r16,r19 + 80066c4: 003e4406 br 8005fd8 <_dtoa_r+0xbec> + 80066c8: 81400117 ldw r5,4(r16) + 80066cc: e009883a mov r4,fp + 80066d0: 80089d40 call 80089d4 <_Balloc> + 80066d4: 81800417 ldw r6,16(r16) + 80066d8: 81400304 addi r5,r16,12 + 80066dc: 11000304 addi r4,r2,12 + 80066e0: 31800084 addi r6,r6,2 + 80066e4: 300c90ba slli r6,r6,2 + 80066e8: 1023883a mov r17,r2 + 80066ec: 80086b80 call 80086b8 + 80066f0: 01800044 movi r6,1 + 80066f4: 880b883a mov r5,r17 + 80066f8: e009883a mov r4,fp + 80066fc: 800911c0 call 800911c <__lshift> + 8006700: 1027883a mov r19,r2 + 8006704: 003ebd06 br 80061fc <_dtoa_r+0xe10> + 8006708: dd400117 ldw r21,4(sp) + 800670c: 003cc906 br 8005a34 <_dtoa_r+0x648> + 8006710: d8800517 ldw r2,20(sp) + 8006714: d8c00617 ldw r3,24(sp) + 8006718: 10e7c83a sub r19,r2,r3 + 800671c: 003db506 br 8005df4 <_dtoa_r+0xa08> + 8006720: 40800e58 cmpnei r2,r8,57 + 8006724: 1000a626 beq r2,zero,80069c0 <_dtoa_r+0x15d4> + 8006728: 42000044 addi r8,r8,1 + 800672c: 003fe206 br 80066b8 <_dtoa_r+0x12cc> + 8006730: 8029883a mov r20,r16 + 8006734: 9821883a mov r16,r19 + 8006738: 003e0f06 br 8005f78 <_dtoa_r+0xb8c> + 800673c: d9000c17 ldw r4,48(sp) + 8006740: d9400d17 ldw r5,52(sp) + 8006744: da401015 stw r9,64(sp) + 8006748: 800e5600 call 800e560 <__muldf3> + 800674c: d9000e17 ldw r4,56(sp) + 8006750: d8c00d15 stw r3,52(sp) + 8006754: da401017 ldw r9,64(sp) + 8006758: d8c00317 ldw r3,12(sp) + 800675c: d8800c15 stw r2,48(sp) + 8006760: 20800058 cmpnei r2,r4,1 + 8006764: 1a400005 stb r9,0(r3) + 8006768: 1907883a add r3,r3,r4 + 800676c: 1809883a mov r4,r3 + 8006770: 10001d26 beq r2,zero,80067e8 <_dtoa_r+0x13fc> + 8006774: 8007883a mov r3,r16 + 8006778: 9005883a mov r2,r18 + 800677c: dc400e15 stw r17,56(sp) + 8006780: 2021883a mov r16,r4 + 8006784: 000d883a mov r6,zero + 8006788: 01d00934 movhi r7,16420 + 800678c: 1009883a mov r4,r2 + 8006790: 180b883a mov r5,r3 + 8006794: 800e5600 call 800e560 <__muldf3> + 8006798: 180b883a mov r5,r3 + 800679c: 1009883a mov r4,r2 + 80067a0: 1825883a mov r18,r3 + 80067a4: 1023883a mov r17,r2 + 80067a8: 800f5ac0 call 800f5ac <__fixdfsi> + 80067ac: 1009883a mov r4,r2 + 80067b0: 1027883a mov r19,r2 + 80067b4: 800f62c0 call 800f62c <__floatsidf> + 80067b8: 100d883a mov r6,r2 + 80067bc: 180f883a mov r7,r3 + 80067c0: 8809883a mov r4,r17 + 80067c4: 900b883a mov r5,r18 + 80067c8: bdc00044 addi r23,r23,1 + 80067cc: 9cc00c04 addi r19,r19,48 + 80067d0: 800ebec0 call 800ebec <__subdf3> + 80067d4: bcffffc5 stb r19,-1(r23) + 80067d8: bc3fea1e bne r23,r16,8006784 <_dtoa_r+0x1398> + 80067dc: dc400e17 ldw r17,56(sp) + 80067e0: 1025883a mov r18,r2 + 80067e4: 1821883a mov r16,r3 + 80067e8: d9000c17 ldw r4,48(sp) + 80067ec: d9400d17 ldw r5,52(sp) + 80067f0: 000d883a mov r6,zero + 80067f4: 01cff834 movhi r7,16352 + 80067f8: 800d0b80 call 800d0b8 <__adddf3> + 80067fc: 100d883a mov r6,r2 + 8006800: 180f883a mov r7,r3 + 8006804: 9009883a mov r4,r18 + 8006808: 800b883a mov r5,r16 + 800680c: 800e3800 call 800e380 <__gedf2> + 8006810: 00807516 blt zero,r2,80069e8 <_dtoa_r+0x15fc> + 8006814: d9800c17 ldw r6,48(sp) + 8006818: d9c00d17 ldw r7,52(sp) + 800681c: 0009883a mov r4,zero + 8006820: 014ff834 movhi r5,16352 + 8006824: 800ebec0 call 800ebec <__subdf3> + 8006828: 100d883a mov r6,r2 + 800682c: 180f883a mov r7,r3 + 8006830: 9009883a mov r4,r18 + 8006834: 800b883a mov r5,r16 + 8006838: 800e4700 call 800e470 <__ledf2> + 800683c: 103cb70e bge r2,zero,8005b1c <_dtoa_r+0x730> + 8006840: 00000106 br 8006848 <_dtoa_r+0x145c> + 8006844: 182f883a mov r23,r3 + 8006848: b8bfffc7 ldb r2,-1(r23) + 800684c: b8ffffc4 addi r3,r23,-1 + 8006850: 10800c20 cmpeqi r2,r2,48 + 8006854: 103ffb1e bne r2,zero,8006844 <_dtoa_r+0x1458> + 8006858: 003c7306 br 8005a28 <_dtoa_r+0x63c> + 800685c: d8c01217 ldw r3,72(sp) + 8006860: d9000517 ldw r4,20(sp) + 8006864: 00800d84 movi r2,54 + 8006868: 10c5c83a sub r2,r2,r3 + 800686c: a0a9883a add r20,r20,r2 + 8006870: 2085883a add r2,r4,r2 + 8006874: 2027883a mov r19,r4 + 8006878: dc800817 ldw r18,32(sp) + 800687c: d8800515 stw r2,20(sp) + 8006880: 003d5c06 br 8005df4 <_dtoa_r+0xa08> + 8006884: d8800617 ldw r2,24(sp) + 8006888: 103f4726 beq r2,zero,80065a8 <_dtoa_r+0x11bc> + 800688c: ddc00b17 ldw r23,44(sp) + 8006890: 05fca20e bge zero,r23,8005b1c <_dtoa_r+0x730> + 8006894: 980b883a mov r5,r19 + 8006898: 000d883a mov r6,zero + 800689c: 01d00934 movhi r7,16420 + 80068a0: 9009883a mov r4,r18 + 80068a4: 800e5600 call 800e560 <__muldf3> + 80068a8: 81000044 addi r4,r16,1 + 80068ac: 1025883a mov r18,r2 + 80068b0: 1827883a mov r19,r3 + 80068b4: 800f62c0 call 800f62c <__floatsidf> + 80068b8: 900d883a mov r6,r18 + 80068bc: 980f883a mov r7,r19 + 80068c0: 1009883a mov r4,r2 + 80068c4: 180b883a mov r5,r3 + 80068c8: 800e5600 call 800e560 <__muldf3> + 80068cc: 000d883a mov r6,zero + 80068d0: 01d00734 movhi r7,16412 + 80068d4: 1009883a mov r4,r2 + 80068d8: 180b883a mov r5,r3 + 80068dc: 800d0b80 call 800d0b8 <__adddf3> + 80068e0: d8800c15 stw r2,48(sp) + 80068e4: d8800417 ldw r2,16(sp) + 80068e8: ddc00e15 stw r23,56(sp) + 80068ec: 10bfffc4 addi r2,r2,-1 + 80068f0: d8800f15 stw r2,60(sp) + 80068f4: 00bf3034 movhi r2,64704 + 80068f8: 1885883a add r2,r3,r2 + 80068fc: d8800d15 stw r2,52(sp) + 8006900: 003bd006 br 8005844 <_dtoa_r+0x458> + 8006904: d8800417 ldw r2,16(sp) + 8006908: d9000117 ldw r4,4(sp) + 800690c: 880b883a mov r5,r17 + 8006910: 00afc83a sub r23,zero,r2 + 8006914: b88003cc andi r2,r23,15 + 8006918: 100690fa slli r3,r2,3 + 800691c: 00820134 movhi r2,2052 + 8006920: 109d4b04 addi r2,r2,29996 + 8006924: 10c5883a add r2,r2,r3 + 8006928: 11800017 ldw r6,0(r2) + 800692c: 11c00117 ldw r7,4(r2) + 8006930: b82fd13a srai r23,r23,4 + 8006934: 800e5600 call 800e560 <__muldf3> + 8006938: 1025883a mov r18,r2 + 800693c: 1827883a mov r19,r3 + 8006940: b8004a26 beq r23,zero,8006a6c <_dtoa_r+0x1680> + 8006944: 02020134 movhi r8,2052 + 8006948: 04000084 movi r16,2 + 800694c: 421d4104 addi r8,r8,29956 + 8006950: dc400c15 stw r17,48(sp) + 8006954: 000f883a mov r7,zero + 8006958: 8023883a mov r17,r16 + 800695c: 4021883a mov r16,r8 + 8006960: b980004c andi r6,r23,1 + 8006964: 1009883a mov r4,r2 + 8006968: b82fd07a srai r23,r23,1 + 800696c: 180b883a mov r5,r3 + 8006970: 30000526 beq r6,zero,8006988 <_dtoa_r+0x159c> + 8006974: 81c00117 ldw r7,4(r16) + 8006978: 81800017 ldw r6,0(r16) + 800697c: 8c400044 addi r17,r17,1 + 8006980: 800e5600 call 800e560 <__muldf3> + 8006984: 01c00044 movi r7,1 + 8006988: 84000204 addi r16,r16,8 + 800698c: b83ff41e bne r23,zero,8006960 <_dtoa_r+0x1574> + 8006990: 39c03fcc andi r7,r7,255 + 8006994: 8821883a mov r16,r17 + 8006998: dc400c17 ldw r17,48(sp) + 800699c: 383b8b26 beq r7,zero,80057cc <_dtoa_r+0x3e0> + 80069a0: 1025883a mov r18,r2 + 80069a4: 1827883a mov r19,r3 + 80069a8: 003b8806 br 80057cc <_dtoa_r+0x3e0> + 80069ac: d8800417 ldw r2,16(sp) + 80069b0: 02000c44 movi r8,49 + 80069b4: 10800044 addi r2,r2,1 + 80069b8: d8800415 stw r2,16(sp) + 80069bc: 003cf606 br 8005d98 <_dtoa_r+0x9ac> + 80069c0: 00800e44 movi r2,57 + 80069c4: 8029883a mov r20,r16 + 80069c8: 88800005 stb r2,0(r17) + 80069cc: 9821883a mov r16,r19 + 80069d0: 00c00e44 movi r3,57 + 80069d4: d9400317 ldw r5,12(sp) + 80069d8: 003d7706 br 8005fb8 <_dtoa_r+0xbcc> + 80069dc: 0025883a mov r18,zero + 80069e0: 0021883a mov r16,zero + 80069e4: 003e6706 br 8006384 <_dtoa_r+0xf98> + 80069e8: d8800f17 ldw r2,60(sp) + 80069ec: ba3fffc3 ldbu r8,-1(r23) + 80069f0: d9000317 ldw r4,12(sp) + 80069f4: 10800044 addi r2,r2,1 + 80069f8: d8800415 stw r2,16(sp) + 80069fc: 003cdf06 br 8005d7c <_dtoa_r+0x990> + 8006a00: 103f2d1e bne r2,zero,80066b8 <_dtoa_r+0x12cc> + 8006a04: 4080004c andi r2,r8,1 + 8006a08: 103f281e bne r2,zero,80066ac <_dtoa_r+0x12c0> + 8006a0c: 003f2a06 br 80066b8 <_dtoa_r+0x12cc> + 8006a10: d8800f17 ldw r2,60(sp) + 8006a14: 8811883a mov r8,r17 + 8006a18: d9000317 ldw r4,12(sp) + 8006a1c: 10800044 addi r2,r2,1 + 8006a20: d8800415 stw r2,16(sp) + 8006a24: 003cd506 br 8005d7c <_dtoa_r+0x990> + 8006a28: 40800e60 cmpeqi r2,r8,57 + 8006a2c: 8dc00044 addi r23,r17,1 + 8006a30: 103fe31e bne r2,zero,80069c0 <_dtoa_r+0x15d4> + 8006a34: 053f1f16 blt zero,r20,80066b4 <_dtoa_r+0x12c8> + 8006a38: 003f1f06 br 80066b8 <_dtoa_r+0x12cc> + 8006a3c: d8800217 ldw r2,8(sp) + 8006a40: 108000c8 cmpgei r2,r2,3 + 8006a44: 103e9326 beq r2,zero,8006494 <_dtoa_r+0x10a8> + 8006a48: d8800b17 ldw r2,44(sp) + 8006a4c: dd000415 stw r20,16(sp) + 8006a50: d8800615 stw r2,24(sp) + 8006a54: 003e3f06 br 8006354 <_dtoa_r+0xf68> + 8006a58: d8800217 ldw r2,8(sp) + 8006a5c: 108000c8 cmpgei r2,r2,3 + 8006a60: 103ff91e bne r2,zero,8006a48 <_dtoa_r+0x165c> + 8006a64: d8800b17 ldw r2,44(sp) + 8006a68: 003de006 br 80061ec <_dtoa_r+0xe00> + 8006a6c: 04000084 movi r16,2 + 8006a70: 003b5606 br 80057cc <_dtoa_r+0x3e0> + 8006a74: d8800f17 ldw r2,60(sp) + 8006a78: d9000317 ldw r4,12(sp) + 8006a7c: 10800044 addi r2,r2,1 + 8006a80: d8800415 stw r2,16(sp) + 8006a84: 003cbd06 br 8005d7c <_dtoa_r+0x990> + 8006a88: 00820134 movhi r2,2052 + 8006a8c: 109d3104 addi r2,r2,29892 + 8006a90: d8800315 stw r2,12(sp) + 8006a94: 003a8706 br 80054b4 <_dtoa_r+0xc8> + 8006a98: 000b883a mov r5,zero + 8006a9c: 003b1b06 br 800570c <_dtoa_r+0x320> + 8006aa0: 18c00120 cmpeqi r3,r3,4 + 8006aa4: 183d0f1e bne r3,zero,8005ee4 <_dtoa_r+0xaf8> + 8006aa8: 00c00f04 movi r3,60 + 8006aac: 1885c83a sub r2,r3,r2 + 8006ab0: 003d0706 br 8005ed0 <_dtoa_r+0xae4> + +08006ab4 <__sflush_r>: + 8006ab4: 2880030b ldhu r2,12(r5) + 8006ab8: defffb04 addi sp,sp,-20 + 8006abc: dcc00315 stw r19,12(sp) + 8006ac0: dc000015 stw r16,0(sp) + 8006ac4: dfc00415 stw ra,16(sp) + 8006ac8: dc800215 stw r18,8(sp) + 8006acc: dc400115 stw r17,4(sp) + 8006ad0: 10c0020c andi r3,r2,8 + 8006ad4: 2821883a mov r16,r5 + 8006ad8: 2027883a mov r19,r4 + 8006adc: 18003f1e bne r3,zero,8006bdc <__sflush_r+0x128> + 8006ae0: 28c00117 ldw r3,4(r5) + 8006ae4: 10820014 ori r2,r2,2048 + 8006ae8: 2880030d sth r2,12(r5) + 8006aec: 00c0550e bge zero,r3,8006c44 <__sflush_r+0x190> + 8006af0: 82000a17 ldw r8,40(r16) + 8006af4: 40003126 beq r8,zero,8006bbc <__sflush_r+0x108> + 8006af8: 9c400017 ldw r17,0(r19) + 8006afc: 1104000c andi r4,r2,4096 + 8006b00: 98000015 stw zero,0(r19) + 8006b04: 1007883a mov r3,r2 + 8006b08: 81400717 ldw r5,28(r16) + 8006b0c: 2000521e bne r4,zero,8006c58 <__sflush_r+0x1a4> + 8006b10: 01c00044 movi r7,1 + 8006b14: 000d883a mov r6,zero + 8006b18: 9809883a mov r4,r19 + 8006b1c: 403ee83a callr r8 + 8006b20: 10ffffd8 cmpnei r3,r2,-1 + 8006b24: 18005826 beq r3,zero,8006c88 <__sflush_r+0x1d4> + 8006b28: 80c0030b ldhu r3,12(r16) + 8006b2c: 82000a17 ldw r8,40(r16) + 8006b30: 81400717 ldw r5,28(r16) + 8006b34: 18c0010c andi r3,r3,4 + 8006b38: 18000626 beq r3,zero,8006b54 <__sflush_r+0xa0> + 8006b3c: 81000117 ldw r4,4(r16) + 8006b40: 80c00c17 ldw r3,48(r16) + 8006b44: 1105c83a sub r2,r2,r4 + 8006b48: 18000226 beq r3,zero,8006b54 <__sflush_r+0xa0> + 8006b4c: 80c00f17 ldw r3,60(r16) + 8006b50: 10c5c83a sub r2,r2,r3 + 8006b54: 000f883a mov r7,zero + 8006b58: 100d883a mov r6,r2 + 8006b5c: 9809883a mov r4,r19 + 8006b60: 403ee83a callr r8 + 8006b64: 10ffffd8 cmpnei r3,r2,-1 + 8006b68: 18003d1e bne r3,zero,8006c60 <__sflush_r+0x1ac> + 8006b6c: 99000017 ldw r4,0(r19) + 8006b70: 80c0030b ldhu r3,12(r16) + 8006b74: 20004e26 beq r4,zero,8006cb0 <__sflush_r+0x1fc> + 8006b78: 21400760 cmpeqi r5,r4,29 + 8006b7c: 2800021e bne r5,zero,8006b88 <__sflush_r+0xd4> + 8006b80: 210005a0 cmpeqi r4,r4,22 + 8006b84: 20002c26 beq r4,zero,8006c38 <__sflush_r+0x184> + 8006b88: 80800417 ldw r2,16(r16) + 8006b8c: 18fdffcc andi r3,r3,63487 + 8006b90: 80c0030d sth r3,12(r16) + 8006b94: 80000115 stw zero,4(r16) + 8006b98: 80800015 stw r2,0(r16) + 8006b9c: 81400c17 ldw r5,48(r16) + 8006ba0: 9c400015 stw r17,0(r19) + 8006ba4: 28000526 beq r5,zero,8006bbc <__sflush_r+0x108> + 8006ba8: 80801004 addi r2,r16,64 + 8006bac: 28800226 beq r5,r2,8006bb8 <__sflush_r+0x104> + 8006bb0: 9809883a mov r4,r19 + 8006bb4: 80071c40 call 80071c4 <_free_r> + 8006bb8: 80000c15 stw zero,48(r16) + 8006bbc: 0005883a mov r2,zero + 8006bc0: dfc00417 ldw ra,16(sp) + 8006bc4: dcc00317 ldw r19,12(sp) + 8006bc8: dc800217 ldw r18,8(sp) + 8006bcc: dc400117 ldw r17,4(sp) + 8006bd0: dc000017 ldw r16,0(sp) + 8006bd4: dec00504 addi sp,sp,20 + 8006bd8: f800283a ret + 8006bdc: 2c800417 ldw r18,16(r5) + 8006be0: 903ff626 beq r18,zero,8006bbc <__sflush_r+0x108> + 8006be4: 2c400017 ldw r17,0(r5) + 8006be8: 108000cc andi r2,r2,3 + 8006bec: 2c800015 stw r18,0(r5) + 8006bf0: 8ca3c83a sub r17,r17,r18 + 8006bf4: 1000161e bne r2,zero,8006c50 <__sflush_r+0x19c> + 8006bf8: 28800517 ldw r2,20(r5) + 8006bfc: 80800215 stw r2,8(r16) + 8006c00: 04400316 blt zero,r17,8006c10 <__sflush_r+0x15c> + 8006c04: 003fed06 br 8006bbc <__sflush_r+0x108> + 8006c08: 90a5883a add r18,r18,r2 + 8006c0c: 047feb0e bge zero,r17,8006bbc <__sflush_r+0x108> + 8006c10: 80800917 ldw r2,36(r16) + 8006c14: 81400717 ldw r5,28(r16) + 8006c18: 880f883a mov r7,r17 + 8006c1c: 900d883a mov r6,r18 + 8006c20: 9809883a mov r4,r19 + 8006c24: 103ee83a callr r2 + 8006c28: 88a3c83a sub r17,r17,r2 + 8006c2c: 00bff616 blt zero,r2,8006c08 <__sflush_r+0x154> + 8006c30: 80c0030b ldhu r3,12(r16) + 8006c34: 00bfffc4 movi r2,-1 + 8006c38: 18c01014 ori r3,r3,64 + 8006c3c: 80c0030d sth r3,12(r16) + 8006c40: 003fdf06 br 8006bc0 <__sflush_r+0x10c> + 8006c44: 28c00f17 ldw r3,60(r5) + 8006c48: 00ffa916 blt zero,r3,8006af0 <__sflush_r+0x3c> + 8006c4c: 003fdb06 br 8006bbc <__sflush_r+0x108> + 8006c50: 0005883a mov r2,zero + 8006c54: 003fe906 br 8006bfc <__sflush_r+0x148> + 8006c58: 80801417 ldw r2,80(r16) + 8006c5c: 003fb506 br 8006b34 <__sflush_r+0x80> + 8006c60: 80c0030b ldhu r3,12(r16) + 8006c64: 81000417 ldw r4,16(r16) + 8006c68: 80000115 stw zero,4(r16) + 8006c6c: 197dffcc andi r5,r3,63487 + 8006c70: 8140030d sth r5,12(r16) + 8006c74: 81000015 stw r4,0(r16) + 8006c78: 18c4000c andi r3,r3,4096 + 8006c7c: 183fc726 beq r3,zero,8006b9c <__sflush_r+0xe8> + 8006c80: 80801415 stw r2,80(r16) + 8006c84: 003fc506 br 8006b9c <__sflush_r+0xe8> + 8006c88: 98c00017 ldw r3,0(r19) + 8006c8c: 183fa626 beq r3,zero,8006b28 <__sflush_r+0x74> + 8006c90: 19000760 cmpeqi r4,r3,29 + 8006c94: 20000e1e bne r4,zero,8006cd0 <__sflush_r+0x21c> + 8006c98: 18c00598 cmpnei r3,r3,22 + 8006c9c: 18000c26 beq r3,zero,8006cd0 <__sflush_r+0x21c> + 8006ca0: 80c0030b ldhu r3,12(r16) + 8006ca4: 18c01014 ori r3,r3,64 + 8006ca8: 80c0030d sth r3,12(r16) + 8006cac: 003fc406 br 8006bc0 <__sflush_r+0x10c> + 8006cb0: 81000417 ldw r4,16(r16) + 8006cb4: 197dffcc andi r5,r3,63487 + 8006cb8: 8140030d sth r5,12(r16) + 8006cbc: 80000115 stw zero,4(r16) + 8006cc0: 81000015 stw r4,0(r16) + 8006cc4: 18c4000c andi r3,r3,4096 + 8006cc8: 183fb426 beq r3,zero,8006b9c <__sflush_r+0xe8> + 8006ccc: 003fec06 br 8006c80 <__sflush_r+0x1cc> + 8006cd0: 9c400015 stw r17,0(r19) + 8006cd4: 0005883a mov r2,zero + 8006cd8: 003fb906 br 8006bc0 <__sflush_r+0x10c> + +08006cdc <_fflush_r>: + 8006cdc: defffd04 addi sp,sp,-12 + 8006ce0: dc000115 stw r16,4(sp) + 8006ce4: dfc00215 stw ra,8(sp) + 8006ce8: 2021883a mov r16,r4 + 8006cec: 20000226 beq r4,zero,8006cf8 <_fflush_r+0x1c> + 8006cf0: 20800e17 ldw r2,56(r4) + 8006cf4: 10000726 beq r2,zero,8006d14 <_fflush_r+0x38> + 8006cf8: 2880030f ldh r2,12(r5) + 8006cfc: 10000a1e bne r2,zero,8006d28 <_fflush_r+0x4c> + 8006d00: 0005883a mov r2,zero + 8006d04: dfc00217 ldw ra,8(sp) + 8006d08: dc000117 ldw r16,4(sp) + 8006d0c: dec00304 addi sp,sp,12 + 8006d10: f800283a ret + 8006d14: d9400015 stw r5,0(sp) + 8006d18: 80070600 call 8007060 <__sinit> + 8006d1c: d9400017 ldw r5,0(sp) + 8006d20: 2880030f ldh r2,12(r5) + 8006d24: 103ff626 beq r2,zero,8006d00 <_fflush_r+0x24> + 8006d28: 8009883a mov r4,r16 + 8006d2c: dfc00217 ldw ra,8(sp) + 8006d30: dc000117 ldw r16,4(sp) + 8006d34: dec00304 addi sp,sp,12 + 8006d38: 8006ab41 jmpi 8006ab4 <__sflush_r> + +08006d3c : + 8006d3c: 200b883a mov r5,r4 + 8006d40: 20000326 beq r4,zero,8006d50 + 8006d44: 00820174 movhi r2,2053 + 8006d48: 1132af17 ldw r4,-13636(r2) + 8006d4c: 8006cdc1 jmpi 8006cdc <_fflush_r> + 8006d50: 00820174 movhi r2,2053 + 8006d54: 1132ae17 ldw r4,-13640(r2) + 8006d58: 01420034 movhi r5,2048 + 8006d5c: 295b3704 addi r5,r5,27868 + 8006d60: 8007a281 jmpi 8007a28 <_fwalk_reent> + +08006d64 <__fp_lock>: + 8006d64: 0005883a mov r2,zero + 8006d68: f800283a ret + +08006d6c <_cleanup_r>: + 8006d6c: 01420074 movhi r5,2049 + 8006d70: 296eb904 addi r5,r5,-17692 + 8006d74: 8007a281 jmpi 8007a28 <_fwalk_reent> + +08006d78 <__sinit.part.0>: + 8006d78: 00c20034 movhi r3,2048 + 8006d7c: 20800117 ldw r2,4(r4) + 8006d80: 18db5b04 addi r3,r3,28012 + 8006d84: 20c00f15 stw r3,60(r4) + 8006d88: 2140bb04 addi r5,r4,748 + 8006d8c: 00c000c4 movi r3,3 + 8006d90: 20c0b915 stw r3,740(r4) + 8006d94: 2140ba15 stw r5,744(r4) + 8006d98: 2000b815 stw zero,736(r4) + 8006d9c: 10001705 stb zero,92(r2) + 8006da0: 10001745 stb zero,93(r2) + 8006da4: 10001785 stb zero,94(r2) + 8006da8: 100017c5 stb zero,95(r2) + 8006dac: 10001805 stb zero,96(r2) + 8006db0: 10001845 stb zero,97(r2) + 8006db4: 10001885 stb zero,98(r2) + 8006db8: 100018c5 stb zero,99(r2) + 8006dbc: 00c00104 movi r3,4 + 8006dc0: 10c00315 stw r3,12(r2) + 8006dc4: 02020074 movhi r8,2049 + 8006dc8: 20c00217 ldw r3,8(r4) + 8006dcc: 01c20074 movhi r7,2049 + 8006dd0: 01820074 movhi r6,2049 + 8006dd4: 01420074 movhi r5,2049 + 8006dd8: 42287104 addi r8,r8,-24124 + 8006ddc: 39e88804 addi r7,r7,-24032 + 8006de0: 31a8a804 addi r6,r6,-23904 + 8006de4: 2968bf04 addi r5,r5,-23812 + 8006de8: 02400074 movhi r9,1 + 8006dec: 10001915 stw zero,100(r2) + 8006df0: 10000015 stw zero,0(r2) + 8006df4: 10000115 stw zero,4(r2) + 8006df8: 10000215 stw zero,8(r2) + 8006dfc: 10000415 stw zero,16(r2) + 8006e00: 10000515 stw zero,20(r2) + 8006e04: 10000615 stw zero,24(r2) + 8006e08: 10800715 stw r2,28(r2) + 8006e0c: 12000815 stw r8,32(r2) + 8006e10: 11c00915 stw r7,36(r2) + 8006e14: 11800a15 stw r6,40(r2) + 8006e18: 11400b15 stw r5,44(r2) + 8006e1c: 4a400284 addi r9,r9,10 + 8006e20: 1a400315 stw r9,12(r3) + 8006e24: 18001915 stw zero,100(r3) + 8006e28: 18000015 stw zero,0(r3) + 8006e2c: 18000115 stw zero,4(r3) + 8006e30: 18000215 stw zero,8(r3) + 8006e34: 18000415 stw zero,16(r3) + 8006e38: 18001705 stb zero,92(r3) + 8006e3c: 18001745 stb zero,93(r3) + 8006e40: 18001785 stb zero,94(r3) + 8006e44: 180017c5 stb zero,95(r3) + 8006e48: 18001805 stb zero,96(r3) + 8006e4c: 18001845 stb zero,97(r3) + 8006e50: 18001885 stb zero,98(r3) + 8006e54: 180018c5 stb zero,99(r3) + 8006e58: 20800317 ldw r2,12(r4) + 8006e5c: 024000b4 movhi r9,2 + 8006e60: 18000515 stw zero,20(r3) + 8006e64: 18000615 stw zero,24(r3) + 8006e68: 18c00715 stw r3,28(r3) + 8006e6c: 1a000815 stw r8,32(r3) + 8006e70: 19c00915 stw r7,36(r3) + 8006e74: 19800a15 stw r6,40(r3) + 8006e78: 19400b15 stw r5,44(r3) + 8006e7c: 4a400484 addi r9,r9,18 + 8006e80: 10001915 stw zero,100(r2) + 8006e84: 10000015 stw zero,0(r2) + 8006e88: 10000115 stw zero,4(r2) + 8006e8c: 10000215 stw zero,8(r2) + 8006e90: 12400315 stw r9,12(r2) + 8006e94: 10000415 stw zero,16(r2) + 8006e98: 10000515 stw zero,20(r2) + 8006e9c: 10000615 stw zero,24(r2) + 8006ea0: 10001705 stb zero,92(r2) + 8006ea4: 10001745 stb zero,93(r2) + 8006ea8: 10001785 stb zero,94(r2) + 8006eac: 100017c5 stb zero,95(r2) + 8006eb0: 10001805 stb zero,96(r2) + 8006eb4: 10001845 stb zero,97(r2) + 8006eb8: 10001885 stb zero,98(r2) + 8006ebc: 100018c5 stb zero,99(r2) + 8006ec0: 10800715 stw r2,28(r2) + 8006ec4: 12000815 stw r8,32(r2) + 8006ec8: 11c00915 stw r7,36(r2) + 8006ecc: 11800a15 stw r6,40(r2) + 8006ed0: 11400b15 stw r5,44(r2) + 8006ed4: 00800044 movi r2,1 + 8006ed8: 20800e15 stw r2,56(r4) + 8006edc: f800283a ret + +08006ee0 <__fp_unlock>: + 8006ee0: 0005883a mov r2,zero + 8006ee4: f800283a ret + +08006ee8 <__sfmoreglue>: + 8006ee8: defffc04 addi sp,sp,-16 + 8006eec: dc400115 stw r17,4(sp) + 8006ef0: 2c7fffc4 addi r17,r5,-1 + 8006ef4: 8c401a24 muli r17,r17,104 + 8006ef8: dc800215 stw r18,8(sp) + 8006efc: 2825883a mov r18,r5 + 8006f00: 89401d04 addi r5,r17,116 + 8006f04: dc000015 stw r16,0(sp) + 8006f08: dfc00315 stw ra,12(sp) + 8006f0c: 8007ddc0 call 8007ddc <_malloc_r> + 8006f10: 1021883a mov r16,r2 + 8006f14: 10000726 beq r2,zero,8006f34 <__sfmoreglue+0x4c> + 8006f18: 11000304 addi r4,r2,12 + 8006f1c: 10000015 stw zero,0(r2) + 8006f20: 14800115 stw r18,4(r2) + 8006f24: 11000215 stw r4,8(r2) + 8006f28: 89801a04 addi r6,r17,104 + 8006f2c: 000b883a mov r5,zero + 8006f30: 80088e40 call 80088e4 + 8006f34: 8005883a mov r2,r16 + 8006f38: dfc00317 ldw ra,12(sp) + 8006f3c: dc800217 ldw r18,8(sp) + 8006f40: dc400117 ldw r17,4(sp) + 8006f44: dc000017 ldw r16,0(sp) + 8006f48: dec00404 addi sp,sp,16 + 8006f4c: f800283a ret + +08006f50 <__sfp>: + 8006f50: defffd04 addi sp,sp,-12 + 8006f54: 00820174 movhi r2,2053 + 8006f58: dc000015 stw r16,0(sp) + 8006f5c: 1432ae17 ldw r16,-13640(r2) + 8006f60: dc400115 stw r17,4(sp) + 8006f64: dfc00215 stw ra,8(sp) + 8006f68: 80800e17 ldw r2,56(r16) + 8006f6c: 2023883a mov r17,r4 + 8006f70: 10002b26 beq r2,zero,8007020 <__sfp+0xd0> + 8006f74: 8400b804 addi r16,r16,736 + 8006f78: 80c00117 ldw r3,4(r16) + 8006f7c: 80800217 ldw r2,8(r16) + 8006f80: 18ffffc4 addi r3,r3,-1 + 8006f84: 1800050e bge r3,zero,8006f9c <__sfp+0x4c> + 8006f88: 00002106 br 8007010 <__sfp+0xc0> + 8006f8c: 18ffffc4 addi r3,r3,-1 + 8006f90: 193fffd8 cmpnei r4,r3,-1 + 8006f94: 10801a04 addi r2,r2,104 + 8006f98: 20001d26 beq r4,zero,8007010 <__sfp+0xc0> + 8006f9c: 1100030f ldh r4,12(r2) + 8006fa0: 203ffa1e bne r4,zero,8006f8c <__sfp+0x3c> + 8006fa4: 00fffff4 movhi r3,65535 + 8006fa8: 18c00044 addi r3,r3,1 + 8006fac: 10001915 stw zero,100(r2) + 8006fb0: 10000015 stw zero,0(r2) + 8006fb4: 10000115 stw zero,4(r2) + 8006fb8: 10000215 stw zero,8(r2) + 8006fbc: 10c00315 stw r3,12(r2) + 8006fc0: 10000415 stw zero,16(r2) + 8006fc4: 10000515 stw zero,20(r2) + 8006fc8: 10000615 stw zero,24(r2) + 8006fcc: 10001705 stb zero,92(r2) + 8006fd0: 10001745 stb zero,93(r2) + 8006fd4: 10001785 stb zero,94(r2) + 8006fd8: 100017c5 stb zero,95(r2) + 8006fdc: 10001805 stb zero,96(r2) + 8006fe0: 10001845 stb zero,97(r2) + 8006fe4: 10001885 stb zero,98(r2) + 8006fe8: 100018c5 stb zero,99(r2) + 8006fec: 10000c15 stw zero,48(r2) + 8006ff0: 10000d15 stw zero,52(r2) + 8006ff4: 10001115 stw zero,68(r2) + 8006ff8: 10001215 stw zero,72(r2) + 8006ffc: dfc00217 ldw ra,8(sp) + 8007000: dc400117 ldw r17,4(sp) + 8007004: dc000017 ldw r16,0(sp) + 8007008: dec00304 addi sp,sp,12 + 800700c: f800283a ret + 8007010: 80800017 ldw r2,0(r16) + 8007014: 10000526 beq r2,zero,800702c <__sfp+0xdc> + 8007018: 1021883a mov r16,r2 + 800701c: 003fd606 br 8006f78 <__sfp+0x28> + 8007020: 8009883a mov r4,r16 + 8007024: 8006d780 call 8006d78 <__sinit.part.0> + 8007028: 003fd206 br 8006f74 <__sfp+0x24> + 800702c: 01400104 movi r5,4 + 8007030: 8809883a mov r4,r17 + 8007034: 8006ee80 call 8006ee8 <__sfmoreglue> + 8007038: 80800015 stw r2,0(r16) + 800703c: 103ff61e bne r2,zero,8007018 <__sfp+0xc8> + 8007040: 00c00304 movi r3,12 + 8007044: 88c00015 stw r3,0(r17) + 8007048: 003fec06 br 8006ffc <__sfp+0xac> + +0800704c <_cleanup>: + 800704c: 00820174 movhi r2,2053 + 8007050: 1132ae17 ldw r4,-13640(r2) + 8007054: 01420074 movhi r5,2049 + 8007058: 296eb904 addi r5,r5,-17692 + 800705c: 8007a281 jmpi 8007a28 <_fwalk_reent> + +08007060 <__sinit>: + 8007060: 20800e17 ldw r2,56(r4) + 8007064: 10000126 beq r2,zero,800706c <__sinit+0xc> + 8007068: f800283a ret + 800706c: 8006d781 jmpi 8006d78 <__sinit.part.0> + +08007070 <__sfp_lock_acquire>: + 8007070: f800283a ret + +08007074 <__sfp_lock_release>: + 8007074: f800283a ret + +08007078 <__sinit_lock_acquire>: + 8007078: f800283a ret + +0800707c <__sinit_lock_release>: + 800707c: f800283a ret + +08007080 <__fp_lock_all>: + 8007080: 00820174 movhi r2,2053 + 8007084: 1132af17 ldw r4,-13636(r2) + 8007088: 01420034 movhi r5,2048 + 800708c: 295b5904 addi r5,r5,28004 + 8007090: 80079841 jmpi 8007984 <_fwalk> + +08007094 <__fp_unlock_all>: + 8007094: 00820174 movhi r2,2053 + 8007098: 1132af17 ldw r4,-13636(r2) + 800709c: 01420034 movhi r5,2048 + 80070a0: 295bb804 addi r5,r5,28384 + 80070a4: 80079841 jmpi 8007984 <_fwalk> + +080070a8 <_malloc_trim_r>: + 80070a8: defffb04 addi sp,sp,-20 + 80070ac: dcc00315 stw r19,12(sp) + 80070b0: 04c20174 movhi r19,2053 + 80070b4: dc800215 stw r18,8(sp) + 80070b8: dc400115 stw r17,4(sp) + 80070bc: dc000015 stw r16,0(sp) + 80070c0: dfc00415 stw ra,16(sp) + 80070c4: 2821883a mov r16,r5 + 80070c8: 9cefa904 addi r19,r19,-16732 + 80070cc: 2025883a mov r18,r4 + 80070d0: 800fe0c0 call 800fe0c <__malloc_lock> + 80070d4: 98800217 ldw r2,8(r19) + 80070d8: 14400117 ldw r17,4(r2) + 80070dc: 00bfff04 movi r2,-4 + 80070e0: 88a2703a and r17,r17,r2 + 80070e4: 8c21c83a sub r16,r17,r16 + 80070e8: 8403fbc4 addi r16,r16,4079 + 80070ec: 8020d33a srli r16,r16,12 + 80070f0: 843fffc4 addi r16,r16,-1 + 80070f4: 8020933a slli r16,r16,12 + 80070f8: 80840008 cmpgei r2,r16,4096 + 80070fc: 10000626 beq r2,zero,8007118 <_malloc_trim_r+0x70> + 8007100: 000b883a mov r5,zero + 8007104: 9009883a mov r4,r18 + 8007108: 800a16c0 call 800a16c <_sbrk_r> + 800710c: 98c00217 ldw r3,8(r19) + 8007110: 1c47883a add r3,r3,r17 + 8007114: 10c00a26 beq r2,r3,8007140 <_malloc_trim_r+0x98> + 8007118: 9009883a mov r4,r18 + 800711c: 800ff2c0 call 800ff2c <__malloc_unlock> + 8007120: 0005883a mov r2,zero + 8007124: dfc00417 ldw ra,16(sp) + 8007128: dcc00317 ldw r19,12(sp) + 800712c: dc800217 ldw r18,8(sp) + 8007130: dc400117 ldw r17,4(sp) + 8007134: dc000017 ldw r16,0(sp) + 8007138: dec00504 addi sp,sp,20 + 800713c: f800283a ret + 8007140: 040bc83a sub r5,zero,r16 + 8007144: 9009883a mov r4,r18 + 8007148: 800a16c0 call 800a16c <_sbrk_r> + 800714c: 10bfffd8 cmpnei r2,r2,-1 + 8007150: 10000d26 beq r2,zero,8007188 <_malloc_trim_r+0xe0> + 8007154: 00820174 movhi r2,2053 + 8007158: 10b36417 ldw r2,-12912(r2) + 800715c: 98c00217 ldw r3,8(r19) + 8007160: 8c23c83a sub r17,r17,r16 + 8007164: 8c400054 ori r17,r17,1 + 8007168: 1421c83a sub r16,r2,r16 + 800716c: 1c400115 stw r17,4(r3) + 8007170: 00820174 movhi r2,2053 + 8007174: 9009883a mov r4,r18 + 8007178: 14336415 stw r16,-12912(r2) + 800717c: 800ff2c0 call 800ff2c <__malloc_unlock> + 8007180: 00800044 movi r2,1 + 8007184: 003fe706 br 8007124 <_malloc_trim_r+0x7c> + 8007188: 000b883a mov r5,zero + 800718c: 9009883a mov r4,r18 + 8007190: 800a16c0 call 800a16c <_sbrk_r> + 8007194: 99000217 ldw r4,8(r19) + 8007198: 1107c83a sub r3,r2,r4 + 800719c: 19400410 cmplti r5,r3,16 + 80071a0: 283fdd1e bne r5,zero,8007118 <_malloc_trim_r+0x70> + 80071a4: 01420174 movhi r5,2053 + 80071a8: 2972b017 ldw r5,-13632(r5) + 80071ac: 18c00054 ori r3,r3,1 + 80071b0: 20c00115 stw r3,4(r4) + 80071b4: 1145c83a sub r2,r2,r5 + 80071b8: 01420174 movhi r5,2053 + 80071bc: 28b36415 stw r2,-12912(r5) + 80071c0: 003fd506 br 8007118 <_malloc_trim_r+0x70> + +080071c4 <_free_r>: + 80071c4: 28004f26 beq r5,zero,8007304 <_free_r+0x140> + 80071c8: defffd04 addi sp,sp,-12 + 80071cc: dc400115 stw r17,4(sp) + 80071d0: dc000015 stw r16,0(sp) + 80071d4: 2023883a mov r17,r4 + 80071d8: 2821883a mov r16,r5 + 80071dc: dfc00215 stw ra,8(sp) + 80071e0: 800fe0c0 call 800fe0c <__malloc_lock> + 80071e4: 81ffff17 ldw r7,-4(r16) + 80071e8: 00bfff84 movi r2,-2 + 80071ec: 80fffe04 addi r3,r16,-8 + 80071f0: 3884703a and r2,r7,r2 + 80071f4: 01820174 movhi r6,2053 + 80071f8: 1889883a add r4,r3,r2 + 80071fc: 31afa904 addi r6,r6,-16732 + 8007200: 21400117 ldw r5,4(r4) + 8007204: 32000217 ldw r8,8(r6) + 8007208: 027fff04 movi r9,-4 + 800720c: 2a4a703a and r5,r5,r9 + 8007210: 41006426 beq r8,r4,80073a4 <_free_r+0x1e0> + 8007214: 21400115 stw r5,4(r4) + 8007218: 39c0004c andi r7,r7,1 + 800721c: 2151883a add r8,r4,r5 + 8007220: 3800281e bne r7,zero,80072c4 <_free_r+0x100> + 8007224: 82bffe17 ldw r10,-8(r16) + 8007228: 42000117 ldw r8,4(r8) + 800722c: 01c20174 movhi r7,2053 + 8007230: 1a87c83a sub r3,r3,r10 + 8007234: 1a400217 ldw r9,8(r3) + 8007238: 39efab04 addi r7,r7,-16724 + 800723c: 1285883a add r2,r2,r10 + 8007240: 4200004c andi r8,r8,1 + 8007244: 49c04c26 beq r9,r7,8007378 <_free_r+0x1b4> + 8007248: 1a800317 ldw r10,12(r3) + 800724c: 4a800315 stw r10,12(r9) + 8007250: 52400215 stw r9,8(r10) + 8007254: 40007126 beq r8,zero,800741c <_free_r+0x258> + 8007258: 11400054 ori r5,r2,1 + 800725c: 19400115 stw r5,4(r3) + 8007260: 20800015 stw r2,0(r4) + 8007264: 11008028 cmpgeui r4,r2,512 + 8007268: 20002c1e bne r4,zero,800731c <_free_r+0x158> + 800726c: 1008d0fa srli r4,r2,3 + 8007270: 31c00117 ldw r7,4(r6) + 8007274: 20800044 addi r2,r4,1 + 8007278: 200bd0ba srai r5,r4,2 + 800727c: 100490fa slli r2,r2,3 + 8007280: 01000044 movi r4,1 + 8007284: 2148983a sll r4,r4,r5 + 8007288: 3085883a add r2,r6,r2 + 800728c: 11400017 ldw r5,0(r2) + 8007290: 21c8b03a or r4,r4,r7 + 8007294: 11fffe04 addi r7,r2,-8 + 8007298: 19c00315 stw r7,12(r3) + 800729c: 19400215 stw r5,8(r3) + 80072a0: 31000115 stw r4,4(r6) + 80072a4: 10c00015 stw r3,0(r2) + 80072a8: 28c00315 stw r3,12(r5) + 80072ac: 8809883a mov r4,r17 + 80072b0: dfc00217 ldw ra,8(sp) + 80072b4: dc400117 ldw r17,4(sp) + 80072b8: dc000017 ldw r16,0(sp) + 80072bc: dec00304 addi sp,sp,12 + 80072c0: 800ff2c1 jmpi 800ff2c <__malloc_unlock> + 80072c4: 41c00117 ldw r7,4(r8) + 80072c8: 39c0004c andi r7,r7,1 + 80072cc: 38000e1e bne r7,zero,8007308 <_free_r+0x144> + 80072d0: 01c20174 movhi r7,2053 + 80072d4: 1145883a add r2,r2,r5 + 80072d8: 39efab04 addi r7,r7,-16724 + 80072dc: 21400217 ldw r5,8(r4) + 80072e0: 12400054 ori r9,r2,1 + 80072e4: 1891883a add r8,r3,r2 + 80072e8: 29c05226 beq r5,r7,8007434 <_free_r+0x270> + 80072ec: 21000317 ldw r4,12(r4) + 80072f0: 29000315 stw r4,12(r5) + 80072f4: 21400215 stw r5,8(r4) + 80072f8: 1a400115 stw r9,4(r3) + 80072fc: 40800015 stw r2,0(r8) + 8007300: 003fd806 br 8007264 <_free_r+0xa0> + 8007304: f800283a ret + 8007308: 11400054 ori r5,r2,1 + 800730c: 817fff15 stw r5,-4(r16) + 8007310: 20800015 stw r2,0(r4) + 8007314: 11008028 cmpgeui r4,r2,512 + 8007318: 203fd426 beq r4,zero,800726c <_free_r+0xa8> + 800731c: 1008d27a srli r4,r2,9 + 8007320: 21400168 cmpgeui r5,r4,5 + 8007324: 2800341e bne r5,zero,80073f8 <_free_r+0x234> + 8007328: 1008d1ba srli r4,r2,6 + 800732c: 21c00e44 addi r7,r4,57 + 8007330: 380e90fa slli r7,r7,3 + 8007334: 21400e04 addi r5,r4,56 + 8007338: 31cf883a add r7,r6,r7 + 800733c: 39000017 ldw r4,0(r7) + 8007340: 39fffe04 addi r7,r7,-8 + 8007344: 39004226 beq r7,r4,8007450 <_free_r+0x28c> + 8007348: 01bfff04 movi r6,-4 + 800734c: 21400117 ldw r5,4(r4) + 8007350: 298a703a and r5,r5,r6 + 8007354: 1140022e bgeu r2,r5,8007360 <_free_r+0x19c> + 8007358: 21000217 ldw r4,8(r4) + 800735c: 393ffb1e bne r7,r4,800734c <_free_r+0x188> + 8007360: 21c00317 ldw r7,12(r4) + 8007364: 19c00315 stw r7,12(r3) + 8007368: 19000215 stw r4,8(r3) + 800736c: 38c00215 stw r3,8(r7) + 8007370: 20c00315 stw r3,12(r4) + 8007374: 003fcd06 br 80072ac <_free_r+0xe8> + 8007378: 40004d1e bne r8,zero,80074b0 <_free_r+0x2ec> + 800737c: 21800317 ldw r6,12(r4) + 8007380: 21000217 ldw r4,8(r4) + 8007384: 2885883a add r2,r5,r2 + 8007388: 11400054 ori r5,r2,1 + 800738c: 21800315 stw r6,12(r4) + 8007390: 31000215 stw r4,8(r6) + 8007394: 19400115 stw r5,4(r3) + 8007398: 1887883a add r3,r3,r2 + 800739c: 18800015 stw r2,0(r3) + 80073a0: 003fc206 br 80072ac <_free_r+0xe8> + 80073a4: 39c0004c andi r7,r7,1 + 80073a8: 1145883a add r2,r2,r5 + 80073ac: 3800071e bne r7,zero,80073cc <_free_r+0x208> + 80073b0: 81fffe17 ldw r7,-8(r16) + 80073b4: 19c7c83a sub r3,r3,r7 + 80073b8: 19000317 ldw r4,12(r3) + 80073bc: 19400217 ldw r5,8(r3) + 80073c0: 11c5883a add r2,r2,r7 + 80073c4: 29000315 stw r4,12(r5) + 80073c8: 21400215 stw r5,8(r4) + 80073cc: 01020174 movhi r4,2053 + 80073d0: 11400054 ori r5,r2,1 + 80073d4: 2132b117 ldw r4,-13628(r4) + 80073d8: 19400115 stw r5,4(r3) + 80073dc: 30c00215 stw r3,8(r6) + 80073e0: 113fb236 bltu r2,r4,80072ac <_free_r+0xe8> + 80073e4: 00820174 movhi r2,2053 + 80073e8: 1172ef17 ldw r5,-13380(r2) + 80073ec: 8809883a mov r4,r17 + 80073f0: 80070a80 call 80070a8 <_malloc_trim_r> + 80073f4: 003fad06 br 80072ac <_free_r+0xe8> + 80073f8: 21400568 cmpgeui r5,r4,21 + 80073fc: 28000926 beq r5,zero,8007424 <_free_r+0x260> + 8007400: 21401568 cmpgeui r5,r4,85 + 8007404: 2800191e bne r5,zero,800746c <_free_r+0x2a8> + 8007408: 1008d33a srli r4,r2,12 + 800740c: 21c01bc4 addi r7,r4,111 + 8007410: 21401b84 addi r5,r4,110 + 8007414: 380e90fa slli r7,r7,3 + 8007418: 003fc706 br 8007338 <_free_r+0x174> + 800741c: 1145883a add r2,r2,r5 + 8007420: 003fae06 br 80072dc <_free_r+0x118> + 8007424: 21c01704 addi r7,r4,92 + 8007428: 214016c4 addi r5,r4,91 + 800742c: 380e90fa slli r7,r7,3 + 8007430: 003fc106 br 8007338 <_free_r+0x174> + 8007434: 30c00515 stw r3,20(r6) + 8007438: 30c00415 stw r3,16(r6) + 800743c: 19c00315 stw r7,12(r3) + 8007440: 19c00215 stw r7,8(r3) + 8007444: 1a400115 stw r9,4(r3) + 8007448: 40800015 stw r2,0(r8) + 800744c: 003f9706 br 80072ac <_free_r+0xe8> + 8007450: 280bd0ba srai r5,r5,2 + 8007454: 00800044 movi r2,1 + 8007458: 32000117 ldw r8,4(r6) + 800745c: 114a983a sll r5,r2,r5 + 8007460: 2a0ab03a or r5,r5,r8 + 8007464: 31400115 stw r5,4(r6) + 8007468: 003fbe06 br 8007364 <_free_r+0x1a0> + 800746c: 21405568 cmpgeui r5,r4,341 + 8007470: 2800051e bne r5,zero,8007488 <_free_r+0x2c4> + 8007474: 1008d3fa srli r4,r2,15 + 8007478: 21c01e04 addi r7,r4,120 + 800747c: 21401dc4 addi r5,r4,119 + 8007480: 380e90fa slli r7,r7,3 + 8007484: 003fac06 br 8007338 <_free_r+0x174> + 8007488: 21015568 cmpgeui r4,r4,1365 + 800748c: 2000051e bne r4,zero,80074a4 <_free_r+0x2e0> + 8007490: 1008d4ba srli r4,r2,18 + 8007494: 21c01f44 addi r7,r4,125 + 8007498: 21401f04 addi r5,r4,124 + 800749c: 380e90fa slli r7,r7,3 + 80074a0: 003fa506 br 8007338 <_free_r+0x174> + 80074a4: 01c0fe04 movi r7,1016 + 80074a8: 01401f84 movi r5,126 + 80074ac: 003fa206 br 8007338 <_free_r+0x174> + 80074b0: 11400054 ori r5,r2,1 + 80074b4: 19400115 stw r5,4(r3) + 80074b8: 20800015 stw r2,0(r4) + 80074bc: 003f7b06 br 80072ac <_free_r+0xe8> + +080074c0 <__sfvwrite_r>: + 80074c0: 30800217 ldw r2,8(r6) + 80074c4: 1000c926 beq r2,zero,80077ec <__sfvwrite_r+0x32c> + 80074c8: 2880030b ldhu r2,12(r5) + 80074cc: defff304 addi sp,sp,-52 + 80074d0: dd000715 stw r20,28(sp) + 80074d4: dc000315 stw r16,12(sp) + 80074d8: dfc00c15 stw ra,48(sp) + 80074dc: df000b15 stw fp,44(sp) + 80074e0: ddc00a15 stw r23,40(sp) + 80074e4: dd800915 stw r22,36(sp) + 80074e8: dd400815 stw r21,32(sp) + 80074ec: dcc00615 stw r19,24(sp) + 80074f0: dc800515 stw r18,20(sp) + 80074f4: dc400415 stw r17,16(sp) + 80074f8: d9000015 stw r4,0(sp) + 80074fc: 10c0020c andi r3,r2,8 + 8007500: 2821883a mov r16,r5 + 8007504: 3029883a mov r20,r6 + 8007508: 18002426 beq r3,zero,800759c <__sfvwrite_r+0xdc> + 800750c: 28c00417 ldw r3,16(r5) + 8007510: 18002226 beq r3,zero,800759c <__sfvwrite_r+0xdc> + 8007514: 10c0008c andi r3,r2,2 + 8007518: a4400017 ldw r17,0(r20) + 800751c: 18002726 beq r3,zero,80075bc <__sfvwrite_r+0xfc> + 8007520: 80c00917 ldw r3,36(r16) + 8007524: 80800717 ldw r2,28(r16) + 8007528: 05600034 movhi r21,32768 + 800752c: 0027883a mov r19,zero + 8007530: 0025883a mov r18,zero + 8007534: ad7f0004 addi r21,r21,-1024 + 8007538: 980d883a mov r6,r19 + 800753c: 100b883a mov r5,r2 + 8007540: d9000017 ldw r4,0(sp) + 8007544: 90001126 beq r18,zero,800758c <__sfvwrite_r+0xcc> + 8007548: 900f883a mov r7,r18 + 800754c: ac80012e bgeu r21,r18,8007554 <__sfvwrite_r+0x94> + 8007550: a80f883a mov r7,r21 + 8007554: 183ee83a callr r3 + 8007558: 00809f0e bge zero,r2,80077d8 <__sfvwrite_r+0x318> + 800755c: a0c00217 ldw r3,8(r20) + 8007560: 98a7883a add r19,r19,r2 + 8007564: 90a5c83a sub r18,r18,r2 + 8007568: 1885c83a sub r2,r3,r2 + 800756c: a0800215 stw r2,8(r20) + 8007570: 10006326 beq r2,zero,8007700 <__sfvwrite_r+0x240> + 8007574: 80800717 ldw r2,28(r16) + 8007578: 80c00917 ldw r3,36(r16) + 800757c: 980d883a mov r6,r19 + 8007580: 100b883a mov r5,r2 + 8007584: d9000017 ldw r4,0(sp) + 8007588: 903fef1e bne r18,zero,8007548 <__sfvwrite_r+0x88> + 800758c: 8cc00017 ldw r19,0(r17) + 8007590: 8c800117 ldw r18,4(r17) + 8007594: 8c400204 addi r17,r17,8 + 8007598: 003fe706 br 8007538 <__sfvwrite_r+0x78> + 800759c: d9000017 ldw r4,0(sp) + 80075a0: 800b883a mov r5,r16 + 80075a4: 800507c0 call 800507c <__swsetup_r> + 80075a8: 1000f41e bne r2,zero,800797c <__sfvwrite_r+0x4bc> + 80075ac: 8080030b ldhu r2,12(r16) + 80075b0: a4400017 ldw r17,0(r20) + 80075b4: 10c0008c andi r3,r2,2 + 80075b8: 183fd91e bne r3,zero,8007520 <__sfvwrite_r+0x60> + 80075bc: 10c0004c andi r3,r2,1 + 80075c0: 84800217 ldw r18,8(r16) + 80075c4: 87000017 ldw fp,0(r16) + 80075c8: 18008a1e bne r3,zero,80077f4 <__sfvwrite_r+0x334> + 80075cc: 00e00034 movhi r3,32768 + 80075d0: 18ffff84 addi r3,r3,-2 + 80075d4: 01200034 movhi r4,32768 + 80075d8: d8c00115 stw r3,4(sp) + 80075dc: 20ffffc4 addi r3,r4,-1 + 80075e0: 002d883a mov r22,zero + 80075e4: 002f883a mov r23,zero + 80075e8: d8c00215 stw r3,8(sp) + 80075ec: b8004026 beq r23,zero,80076f0 <__sfvwrite_r+0x230> + 80075f0: 1100800c andi r4,r2,512 + 80075f4: 20009026 beq r4,zero,8007838 <__sfvwrite_r+0x378> + 80075f8: 902b883a mov r21,r18 + 80075fc: bc80b436 bltu r23,r18,80078d0 <__sfvwrite_r+0x410> + 8007600: 1101200c andi r4,r2,1152 + 8007604: 20002526 beq r4,zero,800769c <__sfvwrite_r+0x1dc> + 8007608: 81800517 ldw r6,20(r16) + 800760c: 81400417 ldw r5,16(r16) + 8007610: b9000044 addi r4,r23,1 + 8007614: 318000e4 muli r6,r6,3 + 8007618: e167c83a sub r19,fp,r5 + 800761c: 24c9883a add r4,r4,r19 + 8007620: 3024d7fa srli r18,r6,31 + 8007624: 91a5883a add r18,r18,r6 + 8007628: 9025d07a srai r18,r18,1 + 800762c: 900d883a mov r6,r18 + 8007630: 9100022e bgeu r18,r4,800763c <__sfvwrite_r+0x17c> + 8007634: 2025883a mov r18,r4 + 8007638: 200d883a mov r6,r4 + 800763c: 1081000c andi r2,r2,1024 + 8007640: 1000bc26 beq r2,zero,8007934 <__sfvwrite_r+0x474> + 8007644: d9000017 ldw r4,0(sp) + 8007648: 300b883a mov r5,r6 + 800764c: 8007ddc0 call 8007ddc <_malloc_r> + 8007650: 1000c526 beq r2,zero,8007968 <__sfvwrite_r+0x4a8> + 8007654: 81400417 ldw r5,16(r16) + 8007658: 980d883a mov r6,r19 + 800765c: 1009883a mov r4,r2 + 8007660: 80086b80 call 80086b8 + 8007664: 100f883a mov r7,r2 + 8007668: 8080030b ldhu r2,12(r16) + 800766c: 00fedfc4 movi r3,-1153 + 8007670: 10c4703a and r2,r2,r3 + 8007674: 10802014 ori r2,r2,128 + 8007678: 8080030d sth r2,12(r16) + 800767c: 94c5c83a sub r2,r18,r19 + 8007680: 3cf9883a add fp,r7,r19 + 8007684: 84800515 stw r18,20(r16) + 8007688: 81c00415 stw r7,16(r16) + 800768c: 87000015 stw fp,0(r16) + 8007690: b825883a mov r18,r23 + 8007694: 80800215 stw r2,8(r16) + 8007698: b82b883a mov r21,r23 + 800769c: a80d883a mov r6,r21 + 80076a0: b00b883a mov r5,r22 + 80076a4: e009883a mov r4,fp + 80076a8: 80087b80 call 80087b8 + 80076ac: 80800217 ldw r2,8(r16) + 80076b0: 81800017 ldw r6,0(r16) + 80076b4: b827883a mov r19,r23 + 80076b8: 14a5c83a sub r18,r2,r18 + 80076bc: 354d883a add r6,r6,r21 + 80076c0: 84800215 stw r18,8(r16) + 80076c4: 81800015 stw r6,0(r16) + 80076c8: 002f883a mov r23,zero + 80076cc: a0800217 ldw r2,8(r20) + 80076d0: b4ed883a add r22,r22,r19 + 80076d4: 14e7c83a sub r19,r2,r19 + 80076d8: a4c00215 stw r19,8(r20) + 80076dc: 98000826 beq r19,zero,8007700 <__sfvwrite_r+0x240> + 80076e0: 8080030b ldhu r2,12(r16) + 80076e4: 84800217 ldw r18,8(r16) + 80076e8: 87000017 ldw fp,0(r16) + 80076ec: b83fc01e bne r23,zero,80075f0 <__sfvwrite_r+0x130> + 80076f0: 8d800017 ldw r22,0(r17) + 80076f4: 8dc00117 ldw r23,4(r17) + 80076f8: 8c400204 addi r17,r17,8 + 80076fc: 003fbb06 br 80075ec <__sfvwrite_r+0x12c> + 8007700: 0005883a mov r2,zero + 8007704: dfc00c17 ldw ra,48(sp) + 8007708: df000b17 ldw fp,44(sp) + 800770c: ddc00a17 ldw r23,40(sp) + 8007710: dd800917 ldw r22,36(sp) + 8007714: dd400817 ldw r21,32(sp) + 8007718: dd000717 ldw r20,28(sp) + 800771c: dcc00617 ldw r19,24(sp) + 8007720: dc800517 ldw r18,20(sp) + 8007724: dc400417 ldw r17,16(sp) + 8007728: dc000317 ldw r16,12(sp) + 800772c: dec00d04 addi sp,sp,52 + 8007730: f800283a ret + 8007734: b1c06e16 blt r22,r7,80078f0 <__sfvwrite_r+0x430> + 8007738: 80800917 ldw r2,36(r16) + 800773c: 81400717 ldw r5,28(r16) + 8007740: d9000017 ldw r4,0(sp) + 8007744: b80d883a mov r6,r23 + 8007748: 103ee83a callr r2 + 800774c: 1025883a mov r18,r2 + 8007750: 0080210e bge zero,r2,80077d8 <__sfvwrite_r+0x318> + 8007754: acabc83a sub r21,r21,r18 + 8007758: a8006026 beq r21,zero,80078dc <__sfvwrite_r+0x41c> + 800775c: 00800044 movi r2,1 + 8007760: a0c00217 ldw r3,8(r20) + 8007764: bcaf883a add r23,r23,r18 + 8007768: 9ca7c83a sub r19,r19,r18 + 800776c: 1ca5c83a sub r18,r3,r18 + 8007770: a4800215 stw r18,8(r20) + 8007774: 903fe226 beq r18,zero,8007700 <__sfvwrite_r+0x240> + 8007778: 84800217 ldw r18,8(r16) + 800777c: 87000017 ldw fp,0(r16) + 8007780: 98002126 beq r19,zero,8007808 <__sfvwrite_r+0x348> + 8007784: 10002426 beq r2,zero,8007818 <__sfvwrite_r+0x358> + 8007788: a805883a mov r2,r21 + 800778c: 982d883a mov r22,r19 + 8007790: 14c0012e bgeu r2,r19,8007798 <__sfvwrite_r+0x2d8> + 8007794: 102d883a mov r22,r2 + 8007798: 80800417 ldw r2,16(r16) + 800779c: 81c00517 ldw r7,20(r16) + 80077a0: 173fe42e bgeu r2,fp,8007734 <__sfvwrite_r+0x274> + 80077a4: 3ca5883a add r18,r7,r18 + 80077a8: 95bfe20e bge r18,r22,8007734 <__sfvwrite_r+0x274> + 80077ac: b80b883a mov r5,r23 + 80077b0: e009883a mov r4,fp + 80077b4: 900d883a mov r6,r18 + 80077b8: 80087b80 call 80087b8 + 80077bc: 80800017 ldw r2,0(r16) + 80077c0: d9000017 ldw r4,0(sp) + 80077c4: 800b883a mov r5,r16 + 80077c8: 1485883a add r2,r2,r18 + 80077cc: 80800015 stw r2,0(r16) + 80077d0: 8006cdc0 call 8006cdc <_fflush_r> + 80077d4: 103fdf26 beq r2,zero,8007754 <__sfvwrite_r+0x294> + 80077d8: 8080030b ldhu r2,12(r16) + 80077dc: 10801014 ori r2,r2,64 + 80077e0: 8080030d sth r2,12(r16) + 80077e4: 00bfffc4 movi r2,-1 + 80077e8: 003fc606 br 8007704 <__sfvwrite_r+0x244> + 80077ec: 0005883a mov r2,zero + 80077f0: f800283a ret + 80077f4: 0027883a mov r19,zero + 80077f8: 002b883a mov r21,zero + 80077fc: 0005883a mov r2,zero + 8007800: 002f883a mov r23,zero + 8007804: 983fdf1e bne r19,zero,8007784 <__sfvwrite_r+0x2c4> + 8007808: 8cc00117 ldw r19,4(r17) + 800780c: 8dc00017 ldw r23,0(r17) + 8007810: 8c400204 addi r17,r17,8 + 8007814: 983ffc26 beq r19,zero,8007808 <__sfvwrite_r+0x348> + 8007818: 980d883a mov r6,r19 + 800781c: 01400284 movi r5,10 + 8007820: b809883a mov r4,r23 + 8007824: 80085d00 call 80085d0 + 8007828: 10003f26 beq r2,zero,8007928 <__sfvwrite_r+0x468> + 800782c: 10800044 addi r2,r2,1 + 8007830: 15ebc83a sub r21,r2,r23 + 8007834: 003fd406 br 8007788 <__sfvwrite_r+0x2c8> + 8007838: 80800417 ldw r2,16(r16) + 800783c: 17001136 bltu r2,fp,8007884 <__sfvwrite_r+0x3c4> + 8007840: 84c00517 ldw r19,20(r16) + 8007844: bcc00f36 bltu r23,r19,8007884 <__sfvwrite_r+0x3c4> + 8007848: d8800117 ldw r2,4(sp) + 800784c: 15c0342e bgeu r2,r23,8007920 <__sfvwrite_r+0x460> + 8007850: d9000217 ldw r4,8(sp) + 8007854: 980b883a mov r5,r19 + 8007858: 800cf000 call 800cf00 <__divsi3> + 800785c: 14cf383a mul r7,r2,r19 + 8007860: 81400717 ldw r5,28(r16) + 8007864: 80800917 ldw r2,36(r16) + 8007868: d9000017 ldw r4,0(sp) + 800786c: b00d883a mov r6,r22 + 8007870: 103ee83a callr r2 + 8007874: 00bfd80e bge zero,r2,80077d8 <__sfvwrite_r+0x318> + 8007878: 1027883a mov r19,r2 + 800787c: bcefc83a sub r23,r23,r19 + 8007880: 003f9206 br 80076cc <__sfvwrite_r+0x20c> + 8007884: 9027883a mov r19,r18 + 8007888: bc80012e bgeu r23,r18,8007890 <__sfvwrite_r+0x3d0> + 800788c: b827883a mov r19,r23 + 8007890: e009883a mov r4,fp + 8007894: 980d883a mov r6,r19 + 8007898: b00b883a mov r5,r22 + 800789c: 80087b80 call 80087b8 + 80078a0: 80800217 ldw r2,8(r16) + 80078a4: 81000017 ldw r4,0(r16) + 80078a8: 14c5c83a sub r2,r2,r19 + 80078ac: 24c9883a add r4,r4,r19 + 80078b0: 80800215 stw r2,8(r16) + 80078b4: 81000015 stw r4,0(r16) + 80078b8: 103ff01e bne r2,zero,800787c <__sfvwrite_r+0x3bc> + 80078bc: d9000017 ldw r4,0(sp) + 80078c0: 800b883a mov r5,r16 + 80078c4: 8006cdc0 call 8006cdc <_fflush_r> + 80078c8: 103fec26 beq r2,zero,800787c <__sfvwrite_r+0x3bc> + 80078cc: 003fc206 br 80077d8 <__sfvwrite_r+0x318> + 80078d0: b825883a mov r18,r23 + 80078d4: b82b883a mov r21,r23 + 80078d8: 003f7006 br 800769c <__sfvwrite_r+0x1dc> + 80078dc: d9000017 ldw r4,0(sp) + 80078e0: 800b883a mov r5,r16 + 80078e4: 8006cdc0 call 8006cdc <_fflush_r> + 80078e8: 103f9d26 beq r2,zero,8007760 <__sfvwrite_r+0x2a0> + 80078ec: 003fba06 br 80077d8 <__sfvwrite_r+0x318> + 80078f0: b00d883a mov r6,r22 + 80078f4: b80b883a mov r5,r23 + 80078f8: e009883a mov r4,fp + 80078fc: 80087b80 call 80087b8 + 8007900: 80c00217 ldw r3,8(r16) + 8007904: 80800017 ldw r2,0(r16) + 8007908: b025883a mov r18,r22 + 800790c: 1d87c83a sub r3,r3,r22 + 8007910: 15ad883a add r22,r2,r22 + 8007914: 80c00215 stw r3,8(r16) + 8007918: 85800015 stw r22,0(r16) + 800791c: 003f8d06 br 8007754 <__sfvwrite_r+0x294> + 8007920: b809883a mov r4,r23 + 8007924: 003fcb06 br 8007854 <__sfvwrite_r+0x394> + 8007928: 98800044 addi r2,r19,1 + 800792c: 102b883a mov r21,r2 + 8007930: 003f9606 br 800778c <__sfvwrite_r+0x2cc> + 8007934: d9000017 ldw r4,0(sp) + 8007938: 8009abc0 call 8009abc <_realloc_r> + 800793c: 100f883a mov r7,r2 + 8007940: 103f4e1e bne r2,zero,800767c <__sfvwrite_r+0x1bc> + 8007944: dc400017 ldw r17,0(sp) + 8007948: 81400417 ldw r5,16(r16) + 800794c: 8809883a mov r4,r17 + 8007950: 80071c40 call 80071c4 <_free_r> + 8007954: 8080030b ldhu r2,12(r16) + 8007958: 00c00304 movi r3,12 + 800795c: 88c00015 stw r3,0(r17) + 8007960: 10bfdfcc andi r2,r2,65407 + 8007964: 003f9d06 br 80077dc <__sfvwrite_r+0x31c> + 8007968: d8c00017 ldw r3,0(sp) + 800796c: 00800304 movi r2,12 + 8007970: 18800015 stw r2,0(r3) + 8007974: 8080030b ldhu r2,12(r16) + 8007978: 003f9806 br 80077dc <__sfvwrite_r+0x31c> + 800797c: 00bfffc4 movi r2,-1 + 8007980: 003f6006 br 8007704 <__sfvwrite_r+0x244> + +08007984 <_fwalk>: + 8007984: defffa04 addi sp,sp,-24 + 8007988: dc800215 stw r18,8(sp) + 800798c: dfc00515 stw ra,20(sp) + 8007990: dd000415 stw r20,16(sp) + 8007994: dcc00315 stw r19,12(sp) + 8007998: dc400115 stw r17,4(sp) + 800799c: dc000015 stw r16,0(sp) + 80079a0: 2480b804 addi r18,r4,736 + 80079a4: 90001e26 beq r18,zero,8007a20 <_fwalk+0x9c> + 80079a8: 2827883a mov r19,r5 + 80079ac: 0029883a mov r20,zero + 80079b0: 94400117 ldw r17,4(r18) + 80079b4: 94000217 ldw r16,8(r18) + 80079b8: 8c7fffc4 addi r17,r17,-1 + 80079bc: 88000d16 blt r17,zero,80079f4 <_fwalk+0x70> + 80079c0: 8080030b ldhu r2,12(r16) + 80079c4: 8c7fffc4 addi r17,r17,-1 + 80079c8: 108000b0 cmpltui r2,r2,2 + 80079cc: 1000061e bne r2,zero,80079e8 <_fwalk+0x64> + 80079d0: 8080038f ldh r2,14(r16) + 80079d4: 8009883a mov r4,r16 + 80079d8: 10bfffe0 cmpeqi r2,r2,-1 + 80079dc: 1000021e bne r2,zero,80079e8 <_fwalk+0x64> + 80079e0: 983ee83a callr r19 + 80079e4: a0a8b03a or r20,r20,r2 + 80079e8: 88bfffd8 cmpnei r2,r17,-1 + 80079ec: 84001a04 addi r16,r16,104 + 80079f0: 103ff31e bne r2,zero,80079c0 <_fwalk+0x3c> + 80079f4: 94800017 ldw r18,0(r18) + 80079f8: 903fed1e bne r18,zero,80079b0 <_fwalk+0x2c> + 80079fc: a005883a mov r2,r20 + 8007a00: dfc00517 ldw ra,20(sp) + 8007a04: dd000417 ldw r20,16(sp) + 8007a08: dcc00317 ldw r19,12(sp) + 8007a0c: dc800217 ldw r18,8(sp) + 8007a10: dc400117 ldw r17,4(sp) + 8007a14: dc000017 ldw r16,0(sp) + 8007a18: dec00604 addi sp,sp,24 + 8007a1c: f800283a ret + 8007a20: 0029883a mov r20,zero + 8007a24: 003ff506 br 80079fc <_fwalk+0x78> + +08007a28 <_fwalk_reent>: + 8007a28: defff904 addi sp,sp,-28 + 8007a2c: dc800215 stw r18,8(sp) + 8007a30: dfc00615 stw ra,24(sp) + 8007a34: dd400515 stw r21,20(sp) + 8007a38: dd000415 stw r20,16(sp) + 8007a3c: dcc00315 stw r19,12(sp) + 8007a40: dc400115 stw r17,4(sp) + 8007a44: dc000015 stw r16,0(sp) + 8007a48: 2480b804 addi r18,r4,736 + 8007a4c: 90002126 beq r18,zero,8007ad4 <_fwalk_reent+0xac> + 8007a50: 2829883a mov r20,r5 + 8007a54: 2027883a mov r19,r4 + 8007a58: 002b883a mov r21,zero + 8007a5c: 94400117 ldw r17,4(r18) + 8007a60: 94000217 ldw r16,8(r18) + 8007a64: 8c7fffc4 addi r17,r17,-1 + 8007a68: 88000e16 blt r17,zero,8007aa4 <_fwalk_reent+0x7c> + 8007a6c: 8080030b ldhu r2,12(r16) + 8007a70: 8c7fffc4 addi r17,r17,-1 + 8007a74: 108000b0 cmpltui r2,r2,2 + 8007a78: 1000071e bne r2,zero,8007a98 <_fwalk_reent+0x70> + 8007a7c: 8080038f ldh r2,14(r16) + 8007a80: 800b883a mov r5,r16 + 8007a84: 9809883a mov r4,r19 + 8007a88: 10bfffe0 cmpeqi r2,r2,-1 + 8007a8c: 1000021e bne r2,zero,8007a98 <_fwalk_reent+0x70> + 8007a90: a03ee83a callr r20 + 8007a94: a8aab03a or r21,r21,r2 + 8007a98: 88bfffd8 cmpnei r2,r17,-1 + 8007a9c: 84001a04 addi r16,r16,104 + 8007aa0: 103ff21e bne r2,zero,8007a6c <_fwalk_reent+0x44> + 8007aa4: 94800017 ldw r18,0(r18) + 8007aa8: 903fec1e bne r18,zero,8007a5c <_fwalk_reent+0x34> + 8007aac: a805883a mov r2,r21 + 8007ab0: dfc00617 ldw ra,24(sp) + 8007ab4: dd400517 ldw r21,20(sp) + 8007ab8: dd000417 ldw r20,16(sp) + 8007abc: dcc00317 ldw r19,12(sp) + 8007ac0: dc800217 ldw r18,8(sp) + 8007ac4: dc400117 ldw r17,4(sp) + 8007ac8: dc000017 ldw r16,0(sp) + 8007acc: dec00704 addi sp,sp,28 + 8007ad0: f800283a ret + 8007ad4: 002b883a mov r21,zero + 8007ad8: 003ff406 br 8007aac <_fwalk_reent+0x84> + +08007adc <_getc_r>: + 8007adc: defffd04 addi sp,sp,-12 + 8007ae0: dc000115 stw r16,4(sp) + 8007ae4: dfc00215 stw ra,8(sp) + 8007ae8: 2021883a mov r16,r4 + 8007aec: 20000226 beq r4,zero,8007af8 <_getc_r+0x1c> + 8007af0: 20800e17 ldw r2,56(r4) + 8007af4: 10000c26 beq r2,zero,8007b28 <_getc_r+0x4c> + 8007af8: 28800117 ldw r2,4(r5) + 8007afc: 10bfffc4 addi r2,r2,-1 + 8007b00: 28800115 stw r2,4(r5) + 8007b04: 10000f16 blt r2,zero,8007b44 <_getc_r+0x68> + 8007b08: 28800017 ldw r2,0(r5) + 8007b0c: 10c00044 addi r3,r2,1 + 8007b10: 28c00015 stw r3,0(r5) + 8007b14: 10800003 ldbu r2,0(r2) + 8007b18: dfc00217 ldw ra,8(sp) + 8007b1c: dc000117 ldw r16,4(sp) + 8007b20: dec00304 addi sp,sp,12 + 8007b24: f800283a ret + 8007b28: d9400015 stw r5,0(sp) + 8007b2c: 80070600 call 8007060 <__sinit> + 8007b30: d9400017 ldw r5,0(sp) + 8007b34: 28800117 ldw r2,4(r5) + 8007b38: 10bfffc4 addi r2,r2,-1 + 8007b3c: 28800115 stw r2,4(r5) + 8007b40: 103ff10e bge r2,zero,8007b08 <_getc_r+0x2c> + 8007b44: 8009883a mov r4,r16 + 8007b48: dfc00217 ldw ra,8(sp) + 8007b4c: dc000117 ldw r16,4(sp) + 8007b50: dec00304 addi sp,sp,12 + 8007b54: 800a0e81 jmpi 800a0e8 <__srget_r> + +08007b58 : + 8007b58: defffd04 addi sp,sp,-12 + 8007b5c: 00820174 movhi r2,2053 + 8007b60: dc400115 stw r17,4(sp) + 8007b64: 1472af17 ldw r17,-13636(r2) + 8007b68: dc000015 stw r16,0(sp) + 8007b6c: dfc00215 stw ra,8(sp) + 8007b70: 2021883a mov r16,r4 + 8007b74: 88000226 beq r17,zero,8007b80 + 8007b78: 88800e17 ldw r2,56(r17) + 8007b7c: 10000d26 beq r2,zero,8007bb4 + 8007b80: 80800117 ldw r2,4(r16) + 8007b84: 10bfffc4 addi r2,r2,-1 + 8007b88: 80800115 stw r2,4(r16) + 8007b8c: 10000f16 blt r2,zero,8007bcc + 8007b90: 80800017 ldw r2,0(r16) + 8007b94: 10c00044 addi r3,r2,1 + 8007b98: 80c00015 stw r3,0(r16) + 8007b9c: 10800003 ldbu r2,0(r2) + 8007ba0: dfc00217 ldw ra,8(sp) + 8007ba4: dc400117 ldw r17,4(sp) + 8007ba8: dc000017 ldw r16,0(sp) + 8007bac: dec00304 addi sp,sp,12 + 8007bb0: f800283a ret + 8007bb4: 8809883a mov r4,r17 + 8007bb8: 80070600 call 8007060 <__sinit> + 8007bbc: 80800117 ldw r2,4(r16) + 8007bc0: 10bfffc4 addi r2,r2,-1 + 8007bc4: 80800115 stw r2,4(r16) + 8007bc8: 103ff10e bge r2,zero,8007b90 + 8007bcc: 800b883a mov r5,r16 + 8007bd0: 8809883a mov r4,r17 + 8007bd4: dfc00217 ldw ra,8(sp) + 8007bd8: dc400117 ldw r17,4(sp) + 8007bdc: dc000017 ldw r16,0(sp) + 8007be0: dec00304 addi sp,sp,12 + 8007be4: 800a0e81 jmpi 800a0e8 <__srget_r> + +08007be8 <__localeconv_l>: + 8007be8: 20803c04 addi r2,r4,240 + 8007bec: f800283a ret + +08007bf0 <_localeconv_r>: + 8007bf0: 00820174 movhi r2,2053 + 8007bf4: 10b0e704 addi r2,r2,-15460 + 8007bf8: f800283a ret + +08007bfc : + 8007bfc: 00820174 movhi r2,2053 + 8007c00: 10b0e704 addi r2,r2,-15460 + 8007c04: f800283a ret + +08007c08 <__swhatbuf_r>: + 8007c08: deffea04 addi sp,sp,-88 + 8007c0c: dc001215 stw r16,72(sp) + 8007c10: 2821883a mov r16,r5 + 8007c14: 2940038f ldh r5,14(r5) + 8007c18: dc801415 stw r18,80(sp) + 8007c1c: dc401315 stw r17,76(sp) + 8007c20: dfc01515 stw ra,84(sp) + 8007c24: 3023883a mov r17,r6 + 8007c28: 3825883a mov r18,r7 + 8007c2c: 28001016 blt r5,zero,8007c70 <__swhatbuf_r+0x68> + 8007c30: d80d883a mov r6,sp + 8007c34: 800bddc0 call 800bddc <_fstat_r> + 8007c38: 10000d16 blt r2,zero,8007c70 <__swhatbuf_r+0x68> + 8007c3c: d8c00117 ldw r3,4(sp) + 8007c40: 00820004 movi r2,2048 + 8007c44: 18fc000c andi r3,r3,61440 + 8007c48: 18c80020 cmpeqi r3,r3,8192 + 8007c4c: 90c00015 stw r3,0(r18) + 8007c50: 00c10004 movi r3,1024 + 8007c54: 88c00015 stw r3,0(r17) + 8007c58: dfc01517 ldw ra,84(sp) + 8007c5c: dc801417 ldw r18,80(sp) + 8007c60: dc401317 ldw r17,76(sp) + 8007c64: dc001217 ldw r16,72(sp) + 8007c68: dec01604 addi sp,sp,88 + 8007c6c: f800283a ret + 8007c70: 8080030b ldhu r2,12(r16) + 8007c74: 90000015 stw zero,0(r18) + 8007c78: 1080200c andi r2,r2,128 + 8007c7c: 10000426 beq r2,zero,8007c90 <__swhatbuf_r+0x88> + 8007c80: 00801004 movi r2,64 + 8007c84: 88800015 stw r2,0(r17) + 8007c88: 0005883a mov r2,zero + 8007c8c: 003ff206 br 8007c58 <__swhatbuf_r+0x50> + 8007c90: 00810004 movi r2,1024 + 8007c94: 88800015 stw r2,0(r17) + 8007c98: 0005883a mov r2,zero + 8007c9c: 003fee06 br 8007c58 <__swhatbuf_r+0x50> + +08007ca0 <__smakebuf_r>: + 8007ca0: 28c0030b ldhu r3,12(r5) + 8007ca4: defffa04 addi sp,sp,-24 + 8007ca8: dc000215 stw r16,8(sp) + 8007cac: dfc00515 stw ra,20(sp) + 8007cb0: dc800415 stw r18,16(sp) + 8007cb4: dc400315 stw r17,12(sp) + 8007cb8: 18c0008c andi r3,r3,2 + 8007cbc: 2821883a mov r16,r5 + 8007cc0: 18000b26 beq r3,zero,8007cf0 <__smakebuf_r+0x50> + 8007cc4: 28c010c4 addi r3,r5,67 + 8007cc8: 28c00015 stw r3,0(r5) + 8007ccc: 28c00415 stw r3,16(r5) + 8007cd0: 00c00044 movi r3,1 + 8007cd4: 28c00515 stw r3,20(r5) + 8007cd8: dfc00517 ldw ra,20(sp) + 8007cdc: dc800417 ldw r18,16(sp) + 8007ce0: dc400317 ldw r17,12(sp) + 8007ce4: dc000217 ldw r16,8(sp) + 8007ce8: dec00604 addi sp,sp,24 + 8007cec: f800283a ret + 8007cf0: d9c00104 addi r7,sp,4 + 8007cf4: d80d883a mov r6,sp + 8007cf8: 2023883a mov r17,r4 + 8007cfc: 8007c080 call 8007c08 <__swhatbuf_r> + 8007d00: 1025883a mov r18,r2 + 8007d04: d8800117 ldw r2,4(sp) + 8007d08: 1000131e bne r2,zero,8007d58 <__smakebuf_r+0xb8> + 8007d0c: d9400017 ldw r5,0(sp) + 8007d10: 8809883a mov r4,r17 + 8007d14: 8007ddc0 call 8007ddc <_malloc_r> + 8007d18: 10001c26 beq r2,zero,8007d8c <__smakebuf_r+0xec> + 8007d1c: 01020034 movhi r4,2048 + 8007d20: 211b5b04 addi r4,r4,28012 + 8007d24: 80c0030b ldhu r3,12(r16) + 8007d28: 89000f15 stw r4,60(r17) + 8007d2c: 80800015 stw r2,0(r16) + 8007d30: 80800415 stw r2,16(r16) + 8007d34: d8800017 ldw r2,0(sp) + 8007d38: d9400117 ldw r5,4(sp) + 8007d3c: 18c02014 ori r3,r3,128 + 8007d40: 80c0030d sth r3,12(r16) + 8007d44: 80800515 stw r2,20(r16) + 8007d48: 28001c1e bne r5,zero,8007dbc <__smakebuf_r+0x11c> + 8007d4c: 90c6b03a or r3,r18,r3 + 8007d50: 80c0030d sth r3,12(r16) + 8007d54: 003fe006 br 8007cd8 <__smakebuf_r+0x38> + 8007d58: 8140038f ldh r5,14(r16) + 8007d5c: 8809883a mov r4,r17 + 8007d60: 800be3c0 call 800be3c <_isatty_r> + 8007d64: 103fe926 beq r2,zero,8007d0c <__smakebuf_r+0x6c> + 8007d68: 8080030b ldhu r2,12(r16) + 8007d6c: 80c010c4 addi r3,r16,67 + 8007d70: 80c00015 stw r3,0(r16) + 8007d74: 10800054 ori r2,r2,1 + 8007d78: 8080030d sth r2,12(r16) + 8007d7c: 00800044 movi r2,1 + 8007d80: 80c00415 stw r3,16(r16) + 8007d84: 80800515 stw r2,20(r16) + 8007d88: 003fe006 br 8007d0c <__smakebuf_r+0x6c> + 8007d8c: 8080030b ldhu r2,12(r16) + 8007d90: 10c0800c andi r3,r2,512 + 8007d94: 183fd01e bne r3,zero,8007cd8 <__smakebuf_r+0x38> + 8007d98: 10bfff0c andi r2,r2,65532 + 8007d9c: 10800094 ori r2,r2,2 + 8007da0: 80c010c4 addi r3,r16,67 + 8007da4: 8080030d sth r2,12(r16) + 8007da8: 00800044 movi r2,1 + 8007dac: 80c00015 stw r3,0(r16) + 8007db0: 80c00415 stw r3,16(r16) + 8007db4: 80800515 stw r2,20(r16) + 8007db8: 003fc706 br 8007cd8 <__smakebuf_r+0x38> + 8007dbc: 8140038f ldh r5,14(r16) + 8007dc0: 8809883a mov r4,r17 + 8007dc4: 800be3c0 call 800be3c <_isatty_r> + 8007dc8: 80c0030b ldhu r3,12(r16) + 8007dcc: 103fdf26 beq r2,zero,8007d4c <__smakebuf_r+0xac> + 8007dd0: 18ffff0c andi r3,r3,65532 + 8007dd4: 18c00054 ori r3,r3,1 + 8007dd8: 003fdc06 br 8007d4c <__smakebuf_r+0xac> + +08007ddc <_malloc_r>: + 8007ddc: defff604 addi sp,sp,-40 + 8007de0: dc400115 stw r17,4(sp) + 8007de4: 2c4002c4 addi r17,r5,11 + 8007de8: dc800215 stw r18,8(sp) + 8007dec: dfc00915 stw ra,36(sp) + 8007df0: df000815 stw fp,32(sp) + 8007df4: ddc00715 stw r23,28(sp) + 8007df8: dd800615 stw r22,24(sp) + 8007dfc: dd400515 stw r21,20(sp) + 8007e00: dd000415 stw r20,16(sp) + 8007e04: dcc00315 stw r19,12(sp) + 8007e08: dc000015 stw r16,0(sp) + 8007e0c: 888005e8 cmpgeui r2,r17,23 + 8007e10: 2025883a mov r18,r4 + 8007e14: 10001b1e bne r2,zero,8007e84 <_malloc_r+0xa8> + 8007e18: 29400468 cmpgeui r5,r5,17 + 8007e1c: 2800951e bne r5,zero,8008074 <_malloc_r+0x298> + 8007e20: 800fe0c0 call 800fe0c <__malloc_lock> + 8007e24: 04400404 movi r17,16 + 8007e28: 00800604 movi r2,24 + 8007e2c: 01800084 movi r6,2 + 8007e30: 04c20174 movhi r19,2053 + 8007e34: 9cefa904 addi r19,r19,-16732 + 8007e38: 9885883a add r2,r19,r2 + 8007e3c: 14000117 ldw r16,4(r2) + 8007e40: 10fffe04 addi r3,r2,-8 + 8007e44: 80c09e26 beq r16,r3,80080c0 <_malloc_r+0x2e4> + 8007e48: 80800117 ldw r2,4(r16) + 8007e4c: 81000317 ldw r4,12(r16) + 8007e50: 00ffff04 movi r3,-4 + 8007e54: 10c4703a and r2,r2,r3 + 8007e58: 81400217 ldw r5,8(r16) + 8007e5c: 8085883a add r2,r16,r2 + 8007e60: 10c00117 ldw r3,4(r2) + 8007e64: 29000315 stw r4,12(r5) + 8007e68: 21400215 stw r5,8(r4) + 8007e6c: 18c00054 ori r3,r3,1 + 8007e70: 10c00115 stw r3,4(r2) + 8007e74: 9009883a mov r4,r18 + 8007e78: 800ff2c0 call 800ff2c <__malloc_unlock> + 8007e7c: 80800204 addi r2,r16,8 + 8007e80: 00007f06 br 8008080 <_malloc_r+0x2a4> + 8007e84: 00bffe04 movi r2,-8 + 8007e88: 88a2703a and r17,r17,r2 + 8007e8c: 88007916 blt r17,zero,8008074 <_malloc_r+0x298> + 8007e90: 89407836 bltu r17,r5,8008074 <_malloc_r+0x298> + 8007e94: 800fe0c0 call 800fe0c <__malloc_lock> + 8007e98: 88807e28 cmpgeui r2,r17,504 + 8007e9c: 10013326 beq r2,zero,800836c <_malloc_r+0x590> + 8007ea0: 8804d27a srli r2,r17,9 + 8007ea4: 10008226 beq r2,zero,80080b0 <_malloc_r+0x2d4> + 8007ea8: 10c00168 cmpgeui r3,r2,5 + 8007eac: 1801151e bne r3,zero,8008304 <_malloc_r+0x528> + 8007eb0: 8804d1ba srli r2,r17,6 + 8007eb4: 11800e44 addi r6,r2,57 + 8007eb8: 300a90fa slli r5,r6,3 + 8007ebc: 12000e04 addi r8,r2,56 + 8007ec0: 04c20174 movhi r19,2053 + 8007ec4: 9cefa904 addi r19,r19,-16732 + 8007ec8: 994b883a add r5,r19,r5 + 8007ecc: 2c000117 ldw r16,4(r5) + 8007ed0: 297ffe04 addi r5,r5,-8 + 8007ed4: 2c001126 beq r5,r16,8007f1c <_malloc_r+0x140> + 8007ed8: 80800117 ldw r2,4(r16) + 8007edc: 00ffff04 movi r3,-4 + 8007ee0: 10c4703a and r2,r2,r3 + 8007ee4: 1447c83a sub r3,r2,r17 + 8007ee8: 19000408 cmpgei r4,r3,16 + 8007eec: 2000e81e bne r4,zero,8008290 <_malloc_r+0x4b4> + 8007ef0: 1800e90e bge r3,zero,8008298 <_malloc_r+0x4bc> + 8007ef4: 01ffff04 movi r7,-4 + 8007ef8: 00000606 br 8007f14 <_malloc_r+0x138> + 8007efc: 80800117 ldw r2,4(r16) + 8007f00: 11c4703a and r2,r2,r7 + 8007f04: 1447c83a sub r3,r2,r17 + 8007f08: 19000408 cmpgei r4,r3,16 + 8007f0c: 2000e01e bne r4,zero,8008290 <_malloc_r+0x4b4> + 8007f10: 1800e10e bge r3,zero,8008298 <_malloc_r+0x4bc> + 8007f14: 84000317 ldw r16,12(r16) + 8007f18: 2c3ff81e bne r5,r16,8007efc <_malloc_r+0x120> + 8007f1c: 9c000417 ldw r16,16(r19) + 8007f20: 02020174 movhi r8,2053 + 8007f24: 422fab04 addi r8,r8,-16724 + 8007f28: 82006c26 beq r16,r8,80080dc <_malloc_r+0x300> + 8007f2c: 80c00117 ldw r3,4(r16) + 8007f30: 00bfff04 movi r2,-4 + 8007f34: 1884703a and r2,r3,r2 + 8007f38: 1447c83a sub r3,r2,r17 + 8007f3c: 19000410 cmplti r4,r3,16 + 8007f40: 20011526 beq r4,zero,8008398 <_malloc_r+0x5bc> + 8007f44: 9a000515 stw r8,20(r19) + 8007f48: 9a000415 stw r8,16(r19) + 8007f4c: 18010a0e bge r3,zero,8008378 <_malloc_r+0x59c> + 8007f50: 10c08028 cmpgeui r3,r2,512 + 8007f54: 1800d21e bne r3,zero,80082a0 <_malloc_r+0x4c4> + 8007f58: 1004d0fa srli r2,r2,3 + 8007f5c: 99400117 ldw r5,4(r19) + 8007f60: 10c00044 addi r3,r2,1 + 8007f64: 1009d0ba srai r4,r2,2 + 8007f68: 180690fa slli r3,r3,3 + 8007f6c: 00800044 movi r2,1 + 8007f70: 1104983a sll r2,r2,r4 + 8007f74: 98c7883a add r3,r19,r3 + 8007f78: 19000017 ldw r4,0(r3) + 8007f7c: 1144b03a or r2,r2,r5 + 8007f80: 197ffe04 addi r5,r3,-8 + 8007f84: 81400315 stw r5,12(r16) + 8007f88: 81000215 stw r4,8(r16) + 8007f8c: 98800115 stw r2,4(r19) + 8007f90: 1c000015 stw r16,0(r3) + 8007f94: 24000315 stw r16,12(r4) + 8007f98: 3007d0ba srai r3,r6,2 + 8007f9c: 01000044 movi r4,1 + 8007fa0: 20c8983a sll r4,r4,r3 + 8007fa4: 11005236 bltu r2,r4,80080f0 <_malloc_r+0x314> + 8007fa8: 2086703a and r3,r4,r2 + 8007fac: 18000a1e bne r3,zero,8007fd8 <_malloc_r+0x1fc> + 8007fb0: 00ffff04 movi r3,-4 + 8007fb4: 2109883a add r4,r4,r4 + 8007fb8: 30cc703a and r6,r6,r3 + 8007fbc: 2086703a and r3,r4,r2 + 8007fc0: 31800104 addi r6,r6,4 + 8007fc4: 1800041e bne r3,zero,8007fd8 <_malloc_r+0x1fc> + 8007fc8: 2109883a add r4,r4,r4 + 8007fcc: 2086703a and r3,r4,r2 + 8007fd0: 31800104 addi r6,r6,4 + 8007fd4: 183ffc26 beq r3,zero,8007fc8 <_malloc_r+0x1ec> + 8007fd8: 027fff04 movi r9,-4 + 8007fdc: 301490fa slli r10,r6,3 + 8007fe0: 3017883a mov r11,r6 + 8007fe4: 9a95883a add r10,r19,r10 + 8007fe8: 500f883a mov r7,r10 + 8007fec: 3c000317 ldw r16,12(r7) + 8007ff0: 3c00cd26 beq r7,r16,8008328 <_malloc_r+0x54c> + 8007ff4: 80800117 ldw r2,4(r16) + 8007ff8: 1244703a and r2,r2,r9 + 8007ffc: 1447c83a sub r3,r2,r17 + 8008000: 19400408 cmpgei r5,r3,16 + 8008004: 2800081e bne r5,zero,8008028 <_malloc_r+0x24c> + 8008008: 1800cc0e bge r3,zero,800833c <_malloc_r+0x560> + 800800c: 84000317 ldw r16,12(r16) + 8008010: 3c00c526 beq r7,r16,8008328 <_malloc_r+0x54c> + 8008014: 80800117 ldw r2,4(r16) + 8008018: 1244703a and r2,r2,r9 + 800801c: 1447c83a sub r3,r2,r17 + 8008020: 19400410 cmplti r5,r3,16 + 8008024: 283ff81e bne r5,zero,8008008 <_malloc_r+0x22c> + 8008028: 81000317 ldw r4,12(r16) + 800802c: 81400217 ldw r5,8(r16) + 8008030: 89800054 ori r6,r17,1 + 8008034: 81800115 stw r6,4(r16) + 8008038: 29000315 stw r4,12(r5) + 800803c: 21400215 stw r5,8(r4) + 8008040: 8463883a add r17,r16,r17 + 8008044: 9c400515 stw r17,20(r19) + 8008048: 9c400415 stw r17,16(r19) + 800804c: 19000054 ori r4,r3,1 + 8008050: 89000115 stw r4,4(r17) + 8008054: 8085883a add r2,r16,r2 + 8008058: 8a000315 stw r8,12(r17) + 800805c: 8a000215 stw r8,8(r17) + 8008060: 10c00015 stw r3,0(r2) + 8008064: 9009883a mov r4,r18 + 8008068: 800ff2c0 call 800ff2c <__malloc_unlock> + 800806c: 80800204 addi r2,r16,8 + 8008070: 00000306 br 8008080 <_malloc_r+0x2a4> + 8008074: 00800304 movi r2,12 + 8008078: 90800015 stw r2,0(r18) + 800807c: 0005883a mov r2,zero + 8008080: dfc00917 ldw ra,36(sp) + 8008084: df000817 ldw fp,32(sp) + 8008088: ddc00717 ldw r23,28(sp) + 800808c: dd800617 ldw r22,24(sp) + 8008090: dd400517 ldw r21,20(sp) + 8008094: dd000417 ldw r20,16(sp) + 8008098: dcc00317 ldw r19,12(sp) + 800809c: dc800217 ldw r18,8(sp) + 80080a0: dc400117 ldw r17,4(sp) + 80080a4: dc000017 ldw r16,0(sp) + 80080a8: dec00a04 addi sp,sp,40 + 80080ac: f800283a ret + 80080b0: 01408004 movi r5,512 + 80080b4: 01801004 movi r6,64 + 80080b8: 02000fc4 movi r8,63 + 80080bc: 003f8006 br 8007ec0 <_malloc_r+0xe4> + 80080c0: 14000317 ldw r16,12(r2) + 80080c4: 31800084 addi r6,r6,2 + 80080c8: 143f5f1e bne r2,r16,8007e48 <_malloc_r+0x6c> + 80080cc: 9c000417 ldw r16,16(r19) + 80080d0: 02020174 movhi r8,2053 + 80080d4: 422fab04 addi r8,r8,-16724 + 80080d8: 823f941e bne r16,r8,8007f2c <_malloc_r+0x150> + 80080dc: 3007d0ba srai r3,r6,2 + 80080e0: 01000044 movi r4,1 + 80080e4: 98800117 ldw r2,4(r19) + 80080e8: 20c8983a sll r4,r4,r3 + 80080ec: 113fae2e bgeu r2,r4,8007fa8 <_malloc_r+0x1cc> + 80080f0: 9c000217 ldw r16,8(r19) + 80080f4: 00bfff04 movi r2,-4 + 80080f8: 85000117 ldw r20,4(r16) + 80080fc: a0ac703a and r22,r20,r2 + 8008100: b4400336 bltu r22,r17,8008110 <_malloc_r+0x334> + 8008104: b445c83a sub r2,r22,r17 + 8008108: 10c00408 cmpgei r3,r2,16 + 800810c: 1800561e bne r3,zero,8008268 <_malloc_r+0x48c> + 8008110: 00820174 movhi r2,2053 + 8008114: 10b2b017 ldw r2,-13632(r2) + 8008118: 00c20174 movhi r3,2053 + 800811c: 1d32ef17 ldw r20,-13380(r3) + 8008120: 10bfffd8 cmpnei r2,r2,-1 + 8008124: 85ab883a add r21,r16,r22 + 8008128: 8d29883a add r20,r17,r20 + 800812c: 1000c826 beq r2,zero,8008450 <_malloc_r+0x674> + 8008130: a50403c4 addi r20,r20,4111 + 8008134: 00bc0004 movi r2,-4096 + 8008138: a0a8703a and r20,r20,r2 + 800813c: a00b883a mov r5,r20 + 8008140: 9009883a mov r4,r18 + 8008144: 800a16c0 call 800a16c <_sbrk_r> + 8008148: 102f883a mov r23,r2 + 800814c: 10bfffd8 cmpnei r2,r2,-1 + 8008150: 10009a26 beq r2,zero,80083bc <_malloc_r+0x5e0> + 8008154: bd409836 bltu r23,r21,80083b8 <_malloc_r+0x5dc> + 8008158: 00820174 movhi r2,2053 + 800815c: 10b36417 ldw r2,-12912(r2) + 8008160: 00c20174 movhi r3,2053 + 8008164: a085883a add r2,r20,r2 + 8008168: 18b36415 stw r2,-12912(r3) + 800816c: 1007883a mov r3,r2 + 8008170: adc0dd26 beq r21,r23,80084e8 <_malloc_r+0x70c> + 8008174: 00820174 movhi r2,2053 + 8008178: 10b2b017 ldw r2,-13632(r2) + 800817c: 10bfffd8 cmpnei r2,r2,-1 + 8008180: 1000e026 beq r2,zero,8008504 <_malloc_r+0x728> + 8008184: bd6bc83a sub r21,r23,r21 + 8008188: a8c7883a add r3,r21,r3 + 800818c: 00820174 movhi r2,2053 + 8008190: 10f36415 stw r3,-12912(r2) + 8008194: bf0001cc andi fp,r23,7 + 8008198: e000b626 beq fp,zero,8008474 <_malloc_r+0x698> + 800819c: bf2fc83a sub r23,r23,fp + 80081a0: bdc00204 addi r23,r23,8 + 80081a4: 00840204 movi r2,4104 + 80081a8: 1705c83a sub r2,r2,fp + 80081ac: bd29883a add r20,r23,r20 + 80081b0: 1505c83a sub r2,r2,r20 + 80081b4: 1543ffcc andi r21,r2,4095 + 80081b8: a80b883a mov r5,r21 + 80081bc: 9009883a mov r4,r18 + 80081c0: 800a16c0 call 800a16c <_sbrk_r> + 80081c4: 10ffffe0 cmpeqi r3,r2,-1 + 80081c8: 1800e41e bne r3,zero,800855c <_malloc_r+0x780> + 80081cc: 15c5c83a sub r2,r2,r23 + 80081d0: 1569883a add r20,r2,r21 + 80081d4: 00820174 movhi r2,2053 + 80081d8: 10b36417 ldw r2,-12912(r2) + 80081dc: 9dc00215 stw r23,8(r19) + 80081e0: a5000054 ori r20,r20,1 + 80081e4: a885883a add r2,r21,r2 + 80081e8: 00c20174 movhi r3,2053 + 80081ec: 18b36415 stw r2,-12912(r3) + 80081f0: bd000115 stw r20,4(r23) + 80081f4: 84c0c626 beq r16,r19,8008510 <_malloc_r+0x734> + 80081f8: b0c00428 cmpgeui r3,r22,16 + 80081fc: 1800c626 beq r3,zero,8008518 <_malloc_r+0x73c> + 8008200: 81000117 ldw r4,4(r16) + 8008204: 017ffe04 movi r5,-8 + 8008208: b0fffd04 addi r3,r22,-12 + 800820c: 1946703a and r3,r3,r5 + 8008210: 2100004c andi r4,r4,1 + 8008214: 20c8b03a or r4,r4,r3 + 8008218: 81000115 stw r4,4(r16) + 800821c: 01400144 movi r5,5 + 8008220: 80c9883a add r4,r16,r3 + 8008224: 21400115 stw r5,4(r4) + 8008228: 21400215 stw r5,8(r4) + 800822c: 18c00428 cmpgeui r3,r3,16 + 8008230: 1800cf1e bne r3,zero,8008570 <_malloc_r+0x794> + 8008234: bd000117 ldw r20,4(r23) + 8008238: b821883a mov r16,r23 + 800823c: 00c20174 movhi r3,2053 + 8008240: 18f2ee17 ldw r3,-13384(r3) + 8008244: 1880022e bgeu r3,r2,8008250 <_malloc_r+0x474> + 8008248: 00c20174 movhi r3,2053 + 800824c: 18b2ee15 stw r2,-13384(r3) + 8008250: 00c20174 movhi r3,2053 + 8008254: 18f2ed17 ldw r3,-13388(r3) + 8008258: 18805a2e bgeu r3,r2,80083c4 <_malloc_r+0x5e8> + 800825c: 00c20174 movhi r3,2053 + 8008260: 18b2ed15 stw r2,-13388(r3) + 8008264: 00005706 br 80083c4 <_malloc_r+0x5e8> + 8008268: 88c00054 ori r3,r17,1 + 800826c: 80c00115 stw r3,4(r16) + 8008270: 8463883a add r17,r16,r17 + 8008274: 10800054 ori r2,r2,1 + 8008278: 9c400215 stw r17,8(r19) + 800827c: 88800115 stw r2,4(r17) + 8008280: 9009883a mov r4,r18 + 8008284: 800ff2c0 call 800ff2c <__malloc_unlock> + 8008288: 80800204 addi r2,r16,8 + 800828c: 003f7c06 br 8008080 <_malloc_r+0x2a4> + 8008290: 400d883a mov r6,r8 + 8008294: 003f2106 br 8007f1c <_malloc_r+0x140> + 8008298: 81000317 ldw r4,12(r16) + 800829c: 003eee06 br 8007e58 <_malloc_r+0x7c> + 80082a0: 1006d27a srli r3,r2,9 + 80082a4: 19000168 cmpgeui r4,r3,5 + 80082a8: 20003e26 beq r4,zero,80083a4 <_malloc_r+0x5c8> + 80082ac: 19000568 cmpgeui r4,r3,21 + 80082b0: 20007a1e bne r4,zero,800849c <_malloc_r+0x6c0> + 80082b4: 19401704 addi r5,r3,92 + 80082b8: 280a90fa slli r5,r5,3 + 80082bc: 190016c4 addi r4,r3,91 + 80082c0: 994b883a add r5,r19,r5 + 80082c4: 28c00017 ldw r3,0(r5) + 80082c8: 297ffe04 addi r5,r5,-8 + 80082cc: 28c06226 beq r5,r3,8008458 <_malloc_r+0x67c> + 80082d0: 01ffff04 movi r7,-4 + 80082d4: 19000117 ldw r4,4(r3) + 80082d8: 21c8703a and r4,r4,r7 + 80082dc: 1100022e bgeu r2,r4,80082e8 <_malloc_r+0x50c> + 80082e0: 18c00217 ldw r3,8(r3) + 80082e4: 28fffb1e bne r5,r3,80082d4 <_malloc_r+0x4f8> + 80082e8: 19400317 ldw r5,12(r3) + 80082ec: 98800117 ldw r2,4(r19) + 80082f0: 81400315 stw r5,12(r16) + 80082f4: 80c00215 stw r3,8(r16) + 80082f8: 2c000215 stw r16,8(r5) + 80082fc: 1c000315 stw r16,12(r3) + 8008300: 003f2506 br 8007f98 <_malloc_r+0x1bc> + 8008304: 10c00568 cmpgeui r3,r2,21 + 8008308: 18003826 beq r3,zero,80083ec <_malloc_r+0x610> + 800830c: 10c01568 cmpgeui r3,r2,85 + 8008310: 1800691e bne r3,zero,80084b8 <_malloc_r+0x6dc> + 8008314: 8804d33a srli r2,r17,12 + 8008318: 11801bc4 addi r6,r2,111 + 800831c: 12001b84 addi r8,r2,110 + 8008320: 300a90fa slli r5,r6,3 + 8008324: 003ee606 br 8007ec0 <_malloc_r+0xe4> + 8008328: 5ac00044 addi r11,r11,1 + 800832c: 588000cc andi r2,r11,3 + 8008330: 39c00204 addi r7,r7,8 + 8008334: 103f2d1e bne r2,zero,8007fec <_malloc_r+0x210> + 8008338: 00003306 br 8008408 <_malloc_r+0x62c> + 800833c: 8085883a add r2,r16,r2 + 8008340: 10c00117 ldw r3,4(r2) + 8008344: 81000317 ldw r4,12(r16) + 8008348: 81400217 ldw r5,8(r16) + 800834c: 18c00054 ori r3,r3,1 + 8008350: 10c00115 stw r3,4(r2) + 8008354: 29000315 stw r4,12(r5) + 8008358: 21400215 stw r5,8(r4) + 800835c: 9009883a mov r4,r18 + 8008360: 800ff2c0 call 800ff2c <__malloc_unlock> + 8008364: 80800204 addi r2,r16,8 + 8008368: 003f4506 br 8008080 <_malloc_r+0x2a4> + 800836c: 880cd0fa srli r6,r17,3 + 8008370: 88800204 addi r2,r17,8 + 8008374: 003eae06 br 8007e30 <_malloc_r+0x54> + 8008378: 8085883a add r2,r16,r2 + 800837c: 10c00117 ldw r3,4(r2) + 8008380: 9009883a mov r4,r18 + 8008384: 18c00054 ori r3,r3,1 + 8008388: 10c00115 stw r3,4(r2) + 800838c: 800ff2c0 call 800ff2c <__malloc_unlock> + 8008390: 80800204 addi r2,r16,8 + 8008394: 003f3a06 br 8008080 <_malloc_r+0x2a4> + 8008398: 89000054 ori r4,r17,1 + 800839c: 81000115 stw r4,4(r16) + 80083a0: 003f2706 br 8008040 <_malloc_r+0x264> + 80083a4: 1006d1ba srli r3,r2,6 + 80083a8: 19400e44 addi r5,r3,57 + 80083ac: 19000e04 addi r4,r3,56 + 80083b0: 280a90fa slli r5,r5,3 + 80083b4: 003fc206 br 80082c0 <_malloc_r+0x4e4> + 80083b8: 84c04626 beq r16,r19,80084d4 <_malloc_r+0x6f8> + 80083bc: 9c000217 ldw r16,8(r19) + 80083c0: 85000117 ldw r20,4(r16) + 80083c4: 00bfff04 movi r2,-4 + 80083c8: a0a8703a and r20,r20,r2 + 80083cc: a445c83a sub r2,r20,r17 + 80083d0: a4400236 bltu r20,r17,80083dc <_malloc_r+0x600> + 80083d4: 10c00408 cmpgei r3,r2,16 + 80083d8: 183fa31e bne r3,zero,8008268 <_malloc_r+0x48c> + 80083dc: 9009883a mov r4,r18 + 80083e0: 800ff2c0 call 800ff2c <__malloc_unlock> + 80083e4: 0005883a mov r2,zero + 80083e8: 003f2506 br 8008080 <_malloc_r+0x2a4> + 80083ec: 11801704 addi r6,r2,92 + 80083f0: 120016c4 addi r8,r2,91 + 80083f4: 300a90fa slli r5,r6,3 + 80083f8: 003eb106 br 8007ec0 <_malloc_r+0xe4> + 80083fc: 50800217 ldw r2,8(r10) + 8008400: 31bfffc4 addi r6,r6,-1 + 8008404: 1280701e bne r2,r10,80085c8 <_malloc_r+0x7ec> + 8008408: 308000cc andi r2,r6,3 + 800840c: 52bffe04 addi r10,r10,-8 + 8008410: 103ffa1e bne r2,zero,80083fc <_malloc_r+0x620> + 8008414: 98c00117 ldw r3,4(r19) + 8008418: 0104303a nor r2,zero,r4 + 800841c: 10c4703a and r2,r2,r3 + 8008420: 98800115 stw r2,4(r19) + 8008424: 2109883a add r4,r4,r4 + 8008428: 113f3136 bltu r2,r4,80080f0 <_malloc_r+0x314> + 800842c: 203f3026 beq r4,zero,80080f0 <_malloc_r+0x314> + 8008430: 2086703a and r3,r4,r2 + 8008434: 1800041e bne r3,zero,8008448 <_malloc_r+0x66c> + 8008438: 2109883a add r4,r4,r4 + 800843c: 2086703a and r3,r4,r2 + 8008440: 5ac00104 addi r11,r11,4 + 8008444: 183ffc26 beq r3,zero,8008438 <_malloc_r+0x65c> + 8008448: 580d883a mov r6,r11 + 800844c: 003ee306 br 8007fdc <_malloc_r+0x200> + 8008450: a5000404 addi r20,r20,16 + 8008454: 003f3906 br 800813c <_malloc_r+0x360> + 8008458: 2009d0ba srai r4,r4,2 + 800845c: 00800044 movi r2,1 + 8008460: 99c00117 ldw r7,4(r19) + 8008464: 1104983a sll r2,r2,r4 + 8008468: 11c4b03a or r2,r2,r7 + 800846c: 98800115 stw r2,4(r19) + 8008470: 003f9f06 br 80082f0 <_malloc_r+0x514> + 8008474: bd05883a add r2,r23,r20 + 8008478: 0085c83a sub r2,zero,r2 + 800847c: 1543ffcc andi r21,r2,4095 + 8008480: a80b883a mov r5,r21 + 8008484: 9009883a mov r4,r18 + 8008488: 800a16c0 call 800a16c <_sbrk_r> + 800848c: 10ffffe0 cmpeqi r3,r2,-1 + 8008490: 183f4e26 beq r3,zero,80081cc <_malloc_r+0x3f0> + 8008494: 002b883a mov r21,zero + 8008498: 003f4e06 br 80081d4 <_malloc_r+0x3f8> + 800849c: 19001568 cmpgeui r4,r3,85 + 80084a0: 2000201e bne r4,zero,8008524 <_malloc_r+0x748> + 80084a4: 1006d33a srli r3,r2,12 + 80084a8: 19401bc4 addi r5,r3,111 + 80084ac: 19001b84 addi r4,r3,110 + 80084b0: 280a90fa slli r5,r5,3 + 80084b4: 003f8206 br 80082c0 <_malloc_r+0x4e4> + 80084b8: 10c05568 cmpgeui r3,r2,341 + 80084bc: 1800201e bne r3,zero,8008540 <_malloc_r+0x764> + 80084c0: 8804d3fa srli r2,r17,15 + 80084c4: 11801e04 addi r6,r2,120 + 80084c8: 12001dc4 addi r8,r2,119 + 80084cc: 300a90fa slli r5,r6,3 + 80084d0: 003e7b06 br 8007ec0 <_malloc_r+0xe4> + 80084d4: 00820174 movhi r2,2053 + 80084d8: 10f36417 ldw r3,-12912(r2) + 80084dc: a0c7883a add r3,r20,r3 + 80084e0: 10f36415 stw r3,-12912(r2) + 80084e4: 003f2306 br 8008174 <_malloc_r+0x398> + 80084e8: a903ffcc andi r4,r21,4095 + 80084ec: 203f211e bne r4,zero,8008174 <_malloc_r+0x398> + 80084f0: 9c000217 ldw r16,8(r19) + 80084f4: b529883a add r20,r22,r20 + 80084f8: a5000054 ori r20,r20,1 + 80084fc: 85000115 stw r20,4(r16) + 8008500: 003f4e06 br 800823c <_malloc_r+0x460> + 8008504: 00820174 movhi r2,2053 + 8008508: 15f2b015 stw r23,-13632(r2) + 800850c: 003f2106 br 8008194 <_malloc_r+0x3b8> + 8008510: b821883a mov r16,r23 + 8008514: 003f4906 br 800823c <_malloc_r+0x460> + 8008518: 00800044 movi r2,1 + 800851c: b8800115 stw r2,4(r23) + 8008520: 003fae06 br 80083dc <_malloc_r+0x600> + 8008524: 19005568 cmpgeui r4,r3,341 + 8008528: 2000191e bne r4,zero,8008590 <_malloc_r+0x7b4> + 800852c: 1006d3fa srli r3,r2,15 + 8008530: 19401e04 addi r5,r3,120 + 8008534: 19001dc4 addi r4,r3,119 + 8008538: 280a90fa slli r5,r5,3 + 800853c: 003f6006 br 80082c0 <_malloc_r+0x4e4> + 8008540: 10815568 cmpgeui r2,r2,1365 + 8008544: 1000191e bne r2,zero,80085ac <_malloc_r+0x7d0> + 8008548: 8804d4ba srli r2,r17,18 + 800854c: 11801f44 addi r6,r2,125 + 8008550: 12001f04 addi r8,r2,124 + 8008554: 300a90fa slli r5,r6,3 + 8008558: 003e5906 br 8007ec0 <_malloc_r+0xe4> + 800855c: e73ffe04 addi fp,fp,-8 + 8008560: a729883a add r20,r20,fp + 8008564: a5e9c83a sub r20,r20,r23 + 8008568: 002b883a mov r21,zero + 800856c: 003f1906 br 80081d4 <_malloc_r+0x3f8> + 8008570: 81400204 addi r5,r16,8 + 8008574: 9009883a mov r4,r18 + 8008578: 80071c40 call 80071c4 <_free_r> + 800857c: 9c000217 ldw r16,8(r19) + 8008580: 00820174 movhi r2,2053 + 8008584: 10b36417 ldw r2,-12912(r2) + 8008588: 85000117 ldw r20,4(r16) + 800858c: 003f2b06 br 800823c <_malloc_r+0x460> + 8008590: 18c15568 cmpgeui r3,r3,1365 + 8008594: 1800091e bne r3,zero,80085bc <_malloc_r+0x7e0> + 8008598: 1006d4ba srli r3,r2,18 + 800859c: 19401f44 addi r5,r3,125 + 80085a0: 19001f04 addi r4,r3,124 + 80085a4: 280a90fa slli r5,r5,3 + 80085a8: 003f4506 br 80082c0 <_malloc_r+0x4e4> + 80085ac: 0140fe04 movi r5,1016 + 80085b0: 01801fc4 movi r6,127 + 80085b4: 02001f84 movi r8,126 + 80085b8: 003e4106 br 8007ec0 <_malloc_r+0xe4> + 80085bc: 0140fe04 movi r5,1016 + 80085c0: 01001f84 movi r4,126 + 80085c4: 003f3e06 br 80082c0 <_malloc_r+0x4e4> + 80085c8: 98800117 ldw r2,4(r19) + 80085cc: 003f9506 br 8008424 <_malloc_r+0x648> + +080085d0 : + 80085d0: 208000cc andi r2,r4,3 + 80085d4: 280f883a mov r7,r5 + 80085d8: 10003526 beq r2,zero,80086b0 + 80085dc: 30bfffc4 addi r2,r6,-1 + 80085e0: 30001926 beq r6,zero,8008648 + 80085e4: 20c00003 ldbu r3,0(r4) + 80085e8: 29803fcc andi r6,r5,255 + 80085ec: 30c0061e bne r6,r3,8008608 + 80085f0: 00001706 br 8008650 + 80085f4: 10bfffc4 addi r2,r2,-1 + 80085f8: 10ffffe0 cmpeqi r3,r2,-1 + 80085fc: 1800121e bne r3,zero,8008648 + 8008600: 20c00003 ldbu r3,0(r4) + 8008604: 19801226 beq r3,r6,8008650 + 8008608: 21000044 addi r4,r4,1 + 800860c: 20c000cc andi r3,r4,3 + 8008610: 183ff81e bne r3,zero,80085f4 + 8008614: 10c00128 cmpgeui r3,r2,4 + 8008618: 18000f1e bne r3,zero,8008658 + 800861c: 10000a26 beq r2,zero,8008648 + 8008620: 20c00003 ldbu r3,0(r4) + 8008624: 29403fcc andi r5,r5,255 + 8008628: 19400926 beq r3,r5,8008650 + 800862c: 2085883a add r2,r4,r2 + 8008630: 39403fcc andi r5,r7,255 + 8008634: 00000206 br 8008640 + 8008638: 20c00003 ldbu r3,0(r4) + 800863c: 19400426 beq r3,r5,8008650 + 8008640: 21000044 addi r4,r4,1 + 8008644: 113ffc1e bne r2,r4,8008638 + 8008648: 0005883a mov r2,zero + 800864c: f800283a ret + 8008650: 2005883a mov r2,r4 + 8008654: f800283a ret + 8008658: 280c923a slli r6,r5,8 + 800865c: 2a403fcc andi r9,r5,255 + 8008660: 02bfbff4 movhi r10,65279 + 8008664: 31bfffcc andi r6,r6,65535 + 8008668: 3246b03a or r3,r6,r9 + 800866c: 1812943a slli r9,r3,16 + 8008670: 02202074 movhi r8,32897 + 8008674: 52bfbfc4 addi r10,r10,-257 + 8008678: 48d2b03a or r9,r9,r3 + 800867c: 42202004 addi r8,r8,-32640 + 8008680: 20c00017 ldw r3,0(r4) + 8008684: 48c6f03a xor r3,r9,r3 + 8008688: 1a8d883a add r6,r3,r10 + 800868c: 00c6303a nor r3,zero,r3 + 8008690: 30c6703a and r3,r6,r3 + 8008694: 1a06703a and r3,r3,r8 + 8008698: 183fe11e bne r3,zero,8008620 + 800869c: 10bfff04 addi r2,r2,-4 + 80086a0: 10c00128 cmpgeui r3,r2,4 + 80086a4: 21000104 addi r4,r4,4 + 80086a8: 183ff51e bne r3,zero,8008680 + 80086ac: 003fdb06 br 800861c + 80086b0: 3005883a mov r2,r6 + 80086b4: 003fd706 br 8008614 + +080086b8 : + 80086b8: 30c00430 cmpltui r3,r6,16 + 80086bc: 2005883a mov r2,r4 + 80086c0: 18002d1e bne r3,zero,8008778 + 80086c4: 2906b03a or r3,r5,r4 + 80086c8: 18c000cc andi r3,r3,3 + 80086cc: 1800351e bne r3,zero,80087a4 + 80086d0: 32fffc04 addi r11,r6,-16 + 80086d4: 5816d13a srli r11,r11,4 + 80086d8: 2007883a mov r3,r4 + 80086dc: 280f883a mov r7,r5 + 80086e0: 5ac00044 addi r11,r11,1 + 80086e4: 5816913a slli r11,r11,4 + 80086e8: 22c9883a add r4,r4,r11 + 80086ec: 3a000017 ldw r8,0(r7) + 80086f0: 3a800117 ldw r10,4(r7) + 80086f4: 3a400217 ldw r9,8(r7) + 80086f8: 39c00404 addi r7,r7,16 + 80086fc: 1a000015 stw r8,0(r3) + 8008700: 3a3fff17 ldw r8,-4(r7) + 8008704: 1a800115 stw r10,4(r3) + 8008708: 1a400215 stw r9,8(r3) + 800870c: 18c00404 addi r3,r3,16 + 8008710: 1a3fff15 stw r8,-4(r3) + 8008714: 20fff51e bne r4,r3,80086ec + 8008718: 3100030c andi r4,r6,12 + 800871c: 2acb883a add r5,r5,r11 + 8008720: 320003cc andi r8,r6,15 + 8008724: 20002226 beq r4,zero,80087b0 + 8008728: 2809883a mov r4,r5 + 800872c: 1813883a mov r9,r3 + 8008730: 21000104 addi r4,r4,4 + 8008734: 22bfff17 ldw r10,-4(r4) + 8008738: 410fc83a sub r7,r8,r4 + 800873c: 4a400104 addi r9,r9,4 + 8008740: 29cf883a add r7,r5,r7 + 8008744: 4abfff15 stw r10,-4(r9) + 8008748: 39c00128 cmpgeui r7,r7,4 + 800874c: 383ff81e bne r7,zero,8008730 + 8008750: 413fff04 addi r4,r8,-4 + 8008754: 2008d0ba srli r4,r4,2 + 8008758: 318000cc andi r6,r6,3 + 800875c: 31ffffc4 addi r7,r6,-1 + 8008760: 21000044 addi r4,r4,1 + 8008764: 200890ba slli r4,r4,2 + 8008768: 1907883a add r3,r3,r4 + 800876c: 290b883a add r5,r5,r4 + 8008770: 3000041e bne r6,zero,8008784 + 8008774: f800283a ret + 8008778: 2007883a mov r3,r4 + 800877c: 31ffffc4 addi r7,r6,-1 + 8008780: 303ffc26 beq r6,zero,8008774 + 8008784: 39c00044 addi r7,r7,1 + 8008788: 19cf883a add r7,r3,r7 + 800878c: 29400044 addi r5,r5,1 + 8008790: 29bfffc3 ldbu r6,-1(r5) + 8008794: 18c00044 addi r3,r3,1 + 8008798: 19bfffc5 stb r6,-1(r3) + 800879c: 19fffb1e bne r3,r7,800878c + 80087a0: f800283a ret + 80087a4: 31ffffc4 addi r7,r6,-1 + 80087a8: 2007883a mov r3,r4 + 80087ac: 003ff506 br 8008784 + 80087b0: 400d883a mov r6,r8 + 80087b4: 003ff106 br 800877c + +080087b8 : + 80087b8: 2005883a mov r2,r4 + 80087bc: 29000a2e bgeu r5,r4,80087e8 + 80087c0: 2989883a add r4,r5,r6 + 80087c4: 1100082e bgeu r2,r4,80087e8 + 80087c8: 1187883a add r3,r2,r6 + 80087cc: 30003e26 beq r6,zero,80088c8 + 80087d0: 213fffc4 addi r4,r4,-1 + 80087d4: 21400003 ldbu r5,0(r4) + 80087d8: 18ffffc4 addi r3,r3,-1 + 80087dc: 19400005 stb r5,0(r3) + 80087e0: 10fffb1e bne r2,r3,80087d0 + 80087e4: f800283a ret + 80087e8: 30c00430 cmpltui r3,r6,16 + 80087ec: 18000b26 beq r3,zero,800881c + 80087f0: 1007883a mov r3,r2 + 80087f4: 31ffffc4 addi r7,r6,-1 + 80087f8: 30003726 beq r6,zero,80088d8 + 80087fc: 39c00044 addi r7,r7,1 + 8008800: 29cf883a add r7,r5,r7 + 8008804: 29400044 addi r5,r5,1 + 8008808: 29bfffc3 ldbu r6,-1(r5) + 800880c: 18c00044 addi r3,r3,1 + 8008810: 19bfffc5 stb r6,-1(r3) + 8008814: 29fffb1e bne r5,r7,8008804 + 8008818: f800283a ret + 800881c: 2886b03a or r3,r5,r2 + 8008820: 18c000cc andi r3,r3,3 + 8008824: 1800291e bne r3,zero,80088cc + 8008828: 327ffc04 addi r9,r6,-16 + 800882c: 4812d13a srli r9,r9,4 + 8008830: 280f883a mov r7,r5 + 8008834: 1007883a mov r3,r2 + 8008838: 4a400044 addi r9,r9,1 + 800883c: 4812913a slli r9,r9,4 + 8008840: 1251883a add r8,r2,r9 + 8008844: 39000017 ldw r4,0(r7) + 8008848: 18c00404 addi r3,r3,16 + 800884c: 39c00404 addi r7,r7,16 + 8008850: 193ffc15 stw r4,-16(r3) + 8008854: 393ffd17 ldw r4,-12(r7) + 8008858: 193ffd15 stw r4,-12(r3) + 800885c: 393ffe17 ldw r4,-8(r7) + 8008860: 193ffe15 stw r4,-8(r3) + 8008864: 393fff17 ldw r4,-4(r7) + 8008868: 193fff15 stw r4,-4(r3) + 800886c: 40fff51e bne r8,r3,8008844 + 8008870: 3100030c andi r4,r6,12 + 8008874: 2a4b883a add r5,r5,r9 + 8008878: 320003cc andi r8,r6,15 + 800887c: 20001726 beq r4,zero,80088dc + 8008880: 2813883a mov r9,r5 + 8008884: 180f883a mov r7,r3 + 8008888: 4a400104 addi r9,r9,4 + 800888c: 39c00104 addi r7,r7,4 + 8008890: 4abfff17 ldw r10,-4(r9) + 8008894: 41c9c83a sub r4,r8,r7 + 8008898: 1909883a add r4,r3,r4 + 800889c: 3abfff15 stw r10,-4(r7) + 80088a0: 21000128 cmpgeui r4,r4,4 + 80088a4: 203ff81e bne r4,zero,8008888 + 80088a8: 413fff04 addi r4,r8,-4 + 80088ac: 2008d0ba srli r4,r4,2 + 80088b0: 318000cc andi r6,r6,3 + 80088b4: 21000044 addi r4,r4,1 + 80088b8: 200890ba slli r4,r4,2 + 80088bc: 1907883a add r3,r3,r4 + 80088c0: 290b883a add r5,r5,r4 + 80088c4: 003fcb06 br 80087f4 + 80088c8: f800283a ret + 80088cc: 31ffffc4 addi r7,r6,-1 + 80088d0: 1007883a mov r3,r2 + 80088d4: 003fc906 br 80087fc + 80088d8: f800283a ret + 80088dc: 400d883a mov r6,r8 + 80088e0: 003fc406 br 80087f4 + +080088e4 : + 80088e4: 20c000cc andi r3,r4,3 + 80088e8: 2005883a mov r2,r4 + 80088ec: 18003626 beq r3,zero,80089c8 + 80088f0: 31ffffc4 addi r7,r6,-1 + 80088f4: 30003326 beq r6,zero,80089c4 + 80088f8: 2811883a mov r8,r5 + 80088fc: 2007883a mov r3,r4 + 8008900: 00000306 br 8008910 + 8008904: 39ffffc4 addi r7,r7,-1 + 8008908: 39bfffe0 cmpeqi r6,r7,-1 + 800890c: 30002d1e bne r6,zero,80089c4 + 8008910: 18c00044 addi r3,r3,1 + 8008914: 1a3fffc5 stb r8,-1(r3) + 8008918: 198000cc andi r6,r3,3 + 800891c: 303ff91e bne r6,zero,8008904 + 8008920: 39000130 cmpltui r4,r7,4 + 8008924: 2000221e bne r4,zero,80089b0 + 8008928: 29003fcc andi r4,r5,255 + 800892c: 200c923a slli r6,r4,8 + 8008930: 3a000430 cmpltui r8,r7,16 + 8008934: 3108b03a or r4,r6,r4 + 8008938: 200c943a slli r6,r4,16 + 800893c: 310cb03a or r6,r6,r4 + 8008940: 40000e1e bne r8,zero,800897c + 8008944: 3a3ffc04 addi r8,r7,-16 + 8008948: 4010d13a srli r8,r8,4 + 800894c: 42000044 addi r8,r8,1 + 8008950: 4010913a slli r8,r8,4 + 8008954: 1a11883a add r8,r3,r8 + 8008958: 19800015 stw r6,0(r3) + 800895c: 19800115 stw r6,4(r3) + 8008960: 19800215 stw r6,8(r3) + 8008964: 18c00404 addi r3,r3,16 + 8008968: 19bfff15 stw r6,-4(r3) + 800896c: 40fffa1e bne r8,r3,8008958 + 8008970: 3900030c andi r4,r7,12 + 8008974: 39c003cc andi r7,r7,15 + 8008978: 20000d26 beq r4,zero,80089b0 + 800897c: 1809883a mov r4,r3 + 8008980: 21000104 addi r4,r4,4 + 8008984: 3911c83a sub r8,r7,r4 + 8008988: 1a11883a add r8,r3,r8 + 800898c: 21bfff15 stw r6,-4(r4) + 8008990: 42000128 cmpgeui r8,r8,4 + 8008994: 403ffa1e bne r8,zero,8008980 + 8008998: 393fff04 addi r4,r7,-4 + 800899c: 2008d0ba srli r4,r4,2 + 80089a0: 39c000cc andi r7,r7,3 + 80089a4: 21000044 addi r4,r4,1 + 80089a8: 200890ba slli r4,r4,2 + 80089ac: 1907883a add r3,r3,r4 + 80089b0: 38000426 beq r7,zero,80089c4 + 80089b4: 19cf883a add r7,r3,r7 + 80089b8: 18c00044 addi r3,r3,1 + 80089bc: 197fffc5 stb r5,-1(r3) + 80089c0: 38fffd1e bne r7,r3,80089b8 + 80089c4: f800283a ret + 80089c8: 2007883a mov r3,r4 + 80089cc: 300f883a mov r7,r6 + 80089d0: 003fd306 br 8008920 + +080089d4 <_Balloc>: + 80089d4: 20801317 ldw r2,76(r4) + 80089d8: defffc04 addi sp,sp,-16 + 80089dc: dc400115 stw r17,4(sp) + 80089e0: dc000015 stw r16,0(sp) + 80089e4: dfc00315 stw ra,12(sp) + 80089e8: dc800215 stw r18,8(sp) + 80089ec: 2021883a mov r16,r4 + 80089f0: 2823883a mov r17,r5 + 80089f4: 10000e26 beq r2,zero,8008a30 <_Balloc+0x5c> + 80089f8: 880690ba slli r3,r17,2 + 80089fc: 10c7883a add r3,r2,r3 + 8008a00: 18800017 ldw r2,0(r3) + 8008a04: 10001126 beq r2,zero,8008a4c <_Balloc+0x78> + 8008a08: 11000017 ldw r4,0(r2) + 8008a0c: 19000015 stw r4,0(r3) + 8008a10: 10000415 stw zero,16(r2) + 8008a14: 10000315 stw zero,12(r2) + 8008a18: dfc00317 ldw ra,12(sp) + 8008a1c: dc800217 ldw r18,8(sp) + 8008a20: dc400117 ldw r17,4(sp) + 8008a24: dc000017 ldw r16,0(sp) + 8008a28: dec00404 addi sp,sp,16 + 8008a2c: f800283a ret + 8008a30: 01800844 movi r6,33 + 8008a34: 01400104 movi r5,4 + 8008a38: 800ba2c0 call 800ba2c <_calloc_r> + 8008a3c: 80801315 stw r2,76(r16) + 8008a40: 103fed1e bne r2,zero,80089f8 <_Balloc+0x24> + 8008a44: 0005883a mov r2,zero + 8008a48: 003ff306 br 8008a18 <_Balloc+0x44> + 8008a4c: 04800044 movi r18,1 + 8008a50: 9464983a sll r18,r18,r17 + 8008a54: 01400044 movi r5,1 + 8008a58: 8009883a mov r4,r16 + 8008a5c: 91800144 addi r6,r18,5 + 8008a60: 300c90ba slli r6,r6,2 + 8008a64: 800ba2c0 call 800ba2c <_calloc_r> + 8008a68: 103ff626 beq r2,zero,8008a44 <_Balloc+0x70> + 8008a6c: 14400115 stw r17,4(r2) + 8008a70: 14800215 stw r18,8(r2) + 8008a74: 003fe606 br 8008a10 <_Balloc+0x3c> + +08008a78 <_Bfree>: + 8008a78: 28000726 beq r5,zero,8008a98 <_Bfree+0x20> + 8008a7c: 28c00117 ldw r3,4(r5) + 8008a80: 20801317 ldw r2,76(r4) + 8008a84: 180690ba slli r3,r3,2 + 8008a88: 10c5883a add r2,r2,r3 + 8008a8c: 10c00017 ldw r3,0(r2) + 8008a90: 28c00015 stw r3,0(r5) + 8008a94: 11400015 stw r5,0(r2) + 8008a98: f800283a ret + +08008a9c <__multadd>: + 8008a9c: defffa04 addi sp,sp,-24 + 8008aa0: dc800315 stw r18,12(sp) + 8008aa4: dc400215 stw r17,8(sp) + 8008aa8: dc000115 stw r16,4(sp) + 8008aac: 2823883a mov r17,r5 + 8008ab0: 2c000417 ldw r16,16(r5) + 8008ab4: 2025883a mov r18,r4 + 8008ab8: dfc00515 stw ra,20(sp) + 8008abc: 29000504 addi r4,r5,20 + 8008ac0: dcc00415 stw r19,16(sp) + 8008ac4: 000b883a mov r5,zero + 8008ac8: 20800017 ldw r2,0(r4) + 8008acc: 21000104 addi r4,r4,4 + 8008ad0: 29400044 addi r5,r5,1 + 8008ad4: 10ffffcc andi r3,r2,65535 + 8008ad8: 1987383a mul r3,r3,r6 + 8008adc: 1004d43a srli r2,r2,16 + 8008ae0: 19cf883a add r7,r3,r7 + 8008ae4: 1185383a mul r2,r2,r6 + 8008ae8: 3810d43a srli r8,r7,16 + 8008aec: 38ffffcc andi r3,r7,65535 + 8008af0: 120f883a add r7,r2,r8 + 8008af4: 3804943a slli r2,r7,16 + 8008af8: 380ed43a srli r7,r7,16 + 8008afc: 10c7883a add r3,r2,r3 + 8008b00: 20ffff15 stw r3,-4(r4) + 8008b04: 2c3ff016 blt r5,r16,8008ac8 <__multadd+0x2c> + 8008b08: 38000826 beq r7,zero,8008b2c <__multadd+0x90> + 8008b0c: 88800217 ldw r2,8(r17) + 8008b10: 80800e0e bge r16,r2,8008b4c <__multadd+0xb0> + 8008b14: 80800144 addi r2,r16,5 + 8008b18: 100490ba slli r2,r2,2 + 8008b1c: 84000044 addi r16,r16,1 + 8008b20: 8885883a add r2,r17,r2 + 8008b24: 11c00015 stw r7,0(r2) + 8008b28: 8c000415 stw r16,16(r17) + 8008b2c: 8805883a mov r2,r17 + 8008b30: dfc00517 ldw ra,20(sp) + 8008b34: dcc00417 ldw r19,16(sp) + 8008b38: dc800317 ldw r18,12(sp) + 8008b3c: dc400217 ldw r17,8(sp) + 8008b40: dc000117 ldw r16,4(sp) + 8008b44: dec00604 addi sp,sp,24 + 8008b48: f800283a ret + 8008b4c: 89400117 ldw r5,4(r17) + 8008b50: 9009883a mov r4,r18 + 8008b54: d9c00015 stw r7,0(sp) + 8008b58: 29400044 addi r5,r5,1 + 8008b5c: 80089d40 call 80089d4 <_Balloc> + 8008b60: 89800417 ldw r6,16(r17) + 8008b64: 89400304 addi r5,r17,12 + 8008b68: 11000304 addi r4,r2,12 + 8008b6c: 31800084 addi r6,r6,2 + 8008b70: 300c90ba slli r6,r6,2 + 8008b74: 1027883a mov r19,r2 + 8008b78: 80086b80 call 80086b8 + 8008b7c: d9c00017 ldw r7,0(sp) + 8008b80: 88000926 beq r17,zero,8008ba8 <__multadd+0x10c> + 8008b84: 88c00117 ldw r3,4(r17) + 8008b88: 90801317 ldw r2,76(r18) + 8008b8c: 180690ba slli r3,r3,2 + 8008b90: 10c5883a add r2,r2,r3 + 8008b94: 10c00017 ldw r3,0(r2) + 8008b98: 88c00015 stw r3,0(r17) + 8008b9c: 14400015 stw r17,0(r2) + 8008ba0: 9823883a mov r17,r19 + 8008ba4: 003fdb06 br 8008b14 <__multadd+0x78> + 8008ba8: 9823883a mov r17,r19 + 8008bac: 003fd906 br 8008b14 <__multadd+0x78> + +08008bb0 <__s2b>: + 8008bb0: defff904 addi sp,sp,-28 + 8008bb4: dc800215 stw r18,8(sp) + 8008bb8: dc000015 stw r16,0(sp) + 8008bbc: 2025883a mov r18,r4 + 8008bc0: 2821883a mov r16,r5 + 8008bc4: 39000204 addi r4,r7,8 + 8008bc8: 01400244 movi r5,9 + 8008bcc: dcc00315 stw r19,12(sp) + 8008bd0: dc400115 stw r17,4(sp) + 8008bd4: dfc00615 stw ra,24(sp) + 8008bd8: 3823883a mov r17,r7 + 8008bdc: dd400515 stw r21,20(sp) + 8008be0: dd000415 stw r20,16(sp) + 8008be4: 3027883a mov r19,r6 + 8008be8: 800cf000 call 800cf00 <__divsi3> + 8008bec: 88c00290 cmplti r3,r17,10 + 8008bf0: 1800311e bne r3,zero,8008cb8 <__s2b+0x108> + 8008bf4: 00c00044 movi r3,1 + 8008bf8: 000b883a mov r5,zero + 8008bfc: 18c7883a add r3,r3,r3 + 8008c00: 29400044 addi r5,r5,1 + 8008c04: 18bffd16 blt r3,r2,8008bfc <__s2b+0x4c> + 8008c08: 9009883a mov r4,r18 + 8008c0c: 80089d40 call 80089d4 <_Balloc> + 8008c10: d8c00717 ldw r3,28(sp) + 8008c14: 10c00515 stw r3,20(r2) + 8008c18: 00c00044 movi r3,1 + 8008c1c: 10c00415 stw r3,16(r2) + 8008c20: 98c00290 cmplti r3,r19,10 + 8008c24: 1800211e bne r3,zero,8008cac <__s2b+0xfc> + 8008c28: 85400244 addi r21,r16,9 + 8008c2c: 84e9883a add r20,r16,r19 + 8008c30: a821883a mov r16,r21 + 8008c34: 84000044 addi r16,r16,1 + 8008c38: 81ffffc7 ldb r7,-1(r16) + 8008c3c: 01800284 movi r6,10 + 8008c40: 100b883a mov r5,r2 + 8008c44: 39fff404 addi r7,r7,-48 + 8008c48: 9009883a mov r4,r18 + 8008c4c: 8008a9c0 call 8008a9c <__multadd> + 8008c50: a43ff81e bne r20,r16,8008c34 <__s2b+0x84> + 8008c54: 9c3ffe04 addi r16,r19,-8 + 8008c58: ac21883a add r16,r21,r16 + 8008c5c: 9c400a0e bge r19,r17,8008c88 <__s2b+0xd8> + 8008c60: 8ce3c83a sub r17,r17,r19 + 8008c64: 8463883a add r17,r16,r17 + 8008c68: 84000044 addi r16,r16,1 + 8008c6c: 81ffffc7 ldb r7,-1(r16) + 8008c70: 01800284 movi r6,10 + 8008c74: 100b883a mov r5,r2 + 8008c78: 39fff404 addi r7,r7,-48 + 8008c7c: 9009883a mov r4,r18 + 8008c80: 8008a9c0 call 8008a9c <__multadd> + 8008c84: 8c3ff81e bne r17,r16,8008c68 <__s2b+0xb8> + 8008c88: dfc00617 ldw ra,24(sp) + 8008c8c: dd400517 ldw r21,20(sp) + 8008c90: dd000417 ldw r20,16(sp) + 8008c94: dcc00317 ldw r19,12(sp) + 8008c98: dc800217 ldw r18,8(sp) + 8008c9c: dc400117 ldw r17,4(sp) + 8008ca0: dc000017 ldw r16,0(sp) + 8008ca4: dec00704 addi sp,sp,28 + 8008ca8: f800283a ret + 8008cac: 84000284 addi r16,r16,10 + 8008cb0: 04c00244 movi r19,9 + 8008cb4: 003fe906 br 8008c5c <__s2b+0xac> + 8008cb8: 000b883a mov r5,zero + 8008cbc: 003fd206 br 8008c08 <__s2b+0x58> + +08008cc0 <__hi0bits>: + 8008cc0: 20bfffec andhi r2,r4,65535 + 8008cc4: 1000131e bne r2,zero,8008d14 <__hi0bits+0x54> + 8008cc8: 2008943a slli r4,r4,16 + 8008ccc: 00800404 movi r2,16 + 8008cd0: 20ffc02c andhi r3,r4,65280 + 8008cd4: 1800021e bne r3,zero,8008ce0 <__hi0bits+0x20> + 8008cd8: 2008923a slli r4,r4,8 + 8008cdc: 10800204 addi r2,r2,8 + 8008ce0: 20fc002c andhi r3,r4,61440 + 8008ce4: 1800021e bne r3,zero,8008cf0 <__hi0bits+0x30> + 8008ce8: 2008913a slli r4,r4,4 + 8008cec: 10800104 addi r2,r2,4 + 8008cf0: 20f0002c andhi r3,r4,49152 + 8008cf4: 1800021e bne r3,zero,8008d00 <__hi0bits+0x40> + 8008cf8: 200890ba slli r4,r4,2 + 8008cfc: 10800084 addi r2,r2,2 + 8008d00: 20000316 blt r4,zero,8008d10 <__hi0bits+0x50> + 8008d04: 2110002c andhi r4,r4,16384 + 8008d08: 10800044 addi r2,r2,1 + 8008d0c: 20000326 beq r4,zero,8008d1c <__hi0bits+0x5c> + 8008d10: f800283a ret + 8008d14: 0005883a mov r2,zero + 8008d18: 003fed06 br 8008cd0 <__hi0bits+0x10> + 8008d1c: 00800804 movi r2,32 + 8008d20: f800283a ret + +08008d24 <__lo0bits>: + 8008d24: 20c00017 ldw r3,0(r4) + 8008d28: 188001cc andi r2,r3,7 + 8008d2c: 10000826 beq r2,zero,8008d50 <__lo0bits+0x2c> + 8008d30: 1880004c andi r2,r3,1 + 8008d34: 10001f1e bne r2,zero,8008db4 <__lo0bits+0x90> + 8008d38: 1880008c andi r2,r3,2 + 8008d3c: 10002126 beq r2,zero,8008dc4 <__lo0bits+0xa0> + 8008d40: 1806d07a srli r3,r3,1 + 8008d44: 00800044 movi r2,1 + 8008d48: 20c00015 stw r3,0(r4) + 8008d4c: f800283a ret + 8008d50: 18bfffcc andi r2,r3,65535 + 8008d54: 1000151e bne r2,zero,8008dac <__lo0bits+0x88> + 8008d58: 1806d43a srli r3,r3,16 + 8008d5c: 00800404 movi r2,16 + 8008d60: 19403fcc andi r5,r3,255 + 8008d64: 2800021e bne r5,zero,8008d70 <__lo0bits+0x4c> + 8008d68: 1806d23a srli r3,r3,8 + 8008d6c: 10800204 addi r2,r2,8 + 8008d70: 194003cc andi r5,r3,15 + 8008d74: 2800021e bne r5,zero,8008d80 <__lo0bits+0x5c> + 8008d78: 1806d13a srli r3,r3,4 + 8008d7c: 10800104 addi r2,r2,4 + 8008d80: 194000cc andi r5,r3,3 + 8008d84: 2800021e bne r5,zero,8008d90 <__lo0bits+0x6c> + 8008d88: 1806d0ba srli r3,r3,2 + 8008d8c: 10800084 addi r2,r2,2 + 8008d90: 1940004c andi r5,r3,1 + 8008d94: 2800031e bne r5,zero,8008da4 <__lo0bits+0x80> + 8008d98: 1806d07a srli r3,r3,1 + 8008d9c: 10800044 addi r2,r2,1 + 8008da0: 18000626 beq r3,zero,8008dbc <__lo0bits+0x98> + 8008da4: 20c00015 stw r3,0(r4) + 8008da8: f800283a ret + 8008dac: 0005883a mov r2,zero + 8008db0: 003feb06 br 8008d60 <__lo0bits+0x3c> + 8008db4: 0005883a mov r2,zero + 8008db8: f800283a ret + 8008dbc: 00800804 movi r2,32 + 8008dc0: f800283a ret + 8008dc4: 1806d0ba srli r3,r3,2 + 8008dc8: 00800084 movi r2,2 + 8008dcc: 20c00015 stw r3,0(r4) + 8008dd0: f800283a ret + +08008dd4 <__i2b>: + 8008dd4: defffe04 addi sp,sp,-8 + 8008dd8: dc000015 stw r16,0(sp) + 8008ddc: 2821883a mov r16,r5 + 8008de0: 01400044 movi r5,1 + 8008de4: dfc00115 stw ra,4(sp) + 8008de8: 80089d40 call 80089d4 <_Balloc> + 8008dec: 01000044 movi r4,1 + 8008df0: 14000515 stw r16,20(r2) + 8008df4: 11000415 stw r4,16(r2) + 8008df8: dfc00117 ldw ra,4(sp) + 8008dfc: dc000017 ldw r16,0(sp) + 8008e00: dec00204 addi sp,sp,8 + 8008e04: f800283a ret + +08008e08 <__multiply>: + 8008e08: defffa04 addi sp,sp,-24 + 8008e0c: dd000415 stw r20,16(sp) + 8008e10: dcc00315 stw r19,12(sp) + 8008e14: 35000417 ldw r20,16(r6) + 8008e18: 2cc00417 ldw r19,16(r5) + 8008e1c: dc800215 stw r18,8(sp) + 8008e20: dc400115 stw r17,4(sp) + 8008e24: dfc00515 stw ra,20(sp) + 8008e28: dc000015 stw r16,0(sp) + 8008e2c: 2823883a mov r17,r5 + 8008e30: 3025883a mov r18,r6 + 8008e34: 9d000516 blt r19,r20,8008e4c <__multiply+0x44> + 8008e38: a007883a mov r3,r20 + 8008e3c: 2825883a mov r18,r5 + 8008e40: 9829883a mov r20,r19 + 8008e44: 3023883a mov r17,r6 + 8008e48: 1827883a mov r19,r3 + 8008e4c: 90800217 ldw r2,8(r18) + 8008e50: a4e1883a add r16,r20,r19 + 8008e54: 91400117 ldw r5,4(r18) + 8008e58: 1400010e bge r2,r16,8008e60 <__multiply+0x58> + 8008e5c: 29400044 addi r5,r5,1 + 8008e60: 80089d40 call 80089d4 <_Balloc> + 8008e64: 801290ba slli r9,r16,2 + 8008e68: 12800504 addi r10,r2,20 + 8008e6c: 5007883a mov r3,r10 + 8008e70: 5253883a add r9,r10,r9 + 8008e74: 5240032e bgeu r10,r9,8008e84 <__multiply+0x7c> + 8008e78: 18000015 stw zero,0(r3) + 8008e7c: 18c00104 addi r3,r3,4 + 8008e80: 1a7ffd36 bltu r3,r9,8008e78 <__multiply+0x70> + 8008e84: 981690ba slli r11,r19,2 + 8008e88: a01090ba slli r8,r20,2 + 8008e8c: 89400504 addi r5,r17,20 + 8008e90: 91800504 addi r6,r18,20 + 8008e94: 2ad7883a add r11,r5,r11 + 8008e98: 3211883a add r8,r6,r8 + 8008e9c: 2ac00636 bltu r5,r11,8008eb8 <__multiply+0xb0> + 8008ea0: 00004106 br 8008fa8 <__multiply+0x1a0> + 8008ea4: 701cd43a srli r14,r14,16 + 8008ea8: 7000221e bne r14,zero,8008f34 <__multiply+0x12c> + 8008eac: 29400104 addi r5,r5,4 + 8008eb0: 52800104 addi r10,r10,4 + 8008eb4: 2ac03c2e bgeu r5,r11,8008fa8 <__multiply+0x1a0> + 8008eb8: 2b800017 ldw r14,0(r5) + 8008ebc: 73ffffcc andi r15,r14,65535 + 8008ec0: 783ff826 beq r15,zero,8008ea4 <__multiply+0x9c> + 8008ec4: 501b883a mov r13,r10 + 8008ec8: 301d883a mov r14,r6 + 8008ecc: 003f883a mov ra,zero + 8008ed0: 71000017 ldw r4,0(r14) + 8008ed4: 6b000017 ldw r12,0(r13) + 8008ed8: 6b400104 addi r13,r13,4 + 8008edc: 21ffffcc andi r7,r4,65535 + 8008ee0: 3bcf383a mul r7,r7,r15 + 8008ee4: 2006d43a srli r3,r4,16 + 8008ee8: 613fffcc andi r4,r12,65535 + 8008eec: 390f883a add r7,r7,r4 + 8008ef0: 3fcf883a add r7,r7,ra + 8008ef4: 1bc7383a mul r3,r3,r15 + 8008ef8: 6018d43a srli r12,r12,16 + 8008efc: 3808d43a srli r4,r7,16 + 8008f00: 39ffffcc andi r7,r7,65535 + 8008f04: 1b07883a add r3,r3,r12 + 8008f08: 1907883a add r3,r3,r4 + 8008f0c: 1808943a slli r4,r3,16 + 8008f10: 73800104 addi r14,r14,4 + 8008f14: 183ed43a srli ra,r3,16 + 8008f18: 21ceb03a or r7,r4,r7 + 8008f1c: 69ffff15 stw r7,-4(r13) + 8008f20: 723feb36 bltu r14,r8,8008ed0 <__multiply+0xc8> + 8008f24: 6fc00015 stw ra,0(r13) + 8008f28: 2b800017 ldw r14,0(r5) + 8008f2c: 701cd43a srli r14,r14,16 + 8008f30: 703fde26 beq r14,zero,8008eac <__multiply+0xa4> + 8008f34: 50c00017 ldw r3,0(r10) + 8008f38: 501b883a mov r13,r10 + 8008f3c: 3019883a mov r12,r6 + 8008f40: 180f883a mov r7,r3 + 8008f44: 001f883a mov r15,zero + 8008f48: 6100000b ldhu r4,0(r12) + 8008f4c: 380ed43a srli r7,r7,16 + 8008f50: 18ffffcc andi r3,r3,65535 + 8008f54: 2389383a mul r4,r4,r14 + 8008f58: 6b400104 addi r13,r13,4 + 8008f5c: 63000104 addi r12,r12,4 + 8008f60: 21c9883a add r4,r4,r7 + 8008f64: 23c9883a add r4,r4,r15 + 8008f68: 201e943a slli r15,r4,16 + 8008f6c: 69c00017 ldw r7,0(r13) + 8008f70: 2008d43a srli r4,r4,16 + 8008f74: 78c6b03a or r3,r15,r3 + 8008f78: 68ffff15 stw r3,-4(r13) + 8008f7c: 60ffff8b ldhu r3,-2(r12) + 8008f80: 3bffffcc andi r15,r7,65535 + 8008f84: 1b87383a mul r3,r3,r14 + 8008f88: 1bc7883a add r3,r3,r15 + 8008f8c: 1907883a add r3,r3,r4 + 8008f90: 181ed43a srli r15,r3,16 + 8008f94: 623fec36 bltu r12,r8,8008f48 <__multiply+0x140> + 8008f98: 68c00015 stw r3,0(r13) + 8008f9c: 29400104 addi r5,r5,4 + 8008fa0: 52800104 addi r10,r10,4 + 8008fa4: 2affc436 bltu r5,r11,8008eb8 <__multiply+0xb0> + 8008fa8: 0400090e bge zero,r16,8008fd0 <__multiply+0x1c8> + 8008fac: 48ffff17 ldw r3,-4(r9) + 8008fb0: 4a7fff04 addi r9,r9,-4 + 8008fb4: 18000326 beq r3,zero,8008fc4 <__multiply+0x1bc> + 8008fb8: 00000506 br 8008fd0 <__multiply+0x1c8> + 8008fbc: 48c00017 ldw r3,0(r9) + 8008fc0: 1800031e bne r3,zero,8008fd0 <__multiply+0x1c8> + 8008fc4: 843fffc4 addi r16,r16,-1 + 8008fc8: 4a7fff04 addi r9,r9,-4 + 8008fcc: 803ffb1e bne r16,zero,8008fbc <__multiply+0x1b4> + 8008fd0: 14000415 stw r16,16(r2) + 8008fd4: dfc00517 ldw ra,20(sp) + 8008fd8: dd000417 ldw r20,16(sp) + 8008fdc: dcc00317 ldw r19,12(sp) + 8008fe0: dc800217 ldw r18,8(sp) + 8008fe4: dc400117 ldw r17,4(sp) + 8008fe8: dc000017 ldw r16,0(sp) + 8008fec: dec00604 addi sp,sp,24 + 8008ff0: f800283a ret + +08008ff4 <__pow5mult>: + 8008ff4: defffb04 addi sp,sp,-20 + 8008ff8: dcc00315 stw r19,12(sp) + 8008ffc: dc000015 stw r16,0(sp) + 8009000: dfc00415 stw ra,16(sp) + 8009004: dc800215 stw r18,8(sp) + 8009008: dc400115 stw r17,4(sp) + 800900c: 308000cc andi r2,r6,3 + 8009010: 3021883a mov r16,r6 + 8009014: 2027883a mov r19,r4 + 8009018: 10002d1e bne r2,zero,80090d0 <__pow5mult+0xdc> + 800901c: 2825883a mov r18,r5 + 8009020: 8021d0ba srai r16,r16,2 + 8009024: 80001926 beq r16,zero,800908c <__pow5mult+0x98> + 8009028: 9c401217 ldw r17,72(r19) + 800902c: 8800061e bne r17,zero,8009048 <__pow5mult+0x54> + 8009030: 00002f06 br 80090f0 <__pow5mult+0xfc> + 8009034: 8021d07a srai r16,r16,1 + 8009038: 80001426 beq r16,zero,800908c <__pow5mult+0x98> + 800903c: 88800017 ldw r2,0(r17) + 8009040: 10001a26 beq r2,zero,80090ac <__pow5mult+0xb8> + 8009044: 1023883a mov r17,r2 + 8009048: 8080004c andi r2,r16,1 + 800904c: 103ff926 beq r2,zero,8009034 <__pow5mult+0x40> + 8009050: 880d883a mov r6,r17 + 8009054: 900b883a mov r5,r18 + 8009058: 9809883a mov r4,r19 + 800905c: 8008e080 call 8008e08 <__multiply> + 8009060: 90001926 beq r18,zero,80090c8 <__pow5mult+0xd4> + 8009064: 91000117 ldw r4,4(r18) + 8009068: 98c01317 ldw r3,76(r19) + 800906c: 8021d07a srai r16,r16,1 + 8009070: 200890ba slli r4,r4,2 + 8009074: 1907883a add r3,r3,r4 + 8009078: 19000017 ldw r4,0(r3) + 800907c: 91000015 stw r4,0(r18) + 8009080: 1c800015 stw r18,0(r3) + 8009084: 1025883a mov r18,r2 + 8009088: 803fec1e bne r16,zero,800903c <__pow5mult+0x48> + 800908c: 9005883a mov r2,r18 + 8009090: dfc00417 ldw ra,16(sp) + 8009094: dcc00317 ldw r19,12(sp) + 8009098: dc800217 ldw r18,8(sp) + 800909c: dc400117 ldw r17,4(sp) + 80090a0: dc000017 ldw r16,0(sp) + 80090a4: dec00504 addi sp,sp,20 + 80090a8: f800283a ret + 80090ac: 880d883a mov r6,r17 + 80090b0: 880b883a mov r5,r17 + 80090b4: 9809883a mov r4,r19 + 80090b8: 8008e080 call 8008e08 <__multiply> + 80090bc: 88800015 stw r2,0(r17) + 80090c0: 10000015 stw zero,0(r2) + 80090c4: 003fdf06 br 8009044 <__pow5mult+0x50> + 80090c8: 1025883a mov r18,r2 + 80090cc: 003fd906 br 8009034 <__pow5mult+0x40> + 80090d0: 100490ba slli r2,r2,2 + 80090d4: 00c20134 movhi r3,2052 + 80090d8: 000f883a mov r7,zero + 80090dc: 10c7883a add r3,r2,r3 + 80090e0: 199d3317 ldw r6,29900(r3) + 80090e4: 8008a9c0 call 8008a9c <__multadd> + 80090e8: 1025883a mov r18,r2 + 80090ec: 003fcc06 br 8009020 <__pow5mult+0x2c> + 80090f0: 01400044 movi r5,1 + 80090f4: 9809883a mov r4,r19 + 80090f8: 80089d40 call 80089d4 <_Balloc> + 80090fc: 1023883a mov r17,r2 + 8009100: 00809c44 movi r2,625 + 8009104: 88800515 stw r2,20(r17) + 8009108: 00800044 movi r2,1 + 800910c: 88800415 stw r2,16(r17) + 8009110: 9c401215 stw r17,72(r19) + 8009114: 88000015 stw zero,0(r17) + 8009118: 003fcb06 br 8009048 <__pow5mult+0x54> + +0800911c <__lshift>: + 800911c: defff904 addi sp,sp,-28 + 8009120: dcc00315 stw r19,12(sp) + 8009124: dc400115 stw r17,4(sp) + 8009128: 2cc00417 ldw r19,16(r5) + 800912c: 3023d17a srai r17,r6,5 + 8009130: 28800217 ldw r2,8(r5) + 8009134: dd400515 stw r21,20(sp) + 8009138: 8ce7883a add r19,r17,r19 + 800913c: dd000415 stw r20,16(sp) + 8009140: dc800215 stw r18,8(sp) + 8009144: dc000015 stw r16,0(sp) + 8009148: dfc00615 stw ra,24(sp) + 800914c: 9c000044 addi r16,r19,1 + 8009150: 2825883a mov r18,r5 + 8009154: 302b883a mov r21,r6 + 8009158: 2029883a mov r20,r4 + 800915c: 29400117 ldw r5,4(r5) + 8009160: 1400030e bge r2,r16,8009170 <__lshift+0x54> + 8009164: 1085883a add r2,r2,r2 + 8009168: 29400044 addi r5,r5,1 + 800916c: 143ffd16 blt r2,r16,8009164 <__lshift+0x48> + 8009170: a009883a mov r4,r20 + 8009174: 80089d40 call 80089d4 <_Balloc> + 8009178: 11000504 addi r4,r2,20 + 800917c: 0440090e bge zero,r17,80091a4 <__lshift+0x88> + 8009180: 8c400144 addi r17,r17,5 + 8009184: 882290ba slli r17,r17,2 + 8009188: 2007883a mov r3,r4 + 800918c: 144b883a add r5,r2,r17 + 8009190: 18c00104 addi r3,r3,4 + 8009194: 183fff15 stw zero,-4(r3) + 8009198: 28fffd1e bne r5,r3,8009190 <__lshift+0x74> + 800919c: 8c7ffb04 addi r17,r17,-20 + 80091a0: 2449883a add r4,r4,r17 + 80091a4: 92000417 ldw r8,16(r18) + 80091a8: 90c00504 addi r3,r18,20 + 80091ac: a98007cc andi r6,r21,31 + 80091b0: 401090ba slli r8,r8,2 + 80091b4: 1a11883a add r8,r3,r8 + 80091b8: 30002126 beq r6,zero,8009240 <__lshift+0x124> + 80091bc: 02400804 movi r9,32 + 80091c0: 4993c83a sub r9,r9,r6 + 80091c4: 000f883a mov r7,zero + 80091c8: 19400017 ldw r5,0(r3) + 80091cc: 21000104 addi r4,r4,4 + 80091d0: 18c00104 addi r3,r3,4 + 80091d4: 298a983a sll r5,r5,r6 + 80091d8: 29cab03a or r5,r5,r7 + 80091dc: 217fff15 stw r5,-4(r4) + 80091e0: 197fff17 ldw r5,-4(r3) + 80091e4: 2a4ed83a srl r7,r5,r9 + 80091e8: 1a3ff736 bltu r3,r8,80091c8 <__lshift+0xac> + 80091ec: 21c00015 stw r7,0(r4) + 80091f0: 38000126 beq r7,zero,80091f8 <__lshift+0xdc> + 80091f4: 8027883a mov r19,r16 + 80091f8: 14c00415 stw r19,16(r2) + 80091fc: 90000726 beq r18,zero,800921c <__lshift+0x100> + 8009200: 91000117 ldw r4,4(r18) + 8009204: a0c01317 ldw r3,76(r20) + 8009208: 200890ba slli r4,r4,2 + 800920c: 1907883a add r3,r3,r4 + 8009210: 19000017 ldw r4,0(r3) + 8009214: 91000015 stw r4,0(r18) + 8009218: 1c800015 stw r18,0(r3) + 800921c: dfc00617 ldw ra,24(sp) + 8009220: dd400517 ldw r21,20(sp) + 8009224: dd000417 ldw r20,16(sp) + 8009228: dcc00317 ldw r19,12(sp) + 800922c: dc800217 ldw r18,8(sp) + 8009230: dc400117 ldw r17,4(sp) + 8009234: dc000017 ldw r16,0(sp) + 8009238: dec00704 addi sp,sp,28 + 800923c: f800283a ret + 8009240: 18c00104 addi r3,r3,4 + 8009244: 197fff17 ldw r5,-4(r3) + 8009248: 21000104 addi r4,r4,4 + 800924c: 217fff15 stw r5,-4(r4) + 8009250: 1a3ffb36 bltu r3,r8,8009240 <__lshift+0x124> + 8009254: 003fe806 br 80091f8 <__lshift+0xdc> + +08009258 <__mcmp>: + 8009258: 20800417 ldw r2,16(r4) + 800925c: 28c00417 ldw r3,16(r5) + 8009260: 10c5c83a sub r2,r2,r3 + 8009264: 10000e1e bne r2,zero,80092a0 <__mcmp+0x48> + 8009268: 180c90ba slli r6,r3,2 + 800926c: 21000504 addi r4,r4,20 + 8009270: 29400504 addi r5,r5,20 + 8009274: 2187883a add r3,r4,r6 + 8009278: 298b883a add r5,r5,r6 + 800927c: 00000106 br 8009284 <__mcmp+0x2c> + 8009280: 20c0082e bgeu r4,r3,80092a4 <__mcmp+0x4c> + 8009284: 18ffff04 addi r3,r3,-4 + 8009288: 297fff04 addi r5,r5,-4 + 800928c: 19c00017 ldw r7,0(r3) + 8009290: 29800017 ldw r6,0(r5) + 8009294: 39bffa26 beq r7,r6,8009280 <__mcmp+0x28> + 8009298: 3980032e bgeu r7,r6,80092a8 <__mcmp+0x50> + 800929c: 00bfffc4 movi r2,-1 + 80092a0: f800283a ret + 80092a4: f800283a ret + 80092a8: 00800044 movi r2,1 + 80092ac: f800283a ret + +080092b0 <__mdiff>: + 80092b0: defffa04 addi sp,sp,-24 + 80092b4: dc800215 stw r18,8(sp) + 80092b8: 30c00417 ldw r3,16(r6) + 80092bc: 2c800417 ldw r18,16(r5) + 80092c0: dd000415 stw r20,16(sp) + 80092c4: dcc00315 stw r19,12(sp) + 80092c8: dc400115 stw r17,4(sp) + 80092cc: dc000015 stw r16,0(sp) + 80092d0: dfc00515 stw ra,20(sp) + 80092d4: 90e5c83a sub r18,r18,r3 + 80092d8: 2827883a mov r19,r5 + 80092dc: 3029883a mov r20,r6 + 80092e0: 2c000504 addi r16,r5,20 + 80092e4: 34400504 addi r17,r6,20 + 80092e8: 9000131e bne r18,zero,8009338 <__mdiff+0x88> + 80092ec: 180690ba slli r3,r3,2 + 80092f0: 80c5883a add r2,r16,r3 + 80092f4: 88c7883a add r3,r17,r3 + 80092f8: 00000106 br 8009300 <__mdiff+0x50> + 80092fc: 8080552e bgeu r16,r2,8009454 <__mdiff+0x1a4> + 8009300: 10bfff04 addi r2,r2,-4 + 8009304: 18ffff04 addi r3,r3,-4 + 8009308: 11c00017 ldw r7,0(r2) + 800930c: 19400017 ldw r5,0(r3) + 8009310: 397ffa26 beq r7,r5,80092fc <__mdiff+0x4c> + 8009314: 39400a2e bgeu r7,r5,8009340 <__mdiff+0x90> + 8009318: 8007883a mov r3,r16 + 800931c: 9805883a mov r2,r19 + 8009320: 8821883a mov r16,r17 + 8009324: a027883a mov r19,r20 + 8009328: 1823883a mov r17,r3 + 800932c: 1029883a mov r20,r2 + 8009330: 04800044 movi r18,1 + 8009334: 00000206 br 8009340 <__mdiff+0x90> + 8009338: 903ff716 blt r18,zero,8009318 <__mdiff+0x68> + 800933c: 0025883a mov r18,zero + 8009340: 99400117 ldw r5,4(r19) + 8009344: 80089d40 call 80089d4 <_Balloc> + 8009348: 9a400417 ldw r9,16(r19) + 800934c: a2c00417 ldw r11,16(r20) + 8009350: 12800504 addi r10,r2,20 + 8009354: 481090ba slli r8,r9,2 + 8009358: 581690ba slli r11,r11,2 + 800935c: 14800315 stw r18,12(r2) + 8009360: 8211883a add r8,r16,r8 + 8009364: 8ad7883a add r11,r17,r11 + 8009368: 0007883a mov r3,zero + 800936c: 00000106 br 8009374 <__mdiff+0xc4> + 8009370: 3815883a mov r10,r7 + 8009374: 81000017 ldw r4,0(r16) + 8009378: 89800017 ldw r6,0(r17) + 800937c: 51c00104 addi r7,r10,4 + 8009380: 217fffcc andi r5,r4,65535 + 8009384: 28cb883a add r5,r5,r3 + 8009388: 30ffffcc andi r3,r6,65535 + 800938c: 28cbc83a sub r5,r5,r3 + 8009390: 300cd43a srli r6,r6,16 + 8009394: 2006d43a srli r3,r4,16 + 8009398: 2809d43a srai r4,r5,16 + 800939c: 297fffcc andi r5,r5,65535 + 80093a0: 1987c83a sub r3,r3,r6 + 80093a4: 1907883a add r3,r3,r4 + 80093a8: 1808943a slli r4,r3,16 + 80093ac: 8c400104 addi r17,r17,4 + 80093b0: 84000104 addi r16,r16,4 + 80093b4: 214ab03a or r5,r4,r5 + 80093b8: 397fff15 stw r5,-4(r7) + 80093bc: 1807d43a srai r3,r3,16 + 80093c0: 8affeb36 bltu r17,r11,8009370 <__mdiff+0xc0> + 80093c4: 8200152e bgeu r16,r8,800941c <__mdiff+0x16c> + 80093c8: 3815883a mov r10,r7 + 80093cc: 800d883a mov r6,r16 + 80093d0: 31000017 ldw r4,0(r6) + 80093d4: 52800104 addi r10,r10,4 + 80093d8: 31800104 addi r6,r6,4 + 80093dc: 217fffcc andi r5,r4,65535 + 80093e0: 28cb883a add r5,r5,r3 + 80093e4: 2817d43a srai r11,r5,16 + 80093e8: 2006d43a srli r3,r4,16 + 80093ec: 293fffcc andi r4,r5,65535 + 80093f0: 1ac7883a add r3,r3,r11 + 80093f4: 180a943a slli r5,r3,16 + 80093f8: 1807d43a srai r3,r3,16 + 80093fc: 290ab03a or r5,r5,r4 + 8009400: 517fff15 stw r5,-4(r10) + 8009404: 323ff236 bltu r6,r8,80093d0 <__mdiff+0x120> + 8009408: 42bfffc4 addi r10,r8,-1 + 800940c: 5415c83a sub r10,r10,r16 + 8009410: 5014d0ba srli r10,r10,2 + 8009414: 501490ba slli r10,r10,2 + 8009418: 3a95883a add r10,r7,r10 + 800941c: 2800041e bne r5,zero,8009430 <__mdiff+0x180> + 8009420: 52bfff04 addi r10,r10,-4 + 8009424: 50c00017 ldw r3,0(r10) + 8009428: 4a7fffc4 addi r9,r9,-1 + 800942c: 183ffc26 beq r3,zero,8009420 <__mdiff+0x170> + 8009430: 12400415 stw r9,16(r2) + 8009434: dfc00517 ldw ra,20(sp) + 8009438: dd000417 ldw r20,16(sp) + 800943c: dcc00317 ldw r19,12(sp) + 8009440: dc800217 ldw r18,8(sp) + 8009444: dc400117 ldw r17,4(sp) + 8009448: dc000017 ldw r16,0(sp) + 800944c: dec00604 addi sp,sp,24 + 8009450: f800283a ret + 8009454: 000b883a mov r5,zero + 8009458: 80089d40 call 80089d4 <_Balloc> + 800945c: 00c00044 movi r3,1 + 8009460: 10c00415 stw r3,16(r2) + 8009464: 10000515 stw zero,20(r2) + 8009468: 003ff206 br 8009434 <__mdiff+0x184> + +0800946c <__ulp>: + 800946c: 295ffc2c andhi r5,r5,32752 + 8009470: 00ff3034 movhi r3,64704 + 8009474: 28c7883a add r3,r5,r3 + 8009478: 00c0020e bge zero,r3,8009484 <__ulp+0x18> + 800947c: 0005883a mov r2,zero + 8009480: f800283a ret + 8009484: 00c7c83a sub r3,zero,r3 + 8009488: 1807d53a srai r3,r3,20 + 800948c: 18800508 cmpgei r2,r3,20 + 8009490: 1000041e bne r2,zero,80094a4 <__ulp+0x38> + 8009494: 01400234 movhi r5,8 + 8009498: 28c7d83a sra r3,r5,r3 + 800949c: 0005883a mov r2,zero + 80094a0: f800283a ret + 80094a4: 193ffb04 addi r4,r3,-20 + 80094a8: 208007c8 cmpgei r2,r4,31 + 80094ac: 0007883a mov r3,zero + 80094b0: 1000031e bne r2,zero,80094c0 <__ulp+0x54> + 80094b4: 00a00034 movhi r2,32768 + 80094b8: 1104d83a srl r2,r2,r4 + 80094bc: f800283a ret + 80094c0: 00800044 movi r2,1 + 80094c4: f800283a ret + +080094c8 <__b2d>: + 80094c8: defffa04 addi sp,sp,-24 + 80094cc: dc000015 stw r16,0(sp) + 80094d0: 24000417 ldw r16,16(r4) + 80094d4: dc800215 stw r18,8(sp) + 80094d8: 24800504 addi r18,r4,20 + 80094dc: 802090ba slli r16,r16,2 + 80094e0: dc400115 stw r17,4(sp) + 80094e4: dd000415 stw r20,16(sp) + 80094e8: 9421883a add r16,r18,r16 + 80094ec: 847fff17 ldw r17,-4(r16) + 80094f0: dcc00315 stw r19,12(sp) + 80094f4: 2829883a mov r20,r5 + 80094f8: 8809883a mov r4,r17 + 80094fc: dfc00515 stw ra,20(sp) + 8009500: 8008cc00 call 8008cc0 <__hi0bits> + 8009504: 01000804 movi r4,32 + 8009508: 2087c83a sub r3,r4,r2 + 800950c: a0c00015 stw r3,0(r20) + 8009510: 10c002c8 cmpgei r3,r2,11 + 8009514: 84ffff04 addi r19,r16,-4 + 8009518: 18001f26 beq r3,zero,8009598 <__b2d+0xd0> + 800951c: 10fffd44 addi r3,r2,-11 + 8009520: 94c00e2e bgeu r18,r19,800955c <__b2d+0x94> + 8009524: 80bffe17 ldw r2,-8(r16) + 8009528: 18001226 beq r3,zero,8009574 <__b2d+0xac> + 800952c: 20c9c83a sub r4,r4,r3 + 8009530: 110cd83a srl r6,r2,r4 + 8009534: 88e2983a sll r17,r17,r3 + 8009538: 10c4983a sll r2,r2,r3 + 800953c: 817ffe04 addi r5,r16,-8 + 8009540: 8986b03a or r3,r17,r6 + 8009544: 18cffc34 orhi r3,r3,16368 + 8009548: 91400b2e bgeu r18,r5,8009578 <__b2d+0xb0> + 800954c: 817ffd17 ldw r5,-12(r16) + 8009550: 2908d83a srl r4,r5,r4 + 8009554: 1104b03a or r2,r2,r4 + 8009558: 00000706 br 8009578 <__b2d+0xb0> + 800955c: 18000426 beq r3,zero,8009570 <__b2d+0xa8> + 8009560: 88c6983a sll r3,r17,r3 + 8009564: 0005883a mov r2,zero + 8009568: 18cffc34 orhi r3,r3,16368 + 800956c: 00000206 br 8009578 <__b2d+0xb0> + 8009570: 0005883a mov r2,zero + 8009574: 88cffc34 orhi r3,r17,16368 + 8009578: dfc00517 ldw ra,20(sp) + 800957c: dd000417 ldw r20,16(sp) + 8009580: dcc00317 ldw r19,12(sp) + 8009584: dc800217 ldw r18,8(sp) + 8009588: dc400117 ldw r17,4(sp) + 800958c: dc000017 ldw r16,0(sp) + 8009590: dec00604 addi sp,sp,24 + 8009594: f800283a ret + 8009598: 014002c4 movi r5,11 + 800959c: 2889c83a sub r4,r5,r2 + 80095a0: 8906d83a srl r3,r17,r4 + 80095a4: 18cffc34 orhi r3,r3,16368 + 80095a8: 94c00536 bltu r18,r19,80095c0 <__b2d+0xf8> + 80095ac: 000b883a mov r5,zero + 80095b0: 10800544 addi r2,r2,21 + 80095b4: 8884983a sll r2,r17,r2 + 80095b8: 1144b03a or r2,r2,r5 + 80095bc: 003fee06 br 8009578 <__b2d+0xb0> + 80095c0: 817ffe17 ldw r5,-8(r16) + 80095c4: 290ad83a srl r5,r5,r4 + 80095c8: 003ff906 br 80095b0 <__b2d+0xe8> + +080095cc <__d2b>: + 80095cc: defff804 addi sp,sp,-32 + 80095d0: dc400315 stw r17,12(sp) + 80095d4: 3023883a mov r17,r6 + 80095d8: dd000615 stw r20,24(sp) + 80095dc: dc000215 stw r16,8(sp) + 80095e0: 2829883a mov r20,r5 + 80095e4: 8820d53a srli r16,r17,20 + 80095e8: 01400044 movi r5,1 + 80095ec: dcc00515 stw r19,20(sp) + 80095f0: dc800415 stw r18,16(sp) + 80095f4: dfc00715 stw ra,28(sp) + 80095f8: 3825883a mov r18,r7 + 80095fc: 80089d40 call 80089d4 <_Balloc> + 8009600: 01800434 movhi r6,16 + 8009604: 31bfffc4 addi r6,r6,-1 + 8009608: 8401ffcc andi r16,r16,2047 + 800960c: 1027883a mov r19,r2 + 8009610: 89a2703a and r17,r17,r6 + 8009614: 80000126 beq r16,zero,800961c <__d2b+0x50> + 8009618: 8c400434 orhi r17,r17,16 + 800961c: dc400115 stw r17,4(sp) + 8009620: a0002826 beq r20,zero,80096c4 <__d2b+0xf8> + 8009624: d809883a mov r4,sp + 8009628: dd000015 stw r20,0(sp) + 800962c: 8008d240 call 8008d24 <__lo0bits> + 8009630: d8c00117 ldw r3,4(sp) + 8009634: 1000171e bne r2,zero,8009694 <__d2b+0xc8> + 8009638: d9000017 ldw r4,0(sp) + 800963c: 98c00615 stw r3,24(r19) + 8009640: 99000515 stw r4,20(r19) + 8009644: 18001d1e bne r3,zero,80096bc <__d2b+0xf0> + 8009648: 04400044 movi r17,1 + 800964c: 9c400415 stw r17,16(r19) + 8009650: 80002526 beq r16,zero,80096e8 <__d2b+0x11c> + 8009654: 00c00d44 movi r3,53 + 8009658: 843ef344 addi r16,r16,-1075 + 800965c: 80a1883a add r16,r16,r2 + 8009660: 1885c83a sub r2,r3,r2 + 8009664: d8c00817 ldw r3,32(sp) + 8009668: 94000015 stw r16,0(r18) + 800966c: 18800015 stw r2,0(r3) + 8009670: 9805883a mov r2,r19 + 8009674: dfc00717 ldw ra,28(sp) + 8009678: dd000617 ldw r20,24(sp) + 800967c: dcc00517 ldw r19,20(sp) + 8009680: dc800417 ldw r18,16(sp) + 8009684: dc400317 ldw r17,12(sp) + 8009688: dc000217 ldw r16,8(sp) + 800968c: dec00804 addi sp,sp,32 + 8009690: f800283a ret + 8009694: 01000804 movi r4,32 + 8009698: 2089c83a sub r4,r4,r2 + 800969c: 1908983a sll r4,r3,r4 + 80096a0: d9400017 ldw r5,0(sp) + 80096a4: 1886d83a srl r3,r3,r2 + 80096a8: 2148b03a or r4,r4,r5 + 80096ac: 99000515 stw r4,20(r19) + 80096b0: d8c00115 stw r3,4(sp) + 80096b4: 98c00615 stw r3,24(r19) + 80096b8: 183fe326 beq r3,zero,8009648 <__d2b+0x7c> + 80096bc: 04400084 movi r17,2 + 80096c0: 003fe206 br 800964c <__d2b+0x80> + 80096c4: d9000104 addi r4,sp,4 + 80096c8: 8008d240 call 8008d24 <__lo0bits> + 80096cc: 00c00044 movi r3,1 + 80096d0: 98c00415 stw r3,16(r19) + 80096d4: d8c00117 ldw r3,4(sp) + 80096d8: 10800804 addi r2,r2,32 + 80096dc: 04400044 movi r17,1 + 80096e0: 98c00515 stw r3,20(r19) + 80096e4: 803fdb1e bne r16,zero,8009654 <__d2b+0x88> + 80096e8: 880690ba slli r3,r17,2 + 80096ec: 10bef384 addi r2,r2,-1074 + 80096f0: 8822917a slli r17,r17,5 + 80096f4: 98c7883a add r3,r19,r3 + 80096f8: 19000417 ldw r4,16(r3) + 80096fc: 90800015 stw r2,0(r18) + 8009700: 8008cc00 call 8008cc0 <__hi0bits> + 8009704: 88a3c83a sub r17,r17,r2 + 8009708: d8800817 ldw r2,32(sp) + 800970c: 14400015 stw r17,0(r2) + 8009710: 003fd706 br 8009670 <__d2b+0xa4> + +08009714 <__ratio>: + 8009714: defff904 addi sp,sp,-28 + 8009718: dc400315 stw r17,12(sp) + 800971c: 2823883a mov r17,r5 + 8009720: d80b883a mov r5,sp + 8009724: dfc00615 stw ra,24(sp) + 8009728: dcc00515 stw r19,20(sp) + 800972c: dc800415 stw r18,16(sp) + 8009730: 2027883a mov r19,r4 + 8009734: dc000215 stw r16,8(sp) + 8009738: 80094c80 call 80094c8 <__b2d> + 800973c: d9400104 addi r5,sp,4 + 8009740: 8809883a mov r4,r17 + 8009744: 1025883a mov r18,r2 + 8009748: 1821883a mov r16,r3 + 800974c: 80094c80 call 80094c8 <__b2d> + 8009750: 89400417 ldw r5,16(r17) + 8009754: 99000417 ldw r4,16(r19) + 8009758: d9800117 ldw r6,4(sp) + 800975c: 2149c83a sub r4,r4,r5 + 8009760: d9400017 ldw r5,0(sp) + 8009764: 2008917a slli r4,r4,5 + 8009768: 298bc83a sub r5,r5,r6 + 800976c: 2149883a add r4,r4,r5 + 8009770: 01000e0e bge zero,r4,80097ac <__ratio+0x98> + 8009774: 2008953a slli r4,r4,20 + 8009778: 2421883a add r16,r4,r16 + 800977c: 100d883a mov r6,r2 + 8009780: 180f883a mov r7,r3 + 8009784: 9009883a mov r4,r18 + 8009788: 800b883a mov r5,r16 + 800978c: 800da580 call 800da58 <__divdf3> + 8009790: dfc00617 ldw ra,24(sp) + 8009794: dcc00517 ldw r19,20(sp) + 8009798: dc800417 ldw r18,16(sp) + 800979c: dc400317 ldw r17,12(sp) + 80097a0: dc000217 ldw r16,8(sp) + 80097a4: dec00704 addi sp,sp,28 + 80097a8: f800283a ret + 80097ac: 017ffc34 movhi r5,65520 + 80097b0: 2149383a mul r4,r4,r5 + 80097b4: 20c7883a add r3,r4,r3 + 80097b8: 003ff006 br 800977c <__ratio+0x68> + +080097bc <_mprec_log10>: + 80097bc: defffe04 addi sp,sp,-8 + 80097c0: dc000015 stw r16,0(sp) + 80097c4: dfc00115 stw ra,4(sp) + 80097c8: 20800608 cmpgei r2,r4,24 + 80097cc: 2021883a mov r16,r4 + 80097d0: 10000d26 beq r2,zero,8009808 <_mprec_log10+0x4c> + 80097d4: 0005883a mov r2,zero + 80097d8: 00cffc34 movhi r3,16368 + 80097dc: 843fffc4 addi r16,r16,-1 + 80097e0: 000d883a mov r6,zero + 80097e4: 01d00934 movhi r7,16420 + 80097e8: 1009883a mov r4,r2 + 80097ec: 180b883a mov r5,r3 + 80097f0: 800e5600 call 800e560 <__muldf3> + 80097f4: 803ff91e bne r16,zero,80097dc <_mprec_log10+0x20> + 80097f8: dfc00117 ldw ra,4(sp) + 80097fc: dc000017 ldw r16,0(sp) + 8009800: dec00204 addi sp,sp,8 + 8009804: f800283a ret + 8009808: 202090fa slli r16,r4,3 + 800980c: 00820134 movhi r2,2052 + 8009810: 109d4b04 addi r2,r2,29996 + 8009814: 1421883a add r16,r2,r16 + 8009818: 80800017 ldw r2,0(r16) + 800981c: 80c00117 ldw r3,4(r16) + 8009820: dfc00117 ldw ra,4(sp) + 8009824: dc000017 ldw r16,0(sp) + 8009828: dec00204 addi sp,sp,8 + 800982c: f800283a ret + +08009830 <__copybits>: + 8009830: 29ffffc4 addi r7,r5,-1 + 8009834: 380fd17a srai r7,r7,5 + 8009838: 31400417 ldw r5,16(r6) + 800983c: 30800504 addi r2,r6,20 + 8009840: 39c00044 addi r7,r7,1 + 8009844: 280a90ba slli r5,r5,2 + 8009848: 380e90ba slli r7,r7,2 + 800984c: 114b883a add r5,r2,r5 + 8009850: 21cf883a add r7,r4,r7 + 8009854: 11400c2e bgeu r2,r5,8009888 <__copybits+0x58> + 8009858: 2007883a mov r3,r4 + 800985c: 10800104 addi r2,r2,4 + 8009860: 123fff17 ldw r8,-4(r2) + 8009864: 18c00104 addi r3,r3,4 + 8009868: 1a3fff15 stw r8,-4(r3) + 800986c: 117ffb36 bltu r2,r5,800985c <__copybits+0x2c> + 8009870: 2985c83a sub r2,r5,r6 + 8009874: 10bffac4 addi r2,r2,-21 + 8009878: 1004d0ba srli r2,r2,2 + 800987c: 10800044 addi r2,r2,1 + 8009880: 100490ba slli r2,r2,2 + 8009884: 2089883a add r4,r4,r2 + 8009888: 21c0032e bgeu r4,r7,8009898 <__copybits+0x68> + 800988c: 21000104 addi r4,r4,4 + 8009890: 203fff15 stw zero,-4(r4) + 8009894: 21fffd36 bltu r4,r7,800988c <__copybits+0x5c> + 8009898: f800283a ret + +0800989c <__any_on>: + 800989c: 20800417 ldw r2,16(r4) + 80098a0: 280dd17a srai r6,r5,5 + 80098a4: 21000504 addi r4,r4,20 + 80098a8: 11800c0e bge r2,r6,80098dc <__any_on+0x40> + 80098ac: 100690ba slli r3,r2,2 + 80098b0: 20c7883a add r3,r4,r3 + 80098b4: 20c0142e bgeu r4,r3,8009908 <__any_on+0x6c> + 80098b8: 18bfff17 ldw r2,-4(r3) + 80098bc: 18ffff04 addi r3,r3,-4 + 80098c0: 1000041e bne r2,zero,80098d4 <__any_on+0x38> + 80098c4: 20c00f2e bgeu r4,r3,8009904 <__any_on+0x68> + 80098c8: 18ffff04 addi r3,r3,-4 + 80098cc: 19400017 ldw r5,0(r3) + 80098d0: 283ffc26 beq r5,zero,80098c4 <__any_on+0x28> + 80098d4: 00800044 movi r2,1 + 80098d8: f800283a ret + 80098dc: 300690ba slli r3,r6,2 + 80098e0: 20c7883a add r3,r4,r3 + 80098e4: 30bff30e bge r6,r2,80098b4 <__any_on+0x18> + 80098e8: 294007cc andi r5,r5,31 + 80098ec: 283ff126 beq r5,zero,80098b4 <__any_on+0x18> + 80098f0: 19800017 ldw r6,0(r3) + 80098f4: 3144d83a srl r2,r6,r5 + 80098f8: 114a983a sll r5,r2,r5 + 80098fc: 317ff51e bne r6,r5,80098d4 <__any_on+0x38> + 8009900: 003fec06 br 80098b4 <__any_on+0x18> + 8009904: f800283a ret + 8009908: 0005883a mov r2,zero + 800990c: f800283a ret + +08009910 <_putc_r>: + 8009910: defffc04 addi sp,sp,-16 + 8009914: dc000215 stw r16,8(sp) + 8009918: dfc00315 stw ra,12(sp) + 800991c: 2021883a mov r16,r4 + 8009920: 20000226 beq r4,zero,800992c <_putc_r+0x1c> + 8009924: 20800e17 ldw r2,56(r4) + 8009928: 10000e26 beq r2,zero,8009964 <_putc_r+0x54> + 800992c: 30800217 ldw r2,8(r6) + 8009930: 10bfffc4 addi r2,r2,-1 + 8009934: 30800215 stw r2,8(r6) + 8009938: 10001316 blt r2,zero,8009988 <_putc_r+0x78> + 800993c: 30800017 ldw r2,0(r6) + 8009940: 11400005 stb r5,0(r2) + 8009944: 30800017 ldw r2,0(r6) + 8009948: 10c00044 addi r3,r2,1 + 800994c: 30c00015 stw r3,0(r6) + 8009950: 10800003 ldbu r2,0(r2) + 8009954: dfc00317 ldw ra,12(sp) + 8009958: dc000217 ldw r16,8(sp) + 800995c: dec00404 addi sp,sp,16 + 8009960: f800283a ret + 8009964: d9800115 stw r6,4(sp) + 8009968: d9400015 stw r5,0(sp) + 800996c: 80070600 call 8007060 <__sinit> + 8009970: d9800117 ldw r6,4(sp) + 8009974: d9400017 ldw r5,0(sp) + 8009978: 30800217 ldw r2,8(r6) + 800997c: 10bfffc4 addi r2,r2,-1 + 8009980: 30800215 stw r2,8(r6) + 8009984: 103fed0e bge r2,zero,800993c <_putc_r+0x2c> + 8009988: 30c00617 ldw r3,24(r6) + 800998c: 10c00e16 blt r2,r3,80099c8 <_putc_r+0xb8> + 8009990: 30800017 ldw r2,0(r6) + 8009994: 11400005 stb r5,0(r2) + 8009998: 30c00017 ldw r3,0(r6) + 800999c: 18800003 ldbu r2,0(r3) + 80099a0: 108002a0 cmpeqi r2,r2,10 + 80099a4: 1000071e bne r2,zero,80099c4 <_putc_r+0xb4> + 80099a8: 18800044 addi r2,r3,1 + 80099ac: 30800015 stw r2,0(r6) + 80099b0: 18800003 ldbu r2,0(r3) + 80099b4: dfc00317 ldw ra,12(sp) + 80099b8: dc000217 ldw r16,8(sp) + 80099bc: dec00404 addi sp,sp,16 + 80099c0: f800283a ret + 80099c4: 01400284 movi r5,10 + 80099c8: 8009883a mov r4,r16 + 80099cc: dfc00317 ldw ra,12(sp) + 80099d0: dc000217 ldw r16,8(sp) + 80099d4: dec00404 addi sp,sp,16 + 80099d8: 800b8141 jmpi 800b814 <__swbuf_r> + +080099dc : + 80099dc: defffc04 addi sp,sp,-16 + 80099e0: 00820174 movhi r2,2053 + 80099e4: dc000115 stw r16,4(sp) + 80099e8: 1432af17 ldw r16,-13636(r2) + 80099ec: dc400215 stw r17,8(sp) + 80099f0: dfc00315 stw ra,12(sp) + 80099f4: 2023883a mov r17,r4 + 80099f8: 80000226 beq r16,zero,8009a04 + 80099fc: 80800e17 ldw r2,56(r16) + 8009a00: 10000f26 beq r2,zero,8009a40 + 8009a04: 28800217 ldw r2,8(r5) + 8009a08: 10bfffc4 addi r2,r2,-1 + 8009a0c: 28800215 stw r2,8(r5) + 8009a10: 10001316 blt r2,zero,8009a60 + 8009a14: 28800017 ldw r2,0(r5) + 8009a18: 14400005 stb r17,0(r2) + 8009a1c: 28800017 ldw r2,0(r5) + 8009a20: 10c00044 addi r3,r2,1 + 8009a24: 28c00015 stw r3,0(r5) + 8009a28: 10800003 ldbu r2,0(r2) + 8009a2c: dfc00317 ldw ra,12(sp) + 8009a30: dc400217 ldw r17,8(sp) + 8009a34: dc000117 ldw r16,4(sp) + 8009a38: dec00404 addi sp,sp,16 + 8009a3c: f800283a ret + 8009a40: 8009883a mov r4,r16 + 8009a44: d9400015 stw r5,0(sp) + 8009a48: 80070600 call 8007060 <__sinit> + 8009a4c: d9400017 ldw r5,0(sp) + 8009a50: 28800217 ldw r2,8(r5) + 8009a54: 10bfffc4 addi r2,r2,-1 + 8009a58: 28800215 stw r2,8(r5) + 8009a5c: 103fed0e bge r2,zero,8009a14 + 8009a60: 28c00617 ldw r3,24(r5) + 8009a64: 10c00a16 blt r2,r3,8009a90 + 8009a68: 28800017 ldw r2,0(r5) + 8009a6c: 14400005 stb r17,0(r2) + 8009a70: 28c00017 ldw r3,0(r5) + 8009a74: 18800003 ldbu r2,0(r3) + 8009a78: 108002a0 cmpeqi r2,r2,10 + 8009a7c: 10000c1e bne r2,zero,8009ab0 + 8009a80: 18800044 addi r2,r3,1 + 8009a84: 28800015 stw r2,0(r5) + 8009a88: 18800003 ldbu r2,0(r3) + 8009a8c: 003fe706 br 8009a2c + 8009a90: 280d883a mov r6,r5 + 8009a94: 880b883a mov r5,r17 + 8009a98: 8009883a mov r4,r16 + 8009a9c: dfc00317 ldw ra,12(sp) + 8009aa0: dc400217 ldw r17,8(sp) + 8009aa4: dc000117 ldw r16,4(sp) + 8009aa8: dec00404 addi sp,sp,16 + 8009aac: 800b8141 jmpi 800b814 <__swbuf_r> + 8009ab0: 280d883a mov r6,r5 + 8009ab4: 01400284 movi r5,10 + 8009ab8: 003ff706 br 8009a98 + +08009abc <_realloc_r>: + 8009abc: defff504 addi sp,sp,-44 + 8009ac0: dcc00415 stw r19,16(sp) + 8009ac4: dfc00a15 stw ra,40(sp) + 8009ac8: df000915 stw fp,36(sp) + 8009acc: ddc00815 stw r23,32(sp) + 8009ad0: dd800715 stw r22,28(sp) + 8009ad4: dd400615 stw r21,24(sp) + 8009ad8: dd000515 stw r20,20(sp) + 8009adc: dc800315 stw r18,12(sp) + 8009ae0: dc400215 stw r17,8(sp) + 8009ae4: dc000115 stw r16,4(sp) + 8009ae8: 3027883a mov r19,r6 + 8009aec: 28008b26 beq r5,zero,8009d1c <_realloc_r+0x260> + 8009af0: 282d883a mov r22,r5 + 8009af4: 202b883a mov r21,r4 + 8009af8: 9c0002c4 addi r16,r19,11 + 8009afc: 800fe0c0 call 800fe0c <__malloc_lock> + 8009b00: 808005f0 cmpltui r2,r16,23 + 8009b04: 1000521e bne r2,zero,8009c50 <_realloc_r+0x194> + 8009b08: 017ffe04 movi r5,-8 + 8009b0c: 8160703a and r16,r16,r5 + 8009b10: 8007883a mov r3,r16 + 8009b14: 80005116 blt r16,zero,8009c5c <_realloc_r+0x1a0> + 8009b18: 84c05036 bltu r16,r19,8009c5c <_realloc_r+0x1a0> + 8009b1c: b0bfff17 ldw r2,-4(r22) + 8009b20: 017fff04 movi r5,-4 + 8009b24: b4bffe04 addi r18,r22,-8 + 8009b28: 1162703a and r17,r2,r5 + 8009b2c: 9469883a add r20,r18,r17 + 8009b30: 88c0390e bge r17,r3,8009c18 <_realloc_r+0x15c> + 8009b34: 07020174 movhi fp,2053 + 8009b38: e72fa904 addi fp,fp,-16732 + 8009b3c: e2000217 ldw r8,8(fp) + 8009b40: a1000117 ldw r4,4(r20) + 8009b44: 45008e26 beq r8,r20,8009d80 <_realloc_r+0x2c4> + 8009b48: 01bfff84 movi r6,-2 + 8009b4c: 218c703a and r6,r4,r6 + 8009b50: a18d883a add r6,r20,r6 + 8009b54: 31800117 ldw r6,4(r6) + 8009b58: 3180004c andi r6,r6,1 + 8009b5c: 30004f1e bne r6,zero,8009c9c <_realloc_r+0x1e0> + 8009b60: 2148703a and r4,r4,r5 + 8009b64: 890b883a add r5,r17,r4 + 8009b68: 28c0cb0e bge r5,r3,8009e98 <_realloc_r+0x3dc> + 8009b6c: 1080004c andi r2,r2,1 + 8009b70: 10004c1e bne r2,zero,8009ca4 <_realloc_r+0x1e8> + 8009b74: b1fffe17 ldw r7,-8(r22) + 8009b78: 00bfff04 movi r2,-4 + 8009b7c: 91cfc83a sub r7,r18,r7 + 8009b80: 39400117 ldw r5,4(r7) + 8009b84: 288a703a and r5,r5,r2 + 8009b88: a0000426 beq r20,zero,8009b9c <_realloc_r+0xe0> + 8009b8c: 896f883a add r23,r17,r5 + 8009b90: b92f883a add r23,r23,r4 + 8009b94: 4500cb26 beq r8,r20,8009ec4 <_realloc_r+0x408> + 8009b98: b8c0930e bge r23,r3,8009de8 <_realloc_r+0x32c> + 8009b9c: 38004126 beq r7,zero,8009ca4 <_realloc_r+0x1e8> + 8009ba0: 896f883a add r23,r17,r5 + 8009ba4: b8c03f16 blt r23,r3,8009ca4 <_realloc_r+0x1e8> + 8009ba8: 38c00217 ldw r3,8(r7) + 8009bac: 38800317 ldw r2,12(r7) + 8009bb0: 89bfff04 addi r6,r17,-4 + 8009bb4: 31000968 cmpgeui r4,r6,37 + 8009bb8: 18800315 stw r2,12(r3) + 8009bbc: 10c00215 stw r3,8(r2) + 8009bc0: 3de9883a add r20,r7,r23 + 8009bc4: 38c00204 addi r3,r7,8 + 8009bc8: 2000f81e bne r4,zero,8009fac <_realloc_r+0x4f0> + 8009bcc: 30800530 cmpltui r2,r6,20 + 8009bd0: b1000017 ldw r4,0(r22) + 8009bd4: 1000eb1e bne r2,zero,8009f84 <_realloc_r+0x4c8> + 8009bd8: 39000215 stw r4,8(r7) + 8009bdc: b1000117 ldw r4,4(r22) + 8009be0: 30800728 cmpgeui r2,r6,28 + 8009be4: 39000315 stw r4,12(r7) + 8009be8: 1001041e bne r2,zero,8009ffc <_realloc_r+0x540> + 8009bec: b1000217 ldw r4,8(r22) + 8009bf0: 38800404 addi r2,r7,16 + 8009bf4: b5800204 addi r22,r22,8 + 8009bf8: 11000015 stw r4,0(r2) + 8009bfc: b1000117 ldw r4,4(r22) + 8009c00: b823883a mov r17,r23 + 8009c04: 3825883a mov r18,r7 + 8009c08: 11000115 stw r4,4(r2) + 8009c0c: b1000217 ldw r4,8(r22) + 8009c10: 182d883a mov r22,r3 + 8009c14: 11000215 stw r4,8(r2) + 8009c18: 91800117 ldw r6,4(r18) + 8009c1c: 8c05c83a sub r2,r17,r16 + 8009c20: 10c00430 cmpltui r3,r2,16 + 8009c24: 3180004c andi r6,r6,1 + 8009c28: 18004926 beq r3,zero,8009d50 <_realloc_r+0x294> + 8009c2c: 898cb03a or r6,r17,r6 + 8009c30: 91800115 stw r6,4(r18) + 8009c34: a0800117 ldw r2,4(r20) + 8009c38: 10800054 ori r2,r2,1 + 8009c3c: a0800115 stw r2,4(r20) + 8009c40: a809883a mov r4,r21 + 8009c44: 800ff2c0 call 800ff2c <__malloc_unlock> + 8009c48: b027883a mov r19,r22 + 8009c4c: 00000606 br 8009c68 <_realloc_r+0x1ac> + 8009c50: 04000404 movi r16,16 + 8009c54: 00c00404 movi r3,16 + 8009c58: 84ffb02e bgeu r16,r19,8009b1c <_realloc_r+0x60> + 8009c5c: 00800304 movi r2,12 + 8009c60: a8800015 stw r2,0(r21) + 8009c64: 0027883a mov r19,zero + 8009c68: 9805883a mov r2,r19 + 8009c6c: dfc00a17 ldw ra,40(sp) + 8009c70: df000917 ldw fp,36(sp) + 8009c74: ddc00817 ldw r23,32(sp) + 8009c78: dd800717 ldw r22,28(sp) + 8009c7c: dd400617 ldw r21,24(sp) + 8009c80: dd000517 ldw r20,20(sp) + 8009c84: dcc00417 ldw r19,16(sp) + 8009c88: dc800317 ldw r18,12(sp) + 8009c8c: dc400217 ldw r17,8(sp) + 8009c90: dc000117 ldw r16,4(sp) + 8009c94: dec00b04 addi sp,sp,44 + 8009c98: f800283a ret + 8009c9c: 1080004c andi r2,r2,1 + 8009ca0: 10007826 beq r2,zero,8009e84 <_realloc_r+0x3c8> + 8009ca4: 980b883a mov r5,r19 + 8009ca8: a809883a mov r4,r21 + 8009cac: 8007ddc0 call 8007ddc <_malloc_r> + 8009cb0: 1027883a mov r19,r2 + 8009cb4: 10001626 beq r2,zero,8009d10 <_realloc_r+0x254> + 8009cb8: b0bfff17 ldw r2,-4(r22) + 8009cbc: 013fff84 movi r4,-2 + 8009cc0: 98fffe04 addi r3,r19,-8 + 8009cc4: 1104703a and r2,r2,r4 + 8009cc8: 9085883a add r2,r18,r2 + 8009ccc: 10c06726 beq r2,r3,8009e6c <_realloc_r+0x3b0> + 8009cd0: 89bfff04 addi r6,r17,-4 + 8009cd4: 30800968 cmpgeui r2,r6,37 + 8009cd8: 1000761e bne r2,zero,8009eb4 <_realloc_r+0x3f8> + 8009cdc: 30800530 cmpltui r2,r6,20 + 8009ce0: b1000017 ldw r4,0(r22) + 8009ce4: 10003726 beq r2,zero,8009dc4 <_realloc_r+0x308> + 8009ce8: 9805883a mov r2,r19 + 8009cec: b007883a mov r3,r22 + 8009cf0: 11000015 stw r4,0(r2) + 8009cf4: 19000117 ldw r4,4(r3) + 8009cf8: 11000115 stw r4,4(r2) + 8009cfc: 18c00217 ldw r3,8(r3) + 8009d00: 10c00215 stw r3,8(r2) + 8009d04: b00b883a mov r5,r22 + 8009d08: a809883a mov r4,r21 + 8009d0c: 80071c40 call 80071c4 <_free_r> + 8009d10: a809883a mov r4,r21 + 8009d14: 800ff2c0 call 800ff2c <__malloc_unlock> + 8009d18: 003fd306 br 8009c68 <_realloc_r+0x1ac> + 8009d1c: 300b883a mov r5,r6 + 8009d20: dfc00a17 ldw ra,40(sp) + 8009d24: df000917 ldw fp,36(sp) + 8009d28: ddc00817 ldw r23,32(sp) + 8009d2c: dd800717 ldw r22,28(sp) + 8009d30: dd400617 ldw r21,24(sp) + 8009d34: dd000517 ldw r20,20(sp) + 8009d38: dcc00417 ldw r19,16(sp) + 8009d3c: dc800317 ldw r18,12(sp) + 8009d40: dc400217 ldw r17,8(sp) + 8009d44: dc000117 ldw r16,4(sp) + 8009d48: dec00b04 addi sp,sp,44 + 8009d4c: 8007ddc1 jmpi 8007ddc <_malloc_r> + 8009d50: 340cb03a or r6,r6,r16 + 8009d54: 91800115 stw r6,4(r18) + 8009d58: 940b883a add r5,r18,r16 + 8009d5c: 10800054 ori r2,r2,1 + 8009d60: 28800115 stw r2,4(r5) + 8009d64: a0800117 ldw r2,4(r20) + 8009d68: 29400204 addi r5,r5,8 + 8009d6c: a809883a mov r4,r21 + 8009d70: 10800054 ori r2,r2,1 + 8009d74: a0800115 stw r2,4(r20) + 8009d78: 80071c40 call 80071c4 <_free_r> + 8009d7c: 003fb006 br 8009c40 <_realloc_r+0x184> + 8009d80: 2148703a and r4,r4,r5 + 8009d84: 890b883a add r5,r17,r4 + 8009d88: 81800404 addi r6,r16,16 + 8009d8c: 29bf7716 blt r5,r6,8009b6c <_realloc_r+0xb0> + 8009d90: 9425883a add r18,r18,r16 + 8009d94: 2c05c83a sub r2,r5,r16 + 8009d98: e4800215 stw r18,8(fp) + 8009d9c: 10800054 ori r2,r2,1 + 8009da0: 90800115 stw r2,4(r18) + 8009da4: b0bfff17 ldw r2,-4(r22) + 8009da8: a809883a mov r4,r21 + 8009dac: b027883a mov r19,r22 + 8009db0: 1080004c andi r2,r2,1 + 8009db4: 1420b03a or r16,r2,r16 + 8009db8: b43fff15 stw r16,-4(r22) + 8009dbc: 800ff2c0 call 800ff2c <__malloc_unlock> + 8009dc0: 003fa906 br 8009c68 <_realloc_r+0x1ac> + 8009dc4: 99000015 stw r4,0(r19) + 8009dc8: b0c00117 ldw r3,4(r22) + 8009dcc: 30800728 cmpgeui r2,r6,28 + 8009dd0: 98c00115 stw r3,4(r19) + 8009dd4: 1000611e bne r2,zero,8009f5c <_realloc_r+0x4a0> + 8009dd8: b0c00204 addi r3,r22,8 + 8009ddc: 98800204 addi r2,r19,8 + 8009de0: b1000217 ldw r4,8(r22) + 8009de4: 003fc206 br 8009cf0 <_realloc_r+0x234> + 8009de8: a0800317 ldw r2,12(r20) + 8009dec: a0c00217 ldw r3,8(r20) + 8009df0: 89bfff04 addi r6,r17,-4 + 8009df4: 31000968 cmpgeui r4,r6,37 + 8009df8: 18800315 stw r2,12(r3) + 8009dfc: 10c00215 stw r3,8(r2) + 8009e00: 38c00217 ldw r3,8(r7) + 8009e04: 38800317 ldw r2,12(r7) + 8009e08: 3a000204 addi r8,r7,8 + 8009e0c: 3de9883a add r20,r7,r23 + 8009e10: 18800315 stw r2,12(r3) + 8009e14: 10c00215 stw r3,8(r2) + 8009e18: 20006f1e bne r4,zero,8009fd8 <_realloc_r+0x51c> + 8009e1c: 30800530 cmpltui r2,r6,20 + 8009e20: b0c00017 ldw r3,0(r22) + 8009e24: 10006a1e bne r2,zero,8009fd0 <_realloc_r+0x514> + 8009e28: 38c00215 stw r3,8(r7) + 8009e2c: b0c00117 ldw r3,4(r22) + 8009e30: 30800728 cmpgeui r2,r6,28 + 8009e34: 38c00315 stw r3,12(r7) + 8009e38: 10007a1e bne r2,zero,800a024 <_realloc_r+0x568> + 8009e3c: b0c00217 ldw r3,8(r22) + 8009e40: 38800404 addi r2,r7,16 + 8009e44: b5800204 addi r22,r22,8 + 8009e48: 10c00015 stw r3,0(r2) + 8009e4c: b0c00117 ldw r3,4(r22) + 8009e50: b823883a mov r17,r23 + 8009e54: 3825883a mov r18,r7 + 8009e58: 10c00115 stw r3,4(r2) + 8009e5c: b0c00217 ldw r3,8(r22) + 8009e60: 402d883a mov r22,r8 + 8009e64: 10c00215 stw r3,8(r2) + 8009e68: 003f6b06 br 8009c18 <_realloc_r+0x15c> + 8009e6c: 98bfff17 ldw r2,-4(r19) + 8009e70: 00ffff04 movi r3,-4 + 8009e74: 10c4703a and r2,r2,r3 + 8009e78: 88a3883a add r17,r17,r2 + 8009e7c: 9469883a add r20,r18,r17 + 8009e80: 003f6506 br 8009c18 <_realloc_r+0x15c> + 8009e84: b1fffe17 ldw r7,-8(r22) + 8009e88: 91cfc83a sub r7,r18,r7 + 8009e8c: 39000117 ldw r4,4(r7) + 8009e90: 214a703a and r5,r4,r5 + 8009e94: 003f4106 br 8009b9c <_realloc_r+0xe0> + 8009e98: a0800317 ldw r2,12(r20) + 8009e9c: a0c00217 ldw r3,8(r20) + 8009ea0: 2823883a mov r17,r5 + 8009ea4: 9169883a add r20,r18,r5 + 8009ea8: 18800315 stw r2,12(r3) + 8009eac: 10c00215 stw r3,8(r2) + 8009eb0: 003f5906 br 8009c18 <_realloc_r+0x15c> + 8009eb4: b00b883a mov r5,r22 + 8009eb8: 9809883a mov r4,r19 + 8009ebc: 80087b80 call 80087b8 + 8009ec0: 003f9006 br 8009d04 <_realloc_r+0x248> + 8009ec4: 80800404 addi r2,r16,16 + 8009ec8: b8bf3416 blt r23,r2,8009b9c <_realloc_r+0xe0> + 8009ecc: 38800317 ldw r2,12(r7) + 8009ed0: 38c00217 ldw r3,8(r7) + 8009ed4: 89bfff04 addi r6,r17,-4 + 8009ed8: 31000968 cmpgeui r4,r6,37 + 8009edc: 18800315 stw r2,12(r3) + 8009ee0: 10c00215 stw r3,8(r2) + 8009ee4: 3cc00204 addi r19,r7,8 + 8009ee8: 20005a1e bne r4,zero,800a054 <_realloc_r+0x598> + 8009eec: 30800530 cmpltui r2,r6,20 + 8009ef0: b0c00017 ldw r3,0(r22) + 8009ef4: 1000551e bne r2,zero,800a04c <_realloc_r+0x590> + 8009ef8: 38c00215 stw r3,8(r7) + 8009efc: b0c00117 ldw r3,4(r22) + 8009f00: 30800728 cmpgeui r2,r6,28 + 8009f04: 38c00315 stw r3,12(r7) + 8009f08: 1000661e bne r2,zero,800a0a4 <_realloc_r+0x5e8> + 8009f0c: b0c00217 ldw r3,8(r22) + 8009f10: 38800404 addi r2,r7,16 + 8009f14: b5800204 addi r22,r22,8 + 8009f18: 10c00015 stw r3,0(r2) + 8009f1c: b0c00117 ldw r3,4(r22) + 8009f20: 10c00115 stw r3,4(r2) + 8009f24: b0c00217 ldw r3,8(r22) + 8009f28: 10c00215 stw r3,8(r2) + 8009f2c: 3c07883a add r3,r7,r16 + 8009f30: bc05c83a sub r2,r23,r16 + 8009f34: e0c00215 stw r3,8(fp) + 8009f38: 10800054 ori r2,r2,1 + 8009f3c: 18800115 stw r2,4(r3) + 8009f40: 38800117 ldw r2,4(r7) + 8009f44: a809883a mov r4,r21 + 8009f48: 1080004c andi r2,r2,1 + 8009f4c: 1420b03a or r16,r2,r16 + 8009f50: 3c000115 stw r16,4(r7) + 8009f54: 800ff2c0 call 800ff2c <__malloc_unlock> + 8009f58: 003f4306 br 8009c68 <_realloc_r+0x1ac> + 8009f5c: b0800217 ldw r2,8(r22) + 8009f60: 31800920 cmpeqi r6,r6,36 + 8009f64: 98800215 stw r2,8(r19) + 8009f68: b0800317 ldw r2,12(r22) + 8009f6c: 98800315 stw r2,12(r19) + 8009f70: 3000061e bne r6,zero,8009f8c <_realloc_r+0x4d0> + 8009f74: b0c00404 addi r3,r22,16 + 8009f78: 98800404 addi r2,r19,16 + 8009f7c: b1000417 ldw r4,16(r22) + 8009f80: 003f5b06 br 8009cf0 <_realloc_r+0x234> + 8009f84: 1805883a mov r2,r3 + 8009f88: 003f1b06 br 8009bf8 <_realloc_r+0x13c> + 8009f8c: b1000417 ldw r4,16(r22) + 8009f90: b0c00604 addi r3,r22,24 + 8009f94: 98800604 addi r2,r19,24 + 8009f98: 99000415 stw r4,16(r19) + 8009f9c: b1000517 ldw r4,20(r22) + 8009fa0: 99000515 stw r4,20(r19) + 8009fa4: b1000617 ldw r4,24(r22) + 8009fa8: 003f5106 br 8009cf0 <_realloc_r+0x234> + 8009fac: b00b883a mov r5,r22 + 8009fb0: 1809883a mov r4,r3 + 8009fb4: d9c00015 stw r7,0(sp) + 8009fb8: 80087b80 call 80087b8 + 8009fbc: d9c00017 ldw r7,0(sp) + 8009fc0: 102d883a mov r22,r2 + 8009fc4: b823883a mov r17,r23 + 8009fc8: 3825883a mov r18,r7 + 8009fcc: 003f1206 br 8009c18 <_realloc_r+0x15c> + 8009fd0: 4005883a mov r2,r8 + 8009fd4: 003f9c06 br 8009e48 <_realloc_r+0x38c> + 8009fd8: b00b883a mov r5,r22 + 8009fdc: 4009883a mov r4,r8 + 8009fe0: d9c00015 stw r7,0(sp) + 8009fe4: 80087b80 call 80087b8 + 8009fe8: d9c00017 ldw r7,0(sp) + 8009fec: 102d883a mov r22,r2 + 8009ff0: b823883a mov r17,r23 + 8009ff4: 3825883a mov r18,r7 + 8009ff8: 003f0706 br 8009c18 <_realloc_r+0x15c> + 8009ffc: b0800217 ldw r2,8(r22) + 800a000: 31800920 cmpeqi r6,r6,36 + 800a004: 38800415 stw r2,16(r7) + 800a008: b0800317 ldw r2,12(r22) + 800a00c: 38800515 stw r2,20(r7) + 800a010: b1000417 ldw r4,16(r22) + 800a014: 3000151e bne r6,zero,800a06c <_realloc_r+0x5b0> + 800a018: 38800604 addi r2,r7,24 + 800a01c: b5800404 addi r22,r22,16 + 800a020: 003ef506 br 8009bf8 <_realloc_r+0x13c> + 800a024: b0800217 ldw r2,8(r22) + 800a028: 31800920 cmpeqi r6,r6,36 + 800a02c: 38800415 stw r2,16(r7) + 800a030: b0800317 ldw r2,12(r22) + 800a034: 38800515 stw r2,20(r7) + 800a038: b0c00417 ldw r3,16(r22) + 800a03c: 3000121e bne r6,zero,800a088 <_realloc_r+0x5cc> + 800a040: 38800604 addi r2,r7,24 + 800a044: b5800404 addi r22,r22,16 + 800a048: 003f7f06 br 8009e48 <_realloc_r+0x38c> + 800a04c: 9805883a mov r2,r19 + 800a050: 003fb106 br 8009f18 <_realloc_r+0x45c> + 800a054: b00b883a mov r5,r22 + 800a058: 9809883a mov r4,r19 + 800a05c: d9c00015 stw r7,0(sp) + 800a060: 80087b80 call 80087b8 + 800a064: d9c00017 ldw r7,0(sp) + 800a068: 003fb006 br 8009f2c <_realloc_r+0x470> + 800a06c: b5800604 addi r22,r22,24 + 800a070: 39000615 stw r4,24(r7) + 800a074: b13fff17 ldw r4,-4(r22) + 800a078: 38800804 addi r2,r7,32 + 800a07c: 39000715 stw r4,28(r7) + 800a080: b1000017 ldw r4,0(r22) + 800a084: 003edc06 br 8009bf8 <_realloc_r+0x13c> + 800a088: b5800604 addi r22,r22,24 + 800a08c: 38c00615 stw r3,24(r7) + 800a090: b0ffff17 ldw r3,-4(r22) + 800a094: 38800804 addi r2,r7,32 + 800a098: 38c00715 stw r3,28(r7) + 800a09c: b0c00017 ldw r3,0(r22) + 800a0a0: 003f6906 br 8009e48 <_realloc_r+0x38c> + 800a0a4: b0800217 ldw r2,8(r22) + 800a0a8: 31800920 cmpeqi r6,r6,36 + 800a0ac: 38800415 stw r2,16(r7) + 800a0b0: b0800317 ldw r2,12(r22) + 800a0b4: 38800515 stw r2,20(r7) + 800a0b8: b0c00417 ldw r3,16(r22) + 800a0bc: 3000031e bne r6,zero,800a0cc <_realloc_r+0x610> + 800a0c0: 38800604 addi r2,r7,24 + 800a0c4: b5800404 addi r22,r22,16 + 800a0c8: 003f9306 br 8009f18 <_realloc_r+0x45c> + 800a0cc: b5800604 addi r22,r22,24 + 800a0d0: 38c00615 stw r3,24(r7) + 800a0d4: b0ffff17 ldw r3,-4(r22) + 800a0d8: 38800804 addi r2,r7,32 + 800a0dc: 38c00715 stw r3,28(r7) + 800a0e0: b0c00017 ldw r3,0(r22) + 800a0e4: 003f8c06 br 8009f18 <_realloc_r+0x45c> + +0800a0e8 <__srget_r>: + 800a0e8: defffd04 addi sp,sp,-12 + 800a0ec: dc400115 stw r17,4(sp) + 800a0f0: dc000015 stw r16,0(sp) + 800a0f4: dfc00215 stw ra,8(sp) + 800a0f8: 2023883a mov r17,r4 + 800a0fc: 2821883a mov r16,r5 + 800a100: 20000226 beq r4,zero,800a10c <__srget_r+0x24> + 800a104: 20800e17 ldw r2,56(r4) + 800a108: 10001026 beq r2,zero,800a14c <__srget_r+0x64> + 800a10c: 800b883a mov r5,r16 + 800a110: 8809883a mov r4,r17 + 800a114: 800c0580 call 800c058 <__srefill_r> + 800a118: 10000e1e bne r2,zero,800a154 <__srget_r+0x6c> + 800a11c: 80c00017 ldw r3,0(r16) + 800a120: 80800117 ldw r2,4(r16) + 800a124: 19000044 addi r4,r3,1 + 800a128: 10bfffc4 addi r2,r2,-1 + 800a12c: 80800115 stw r2,4(r16) + 800a130: 81000015 stw r4,0(r16) + 800a134: 18800003 ldbu r2,0(r3) + 800a138: dfc00217 ldw ra,8(sp) + 800a13c: dc400117 ldw r17,4(sp) + 800a140: dc000017 ldw r16,0(sp) + 800a144: dec00304 addi sp,sp,12 + 800a148: f800283a ret + 800a14c: 80070600 call 8007060 <__sinit> + 800a150: 003fee06 br 800a10c <__srget_r+0x24> + 800a154: 00bfffc4 movi r2,-1 + 800a158: 003ff706 br 800a138 <__srget_r+0x50> + +0800a15c <__srget>: + 800a15c: 00820174 movhi r2,2053 + 800a160: 200b883a mov r5,r4 + 800a164: 1132af17 ldw r4,-13636(r2) + 800a168: 800a0e81 jmpi 800a0e8 <__srget_r> + +0800a16c <_sbrk_r>: + 800a16c: defffe04 addi sp,sp,-8 + 800a170: dc000015 stw r16,0(sp) + 800a174: 00820174 movhi r2,2053 + 800a178: 2021883a mov r16,r4 + 800a17c: 2809883a mov r4,r5 + 800a180: dfc00115 stw ra,4(sp) + 800a184: 1032f015 stw zero,-13376(r2) + 800a188: 800fc380 call 800fc38 + 800a18c: 10ffffd8 cmpnei r3,r2,-1 + 800a190: 18000426 beq r3,zero,800a1a4 <_sbrk_r+0x38> + 800a194: dfc00117 ldw ra,4(sp) + 800a198: dc000017 ldw r16,0(sp) + 800a19c: dec00204 addi sp,sp,8 + 800a1a0: f800283a ret + 800a1a4: 00c20174 movhi r3,2053 + 800a1a8: 18f2f017 ldw r3,-13376(r3) + 800a1ac: 183ff926 beq r3,zero,800a194 <_sbrk_r+0x28> + 800a1b0: 80c00015 stw r3,0(r16) + 800a1b4: dfc00117 ldw ra,4(sp) + 800a1b8: dc000017 ldw r16,0(sp) + 800a1bc: dec00204 addi sp,sp,8 + 800a1c0: f800283a ret + +0800a1c4 <__sread>: + 800a1c4: defffe04 addi sp,sp,-8 + 800a1c8: dc000015 stw r16,0(sp) + 800a1cc: 2821883a mov r16,r5 + 800a1d0: 2940038f ldh r5,14(r5) + 800a1d4: dfc00115 stw ra,4(sp) + 800a1d8: 800bfd80 call 800bfd8 <_read_r> + 800a1dc: 10000716 blt r2,zero,800a1fc <__sread+0x38> + 800a1e0: 80c01417 ldw r3,80(r16) + 800a1e4: 1887883a add r3,r3,r2 + 800a1e8: 80c01415 stw r3,80(r16) + 800a1ec: dfc00117 ldw ra,4(sp) + 800a1f0: dc000017 ldw r16,0(sp) + 800a1f4: dec00204 addi sp,sp,8 + 800a1f8: f800283a ret + 800a1fc: 80c0030b ldhu r3,12(r16) + 800a200: 18fbffcc andi r3,r3,61439 + 800a204: 80c0030d sth r3,12(r16) + 800a208: dfc00117 ldw ra,4(sp) + 800a20c: dc000017 ldw r16,0(sp) + 800a210: dec00204 addi sp,sp,8 + 800a214: f800283a ret + +0800a218 <__seofread>: + 800a218: 0005883a mov r2,zero + 800a21c: f800283a ret + +0800a220 <__swrite>: + 800a220: 2880030b ldhu r2,12(r5) + 800a224: defffb04 addi sp,sp,-20 + 800a228: dcc00315 stw r19,12(sp) + 800a22c: dc800215 stw r18,8(sp) + 800a230: dc400115 stw r17,4(sp) + 800a234: dc000015 stw r16,0(sp) + 800a238: dfc00415 stw ra,16(sp) + 800a23c: 10c0400c andi r3,r2,256 + 800a240: 2821883a mov r16,r5 + 800a244: 2023883a mov r17,r4 + 800a248: 3025883a mov r18,r6 + 800a24c: 3827883a mov r19,r7 + 800a250: 2940038f ldh r5,14(r5) + 800a254: 18000c1e bne r3,zero,800a288 <__swrite+0x68> + 800a258: 10bbffcc andi r2,r2,61439 + 800a25c: 980f883a mov r7,r19 + 800a260: 900d883a mov r6,r18 + 800a264: 8809883a mov r4,r17 + 800a268: 8080030d sth r2,12(r16) + 800a26c: dfc00417 ldw ra,16(sp) + 800a270: dcc00317 ldw r19,12(sp) + 800a274: dc800217 ldw r18,8(sp) + 800a278: dc400117 ldw r17,4(sp) + 800a27c: dc000017 ldw r16,0(sp) + 800a280: dec00504 addi sp,sp,20 + 800a284: 800b9701 jmpi 800b970 <_write_r> + 800a288: 01c00084 movi r7,2 + 800a28c: 000d883a mov r6,zero + 800a290: 800bf240 call 800bf24 <_lseek_r> + 800a294: 8080030b ldhu r2,12(r16) + 800a298: 8140038f ldh r5,14(r16) + 800a29c: 003fee06 br 800a258 <__swrite+0x38> + +0800a2a0 <__sseek>: + 800a2a0: defffe04 addi sp,sp,-8 + 800a2a4: dc000015 stw r16,0(sp) + 800a2a8: 2821883a mov r16,r5 + 800a2ac: 2940038f ldh r5,14(r5) + 800a2b0: dfc00115 stw ra,4(sp) + 800a2b4: 800bf240 call 800bf24 <_lseek_r> + 800a2b8: 10ffffd8 cmpnei r3,r2,-1 + 800a2bc: 18000826 beq r3,zero,800a2e0 <__sseek+0x40> + 800a2c0: 80c0030b ldhu r3,12(r16) + 800a2c4: 80801415 stw r2,80(r16) + 800a2c8: 18c40014 ori r3,r3,4096 + 800a2cc: 80c0030d sth r3,12(r16) + 800a2d0: dfc00117 ldw ra,4(sp) + 800a2d4: dc000017 ldw r16,0(sp) + 800a2d8: dec00204 addi sp,sp,8 + 800a2dc: f800283a ret + 800a2e0: 80c0030b ldhu r3,12(r16) + 800a2e4: 18fbffcc andi r3,r3,61439 + 800a2e8: 80c0030d sth r3,12(r16) + 800a2ec: dfc00117 ldw ra,4(sp) + 800a2f0: dc000017 ldw r16,0(sp) + 800a2f4: dec00204 addi sp,sp,8 + 800a2f8: f800283a ret + +0800a2fc <__sclose>: + 800a2fc: 2940038f ldh r5,14(r5) + 800a300: 800b9d41 jmpi 800b9d4 <_close_r> + +0800a304 <__sprint_r.part.0>: + 800a304: 28801917 ldw r2,100(r5) + 800a308: defff604 addi sp,sp,-40 + 800a30c: dd000415 stw r20,16(sp) + 800a310: dfc00915 stw ra,36(sp) + 800a314: df000815 stw fp,32(sp) + 800a318: ddc00715 stw r23,28(sp) + 800a31c: dd800615 stw r22,24(sp) + 800a320: dd400515 stw r21,20(sp) + 800a324: dcc00315 stw r19,12(sp) + 800a328: dc800215 stw r18,8(sp) + 800a32c: dc400115 stw r17,4(sp) + 800a330: dc000015 stw r16,0(sp) + 800a334: 1088000c andi r2,r2,8192 + 800a338: 3029883a mov r20,r6 + 800a33c: 10002c26 beq r2,zero,800a3f0 <__sprint_r.part.0+0xec> + 800a340: 30800217 ldw r2,8(r6) + 800a344: 2823883a mov r17,r5 + 800a348: 2027883a mov r19,r4 + 800a34c: 35400017 ldw r21,0(r6) + 800a350: 05ffff04 movi r23,-4 + 800a354: 10002426 beq r2,zero,800a3e8 <__sprint_r.part.0+0xe4> + 800a358: ad800117 ldw r22,4(r21) + 800a35c: ac000017 ldw r16,0(r21) + 800a360: b024d0ba srli r18,r22,2 + 800a364: 90001b26 beq r18,zero,800a3d4 <__sprint_r.part.0+0xd0> + 800a368: 0039883a mov fp,zero + 800a36c: 00000206 br 800a378 <__sprint_r.part.0+0x74> + 800a370: 84000104 addi r16,r16,4 + 800a374: 97001626 beq r18,fp,800a3d0 <__sprint_r.part.0+0xcc> + 800a378: 81400017 ldw r5,0(r16) + 800a37c: 880d883a mov r6,r17 + 800a380: 9809883a mov r4,r19 + 800a384: 800bd3c0 call 800bd3c <_fputwc_r> + 800a388: 10bfffe0 cmpeqi r2,r2,-1 + 800a38c: e7000044 addi fp,fp,1 + 800a390: 103ff726 beq r2,zero,800a370 <__sprint_r.part.0+0x6c> + 800a394: 00bfffc4 movi r2,-1 + 800a398: a0000215 stw zero,8(r20) + 800a39c: a0000115 stw zero,4(r20) + 800a3a0: dfc00917 ldw ra,36(sp) + 800a3a4: df000817 ldw fp,32(sp) + 800a3a8: ddc00717 ldw r23,28(sp) + 800a3ac: dd800617 ldw r22,24(sp) + 800a3b0: dd400517 ldw r21,20(sp) + 800a3b4: dd000417 ldw r20,16(sp) + 800a3b8: dcc00317 ldw r19,12(sp) + 800a3bc: dc800217 ldw r18,8(sp) + 800a3c0: dc400117 ldw r17,4(sp) + 800a3c4: dc000017 ldw r16,0(sp) + 800a3c8: dec00a04 addi sp,sp,40 + 800a3cc: f800283a ret + 800a3d0: a0800217 ldw r2,8(r20) + 800a3d4: b5ec703a and r22,r22,r23 + 800a3d8: 1585c83a sub r2,r2,r22 + 800a3dc: a0800215 stw r2,8(r20) + 800a3e0: ad400204 addi r21,r21,8 + 800a3e4: 103fdc1e bne r2,zero,800a358 <__sprint_r.part.0+0x54> + 800a3e8: 0005883a mov r2,zero + 800a3ec: 003fea06 br 800a398 <__sprint_r.part.0+0x94> + 800a3f0: 80074c00 call 80074c0 <__sfvwrite_r> + 800a3f4: 003fe806 br 800a398 <__sprint_r.part.0+0x94> + +0800a3f8 <__sprint_r>: + 800a3f8: 30c00217 ldw r3,8(r6) + 800a3fc: 18000126 beq r3,zero,800a404 <__sprint_r+0xc> + 800a400: 800a3041 jmpi 800a304 <__sprint_r.part.0> + 800a404: 30000115 stw zero,4(r6) + 800a408: 0005883a mov r2,zero + 800a40c: f800283a ret + +0800a410 <___vfiprintf_internal_r>: + 800a410: deffd004 addi sp,sp,-192 + 800a414: df002e15 stw fp,184(sp) + 800a418: dcc02915 stw r19,164(sp) + 800a41c: dc802815 stw r18,160(sp) + 800a420: dfc02f15 stw ra,188(sp) + 800a424: ddc02d15 stw r23,180(sp) + 800a428: dd802c15 stw r22,176(sp) + 800a42c: dd402b15 stw r21,172(sp) + 800a430: dd002a15 stw r20,168(sp) + 800a434: dc402715 stw r17,156(sp) + 800a438: dc002615 stw r16,152(sp) + 800a43c: d9c00315 stw r7,12(sp) + 800a440: 2027883a mov r19,r4 + 800a444: 2825883a mov r18,r5 + 800a448: 3039883a mov fp,r6 + 800a44c: 20000226 beq r4,zero,800a458 <___vfiprintf_internal_r+0x48> + 800a450: 20800e17 ldw r2,56(r4) + 800a454: 1002b626 beq r2,zero,800af30 <___vfiprintf_internal_r+0xb20> + 800a458: 9080030b ldhu r2,12(r18) + 800a45c: 10c8000c andi r3,r2,8192 + 800a460: 1800061e bne r3,zero,800a47c <___vfiprintf_internal_r+0x6c> + 800a464: 90c01917 ldw r3,100(r18) + 800a468: 0137ffc4 movi r4,-8193 + 800a46c: 10880014 ori r2,r2,8192 + 800a470: 1906703a and r3,r3,r4 + 800a474: 9080030d sth r2,12(r18) + 800a478: 90c01915 stw r3,100(r18) + 800a47c: 10c0020c andi r3,r2,8 + 800a480: 18009426 beq r3,zero,800a6d4 <___vfiprintf_internal_r+0x2c4> + 800a484: 90c00417 ldw r3,16(r18) + 800a488: 18009226 beq r3,zero,800a6d4 <___vfiprintf_internal_r+0x2c4> + 800a48c: 1080068c andi r2,r2,26 + 800a490: 10800298 cmpnei r2,r2,10 + 800a494: 10009726 beq r2,zero,800a6f4 <___vfiprintf_internal_r+0x2e4> + 800a498: dc401604 addi r17,sp,88 + 800a49c: dc400915 stw r17,36(sp) + 800a4a0: d8000b15 stw zero,44(sp) + 800a4a4: d8000a15 stw zero,40(sp) + 800a4a8: 8811883a mov r8,r17 + 800a4ac: d8000415 stw zero,16(sp) + 800a4b0: d8000015 stw zero,0(sp) + 800a4b4: e0800007 ldb r2,0(fp) + 800a4b8: 1000a226 beq r2,zero,800a744 <___vfiprintf_internal_r+0x334> + 800a4bc: 10800960 cmpeqi r2,r2,37 + 800a4c0: 1003e71e bne r2,zero,800b460 <___vfiprintf_internal_r+0x1050> + 800a4c4: e021883a mov r16,fp + 800a4c8: 00000206 br 800a4d4 <___vfiprintf_internal_r+0xc4> + 800a4cc: 18009226 beq r3,zero,800a718 <___vfiprintf_internal_r+0x308> + 800a4d0: a021883a mov r16,r20 + 800a4d4: 80800047 ldb r2,1(r16) + 800a4d8: 85000044 addi r20,r16,1 + 800a4dc: 10c00958 cmpnei r3,r2,37 + 800a4e0: 103ffa1e bne r2,zero,800a4cc <___vfiprintf_internal_r+0xbc> + 800a4e4: a72bc83a sub r21,r20,fp + 800a4e8: a8009626 beq r21,zero,800a744 <___vfiprintf_internal_r+0x334> + 800a4ec: d8c00b17 ldw r3,44(sp) + 800a4f0: d8800a17 ldw r2,40(sp) + 800a4f4: 47000015 stw fp,0(r8) + 800a4f8: a8c7883a add r3,r21,r3 + 800a4fc: 10800044 addi r2,r2,1 + 800a500: d8800a15 stw r2,40(sp) + 800a504: 45400115 stw r21,4(r8) + 800a508: d8c00b15 stw r3,44(sp) + 800a50c: 10800208 cmpgei r2,r2,8 + 800a510: 1000841e bne r2,zero,800a724 <___vfiprintf_internal_r+0x314> + 800a514: 42000204 addi r8,r8,8 + 800a518: d8c00017 ldw r3,0(sp) + 800a51c: 80800047 ldb r2,1(r16) + 800a520: 1d47883a add r3,r3,r21 + 800a524: d8c00015 stw r3,0(sp) + 800a528: 10008626 beq r2,zero,800a744 <___vfiprintf_internal_r+0x334> + 800a52c: a0800047 ldb r2,1(r20) + 800a530: a7000044 addi fp,r20,1 + 800a534: d8000845 stb zero,33(sp) + 800a538: 000b883a mov r5,zero + 800a53c: 000d883a mov r6,zero + 800a540: 027fffc4 movi r9,-1 + 800a544: 0021883a mov r16,zero + 800a548: 0019883a mov r12,zero + 800a54c: e7000044 addi fp,fp,1 + 800a550: 10fff804 addi r3,r2,-32 + 800a554: 19001668 cmpgeui r4,r3,89 + 800a558: 20009c1e bne r4,zero,800a7cc <___vfiprintf_internal_r+0x3bc> + 800a55c: 180690ba slli r3,r3,2 + 800a560: 01020074 movhi r4,2049 + 800a564: 1909883a add r4,r3,r4 + 800a568: 20e95c17 ldw r3,-23184(r4) + 800a56c: 1800683a jmp r3 + 800a570: 0800a89c xori zero,at,674 + 800a574: 0800a7cc andi zero,at,671 + 800a578: 0800a7cc andi zero,at,671 + 800a57c: 0800a890 cmplti zero,at,674 + 800a580: 0800a7cc andi zero,at,671 + 800a584: 0800a7cc andi zero,at,671 + 800a588: 0800a7cc andi zero,at,671 + 800a58c: 0800a7cc andi zero,at,671 + 800a590: 0800a7cc andi zero,at,671 + 800a594: 0800a7cc andi zero,at,671 + 800a598: 0800a868 cmpgeui zero,at,673 + 800a59c: 0800a858 cmpnei zero,at,673 + 800a5a0: 0800a7cc andi zero,at,671 + 800a5a4: 0800a840 call 800a84 + 800a5a8: 0800a7fc xorhi zero,at,671 + 800a5ac: 0800a7cc andi zero,at,671 + 800a5b0: 0800a7f0 cmpltui zero,at,671 + 800a5b4: 0800a79c xori zero,at,670 + 800a5b8: 0800a79c xori zero,at,670 + 800a5bc: 0800a79c xori zero,at,670 + 800a5c0: 0800a79c xori zero,at,670 + 800a5c4: 0800a79c xori zero,at,670 + 800a5c8: 0800a79c xori zero,at,670 + 800a5cc: 0800a79c xori zero,at,670 + 800a5d0: 0800a79c xori zero,at,670 + 800a5d4: 0800a79c xori zero,at,670 + 800a5d8: 0800a7cc andi zero,at,671 + 800a5dc: 0800a7cc andi zero,at,671 + 800a5e0: 0800a7cc andi zero,at,671 + 800a5e4: 0800a7cc andi zero,at,671 + 800a5e8: 0800a7cc andi zero,at,671 + 800a5ec: 0800a7cc andi zero,at,671 + 800a5f0: 0800a7cc andi zero,at,671 + 800a5f4: 0800a7cc andi zero,at,671 + 800a5f8: 0800a7cc andi zero,at,671 + 800a5fc: 0800a7cc andi zero,at,671 + 800a600: 0800ae58 cmpnei zero,at,697 + 800a604: 0800a7cc andi zero,at,671 + 800a608: 0800a7cc andi zero,at,671 + 800a60c: 0800a7cc andi zero,at,671 + 800a610: 0800a7cc andi zero,at,671 + 800a614: 0800a7cc andi zero,at,671 + 800a618: 0800a7cc andi zero,at,671 + 800a61c: 0800a7cc andi zero,at,671 + 800a620: 0800a7cc andi zero,at,671 + 800a624: 0800a7cc andi zero,at,671 + 800a628: 0800a7cc andi zero,at,671 + 800a62c: 0800adf0 cmpltui zero,at,695 + 800a630: 0800a7cc andi zero,at,671 + 800a634: 0800a7cc andi zero,at,671 + 800a638: 0800a7cc andi zero,at,671 + 800a63c: 0800a7cc andi zero,at,671 + 800a640: 0800a7cc andi zero,at,671 + 800a644: 0800ae24 muli zero,at,696 + 800a648: 0800a7cc andi zero,at,671 + 800a64c: 0800a7cc andi zero,at,671 + 800a650: 0800a9f4 orhi zero,at,679 + 800a654: 0800a7cc andi zero,at,671 + 800a658: 0800a7cc andi zero,at,671 + 800a65c: 0800a7cc andi zero,at,671 + 800a660: 0800a7cc andi zero,at,671 + 800a664: 0800a7cc andi zero,at,671 + 800a668: 0800a7cc andi zero,at,671 + 800a66c: 0800a7cc andi zero,at,671 + 800a670: 0800a7cc andi zero,at,671 + 800a674: 0800a7cc andi zero,at,671 + 800a678: 0800a7cc andi zero,at,671 + 800a67c: 0800ab90 cmplti zero,at,686 + 800a680: 0800ab1c xori zero,at,684 + 800a684: 0800a7cc andi zero,at,671 + 800a688: 0800a7cc andi zero,at,671 + 800a68c: 0800a7cc andi zero,at,671 + 800a690: 0800a924 muli zero,at,676 + 800a694: 0800ab1c xori zero,at,684 + 800a698: 0800a7cc andi zero,at,671 + 800a69c: 0800a7cc andi zero,at,671 + 800a6a0: 0800a910 cmplti zero,at,676 + 800a6a4: 0800a7cc andi zero,at,671 + 800a6a8: 0800aadc xori zero,at,683 + 800a6ac: 0800a9b4 orhi zero,at,678 + 800a6b0: 0800a93c xorhi zero,at,676 + 800a6b4: 0800a930 cmpltui zero,at,676 + 800a6b8: 0800a7cc andi zero,at,671 + 800a6bc: 0800aa7c xorhi zero,at,681 + 800a6c0: 0800a7cc andi zero,at,671 + 800a6c4: 0800aa3c xorhi zero,at,680 + 800a6c8: 0800a7cc andi zero,at,671 + 800a6cc: 0800a7cc andi zero,at,671 + 800a6d0: 0800a8c8 cmpgei zero,at,675 + 800a6d4: 900b883a mov r5,r18 + 800a6d8: 9809883a mov r4,r19 + 800a6dc: 800507c0 call 800507c <__swsetup_r> + 800a6e0: 1004071e bne r2,zero,800b700 <___vfiprintf_internal_r+0x12f0> + 800a6e4: 9080030b ldhu r2,12(r18) + 800a6e8: 1080068c andi r2,r2,26 + 800a6ec: 10800298 cmpnei r2,r2,10 + 800a6f0: 103f691e bne r2,zero,800a498 <___vfiprintf_internal_r+0x88> + 800a6f4: 9080038f ldh r2,14(r18) + 800a6f8: 103f6716 blt r2,zero,800a498 <___vfiprintf_internal_r+0x88> + 800a6fc: d9c00317 ldw r7,12(sp) + 800a700: e00d883a mov r6,fp + 800a704: 900b883a mov r5,r18 + 800a708: 9809883a mov r4,r19 + 800a70c: 800b7540 call 800b754 <__sbprintf> + 800a710: d8800015 stw r2,0(sp) + 800a714: 00001406 br 800a768 <___vfiprintf_internal_r+0x358> + 800a718: a72bc83a sub r21,r20,fp + 800a71c: a83f8326 beq r21,zero,800a52c <___vfiprintf_internal_r+0x11c> + 800a720: 003f7206 br 800a4ec <___vfiprintf_internal_r+0xdc> + 800a724: 18032b26 beq r3,zero,800b3d4 <___vfiprintf_internal_r+0xfc4> + 800a728: d9800904 addi r6,sp,36 + 800a72c: 900b883a mov r5,r18 + 800a730: 9809883a mov r4,r19 + 800a734: 800a3040 call 800a304 <__sprint_r.part.0> + 800a738: 1000081e bne r2,zero,800a75c <___vfiprintf_internal_r+0x34c> + 800a73c: 8811883a mov r8,r17 + 800a740: 003f7506 br 800a518 <___vfiprintf_internal_r+0x108> + 800a744: d8800b17 ldw r2,44(sp) + 800a748: 10000426 beq r2,zero,800a75c <___vfiprintf_internal_r+0x34c> + 800a74c: d9800904 addi r6,sp,36 + 800a750: 900b883a mov r5,r18 + 800a754: 9809883a mov r4,r19 + 800a758: 800a3040 call 800a304 <__sprint_r.part.0> + 800a75c: 9080030b ldhu r2,12(r18) + 800a760: 1080100c andi r2,r2,64 + 800a764: 1003e61e bne r2,zero,800b700 <___vfiprintf_internal_r+0x12f0> + 800a768: d8800017 ldw r2,0(sp) + 800a76c: dfc02f17 ldw ra,188(sp) + 800a770: df002e17 ldw fp,184(sp) + 800a774: ddc02d17 ldw r23,180(sp) + 800a778: dd802c17 ldw r22,176(sp) + 800a77c: dd402b17 ldw r21,172(sp) + 800a780: dd002a17 ldw r20,168(sp) + 800a784: dcc02917 ldw r19,164(sp) + 800a788: dc802817 ldw r18,160(sp) + 800a78c: dc402717 ldw r17,156(sp) + 800a790: dc002617 ldw r16,152(sp) + 800a794: dec03004 addi sp,sp,192 + 800a798: f800283a ret + 800a79c: 0021883a mov r16,zero + 800a7a0: 10fff404 addi r3,r2,-48 + 800a7a4: e7000044 addi fp,fp,1 + 800a7a8: 840002a4 muli r16,r16,10 + 800a7ac: e0bfffc7 ldb r2,-1(fp) + 800a7b0: 1c21883a add r16,r3,r16 + 800a7b4: 10fff404 addi r3,r2,-48 + 800a7b8: 190002b0 cmpltui r4,r3,10 + 800a7bc: 203ff91e bne r4,zero,800a7a4 <___vfiprintf_internal_r+0x394> + 800a7c0: 10fff804 addi r3,r2,-32 + 800a7c4: 19001668 cmpgeui r4,r3,89 + 800a7c8: 203f6426 beq r4,zero,800a55c <___vfiprintf_internal_r+0x14c> + 800a7cc: 29403fcc andi r5,r5,255 + 800a7d0: 2803a91e bne r5,zero,800b678 <___vfiprintf_internal_r+0x1268> + 800a7d4: 103fdb26 beq r2,zero,800a744 <___vfiprintf_internal_r+0x334> + 800a7d8: d8800c05 stb r2,48(sp) + 800a7dc: d8000845 stb zero,33(sp) + 800a7e0: 05400044 movi r21,1 + 800a7e4: 05800044 movi r22,1 + 800a7e8: ddc00c04 addi r23,sp,48 + 800a7ec: 0000f106 br 800abb4 <___vfiprintf_internal_r+0x7a4> + 800a7f0: 63002014 ori r12,r12,128 + 800a7f4: e0800007 ldb r2,0(fp) + 800a7f8: 003f5406 br 800a54c <___vfiprintf_internal_r+0x13c> + 800a7fc: e0800007 ldb r2,0(fp) + 800a800: e1000044 addi r4,fp,1 + 800a804: 10c00aa0 cmpeqi r3,r2,42 + 800a808: 1803c01e bne r3,zero,800b70c <___vfiprintf_internal_r+0x12fc> + 800a80c: 10fff404 addi r3,r2,-48 + 800a810: 19c002b0 cmpltui r7,r3,10 + 800a814: 2039883a mov fp,r4 + 800a818: 0013883a mov r9,zero + 800a81c: 383f4c26 beq r7,zero,800a550 <___vfiprintf_internal_r+0x140> + 800a820: e7000044 addi fp,fp,1 + 800a824: 4a4002a4 muli r9,r9,10 + 800a828: e0bfffc7 ldb r2,-1(fp) + 800a82c: 48d3883a add r9,r9,r3 + 800a830: 10fff404 addi r3,r2,-48 + 800a834: 190002b0 cmpltui r4,r3,10 + 800a838: 203ff91e bne r4,zero,800a820 <___vfiprintf_internal_r+0x410> + 800a83c: 003f4406 br 800a550 <___vfiprintf_internal_r+0x140> + 800a840: e0800003 ldbu r2,0(fp) + 800a844: 10803fcc andi r2,r2,255 + 800a848: 1080201c xori r2,r2,128 + 800a84c: 63000114 ori r12,r12,4 + 800a850: 10bfe004 addi r2,r2,-128 + 800a854: 003f3d06 br 800a54c <___vfiprintf_internal_r+0x13c> + 800a858: 01400044 movi r5,1 + 800a85c: 01800ac4 movi r6,43 + 800a860: e0800007 ldb r2,0(fp) + 800a864: 003f3906 br 800a54c <___vfiprintf_internal_r+0x13c> + 800a868: d8800317 ldw r2,12(sp) + 800a86c: 14000017 ldw r16,0(r2) + 800a870: 15c00104 addi r23,r2,4 + 800a874: e0800003 ldbu r2,0(fp) + 800a878: 80031416 blt r16,zero,800b4cc <___vfiprintf_internal_r+0x10bc> + 800a87c: ddc00315 stw r23,12(sp) + 800a880: 10803fcc andi r2,r2,255 + 800a884: 1080201c xori r2,r2,128 + 800a888: 10bfe004 addi r2,r2,-128 + 800a88c: 003f2f06 br 800a54c <___vfiprintf_internal_r+0x13c> + 800a890: 63000054 ori r12,r12,1 + 800a894: e0800007 ldb r2,0(fp) + 800a898: 003f2c06 br 800a54c <___vfiprintf_internal_r+0x13c> + 800a89c: 30c03fcc andi r3,r6,255 + 800a8a0: 18c0201c xori r3,r3,128 + 800a8a4: 18ffe004 addi r3,r3,-128 + 800a8a8: e0800003 ldbu r2,0(fp) + 800a8ac: 183ff41e bne r3,zero,800a880 <___vfiprintf_internal_r+0x470> + 800a8b0: 10803fcc andi r2,r2,255 + 800a8b4: 1080201c xori r2,r2,128 + 800a8b8: 01400044 movi r5,1 + 800a8bc: 01800804 movi r6,32 + 800a8c0: 10bfe004 addi r2,r2,-128 + 800a8c4: 003f2106 br 800a54c <___vfiprintf_internal_r+0x13c> + 800a8c8: 29403fcc andi r5,r5,255 + 800a8cc: 2803741e bne r5,zero,800b6a0 <___vfiprintf_internal_r+0x1290> + 800a8d0: 00c20134 movhi r3,2052 + 800a8d4: 18dd2004 addi r3,r3,29824 + 800a8d8: d8c00415 stw r3,16(sp) + 800a8dc: 60c0080c andi r3,r12,32 + 800a8e0: 18004b26 beq r3,zero,800aa10 <___vfiprintf_internal_r+0x600> + 800a8e4: d8c00317 ldw r3,12(sp) + 800a8e8: 1d400017 ldw r21,0(r3) + 800a8ec: 1d800117 ldw r22,4(r3) + 800a8f0: 18c00204 addi r3,r3,8 + 800a8f4: d8c00315 stw r3,12(sp) + 800a8f8: 60c0004c andi r3,r12,1 + 800a8fc: 18000226 beq r3,zero,800a908 <___vfiprintf_internal_r+0x4f8> + 800a900: ad86b03a or r3,r21,r22 + 800a904: 1802df1e bne r3,zero,800b484 <___vfiprintf_internal_r+0x1074> + 800a908: 00800084 movi r2,2 + 800a90c: 00001906 br 800a974 <___vfiprintf_internal_r+0x564> + 800a910: e0800007 ldb r2,0(fp) + 800a914: 10c01b18 cmpnei r3,r2,108 + 800a918: 18033026 beq r3,zero,800b5dc <___vfiprintf_internal_r+0x11cc> + 800a91c: 63000414 ori r12,r12,16 + 800a920: 003f0a06 br 800a54c <___vfiprintf_internal_r+0x13c> + 800a924: 63001014 ori r12,r12,64 + 800a928: e0800007 ldb r2,0(fp) + 800a92c: 003f0706 br 800a54c <___vfiprintf_internal_r+0x13c> + 800a930: 63000814 ori r12,r12,32 + 800a934: e0800007 ldb r2,0(fp) + 800a938: 003f0406 br 800a54c <___vfiprintf_internal_r+0x13c> + 800a93c: d8c00317 ldw r3,12(sp) + 800a940: 00800c04 movi r2,48 + 800a944: d8800885 stb r2,34(sp) + 800a948: 00801e04 movi r2,120 + 800a94c: 01020134 movhi r4,2052 + 800a950: d88008c5 stb r2,35(sp) + 800a954: 1d400017 ldw r21,0(r3) + 800a958: 18800104 addi r2,r3,4 + 800a95c: d8800315 stw r2,12(sp) + 800a960: 209d2004 addi r2,r4,29824 + 800a964: d8800415 stw r2,16(sp) + 800a968: 002d883a mov r22,zero + 800a96c: 63000094 ori r12,r12,2 + 800a970: 00800084 movi r2,2 + 800a974: d8000845 stb zero,33(sp) + 800a978: 48ffffe0 cmpeqi r3,r9,-1 + 800a97c: 001b883a mov r13,zero + 800a980: 18014c1e bne r3,zero,800aeb4 <___vfiprintf_internal_r+0xaa4> + 800a984: 053fdfc4 movi r20,-129 + 800a988: ad86b03a or r3,r21,r22 + 800a98c: 6528703a and r20,r12,r20 + 800a990: 1802411e bne r3,zero,800b298 <___vfiprintf_internal_r+0xe88> + 800a994: 48030d1e bne r9,zero,800b5cc <___vfiprintf_internal_r+0x11bc> + 800a998: 1000791e bne r2,zero,800ab80 <___vfiprintf_internal_r+0x770> + 800a99c: 6580004c andi r22,r12,1 + 800a9a0: b002b126 beq r22,zero,800b468 <___vfiprintf_internal_r+0x1058> + 800a9a4: 00800c04 movi r2,48 + 800a9a8: d88015c5 stb r2,87(sp) + 800a9ac: ddc015c4 addi r23,sp,87 + 800a9b0: 00017e06 br 800afac <___vfiprintf_internal_r+0xb9c> + 800a9b4: 29403fcc andi r5,r5,255 + 800a9b8: 2803461e bne r5,zero,800b6d4 <___vfiprintf_internal_r+0x12c4> + 800a9bc: 6080080c andi r2,r12,32 + 800a9c0: 10016b1e bne r2,zero,800af70 <___vfiprintf_internal_r+0xb60> + 800a9c4: d8800317 ldw r2,12(sp) + 800a9c8: 60c0040c andi r3,r12,16 + 800a9cc: 15400017 ldw r21,0(r2) + 800a9d0: 10800104 addi r2,r2,4 + 800a9d4: 18010d1e bne r3,zero,800ae0c <___vfiprintf_internal_r+0x9fc> + 800a9d8: 60c0100c andi r3,r12,64 + 800a9dc: 18031326 beq r3,zero,800b62c <___vfiprintf_internal_r+0x121c> + 800a9e0: d8800315 stw r2,12(sp) + 800a9e4: ad7fffcc andi r21,r21,65535 + 800a9e8: 002d883a mov r22,zero + 800a9ec: 0005883a mov r2,zero + 800a9f0: 003fe006 br 800a974 <___vfiprintf_internal_r+0x564> + 800a9f4: 29403fcc andi r5,r5,255 + 800a9f8: 2803251e bne r5,zero,800b690 <___vfiprintf_internal_r+0x1280> + 800a9fc: 00c20134 movhi r3,2052 + 800aa00: 18dd1b04 addi r3,r3,29804 + 800aa04: d8c00415 stw r3,16(sp) + 800aa08: 60c0080c andi r3,r12,32 + 800aa0c: 183fb51e bne r3,zero,800a8e4 <___vfiprintf_internal_r+0x4d4> + 800aa10: d9000317 ldw r4,12(sp) + 800aa14: 60c0040c andi r3,r12,16 + 800aa18: 25400017 ldw r21,0(r4) + 800aa1c: 21000104 addi r4,r4,4 + 800aa20: d9000315 stw r4,12(sp) + 800aa24: 18026e1e bne r3,zero,800b3e0 <___vfiprintf_internal_r+0xfd0> + 800aa28: 60c0100c andi r3,r12,64 + 800aa2c: 18026c26 beq r3,zero,800b3e0 <___vfiprintf_internal_r+0xfd0> + 800aa30: ad7fffcc andi r21,r21,65535 + 800aa34: 002d883a mov r22,zero + 800aa38: 003faf06 br 800a8f8 <___vfiprintf_internal_r+0x4e8> + 800aa3c: 29403fcc andi r5,r5,255 + 800aa40: 2803151e bne r5,zero,800b698 <___vfiprintf_internal_r+0x1288> + 800aa44: 6080080c andi r2,r12,32 + 800aa48: 10013b1e bne r2,zero,800af38 <___vfiprintf_internal_r+0xb28> + 800aa4c: d8800317 ldw r2,12(sp) + 800aa50: 60c0040c andi r3,r12,16 + 800aa54: 15400017 ldw r21,0(r2) + 800aa58: 10800104 addi r2,r2,4 + 800aa5c: 1800f81e bne r3,zero,800ae40 <___vfiprintf_internal_r+0xa30> + 800aa60: 60c0100c andi r3,r12,64 + 800aa64: 1802ed26 beq r3,zero,800b61c <___vfiprintf_internal_r+0x120c> + 800aa68: d8800315 stw r2,12(sp) + 800aa6c: ad7fffcc andi r21,r21,65535 + 800aa70: 002d883a mov r22,zero + 800aa74: 00800044 movi r2,1 + 800aa78: 003fbe06 br 800a974 <___vfiprintf_internal_r+0x564> + 800aa7c: d8800317 ldw r2,12(sp) + 800aa80: d8000845 stb zero,33(sp) + 800aa84: 15c00017 ldw r23,0(r2) + 800aa88: 15000104 addi r20,r2,4 + 800aa8c: b802da26 beq r23,zero,800b5f8 <___vfiprintf_internal_r+0x11e8> + 800aa90: 48bfffe0 cmpeqi r2,r9,-1 + 800aa94: 1002901e bne r2,zero,800b4d8 <___vfiprintf_internal_r+0x10c8> + 800aa98: 480d883a mov r6,r9 + 800aa9c: 000b883a mov r5,zero + 800aaa0: b809883a mov r4,r23 + 800aaa4: da000315 stw r8,12(sp) + 800aaa8: db000215 stw r12,8(sp) + 800aaac: da400115 stw r9,4(sp) + 800aab0: 80085d00 call 80085d0 + 800aab4: da400117 ldw r9,4(sp) + 800aab8: db000217 ldw r12,8(sp) + 800aabc: da000317 ldw r8,12(sp) + 800aac0: 1002ef26 beq r2,zero,800b680 <___vfiprintf_internal_r+0x1270> + 800aac4: 15edc83a sub r22,r2,r23 + 800aac8: b02b883a mov r21,r22 + 800aacc: b000010e bge r22,zero,800aad4 <___vfiprintf_internal_r+0x6c4> + 800aad0: 002b883a mov r21,zero + 800aad4: dd000315 stw r20,12(sp) + 800aad8: 00003606 br 800abb4 <___vfiprintf_internal_r+0x7a4> + 800aadc: 29403fcc andi r5,r5,255 + 800aae0: 2802fa1e bne r5,zero,800b6cc <___vfiprintf_internal_r+0x12bc> + 800aae4: d9000317 ldw r4,12(sp) + 800aae8: 6080080c andi r2,r12,32 + 800aaec: 20c00104 addi r3,r4,4 + 800aaf0: 10026a1e bne r2,zero,800b49c <___vfiprintf_internal_r+0x108c> + 800aaf4: 6080040c andi r2,r12,16 + 800aaf8: 1002891e bne r2,zero,800b520 <___vfiprintf_internal_r+0x1110> + 800aafc: 6300100c andi r12,r12,64 + 800ab00: 60028726 beq r12,zero,800b520 <___vfiprintf_internal_r+0x1110> + 800ab04: d8800317 ldw r2,12(sp) + 800ab08: d8c00315 stw r3,12(sp) + 800ab0c: d8c00017 ldw r3,0(sp) + 800ab10: 10800017 ldw r2,0(r2) + 800ab14: 10c0000d sth r3,0(r2) + 800ab18: 003e6606 br 800a4b4 <___vfiprintf_internal_r+0xa4> + 800ab1c: 29403fcc andi r5,r5,255 + 800ab20: 2802e81e bne r5,zero,800b6c4 <___vfiprintf_internal_r+0x12b4> + 800ab24: 6080080c andi r2,r12,32 + 800ab28: 10010a1e bne r2,zero,800af54 <___vfiprintf_internal_r+0xb44> + 800ab2c: d8800317 ldw r2,12(sp) + 800ab30: 60c0040c andi r3,r12,16 + 800ab34: 10800104 addi r2,r2,4 + 800ab38: 1800ce1e bne r3,zero,800ae74 <___vfiprintf_internal_r+0xa64> + 800ab3c: 60c0100c andi r3,r12,64 + 800ab40: 1800cc26 beq r3,zero,800ae74 <___vfiprintf_internal_r+0xa64> + 800ab44: d8c00317 ldw r3,12(sp) + 800ab48: d8800315 stw r2,12(sp) + 800ab4c: 1d40000f ldh r21,0(r3) + 800ab50: a82dd7fa srai r22,r21,31 + 800ab54: b005883a mov r2,r22 + 800ab58: 1000cc16 blt r2,zero,800ae8c <___vfiprintf_internal_r+0xa7c> + 800ab5c: 48bfffd8 cmpnei r2,r9,-1 + 800ab60: db400843 ldbu r13,33(sp) + 800ab64: 10010926 beq r2,zero,800af8c <___vfiprintf_internal_r+0xb7c> + 800ab68: 00ffdfc4 movi r3,-129 + 800ab6c: ad84b03a or r2,r21,r22 + 800ab70: 60d8703a and r12,r12,r3 + 800ab74: 1001051e bne r2,zero,800af8c <___vfiprintf_internal_r+0xb7c> + 800ab78: 4801071e bne r9,zero,800af98 <___vfiprintf_internal_r+0xb88> + 800ab7c: 6029883a mov r20,r12 + 800ab80: 0013883a mov r9,zero + 800ab84: 002d883a mov r22,zero + 800ab88: 882f883a mov r23,r17 + 800ab8c: 00010706 br 800afac <___vfiprintf_internal_r+0xb9c> + 800ab90: d8c00317 ldw r3,12(sp) + 800ab94: d8000845 stb zero,33(sp) + 800ab98: 05400044 movi r21,1 + 800ab9c: 18800017 ldw r2,0(r3) + 800aba0: 18c00104 addi r3,r3,4 + 800aba4: d8c00315 stw r3,12(sp) + 800aba8: d8800c05 stb r2,48(sp) + 800abac: 05800044 movi r22,1 + 800abb0: ddc00c04 addi r23,sp,48 + 800abb4: 6029883a mov r20,r12 + 800abb8: 0013883a mov r9,zero + 800abbc: a340008c andi r13,r20,2 + 800abc0: 68000126 beq r13,zero,800abc8 <___vfiprintf_internal_r+0x7b8> + 800abc4: ad400084 addi r21,r21,2 + 800abc8: d9000a17 ldw r4,40(sp) + 800abcc: a300210c andi r12,r20,132 + 800abd0: d8800b17 ldw r2,44(sp) + 800abd4: 21800044 addi r6,r4,1 + 800abd8: 300b883a mov r5,r6 + 800abdc: 6000021e bne r12,zero,800abe8 <___vfiprintf_internal_r+0x7d8> + 800abe0: 8547c83a sub r3,r16,r21 + 800abe4: 00c1ae16 blt zero,r3,800b2a0 <___vfiprintf_internal_r+0xe90> + 800abe8: d9800847 ldb r6,33(sp) + 800abec: 40c00204 addi r3,r8,8 + 800abf0: 30000d26 beq r6,zero,800ac28 <___vfiprintf_internal_r+0x818> + 800abf4: d9000844 addi r4,sp,33 + 800abf8: 10800044 addi r2,r2,1 + 800abfc: 41000015 stw r4,0(r8) + 800ac00: 01000044 movi r4,1 + 800ac04: 41000115 stw r4,4(r8) + 800ac08: d8800b15 stw r2,44(sp) + 800ac0c: d9400a15 stw r5,40(sp) + 800ac10: 29000208 cmpgei r4,r5,8 + 800ac14: 2001831e bne r4,zero,800b224 <___vfiprintf_internal_r+0xe14> + 800ac18: 2809883a mov r4,r5 + 800ac1c: 1811883a mov r8,r3 + 800ac20: 29400044 addi r5,r5,1 + 800ac24: 18c00204 addi r3,r3,8 + 800ac28: 68001826 beq r13,zero,800ac8c <___vfiprintf_internal_r+0x87c> + 800ac2c: d9000884 addi r4,sp,34 + 800ac30: 10800084 addi r2,r2,2 + 800ac34: 41000015 stw r4,0(r8) + 800ac38: 01000084 movi r4,2 + 800ac3c: 41000115 stw r4,4(r8) + 800ac40: d8800b15 stw r2,44(sp) + 800ac44: d9400a15 stw r5,40(sp) + 800ac48: 29000208 cmpgei r4,r5,8 + 800ac4c: 20018d26 beq r4,zero,800b284 <___vfiprintf_internal_r+0xe74> + 800ac50: 1001ed26 beq r2,zero,800b408 <___vfiprintf_internal_r+0xff8> + 800ac54: d9800904 addi r6,sp,36 + 800ac58: 900b883a mov r5,r18 + 800ac5c: 9809883a mov r4,r19 + 800ac60: da400215 stw r9,8(sp) + 800ac64: db000115 stw r12,4(sp) + 800ac68: 800a3040 call 800a304 <__sprint_r.part.0> + 800ac6c: 103ebb1e bne r2,zero,800a75c <___vfiprintf_internal_r+0x34c> + 800ac70: d9000a17 ldw r4,40(sp) + 800ac74: d8800b17 ldw r2,44(sp) + 800ac78: da400217 ldw r9,8(sp) + 800ac7c: db000117 ldw r12,4(sp) + 800ac80: d8c01804 addi r3,sp,96 + 800ac84: 21400044 addi r5,r4,1 + 800ac88: 8811883a mov r8,r17 + 800ac8c: 63002018 cmpnei r12,r12,128 + 800ac90: 6000e326 beq r12,zero,800b020 <___vfiprintf_internal_r+0xc10> + 800ac94: 4d93c83a sub r9,r9,r22 + 800ac98: 02412216 blt zero,r9,800b124 <___vfiprintf_internal_r+0xd14> + 800ac9c: b085883a add r2,r22,r2 + 800aca0: d9400a15 stw r5,40(sp) + 800aca4: 45c00015 stw r23,0(r8) + 800aca8: 45800115 stw r22,4(r8) + 800acac: d8800b15 stw r2,44(sp) + 800acb0: 29400210 cmplti r5,r5,8 + 800acb4: 2800081e bne r5,zero,800acd8 <___vfiprintf_internal_r+0x8c8> + 800acb8: 10001426 beq r2,zero,800ad0c <___vfiprintf_internal_r+0x8fc> + 800acbc: d9800904 addi r6,sp,36 + 800acc0: 900b883a mov r5,r18 + 800acc4: 9809883a mov r4,r19 + 800acc8: 800a3040 call 800a304 <__sprint_r.part.0> + 800accc: 103ea31e bne r2,zero,800a75c <___vfiprintf_internal_r+0x34c> + 800acd0: d8800b17 ldw r2,44(sp) + 800acd4: 8807883a mov r3,r17 + 800acd8: a500010c andi r20,r20,4 + 800acdc: a0000226 beq r20,zero,800ace8 <___vfiprintf_internal_r+0x8d8> + 800ace0: 8569c83a sub r20,r16,r21 + 800ace4: 05000f16 blt zero,r20,800ad24 <___vfiprintf_internal_r+0x914> + 800ace8: 8540010e bge r16,r21,800acf0 <___vfiprintf_internal_r+0x8e0> + 800acec: a821883a mov r16,r21 + 800acf0: d8c00017 ldw r3,0(sp) + 800acf4: 1c07883a add r3,r3,r16 + 800acf8: d8c00015 stw r3,0(sp) + 800acfc: 10013f1e bne r2,zero,800b1fc <___vfiprintf_internal_r+0xdec> + 800ad00: d8000a15 stw zero,40(sp) + 800ad04: 8811883a mov r8,r17 + 800ad08: 003dea06 br 800a4b4 <___vfiprintf_internal_r+0xa4> + 800ad0c: d8000a15 stw zero,40(sp) + 800ad10: a500010c andi r20,r20,4 + 800ad14: a0019d26 beq r20,zero,800b38c <___vfiprintf_internal_r+0xf7c> + 800ad18: 8569c83a sub r20,r16,r21 + 800ad1c: 05019b0e bge zero,r20,800b38c <___vfiprintf_internal_r+0xf7c> + 800ad20: 8807883a mov r3,r17 + 800ad24: a1000450 cmplti r4,r20,17 + 800ad28: 01c20134 movhi r7,2052 + 800ad2c: d9400a17 ldw r5,40(sp) + 800ad30: 20026c1e bne r4,zero,800b6e4 <___vfiprintf_internal_r+0x12d4> + 800ad34: 39dd8104 addi r7,r7,30212 + 800ad38: 05800404 movi r22,16 + 800ad3c: 00000606 br 800ad58 <___vfiprintf_internal_r+0x948> + 800ad40: 29800084 addi r6,r5,2 + 800ad44: 18c00204 addi r3,r3,8 + 800ad48: 200b883a mov r5,r4 + 800ad4c: a53ffc04 addi r20,r20,-16 + 800ad50: a1000448 cmpgei r4,r20,17 + 800ad54: 20001726 beq r4,zero,800adb4 <___vfiprintf_internal_r+0x9a4> + 800ad58: 29000044 addi r4,r5,1 + 800ad5c: 10800404 addi r2,r2,16 + 800ad60: 19c00015 stw r7,0(r3) + 800ad64: 1d800115 stw r22,4(r3) + 800ad68: d8800b15 stw r2,44(sp) + 800ad6c: d9000a15 stw r4,40(sp) + 800ad70: 21800208 cmpgei r6,r4,8 + 800ad74: 303ff226 beq r6,zero,800ad40 <___vfiprintf_internal_r+0x930> + 800ad78: d9800904 addi r6,sp,36 + 800ad7c: 900b883a mov r5,r18 + 800ad80: 9809883a mov r4,r19 + 800ad84: 1000a226 beq r2,zero,800b010 <___vfiprintf_internal_r+0xc00> + 800ad88: d9c00115 stw r7,4(sp) + 800ad8c: 800a3040 call 800a304 <__sprint_r.part.0> + 800ad90: 103e721e bne r2,zero,800a75c <___vfiprintf_internal_r+0x34c> + 800ad94: d9400a17 ldw r5,40(sp) + 800ad98: a53ffc04 addi r20,r20,-16 + 800ad9c: a1000448 cmpgei r4,r20,17 + 800ada0: d8800b17 ldw r2,44(sp) + 800ada4: 8807883a mov r3,r17 + 800ada8: 29800044 addi r6,r5,1 + 800adac: d9c00117 ldw r7,4(sp) + 800adb0: 203fe91e bne r4,zero,800ad58 <___vfiprintf_internal_r+0x948> + 800adb4: 1505883a add r2,r2,r20 + 800adb8: d9800a15 stw r6,40(sp) + 800adbc: 19c00015 stw r7,0(r3) + 800adc0: 1d000115 stw r20,4(r3) + 800adc4: d8800b15 stw r2,44(sp) + 800adc8: 31800210 cmplti r6,r6,8 + 800adcc: 303fc61e bne r6,zero,800ace8 <___vfiprintf_internal_r+0x8d8> + 800add0: 10016e26 beq r2,zero,800b38c <___vfiprintf_internal_r+0xf7c> + 800add4: d9800904 addi r6,sp,36 + 800add8: 900b883a mov r5,r18 + 800addc: 9809883a mov r4,r19 + 800ade0: 800a3040 call 800a304 <__sprint_r.part.0> + 800ade4: 103e5d1e bne r2,zero,800a75c <___vfiprintf_internal_r+0x34c> + 800ade8: d8800b17 ldw r2,44(sp) + 800adec: 003fbe06 br 800ace8 <___vfiprintf_internal_r+0x8d8> + 800adf0: 29403fcc andi r5,r5,255 + 800adf4: 28022c1e bne r5,zero,800b6a8 <___vfiprintf_internal_r+0x1298> + 800adf8: 6080080c andi r2,r12,32 + 800adfc: 63000414 ori r12,r12,16 + 800ae00: 10005b1e bne r2,zero,800af70 <___vfiprintf_internal_r+0xb60> + 800ae04: d8800317 ldw r2,12(sp) + 800ae08: 10800104 addi r2,r2,4 + 800ae0c: d8c00317 ldw r3,12(sp) + 800ae10: 002d883a mov r22,zero + 800ae14: d8800315 stw r2,12(sp) + 800ae18: 1d400017 ldw r21,0(r3) + 800ae1c: 0005883a mov r2,zero + 800ae20: 003ed406 br 800a974 <___vfiprintf_internal_r+0x564> + 800ae24: 29403fcc andi r5,r5,255 + 800ae28: 2802211e bne r5,zero,800b6b0 <___vfiprintf_internal_r+0x12a0> + 800ae2c: 6080080c andi r2,r12,32 + 800ae30: 63000414 ori r12,r12,16 + 800ae34: 1000401e bne r2,zero,800af38 <___vfiprintf_internal_r+0xb28> + 800ae38: d8800317 ldw r2,12(sp) + 800ae3c: 10800104 addi r2,r2,4 + 800ae40: d8c00317 ldw r3,12(sp) + 800ae44: 002d883a mov r22,zero + 800ae48: d8800315 stw r2,12(sp) + 800ae4c: 1d400017 ldw r21,0(r3) + 800ae50: 00800044 movi r2,1 + 800ae54: 003ec706 br 800a974 <___vfiprintf_internal_r+0x564> + 800ae58: 29403fcc andi r5,r5,255 + 800ae5c: 28021f1e bne r5,zero,800b6dc <___vfiprintf_internal_r+0x12cc> + 800ae60: 6080080c andi r2,r12,32 + 800ae64: 63000414 ori r12,r12,16 + 800ae68: 10003a1e bne r2,zero,800af54 <___vfiprintf_internal_r+0xb44> + 800ae6c: d8800317 ldw r2,12(sp) + 800ae70: 10800104 addi r2,r2,4 + 800ae74: d8c00317 ldw r3,12(sp) + 800ae78: 1d400017 ldw r21,0(r3) + 800ae7c: d8800315 stw r2,12(sp) + 800ae80: a82dd7fa srai r22,r21,31 + 800ae84: b005883a mov r2,r22 + 800ae88: 103f340e bge r2,zero,800ab5c <___vfiprintf_internal_r+0x74c> + 800ae8c: 056bc83a sub r21,zero,r21 + 800ae90: a804c03a cmpne r2,r21,zero + 800ae94: 05adc83a sub r22,zero,r22 + 800ae98: b0adc83a sub r22,r22,r2 + 800ae9c: 00800b44 movi r2,45 + 800aea0: d8800845 stb r2,33(sp) + 800aea4: 48ffffe0 cmpeqi r3,r9,-1 + 800aea8: 03400b44 movi r13,45 + 800aeac: 00800044 movi r2,1 + 800aeb0: 183eb426 beq r3,zero,800a984 <___vfiprintf_internal_r+0x574> + 800aeb4: 10c00060 cmpeqi r3,r2,1 + 800aeb8: 1800341e bne r3,zero,800af8c <___vfiprintf_internal_r+0xb7c> + 800aebc: 108000a0 cmpeqi r2,r2,2 + 800aec0: 1000431e bne r2,zero,800afd0 <___vfiprintf_internal_r+0xbc0> + 800aec4: 8807883a mov r3,r17 + 800aec8: 00000106 br 800aed0 <___vfiprintf_internal_r+0xac0> + 800aecc: b807883a mov r3,r23 + 800aed0: a808d0fa srli r4,r21,3 + 800aed4: b00a977a slli r5,r22,29 + 800aed8: b02cd0fa srli r22,r22,3 + 800aedc: ad4001cc andi r21,r21,7 + 800aee0: a8800c04 addi r2,r21,48 + 800aee4: 292ab03a or r21,r5,r4 + 800aee8: 18bfffc5 stb r2,-1(r3) + 800aeec: ad88b03a or r4,r21,r22 + 800aef0: 1dffffc4 addi r23,r3,-1 + 800aef4: 203ff51e bne r4,zero,800aecc <___vfiprintf_internal_r+0xabc> + 800aef8: 6100004c andi r4,r12,1 + 800aefc: 20004126 beq r4,zero,800b004 <___vfiprintf_internal_r+0xbf4> + 800af00: 10803fcc andi r2,r2,255 + 800af04: 1080201c xori r2,r2,128 + 800af08: 10bfe004 addi r2,r2,-128 + 800af0c: 10800c18 cmpnei r2,r2,48 + 800af10: 10003c26 beq r2,zero,800b004 <___vfiprintf_internal_r+0xbf4> + 800af14: 18ffff84 addi r3,r3,-2 + 800af18: 00800c04 movi r2,48 + 800af1c: b8bfffc5 stb r2,-1(r23) + 800af20: 88edc83a sub r22,r17,r3 + 800af24: 6029883a mov r20,r12 + 800af28: 182f883a mov r23,r3 + 800af2c: 00001f06 br 800afac <___vfiprintf_internal_r+0xb9c> + 800af30: 80070600 call 8007060 <__sinit> + 800af34: 003d4806 br 800a458 <___vfiprintf_internal_r+0x48> + 800af38: d8c00317 ldw r3,12(sp) + 800af3c: 00800044 movi r2,1 + 800af40: 1d400017 ldw r21,0(r3) + 800af44: 1d800117 ldw r22,4(r3) + 800af48: 18c00204 addi r3,r3,8 + 800af4c: d8c00315 stw r3,12(sp) + 800af50: 003e8806 br 800a974 <___vfiprintf_internal_r+0x564> + 800af54: d8c00317 ldw r3,12(sp) + 800af58: 18800117 ldw r2,4(r3) + 800af5c: 1d400017 ldw r21,0(r3) + 800af60: 18c00204 addi r3,r3,8 + 800af64: d8c00315 stw r3,12(sp) + 800af68: 102d883a mov r22,r2 + 800af6c: 003efa06 br 800ab58 <___vfiprintf_internal_r+0x748> + 800af70: d8c00317 ldw r3,12(sp) + 800af74: 0005883a mov r2,zero + 800af78: 1d400017 ldw r21,0(r3) + 800af7c: 1d800117 ldw r22,4(r3) + 800af80: 18c00204 addi r3,r3,8 + 800af84: d8c00315 stw r3,12(sp) + 800af88: 003e7a06 br 800a974 <___vfiprintf_internal_r+0x564> + 800af8c: b0016a1e bne r22,zero,800b538 <___vfiprintf_internal_r+0x1128> + 800af90: a88002a8 cmpgeui r2,r21,10 + 800af94: 1001681e bne r2,zero,800b538 <___vfiprintf_internal_r+0x1128> + 800af98: ad400c04 addi r21,r21,48 + 800af9c: dd4015c5 stb r21,87(sp) + 800afa0: 6029883a mov r20,r12 + 800afa4: 05800044 movi r22,1 + 800afa8: ddc015c4 addi r23,sp,87 + 800afac: 482b883a mov r21,r9 + 800afb0: 4d80010e bge r9,r22,800afb8 <___vfiprintf_internal_r+0xba8> + 800afb4: b02b883a mov r21,r22 + 800afb8: 6b403fcc andi r13,r13,255 + 800afbc: 6b40201c xori r13,r13,128 + 800afc0: 6b7fe004 addi r13,r13,-128 + 800afc4: 683efd26 beq r13,zero,800abbc <___vfiprintf_internal_r+0x7ac> + 800afc8: ad400044 addi r21,r21,1 + 800afcc: 003efb06 br 800abbc <___vfiprintf_internal_r+0x7ac> + 800afd0: 882f883a mov r23,r17 + 800afd4: d9000417 ldw r4,16(sp) + 800afd8: a88003cc andi r2,r21,15 + 800afdc: b006973a slli r3,r22,28 + 800afe0: 2085883a add r2,r4,r2 + 800afe4: a82ad13a srli r21,r21,4 + 800afe8: 10800003 ldbu r2,0(r2) + 800afec: b02cd13a srli r22,r22,4 + 800aff0: bdffffc4 addi r23,r23,-1 + 800aff4: 1d6ab03a or r21,r3,r21 + 800aff8: b8800005 stb r2,0(r23) + 800affc: ad84b03a or r2,r21,r22 + 800b000: 103ff41e bne r2,zero,800afd4 <___vfiprintf_internal_r+0xbc4> + 800b004: 8dedc83a sub r22,r17,r23 + 800b008: 6029883a mov r20,r12 + 800b00c: 003fe706 br 800afac <___vfiprintf_internal_r+0xb9c> + 800b010: 01800044 movi r6,1 + 800b014: 000b883a mov r5,zero + 800b018: 8807883a mov r3,r17 + 800b01c: 003f4b06 br 800ad4c <___vfiprintf_internal_r+0x93c> + 800b020: 8559c83a sub r12,r16,r21 + 800b024: 033f1b0e bge zero,r12,800ac94 <___vfiprintf_internal_r+0x884> + 800b028: 61800450 cmplti r6,r12,17 + 800b02c: 01c20134 movhi r7,2052 + 800b030: 3001af1e bne r6,zero,800b6f0 <___vfiprintf_internal_r+0x12e0> + 800b034: 39dd7d04 addi r7,r7,30196 + 800b038: 03400404 movi r13,16 + 800b03c: 00000606 br 800b058 <___vfiprintf_internal_r+0xc48> + 800b040: 21800084 addi r6,r4,2 + 800b044: 42000204 addi r8,r8,8 + 800b048: 1809883a mov r4,r3 + 800b04c: 633ffc04 addi r12,r12,-16 + 800b050: 60c00448 cmpgei r3,r12,17 + 800b054: 18001c26 beq r3,zero,800b0c8 <___vfiprintf_internal_r+0xcb8> + 800b058: 20c00044 addi r3,r4,1 + 800b05c: 10800404 addi r2,r2,16 + 800b060: 41c00015 stw r7,0(r8) + 800b064: 43400115 stw r13,4(r8) + 800b068: d8800b15 stw r2,44(sp) + 800b06c: d8c00a15 stw r3,40(sp) + 800b070: 19400208 cmpgei r5,r3,8 + 800b074: 283ff226 beq r5,zero,800b040 <___vfiprintf_internal_r+0xc30> + 800b078: d9800904 addi r6,sp,36 + 800b07c: 900b883a mov r5,r18 + 800b080: 9809883a mov r4,r19 + 800b084: 10006326 beq r2,zero,800b214 <___vfiprintf_internal_r+0xe04> + 800b088: d9c00515 stw r7,20(sp) + 800b08c: db000215 stw r12,8(sp) + 800b090: da400115 stw r9,4(sp) + 800b094: 800a3040 call 800a304 <__sprint_r.part.0> + 800b098: 103db01e bne r2,zero,800a75c <___vfiprintf_internal_r+0x34c> + 800b09c: db000217 ldw r12,8(sp) + 800b0a0: d9000a17 ldw r4,40(sp) + 800b0a4: d8800b17 ldw r2,44(sp) + 800b0a8: 633ffc04 addi r12,r12,-16 + 800b0ac: 60c00448 cmpgei r3,r12,17 + 800b0b0: 8811883a mov r8,r17 + 800b0b4: 21800044 addi r6,r4,1 + 800b0b8: d9c00517 ldw r7,20(sp) + 800b0bc: 03400404 movi r13,16 + 800b0c0: da400117 ldw r9,4(sp) + 800b0c4: 183fe41e bne r3,zero,800b058 <___vfiprintf_internal_r+0xc48> + 800b0c8: 43400204 addi r13,r8,8 + 800b0cc: 1305883a add r2,r2,r12 + 800b0d0: 41c00015 stw r7,0(r8) + 800b0d4: 43000115 stw r12,4(r8) + 800b0d8: d8800b15 stw r2,44(sp) + 800b0dc: d9800a15 stw r6,40(sp) + 800b0e0: 30c00208 cmpgei r3,r6,8 + 800b0e4: 1800e226 beq r3,zero,800b470 <___vfiprintf_internal_r+0x1060> + 800b0e8: 10015726 beq r2,zero,800b648 <___vfiprintf_internal_r+0x1238> + 800b0ec: d9800904 addi r6,sp,36 + 800b0f0: 900b883a mov r5,r18 + 800b0f4: 9809883a mov r4,r19 + 800b0f8: da400115 stw r9,4(sp) + 800b0fc: 800a3040 call 800a304 <__sprint_r.part.0> + 800b100: 103d961e bne r2,zero,800a75c <___vfiprintf_internal_r+0x34c> + 800b104: da400117 ldw r9,4(sp) + 800b108: d9000a17 ldw r4,40(sp) + 800b10c: d8800b17 ldw r2,44(sp) + 800b110: 4d93c83a sub r9,r9,r22 + 800b114: d8c01804 addi r3,sp,96 + 800b118: 21400044 addi r5,r4,1 + 800b11c: 8811883a mov r8,r17 + 800b120: 027ede0e bge zero,r9,800ac9c <___vfiprintf_internal_r+0x88c> + 800b124: 49800450 cmplti r6,r9,17 + 800b128: 01c20134 movhi r7,2052 + 800b12c: 3001431e bne r6,zero,800b63c <___vfiprintf_internal_r+0x122c> + 800b130: 39dd7d04 addi r7,r7,30196 + 800b134: 03000404 movi r12,16 + 800b138: 00000606 br 800b154 <___vfiprintf_internal_r+0xd44> + 800b13c: 21400084 addi r5,r4,2 + 800b140: 42000204 addi r8,r8,8 + 800b144: 1809883a mov r4,r3 + 800b148: 4a7ffc04 addi r9,r9,-16 + 800b14c: 48c00448 cmpgei r3,r9,17 + 800b150: 18001a26 beq r3,zero,800b1bc <___vfiprintf_internal_r+0xdac> + 800b154: 20c00044 addi r3,r4,1 + 800b158: 10800404 addi r2,r2,16 + 800b15c: 41c00015 stw r7,0(r8) + 800b160: 43000115 stw r12,4(r8) + 800b164: d8800b15 stw r2,44(sp) + 800b168: d8c00a15 stw r3,40(sp) + 800b16c: 19400208 cmpgei r5,r3,8 + 800b170: 283ff226 beq r5,zero,800b13c <___vfiprintf_internal_r+0xd2c> + 800b174: d9800904 addi r6,sp,36 + 800b178: 900b883a mov r5,r18 + 800b17c: 9809883a mov r4,r19 + 800b180: 10001a26 beq r2,zero,800b1ec <___vfiprintf_internal_r+0xddc> + 800b184: d9c00215 stw r7,8(sp) + 800b188: da400115 stw r9,4(sp) + 800b18c: 800a3040 call 800a304 <__sprint_r.part.0> + 800b190: 103d721e bne r2,zero,800a75c <___vfiprintf_internal_r+0x34c> + 800b194: da400117 ldw r9,4(sp) + 800b198: d9000a17 ldw r4,40(sp) + 800b19c: d8800b17 ldw r2,44(sp) + 800b1a0: 4a7ffc04 addi r9,r9,-16 + 800b1a4: 48c00448 cmpgei r3,r9,17 + 800b1a8: 8811883a mov r8,r17 + 800b1ac: 21400044 addi r5,r4,1 + 800b1b0: d9c00217 ldw r7,8(sp) + 800b1b4: 03000404 movi r12,16 + 800b1b8: 183fe61e bne r3,zero,800b154 <___vfiprintf_internal_r+0xd44> + 800b1bc: 41000204 addi r4,r8,8 + 800b1c0: 1245883a add r2,r2,r9 + 800b1c4: 41c00015 stw r7,0(r8) + 800b1c8: 42400115 stw r9,4(r8) + 800b1cc: d8800b15 stw r2,44(sp) + 800b1d0: d9400a15 stw r5,40(sp) + 800b1d4: 28c00208 cmpgei r3,r5,8 + 800b1d8: 1800721e bne r3,zero,800b3a4 <___vfiprintf_internal_r+0xf94> + 800b1dc: 29400044 addi r5,r5,1 + 800b1e0: 20c00204 addi r3,r4,8 + 800b1e4: 2011883a mov r8,r4 + 800b1e8: 003eac06 br 800ac9c <___vfiprintf_internal_r+0x88c> + 800b1ec: 01400044 movi r5,1 + 800b1f0: 0009883a mov r4,zero + 800b1f4: 8811883a mov r8,r17 + 800b1f8: 003fd306 br 800b148 <___vfiprintf_internal_r+0xd38> + 800b1fc: d9800904 addi r6,sp,36 + 800b200: 900b883a mov r5,r18 + 800b204: 9809883a mov r4,r19 + 800b208: 800a3040 call 800a304 <__sprint_r.part.0> + 800b20c: 103ebc26 beq r2,zero,800ad00 <___vfiprintf_internal_r+0x8f0> + 800b210: 003d5206 br 800a75c <___vfiprintf_internal_r+0x34c> + 800b214: 01800044 movi r6,1 + 800b218: 0009883a mov r4,zero + 800b21c: 8811883a mov r8,r17 + 800b220: 003f8a06 br 800b04c <___vfiprintf_internal_r+0xc3c> + 800b224: 10007026 beq r2,zero,800b3e8 <___vfiprintf_internal_r+0xfd8> + 800b228: d9800904 addi r6,sp,36 + 800b22c: 900b883a mov r5,r18 + 800b230: 9809883a mov r4,r19 + 800b234: da400515 stw r9,20(sp) + 800b238: db000215 stw r12,8(sp) + 800b23c: db400115 stw r13,4(sp) + 800b240: 800a3040 call 800a304 <__sprint_r.part.0> + 800b244: 103d451e bne r2,zero,800a75c <___vfiprintf_internal_r+0x34c> + 800b248: d9000a17 ldw r4,40(sp) + 800b24c: d8800b17 ldw r2,44(sp) + 800b250: d8c01804 addi r3,sp,96 + 800b254: 21400044 addi r5,r4,1 + 800b258: 8811883a mov r8,r17 + 800b25c: da400517 ldw r9,20(sp) + 800b260: db000217 ldw r12,8(sp) + 800b264: db400117 ldw r13,4(sp) + 800b268: 003e6f06 br 800ac28 <___vfiprintf_internal_r+0x818> + 800b26c: d8800884 addi r2,sp,34 + 800b270: d8801615 stw r2,88(sp) + 800b274: 00800084 movi r2,2 + 800b278: d8801715 stw r2,92(sp) + 800b27c: d8c01804 addi r3,sp,96 + 800b280: 01400044 movi r5,1 + 800b284: 1811883a mov r8,r3 + 800b288: 2809883a mov r4,r5 + 800b28c: 21400044 addi r5,r4,1 + 800b290: 40c00204 addi r3,r8,8 + 800b294: 003e7d06 br 800ac8c <___vfiprintf_internal_r+0x87c> + 800b298: a019883a mov r12,r20 + 800b29c: 003f0506 br 800aeb4 <___vfiprintf_internal_r+0xaa4> + 800b2a0: 19400450 cmplti r5,r3,17 + 800b2a4: 01c20134 movhi r7,2052 + 800b2a8: 2801031e bne r5,zero,800b6b8 <___vfiprintf_internal_r+0x12a8> + 800b2ac: 39dd8104 addi r7,r7,30212 + 800b2b0: 03800404 movi r14,16 + 800b2b4: 00000706 br 800b2d4 <___vfiprintf_internal_r+0xec4> + 800b2b8: 23c00084 addi r15,r4,2 + 800b2bc: 42000204 addi r8,r8,8 + 800b2c0: 3009883a mov r4,r6 + 800b2c4: 18fffc04 addi r3,r3,-16 + 800b2c8: 19400448 cmpgei r5,r3,17 + 800b2cc: 28002026 beq r5,zero,800b350 <___vfiprintf_internal_r+0xf40> + 800b2d0: 21800044 addi r6,r4,1 + 800b2d4: 10800404 addi r2,r2,16 + 800b2d8: 41c00015 stw r7,0(r8) + 800b2dc: 43800115 stw r14,4(r8) + 800b2e0: d8800b15 stw r2,44(sp) + 800b2e4: d9800a15 stw r6,40(sp) + 800b2e8: 31400208 cmpgei r5,r6,8 + 800b2ec: 283ff226 beq r5,zero,800b2b8 <___vfiprintf_internal_r+0xea8> + 800b2f0: d9800904 addi r6,sp,36 + 800b2f4: 900b883a mov r5,r18 + 800b2f8: 9809883a mov r4,r19 + 800b2fc: 10001f26 beq r2,zero,800b37c <___vfiprintf_internal_r+0xf6c> + 800b300: d9c00715 stw r7,28(sp) + 800b304: d8c00615 stw r3,24(sp) + 800b308: da400515 stw r9,20(sp) + 800b30c: db000215 stw r12,8(sp) + 800b310: db400115 stw r13,4(sp) + 800b314: 800a3040 call 800a304 <__sprint_r.part.0> + 800b318: 103d101e bne r2,zero,800a75c <___vfiprintf_internal_r+0x34c> + 800b31c: d8c00617 ldw r3,24(sp) + 800b320: d9000a17 ldw r4,40(sp) + 800b324: d8800b17 ldw r2,44(sp) + 800b328: 18fffc04 addi r3,r3,-16 + 800b32c: 19400448 cmpgei r5,r3,17 + 800b330: 8811883a mov r8,r17 + 800b334: 23c00044 addi r15,r4,1 + 800b338: d9c00717 ldw r7,28(sp) + 800b33c: 03800404 movi r14,16 + 800b340: da400517 ldw r9,20(sp) + 800b344: db000217 ldw r12,8(sp) + 800b348: db400117 ldw r13,4(sp) + 800b34c: 283fe01e bne r5,zero,800b2d0 <___vfiprintf_internal_r+0xec0> + 800b350: 10c5883a add r2,r2,r3 + 800b354: 40c00115 stw r3,4(r8) + 800b358: 41c00015 stw r7,0(r8) + 800b35c: d8800b15 stw r2,44(sp) + 800b360: dbc00a15 stw r15,40(sp) + 800b364: 78c00208 cmpgei r3,r15,8 + 800b368: 18002c1e bne r3,zero,800b41c <___vfiprintf_internal_r+0x100c> + 800b36c: 42000204 addi r8,r8,8 + 800b370: 79400044 addi r5,r15,1 + 800b374: 7809883a mov r4,r15 + 800b378: 003e1b06 br 800abe8 <___vfiprintf_internal_r+0x7d8> + 800b37c: 0009883a mov r4,zero + 800b380: 03c00044 movi r15,1 + 800b384: 8811883a mov r8,r17 + 800b388: 003fce06 br 800b2c4 <___vfiprintf_internal_r+0xeb4> + 800b38c: 8540010e bge r16,r21,800b394 <___vfiprintf_internal_r+0xf84> + 800b390: a821883a mov r16,r21 + 800b394: d8800017 ldw r2,0(sp) + 800b398: 1405883a add r2,r2,r16 + 800b39c: d8800015 stw r2,0(sp) + 800b3a0: 003e5706 br 800ad00 <___vfiprintf_internal_r+0x8f0> + 800b3a4: 10008126 beq r2,zero,800b5ac <___vfiprintf_internal_r+0x119c> + 800b3a8: d9800904 addi r6,sp,36 + 800b3ac: 900b883a mov r5,r18 + 800b3b0: 9809883a mov r4,r19 + 800b3b4: 800a3040 call 800a304 <__sprint_r.part.0> + 800b3b8: 103ce81e bne r2,zero,800a75c <___vfiprintf_internal_r+0x34c> + 800b3bc: d9400a17 ldw r5,40(sp) + 800b3c0: d8800b17 ldw r2,44(sp) + 800b3c4: d8c01804 addi r3,sp,96 + 800b3c8: 29400044 addi r5,r5,1 + 800b3cc: 8811883a mov r8,r17 + 800b3d0: 003e3206 br 800ac9c <___vfiprintf_internal_r+0x88c> + 800b3d4: d8000a15 stw zero,40(sp) + 800b3d8: 8811883a mov r8,r17 + 800b3dc: 003c4e06 br 800a518 <___vfiprintf_internal_r+0x108> + 800b3e0: 002d883a mov r22,zero + 800b3e4: 003d4406 br 800a8f8 <___vfiprintf_internal_r+0x4e8> + 800b3e8: 68003326 beq r13,zero,800b4b8 <___vfiprintf_internal_r+0x10a8> + 800b3ec: d8800884 addi r2,sp,34 + 800b3f0: d8801615 stw r2,88(sp) + 800b3f4: 00800084 movi r2,2 + 800b3f8: d8801715 stw r2,92(sp) + 800b3fc: da001804 addi r8,sp,96 + 800b400: 01000044 movi r4,1 + 800b404: 003fa106 br 800b28c <___vfiprintf_internal_r+0xe7c> + 800b408: d8c01804 addi r3,sp,96 + 800b40c: 01400044 movi r5,1 + 800b410: 0009883a mov r4,zero + 800b414: 8811883a mov r8,r17 + 800b418: 003e1c06 br 800ac8c <___vfiprintf_internal_r+0x87c> + 800b41c: 10003826 beq r2,zero,800b500 <___vfiprintf_internal_r+0x10f0> + 800b420: d9800904 addi r6,sp,36 + 800b424: 900b883a mov r5,r18 + 800b428: 9809883a mov r4,r19 + 800b42c: da400515 stw r9,20(sp) + 800b430: db000215 stw r12,8(sp) + 800b434: db400115 stw r13,4(sp) + 800b438: 800a3040 call 800a304 <__sprint_r.part.0> + 800b43c: 103cc71e bne r2,zero,800a75c <___vfiprintf_internal_r+0x34c> + 800b440: d9000a17 ldw r4,40(sp) + 800b444: d8800b17 ldw r2,44(sp) + 800b448: 8811883a mov r8,r17 + 800b44c: 21400044 addi r5,r4,1 + 800b450: da400517 ldw r9,20(sp) + 800b454: db000217 ldw r12,8(sp) + 800b458: db400117 ldw r13,4(sp) + 800b45c: 003de206 br 800abe8 <___vfiprintf_internal_r+0x7d8> + 800b460: e029883a mov r20,fp + 800b464: 003c3106 br 800a52c <___vfiprintf_internal_r+0x11c> + 800b468: 882f883a mov r23,r17 + 800b46c: 003ecf06 br 800afac <___vfiprintf_internal_r+0xb9c> + 800b470: 31400044 addi r5,r6,1 + 800b474: 68c00204 addi r3,r13,8 + 800b478: 3009883a mov r4,r6 + 800b47c: 6811883a mov r8,r13 + 800b480: 003e0406 br 800ac94 <___vfiprintf_internal_r+0x884> + 800b484: 00c00c04 movi r3,48 + 800b488: d88008c5 stb r2,35(sp) + 800b48c: d8c00885 stb r3,34(sp) + 800b490: 63000094 ori r12,r12,2 + 800b494: 00800084 movi r2,2 + 800b498: 003d3606 br 800a974 <___vfiprintf_internal_r+0x564> + 800b49c: d9400017 ldw r5,0(sp) + 800b4a0: 20800017 ldw r2,0(r4) + 800b4a4: d8c00315 stw r3,12(sp) + 800b4a8: 2809d7fa srai r4,r5,31 + 800b4ac: 11400015 stw r5,0(r2) + 800b4b0: 11000115 stw r4,4(r2) + 800b4b4: 003bff06 br 800a4b4 <___vfiprintf_internal_r+0xa4> + 800b4b8: 0009883a mov r4,zero + 800b4bc: d8c01804 addi r3,sp,96 + 800b4c0: 01400044 movi r5,1 + 800b4c4: 8811883a mov r8,r17 + 800b4c8: 003df006 br 800ac8c <___vfiprintf_internal_r+0x87c> + 800b4cc: 0421c83a sub r16,zero,r16 + 800b4d0: ddc00315 stw r23,12(sp) + 800b4d4: 003cdb06 br 800a844 <___vfiprintf_internal_r+0x434> + 800b4d8: b809883a mov r4,r23 + 800b4dc: da000215 stw r8,8(sp) + 800b4e0: db000115 stw r12,4(sp) + 800b4e4: 8002dac0 call 8002dac + 800b4e8: 102d883a mov r22,r2 + 800b4ec: 102b883a mov r21,r2 + 800b4f0: dd000315 stw r20,12(sp) + 800b4f4: db000117 ldw r12,4(sp) + 800b4f8: da000217 ldw r8,8(sp) + 800b4fc: 003dad06 br 800abb4 <___vfiprintf_internal_r+0x7a4> + 800b500: d8c00847 ldb r3,33(sp) + 800b504: 1800551e bne r3,zero,800b65c <___vfiprintf_internal_r+0x124c> + 800b508: 683f581e bne r13,zero,800b26c <___vfiprintf_internal_r+0xe5c> + 800b50c: 0009883a mov r4,zero + 800b510: d8c01804 addi r3,sp,96 + 800b514: 01400044 movi r5,1 + 800b518: 8811883a mov r8,r17 + 800b51c: 003ddd06 br 800ac94 <___vfiprintf_internal_r+0x884> + 800b520: d8800317 ldw r2,12(sp) + 800b524: 10800017 ldw r2,0(r2) + 800b528: d8c00315 stw r3,12(sp) + 800b52c: d8c00017 ldw r3,0(sp) + 800b530: 10c00015 stw r3,0(r2) + 800b534: 003bdf06 br 800a4b4 <___vfiprintf_internal_r+0xa4> + 800b538: 882f883a mov r23,r17 + 800b53c: 00000206 br 800b548 <___vfiprintf_internal_r+0x1138> + 800b540: 102b883a mov r21,r2 + 800b544: 182d883a mov r22,r3 + 800b548: a809883a mov r4,r21 + 800b54c: b00b883a mov r5,r22 + 800b550: 01800284 movi r6,10 + 800b554: 000f883a mov r7,zero + 800b558: db400615 stw r13,24(sp) + 800b55c: da000515 stw r8,20(sp) + 800b560: da400215 stw r9,8(sp) + 800b564: db000115 stw r12,4(sp) + 800b568: 800c9c00 call 800c9c0 <__umoddi3> + 800b56c: 10800c04 addi r2,r2,48 + 800b570: bdffffc4 addi r23,r23,-1 + 800b574: a809883a mov r4,r21 + 800b578: b00b883a mov r5,r22 + 800b57c: b8800005 stb r2,0(r23) + 800b580: 01800284 movi r6,10 + 800b584: 000f883a mov r7,zero + 800b588: 800c4280 call 800c428 <__udivdi3> + 800b58c: db000117 ldw r12,4(sp) + 800b590: da400217 ldw r9,8(sp) + 800b594: da000517 ldw r8,20(sp) + 800b598: db400617 ldw r13,24(sp) + 800b59c: b03fe81e bne r22,zero,800b540 <___vfiprintf_internal_r+0x1130> + 800b5a0: ad4002a8 cmpgeui r21,r21,10 + 800b5a4: a83fe61e bne r21,zero,800b540 <___vfiprintf_internal_r+0x1130> + 800b5a8: 003e9606 br 800b004 <___vfiprintf_internal_r+0xbf4> + 800b5ac: 00c00044 movi r3,1 + 800b5b0: d8c00a15 stw r3,40(sp) + 800b5b4: b005883a mov r2,r22 + 800b5b8: ddc01615 stw r23,88(sp) + 800b5bc: dd801715 stw r22,92(sp) + 800b5c0: dd800b15 stw r22,44(sp) + 800b5c4: d8c01804 addi r3,sp,96 + 800b5c8: 003dc306 br 800acd8 <___vfiprintf_internal_r+0x8c8> + 800b5cc: 10c00060 cmpeqi r3,r2,1 + 800b5d0: a019883a mov r12,r20 + 800b5d4: 183e3926 beq r3,zero,800aebc <___vfiprintf_internal_r+0xaac> + 800b5d8: 003e6f06 br 800af98 <___vfiprintf_internal_r+0xb88> + 800b5dc: e0800043 ldbu r2,1(fp) + 800b5e0: 63000814 ori r12,r12,32 + 800b5e4: e7000044 addi fp,fp,1 + 800b5e8: 10803fcc andi r2,r2,255 + 800b5ec: 1080201c xori r2,r2,128 + 800b5f0: 10bfe004 addi r2,r2,-128 + 800b5f4: 003bd506 br 800a54c <___vfiprintf_internal_r+0x13c> + 800b5f8: 488001f0 cmpltui r2,r9,7 + 800b5fc: 482d883a mov r22,r9 + 800b600: 1000011e bne r2,zero,800b608 <___vfiprintf_internal_r+0x11f8> + 800b604: 05800184 movi r22,6 + 800b608: 05c20134 movhi r23,2052 + 800b60c: b02b883a mov r21,r22 + 800b610: dd000315 stw r20,12(sp) + 800b614: bddd2504 addi r23,r23,29844 + 800b618: 003d6606 br 800abb4 <___vfiprintf_internal_r+0x7a4> + 800b61c: d8800315 stw r2,12(sp) + 800b620: 002d883a mov r22,zero + 800b624: 00800044 movi r2,1 + 800b628: 003cd206 br 800a974 <___vfiprintf_internal_r+0x564> + 800b62c: d8800315 stw r2,12(sp) + 800b630: 002d883a mov r22,zero + 800b634: 0005883a mov r2,zero + 800b638: 003cce06 br 800a974 <___vfiprintf_internal_r+0x564> + 800b63c: 1809883a mov r4,r3 + 800b640: 39dd7d04 addi r7,r7,30196 + 800b644: 003ede06 br 800b1c0 <___vfiprintf_internal_r+0xdb0> + 800b648: d8c01804 addi r3,sp,96 + 800b64c: 01400044 movi r5,1 + 800b650: 0009883a mov r4,zero + 800b654: 8811883a mov r8,r17 + 800b658: 003d8e06 br 800ac94 <___vfiprintf_internal_r+0x884> + 800b65c: d8800844 addi r2,sp,33 + 800b660: d8801615 stw r2,88(sp) + 800b664: 00800044 movi r2,1 + 800b668: d8801715 stw r2,92(sp) + 800b66c: d8c01804 addi r3,sp,96 + 800b670: 01400044 movi r5,1 + 800b674: 003d6806 br 800ac18 <___vfiprintf_internal_r+0x808> + 800b678: d9800845 stb r6,33(sp) + 800b67c: 003c5506 br 800a7d4 <___vfiprintf_internal_r+0x3c4> + 800b680: 482b883a mov r21,r9 + 800b684: dd000315 stw r20,12(sp) + 800b688: 482d883a mov r22,r9 + 800b68c: 003d4906 br 800abb4 <___vfiprintf_internal_r+0x7a4> + 800b690: d9800845 stb r6,33(sp) + 800b694: 003cd906 br 800a9fc <___vfiprintf_internal_r+0x5ec> + 800b698: d9800845 stb r6,33(sp) + 800b69c: 003ce906 br 800aa44 <___vfiprintf_internal_r+0x634> + 800b6a0: d9800845 stb r6,33(sp) + 800b6a4: 003c8a06 br 800a8d0 <___vfiprintf_internal_r+0x4c0> + 800b6a8: d9800845 stb r6,33(sp) + 800b6ac: 003dd206 br 800adf8 <___vfiprintf_internal_r+0x9e8> + 800b6b0: d9800845 stb r6,33(sp) + 800b6b4: 003ddd06 br 800ae2c <___vfiprintf_internal_r+0xa1c> + 800b6b8: 301f883a mov r15,r6 + 800b6bc: 39dd8104 addi r7,r7,30212 + 800b6c0: 003f2306 br 800b350 <___vfiprintf_internal_r+0xf40> + 800b6c4: d9800845 stb r6,33(sp) + 800b6c8: 003d1606 br 800ab24 <___vfiprintf_internal_r+0x714> + 800b6cc: d9800845 stb r6,33(sp) + 800b6d0: 003d0406 br 800aae4 <___vfiprintf_internal_r+0x6d4> + 800b6d4: d9800845 stb r6,33(sp) + 800b6d8: 003cb806 br 800a9bc <___vfiprintf_internal_r+0x5ac> + 800b6dc: d9800845 stb r6,33(sp) + 800b6e0: 003ddf06 br 800ae60 <___vfiprintf_internal_r+0xa50> + 800b6e4: 29800044 addi r6,r5,1 + 800b6e8: 39dd8104 addi r7,r7,30212 + 800b6ec: 003db106 br 800adb4 <___vfiprintf_internal_r+0x9a4> + 800b6f0: 181b883a mov r13,r3 + 800b6f4: 280d883a mov r6,r5 + 800b6f8: 39dd7d04 addi r7,r7,30196 + 800b6fc: 003e7306 br 800b0cc <___vfiprintf_internal_r+0xcbc> + 800b700: 00bfffc4 movi r2,-1 + 800b704: d8800015 stw r2,0(sp) + 800b708: 003c1706 br 800a768 <___vfiprintf_internal_r+0x358> + 800b70c: d8800317 ldw r2,12(sp) + 800b710: 12400017 ldw r9,0(r2) + 800b714: 15c00104 addi r23,r2,4 + 800b718: 4800010e bge r9,zero,800b720 <___vfiprintf_internal_r+0x1310> + 800b71c: 027fffc4 movi r9,-1 + 800b720: e0800043 ldbu r2,1(fp) + 800b724: ddc00315 stw r23,12(sp) + 800b728: 2039883a mov fp,r4 + 800b72c: 10803fcc andi r2,r2,255 + 800b730: 1080201c xori r2,r2,128 + 800b734: 10bfe004 addi r2,r2,-128 + 800b738: 003b8406 br 800a54c <___vfiprintf_internal_r+0x13c> + +0800b73c <__vfiprintf_internal>: + 800b73c: 00820174 movhi r2,2053 + 800b740: 300f883a mov r7,r6 + 800b744: 280d883a mov r6,r5 + 800b748: 200b883a mov r5,r4 + 800b74c: 1132af17 ldw r4,-13636(r2) + 800b750: 800a4101 jmpi 800a410 <___vfiprintf_internal_r> + +0800b754 <__sbprintf>: + 800b754: 2880030b ldhu r2,12(r5) + 800b758: 2b001917 ldw r12,100(r5) + 800b75c: 2ac0038b ldhu r11,14(r5) + 800b760: 2a800717 ldw r10,28(r5) + 800b764: 2a400917 ldw r9,36(r5) + 800b768: defee204 addi sp,sp,-1144 + 800b76c: da001a04 addi r8,sp,104 + 800b770: 00c10004 movi r3,1024 + 800b774: dc011a15 stw r16,1128(sp) + 800b778: 10bfff4c andi r2,r2,65533 + 800b77c: 2821883a mov r16,r5 + 800b780: d80b883a mov r5,sp + 800b784: dc811c15 stw r18,1136(sp) + 800b788: dc411b15 stw r17,1132(sp) + 800b78c: dfc11d15 stw ra,1140(sp) + 800b790: 2025883a mov r18,r4 + 800b794: d880030d sth r2,12(sp) + 800b798: db001915 stw r12,100(sp) + 800b79c: dac0038d sth r11,14(sp) + 800b7a0: da800715 stw r10,28(sp) + 800b7a4: da400915 stw r9,36(sp) + 800b7a8: da000015 stw r8,0(sp) + 800b7ac: da000415 stw r8,16(sp) + 800b7b0: d8c00215 stw r3,8(sp) + 800b7b4: d8c00515 stw r3,20(sp) + 800b7b8: d8000615 stw zero,24(sp) + 800b7bc: 800a4100 call 800a410 <___vfiprintf_internal_r> + 800b7c0: 1023883a mov r17,r2 + 800b7c4: 10000d0e bge r2,zero,800b7fc <__sbprintf+0xa8> + 800b7c8: d880030b ldhu r2,12(sp) + 800b7cc: 1080100c andi r2,r2,64 + 800b7d0: 10000326 beq r2,zero,800b7e0 <__sbprintf+0x8c> + 800b7d4: 8080030b ldhu r2,12(r16) + 800b7d8: 10801014 ori r2,r2,64 + 800b7dc: 8080030d sth r2,12(r16) + 800b7e0: 8805883a mov r2,r17 + 800b7e4: dfc11d17 ldw ra,1140(sp) + 800b7e8: dc811c17 ldw r18,1136(sp) + 800b7ec: dc411b17 ldw r17,1132(sp) + 800b7f0: dc011a17 ldw r16,1128(sp) + 800b7f4: dec11e04 addi sp,sp,1144 + 800b7f8: f800283a ret + 800b7fc: d80b883a mov r5,sp + 800b800: 9009883a mov r4,r18 + 800b804: 8006cdc0 call 8006cdc <_fflush_r> + 800b808: 103fef26 beq r2,zero,800b7c8 <__sbprintf+0x74> + 800b80c: 047fffc4 movi r17,-1 + 800b810: 003fed06 br 800b7c8 <__sbprintf+0x74> + +0800b814 <__swbuf_r>: + 800b814: defffb04 addi sp,sp,-20 + 800b818: dc800215 stw r18,8(sp) + 800b81c: dc400115 stw r17,4(sp) + 800b820: dc000015 stw r16,0(sp) + 800b824: dfc00415 stw ra,16(sp) + 800b828: dcc00315 stw r19,12(sp) + 800b82c: 2023883a mov r17,r4 + 800b830: 2825883a mov r18,r5 + 800b834: 3021883a mov r16,r6 + 800b838: 20000226 beq r4,zero,800b844 <__swbuf_r+0x30> + 800b83c: 20800e17 ldw r2,56(r4) + 800b840: 10003e26 beq r2,zero,800b93c <__swbuf_r+0x128> + 800b844: 80800617 ldw r2,24(r16) + 800b848: 80c0030b ldhu r3,12(r16) + 800b84c: 80800215 stw r2,8(r16) + 800b850: 1880020c andi r2,r3,8 + 800b854: 10001f26 beq r2,zero,800b8d4 <__swbuf_r+0xc0> + 800b858: 80800417 ldw r2,16(r16) + 800b85c: 10001d26 beq r2,zero,800b8d4 <__swbuf_r+0xc0> + 800b860: 1908000c andi r4,r3,8192 + 800b864: 94c03fcc andi r19,r18,255 + 800b868: 20002326 beq r4,zero,800b8f8 <__swbuf_r+0xe4> + 800b86c: 80c00017 ldw r3,0(r16) + 800b870: 81000517 ldw r4,20(r16) + 800b874: 1885c83a sub r2,r3,r2 + 800b878: 1100290e bge r2,r4,800b920 <__swbuf_r+0x10c> + 800b87c: 10800044 addi r2,r2,1 + 800b880: 81000217 ldw r4,8(r16) + 800b884: 19400044 addi r5,r3,1 + 800b888: 81400015 stw r5,0(r16) + 800b88c: 213fffc4 addi r4,r4,-1 + 800b890: 81000215 stw r4,8(r16) + 800b894: 1c800005 stb r18,0(r3) + 800b898: 80c00517 ldw r3,20(r16) + 800b89c: 18802926 beq r3,r2,800b944 <__swbuf_r+0x130> + 800b8a0: 8080030b ldhu r2,12(r16) + 800b8a4: 1080004c andi r2,r2,1 + 800b8a8: 10000226 beq r2,zero,800b8b4 <__swbuf_r+0xa0> + 800b8ac: 98800298 cmpnei r2,r19,10 + 800b8b0: 10002426 beq r2,zero,800b944 <__swbuf_r+0x130> + 800b8b4: 9805883a mov r2,r19 + 800b8b8: dfc00417 ldw ra,16(sp) + 800b8bc: dcc00317 ldw r19,12(sp) + 800b8c0: dc800217 ldw r18,8(sp) + 800b8c4: dc400117 ldw r17,4(sp) + 800b8c8: dc000017 ldw r16,0(sp) + 800b8cc: dec00504 addi sp,sp,20 + 800b8d0: f800283a ret + 800b8d4: 800b883a mov r5,r16 + 800b8d8: 8809883a mov r4,r17 + 800b8dc: 800507c0 call 800507c <__swsetup_r> + 800b8e0: 10001c1e bne r2,zero,800b954 <__swbuf_r+0x140> + 800b8e4: 80c0030b ldhu r3,12(r16) + 800b8e8: 80800417 ldw r2,16(r16) + 800b8ec: 94c03fcc andi r19,r18,255 + 800b8f0: 1908000c andi r4,r3,8192 + 800b8f4: 203fdd1e bne r4,zero,800b86c <__swbuf_r+0x58> + 800b8f8: 81001917 ldw r4,100(r16) + 800b8fc: 18c80014 ori r3,r3,8192 + 800b900: 0177ffc4 movi r5,-8193 + 800b904: 2148703a and r4,r4,r5 + 800b908: 80c0030d sth r3,12(r16) + 800b90c: 80c00017 ldw r3,0(r16) + 800b910: 81001915 stw r4,100(r16) + 800b914: 81000517 ldw r4,20(r16) + 800b918: 1885c83a sub r2,r3,r2 + 800b91c: 113fd716 blt r2,r4,800b87c <__swbuf_r+0x68> + 800b920: 800b883a mov r5,r16 + 800b924: 8809883a mov r4,r17 + 800b928: 8006cdc0 call 8006cdc <_fflush_r> + 800b92c: 1000091e bne r2,zero,800b954 <__swbuf_r+0x140> + 800b930: 80c00017 ldw r3,0(r16) + 800b934: 00800044 movi r2,1 + 800b938: 003fd106 br 800b880 <__swbuf_r+0x6c> + 800b93c: 80070600 call 8007060 <__sinit> + 800b940: 003fc006 br 800b844 <__swbuf_r+0x30> + 800b944: 800b883a mov r5,r16 + 800b948: 8809883a mov r4,r17 + 800b94c: 8006cdc0 call 8006cdc <_fflush_r> + 800b950: 103fd826 beq r2,zero,800b8b4 <__swbuf_r+0xa0> + 800b954: 04ffffc4 movi r19,-1 + 800b958: 003fd606 br 800b8b4 <__swbuf_r+0xa0> + +0800b95c <__swbuf>: + 800b95c: 00820174 movhi r2,2053 + 800b960: 280d883a mov r6,r5 + 800b964: 200b883a mov r5,r4 + 800b968: 1132af17 ldw r4,-13636(r2) + 800b96c: 800b8141 jmpi 800b814 <__swbuf_r> + +0800b970 <_write_r>: + 800b970: defffe04 addi sp,sp,-8 + 800b974: 2805883a mov r2,r5 + 800b978: dc000015 stw r16,0(sp) + 800b97c: 300b883a mov r5,r6 + 800b980: 2021883a mov r16,r4 + 800b984: 380d883a mov r6,r7 + 800b988: 1009883a mov r4,r2 + 800b98c: 00820174 movhi r2,2053 + 800b990: dfc00115 stw ra,4(sp) + 800b994: 1032f015 stw zero,-13376(r2) + 800b998: 8022c3c0 call 8022c3c + 800b99c: 10ffffd8 cmpnei r3,r2,-1 + 800b9a0: 18000426 beq r3,zero,800b9b4 <_write_r+0x44> + 800b9a4: dfc00117 ldw ra,4(sp) + 800b9a8: dc000017 ldw r16,0(sp) + 800b9ac: dec00204 addi sp,sp,8 + 800b9b0: f800283a ret + 800b9b4: 00c20174 movhi r3,2053 + 800b9b8: 18f2f017 ldw r3,-13376(r3) + 800b9bc: 183ff926 beq r3,zero,800b9a4 <_write_r+0x34> + 800b9c0: 80c00015 stw r3,0(r16) + 800b9c4: dfc00117 ldw ra,4(sp) + 800b9c8: dc000017 ldw r16,0(sp) + 800b9cc: dec00204 addi sp,sp,8 + 800b9d0: f800283a ret + +0800b9d4 <_close_r>: + 800b9d4: defffe04 addi sp,sp,-8 + 800b9d8: dc000015 stw r16,0(sp) + 800b9dc: 00820174 movhi r2,2053 + 800b9e0: 2021883a mov r16,r4 + 800b9e4: 2809883a mov r4,r5 + 800b9e8: dfc00115 stw ra,4(sp) + 800b9ec: 1032f015 stw zero,-13376(r2) + 800b9f0: 8022a600 call 8022a60 + 800b9f4: 10ffffd8 cmpnei r3,r2,-1 + 800b9f8: 18000426 beq r3,zero,800ba0c <_close_r+0x38> + 800b9fc: dfc00117 ldw ra,4(sp) + 800ba00: dc000017 ldw r16,0(sp) + 800ba04: dec00204 addi sp,sp,8 + 800ba08: f800283a ret + 800ba0c: 00c20174 movhi r3,2053 + 800ba10: 18f2f017 ldw r3,-13376(r3) + 800ba14: 183ff926 beq r3,zero,800b9fc <_close_r+0x28> + 800ba18: 80c00015 stw r3,0(r16) + 800ba1c: dfc00117 ldw ra,4(sp) + 800ba20: dc000017 ldw r16,0(sp) + 800ba24: dec00204 addi sp,sp,8 + 800ba28: f800283a ret + +0800ba2c <_calloc_r>: + 800ba2c: 298b383a mul r5,r5,r6 + 800ba30: deffff04 addi sp,sp,-4 + 800ba34: dfc00015 stw ra,0(sp) + 800ba38: 8007ddc0 call 8007ddc <_malloc_r> + 800ba3c: 1007883a mov r3,r2 + 800ba40: 10000c26 beq r2,zero,800ba74 <_calloc_r+0x48> + 800ba44: 11bfff17 ldw r6,-4(r2) + 800ba48: 00bfff04 movi r2,-4 + 800ba4c: 308c703a and r6,r6,r2 + 800ba50: 31bfff04 addi r6,r6,-4 + 800ba54: 30800968 cmpgeui r2,r6,37 + 800ba58: 1000141e bne r2,zero,800baac <_calloc_r+0x80> + 800ba5c: 30800530 cmpltui r2,r6,20 + 800ba60: 10000826 beq r2,zero,800ba84 <_calloc_r+0x58> + 800ba64: 1805883a mov r2,r3 + 800ba68: 10000015 stw zero,0(r2) + 800ba6c: 10000115 stw zero,4(r2) + 800ba70: 10000215 stw zero,8(r2) + 800ba74: 1805883a mov r2,r3 + 800ba78: dfc00017 ldw ra,0(sp) + 800ba7c: dec00104 addi sp,sp,4 + 800ba80: f800283a ret + 800ba84: 18000015 stw zero,0(r3) + 800ba88: 18000115 stw zero,4(r3) + 800ba8c: 30800728 cmpgeui r2,r6,28 + 800ba90: 10000e26 beq r2,zero,800bacc <_calloc_r+0xa0> + 800ba94: 18000215 stw zero,8(r3) + 800ba98: 18000315 stw zero,12(r3) + 800ba9c: 31800920 cmpeqi r6,r6,36 + 800baa0: 30000c1e bne r6,zero,800bad4 <_calloc_r+0xa8> + 800baa4: 18800404 addi r2,r3,16 + 800baa8: 003fef06 br 800ba68 <_calloc_r+0x3c> + 800baac: 1809883a mov r4,r3 + 800bab0: 000b883a mov r5,zero + 800bab4: 80088e40 call 80088e4 + 800bab8: 1007883a mov r3,r2 + 800babc: 1805883a mov r2,r3 + 800bac0: dfc00017 ldw ra,0(sp) + 800bac4: dec00104 addi sp,sp,4 + 800bac8: f800283a ret + 800bacc: 18800204 addi r2,r3,8 + 800bad0: 003fe506 br 800ba68 <_calloc_r+0x3c> + 800bad4: 18000415 stw zero,16(r3) + 800bad8: 18800604 addi r2,r3,24 + 800badc: 18000515 stw zero,20(r3) + 800bae0: 003fe106 br 800ba68 <_calloc_r+0x3c> + +0800bae4 <_fclose_r>: + 800bae4: defffc04 addi sp,sp,-16 + 800bae8: dfc00315 stw ra,12(sp) + 800baec: dc800215 stw r18,8(sp) + 800baf0: dc400115 stw r17,4(sp) + 800baf4: dc000015 stw r16,0(sp) + 800baf8: 28000726 beq r5,zero,800bb18 <_fclose_r+0x34> + 800bafc: 2023883a mov r17,r4 + 800bb00: 2821883a mov r16,r5 + 800bb04: 20000226 beq r4,zero,800bb10 <_fclose_r+0x2c> + 800bb08: 20800e17 ldw r2,56(r4) + 800bb0c: 10002726 beq r2,zero,800bbac <_fclose_r+0xc8> + 800bb10: 8080030f ldh r2,12(r16) + 800bb14: 1000081e bne r2,zero,800bb38 <_fclose_r+0x54> + 800bb18: 0025883a mov r18,zero + 800bb1c: 9005883a mov r2,r18 + 800bb20: dfc00317 ldw ra,12(sp) + 800bb24: dc800217 ldw r18,8(sp) + 800bb28: dc400117 ldw r17,4(sp) + 800bb2c: dc000017 ldw r16,0(sp) + 800bb30: dec00404 addi sp,sp,16 + 800bb34: f800283a ret + 800bb38: 800b883a mov r5,r16 + 800bb3c: 8809883a mov r4,r17 + 800bb40: 8006ab40 call 8006ab4 <__sflush_r> + 800bb44: 1025883a mov r18,r2 + 800bb48: 80800b17 ldw r2,44(r16) + 800bb4c: 10000426 beq r2,zero,800bb60 <_fclose_r+0x7c> + 800bb50: 81400717 ldw r5,28(r16) + 800bb54: 8809883a mov r4,r17 + 800bb58: 103ee83a callr r2 + 800bb5c: 10001716 blt r2,zero,800bbbc <_fclose_r+0xd8> + 800bb60: 8080030b ldhu r2,12(r16) + 800bb64: 1080200c andi r2,r2,128 + 800bb68: 1000181e bne r2,zero,800bbcc <_fclose_r+0xe8> + 800bb6c: 81400c17 ldw r5,48(r16) + 800bb70: 28000526 beq r5,zero,800bb88 <_fclose_r+0xa4> + 800bb74: 80801004 addi r2,r16,64 + 800bb78: 28800226 beq r5,r2,800bb84 <_fclose_r+0xa0> + 800bb7c: 8809883a mov r4,r17 + 800bb80: 80071c40 call 80071c4 <_free_r> + 800bb84: 80000c15 stw zero,48(r16) + 800bb88: 81401117 ldw r5,68(r16) + 800bb8c: 28000326 beq r5,zero,800bb9c <_fclose_r+0xb8> + 800bb90: 8809883a mov r4,r17 + 800bb94: 80071c40 call 80071c4 <_free_r> + 800bb98: 80001115 stw zero,68(r16) + 800bb9c: 80070700 call 8007070 <__sfp_lock_acquire> + 800bba0: 8000030d sth zero,12(r16) + 800bba4: 80070740 call 8007074 <__sfp_lock_release> + 800bba8: 003fdc06 br 800bb1c <_fclose_r+0x38> + 800bbac: 80070600 call 8007060 <__sinit> + 800bbb0: 8080030f ldh r2,12(r16) + 800bbb4: 103fd826 beq r2,zero,800bb18 <_fclose_r+0x34> + 800bbb8: 003fdf06 br 800bb38 <_fclose_r+0x54> + 800bbbc: 8080030b ldhu r2,12(r16) + 800bbc0: 04bfffc4 movi r18,-1 + 800bbc4: 1080200c andi r2,r2,128 + 800bbc8: 103fe826 beq r2,zero,800bb6c <_fclose_r+0x88> + 800bbcc: 81400417 ldw r5,16(r16) + 800bbd0: 8809883a mov r4,r17 + 800bbd4: 80071c40 call 80071c4 <_free_r> + 800bbd8: 003fe406 br 800bb6c <_fclose_r+0x88> + +0800bbdc : + 800bbdc: 00820174 movhi r2,2053 + 800bbe0: 200b883a mov r5,r4 + 800bbe4: 1132af17 ldw r4,-13636(r2) + 800bbe8: 800bae41 jmpi 800bae4 <_fclose_r> + +0800bbec <__fputwc>: + 800bbec: defff904 addi sp,sp,-28 + 800bbf0: dcc00415 stw r19,16(sp) + 800bbf4: dc800315 stw r18,12(sp) + 800bbf8: dc000115 stw r16,4(sp) + 800bbfc: dfc00615 stw ra,24(sp) + 800bc00: dd000515 stw r20,20(sp) + 800bc04: dc400215 stw r17,8(sp) + 800bc08: 2025883a mov r18,r4 + 800bc0c: 2827883a mov r19,r5 + 800bc10: 3021883a mov r16,r6 + 800bc14: 800bf040 call 800bf04 <__locale_mb_cur_max> + 800bc18: 10800058 cmpnei r2,r2,1 + 800bc1c: 1000071e bne r2,zero,800bc3c <__fputwc+0x50> + 800bc20: 98bfffc4 addi r2,r19,-1 + 800bc24: 10803fe8 cmpgeui r2,r2,255 + 800bc28: 1000041e bne r2,zero,800bc3c <__fputwc+0x50> + 800bc2c: 980b883a mov r5,r19 + 800bc30: dcc000c5 stb r19,3(sp) + 800bc34: 05000044 movi r20,1 + 800bc38: 00000a06 br 800bc64 <__fputwc+0x78> + 800bc3c: 81c01704 addi r7,r16,92 + 800bc40: 980d883a mov r6,r19 + 800bc44: d94000c4 addi r5,sp,3 + 800bc48: 9009883a mov r4,r18 + 800bc4c: 800c2fc0 call 800c2fc <_wcrtomb_r> + 800bc50: 1029883a mov r20,r2 + 800bc54: 10bfffd8 cmpnei r2,r2,-1 + 800bc58: 10003426 beq r2,zero,800bd2c <__fputwc+0x140> + 800bc5c: a0002926 beq r20,zero,800bd04 <__fputwc+0x118> + 800bc60: d94000c3 ldbu r5,3(sp) + 800bc64: 0023883a mov r17,zero + 800bc68: 00000a06 br 800bc94 <__fputwc+0xa8> + 800bc6c: 80800017 ldw r2,0(r16) + 800bc70: 11400005 stb r5,0(r2) + 800bc74: 80800017 ldw r2,0(r16) + 800bc78: 10800044 addi r2,r2,1 + 800bc7c: 80800015 stw r2,0(r16) + 800bc80: 8c400044 addi r17,r17,1 + 800bc84: d88000c4 addi r2,sp,3 + 800bc88: 1445883a add r2,r2,r17 + 800bc8c: 8d001d2e bgeu r17,r20,800bd04 <__fputwc+0x118> + 800bc90: 11400003 ldbu r5,0(r2) + 800bc94: 80800217 ldw r2,8(r16) + 800bc98: 10bfffc4 addi r2,r2,-1 + 800bc9c: 80800215 stw r2,8(r16) + 800bca0: 103ff20e bge r2,zero,800bc6c <__fputwc+0x80> + 800bca4: 80c00617 ldw r3,24(r16) + 800bca8: 10c01016 blt r2,r3,800bcec <__fputwc+0x100> + 800bcac: 80800017 ldw r2,0(r16) + 800bcb0: 11400005 stb r5,0(r2) + 800bcb4: 80800017 ldw r2,0(r16) + 800bcb8: 10c00003 ldbu r3,0(r2) + 800bcbc: 10800044 addi r2,r2,1 + 800bcc0: 18c002a0 cmpeqi r3,r3,10 + 800bcc4: 183fed26 beq r3,zero,800bc7c <__fputwc+0x90> + 800bcc8: 800d883a mov r6,r16 + 800bccc: 01400284 movi r5,10 + 800bcd0: 9009883a mov r4,r18 + 800bcd4: 800b8140 call 800b814 <__swbuf_r> + 800bcd8: 10bfffe0 cmpeqi r2,r2,-1 + 800bcdc: 10803fcc andi r2,r2,255 + 800bce0: 103fe726 beq r2,zero,800bc80 <__fputwc+0x94> + 800bce4: 053fffc4 movi r20,-1 + 800bce8: 00000706 br 800bd08 <__fputwc+0x11c> + 800bcec: 29403fcc andi r5,r5,255 + 800bcf0: 800d883a mov r6,r16 + 800bcf4: 9009883a mov r4,r18 + 800bcf8: 800b8140 call 800b814 <__swbuf_r> + 800bcfc: 10bfffe0 cmpeqi r2,r2,-1 + 800bd00: 003ff606 br 800bcdc <__fputwc+0xf0> + 800bd04: 9829883a mov r20,r19 + 800bd08: a005883a mov r2,r20 + 800bd0c: dfc00617 ldw ra,24(sp) + 800bd10: dd000517 ldw r20,20(sp) + 800bd14: dcc00417 ldw r19,16(sp) + 800bd18: dc800317 ldw r18,12(sp) + 800bd1c: dc400217 ldw r17,8(sp) + 800bd20: dc000117 ldw r16,4(sp) + 800bd24: dec00704 addi sp,sp,28 + 800bd28: f800283a ret + 800bd2c: 8080030b ldhu r2,12(r16) + 800bd30: 10801014 ori r2,r2,64 + 800bd34: 8080030d sth r2,12(r16) + 800bd38: 003ff306 br 800bd08 <__fputwc+0x11c> + +0800bd3c <_fputwc_r>: + 800bd3c: 3080030b ldhu r2,12(r6) + 800bd40: 10c8000c andi r3,r2,8192 + 800bd44: 1800051e bne r3,zero,800bd5c <_fputwc_r+0x20> + 800bd48: 30c01917 ldw r3,100(r6) + 800bd4c: 10880014 ori r2,r2,8192 + 800bd50: 3080030d sth r2,12(r6) + 800bd54: 18880014 ori r2,r3,8192 + 800bd58: 30801915 stw r2,100(r6) + 800bd5c: 800bbec1 jmpi 800bbec <__fputwc> + +0800bd60 : + 800bd60: defffc04 addi sp,sp,-16 + 800bd64: 00820174 movhi r2,2053 + 800bd68: dc000115 stw r16,4(sp) + 800bd6c: 1432af17 ldw r16,-13636(r2) + 800bd70: dc400215 stw r17,8(sp) + 800bd74: dfc00315 stw ra,12(sp) + 800bd78: 2023883a mov r17,r4 + 800bd7c: 80000226 beq r16,zero,800bd88 + 800bd80: 80800e17 ldw r2,56(r16) + 800bd84: 10001026 beq r2,zero,800bdc8 + 800bd88: 2880030b ldhu r2,12(r5) + 800bd8c: 10c8000c andi r3,r2,8192 + 800bd90: 1800051e bne r3,zero,800bda8 + 800bd94: 28c01917 ldw r3,100(r5) + 800bd98: 10880014 ori r2,r2,8192 + 800bd9c: 2880030d sth r2,12(r5) + 800bda0: 18880014 ori r2,r3,8192 + 800bda4: 28801915 stw r2,100(r5) + 800bda8: 280d883a mov r6,r5 + 800bdac: 8009883a mov r4,r16 + 800bdb0: 880b883a mov r5,r17 + 800bdb4: dfc00317 ldw ra,12(sp) + 800bdb8: dc400217 ldw r17,8(sp) + 800bdbc: dc000117 ldw r16,4(sp) + 800bdc0: dec00404 addi sp,sp,16 + 800bdc4: 800bbec1 jmpi 800bbec <__fputwc> + 800bdc8: 8009883a mov r4,r16 + 800bdcc: d9400015 stw r5,0(sp) + 800bdd0: 80070600 call 8007060 <__sinit> + 800bdd4: d9400017 ldw r5,0(sp) + 800bdd8: 003feb06 br 800bd88 + +0800bddc <_fstat_r>: + 800bddc: defffe04 addi sp,sp,-8 + 800bde0: 2805883a mov r2,r5 + 800bde4: dc000015 stw r16,0(sp) + 800bde8: 300b883a mov r5,r6 + 800bdec: 2021883a mov r16,r4 + 800bdf0: 1009883a mov r4,r2 + 800bdf4: 00820174 movhi r2,2053 + 800bdf8: dfc00115 stw ra,4(sp) + 800bdfc: 1032f015 stw zero,-13376(r2) + 800be00: 800f8dc0 call 800f8dc + 800be04: 10ffffd8 cmpnei r3,r2,-1 + 800be08: 18000426 beq r3,zero,800be1c <_fstat_r+0x40> + 800be0c: dfc00117 ldw ra,4(sp) + 800be10: dc000017 ldw r16,0(sp) + 800be14: dec00204 addi sp,sp,8 + 800be18: f800283a ret + 800be1c: 00c20174 movhi r3,2053 + 800be20: 18f2f017 ldw r3,-13376(r3) + 800be24: 183ff926 beq r3,zero,800be0c <_fstat_r+0x30> + 800be28: 80c00015 stw r3,0(r16) + 800be2c: dfc00117 ldw ra,4(sp) + 800be30: dc000017 ldw r16,0(sp) + 800be34: dec00204 addi sp,sp,8 + 800be38: f800283a ret + +0800be3c <_isatty_r>: + 800be3c: defffe04 addi sp,sp,-8 + 800be40: dc000015 stw r16,0(sp) + 800be44: 00820174 movhi r2,2053 + 800be48: 2021883a mov r16,r4 + 800be4c: 2809883a mov r4,r5 + 800be50: dfc00115 stw ra,4(sp) + 800be54: 1032f015 stw zero,-13376(r2) + 800be58: 800f9c80 call 800f9c8 + 800be5c: 10ffffd8 cmpnei r3,r2,-1 + 800be60: 18000426 beq r3,zero,800be74 <_isatty_r+0x38> + 800be64: dfc00117 ldw ra,4(sp) + 800be68: dc000017 ldw r16,0(sp) + 800be6c: dec00204 addi sp,sp,8 + 800be70: f800283a ret + 800be74: 00c20174 movhi r3,2053 + 800be78: 18f2f017 ldw r3,-13376(r3) + 800be7c: 183ff926 beq r3,zero,800be64 <_isatty_r+0x28> + 800be80: 80c00015 stw r3,0(r16) + 800be84: dfc00117 ldw ra,4(sp) + 800be88: dc000017 ldw r16,0(sp) + 800be8c: dec00204 addi sp,sp,8 + 800be90: f800283a ret + +0800be94 <_setlocale_r>: + 800be94: 30001826 beq r6,zero,800bef8 <_setlocale_r+0x64> + 800be98: 01420134 movhi r5,2052 + 800be9c: defffe04 addi sp,sp,-8 + 800bea0: 295d8604 addi r5,r5,30232 + 800bea4: 3009883a mov r4,r6 + 800bea8: dc000015 stw r16,0(sp) + 800beac: dfc00115 stw ra,4(sp) + 800beb0: 3021883a mov r16,r6 + 800beb4: 800c2240 call 800c224 + 800beb8: 1000061e bne r2,zero,800bed4 <_setlocale_r+0x40> + 800bebc: 00820134 movhi r2,2052 + 800bec0: 109d8504 addi r2,r2,30228 + 800bec4: dfc00117 ldw ra,4(sp) + 800bec8: dc000017 ldw r16,0(sp) + 800becc: dec00204 addi sp,sp,8 + 800bed0: f800283a ret + 800bed4: 01420134 movhi r5,2052 + 800bed8: 295d8504 addi r5,r5,30228 + 800bedc: 8009883a mov r4,r16 + 800bee0: 800c2240 call 800c224 + 800bee4: 103ff526 beq r2,zero,800bebc <_setlocale_r+0x28> + 800bee8: 80800003 ldbu r2,0(r16) + 800beec: 103ff326 beq r2,zero,800bebc <_setlocale_r+0x28> + 800bef0: 0005883a mov r2,zero + 800bef4: 003ff306 br 800bec4 <_setlocale_r+0x30> + 800bef8: 00820134 movhi r2,2052 + 800befc: 109d8504 addi r2,r2,30228 + 800bf00: f800283a ret + +0800bf04 <__locale_mb_cur_max>: + 800bf04: 00820174 movhi r2,2053 + 800bf08: 10b0f507 ldb r2,-15404(r2) + 800bf0c: f800283a ret + +0800bf10 : + 800bf10: 00820174 movhi r2,2053 + 800bf14: 280d883a mov r6,r5 + 800bf18: 200b883a mov r5,r4 + 800bf1c: 1132af17 ldw r4,-13636(r2) + 800bf20: 800be941 jmpi 800be94 <_setlocale_r> + +0800bf24 <_lseek_r>: + 800bf24: defffe04 addi sp,sp,-8 + 800bf28: 2805883a mov r2,r5 + 800bf2c: dc000015 stw r16,0(sp) + 800bf30: 300b883a mov r5,r6 + 800bf34: 2021883a mov r16,r4 + 800bf38: 380d883a mov r6,r7 + 800bf3c: 1009883a mov r4,r2 + 800bf40: 00820174 movhi r2,2053 + 800bf44: dfc00115 stw ra,4(sp) + 800bf48: 1032f015 stw zero,-13376(r2) + 800bf4c: 800faa80 call 800faa8 + 800bf50: 10ffffd8 cmpnei r3,r2,-1 + 800bf54: 18000426 beq r3,zero,800bf68 <_lseek_r+0x44> + 800bf58: dfc00117 ldw ra,4(sp) + 800bf5c: dc000017 ldw r16,0(sp) + 800bf60: dec00204 addi sp,sp,8 + 800bf64: f800283a ret + 800bf68: 00c20174 movhi r3,2053 + 800bf6c: 18f2f017 ldw r3,-13376(r3) + 800bf70: 183ff926 beq r3,zero,800bf58 <_lseek_r+0x34> + 800bf74: 80c00015 stw r3,0(r16) + 800bf78: dfc00117 ldw ra,4(sp) + 800bf7c: dc000017 ldw r16,0(sp) + 800bf80: dec00204 addi sp,sp,8 + 800bf84: f800283a ret + +0800bf88 <_mbtowc_r>: + 800bf88: 00820174 movhi r2,2053 + 800bf8c: 10b0e417 ldw r2,-15472(r2) + 800bf90: 1000683a jmp r2 + +0800bf94 <__ascii_mbtowc>: + 800bf94: deffff04 addi sp,sp,-4 + 800bf98: 28000826 beq r5,zero,800bfbc <__ascii_mbtowc+0x28> + 800bf9c: 30000926 beq r6,zero,800bfc4 <__ascii_mbtowc+0x30> + 800bfa0: 38000b26 beq r7,zero,800bfd0 <__ascii_mbtowc+0x3c> + 800bfa4: 30800003 ldbu r2,0(r6) + 800bfa8: 28800015 stw r2,0(r5) + 800bfac: 30800003 ldbu r2,0(r6) + 800bfb0: 1004c03a cmpne r2,r2,zero + 800bfb4: dec00104 addi sp,sp,4 + 800bfb8: f800283a ret + 800bfbc: d80b883a mov r5,sp + 800bfc0: 303ff71e bne r6,zero,800bfa0 <__ascii_mbtowc+0xc> + 800bfc4: 0005883a mov r2,zero + 800bfc8: dec00104 addi sp,sp,4 + 800bfcc: f800283a ret + 800bfd0: 00bfff84 movi r2,-2 + 800bfd4: 003ff706 br 800bfb4 <__ascii_mbtowc+0x20> + +0800bfd8 <_read_r>: + 800bfd8: defffe04 addi sp,sp,-8 + 800bfdc: 2805883a mov r2,r5 + 800bfe0: dc000015 stw r16,0(sp) + 800bfe4: 300b883a mov r5,r6 + 800bfe8: 2021883a mov r16,r4 + 800bfec: 380d883a mov r6,r7 + 800bff0: 1009883a mov r4,r2 + 800bff4: 00820174 movhi r2,2053 + 800bff8: dfc00115 stw ra,4(sp) + 800bffc: 1032f015 stw zero,-13376(r2) + 800c000: 8022bcc0 call 8022bcc + 800c004: 10ffffd8 cmpnei r3,r2,-1 + 800c008: 18000426 beq r3,zero,800c01c <_read_r+0x44> + 800c00c: dfc00117 ldw ra,4(sp) + 800c010: dc000017 ldw r16,0(sp) + 800c014: dec00204 addi sp,sp,8 + 800c018: f800283a ret + 800c01c: 00c20174 movhi r3,2053 + 800c020: 18f2f017 ldw r3,-13376(r3) + 800c024: 183ff926 beq r3,zero,800c00c <_read_r+0x34> + 800c028: 80c00015 stw r3,0(r16) + 800c02c: dfc00117 ldw ra,4(sp) + 800c030: dc000017 ldw r16,0(sp) + 800c034: dec00204 addi sp,sp,8 + 800c038: f800283a ret + +0800c03c : + 800c03c: 2080030b ldhu r2,12(r4) + 800c040: 1080024c andi r2,r2,9 + 800c044: 10800258 cmpnei r2,r2,9 + 800c048: 10000226 beq r2,zero,800c054 + 800c04c: 0005883a mov r2,zero + 800c050: f800283a ret + 800c054: 8006d3c1 jmpi 8006d3c + +0800c058 <__srefill_r>: + 800c058: defffc04 addi sp,sp,-16 + 800c05c: dc400115 stw r17,4(sp) + 800c060: dc000015 stw r16,0(sp) + 800c064: dfc00315 stw ra,12(sp) + 800c068: dc800215 stw r18,8(sp) + 800c06c: 2023883a mov r17,r4 + 800c070: 2821883a mov r16,r5 + 800c074: 20000226 beq r4,zero,800c080 <__srefill_r+0x28> + 800c078: 20800e17 ldw r2,56(r4) + 800c07c: 10003a26 beq r2,zero,800c168 <__srefill_r+0x110> + 800c080: 80c0030b ldhu r3,12(r16) + 800c084: 1908000c andi r4,r3,8192 + 800c088: 1805883a mov r2,r3 + 800c08c: 2000071e bne r4,zero,800c0ac <__srefill_r+0x54> + 800c090: 81001917 ldw r4,100(r16) + 800c094: 18880014 ori r2,r3,8192 + 800c098: 00f7ffc4 movi r3,-8193 + 800c09c: 20c8703a and r4,r4,r3 + 800c0a0: 8080030d sth r2,12(r16) + 800c0a4: 1007883a mov r3,r2 + 800c0a8: 81001915 stw r4,100(r16) + 800c0ac: 80000115 stw zero,4(r16) + 800c0b0: 1100080c andi r4,r2,32 + 800c0b4: 20004d1e bne r4,zero,800c1ec <__srefill_r+0x194> + 800c0b8: 1100010c andi r4,r2,4 + 800c0bc: 20001c1e bne r4,zero,800c130 <__srefill_r+0xd8> + 800c0c0: 1100040c andi r4,r2,16 + 800c0c4: 20005126 beq r4,zero,800c20c <__srefill_r+0x1b4> + 800c0c8: 1080020c andi r2,r2,8 + 800c0cc: 1000371e bne r2,zero,800c1ac <__srefill_r+0x154> + 800c0d0: 18c00114 ori r3,r3,4 + 800c0d4: 80c0030d sth r3,12(r16) + 800c0d8: 80800417 ldw r2,16(r16) + 800c0dc: 10003c26 beq r2,zero,800c1d0 <__srefill_r+0x178> + 800c0e0: 8480030b ldhu r18,12(r16) + 800c0e4: 908000cc andi r2,r18,3 + 800c0e8: 1000211e bne r2,zero,800c170 <__srefill_r+0x118> + 800c0ec: 81800417 ldw r6,16(r16) + 800c0f0: 80800817 ldw r2,32(r16) + 800c0f4: 81c00517 ldw r7,20(r16) + 800c0f8: 81400717 ldw r5,28(r16) + 800c0fc: 81800015 stw r6,0(r16) + 800c100: 8809883a mov r4,r17 + 800c104: 103ee83a callr r2 + 800c108: 1007883a mov r3,r2 + 800c10c: 80800115 stw r2,4(r16) + 800c110: 0005883a mov r2,zero + 800c114: 00c0370e bge zero,r3,800c1f4 <__srefill_r+0x19c> + 800c118: dfc00317 ldw ra,12(sp) + 800c11c: dc800217 ldw r18,8(sp) + 800c120: dc400117 ldw r17,4(sp) + 800c124: dc000017 ldw r16,0(sp) + 800c128: dec00404 addi sp,sp,16 + 800c12c: f800283a ret + 800c130: 81400c17 ldw r5,48(r16) + 800c134: 283fe826 beq r5,zero,800c0d8 <__srefill_r+0x80> + 800c138: 80801004 addi r2,r16,64 + 800c13c: 28800226 beq r5,r2,800c148 <__srefill_r+0xf0> + 800c140: 8809883a mov r4,r17 + 800c144: 80071c40 call 80071c4 <_free_r> + 800c148: 80800f17 ldw r2,60(r16) + 800c14c: 80000c15 stw zero,48(r16) + 800c150: 80800115 stw r2,4(r16) + 800c154: 103fe026 beq r2,zero,800c0d8 <__srefill_r+0x80> + 800c158: 80c00e17 ldw r3,56(r16) + 800c15c: 0005883a mov r2,zero + 800c160: 80c00015 stw r3,0(r16) + 800c164: 003fec06 br 800c118 <__srefill_r+0xc0> + 800c168: 80070600 call 8007060 <__sinit> + 800c16c: 003fc406 br 800c080 <__srefill_r+0x28> + 800c170: 00820174 movhi r2,2053 + 800c174: 1132ae17 ldw r4,-13640(r2) + 800c178: 01420074 movhi r5,2049 + 800c17c: 00800044 movi r2,1 + 800c180: 8080030d sth r2,12(r16) + 800c184: 29700f04 addi r5,r5,-16324 + 800c188: 80079840 call 8007984 <_fwalk> + 800c18c: 9080024c andi r2,r18,9 + 800c190: 8480030d sth r18,12(r16) + 800c194: 10800258 cmpnei r2,r2,9 + 800c198: 103fd41e bne r2,zero,800c0ec <__srefill_r+0x94> + 800c19c: 800b883a mov r5,r16 + 800c1a0: 8809883a mov r4,r17 + 800c1a4: 8006ab40 call 8006ab4 <__sflush_r> + 800c1a8: 003fd006 br 800c0ec <__srefill_r+0x94> + 800c1ac: 800b883a mov r5,r16 + 800c1b0: 8809883a mov r4,r17 + 800c1b4: 8006cdc0 call 8006cdc <_fflush_r> + 800c1b8: 10000c1e bne r2,zero,800c1ec <__srefill_r+0x194> + 800c1bc: 80c0030b ldhu r3,12(r16) + 800c1c0: 80000215 stw zero,8(r16) + 800c1c4: 80000615 stw zero,24(r16) + 800c1c8: 18fffdcc andi r3,r3,65527 + 800c1cc: 003fc006 br 800c0d0 <__srefill_r+0x78> + 800c1d0: 800b883a mov r5,r16 + 800c1d4: 8809883a mov r4,r17 + 800c1d8: 8007ca00 call 8007ca0 <__smakebuf_r> + 800c1dc: 003fc006 br 800c0e0 <__srefill_r+0x88> + 800c1e0: 10801014 ori r2,r2,64 + 800c1e4: 80000115 stw zero,4(r16) + 800c1e8: 8080030d sth r2,12(r16) + 800c1ec: 00bfffc4 movi r2,-1 + 800c1f0: 003fc906 br 800c118 <__srefill_r+0xc0> + 800c1f4: 8080030b ldhu r2,12(r16) + 800c1f8: 183ff91e bne r3,zero,800c1e0 <__srefill_r+0x188> + 800c1fc: 10800814 ori r2,r2,32 + 800c200: 8080030d sth r2,12(r16) + 800c204: 00bfffc4 movi r2,-1 + 800c208: 003fc306 br 800c118 <__srefill_r+0xc0> + 800c20c: 00800244 movi r2,9 + 800c210: 88800015 stw r2,0(r17) + 800c214: 18c01014 ori r3,r3,64 + 800c218: 80c0030d sth r3,12(r16) + 800c21c: 00bfffc4 movi r2,-1 + 800c220: 003fbd06 br 800c118 <__srefill_r+0xc0> + +0800c224 : + 800c224: 2144b03a or r2,r4,r5 + 800c228: 108000cc andi r2,r2,3 + 800c22c: 1000171e bne r2,zero,800c28c + 800c230: 20800017 ldw r2,0(r4) + 800c234: 28c00017 ldw r3,0(r5) + 800c238: 10c0141e bne r2,r3,800c28c + 800c23c: 027fbff4 movhi r9,65279 + 800c240: 4a7fbfc4 addi r9,r9,-257 + 800c244: 1247883a add r3,r2,r9 + 800c248: 02202074 movhi r8,32897 + 800c24c: 0084303a nor r2,zero,r2 + 800c250: 1884703a and r2,r3,r2 + 800c254: 42202004 addi r8,r8,-32640 + 800c258: 1204703a and r2,r2,r8 + 800c25c: 10000226 beq r2,zero,800c268 + 800c260: 00002406 br 800c2f4 + 800c264: 1000231e bne r2,zero,800c2f4 + 800c268: 21000104 addi r4,r4,4 + 800c26c: 20c00017 ldw r3,0(r4) + 800c270: 29400104 addi r5,r5,4 + 800c274: 29800017 ldw r6,0(r5) + 800c278: 1a45883a add r2,r3,r9 + 800c27c: 00ce303a nor r7,zero,r3 + 800c280: 11c4703a and r2,r2,r7 + 800c284: 1204703a and r2,r2,r8 + 800c288: 19bff626 beq r3,r6,800c264 + 800c28c: 20800003 ldbu r2,0(r4) + 800c290: 10c03fcc andi r3,r2,255 + 800c294: 18c0201c xori r3,r3,128 + 800c298: 18ffe004 addi r3,r3,-128 + 800c29c: 18000d26 beq r3,zero,800c2d4 + 800c2a0: 29800007 ldb r6,0(r5) + 800c2a4: 10803fcc andi r2,r2,255 + 800c2a8: 19800326 beq r3,r6,800c2b8 + 800c2ac: 00000a06 br 800c2d8 + 800c2b0: 29800007 ldb r6,0(r5) + 800c2b4: 11800b1e bne r2,r6,800c2e4 + 800c2b8: 21000044 addi r4,r4,1 + 800c2bc: 20c00003 ldbu r3,0(r4) + 800c2c0: 29400044 addi r5,r5,1 + 800c2c4: 18803fcc andi r2,r3,255 + 800c2c8: 1080201c xori r2,r2,128 + 800c2cc: 10bfe004 addi r2,r2,-128 + 800c2d0: 103ff71e bne r2,zero,800c2b0 + 800c2d4: 0005883a mov r2,zero + 800c2d8: 28c00003 ldbu r3,0(r5) + 800c2dc: 10c5c83a sub r2,r2,r3 + 800c2e0: f800283a ret + 800c2e4: 18803fcc andi r2,r3,255 + 800c2e8: 28c00003 ldbu r3,0(r5) + 800c2ec: 10c5c83a sub r2,r2,r3 + 800c2f0: f800283a ret + 800c2f4: 0005883a mov r2,zero + 800c2f8: f800283a ret + +0800c2fc <_wcrtomb_r>: + 800c2fc: defffa04 addi sp,sp,-24 + 800c300: dc400415 stw r17,16(sp) + 800c304: dc000315 stw r16,12(sp) + 800c308: 00820174 movhi r2,2053 + 800c30c: dfc00515 stw ra,20(sp) + 800c310: 2021883a mov r16,r4 + 800c314: 3823883a mov r17,r7 + 800c318: 10b0e317 ldw r2,-15476(r2) + 800c31c: 28000826 beq r5,zero,800c340 <_wcrtomb_r+0x44> + 800c320: 103ee83a callr r2 + 800c324: 10ffffd8 cmpnei r3,r2,-1 + 800c328: 18000a26 beq r3,zero,800c354 <_wcrtomb_r+0x58> + 800c32c: dfc00517 ldw ra,20(sp) + 800c330: dc400417 ldw r17,16(sp) + 800c334: dc000317 ldw r16,12(sp) + 800c338: dec00604 addi sp,sp,24 + 800c33c: f800283a ret + 800c340: 000d883a mov r6,zero + 800c344: d9400084 addi r5,sp,2 + 800c348: 103ee83a callr r2 + 800c34c: 10ffffd8 cmpnei r3,r2,-1 + 800c350: 183ff61e bne r3,zero,800c32c <_wcrtomb_r+0x30> + 800c354: 00802284 movi r2,138 + 800c358: 88000015 stw zero,0(r17) + 800c35c: 80800015 stw r2,0(r16) + 800c360: 00bfffc4 movi r2,-1 + 800c364: 003ff106 br 800c32c <_wcrtomb_r+0x30> + +0800c368 : + 800c368: defffa04 addi sp,sp,-24 + 800c36c: 00820174 movhi r2,2053 + 800c370: dc400415 stw r17,16(sp) + 800c374: dc000315 stw r16,12(sp) + 800c378: dfc00515 stw ra,20(sp) + 800c37c: 1432af17 ldw r16,-13636(r2) + 800c380: 00820174 movhi r2,2053 + 800c384: 3023883a mov r17,r6 + 800c388: 10b0e317 ldw r2,-15476(r2) + 800c38c: 300f883a mov r7,r6 + 800c390: 20000b26 beq r4,zero,800c3c0 + 800c394: 280d883a mov r6,r5 + 800c398: 200b883a mov r5,r4 + 800c39c: 8009883a mov r4,r16 + 800c3a0: 103ee83a callr r2 + 800c3a4: 10ffffd8 cmpnei r3,r2,-1 + 800c3a8: 18000b26 beq r3,zero,800c3d8 + 800c3ac: dfc00517 ldw ra,20(sp) + 800c3b0: dc400417 ldw r17,16(sp) + 800c3b4: dc000317 ldw r16,12(sp) + 800c3b8: dec00604 addi sp,sp,24 + 800c3bc: f800283a ret + 800c3c0: 000d883a mov r6,zero + 800c3c4: d9400084 addi r5,sp,2 + 800c3c8: 8009883a mov r4,r16 + 800c3cc: 103ee83a callr r2 + 800c3d0: 10ffffd8 cmpnei r3,r2,-1 + 800c3d4: 183ff51e bne r3,zero,800c3ac + 800c3d8: 00802284 movi r2,138 + 800c3dc: 88000015 stw zero,0(r17) + 800c3e0: 80800015 stw r2,0(r16) + 800c3e4: 00bfffc4 movi r2,-1 + 800c3e8: 003ff006 br 800c3ac + +0800c3ec <_wctomb_r>: + 800c3ec: 00820174 movhi r2,2053 + 800c3f0: 10b0e317 ldw r2,-15476(r2) + 800c3f4: 1000683a jmp r2 + +0800c3f8 <__ascii_wctomb>: + 800c3f8: 28000926 beq r5,zero,800c420 <__ascii_wctomb+0x28> + 800c3fc: 30804030 cmpltui r2,r6,256 + 800c400: 10000326 beq r2,zero,800c410 <__ascii_wctomb+0x18> + 800c404: 29800005 stb r6,0(r5) + 800c408: 00800044 movi r2,1 + 800c40c: f800283a ret + 800c410: 00802284 movi r2,138 + 800c414: 20800015 stw r2,0(r4) + 800c418: 00bfffc4 movi r2,-1 + 800c41c: f800283a ret + 800c420: 0005883a mov r2,zero + 800c424: f800283a ret + +0800c428 <__udivdi3>: + 800c428: defff504 addi sp,sp,-44 + 800c42c: dd400615 stw r21,24(sp) + 800c430: dc000115 stw r16,4(sp) + 800c434: dfc00a15 stw ra,40(sp) + 800c438: df000915 stw fp,36(sp) + 800c43c: ddc00815 stw r23,32(sp) + 800c440: dd800715 stw r22,28(sp) + 800c444: dd000515 stw r20,20(sp) + 800c448: dcc00415 stw r19,16(sp) + 800c44c: dc800315 stw r18,12(sp) + 800c450: dc400215 stw r17,8(sp) + 800c454: 202b883a mov r21,r4 + 800c458: 2821883a mov r16,r5 + 800c45c: 3800821e bne r7,zero,800c668 <__udivdi3+0x240> + 800c460: 3827883a mov r19,r7 + 800c464: 3023883a mov r17,r6 + 800c468: 2025883a mov r18,r4 + 800c46c: 29803d2e bgeu r5,r6,800c564 <__udivdi3+0x13c> + 800c470: 00bfffd4 movui r2,65535 + 800c474: 282d883a mov r22,r5 + 800c478: 1180a52e bgeu r2,r6,800c710 <__udivdi3+0x2e8> + 800c47c: 00804034 movhi r2,256 + 800c480: 30813836 bltu r6,r2,800c964 <__udivdi3+0x53c> + 800c484: 3006d63a srli r3,r6,24 + 800c488: 04c00604 movi r19,24 + 800c48c: 00820134 movhi r2,2052 + 800c490: 1885883a add r2,r3,r2 + 800c494: 109d8903 ldbu r2,30244(r2) + 800c498: 14e7883a add r19,r2,r19 + 800c49c: 00800804 movi r2,32 + 800c4a0: 14c5c83a sub r2,r2,r19 + 800c4a4: 10000526 beq r2,zero,800c4bc <__udivdi3+0x94> + 800c4a8: 80a0983a sll r16,r16,r2 + 800c4ac: ace6d83a srl r19,r21,r19 + 800c4b0: 30a2983a sll r17,r6,r2 + 800c4b4: a8a4983a sll r18,r21,r2 + 800c4b8: 9c2cb03a or r22,r19,r16 + 800c4bc: 882ad43a srli r21,r17,16 + 800c4c0: b009883a mov r4,r22 + 800c4c4: 8d3fffcc andi r20,r17,65535 + 800c4c8: a80b883a mov r5,r21 + 800c4cc: 800d05c0 call 800d05c <__umodsi3> + 800c4d0: a80b883a mov r5,r21 + 800c4d4: b009883a mov r4,r22 + 800c4d8: 1027883a mov r19,r2 + 800c4dc: 800cff80 call 800cff8 <__udivsi3> + 800c4e0: 1021883a mov r16,r2 + 800c4e4: 9826943a slli r19,r19,16 + 800c4e8: 9004d43a srli r2,r18,16 + 800c4ec: a407383a mul r3,r20,r16 + 800c4f0: 9884b03a or r2,r19,r2 + 800c4f4: 10c0052e bgeu r2,r3,800c50c <__udivdi3+0xe4> + 800c4f8: 1445883a add r2,r2,r17 + 800c4fc: 813fffc4 addi r4,r16,-1 + 800c500: 14400136 bltu r2,r17,800c508 <__udivdi3+0xe0> + 800c504: 10c12836 bltu r2,r3,800c9a8 <__udivdi3+0x580> + 800c508: 2021883a mov r16,r4 + 800c50c: 10e7c83a sub r19,r2,r3 + 800c510: a80b883a mov r5,r21 + 800c514: 9809883a mov r4,r19 + 800c518: 800d05c0 call 800d05c <__umodsi3> + 800c51c: 102d883a mov r22,r2 + 800c520: a80b883a mov r5,r21 + 800c524: 9809883a mov r4,r19 + 800c528: 800cff80 call 800cff8 <__udivsi3> + 800c52c: b02c943a slli r22,r22,16 + 800c530: a0a9383a mul r20,r20,r2 + 800c534: 94bfffcc andi r18,r18,65535 + 800c538: b4a4b03a or r18,r22,r18 + 800c53c: 9500052e bgeu r18,r20,800c554 <__udivdi3+0x12c> + 800c540: 8ca5883a add r18,r17,r18 + 800c544: 10ffffc4 addi r3,r2,-1 + 800c548: 94400136 bltu r18,r17,800c550 <__udivdi3+0x128> + 800c54c: 95011436 bltu r18,r20,800c9a0 <__udivdi3+0x578> + 800c550: 1805883a mov r2,r3 + 800c554: 800c943a slli r6,r16,16 + 800c558: 0007883a mov r3,zero + 800c55c: 3084b03a or r2,r6,r2 + 800c560: 00005506 br 800c6b8 <__udivdi3+0x290> + 800c564: 3000041e bne r6,zero,800c578 <__udivdi3+0x150> + 800c568: 000b883a mov r5,zero + 800c56c: 01000044 movi r4,1 + 800c570: 800cff80 call 800cff8 <__udivsi3> + 800c574: 1023883a mov r17,r2 + 800c578: 00bfffd4 movui r2,65535 + 800c57c: 14405f2e bgeu r2,r17,800c6fc <__udivdi3+0x2d4> + 800c580: 00804034 movhi r2,256 + 800c584: 8880f436 bltu r17,r2,800c958 <__udivdi3+0x530> + 800c588: 8806d63a srli r3,r17,24 + 800c58c: 04c00604 movi r19,24 + 800c590: 00820134 movhi r2,2052 + 800c594: 1885883a add r2,r3,r2 + 800c598: 109d8903 ldbu r2,30244(r2) + 800c59c: 14e7883a add r19,r2,r19 + 800c5a0: 00800804 movi r2,32 + 800c5a4: 14c5c83a sub r2,r2,r19 + 800c5a8: 10005e1e bne r2,zero,800c724 <__udivdi3+0x2fc> + 800c5ac: 8828d43a srli r20,r17,16 + 800c5b0: 8461c83a sub r16,r16,r17 + 800c5b4: 8d7fffcc andi r21,r17,65535 + 800c5b8: 00c00044 movi r3,1 + 800c5bc: 8009883a mov r4,r16 + 800c5c0: a00b883a mov r5,r20 + 800c5c4: d8c00015 stw r3,0(sp) + 800c5c8: 800d05c0 call 800d05c <__umodsi3> + 800c5cc: 8009883a mov r4,r16 + 800c5d0: a00b883a mov r5,r20 + 800c5d4: 1027883a mov r19,r2 + 800c5d8: 800cff80 call 800cff8 <__udivsi3> + 800c5dc: 1021883a mov r16,r2 + 800c5e0: 9826943a slli r19,r19,16 + 800c5e4: 9004d43a srli r2,r18,16 + 800c5e8: 8549383a mul r4,r16,r21 + 800c5ec: d8c00017 ldw r3,0(sp) + 800c5f0: 9884b03a or r2,r19,r2 + 800c5f4: 1100052e bgeu r2,r4,800c60c <__udivdi3+0x1e4> + 800c5f8: 1445883a add r2,r2,r17 + 800c5fc: 817fffc4 addi r5,r16,-1 + 800c600: 14400136 bltu r2,r17,800c608 <__udivdi3+0x1e0> + 800c604: 1100eb36 bltu r2,r4,800c9b4 <__udivdi3+0x58c> + 800c608: 2821883a mov r16,r5 + 800c60c: 1127c83a sub r19,r2,r4 + 800c610: a00b883a mov r5,r20 + 800c614: 9809883a mov r4,r19 + 800c618: d8c00015 stw r3,0(sp) + 800c61c: 800d05c0 call 800d05c <__umodsi3> + 800c620: 102d883a mov r22,r2 + 800c624: a00b883a mov r5,r20 + 800c628: 9809883a mov r4,r19 + 800c62c: 800cff80 call 800cff8 <__udivsi3> + 800c630: b02c943a slli r22,r22,16 + 800c634: 156b383a mul r21,r2,r21 + 800c638: 94bfffcc andi r18,r18,65535 + 800c63c: b4a4b03a or r18,r22,r18 + 800c640: d8c00017 ldw r3,0(sp) + 800c644: 9540052e bgeu r18,r21,800c65c <__udivdi3+0x234> + 800c648: 8ca5883a add r18,r17,r18 + 800c64c: 113fffc4 addi r4,r2,-1 + 800c650: 94400136 bltu r18,r17,800c658 <__udivdi3+0x230> + 800c654: 9540d036 bltu r18,r21,800c998 <__udivdi3+0x570> + 800c658: 2005883a mov r2,r4 + 800c65c: 800c943a slli r6,r16,16 + 800c660: 3084b03a or r2,r6,r2 + 800c664: 00001406 br 800c6b8 <__udivdi3+0x290> + 800c668: 29c01136 bltu r5,r7,800c6b0 <__udivdi3+0x288> + 800c66c: 00bfffd4 movui r2,65535 + 800c670: 11c01d2e bgeu r2,r7,800c6e8 <__udivdi3+0x2c0> + 800c674: 00804034 movhi r2,256 + 800c678: 3880ac36 bltu r7,r2,800c92c <__udivdi3+0x504> + 800c67c: 3806d63a srli r3,r7,24 + 800c680: 01000604 movi r4,24 + 800c684: 00820134 movhi r2,2052 + 800c688: 1885883a add r2,r3,r2 + 800c68c: 10dd8903 ldbu r3,30244(r2) + 800c690: 05800804 movi r22,32 + 800c694: 1907883a add r3,r3,r4 + 800c698: b0edc83a sub r22,r22,r3 + 800c69c: b000531e bne r22,zero,800c7ec <__udivdi3+0x3c4> + 800c6a0: 3c00a536 bltu r7,r16,800c938 <__udivdi3+0x510> + 800c6a4: a985403a cmpgeu r2,r21,r6 + 800c6a8: 0007883a mov r3,zero + 800c6ac: 00000206 br 800c6b8 <__udivdi3+0x290> + 800c6b0: 0007883a mov r3,zero + 800c6b4: 0005883a mov r2,zero + 800c6b8: dfc00a17 ldw ra,40(sp) + 800c6bc: df000917 ldw fp,36(sp) + 800c6c0: ddc00817 ldw r23,32(sp) + 800c6c4: dd800717 ldw r22,28(sp) + 800c6c8: dd400617 ldw r21,24(sp) + 800c6cc: dd000517 ldw r20,20(sp) + 800c6d0: dcc00417 ldw r19,16(sp) + 800c6d4: dc800317 ldw r18,12(sp) + 800c6d8: dc400217 ldw r17,8(sp) + 800c6dc: dc000117 ldw r16,4(sp) + 800c6e0: dec00b04 addi sp,sp,44 + 800c6e4: f800283a ret + 800c6e8: 38804030 cmpltui r2,r7,256 + 800c6ec: 1000951e bne r2,zero,800c944 <__udivdi3+0x51c> + 800c6f0: 3806d23a srli r3,r7,8 + 800c6f4: 01000204 movi r4,8 + 800c6f8: 003fe206 br 800c684 <__udivdi3+0x25c> + 800c6fc: 88804030 cmpltui r2,r17,256 + 800c700: 10009b1e bne r2,zero,800c970 <__udivdi3+0x548> + 800c704: 8806d23a srli r3,r17,8 + 800c708: 04c00204 movi r19,8 + 800c70c: 003fa006 br 800c590 <__udivdi3+0x168> + 800c710: 30804030 cmpltui r2,r6,256 + 800c714: 10008e1e bne r2,zero,800c950 <__udivdi3+0x528> + 800c718: 3006d23a srli r3,r6,8 + 800c71c: 04c00204 movi r19,8 + 800c720: 003f5a06 br 800c48c <__udivdi3+0x64> + 800c724: 88a2983a sll r17,r17,r2 + 800c728: 84ecd83a srl r22,r16,r19 + 800c72c: 80a0983a sll r16,r16,r2 + 800c730: 8828d43a srli r20,r17,16 + 800c734: b009883a mov r4,r22 + 800c738: ace6d83a srl r19,r21,r19 + 800c73c: a00b883a mov r5,r20 + 800c740: a8a4983a sll r18,r21,r2 + 800c744: 800d05c0 call 800d05c <__umodsi3> + 800c748: b009883a mov r4,r22 + 800c74c: a00b883a mov r5,r20 + 800c750: 9c26b03a or r19,r19,r16 + 800c754: 1021883a mov r16,r2 + 800c758: 800cff80 call 800cff8 <__udivsi3> + 800c75c: 102f883a mov r23,r2 + 800c760: 8d7fffcc andi r21,r17,65535 + 800c764: 8020943a slli r16,r16,16 + 800c768: 9804d43a srli r2,r19,16 + 800c76c: aded383a mul r22,r21,r23 + 800c770: 8084b03a or r2,r16,r2 + 800c774: 1580062e bgeu r2,r22,800c790 <__udivdi3+0x368> + 800c778: 1445883a add r2,r2,r17 + 800c77c: b8ffffc4 addi r3,r23,-1 + 800c780: 14408336 bltu r2,r17,800c990 <__udivdi3+0x568> + 800c784: 1580822e bgeu r2,r22,800c990 <__udivdi3+0x568> + 800c788: bdffff84 addi r23,r23,-2 + 800c78c: 1445883a add r2,r2,r17 + 800c790: 15adc83a sub r22,r2,r22 + 800c794: a00b883a mov r5,r20 + 800c798: b009883a mov r4,r22 + 800c79c: 800d05c0 call 800d05c <__umodsi3> + 800c7a0: 1021883a mov r16,r2 + 800c7a4: b009883a mov r4,r22 + 800c7a8: a00b883a mov r5,r20 + 800c7ac: 800cff80 call 800cff8 <__udivsi3> + 800c7b0: 8020943a slli r16,r16,16 + 800c7b4: a889383a mul r4,r21,r2 + 800c7b8: 9cffffcc andi r19,r19,65535 + 800c7bc: 84e0b03a or r16,r16,r19 + 800c7c0: 8100062e bgeu r16,r4,800c7dc <__udivdi3+0x3b4> + 800c7c4: 8461883a add r16,r16,r17 + 800c7c8: 10ffffc4 addi r3,r2,-1 + 800c7cc: 84406c36 bltu r16,r17,800c980 <__udivdi3+0x558> + 800c7d0: 81006b2e bgeu r16,r4,800c980 <__udivdi3+0x558> + 800c7d4: 10bfff84 addi r2,r2,-2 + 800c7d8: 8461883a add r16,r16,r17 + 800c7dc: b806943a slli r3,r23,16 + 800c7e0: 8121c83a sub r16,r16,r4 + 800c7e4: 1886b03a or r3,r3,r2 + 800c7e8: 003f7406 br 800c5bc <__udivdi3+0x194> + 800c7ec: 30f8d83a srl fp,r6,r3 + 800c7f0: 3d8e983a sll r7,r7,r22 + 800c7f4: 80eed83a srl r23,r16,r3 + 800c7f8: a8c6d83a srl r3,r21,r3 + 800c7fc: e1f8b03a or fp,fp,r7 + 800c800: e024d43a srli r18,fp,16 + 800c804: 85a0983a sll r16,r16,r22 + 800c808: b809883a mov r4,r23 + 800c80c: 900b883a mov r5,r18 + 800c810: 1c22b03a or r17,r3,r16 + 800c814: 35a8983a sll r20,r6,r22 + 800c818: 800d05c0 call 800d05c <__umodsi3> + 800c81c: b809883a mov r4,r23 + 800c820: 900b883a mov r5,r18 + 800c824: 1027883a mov r19,r2 + 800c828: 800cff80 call 800cff8 <__udivsi3> + 800c82c: 1021883a mov r16,r2 + 800c830: e0ffffcc andi r3,fp,65535 + 800c834: 9826943a slli r19,r19,16 + 800c838: 8804d43a srli r2,r17,16 + 800c83c: 1c09383a mul r4,r3,r16 + 800c840: 9884b03a or r2,r19,r2 + 800c844: 1100062e bgeu r2,r4,800c860 <__udivdi3+0x438> + 800c848: 1705883a add r2,r2,fp + 800c84c: 817fffc4 addi r5,r16,-1 + 800c850: 17004d36 bltu r2,fp,800c988 <__udivdi3+0x560> + 800c854: 11004c2e bgeu r2,r4,800c988 <__udivdi3+0x560> + 800c858: 843fff84 addi r16,r16,-2 + 800c85c: 1705883a add r2,r2,fp + 800c860: 1127c83a sub r19,r2,r4 + 800c864: 900b883a mov r5,r18 + 800c868: 9809883a mov r4,r19 + 800c86c: d8c00015 stw r3,0(sp) + 800c870: 800d05c0 call 800d05c <__umodsi3> + 800c874: 9809883a mov r4,r19 + 800c878: 900b883a mov r5,r18 + 800c87c: 102f883a mov r23,r2 + 800c880: 800cff80 call 800cff8 <__udivsi3> + 800c884: d8c00017 ldw r3,0(sp) + 800c888: b82e943a slli r23,r23,16 + 800c88c: 8c7fffcc andi r17,r17,65535 + 800c890: 1889383a mul r4,r3,r2 + 800c894: bc62b03a or r17,r23,r17 + 800c898: 8900062e bgeu r17,r4,800c8b4 <__udivdi3+0x48c> + 800c89c: 8f23883a add r17,r17,fp + 800c8a0: 10ffffc4 addi r3,r2,-1 + 800c8a4: 8f003436 bltu r17,fp,800c978 <__udivdi3+0x550> + 800c8a8: 8900332e bgeu r17,r4,800c978 <__udivdi3+0x550> + 800c8ac: 10bfff84 addi r2,r2,-2 + 800c8b0: 8f23883a add r17,r17,fp + 800c8b4: 8020943a slli r16,r16,16 + 800c8b8: a17fffcc andi r5,r20,65535 + 800c8bc: a00cd43a srli r6,r20,16 + 800c8c0: 8084b03a or r2,r16,r2 + 800c8c4: 10ffffcc andi r3,r2,65535 + 800c8c8: 1028d43a srli r20,r2,16 + 800c8cc: 1951383a mul r8,r3,r5 + 800c8d0: 1987383a mul r3,r3,r6 + 800c8d4: a14b383a mul r5,r20,r5 + 800c8d8: 400ed43a srli r7,r8,16 + 800c8dc: 8923c83a sub r17,r17,r4 + 800c8e0: 1947883a add r3,r3,r5 + 800c8e4: 38c7883a add r3,r7,r3 + 800c8e8: a1a9383a mul r20,r20,r6 + 800c8ec: 1940022e bgeu r3,r5,800c8f8 <__udivdi3+0x4d0> + 800c8f0: 01000074 movhi r4,1 + 800c8f4: a129883a add r20,r20,r4 + 800c8f8: 180cd43a srli r6,r3,16 + 800c8fc: 3529883a add r20,r6,r20 + 800c900: 8d000836 bltu r17,r20,800c924 <__udivdi3+0x4fc> + 800c904: 8d000226 beq r17,r20,800c910 <__udivdi3+0x4e8> + 800c908: 0007883a mov r3,zero + 800c90c: 003f6a06 br 800c6b8 <__udivdi3+0x290> + 800c910: 1806943a slli r3,r3,16 + 800c914: ad8c983a sll r6,r21,r22 + 800c918: 423fffcc andi r8,r8,65535 + 800c91c: 1a07883a add r3,r3,r8 + 800c920: 30fff92e bgeu r6,r3,800c908 <__udivdi3+0x4e0> + 800c924: 10bfffc4 addi r2,r2,-1 + 800c928: 003ff706 br 800c908 <__udivdi3+0x4e0> + 800c92c: 3806d43a srli r3,r7,16 + 800c930: 01000404 movi r4,16 + 800c934: 003f5306 br 800c684 <__udivdi3+0x25c> + 800c938: 0007883a mov r3,zero + 800c93c: 00800044 movi r2,1 + 800c940: 003f5d06 br 800c6b8 <__udivdi3+0x290> + 800c944: 3807883a mov r3,r7 + 800c948: 0009883a mov r4,zero + 800c94c: 003f4d06 br 800c684 <__udivdi3+0x25c> + 800c950: 3007883a mov r3,r6 + 800c954: 003ecd06 br 800c48c <__udivdi3+0x64> + 800c958: 8806d43a srli r3,r17,16 + 800c95c: 04c00404 movi r19,16 + 800c960: 003f0b06 br 800c590 <__udivdi3+0x168> + 800c964: 3006d43a srli r3,r6,16 + 800c968: 04c00404 movi r19,16 + 800c96c: 003ec706 br 800c48c <__udivdi3+0x64> + 800c970: 8807883a mov r3,r17 + 800c974: 003f0606 br 800c590 <__udivdi3+0x168> + 800c978: 1805883a mov r2,r3 + 800c97c: 003fcd06 br 800c8b4 <__udivdi3+0x48c> + 800c980: 1805883a mov r2,r3 + 800c984: 003f9506 br 800c7dc <__udivdi3+0x3b4> + 800c988: 2821883a mov r16,r5 + 800c98c: 003fb406 br 800c860 <__udivdi3+0x438> + 800c990: 182f883a mov r23,r3 + 800c994: 003f7e06 br 800c790 <__udivdi3+0x368> + 800c998: 10bfff84 addi r2,r2,-2 + 800c99c: 003f2f06 br 800c65c <__udivdi3+0x234> + 800c9a0: 10bfff84 addi r2,r2,-2 + 800c9a4: 003eeb06 br 800c554 <__udivdi3+0x12c> + 800c9a8: 843fff84 addi r16,r16,-2 + 800c9ac: 1445883a add r2,r2,r17 + 800c9b0: 003ed606 br 800c50c <__udivdi3+0xe4> + 800c9b4: 843fff84 addi r16,r16,-2 + 800c9b8: 1445883a add r2,r2,r17 + 800c9bc: 003f1306 br 800c60c <__udivdi3+0x1e4> + +0800c9c0 <__umoddi3>: + 800c9c0: defff404 addi sp,sp,-48 + 800c9c4: dc400315 stw r17,12(sp) + 800c9c8: dc000215 stw r16,8(sp) + 800c9cc: dfc00b15 stw ra,44(sp) + 800c9d0: df000a15 stw fp,40(sp) + 800c9d4: ddc00915 stw r23,36(sp) + 800c9d8: dd800815 stw r22,32(sp) + 800c9dc: dd400715 stw r21,28(sp) + 800c9e0: dd000615 stw r20,24(sp) + 800c9e4: dcc00515 stw r19,20(sp) + 800c9e8: dc800415 stw r18,16(sp) + 800c9ec: 2823883a mov r17,r5 + 800c9f0: 2021883a mov r16,r4 + 800c9f4: 3800701e bne r7,zero,800cbb8 <__umoddi3+0x1f8> + 800c9f8: 382b883a mov r21,r7 + 800c9fc: 3027883a mov r19,r6 + 800ca00: 2029883a mov r20,r4 + 800ca04: 2980392e bgeu r5,r6,800caec <__umoddi3+0x12c> + 800ca08: 00bfffd4 movui r2,65535 + 800ca0c: 282f883a mov r23,r5 + 800ca10: 11809736 bltu r2,r6,800cc70 <__umoddi3+0x2b0> + 800ca14: 30804030 cmpltui r2,r6,256 + 800ca18: 1001231e bne r2,zero,800cea8 <__umoddi3+0x4e8> + 800ca1c: 3006d23a srli r3,r6,8 + 800ca20: 05400204 movi r21,8 + 800ca24: 00820134 movhi r2,2052 + 800ca28: 1885883a add r2,r3,r2 + 800ca2c: 109d8903 ldbu r2,30244(r2) + 800ca30: 156b883a add r21,r2,r21 + 800ca34: 00800804 movi r2,32 + 800ca38: 1565c83a sub r18,r2,r21 + 800ca3c: 90000526 beq r18,zero,800ca54 <__umoddi3+0x94> + 800ca40: 8ca2983a sll r17,r17,r18 + 800ca44: 856ad83a srl r21,r16,r21 + 800ca48: 34a6983a sll r19,r6,r18 + 800ca4c: 84a8983a sll r20,r16,r18 + 800ca50: ac6eb03a or r23,r21,r17 + 800ca54: 982cd43a srli r22,r19,16 + 800ca58: b809883a mov r4,r23 + 800ca5c: 9c3fffcc andi r16,r19,65535 + 800ca60: b00b883a mov r5,r22 + 800ca64: 800d05c0 call 800d05c <__umodsi3> + 800ca68: b00b883a mov r5,r22 + 800ca6c: b809883a mov r4,r23 + 800ca70: 102b883a mov r21,r2 + 800ca74: 800cff80 call 800cff8 <__udivsi3> + 800ca78: a82a943a slli r21,r21,16 + 800ca7c: a006d43a srli r3,r20,16 + 800ca80: 8085383a mul r2,r16,r2 + 800ca84: a8c6b03a or r3,r21,r3 + 800ca88: 1880032e bgeu r3,r2,800ca98 <__umoddi3+0xd8> + 800ca8c: 1cc7883a add r3,r3,r19 + 800ca90: 1cc00136 bltu r3,r19,800ca98 <__umoddi3+0xd8> + 800ca94: 18811836 bltu r3,r2,800cef8 <__umoddi3+0x538> + 800ca98: 18abc83a sub r21,r3,r2 + 800ca9c: b00b883a mov r5,r22 + 800caa0: a809883a mov r4,r21 + 800caa4: 800d05c0 call 800d05c <__umodsi3> + 800caa8: 1023883a mov r17,r2 + 800caac: b00b883a mov r5,r22 + 800cab0: a809883a mov r4,r21 + 800cab4: 800cff80 call 800cff8 <__udivsi3> + 800cab8: 8822943a slli r17,r17,16 + 800cabc: 8085383a mul r2,r16,r2 + 800cac0: a0ffffcc andi r3,r20,65535 + 800cac4: 88c6b03a or r3,r17,r3 + 800cac8: 1880042e bgeu r3,r2,800cadc <__umoddi3+0x11c> + 800cacc: 1cc7883a add r3,r3,r19 + 800cad0: 1cc00236 bltu r3,r19,800cadc <__umoddi3+0x11c> + 800cad4: 1880012e bgeu r3,r2,800cadc <__umoddi3+0x11c> + 800cad8: 1cc7883a add r3,r3,r19 + 800cadc: 1885c83a sub r2,r3,r2 + 800cae0: 1484d83a srl r2,r2,r18 + 800cae4: 0007883a mov r3,zero + 800cae8: 00003606 br 800cbc4 <__umoddi3+0x204> + 800caec: 3000041e bne r6,zero,800cb00 <__umoddi3+0x140> + 800caf0: 000b883a mov r5,zero + 800caf4: 01000044 movi r4,1 + 800caf8: 800cff80 call 800cff8 <__udivsi3> + 800cafc: 1027883a mov r19,r2 + 800cb00: 00bfffd4 movui r2,65535 + 800cb04: 14c0552e bgeu r2,r19,800cc5c <__umoddi3+0x29c> + 800cb08: 00804034 movhi r2,256 + 800cb0c: 9880ee36 bltu r19,r2,800cec8 <__umoddi3+0x508> + 800cb10: 9806d63a srli r3,r19,24 + 800cb14: 05400604 movi r21,24 + 800cb18: 00820134 movhi r2,2052 + 800cb1c: 1885883a add r2,r3,r2 + 800cb20: 109d8903 ldbu r2,30244(r2) + 800cb24: 156b883a add r21,r2,r21 + 800cb28: 00800804 movi r2,32 + 800cb2c: 1565c83a sub r18,r2,r21 + 800cb30: 9000ab1e bne r18,zero,800cde0 <__umoddi3+0x420> + 800cb34: 982cd43a srli r22,r19,16 + 800cb38: 8ce3c83a sub r17,r17,r19 + 800cb3c: 9d7fffcc andi r21,r19,65535 + 800cb40: b00b883a mov r5,r22 + 800cb44: 8809883a mov r4,r17 + 800cb48: 800d05c0 call 800d05c <__umodsi3> + 800cb4c: b00b883a mov r5,r22 + 800cb50: 8809883a mov r4,r17 + 800cb54: 1021883a mov r16,r2 + 800cb58: 800cff80 call 800cff8 <__udivsi3> + 800cb5c: 8020943a slli r16,r16,16 + 800cb60: a006d43a srli r3,r20,16 + 800cb64: 1545383a mul r2,r2,r21 + 800cb68: 80c6b03a or r3,r16,r3 + 800cb6c: 1880042e bgeu r3,r2,800cb80 <__umoddi3+0x1c0> + 800cb70: 1cc7883a add r3,r3,r19 + 800cb74: 1cc00236 bltu r3,r19,800cb80 <__umoddi3+0x1c0> + 800cb78: 1880012e bgeu r3,r2,800cb80 <__umoddi3+0x1c0> + 800cb7c: 1cc7883a add r3,r3,r19 + 800cb80: 18a1c83a sub r16,r3,r2 + 800cb84: b00b883a mov r5,r22 + 800cb88: 8009883a mov r4,r16 + 800cb8c: 800d05c0 call 800d05c <__umodsi3> + 800cb90: 1023883a mov r17,r2 + 800cb94: b00b883a mov r5,r22 + 800cb98: 8009883a mov r4,r16 + 800cb9c: 800cff80 call 800cff8 <__udivsi3> + 800cba0: 8822943a slli r17,r17,16 + 800cba4: 1545383a mul r2,r2,r21 + 800cba8: a53fffcc andi r20,r20,65535 + 800cbac: 8d06b03a or r3,r17,r20 + 800cbb0: 18bfca2e bgeu r3,r2,800cadc <__umoddi3+0x11c> + 800cbb4: 003fc506 br 800cacc <__umoddi3+0x10c> + 800cbb8: 2005883a mov r2,r4 + 800cbbc: 29c00d2e bgeu r5,r7,800cbf4 <__umoddi3+0x234> + 800cbc0: 2807883a mov r3,r5 + 800cbc4: dfc00b17 ldw ra,44(sp) + 800cbc8: df000a17 ldw fp,40(sp) + 800cbcc: ddc00917 ldw r23,36(sp) + 800cbd0: dd800817 ldw r22,32(sp) + 800cbd4: dd400717 ldw r21,28(sp) + 800cbd8: dd000617 ldw r20,24(sp) + 800cbdc: dcc00517 ldw r19,20(sp) + 800cbe0: dc800417 ldw r18,16(sp) + 800cbe4: dc400317 ldw r17,12(sp) + 800cbe8: dc000217 ldw r16,8(sp) + 800cbec: dec00c04 addi sp,sp,48 + 800cbf0: f800283a ret + 800cbf4: 013fffd4 movui r4,65535 + 800cbf8: 2807883a mov r3,r5 + 800cbfc: 21c0122e bgeu r4,r7,800cc48 <__umoddi3+0x288> + 800cc00: 01004034 movhi r4,256 + 800cc04: 3900ad36 bltu r7,r4,800cebc <__umoddi3+0x4fc> + 800cc08: 3810d63a srli r8,r7,24 + 800cc0c: 01400604 movi r5,24 + 800cc10: 01020134 movhi r4,2052 + 800cc14: 4109883a add r4,r8,r4 + 800cc18: 251d8903 ldbu r20,30244(r4) + 800cc1c: 04c00804 movi r19,32 + 800cc20: a169883a add r20,r20,r5 + 800cc24: 9d27c83a sub r19,r19,r20 + 800cc28: 9800161e bne r19,zero,800cc84 <__umoddi3+0x2c4> + 800cc2c: 3c400136 bltu r7,r17,800cc34 <__umoddi3+0x274> + 800cc30: 81bfe436 bltu r16,r6,800cbc4 <__umoddi3+0x204> + 800cc34: 8185c83a sub r2,r16,r6 + 800cc38: 89cfc83a sub r7,r17,r7 + 800cc3c: 8087803a cmpltu r3,r16,r2 + 800cc40: 38c7c83a sub r3,r7,r3 + 800cc44: 003fdf06 br 800cbc4 <__umoddi3+0x204> + 800cc48: 39004030 cmpltui r4,r7,256 + 800cc4c: 2000981e bne r4,zero,800ceb0 <__umoddi3+0x4f0> + 800cc50: 3810d23a srli r8,r7,8 + 800cc54: 01400204 movi r5,8 + 800cc58: 003fed06 br 800cc10 <__umoddi3+0x250> + 800cc5c: 98804030 cmpltui r2,r19,256 + 800cc60: 10009c1e bne r2,zero,800ced4 <__umoddi3+0x514> + 800cc64: 9806d23a srli r3,r19,8 + 800cc68: 05400204 movi r21,8 + 800cc6c: 003faa06 br 800cb18 <__umoddi3+0x158> + 800cc70: 00804034 movhi r2,256 + 800cc74: 30809936 bltu r6,r2,800cedc <__umoddi3+0x51c> + 800cc78: 3006d63a srli r3,r6,24 + 800cc7c: 05400604 movi r21,24 + 800cc80: 003f6806 br 800ca24 <__umoddi3+0x64> + 800cc84: 3504d83a srl r2,r6,r20 + 800cc88: 3cce983a sll r7,r7,r19 + 800cc8c: 8d38d83a srl fp,r17,r20 + 800cc90: 8ce2983a sll r17,r17,r19 + 800cc94: 11eeb03a or r23,r2,r7 + 800cc98: b82cd43a srli r22,r23,16 + 800cc9c: 8504d83a srl r2,r16,r20 + 800cca0: e009883a mov r4,fp + 800cca4: b00b883a mov r5,r22 + 800cca8: 34e4983a sll r18,r6,r19 + 800ccac: 1462b03a or r17,r2,r17 + 800ccb0: 800d05c0 call 800d05c <__umodsi3> + 800ccb4: e009883a mov r4,fp + 800ccb8: b00b883a mov r5,r22 + 800ccbc: 102b883a mov r21,r2 + 800ccc0: 800cff80 call 800cff8 <__udivsi3> + 800ccc4: 100d883a mov r6,r2 + 800ccc8: b8ffffcc andi r3,r23,65535 + 800cccc: a82a943a slli r21,r21,16 + 800ccd0: 8804d43a srli r2,r17,16 + 800ccd4: 1989383a mul r4,r3,r6 + 800ccd8: 84e0983a sll r16,r16,r19 + 800ccdc: a884b03a or r2,r21,r2 + 800cce0: 1100062e bgeu r2,r4,800ccfc <__umoddi3+0x33c> + 800cce4: 15c5883a add r2,r2,r23 + 800cce8: 317fffc4 addi r5,r6,-1 + 800ccec: 15c08036 bltu r2,r23,800cef0 <__umoddi3+0x530> + 800ccf0: 11007f2e bgeu r2,r4,800cef0 <__umoddi3+0x530> + 800ccf4: 31bfff84 addi r6,r6,-2 + 800ccf8: 15c5883a add r2,r2,r23 + 800ccfc: 112bc83a sub r21,r2,r4 + 800cd00: b00b883a mov r5,r22 + 800cd04: a809883a mov r4,r21 + 800cd08: d9800115 stw r6,4(sp) + 800cd0c: d8c00015 stw r3,0(sp) + 800cd10: 800d05c0 call 800d05c <__umodsi3> + 800cd14: b00b883a mov r5,r22 + 800cd18: a809883a mov r4,r21 + 800cd1c: 1039883a mov fp,r2 + 800cd20: 800cff80 call 800cff8 <__udivsi3> + 800cd24: d8c00017 ldw r3,0(sp) + 800cd28: e038943a slli fp,fp,16 + 800cd2c: 8c7fffcc andi r17,r17,65535 + 800cd30: 1887383a mul r3,r3,r2 + 800cd34: e462b03a or r17,fp,r17 + 800cd38: d9800117 ldw r6,4(sp) + 800cd3c: 88c0062e bgeu r17,r3,800cd58 <__umoddi3+0x398> + 800cd40: 8de3883a add r17,r17,r23 + 800cd44: 113fffc4 addi r4,r2,-1 + 800cd48: 8dc06736 bltu r17,r23,800cee8 <__umoddi3+0x528> + 800cd4c: 88c0662e bgeu r17,r3,800cee8 <__umoddi3+0x528> + 800cd50: 10bfff84 addi r2,r2,-2 + 800cd54: 8de3883a add r17,r17,r23 + 800cd58: 300a943a slli r5,r6,16 + 800cd5c: 9010d43a srli r8,r18,16 + 800cd60: 91bfffcc andi r6,r18,65535 + 800cd64: 2888b03a or r4,r5,r2 + 800cd68: 21ffffcc andi r7,r4,65535 + 800cd6c: 2008d43a srli r4,r4,16 + 800cd70: 300b883a mov r5,r6 + 800cd74: 398d383a mul r6,r7,r6 + 800cd78: 214b383a mul r5,r4,r5 + 800cd7c: 3a0f383a mul r7,r7,r8 + 800cd80: 3004d43a srli r2,r6,16 + 800cd84: 88c7c83a sub r3,r17,r3 + 800cd88: 394f883a add r7,r7,r5 + 800cd8c: 11c5883a add r2,r2,r7 + 800cd90: 2209383a mul r4,r4,r8 + 800cd94: 1140022e bgeu r2,r5,800cda0 <__umoddi3+0x3e0> + 800cd98: 01400074 movhi r5,1 + 800cd9c: 2149883a add r4,r4,r5 + 800cda0: 100ad43a srli r5,r2,16 + 800cda4: 1004943a slli r2,r2,16 + 800cda8: 31bfffcc andi r6,r6,65535 + 800cdac: 2909883a add r4,r5,r4 + 800cdb0: 1185883a add r2,r2,r6 + 800cdb4: 19003636 bltu r3,r4,800ce90 <__umoddi3+0x4d0> + 800cdb8: 19003426 beq r3,r4,800ce8c <__umoddi3+0x4cc> + 800cdbc: 8085c83a sub r2,r16,r2 + 800cdc0: 80a1803a cmpltu r16,r16,r2 + 800cdc4: 1907c83a sub r3,r3,r4 + 800cdc8: 1c07c83a sub r3,r3,r16 + 800cdcc: 1d20983a sll r16,r3,r20 + 800cdd0: 14c4d83a srl r2,r2,r19 + 800cdd4: 1cc6d83a srl r3,r3,r19 + 800cdd8: 8084b03a or r2,r16,r2 + 800cddc: 003f7906 br 800cbc4 <__umoddi3+0x204> + 800cde0: 9ca6983a sll r19,r19,r18 + 800cde4: 8d68d83a srl r20,r17,r21 + 800cde8: 856ad83a srl r21,r16,r21 + 800cdec: 982cd43a srli r22,r19,16 + 800cdf0: a009883a mov r4,r20 + 800cdf4: 8ca2983a sll r17,r17,r18 + 800cdf8: b00b883a mov r5,r22 + 800cdfc: 800d05c0 call 800d05c <__umodsi3> + 800ce00: a009883a mov r4,r20 + 800ce04: b00b883a mov r5,r22 + 800ce08: ac6eb03a or r23,r21,r17 + 800ce0c: 1023883a mov r17,r2 + 800ce10: 800cff80 call 800cff8 <__udivsi3> + 800ce14: 9d7fffcc andi r21,r19,65535 + 800ce18: 8822943a slli r17,r17,16 + 800ce1c: b806d43a srli r3,r23,16 + 800ce20: a885383a mul r2,r21,r2 + 800ce24: 84a8983a sll r20,r16,r18 + 800ce28: 88c6b03a or r3,r17,r3 + 800ce2c: 1880042e bgeu r3,r2,800ce40 <__umoddi3+0x480> + 800ce30: 1cc7883a add r3,r3,r19 + 800ce34: 1cc00236 bltu r3,r19,800ce40 <__umoddi3+0x480> + 800ce38: 1880012e bgeu r3,r2,800ce40 <__umoddi3+0x480> + 800ce3c: 1cc7883a add r3,r3,r19 + 800ce40: 18a3c83a sub r17,r3,r2 + 800ce44: 8809883a mov r4,r17 + 800ce48: b00b883a mov r5,r22 + 800ce4c: 800d05c0 call 800d05c <__umodsi3> + 800ce50: 1021883a mov r16,r2 + 800ce54: 8809883a mov r4,r17 + 800ce58: b00b883a mov r5,r22 + 800ce5c: 800cff80 call 800cff8 <__udivsi3> + 800ce60: 8022943a slli r17,r16,16 + 800ce64: a885383a mul r2,r21,r2 + 800ce68: bdffffcc andi r23,r23,65535 + 800ce6c: 8de2b03a or r17,r17,r23 + 800ce70: 8880042e bgeu r17,r2,800ce84 <__umoddi3+0x4c4> + 800ce74: 8ce3883a add r17,r17,r19 + 800ce78: 8cc00236 bltu r17,r19,800ce84 <__umoddi3+0x4c4> + 800ce7c: 8880012e bgeu r17,r2,800ce84 <__umoddi3+0x4c4> + 800ce80: 8ce3883a add r17,r17,r19 + 800ce84: 88a3c83a sub r17,r17,r2 + 800ce88: 003f2d06 br 800cb40 <__umoddi3+0x180> + 800ce8c: 80bfcb2e bgeu r16,r2,800cdbc <__umoddi3+0x3fc> + 800ce90: 14a5c83a sub r18,r2,r18 + 800ce94: 1485803a cmpltu r2,r2,r18 + 800ce98: 15c5883a add r2,r2,r23 + 800ce9c: 2089c83a sub r4,r4,r2 + 800cea0: 9005883a mov r2,r18 + 800cea4: 003fc506 br 800cdbc <__umoddi3+0x3fc> + 800cea8: 3007883a mov r3,r6 + 800ceac: 003edd06 br 800ca24 <__umoddi3+0x64> + 800ceb0: 3811883a mov r8,r7 + 800ceb4: 000b883a mov r5,zero + 800ceb8: 003f5506 br 800cc10 <__umoddi3+0x250> + 800cebc: 3810d43a srli r8,r7,16 + 800cec0: 01400404 movi r5,16 + 800cec4: 003f5206 br 800cc10 <__umoddi3+0x250> + 800cec8: 9806d43a srli r3,r19,16 + 800cecc: 05400404 movi r21,16 + 800ced0: 003f1106 br 800cb18 <__umoddi3+0x158> + 800ced4: 9807883a mov r3,r19 + 800ced8: 003f0f06 br 800cb18 <__umoddi3+0x158> + 800cedc: 3006d43a srli r3,r6,16 + 800cee0: 05400404 movi r21,16 + 800cee4: 003ecf06 br 800ca24 <__umoddi3+0x64> + 800cee8: 2005883a mov r2,r4 + 800ceec: 003f9a06 br 800cd58 <__umoddi3+0x398> + 800cef0: 280d883a mov r6,r5 + 800cef4: 003f8106 br 800ccfc <__umoddi3+0x33c> + 800cef8: 1cc7883a add r3,r3,r19 + 800cefc: 003ee606 br 800ca98 <__umoddi3+0xd8> + +0800cf00 <__divsi3>: + 800cf00: 20001a16 blt r4,zero,800cf6c <__divsi3+0x6c> + 800cf04: 000f883a mov r7,zero + 800cf08: 2800020e bge r5,zero,800cf14 <__divsi3+0x14> + 800cf0c: 014bc83a sub r5,zero,r5 + 800cf10: 39c0005c xori r7,r7,1 + 800cf14: 200d883a mov r6,r4 + 800cf18: 00c00044 movi r3,1 + 800cf1c: 2900092e bgeu r5,r4,800cf44 <__divsi3+0x44> + 800cf20: 00800804 movi r2,32 + 800cf24: 00c00044 movi r3,1 + 800cf28: 00000106 br 800cf30 <__divsi3+0x30> + 800cf2c: 10001226 beq r2,zero,800cf78 <__divsi3+0x78> + 800cf30: 294b883a add r5,r5,r5 + 800cf34: 10bfffc4 addi r2,r2,-1 + 800cf38: 18c7883a add r3,r3,r3 + 800cf3c: 293ffb36 bltu r5,r4,800cf2c <__divsi3+0x2c> + 800cf40: 18000d26 beq r3,zero,800cf78 <__divsi3+0x78> + 800cf44: 0005883a mov r2,zero + 800cf48: 31400236 bltu r6,r5,800cf54 <__divsi3+0x54> + 800cf4c: 314dc83a sub r6,r6,r5 + 800cf50: 10c4b03a or r2,r2,r3 + 800cf54: 1806d07a srli r3,r3,1 + 800cf58: 280ad07a srli r5,r5,1 + 800cf5c: 183ffa1e bne r3,zero,800cf48 <__divsi3+0x48> + 800cf60: 38000126 beq r7,zero,800cf68 <__divsi3+0x68> + 800cf64: 0085c83a sub r2,zero,r2 + 800cf68: f800283a ret + 800cf6c: 0109c83a sub r4,zero,r4 + 800cf70: 01c00044 movi r7,1 + 800cf74: 003fe406 br 800cf08 <__divsi3+0x8> + 800cf78: 0005883a mov r2,zero + 800cf7c: 003ff806 br 800cf60 <__divsi3+0x60> + +0800cf80 <__modsi3>: + 800cf80: 20001a16 blt r4,zero,800cfec <__modsi3+0x6c> + 800cf84: 000f883a mov r7,zero + 800cf88: 2005883a mov r2,r4 + 800cf8c: 2800010e bge r5,zero,800cf94 <__modsi3+0x14> + 800cf90: 014bc83a sub r5,zero,r5 + 800cf94: 00c00044 movi r3,1 + 800cf98: 2900092e bgeu r5,r4,800cfc0 <__modsi3+0x40> + 800cf9c: 01800804 movi r6,32 + 800cfa0: 00c00044 movi r3,1 + 800cfa4: 00000106 br 800cfac <__modsi3+0x2c> + 800cfa8: 30000d26 beq r6,zero,800cfe0 <__modsi3+0x60> + 800cfac: 294b883a add r5,r5,r5 + 800cfb0: 31bfffc4 addi r6,r6,-1 + 800cfb4: 18c7883a add r3,r3,r3 + 800cfb8: 293ffb36 bltu r5,r4,800cfa8 <__modsi3+0x28> + 800cfbc: 18000826 beq r3,zero,800cfe0 <__modsi3+0x60> + 800cfc0: 1806d07a srli r3,r3,1 + 800cfc4: 11400136 bltu r2,r5,800cfcc <__modsi3+0x4c> + 800cfc8: 1145c83a sub r2,r2,r5 + 800cfcc: 280ad07a srli r5,r5,1 + 800cfd0: 183ffb1e bne r3,zero,800cfc0 <__modsi3+0x40> + 800cfd4: 38000126 beq r7,zero,800cfdc <__modsi3+0x5c> + 800cfd8: 0085c83a sub r2,zero,r2 + 800cfdc: f800283a ret + 800cfe0: 2005883a mov r2,r4 + 800cfe4: 383ffd26 beq r7,zero,800cfdc <__modsi3+0x5c> + 800cfe8: 003ffb06 br 800cfd8 <__modsi3+0x58> + 800cfec: 0109c83a sub r4,zero,r4 + 800cff0: 01c00044 movi r7,1 + 800cff4: 003fe406 br 800cf88 <__modsi3+0x8> + +0800cff8 <__udivsi3>: + 800cff8: 200d883a mov r6,r4 + 800cffc: 2900152e bgeu r5,r4,800d054 <__udivsi3+0x5c> + 800d000: 28001416 blt r5,zero,800d054 <__udivsi3+0x5c> + 800d004: 00800804 movi r2,32 + 800d008: 00c00044 movi r3,1 + 800d00c: 00000206 br 800d018 <__udivsi3+0x20> + 800d010: 10000e26 beq r2,zero,800d04c <__udivsi3+0x54> + 800d014: 28000516 blt r5,zero,800d02c <__udivsi3+0x34> + 800d018: 294b883a add r5,r5,r5 + 800d01c: 10bfffc4 addi r2,r2,-1 + 800d020: 18c7883a add r3,r3,r3 + 800d024: 293ffa36 bltu r5,r4,800d010 <__udivsi3+0x18> + 800d028: 18000826 beq r3,zero,800d04c <__udivsi3+0x54> + 800d02c: 0005883a mov r2,zero + 800d030: 31400236 bltu r6,r5,800d03c <__udivsi3+0x44> + 800d034: 314dc83a sub r6,r6,r5 + 800d038: 10c4b03a or r2,r2,r3 + 800d03c: 1806d07a srli r3,r3,1 + 800d040: 280ad07a srli r5,r5,1 + 800d044: 183ffa1e bne r3,zero,800d030 <__udivsi3+0x38> + 800d048: f800283a ret + 800d04c: 0005883a mov r2,zero + 800d050: f800283a ret + 800d054: 00c00044 movi r3,1 + 800d058: 003ff406 br 800d02c <__udivsi3+0x34> + +0800d05c <__umodsi3>: + 800d05c: 2005883a mov r2,r4 + 800d060: 2900132e bgeu r5,r4,800d0b0 <__umodsi3+0x54> + 800d064: 28001216 blt r5,zero,800d0b0 <__umodsi3+0x54> + 800d068: 01800804 movi r6,32 + 800d06c: 00c00044 movi r3,1 + 800d070: 00000206 br 800d07c <__umodsi3+0x20> + 800d074: 30000c26 beq r6,zero,800d0a8 <__umodsi3+0x4c> + 800d078: 28000516 blt r5,zero,800d090 <__umodsi3+0x34> + 800d07c: 294b883a add r5,r5,r5 + 800d080: 31bfffc4 addi r6,r6,-1 + 800d084: 18c7883a add r3,r3,r3 + 800d088: 293ffa36 bltu r5,r4,800d074 <__umodsi3+0x18> + 800d08c: 18000626 beq r3,zero,800d0a8 <__umodsi3+0x4c> + 800d090: 1806d07a srli r3,r3,1 + 800d094: 11400136 bltu r2,r5,800d09c <__umodsi3+0x40> + 800d098: 1145c83a sub r2,r2,r5 + 800d09c: 280ad07a srli r5,r5,1 + 800d0a0: 183ffb1e bne r3,zero,800d090 <__umodsi3+0x34> + 800d0a4: f800283a ret + 800d0a8: 2005883a mov r2,r4 + 800d0ac: f800283a ret + 800d0b0: 00c00044 movi r3,1 + 800d0b4: 003ff606 br 800d090 <__umodsi3+0x34> + +0800d0b8 <__adddf3>: + 800d0b8: 02000434 movhi r8,16 + 800d0bc: defffb04 addi sp,sp,-20 + 800d0c0: 423fffc4 addi r8,r8,-1 + 800d0c4: 2a12703a and r9,r5,r8 + 800d0c8: 3a06703a and r3,r7,r8 + 800d0cc: 3804d53a srli r2,r7,20 + 800d0d0: dc000015 stw r16,0(sp) + 800d0d4: 2820d53a srli r16,r5,20 + 800d0d8: 2016d77a srli r11,r4,29 + 800d0dc: 3014d77a srli r10,r6,29 + 800d0e0: 280ad7fa srli r5,r5,31 + 800d0e4: 481290fa slli r9,r9,3 + 800d0e8: 180690fa slli r3,r3,3 + 800d0ec: 380ed7fa srli r7,r7,31 + 800d0f0: dc400115 stw r17,4(sp) + 800d0f4: 8401ffcc andi r16,r16,2047 + 800d0f8: 1081ffcc andi r2,r2,2047 + 800d0fc: dfc00415 stw ra,16(sp) + 800d100: dcc00315 stw r19,12(sp) + 800d104: dc800215 stw r18,8(sp) + 800d108: 5a52b03a or r9,r11,r9 + 800d10c: 50c6b03a or r3,r10,r3 + 800d110: 2823883a mov r17,r5 + 800d114: 201890fa slli r12,r4,3 + 800d118: 301690fa slli r11,r6,3 + 800d11c: 8095c83a sub r10,r16,r2 + 800d120: 29c06a26 beq r5,r7,800d2cc <__adddf3+0x214> + 800d124: 0280590e bge zero,r10,800d28c <__adddf3+0x1d4> + 800d128: 10007c26 beq r2,zero,800d31c <__adddf3+0x264> + 800d12c: 8081ffd8 cmpnei r2,r16,2047 + 800d130: 10010726 beq r2,zero,800d550 <__adddf3+0x498> + 800d134: 18c02034 orhi r3,r3,128 + 800d138: 50800e48 cmpgei r2,r10,57 + 800d13c: 1000ed1e bne r2,zero,800d4f4 <__adddf3+0x43c> + 800d140: 50800808 cmpgei r2,r10,32 + 800d144: 1001541e bne r2,zero,800d698 <__adddf3+0x5e0> + 800d148: 01000804 movi r4,32 + 800d14c: 2289c83a sub r4,r4,r10 + 800d150: 1926983a sll r19,r3,r4 + 800d154: 5a84d83a srl r2,r11,r10 + 800d158: 5908983a sll r4,r11,r4 + 800d15c: 1a86d83a srl r3,r3,r10 + 800d160: 98a6b03a or r19,r19,r2 + 800d164: 2016c03a cmpne r11,r4,zero + 800d168: 9ae6b03a or r19,r19,r11 + 800d16c: 48d3c83a sub r9,r9,r3 + 800d170: 64e7c83a sub r19,r12,r19 + 800d174: 64c9803a cmpltu r4,r12,r19 + 800d178: 4909c83a sub r4,r9,r4 + 800d17c: 2080202c andhi r2,r4,128 + 800d180: 10008726 beq r2,zero,800d3a0 <__adddf3+0x2e8> + 800d184: 02402034 movhi r9,128 + 800d188: 4a7fffc4 addi r9,r9,-1 + 800d18c: 2264703a and r18,r4,r9 + 800d190: 9000cf26 beq r18,zero,800d4d0 <__adddf3+0x418> + 800d194: 9009883a mov r4,r18 + 800d198: 800f7900 call 800f790 <__clzsi2> + 800d19c: 10fffe04 addi r3,r2,-8 + 800d1a0: 01000804 movi r4,32 + 800d1a4: 20c9c83a sub r4,r4,r3 + 800d1a8: 990ad83a srl r5,r19,r4 + 800d1ac: 90c8983a sll r4,r18,r3 + 800d1b0: 98e6983a sll r19,r19,r3 + 800d1b4: 2908b03a or r4,r5,r4 + 800d1b8: 1c00be16 blt r3,r16,800d4b4 <__adddf3+0x3fc> + 800d1bc: 1c21c83a sub r16,r3,r16 + 800d1c0: 81400044 addi r5,r16,1 + 800d1c4: 28800808 cmpgei r2,r5,32 + 800d1c8: 10011b1e bne r2,zero,800d638 <__adddf3+0x580> + 800d1cc: 00800804 movi r2,32 + 800d1d0: 1145c83a sub r2,r2,r5 + 800d1d4: 9946d83a srl r3,r19,r5 + 800d1d8: 98a6983a sll r19,r19,r2 + 800d1dc: 2084983a sll r2,r4,r2 + 800d1e0: 2148d83a srl r4,r4,r5 + 800d1e4: 9826c03a cmpne r19,r19,zero + 800d1e8: 10c4b03a or r2,r2,r3 + 800d1ec: 14e6b03a or r19,r2,r19 + 800d1f0: 0021883a mov r16,zero + 800d1f4: 988001cc andi r2,r19,7 + 800d1f8: 10000726 beq r2,zero,800d218 <__adddf3+0x160> + 800d1fc: 988003cc andi r2,r19,15 + 800d200: 10800120 cmpeqi r2,r2,4 + 800d204: 1000041e bne r2,zero,800d218 <__adddf3+0x160> + 800d208: 99400104 addi r5,r19,4 + 800d20c: 2ce7803a cmpltu r19,r5,r19 + 800d210: 24c9883a add r4,r4,r19 + 800d214: 2827883a mov r19,r5 + 800d218: 2080202c andhi r2,r4,128 + 800d21c: 10006226 beq r2,zero,800d3a8 <__adddf3+0x2f0> + 800d220: 84000044 addi r16,r16,1 + 800d224: 8081ffe0 cmpeqi r2,r16,2047 + 800d228: 8401ffcc andi r16,r16,2047 + 800d22c: 1000731e bne r2,zero,800d3fc <__adddf3+0x344> + 800d230: 017fe034 movhi r5,65408 + 800d234: 297fffc4 addi r5,r5,-1 + 800d238: 214a703a and r5,r4,r5 + 800d23c: 2804977a slli r2,r5,29 + 800d240: 280a927a slli r5,r5,9 + 800d244: 9826d0fa srli r19,r19,3 + 800d248: 2808d33a srli r4,r5,12 + 800d24c: 14c4b03a or r2,r2,r19 + 800d250: 8020953a slli r16,r16,20 + 800d254: 00c00434 movhi r3,16 + 800d258: 8c403fcc andi r17,r17,255 + 800d25c: 882297fa slli r17,r17,31 + 800d260: 18ffffc4 addi r3,r3,-1 + 800d264: 20c6703a and r3,r4,r3 + 800d268: 1c06b03a or r3,r3,r16 + 800d26c: 1c46b03a or r3,r3,r17 + 800d270: dfc00417 ldw ra,16(sp) + 800d274: dcc00317 ldw r19,12(sp) + 800d278: dc800217 ldw r18,8(sp) + 800d27c: dc400117 ldw r17,4(sp) + 800d280: dc000017 ldw r16,0(sp) + 800d284: dec00504 addi sp,sp,20 + 800d288: f800283a ret + 800d28c: 50002b1e bne r10,zero,800d33c <__adddf3+0x284> + 800d290: 80800044 addi r2,r16,1 + 800d294: 1081ff8c andi r2,r2,2046 + 800d298: 1000a11e bne r2,zero,800d520 <__adddf3+0x468> + 800d29c: 4b0ab03a or r5,r9,r12 + 800d2a0: 1ac4b03a or r2,r3,r11 + 800d2a4: 80015c1e bne r16,zero,800d818 <__adddf3+0x760> + 800d2a8: 28012826 beq r5,zero,800d74c <__adddf3+0x694> + 800d2ac: 1001671e bne r2,zero,800d84c <__adddf3+0x794> + 800d2b0: 4826977a slli r19,r9,29 + 800d2b4: 00c80034 movhi r3,8192 + 800d2b8: 18ffffc4 addi r3,r3,-1 + 800d2bc: 20c4703a and r2,r4,r3 + 800d2c0: 9884b03a or r2,r19,r2 + 800d2c4: 4812d0fa srli r9,r9,3 + 800d2c8: 00003d06 br 800d3c0 <__adddf3+0x308> + 800d2cc: 02804f0e bge zero,r10,800d40c <__adddf3+0x354> + 800d2d0: 10002426 beq r2,zero,800d364 <__adddf3+0x2ac> + 800d2d4: 8081ffd8 cmpnei r2,r16,2047 + 800d2d8: 10009d26 beq r2,zero,800d550 <__adddf3+0x498> + 800d2dc: 18c02034 orhi r3,r3,128 + 800d2e0: 50800e48 cmpgei r2,r10,57 + 800d2e4: 10003b1e bne r2,zero,800d3d4 <__adddf3+0x31c> + 800d2e8: 50800808 cmpgei r2,r10,32 + 800d2ec: 10010326 beq r2,zero,800d6fc <__adddf3+0x644> + 800d2f0: 54fff804 addi r19,r10,-32 + 800d2f4: 51000820 cmpeqi r4,r10,32 + 800d2f8: 1cc4d83a srl r2,r3,r19 + 800d2fc: 2000041e bne r4,zero,800d310 <__adddf3+0x258> + 800d300: 01001004 movi r4,64 + 800d304: 2295c83a sub r10,r4,r10 + 800d308: 1a86983a sll r3,r3,r10 + 800d30c: 58d6b03a or r11,r11,r3 + 800d310: 5826c03a cmpne r19,r11,zero + 800d314: 98a6b03a or r19,r19,r2 + 800d318: 00003006 br 800d3dc <__adddf3+0x324> + 800d31c: 1ac4b03a or r2,r3,r11 + 800d320: 10007726 beq r2,zero,800d500 <__adddf3+0x448> + 800d324: 50bfffc4 addi r2,r10,-1 + 800d328: 10011926 beq r2,zero,800d790 <__adddf3+0x6d8> + 800d32c: 5281ffd8 cmpnei r10,r10,2047 + 800d330: 50012026 beq r10,zero,800d7b4 <__adddf3+0x6fc> + 800d334: 1015883a mov r10,r2 + 800d338: 003f7f06 br 800d138 <__adddf3+0x80> + 800d33c: 1409c83a sub r4,r2,r16 + 800d340: 8000a61e bne r16,zero,800d5dc <__adddf3+0x524> + 800d344: 4b0ab03a or r5,r9,r12 + 800d348: 2800f726 beq r5,zero,800d728 <__adddf3+0x670> + 800d34c: 217fffc4 addi r5,r4,-1 + 800d350: 28017f26 beq r5,zero,800d950 <__adddf3+0x898> + 800d354: 2101ffd8 cmpnei r4,r4,2047 + 800d358: 2001a326 beq r4,zero,800d9e8 <__adddf3+0x930> + 800d35c: 2809883a mov r4,r5 + 800d360: 0000a106 br 800d5e8 <__adddf3+0x530> + 800d364: 1ac4b03a or r2,r3,r11 + 800d368: 10006526 beq r2,zero,800d500 <__adddf3+0x448> + 800d36c: 50bfffc4 addi r2,r10,-1 + 800d370: 10000426 beq r2,zero,800d384 <__adddf3+0x2cc> + 800d374: 5281ffd8 cmpnei r10,r10,2047 + 800d378: 50014326 beq r10,zero,800d888 <__adddf3+0x7d0> + 800d37c: 1015883a mov r10,r2 + 800d380: 003fd706 br 800d2e0 <__adddf3+0x228> + 800d384: 62e7883a add r19,r12,r11 + 800d388: 48d3883a add r9,r9,r3 + 800d38c: 9b09803a cmpltu r4,r19,r12 + 800d390: 4909883a add r4,r9,r4 + 800d394: 2080202c andhi r2,r4,128 + 800d398: 1000b41e bne r2,zero,800d66c <__adddf3+0x5b4> + 800d39c: 04000044 movi r16,1 + 800d3a0: 988001cc andi r2,r19,7 + 800d3a4: 103f951e bne r2,zero,800d1fc <__adddf3+0x144> + 800d3a8: 9826d0fa srli r19,r19,3 + 800d3ac: 2004977a slli r2,r4,29 + 800d3b0: 2012d0fa srli r9,r4,3 + 800d3b4: 9884b03a or r2,r19,r2 + 800d3b8: 80c1ffe0 cmpeqi r3,r16,2047 + 800d3bc: 1800351e bne r3,zero,800d494 <__adddf3+0x3dc> + 800d3c0: 01000434 movhi r4,16 + 800d3c4: 213fffc4 addi r4,r4,-1 + 800d3c8: 4908703a and r4,r9,r4 + 800d3cc: 8401ffcc andi r16,r16,2047 + 800d3d0: 003f9f06 br 800d250 <__adddf3+0x198> + 800d3d4: 1ac8b03a or r4,r3,r11 + 800d3d8: 2026c03a cmpne r19,r4,zero + 800d3dc: 9b27883a add r19,r19,r12 + 800d3e0: 9b09803a cmpltu r4,r19,r12 + 800d3e4: 2249883a add r4,r4,r9 + 800d3e8: 2080202c andhi r2,r4,128 + 800d3ec: 103fec26 beq r2,zero,800d3a0 <__adddf3+0x2e8> + 800d3f0: 84000044 addi r16,r16,1 + 800d3f4: 8081ffe0 cmpeqi r2,r16,2047 + 800d3f8: 10009d26 beq r2,zero,800d670 <__adddf3+0x5b8> + 800d3fc: 0401ffc4 movi r16,2047 + 800d400: 0009883a mov r4,zero + 800d404: 0005883a mov r2,zero + 800d408: 003f9106 br 800d250 <__adddf3+0x198> + 800d40c: 5000571e bne r10,zero,800d56c <__adddf3+0x4b4> + 800d410: 80800044 addi r2,r16,1 + 800d414: 1141ff8c andi r5,r2,2046 + 800d418: 2800ed1e bne r5,zero,800d7d0 <__adddf3+0x718> + 800d41c: 4b04b03a or r2,r9,r12 + 800d420: 8000a826 beq r16,zero,800d6c4 <__adddf3+0x60c> + 800d424: 10010226 beq r2,zero,800d830 <__adddf3+0x778> + 800d428: 1ad6b03a or r11,r3,r11 + 800d42c: 480a977a slli r5,r9,29 + 800d430: 4812d0fa srli r9,r9,3 + 800d434: 58015f26 beq r11,zero,800d9b4 <__adddf3+0x8fc> + 800d438: 02080034 movhi r8,8192 + 800d43c: 423fffc4 addi r8,r8,-1 + 800d440: 2204703a and r2,r4,r8 + 800d444: 4900022c andhi r4,r9,8 + 800d448: 114ab03a or r5,r2,r5 + 800d44c: 20000826 beq r4,zero,800d470 <__adddf3+0x3b8> + 800d450: 1808d0fa srli r4,r3,3 + 800d454: 2080022c andhi r2,r4,8 + 800d458: 1000051e bne r2,zero,800d470 <__adddf3+0x3b8> + 800d45c: 1806977a slli r3,r3,29 + 800d460: 3204703a and r2,r6,r8 + 800d464: 3823883a mov r17,r7 + 800d468: 10cab03a or r5,r2,r3 + 800d46c: 2013883a mov r9,r4 + 800d470: 2804d77a srli r2,r5,29 + 800d474: 480890fa slli r4,r9,3 + 800d478: 00c80034 movhi r3,8192 + 800d47c: 18ffffc4 addi r3,r3,-1 + 800d480: 1108b03a or r4,r2,r4 + 800d484: 2004977a slli r2,r4,29 + 800d488: 2012d0fa srli r9,r4,3 + 800d48c: 28ca703a and r5,r5,r3 + 800d490: 1144b03a or r2,r2,r5 + 800d494: 4886b03a or r3,r9,r2 + 800d498: 18016b26 beq r3,zero,800da48 <__adddf3+0x990> + 800d49c: 00c00434 movhi r3,16 + 800d4a0: 49000234 orhi r4,r9,8 + 800d4a4: 18ffffc4 addi r3,r3,-1 + 800d4a8: 20c8703a and r4,r4,r3 + 800d4ac: 0401ffc4 movi r16,2047 + 800d4b0: 003f6706 br 800d250 <__adddf3+0x198> + 800d4b4: 017fe034 movhi r5,65408 + 800d4b8: 297fffc4 addi r5,r5,-1 + 800d4bc: 988001cc andi r2,r19,7 + 800d4c0: 80e1c83a sub r16,r16,r3 + 800d4c4: 2148703a and r4,r4,r5 + 800d4c8: 103f4c1e bne r2,zero,800d1fc <__adddf3+0x144> + 800d4cc: 003fb606 br 800d3a8 <__adddf3+0x2f0> + 800d4d0: 9809883a mov r4,r19 + 800d4d4: 800f7900 call 800f790 <__clzsi2> + 800d4d8: 10c00604 addi r3,r2,24 + 800d4dc: 19000808 cmpgei r4,r3,32 + 800d4e0: 203f2f26 beq r4,zero,800d1a0 <__adddf3+0xe8> + 800d4e4: 113ffe04 addi r4,r2,-8 + 800d4e8: 9908983a sll r4,r19,r4 + 800d4ec: 0027883a mov r19,zero + 800d4f0: 003f3106 br 800d1b8 <__adddf3+0x100> + 800d4f4: 1ac8b03a or r4,r3,r11 + 800d4f8: 2026c03a cmpne r19,r4,zero + 800d4fc: 003f1c06 br 800d170 <__adddf3+0xb8> + 800d500: 4826977a slli r19,r9,29 + 800d504: 00c80034 movhi r3,8192 + 800d508: 18ffffc4 addi r3,r3,-1 + 800d50c: 20c4703a and r2,r4,r3 + 800d510: 14c4b03a or r2,r2,r19 + 800d514: 4812d0fa srli r9,r9,3 + 800d518: 5021883a mov r16,r10 + 800d51c: 003fa606 br 800d3b8 <__adddf3+0x300> + 800d520: 62e7c83a sub r19,r12,r11 + 800d524: 48e5c83a sub r18,r9,r3 + 800d528: 64c9803a cmpltu r4,r12,r19 + 800d52c: 9125c83a sub r18,r18,r4 + 800d530: 9080202c andhi r2,r18,128 + 800d534: 1000b21e bne r2,zero,800d800 <__adddf3+0x748> + 800d538: 9c84b03a or r2,r19,r18 + 800d53c: 103f141e bne r2,zero,800d190 <__adddf3+0xd8> + 800d540: 0013883a mov r9,zero + 800d544: 0021883a mov r16,zero + 800d548: 0023883a mov r17,zero + 800d54c: 003f9c06 br 800d3c0 <__adddf3+0x308> + 800d550: 4826977a slli r19,r9,29 + 800d554: 00c80034 movhi r3,8192 + 800d558: 18ffffc4 addi r3,r3,-1 + 800d55c: 20c4703a and r2,r4,r3 + 800d560: 14c4b03a or r2,r2,r19 + 800d564: 4812d0fa srli r9,r9,3 + 800d568: 003fca06 br 800d494 <__adddf3+0x3dc> + 800d56c: 1409c83a sub r4,r2,r16 + 800d570: 80005e1e bne r16,zero,800d6ec <__adddf3+0x634> + 800d574: 4b0ab03a or r5,r9,r12 + 800d578: 28011326 beq r5,zero,800d9c8 <__adddf3+0x910> + 800d57c: 217fffc4 addi r5,r4,-1 + 800d580: 28012c26 beq r5,zero,800da34 <__adddf3+0x97c> + 800d584: 2101ffd8 cmpnei r4,r4,2047 + 800d588: 2000a926 beq r4,zero,800d830 <__adddf3+0x778> + 800d58c: 2809883a mov r4,r5 + 800d590: 21400e48 cmpgei r5,r4,57 + 800d594: 2800b91e bne r5,zero,800d87c <__adddf3+0x7c4> + 800d598: 21400808 cmpgei r5,r4,32 + 800d59c: 28011a1e bne r5,zero,800da08 <__adddf3+0x950> + 800d5a0: 01400804 movi r5,32 + 800d5a4: 290bc83a sub r5,r5,r4 + 800d5a8: 4966983a sll r19,r9,r5 + 800d5ac: 610cd83a srl r6,r12,r4 + 800d5b0: 614a983a sll r5,r12,r5 + 800d5b4: 4912d83a srl r9,r9,r4 + 800d5b8: 99a6b03a or r19,r19,r6 + 800d5bc: 280ac03a cmpne r5,r5,zero + 800d5c0: 9966b03a or r19,r19,r5 + 800d5c4: 1a47883a add r3,r3,r9 + 800d5c8: 9ae7883a add r19,r19,r11 + 800d5cc: 9ac9803a cmpltu r4,r19,r11 + 800d5d0: 20c9883a add r4,r4,r3 + 800d5d4: 1021883a mov r16,r2 + 800d5d8: 003f8306 br 800d3e8 <__adddf3+0x330> + 800d5dc: 1141ffd8 cmpnei r5,r2,2047 + 800d5e0: 28006326 beq r5,zero,800d770 <__adddf3+0x6b8> + 800d5e4: 4a402034 orhi r9,r9,128 + 800d5e8: 21400e48 cmpgei r5,r4,57 + 800d5ec: 28006e1e bne r5,zero,800d7a8 <__adddf3+0x6f0> + 800d5f0: 21400808 cmpgei r5,r4,32 + 800d5f4: 2800ab1e bne r5,zero,800d8a4 <__adddf3+0x7ec> + 800d5f8: 01400804 movi r5,32 + 800d5fc: 290bc83a sub r5,r5,r4 + 800d600: 4966983a sll r19,r9,r5 + 800d604: 610cd83a srl r6,r12,r4 + 800d608: 614a983a sll r5,r12,r5 + 800d60c: 4912d83a srl r9,r9,r4 + 800d610: 99a6b03a or r19,r19,r6 + 800d614: 280ac03a cmpne r5,r5,zero + 800d618: 9966b03a or r19,r19,r5 + 800d61c: 1a47c83a sub r3,r3,r9 + 800d620: 5ce7c83a sub r19,r11,r19 + 800d624: 5cc9803a cmpltu r4,r11,r19 + 800d628: 1909c83a sub r4,r3,r4 + 800d62c: 3823883a mov r17,r7 + 800d630: 1021883a mov r16,r2 + 800d634: 003ed106 br 800d17c <__adddf3+0xc4> + 800d638: 843ff844 addi r16,r16,-31 + 800d63c: 28800820 cmpeqi r2,r5,32 + 800d640: 2420d83a srl r16,r4,r16 + 800d644: 1000041e bne r2,zero,800d658 <__adddf3+0x5a0> + 800d648: 00801004 movi r2,64 + 800d64c: 114bc83a sub r5,r2,r5 + 800d650: 2148983a sll r4,r4,r5 + 800d654: 9926b03a or r19,r19,r4 + 800d658: 9826c03a cmpne r19,r19,zero + 800d65c: 9c26b03a or r19,r19,r16 + 800d660: 0009883a mov r4,zero + 800d664: 0021883a mov r16,zero + 800d668: 003f4d06 br 800d3a0 <__adddf3+0x2e8> + 800d66c: 04000084 movi r16,2 + 800d670: 00bfe034 movhi r2,65408 + 800d674: 10bfffc4 addi r2,r2,-1 + 800d678: 208a703a and r5,r4,r2 + 800d67c: 9804d07a srli r2,r19,1 + 800d680: 280697fa slli r3,r5,31 + 800d684: 9cc0004c andi r19,r19,1 + 800d688: 14e6b03a or r19,r2,r19 + 800d68c: 2808d07a srli r4,r5,1 + 800d690: 1ce6b03a or r19,r3,r19 + 800d694: 003ed706 br 800d1f4 <__adddf3+0x13c> + 800d698: 54fff804 addi r19,r10,-32 + 800d69c: 50800820 cmpeqi r2,r10,32 + 800d6a0: 1ce6d83a srl r19,r3,r19 + 800d6a4: 1000041e bne r2,zero,800d6b8 <__adddf3+0x600> + 800d6a8: 00801004 movi r2,64 + 800d6ac: 1295c83a sub r10,r2,r10 + 800d6b0: 1a86983a sll r3,r3,r10 + 800d6b4: 58d6b03a or r11,r11,r3 + 800d6b8: 5808c03a cmpne r4,r11,zero + 800d6bc: 24e6b03a or r19,r4,r19 + 800d6c0: 003eab06 br 800d170 <__adddf3+0xb8> + 800d6c4: 1000a926 beq r2,zero,800d96c <__adddf3+0x8b4> + 800d6c8: 1ac4b03a or r2,r3,r11 + 800d6cc: 1000ae1e bne r2,zero,800d988 <__adddf3+0x8d0> + 800d6d0: 4806977a slli r3,r9,29 + 800d6d4: 00880034 movhi r2,8192 + 800d6d8: 10bfffc4 addi r2,r2,-1 + 800d6dc: 2084703a and r2,r4,r2 + 800d6e0: 10c4b03a or r2,r2,r3 + 800d6e4: 4812d0fa srli r9,r9,3 + 800d6e8: 003f3506 br 800d3c0 <__adddf3+0x308> + 800d6ec: 1141ffd8 cmpnei r5,r2,2047 + 800d6f0: 28004f26 beq r5,zero,800d830 <__adddf3+0x778> + 800d6f4: 4a402034 orhi r9,r9,128 + 800d6f8: 003fa506 br 800d590 <__adddf3+0x4d8> + 800d6fc: 01000804 movi r4,32 + 800d700: 2289c83a sub r4,r4,r10 + 800d704: 1926983a sll r19,r3,r4 + 800d708: 5a84d83a srl r2,r11,r10 + 800d70c: 5908983a sll r4,r11,r4 + 800d710: 1a86d83a srl r3,r3,r10 + 800d714: 98a6b03a or r19,r19,r2 + 800d718: 2016c03a cmpne r11,r4,zero + 800d71c: 9ae6b03a or r19,r19,r11 + 800d720: 48d3883a add r9,r9,r3 + 800d724: 003f2d06 br 800d3dc <__adddf3+0x324> + 800d728: 01480034 movhi r5,8192 + 800d72c: 1826977a slli r19,r3,29 + 800d730: 297fffc4 addi r5,r5,-1 + 800d734: 3144703a and r2,r6,r5 + 800d738: 14c4b03a or r2,r2,r19 + 800d73c: 1812d0fa srli r9,r3,3 + 800d740: 3823883a mov r17,r7 + 800d744: 2021883a mov r16,r4 + 800d748: 003f1b06 br 800d3b8 <__adddf3+0x300> + 800d74c: 10007d26 beq r2,zero,800d944 <__adddf3+0x88c> + 800d750: 00880034 movhi r2,8192 + 800d754: 1808977a slli r4,r3,29 + 800d758: 10bfffc4 addi r2,r2,-1 + 800d75c: 3084703a and r2,r6,r2 + 800d760: 1104b03a or r2,r2,r4 + 800d764: 1812d0fa srli r9,r3,3 + 800d768: 3823883a mov r17,r7 + 800d76c: 003f1406 br 800d3c0 <__adddf3+0x308> + 800d770: 180a977a slli r5,r3,29 + 800d774: 01080034 movhi r4,8192 + 800d778: 213fffc4 addi r4,r4,-1 + 800d77c: 3104703a and r2,r6,r4 + 800d780: 2884b03a or r2,r5,r2 + 800d784: 1812d0fa srli r9,r3,3 + 800d788: 3823883a mov r17,r7 + 800d78c: 003f4106 br 800d494 <__adddf3+0x3dc> + 800d790: 62e7c83a sub r19,r12,r11 + 800d794: 48d3c83a sub r9,r9,r3 + 800d798: 64c9803a cmpltu r4,r12,r19 + 800d79c: 4909c83a sub r4,r9,r4 + 800d7a0: 04000044 movi r16,1 + 800d7a4: 003e7506 br 800d17c <__adddf3+0xc4> + 800d7a8: 4b12b03a or r9,r9,r12 + 800d7ac: 4826c03a cmpne r19,r9,zero + 800d7b0: 003f9b06 br 800d620 <__adddf3+0x568> + 800d7b4: 4826977a slli r19,r9,29 + 800d7b8: 00c80034 movhi r3,8192 + 800d7bc: 18ffffc4 addi r3,r3,-1 + 800d7c0: 20c4703a and r2,r4,r3 + 800d7c4: 9884b03a or r2,r19,r2 + 800d7c8: 4812d0fa srli r9,r9,3 + 800d7cc: 003f3106 br 800d494 <__adddf3+0x3dc> + 800d7d0: 1101ffe0 cmpeqi r4,r2,2047 + 800d7d4: 203f091e bne r4,zero,800d3fc <__adddf3+0x344> + 800d7d8: 62d7883a add r11,r12,r11 + 800d7dc: 5b09803a cmpltu r4,r11,r12 + 800d7e0: 48d3883a add r9,r9,r3 + 800d7e4: 490b883a add r5,r9,r4 + 800d7e8: 282697fa slli r19,r5,31 + 800d7ec: 5816d07a srli r11,r11,1 + 800d7f0: 2808d07a srli r4,r5,1 + 800d7f4: 1021883a mov r16,r2 + 800d7f8: 9ae6b03a or r19,r19,r11 + 800d7fc: 003ee806 br 800d3a0 <__adddf3+0x2e8> + 800d800: 5b27c83a sub r19,r11,r12 + 800d804: 1a53c83a sub r9,r3,r9 + 800d808: 5cc9803a cmpltu r4,r11,r19 + 800d80c: 4925c83a sub r18,r9,r4 + 800d810: 3823883a mov r17,r7 + 800d814: 003e5e06 br 800d190 <__adddf3+0xd8> + 800d818: 28002d1e bne r5,zero,800d8d0 <__adddf3+0x818> + 800d81c: 103fd41e bne r2,zero,800d770 <__adddf3+0x6b8> + 800d820: 00bfffc4 movi r2,-1 + 800d824: 0023883a mov r17,zero + 800d828: 4013883a mov r9,r8 + 800d82c: 003f1b06 br 800d49c <__adddf3+0x3e4> + 800d830: 00880034 movhi r2,8192 + 800d834: 1808977a slli r4,r3,29 + 800d838: 10bfffc4 addi r2,r2,-1 + 800d83c: 3084703a and r2,r6,r2 + 800d840: 1104b03a or r2,r2,r4 + 800d844: 1812d0fa srli r9,r3,3 + 800d848: 003f1206 br 800d494 <__adddf3+0x3dc> + 800d84c: 62e7c83a sub r19,r12,r11 + 800d850: 48cbc83a sub r5,r9,r3 + 800d854: 64c9803a cmpltu r4,r12,r19 + 800d858: 2909c83a sub r4,r5,r4 + 800d85c: 2080202c andhi r2,r4,128 + 800d860: 10003626 beq r2,zero,800d93c <__adddf3+0x884> + 800d864: 5b27c83a sub r19,r11,r12 + 800d868: 1a53c83a sub r9,r3,r9 + 800d86c: 5cc9803a cmpltu r4,r11,r19 + 800d870: 4909c83a sub r4,r9,r4 + 800d874: 3823883a mov r17,r7 + 800d878: 003e5e06 br 800d1f4 <__adddf3+0x13c> + 800d87c: 4b12b03a or r9,r9,r12 + 800d880: 4826c03a cmpne r19,r9,zero + 800d884: 003f5006 br 800d5c8 <__adddf3+0x510> + 800d888: 4806977a slli r3,r9,29 + 800d88c: 00880034 movhi r2,8192 + 800d890: 10bfffc4 addi r2,r2,-1 + 800d894: 2084703a and r2,r4,r2 + 800d898: 10c4b03a or r2,r2,r3 + 800d89c: 4812d0fa srli r9,r9,3 + 800d8a0: 003efc06 br 800d494 <__adddf3+0x3dc> + 800d8a4: 217ff804 addi r5,r4,-32 + 800d8a8: 21800820 cmpeqi r6,r4,32 + 800d8ac: 494ad83a srl r5,r9,r5 + 800d8b0: 3000041e bne r6,zero,800d8c4 <__adddf3+0x80c> + 800d8b4: 01801004 movi r6,64 + 800d8b8: 3109c83a sub r4,r6,r4 + 800d8bc: 4912983a sll r9,r9,r4 + 800d8c0: 6258b03a or r12,r12,r9 + 800d8c4: 6026c03a cmpne r19,r12,zero + 800d8c8: 9966b03a or r19,r19,r5 + 800d8cc: 003f5406 br 800d620 <__adddf3+0x568> + 800d8d0: 480a977a slli r5,r9,29 + 800d8d4: 4812d0fa srli r9,r9,3 + 800d8d8: 10003626 beq r2,zero,800d9b4 <__adddf3+0x8fc> + 800d8dc: 02080034 movhi r8,8192 + 800d8e0: 423fffc4 addi r8,r8,-1 + 800d8e4: 2204703a and r2,r4,r8 + 800d8e8: 4900022c andhi r4,r9,8 + 800d8ec: 114ab03a or r5,r2,r5 + 800d8f0: 20000826 beq r4,zero,800d914 <__adddf3+0x85c> + 800d8f4: 1808d0fa srli r4,r3,3 + 800d8f8: 2080022c andhi r2,r4,8 + 800d8fc: 1000051e bne r2,zero,800d914 <__adddf3+0x85c> + 800d900: 1806977a slli r3,r3,29 + 800d904: 3204703a and r2,r6,r8 + 800d908: 3823883a mov r17,r7 + 800d90c: 10cab03a or r5,r2,r3 + 800d910: 2013883a mov r9,r4 + 800d914: 480890fa slli r4,r9,3 + 800d918: 2804d77a srli r2,r5,29 + 800d91c: 00c80034 movhi r3,8192 + 800d920: 18ffffc4 addi r3,r3,-1 + 800d924: 1108b03a or r4,r2,r4 + 800d928: 200c977a slli r6,r4,29 + 800d92c: 28c4703a and r2,r5,r3 + 800d930: 2012d0fa srli r9,r4,3 + 800d934: 3084b03a or r2,r6,r2 + 800d938: 003ed606 br 800d494 <__adddf3+0x3dc> + 800d93c: 9904b03a or r2,r19,r4 + 800d940: 103e971e bne r2,zero,800d3a0 <__adddf3+0x2e8> + 800d944: 0013883a mov r9,zero + 800d948: 0023883a mov r17,zero + 800d94c: 003e9c06 br 800d3c0 <__adddf3+0x308> + 800d950: 5b27c83a sub r19,r11,r12 + 800d954: 1a53c83a sub r9,r3,r9 + 800d958: 5cc9803a cmpltu r4,r11,r19 + 800d95c: 4909c83a sub r4,r9,r4 + 800d960: 3823883a mov r17,r7 + 800d964: 04000044 movi r16,1 + 800d968: 003e0406 br 800d17c <__adddf3+0xc4> + 800d96c: 180a977a slli r5,r3,29 + 800d970: 01080034 movhi r4,8192 + 800d974: 213fffc4 addi r4,r4,-1 + 800d978: 3104703a and r2,r6,r4 + 800d97c: 2884b03a or r2,r5,r2 + 800d980: 1812d0fa srli r9,r3,3 + 800d984: 003e8e06 br 800d3c0 <__adddf3+0x308> + 800d988: 62e7883a add r19,r12,r11 + 800d98c: 48d3883a add r9,r9,r3 + 800d990: 9b09803a cmpltu r4,r19,r12 + 800d994: 4909883a add r4,r9,r4 + 800d998: 2080202c andhi r2,r4,128 + 800d99c: 103e8026 beq r2,zero,800d3a0 <__adddf3+0x2e8> + 800d9a0: 00bfe034 movhi r2,65408 + 800d9a4: 10bfffc4 addi r2,r2,-1 + 800d9a8: 2088703a and r4,r4,r2 + 800d9ac: 04000044 movi r16,1 + 800d9b0: 003e7b06 br 800d3a0 <__adddf3+0x2e8> + 800d9b4: 00880034 movhi r2,8192 + 800d9b8: 10bfffc4 addi r2,r2,-1 + 800d9bc: 2084703a and r2,r4,r2 + 800d9c0: 1144b03a or r2,r2,r5 + 800d9c4: 003eb306 br 800d494 <__adddf3+0x3dc> + 800d9c8: 180e977a slli r7,r3,29 + 800d9cc: 01480034 movhi r5,8192 + 800d9d0: 297fffc4 addi r5,r5,-1 + 800d9d4: 3144703a and r2,r6,r5 + 800d9d8: 3884b03a or r2,r7,r2 + 800d9dc: 1812d0fa srli r9,r3,3 + 800d9e0: 2021883a mov r16,r4 + 800d9e4: 003e7406 br 800d3b8 <__adddf3+0x300> + 800d9e8: 00880034 movhi r2,8192 + 800d9ec: 1808977a slli r4,r3,29 + 800d9f0: 10bfffc4 addi r2,r2,-1 + 800d9f4: 3084703a and r2,r6,r2 + 800d9f8: 1104b03a or r2,r2,r4 + 800d9fc: 1812d0fa srli r9,r3,3 + 800da00: 3823883a mov r17,r7 + 800da04: 003ea306 br 800d494 <__adddf3+0x3dc> + 800da08: 217ff804 addi r5,r4,-32 + 800da0c: 21800820 cmpeqi r6,r4,32 + 800da10: 494ad83a srl r5,r9,r5 + 800da14: 3000041e bne r6,zero,800da28 <__adddf3+0x970> + 800da18: 01801004 movi r6,64 + 800da1c: 3109c83a sub r4,r6,r4 + 800da20: 4912983a sll r9,r9,r4 + 800da24: 6258b03a or r12,r12,r9 + 800da28: 6026c03a cmpne r19,r12,zero + 800da2c: 9966b03a or r19,r19,r5 + 800da30: 003ee506 br 800d5c8 <__adddf3+0x510> + 800da34: 62e7883a add r19,r12,r11 + 800da38: 48d3883a add r9,r9,r3 + 800da3c: 9ac9803a cmpltu r4,r19,r11 + 800da40: 4909883a add r4,r9,r4 + 800da44: 003e5306 br 800d394 <__adddf3+0x2dc> + 800da48: 0005883a mov r2,zero + 800da4c: 0401ffc4 movi r16,2047 + 800da50: 0009883a mov r4,zero + 800da54: 003dfe06 br 800d250 <__adddf3+0x198> + +0800da58 <__divdf3>: + 800da58: defff104 addi sp,sp,-60 + 800da5c: 2804d53a srli r2,r5,20 + 800da60: dd000915 stw r20,36(sp) + 800da64: 2828d7fa srli r20,r5,31 + 800da68: dc000515 stw r16,20(sp) + 800da6c: 04000434 movhi r16,16 + 800da70: ddc00c15 stw r23,48(sp) + 800da74: dc800715 stw r18,28(sp) + 800da78: 843fffc4 addi r16,r16,-1 + 800da7c: dfc00e15 stw ra,56(sp) + 800da80: df000d15 stw fp,52(sp) + 800da84: dd800b15 stw r22,44(sp) + 800da88: dd400a15 stw r21,40(sp) + 800da8c: dcc00815 stw r19,32(sp) + 800da90: dc400615 stw r17,24(sp) + 800da94: 1081ffcc andi r2,r2,2047 + 800da98: 2025883a mov r18,r4 + 800da9c: 2c20703a and r16,r5,r16 + 800daa0: a02f883a mov r23,r20 + 800daa4: 10008926 beq r2,zero,800dccc <__divdf3+0x274> + 800daa8: 10c1ffe0 cmpeqi r3,r2,2047 + 800daac: 18009f1e bne r3,zero,800dd2c <__divdf3+0x2d4> + 800dab0: 800a90fa slli r5,r16,3 + 800dab4: 2008d77a srli r4,r4,29 + 800dab8: 902490fa slli r18,r18,3 + 800dabc: 157f0044 addi r21,r2,-1023 + 800dac0: 2148b03a or r4,r4,r5 + 800dac4: 25802034 orhi r22,r4,128 + 800dac8: 0023883a mov r17,zero + 800dacc: 0021883a mov r16,zero + 800dad0: 3806d53a srli r3,r7,20 + 800dad4: 01000434 movhi r4,16 + 800dad8: 213fffc4 addi r4,r4,-1 + 800dadc: 18c1ffcc andi r3,r3,2047 + 800dae0: 3926703a and r19,r7,r4 + 800dae4: 380ed7fa srli r7,r7,31 + 800dae8: 18006326 beq r3,zero,800dc78 <__divdf3+0x220> + 800daec: 1881ffe0 cmpeqi r2,r3,2047 + 800daf0: 1000201e bne r2,zero,800db74 <__divdf3+0x11c> + 800daf4: 980890fa slli r4,r19,3 + 800daf8: 300ad77a srli r5,r6,29 + 800dafc: 301090fa slli r8,r6,3 + 800db00: 18ff0044 addi r3,r3,-1023 + 800db04: 2908b03a or r4,r5,r4 + 800db08: a8ebc83a sub r21,r21,r3 + 800db0c: 24c02034 orhi r19,r4,128 + 800db10: 0007883a mov r3,zero + 800db14: 89800428 cmpgeui r6,r17,16 + 800db18: a1f8f03a xor fp,r20,r7 + 800db1c: 3000ad1e bne r6,zero,800ddd4 <__divdf3+0x37c> + 800db20: 882290ba slli r17,r17,2 + 800db24: 00820074 movhi r2,2049 + 800db28: 8885883a add r2,r17,r2 + 800db2c: 10b6cd17 ldw r2,-9420(r2) + 800db30: 1000683a jmp r2 + 800db34: 0800ddd4 ori zero,at,887 + 800db38: 0800dc68 cmpgeui zero,at,881 + 800db3c: 0800dc0c andi zero,at,880 + 800db40: 0800db90 cmplti zero,at,878 + 800db44: 0800dc0c andi zero,at,880 + 800db48: 0800dd90 cmplti zero,at,886 + 800db4c: 0800dc0c andi zero,at,880 + 800db50: 0800db90 cmplti zero,at,878 + 800db54: 0800dc68 cmpgeui zero,at,881 + 800db58: 0800dc68 cmpgeui zero,at,881 + 800db5c: 0800dd90 cmplti zero,at,886 + 800db60: 0800db90 cmplti zero,at,878 + 800db64: 0800dba0 cmpeqi zero,at,878 + 800db68: 0800dba0 cmpeqi zero,at,878 + 800db6c: 0800dba0 cmpeqi zero,at,878 + 800db70: 0800dda8 cmpgeui zero,at,886 + 800db74: 9990b03a or r8,r19,r6 + 800db78: ad7e0044 addi r21,r21,-2047 + 800db7c: 4000801e bne r8,zero,800dd80 <__divdf3+0x328> + 800db80: 8c400094 ori r17,r17,2 + 800db84: 0027883a mov r19,zero + 800db88: 00c00084 movi r3,2 + 800db8c: 003fe106 br 800db14 <__divdf3+0xbc> + 800db90: 382f883a mov r23,r7 + 800db94: 982d883a mov r22,r19 + 800db98: 4025883a mov r18,r8 + 800db9c: 1821883a mov r16,r3 + 800dba0: 808000a0 cmpeqi r2,r16,2 + 800dba4: 10017c1e bne r2,zero,800e198 <__divdf3+0x740> + 800dba8: 808000e0 cmpeqi r2,r16,3 + 800dbac: 1001ca1e bne r2,zero,800e2d8 <__divdf3+0x880> + 800dbb0: 80800060 cmpeqi r2,r16,1 + 800dbb4: 1000141e bne r2,zero,800dc08 <__divdf3+0x1b0> + 800dbb8: ac00ffc4 addi r16,r21,1023 + 800dbbc: b839883a mov fp,r23 + 800dbc0: 0401580e bge zero,r16,800e124 <__divdf3+0x6cc> + 800dbc4: 908001cc andi r2,r18,7 + 800dbc8: 1001921e bne r2,zero,800e214 <__divdf3+0x7bc> + 800dbcc: 900ad0fa srli r5,r18,3 + 800dbd0: b080402c andhi r2,r22,256 + 800dbd4: 10000426 beq r2,zero,800dbe8 <__divdf3+0x190> + 800dbd8: 00bfc034 movhi r2,65280 + 800dbdc: 10bfffc4 addi r2,r2,-1 + 800dbe0: b0ac703a and r22,r22,r2 + 800dbe4: ac010004 addi r16,r21,1024 + 800dbe8: 8081ffc8 cmpgei r2,r16,2047 + 800dbec: 10001e1e bne r2,zero,800dc68 <__divdf3+0x210> + 800dbf0: b024977a slli r18,r22,29 + 800dbf4: b008927a slli r4,r22,9 + 800dbf8: 8081ffcc andi r2,r16,2047 + 800dbfc: 9164b03a or r18,r18,r5 + 800dc00: 2008d33a srli r4,r4,12 + 800dc04: 00000406 br 800dc18 <__divdf3+0x1c0> + 800dc08: b839883a mov fp,r23 + 800dc0c: 0005883a mov r2,zero + 800dc10: 0009883a mov r4,zero + 800dc14: 0025883a mov r18,zero + 800dc18: 1004953a slli r2,r2,20 + 800dc1c: 00c00434 movhi r3,16 + 800dc20: e03897fa slli fp,fp,31 + 800dc24: 18ffffc4 addi r3,r3,-1 + 800dc28: 20c6703a and r3,r4,r3 + 800dc2c: 1886b03a or r3,r3,r2 + 800dc30: 1f06b03a or r3,r3,fp + 800dc34: 9005883a mov r2,r18 + 800dc38: dfc00e17 ldw ra,56(sp) + 800dc3c: df000d17 ldw fp,52(sp) + 800dc40: ddc00c17 ldw r23,48(sp) + 800dc44: dd800b17 ldw r22,44(sp) + 800dc48: dd400a17 ldw r21,40(sp) + 800dc4c: dd000917 ldw r20,36(sp) + 800dc50: dcc00817 ldw r19,32(sp) + 800dc54: dc800717 ldw r18,28(sp) + 800dc58: dc400617 ldw r17,24(sp) + 800dc5c: dc000517 ldw r16,20(sp) + 800dc60: dec00f04 addi sp,sp,60 + 800dc64: f800283a ret + 800dc68: 0081ffc4 movi r2,2047 + 800dc6c: 0009883a mov r4,zero + 800dc70: 0025883a mov r18,zero + 800dc74: 003fe806 br 800dc18 <__divdf3+0x1c0> + 800dc78: 9990b03a or r8,r19,r6 + 800dc7c: 40003c26 beq r8,zero,800dd70 <__divdf3+0x318> + 800dc80: 98011826 beq r19,zero,800e0e4 <__divdf3+0x68c> + 800dc84: 9809883a mov r4,r19 + 800dc88: d9800115 stw r6,4(sp) + 800dc8c: d9c00015 stw r7,0(sp) + 800dc90: 800f7900 call 800f790 <__clzsi2> + 800dc94: d9c00017 ldw r7,0(sp) + 800dc98: d9800117 ldw r6,4(sp) + 800dc9c: 117ffd44 addi r5,r2,-11 + 800dca0: 00c00744 movi r3,29 + 800dca4: 123ffe04 addi r8,r2,-8 + 800dca8: 1947c83a sub r3,r3,r5 + 800dcac: 9a08983a sll r4,r19,r8 + 800dcb0: 30c6d83a srl r3,r6,r3 + 800dcb4: 3210983a sll r8,r6,r8 + 800dcb8: 1926b03a or r19,r3,r4 + 800dcbc: 1545883a add r2,r2,r21 + 800dcc0: 1540fcc4 addi r21,r2,1011 + 800dcc4: 0007883a mov r3,zero + 800dcc8: 003f9206 br 800db14 <__divdf3+0xbc> + 800dccc: 242cb03a or r22,r4,r16 + 800dcd0: 2023883a mov r17,r4 + 800dcd4: b0002126 beq r22,zero,800dd5c <__divdf3+0x304> + 800dcd8: d9c00115 stw r7,4(sp) + 800dcdc: d9800015 stw r6,0(sp) + 800dce0: 8000f526 beq r16,zero,800e0b8 <__divdf3+0x660> + 800dce4: 8009883a mov r4,r16 + 800dce8: 800f7900 call 800f790 <__clzsi2> + 800dcec: d9800017 ldw r6,0(sp) + 800dcf0: d9c00117 ldw r7,4(sp) + 800dcf4: 102b883a mov r21,r2 + 800dcf8: 113ffd44 addi r4,r2,-11 + 800dcfc: 05800744 movi r22,29 + 800dd00: acbffe04 addi r18,r21,-8 + 800dd04: b12dc83a sub r22,r22,r4 + 800dd08: 848a983a sll r5,r16,r18 + 800dd0c: 8d88d83a srl r4,r17,r22 + 800dd10: 8ca4983a sll r18,r17,r18 + 800dd14: 216cb03a or r22,r4,r5 + 800dd18: 00bf0344 movi r2,-1011 + 800dd1c: 156bc83a sub r21,r2,r21 + 800dd20: 0023883a mov r17,zero + 800dd24: 0021883a mov r16,zero + 800dd28: 003f6906 br 800dad0 <__divdf3+0x78> + 800dd2c: 242cb03a or r22,r4,r16 + 800dd30: b000051e bne r22,zero,800dd48 <__divdf3+0x2f0> + 800dd34: 0025883a mov r18,zero + 800dd38: 04400204 movi r17,8 + 800dd3c: 0541ffc4 movi r21,2047 + 800dd40: 04000084 movi r16,2 + 800dd44: 003f6206 br 800dad0 <__divdf3+0x78> + 800dd48: 802d883a mov r22,r16 + 800dd4c: 04400304 movi r17,12 + 800dd50: 0541ffc4 movi r21,2047 + 800dd54: 040000c4 movi r16,3 + 800dd58: 003f5d06 br 800dad0 <__divdf3+0x78> + 800dd5c: 0025883a mov r18,zero + 800dd60: 04400104 movi r17,4 + 800dd64: 002b883a mov r21,zero + 800dd68: 04000044 movi r16,1 + 800dd6c: 003f5806 br 800dad0 <__divdf3+0x78> + 800dd70: 8c400054 ori r17,r17,1 + 800dd74: 0027883a mov r19,zero + 800dd78: 00c00044 movi r3,1 + 800dd7c: 003f6506 br 800db14 <__divdf3+0xbc> + 800dd80: 8c4000d4 ori r17,r17,3 + 800dd84: 3011883a mov r8,r6 + 800dd88: 00c000c4 movi r3,3 + 800dd8c: 003f6106 br 800db14 <__divdf3+0xbc> + 800dd90: 01000434 movhi r4,16 + 800dd94: 0039883a mov fp,zero + 800dd98: 213fffc4 addi r4,r4,-1 + 800dd9c: 04bfffc4 movi r18,-1 + 800dda0: 0081ffc4 movi r2,2047 + 800dda4: 003f9c06 br 800dc18 <__divdf3+0x1c0> + 800dda8: b080022c andhi r2,r22,8 + 800ddac: 1000a126 beq r2,zero,800e034 <__divdf3+0x5dc> + 800ddb0: 9880022c andhi r2,r19,8 + 800ddb4: 10009f1e bne r2,zero,800e034 <__divdf3+0x5dc> + 800ddb8: 00800434 movhi r2,16 + 800ddbc: 99000234 orhi r4,r19,8 + 800ddc0: 10bfffc4 addi r2,r2,-1 + 800ddc4: 2088703a and r4,r4,r2 + 800ddc8: 3839883a mov fp,r7 + 800ddcc: 4025883a mov r18,r8 + 800ddd0: 003ff306 br 800dda0 <__divdf3+0x348> + 800ddd4: 9d80b236 bltu r19,r22,800e0a0 <__divdf3+0x648> + 800ddd8: 9d80b026 beq r19,r22,800e09c <__divdf3+0x644> + 800dddc: ad7fffc4 addi r21,r21,-1 + 800dde0: b007883a mov r3,r22 + 800dde4: 0021883a mov r16,zero + 800dde8: 400cd63a srli r6,r8,24 + 800ddec: 9826923a slli r19,r19,8 + 800ddf0: 4004923a slli r2,r8,8 + 800ddf4: 1809883a mov r4,r3 + 800ddf8: 34e2b03a or r17,r6,r19 + 800ddfc: 8828d43a srli r20,r17,16 + 800de00: d8c00115 stw r3,4(sp) + 800de04: d8800015 stw r2,0(sp) + 800de08: a00b883a mov r5,r20 + 800de0c: 800cff80 call 800cff8 <__udivsi3> + 800de10: d8c00117 ldw r3,4(sp) + 800de14: a00b883a mov r5,r20 + 800de18: 102d883a mov r22,r2 + 800de1c: 1809883a mov r4,r3 + 800de20: 800d05c0 call 800d05c <__umodsi3> + 800de24: 1006943a slli r3,r2,16 + 800de28: 8dffffcc andi r23,r17,65535 + 800de2c: 9004d43a srli r2,r18,16 + 800de30: bda7383a mul r19,r23,r22 + 800de34: 10c4b03a or r2,r2,r3 + 800de38: 14c0042e bgeu r2,r19,800de4c <__divdf3+0x3f4> + 800de3c: 1445883a add r2,r2,r17 + 800de40: b0ffffc4 addi r3,r22,-1 + 800de44: 1440e12e bgeu r2,r17,800e1cc <__divdf3+0x774> + 800de48: 182d883a mov r22,r3 + 800de4c: 14e7c83a sub r19,r2,r19 + 800de50: a00b883a mov r5,r20 + 800de54: 9809883a mov r4,r19 + 800de58: 800cff80 call 800cff8 <__udivsi3> + 800de5c: a00b883a mov r5,r20 + 800de60: 9809883a mov r4,r19 + 800de64: d8800115 stw r2,4(sp) + 800de68: 800d05c0 call 800d05c <__umodsi3> + 800de6c: d8c00117 ldw r3,4(sp) + 800de70: 1004943a slli r2,r2,16 + 800de74: 94bfffcc andi r18,r18,65535 + 800de78: b8cb383a mul r5,r23,r3 + 800de7c: 9084b03a or r2,r18,r2 + 800de80: 1140042e bgeu r2,r5,800de94 <__divdf3+0x43c> + 800de84: 1445883a add r2,r2,r17 + 800de88: 193fffc4 addi r4,r3,-1 + 800de8c: 1440cb2e bgeu r2,r17,800e1bc <__divdf3+0x764> + 800de90: 2007883a mov r3,r4 + 800de94: b008943a slli r4,r22,16 + 800de98: d9800017 ldw r6,0(sp) + 800de9c: 1145c83a sub r2,r2,r5 + 800dea0: 20ecb03a or r22,r4,r3 + 800dea4: b0ffffcc andi r3,r22,65535 + 800dea8: 300ed43a srli r7,r6,16 + 800deac: 323fffcc andi r8,r6,65535 + 800deb0: b026d43a srli r19,r22,16 + 800deb4: 40e5383a mul r18,r8,r3 + 800deb8: 38c9383a mul r4,r7,r3 + 800debc: 9a13383a mul r9,r19,r8 + 800dec0: 9006d43a srli r3,r18,16 + 800dec4: 2249883a add r4,r4,r9 + 800dec8: 1907883a add r3,r3,r4 + 800decc: 99c9383a mul r4,r19,r7 + 800ded0: 1a40022e bgeu r3,r9,800dedc <__divdf3+0x484> + 800ded4: 01400074 movhi r5,1 + 800ded8: 2149883a add r4,r4,r5 + 800dedc: 1826d43a srli r19,r3,16 + 800dee0: 1806943a slli r3,r3,16 + 800dee4: 94bfffcc andi r18,r18,65535 + 800dee8: 9927883a add r19,r19,r4 + 800deec: 1ca5883a add r18,r3,r18 + 800def0: 14c05f36 bltu r2,r19,800e070 <__divdf3+0x618> + 800def4: 14c05d26 beq r2,r19,800e06c <__divdf3+0x614> + 800def8: 84a5c83a sub r18,r16,r18 + 800defc: 14c5c83a sub r2,r2,r19 + 800df00: 84a7803a cmpltu r19,r16,r18 + 800df04: da000215 stw r8,8(sp) + 800df08: d9c00115 stw r7,4(sp) + 800df0c: 14e7c83a sub r19,r2,r19 + 800df10: ac00ffc4 addi r16,r21,1023 + 800df14: 8cc0b626 beq r17,r19,800e1f0 <__divdf3+0x798> + 800df18: 9809883a mov r4,r19 + 800df1c: a00b883a mov r5,r20 + 800df20: 800cff80 call 800cff8 <__udivsi3> + 800df24: 9809883a mov r4,r19 + 800df28: a00b883a mov r5,r20 + 800df2c: d8800315 stw r2,12(sp) + 800df30: 800d05c0 call 800d05c <__umodsi3> + 800df34: d8c00317 ldw r3,12(sp) + 800df38: 1008943a slli r4,r2,16 + 800df3c: 9004d43a srli r2,r18,16 + 800df40: b8e7383a mul r19,r23,r3 + 800df44: d9c00117 ldw r7,4(sp) + 800df48: 1104b03a or r2,r2,r4 + 800df4c: da000217 ldw r8,8(sp) + 800df50: 14c0062e bgeu r2,r19,800df6c <__divdf3+0x514> + 800df54: 1445883a add r2,r2,r17 + 800df58: 193fffc4 addi r4,r3,-1 + 800df5c: 1440ab36 bltu r2,r17,800e20c <__divdf3+0x7b4> + 800df60: 14c0aa2e bgeu r2,r19,800e20c <__divdf3+0x7b4> + 800df64: 18ffff84 addi r3,r3,-2 + 800df68: 1445883a add r2,r2,r17 + 800df6c: 14e7c83a sub r19,r2,r19 + 800df70: a00b883a mov r5,r20 + 800df74: 9809883a mov r4,r19 + 800df78: da000415 stw r8,16(sp) + 800df7c: d8c00315 stw r3,12(sp) + 800df80: d9c00215 stw r7,8(sp) + 800df84: 800cff80 call 800cff8 <__udivsi3> + 800df88: a00b883a mov r5,r20 + 800df8c: 9809883a mov r4,r19 + 800df90: d8800115 stw r2,4(sp) + 800df94: 800d05c0 call 800d05c <__umodsi3> + 800df98: da400117 ldw r9,4(sp) + 800df9c: 1004943a slli r2,r2,16 + 800dfa0: 94bfffcc andi r18,r18,65535 + 800dfa4: ba6f383a mul r23,r23,r9 + 800dfa8: 9084b03a or r2,r18,r2 + 800dfac: d9c00217 ldw r7,8(sp) + 800dfb0: d8c00317 ldw r3,12(sp) + 800dfb4: da000417 ldw r8,16(sp) + 800dfb8: 15c0062e bgeu r2,r23,800dfd4 <__divdf3+0x57c> + 800dfbc: 1445883a add r2,r2,r17 + 800dfc0: 493fffc4 addi r4,r9,-1 + 800dfc4: 14408f36 bltu r2,r17,800e204 <__divdf3+0x7ac> + 800dfc8: 15c08e2e bgeu r2,r23,800e204 <__divdf3+0x7ac> + 800dfcc: 4a7fff84 addi r9,r9,-2 + 800dfd0: 1445883a add r2,r2,r17 + 800dfd4: 180a943a slli r5,r3,16 + 800dfd8: 15c5c83a sub r2,r2,r23 + 800dfdc: 2a64b03a or r18,r5,r9 + 800dfe0: 9012d43a srli r9,r18,16 + 800dfe4: 913fffcc andi r4,r18,65535 + 800dfe8: 220b383a mul r5,r4,r8 + 800dfec: 3909383a mul r4,r7,r4 + 800dff0: 4a11383a mul r8,r9,r8 + 800dff4: 2806d43a srli r3,r5,16 + 800dff8: 3a4f383a mul r7,r7,r9 + 800dffc: 2209883a add r4,r4,r8 + 800e000: 1907883a add r3,r3,r4 + 800e004: 1a00022e bgeu r3,r8,800e010 <__divdf3+0x5b8> + 800e008: 01000074 movhi r4,1 + 800e00c: 390f883a add r7,r7,r4 + 800e010: 1808d43a srli r4,r3,16 + 800e014: 1806943a slli r3,r3,16 + 800e018: 297fffcc andi r5,r5,65535 + 800e01c: 21cf883a add r7,r4,r7 + 800e020: 1947883a add r3,r3,r5 + 800e024: 11c00a36 bltu r2,r7,800e050 <__divdf3+0x5f8> + 800e028: 11c00826 beq r2,r7,800e04c <__divdf3+0x5f4> + 800e02c: 94800054 ori r18,r18,1 + 800e030: 003ee306 br 800dbc0 <__divdf3+0x168> + 800e034: 00800434 movhi r2,16 + 800e038: b1000234 orhi r4,r22,8 + 800e03c: 10bfffc4 addi r2,r2,-1 + 800e040: 2088703a and r4,r4,r2 + 800e044: a039883a mov fp,r20 + 800e048: 003f5506 br 800dda0 <__divdf3+0x348> + 800e04c: 183edc26 beq r3,zero,800dbc0 <__divdf3+0x168> + 800e050: 8885883a add r2,r17,r2 + 800e054: 913fffc4 addi r4,r18,-1 + 800e058: 14406036 bltu r2,r17,800e1dc <__divdf3+0x784> + 800e05c: 11c07d36 bltu r2,r7,800e254 <__divdf3+0x7fc> + 800e060: 11c0a326 beq r2,r7,800e2f0 <__divdf3+0x898> + 800e064: 2025883a mov r18,r4 + 800e068: 003ff006 br 800e02c <__divdf3+0x5d4> + 800e06c: 84bfa22e bgeu r16,r18,800def8 <__divdf3+0x4a0> + 800e070: d8c00017 ldw r3,0(sp) + 800e074: 80e1883a add r16,r16,r3 + 800e078: 80c7803a cmpltu r3,r16,r3 + 800e07c: 1c47883a add r3,r3,r17 + 800e080: 10c5883a add r2,r2,r3 + 800e084: b0ffffc4 addi r3,r22,-1 + 800e088: 8880482e bgeu r17,r2,800e1ac <__divdf3+0x754> + 800e08c: 14c06a36 bltu r2,r19,800e238 <__divdf3+0x7e0> + 800e090: 98806826 beq r19,r2,800e234 <__divdf3+0x7dc> + 800e094: 182d883a mov r22,r3 + 800e098: 003f9706 br 800def8 <__divdf3+0x4a0> + 800e09c: 923f4f36 bltu r18,r8,800dddc <__divdf3+0x384> + 800e0a0: b00a97fa slli r5,r22,31 + 800e0a4: 9004d07a srli r2,r18,1 + 800e0a8: 902097fa slli r16,r18,31 + 800e0ac: b006d07a srli r3,r22,1 + 800e0b0: 28a4b03a or r18,r5,r2 + 800e0b4: 003f4c06 br 800dde8 <__divdf3+0x390> + 800e0b8: 800f7900 call 800f790 <__clzsi2> + 800e0bc: 11000544 addi r4,r2,21 + 800e0c0: 21400748 cmpgei r5,r4,29 + 800e0c4: 15400804 addi r21,r2,32 + 800e0c8: d9800017 ldw r6,0(sp) + 800e0cc: d9c00117 ldw r7,4(sp) + 800e0d0: 283f0a26 beq r5,zero,800dcfc <__divdf3+0x2a4> + 800e0d4: 113ffe04 addi r4,r2,-8 + 800e0d8: 912c983a sll r22,r18,r4 + 800e0dc: 0025883a mov r18,zero + 800e0e0: 003f0d06 br 800dd18 <__divdf3+0x2c0> + 800e0e4: 3009883a mov r4,r6 + 800e0e8: d9c00115 stw r7,4(sp) + 800e0ec: d9800015 stw r6,0(sp) + 800e0f0: 800f7900 call 800f790 <__clzsi2> + 800e0f4: 11400544 addi r5,r2,21 + 800e0f8: 28c00748 cmpgei r3,r5,29 + 800e0fc: 1009883a mov r4,r2 + 800e100: d9800017 ldw r6,0(sp) + 800e104: 10800804 addi r2,r2,32 + 800e108: d9c00117 ldw r7,4(sp) + 800e10c: 183ee426 beq r3,zero,800dca0 <__divdf3+0x248> + 800e110: 213ffe04 addi r4,r4,-8 + 800e114: 3126983a sll r19,r6,r4 + 800e118: 0011883a mov r8,zero + 800e11c: 003ee706 br 800dcbc <__divdf3+0x264> + 800e120: 04bfffc4 movi r18,-1 + 800e124: 01000044 movi r4,1 + 800e128: 2409c83a sub r4,r4,r16 + 800e12c: 20800e48 cmpgei r2,r4,57 + 800e130: 103eb61e bne r2,zero,800dc0c <__divdf3+0x1b4> + 800e134: 20800808 cmpgei r2,r4,32 + 800e138: 10004e1e bne r2,zero,800e274 <__divdf3+0x81c> + 800e13c: a8810784 addi r2,r21,1054 + 800e140: b086983a sll r3,r22,r2 + 800e144: 910ad83a srl r5,r18,r4 + 800e148: 9084983a sll r2,r18,r2 + 800e14c: b108d83a srl r4,r22,r4 + 800e150: 1964b03a or r18,r3,r5 + 800e154: 1004c03a cmpne r2,r2,zero + 800e158: 90a4b03a or r18,r18,r2 + 800e15c: 908001cc andi r2,r18,7 + 800e160: 10000726 beq r2,zero,800e180 <__divdf3+0x728> + 800e164: 908003cc andi r2,r18,15 + 800e168: 10800120 cmpeqi r2,r2,4 + 800e16c: 1000041e bne r2,zero,800e180 <__divdf3+0x728> + 800e170: 90800104 addi r2,r18,4 + 800e174: 14a5803a cmpltu r18,r2,r18 + 800e178: 2489883a add r4,r4,r18 + 800e17c: 1025883a mov r18,r2 + 800e180: 2080202c andhi r2,r4,128 + 800e184: 10005026 beq r2,zero,800e2c8 <__divdf3+0x870> + 800e188: 00800044 movi r2,1 + 800e18c: 0009883a mov r4,zero + 800e190: 0025883a mov r18,zero + 800e194: 003ea006 br 800dc18 <__divdf3+0x1c0> + 800e198: b839883a mov fp,r23 + 800e19c: 0081ffc4 movi r2,2047 + 800e1a0: 0009883a mov r4,zero + 800e1a4: 0025883a mov r18,zero + 800e1a8: 003e9b06 br 800dc18 <__divdf3+0x1c0> + 800e1ac: 88bfb91e bne r17,r2,800e094 <__divdf3+0x63c> + 800e1b0: d9000017 ldw r4,0(sp) + 800e1b4: 813fb736 bltu r16,r4,800e094 <__divdf3+0x63c> + 800e1b8: 003fb406 br 800e08c <__divdf3+0x634> + 800e1bc: 117f342e bgeu r2,r5,800de90 <__divdf3+0x438> + 800e1c0: 18ffff84 addi r3,r3,-2 + 800e1c4: 1445883a add r2,r2,r17 + 800e1c8: 003f3206 br 800de94 <__divdf3+0x43c> + 800e1cc: 14ff1e2e bgeu r2,r19,800de48 <__divdf3+0x3f0> + 800e1d0: b5bfff84 addi r22,r22,-2 + 800e1d4: 1445883a add r2,r2,r17 + 800e1d8: 003f1c06 br 800de4c <__divdf3+0x3f4> + 800e1dc: 2025883a mov r18,r4 + 800e1e0: 11ff921e bne r2,r7,800e02c <__divdf3+0x5d4> + 800e1e4: d8800017 ldw r2,0(sp) + 800e1e8: 10ff901e bne r2,r3,800e02c <__divdf3+0x5d4> + 800e1ec: 003e7406 br 800dbc0 <__divdf3+0x168> + 800e1f0: 043fcb0e bge zero,r16,800e120 <__divdf3+0x6c8> + 800e1f4: 000b883a mov r5,zero + 800e1f8: 04800044 movi r18,1 + 800e1fc: b4ad883a add r22,r22,r18 + 800e200: 003e7306 br 800dbd0 <__divdf3+0x178> + 800e204: 2013883a mov r9,r4 + 800e208: 003f7206 br 800dfd4 <__divdf3+0x57c> + 800e20c: 2007883a mov r3,r4 + 800e210: 003f5606 br 800df6c <__divdf3+0x514> + 800e214: 908003cc andi r2,r18,15 + 800e218: 10800118 cmpnei r2,r2,4 + 800e21c: 103e6b26 beq r2,zero,800dbcc <__divdf3+0x174> + 800e220: 91400104 addi r5,r18,4 + 800e224: 00bffec4 movi r2,-5 + 800e228: 14a5803a cmpltu r18,r2,r18 + 800e22c: 280ad0fa srli r5,r5,3 + 800e230: 003ff206 br 800e1fc <__divdf3+0x7a4> + 800e234: 84bf972e bgeu r16,r18,800e094 <__divdf3+0x63c> + 800e238: d8c00017 ldw r3,0(sp) + 800e23c: b5bfff84 addi r22,r22,-2 + 800e240: 80e1883a add r16,r16,r3 + 800e244: 80c7803a cmpltu r3,r16,r3 + 800e248: 1c47883a add r3,r3,r17 + 800e24c: 10c5883a add r2,r2,r3 + 800e250: 003f2906 br 800def8 <__divdf3+0x4a0> + 800e254: d9400017 ldw r5,0(sp) + 800e258: 94bfff84 addi r18,r18,-2 + 800e25c: 2949883a add r4,r5,r5 + 800e260: 214b803a cmpltu r5,r4,r5 + 800e264: 2c4d883a add r6,r5,r17 + 800e268: 1185883a add r2,r2,r6 + 800e26c: d9000015 stw r4,0(sp) + 800e270: 003fdb06 br 800e1e0 <__divdf3+0x788> + 800e274: 00bff844 movi r2,-31 + 800e278: 1421c83a sub r16,r2,r16 + 800e27c: 21000820 cmpeqi r4,r4,32 + 800e280: b420d83a srl r16,r22,r16 + 800e284: 2000031e bne r4,zero,800e294 <__divdf3+0x83c> + 800e288: a8810f84 addi r2,r21,1086 + 800e28c: b088983a sll r4,r22,r2 + 800e290: 9124b03a or r18,r18,r4 + 800e294: 9024c03a cmpne r18,r18,zero + 800e298: 9424b03a or r18,r18,r16 + 800e29c: 914001cc andi r5,r18,7 + 800e2a0: 2800051e bne r5,zero,800e2b8 <__divdf3+0x860> + 800e2a4: 0009883a mov r4,zero + 800e2a8: 9024d0fa srli r18,r18,3 + 800e2ac: 0005883a mov r2,zero + 800e2b0: 9164b03a or r18,r18,r5 + 800e2b4: 003e5806 br 800dc18 <__divdf3+0x1c0> + 800e2b8: 908003cc andi r2,r18,15 + 800e2bc: 10800118 cmpnei r2,r2,4 + 800e2c0: 0009883a mov r4,zero + 800e2c4: 103faa1e bne r2,zero,800e170 <__divdf3+0x718> + 800e2c8: 2004927a slli r2,r4,9 + 800e2cc: 200a977a slli r5,r4,29 + 800e2d0: 1008d33a srli r4,r2,12 + 800e2d4: 003ff406 br 800e2a8 <__divdf3+0x850> + 800e2d8: 00800434 movhi r2,16 + 800e2dc: b1000234 orhi r4,r22,8 + 800e2e0: 10bfffc4 addi r2,r2,-1 + 800e2e4: 2088703a and r4,r4,r2 + 800e2e8: b839883a mov fp,r23 + 800e2ec: 003eac06 br 800dda0 <__divdf3+0x348> + 800e2f0: d9400017 ldw r5,0(sp) + 800e2f4: 28ffd736 bltu r5,r3,800e254 <__divdf3+0x7fc> + 800e2f8: 2025883a mov r18,r4 + 800e2fc: 003fb906 br 800e1e4 <__divdf3+0x78c> + +0800e300 <__eqdf2>: + 800e300: 2810d53a srli r8,r5,20 + 800e304: 3806d53a srli r3,r7,20 + 800e308: 00800434 movhi r2,16 + 800e30c: 4201ffcc andi r8,r8,2047 + 800e310: 10bfffc4 addi r2,r2,-1 + 800e314: 4281ffd8 cmpnei r10,r8,2047 + 800e318: 2892703a and r9,r5,r2 + 800e31c: 18c1ffcc andi r3,r3,2047 + 800e320: 3884703a and r2,r7,r2 + 800e324: 280ad7fa srli r5,r5,31 + 800e328: 380ed7fa srli r7,r7,31 + 800e32c: 50000626 beq r10,zero,800e348 <__eqdf2+0x48> + 800e330: 1a81ffe0 cmpeqi r10,r3,2047 + 800e334: 5000021e bne r10,zero,800e340 <__eqdf2+0x40> + 800e338: 40c0011e bne r8,r3,800e340 <__eqdf2+0x40> + 800e33c: 48800826 beq r9,r2,800e360 <__eqdf2+0x60> + 800e340: 00800044 movi r2,1 + 800e344: f800283a ret + 800e348: 4914b03a or r10,r9,r4 + 800e34c: 503ffc1e bne r10,zero,800e340 <__eqdf2+0x40> + 800e350: 18c1ffd8 cmpnei r3,r3,2047 + 800e354: 183ffa1e bne r3,zero,800e340 <__eqdf2+0x40> + 800e358: 1184b03a or r2,r2,r6 + 800e35c: 103ff81e bne r2,zero,800e340 <__eqdf2+0x40> + 800e360: 21bff71e bne r4,r6,800e340 <__eqdf2+0x40> + 800e364: 29c00426 beq r5,r7,800e378 <__eqdf2+0x78> + 800e368: 403ff51e bne r8,zero,800e340 <__eqdf2+0x40> + 800e36c: 4904b03a or r2,r9,r4 + 800e370: 1004c03a cmpne r2,r2,zero + 800e374: f800283a ret + 800e378: 0005883a mov r2,zero + 800e37c: f800283a ret + +0800e380 <__gedf2>: + 800e380: 2810d53a srli r8,r5,20 + 800e384: 3812d53a srli r9,r7,20 + 800e388: 00800434 movhi r2,16 + 800e38c: 4201ffcc andi r8,r8,2047 + 800e390: 10bfffc4 addi r2,r2,-1 + 800e394: 4281ffd8 cmpnei r10,r8,2047 + 800e398: 2896703a and r11,r5,r2 + 800e39c: 3886703a and r3,r7,r2 + 800e3a0: 280ad7fa srli r5,r5,31 + 800e3a4: 4a41ffcc andi r9,r9,2047 + 800e3a8: 3804d7fa srli r2,r7,31 + 800e3ac: 50000b26 beq r10,zero,800e3dc <__gedf2+0x5c> + 800e3b0: 49c1ffd8 cmpnei r7,r9,2047 + 800e3b4: 38000d26 beq r7,zero,800e3ec <__gedf2+0x6c> + 800e3b8: 4000191e bne r8,zero,800e420 <__gedf2+0xa0> + 800e3bc: 5914b03a or r10,r11,r4 + 800e3c0: 500f003a cmpeq r7,r10,zero + 800e3c4: 4800131e bne r9,zero,800e414 <__gedf2+0x94> + 800e3c8: 1998b03a or r12,r3,r6 + 800e3cc: 6000111e bne r12,zero,800e414 <__gedf2+0x94> + 800e3d0: 50000a1e bne r10,zero,800e3fc <__gedf2+0x7c> + 800e3d4: 0005883a mov r2,zero + 800e3d8: f800283a ret + 800e3dc: 590eb03a or r7,r11,r4 + 800e3e0: 38001e1e bne r7,zero,800e45c <__gedf2+0xdc> + 800e3e4: 49c1ffe0 cmpeqi r7,r9,2047 + 800e3e8: 38000d26 beq r7,zero,800e420 <__gedf2+0xa0> + 800e3ec: 198eb03a or r7,r3,r6 + 800e3f0: 38001a1e bne r7,zero,800e45c <__gedf2+0xdc> + 800e3f4: 40000526 beq r8,zero,800e40c <__gedf2+0x8c> + 800e3f8: 28800d26 beq r5,r2,800e430 <__gedf2+0xb0> + 800e3fc: 00800044 movi r2,1 + 800e400: 28000626 beq r5,zero,800e41c <__gedf2+0x9c> + 800e404: 00bfffc4 movi r2,-1 + 800e408: f800283a ret + 800e40c: 590eb03a or r7,r11,r4 + 800e410: 380f003a cmpeq r7,r7,zero + 800e414: 383ff826 beq r7,zero,800e3f8 <__gedf2+0x78> + 800e418: 103ffa26 beq r2,zero,800e404 <__gedf2+0x84> + 800e41c: f800283a ret + 800e420: 483ff51e bne r9,zero,800e3f8 <__gedf2+0x78> + 800e424: 198eb03a or r7,r3,r6 + 800e428: 383ff31e bne r7,zero,800e3f8 <__gedf2+0x78> + 800e42c: 003ff306 br 800e3fc <__gedf2+0x7c> + 800e430: 4a000716 blt r9,r8,800e450 <__gedf2+0xd0> + 800e434: 427ff816 blt r8,r9,800e418 <__gedf2+0x98> + 800e438: 1afff036 bltu r3,r11,800e3fc <__gedf2+0x7c> + 800e43c: 58c00926 beq r11,r3,800e464 <__gedf2+0xe4> + 800e440: 58ffe42e bgeu r11,r3,800e3d4 <__gedf2+0x54> + 800e444: 283fef26 beq r5,zero,800e404 <__gedf2+0x84> + 800e448: 2805883a mov r2,r5 + 800e44c: f800283a ret + 800e450: 103fec1e bne r2,zero,800e404 <__gedf2+0x84> + 800e454: 00800044 movi r2,1 + 800e458: f800283a ret + 800e45c: 00bfff84 movi r2,-2 + 800e460: f800283a ret + 800e464: 313fe536 bltu r6,r4,800e3fc <__gedf2+0x7c> + 800e468: 21bfda2e bgeu r4,r6,800e3d4 <__gedf2+0x54> + 800e46c: 003ff506 br 800e444 <__gedf2+0xc4> + +0800e470 <__ledf2>: + 800e470: 2810d53a srli r8,r5,20 + 800e474: 3812d53a srli r9,r7,20 + 800e478: 00800434 movhi r2,16 + 800e47c: 4201ffcc andi r8,r8,2047 + 800e480: 10bfffc4 addi r2,r2,-1 + 800e484: 4281ffd8 cmpnei r10,r8,2047 + 800e488: 2896703a and r11,r5,r2 + 800e48c: 3886703a and r3,r7,r2 + 800e490: 280ad7fa srli r5,r5,31 + 800e494: 4a41ffcc andi r9,r9,2047 + 800e498: 3804d7fa srli r2,r7,31 + 800e49c: 50000b26 beq r10,zero,800e4cc <__ledf2+0x5c> + 800e4a0: 49c1ffd8 cmpnei r7,r9,2047 + 800e4a4: 38000d26 beq r7,zero,800e4dc <__ledf2+0x6c> + 800e4a8: 40001b1e bne r8,zero,800e518 <__ledf2+0xa8> + 800e4ac: 5914b03a or r10,r11,r4 + 800e4b0: 500f003a cmpeq r7,r10,zero + 800e4b4: 48000e1e bne r9,zero,800e4f0 <__ledf2+0x80> + 800e4b8: 1998b03a or r12,r3,r6 + 800e4bc: 60000c1e bne r12,zero,800e4f0 <__ledf2+0x80> + 800e4c0: 50000d1e bne r10,zero,800e4f8 <__ledf2+0x88> + 800e4c4: 0005883a mov r2,zero + 800e4c8: f800283a ret + 800e4cc: 590eb03a or r7,r11,r4 + 800e4d0: 38000d1e bne r7,zero,800e508 <__ledf2+0x98> + 800e4d4: 49c1ffe0 cmpeqi r7,r9,2047 + 800e4d8: 38000f26 beq r7,zero,800e518 <__ledf2+0xa8> + 800e4dc: 198eb03a or r7,r3,r6 + 800e4e0: 3800091e bne r7,zero,800e508 <__ledf2+0x98> + 800e4e4: 4000031e bne r8,zero,800e4f4 <__ledf2+0x84> + 800e4e8: 590eb03a or r7,r11,r4 + 800e4ec: 380f003a cmpeq r7,r7,zero + 800e4f0: 3800071e bne r7,zero,800e510 <__ledf2+0xa0> + 800e4f4: 28800c26 beq r5,r2,800e528 <__ledf2+0xb8> + 800e4f8: 00800044 movi r2,1 + 800e4fc: 28000526 beq r5,zero,800e514 <__ledf2+0xa4> + 800e500: 00bfffc4 movi r2,-1 + 800e504: f800283a ret + 800e508: 00800084 movi r2,2 + 800e50c: f800283a ret + 800e510: 103ffb26 beq r2,zero,800e500 <__ledf2+0x90> + 800e514: f800283a ret + 800e518: 483ff61e bne r9,zero,800e4f4 <__ledf2+0x84> + 800e51c: 198eb03a or r7,r3,r6 + 800e520: 383ff41e bne r7,zero,800e4f4 <__ledf2+0x84> + 800e524: 003ff406 br 800e4f8 <__ledf2+0x88> + 800e528: 4a00030e bge r9,r8,800e538 <__ledf2+0xc8> + 800e52c: 103ff41e bne r2,zero,800e500 <__ledf2+0x90> + 800e530: 00800044 movi r2,1 + 800e534: f800283a ret + 800e538: 427ff516 blt r8,r9,800e510 <__ledf2+0xa0> + 800e53c: 1affee36 bltu r3,r11,800e4f8 <__ledf2+0x88> + 800e540: 58c00426 beq r11,r3,800e554 <__ledf2+0xe4> + 800e544: 58ffdf2e bgeu r11,r3,800e4c4 <__ledf2+0x54> + 800e548: 283fed26 beq r5,zero,800e500 <__ledf2+0x90> + 800e54c: 2805883a mov r2,r5 + 800e550: f800283a ret + 800e554: 313fe836 bltu r6,r4,800e4f8 <__ledf2+0x88> + 800e558: 21bfda2e bgeu r4,r6,800e4c4 <__ledf2+0x54> + 800e55c: 003ffa06 br 800e548 <__ledf2+0xd8> + +0800e560 <__muldf3>: + 800e560: 2806d53a srli r3,r5,20 + 800e564: defff504 addi sp,sp,-44 + 800e568: dc000215 stw r16,8(sp) + 800e56c: 04000434 movhi r16,16 + 800e570: dd000615 stw r20,24(sp) + 800e574: dc800415 stw r18,16(sp) + 800e578: 843fffc4 addi r16,r16,-1 + 800e57c: dfc00a15 stw ra,40(sp) + 800e580: ddc00915 stw r23,36(sp) + 800e584: dd800815 stw r22,32(sp) + 800e588: dd400715 stw r21,28(sp) + 800e58c: dcc00515 stw r19,20(sp) + 800e590: dc400315 stw r17,12(sp) + 800e594: 18c1ffcc andi r3,r3,2047 + 800e598: 2025883a mov r18,r4 + 800e59c: 2c20703a and r16,r5,r16 + 800e5a0: 2828d7fa srli r20,r5,31 + 800e5a4: 18005c26 beq r3,zero,800e718 <__muldf3+0x1b8> + 800e5a8: 1881ffe0 cmpeqi r2,r3,2047 + 800e5ac: 1000711e bne r2,zero,800e774 <__muldf3+0x214> + 800e5b0: 800490fa slli r2,r16,3 + 800e5b4: 2020d77a srli r16,r4,29 + 800e5b8: 202290fa slli r17,r4,3 + 800e5bc: 1cff0044 addi r19,r3,-1023 + 800e5c0: 80a0b03a or r16,r16,r2 + 800e5c4: 84002034 orhi r16,r16,128 + 800e5c8: 002d883a mov r22,zero + 800e5cc: 002f883a mov r23,zero + 800e5d0: 3806d53a srli r3,r7,20 + 800e5d4: 01000434 movhi r4,16 + 800e5d8: 213fffc4 addi r4,r4,-1 + 800e5dc: 18c1ffcc andi r3,r3,2047 + 800e5e0: 3924703a and r18,r7,r4 + 800e5e4: 382ad7fa srli r21,r7,31 + 800e5e8: 18006926 beq r3,zero,800e790 <__muldf3+0x230> + 800e5ec: 1881ffe0 cmpeqi r2,r3,2047 + 800e5f0: 1000211e bne r2,zero,800e678 <__muldf3+0x118> + 800e5f4: 900890fa slli r4,r18,3 + 800e5f8: 300ad77a srli r5,r6,29 + 800e5fc: 301090fa slli r8,r6,3 + 800e600: 18ff0044 addi r3,r3,-1023 + 800e604: 2908b03a or r4,r5,r4 + 800e608: 98e7883a add r19,r19,r3 + 800e60c: 24802034 orhi r18,r4,128 + 800e610: 0007883a mov r3,zero + 800e614: b1000428 cmpgeui r4,r22,16 + 800e618: a54cf03a xor r6,r20,r21 + 800e61c: 99400044 addi r5,r19,1 + 800e620: 2000981e bne r4,zero,800e884 <__muldf3+0x324> + 800e624: b00890ba slli r4,r22,2 + 800e628: 00820074 movhi r2,2049 + 800e62c: 2085883a add r2,r4,r2 + 800e630: 10b98e17 ldw r2,-6600(r2) + 800e634: 1000683a jmp r2 + 800e638: 0800e884 addi zero,at,930 + 800e63c: 0800e698 cmpnei zero,at,922 + 800e640: 0800e698 cmpnei zero,at,922 + 800e644: 0800e694 ori zero,at,922 + 800e648: 0800e6a4 muli zero,at,922 + 800e64c: 0800e6a4 muli zero,at,922 + 800e650: 0800e840 call 800e84 + 800e654: 0800e694 ori zero,at,922 + 800e658: 0800e6a4 muli zero,at,922 + 800e65c: 0800e840 call 800e84 + 800e660: 0800e6a4 muli zero,at,922 + 800e664: 0800e694 ori zero,at,922 + 800e668: 0800e838 rdprs zero,at,928 + 800e66c: 0800e838 rdprs zero,at,928 + 800e670: 0800e838 rdprs zero,at,928 + 800e674: 0800e858 cmpnei zero,at,929 + 800e678: 3490b03a or r8,r6,r18 + 800e67c: 9cc1ffc4 addi r19,r19,2047 + 800e680: 4000691e bne r8,zero,800e828 <__muldf3+0x2c8> + 800e684: b5800094 ori r22,r22,2 + 800e688: 0025883a mov r18,zero + 800e68c: 00c00084 movi r3,2 + 800e690: 003fe006 br 800e614 <__muldf3+0xb4> + 800e694: a80d883a mov r6,r21 + 800e698: 9021883a mov r16,r18 + 800e69c: 4023883a mov r17,r8 + 800e6a0: 182f883a mov r23,r3 + 800e6a4: b88000a0 cmpeqi r2,r23,2 + 800e6a8: 10004d1e bne r2,zero,800e7e0 <__muldf3+0x280> + 800e6ac: b88000e0 cmpeqi r2,r23,3 + 800e6b0: 1001491e bne r2,zero,800ebd8 <__muldf3+0x678> + 800e6b4: b8800060 cmpeqi r2,r23,1 + 800e6b8: 1000d826 beq r2,zero,800ea1c <__muldf3+0x4bc> + 800e6bc: 0007883a mov r3,zero + 800e6c0: 0021883a mov r16,zero + 800e6c4: 0023883a mov r17,zero + 800e6c8: 30803fcc andi r2,r6,255 + 800e6cc: 01000434 movhi r4,16 + 800e6d0: 1806953a slli r3,r3,20 + 800e6d4: 213fffc4 addi r4,r4,-1 + 800e6d8: 100497fa slli r2,r2,31 + 800e6dc: 8120703a and r16,r16,r4 + 800e6e0: 80c6b03a or r3,r16,r3 + 800e6e4: 1886b03a or r3,r3,r2 + 800e6e8: 8805883a mov r2,r17 + 800e6ec: dfc00a17 ldw ra,40(sp) + 800e6f0: ddc00917 ldw r23,36(sp) + 800e6f4: dd800817 ldw r22,32(sp) + 800e6f8: dd400717 ldw r21,28(sp) + 800e6fc: dd000617 ldw r20,24(sp) + 800e700: dcc00517 ldw r19,20(sp) + 800e704: dc800417 ldw r18,16(sp) + 800e708: dc400317 ldw r17,12(sp) + 800e70c: dc000217 ldw r16,8(sp) + 800e710: dec00b04 addi sp,sp,44 + 800e714: f800283a ret + 800e718: 8122b03a or r17,r16,r4 + 800e71c: 88003d26 beq r17,zero,800e814 <__muldf3+0x2b4> + 800e720: d9c00115 stw r7,4(sp) + 800e724: d9800015 stw r6,0(sp) + 800e728: 8000e826 beq r16,zero,800eacc <__muldf3+0x56c> + 800e72c: 8009883a mov r4,r16 + 800e730: 800f7900 call 800f790 <__clzsi2> + 800e734: d9800017 ldw r6,0(sp) + 800e738: d9c00117 ldw r7,4(sp) + 800e73c: 1007883a mov r3,r2 + 800e740: 117ffd44 addi r5,r2,-11 + 800e744: 01000744 movi r4,29 + 800e748: 1c7ffe04 addi r17,r3,-8 + 800e74c: 2149c83a sub r4,r4,r5 + 800e750: 8460983a sll r16,r16,r17 + 800e754: 9108d83a srl r4,r18,r4 + 800e758: 9462983a sll r17,r18,r17 + 800e75c: 2420b03a or r16,r4,r16 + 800e760: 04ff0344 movi r19,-1011 + 800e764: 98e7c83a sub r19,r19,r3 + 800e768: 002d883a mov r22,zero + 800e76c: 002f883a mov r23,zero + 800e770: 003f9706 br 800e5d0 <__muldf3+0x70> + 800e774: 8122b03a or r17,r16,r4 + 800e778: 8800211e bne r17,zero,800e800 <__muldf3+0x2a0> + 800e77c: 0021883a mov r16,zero + 800e780: 05800204 movi r22,8 + 800e784: 04c1ffc4 movi r19,2047 + 800e788: 05c00084 movi r23,2 + 800e78c: 003f9006 br 800e5d0 <__muldf3+0x70> + 800e790: 3490b03a or r8,r6,r18 + 800e794: 40001626 beq r8,zero,800e7f0 <__muldf3+0x290> + 800e798: 9000c026 beq r18,zero,800ea9c <__muldf3+0x53c> + 800e79c: 9009883a mov r4,r18 + 800e7a0: d9800015 stw r6,0(sp) + 800e7a4: 800f7900 call 800f790 <__clzsi2> + 800e7a8: d9800017 ldw r6,0(sp) + 800e7ac: 1007883a mov r3,r2 + 800e7b0: 113ffd44 addi r4,r2,-11 + 800e7b4: 01400744 movi r5,29 + 800e7b8: 1a3ffe04 addi r8,r3,-8 + 800e7bc: 290bc83a sub r5,r5,r4 + 800e7c0: 314ad83a srl r5,r6,r5 + 800e7c4: 9208983a sll r4,r18,r8 + 800e7c8: 3210983a sll r8,r6,r8 + 800e7cc: 2924b03a or r18,r5,r4 + 800e7d0: 98c7c83a sub r3,r19,r3 + 800e7d4: 1cff0344 addi r19,r3,-1011 + 800e7d8: 0007883a mov r3,zero + 800e7dc: 003f8d06 br 800e614 <__muldf3+0xb4> + 800e7e0: 00c1ffc4 movi r3,2047 + 800e7e4: 0021883a mov r16,zero + 800e7e8: 0023883a mov r17,zero + 800e7ec: 003fb606 br 800e6c8 <__muldf3+0x168> + 800e7f0: b5800054 ori r22,r22,1 + 800e7f4: 0025883a mov r18,zero + 800e7f8: 00c00044 movi r3,1 + 800e7fc: 003f8506 br 800e614 <__muldf3+0xb4> + 800e800: 2023883a mov r17,r4 + 800e804: 05800304 movi r22,12 + 800e808: 04c1ffc4 movi r19,2047 + 800e80c: 05c000c4 movi r23,3 + 800e810: 003f6f06 br 800e5d0 <__muldf3+0x70> + 800e814: 0021883a mov r16,zero + 800e818: 05800104 movi r22,4 + 800e81c: 0027883a mov r19,zero + 800e820: 05c00044 movi r23,1 + 800e824: 003f6a06 br 800e5d0 <__muldf3+0x70> + 800e828: b58000d4 ori r22,r22,3 + 800e82c: 3011883a mov r8,r6 + 800e830: 00c000c4 movi r3,3 + 800e834: 003f7706 br 800e614 <__muldf3+0xb4> + 800e838: a00d883a mov r6,r20 + 800e83c: 003f9906 br 800e6a4 <__muldf3+0x144> + 800e840: 04000434 movhi r16,16 + 800e844: 000d883a mov r6,zero + 800e848: 843fffc4 addi r16,r16,-1 + 800e84c: 047fffc4 movi r17,-1 + 800e850: 00c1ffc4 movi r3,2047 + 800e854: 003f9c06 br 800e6c8 <__muldf3+0x168> + 800e858: 8080022c andhi r2,r16,8 + 800e85c: 10008926 beq r2,zero,800ea84 <__muldf3+0x524> + 800e860: 9080022c andhi r2,r18,8 + 800e864: 1000871e bne r2,zero,800ea84 <__muldf3+0x524> + 800e868: 00800434 movhi r2,16 + 800e86c: 94000234 orhi r16,r18,8 + 800e870: 10bfffc4 addi r2,r2,-1 + 800e874: 80a0703a and r16,r16,r2 + 800e878: a80d883a mov r6,r21 + 800e87c: 4023883a mov r17,r8 + 800e880: 003ff306 br 800e850 <__muldf3+0x2f0> + 800e884: 8818d43a srli r12,r17,16 + 800e888: 4028d43a srli r20,r8,16 + 800e88c: 42ffffcc andi r11,r8,65535 + 800e890: 8c7fffcc andi r17,r17,65535 + 800e894: 5c47383a mul r3,r11,r17 + 800e898: 62c9383a mul r4,r12,r11 + 800e89c: a445383a mul r2,r20,r17 + 800e8a0: 1810d43a srli r8,r3,16 + 800e8a4: 651d383a mul r14,r12,r20 + 800e8a8: 1105883a add r2,r2,r4 + 800e8ac: 4091883a add r8,r8,r2 + 800e8b0: 4100022e bgeu r8,r4,800e8bc <__muldf3+0x35c> + 800e8b4: 00800074 movhi r2,1 + 800e8b8: 709d883a add r14,r14,r2 + 800e8bc: 901ed43a srli r15,r18,16 + 800e8c0: 94bfffcc andi r18,r18,65535 + 800e8c4: 9449383a mul r4,r18,r17 + 800e8c8: 648f383a mul r7,r12,r18 + 800e8cc: 7c63383a mul r17,r15,r17 + 800e8d0: 201ad43a srli r13,r4,16 + 800e8d4: 4014943a slli r10,r8,16 + 800e8d8: 89e3883a add r17,r17,r7 + 800e8dc: 1a7fffcc andi r9,r3,65535 + 800e8e0: 6c5b883a add r13,r13,r17 + 800e8e4: 4006d43a srli r3,r8,16 + 800e8e8: 5253883a add r9,r10,r9 + 800e8ec: 63c5383a mul r2,r12,r15 + 800e8f0: 69c0022e bgeu r13,r7,800e8fc <__muldf3+0x39c> + 800e8f4: 01c00074 movhi r7,1 + 800e8f8: 11c5883a add r2,r2,r7 + 800e8fc: 802ad43a srli r21,r16,16 + 800e900: 823fffcc andi r8,r16,65535 + 800e904: 5a2d383a mul r22,r11,r8 + 800e908: a20f383a mul r7,r20,r8 + 800e90c: aad7383a mul r11,r21,r11 + 800e910: 6814943a slli r10,r13,16 + 800e914: b018d43a srli r12,r22,16 + 800e918: 6822d43a srli r17,r13,16 + 800e91c: 213fffcc andi r4,r4,65535 + 800e920: 3acf883a add r7,r7,r11 + 800e924: 5115883a add r10,r10,r4 + 800e928: 61cf883a add r7,r12,r7 + 800e92c: 889b883a add r13,r17,r2 + 800e930: 1a87883a add r3,r3,r10 + 800e934: a569383a mul r20,r20,r21 + 800e938: 3ac0022e bgeu r7,r11,800e944 <__muldf3+0x3e4> + 800e93c: 00800074 movhi r2,1 + 800e940: a0a9883a add r20,r20,r2 + 800e944: 9217383a mul r11,r18,r8 + 800e948: aca5383a mul r18,r21,r18 + 800e94c: 7a11383a mul r8,r15,r8 + 800e950: 5820d43a srli r16,r11,16 + 800e954: 3808d43a srli r4,r7,16 + 800e958: 380e943a slli r7,r7,16 + 800e95c: 4491883a add r8,r8,r18 + 800e960: b5bfffcc andi r22,r22,65535 + 800e964: 8211883a add r8,r16,r8 + 800e968: 2529883a add r20,r4,r20 + 800e96c: 3d8f883a add r7,r7,r22 + 800e970: 7d59383a mul r12,r15,r21 + 800e974: 4480022e bgeu r8,r18,800e980 <__muldf3+0x420> + 800e978: 00800074 movhi r2,1 + 800e97c: 6099883a add r12,r12,r2 + 800e980: 4004943a slli r2,r8,16 + 800e984: 5affffcc andi r11,r11,65535 + 800e988: 1b87883a add r3,r3,r14 + 800e98c: 12c5883a add r2,r2,r11 + 800e990: 1a95803a cmpltu r10,r3,r10 + 800e994: 1345883a add r2,r2,r13 + 800e998: 19c7883a add r3,r3,r7 + 800e99c: 129d883a add r14,r2,r10 + 800e9a0: 19cf803a cmpltu r7,r3,r7 + 800e9a4: 7509883a add r4,r14,r20 + 800e9a8: 4010d43a srli r8,r8,16 + 800e9ac: 21d7883a add r11,r4,r7 + 800e9b0: 1345803a cmpltu r2,r2,r13 + 800e9b4: 72a1803a cmpltu r16,r14,r10 + 800e9b8: 1420b03a or r16,r2,r16 + 800e9bc: 2509803a cmpltu r4,r4,r20 + 800e9c0: 59cf803a cmpltu r7,r11,r7 + 800e9c4: 21ceb03a or r7,r4,r7 + 800e9c8: 8221883a add r16,r16,r8 + 800e9cc: 81e1883a add r16,r16,r7 + 800e9d0: 1822927a slli r17,r3,9 + 800e9d4: 8321883a add r16,r16,r12 + 800e9d8: 8020927a slli r16,r16,9 + 800e9dc: 5808d5fa srli r4,r11,23 + 800e9e0: 1806d5fa srli r3,r3,23 + 800e9e4: 8a62b03a or r17,r17,r9 + 800e9e8: 5804927a slli r2,r11,9 + 800e9ec: 8120b03a or r16,r16,r4 + 800e9f0: 8822c03a cmpne r17,r17,zero + 800e9f4: 88e2b03a or r17,r17,r3 + 800e9f8: 80c0402c andhi r3,r16,256 + 800e9fc: 88a2b03a or r17,r17,r2 + 800ea00: 18005a26 beq r3,zero,800eb6c <__muldf3+0x60c> + 800ea04: 8804d07a srli r2,r17,1 + 800ea08: 800697fa slli r3,r16,31 + 800ea0c: 8c40004c andi r17,r17,1 + 800ea10: 8020d07a srli r16,r16,1 + 800ea14: 1462b03a or r17,r2,r17 + 800ea18: 88e2b03a or r17,r17,r3 + 800ea1c: 28c0ffc4 addi r3,r5,1023 + 800ea20: 00c0350e bge zero,r3,800eaf8 <__muldf3+0x598> + 800ea24: 888001cc andi r2,r17,7 + 800ea28: 10000726 beq r2,zero,800ea48 <__muldf3+0x4e8> + 800ea2c: 888003cc andi r2,r17,15 + 800ea30: 10800120 cmpeqi r2,r2,4 + 800ea34: 1000041e bne r2,zero,800ea48 <__muldf3+0x4e8> + 800ea38: 88800104 addi r2,r17,4 + 800ea3c: 1463803a cmpltu r17,r2,r17 + 800ea40: 8461883a add r16,r16,r17 + 800ea44: 1023883a mov r17,r2 + 800ea48: 8080402c andhi r2,r16,256 + 800ea4c: 10000426 beq r2,zero,800ea60 <__muldf3+0x500> + 800ea50: 00bfc034 movhi r2,65280 + 800ea54: 10bfffc4 addi r2,r2,-1 + 800ea58: 80a0703a and r16,r16,r2 + 800ea5c: 28c10004 addi r3,r5,1024 + 800ea60: 1881ffc8 cmpgei r2,r3,2047 + 800ea64: 103f5e1e bne r2,zero,800e7e0 <__muldf3+0x280> + 800ea68: 8004977a slli r2,r16,29 + 800ea6c: 8822d0fa srli r17,r17,3 + 800ea70: 8020927a slli r16,r16,9 + 800ea74: 18c1ffcc andi r3,r3,2047 + 800ea78: 1462b03a or r17,r2,r17 + 800ea7c: 8020d33a srli r16,r16,12 + 800ea80: 003f1106 br 800e6c8 <__muldf3+0x168> + 800ea84: 00800434 movhi r2,16 + 800ea88: 84000234 orhi r16,r16,8 + 800ea8c: 10bfffc4 addi r2,r2,-1 + 800ea90: 80a0703a and r16,r16,r2 + 800ea94: a00d883a mov r6,r20 + 800ea98: 003f6d06 br 800e850 <__muldf3+0x2f0> + 800ea9c: 3009883a mov r4,r6 + 800eaa0: d9800015 stw r6,0(sp) + 800eaa4: 800f7900 call 800f790 <__clzsi2> + 800eaa8: 11000544 addi r4,r2,21 + 800eaac: 21400748 cmpgei r5,r4,29 + 800eab0: 10c00804 addi r3,r2,32 + 800eab4: d9800017 ldw r6,0(sp) + 800eab8: 283f3e26 beq r5,zero,800e7b4 <__muldf3+0x254> + 800eabc: 10bffe04 addi r2,r2,-8 + 800eac0: 30a4983a sll r18,r6,r2 + 800eac4: 0011883a mov r8,zero + 800eac8: 003f4106 br 800e7d0 <__muldf3+0x270> + 800eacc: 800f7900 call 800f790 <__clzsi2> + 800ead0: 11400544 addi r5,r2,21 + 800ead4: 29000748 cmpgei r4,r5,29 + 800ead8: 10c00804 addi r3,r2,32 + 800eadc: d9800017 ldw r6,0(sp) + 800eae0: d9c00117 ldw r7,4(sp) + 800eae4: 203f1726 beq r4,zero,800e744 <__muldf3+0x1e4> + 800eae8: 10bffe04 addi r2,r2,-8 + 800eaec: 90a0983a sll r16,r18,r2 + 800eaf0: 0023883a mov r17,zero + 800eaf4: 003f1a06 br 800e760 <__muldf3+0x200> + 800eaf8: 00800044 movi r2,1 + 800eafc: 10c5c83a sub r2,r2,r3 + 800eb00: 11000e48 cmpgei r4,r2,57 + 800eb04: 203eed1e bne r4,zero,800e6bc <__muldf3+0x15c> + 800eb08: 11000808 cmpgei r4,r2,32 + 800eb0c: 2000191e bne r4,zero,800eb74 <__muldf3+0x614> + 800eb10: 29410784 addi r5,r5,1054 + 800eb14: 8146983a sll r3,r16,r5 + 800eb18: 8888d83a srl r4,r17,r2 + 800eb1c: 894a983a sll r5,r17,r5 + 800eb20: 80a0d83a srl r16,r16,r2 + 800eb24: 1904b03a or r2,r3,r4 + 800eb28: 2822c03a cmpne r17,r5,zero + 800eb2c: 1444b03a or r2,r2,r17 + 800eb30: 10c001cc andi r3,r2,7 + 800eb34: 18000726 beq r3,zero,800eb54 <__muldf3+0x5f4> + 800eb38: 10c003cc andi r3,r2,15 + 800eb3c: 18c00120 cmpeqi r3,r3,4 + 800eb40: 1800041e bne r3,zero,800eb54 <__muldf3+0x5f4> + 800eb44: 10c00104 addi r3,r2,4 + 800eb48: 1885803a cmpltu r2,r3,r2 + 800eb4c: 80a1883a add r16,r16,r2 + 800eb50: 1805883a mov r2,r3 + 800eb54: 80c0202c andhi r3,r16,128 + 800eb58: 18001b26 beq r3,zero,800ebc8 <__muldf3+0x668> + 800eb5c: 00c00044 movi r3,1 + 800eb60: 0021883a mov r16,zero + 800eb64: 0023883a mov r17,zero + 800eb68: 003ed706 br 800e6c8 <__muldf3+0x168> + 800eb6c: 980b883a mov r5,r19 + 800eb70: 003faa06 br 800ea1c <__muldf3+0x4bc> + 800eb74: 013ff844 movi r4,-31 + 800eb78: 20c7c83a sub r3,r4,r3 + 800eb7c: 10800820 cmpeqi r2,r2,32 + 800eb80: 80c6d83a srl r3,r16,r3 + 800eb84: 1000031e bne r2,zero,800eb94 <__muldf3+0x634> + 800eb88: 28810f84 addi r2,r5,1086 + 800eb8c: 8084983a sll r2,r16,r2 + 800eb90: 88a2b03a or r17,r17,r2 + 800eb94: 8822c03a cmpne r17,r17,zero + 800eb98: 88c4b03a or r2,r17,r3 + 800eb9c: 144001cc andi r17,r2,7 + 800eba0: 8800051e bne r17,zero,800ebb8 <__muldf3+0x658> + 800eba4: 0021883a mov r16,zero + 800eba8: 1004d0fa srli r2,r2,3 + 800ebac: 0007883a mov r3,zero + 800ebb0: 1462b03a or r17,r2,r17 + 800ebb4: 003ec406 br 800e6c8 <__muldf3+0x168> + 800ebb8: 10c003cc andi r3,r2,15 + 800ebbc: 18c00118 cmpnei r3,r3,4 + 800ebc0: 0021883a mov r16,zero + 800ebc4: 183fdf1e bne r3,zero,800eb44 <__muldf3+0x5e4> + 800ebc8: 8006927a slli r3,r16,9 + 800ebcc: 8022977a slli r17,r16,29 + 800ebd0: 1820d33a srli r16,r3,12 + 800ebd4: 003ff406 br 800eba8 <__muldf3+0x648> + 800ebd8: 00800434 movhi r2,16 + 800ebdc: 84000234 orhi r16,r16,8 + 800ebe0: 10bfffc4 addi r2,r2,-1 + 800ebe4: 80a0703a and r16,r16,r2 + 800ebe8: 003f1906 br 800e850 <__muldf3+0x2f0> + +0800ebec <__subdf3>: + 800ebec: 00800434 movhi r2,16 + 800ebf0: 3812d53a srli r9,r7,20 + 800ebf4: 10bfffc4 addi r2,r2,-1 + 800ebf8: defffb04 addi sp,sp,-20 + 800ebfc: 2890703a and r8,r5,r2 + 800ec00: 3884703a and r2,r7,r2 + 800ec04: 2806d7fa srli r3,r5,31 + 800ec08: dcc00315 stw r19,12(sp) + 800ec0c: dc400115 stw r17,4(sp) + 800ec10: 280ad53a srli r5,r5,20 + 800ec14: 401090fa slli r8,r8,3 + 800ec18: 2026d77a srli r19,r4,29 + 800ec1c: 100490fa slli r2,r2,3 + 800ec20: 3022d77a srli r17,r6,29 + 800ec24: 4a81ffcc andi r10,r9,2047 + 800ec28: dc800215 stw r18,8(sp) + 800ec2c: dc000015 stw r16,0(sp) + 800ec30: dfc00415 stw ra,16(sp) + 800ec34: 5241ffe0 cmpeqi r9,r10,2047 + 800ec38: 1825883a mov r18,r3 + 800ec3c: 2c01ffcc andi r16,r5,2047 + 800ec40: 18c03fcc andi r3,r3,255 + 800ec44: 9a18b03a or r12,r19,r8 + 800ec48: 201a90fa slli r13,r4,3 + 800ec4c: 380ed7fa srli r7,r7,31 + 800ec50: 8896b03a or r11,r17,r2 + 800ec54: 301c90fa slli r14,r6,3 + 800ec58: 4800711e bne r9,zero,800ee20 <__subdf3+0x234> + 800ec5c: 39c0005c xori r7,r7,1 + 800ec60: 8291c83a sub r8,r16,r10 + 800ec64: 19c05a26 beq r3,r7,800edd0 <__subdf3+0x1e4> + 800ec68: 0200720e bge zero,r8,800ee34 <__subdf3+0x248> + 800ec6c: 50008126 beq r10,zero,800ee74 <__subdf3+0x288> + 800ec70: 8081ffd8 cmpnei r2,r16,2047 + 800ec74: 10011626 beq r2,zero,800f0d0 <__subdf3+0x4e4> + 800ec78: 5ac02034 orhi r11,r11,128 + 800ec7c: 40800e48 cmpgei r2,r8,57 + 800ec80: 1000fe1e bne r2,zero,800f07c <__subdf3+0x490> + 800ec84: 40800808 cmpgei r2,r8,32 + 800ec88: 10015e1e bne r2,zero,800f204 <__subdf3+0x618> + 800ec8c: 00800804 movi r2,32 + 800ec90: 1205c83a sub r2,r2,r8 + 800ec94: 58a2983a sll r17,r11,r2 + 800ec98: 7206d83a srl r3,r14,r8 + 800ec9c: 709c983a sll r14,r14,r2 + 800eca0: 5a04d83a srl r2,r11,r8 + 800eca4: 88e2b03a or r17,r17,r3 + 800eca8: 701cc03a cmpne r14,r14,zero + 800ecac: 8ba2b03a or r17,r17,r14 + 800ecb0: 6099c83a sub r12,r12,r2 + 800ecb4: 6c63c83a sub r17,r13,r17 + 800ecb8: 6c49803a cmpltu r4,r13,r17 + 800ecbc: 6109c83a sub r4,r12,r4 + 800ecc0: 2080202c andhi r2,r4,128 + 800ecc4: 10009f26 beq r2,zero,800ef44 <__subdf3+0x358> + 800ecc8: 04c02034 movhi r19,128 + 800eccc: 9cffffc4 addi r19,r19,-1 + 800ecd0: 24e6703a and r19,r4,r19 + 800ecd4: 9800e026 beq r19,zero,800f058 <__subdf3+0x46c> + 800ecd8: 9809883a mov r4,r19 + 800ecdc: 800f7900 call 800f790 <__clzsi2> + 800ece0: 123ffe04 addi r8,r2,-8 + 800ece4: 01000804 movi r4,32 + 800ece8: 2209c83a sub r4,r4,r8 + 800ecec: 8906d83a srl r3,r17,r4 + 800ecf0: 9a08983a sll r4,r19,r8 + 800ecf4: 8a22983a sll r17,r17,r8 + 800ecf8: 1908b03a or r4,r3,r4 + 800ecfc: 4400cf16 blt r8,r16,800f03c <__subdf3+0x450> + 800ed00: 4411c83a sub r8,r8,r16 + 800ed04: 40800044 addi r2,r8,1 + 800ed08: 10c00808 cmpgei r3,r2,32 + 800ed0c: 1801251e bne r3,zero,800f1a4 <__subdf3+0x5b8> + 800ed10: 00c00804 movi r3,32 + 800ed14: 1887c83a sub r3,r3,r2 + 800ed18: 888ad83a srl r5,r17,r2 + 800ed1c: 88e2983a sll r17,r17,r3 + 800ed20: 20c6983a sll r3,r4,r3 + 800ed24: 2088d83a srl r4,r4,r2 + 800ed28: 8822c03a cmpne r17,r17,zero + 800ed2c: 1946b03a or r3,r3,r5 + 800ed30: 1c62b03a or r17,r3,r17 + 800ed34: 0021883a mov r16,zero + 800ed38: 888001cc andi r2,r17,7 + 800ed3c: 10000726 beq r2,zero,800ed5c <__subdf3+0x170> + 800ed40: 888003cc andi r2,r17,15 + 800ed44: 10800120 cmpeqi r2,r2,4 + 800ed48: 1000041e bne r2,zero,800ed5c <__subdf3+0x170> + 800ed4c: 88c00104 addi r3,r17,4 + 800ed50: 1c63803a cmpltu r17,r3,r17 + 800ed54: 2449883a add r4,r4,r17 + 800ed58: 1823883a mov r17,r3 + 800ed5c: 2080202c andhi r2,r4,128 + 800ed60: 10007a26 beq r2,zero,800ef4c <__subdf3+0x360> + 800ed64: 82000044 addi r8,r16,1 + 800ed68: 4081ffe0 cmpeqi r2,r8,2047 + 800ed6c: 4201ffcc andi r8,r8,2047 + 800ed70: 10008c1e bne r2,zero,800efa4 <__subdf3+0x3b8> + 800ed74: 00bfe034 movhi r2,65408 + 800ed78: 10bfffc4 addi r2,r2,-1 + 800ed7c: 2084703a and r2,r4,r2 + 800ed80: 1008927a slli r4,r2,9 + 800ed84: 8822d0fa srli r17,r17,3 + 800ed88: 100c977a slli r6,r2,29 + 800ed8c: 2008d33a srli r4,r4,12 + 800ed90: 3444b03a or r2,r6,r17 + 800ed94: 4010953a slli r8,r8,20 + 800ed98: 00c00434 movhi r3,16 + 800ed9c: 94803fcc andi r18,r18,255 + 800eda0: 902497fa slli r18,r18,31 + 800eda4: 18ffffc4 addi r3,r3,-1 + 800eda8: 20c6703a and r3,r4,r3 + 800edac: 1a06b03a or r3,r3,r8 + 800edb0: 1c86b03a or r3,r3,r18 + 800edb4: dfc00417 ldw ra,16(sp) + 800edb8: dcc00317 ldw r19,12(sp) + 800edbc: dc800217 ldw r18,8(sp) + 800edc0: dc400117 ldw r17,4(sp) + 800edc4: dc000017 ldw r16,0(sp) + 800edc8: dec00504 addi sp,sp,20 + 800edcc: f800283a ret + 800edd0: 0200320e bge zero,r8,800ee9c <__subdf3+0x2b0> + 800edd4: 50004c26 beq r10,zero,800ef08 <__subdf3+0x31c> + 800edd8: 8081ffd8 cmpnei r2,r16,2047 + 800eddc: 1000bc26 beq r2,zero,800f0d0 <__subdf3+0x4e4> + 800ede0: 5ac02034 orhi r11,r11,128 + 800ede4: 40800e48 cmpgei r2,r8,57 + 800ede8: 1000641e bne r2,zero,800ef7c <__subdf3+0x390> + 800edec: 40800808 cmpgei r2,r8,32 + 800edf0: 10011726 beq r2,zero,800f250 <__subdf3+0x664> + 800edf4: 447ff804 addi r17,r8,-32 + 800edf8: 40800820 cmpeqi r2,r8,32 + 800edfc: 5c46d83a srl r3,r11,r17 + 800ee00: 1000041e bne r2,zero,800ee14 <__subdf3+0x228> + 800ee04: 00801004 movi r2,64 + 800ee08: 1205c83a sub r2,r2,r8 + 800ee0c: 5884983a sll r2,r11,r2 + 800ee10: 709cb03a or r14,r14,r2 + 800ee14: 7022c03a cmpne r17,r14,zero + 800ee18: 88e2b03a or r17,r17,r3 + 800ee1c: 00005906 br 800ef84 <__subdf3+0x398> + 800ee20: 5b8ab03a or r5,r11,r14 + 800ee24: 823e0044 addi r8,r16,-2047 + 800ee28: 28001a1e bne r5,zero,800ee94 <__subdf3+0x2a8> + 800ee2c: 39c0005c xori r7,r7,1 + 800ee30: 19c01a26 beq r3,r7,800ee9c <__subdf3+0x2b0> + 800ee34: 4000291e bne r8,zero,800eedc <__subdf3+0x2f0> + 800ee38: 80800044 addi r2,r16,1 + 800ee3c: 1081ff8c andi r2,r2,2046 + 800ee40: 1000911e bne r2,zero,800f088 <__subdf3+0x49c> + 800ee44: 6346b03a or r3,r12,r13 + 800ee48: 5b84b03a or r2,r11,r14 + 800ee4c: 8001551e bne r16,zero,800f3a4 <__subdf3+0x7b8> + 800ee50: 18011b26 beq r3,zero,800f2c0 <__subdf3+0x6d4> + 800ee54: 1001641e bne r2,zero,800f3e8 <__subdf3+0x7fc> + 800ee58: 00880034 movhi r2,8192 + 800ee5c: 6022977a slli r17,r12,29 + 800ee60: 10bfffc4 addi r2,r2,-1 + 800ee64: 2088703a and r4,r4,r2 + 800ee68: 2444b03a or r2,r4,r17 + 800ee6c: 6026d0fa srli r19,r12,3 + 800ee70: 00003d06 br 800ef68 <__subdf3+0x37c> + 800ee74: 5b84b03a or r2,r11,r14 + 800ee78: 10008e26 beq r2,zero,800f0b4 <__subdf3+0x4c8> + 800ee7c: 40bfffc4 addi r2,r8,-1 + 800ee80: 10011f26 beq r2,zero,800f300 <__subdf3+0x714> + 800ee84: 4201ffd8 cmpnei r8,r8,2047 + 800ee88: 40012d26 beq r8,zero,800f340 <__subdf3+0x754> + 800ee8c: 1011883a mov r8,r2 + 800ee90: 003f7a06 br 800ec7c <__subdf3+0x90> + 800ee94: 39c03fcc andi r7,r7,255 + 800ee98: 19ffe61e bne r3,r7,800ee34 <__subdf3+0x248> + 800ee9c: 4000931e bne r8,zero,800f0ec <__subdf3+0x500> + 800eea0: 80c00044 addi r3,r16,1 + 800eea4: 1881ff8c andi r2,r3,2046 + 800eea8: 10012c1e bne r2,zero,800f35c <__subdf3+0x770> + 800eeac: 6344b03a or r2,r12,r13 + 800eeb0: 8000f91e bne r16,zero,800f298 <__subdf3+0x6ac> + 800eeb4: 10017326 beq r2,zero,800f484 <__subdf3+0x898> + 800eeb8: 5b84b03a or r2,r11,r14 + 800eebc: 1001781e bne r2,zero,800f4a0 <__subdf3+0x8b4> + 800eec0: 6004977a slli r2,r12,29 + 800eec4: 00c80034 movhi r3,8192 + 800eec8: 18ffffc4 addi r3,r3,-1 + 800eecc: 20c6703a and r3,r4,r3 + 800eed0: 10c4b03a or r2,r2,r3 + 800eed4: 6026d0fa srli r19,r12,3 + 800eed8: 00002306 br 800ef68 <__subdf3+0x37c> + 800eedc: 5411c83a sub r8,r10,r16 + 800eee0: 3825883a mov r18,r7 + 800eee4: 8000991e bne r16,zero,800f14c <__subdf3+0x560> + 800eee8: 6344b03a or r2,r12,r13 + 800eeec: 1000e326 beq r2,zero,800f27c <__subdf3+0x690> + 800eef0: 40bfffc4 addi r2,r8,-1 + 800eef4: 10015d26 beq r2,zero,800f46c <__subdf3+0x880> + 800eef8: 4201ffd8 cmpnei r8,r8,2047 + 800eefc: 4000f926 beq r8,zero,800f2e4 <__subdf3+0x6f8> + 800ef00: 1011883a mov r8,r2 + 800ef04: 00009406 br 800f158 <__subdf3+0x56c> + 800ef08: 5b84b03a or r2,r11,r14 + 800ef0c: 10010226 beq r2,zero,800f318 <__subdf3+0x72c> + 800ef10: 40bfffc4 addi r2,r8,-1 + 800ef14: 10000426 beq r2,zero,800ef28 <__subdf3+0x33c> + 800ef18: 4201ffd8 cmpnei r8,r8,2047 + 800ef1c: 40014126 beq r8,zero,800f424 <__subdf3+0x838> + 800ef20: 1011883a mov r8,r2 + 800ef24: 003faf06 br 800ede4 <__subdf3+0x1f8> + 800ef28: 6ba3883a add r17,r13,r14 + 800ef2c: 62c9883a add r4,r12,r11 + 800ef30: 8b5b803a cmpltu r13,r17,r13 + 800ef34: 2349883a add r4,r4,r13 + 800ef38: 2080202c andhi r2,r4,128 + 800ef3c: 1000a61e bne r2,zero,800f1d8 <__subdf3+0x5ec> + 800ef40: 04000044 movi r16,1 + 800ef44: 888001cc andi r2,r17,7 + 800ef48: 103f7d1e bne r2,zero,800ed40 <__subdf3+0x154> + 800ef4c: 8822d0fa srli r17,r17,3 + 800ef50: 2004977a slli r2,r4,29 + 800ef54: 2026d0fa srli r19,r4,3 + 800ef58: 8011883a mov r8,r16 + 800ef5c: 8884b03a or r2,r17,r2 + 800ef60: 40c1ffe0 cmpeqi r3,r8,2047 + 800ef64: 18002d1e bne r3,zero,800f01c <__subdf3+0x430> + 800ef68: 01000434 movhi r4,16 + 800ef6c: 213fffc4 addi r4,r4,-1 + 800ef70: 9908703a and r4,r19,r4 + 800ef74: 4201ffcc andi r8,r8,2047 + 800ef78: 003f8606 br 800ed94 <__subdf3+0x1a8> + 800ef7c: 5ba2b03a or r17,r11,r14 + 800ef80: 8822c03a cmpne r17,r17,zero + 800ef84: 8b63883a add r17,r17,r13 + 800ef88: 8b49803a cmpltu r4,r17,r13 + 800ef8c: 2309883a add r4,r4,r12 + 800ef90: 2080202c andhi r2,r4,128 + 800ef94: 103feb26 beq r2,zero,800ef44 <__subdf3+0x358> + 800ef98: 84000044 addi r16,r16,1 + 800ef9c: 8081ffe0 cmpeqi r2,r16,2047 + 800efa0: 10008e26 beq r2,zero,800f1dc <__subdf3+0x5f0> + 800efa4: 0201ffc4 movi r8,2047 + 800efa8: 0009883a mov r4,zero + 800efac: 0005883a mov r2,zero + 800efb0: 003f7806 br 800ed94 <__subdf3+0x1a8> + 800efb4: 6010977a slli r8,r12,29 + 800efb8: 6026d0fa srli r19,r12,3 + 800efbc: 1000bb26 beq r2,zero,800f2ac <__subdf3+0x6c0> + 800efc0: 01480034 movhi r5,8192 + 800efc4: 297fffc4 addi r5,r5,-1 + 800efc8: 2146703a and r3,r4,r5 + 800efcc: 9880022c andhi r2,r19,8 + 800efd0: 1a06b03a or r3,r3,r8 + 800efd4: 10000826 beq r2,zero,800eff8 <__subdf3+0x40c> + 800efd8: 5808d0fa srli r4,r11,3 + 800efdc: 2080022c andhi r2,r4,8 + 800efe0: 1000051e bne r2,zero,800eff8 <__subdf3+0x40c> + 800efe4: 5804977a slli r2,r11,29 + 800efe8: 3146703a and r3,r6,r5 + 800efec: 3825883a mov r18,r7 + 800eff0: 1886b03a or r3,r3,r2 + 800eff4: 2027883a mov r19,r4 + 800eff8: 1804d77a srli r2,r3,29 + 800effc: 980890fa slli r4,r19,3 + 800f000: 01480034 movhi r5,8192 + 800f004: 297fffc4 addi r5,r5,-1 + 800f008: 1108b03a or r4,r2,r4 + 800f00c: 2004977a slli r2,r4,29 + 800f010: 2026d0fa srli r19,r4,3 + 800f014: 1946703a and r3,r3,r5 + 800f018: 10c4b03a or r2,r2,r3 + 800f01c: 14c6b03a or r3,r2,r19 + 800f020: 18014926 beq r3,zero,800f548 <__subdf3+0x95c> + 800f024: 00c00434 movhi r3,16 + 800f028: 99000234 orhi r4,r19,8 + 800f02c: 18ffffc4 addi r3,r3,-1 + 800f030: 20c8703a and r4,r4,r3 + 800f034: 0201ffc4 movi r8,2047 + 800f038: 003f5606 br 800ed94 <__subdf3+0x1a8> + 800f03c: 00bfe034 movhi r2,65408 + 800f040: 10bfffc4 addi r2,r2,-1 + 800f044: 2088703a and r4,r4,r2 + 800f048: 888001cc andi r2,r17,7 + 800f04c: 8221c83a sub r16,r16,r8 + 800f050: 103f3b1e bne r2,zero,800ed40 <__subdf3+0x154> + 800f054: 003fbd06 br 800ef4c <__subdf3+0x360> + 800f058: 8809883a mov r4,r17 + 800f05c: 800f7900 call 800f790 <__clzsi2> + 800f060: 12000604 addi r8,r2,24 + 800f064: 40c00808 cmpgei r3,r8,32 + 800f068: 183f1e26 beq r3,zero,800ece4 <__subdf3+0xf8> + 800f06c: 113ffe04 addi r4,r2,-8 + 800f070: 8908983a sll r4,r17,r4 + 800f074: 0023883a mov r17,zero + 800f078: 003f2006 br 800ecfc <__subdf3+0x110> + 800f07c: 5ba2b03a or r17,r11,r14 + 800f080: 8822c03a cmpne r17,r17,zero + 800f084: 003f0b06 br 800ecb4 <__subdf3+0xc8> + 800f088: 6ba3c83a sub r17,r13,r14 + 800f08c: 62e7c83a sub r19,r12,r11 + 800f090: 6c49803a cmpltu r4,r13,r17 + 800f094: 9927c83a sub r19,r19,r4 + 800f098: 9880202c andhi r2,r19,128 + 800f09c: 1000bb1e bne r2,zero,800f38c <__subdf3+0x7a0> + 800f0a0: 8cc4b03a or r2,r17,r19 + 800f0a4: 103f0b1e bne r2,zero,800ecd4 <__subdf3+0xe8> + 800f0a8: 0027883a mov r19,zero + 800f0ac: 0025883a mov r18,zero + 800f0b0: 003fad06 br 800ef68 <__subdf3+0x37c> + 800f0b4: 00880034 movhi r2,8192 + 800f0b8: 6022977a slli r17,r12,29 + 800f0bc: 10bfffc4 addi r2,r2,-1 + 800f0c0: 2088703a and r4,r4,r2 + 800f0c4: 2444b03a or r2,r4,r17 + 800f0c8: 6026d0fa srli r19,r12,3 + 800f0cc: 003fa406 br 800ef60 <__subdf3+0x374> + 800f0d0: 00880034 movhi r2,8192 + 800f0d4: 6022977a slli r17,r12,29 + 800f0d8: 10bfffc4 addi r2,r2,-1 + 800f0dc: 2088703a and r4,r4,r2 + 800f0e0: 2444b03a or r2,r4,r17 + 800f0e4: 6026d0fa srli r19,r12,3 + 800f0e8: 003fcc06 br 800f01c <__subdf3+0x430> + 800f0ec: 5411c83a sub r8,r10,r16 + 800f0f0: 80004f26 beq r16,zero,800f230 <__subdf3+0x644> + 800f0f4: 5081ffd8 cmpnei r2,r10,2047 + 800f0f8: 1000b426 beq r2,zero,800f3cc <__subdf3+0x7e0> + 800f0fc: 63002034 orhi r12,r12,128 + 800f100: 40800e48 cmpgei r2,r8,57 + 800f104: 1000c41e bne r2,zero,800f418 <__subdf3+0x82c> + 800f108: 40800808 cmpgei r2,r8,32 + 800f10c: 1000f91e bne r2,zero,800f4f4 <__subdf3+0x908> + 800f110: 00800804 movi r2,32 + 800f114: 1205c83a sub r2,r2,r8 + 800f118: 60a2983a sll r17,r12,r2 + 800f11c: 6a06d83a srl r3,r13,r8 + 800f120: 6884983a sll r2,r13,r2 + 800f124: 6210d83a srl r8,r12,r8 + 800f128: 88e2b03a or r17,r17,r3 + 800f12c: 1004c03a cmpne r2,r2,zero + 800f130: 88a2b03a or r17,r17,r2 + 800f134: 5a17883a add r11,r11,r8 + 800f138: 8ba3883a add r17,r17,r14 + 800f13c: 8b85803a cmpltu r2,r17,r14 + 800f140: 12c9883a add r4,r2,r11 + 800f144: 5021883a mov r16,r10 + 800f148: 003f9106 br 800ef90 <__subdf3+0x3a4> + 800f14c: 5081ffd8 cmpnei r2,r10,2047 + 800f150: 10006426 beq r2,zero,800f2e4 <__subdf3+0x6f8> + 800f154: 63002034 orhi r12,r12,128 + 800f158: 40800e48 cmpgei r2,r8,57 + 800f15c: 1000751e bne r2,zero,800f334 <__subdf3+0x748> + 800f160: 40800808 cmpgei r2,r8,32 + 800f164: 1000b61e bne r2,zero,800f440 <__subdf3+0x854> + 800f168: 00800804 movi r2,32 + 800f16c: 1205c83a sub r2,r2,r8 + 800f170: 60a2983a sll r17,r12,r2 + 800f174: 6a06d83a srl r3,r13,r8 + 800f178: 6884983a sll r2,r13,r2 + 800f17c: 6210d83a srl r8,r12,r8 + 800f180: 88e2b03a or r17,r17,r3 + 800f184: 1004c03a cmpne r2,r2,zero + 800f188: 88a2b03a or r17,r17,r2 + 800f18c: 5a17c83a sub r11,r11,r8 + 800f190: 7463c83a sub r17,r14,r17 + 800f194: 7445803a cmpltu r2,r14,r17 + 800f198: 5889c83a sub r4,r11,r2 + 800f19c: 5021883a mov r16,r10 + 800f1a0: 003ec706 br 800ecc0 <__subdf3+0xd4> + 800f1a4: 423ff844 addi r8,r8,-31 + 800f1a8: 10c00820 cmpeqi r3,r2,32 + 800f1ac: 2210d83a srl r8,r4,r8 + 800f1b0: 1800041e bne r3,zero,800f1c4 <__subdf3+0x5d8> + 800f1b4: 00c01004 movi r3,64 + 800f1b8: 1885c83a sub r2,r3,r2 + 800f1bc: 2088983a sll r4,r4,r2 + 800f1c0: 8922b03a or r17,r17,r4 + 800f1c4: 8822c03a cmpne r17,r17,zero + 800f1c8: 8a22b03a or r17,r17,r8 + 800f1cc: 0009883a mov r4,zero + 800f1d0: 0021883a mov r16,zero + 800f1d4: 003f5b06 br 800ef44 <__subdf3+0x358> + 800f1d8: 04000084 movi r16,2 + 800f1dc: 00bfe034 movhi r2,65408 + 800f1e0: 10bfffc4 addi r2,r2,-1 + 800f1e4: 2084703a and r2,r4,r2 + 800f1e8: 8806d07a srli r3,r17,1 + 800f1ec: 100a97fa slli r5,r2,31 + 800f1f0: 8c40004c andi r17,r17,1 + 800f1f4: 1c62b03a or r17,r3,r17 + 800f1f8: 1008d07a srli r4,r2,1 + 800f1fc: 2c62b03a or r17,r5,r17 + 800f200: 003ecd06 br 800ed38 <__subdf3+0x14c> + 800f204: 447ff804 addi r17,r8,-32 + 800f208: 40800820 cmpeqi r2,r8,32 + 800f20c: 5c46d83a srl r3,r11,r17 + 800f210: 1000041e bne r2,zero,800f224 <__subdf3+0x638> + 800f214: 00801004 movi r2,64 + 800f218: 1205c83a sub r2,r2,r8 + 800f21c: 5884983a sll r2,r11,r2 + 800f220: 709cb03a or r14,r14,r2 + 800f224: 7022c03a cmpne r17,r14,zero + 800f228: 88e2b03a or r17,r17,r3 + 800f22c: 003ea106 br 800ecb4 <__subdf3+0xc8> + 800f230: 6344b03a or r2,r12,r13 + 800f234: 1000a526 beq r2,zero,800f4cc <__subdf3+0x8e0> + 800f238: 40bfffc4 addi r2,r8,-1 + 800f23c: 1000bd26 beq r2,zero,800f534 <__subdf3+0x948> + 800f240: 4201ffd8 cmpnei r8,r8,2047 + 800f244: 40006126 beq r8,zero,800f3cc <__subdf3+0x7e0> + 800f248: 1011883a mov r8,r2 + 800f24c: 003fac06 br 800f100 <__subdf3+0x514> + 800f250: 00800804 movi r2,32 + 800f254: 1205c83a sub r2,r2,r8 + 800f258: 58a2983a sll r17,r11,r2 + 800f25c: 7206d83a srl r3,r14,r8 + 800f260: 709c983a sll r14,r14,r2 + 800f264: 5a04d83a srl r2,r11,r8 + 800f268: 88e2b03a or r17,r17,r3 + 800f26c: 701cc03a cmpne r14,r14,zero + 800f270: 8ba2b03a or r17,r17,r14 + 800f274: 6099883a add r12,r12,r2 + 800f278: 003f4206 br 800ef84 <__subdf3+0x398> + 800f27c: 5808977a slli r4,r11,29 + 800f280: 00c80034 movhi r3,8192 + 800f284: 18ffffc4 addi r3,r3,-1 + 800f288: 30cc703a and r6,r6,r3 + 800f28c: 2184b03a or r2,r4,r6 + 800f290: 5826d0fa srli r19,r11,3 + 800f294: 003f3206 br 800ef60 <__subdf3+0x374> + 800f298: 10004c26 beq r2,zero,800f3cc <__subdf3+0x7e0> + 800f29c: 5b9cb03a or r14,r11,r14 + 800f2a0: 6010977a slli r8,r12,29 + 800f2a4: 6026d0fa srli r19,r12,3 + 800f2a8: 703f451e bne r14,zero,800efc0 <__subdf3+0x3d4> + 800f2ac: 00880034 movhi r2,8192 + 800f2b0: 10bfffc4 addi r2,r2,-1 + 800f2b4: 2084703a and r2,r4,r2 + 800f2b8: 1204b03a or r2,r2,r8 + 800f2bc: 003f5706 br 800f01c <__subdf3+0x430> + 800f2c0: 103f7926 beq r2,zero,800f0a8 <__subdf3+0x4bc> + 800f2c4: 5804977a slli r2,r11,29 + 800f2c8: 00c80034 movhi r3,8192 + 800f2cc: 18ffffc4 addi r3,r3,-1 + 800f2d0: 30c6703a and r3,r6,r3 + 800f2d4: 10c4b03a or r2,r2,r3 + 800f2d8: 5826d0fa srli r19,r11,3 + 800f2dc: 3825883a mov r18,r7 + 800f2e0: 003f2106 br 800ef68 <__subdf3+0x37c> + 800f2e4: 5804977a slli r2,r11,29 + 800f2e8: 00c80034 movhi r3,8192 + 800f2ec: 18ffffc4 addi r3,r3,-1 + 800f2f0: 30c6703a and r3,r6,r3 + 800f2f4: 10c4b03a or r2,r2,r3 + 800f2f8: 5826d0fa srli r19,r11,3 + 800f2fc: 003f4706 br 800f01c <__subdf3+0x430> + 800f300: 6ba3c83a sub r17,r13,r14 + 800f304: 62c9c83a sub r4,r12,r11 + 800f308: 6c5b803a cmpltu r13,r13,r17 + 800f30c: 2349c83a sub r4,r4,r13 + 800f310: 04000044 movi r16,1 + 800f314: 003e6a06 br 800ecc0 <__subdf3+0xd4> + 800f318: 6004977a slli r2,r12,29 + 800f31c: 00c80034 movhi r3,8192 + 800f320: 18ffffc4 addi r3,r3,-1 + 800f324: 20c8703a and r4,r4,r3 + 800f328: 1104b03a or r2,r2,r4 + 800f32c: 6026d0fa srli r19,r12,3 + 800f330: 003f0b06 br 800ef60 <__subdf3+0x374> + 800f334: 6366b03a or r19,r12,r13 + 800f338: 9822c03a cmpne r17,r19,zero + 800f33c: 003f9406 br 800f190 <__subdf3+0x5a4> + 800f340: 6004977a slli r2,r12,29 + 800f344: 00c80034 movhi r3,8192 + 800f348: 18ffffc4 addi r3,r3,-1 + 800f34c: 20c8703a and r4,r4,r3 + 800f350: 1104b03a or r2,r2,r4 + 800f354: 6026d0fa srli r19,r12,3 + 800f358: 003f3006 br 800f01c <__subdf3+0x430> + 800f35c: 1881ffe0 cmpeqi r2,r3,2047 + 800f360: 103f101e bne r2,zero,800efa4 <__subdf3+0x3b8> + 800f364: 6b9d883a add r14,r13,r14 + 800f368: 62c9883a add r4,r12,r11 + 800f36c: 7345803a cmpltu r2,r14,r13 + 800f370: 2085883a add r2,r4,r2 + 800f374: 102297fa slli r17,r2,31 + 800f378: 701cd07a srli r14,r14,1 + 800f37c: 1008d07a srli r4,r2,1 + 800f380: 1821883a mov r16,r3 + 800f384: 8ba2b03a or r17,r17,r14 + 800f388: 003eee06 br 800ef44 <__subdf3+0x358> + 800f38c: 7363c83a sub r17,r14,r13 + 800f390: 5b09c83a sub r4,r11,r12 + 800f394: 7467803a cmpltu r19,r14,r17 + 800f398: 24e7c83a sub r19,r4,r19 + 800f39c: 3825883a mov r18,r7 + 800f3a0: 003e4c06 br 800ecd4 <__subdf3+0xe8> + 800f3a4: 183f031e bne r3,zero,800efb4 <__subdf3+0x3c8> + 800f3a8: 10005d26 beq r2,zero,800f520 <__subdf3+0x934> + 800f3ac: 00880034 movhi r2,8192 + 800f3b0: 5806977a slli r3,r11,29 + 800f3b4: 10bfffc4 addi r2,r2,-1 + 800f3b8: 3084703a and r2,r6,r2 + 800f3bc: 10c4b03a or r2,r2,r3 + 800f3c0: 5826d0fa srli r19,r11,3 + 800f3c4: 3825883a mov r18,r7 + 800f3c8: 003f1406 br 800f01c <__subdf3+0x430> + 800f3cc: 00880034 movhi r2,8192 + 800f3d0: 5806977a slli r3,r11,29 + 800f3d4: 10bfffc4 addi r2,r2,-1 + 800f3d8: 3084703a and r2,r6,r2 + 800f3dc: 10c4b03a or r2,r2,r3 + 800f3e0: 5826d0fa srli r19,r11,3 + 800f3e4: 003f0d06 br 800f01c <__subdf3+0x430> + 800f3e8: 6ba3c83a sub r17,r13,r14 + 800f3ec: 62c5c83a sub r2,r12,r11 + 800f3f0: 6c49803a cmpltu r4,r13,r17 + 800f3f4: 1109c83a sub r4,r2,r4 + 800f3f8: 2080202c andhi r2,r4,128 + 800f3fc: 10003a26 beq r2,zero,800f4e8 <__subdf3+0x8fc> + 800f400: 7363c83a sub r17,r14,r13 + 800f404: 5b09c83a sub r4,r11,r12 + 800f408: 745d803a cmpltu r14,r14,r17 + 800f40c: 2389c83a sub r4,r4,r14 + 800f410: 3825883a mov r18,r7 + 800f414: 003e4806 br 800ed38 <__subdf3+0x14c> + 800f418: 6362b03a or r17,r12,r13 + 800f41c: 8822c03a cmpne r17,r17,zero + 800f420: 003f4506 br 800f138 <__subdf3+0x54c> + 800f424: 6004977a slli r2,r12,29 + 800f428: 00c80034 movhi r3,8192 + 800f42c: 18ffffc4 addi r3,r3,-1 + 800f430: 20c6703a and r3,r4,r3 + 800f434: 10c4b03a or r2,r2,r3 + 800f438: 6026d0fa srli r19,r12,3 + 800f43c: 003ef706 br 800f01c <__subdf3+0x430> + 800f440: 40bff804 addi r2,r8,-32 + 800f444: 40c00820 cmpeqi r3,r8,32 + 800f448: 6084d83a srl r2,r12,r2 + 800f44c: 1800041e bne r3,zero,800f460 <__subdf3+0x874> + 800f450: 04c01004 movi r19,64 + 800f454: 9a11c83a sub r8,r19,r8 + 800f458: 6226983a sll r19,r12,r8 + 800f45c: 6cdab03a or r13,r13,r19 + 800f460: 6822c03a cmpne r17,r13,zero + 800f464: 88a2b03a or r17,r17,r2 + 800f468: 003f4906 br 800f190 <__subdf3+0x5a4> + 800f46c: 7363c83a sub r17,r14,r13 + 800f470: 5b09c83a sub r4,r11,r12 + 800f474: 745d803a cmpltu r14,r14,r17 + 800f478: 2389c83a sub r4,r4,r14 + 800f47c: 04000044 movi r16,1 + 800f480: 003e0f06 br 800ecc0 <__subdf3+0xd4> + 800f484: 00880034 movhi r2,8192 + 800f488: 5806977a slli r3,r11,29 + 800f48c: 10bfffc4 addi r2,r2,-1 + 800f490: 3084703a and r2,r6,r2 + 800f494: 10c4b03a or r2,r2,r3 + 800f498: 5826d0fa srli r19,r11,3 + 800f49c: 003eb206 br 800ef68 <__subdf3+0x37c> + 800f4a0: 6ba3883a add r17,r13,r14 + 800f4a4: 62c9883a add r4,r12,r11 + 800f4a8: 8b5b803a cmpltu r13,r17,r13 + 800f4ac: 2349883a add r4,r4,r13 + 800f4b0: 2080202c andhi r2,r4,128 + 800f4b4: 103ea326 beq r2,zero,800ef44 <__subdf3+0x358> + 800f4b8: 00bfe034 movhi r2,65408 + 800f4bc: 10bfffc4 addi r2,r2,-1 + 800f4c0: 2088703a and r4,r4,r2 + 800f4c4: 04000044 movi r16,1 + 800f4c8: 003e9e06 br 800ef44 <__subdf3+0x358> + 800f4cc: 00880034 movhi r2,8192 + 800f4d0: 5806977a slli r3,r11,29 + 800f4d4: 10bfffc4 addi r2,r2,-1 + 800f4d8: 3084703a and r2,r6,r2 + 800f4dc: 10c4b03a or r2,r2,r3 + 800f4e0: 5826d0fa srli r19,r11,3 + 800f4e4: 003e9e06 br 800ef60 <__subdf3+0x374> + 800f4e8: 8904b03a or r2,r17,r4 + 800f4ec: 103eee26 beq r2,zero,800f0a8 <__subdf3+0x4bc> + 800f4f0: 003e9406 br 800ef44 <__subdf3+0x358> + 800f4f4: 40bff804 addi r2,r8,-32 + 800f4f8: 40c00820 cmpeqi r3,r8,32 + 800f4fc: 6084d83a srl r2,r12,r2 + 800f500: 1800041e bne r3,zero,800f514 <__subdf3+0x928> + 800f504: 04c01004 movi r19,64 + 800f508: 9a11c83a sub r8,r19,r8 + 800f50c: 6226983a sll r19,r12,r8 + 800f510: 6cdab03a or r13,r13,r19 + 800f514: 6822c03a cmpne r17,r13,zero + 800f518: 88a2b03a or r17,r17,r2 + 800f51c: 003f0606 br 800f138 <__subdf3+0x54c> + 800f520: 04c00434 movhi r19,16 + 800f524: 9cffffc4 addi r19,r19,-1 + 800f528: 0025883a mov r18,zero + 800f52c: 00bfffc4 movi r2,-1 + 800f530: 003ebc06 br 800f024 <__subdf3+0x438> + 800f534: 6ba3883a add r17,r13,r14 + 800f538: 62c9883a add r4,r12,r11 + 800f53c: 8b9d803a cmpltu r14,r17,r14 + 800f540: 2389883a add r4,r4,r14 + 800f544: 003e7c06 br 800ef38 <__subdf3+0x34c> + 800f548: 0005883a mov r2,zero + 800f54c: 0201ffc4 movi r8,2047 + 800f550: 0009883a mov r4,zero + 800f554: 003e0f06 br 800ed94 <__subdf3+0x1a8> + +0800f558 <__unorddf2>: + 800f558: 2806d53a srli r3,r5,20 + 800f55c: 3810d53a srli r8,r7,20 + 800f560: 00800434 movhi r2,16 + 800f564: 18c1ffcc andi r3,r3,2047 + 800f568: 10bfffc4 addi r2,r2,-1 + 800f56c: 18c1ffd8 cmpnei r3,r3,2047 + 800f570: 288a703a and r5,r5,r2 + 800f574: 388e703a and r7,r7,r2 + 800f578: 4201ffcc andi r8,r8,2047 + 800f57c: 18000426 beq r3,zero,800f590 <__unorddf2+0x38> + 800f580: 4201ffd8 cmpnei r8,r8,2047 + 800f584: 40000626 beq r8,zero,800f5a0 <__unorddf2+0x48> + 800f588: 0005883a mov r2,zero + 800f58c: f800283a ret + 800f590: 214ab03a or r5,r4,r5 + 800f594: 283ffa26 beq r5,zero,800f580 <__unorddf2+0x28> + 800f598: 00800044 movi r2,1 + 800f59c: f800283a ret + 800f5a0: 398eb03a or r7,r7,r6 + 800f5a4: 3804c03a cmpne r2,r7,zero + 800f5a8: f800283a ret + +0800f5ac <__fixdfsi>: + 800f5ac: 280cd53a srli r6,r5,20 + 800f5b0: 00c00434 movhi r3,16 + 800f5b4: 18ffffc4 addi r3,r3,-1 + 800f5b8: 3181ffcc andi r6,r6,2047 + 800f5bc: 31c0ffd0 cmplti r7,r6,1023 + 800f5c0: 28c6703a and r3,r5,r3 + 800f5c4: 280ad7fa srli r5,r5,31 + 800f5c8: 3800061e bne r7,zero,800f5e4 <__fixdfsi+0x38> + 800f5cc: 30810790 cmplti r2,r6,1054 + 800f5d0: 1000061e bne r2,zero,800f5ec <__fixdfsi+0x40> + 800f5d4: 00a00034 movhi r2,32768 + 800f5d8: 10bfffc4 addi r2,r2,-1 + 800f5dc: 2885883a add r2,r5,r2 + 800f5e0: f800283a ret + 800f5e4: 0005883a mov r2,zero + 800f5e8: f800283a ret + 800f5ec: 00810cc4 movi r2,1075 + 800f5f0: 118fc83a sub r7,r2,r6 + 800f5f4: 38800808 cmpgei r2,r7,32 + 800f5f8: 18c00434 orhi r3,r3,16 + 800f5fc: 1000071e bne r2,zero,800f61c <__fixdfsi+0x70> + 800f600: 30befb44 addi r2,r6,-1043 + 800f604: 1886983a sll r3,r3,r2 + 800f608: 21c4d83a srl r2,r4,r7 + 800f60c: 1884b03a or r2,r3,r2 + 800f610: 283ff526 beq r5,zero,800f5e8 <__fixdfsi+0x3c> + 800f614: 0085c83a sub r2,zero,r2 + 800f618: f800283a ret + 800f61c: 008104c4 movi r2,1043 + 800f620: 1185c83a sub r2,r2,r6 + 800f624: 1884d83a srl r2,r3,r2 + 800f628: 003ff906 br 800f610 <__fixdfsi+0x64> + +0800f62c <__floatsidf>: + 800f62c: defffd04 addi sp,sp,-12 + 800f630: dfc00215 stw ra,8(sp) + 800f634: dc400115 stw r17,4(sp) + 800f638: dc000015 stw r16,0(sp) + 800f63c: 20001326 beq r4,zero,800f68c <__floatsidf+0x60> + 800f640: 2021883a mov r16,r4 + 800f644: 2022d7fa srli r17,r4,31 + 800f648: 20002116 blt r4,zero,800f6d0 <__floatsidf+0xa4> + 800f64c: 8009883a mov r4,r16 + 800f650: 800f7900 call 800f790 <__clzsi2> + 800f654: 01010784 movi r4,1054 + 800f658: 2089c83a sub r4,r4,r2 + 800f65c: 10c002c8 cmpgei r3,r2,11 + 800f660: 2101ffcc andi r4,r4,2047 + 800f664: 18001c1e bne r3,zero,800f6d8 <__floatsidf+0xac> + 800f668: 018002c4 movi r6,11 + 800f66c: 308dc83a sub r6,r6,r2 + 800f670: 818ad83a srl r5,r16,r6 + 800f674: 00c00434 movhi r3,16 + 800f678: 10800544 addi r2,r2,21 + 800f67c: 18ffffc4 addi r3,r3,-1 + 800f680: 8084983a sll r2,r16,r2 + 800f684: 28ca703a and r5,r5,r3 + 800f688: 00000406 br 800f69c <__floatsidf+0x70> + 800f68c: 0023883a mov r17,zero + 800f690: 0009883a mov r4,zero + 800f694: 000b883a mov r5,zero + 800f698: 0005883a mov r2,zero + 800f69c: 2008953a slli r4,r4,20 + 800f6a0: 8c403fcc andi r17,r17,255 + 800f6a4: 01800434 movhi r6,16 + 800f6a8: 31bfffc4 addi r6,r6,-1 + 800f6ac: 880697fa slli r3,r17,31 + 800f6b0: 298a703a and r5,r5,r6 + 800f6b4: 290ab03a or r5,r5,r4 + 800f6b8: 28c6b03a or r3,r5,r3 + 800f6bc: dfc00217 ldw ra,8(sp) + 800f6c0: dc400117 ldw r17,4(sp) + 800f6c4: dc000017 ldw r16,0(sp) + 800f6c8: dec00304 addi sp,sp,12 + 800f6cc: f800283a ret + 800f6d0: 0121c83a sub r16,zero,r4 + 800f6d4: 003fdd06 br 800f64c <__floatsidf+0x20> + 800f6d8: 10bffd44 addi r2,r2,-11 + 800f6dc: 808a983a sll r5,r16,r2 + 800f6e0: 00800434 movhi r2,16 + 800f6e4: 10bfffc4 addi r2,r2,-1 + 800f6e8: 288a703a and r5,r5,r2 + 800f6ec: 0005883a mov r2,zero + 800f6f0: 003fea06 br 800f69c <__floatsidf+0x70> + +0800f6f4 <__floatunsidf>: + 800f6f4: defffe04 addi sp,sp,-8 + 800f6f8: dc000015 stw r16,0(sp) + 800f6fc: dfc00115 stw ra,4(sp) + 800f700: 2021883a mov r16,r4 + 800f704: 20000f26 beq r4,zero,800f744 <__floatunsidf+0x50> + 800f708: 800f7900 call 800f790 <__clzsi2> + 800f70c: 01010784 movi r4,1054 + 800f710: 2089c83a sub r4,r4,r2 + 800f714: 10c002c8 cmpgei r3,r2,11 + 800f718: 2101ffcc andi r4,r4,2047 + 800f71c: 1800151e bne r3,zero,800f774 <__floatunsidf+0x80> + 800f720: 00c002c4 movi r3,11 + 800f724: 1887c83a sub r3,r3,r2 + 800f728: 80c6d83a srl r3,r16,r3 + 800f72c: 01400434 movhi r5,16 + 800f730: 10800544 addi r2,r2,21 + 800f734: 297fffc4 addi r5,r5,-1 + 800f738: 80a0983a sll r16,r16,r2 + 800f73c: 1944703a and r2,r3,r5 + 800f740: 00000206 br 800f74c <__floatunsidf+0x58> + 800f744: 0009883a mov r4,zero + 800f748: 0005883a mov r2,zero + 800f74c: 2008953a slli r4,r4,20 + 800f750: 00c00434 movhi r3,16 + 800f754: 18ffffc4 addi r3,r3,-1 + 800f758: 10c6703a and r3,r2,r3 + 800f75c: 1906b03a or r3,r3,r4 + 800f760: 8005883a mov r2,r16 + 800f764: dfc00117 ldw ra,4(sp) + 800f768: dc000017 ldw r16,0(sp) + 800f76c: dec00204 addi sp,sp,8 + 800f770: f800283a ret + 800f774: 10bffd44 addi r2,r2,-11 + 800f778: 8084983a sll r2,r16,r2 + 800f77c: 00c00434 movhi r3,16 + 800f780: 18ffffc4 addi r3,r3,-1 + 800f784: 10c4703a and r2,r2,r3 + 800f788: 0021883a mov r16,zero + 800f78c: 003fef06 br 800f74c <__floatunsidf+0x58> + +0800f790 <__clzsi2>: + 800f790: 00bfffd4 movui r2,65535 + 800f794: 11000b36 bltu r2,r4,800f7c4 <__clzsi2+0x34> + 800f798: 20804030 cmpltui r2,r4,256 + 800f79c: 1000071e bne r2,zero,800f7bc <__clzsi2+0x2c> + 800f7a0: 2008d23a srli r4,r4,8 + 800f7a4: 01400604 movi r5,24 + 800f7a8: 00c20134 movhi r3,2052 + 800f7ac: 20c7883a add r3,r4,r3 + 800f7b0: 189d8903 ldbu r2,30244(r3) + 800f7b4: 2885c83a sub r2,r5,r2 + 800f7b8: f800283a ret + 800f7bc: 01400804 movi r5,32 + 800f7c0: 003ff906 br 800f7a8 <__clzsi2+0x18> + 800f7c4: 00804034 movhi r2,256 + 800f7c8: 20800336 bltu r4,r2,800f7d8 <__clzsi2+0x48> + 800f7cc: 2008d63a srli r4,r4,24 + 800f7d0: 01400204 movi r5,8 + 800f7d4: 003ff406 br 800f7a8 <__clzsi2+0x18> + 800f7d8: 2008d43a srli r4,r4,16 + 800f7dc: 01400404 movi r5,16 + 800f7e0: 003ff106 br 800f7a8 <__clzsi2+0x18> + +0800f7e4 : +#include "priv/alt_file.h" + +ALT_LLIST_HEAD(alt_flash_dev_list); + +alt_flash_fd* alt_flash_open_dev(const char* name) +{ + 800f7e4: defffc04 addi sp,sp,-16 + 800f7e8: dfc00315 stw ra,12(sp) + 800f7ec: df000215 stw fp,8(sp) + 800f7f0: df000204 addi fp,sp,8 + 800f7f4: e13ffe15 stw r4,-8(fp) + alt_flash_dev* dev = (alt_flash_dev*)alt_find_dev(name, &alt_flash_dev_list); + 800f7f8: d1600404 addi r5,gp,-32752 + 800f7fc: e13ffe17 ldw r4,-8(fp) + 800f800: 80374040 call 8037404 + 800f804: e0bfff15 stw r2,-4(fp) + + if ((dev) && dev->open) + 800f808: e0bfff17 ldw r2,-4(fp) + 800f80c: 10000926 beq r2,zero,800f834 + 800f810: e0bfff17 ldw r2,-4(fp) + 800f814: 10800317 ldw r2,12(r2) + 800f818: 10000626 beq r2,zero,800f834 + { + return dev->open(dev, name); + 800f81c: e0bfff17 ldw r2,-4(fp) + 800f820: 10800317 ldw r2,12(r2) + 800f824: e17ffe17 ldw r5,-8(fp) + 800f828: e13fff17 ldw r4,-4(fp) + 800f82c: 103ee83a callr r2 + 800f830: 00000106 br 800f838 + } + + return dev; + 800f834: e0bfff17 ldw r2,-4(fp) +} + 800f838: e037883a mov sp,fp + 800f83c: dfc00117 ldw ra,4(sp) + 800f840: df000017 ldw fp,0(sp) + 800f844: dec00204 addi sp,sp,8 + 800f848: f800283a ret + +0800f84c : + +void alt_flash_close_dev(alt_flash_fd* fd) +{ + 800f84c: defffd04 addi sp,sp,-12 + 800f850: dfc00215 stw ra,8(sp) + 800f854: df000115 stw fp,4(sp) + 800f858: df000104 addi fp,sp,4 + 800f85c: e13fff15 stw r4,-4(fp) + if (fd && fd->close) + 800f860: e0bfff17 ldw r2,-4(fp) + 800f864: 10000826 beq r2,zero,800f888 + 800f868: e0bfff17 ldw r2,-4(fp) + 800f86c: 10800417 ldw r2,16(r2) + 800f870: 10000526 beq r2,zero,800f888 + { + fd->close(fd); + 800f874: e0bfff17 ldw r2,-4(fp) + 800f878: 10800417 ldw r2,16(r2) + 800f87c: e13fff17 ldw r4,-4(fp) + 800f880: 103ee83a callr r2 + } + return; + 800f884: 0001883a nop + 800f888: 0001883a nop +} + 800f88c: e037883a mov sp,fp + 800f890: dfc00117 ldw ra,4(sp) + 800f894: df000017 ldw fp,0(sp) + 800f898: dec00204 addi sp,sp,8 + 800f89c: f800283a ret + +0800f8a0 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 800f8a0: defffe04 addi sp,sp,-8 + 800f8a4: dfc00115 stw ra,4(sp) + 800f8a8: df000015 stw fp,0(sp) + 800f8ac: d839883a mov fp,sp + return ((alt_errno) ? alt_errno() : &errno); + 800f8b0: d0a02717 ldw r2,-32612(gp) + 800f8b4: 10000326 beq r2,zero,800f8c4 + 800f8b8: d0a02717 ldw r2,-32612(gp) + 800f8bc: 103ee83a callr r2 + 800f8c0: 00000106 br 800f8c8 + 800f8c4: d0a04204 addi r2,gp,-32504 +} + 800f8c8: e037883a mov sp,fp + 800f8cc: dfc00117 ldw ra,4(sp) + 800f8d0: df000017 ldw fp,0(sp) + 800f8d4: dec00204 addi sp,sp,8 + 800f8d8: f800283a ret + +0800f8dc : +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_FSTAT (int file, struct stat *st) +{ + 800f8dc: defffb04 addi sp,sp,-20 + 800f8e0: dfc00415 stw ra,16(sp) + 800f8e4: df000315 stw fp,12(sp) + 800f8e8: df000304 addi fp,sp,12 + 800f8ec: e13ffe15 stw r4,-8(fp) + 800f8f0: e17ffd15 stw r5,-12(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 800f8f4: e0bffe17 ldw r2,-8(fp) + 800f8f8: 10000616 blt r2,zero,800f914 + 800f8fc: e0bffe17 ldw r2,-8(fp) + 800f900: 10c00324 muli r3,r2,12 + 800f904: 00820174 movhi r2,2053 + 800f908: 10b21a04 addi r2,r2,-14232 + 800f90c: 1885883a add r2,r3,r2 + 800f910: 00000106 br 800f918 + 800f914: 0005883a mov r2,zero + 800f918: e0bfff15 stw r2,-4(fp) + + if (fd) + 800f91c: e0bfff17 ldw r2,-4(fp) + 800f920: 10001026 beq r2,zero,800f964 + { + /* Call the drivers fstat() function to fill out the "st" structure. */ + + if (fd->dev->fstat) + 800f924: e0bfff17 ldw r2,-4(fp) + 800f928: 10800017 ldw r2,0(r2) + 800f92c: 10800817 ldw r2,32(r2) + 800f930: 10000726 beq r2,zero,800f950 + { + return fd->dev->fstat(fd, st); + 800f934: e0bfff17 ldw r2,-4(fp) + 800f938: 10800017 ldw r2,0(r2) + 800f93c: 10800817 ldw r2,32(r2) + 800f940: e17ffd17 ldw r5,-12(fp) + 800f944: e13fff17 ldw r4,-4(fp) + 800f948: 103ee83a callr r2 + 800f94c: 00000a06 br 800f978 + * device. + */ + + else + { + st->st_mode = _IFCHR; + 800f950: e0bffd17 ldw r2,-12(fp) + 800f954: 00c80004 movi r3,8192 + 800f958: 10c00115 stw r3,4(r2) + return 0; + 800f95c: 0005883a mov r2,zero + 800f960: 00000506 br 800f978 + } + } + else + { + ALT_ERRNO = EBADFD; + 800f964: 800f8a00 call 800f8a0 + 800f968: 1007883a mov r3,r2 + 800f96c: 00801444 movi r2,81 + 800f970: 18800015 stw r2,0(r3) + return -1; + 800f974: 00bfffc4 movi r2,-1 + } +} + 800f978: e037883a mov sp,fp + 800f97c: dfc00117 ldw ra,4(sp) + 800f980: df000017 ldw fp,0(sp) + 800f984: dec00204 addi sp,sp,8 + 800f988: f800283a ret + +0800f98c : +{ + 800f98c: defffe04 addi sp,sp,-8 + 800f990: dfc00115 stw ra,4(sp) + 800f994: df000015 stw fp,0(sp) + 800f998: d839883a mov fp,sp + return ((alt_errno) ? alt_errno() : &errno); + 800f99c: d0a02717 ldw r2,-32612(gp) + 800f9a0: 10000326 beq r2,zero,800f9b0 + 800f9a4: d0a02717 ldw r2,-32612(gp) + 800f9a8: 103ee83a callr r2 + 800f9ac: 00000106 br 800f9b4 + 800f9b0: d0a04204 addi r2,gp,-32504 +} + 800f9b4: e037883a mov sp,fp + 800f9b8: dfc00117 ldw ra,4(sp) + 800f9bc: df000017 ldw fp,0(sp) + 800f9c0: dec00204 addi sp,sp,8 + 800f9c4: f800283a ret + +0800f9c8 : + * + * ALT_ISATTY is mapped onto the isatty() system call in alt_syscall.h + */ + +int ALT_ISATTY (int file) +{ + 800f9c8: deffea04 addi sp,sp,-88 + 800f9cc: dfc01515 stw ra,84(sp) + 800f9d0: df001415 stw fp,80(sp) + 800f9d4: df001404 addi fp,sp,80 + 800f9d8: e13fec15 stw r4,-80(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 800f9dc: e0bfec17 ldw r2,-80(fp) + 800f9e0: 10000616 blt r2,zero,800f9fc + 800f9e4: e0bfec17 ldw r2,-80(fp) + 800f9e8: 10c00324 muli r3,r2,12 + 800f9ec: 00820174 movhi r2,2053 + 800f9f0: 10b21a04 addi r2,r2,-14232 + 800f9f4: 1885883a add r2,r3,r2 + 800f9f8: 00000106 br 800fa00 + 800f9fc: 0005883a mov r2,zero + 800fa00: e0bfff15 stw r2,-4(fp) + + if (fd) + 800fa04: e0bfff17 ldw r2,-4(fp) + 800fa08: 10000e26 beq r2,zero,800fa44 + /* + * If a device driver does not provide an fstat() function, then it is + * treated as a terminal device by default. + */ + + if (!fd->dev->fstat) + 800fa0c: e0bfff17 ldw r2,-4(fp) + 800fa10: 10800017 ldw r2,0(r2) + 800fa14: 10800817 ldw r2,32(r2) + 800fa18: 1000021e bne r2,zero,800fa24 + { + return 1; + 800fa1c: 00800044 movi r2,1 + 800fa20: 00000d06 br 800fa58 + * this is called so that the device can identify itself. + */ + + else + { + fstat (file, &stat); + 800fa24: e0bfed04 addi r2,fp,-76 + 800fa28: 100b883a mov r5,r2 + 800fa2c: e13fec17 ldw r4,-80(fp) + 800fa30: 800f8dc0 call 800f8dc + return (stat.st_mode == _IFCHR) ? 1 : 0; + 800fa34: e0bfee17 ldw r2,-72(fp) + 800fa38: 10880020 cmpeqi r2,r2,8192 + 800fa3c: 10803fcc andi r2,r2,255 + 800fa40: 00000506 br 800fa58 + } + } + else + { + ALT_ERRNO = EBADFD; + 800fa44: 800f98c0 call 800f98c + 800fa48: 1007883a mov r3,r2 + 800fa4c: 00801444 movi r2,81 + 800fa50: 18800015 stw r2,0(r3) + return 0; + 800fa54: 0005883a mov r2,zero + } +} + 800fa58: e037883a mov sp,fp + 800fa5c: dfc00117 ldw ra,4(sp) + 800fa60: df000017 ldw fp,0(sp) + 800fa64: dec00204 addi sp,sp,8 + 800fa68: f800283a ret + +0800fa6c : +{ + 800fa6c: defffe04 addi sp,sp,-8 + 800fa70: dfc00115 stw ra,4(sp) + 800fa74: df000015 stw fp,0(sp) + 800fa78: d839883a mov fp,sp + return ((alt_errno) ? alt_errno() : &errno); + 800fa7c: d0a02717 ldw r2,-32612(gp) + 800fa80: 10000326 beq r2,zero,800fa90 + 800fa84: d0a02717 ldw r2,-32612(gp) + 800fa88: 103ee83a callr r2 + 800fa8c: 00000106 br 800fa94 + 800fa90: d0a04204 addi r2,gp,-32504 +} + 800fa94: e037883a mov sp,fp + 800fa98: dfc00117 ldw ra,4(sp) + 800fa9c: df000017 ldw fp,0(sp) + 800faa0: dec00204 addi sp,sp,8 + 800faa4: f800283a ret + +0800faa8 : + * ALT_LSEEK is mapped onto the lseek() system call in alt_syscall.h + * + */ + +off_t ALT_LSEEK (int file, off_t ptr, int dir) +{ + 800faa8: defff904 addi sp,sp,-28 + 800faac: dfc00615 stw ra,24(sp) + 800fab0: df000515 stw fp,20(sp) + 800fab4: df000504 addi fp,sp,20 + 800fab8: e13ffd15 stw r4,-12(fp) + 800fabc: e17ffc15 stw r5,-16(fp) + 800fac0: e1bffb15 stw r6,-20(fp) + alt_fd* fd; + off_t rc = 0; + 800fac4: e03fff15 stw zero,-4(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 800fac8: e0bffd17 ldw r2,-12(fp) + 800facc: 10000616 blt r2,zero,800fae8 + 800fad0: e0bffd17 ldw r2,-12(fp) + 800fad4: 10c00324 muli r3,r2,12 + 800fad8: 00820174 movhi r2,2053 + 800fadc: 10b21a04 addi r2,r2,-14232 + 800fae0: 1885883a add r2,r3,r2 + 800fae4: 00000106 br 800faec + 800fae8: 0005883a mov r2,zero + 800faec: e0bffe15 stw r2,-8(fp) + + if (fd) + 800faf0: e0bffe17 ldw r2,-8(fp) + 800faf4: 10001026 beq r2,zero,800fb38 + /* + * If the device driver provides an implementation of the lseek() function, + * then call that to process the request. + */ + + if (fd->dev->lseek) + 800faf8: e0bffe17 ldw r2,-8(fp) + 800fafc: 10800017 ldw r2,0(r2) + 800fb00: 10800717 ldw r2,28(r2) + 800fb04: 10000926 beq r2,zero,800fb2c + { + rc = fd->dev->lseek(fd, ptr, dir); + 800fb08: e0bffe17 ldw r2,-8(fp) + 800fb0c: 10800017 ldw r2,0(r2) + 800fb10: 10800717 ldw r2,28(r2) + 800fb14: e1bffb17 ldw r6,-20(fp) + 800fb18: e17ffc17 ldw r5,-16(fp) + 800fb1c: e13ffe17 ldw r4,-8(fp) + 800fb20: 103ee83a callr r2 + 800fb24: e0bfff15 stw r2,-4(fp) + 800fb28: 00000506 br 800fb40 + * Otherwise return an error. + */ + + else + { + rc = -ENOTSUP; + 800fb2c: 00bfde84 movi r2,-134 + 800fb30: e0bfff15 stw r2,-4(fp) + 800fb34: 00000206 br 800fb40 + } + } + else + { + rc = -EBADFD; + 800fb38: 00bfebc4 movi r2,-81 + 800fb3c: e0bfff15 stw r2,-4(fp) + } + + if (rc < 0) + 800fb40: e0bfff17 ldw r2,-4(fp) + 800fb44: 1000070e bge r2,zero,800fb64 + { + ALT_ERRNO = -rc; + 800fb48: 800fa6c0 call 800fa6c + 800fb4c: 1007883a mov r3,r2 + 800fb50: e0bfff17 ldw r2,-4(fp) + 800fb54: 0085c83a sub r2,zero,r2 + 800fb58: 18800015 stw r2,0(r3) + rc = -1; + 800fb5c: 00bfffc4 movi r2,-1 + 800fb60: e0bfff15 stw r2,-4(fp) + } + + return rc; + 800fb64: e0bfff17 ldw r2,-4(fp) +} + 800fb68: e037883a mov sp,fp + 800fb6c: dfc00117 ldw ra,4(sp) + 800fb70: df000017 ldw fp,0(sp) + 800fb74: dec00204 addi sp,sp,8 + 800fb78: f800283a ret + +0800fb7c : + * devices/filesystems/components in the system; and call the entry point for + * the users application, i.e. main(). + */ + +void alt_main (void) +{ + 800fb7c: defffb04 addi sp,sp,-20 + 800fb80: dfc00415 stw ra,16(sp) + 800fb84: df000315 stw fp,12(sp) + 800fb88: df000304 addi fp,sp,12 +#endif + + /* ALT LOG - please see HAL/sys/alt_log_printf.h for details */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Entering alt_main, calling alt_irq_init.\r\n"); + /* Initialize the interrupt controller. */ + alt_irq_init (NULL); + 800fb8c: 0009883a mov r4,zero + 800fb90: 80177c80 call 80177c8 + + /* Initialize the operating system */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Done alt_irq_init, calling alt_os_init.\r\n"); + ALT_OS_INIT(); + 800fb94: 801077c0 call 801077c + 800fb98: 01000044 movi r4,1 + 800fb9c: 80157740 call 8015774 + 800fba0: d0a04815 stw r2,-32480(gp) + 800fba4: 01000044 movi r4,1 + 800fba8: 80157740 call 8015774 + 800fbac: d0a04a15 stw r2,-32472(gp) + 800fbb0: d0a08b04 addi r2,gp,-32212 + 800fbb4: e0bffe15 stw r2,-8(fp) + 800fbb8: 00800044 movi r2,1 + 800fbbc: e0bffd8d sth r2,-10(fp) + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sem_create (OS_EVENT** sem, + INT16U value) +{ + *sem = OSSemCreate (value); + 800fbc0: e0bffd8b ldhu r2,-10(fp) + 800fbc4: 1009883a mov r4,r2 + 800fbc8: 80157740 call 8015774 + 800fbcc: 1007883a mov r3,r2 + 800fbd0: e0bffe17 ldw r2,-8(fp) + 800fbd4: 10c00015 stw r3,0(r2) + ALT_LOG_PRINT_BOOT("[alt_main.c] Done OS Init, calling alt_sem_create.\r\n"); + ALT_SEM_CREATE (&alt_fd_list_lock, 1); + + /* Initialize the device drivers/software components. */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling alt_sys_init.\r\n"); + alt_sys_init(); + 800fbd8: 80178000 call 8017800 + * devices be present (not equal to /dev/null) and if direct drivers + * aren't being used. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Redirecting IO.\r\n"); + alt_io_redirect(ALT_STDOUT, ALT_STDIN, ALT_STDERR); + 800fbdc: 01820134 movhi r6,2052 + 800fbe0: 319dc904 addi r6,r6,30500 + 800fbe4: 01420134 movhi r5,2052 + 800fbe8: 295dc904 addi r5,r5,30500 + 800fbec: 01020134 movhi r4,2052 + 800fbf0: 211dc904 addi r4,r4,30500 + 800fbf4: 80377d80 call 80377d8 + /* + * Call the C++ constructors + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling C++ constructors.\r\n"); + _do_ctors (); + 800fbf8: 80373440 call 8037344 <_do_ctors> + * redefined as _exit()). This is in the interest of reducing code footprint, + * in that the atexit() overhead is removed when it's not needed. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling atexit.\r\n"); + atexit (_do_dtors); + 800fbfc: 010200f4 movhi r4,2051 + 800fc00: 211ce904 addi r4,r4,29604 + 800fc04: 8042a900 call 8042a90 + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling main.\r\n"); + +#ifdef ALT_NO_EXIT + main (alt_argc, alt_argv, alt_envp); +#else + result = main (alt_argc, alt_argv, alt_envp); + 800fc08: d0a04417 ldw r2,-32496(gp) + 800fc0c: d0e04517 ldw r3,-32492(gp) + 800fc10: d1204617 ldw r4,-32488(gp) + 800fc14: 200d883a mov r6,r4 + 800fc18: 180b883a mov r5,r3 + 800fc1c: 1009883a mov r4,r2 + 800fc20: 80011780 call 8001178
+ 800fc24: e0bfff15 stw r2,-4(fp) + close(STDOUT_FILENO); + 800fc28: 01000044 movi r4,1 + 800fc2c: 8022a600 call 8022a60 + exit (result); + 800fc30: e13fff17 ldw r4,-4(fp) + 800fc34: 8042abc0 call 8042abc + +0800fc38 : +#endif + +caddr_t ALT_SBRK (int incr) __attribute__ ((no_instrument_function )); + +caddr_t ALT_SBRK (int incr) +{ + 800fc38: defff904 addi sp,sp,-28 + 800fc3c: df000615 stw fp,24(sp) + 800fc40: df000604 addi fp,sp,24 + 800fc44: e13ffa15 stw r4,-24(fp) + NIOS2_READ_STATUS (context); + 800fc48: 0005303a rdctl r2,status + 800fc4c: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 800fc50: e0fffd17 ldw r3,-12(fp) + 800fc54: 00bfff84 movi r2,-2 + 800fc58: 1884703a and r2,r3,r2 + 800fc5c: 1001703a wrctl status,r2 + return context; + 800fc60: e0bffd17 ldw r2,-12(fp) + alt_irq_context context; + char *prev_heap_end; + + context = alt_irq_disable_all(); + 800fc64: e0bfff15 stw r2,-4(fp) + + /* Always return data aligned on a word boundary */ + heap_end = (char *)(((unsigned int)heap_end + 3) & ~3); + 800fc68: d0a00617 ldw r2,-32744(gp) + 800fc6c: 10c000c4 addi r3,r2,3 + 800fc70: 00bfff04 movi r2,-4 + 800fc74: 1884703a and r2,r3,r2 + 800fc78: d0a00615 stw r2,-32744(gp) + if (((heap_end + incr) - __alt_heap_start) > ALT_MAX_HEAP_BYTES) { + alt_irq_enable_all(context); + return (caddr_t)-1; + } +#else + if ((heap_end + incr) > __alt_heap_limit) { + 800fc7c: d0e00617 ldw r3,-32744(gp) + 800fc80: e0bffa17 ldw r2,-24(fp) + 800fc84: 1887883a add r3,r3,r2 + 800fc88: 00840034 movhi r2,4096 + 800fc8c: 10800004 addi r2,r2,0 + 800fc90: 10c0062e bgeu r2,r3,800fcac + 800fc94: e0bfff17 ldw r2,-4(fp) + 800fc98: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 800fc9c: e0bffc17 ldw r2,-16(fp) + 800fca0: 1001703a wrctl status,r2 + alt_irq_enable_all(context); + return (caddr_t)-1; + 800fca4: 00bfffc4 movi r2,-1 + 800fca8: 00000b06 br 800fcd8 + } +#endif + + prev_heap_end = heap_end; + 800fcac: d0a00617 ldw r2,-32744(gp) + 800fcb0: e0bffe15 stw r2,-8(fp) + heap_end += incr; + 800fcb4: d0e00617 ldw r3,-32744(gp) + 800fcb8: e0bffa17 ldw r2,-24(fp) + 800fcbc: 1885883a add r2,r3,r2 + 800fcc0: d0a00615 stw r2,-32744(gp) + 800fcc4: e0bfff17 ldw r2,-4(fp) + 800fcc8: e0bffb15 stw r2,-20(fp) + 800fccc: e0bffb17 ldw r2,-20(fp) + 800fcd0: 1001703a wrctl status,r2 + +#endif + + alt_irq_enable_all(context); + + return (caddr_t) prev_heap_end; + 800fcd4: e0bffe17 ldw r2,-8(fp) +} + 800fcd8: e037883a mov sp,fp + 800fcdc: df000017 ldw fp,0(sp) + 800fce0: dec00104 addi sp,sp,4 + 800fce4: f800283a ret + +0800fce8 <__env_lock>: +/* + * + */ + +void __env_lock ( struct _reent *_r ) +{ + 800fce8: deffdf04 addi sp,sp,-132 + 800fcec: dfc02015 stw ra,128(sp) + 800fcf0: df001f15 stw fp,124(sp) + 800fcf4: df001f04 addi fp,sp,124 + 800fcf8: e13fe115 stw r4,-124(fp) + INT8U err; + int id; + + /* use our priority as a task id */ + + err = OSTaskQuery( OS_PRIO_SELF, &tcb ); + 800fcfc: e0bfe404 addi r2,fp,-112 + 800fd00: 100b883a mov r5,r2 + 800fd04: 01003fc4 movi r4,255 + 800fd08: 80172200 call 8017220 + 800fd0c: e0bfe245 stb r2,-119(fp) + if (err != OS_NO_ERR) + 800fd10: e0bfe243 ldbu r2,-119(fp) + 800fd14: 10803fcc andi r2,r2,255 + 800fd18: 10001e1e bne r2,zero,800fd94 <__env_lock+0xac> + return; + + id = tcb.OSTCBPrio; + 800fd1c: e0bff083 ldbu r2,-62(fp) + 800fd20: 10803fcc andi r2,r2,255 + 800fd24: e0bfff15 stw r2,-4(fp) + + /* see if we own the environment already */ + + OSSemQuery( alt_envsem, &semdata ); + 800fd28: d0a04817 ldw r2,-32480(gp) + 800fd2c: e0ffe284 addi r3,fp,-118 + 800fd30: 180b883a mov r5,r3 + 800fd34: 1009883a mov r4,r2 + 800fd38: 8015e840 call 8015e84 + if( semdata.OSEventGrp && id == lockid ) + 800fd3c: e0bfe3c3 ldbu r2,-113(fp) + 800fd40: 10803fcc andi r2,r2,255 + 800fd44: 10000726 beq r2,zero,800fd64 <__env_lock+0x7c> + 800fd48: d0a00717 ldw r2,-32740(gp) + 800fd4c: e0ffff17 ldw r3,-4(fp) + 800fd50: 1880041e bne r3,r2,800fd64 <__env_lock+0x7c> + { + /* we do; just count the recursion */ + + locks++; + 800fd54: d0a04717 ldw r2,-32484(gp) + 800fd58: 10800044 addi r2,r2,1 + 800fd5c: d0a04715 stw r2,-32484(gp) + 800fd60: 00000a06 br 800fd8c <__env_lock+0xa4> + } + else + { + /* wait on the other task to yield, then claim ownership */ + + OSSemPend( alt_envsem, 0, &err ); + 800fd64: d0a04817 ldw r2,-32480(gp) + 800fd68: e0ffe244 addi r3,fp,-119 + 800fd6c: 180d883a mov r6,r3 + 800fd70: 000b883a mov r5,zero + 800fd74: 1009883a mov r4,r2 + 800fd78: 8015a600 call 8015a60 + locks = 1; + 800fd7c: 00800044 movi r2,1 + 800fd80: d0a04715 stw r2,-32484(gp) + lockid = id; + 800fd84: e0bfff17 ldw r2,-4(fp) + 800fd88: d0a00715 stw r2,-32740(gp) + } + +#endif /* OS_THREAD_SAFE_NEWLIB */ + return; + 800fd8c: 0001883a nop + 800fd90: 00000106 br 800fd98 <__env_lock+0xb0> + return; + 800fd94: 0001883a nop +} + 800fd98: e037883a mov sp,fp + 800fd9c: dfc00117 ldw ra,4(sp) + 800fda0: df000017 ldw fp,0(sp) + 800fda4: dec00204 addi sp,sp,8 + 800fda8: f800283a ret + +0800fdac <__env_unlock>: +/* + * + */ + +void __env_unlock ( struct _reent *_r ) +{ + 800fdac: defffd04 addi sp,sp,-12 + 800fdb0: dfc00215 stw ra,8(sp) + 800fdb4: df000115 stw fp,4(sp) + 800fdb8: df000104 addi fp,sp,4 + 800fdbc: e13fff15 stw r4,-4(fp) +#if OS_THREAD_SAFE_NEWLIB + if (locks == 0) + 800fdc0: d0a04717 ldw r2,-32484(gp) + 800fdc4: 10000b26 beq r2,zero,800fdf4 <__env_unlock+0x48> + /* + * release the environment once the number of locks == the number + * of unlocks + */ + + if( (--locks) == 0 ) + 800fdc8: d0a04717 ldw r2,-32484(gp) + 800fdcc: 10bfffc4 addi r2,r2,-1 + 800fdd0: d0a04715 stw r2,-32484(gp) + 800fdd4: d0a04717 ldw r2,-32484(gp) + 800fdd8: 1000071e bne r2,zero,800fdf8 <__env_unlock+0x4c> + { + lockid = -1; + 800fddc: 00bfffc4 movi r2,-1 + 800fde0: d0a00715 stw r2,-32740(gp) + OSSemPost( alt_envsem ); + 800fde4: d0a04817 ldw r2,-32480(gp) + 800fde8: 1009883a mov r4,r2 + 800fdec: 8015d840 call 8015d84 + 800fdf0: 00000106 br 800fdf8 <__env_unlock+0x4c> + return; + 800fdf4: 0001883a nop + } +#endif /* OS_THREAD_SAFE_NEWLIB */ +} + 800fdf8: e037883a mov sp,fp + 800fdfc: dfc00117 ldw ra,4(sp) + 800fe00: df000017 ldw fp,0(sp) + 800fe04: dec00204 addi sp,sp,8 + 800fe08: f800283a ret + +0800fe0c <__malloc_lock>: +/* + * + */ + +void __malloc_lock ( struct _reent *_r ) +{ + 800fe0c: deffdb04 addi sp,sp,-148 + 800fe10: dfc02415 stw ra,144(sp) + 800fe14: df002315 stw fp,140(sp) + 800fe18: df002304 addi fp,sp,140 + 800fe1c: e13fdd15 stw r4,-140(fp) + OS_TCB tcb; + OS_SEM_DATA semdata; + INT8U err; + int id; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 800fe20: e03fff15 stw zero,-4(fp) +#endif + + if (OSRunning != OS_TRUE) + 800fe24: d0a04b43 ldbu r2,-32467(gp) + 800fe28: 10803fcc andi r2,r2,255 + 800fe2c: 10800060 cmpeqi r2,r2,1 + 800fe30: 10003626 beq r2,zero,800ff0c <__malloc_lock+0x100> + return; + + /* use our priority as a task id */ + + err = OSTaskQuery( OS_PRIO_SELF, &tcb ); + 800fe34: e0bfe004 addi r2,fp,-128 + 800fe38: 100b883a mov r5,r2 + 800fe3c: 01003fc4 movi r4,255 + 800fe40: 80172200 call 8017220 + 800fe44: e0bfde45 stb r2,-135(fp) + if (err != OS_NO_ERR) + 800fe48: e0bfde43 ldbu r2,-135(fp) + 800fe4c: 10803fcc andi r2,r2,255 + 800fe50: 1000301e bne r2,zero,800ff14 <__malloc_lock+0x108> + return; + + id = tcb.OSTCBPrio; + 800fe54: e0bfec83 ldbu r2,-78(fp) + 800fe58: 10803fcc andi r2,r2,255 + 800fe5c: e0bffe15 stw r2,-8(fp) + + /* see if we own the heap already */ + + OSSemQuery( alt_heapsem, &semdata ); + 800fe60: d0a04a17 ldw r2,-32472(gp) + 800fe64: e0ffde84 addi r3,fp,-134 + 800fe68: 180b883a mov r5,r3 + 800fe6c: 1009883a mov r4,r2 + 800fe70: 8015e840 call 8015e84 + NIOS2_READ_STATUS (context); + 800fe74: 0005303a rdctl r2,status + 800fe78: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 800fe7c: e0fffd17 ldw r3,-12(fp) + 800fe80: 00bfff84 movi r2,-2 + 800fe84: 1884703a and r2,r3,r2 + 800fe88: 1001703a wrctl status,r2 + return context; + 800fe8c: e0bffd17 ldw r2,-12(fp) + + OS_ENTER_CRITICAL(); + 800fe90: e0bfff15 stw r2,-4(fp) + + if( !semdata.OSCnt && id == lockid ) + 800fe94: e0bfde8b ldhu r2,-134(fp) + 800fe98: 10bfffcc andi r2,r2,65535 + 800fe9c: 10000b1e bne r2,zero,800fecc <__malloc_lock+0xc0> + 800fea0: d0a00817 ldw r2,-32736(gp) + 800fea4: e0fffe17 ldw r3,-8(fp) + 800fea8: 1880081e bne r3,r2,800fecc <__malloc_lock+0xc0> + { + /* we do; just count the recursion */ + locks++; + 800feac: d0a04917 ldw r2,-32476(gp) + 800feb0: 10800044 addi r2,r2,1 + 800feb4: d0a04915 stw r2,-32476(gp) + 800feb8: e0bfff17 ldw r2,-4(fp) + 800febc: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 800fec0: e0bffc17 ldw r2,-16(fp) + 800fec4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + 800fec8: 00000e06 br 800ff04 <__malloc_lock+0xf8> + 800fecc: e0bfff17 ldw r2,-4(fp) + 800fed0: e0bffb15 stw r2,-20(fp) + 800fed4: e0bffb17 ldw r2,-20(fp) + 800fed8: 1001703a wrctl status,r2 + else + { + /* wait on the other task to yield the heap, then claim ownership of it */ + OS_EXIT_CRITICAL(); + + OSSemPend( alt_heapsem, 0, &err ); + 800fedc: d0a04a17 ldw r2,-32472(gp) + 800fee0: e0ffde44 addi r3,fp,-135 + 800fee4: 180d883a mov r6,r3 + 800fee8: 000b883a mov r5,zero + 800feec: 1009883a mov r4,r2 + 800fef0: 8015a600 call 8015a60 + locks = 1; + 800fef4: 00800044 movi r2,1 + 800fef8: d0a04915 stw r2,-32476(gp) + lockid = id; + 800fefc: e0bffe17 ldw r2,-8(fp) + 800ff00: d0a00815 stw r2,-32736(gp) + } + +#endif /* OS_THREAD_SAFE_NEWLIB */ + return; + 800ff04: 0001883a nop + 800ff08: 00000306 br 800ff18 <__malloc_lock+0x10c> + return; + 800ff0c: 0001883a nop + 800ff10: 00000106 br 800ff18 <__malloc_lock+0x10c> + return; + 800ff14: 0001883a nop +} + 800ff18: e037883a mov sp,fp + 800ff1c: dfc00117 ldw ra,4(sp) + 800ff20: df000017 ldw fp,0(sp) + 800ff24: dec00204 addi sp,sp,8 + 800ff28: f800283a ret + +0800ff2c <__malloc_unlock>: +/* + * + */ + +void __malloc_unlock ( struct _reent *_r ) +{ + 800ff2c: defff804 addi sp,sp,-32 + 800ff30: dfc00715 stw ra,28(sp) + 800ff34: df000615 stw fp,24(sp) + 800ff38: df000604 addi fp,sp,24 + 800ff3c: e13ffa15 stw r4,-24(fp) +#if OS_THREAD_SAFE_NEWLIB + +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 800ff40: e03fff15 stw zero,-4(fp) +#endif + + if (OSRunning != OS_TRUE) + 800ff44: d0a04b43 ldbu r2,-32467(gp) + 800ff48: 10803fcc andi r2,r2,255 + 800ff4c: 10800060 cmpeqi r2,r2,1 + 800ff50: 10002326 beq r2,zero,800ffe0 <__malloc_unlock+0xb4> + NIOS2_READ_STATUS (context); + 800ff54: 0005303a rdctl r2,status + 800ff58: e0bffe15 stw r2,-8(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 800ff5c: e0fffe17 ldw r3,-8(fp) + 800ff60: 00bfff84 movi r2,-2 + 800ff64: 1884703a and r2,r3,r2 + 800ff68: 1001703a wrctl status,r2 + return context; + 800ff6c: e0bffe17 ldw r2,-8(fp) + return; + + OS_ENTER_CRITICAL(); + 800ff70: e0bfff15 stw r2,-4(fp) + if (locks == 0) + 800ff74: d0a04917 ldw r2,-32476(gp) + 800ff78: 1000051e bne r2,zero,800ff90 <__malloc_unlock+0x64> + 800ff7c: e0bfff17 ldw r2,-4(fp) + 800ff80: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context); + 800ff84: e0bffd17 ldw r2,-12(fp) + 800ff88: 1001703a wrctl status,r2 + { + OS_EXIT_CRITICAL(); + return; + 800ff8c: 00001506 br 800ffe4 <__malloc_unlock+0xb8> + } + + /* release the heap once the number of locks == the number of unlocks */ + if( (--locks) == 0 ) + 800ff90: d0a04917 ldw r2,-32476(gp) + 800ff94: 10bfffc4 addi r2,r2,-1 + 800ff98: d0a04915 stw r2,-32476(gp) + 800ff9c: d0a04917 ldw r2,-32476(gp) + 800ffa0: 10000a1e bne r2,zero,800ffcc <__malloc_unlock+0xa0> + { + lockid = -1; + 800ffa4: 00bfffc4 movi r2,-1 + 800ffa8: d0a00815 stw r2,-32736(gp) + 800ffac: e0bfff17 ldw r2,-4(fp) + 800ffb0: e0bffc15 stw r2,-16(fp) + 800ffb4: e0bffc17 ldw r2,-16(fp) + 800ffb8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OSSemPost( alt_heapsem ); + 800ffbc: d0a04a17 ldw r2,-32472(gp) + 800ffc0: 1009883a mov r4,r2 + 800ffc4: 8015d840 call 8015d84 + 800ffc8: 00000606 br 800ffe4 <__malloc_unlock+0xb8> + 800ffcc: e0bfff17 ldw r2,-4(fp) + 800ffd0: e0bffb15 stw r2,-20(fp) + 800ffd4: e0bffb17 ldw r2,-20(fp) + 800ffd8: 1001703a wrctl status,r2 + 800ffdc: 00000106 br 800ffe4 <__malloc_unlock+0xb8> + return; + 800ffe0: 0001883a nop + { + OS_EXIT_CRITICAL(); + } + +#endif /* OS_THREAD_SAFE_NEWLIB */ +} + 800ffe4: e037883a mov sp,fp + 800ffe8: dfc00117 ldw ra,4(sp) + 800ffec: df000017 ldw fp,0(sp) + 800fff0: dec00204 addi sp,sp,8 + 800fff4: f800283a ret + +0800fff8 : +********************************************************************************************************* +*/ + +#if (OS_EVENT_EN) && (OS_EVENT_NAME_SIZE > 1) +INT8U OSEventNameGet (OS_EVENT *pevent, INT8U *pname, INT8U *perr) +{ + 800fff8: defff704 addi sp,sp,-36 + 800fffc: dfc00815 stw ra,32(sp) + 8010000: df000715 stw fp,28(sp) + 8010004: df000704 addi fp,sp,28 + 8010008: e13ffb15 stw r4,-20(fp) + 801000c: e17ffa15 stw r5,-24(fp) + 8010010: e1bff915 stw r6,-28(fp) + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8010014: e03fff15 stw zero,-4(fp) + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + *perr = OS_ERR_PNAME_NULL; + return (0); + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 8010018: d0a05703 ldbu r2,-32420(gp) + 801001c: 10803fcc andi r2,r2,255 + 8010020: 10000526 beq r2,zero,8010038 + *perr = OS_ERR_NAME_GET_ISR; + 8010024: e0bff917 ldw r2,-28(fp) + 8010028: 00c00444 movi r3,17 + 801002c: 10c00005 stb r3,0(r2) + return (0); + 8010030: 0005883a mov r2,zero + 8010034: 00002106 br 80100bc + } + switch (pevent->OSEventType) { + 8010038: e0bffb17 ldw r2,-20(fp) + 801003c: 10800003 ldbu r2,0(r2) + 8010040: 10803fcc andi r2,r2,255 + 8010044: 10bfffc4 addi r2,r2,-1 + 8010048: 10800128 cmpgeui r2,r2,4 + 801004c: 10000526 beq r2,zero,8010064 + case OS_EVENT_TYPE_MBOX: + case OS_EVENT_TYPE_Q: + break; + + default: + *perr = OS_ERR_EVENT_TYPE; + 8010050: e0bff917 ldw r2,-28(fp) + 8010054: 00c00044 movi r3,1 + 8010058: 10c00005 stb r3,0(r2) + return (0); + 801005c: 0005883a mov r2,zero + 8010060: 00001606 br 80100bc + break; + 8010064: 0001883a nop + NIOS2_READ_STATUS (context); + 8010068: 0005303a rdctl r2,status + 801006c: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8010070: e0fffc17 ldw r3,-16(fp) + 8010074: 00bfff84 movi r2,-2 + 8010078: 1884703a and r2,r3,r2 + 801007c: 1001703a wrctl status,r2 + return context; + 8010080: e0bffc17 ldw r2,-16(fp) + } + OS_ENTER_CRITICAL(); + 8010084: e0bfff15 stw r2,-4(fp) + len = OS_StrCopy(pname, pevent->OSEventName); /* Copy name from OS_EVENT */ + 8010088: e0bffb17 ldw r2,-20(fp) + 801008c: 10800384 addi r2,r2,14 + 8010090: 100b883a mov r5,r2 + 8010094: e13ffa17 ldw r4,-24(fp) + 8010098: 80117a00 call 80117a0 + 801009c: e0bffec5 stb r2,-5(fp) + 80100a0: e0bfff17 ldw r2,-4(fp) + 80100a4: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context); + 80100a8: e0bffd17 ldw r2,-12(fp) + 80100ac: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 80100b0: e0bff917 ldw r2,-28(fp) + 80100b4: 10000005 stb zero,0(r2) + return (len); + 80100b8: e0bffec3 ldbu r2,-5(fp) +} + 80100bc: e037883a mov sp,fp + 80100c0: dfc00117 ldw ra,4(sp) + 80100c4: df000017 ldw fp,0(sp) + 80100c8: dec00204 addi sp,sp,8 + 80100cc: f800283a ret + +080100d0 : +********************************************************************************************************* +*/ + +#if (OS_EVENT_EN) && (OS_EVENT_NAME_SIZE > 1) +void OSEventNameSet (OS_EVENT *pevent, INT8U *pname, INT8U *perr) +{ + 80100d0: defff604 addi sp,sp,-40 + 80100d4: dfc00915 stw ra,36(sp) + 80100d8: df000815 stw fp,32(sp) + 80100dc: df000804 addi fp,sp,32 + 80100e0: e13ffa15 stw r4,-24(fp) + 80100e4: e17ff915 stw r5,-28(fp) + 80100e8: e1bff815 stw r6,-32(fp) + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 80100ec: e03fff15 stw zero,-4(fp) + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + *perr = OS_ERR_PNAME_NULL; + return; + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 80100f0: d0a05703 ldbu r2,-32420(gp) + 80100f4: 10803fcc andi r2,r2,255 + 80100f8: 10000426 beq r2,zero,801010c + *perr = OS_ERR_NAME_SET_ISR; + 80100fc: e0bff817 ldw r2,-32(fp) + 8010100: 00c00484 movi r3,18 + 8010104: 10c00005 stb r3,0(r2) + return; + 8010108: 00002c06 br 80101bc + } + switch (pevent->OSEventType) { + 801010c: e0bffa17 ldw r2,-24(fp) + 8010110: 10800003 ldbu r2,0(r2) + 8010114: 10803fcc andi r2,r2,255 + 8010118: 10bfffc4 addi r2,r2,-1 + 801011c: 10800128 cmpgeui r2,r2,4 + 8010120: 10000426 beq r2,zero,8010134 + case OS_EVENT_TYPE_MBOX: + case OS_EVENT_TYPE_Q: + break; + + default: + *perr = OS_ERR_EVENT_TYPE; + 8010124: e0bff817 ldw r2,-32(fp) + 8010128: 00c00044 movi r3,1 + 801012c: 10c00005 stb r3,0(r2) + return; + 8010130: 00002206 br 80101bc + break; + 8010134: 0001883a nop + NIOS2_READ_STATUS (context); + 8010138: 0005303a rdctl r2,status + 801013c: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8010140: e0fffd17 ldw r3,-12(fp) + 8010144: 00bfff84 movi r2,-2 + 8010148: 1884703a and r2,r3,r2 + 801014c: 1001703a wrctl status,r2 + return context; + 8010150: e0bffd17 ldw r2,-12(fp) + } + OS_ENTER_CRITICAL(); + 8010154: e0bfff15 stw r2,-4(fp) + len = OS_StrLen(pname); /* Can we fit the string in the storage area? */ + 8010158: e13ff917 ldw r4,-28(fp) + 801015c: 80118140 call 8011814 + 8010160: e0bffec5 stb r2,-5(fp) + if (len > (OS_EVENT_NAME_SIZE - 1)) { /* No */ + 8010164: e0bffec3 ldbu r2,-5(fp) + 8010168: 10800830 cmpltui r2,r2,32 + 801016c: 1000081e bne r2,zero,8010190 + 8010170: e0bfff17 ldw r2,-4(fp) + 8010174: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 8010178: e0bffc17 ldw r2,-16(fp) + 801017c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_EVENT_NAME_TOO_LONG; + 8010180: e0bff817 ldw r2,-32(fp) + 8010184: 00c002c4 movi r3,11 + 8010188: 10c00005 stb r3,0(r2) + return; + 801018c: 00000b06 br 80101bc + } + (void)OS_StrCopy(pevent->OSEventName, pname); /* Yes, copy name to the event control block */ + 8010190: e0bffa17 ldw r2,-24(fp) + 8010194: 10800384 addi r2,r2,14 + 8010198: e17ff917 ldw r5,-28(fp) + 801019c: 1009883a mov r4,r2 + 80101a0: 80117a00 call 80117a0 + 80101a4: e0bfff17 ldw r2,-4(fp) + 80101a8: e0bffb15 stw r2,-20(fp) + 80101ac: e0bffb17 ldw r2,-20(fp) + 80101b0: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 80101b4: e0bff817 ldw r2,-32(fp) + 80101b8: 10000005 stb zero,0(r2) +} + 80101bc: e037883a mov sp,fp + 80101c0: dfc00117 ldw ra,4(sp) + 80101c4: df000017 ldw fp,0(sp) + 80101c8: dec00204 addi sp,sp,8 + 80101cc: f800283a ret + +080101d0 : +********************************************************************************************************* +*/ +/*$PAGE*/ +#if ((OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0)) +INT16U OSEventPendMulti (OS_EVENT **pevents_pend, OS_EVENT **pevents_rdy, void **pmsgs_rdy, INT16U timeout, INT8U *perr) +{ + 80101d0: deffed04 addi sp,sp,-76 + 80101d4: dfc01215 stw ra,72(sp) + 80101d8: df001115 stw fp,68(sp) + 80101dc: df001104 addi fp,sp,68 + 80101e0: e13ff215 stw r4,-56(fp) + 80101e4: e17ff115 stw r5,-60(fp) + 80101e8: e1bff015 stw r6,-64(fp) + 80101ec: 3805883a mov r2,r7 + 80101f0: e0bfef0d sth r2,-68(fp) +#endif + BOOLEAN events_rdy; + INT16U events_rdy_nbr; + INT8U events_stat; +#if (OS_CRITICAL_METHOD == 3) /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 80101f4: e03ffb15 stw zero,-20(fp) + *perr = OS_ERR_PEVENT_NULL; + return (0); + } +#endif + + *pevents_rdy = (OS_EVENT *)0; /* Init array to NULL in case of errors */ + 80101f8: e0bff117 ldw r2,-60(fp) + 80101fc: 10000015 stw zero,0(r2) + + pevents = pevents_pend; + 8010200: e0bff217 ldw r2,-56(fp) + 8010204: e0bfff15 stw r2,-4(fp) + pevent = *pevents; + 8010208: e0bfff17 ldw r2,-4(fp) + 801020c: 10800017 ldw r2,0(r2) + 8010210: e0bffe15 stw r2,-8(fp) + while (pevent != (OS_EVENT *)0) { + 8010214: 00001906 br 801027c + switch (pevent->OSEventType) { /* Validate event block types */ + 8010218: e0bffe17 ldw r2,-8(fp) + 801021c: 10800003 ldbu r2,0(r2) + 8010220: 10803fcc andi r2,r2,255 + 8010224: 10c000a0 cmpeqi r3,r2,2 + 8010228: 1800091e bne r3,zero,8010250 + 801022c: 10c000e0 cmpeqi r3,r2,3 + 8010230: 1800091e bne r3,zero,8010258 + 8010234: 10800060 cmpeqi r2,r2,1 + 8010238: 1000091e bne r2,zero,8010260 +#endif + + case OS_EVENT_TYPE_MUTEX: + case OS_EVENT_TYPE_FLAG: + default: + *perr = OS_ERR_EVENT_TYPE; + 801023c: e0800217 ldw r2,8(fp) + 8010240: 00c00044 movi r3,1 + 8010244: 10c00005 stb r3,0(r2) + return (0); + 8010248: 0005883a mov r2,zero + 801024c: 00014606 br 8010768 + break; + 8010250: 0001883a nop + 8010254: 00000306 br 8010264 + break; + 8010258: 0001883a nop + 801025c: 00000106 br 8010264 + break; + 8010260: 0001883a nop + } + pevents++; + 8010264: e0bfff17 ldw r2,-4(fp) + 8010268: 10800104 addi r2,r2,4 + 801026c: e0bfff15 stw r2,-4(fp) + pevent = *pevents; + 8010270: e0bfff17 ldw r2,-4(fp) + 8010274: 10800017 ldw r2,0(r2) + 8010278: e0bffe15 stw r2,-8(fp) + while (pevent != (OS_EVENT *)0) { + 801027c: e0bffe17 ldw r2,-8(fp) + 8010280: 103fe51e bne r2,zero,8010218 + } + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 8010284: d0a05703 ldbu r2,-32420(gp) + 8010288: 10803fcc andi r2,r2,255 + 801028c: 10000526 beq r2,zero,80102a4 + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + 8010290: e0800217 ldw r2,8(fp) + 8010294: 00c00084 movi r3,2 + 8010298: 10c00005 stb r3,0(r2) + return (0); + 801029c: 0005883a mov r2,zero + 80102a0: 00013106 br 8010768 + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + 80102a4: d0a04b03 ldbu r2,-32468(gp) + 80102a8: 10803fcc andi r2,r2,255 + 80102ac: 10000526 beq r2,zero,80102c4 + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + 80102b0: e0800217 ldw r2,8(fp) + 80102b4: 00c00344 movi r3,13 + 80102b8: 10c00005 stb r3,0(r2) + return (0); + 80102bc: 0005883a mov r2,zero + 80102c0: 00012906 br 8010768 + NIOS2_READ_STATUS (context); + 80102c4: 0005303a rdctl r2,status + 80102c8: e0bff915 stw r2,-28(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 80102cc: e0fff917 ldw r3,-28(fp) + 80102d0: 00bfff84 movi r2,-2 + 80102d4: 1884703a and r2,r3,r2 + 80102d8: 1001703a wrctl status,r2 + return context; + 80102dc: e0bff917 ldw r2,-28(fp) + } + +/*$PAGE*/ + OS_ENTER_CRITICAL(); + 80102e0: e0bffb15 stw r2,-20(fp) + events_rdy = OS_FALSE; + 80102e4: e03ffdc5 stb zero,-9(fp) + events_rdy_nbr = 0; + 80102e8: e03ffd0d sth zero,-12(fp) + events_stat = OS_STAT_RDY; + 80102ec: e03ffcc5 stb zero,-13(fp) + pevents = pevents_pend; + 80102f0: e0bff217 ldw r2,-56(fp) + 80102f4: e0bfff15 stw r2,-4(fp) + pevent = *pevents; + 80102f8: e0bfff17 ldw r2,-4(fp) + 80102fc: 10800017 ldw r2,0(r2) + 8010300: e0bffe15 stw r2,-8(fp) + while (pevent != (OS_EVENT *)0) { /* See if any events already available */ + 8010304: 00008106 br 801050c + switch (pevent->OSEventType) { + 8010308: e0bffe17 ldw r2,-8(fp) + 801030c: 10800003 ldbu r2,0(r2) + 8010310: 10803fcc andi r2,r2,255 + 8010314: 10c000a0 cmpeqi r3,r2,2 + 8010318: 18003c1e bne r3,zero,801040c + 801031c: 10c000e0 cmpeqi r3,r2,3 + 8010320: 1800031e bne r3,zero,8010330 + 8010324: 10800060 cmpeqi r2,r2,1 + 8010328: 10001e1e bne r2,zero,80103a4 + 801032c: 00006606 br 80104c8 +#if (OS_SEM_EN > 0) + case OS_EVENT_TYPE_SEM: + if (pevent->OSEventCnt > 0) { /* If semaphore count > 0, resource available; */ + 8010330: e0bffe17 ldw r2,-8(fp) + 8010334: 1080020b ldhu r2,8(r2) + 8010338: 10bfffcc andi r2,r2,65535 + 801033c: 10001526 beq r2,zero,8010394 + pevent->OSEventCnt--; /* ... decrement semaphore, ... */ + 8010340: e0bffe17 ldw r2,-8(fp) + 8010344: 1080020b ldhu r2,8(r2) + 8010348: 10bfffc4 addi r2,r2,-1 + 801034c: 1007883a mov r3,r2 + 8010350: e0bffe17 ldw r2,-8(fp) + 8010354: 10c0020d sth r3,8(r2) + *pevents_rdy++ = pevent; /* ... and return available semaphore event */ + 8010358: e0bff117 ldw r2,-60(fp) + 801035c: 10c00104 addi r3,r2,4 + 8010360: e0fff115 stw r3,-60(fp) + 8010364: e0fffe17 ldw r3,-8(fp) + 8010368: 10c00015 stw r3,0(r2) + events_rdy = OS_TRUE; + 801036c: 00800044 movi r2,1 + 8010370: e0bffdc5 stb r2,-9(fp) + *pmsgs_rdy++ = (void *)0; /* NO message returned for semaphores */ + 8010374: e0bff017 ldw r2,-64(fp) + 8010378: 10c00104 addi r3,r2,4 + 801037c: e0fff015 stw r3,-64(fp) + 8010380: 10000015 stw zero,0(r2) + events_rdy_nbr++; + 8010384: e0bffd0b ldhu r2,-12(fp) + 8010388: 10800044 addi r2,r2,1 + 801038c: e0bffd0d sth r2,-12(fp) + + } else { + events_stat |= OS_STAT_SEM; /* Configure multi-pend for semaphore events */ + } + break; + 8010390: 00005806 br 80104f4 + events_stat |= OS_STAT_SEM; /* Configure multi-pend for semaphore events */ + 8010394: e0bffcc3 ldbu r2,-13(fp) + 8010398: 10800054 ori r2,r2,1 + 801039c: e0bffcc5 stb r2,-13(fp) + break; + 80103a0: 00005406 br 80104f4 +#endif + +#if (OS_MBOX_EN > 0) + case OS_EVENT_TYPE_MBOX: + if (pevent->OSEventPtr != (void *)0) { /* If mailbox NOT empty; ... */ + 80103a4: e0bffe17 ldw r2,-8(fp) + 80103a8: 10800117 ldw r2,4(r2) + 80103ac: 10001326 beq r2,zero,80103fc + /* ... return available message, ... */ + *pmsgs_rdy++ = (void *)pevent->OSEventPtr; + 80103b0: e0bff017 ldw r2,-64(fp) + 80103b4: 10c00104 addi r3,r2,4 + 80103b8: e0fff015 stw r3,-64(fp) + 80103bc: e0fffe17 ldw r3,-8(fp) + 80103c0: 18c00117 ldw r3,4(r3) + 80103c4: 10c00015 stw r3,0(r2) + pevent->OSEventPtr = (void *)0; + 80103c8: e0bffe17 ldw r2,-8(fp) + 80103cc: 10000115 stw zero,4(r2) + *pevents_rdy++ = pevent; /* ... and return available mailbox event */ + 80103d0: e0bff117 ldw r2,-60(fp) + 80103d4: 10c00104 addi r3,r2,4 + 80103d8: e0fff115 stw r3,-60(fp) + 80103dc: e0fffe17 ldw r3,-8(fp) + 80103e0: 10c00015 stw r3,0(r2) + events_rdy = OS_TRUE; + 80103e4: 00800044 movi r2,1 + 80103e8: e0bffdc5 stb r2,-9(fp) + events_rdy_nbr++; + 80103ec: e0bffd0b ldhu r2,-12(fp) + 80103f0: 10800044 addi r2,r2,1 + 80103f4: e0bffd0d sth r2,-12(fp) + + } else { + events_stat |= OS_STAT_MBOX; /* Configure multi-pend for mailbox events */ + } + break; + 80103f8: 00003e06 br 80104f4 + events_stat |= OS_STAT_MBOX; /* Configure multi-pend for mailbox events */ + 80103fc: e0bffcc3 ldbu r2,-13(fp) + 8010400: 10800094 ori r2,r2,2 + 8010404: e0bffcc5 stb r2,-13(fp) + break; + 8010408: 00003a06 br 80104f4 +#endif + +#if ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) + case OS_EVENT_TYPE_Q: + pq = (OS_Q *)pevent->OSEventPtr; + 801040c: e0bffe17 ldw r2,-8(fp) + 8010410: 10800117 ldw r2,4(r2) + 8010414: e0bffa15 stw r2,-24(fp) + if (pq->OSQEntries > 0) { /* If queue NOT empty; ... */ + 8010418: e0bffa17 ldw r2,-24(fp) + 801041c: 1080058b ldhu r2,22(r2) + 8010420: 10bfffcc andi r2,r2,65535 + 8010424: 10002426 beq r2,zero,80104b8 + /* ... return available message, ... */ + *pmsgs_rdy++ = (void *)*pq->OSQOut++; + 8010428: e0bffa17 ldw r2,-24(fp) + 801042c: 10c00417 ldw r3,16(r2) + 8010430: 19000104 addi r4,r3,4 + 8010434: e0bffa17 ldw r2,-24(fp) + 8010438: 11000415 stw r4,16(r2) + 801043c: e0bff017 ldw r2,-64(fp) + 8010440: 11000104 addi r4,r2,4 + 8010444: e13ff015 stw r4,-64(fp) + 8010448: 18c00017 ldw r3,0(r3) + 801044c: 10c00015 stw r3,0(r2) + if (pq->OSQOut == pq->OSQEnd) { /* If OUT ptr at queue end, ... */ + 8010450: e0bffa17 ldw r2,-24(fp) + 8010454: 10c00417 ldw r3,16(r2) + 8010458: e0bffa17 ldw r2,-24(fp) + 801045c: 10800217 ldw r2,8(r2) + 8010460: 1880041e bne r3,r2,8010474 + pq->OSQOut = pq->OSQStart; /* ... wrap to queue start */ + 8010464: e0bffa17 ldw r2,-24(fp) + 8010468: 10c00117 ldw r3,4(r2) + 801046c: e0bffa17 ldw r2,-24(fp) + 8010470: 10c00415 stw r3,16(r2) + } + pq->OSQEntries--; /* Update number of queue entries */ + 8010474: e0bffa17 ldw r2,-24(fp) + 8010478: 1080058b ldhu r2,22(r2) + 801047c: 10bfffc4 addi r2,r2,-1 + 8010480: 1007883a mov r3,r2 + 8010484: e0bffa17 ldw r2,-24(fp) + 8010488: 10c0058d sth r3,22(r2) + *pevents_rdy++ = pevent; /* ... and return available queue event */ + 801048c: e0bff117 ldw r2,-60(fp) + 8010490: 10c00104 addi r3,r2,4 + 8010494: e0fff115 stw r3,-60(fp) + 8010498: e0fffe17 ldw r3,-8(fp) + 801049c: 10c00015 stw r3,0(r2) + events_rdy = OS_TRUE; + 80104a0: 00800044 movi r2,1 + 80104a4: e0bffdc5 stb r2,-9(fp) + events_rdy_nbr++; + 80104a8: e0bffd0b ldhu r2,-12(fp) + 80104ac: 10800044 addi r2,r2,1 + 80104b0: e0bffd0d sth r2,-12(fp) + + } else { + events_stat |= OS_STAT_Q; /* Configure multi-pend for queue events */ + } + break; + 80104b4: 00000f06 br 80104f4 + events_stat |= OS_STAT_Q; /* Configure multi-pend for queue events */ + 80104b8: e0bffcc3 ldbu r2,-13(fp) + 80104bc: 10800114 ori r2,r2,4 + 80104c0: e0bffcc5 stb r2,-13(fp) + break; + 80104c4: 00000b06 br 80104f4 + 80104c8: e0bffb17 ldw r2,-20(fp) + 80104cc: e0bff815 stw r2,-32(fp) + NIOS2_WRITE_STATUS (context); + 80104d0: e0bff817 ldw r2,-32(fp) + 80104d4: 1001703a wrctl status,r2 + + case OS_EVENT_TYPE_MUTEX: + case OS_EVENT_TYPE_FLAG: + default: + OS_EXIT_CRITICAL(); + *pevents_rdy = (OS_EVENT *)0; /* NULL terminate return event array */ + 80104d8: e0bff117 ldw r2,-60(fp) + 80104dc: 10000015 stw zero,0(r2) + *perr = OS_ERR_EVENT_TYPE; + 80104e0: e0800217 ldw r2,8(fp) + 80104e4: 00c00044 movi r3,1 + 80104e8: 10c00005 stb r3,0(r2) + return (events_rdy_nbr); + 80104ec: e0bffd0b ldhu r2,-12(fp) + 80104f0: 00009d06 br 8010768 + } + pevents++; + 80104f4: e0bfff17 ldw r2,-4(fp) + 80104f8: 10800104 addi r2,r2,4 + 80104fc: e0bfff15 stw r2,-4(fp) + pevent = *pevents; + 8010500: e0bfff17 ldw r2,-4(fp) + 8010504: 10800017 ldw r2,0(r2) + 8010508: e0bffe15 stw r2,-8(fp) + while (pevent != (OS_EVENT *)0) { /* See if any events already available */ + 801050c: e0bffe17 ldw r2,-8(fp) + 8010510: 103f7d1e bne r2,zero,8010308 + } + + if ( events_rdy == OS_TRUE) { /* Return any events already available */ + 8010514: e0bffdc3 ldbu r2,-9(fp) + 8010518: 10800058 cmpnei r2,r2,1 + 801051c: 10000a1e bne r2,zero,8010548 + *pevents_rdy = (OS_EVENT *)0; /* NULL terminate return event array */ + 8010520: e0bff117 ldw r2,-60(fp) + 8010524: 10000015 stw zero,0(r2) + 8010528: e0bffb17 ldw r2,-20(fp) + 801052c: e0bff715 stw r2,-36(fp) + 8010530: e0bff717 ldw r2,-36(fp) + 8010534: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 8010538: e0800217 ldw r2,8(fp) + 801053c: 10000005 stb zero,0(r2) + return (events_rdy_nbr); + 8010540: e0bffd0b ldhu r2,-12(fp) + 8010544: 00008806 br 8010768 + } +/*$PAGE*/ + /* Otherwise, must wait until any event occurs */ + OSTCBCur->OSTCBStat |= events_stat | /* Resource not available, ... */ + 8010548: d0a05817 ldw r2,-32416(gp) + 801054c: 10800c03 ldbu r2,48(r2) + 8010550: e0fffcc3 ldbu r3,-13(fp) + 8010554: 1884b03a or r2,r3,r2 + 8010558: 1009883a mov r4,r2 + 801055c: d0a05817 ldw r2,-32416(gp) + 8010560: 00ffe004 movi r3,-128 + 8010564: 20c6b03a or r3,r4,r3 + 8010568: 10c00c05 stb r3,48(r2) + OS_STAT_MULTI; /* ... pend on multiple events */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + 801056c: d0a05817 ldw r2,-32416(gp) + 8010570: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBDly = timeout; /* Store pend timeout in TCB */ + 8010574: d0a05817 ldw r2,-32416(gp) + 8010578: e0ffef0b ldhu r3,-68(fp) + 801057c: 10c00b8d sth r3,46(r2) + OS_EventTaskWaitMulti(pevents_pend); /* Suspend task until events or timeout occurs */ + 8010580: e13ff217 ldw r4,-56(fp) + 8010584: 8010f680 call 8010f68 + 8010588: e0bffb17 ldw r2,-20(fp) + 801058c: e0bff515 stw r2,-44(fp) + 8010590: e0bff517 ldw r2,-44(fp) + 8010594: 1001703a wrctl status,r2 + + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next highest priority task ready */ + 8010598: 801166c0 call 801166c + NIOS2_READ_STATUS (context); + 801059c: 0005303a rdctl r2,status + 80105a0: e0bff615 stw r2,-40(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 80105a4: e0fff617 ldw r3,-40(fp) + 80105a8: 00bfff84 movi r2,-2 + 80105ac: 1884703a and r2,r3,r2 + 80105b0: 1001703a wrctl status,r2 + return context; + 80105b4: e0bff617 ldw r2,-40(fp) + OS_ENTER_CRITICAL(); + 80105b8: e0bffb15 stw r2,-20(fp) + + switch (OSTCBCur->OSTCBStatPend) { /* Handle event posted, aborted, or timed-out */ + 80105bc: d0a05817 ldw r2,-32416(gp) + 80105c0: 10800c43 ldbu r2,49(r2) + 80105c4: 10803fcc andi r2,r2,255 + 80105c8: 10000226 beq r2,zero,80105d4 + 80105cc: 10800098 cmpnei r2,r2,2 + 80105d0: 1000181e bne r2,zero,8010634 + case OS_STAT_PEND_OK: + case OS_STAT_PEND_ABORT: + pevent = OSTCBCur->OSTCBEventPtr; + 80105d4: d0a05817 ldw r2,-32416(gp) + 80105d8: 10800717 ldw r2,28(r2) + 80105dc: e0bffe15 stw r2,-8(fp) + if (pevent != (OS_EVENT *)0) { /* If task event ptr != NULL, ... */ + 80105e0: e0bffe17 ldw r2,-8(fp) + 80105e4: 10000b26 beq r2,zero,8010614 + *pevents_rdy++ = pevent; /* ... return available event ... */ + 80105e8: e0bff117 ldw r2,-60(fp) + 80105ec: 10c00104 addi r3,r2,4 + 80105f0: e0fff115 stw r3,-60(fp) + 80105f4: e0fffe17 ldw r3,-8(fp) + 80105f8: 10c00015 stw r3,0(r2) + *pevents_rdy = (OS_EVENT *)0; /* ... & NULL terminate return event array */ + 80105fc: e0bff117 ldw r2,-60(fp) + 8010600: 10000015 stw zero,0(r2) + events_rdy_nbr++; + 8010604: e0bffd0b ldhu r2,-12(fp) + 8010608: 10800044 addi r2,r2,1 + 801060c: e0bffd0d sth r2,-12(fp) + + } else { /* Else NO event available, handle as timeout */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_TO; + OS_EventTaskRemoveMulti(OSTCBCur, pevents_pend); + } + break; + 8010610: 00000d06 br 8010648 + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_TO; + 8010614: d0a05817 ldw r2,-32416(gp) + 8010618: 00c00044 movi r3,1 + 801061c: 10c00c45 stb r3,49(r2) + OS_EventTaskRemoveMulti(OSTCBCur, pevents_pend); + 8010620: d0a05817 ldw r2,-32416(gp) + 8010624: e17ff217 ldw r5,-56(fp) + 8010628: 1009883a mov r4,r2 + 801062c: 80111600 call 8011160 + break; + 8010630: 00000506 br 8010648 + + case OS_STAT_PEND_TO: + default: /* ... remove task from events' wait lists */ + OS_EventTaskRemoveMulti(OSTCBCur, pevents_pend); + 8010634: d0a05817 ldw r2,-32416(gp) + 8010638: e17ff217 ldw r5,-56(fp) + 801063c: 1009883a mov r4,r2 + 8010640: 80111600 call 8011160 + break; + 8010644: 0001883a nop + } + + switch (OSTCBCur->OSTCBStatPend) { + 8010648: d0a05817 ldw r2,-32416(gp) + 801064c: 10800c43 ldbu r2,49(r2) + 8010650: 10803fcc andi r2,r2,255 + 8010654: 10000326 beq r2,zero,8010664 + 8010658: 108000a0 cmpeqi r2,r2,2 + 801065c: 1000231e bne r2,zero,80106ec + 8010660: 00002a06 br 801070c + case OS_STAT_PEND_OK: + switch (pevent->OSEventType) { /* Return event's message */ + 8010664: e0bffe17 ldw r2,-8(fp) + 8010668: 10800003 ldbu r2,0(r2) + 801066c: 10803fcc andi r2,r2,255 + 8010670: 0080100e bge zero,r2,80106b4 + 8010674: 10c000d0 cmplti r3,r2,3 + 8010678: 1800071e bne r3,zero,8010698 + 801067c: 108000d8 cmpnei r2,r2,3 + 8010680: 10000c1e bne r2,zero,80106b4 +#if (OS_SEM_EN > 0) + case OS_EVENT_TYPE_SEM: + *pmsgs_rdy++ = (void *)0; /* NO message returned for semaphores */ + 8010684: e0bff017 ldw r2,-64(fp) + 8010688: 10c00104 addi r3,r2,4 + 801068c: e0fff015 stw r3,-64(fp) + 8010690: 10000015 stw zero,0(r2) + break; + 8010694: 00001206 br 80106e0 + +#if ((OS_MBOX_EN > 0) || \ + ((OS_Q_EN > 0) && (OS_MAX_QS > 0))) + case OS_EVENT_TYPE_MBOX: + case OS_EVENT_TYPE_Q: + *pmsgs_rdy++ = (void *)OSTCBCur->OSTCBMsg; /* Return received message */ + 8010698: d0e05817 ldw r3,-32416(gp) + 801069c: e0bff017 ldw r2,-64(fp) + 80106a0: 11000104 addi r4,r2,4 + 80106a4: e13ff015 stw r4,-64(fp) + 80106a8: 18c00917 ldw r3,36(r3) + 80106ac: 10c00015 stw r3,0(r2) + break; + 80106b0: 00000b06 br 80106e0 + 80106b4: e0bffb17 ldw r2,-20(fp) + 80106b8: e0bff415 stw r2,-48(fp) + NIOS2_WRITE_STATUS (context); + 80106bc: e0bff417 ldw r2,-48(fp) + 80106c0: 1001703a wrctl status,r2 + + case OS_EVENT_TYPE_MUTEX: + case OS_EVENT_TYPE_FLAG: + default: + OS_EXIT_CRITICAL(); + *pevents_rdy = (OS_EVENT *)0; /* NULL terminate return event array */ + 80106c4: e0bff117 ldw r2,-60(fp) + 80106c8: 10000015 stw zero,0(r2) + *perr = OS_ERR_EVENT_TYPE; + 80106cc: e0800217 ldw r2,8(fp) + 80106d0: 00c00044 movi r3,1 + 80106d4: 10c00005 stb r3,0(r2) + return (events_rdy_nbr); + 80106d8: e0bffd0b ldhu r2,-12(fp) + 80106dc: 00002206 br 8010768 + } + *perr = OS_ERR_NONE; + 80106e0: e0800217 ldw r2,8(fp) + 80106e4: 10000005 stb zero,0(r2) + break; + 80106e8: 00001006 br 801072c + + case OS_STAT_PEND_ABORT: + *pmsgs_rdy++ = (void *)0; /* NO message returned for abort */ + 80106ec: e0bff017 ldw r2,-64(fp) + 80106f0: 10c00104 addi r3,r2,4 + 80106f4: e0fff015 stw r3,-64(fp) + 80106f8: 10000015 stw zero,0(r2) + *perr = OS_ERR_PEND_ABORT; /* Indicate that event aborted */ + 80106fc: e0800217 ldw r2,8(fp) + 8010700: 00c00384 movi r3,14 + 8010704: 10c00005 stb r3,0(r2) + break; + 8010708: 00000806 br 801072c + + case OS_STAT_PEND_TO: + default: + *pmsgs_rdy++ = (void *)0; /* NO message returned for timeout */ + 801070c: e0bff017 ldw r2,-64(fp) + 8010710: 10c00104 addi r3,r2,4 + 8010714: e0fff015 stw r3,-64(fp) + 8010718: 10000015 stw zero,0(r2) + *perr = OS_ERR_TIMEOUT; /* Indicate that events timed out */ + 801071c: e0800217 ldw r2,8(fp) + 8010720: 00c00284 movi r3,10 + 8010724: 10c00005 stb r3,0(r2) + break; + 8010728: 0001883a nop + } + + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Set task status to ready */ + 801072c: d0a05817 ldw r2,-32416(gp) + 8010730: 10000c05 stb zero,48(r2) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + 8010734: d0a05817 ldw r2,-32416(gp) + 8010738: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; /* Clear event pointers */ + 801073c: d0a05817 ldw r2,-32416(gp) + 8010740: 10000715 stw zero,28(r2) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0; + 8010744: d0a05817 ldw r2,-32416(gp) + 8010748: 10000815 stw zero,32(r2) + OSTCBCur->OSTCBMsg = (void *)0; /* Clear task message */ + 801074c: d0a05817 ldw r2,-32416(gp) + 8010750: 10000915 stw zero,36(r2) + 8010754: e0bffb17 ldw r2,-20(fp) + 8010758: e0bff315 stw r2,-52(fp) + 801075c: e0bff317 ldw r2,-52(fp) + 8010760: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + + return (events_rdy_nbr); + 8010764: e0bffd0b ldhu r2,-12(fp) +} + 8010768: e037883a mov sp,fp + 801076c: dfc00117 ldw ra,4(sp) + 8010770: df000017 ldw fp,0(sp) + 8010774: dec00204 addi sp,sp,8 + 8010778: f800283a ret + +0801077c : +* Returns : none +********************************************************************************************************* +*/ + +void OSInit (void) +{ + 801077c: defffe04 addi sp,sp,-8 + 8010780: dfc00115 stw ra,4(sp) + 8010784: df000015 stw fp,0(sp) + 8010788: d839883a mov fp,sp + OSInitHookBegin(); /* Call port specific initialization code */ + 801078c: 80386580 call 8038658 + + OS_InitMisc(); /* Initialize miscellaneous variables */ + 8010790: 80113a00 call 80113a0 + + OS_InitRdyList(); /* Initialize the Ready List */ + 8010794: 80113dc0 call 80113dc + + OS_InitTCBList(); /* Initialize the free list of OS_TCBs */ + 8010798: 80114cc0 call 80114cc + + OS_InitEventList(); /* Initialize the free list of OS_EVENTs */ + 801079c: 80112c00 call 80112c0 + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) + OS_FlagInit(); /* Initialize the event flag structures */ + 80107a0: 8012ed80 call 8012ed8 +#endif + +#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0) + OS_MemInit(); /* Initialize the memory manager */ + 80107a4: 80136580 call 8013658 +#endif + +#if (OS_Q_EN > 0) && (OS_MAX_QS > 0) + OS_QInit(); /* Initialize the message queue structures */ + 80107a8: 801562c0 call 801562c +#endif + + OS_InitTaskIdle(); /* Create the Idle Task */ + 80107ac: 80114480 call 8011448 + +#if OS_TMR_EN > 0 + OSTmr_Init(); /* Initialize the Timer Manager */ +#endif + + OSInitHookEnd(); /* Call port specific init. code */ + 80107b0: 80386780 call 8038678 + +#if OS_DEBUG_EN > 0 + OSDebugInit(); +#endif +} + 80107b4: 0001883a nop + 80107b8: e037883a mov sp,fp + 80107bc: dfc00117 ldw ra,4(sp) + 80107c0: df000017 ldw fp,0(sp) + 80107c4: dec00204 addi sp,sp,8 + 80107c8: f800283a ret + +080107cc : +* 5) You are allowed to nest interrupts up to 255 levels deep. +********************************************************************************************************* +*/ + +void OSIntEnter (void) +{ + 80107cc: deffff04 addi sp,sp,-4 + 80107d0: df000015 stw fp,0(sp) + 80107d4: d839883a mov fp,sp + if (OSRunning == OS_TRUE) { + 80107d8: d0a04b43 ldbu r2,-32467(gp) + 80107dc: 10803fcc andi r2,r2,255 + 80107e0: 10800058 cmpnei r2,r2,1 + 80107e4: 1000071e bne r2,zero,8010804 + if (OSIntNesting < 255u) { + 80107e8: d0a05703 ldbu r2,-32420(gp) + 80107ec: 10803fcc andi r2,r2,255 + 80107f0: 10803fe0 cmpeqi r2,r2,255 + 80107f4: 1000031e bne r2,zero,8010804 + OSIntNesting++; /* Increment ISR nesting level */ + 80107f8: d0a05703 ldbu r2,-32420(gp) + 80107fc: 10800044 addi r2,r2,1 + 8010800: d0a05705 stb r2,-32420(gp) + } + } +} + 8010804: 0001883a nop + 8010808: e037883a mov sp,fp + 801080c: df000017 ldw fp,0(sp) + 8010810: dec00104 addi sp,sp,4 + 8010814: f800283a ret + +08010818 : +* 2) Rescheduling is prevented when the scheduler is locked (see OS_SchedLock()) +********************************************************************************************************* +*/ + +void OSIntExit (void) +{ + 8010818: defffb04 addi sp,sp,-20 + 801081c: dfc00415 stw ra,16(sp) + 8010820: df000315 stw fp,12(sp) + 8010824: df000304 addi fp,sp,12 +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8010828: e03fff15 stw zero,-4(fp) +#endif + + + + if (OSRunning == OS_TRUE) { + 801082c: d0a04b43 ldbu r2,-32467(gp) + 8010830: 10803fcc andi r2,r2,255 + 8010834: 10800058 cmpnei r2,r2,1 + 8010838: 10002d1e bne r2,zero,80108f0 + NIOS2_READ_STATUS (context); + 801083c: 0005303a rdctl r2,status + 8010840: e0bffe15 stw r2,-8(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8010844: e0fffe17 ldw r3,-8(fp) + 8010848: 00bfff84 movi r2,-2 + 801084c: 1884703a and r2,r3,r2 + 8010850: 1001703a wrctl status,r2 + return context; + 8010854: e0bffe17 ldw r2,-8(fp) + OS_ENTER_CRITICAL(); + 8010858: e0bfff15 stw r2,-4(fp) + if (OSIntNesting > 0) { /* Prevent OSIntNesting from wrapping */ + 801085c: d0a05703 ldbu r2,-32420(gp) + 8010860: 10803fcc andi r2,r2,255 + 8010864: 10000326 beq r2,zero,8010874 + OSIntNesting--; + 8010868: d0a05703 ldbu r2,-32420(gp) + 801086c: 10bfffc4 addi r2,r2,-1 + 8010870: d0a05705 stb r2,-32420(gp) + } + if (OSIntNesting == 0) { /* Reschedule only if all ISRs complete ... */ + 8010874: d0a05703 ldbu r2,-32420(gp) + 8010878: 10803fcc andi r2,r2,255 + 801087c: 1000181e bne r2,zero,80108e0 + if (OSLockNesting == 0) { /* ... and not locked. */ + 8010880: d0a04b03 ldbu r2,-32468(gp) + 8010884: 10803fcc andi r2,r2,255 + 8010888: 1000151e bne r2,zero,80108e0 + OS_SchedNew(); + 801088c: 80117340 call 8011734 + if (OSPrioHighRdy != OSPrioCur) { /* No Ctx Sw if current task is highest rdy */ + 8010890: d0e04d03 ldbu r3,-32460(gp) + 8010894: d0a04d43 ldbu r2,-32459(gp) + 8010898: 18c03fcc andi r3,r3,255 + 801089c: 10803fcc andi r2,r2,255 + 80108a0: 18800f26 beq r3,r2,80108e0 + OSTCBHighRdy = OSTCBPrioTbl[OSPrioHighRdy]; + 80108a4: d0a04d03 ldbu r2,-32460(gp) + 80108a8: 10803fcc andi r2,r2,255 + 80108ac: 100690ba slli r3,r2,2 + 80108b0: 008201b4 movhi r2,2054 + 80108b4: 1885883a add r2,r3,r2 + 80108b8: 10b55d17 ldw r2,-10892(r2) + 80108bc: d0a05315 stw r2,-32436(gp) +#if OS_TASK_PROFILE_EN > 0 + OSTCBHighRdy->OSTCBCtxSwCtr++; /* Inc. # of context switches to this task */ + 80108c0: d0a05317 ldw r2,-32436(gp) + 80108c4: 10c00e17 ldw r3,56(r2) + 80108c8: 18c00044 addi r3,r3,1 + 80108cc: 10c00e15 stw r3,56(r2) +#endif + OSCtxSwCtr++; /* Keep track of the number of ctx switches */ + 80108d0: d0a04f17 ldw r2,-32452(gp) + 80108d4: 10800044 addi r2,r2,1 + 80108d8: d0a04f15 stw r2,-32452(gp) + OSIntCtxSw(); /* Perform interrupt level ctx switch */ + 80108dc: 80383880 call 8038388 + 80108e0: e0bfff17 ldw r2,-4(fp) + 80108e4: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context); + 80108e8: e0bffd17 ldw r2,-12(fp) + 80108ec: 1001703a wrctl status,r2 + } + } + } + OS_EXIT_CRITICAL(); + } +} + 80108f0: 0001883a nop + 80108f4: e037883a mov sp,fp + 80108f8: dfc00117 ldw ra,4(sp) + 80108fc: df000017 ldw fp,0(sp) + 8010900: dec00204 addi sp,sp,8 + 8010904: f800283a ret + +08010908 : +********************************************************************************************************* +*/ + +#if OS_SCHED_LOCK_EN > 0 +void OSSchedLock (void) +{ + 8010908: defffc04 addi sp,sp,-16 + 801090c: df000315 stw fp,12(sp) + 8010910: df000304 addi fp,sp,12 +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8010914: e03fff15 stw zero,-4(fp) +#endif + + + + if (OSRunning == OS_TRUE) { /* Make sure multitasking is running */ + 8010918: d0a04b43 ldbu r2,-32467(gp) + 801091c: 10803fcc andi r2,r2,255 + 8010920: 10800058 cmpnei r2,r2,1 + 8010924: 1000161e bne r2,zero,8010980 + NIOS2_READ_STATUS (context); + 8010928: 0005303a rdctl r2,status + 801092c: e0bffe15 stw r2,-8(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8010930: e0fffe17 ldw r3,-8(fp) + 8010934: 00bfff84 movi r2,-2 + 8010938: 1884703a and r2,r3,r2 + 801093c: 1001703a wrctl status,r2 + return context; + 8010940: e0bffe17 ldw r2,-8(fp) + OS_ENTER_CRITICAL(); + 8010944: e0bfff15 stw r2,-4(fp) + if (OSIntNesting == 0) { /* Can't call from an ISR */ + 8010948: d0a05703 ldbu r2,-32420(gp) + 801094c: 10803fcc andi r2,r2,255 + 8010950: 1000071e bne r2,zero,8010970 + if (OSLockNesting < 255u) { /* Prevent OSLockNesting from wrapping back to 0 */ + 8010954: d0a04b03 ldbu r2,-32468(gp) + 8010958: 10803fcc andi r2,r2,255 + 801095c: 10803fe0 cmpeqi r2,r2,255 + 8010960: 1000031e bne r2,zero,8010970 + OSLockNesting++; /* Increment lock nesting level */ + 8010964: d0a04b03 ldbu r2,-32468(gp) + 8010968: 10800044 addi r2,r2,1 + 801096c: d0a04b05 stb r2,-32468(gp) + 8010970: e0bfff17 ldw r2,-4(fp) + 8010974: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context); + 8010978: e0bffd17 ldw r2,-12(fp) + 801097c: 1001703a wrctl status,r2 + } + } + OS_EXIT_CRITICAL(); + } +} + 8010980: 0001883a nop + 8010984: e037883a mov sp,fp + 8010988: df000017 ldw fp,0(sp) + 801098c: dec00104 addi sp,sp,4 + 8010990: f800283a ret + +08010994 : +********************************************************************************************************* +*/ + +#if OS_SCHED_LOCK_EN > 0 +void OSSchedUnlock (void) +{ + 8010994: defff804 addi sp,sp,-32 + 8010998: dfc00715 stw ra,28(sp) + 801099c: df000615 stw fp,24(sp) + 80109a0: df000604 addi fp,sp,24 +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 80109a4: e03fff15 stw zero,-4(fp) +#endif + + + + if (OSRunning == OS_TRUE) { /* Make sure multitasking is running */ + 80109a8: d0a04b43 ldbu r2,-32467(gp) + 80109ac: 10803fcc andi r2,r2,255 + 80109b0: 10800058 cmpnei r2,r2,1 + 80109b4: 1000281e bne r2,zero,8010a58 + NIOS2_READ_STATUS (context); + 80109b8: 0005303a rdctl r2,status + 80109bc: e0bffe15 stw r2,-8(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 80109c0: e0fffe17 ldw r3,-8(fp) + 80109c4: 00bfff84 movi r2,-2 + 80109c8: 1884703a and r2,r3,r2 + 80109cc: 1001703a wrctl status,r2 + return context; + 80109d0: e0bffe17 ldw r2,-8(fp) + OS_ENTER_CRITICAL(); + 80109d4: e0bfff15 stw r2,-4(fp) + if (OSLockNesting > 0) { /* Do not decrement if already 0 */ + 80109d8: d0a04b03 ldbu r2,-32468(gp) + 80109dc: 10803fcc andi r2,r2,255 + 80109e0: 10001926 beq r2,zero,8010a48 + OSLockNesting--; /* Decrement lock nesting level */ + 80109e4: d0a04b03 ldbu r2,-32468(gp) + 80109e8: 10bfffc4 addi r2,r2,-1 + 80109ec: d0a04b05 stb r2,-32468(gp) + if (OSLockNesting == 0) { /* See if scheduler is enabled and ... */ + 80109f0: d0a04b03 ldbu r2,-32468(gp) + 80109f4: 10803fcc andi r2,r2,255 + 80109f8: 10000e1e bne r2,zero,8010a34 + if (OSIntNesting == 0) { /* ... not in an ISR */ + 80109fc: d0a05703 ldbu r2,-32420(gp) + 8010a00: 10803fcc andi r2,r2,255 + 8010a04: 1000061e bne r2,zero,8010a20 + 8010a08: e0bfff17 ldw r2,-4(fp) + 8010a0c: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context); + 8010a10: e0bffd17 ldw r2,-12(fp) + 8010a14: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* See if a HPT is ready */ + 8010a18: 801166c0 call 801166c + } + } else { + OS_EXIT_CRITICAL(); + } + } +} + 8010a1c: 00000e06 br 8010a58 + 8010a20: e0bfff17 ldw r2,-4(fp) + 8010a24: e0bffc15 stw r2,-16(fp) + 8010a28: e0bffc17 ldw r2,-16(fp) + 8010a2c: 1001703a wrctl status,r2 + 8010a30: 00000906 br 8010a58 + 8010a34: e0bfff17 ldw r2,-4(fp) + 8010a38: e0bffb15 stw r2,-20(fp) + 8010a3c: e0bffb17 ldw r2,-20(fp) + 8010a40: 1001703a wrctl status,r2 + 8010a44: 00000406 br 8010a58 + 8010a48: e0bfff17 ldw r2,-4(fp) + 8010a4c: e0bffa15 stw r2,-24(fp) + 8010a50: e0bffa17 ldw r2,-24(fp) + 8010a54: 1001703a wrctl status,r2 + 8010a58: 0001883a nop + 8010a5c: e037883a mov sp,fp + 8010a60: dfc00117 ldw ra,4(sp) + 8010a64: df000017 ldw fp,0(sp) + 8010a68: dec00204 addi sp,sp,8 + 8010a6c: f800283a ret + +08010a70 : +* d_ Execute the task. +********************************************************************************************************* +*/ + +void OSStart (void) +{ + 8010a70: defffe04 addi sp,sp,-8 + 8010a74: dfc00115 stw ra,4(sp) + 8010a78: df000015 stw fp,0(sp) + 8010a7c: d839883a mov fp,sp + if (OSRunning == OS_FALSE) { + 8010a80: d0a04b43 ldbu r2,-32467(gp) + 8010a84: 10803fcc andi r2,r2,255 + 8010a88: 10000d1e bne r2,zero,8010ac0 + OS_SchedNew(); /* Find highest priority's task priority number */ + 8010a8c: 80117340 call 8011734 + OSPrioCur = OSPrioHighRdy; + 8010a90: d0a04d03 ldbu r2,-32460(gp) + 8010a94: d0a04d45 stb r2,-32459(gp) + OSTCBHighRdy = OSTCBPrioTbl[OSPrioHighRdy]; /* Point to highest priority task ready to run */ + 8010a98: d0a04d03 ldbu r2,-32460(gp) + 8010a9c: 10803fcc andi r2,r2,255 + 8010aa0: 100690ba slli r3,r2,2 + 8010aa4: 008201b4 movhi r2,2054 + 8010aa8: 1885883a add r2,r3,r2 + 8010aac: 10b55d17 ldw r2,-10892(r2) + 8010ab0: d0a05315 stw r2,-32436(gp) + OSTCBCur = OSTCBHighRdy; + 8010ab4: d0a05317 ldw r2,-32436(gp) + 8010ab8: d0a05815 stw r2,-32416(gp) + OSStartHighRdy(); /* Execute target specific code to start task */ + 8010abc: 80384140 call 8038414 + } +} + 8010ac0: 0001883a nop + 8010ac4: e037883a mov sp,fp + 8010ac8: dfc00117 ldw ra,4(sp) + 8010acc: df000017 ldw fp,0(sp) + 8010ad0: dec00204 addi sp,sp,8 + 8010ad4: f800283a ret + +08010ad8 : +* Returns : none +********************************************************************************************************* +*/ + +void OSTimeTick (void) +{ + 8010ad8: defff804 addi sp,sp,-32 + 8010adc: dfc00715 stw ra,28(sp) + 8010ae0: df000615 stw fp,24(sp) + 8010ae4: df000604 addi fp,sp,24 + OS_TCB *ptcb; +#if OS_TICK_STEP_EN > 0 + BOOLEAN step; +#endif +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8010ae8: e03ffe15 stw zero,-8(fp) +#endif + + + +#if OS_TIME_TICK_HOOK_EN > 0 + OSTimeTickHook(); /* Call user definable hook */ + 8010aec: 803862c0 call 803862c + NIOS2_READ_STATUS (context); + 8010af0: 0005303a rdctl r2,status + 8010af4: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8010af8: e0fffc17 ldw r3,-16(fp) + 8010afc: 00bfff84 movi r2,-2 + 8010b00: 1884703a and r2,r3,r2 + 8010b04: 1001703a wrctl status,r2 + return context; + 8010b08: e0bffc17 ldw r2,-16(fp) +#endif +#if OS_TIME_GET_SET_EN > 0 + OS_ENTER_CRITICAL(); /* Update the 32-bit tick counter */ + 8010b0c: e0bffe15 stw r2,-8(fp) + OSTime++; + 8010b10: d0a05917 ldw r2,-32412(gp) + 8010b14: 10800044 addi r2,r2,1 + 8010b18: d0a05915 stw r2,-32412(gp) + 8010b1c: e0bffe17 ldw r2,-8(fp) + 8010b20: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context); + 8010b24: e0bffd17 ldw r2,-12(fp) + 8010b28: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); +#endif + if (OSRunning == OS_TRUE) { + 8010b2c: d0a04b43 ldbu r2,-32467(gp) + 8010b30: 10803fcc andi r2,r2,255 + 8010b34: 10800058 cmpnei r2,r2,1 + 8010b38: 1000511e bne r2,zero,8010c80 + } + if (step == OS_FALSE) { /* Return if waiting for step command */ + return; + } +#endif + ptcb = OSTCBList; /* Point at first TCB in TCB list */ + 8010b3c: d0a04e17 ldw r2,-32456(gp) + 8010b40: e0bfff15 stw r2,-4(fp) + while (ptcb->OSTCBPrio != OS_TASK_IDLE_PRIO) { /* Go through all TCBs in TCB list */ + 8010b44: 00004906 br 8010c6c + NIOS2_READ_STATUS (context); + 8010b48: 0005303a rdctl r2,status + 8010b4c: e0bffb15 stw r2,-20(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8010b50: e0fffb17 ldw r3,-20(fp) + 8010b54: 00bfff84 movi r2,-2 + 8010b58: 1884703a and r2,r3,r2 + 8010b5c: 1001703a wrctl status,r2 + return context; + 8010b60: e0bffb17 ldw r2,-20(fp) + OS_ENTER_CRITICAL(); + 8010b64: e0bffe15 stw r2,-8(fp) + if (ptcb->OSTCBDly != 0) { /* No, Delayed or waiting for event with TO */ + 8010b68: e0bfff17 ldw r2,-4(fp) + 8010b6c: 10800b8b ldhu r2,46(r2) + 8010b70: 10bfffcc andi r2,r2,65535 + 8010b74: 10003626 beq r2,zero,8010c50 + if (--ptcb->OSTCBDly == 0) { /* Decrement nbr of ticks to end of delay */ + 8010b78: e0bfff17 ldw r2,-4(fp) + 8010b7c: 10800b8b ldhu r2,46(r2) + 8010b80: 10bfffc4 addi r2,r2,-1 + 8010b84: 1007883a mov r3,r2 + 8010b88: e0bfff17 ldw r2,-4(fp) + 8010b8c: 10c00b8d sth r3,46(r2) + 8010b90: e0bfff17 ldw r2,-4(fp) + 8010b94: 10800b8b ldhu r2,46(r2) + 8010b98: 10bfffcc andi r2,r2,65535 + 8010b9c: 10002c1e bne r2,zero,8010c50 + /* Check for timeout */ + if ((ptcb->OSTCBStat & OS_STAT_PEND_ANY) != OS_STAT_RDY) { + 8010ba0: e0bfff17 ldw r2,-4(fp) + 8010ba4: 10800c03 ldbu r2,48(r2) + 8010ba8: 10803fcc andi r2,r2,255 + 8010bac: 10800dcc andi r2,r2,55 + 8010bb0: 10000b26 beq r2,zero,8010be0 + ptcb->OSTCBStat &= ~(INT8U)OS_STAT_PEND_ANY; /* Yes, Clear status flag */ + 8010bb4: e0bfff17 ldw r2,-4(fp) + 8010bb8: 10c00c03 ldbu r3,48(r2) + 8010bbc: 00bff204 movi r2,-56 + 8010bc0: 1884703a and r2,r3,r2 + 8010bc4: 1007883a mov r3,r2 + 8010bc8: e0bfff17 ldw r2,-4(fp) + 8010bcc: 10c00c05 stb r3,48(r2) + ptcb->OSTCBStatPend = OS_STAT_PEND_TO; /* Indicate PEND timeout */ + 8010bd0: e0bfff17 ldw r2,-4(fp) + 8010bd4: 00c00044 movi r3,1 + 8010bd8: 10c00c45 stb r3,49(r2) + 8010bdc: 00000206 br 8010be8 + } else { + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; + 8010be0: e0bfff17 ldw r2,-4(fp) + 8010be4: 10000c45 stb zero,49(r2) + } + + if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) == OS_STAT_RDY) { /* Is task suspended? */ + 8010be8: e0bfff17 ldw r2,-4(fp) + 8010bec: 10800c03 ldbu r2,48(r2) + 8010bf0: 10803fcc andi r2,r2,255 + 8010bf4: 1080020c andi r2,r2,8 + 8010bf8: 1000151e bne r2,zero,8010c50 + OSRdyGrp |= ptcb->OSTCBBitY; /* No, Make ready */ + 8010bfc: e0bfff17 ldw r2,-4(fp) + 8010c00: 10c00d83 ldbu r3,54(r2) + 8010c04: d0a05503 ldbu r2,-32428(gp) + 8010c08: 1884b03a or r2,r3,r2 + 8010c0c: d0a05505 stb r2,-32428(gp) + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + 8010c10: e0bfff17 ldw r2,-4(fp) + 8010c14: 10800d03 ldbu r2,52(r2) + 8010c18: 10c03fcc andi r3,r2,255 + 8010c1c: d0a05544 addi r2,gp,-32427 + 8010c20: 1885883a add r2,r3,r2 + 8010c24: 11000003 ldbu r4,0(r2) + 8010c28: e0bfff17 ldw r2,-4(fp) + 8010c2c: 10800d43 ldbu r2,53(r2) + 8010c30: e0ffff17 ldw r3,-4(fp) + 8010c34: 18c00d03 ldbu r3,52(r3) + 8010c38: 18c03fcc andi r3,r3,255 + 8010c3c: 2084b03a or r2,r4,r2 + 8010c40: 1009883a mov r4,r2 + 8010c44: d0a05544 addi r2,gp,-32427 + 8010c48: 1885883a add r2,r3,r2 + 8010c4c: 11000005 stb r4,0(r2) + } + } + } + ptcb = ptcb->OSTCBNext; /* Point at next TCB in TCB list */ + 8010c50: e0bfff17 ldw r2,-4(fp) + 8010c54: 10800517 ldw r2,20(r2) + 8010c58: e0bfff15 stw r2,-4(fp) + 8010c5c: e0bffe17 ldw r2,-8(fp) + 8010c60: e0bffa15 stw r2,-24(fp) + NIOS2_WRITE_STATUS (context); + 8010c64: e0bffa17 ldw r2,-24(fp) + 8010c68: 1001703a wrctl status,r2 + while (ptcb->OSTCBPrio != OS_TASK_IDLE_PRIO) { /* Go through all TCBs in TCB list */ + 8010c6c: e0bfff17 ldw r2,-4(fp) + 8010c70: 10800c83 ldbu r2,50(r2) + 8010c74: 10803fcc andi r2,r2,255 + 8010c78: 10800518 cmpnei r2,r2,20 + 8010c7c: 103fb21e bne r2,zero,8010b48 + OS_EXIT_CRITICAL(); + } + } +} + 8010c80: 0001883a nop + 8010c84: e037883a mov sp,fp + 8010c88: dfc00117 ldw ra,4(sp) + 8010c8c: df000017 ldw fp,0(sp) + 8010c90: dec00204 addi sp,sp,8 + 8010c94: f800283a ret + +08010c98 : +* Returns : the version number of uC/OS-II multiplied by 100. +********************************************************************************************************* +*/ + +INT16U OSVersion (void) +{ + 8010c98: deffff04 addi sp,sp,-4 + 8010c9c: df000015 stw fp,0(sp) + 8010ca0: d839883a mov fp,sp + return (OS_VERSION); + 8010ca4: 00804784 movi r2,286 +} + 8010ca8: e037883a mov sp,fp + 8010cac: df000017 ldw fp,0(sp) + 8010cb0: dec00104 addi sp,sp,4 + 8010cb4: f800283a ret + +08010cb8 : +********************************************************************************************************* +*/ + +#if OS_TASK_DEL_EN > 0 +void OS_Dummy (void) +{ + 8010cb8: deffff04 addi sp,sp,-4 + 8010cbc: df000015 stw fp,0(sp) + 8010cc0: d839883a mov fp,sp +} + 8010cc4: 0001883a nop + 8010cc8: e037883a mov sp,fp + 8010ccc: df000017 ldw fp,0(sp) + 8010cd0: dec00104 addi sp,sp,4 + 8010cd4: f800283a ret + +08010cd8 : +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if (OS_EVENT_EN) +INT8U OS_EventTaskRdy (OS_EVENT *pevent, void *pmsg, INT8U msk, INT8U pend_stat) +{ + 8010cd8: defff804 addi sp,sp,-32 + 8010cdc: dfc00715 stw ra,28(sp) + 8010ce0: df000615 stw fp,24(sp) + 8010ce4: df000604 addi fp,sp,24 + 8010ce8: e13ffd15 stw r4,-12(fp) + 8010cec: e17ffc15 stw r5,-16(fp) + 8010cf0: 3005883a mov r2,r6 + 8010cf4: 3807883a mov r3,r7 + 8010cf8: e0bffb05 stb r2,-20(fp) + 8010cfc: 1805883a mov r2,r3 + 8010d00: e0bffa05 stb r2,-24(fp) + INT16U *ptbl; +#endif + + +#if OS_LOWEST_PRIO <= 63 + y = OSUnMapTbl[pevent->OSEventGrp]; /* Find HPT waiting for message */ + 8010d04: e0bffd17 ldw r2,-12(fp) + 8010d08: 10800283 ldbu r2,10(r2) + 8010d0c: 10c03fcc andi r3,r2,255 + 8010d10: 00820134 movhi r2,2052 + 8010d14: 1885883a add r2,r3,r2 + 8010d18: 109dcd03 ldbu r2,30516(r2) + 8010d1c: e0bfffc5 stb r2,-1(fp) + x = OSUnMapTbl[pevent->OSEventTbl[y]]; + 8010d20: e0bfffc3 ldbu r2,-1(fp) + 8010d24: e0fffd17 ldw r3,-12(fp) + 8010d28: 1885883a add r2,r3,r2 + 8010d2c: 108002c3 ldbu r2,11(r2) + 8010d30: 10c03fcc andi r3,r2,255 + 8010d34: 00820134 movhi r2,2052 + 8010d38: 1885883a add r2,r3,r2 + 8010d3c: 109dcd03 ldbu r2,30516(r2) + 8010d40: e0bfff85 stb r2,-2(fp) + prio = (INT8U)((y << 3) + x); /* Find priority of task getting the msg */ + 8010d44: e0bfffc3 ldbu r2,-1(fp) + 8010d48: 100490fa slli r2,r2,3 + 8010d4c: 1007883a mov r3,r2 + 8010d50: e0bfff83 ldbu r2,-2(fp) + 8010d54: 10c5883a add r2,r2,r3 + 8010d58: e0bfff45 stb r2,-3(fp) + x = OSUnMapTbl[(*ptbl >> 8) & 0xFF] + 8; + } + prio = (INT8U)((y << 4) + x); /* Find priority of task getting the msg */ +#endif + + ptcb = OSTCBPrioTbl[prio]; /* Point to this task's OS_TCB */ + 8010d5c: e0bfff43 ldbu r2,-3(fp) + 8010d60: 100690ba slli r3,r2,2 + 8010d64: 008201b4 movhi r2,2054 + 8010d68: 1885883a add r2,r3,r2 + 8010d6c: 10b55d17 ldw r2,-10892(r2) + 8010d70: e0bffe15 stw r2,-8(fp) + ptcb->OSTCBDly = 0; /* Prevent OSTimeTick() from readying task */ + 8010d74: e0bffe17 ldw r2,-8(fp) + 8010d78: 10000b8d sth zero,46(r2) +#if ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) || (OS_MBOX_EN > 0) + ptcb->OSTCBMsg = pmsg; /* Send message directly to waiting task */ + 8010d7c: e0bffe17 ldw r2,-8(fp) + 8010d80: e0fffc17 ldw r3,-16(fp) + 8010d84: 10c00915 stw r3,36(r2) +#else + pmsg = pmsg; /* Prevent compiler warning if not used */ +#endif + ptcb->OSTCBStat &= ~msk; /* Clear bit associated with event type */ + 8010d88: e0bffe17 ldw r2,-8(fp) + 8010d8c: 10800c03 ldbu r2,48(r2) + 8010d90: 1007883a mov r3,r2 + 8010d94: e0bffb03 ldbu r2,-20(fp) + 8010d98: 0084303a nor r2,zero,r2 + 8010d9c: 1884703a and r2,r3,r2 + 8010da0: 1007883a mov r3,r2 + 8010da4: e0bffe17 ldw r2,-8(fp) + 8010da8: 10c00c05 stb r3,48(r2) + ptcb->OSTCBStatPend = pend_stat; /* Set pend status of post or abort */ + 8010dac: e0bffe17 ldw r2,-8(fp) + 8010db0: e0fffa03 ldbu r3,-24(fp) + 8010db4: 10c00c45 stb r3,49(r2) + /* See if task is ready (could be susp'd) */ + if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) == OS_STAT_RDY) { + 8010db8: e0bffe17 ldw r2,-8(fp) + 8010dbc: 10800c03 ldbu r2,48(r2) + 8010dc0: 10803fcc andi r2,r2,255 + 8010dc4: 1080020c andi r2,r2,8 + 8010dc8: 1000111e bne r2,zero,8010e10 + OSRdyGrp |= ptcb->OSTCBBitY; /* Put task in the ready to run list */ + 8010dcc: e0bffe17 ldw r2,-8(fp) + 8010dd0: 10c00d83 ldbu r3,54(r2) + 8010dd4: d0a05503 ldbu r2,-32428(gp) + 8010dd8: 1884b03a or r2,r3,r2 + 8010ddc: d0a05505 stb r2,-32428(gp) + OSRdyTbl[y] |= ptcb->OSTCBBitX; + 8010de0: e0ffffc3 ldbu r3,-1(fp) + 8010de4: d0a05544 addi r2,gp,-32427 + 8010de8: 1885883a add r2,r3,r2 + 8010dec: 11000003 ldbu r4,0(r2) + 8010df0: e0bffe17 ldw r2,-8(fp) + 8010df4: 10800d43 ldbu r2,53(r2) + 8010df8: e0ffffc3 ldbu r3,-1(fp) + 8010dfc: 2084b03a or r2,r4,r2 + 8010e00: 1009883a mov r4,r2 + 8010e04: d0a05544 addi r2,gp,-32427 + 8010e08: 1885883a add r2,r3,r2 + 8010e0c: 11000005 stb r4,0(r2) + } + + OS_EventTaskRemove(ptcb, pevent); /* Remove this task from event wait list */ + 8010e10: e17ffd17 ldw r5,-12(fp) + 8010e14: e13ffe17 ldw r4,-8(fp) + 8010e18: 80110b00 call 80110b0 +#if (OS_EVENT_MULTI_EN > 0) + if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) { /* Remove this task from events' wait lists */ + 8010e1c: e0bffe17 ldw r2,-8(fp) + 8010e20: 10800817 ldw r2,32(r2) + 8010e24: 10000826 beq r2,zero,8010e48 + OS_EventTaskRemoveMulti(ptcb, ptcb->OSTCBEventMultiPtr); + 8010e28: e0bffe17 ldw r2,-8(fp) + 8010e2c: 10800817 ldw r2,32(r2) + 8010e30: 100b883a mov r5,r2 + 8010e34: e13ffe17 ldw r4,-8(fp) + 8010e38: 80111600 call 8011160 + ptcb->OSTCBEventPtr = (OS_EVENT *)pevent;/* Return event as first multi-pend event ready*/ + 8010e3c: e0bffe17 ldw r2,-8(fp) + 8010e40: e0fffd17 ldw r3,-12(fp) + 8010e44: 10c00715 stw r3,28(r2) + } +#endif + + return (prio); + 8010e48: e0bfff43 ldbu r2,-3(fp) +} + 8010e4c: e037883a mov sp,fp + 8010e50: dfc00117 ldw ra,4(sp) + 8010e54: df000017 ldw fp,0(sp) + 8010e58: dec00204 addi sp,sp,8 + 8010e5c: f800283a ret + +08010e60 : +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if (OS_EVENT_EN) +void OS_EventTaskWait (OS_EVENT *pevent) +{ + 8010e60: defffd04 addi sp,sp,-12 + 8010e64: df000215 stw fp,8(sp) + 8010e68: df000204 addi fp,sp,8 + 8010e6c: e13ffe15 stw r4,-8(fp) + INT8U y; + + + OSTCBCur->OSTCBEventPtr = pevent; /* Store ptr to ECB in TCB */ + 8010e70: d0a05817 ldw r2,-32416(gp) + 8010e74: e0fffe17 ldw r3,-8(fp) + 8010e78: 10c00715 stw r3,28(r2) + + pevent->OSEventTbl[OSTCBCur->OSTCBY] |= OSTCBCur->OSTCBBitX; /* Put task in waiting list */ + 8010e7c: d0a05817 ldw r2,-32416(gp) + 8010e80: 10800d03 ldbu r2,52(r2) + 8010e84: 10803fcc andi r2,r2,255 + 8010e88: e0fffe17 ldw r3,-8(fp) + 8010e8c: 1885883a add r2,r3,r2 + 8010e90: 110002c3 ldbu r4,11(r2) + 8010e94: d0a05817 ldw r2,-32416(gp) + 8010e98: 10c00d43 ldbu r3,53(r2) + 8010e9c: d0a05817 ldw r2,-32416(gp) + 8010ea0: 10800d03 ldbu r2,52(r2) + 8010ea4: 10803fcc andi r2,r2,255 + 8010ea8: 20c6b03a or r3,r4,r3 + 8010eac: 1809883a mov r4,r3 + 8010eb0: e0fffe17 ldw r3,-8(fp) + 8010eb4: 1885883a add r2,r3,r2 + 8010eb8: 110002c5 stb r4,11(r2) + pevent->OSEventGrp |= OSTCBCur->OSTCBBitY; + 8010ebc: e0bffe17 ldw r2,-8(fp) + 8010ec0: 10c00283 ldbu r3,10(r2) + 8010ec4: d0a05817 ldw r2,-32416(gp) + 8010ec8: 10800d83 ldbu r2,54(r2) + 8010ecc: 1884b03a or r2,r3,r2 + 8010ed0: 1007883a mov r3,r2 + 8010ed4: e0bffe17 ldw r2,-8(fp) + 8010ed8: 10c00285 stb r3,10(r2) + + y = OSTCBCur->OSTCBY; /* Task no longer ready */ + 8010edc: d0a05817 ldw r2,-32416(gp) + 8010ee0: 10800d03 ldbu r2,52(r2) + 8010ee4: e0bfffc5 stb r2,-1(fp) + OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX; + 8010ee8: e0ffffc3 ldbu r3,-1(fp) + 8010eec: d0a05544 addi r2,gp,-32427 + 8010ef0: 1885883a add r2,r3,r2 + 8010ef4: 10800003 ldbu r2,0(r2) + 8010ef8: 1007883a mov r3,r2 + 8010efc: d0a05817 ldw r2,-32416(gp) + 8010f00: 10800d43 ldbu r2,53(r2) + 8010f04: 0084303a nor r2,zero,r2 + 8010f08: 1884703a and r2,r3,r2 + 8010f0c: e0ffffc3 ldbu r3,-1(fp) + 8010f10: 1009883a mov r4,r2 + 8010f14: d0a05544 addi r2,gp,-32427 + 8010f18: 1885883a add r2,r3,r2 + 8010f1c: 11000005 stb r4,0(r2) + if (OSRdyTbl[y] == 0) { + 8010f20: e0ffffc3 ldbu r3,-1(fp) + 8010f24: d0a05544 addi r2,gp,-32427 + 8010f28: 1885883a add r2,r3,r2 + 8010f2c: 10800003 ldbu r2,0(r2) + 8010f30: 10803fcc andi r2,r2,255 + 8010f34: 1000071e bne r2,zero,8010f54 + OSRdyGrp &= ~OSTCBCur->OSTCBBitY; /* Clear event grp bit if this was only task pending */ + 8010f38: d0a05817 ldw r2,-32416(gp) + 8010f3c: 10800d83 ldbu r2,54(r2) + 8010f40: 0084303a nor r2,zero,r2 + 8010f44: 1007883a mov r3,r2 + 8010f48: d0a05503 ldbu r2,-32428(gp) + 8010f4c: 1884703a and r2,r3,r2 + 8010f50: d0a05505 stb r2,-32428(gp) + } +} + 8010f54: 0001883a nop + 8010f58: e037883a mov sp,fp + 8010f5c: df000017 ldw fp,0(sp) + 8010f60: dec00104 addi sp,sp,4 + 8010f64: f800283a ret + +08010f68 : +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if ((OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0)) +void OS_EventTaskWaitMulti (OS_EVENT **pevents_wait) +{ + 8010f68: defffb04 addi sp,sp,-20 + 8010f6c: df000415 stw fp,16(sp) + 8010f70: df000404 addi fp,sp,16 + 8010f74: e13ffc15 stw r4,-16(fp) + OS_EVENT **pevents; + OS_EVENT *pevent; + INT8U y; + + + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; + 8010f78: d0a05817 ldw r2,-32416(gp) + 8010f7c: 10000715 stw zero,28(r2) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)pevents_wait; /* Store ptr to ECBs in TCB */ + 8010f80: d0a05817 ldw r2,-32416(gp) + 8010f84: e0fffc17 ldw r3,-16(fp) + 8010f88: 10c00815 stw r3,32(r2) + + pevents = pevents_wait; + 8010f8c: e0bffc17 ldw r2,-16(fp) + 8010f90: e0bfff15 stw r2,-4(fp) + pevent = *pevents; + 8010f94: e0bfff17 ldw r2,-4(fp) + 8010f98: 10800017 ldw r2,0(r2) + 8010f9c: e0bffe15 stw r2,-8(fp) + while (pevent != (OS_EVENT *)0) { /* Put task in waiting lists */ + 8010fa0: 00001e06 br 801101c + pevent->OSEventTbl[OSTCBCur->OSTCBY] |= OSTCBCur->OSTCBBitX; + 8010fa4: d0a05817 ldw r2,-32416(gp) + 8010fa8: 10800d03 ldbu r2,52(r2) + 8010fac: 10803fcc andi r2,r2,255 + 8010fb0: e0fffe17 ldw r3,-8(fp) + 8010fb4: 1885883a add r2,r3,r2 + 8010fb8: 110002c3 ldbu r4,11(r2) + 8010fbc: d0a05817 ldw r2,-32416(gp) + 8010fc0: 10c00d43 ldbu r3,53(r2) + 8010fc4: d0a05817 ldw r2,-32416(gp) + 8010fc8: 10800d03 ldbu r2,52(r2) + 8010fcc: 10803fcc andi r2,r2,255 + 8010fd0: 20c6b03a or r3,r4,r3 + 8010fd4: 1809883a mov r4,r3 + 8010fd8: e0fffe17 ldw r3,-8(fp) + 8010fdc: 1885883a add r2,r3,r2 + 8010fe0: 110002c5 stb r4,11(r2) + pevent->OSEventGrp |= OSTCBCur->OSTCBBitY; + 8010fe4: e0bffe17 ldw r2,-8(fp) + 8010fe8: 10c00283 ldbu r3,10(r2) + 8010fec: d0a05817 ldw r2,-32416(gp) + 8010ff0: 10800d83 ldbu r2,54(r2) + 8010ff4: 1884b03a or r2,r3,r2 + 8010ff8: 1007883a mov r3,r2 + 8010ffc: e0bffe17 ldw r2,-8(fp) + 8011000: 10c00285 stb r3,10(r2) + pevents++; + 8011004: e0bfff17 ldw r2,-4(fp) + 8011008: 10800104 addi r2,r2,4 + 801100c: e0bfff15 stw r2,-4(fp) + pevent = *pevents; + 8011010: e0bfff17 ldw r2,-4(fp) + 8011014: 10800017 ldw r2,0(r2) + 8011018: e0bffe15 stw r2,-8(fp) + while (pevent != (OS_EVENT *)0) { /* Put task in waiting lists */ + 801101c: e0bffe17 ldw r2,-8(fp) + 8011020: 103fe01e bne r2,zero,8010fa4 + } + + y = OSTCBCur->OSTCBY; /* Task no longer ready */ + 8011024: d0a05817 ldw r2,-32416(gp) + 8011028: 10800d03 ldbu r2,52(r2) + 801102c: e0bffdc5 stb r2,-9(fp) + OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX; + 8011030: e0fffdc3 ldbu r3,-9(fp) + 8011034: d0a05544 addi r2,gp,-32427 + 8011038: 1885883a add r2,r3,r2 + 801103c: 10800003 ldbu r2,0(r2) + 8011040: 1007883a mov r3,r2 + 8011044: d0a05817 ldw r2,-32416(gp) + 8011048: 10800d43 ldbu r2,53(r2) + 801104c: 0084303a nor r2,zero,r2 + 8011050: 1884703a and r2,r3,r2 + 8011054: e0fffdc3 ldbu r3,-9(fp) + 8011058: 1009883a mov r4,r2 + 801105c: d0a05544 addi r2,gp,-32427 + 8011060: 1885883a add r2,r3,r2 + 8011064: 11000005 stb r4,0(r2) + if (OSRdyTbl[y] == 0) { + 8011068: e0fffdc3 ldbu r3,-9(fp) + 801106c: d0a05544 addi r2,gp,-32427 + 8011070: 1885883a add r2,r3,r2 + 8011074: 10800003 ldbu r2,0(r2) + 8011078: 10803fcc andi r2,r2,255 + 801107c: 1000071e bne r2,zero,801109c + OSRdyGrp &= ~OSTCBCur->OSTCBBitY; /* Clear event grp bit if this was only task pending */ + 8011080: d0a05817 ldw r2,-32416(gp) + 8011084: 10800d83 ldbu r2,54(r2) + 8011088: 0084303a nor r2,zero,r2 + 801108c: 1007883a mov r3,r2 + 8011090: d0a05503 ldbu r2,-32428(gp) + 8011094: 1884703a and r2,r3,r2 + 8011098: d0a05505 stb r2,-32428(gp) + } +} + 801109c: 0001883a nop + 80110a0: e037883a mov sp,fp + 80110a4: df000017 ldw fp,0(sp) + 80110a8: dec00104 addi sp,sp,4 + 80110ac: f800283a ret + +080110b0 : +********************************************************************************************************* +*/ +#if (OS_EVENT_EN) +void OS_EventTaskRemove (OS_TCB *ptcb, + OS_EVENT *pevent) +{ + 80110b0: defffc04 addi sp,sp,-16 + 80110b4: df000315 stw fp,12(sp) + 80110b8: df000304 addi fp,sp,12 + 80110bc: e13ffe15 stw r4,-8(fp) + 80110c0: e17ffd15 stw r5,-12(fp) + INT8U y; + + + y = ptcb->OSTCBY; + 80110c4: e0bffe17 ldw r2,-8(fp) + 80110c8: 10800d03 ldbu r2,52(r2) + 80110cc: e0bfffc5 stb r2,-1(fp) + pevent->OSEventTbl[y] &= ~ptcb->OSTCBBitX; /* Remove task from wait list */ + 80110d0: e0bfffc3 ldbu r2,-1(fp) + 80110d4: e0fffd17 ldw r3,-12(fp) + 80110d8: 1885883a add r2,r3,r2 + 80110dc: 108002c3 ldbu r2,11(r2) + 80110e0: 1007883a mov r3,r2 + 80110e4: e0bffe17 ldw r2,-8(fp) + 80110e8: 10800d43 ldbu r2,53(r2) + 80110ec: 0084303a nor r2,zero,r2 + 80110f0: 1884703a and r2,r3,r2 + 80110f4: 1007883a mov r3,r2 + 80110f8: e0bfffc3 ldbu r2,-1(fp) + 80110fc: 1809883a mov r4,r3 + 8011100: e0fffd17 ldw r3,-12(fp) + 8011104: 1885883a add r2,r3,r2 + 8011108: 110002c5 stb r4,11(r2) + if (pevent->OSEventTbl[y] == 0) { + 801110c: e0bfffc3 ldbu r2,-1(fp) + 8011110: e0fffd17 ldw r3,-12(fp) + 8011114: 1885883a add r2,r3,r2 + 8011118: 108002c3 ldbu r2,11(r2) + 801111c: 10803fcc andi r2,r2,255 + 8011120: 10000a1e bne r2,zero,801114c + pevent->OSEventGrp &= ~ptcb->OSTCBBitY; + 8011124: e0bffd17 ldw r2,-12(fp) + 8011128: 10800283 ldbu r2,10(r2) + 801112c: 1007883a mov r3,r2 + 8011130: e0bffe17 ldw r2,-8(fp) + 8011134: 10800d83 ldbu r2,54(r2) + 8011138: 0084303a nor r2,zero,r2 + 801113c: 1884703a and r2,r3,r2 + 8011140: 1007883a mov r3,r2 + 8011144: e0bffd17 ldw r2,-12(fp) + 8011148: 10c00285 stb r3,10(r2) + } +} + 801114c: 0001883a nop + 8011150: e037883a mov sp,fp + 8011154: df000017 ldw fp,0(sp) + 8011158: dec00104 addi sp,sp,4 + 801115c: f800283a ret + +08011160 : +********************************************************************************************************* +*/ +#if ((OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0)) +void OS_EventTaskRemoveMulti (OS_TCB *ptcb, + OS_EVENT **pevents_multi) +{ + 8011160: defffa04 addi sp,sp,-24 + 8011164: df000515 stw fp,20(sp) + 8011168: df000504 addi fp,sp,20 + 801116c: e13ffc15 stw r4,-16(fp) + 8011170: e17ffb15 stw r5,-20(fp) + INT16U bity; + INT16U bitx; +#endif + + + y = ptcb->OSTCBY; + 8011174: e0bffc17 ldw r2,-16(fp) + 8011178: 10800d03 ldbu r2,52(r2) + 801117c: e0bffdc5 stb r2,-9(fp) + bity = ptcb->OSTCBBitY; + 8011180: e0bffc17 ldw r2,-16(fp) + 8011184: 10800d83 ldbu r2,54(r2) + 8011188: e0bffd85 stb r2,-10(fp) + bitx = ptcb->OSTCBBitX; + 801118c: e0bffc17 ldw r2,-16(fp) + 8011190: 10800d43 ldbu r2,53(r2) + 8011194: e0bffd45 stb r2,-11(fp) + pevents = pevents_multi; + 8011198: e0bffb17 ldw r2,-20(fp) + 801119c: e0bfff15 stw r2,-4(fp) + pevent = *pevents; + 80111a0: e0bfff17 ldw r2,-4(fp) + 80111a4: 10800017 ldw r2,0(r2) + 80111a8: e0bffe15 stw r2,-8(fp) + while (pevent != (OS_EVENT *)0) { /* Remove task from all events' wait lists */ + 80111ac: 00002306 br 801123c + pevent->OSEventTbl[y] &= ~bitx; + 80111b0: e0bffdc3 ldbu r2,-9(fp) + 80111b4: e0fffe17 ldw r3,-8(fp) + 80111b8: 1885883a add r2,r3,r2 + 80111bc: 108002c3 ldbu r2,11(r2) + 80111c0: 1007883a mov r3,r2 + 80111c4: e0bffd43 ldbu r2,-11(fp) + 80111c8: 0084303a nor r2,zero,r2 + 80111cc: 1884703a and r2,r3,r2 + 80111d0: 1007883a mov r3,r2 + 80111d4: e0bffdc3 ldbu r2,-9(fp) + 80111d8: 1809883a mov r4,r3 + 80111dc: e0fffe17 ldw r3,-8(fp) + 80111e0: 1885883a add r2,r3,r2 + 80111e4: 110002c5 stb r4,11(r2) + if (pevent->OSEventTbl[y] == 0) { + 80111e8: e0bffdc3 ldbu r2,-9(fp) + 80111ec: e0fffe17 ldw r3,-8(fp) + 80111f0: 1885883a add r2,r3,r2 + 80111f4: 108002c3 ldbu r2,11(r2) + 80111f8: 10803fcc andi r2,r2,255 + 80111fc: 1000091e bne r2,zero,8011224 + pevent->OSEventGrp &= ~bity; + 8011200: e0bffe17 ldw r2,-8(fp) + 8011204: 10800283 ldbu r2,10(r2) + 8011208: 1007883a mov r3,r2 + 801120c: e0bffd83 ldbu r2,-10(fp) + 8011210: 0084303a nor r2,zero,r2 + 8011214: 1884703a and r2,r3,r2 + 8011218: 1007883a mov r3,r2 + 801121c: e0bffe17 ldw r2,-8(fp) + 8011220: 10c00285 stb r3,10(r2) + } + pevents++; + 8011224: e0bfff17 ldw r2,-4(fp) + 8011228: 10800104 addi r2,r2,4 + 801122c: e0bfff15 stw r2,-4(fp) + pevent = *pevents; + 8011230: e0bfff17 ldw r2,-4(fp) + 8011234: 10800017 ldw r2,0(r2) + 8011238: e0bffe15 stw r2,-8(fp) + while (pevent != (OS_EVENT *)0) { /* Remove task from all events' wait lists */ + 801123c: e0bffe17 ldw r2,-8(fp) + 8011240: 103fdb1e bne r2,zero,80111b0 + } +} + 8011244: 0001883a nop + 8011248: e037883a mov sp,fp + 801124c: df000017 ldw fp,0(sp) + 8011250: dec00104 addi sp,sp,4 + 8011254: f800283a ret + +08011258 : +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if (OS_EVENT_EN) +void OS_EventWaitListInit (OS_EVENT *pevent) +{ + 8011258: defffc04 addi sp,sp,-16 + 801125c: df000315 stw fp,12(sp) + 8011260: df000304 addi fp,sp,12 + 8011264: e13ffd15 stw r4,-12(fp) + INT16U *ptbl; +#endif + INT8U i; + + + pevent->OSEventGrp = 0; /* No task waiting on event */ + 8011268: e0bffd17 ldw r2,-12(fp) + 801126c: 10000285 stb zero,10(r2) + ptbl = &pevent->OSEventTbl[0]; + 8011270: e0bffd17 ldw r2,-12(fp) + 8011274: 108002c4 addi r2,r2,11 + 8011278: e0bfff15 stw r2,-4(fp) + + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 801127c: e03ffec5 stb zero,-5(fp) + 8011280: 00000706 br 80112a0 + *ptbl++ = 0; + 8011284: e0bfff17 ldw r2,-4(fp) + 8011288: 10c00044 addi r3,r2,1 + 801128c: e0ffff15 stw r3,-4(fp) + 8011290: 10000005 stb zero,0(r2) + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 8011294: e0bffec3 ldbu r2,-5(fp) + 8011298: 10800044 addi r2,r2,1 + 801129c: e0bffec5 stb r2,-5(fp) + 80112a0: e0bffec3 ldbu r2,-5(fp) + 80112a4: 108000f0 cmpltui r2,r2,3 + 80112a8: 103ff61e bne r2,zero,8011284 + } +} + 80112ac: 0001883a nop + 80112b0: e037883a mov sp,fp + 80112b4: df000017 ldw fp,0(sp) + 80112b8: dec00104 addi sp,sp,4 + 80112bc: f800283a ret + +080112c0 : +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitEventList (void) +{ + 80112c0: defffb04 addi sp,sp,-20 + 80112c4: dfc00415 stw ra,16(sp) + 80112c8: df000315 stw fp,12(sp) + 80112cc: df000304 addi fp,sp,12 + INT16U i; + OS_EVENT *pevent1; + OS_EVENT *pevent2; + + + OS_MemClr((INT8U *)&OSEventTbl[0], sizeof(OSEventTbl)); /* Clear the event table */ + 80112d0: 0142d004 movi r5,2880 + 80112d4: 010201b4 movhi r4,2054 + 80112d8: 2131eb04 addi r4,r4,-14420 + 80112dc: 80115b00 call 80115b0 + pevent1 = &OSEventTbl[0]; + 80112e0: 008201b4 movhi r2,2054 + 80112e4: 10b1eb04 addi r2,r2,-14420 + 80112e8: e0bffe15 stw r2,-8(fp) + pevent2 = &OSEventTbl[1]; + 80112ec: 008201b4 movhi r2,2054 + 80112f0: 10b1f704 addi r2,r2,-14372 + 80112f4: e0bffd15 stw r2,-12(fp) + for (i = 0; i < (OS_MAX_EVENTS - 1); i++) { /* Init. list of free EVENT control blocks */ + 80112f8: e03fff8d sth zero,-2(fp) + 80112fc: 00001306 br 801134c + pevent1->OSEventType = OS_EVENT_TYPE_UNUSED; + 8011300: e0bffe17 ldw r2,-8(fp) + 8011304: 10000005 stb zero,0(r2) + pevent1->OSEventPtr = pevent2; + 8011308: e0bffe17 ldw r2,-8(fp) + 801130c: e0fffd17 ldw r3,-12(fp) + 8011310: 10c00115 stw r3,4(r2) +#if OS_EVENT_NAME_SIZE > 1 + pevent1->OSEventName[0] = '?'; /* Unknown name */ + 8011314: e0bffe17 ldw r2,-8(fp) + 8011318: 00c00fc4 movi r3,63 + 801131c: 10c00385 stb r3,14(r2) + pevent1->OSEventName[1] = OS_ASCII_NUL; + 8011320: e0bffe17 ldw r2,-8(fp) + 8011324: 100003c5 stb zero,15(r2) +#endif + pevent1++; + 8011328: e0bffe17 ldw r2,-8(fp) + 801132c: 10800c04 addi r2,r2,48 + 8011330: e0bffe15 stw r2,-8(fp) + pevent2++; + 8011334: e0bffd17 ldw r2,-12(fp) + 8011338: 10800c04 addi r2,r2,48 + 801133c: e0bffd15 stw r2,-12(fp) + for (i = 0; i < (OS_MAX_EVENTS - 1); i++) { /* Init. list of free EVENT control blocks */ + 8011340: e0bfff8b ldhu r2,-2(fp) + 8011344: 10800044 addi r2,r2,1 + 8011348: e0bfff8d sth r2,-2(fp) + 801134c: e0bfff8b ldhu r2,-2(fp) + 8011350: 10800ef0 cmpltui r2,r2,59 + 8011354: 103fea1e bne r2,zero,8011300 + } + pevent1->OSEventType = OS_EVENT_TYPE_UNUSED; + 8011358: e0bffe17 ldw r2,-8(fp) + 801135c: 10000005 stb zero,0(r2) + pevent1->OSEventPtr = (OS_EVENT *)0; + 8011360: e0bffe17 ldw r2,-8(fp) + 8011364: 10000115 stw zero,4(r2) +#if OS_EVENT_NAME_SIZE > 1 + pevent1->OSEventName[0] = '?'; + 8011368: e0bffe17 ldw r2,-8(fp) + 801136c: 00c00fc4 movi r3,63 + 8011370: 10c00385 stb r3,14(r2) + pevent1->OSEventName[1] = OS_ASCII_NUL; + 8011374: e0bffe17 ldw r2,-8(fp) + 8011378: 100003c5 stb zero,15(r2) +#endif + OSEventFreeList = &OSEventTbl[0]; + 801137c: 008201b4 movhi r2,2054 + 8011380: 10b1eb04 addi r2,r2,-14420 + 8011384: d0a05615 stw r2,-32424(gp) + OSEventFreeList->OSEventName[0] = '?'; /* Unknown name */ + OSEventFreeList->OSEventName[1] = OS_ASCII_NUL; +#endif +#endif +#endif +} + 8011388: 0001883a nop + 801138c: e037883a mov sp,fp + 8011390: dfc00117 ldw ra,4(sp) + 8011394: df000017 ldw fp,0(sp) + 8011398: dec00204 addi sp,sp,8 + 801139c: f800283a ret + +080113a0 : +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitMisc (void) +{ + 80113a0: deffff04 addi sp,sp,-4 + 80113a4: df000015 stw fp,0(sp) + 80113a8: d839883a mov fp,sp +#if OS_TIME_GET_SET_EN > 0 + OSTime = 0L; /* Clear the 32-bit system clock */ + 80113ac: d0205915 stw zero,-32412(gp) +#endif + + OSIntNesting = 0; /* Clear the interrupt nesting counter */ + 80113b0: d0205705 stb zero,-32420(gp) + OSLockNesting = 0; /* Clear the scheduling lock counter */ + 80113b4: d0204b05 stb zero,-32468(gp) + + OSTaskCtr = 0; /* Clear the number of tasks */ + 80113b8: d0205105 stb zero,-32444(gp) + + OSRunning = OS_FALSE; /* Indicate that multitasking not started */ + 80113bc: d0204b45 stb zero,-32467(gp) + + OSCtxSwCtr = 0; /* Clear the context switch counter */ + 80113c0: d0204f15 stw zero,-32452(gp) + OSIdleCtr = 0L; /* Clear the 32-bit idle counter */ + 80113c4: d0204c15 stw zero,-32464(gp) +#if OS_TASK_STAT_EN > 0 + OSIdleCtrRun = 0L; + OSIdleCtrMax = 0L; + OSStatRdy = OS_FALSE; /* Statistic task is not ready */ +#endif +} + 80113c8: 0001883a nop + 80113cc: e037883a mov sp,fp + 80113d0: df000017 ldw fp,0(sp) + 80113d4: dec00104 addi sp,sp,4 + 80113d8: f800283a ret + +080113dc : +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitRdyList (void) +{ + 80113dc: defffd04 addi sp,sp,-12 + 80113e0: df000215 stw fp,8(sp) + 80113e4: df000204 addi fp,sp,8 +#else + INT16U *prdytbl; +#endif + + + OSRdyGrp = 0; /* Clear the ready list */ + 80113e8: d0205505 stb zero,-32428(gp) + prdytbl = &OSRdyTbl[0]; + 80113ec: d0a05544 addi r2,gp,-32427 + 80113f0: e0bffe15 stw r2,-8(fp) + for (i = 0; i < OS_RDY_TBL_SIZE; i++) { + 80113f4: e03fffc5 stb zero,-1(fp) + 80113f8: 00000706 br 8011418 + *prdytbl++ = 0; + 80113fc: e0bffe17 ldw r2,-8(fp) + 8011400: 10c00044 addi r3,r2,1 + 8011404: e0fffe15 stw r3,-8(fp) + 8011408: 10000005 stb zero,0(r2) + for (i = 0; i < OS_RDY_TBL_SIZE; i++) { + 801140c: e0bfffc3 ldbu r2,-1(fp) + 8011410: 10800044 addi r2,r2,1 + 8011414: e0bfffc5 stb r2,-1(fp) + 8011418: e0bfffc3 ldbu r2,-1(fp) + 801141c: 108000f0 cmpltui r2,r2,3 + 8011420: 103ff61e bne r2,zero,80113fc + } + + OSPrioCur = 0; + 8011424: d0204d45 stb zero,-32459(gp) + OSPrioHighRdy = 0; + 8011428: d0204d05 stb zero,-32460(gp) + + OSTCBHighRdy = (OS_TCB *)0; + 801142c: d0205315 stw zero,-32436(gp) + OSTCBCur = (OS_TCB *)0; + 8011430: d0205815 stw zero,-32416(gp) +} + 8011434: 0001883a nop + 8011438: e037883a mov sp,fp + 801143c: df000017 ldw fp,0(sp) + 8011440: dec00104 addi sp,sp,4 + 8011444: f800283a ret + +08011448 : +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitTaskIdle (void) +{ + 8011448: defff804 addi sp,sp,-32 + 801144c: dfc00715 stw ra,28(sp) + 8011450: df000615 stw fp,24(sp) + 8011454: df000604 addi fp,sp,24 +#endif + + +#if OS_TASK_CREATE_EXT_EN > 0 + #if OS_STK_GROWTH == 1 + (void)OSTaskCreateExt(OS_TaskIdle, + 8011458: 008000c4 movi r2,3 + 801145c: d8800415 stw r2,16(sp) + 8011460: d8000315 stw zero,12(sp) + 8011464: 00808004 movi r2,512 + 8011468: d8800215 stw r2,8(sp) + 801146c: 008201b4 movhi r2,2054 + 8011470: 10afeb04 addi r2,r2,-16468 + 8011474: d8800115 stw r2,4(sp) + 8011478: 00bfffd4 movui r2,65535 + 801147c: d8800015 stw r2,0(sp) + 8011480: 01c00504 movi r7,20 + 8011484: 018201b4 movhi r6,2054 + 8011488: 31b1ea04 addi r6,r6,-14424 + 801148c: 000b883a mov r5,zero + 8011490: 01020074 movhi r4,2049 + 8011494: 21061a04 addi r4,r4,6248 + 8011498: 801664c0 call 801664c + OS_TASK_IDLE_PRIO); + #endif +#endif + +#if OS_TASK_NAME_SIZE > 14 + OSTaskNameSet(OS_TASK_IDLE_PRIO, (INT8U *)"uC/OS-II Idle", &err); + 801149c: e0bfffc4 addi r2,fp,-1 + 80114a0: 100d883a mov r6,r2 + 80114a4: 01420134 movhi r5,2052 + 80114a8: 295e0d04 addi r5,r5,30772 + 80114ac: 01000504 movi r4,20 + 80114b0: 8016d640 call 8016d64 +#else +#if OS_TASK_NAME_SIZE > 7 + OSTaskNameSet(OS_TASK_IDLE_PRIO, (INT8U *)"OS-Idle", &err); +#endif +#endif +} + 80114b4: 0001883a nop + 80114b8: e037883a mov sp,fp + 80114bc: dfc00117 ldw ra,4(sp) + 80114c0: df000017 ldw fp,0(sp) + 80114c4: dec00204 addi sp,sp,8 + 80114c8: f800283a ret + +080114cc : +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitTCBList (void) +{ + 80114cc: defffb04 addi sp,sp,-20 + 80114d0: dfc00415 stw ra,16(sp) + 80114d4: df000315 stw fp,12(sp) + 80114d8: df000304 addi fp,sp,12 + INT8U i; + OS_TCB *ptcb1; + OS_TCB *ptcb2; + + + OS_MemClr((INT8U *)&OSTCBTbl[0], sizeof(OSTCBTbl)); /* Clear all the TCBs */ + 80114dc: 0140a204 movi r5,648 + 80114e0: 010201b4 movhi r4,2054 + 80114e4: 2134bb04 addi r4,r4,-11540 + 80114e8: 80115b00 call 80115b0 + OS_MemClr((INT8U *)&OSTCBPrioTbl[0], sizeof(OSTCBPrioTbl)); /* Clear the priority table */ + 80114ec: 01401504 movi r5,84 + 80114f0: 010201b4 movhi r4,2054 + 80114f4: 21355d04 addi r4,r4,-10892 + 80114f8: 80115b00 call 80115b0 + ptcb1 = &OSTCBTbl[0]; + 80114fc: 008201b4 movhi r2,2054 + 8011500: 10b4bb04 addi r2,r2,-11540 + 8011504: e0bffe15 stw r2,-8(fp) + ptcb2 = &OSTCBTbl[1]; + 8011508: 008201b4 movhi r2,2054 + 801150c: 10b4d604 addi r2,r2,-11432 + 8011510: e0bffd15 stw r2,-12(fp) + for (i = 0; i < (OS_MAX_TASKS + OS_N_SYS_TASKS - 1); i++) { /* Init. list of free TCBs */ + 8011514: e03fffc5 stb zero,-1(fp) + 8011518: 00001106 br 8011560 + ptcb1->OSTCBNext = ptcb2; + 801151c: e0bffe17 ldw r2,-8(fp) + 8011520: e0fffd17 ldw r3,-12(fp) + 8011524: 10c00515 stw r3,20(r2) +#if OS_TASK_NAME_SIZE > 1 + ptcb1->OSTCBTaskName[0] = '?'; /* Unknown name */ + 8011528: e0bffe17 ldw r2,-8(fp) + 801152c: 00c00fc4 movi r3,63 + 8011530: 10c01305 stb r3,76(r2) + ptcb1->OSTCBTaskName[1] = OS_ASCII_NUL; + 8011534: e0bffe17 ldw r2,-8(fp) + 8011538: 10001345 stb zero,77(r2) +#endif + ptcb1++; + 801153c: e0bffe17 ldw r2,-8(fp) + 8011540: 10801b04 addi r2,r2,108 + 8011544: e0bffe15 stw r2,-8(fp) + ptcb2++; + 8011548: e0bffd17 ldw r2,-12(fp) + 801154c: 10801b04 addi r2,r2,108 + 8011550: e0bffd15 stw r2,-12(fp) + for (i = 0; i < (OS_MAX_TASKS + OS_N_SYS_TASKS - 1); i++) { /* Init. list of free TCBs */ + 8011554: e0bfffc3 ldbu r2,-1(fp) + 8011558: 10800044 addi r2,r2,1 + 801155c: e0bfffc5 stb r2,-1(fp) + 8011560: e0bfffc3 ldbu r2,-1(fp) + 8011564: 10800170 cmpltui r2,r2,5 + 8011568: 103fec1e bne r2,zero,801151c + } + ptcb1->OSTCBNext = (OS_TCB *)0; /* Last OS_TCB */ + 801156c: e0bffe17 ldw r2,-8(fp) + 8011570: 10000515 stw zero,20(r2) +#if OS_TASK_NAME_SIZE > 1 + ptcb1->OSTCBTaskName[0] = '?'; /* Unknown name */ + 8011574: e0bffe17 ldw r2,-8(fp) + 8011578: 00c00fc4 movi r3,63 + 801157c: 10c01305 stb r3,76(r2) + ptcb1->OSTCBTaskName[1] = OS_ASCII_NUL; + 8011580: e0bffe17 ldw r2,-8(fp) + 8011584: 10001345 stb zero,77(r2) +#endif + OSTCBList = (OS_TCB *)0; /* TCB lists initializations */ + 8011588: d0204e15 stw zero,-32456(gp) + OSTCBFreeList = &OSTCBTbl[0]; + 801158c: 008201b4 movhi r2,2054 + 8011590: 10b4bb04 addi r2,r2,-11540 + 8011594: d0a05015 stw r2,-32448(gp) +} + 8011598: 0001883a nop + 801159c: e037883a mov sp,fp + 80115a0: dfc00117 ldw ra,4(sp) + 80115a4: df000017 ldw fp,0(sp) + 80115a8: dec00204 addi sp,sp,8 + 80115ac: f800283a ret + +080115b0 : +* of the alignment of the destination. +********************************************************************************************************* +*/ + +void OS_MemClr (INT8U *pdest, INT16U size) +{ + 80115b0: defffd04 addi sp,sp,-12 + 80115b4: df000215 stw fp,8(sp) + 80115b8: df000204 addi fp,sp,8 + 80115bc: e13fff15 stw r4,-4(fp) + 80115c0: 2805883a mov r2,r5 + 80115c4: e0bffe0d sth r2,-8(fp) + while (size > 0) { + 80115c8: 00000706 br 80115e8 + *pdest++ = (INT8U)0; + 80115cc: e0bfff17 ldw r2,-4(fp) + 80115d0: 10c00044 addi r3,r2,1 + 80115d4: e0ffff15 stw r3,-4(fp) + 80115d8: 10000005 stb zero,0(r2) + size--; + 80115dc: e0bffe0b ldhu r2,-8(fp) + 80115e0: 10bfffc4 addi r2,r2,-1 + 80115e4: e0bffe0d sth r2,-8(fp) + while (size > 0) { + 80115e8: e0bffe0b ldhu r2,-8(fp) + 80115ec: 103ff71e bne r2,zero,80115cc + } +} + 80115f0: 0001883a nop + 80115f4: e037883a mov sp,fp + 80115f8: df000017 ldw fp,0(sp) + 80115fc: dec00104 addi sp,sp,4 + 8011600: f800283a ret + +08011604 : +* of the alignment of the source and destination. +********************************************************************************************************* +*/ + +void OS_MemCopy (INT8U *pdest, INT8U *psrc, INT16U size) +{ + 8011604: defffc04 addi sp,sp,-16 + 8011608: df000315 stw fp,12(sp) + 801160c: df000304 addi fp,sp,12 + 8011610: e13fff15 stw r4,-4(fp) + 8011614: e17ffe15 stw r5,-8(fp) + 8011618: 3005883a mov r2,r6 + 801161c: e0bffd0d sth r2,-12(fp) + while (size > 0) { + 8011620: 00000b06 br 8011650 + *pdest++ = *psrc++; + 8011624: e0fffe17 ldw r3,-8(fp) + 8011628: 18800044 addi r2,r3,1 + 801162c: e0bffe15 stw r2,-8(fp) + 8011630: e0bfff17 ldw r2,-4(fp) + 8011634: 11000044 addi r4,r2,1 + 8011638: e13fff15 stw r4,-4(fp) + 801163c: 18c00003 ldbu r3,0(r3) + 8011640: 10c00005 stb r3,0(r2) + size--; + 8011644: e0bffd0b ldhu r2,-12(fp) + 8011648: 10bfffc4 addi r2,r2,-1 + 801164c: e0bffd0d sth r2,-12(fp) + while (size > 0) { + 8011650: e0bffd0b ldhu r2,-12(fp) + 8011654: 103ff31e bne r2,zero,8011624 + } +} + 8011658: 0001883a nop + 801165c: e037883a mov sp,fp + 8011660: df000017 ldw fp,0(sp) + 8011664: dec00104 addi sp,sp,4 + 8011668: f800283a ret + +0801166c : +* 2) Rescheduling is prevented when the scheduler is locked (see OS_SchedLock()) +********************************************************************************************************* +*/ + +void OS_Sched (void) +{ + 801166c: defffb04 addi sp,sp,-20 + 8011670: dfc00415 stw ra,16(sp) + 8011674: df000315 stw fp,12(sp) + 8011678: df000304 addi fp,sp,12 +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 801167c: e03fff15 stw zero,-4(fp) + NIOS2_READ_STATUS (context); + 8011680: 0005303a rdctl r2,status + 8011684: e0bffe15 stw r2,-8(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8011688: e0fffe17 ldw r3,-8(fp) + 801168c: 00bfff84 movi r2,-2 + 8011690: 1884703a and r2,r3,r2 + 8011694: 1001703a wrctl status,r2 + return context; + 8011698: e0bffe17 ldw r2,-8(fp) +#endif + + + + OS_ENTER_CRITICAL(); + 801169c: e0bfff15 stw r2,-4(fp) + if (OSIntNesting == 0) { /* Schedule only if all ISRs done and ... */ + 80116a0: d0a05703 ldbu r2,-32420(gp) + 80116a4: 10803fcc andi r2,r2,255 + 80116a8: 1000181e bne r2,zero,801170c + if (OSLockNesting == 0) { /* ... scheduler is not locked */ + 80116ac: d0a04b03 ldbu r2,-32468(gp) + 80116b0: 10803fcc andi r2,r2,255 + 80116b4: 1000151e bne r2,zero,801170c + OS_SchedNew(); + 80116b8: 80117340 call 8011734 + if (OSPrioHighRdy != OSPrioCur) { /* No Ctx Sw if current task is highest rdy */ + 80116bc: d0e04d03 ldbu r3,-32460(gp) + 80116c0: d0a04d43 ldbu r2,-32459(gp) + 80116c4: 18c03fcc andi r3,r3,255 + 80116c8: 10803fcc andi r2,r2,255 + 80116cc: 18800f26 beq r3,r2,801170c + OSTCBHighRdy = OSTCBPrioTbl[OSPrioHighRdy]; + 80116d0: d0a04d03 ldbu r2,-32460(gp) + 80116d4: 10803fcc andi r2,r2,255 + 80116d8: 100690ba slli r3,r2,2 + 80116dc: 008201b4 movhi r2,2054 + 80116e0: 1885883a add r2,r3,r2 + 80116e4: 10b55d17 ldw r2,-10892(r2) + 80116e8: d0a05315 stw r2,-32436(gp) +#if OS_TASK_PROFILE_EN > 0 + OSTCBHighRdy->OSTCBCtxSwCtr++; /* Inc. # of context switches to this task */ + 80116ec: d0a05317 ldw r2,-32436(gp) + 80116f0: 10c00e17 ldw r3,56(r2) + 80116f4: 18c00044 addi r3,r3,1 + 80116f8: 10c00e15 stw r3,56(r2) +#endif + OSCtxSwCtr++; /* Increment context switch counter */ + 80116fc: d0a04f17 ldw r2,-32452(gp) + 8011700: 10800044 addi r2,r2,1 + 8011704: d0a04f15 stw r2,-32452(gp) + OS_TASK_SW(); /* Perform a context switch */ + 8011708: 80383880 call 8038388 + 801170c: e0bfff17 ldw r2,-4(fp) + 8011710: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context); + 8011714: e0bffd17 ldw r2,-12(fp) + 8011718: 1001703a wrctl status,r2 + } + } + } + OS_EXIT_CRITICAL(); +} + 801171c: 0001883a nop + 8011720: e037883a mov sp,fp + 8011724: dfc00117 ldw ra,4(sp) + 8011728: df000017 ldw fp,0(sp) + 801172c: dec00204 addi sp,sp,8 + 8011730: f800283a ret + +08011734 : +* 2) Interrupts are assumed to be disabled when this function is called. +********************************************************************************************************* +*/ + +static void OS_SchedNew (void) +{ + 8011734: defffe04 addi sp,sp,-8 + 8011738: df000115 stw fp,4(sp) + 801173c: df000104 addi fp,sp,4 +#if OS_LOWEST_PRIO <= 63 /* See if we support up to 64 tasks */ + INT8U y; + + + y = OSUnMapTbl[OSRdyGrp]; + 8011740: d0a05503 ldbu r2,-32428(gp) + 8011744: 10c03fcc andi r3,r2,255 + 8011748: 00820134 movhi r2,2052 + 801174c: 1885883a add r2,r3,r2 + 8011750: 109dcd03 ldbu r2,30516(r2) + 8011754: e0bfffc5 stb r2,-1(fp) + OSPrioHighRdy = (INT8U)((y << 3) + OSUnMapTbl[OSRdyTbl[y]]); + 8011758: e0bfffc3 ldbu r2,-1(fp) + 801175c: 100490fa slli r2,r2,3 + 8011760: 1009883a mov r4,r2 + 8011764: e0ffffc3 ldbu r3,-1(fp) + 8011768: d0a05544 addi r2,gp,-32427 + 801176c: 1885883a add r2,r3,r2 + 8011770: 10800003 ldbu r2,0(r2) + 8011774: 10c03fcc andi r3,r2,255 + 8011778: 00820134 movhi r2,2052 + 801177c: 1885883a add r2,r3,r2 + 8011780: 109dcd03 ldbu r2,30516(r2) + 8011784: 2085883a add r2,r4,r2 + 8011788: d0a04d05 stb r2,-32460(gp) + OSPrioHighRdy = (INT8U)((y << 4) + OSUnMapTbl[(*ptbl & 0xFF)]); + } else { + OSPrioHighRdy = (INT8U)((y << 4) + OSUnMapTbl[(*ptbl >> 8) & 0xFF] + 8); + } +#endif +} + 801178c: 0001883a nop + 8011790: e037883a mov sp,fp + 8011794: df000017 ldw fp,0(sp) + 8011798: dec00104 addi sp,sp,4 + 801179c: f800283a ret + +080117a0 : +********************************************************************************************************* +*/ + +#if (OS_EVENT_NAME_SIZE > 1) || (OS_FLAG_NAME_SIZE > 1) || (OS_MEM_NAME_SIZE > 1) || (OS_TASK_NAME_SIZE > 1) || (OS_TMR_CFG_NAME_SIZE > 1) +INT8U OS_StrCopy (INT8U *pdest, INT8U *psrc) +{ + 80117a0: defffc04 addi sp,sp,-16 + 80117a4: df000315 stw fp,12(sp) + 80117a8: df000304 addi fp,sp,12 + 80117ac: e13ffe15 stw r4,-8(fp) + 80117b0: e17ffd15 stw r5,-12(fp) + INT8U len; + + + len = 0; + 80117b4: e03fffc5 stb zero,-1(fp) + while (*psrc != OS_ASCII_NUL) { + 80117b8: 00000b06 br 80117e8 + *pdest++ = *psrc++; + 80117bc: e0fffd17 ldw r3,-12(fp) + 80117c0: 18800044 addi r2,r3,1 + 80117c4: e0bffd15 stw r2,-12(fp) + 80117c8: e0bffe17 ldw r2,-8(fp) + 80117cc: 11000044 addi r4,r2,1 + 80117d0: e13ffe15 stw r4,-8(fp) + 80117d4: 18c00003 ldbu r3,0(r3) + 80117d8: 10c00005 stb r3,0(r2) + len++; + 80117dc: e0bfffc3 ldbu r2,-1(fp) + 80117e0: 10800044 addi r2,r2,1 + 80117e4: e0bfffc5 stb r2,-1(fp) + while (*psrc != OS_ASCII_NUL) { + 80117e8: e0bffd17 ldw r2,-12(fp) + 80117ec: 10800003 ldbu r2,0(r2) + 80117f0: 10803fcc andi r2,r2,255 + 80117f4: 103ff11e bne r2,zero,80117bc + } + *pdest = OS_ASCII_NUL; + 80117f8: e0bffe17 ldw r2,-8(fp) + 80117fc: 10000005 stb zero,0(r2) + return (len); + 8011800: e0bfffc3 ldbu r2,-1(fp) +} + 8011804: e037883a mov sp,fp + 8011808: df000017 ldw fp,0(sp) + 801180c: dec00104 addi sp,sp,4 + 8011810: f800283a ret + +08011814 : +********************************************************************************************************* +*/ + +#if (OS_EVENT_NAME_SIZE > 1) || (OS_FLAG_NAME_SIZE > 1) || (OS_MEM_NAME_SIZE > 1) || (OS_TASK_NAME_SIZE > 1) || (OS_TMR_CFG_NAME_SIZE > 1) +INT8U OS_StrLen (INT8U *psrc) +{ + 8011814: defffd04 addi sp,sp,-12 + 8011818: df000215 stw fp,8(sp) + 801181c: df000204 addi fp,sp,8 + 8011820: e13ffe15 stw r4,-8(fp) + INT8U len; + + + len = 0; + 8011824: e03fffc5 stb zero,-1(fp) + while (*psrc != OS_ASCII_NUL) { + 8011828: 00000606 br 8011844 + psrc++; + 801182c: e0bffe17 ldw r2,-8(fp) + 8011830: 10800044 addi r2,r2,1 + 8011834: e0bffe15 stw r2,-8(fp) + len++; + 8011838: e0bfffc3 ldbu r2,-1(fp) + 801183c: 10800044 addi r2,r2,1 + 8011840: e0bfffc5 stb r2,-1(fp) + while (*psrc != OS_ASCII_NUL) { + 8011844: e0bffe17 ldw r2,-8(fp) + 8011848: 10800003 ldbu r2,0(r2) + 801184c: 10803fcc andi r2,r2,255 + 8011850: 103ff61e bne r2,zero,801182c + } + return (len); + 8011854: e0bfffc3 ldbu r2,-1(fp) +} + 8011858: e037883a mov sp,fp + 801185c: df000017 ldw fp,0(sp) + 8011860: dec00104 addi sp,sp,4 + 8011864: f800283a ret + +08011868 : +* power. +********************************************************************************************************* +*/ + +void OS_TaskIdle (void *p_arg) +{ + 8011868: defffa04 addi sp,sp,-24 + 801186c: dfc00515 stw ra,20(sp) + 8011870: df000415 stw fp,16(sp) + 8011874: df000404 addi fp,sp,16 + 8011878: e13ffc15 stw r4,-16(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 801187c: e03fff15 stw zero,-4(fp) + NIOS2_READ_STATUS (context); + 8011880: 0005303a rdctl r2,status + 8011884: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8011888: e0fffd17 ldw r3,-12(fp) + 801188c: 00bfff84 movi r2,-2 + 8011890: 1884703a and r2,r3,r2 + 8011894: 1001703a wrctl status,r2 + return context; + 8011898: e0bffd17 ldw r2,-12(fp) + + + + (void)p_arg; /* Prevent compiler warning for not using 'p_arg' */ + for (;;) { + OS_ENTER_CRITICAL(); + 801189c: e0bfff15 stw r2,-4(fp) + OSIdleCtr++; + 80118a0: d0a04c17 ldw r2,-32464(gp) + 80118a4: 10800044 addi r2,r2,1 + 80118a8: d0a04c15 stw r2,-32464(gp) + 80118ac: e0bfff17 ldw r2,-4(fp) + 80118b0: e0bffe15 stw r2,-8(fp) + NIOS2_WRITE_STATUS (context); + 80118b4: e0bffe17 ldw r2,-8(fp) + 80118b8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OSTaskIdleHook(); /* Call user definable HOOK */ + 80118bc: 80386980 call 8038698 + OS_ENTER_CRITICAL(); + 80118c0: 003fef06 br 8011880 + +080118c4 : +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +INT8U OS_TCBInit (INT8U prio, OS_STK *ptos, OS_STK *pbos, INT16U id, INT32U stk_size, void *pext, INT16U opt) +{ + 80118c4: defff204 addi sp,sp,-56 + 80118c8: dfc00d15 stw ra,52(sp) + 80118cc: df000c15 stw fp,48(sp) + 80118d0: df000c04 addi fp,sp,48 + 80118d4: 2007883a mov r3,r4 + 80118d8: e17ff715 stw r5,-36(fp) + 80118dc: e1bff615 stw r6,-40(fp) + 80118e0: 3809883a mov r4,r7 + 80118e4: e0800417 ldw r2,16(fp) + 80118e8: e0fff805 stb r3,-32(fp) + 80118ec: 2007883a mov r3,r4 + 80118f0: e0fff50d sth r3,-44(fp) + 80118f4: e0bff40d sth r2,-48(fp) + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 80118f8: e03fff15 stw zero,-4(fp) + NIOS2_READ_STATUS (context); + 80118fc: 0005303a rdctl r2,status + 8011900: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8011904: e0fffd17 ldw r3,-12(fp) + 8011908: 00bfff84 movi r2,-2 + 801190c: 1884703a and r2,r3,r2 + 8011910: 1001703a wrctl status,r2 + return context; + 8011914: e0bffd17 ldw r2,-12(fp) +#endif + + + + OS_ENTER_CRITICAL(); + 8011918: e0bfff15 stw r2,-4(fp) + ptcb = OSTCBFreeList; /* Get a free TCB from the free TCB list */ + 801191c: d0a05017 ldw r2,-32448(gp) + 8011920: e0bffe15 stw r2,-8(fp) + if (ptcb != (OS_TCB *)0) { + 8011924: e0bffe17 ldw r2,-8(fp) + 8011928: 10009126 beq r2,zero,8011b70 + OSTCBFreeList = ptcb->OSTCBNext; /* Update pointer to free TCB list */ + 801192c: e0bffe17 ldw r2,-8(fp) + 8011930: 10800517 ldw r2,20(r2) + 8011934: d0a05015 stw r2,-32448(gp) + 8011938: e0bfff17 ldw r2,-4(fp) + 801193c: e0bffb15 stw r2,-20(fp) + NIOS2_WRITE_STATUS (context); + 8011940: e0bffb17 ldw r2,-20(fp) + 8011944: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + ptcb->OSTCBStkPtr = ptos; /* Load Stack pointer in TCB */ + 8011948: e0bffe17 ldw r2,-8(fp) + 801194c: e0fff717 ldw r3,-36(fp) + 8011950: 10c00015 stw r3,0(r2) + ptcb->OSTCBPrio = prio; /* Load task priority into TCB */ + 8011954: e0bffe17 ldw r2,-8(fp) + 8011958: e0fff803 ldbu r3,-32(fp) + 801195c: 10c00c85 stb r3,50(r2) + ptcb->OSTCBStat = OS_STAT_RDY; /* Task is ready to run */ + 8011960: e0bffe17 ldw r2,-8(fp) + 8011964: 10000c05 stb zero,48(r2) + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + 8011968: e0bffe17 ldw r2,-8(fp) + 801196c: 10000c45 stb zero,49(r2) + ptcb->OSTCBDly = 0; /* Task is not delayed */ + 8011970: e0bffe17 ldw r2,-8(fp) + 8011974: 10000b8d sth zero,46(r2) + +#if OS_TASK_CREATE_EXT_EN > 0 + ptcb->OSTCBExtPtr = pext; /* Store pointer to TCB extension */ + 8011978: e0bffe17 ldw r2,-8(fp) + 801197c: e0c00317 ldw r3,12(fp) + 8011980: 10c00115 stw r3,4(r2) + ptcb->OSTCBStkSize = stk_size; /* Store stack size */ + 8011984: e0bffe17 ldw r2,-8(fp) + 8011988: e0c00217 ldw r3,8(fp) + 801198c: 10c00315 stw r3,12(r2) + ptcb->OSTCBStkBottom = pbos; /* Store pointer to bottom of stack */ + 8011990: e0bffe17 ldw r2,-8(fp) + 8011994: e0fff617 ldw r3,-40(fp) + 8011998: 10c00215 stw r3,8(r2) + ptcb->OSTCBOpt = opt; /* Store task options */ + 801199c: e0bffe17 ldw r2,-8(fp) + 80119a0: e0fff40b ldhu r3,-48(fp) + 80119a4: 10c0040d sth r3,16(r2) + ptcb->OSTCBId = id; /* Store task ID */ + 80119a8: e0bffe17 ldw r2,-8(fp) + 80119ac: e0fff50b ldhu r3,-44(fp) + 80119b0: 10c0048d sth r3,18(r2) + opt = opt; + id = id; +#endif + +#if OS_TASK_DEL_EN > 0 + ptcb->OSTCBDelReq = OS_ERR_NONE; + 80119b4: e0bffe17 ldw r2,-8(fp) + 80119b8: 10000dc5 stb zero,55(r2) +#endif + +#if OS_LOWEST_PRIO <= 63 + ptcb->OSTCBY = (INT8U)(prio >> 3); /* Pre-compute X, Y, BitX and BitY */ + 80119bc: e0bff803 ldbu r2,-32(fp) + 80119c0: 1004d0fa srli r2,r2,3 + 80119c4: 1007883a mov r3,r2 + 80119c8: e0bffe17 ldw r2,-8(fp) + 80119cc: 10c00d05 stb r3,52(r2) + ptcb->OSTCBX = (INT8U)(prio & 0x07); + 80119d0: e0bff803 ldbu r2,-32(fp) + 80119d4: 108001cc andi r2,r2,7 + 80119d8: 1007883a mov r3,r2 + 80119dc: e0bffe17 ldw r2,-8(fp) + 80119e0: 10c00cc5 stb r3,51(r2) + ptcb->OSTCBBitY = (INT8U)(1 << ptcb->OSTCBY); + 80119e4: e0bffe17 ldw r2,-8(fp) + 80119e8: 10800d03 ldbu r2,52(r2) + 80119ec: 10803fcc andi r2,r2,255 + 80119f0: 00c00044 movi r3,1 + 80119f4: 1884983a sll r2,r3,r2 + 80119f8: 1007883a mov r3,r2 + 80119fc: e0bffe17 ldw r2,-8(fp) + 8011a00: 10c00d85 stb r3,54(r2) + ptcb->OSTCBBitX = (INT8U)(1 << ptcb->OSTCBX); + 8011a04: e0bffe17 ldw r2,-8(fp) + 8011a08: 10800cc3 ldbu r2,51(r2) + 8011a0c: 10803fcc andi r2,r2,255 + 8011a10: 00c00044 movi r3,1 + 8011a14: 1884983a sll r2,r3,r2 + 8011a18: 1007883a mov r3,r2 + 8011a1c: e0bffe17 ldw r2,-8(fp) + 8011a20: 10c00d45 stb r3,53(r2) + ptcb->OSTCBBitY = (INT16U)(1 << ptcb->OSTCBY); + ptcb->OSTCBBitX = (INT16U)(1 << ptcb->OSTCBX); +#endif + +#if (OS_EVENT_EN) + ptcb->OSTCBEventPtr = (OS_EVENT *)0; /* Task is not pending on an event */ + 8011a24: e0bffe17 ldw r2,-8(fp) + 8011a28: 10000715 stw zero,28(r2) +#if (OS_EVENT_MULTI_EN > 0) + ptcb->OSTCBEventMultiPtr = (OS_EVENT **)0; /* Task is not pending on any events */ + 8011a2c: e0bffe17 ldw r2,-8(fp) + 8011a30: 10000815 stw zero,32(r2) +#endif +#endif + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) && (OS_TASK_DEL_EN > 0) + ptcb->OSTCBFlagNode = (OS_FLAG_NODE *)0; /* Task is not pending on an event flag */ + 8011a34: e0bffe17 ldw r2,-8(fp) + 8011a38: 10000a15 stw zero,40(r2) +#endif + +#if (OS_MBOX_EN > 0) || ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) + ptcb->OSTCBMsg = (void *)0; /* No message received */ + 8011a3c: e0bffe17 ldw r2,-8(fp) + 8011a40: 10000915 stw zero,36(r2) +#endif + +#if OS_TASK_PROFILE_EN > 0 + ptcb->OSTCBCtxSwCtr = 0L; /* Initialize profiling variables */ + 8011a44: e0bffe17 ldw r2,-8(fp) + 8011a48: 10000e15 stw zero,56(r2) + ptcb->OSTCBCyclesStart = 0L; + 8011a4c: e0bffe17 ldw r2,-8(fp) + 8011a50: 10001015 stw zero,64(r2) + ptcb->OSTCBCyclesTot = 0L; + 8011a54: e0bffe17 ldw r2,-8(fp) + 8011a58: 10000f15 stw zero,60(r2) + ptcb->OSTCBStkBase = (OS_STK *)0; + 8011a5c: e0bffe17 ldw r2,-8(fp) + 8011a60: 10001115 stw zero,68(r2) + ptcb->OSTCBStkUsed = 0L; + 8011a64: e0bffe17 ldw r2,-8(fp) + 8011a68: 10001215 stw zero,72(r2) +#endif + +#if OS_TASK_NAME_SIZE > 1 + ptcb->OSTCBTaskName[0] = '?'; /* Unknown name at task creation */ + 8011a6c: e0bffe17 ldw r2,-8(fp) + 8011a70: 00c00fc4 movi r3,63 + 8011a74: 10c01305 stb r3,76(r2) + ptcb->OSTCBTaskName[1] = OS_ASCII_NUL; + 8011a78: e0bffe17 ldw r2,-8(fp) + 8011a7c: 10001345 stb zero,77(r2) +#endif + + OSTCBInitHook(ptcb); + 8011a80: e13ffe17 ldw r4,-8(fp) + 8011a84: 80386b80 call 80386b8 + + OSTaskCreateHook(ptcb); /* Call user defined hook */ + 8011a88: e13ffe17 ldw r4,-8(fp) + 8011a8c: 80385a40 call 80385a4 + NIOS2_READ_STATUS (context); + 8011a90: 0005303a rdctl r2,status + 8011a94: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8011a98: e0fffc17 ldw r3,-16(fp) + 8011a9c: 00bfff84 movi r2,-2 + 8011aa0: 1884703a and r2,r3,r2 + 8011aa4: 1001703a wrctl status,r2 + return context; + 8011aa8: e0bffc17 ldw r2,-16(fp) + + OS_ENTER_CRITICAL(); + 8011aac: e0bfff15 stw r2,-4(fp) + OSTCBPrioTbl[prio] = ptcb; + 8011ab0: e0bff803 ldbu r2,-32(fp) + 8011ab4: 100890ba slli r4,r2,2 + 8011ab8: e0fffe17 ldw r3,-8(fp) + 8011abc: 008201b4 movhi r2,2054 + 8011ac0: 2085883a add r2,r4,r2 + 8011ac4: 10f55d15 stw r3,-10892(r2) + ptcb->OSTCBNext = OSTCBList; /* Link into TCB chain */ + 8011ac8: d0e04e17 ldw r3,-32456(gp) + 8011acc: e0bffe17 ldw r2,-8(fp) + 8011ad0: 10c00515 stw r3,20(r2) + ptcb->OSTCBPrev = (OS_TCB *)0; + 8011ad4: e0bffe17 ldw r2,-8(fp) + 8011ad8: 10000615 stw zero,24(r2) + if (OSTCBList != (OS_TCB *)0) { + 8011adc: d0a04e17 ldw r2,-32456(gp) + 8011ae0: 10000326 beq r2,zero,8011af0 + OSTCBList->OSTCBPrev = ptcb; + 8011ae4: d0a04e17 ldw r2,-32456(gp) + 8011ae8: e0fffe17 ldw r3,-8(fp) + 8011aec: 10c00615 stw r3,24(r2) + } + OSTCBList = ptcb; + 8011af0: e0bffe17 ldw r2,-8(fp) + 8011af4: d0a04e15 stw r2,-32456(gp) + OSRdyGrp |= ptcb->OSTCBBitY; /* Make task ready to run */ + 8011af8: e0bffe17 ldw r2,-8(fp) + 8011afc: 10c00d83 ldbu r3,54(r2) + 8011b00: d0a05503 ldbu r2,-32428(gp) + 8011b04: 1884b03a or r2,r3,r2 + 8011b08: d0a05505 stb r2,-32428(gp) + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + 8011b0c: e0bffe17 ldw r2,-8(fp) + 8011b10: 10800d03 ldbu r2,52(r2) + 8011b14: 10c03fcc andi r3,r2,255 + 8011b18: d0a05544 addi r2,gp,-32427 + 8011b1c: 1885883a add r2,r3,r2 + 8011b20: 11000003 ldbu r4,0(r2) + 8011b24: e0bffe17 ldw r2,-8(fp) + 8011b28: 10800d43 ldbu r2,53(r2) + 8011b2c: e0fffe17 ldw r3,-8(fp) + 8011b30: 18c00d03 ldbu r3,52(r3) + 8011b34: 18c03fcc andi r3,r3,255 + 8011b38: 2084b03a or r2,r4,r2 + 8011b3c: 1009883a mov r4,r2 + 8011b40: d0a05544 addi r2,gp,-32427 + 8011b44: 1885883a add r2,r3,r2 + 8011b48: 11000005 stb r4,0(r2) + OSTaskCtr++; /* Increment the #tasks counter */ + 8011b4c: d0a05103 ldbu r2,-32444(gp) + 8011b50: 10800044 addi r2,r2,1 + 8011b54: d0a05105 stb r2,-32444(gp) + 8011b58: e0bfff17 ldw r2,-4(fp) + 8011b5c: e0bffa15 stw r2,-24(fp) + NIOS2_WRITE_STATUS (context); + 8011b60: e0bffa17 ldw r2,-24(fp) + 8011b64: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 8011b68: 0005883a mov r2,zero + 8011b6c: 00000506 br 8011b84 + 8011b70: e0bfff17 ldw r2,-4(fp) + 8011b74: e0bff915 stw r2,-28(fp) + 8011b78: e0bff917 ldw r2,-28(fp) + 8011b7c: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NO_MORE_TCB); + 8011b80: 00801084 movi r2,66 +} + 8011b84: e037883a mov sp,fp + 8011b88: dfc00117 ldw ra,4(sp) + 8011b8c: df000017 ldw fp,0(sp) + 8011b90: dec00204 addi sp,sp,8 + 8011b94: f800283a ret + +08011b98 : +********************************************************************************************************* +*/ + +#if OS_FLAG_ACCEPT_EN > 0 +OS_FLAGS OSFlagAccept (OS_FLAG_GRP *pgrp, OS_FLAGS flags, INT8U wait_type, INT8U *perr) +{ + 8011b98: defff204 addi sp,sp,-56 + 8011b9c: df000d15 stw fp,52(sp) + 8011ba0: df000d04 addi fp,sp,52 + 8011ba4: e13ff615 stw r4,-40(fp) + 8011ba8: 2805883a mov r2,r5 + 8011bac: 3007883a mov r3,r6 + 8011bb0: e1fff315 stw r7,-52(fp) + 8011bb4: e0bff50d sth r2,-44(fp) + 8011bb8: 1805883a mov r2,r3 + 8011bbc: e0bff405 stb r2,-48(fp) + OS_FLAGS flags_rdy; + INT8U result; + BOOLEAN consume; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8011bc0: e03ffe15 stw zero,-8(fp) + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + *perr = OS_ERR_FLAG_INVALID_PGRP; + return ((OS_FLAGS)0); + } +#endif + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event block type */ + 8011bc4: e0bff617 ldw r2,-40(fp) + 8011bc8: 10800003 ldbu r2,0(r2) + 8011bcc: 10803fcc andi r2,r2,255 + 8011bd0: 10800160 cmpeqi r2,r2,5 + 8011bd4: 1000051e bne r2,zero,8011bec + *perr = OS_ERR_EVENT_TYPE; + 8011bd8: e0bff317 ldw r2,-52(fp) + 8011bdc: 00c00044 movi r3,1 + 8011be0: 10c00005 stb r3,0(r2) + return ((OS_FLAGS)0); + 8011be4: 0005883a mov r2,zero + 8011be8: 00009f06 br 8011e68 + } + result = (INT8U)(wait_type & OS_FLAG_CONSUME); + 8011bec: e0fff403 ldbu r3,-48(fp) + 8011bf0: 00bfe004 movi r2,-128 + 8011bf4: 1884703a and r2,r3,r2 + 8011bf8: e0bffdc5 stb r2,-9(fp) + if (result != (INT8U)0) { /* See if we need to consume the flags */ + 8011bfc: e0bffdc3 ldbu r2,-9(fp) + 8011c00: 10000626 beq r2,zero,8011c1c + wait_type &= ~OS_FLAG_CONSUME; + 8011c04: e0bff403 ldbu r2,-48(fp) + 8011c08: 10801fcc andi r2,r2,127 + 8011c0c: e0bff405 stb r2,-48(fp) + consume = OS_TRUE; + 8011c10: 00800044 movi r2,1 + 8011c14: e0bfff45 stb r2,-3(fp) + 8011c18: 00000106 br 8011c20 + } else { + consume = OS_FALSE; + 8011c1c: e03fff45 stb zero,-3(fp) + } +/*$PAGE*/ + *perr = OS_ERR_NONE; /* Assume NO error until proven otherwise. */ + 8011c20: e0bff317 ldw r2,-52(fp) + 8011c24: 10000005 stb zero,0(r2) + NIOS2_READ_STATUS (context); + 8011c28: 0005303a rdctl r2,status + 8011c2c: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8011c30: e0fffc17 ldw r3,-16(fp) + 8011c34: 00bfff84 movi r2,-2 + 8011c38: 1884703a and r2,r3,r2 + 8011c3c: 1001703a wrctl status,r2 + return context; + 8011c40: e0bffc17 ldw r2,-16(fp) + OS_ENTER_CRITICAL(); + 8011c44: e0bffe15 stw r2,-8(fp) + switch (wait_type) { + 8011c48: e0bff403 ldbu r2,-48(fp) + 8011c4c: 10c00060 cmpeqi r3,r2,1 + 8011c50: 18005f1e bne r3,zero,8011dd0 + 8011c54: 10c00088 cmpgei r3,r2,2 + 8011c58: 1800021e bne r3,zero,8011c64 + 8011c5c: 10003f26 beq r2,zero,8011d5c + 8011c60: 00007706 br 8011e40 + 8011c64: 10c000a0 cmpeqi r3,r2,2 + 8011c68: 1800031e bne r3,zero,8011c78 + 8011c6c: 108000e0 cmpeqi r2,r2,3 + 8011c70: 10001e1e bne r2,zero,8011cec + 8011c74: 00007206 br 8011e40 + case OS_FLAG_WAIT_SET_ALL: /* See if all required flags are set */ + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 8011c78: e0bff617 ldw r2,-40(fp) + 8011c7c: 1080020b ldhu r2,8(r2) + 8011c80: e0fff50b ldhu r3,-44(fp) + 8011c84: 1884703a and r2,r3,r2 + 8011c88: e0bfff8d sth r2,-2(fp) + if (flags_rdy == flags) { /* Must match ALL the bits that we want */ + 8011c8c: e0ffff8b ldhu r3,-2(fp) + 8011c90: e0bff50b ldhu r2,-44(fp) + 8011c94: 18800d1e bne r3,r2,8011ccc + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 8011c98: e0bfff43 ldbu r2,-3(fp) + 8011c9c: 10800058 cmpnei r2,r2,1 + 8011ca0: 10000d1e bne r2,zero,8011cd8 + pgrp->OSFlagFlags &= ~flags_rdy; /* Clear ONLY the flags that we wanted */ + 8011ca4: e0bff617 ldw r2,-40(fp) + 8011ca8: 1080020b ldhu r2,8(r2) + 8011cac: 1007883a mov r3,r2 + 8011cb0: e0bfff8b ldhu r2,-2(fp) + 8011cb4: 0084303a nor r2,zero,r2 + 8011cb8: 1884703a and r2,r3,r2 + 8011cbc: 1007883a mov r3,r2 + 8011cc0: e0bff617 ldw r2,-40(fp) + 8011cc4: 10c0020d sth r3,8(r2) + 8011cc8: 00000306 br 8011cd8 + } + } else { + *perr = OS_ERR_FLAG_NOT_RDY; + 8011ccc: e0bff317 ldw r2,-52(fp) + 8011cd0: 00c01c04 movi r3,112 + 8011cd4: 10c00005 stb r3,0(r2) + 8011cd8: e0bffe17 ldw r2,-8(fp) + 8011cdc: e0bffb15 stw r2,-20(fp) + NIOS2_WRITE_STATUS (context); + 8011ce0: e0bffb17 ldw r2,-20(fp) + 8011ce4: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + break; + 8011ce8: 00005e06 br 8011e64 + + case OS_FLAG_WAIT_SET_ANY: + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 8011cec: e0bff617 ldw r2,-40(fp) + 8011cf0: 1080020b ldhu r2,8(r2) + 8011cf4: e0fff50b ldhu r3,-44(fp) + 8011cf8: 1884703a and r2,r3,r2 + 8011cfc: e0bfff8d sth r2,-2(fp) + if (flags_rdy != (OS_FLAGS)0) { /* See if any flag set */ + 8011d00: e0bfff8b ldhu r2,-2(fp) + 8011d04: 10000d26 beq r2,zero,8011d3c + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 8011d08: e0bfff43 ldbu r2,-3(fp) + 8011d0c: 10800058 cmpnei r2,r2,1 + 8011d10: 10000d1e bne r2,zero,8011d48 + pgrp->OSFlagFlags &= ~flags_rdy; /* Clear ONLY the flags that we got */ + 8011d14: e0bff617 ldw r2,-40(fp) + 8011d18: 1080020b ldhu r2,8(r2) + 8011d1c: 1007883a mov r3,r2 + 8011d20: e0bfff8b ldhu r2,-2(fp) + 8011d24: 0084303a nor r2,zero,r2 + 8011d28: 1884703a and r2,r3,r2 + 8011d2c: 1007883a mov r3,r2 + 8011d30: e0bff617 ldw r2,-40(fp) + 8011d34: 10c0020d sth r3,8(r2) + 8011d38: 00000306 br 8011d48 + } + } else { + *perr = OS_ERR_FLAG_NOT_RDY; + 8011d3c: e0bff317 ldw r2,-52(fp) + 8011d40: 00c01c04 movi r3,112 + 8011d44: 10c00005 stb r3,0(r2) + 8011d48: e0bffe17 ldw r2,-8(fp) + 8011d4c: e0bffa15 stw r2,-24(fp) + 8011d50: e0bffa17 ldw r2,-24(fp) + 8011d54: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + break; + 8011d58: 00004206 br 8011e64 + +#if OS_FLAG_WAIT_CLR_EN > 0 + case OS_FLAG_WAIT_CLR_ALL: /* See if all required flags are cleared */ + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 8011d5c: e0bff617 ldw r2,-40(fp) + 8011d60: 1080020b ldhu r2,8(r2) + 8011d64: 0084303a nor r2,zero,r2 + 8011d68: 1007883a mov r3,r2 + 8011d6c: e0bff50b ldhu r2,-44(fp) + 8011d70: 1884703a and r2,r3,r2 + 8011d74: e0bfff8d sth r2,-2(fp) + if (flags_rdy == flags) { /* Must match ALL the bits that we want */ + 8011d78: e0ffff8b ldhu r3,-2(fp) + 8011d7c: e0bff50b ldhu r2,-44(fp) + 8011d80: 18800b1e bne r3,r2,8011db0 + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 8011d84: e0bfff43 ldbu r2,-3(fp) + 8011d88: 10800058 cmpnei r2,r2,1 + 8011d8c: 10000b1e bne r2,zero,8011dbc + pgrp->OSFlagFlags |= flags_rdy; /* Set ONLY the flags that we wanted */ + 8011d90: e0bff617 ldw r2,-40(fp) + 8011d94: 1080020b ldhu r2,8(r2) + 8011d98: e0ffff8b ldhu r3,-2(fp) + 8011d9c: 1884b03a or r2,r3,r2 + 8011da0: 1007883a mov r3,r2 + 8011da4: e0bff617 ldw r2,-40(fp) + 8011da8: 10c0020d sth r3,8(r2) + 8011dac: 00000306 br 8011dbc + } + } else { + *perr = OS_ERR_FLAG_NOT_RDY; + 8011db0: e0bff317 ldw r2,-52(fp) + 8011db4: 00c01c04 movi r3,112 + 8011db8: 10c00005 stb r3,0(r2) + 8011dbc: e0bffe17 ldw r2,-8(fp) + 8011dc0: e0bff915 stw r2,-28(fp) + 8011dc4: e0bff917 ldw r2,-28(fp) + 8011dc8: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + break; + 8011dcc: 00002506 br 8011e64 + + case OS_FLAG_WAIT_CLR_ANY: + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 8011dd0: e0bff617 ldw r2,-40(fp) + 8011dd4: 1080020b ldhu r2,8(r2) + 8011dd8: 0084303a nor r2,zero,r2 + 8011ddc: 1007883a mov r3,r2 + 8011de0: e0bff50b ldhu r2,-44(fp) + 8011de4: 1884703a and r2,r3,r2 + 8011de8: e0bfff8d sth r2,-2(fp) + if (flags_rdy != (OS_FLAGS)0) { /* See if any flag cleared */ + 8011dec: e0bfff8b ldhu r2,-2(fp) + 8011df0: 10000b26 beq r2,zero,8011e20 + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 8011df4: e0bfff43 ldbu r2,-3(fp) + 8011df8: 10800058 cmpnei r2,r2,1 + 8011dfc: 10000b1e bne r2,zero,8011e2c + pgrp->OSFlagFlags |= flags_rdy; /* Set ONLY the flags that we got */ + 8011e00: e0bff617 ldw r2,-40(fp) + 8011e04: 1080020b ldhu r2,8(r2) + 8011e08: e0ffff8b ldhu r3,-2(fp) + 8011e0c: 1884b03a or r2,r3,r2 + 8011e10: 1007883a mov r3,r2 + 8011e14: e0bff617 ldw r2,-40(fp) + 8011e18: 10c0020d sth r3,8(r2) + 8011e1c: 00000306 br 8011e2c + } + } else { + *perr = OS_ERR_FLAG_NOT_RDY; + 8011e20: e0bff317 ldw r2,-52(fp) + 8011e24: 00c01c04 movi r3,112 + 8011e28: 10c00005 stb r3,0(r2) + 8011e2c: e0bffe17 ldw r2,-8(fp) + 8011e30: e0bff815 stw r2,-32(fp) + 8011e34: e0bff817 ldw r2,-32(fp) + 8011e38: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + break; + 8011e3c: 00000906 br 8011e64 + 8011e40: e0bffe17 ldw r2,-8(fp) + 8011e44: e0bff715 stw r2,-36(fp) + 8011e48: e0bff717 ldw r2,-36(fp) + 8011e4c: 1001703a wrctl status,r2 +#endif + + default: + OS_EXIT_CRITICAL(); + flags_rdy = (OS_FLAGS)0; + 8011e50: e03fff8d sth zero,-2(fp) + *perr = OS_ERR_FLAG_WAIT_TYPE; + 8011e54: e0bff317 ldw r2,-52(fp) + 8011e58: 00c01bc4 movi r3,111 + 8011e5c: 10c00005 stb r3,0(r2) + break; + 8011e60: 0001883a nop + } + return (flags_rdy); + 8011e64: e0bfff8b ldhu r2,-2(fp) +} + 8011e68: e037883a mov sp,fp + 8011e6c: df000017 ldw fp,0(sp) + 8011e70: dec00104 addi sp,sp,4 + 8011e74: f800283a ret + +08011e78 : +* Called from: Task ONLY +********************************************************************************************************* +*/ + +OS_FLAG_GRP *OSFlagCreate (OS_FLAGS flags, INT8U *perr) +{ + 8011e78: defff804 addi sp,sp,-32 + 8011e7c: df000715 stw fp,28(sp) + 8011e80: df000704 addi fp,sp,28 + 8011e84: 2005883a mov r2,r4 + 8011e88: e17ff915 stw r5,-28(fp) + 8011e8c: e0bffa0d sth r2,-24(fp) + OS_FLAG_GRP *pgrp; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8011e90: e03fff15 stw zero,-4(fp) +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return ((OS_FLAG_GRP *)0); + } +#endif + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 8011e94: d0a05703 ldbu r2,-32420(gp) + 8011e98: 10803fcc andi r2,r2,255 + 8011e9c: 10000526 beq r2,zero,8011eb4 + *perr = OS_ERR_CREATE_ISR; /* ... can't CREATE from an ISR */ + 8011ea0: e0bff917 ldw r2,-28(fp) + 8011ea4: 00c00404 movi r3,16 + 8011ea8: 10c00005 stb r3,0(r2) + return ((OS_FLAG_GRP *)0); + 8011eac: 0005883a mov r2,zero + 8011eb0: 00002b06 br 8011f60 + NIOS2_READ_STATUS (context); + 8011eb4: 0005303a rdctl r2,status + 8011eb8: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8011ebc: e0fffd17 ldw r3,-12(fp) + 8011ec0: 00bfff84 movi r2,-2 + 8011ec4: 1884703a and r2,r3,r2 + 8011ec8: 1001703a wrctl status,r2 + return context; + 8011ecc: e0bffd17 ldw r2,-12(fp) + } + OS_ENTER_CRITICAL(); + 8011ed0: e0bfff15 stw r2,-4(fp) + pgrp = OSFlagFreeList; /* Get next free event flag */ + 8011ed4: d0a05a17 ldw r2,-32408(gp) + 8011ed8: e0bffe15 stw r2,-8(fp) + if (pgrp != (OS_FLAG_GRP *)0) { /* See if we have event flag groups available */ + 8011edc: e0bffe17 ldw r2,-8(fp) + 8011ee0: 10001726 beq r2,zero,8011f40 + /* Adjust free list */ + OSFlagFreeList = (OS_FLAG_GRP *)OSFlagFreeList->OSFlagWaitList; + 8011ee4: d0a05a17 ldw r2,-32408(gp) + 8011ee8: 10800117 ldw r2,4(r2) + 8011eec: d0a05a15 stw r2,-32408(gp) + pgrp->OSFlagType = OS_EVENT_TYPE_FLAG; /* Set to event flag group type */ + 8011ef0: e0bffe17 ldw r2,-8(fp) + 8011ef4: 00c00144 movi r3,5 + 8011ef8: 10c00005 stb r3,0(r2) + pgrp->OSFlagFlags = flags; /* Set to desired initial value */ + 8011efc: e0bffe17 ldw r2,-8(fp) + 8011f00: e0fffa0b ldhu r3,-24(fp) + 8011f04: 10c0020d sth r3,8(r2) + pgrp->OSFlagWaitList = (void *)0; /* Clear list of tasks waiting on flags */ + 8011f08: e0bffe17 ldw r2,-8(fp) + 8011f0c: 10000115 stw zero,4(r2) +#if OS_FLAG_NAME_SIZE > 1 + pgrp->OSFlagName[0] = '?'; + 8011f10: e0bffe17 ldw r2,-8(fp) + 8011f14: 00c00fc4 movi r3,63 + 8011f18: 10c00285 stb r3,10(r2) + pgrp->OSFlagName[1] = OS_ASCII_NUL; + 8011f1c: e0bffe17 ldw r2,-8(fp) + 8011f20: 100002c5 stb zero,11(r2) + 8011f24: e0bfff17 ldw r2,-4(fp) + 8011f28: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 8011f2c: e0bffc17 ldw r2,-16(fp) + 8011f30: 1001703a wrctl status,r2 +#endif + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 8011f34: e0bff917 ldw r2,-28(fp) + 8011f38: 10000005 stb zero,0(r2) + 8011f3c: 00000706 br 8011f5c + 8011f40: e0bfff17 ldw r2,-4(fp) + 8011f44: e0bffb15 stw r2,-20(fp) + 8011f48: e0bffb17 ldw r2,-20(fp) + 8011f4c: 1001703a wrctl status,r2 + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_FLAG_GRP_DEPLETED; + 8011f50: e0bff917 ldw r2,-28(fp) + 8011f54: 00c01c84 movi r3,114 + 8011f58: 10c00005 stb r3,0(r2) + } + return (pgrp); /* Return pointer to event flag group */ + 8011f5c: e0bffe17 ldw r2,-8(fp) +} + 8011f60: e037883a mov sp,fp + 8011f64: df000017 ldw fp,0(sp) + 8011f68: dec00104 addi sp,sp,4 + 8011f6c: f800283a ret + +08011f70 : +********************************************************************************************************* +*/ + +#if OS_FLAG_DEL_EN > 0 +OS_FLAG_GRP *OSFlagDel (OS_FLAG_GRP *pgrp, INT8U opt, INT8U *perr) +{ + 8011f70: defff204 addi sp,sp,-56 + 8011f74: dfc00d15 stw ra,52(sp) + 8011f78: df000c15 stw fp,48(sp) + 8011f7c: df000c04 addi fp,sp,48 + 8011f80: e13ff615 stw r4,-40(fp) + 8011f84: 2805883a mov r2,r5 + 8011f88: e1bff415 stw r6,-48(fp) + 8011f8c: e0bff505 stb r2,-44(fp) + BOOLEAN tasks_waiting; + OS_FLAG_NODE *pnode; + OS_FLAG_GRP *pgrp_return; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8011f90: e03ffc15 stw zero,-16(fp) + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + *perr = OS_ERR_FLAG_INVALID_PGRP; + return (pgrp); + } +#endif + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 8011f94: d0a05703 ldbu r2,-32420(gp) + 8011f98: 10803fcc andi r2,r2,255 + 8011f9c: 10000526 beq r2,zero,8011fb4 + *perr = OS_ERR_DEL_ISR; /* ... can't DELETE from an ISR */ + 8011fa0: e0bff417 ldw r2,-48(fp) + 8011fa4: 00c003c4 movi r3,15 + 8011fa8: 10c00005 stb r3,0(r2) + return (pgrp); + 8011fac: e0bff617 ldw r2,-40(fp) + 8011fb0: 00007106 br 8012178 + } + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event group type */ + 8011fb4: e0bff617 ldw r2,-40(fp) + 8011fb8: 10800003 ldbu r2,0(r2) + 8011fbc: 10803fcc andi r2,r2,255 + 8011fc0: 10800160 cmpeqi r2,r2,5 + 8011fc4: 1000051e bne r2,zero,8011fdc + *perr = OS_ERR_EVENT_TYPE; + 8011fc8: e0bff417 ldw r2,-48(fp) + 8011fcc: 00c00044 movi r3,1 + 8011fd0: 10c00005 stb r3,0(r2) + return (pgrp); + 8011fd4: e0bff617 ldw r2,-40(fp) + 8011fd8: 00006706 br 8012178 + NIOS2_READ_STATUS (context); + 8011fdc: 0005303a rdctl r2,status + 8011fe0: e0bffb15 stw r2,-20(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8011fe4: e0fffb17 ldw r3,-20(fp) + 8011fe8: 00bfff84 movi r2,-2 + 8011fec: 1884703a and r2,r3,r2 + 8011ff0: 1001703a wrctl status,r2 + return context; + 8011ff4: e0bffb17 ldw r2,-20(fp) + } + OS_ENTER_CRITICAL(); + 8011ff8: e0bffc15 stw r2,-16(fp) + if (pgrp->OSFlagWaitList != (void *)0) { /* See if any tasks waiting on event flags */ + 8011ffc: e0bff617 ldw r2,-40(fp) + 8012000: 10800117 ldw r2,4(r2) + 8012004: 10000326 beq r2,zero,8012014 + tasks_waiting = OS_TRUE; /* Yes */ + 8012008: 00800044 movi r2,1 + 801200c: e0bfffc5 stb r2,-1(fp) + 8012010: 00000106 br 8012018 + } else { + tasks_waiting = OS_FALSE; /* No */ + 8012014: e03fffc5 stb zero,-1(fp) + } + switch (opt) { + 8012018: e0bff503 ldbu r2,-44(fp) + 801201c: 10000326 beq r2,zero,801202c + 8012020: 10800060 cmpeqi r2,r2,1 + 8012024: 1000231e bne r2,zero,80120b4 + 8012028: 00004806 br 801214c + case OS_DEL_NO_PEND: /* Delete group if no task waiting */ + if (tasks_waiting == OS_FALSE) { + 801202c: e0bfffc3 ldbu r2,-1(fp) + 8012030: 1000161e bne r2,zero,801208c +#if OS_FLAG_NAME_SIZE > 1 + pgrp->OSFlagName[0] = '?'; /* Unknown name */ + 8012034: e0bff617 ldw r2,-40(fp) + 8012038: 00c00fc4 movi r3,63 + 801203c: 10c00285 stb r3,10(r2) + pgrp->OSFlagName[1] = OS_ASCII_NUL; + 8012040: e0bff617 ldw r2,-40(fp) + 8012044: 100002c5 stb zero,11(r2) +#endif + pgrp->OSFlagType = OS_EVENT_TYPE_UNUSED; + 8012048: e0bff617 ldw r2,-40(fp) + 801204c: 10000005 stb zero,0(r2) + pgrp->OSFlagWaitList = (void *)OSFlagFreeList; /* Return group to free list */ + 8012050: d0e05a17 ldw r3,-32408(gp) + 8012054: e0bff617 ldw r2,-40(fp) + 8012058: 10c00115 stw r3,4(r2) + pgrp->OSFlagFlags = (OS_FLAGS)0; + 801205c: e0bff617 ldw r2,-40(fp) + 8012060: 1000020d sth zero,8(r2) + OSFlagFreeList = pgrp; + 8012064: e0bff617 ldw r2,-40(fp) + 8012068: d0a05a15 stw r2,-32408(gp) + 801206c: e0bffc17 ldw r2,-16(fp) + 8012070: e0bffa15 stw r2,-24(fp) + NIOS2_WRITE_STATUS (context); + 8012074: e0bffa17 ldw r2,-24(fp) + 8012078: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 801207c: e0bff417 ldw r2,-48(fp) + 8012080: 10000005 stb zero,0(r2) + pgrp_return = (OS_FLAG_GRP *)0; /* Event Flag Group has been deleted */ + 8012084: e03ffd15 stw zero,-12(fp) + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_WAITING; + pgrp_return = pgrp; + } + break; + 8012088: 00003a06 br 8012174 + 801208c: e0bffc17 ldw r2,-16(fp) + 8012090: e0bff915 stw r2,-28(fp) + 8012094: e0bff917 ldw r2,-28(fp) + 8012098: 1001703a wrctl status,r2 + *perr = OS_ERR_TASK_WAITING; + 801209c: e0bff417 ldw r2,-48(fp) + 80120a0: 00c01244 movi r3,73 + 80120a4: 10c00005 stb r3,0(r2) + pgrp_return = pgrp; + 80120a8: e0bff617 ldw r2,-40(fp) + 80120ac: e0bffd15 stw r2,-12(fp) + break; + 80120b0: 00003006 br 8012174 + + case OS_DEL_ALWAYS: /* Always delete the event flag group */ + pnode = (OS_FLAG_NODE *)pgrp->OSFlagWaitList; + 80120b4: e0bff617 ldw r2,-40(fp) + 80120b8: 10800117 ldw r2,4(r2) + 80120bc: e0bffe15 stw r2,-8(fp) + while (pnode != (OS_FLAG_NODE *)0) { /* Ready ALL tasks waiting for flags */ + 80120c0: 00000606 br 80120dc + (void)OS_FlagTaskRdy(pnode, (OS_FLAGS)0); + 80120c4: 000b883a mov r5,zero + 80120c8: e13ffe17 ldw r4,-8(fp) + 80120cc: 8012fb80 call 8012fb8 + pnode = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; + 80120d0: e0bffe17 ldw r2,-8(fp) + 80120d4: 10800017 ldw r2,0(r2) + 80120d8: e0bffe15 stw r2,-8(fp) + while (pnode != (OS_FLAG_NODE *)0) { /* Ready ALL tasks waiting for flags */ + 80120dc: e0bffe17 ldw r2,-8(fp) + 80120e0: 103ff81e bne r2,zero,80120c4 + } +#if OS_FLAG_NAME_SIZE > 1 + pgrp->OSFlagName[0] = '?'; /* Unknown name */ + 80120e4: e0bff617 ldw r2,-40(fp) + 80120e8: 00c00fc4 movi r3,63 + 80120ec: 10c00285 stb r3,10(r2) + pgrp->OSFlagName[1] = OS_ASCII_NUL; + 80120f0: e0bff617 ldw r2,-40(fp) + 80120f4: 100002c5 stb zero,11(r2) +#endif + pgrp->OSFlagType = OS_EVENT_TYPE_UNUSED; + 80120f8: e0bff617 ldw r2,-40(fp) + 80120fc: 10000005 stb zero,0(r2) + pgrp->OSFlagWaitList = (void *)OSFlagFreeList;/* Return group to free list */ + 8012100: d0e05a17 ldw r3,-32408(gp) + 8012104: e0bff617 ldw r2,-40(fp) + 8012108: 10c00115 stw r3,4(r2) + pgrp->OSFlagFlags = (OS_FLAGS)0; + 801210c: e0bff617 ldw r2,-40(fp) + 8012110: 1000020d sth zero,8(r2) + OSFlagFreeList = pgrp; + 8012114: e0bff617 ldw r2,-40(fp) + 8012118: d0a05a15 stw r2,-32408(gp) + 801211c: e0bffc17 ldw r2,-16(fp) + 8012120: e0bff815 stw r2,-32(fp) + 8012124: e0bff817 ldw r2,-32(fp) + 8012128: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (tasks_waiting == OS_TRUE) { /* Reschedule only if task(s) were waiting */ + 801212c: e0bfffc3 ldbu r2,-1(fp) + 8012130: 10800058 cmpnei r2,r2,1 + 8012134: 1000011e bne r2,zero,801213c + OS_Sched(); /* Find highest priority task ready to run */ + 8012138: 801166c0 call 801166c + } + *perr = OS_ERR_NONE; + 801213c: e0bff417 ldw r2,-48(fp) + 8012140: 10000005 stb zero,0(r2) + pgrp_return = (OS_FLAG_GRP *)0; /* Event Flag Group has been deleted */ + 8012144: e03ffd15 stw zero,-12(fp) + break; + 8012148: 00000a06 br 8012174 + 801214c: e0bffc17 ldw r2,-16(fp) + 8012150: e0bff715 stw r2,-36(fp) + 8012154: e0bff717 ldw r2,-36(fp) + 8012158: 1001703a wrctl status,r2 + + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_INVALID_OPT; + 801215c: e0bff417 ldw r2,-48(fp) + 8012160: 00c001c4 movi r3,7 + 8012164: 10c00005 stb r3,0(r2) + pgrp_return = pgrp; + 8012168: e0bff617 ldw r2,-40(fp) + 801216c: e0bffd15 stw r2,-12(fp) + break; + 8012170: 0001883a nop + } + return (pgrp_return); + 8012174: e0bffd17 ldw r2,-12(fp) +} + 8012178: e037883a mov sp,fp + 801217c: dfc00117 ldw ra,4(sp) + 8012180: df000017 ldw fp,0(sp) + 8012184: dec00204 addi sp,sp,8 + 8012188: f800283a ret + +0801218c : +********************************************************************************************************* +*/ + +#if OS_FLAG_NAME_SIZE > 1 +INT8U OSFlagNameGet (OS_FLAG_GRP *pgrp, INT8U *pname, INT8U *perr) +{ + 801218c: defff604 addi sp,sp,-40 + 8012190: dfc00915 stw ra,36(sp) + 8012194: df000815 stw fp,32(sp) + 8012198: df000804 addi fp,sp,32 + 801219c: e13ffa15 stw r4,-24(fp) + 80121a0: e17ff915 stw r5,-28(fp) + 80121a4: e1bff815 stw r6,-32(fp) + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 80121a8: e03fff15 stw zero,-4(fp) + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + *perr = OS_ERR_PNAME_NULL; + return (0); + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 80121ac: d0a05703 ldbu r2,-32420(gp) + 80121b0: 10803fcc andi r2,r2,255 + 80121b4: 10000526 beq r2,zero,80121cc + *perr = OS_ERR_NAME_GET_ISR; + 80121b8: e0bff817 ldw r2,-32(fp) + 80121bc: 00c00444 movi r3,17 + 80121c0: 10c00005 stb r3,0(r2) + return (0); + 80121c4: 0005883a mov r2,zero + 80121c8: 00002306 br 8012258 + NIOS2_READ_STATUS (context); + 80121cc: 0005303a rdctl r2,status + 80121d0: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 80121d4: e0fffd17 ldw r3,-12(fp) + 80121d8: 00bfff84 movi r2,-2 + 80121dc: 1884703a and r2,r3,r2 + 80121e0: 1001703a wrctl status,r2 + return context; + 80121e4: e0bffd17 ldw r2,-12(fp) + } + OS_ENTER_CRITICAL(); + 80121e8: e0bfff15 stw r2,-4(fp) + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { + 80121ec: e0bffa17 ldw r2,-24(fp) + 80121f0: 10800003 ldbu r2,0(r2) + 80121f4: 10803fcc andi r2,r2,255 + 80121f8: 10800160 cmpeqi r2,r2,5 + 80121fc: 1000091e bne r2,zero,8012224 + 8012200: e0bfff17 ldw r2,-4(fp) + 8012204: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 8012208: e0bffc17 ldw r2,-16(fp) + 801220c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_EVENT_TYPE; + 8012210: e0bff817 ldw r2,-32(fp) + 8012214: 00c00044 movi r3,1 + 8012218: 10c00005 stb r3,0(r2) + return (0); + 801221c: 0005883a mov r2,zero + 8012220: 00000d06 br 8012258 + } + len = OS_StrCopy(pname, pgrp->OSFlagName); /* Copy name from OS_FLAG_GRP */ + 8012224: e0bffa17 ldw r2,-24(fp) + 8012228: 10800284 addi r2,r2,10 + 801222c: 100b883a mov r5,r2 + 8012230: e13ff917 ldw r4,-28(fp) + 8012234: 80117a00 call 80117a0 + 8012238: e0bffec5 stb r2,-5(fp) + 801223c: e0bfff17 ldw r2,-4(fp) + 8012240: e0bffb15 stw r2,-20(fp) + 8012244: e0bffb17 ldw r2,-20(fp) + 8012248: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 801224c: e0bff817 ldw r2,-32(fp) + 8012250: 10000005 stb zero,0(r2) + return (len); + 8012254: e0bffec3 ldbu r2,-5(fp) +} + 8012258: e037883a mov sp,fp + 801225c: dfc00117 ldw ra,4(sp) + 8012260: df000017 ldw fp,0(sp) + 8012264: dec00204 addi sp,sp,8 + 8012268: f800283a ret + +0801226c : +********************************************************************************************************* +*/ + +#if OS_FLAG_NAME_SIZE > 1 +void OSFlagNameSet (OS_FLAG_GRP *pgrp, INT8U *pname, INT8U *perr) +{ + 801226c: defff504 addi sp,sp,-44 + 8012270: dfc00a15 stw ra,40(sp) + 8012274: df000915 stw fp,36(sp) + 8012278: df000904 addi fp,sp,36 + 801227c: e13ff915 stw r4,-28(fp) + 8012280: e17ff815 stw r5,-32(fp) + 8012284: e1bff715 stw r6,-36(fp) + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8012288: e03fff15 stw zero,-4(fp) + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + *perr = OS_ERR_PNAME_NULL; + return; + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 801228c: d0a05703 ldbu r2,-32420(gp) + 8012290: 10803fcc andi r2,r2,255 + 8012294: 10000426 beq r2,zero,80122a8 + *perr = OS_ERR_NAME_SET_ISR; + 8012298: e0bff717 ldw r2,-36(fp) + 801229c: 00c00484 movi r3,18 + 80122a0: 10c00005 stb r3,0(r2) + return; + 80122a4: 00002f06 br 8012364 + NIOS2_READ_STATUS (context); + 80122a8: 0005303a rdctl r2,status + 80122ac: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 80122b0: e0fffd17 ldw r3,-12(fp) + 80122b4: 00bfff84 movi r2,-2 + 80122b8: 1884703a and r2,r3,r2 + 80122bc: 1001703a wrctl status,r2 + return context; + 80122c0: e0bffd17 ldw r2,-12(fp) + } + OS_ENTER_CRITICAL(); + 80122c4: e0bfff15 stw r2,-4(fp) + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { + 80122c8: e0bff917 ldw r2,-28(fp) + 80122cc: 10800003 ldbu r2,0(r2) + 80122d0: 10803fcc andi r2,r2,255 + 80122d4: 10800160 cmpeqi r2,r2,5 + 80122d8: 1000081e bne r2,zero,80122fc + 80122dc: e0bfff17 ldw r2,-4(fp) + 80122e0: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 80122e4: e0bffc17 ldw r2,-16(fp) + 80122e8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_EVENT_TYPE; + 80122ec: e0bff717 ldw r2,-36(fp) + 80122f0: 00c00044 movi r3,1 + 80122f4: 10c00005 stb r3,0(r2) + return; + 80122f8: 00001a06 br 8012364 + } + len = OS_StrLen(pname); /* Can we fit the string in the storage area? */ + 80122fc: e13ff817 ldw r4,-32(fp) + 8012300: 80118140 call 8011814 + 8012304: e0bffec5 stb r2,-5(fp) + if (len > (OS_FLAG_NAME_SIZE - 1)) { /* No */ + 8012308: e0bffec3 ldbu r2,-5(fp) + 801230c: 10800830 cmpltui r2,r2,32 + 8012310: 1000081e bne r2,zero,8012334 + 8012314: e0bfff17 ldw r2,-4(fp) + 8012318: e0bffb15 stw r2,-20(fp) + 801231c: e0bffb17 ldw r2,-20(fp) + 8012320: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_FLAG_NAME_TOO_LONG; + 8012324: e0bff717 ldw r2,-36(fp) + 8012328: 00c01cc4 movi r3,115 + 801232c: 10c00005 stb r3,0(r2) + return; + 8012330: 00000c06 br 8012364 + } + (void)OS_StrCopy(pgrp->OSFlagName, pname); /* Yes, copy name from OS_FLAG_GRP */ + 8012334: e0bff917 ldw r2,-28(fp) + 8012338: 10800284 addi r2,r2,10 + 801233c: e17ff817 ldw r5,-32(fp) + 8012340: 1009883a mov r4,r2 + 8012344: 80117a00 call 80117a0 + 8012348: e0bfff17 ldw r2,-4(fp) + 801234c: e0bffa15 stw r2,-24(fp) + 8012350: e0bffa17 ldw r2,-24(fp) + 8012354: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 8012358: e0bff717 ldw r2,-36(fp) + 801235c: 10000005 stb zero,0(r2) + return; + 8012360: 0001883a nop +} + 8012364: e037883a mov sp,fp + 8012368: dfc00117 ldw ra,4(sp) + 801236c: df000017 ldw fp,0(sp) + 8012370: dec00204 addi sp,sp,8 + 8012374: f800283a ret + +08012378 : +* event flags. +********************************************************************************************************* +*/ + +OS_FLAGS OSFlagPend (OS_FLAG_GRP *pgrp, OS_FLAGS flags, INT8U wait_type, INT16U timeout, INT8U *perr) +{ + 8012378: deffe204 addi sp,sp,-120 + 801237c: dfc01d15 stw ra,116(sp) + 8012380: df001c15 stw fp,112(sp) + 8012384: df001c04 addi fp,sp,112 + 8012388: e13fe815 stw r4,-96(fp) + 801238c: 2805883a mov r2,r5 + 8012390: 3009883a mov r4,r6 + 8012394: 3807883a mov r3,r7 + 8012398: e0bfe70d sth r2,-100(fp) + 801239c: 2005883a mov r2,r4 + 80123a0: e0bfe605 stb r2,-104(fp) + 80123a4: 1805883a mov r2,r3 + 80123a8: e0bfe50d sth r2,-108(fp) + OS_FLAGS flags_rdy; + INT8U result; + INT8U pend_stat; + BOOLEAN consume; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 80123ac: e03ffe15 stw zero,-8(fp) + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + *perr = OS_ERR_FLAG_INVALID_PGRP; + return ((OS_FLAGS)0); + } +#endif + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 80123b0: d0a05703 ldbu r2,-32420(gp) + 80123b4: 10803fcc andi r2,r2,255 + 80123b8: 10000526 beq r2,zero,80123d0 + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + 80123bc: e0800217 ldw r2,8(fp) + 80123c0: 00c00084 movi r3,2 + 80123c4: 10c00005 stb r3,0(r2) + return ((OS_FLAGS)0); + 80123c8: 0005883a mov r2,zero + 80123cc: 00014b06 br 80128fc + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + 80123d0: d0a04b03 ldbu r2,-32468(gp) + 80123d4: 10803fcc andi r2,r2,255 + 80123d8: 10000526 beq r2,zero,80123f0 + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + 80123dc: e0800217 ldw r2,8(fp) + 80123e0: 00c00344 movi r3,13 + 80123e4: 10c00005 stb r3,0(r2) + return ((OS_FLAGS)0); + 80123e8: 0005883a mov r2,zero + 80123ec: 00014306 br 80128fc + } + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event block type */ + 80123f0: e0bfe817 ldw r2,-96(fp) + 80123f4: 10800003 ldbu r2,0(r2) + 80123f8: 10803fcc andi r2,r2,255 + 80123fc: 10800160 cmpeqi r2,r2,5 + 8012400: 1000051e bne r2,zero,8012418 + *perr = OS_ERR_EVENT_TYPE; + 8012404: e0800217 ldw r2,8(fp) + 8012408: 00c00044 movi r3,1 + 801240c: 10c00005 stb r3,0(r2) + return ((OS_FLAGS)0); + 8012410: 0005883a mov r2,zero + 8012414: 00013906 br 80128fc + } + result = (INT8U)(wait_type & OS_FLAG_CONSUME); + 8012418: e0ffe603 ldbu r3,-104(fp) + 801241c: 00bfe004 movi r2,-128 + 8012420: 1884703a and r2,r3,r2 + 8012424: e0bffdc5 stb r2,-9(fp) + if (result != (INT8U)0) { /* See if we need to consume the flags */ + 8012428: e0bffdc3 ldbu r2,-9(fp) + 801242c: 10000626 beq r2,zero,8012448 + wait_type &= ~(INT8U)OS_FLAG_CONSUME; + 8012430: e0bfe603 ldbu r2,-104(fp) + 8012434: 10801fcc andi r2,r2,127 + 8012438: e0bfe605 stb r2,-104(fp) + consume = OS_TRUE; + 801243c: 00800044 movi r2,1 + 8012440: e0bfffc5 stb r2,-1(fp) + 8012444: 00000106 br 801244c + } else { + consume = OS_FALSE; + 8012448: e03fffc5 stb zero,-1(fp) + NIOS2_READ_STATUS (context); + 801244c: 0005303a rdctl r2,status + 8012450: e0bffb15 stw r2,-20(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8012454: e0fffb17 ldw r3,-20(fp) + 8012458: 00bfff84 movi r2,-2 + 801245c: 1884703a and r2,r3,r2 + 8012460: 1001703a wrctl status,r2 + return context; + 8012464: e0bffb17 ldw r2,-20(fp) + } +/*$PAGE*/ + OS_ENTER_CRITICAL(); + 8012468: e0bffe15 stw r2,-8(fp) + switch (wait_type) { + 801246c: e0bfe603 ldbu r2,-104(fp) + 8012470: 10c00060 cmpeqi r3,r2,1 + 8012474: 1800921e bne r3,zero,80126c0 + 8012478: 10c00088 cmpgei r3,r2,2 + 801247c: 1800021e bne r3,zero,8012488 + 8012480: 10006126 beq r2,zero,8012608 + 8012484: 0000bb06 br 8012774 + 8012488: 10c000a0 cmpeqi r3,r2,2 + 801248c: 1800031e bne r3,zero,801249c + 8012490: 108000e0 cmpeqi r2,r2,3 + 8012494: 10002f1e bne r2,zero,8012554 + 8012498: 0000b606 br 8012774 + case OS_FLAG_WAIT_SET_ALL: /* See if all required flags are set */ + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 801249c: e0bfe817 ldw r2,-96(fp) + 80124a0: 1080020b ldhu r2,8(r2) + 80124a4: e0ffe70b ldhu r3,-100(fp) + 80124a8: 1884703a and r2,r3,r2 + 80124ac: e0bffd0d sth r2,-12(fp) + if (flags_rdy == flags) { /* Must match ALL the bits that we want */ + 80124b0: e0fffd0b ldhu r3,-12(fp) + 80124b4: e0bfe70b ldhu r2,-100(fp) + 80124b8: 1880171e bne r3,r2,8012518 + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 80124bc: e0bfffc3 ldbu r2,-1(fp) + 80124c0: 10800058 cmpnei r2,r2,1 + 80124c4: 1000091e bne r2,zero,80124ec + pgrp->OSFlagFlags &= ~flags_rdy; /* Clear ONLY the flags that we wanted */ + 80124c8: e0bfe817 ldw r2,-96(fp) + 80124cc: 1080020b ldhu r2,8(r2) + 80124d0: 1007883a mov r3,r2 + 80124d4: e0bffd0b ldhu r2,-12(fp) + 80124d8: 0084303a nor r2,zero,r2 + 80124dc: 1884703a and r2,r3,r2 + 80124e0: 1007883a mov r3,r2 + 80124e4: e0bfe817 ldw r2,-96(fp) + 80124e8: 10c0020d sth r3,8(r2) + } + OSTCBCur->OSTCBFlagsRdy = flags_rdy; /* Save flags that were ready */ + 80124ec: d0a05817 ldw r2,-32416(gp) + 80124f0: e0fffd0b ldhu r3,-12(fp) + 80124f4: 10c00b0d sth r3,44(r2) + 80124f8: e0bffe17 ldw r2,-8(fp) + 80124fc: e0bffa15 stw r2,-24(fp) + NIOS2_WRITE_STATUS (context); + 8012500: e0bffa17 ldw r2,-24(fp) + 8012504: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Yes, condition met, return to caller */ + *perr = OS_ERR_NONE; + 8012508: e0800217 ldw r2,8(fp) + 801250c: 10000005 stb zero,0(r2) + return (flags_rdy); + 8012510: e0bffd0b ldhu r2,-12(fp) + 8012514: 0000f906 br 80128fc + } else { /* Block task until events occur or timeout */ + OS_FlagBlock(pgrp, &node, flags, wait_type, timeout); + 8012518: e13fe70b ldhu r4,-100(fp) + 801251c: e17fe603 ldbu r5,-104(fp) + 8012520: e0bfe50b ldhu r2,-108(fp) + 8012524: e0ffe904 addi r3,fp,-92 + 8012528: d8800015 stw r2,0(sp) + 801252c: 280f883a mov r7,r5 + 8012530: 200d883a mov r6,r4 + 8012534: 180b883a mov r5,r3 + 8012538: e13fe817 ldw r4,-96(fp) + 801253c: 8012d740 call 8012d74 + 8012540: e0bffe17 ldw r2,-8(fp) + 8012544: e0bff915 stw r2,-28(fp) + 8012548: e0bff917 ldw r2,-28(fp) + 801254c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + break; + 8012550: 00009206 br 801279c + + case OS_FLAG_WAIT_SET_ANY: + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 8012554: e0bfe817 ldw r2,-96(fp) + 8012558: 1080020b ldhu r2,8(r2) + 801255c: e0ffe70b ldhu r3,-100(fp) + 8012560: 1884703a and r2,r3,r2 + 8012564: e0bffd0d sth r2,-12(fp) + if (flags_rdy != (OS_FLAGS)0) { /* See if any flag set */ + 8012568: e0bffd0b ldhu r2,-12(fp) + 801256c: 10001726 beq r2,zero,80125cc + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 8012570: e0bfffc3 ldbu r2,-1(fp) + 8012574: 10800058 cmpnei r2,r2,1 + 8012578: 1000091e bne r2,zero,80125a0 + pgrp->OSFlagFlags &= ~flags_rdy; /* Clear ONLY the flags that we got */ + 801257c: e0bfe817 ldw r2,-96(fp) + 8012580: 1080020b ldhu r2,8(r2) + 8012584: 1007883a mov r3,r2 + 8012588: e0bffd0b ldhu r2,-12(fp) + 801258c: 0084303a nor r2,zero,r2 + 8012590: 1884703a and r2,r3,r2 + 8012594: 1007883a mov r3,r2 + 8012598: e0bfe817 ldw r2,-96(fp) + 801259c: 10c0020d sth r3,8(r2) + } + OSTCBCur->OSTCBFlagsRdy = flags_rdy; /* Save flags that were ready */ + 80125a0: d0a05817 ldw r2,-32416(gp) + 80125a4: e0fffd0b ldhu r3,-12(fp) + 80125a8: 10c00b0d sth r3,44(r2) + 80125ac: e0bffe17 ldw r2,-8(fp) + 80125b0: e0bff815 stw r2,-32(fp) + 80125b4: e0bff817 ldw r2,-32(fp) + 80125b8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Yes, condition met, return to caller */ + *perr = OS_ERR_NONE; + 80125bc: e0800217 ldw r2,8(fp) + 80125c0: 10000005 stb zero,0(r2) + return (flags_rdy); + 80125c4: e0bffd0b ldhu r2,-12(fp) + 80125c8: 0000cc06 br 80128fc + } else { /* Block task until events occur or timeout */ + OS_FlagBlock(pgrp, &node, flags, wait_type, timeout); + 80125cc: e13fe70b ldhu r4,-100(fp) + 80125d0: e17fe603 ldbu r5,-104(fp) + 80125d4: e0bfe50b ldhu r2,-108(fp) + 80125d8: e0ffe904 addi r3,fp,-92 + 80125dc: d8800015 stw r2,0(sp) + 80125e0: 280f883a mov r7,r5 + 80125e4: 200d883a mov r6,r4 + 80125e8: 180b883a mov r5,r3 + 80125ec: e13fe817 ldw r4,-96(fp) + 80125f0: 8012d740 call 8012d74 + 80125f4: e0bffe17 ldw r2,-8(fp) + 80125f8: e0bff715 stw r2,-36(fp) + 80125fc: e0bff717 ldw r2,-36(fp) + 8012600: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + break; + 8012604: 00006506 br 801279c + +#if OS_FLAG_WAIT_CLR_EN > 0 + case OS_FLAG_WAIT_CLR_ALL: /* See if all required flags are cleared */ + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 8012608: e0bfe817 ldw r2,-96(fp) + 801260c: 1080020b ldhu r2,8(r2) + 8012610: 0084303a nor r2,zero,r2 + 8012614: 1007883a mov r3,r2 + 8012618: e0bfe70b ldhu r2,-100(fp) + 801261c: 1884703a and r2,r3,r2 + 8012620: e0bffd0d sth r2,-12(fp) + if (flags_rdy == flags) { /* Must match ALL the bits that we want */ + 8012624: e0fffd0b ldhu r3,-12(fp) + 8012628: e0bfe70b ldhu r2,-100(fp) + 801262c: 1880151e bne r3,r2,8012684 + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 8012630: e0bfffc3 ldbu r2,-1(fp) + 8012634: 10800058 cmpnei r2,r2,1 + 8012638: 1000071e bne r2,zero,8012658 + pgrp->OSFlagFlags |= flags_rdy; /* Set ONLY the flags that we wanted */ + 801263c: e0bfe817 ldw r2,-96(fp) + 8012640: 1080020b ldhu r2,8(r2) + 8012644: e0fffd0b ldhu r3,-12(fp) + 8012648: 1884b03a or r2,r3,r2 + 801264c: 1007883a mov r3,r2 + 8012650: e0bfe817 ldw r2,-96(fp) + 8012654: 10c0020d sth r3,8(r2) + } + OSTCBCur->OSTCBFlagsRdy = flags_rdy; /* Save flags that were ready */ + 8012658: d0a05817 ldw r2,-32416(gp) + 801265c: e0fffd0b ldhu r3,-12(fp) + 8012660: 10c00b0d sth r3,44(r2) + 8012664: e0bffe17 ldw r2,-8(fp) + 8012668: e0bff615 stw r2,-40(fp) + 801266c: e0bff617 ldw r2,-40(fp) + 8012670: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Yes, condition met, return to caller */ + *perr = OS_ERR_NONE; + 8012674: e0800217 ldw r2,8(fp) + 8012678: 10000005 stb zero,0(r2) + return (flags_rdy); + 801267c: e0bffd0b ldhu r2,-12(fp) + 8012680: 00009e06 br 80128fc + } else { /* Block task until events occur or timeout */ + OS_FlagBlock(pgrp, &node, flags, wait_type, timeout); + 8012684: e13fe70b ldhu r4,-100(fp) + 8012688: e17fe603 ldbu r5,-104(fp) + 801268c: e0bfe50b ldhu r2,-108(fp) + 8012690: e0ffe904 addi r3,fp,-92 + 8012694: d8800015 stw r2,0(sp) + 8012698: 280f883a mov r7,r5 + 801269c: 200d883a mov r6,r4 + 80126a0: 180b883a mov r5,r3 + 80126a4: e13fe817 ldw r4,-96(fp) + 80126a8: 8012d740 call 8012d74 + 80126ac: e0bffe17 ldw r2,-8(fp) + 80126b0: e0bff515 stw r2,-44(fp) + 80126b4: e0bff517 ldw r2,-44(fp) + 80126b8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + break; + 80126bc: 00003706 br 801279c + + case OS_FLAG_WAIT_CLR_ANY: + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 80126c0: e0bfe817 ldw r2,-96(fp) + 80126c4: 1080020b ldhu r2,8(r2) + 80126c8: 0084303a nor r2,zero,r2 + 80126cc: 1007883a mov r3,r2 + 80126d0: e0bfe70b ldhu r2,-100(fp) + 80126d4: 1884703a and r2,r3,r2 + 80126d8: e0bffd0d sth r2,-12(fp) + if (flags_rdy != (OS_FLAGS)0) { /* See if any flag cleared */ + 80126dc: e0bffd0b ldhu r2,-12(fp) + 80126e0: 10001526 beq r2,zero,8012738 + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 80126e4: e0bfffc3 ldbu r2,-1(fp) + 80126e8: 10800058 cmpnei r2,r2,1 + 80126ec: 1000071e bne r2,zero,801270c + pgrp->OSFlagFlags |= flags_rdy; /* Set ONLY the flags that we got */ + 80126f0: e0bfe817 ldw r2,-96(fp) + 80126f4: 1080020b ldhu r2,8(r2) + 80126f8: e0fffd0b ldhu r3,-12(fp) + 80126fc: 1884b03a or r2,r3,r2 + 8012700: 1007883a mov r3,r2 + 8012704: e0bfe817 ldw r2,-96(fp) + 8012708: 10c0020d sth r3,8(r2) + } + OSTCBCur->OSTCBFlagsRdy = flags_rdy; /* Save flags that were ready */ + 801270c: d0a05817 ldw r2,-32416(gp) + 8012710: e0fffd0b ldhu r3,-12(fp) + 8012714: 10c00b0d sth r3,44(r2) + 8012718: e0bffe17 ldw r2,-8(fp) + 801271c: e0bff415 stw r2,-48(fp) + 8012720: e0bff417 ldw r2,-48(fp) + 8012724: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Yes, condition met, return to caller */ + *perr = OS_ERR_NONE; + 8012728: e0800217 ldw r2,8(fp) + 801272c: 10000005 stb zero,0(r2) + return (flags_rdy); + 8012730: e0bffd0b ldhu r2,-12(fp) + 8012734: 00007106 br 80128fc + } else { /* Block task until events occur or timeout */ + OS_FlagBlock(pgrp, &node, flags, wait_type, timeout); + 8012738: e13fe70b ldhu r4,-100(fp) + 801273c: e17fe603 ldbu r5,-104(fp) + 8012740: e0bfe50b ldhu r2,-108(fp) + 8012744: e0ffe904 addi r3,fp,-92 + 8012748: d8800015 stw r2,0(sp) + 801274c: 280f883a mov r7,r5 + 8012750: 200d883a mov r6,r4 + 8012754: 180b883a mov r5,r3 + 8012758: e13fe817 ldw r4,-96(fp) + 801275c: 8012d740 call 8012d74 + 8012760: e0bffe17 ldw r2,-8(fp) + 8012764: e0bff315 stw r2,-52(fp) + 8012768: e0bff317 ldw r2,-52(fp) + 801276c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + break; + 8012770: 00000a06 br 801279c + 8012774: e0bffe17 ldw r2,-8(fp) + 8012778: e0bff215 stw r2,-56(fp) + 801277c: e0bff217 ldw r2,-56(fp) + 8012780: 1001703a wrctl status,r2 +#endif + + default: + OS_EXIT_CRITICAL(); + flags_rdy = (OS_FLAGS)0; + 8012784: e03ffd0d sth zero,-12(fp) + *perr = OS_ERR_FLAG_WAIT_TYPE; + 8012788: e0800217 ldw r2,8(fp) + 801278c: 00c01bc4 movi r3,111 + 8012790: 10c00005 stb r3,0(r2) + return (flags_rdy); + 8012794: e0bffd0b ldhu r2,-12(fp) + 8012798: 00005806 br 80128fc + } +/*$PAGE*/ + OS_Sched(); /* Find next HPT ready to run */ + 801279c: 801166c0 call 801166c + NIOS2_READ_STATUS (context); + 80127a0: 0005303a rdctl r2,status + 80127a4: e0bff115 stw r2,-60(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 80127a8: e0fff117 ldw r3,-60(fp) + 80127ac: 00bfff84 movi r2,-2 + 80127b0: 1884703a and r2,r3,r2 + 80127b4: 1001703a wrctl status,r2 + return context; + 80127b8: e0bff117 ldw r2,-60(fp) + OS_ENTER_CRITICAL(); + 80127bc: e0bffe15 stw r2,-8(fp) + if (OSTCBCur->OSTCBStatPend != OS_STAT_PEND_OK) { /* Have we timed-out or aborted? */ + 80127c0: d0a05817 ldw r2,-32416(gp) + 80127c4: 10800c43 ldbu r2,49(r2) + 80127c8: 10803fcc andi r2,r2,255 + 80127cc: 10001c26 beq r2,zero,8012840 + pend_stat = OSTCBCur->OSTCBStatPend; + 80127d0: d0a05817 ldw r2,-32416(gp) + 80127d4: 10800c43 ldbu r2,49(r2) + 80127d8: e0bffcc5 stb r2,-13(fp) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + 80127dc: d0a05817 ldw r2,-32416(gp) + 80127e0: 10000c45 stb zero,49(r2) + OS_FlagUnlink(&node); + 80127e4: e0bfe904 addi r2,fp,-92 + 80127e8: 1009883a mov r4,r2 + 80127ec: 80130ac0 call 80130ac + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Yes, make task ready-to-run */ + 80127f0: d0a05817 ldw r2,-32416(gp) + 80127f4: 10000c05 stb zero,48(r2) + 80127f8: e0bffe17 ldw r2,-8(fp) + 80127fc: e0bff015 stw r2,-64(fp) + NIOS2_WRITE_STATUS (context); + 8012800: e0bff017 ldw r2,-64(fp) + 8012804: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + flags_rdy = (OS_FLAGS)0; + 8012808: e03ffd0d sth zero,-12(fp) + switch (pend_stat) { + 801280c: e0bffcc3 ldbu r2,-13(fp) + 8012810: 10800098 cmpnei r2,r2,2 + 8012814: 1000041e bne r2,zero,8012828 + case OS_STAT_PEND_ABORT: + *perr = OS_ERR_PEND_ABORT; /* Indicate that we aborted waiting */ + 8012818: e0800217 ldw r2,8(fp) + 801281c: 00c00384 movi r3,14 + 8012820: 10c00005 stb r3,0(r2) + break; + 8012824: 00000406 br 8012838 + + case OS_STAT_PEND_TO: + default: + *perr = OS_ERR_TIMEOUT; /* Indicate that we timed-out waiting */ + 8012828: e0800217 ldw r2,8(fp) + 801282c: 00c00284 movi r3,10 + 8012830: 10c00005 stb r3,0(r2) + break; + 8012834: 0001883a nop + } + return (flags_rdy); + 8012838: e0bffd0b ldhu r2,-12(fp) + 801283c: 00002f06 br 80128fc + } + flags_rdy = OSTCBCur->OSTCBFlagsRdy; + 8012840: d0a05817 ldw r2,-32416(gp) + 8012844: 10800b0b ldhu r2,44(r2) + 8012848: e0bffd0d sth r2,-12(fp) + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 801284c: e0bfffc3 ldbu r2,-1(fp) + 8012850: 10800058 cmpnei r2,r2,1 + 8012854: 1000211e bne r2,zero,80128dc + switch (wait_type) { + 8012858: e0bfe603 ldbu r2,-104(fp) + 801285c: 10001616 blt r2,zero,80128b8 + 8012860: 10c00090 cmplti r3,r2,2 + 8012864: 18000c1e bne r3,zero,8012898 + 8012868: 10800108 cmpgei r2,r2,4 + 801286c: 1000121e bne r2,zero,80128b8 + case OS_FLAG_WAIT_SET_ALL: + case OS_FLAG_WAIT_SET_ANY: /* Clear ONLY the flags we got */ + pgrp->OSFlagFlags &= ~flags_rdy; + 8012870: e0bfe817 ldw r2,-96(fp) + 8012874: 1080020b ldhu r2,8(r2) + 8012878: 1007883a mov r3,r2 + 801287c: e0bffd0b ldhu r2,-12(fp) + 8012880: 0084303a nor r2,zero,r2 + 8012884: 1884703a and r2,r3,r2 + 8012888: 1007883a mov r3,r2 + 801288c: e0bfe817 ldw r2,-96(fp) + 8012890: 10c0020d sth r3,8(r2) + break; + 8012894: 00001206 br 80128e0 + +#if OS_FLAG_WAIT_CLR_EN > 0 + case OS_FLAG_WAIT_CLR_ALL: + case OS_FLAG_WAIT_CLR_ANY: /* Set ONLY the flags we got */ + pgrp->OSFlagFlags |= flags_rdy; + 8012898: e0bfe817 ldw r2,-96(fp) + 801289c: 1080020b ldhu r2,8(r2) + 80128a0: e0fffd0b ldhu r3,-12(fp) + 80128a4: 1884b03a or r2,r3,r2 + 80128a8: 1007883a mov r3,r2 + 80128ac: e0bfe817 ldw r2,-96(fp) + 80128b0: 10c0020d sth r3,8(r2) + break; + 80128b4: 00000a06 br 80128e0 + 80128b8: e0bffe17 ldw r2,-8(fp) + 80128bc: e0bfef15 stw r2,-68(fp) + 80128c0: e0bfef17 ldw r2,-68(fp) + 80128c4: 1001703a wrctl status,r2 +#endif + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_FLAG_WAIT_TYPE; + 80128c8: e0800217 ldw r2,8(fp) + 80128cc: 00c01bc4 movi r3,111 + 80128d0: 10c00005 stb r3,0(r2) + return ((OS_FLAGS)0); + 80128d4: 0005883a mov r2,zero + 80128d8: 00000806 br 80128fc + } + } + 80128dc: 0001883a nop + 80128e0: e0bffe17 ldw r2,-8(fp) + 80128e4: e0bfee15 stw r2,-72(fp) + 80128e8: e0bfee17 ldw r2,-72(fp) + 80128ec: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; /* Event(s) must have occurred */ + 80128f0: e0800217 ldw r2,8(fp) + 80128f4: 10000005 stb zero,0(r2) + return (flags_rdy); + 80128f8: e0bffd0b ldhu r2,-12(fp) +} + 80128fc: e037883a mov sp,fp + 8012900: dfc00117 ldw ra,4(sp) + 8012904: df000017 ldw fp,0(sp) + 8012908: dec00204 addi sp,sp,8 + 801290c: f800283a ret + +08012910 : +* Called from: Task ONLY +********************************************************************************************************* +*/ + +OS_FLAGS OSFlagPendGetFlagsRdy (void) +{ + 8012910: defffb04 addi sp,sp,-20 + 8012914: df000415 stw fp,16(sp) + 8012918: df000404 addi fp,sp,16 + OS_FLAGS flags; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 801291c: e03fff15 stw zero,-4(fp) + NIOS2_READ_STATUS (context); + 8012920: 0005303a rdctl r2,status + 8012924: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8012928: e0fffc17 ldw r3,-16(fp) + 801292c: 00bfff84 movi r2,-2 + 8012930: 1884703a and r2,r3,r2 + 8012934: 1001703a wrctl status,r2 + return context; + 8012938: e0bffc17 ldw r2,-16(fp) +#endif + + + + OS_ENTER_CRITICAL(); + 801293c: e0bfff15 stw r2,-4(fp) + flags = OSTCBCur->OSTCBFlagsRdy; + 8012940: d0a05817 ldw r2,-32416(gp) + 8012944: 10800b0b ldhu r2,44(r2) + 8012948: e0bffe8d sth r2,-6(fp) + 801294c: e0bfff17 ldw r2,-4(fp) + 8012950: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context); + 8012954: e0bffd17 ldw r2,-12(fp) + 8012958: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (flags); + 801295c: e0bffe8b ldhu r2,-6(fp) +} + 8012960: e037883a mov sp,fp + 8012964: df000017 ldw fp,0(sp) + 8012968: dec00104 addi sp,sp,4 + 801296c: f800283a ret + +08012970 : +* 2) The amount of time interrupts are DISABLED depends on the number of tasks waiting on +* the event flag group. +********************************************************************************************************* +*/ +OS_FLAGS OSFlagPost (OS_FLAG_GRP *pgrp, OS_FLAGS flags, INT8U opt, INT8U *perr) +{ + 8012970: deffef04 addi sp,sp,-68 + 8012974: dfc01015 stw ra,64(sp) + 8012978: df000f15 stw fp,60(sp) + 801297c: df000f04 addi fp,sp,60 + 8012980: e13ff415 stw r4,-48(fp) + 8012984: 2805883a mov r2,r5 + 8012988: 3007883a mov r3,r6 + 801298c: e1fff115 stw r7,-60(fp) + 8012990: e0bff30d sth r2,-52(fp) + 8012994: 1805883a mov r2,r3 + 8012998: e0bff205 stb r2,-56(fp) + BOOLEAN sched; + OS_FLAGS flags_cur; + OS_FLAGS flags_rdy; + BOOLEAN rdy; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 801299c: e03ffd15 stw zero,-12(fp) + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + *perr = OS_ERR_FLAG_INVALID_PGRP; + return ((OS_FLAGS)0); + } +#endif + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Make sure we are pointing to an event flag grp */ + 80129a0: e0bff417 ldw r2,-48(fp) + 80129a4: 10800003 ldbu r2,0(r2) + 80129a8: 10803fcc andi r2,r2,255 + 80129ac: 10800160 cmpeqi r2,r2,5 + 80129b0: 1000051e bne r2,zero,80129c8 + *perr = OS_ERR_EVENT_TYPE; + 80129b4: e0bff117 ldw r2,-60(fp) + 80129b8: 00c00044 movi r3,1 + 80129bc: 10c00005 stb r3,0(r2) + return ((OS_FLAGS)0); + 80129c0: 0005883a mov r2,zero + 80129c4: 0000c006 br 8012cc8 + NIOS2_READ_STATUS (context); + 80129c8: 0005303a rdctl r2,status + 80129cc: e0bffa15 stw r2,-24(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 80129d0: e0fffa17 ldw r3,-24(fp) + 80129d4: 00bfff84 movi r2,-2 + 80129d8: 1884703a and r2,r3,r2 + 80129dc: 1001703a wrctl status,r2 + return context; + 80129e0: e0bffa17 ldw r2,-24(fp) + } +/*$PAGE*/ + OS_ENTER_CRITICAL(); + 80129e4: e0bffd15 stw r2,-12(fp) + switch (opt) { + 80129e8: e0bff203 ldbu r2,-56(fp) + 80129ec: 10000326 beq r2,zero,80129fc + 80129f0: 10800060 cmpeqi r2,r2,1 + 80129f4: 10000b1e bne r2,zero,8012a24 + 80129f8: 00001206 br 8012a44 + case OS_FLAG_CLR: + pgrp->OSFlagFlags &= ~flags; /* Clear the flags specified in the group */ + 80129fc: e0bff417 ldw r2,-48(fp) + 8012a00: 1080020b ldhu r2,8(r2) + 8012a04: 1007883a mov r3,r2 + 8012a08: e0bff30b ldhu r2,-52(fp) + 8012a0c: 0084303a nor r2,zero,r2 + 8012a10: 1884703a and r2,r3,r2 + 8012a14: 1007883a mov r3,r2 + 8012a18: e0bff417 ldw r2,-48(fp) + 8012a1c: 10c0020d sth r3,8(r2) + break; + 8012a20: 00001106 br 8012a68 + + case OS_FLAG_SET: + pgrp->OSFlagFlags |= flags; /* Set the flags specified in the group */ + 8012a24: e0bff417 ldw r2,-48(fp) + 8012a28: 1080020b ldhu r2,8(r2) + 8012a2c: e0fff30b ldhu r3,-52(fp) + 8012a30: 1884b03a or r2,r3,r2 + 8012a34: 1007883a mov r3,r2 + 8012a38: e0bff417 ldw r2,-48(fp) + 8012a3c: 10c0020d sth r3,8(r2) + break; + 8012a40: 00000906 br 8012a68 + 8012a44: e0bffd17 ldw r2,-12(fp) + 8012a48: e0bff915 stw r2,-28(fp) + NIOS2_WRITE_STATUS (context); + 8012a4c: e0bff917 ldw r2,-28(fp) + 8012a50: 1001703a wrctl status,r2 + + default: + OS_EXIT_CRITICAL(); /* INVALID option */ + *perr = OS_ERR_FLAG_INVALID_OPT; + 8012a54: e0bff117 ldw r2,-60(fp) + 8012a58: 00c01c44 movi r3,113 + 8012a5c: 10c00005 stb r3,0(r2) + return ((OS_FLAGS)0); + 8012a60: 0005883a mov r2,zero + 8012a64: 00009806 br 8012cc8 + } + sched = OS_FALSE; /* Indicate that we don't need rescheduling */ + 8012a68: e03ffec5 stb zero,-5(fp) + pnode = (OS_FLAG_NODE *)pgrp->OSFlagWaitList; + 8012a6c: e0bff417 ldw r2,-48(fp) + 8012a70: 10800117 ldw r2,4(r2) + 8012a74: e0bfff15 stw r2,-4(fp) + while (pnode != (OS_FLAG_NODE *)0) { /* Go through all tasks waiting on event flag(s) */ + 8012a78: 00007706 br 8012c58 + switch (pnode->OSFlagNodeWaitType) { + 8012a7c: e0bfff17 ldw r2,-4(fp) + 8012a80: 10800483 ldbu r2,18(r2) + 8012a84: 10803fcc andi r2,r2,255 + 8012a88: 10c00060 cmpeqi r3,r2,1 + 8012a8c: 18004a1e bne r3,zero,8012bb8 + 8012a90: 10c00088 cmpgei r3,r2,2 + 8012a94: 1800021e bne r3,zero,8012aa0 + 8012a98: 10002f26 beq r2,zero,8012b58 + 8012a9c: 00005b06 br 8012c0c + 8012aa0: 10c000a0 cmpeqi r3,r2,2 + 8012aa4: 1800031e bne r3,zero,8012ab4 + 8012aa8: 108000e0 cmpeqi r2,r2,3 + 8012aac: 1000171e bne r2,zero,8012b0c + 8012ab0: 00005606 br 8012c0c + case OS_FLAG_WAIT_SET_ALL: /* See if all req. flags are set for current node */ + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & pnode->OSFlagNodeFlags); + 8012ab4: e0bff417 ldw r2,-48(fp) + 8012ab8: 10c0020b ldhu r3,8(r2) + 8012abc: e0bfff17 ldw r2,-4(fp) + 8012ac0: 1080040b ldhu r2,16(r2) + 8012ac4: 1884703a and r2,r3,r2 + 8012ac8: e0bffc8d sth r2,-14(fp) + if (flags_rdy == pnode->OSFlagNodeFlags) { + 8012acc: e0bfff17 ldw r2,-4(fp) + 8012ad0: 1080040b ldhu r2,16(r2) + 8012ad4: e0fffc8b ldhu r3,-14(fp) + 8012ad8: 10bfffcc andi r2,r2,65535 + 8012adc: 1880541e bne r3,r2,8012c30 + rdy = OS_FlagTaskRdy(pnode, flags_rdy); /* Make task RTR, event(s) Rx'd */ + 8012ae0: e0bffc8b ldhu r2,-14(fp) + 8012ae4: 100b883a mov r5,r2 + 8012ae8: e13fff17 ldw r4,-4(fp) + 8012aec: 8012fb80 call 8012fb8 + 8012af0: e0bffc45 stb r2,-15(fp) + if (rdy == OS_TRUE) { + 8012af4: e0bffc43 ldbu r2,-15(fp) + 8012af8: 10800058 cmpnei r2,r2,1 + 8012afc: 10004c1e bne r2,zero,8012c30 + sched = OS_TRUE; /* When done we will reschedule */ + 8012b00: 00800044 movi r2,1 + 8012b04: e0bffec5 stb r2,-5(fp) + } + } + break; + 8012b08: 00004906 br 8012c30 + + case OS_FLAG_WAIT_SET_ANY: /* See if any flag set */ + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & pnode->OSFlagNodeFlags); + 8012b0c: e0bff417 ldw r2,-48(fp) + 8012b10: 10c0020b ldhu r3,8(r2) + 8012b14: e0bfff17 ldw r2,-4(fp) + 8012b18: 1080040b ldhu r2,16(r2) + 8012b1c: 1884703a and r2,r3,r2 + 8012b20: e0bffc8d sth r2,-14(fp) + if (flags_rdy != (OS_FLAGS)0) { + 8012b24: e0bffc8b ldhu r2,-14(fp) + 8012b28: 10004326 beq r2,zero,8012c38 + rdy = OS_FlagTaskRdy(pnode, flags_rdy); /* Make task RTR, event(s) Rx'd */ + 8012b2c: e0bffc8b ldhu r2,-14(fp) + 8012b30: 100b883a mov r5,r2 + 8012b34: e13fff17 ldw r4,-4(fp) + 8012b38: 8012fb80 call 8012fb8 + 8012b3c: e0bffc45 stb r2,-15(fp) + if (rdy == OS_TRUE) { + 8012b40: e0bffc43 ldbu r2,-15(fp) + 8012b44: 10800058 cmpnei r2,r2,1 + 8012b48: 10003b1e bne r2,zero,8012c38 + sched = OS_TRUE; /* When done we will reschedule */ + 8012b4c: 00800044 movi r2,1 + 8012b50: e0bffec5 stb r2,-5(fp) + } + } + break; + 8012b54: 00003806 br 8012c38 + +#if OS_FLAG_WAIT_CLR_EN > 0 + case OS_FLAG_WAIT_CLR_ALL: /* See if all req. flags are set for current node */ + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & pnode->OSFlagNodeFlags); + 8012b58: e0bff417 ldw r2,-48(fp) + 8012b5c: 1080020b ldhu r2,8(r2) + 8012b60: 0084303a nor r2,zero,r2 + 8012b64: 1007883a mov r3,r2 + 8012b68: e0bfff17 ldw r2,-4(fp) + 8012b6c: 1080040b ldhu r2,16(r2) + 8012b70: 1884703a and r2,r3,r2 + 8012b74: e0bffc8d sth r2,-14(fp) + if (flags_rdy == pnode->OSFlagNodeFlags) { + 8012b78: e0bfff17 ldw r2,-4(fp) + 8012b7c: 1080040b ldhu r2,16(r2) + 8012b80: e0fffc8b ldhu r3,-14(fp) + 8012b84: 10bfffcc andi r2,r2,65535 + 8012b88: 18802d1e bne r3,r2,8012c40 + rdy = OS_FlagTaskRdy(pnode, flags_rdy); /* Make task RTR, event(s) Rx'd */ + 8012b8c: e0bffc8b ldhu r2,-14(fp) + 8012b90: 100b883a mov r5,r2 + 8012b94: e13fff17 ldw r4,-4(fp) + 8012b98: 8012fb80 call 8012fb8 + 8012b9c: e0bffc45 stb r2,-15(fp) + if (rdy == OS_TRUE) { + 8012ba0: e0bffc43 ldbu r2,-15(fp) + 8012ba4: 10800058 cmpnei r2,r2,1 + 8012ba8: 1000251e bne r2,zero,8012c40 + sched = OS_TRUE; /* When done we will reschedule */ + 8012bac: 00800044 movi r2,1 + 8012bb0: e0bffec5 stb r2,-5(fp) + } + } + break; + 8012bb4: 00002206 br 8012c40 + + case OS_FLAG_WAIT_CLR_ANY: /* See if any flag set */ + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & pnode->OSFlagNodeFlags); + 8012bb8: e0bff417 ldw r2,-48(fp) + 8012bbc: 1080020b ldhu r2,8(r2) + 8012bc0: 0084303a nor r2,zero,r2 + 8012bc4: 1007883a mov r3,r2 + 8012bc8: e0bfff17 ldw r2,-4(fp) + 8012bcc: 1080040b ldhu r2,16(r2) + 8012bd0: 1884703a and r2,r3,r2 + 8012bd4: e0bffc8d sth r2,-14(fp) + if (flags_rdy != (OS_FLAGS)0) { + 8012bd8: e0bffc8b ldhu r2,-14(fp) + 8012bdc: 10001a26 beq r2,zero,8012c48 + rdy = OS_FlagTaskRdy(pnode, flags_rdy); /* Make task RTR, event(s) Rx'd */ + 8012be0: e0bffc8b ldhu r2,-14(fp) + 8012be4: 100b883a mov r5,r2 + 8012be8: e13fff17 ldw r4,-4(fp) + 8012bec: 8012fb80 call 8012fb8 + 8012bf0: e0bffc45 stb r2,-15(fp) + if (rdy == OS_TRUE) { + 8012bf4: e0bffc43 ldbu r2,-15(fp) + 8012bf8: 10800058 cmpnei r2,r2,1 + 8012bfc: 1000121e bne r2,zero,8012c48 + sched = OS_TRUE; /* When done we will reschedule */ + 8012c00: 00800044 movi r2,1 + 8012c04: e0bffec5 stb r2,-5(fp) + } + } + break; + 8012c08: 00000f06 br 8012c48 + 8012c0c: e0bffd17 ldw r2,-12(fp) + 8012c10: e0bff815 stw r2,-32(fp) + 8012c14: e0bff817 ldw r2,-32(fp) + 8012c18: 1001703a wrctl status,r2 +#endif + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_FLAG_WAIT_TYPE; + 8012c1c: e0bff117 ldw r2,-60(fp) + 8012c20: 00c01bc4 movi r3,111 + 8012c24: 10c00005 stb r3,0(r2) + return ((OS_FLAGS)0); + 8012c28: 0005883a mov r2,zero + 8012c2c: 00002606 br 8012cc8 + break; + 8012c30: 0001883a nop + 8012c34: 00000506 br 8012c4c + break; + 8012c38: 0001883a nop + 8012c3c: 00000306 br 8012c4c + break; + 8012c40: 0001883a nop + 8012c44: 00000106 br 8012c4c + break; + 8012c48: 0001883a nop + } + pnode = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; /* Point to next task waiting for event flag(s) */ + 8012c4c: e0bfff17 ldw r2,-4(fp) + 8012c50: 10800017 ldw r2,0(r2) + 8012c54: e0bfff15 stw r2,-4(fp) + while (pnode != (OS_FLAG_NODE *)0) { /* Go through all tasks waiting on event flag(s) */ + 8012c58: e0bfff17 ldw r2,-4(fp) + 8012c5c: 103f871e bne r2,zero,8012a7c + 8012c60: e0bffd17 ldw r2,-12(fp) + 8012c64: e0bff715 stw r2,-36(fp) + 8012c68: e0bff717 ldw r2,-36(fp) + 8012c6c: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + if (sched == OS_TRUE) { + 8012c70: e0bffec3 ldbu r2,-5(fp) + 8012c74: 10800058 cmpnei r2,r2,1 + 8012c78: 1000011e bne r2,zero,8012c80 + OS_Sched(); + 8012c7c: 801166c0 call 801166c + NIOS2_READ_STATUS (context); + 8012c80: 0005303a rdctl r2,status + 8012c84: e0bff515 stw r2,-44(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8012c88: e0fff517 ldw r3,-44(fp) + 8012c8c: 00bfff84 movi r2,-2 + 8012c90: 1884703a and r2,r3,r2 + 8012c94: 1001703a wrctl status,r2 + return context; + 8012c98: e0bff517 ldw r2,-44(fp) + } + OS_ENTER_CRITICAL(); + 8012c9c: e0bffd15 stw r2,-12(fp) + flags_cur = pgrp->OSFlagFlags; + 8012ca0: e0bff417 ldw r2,-48(fp) + 8012ca4: 1080020b ldhu r2,8(r2) + 8012ca8: e0bffb8d sth r2,-18(fp) + 8012cac: e0bffd17 ldw r2,-12(fp) + 8012cb0: e0bff615 stw r2,-40(fp) + NIOS2_WRITE_STATUS (context); + 8012cb4: e0bff617 ldw r2,-40(fp) + 8012cb8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 8012cbc: e0bff117 ldw r2,-60(fp) + 8012cc0: 10000005 stb zero,0(r2) + return (flags_cur); + 8012cc4: e0bffb8b ldhu r2,-18(fp) +} + 8012cc8: e037883a mov sp,fp + 8012ccc: dfc00117 ldw ra,4(sp) + 8012cd0: df000017 ldw fp,0(sp) + 8012cd4: dec00204 addi sp,sp,8 + 8012cd8: f800283a ret + +08012cdc : +********************************************************************************************************* +*/ + +#if OS_FLAG_QUERY_EN > 0 +OS_FLAGS OSFlagQuery (OS_FLAG_GRP *pgrp, INT8U *perr) +{ + 8012cdc: defff904 addi sp,sp,-28 + 8012ce0: df000615 stw fp,24(sp) + 8012ce4: df000604 addi fp,sp,24 + 8012ce8: e13ffb15 stw r4,-20(fp) + 8012cec: e17ffa15 stw r5,-24(fp) + OS_FLAGS flags; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8012cf0: e03fff15 stw zero,-4(fp) + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + *perr = OS_ERR_FLAG_INVALID_PGRP; + return ((OS_FLAGS)0); + } +#endif + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event block type */ + 8012cf4: e0bffb17 ldw r2,-20(fp) + 8012cf8: 10800003 ldbu r2,0(r2) + 8012cfc: 10803fcc andi r2,r2,255 + 8012d00: 10800160 cmpeqi r2,r2,5 + 8012d04: 1000051e bne r2,zero,8012d1c + *perr = OS_ERR_EVENT_TYPE; + 8012d08: e0bffa17 ldw r2,-24(fp) + 8012d0c: 00c00044 movi r3,1 + 8012d10: 10c00005 stb r3,0(r2) + return ((OS_FLAGS)0); + 8012d14: 0005883a mov r2,zero + 8012d18: 00001206 br 8012d64 + NIOS2_READ_STATUS (context); + 8012d1c: 0005303a rdctl r2,status + 8012d20: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8012d24: e0fffc17 ldw r3,-16(fp) + 8012d28: 00bfff84 movi r2,-2 + 8012d2c: 1884703a and r2,r3,r2 + 8012d30: 1001703a wrctl status,r2 + return context; + 8012d34: e0bffc17 ldw r2,-16(fp) + } + OS_ENTER_CRITICAL(); + 8012d38: e0bfff15 stw r2,-4(fp) + flags = pgrp->OSFlagFlags; + 8012d3c: e0bffb17 ldw r2,-20(fp) + 8012d40: 1080020b ldhu r2,8(r2) + 8012d44: e0bffe8d sth r2,-6(fp) + 8012d48: e0bfff17 ldw r2,-4(fp) + 8012d4c: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context); + 8012d50: e0bffd17 ldw r2,-12(fp) + 8012d54: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 8012d58: e0bffa17 ldw r2,-24(fp) + 8012d5c: 10000005 stb zero,0(r2) + return (flags); /* Return the current value of the event flags */ + 8012d60: e0bffe8b ldhu r2,-6(fp) +} + 8012d64: e037883a mov sp,fp + 8012d68: df000017 ldw fp,0(sp) + 8012d6c: dec00104 addi sp,sp,4 + 8012d70: f800283a ret + +08012d74 : +* Note(s) : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +static void OS_FlagBlock (OS_FLAG_GRP *pgrp, OS_FLAG_NODE *pnode, OS_FLAGS flags, INT8U wait_type, INT16U timeout) +{ + 8012d74: defff804 addi sp,sp,-32 + 8012d78: df000715 stw fp,28(sp) + 8012d7c: df000704 addi fp,sp,28 + 8012d80: e13ffd15 stw r4,-12(fp) + 8012d84: e17ffc15 stw r5,-16(fp) + 8012d88: 3007883a mov r3,r6 + 8012d8c: 3809883a mov r4,r7 + 8012d90: e0800117 ldw r2,4(fp) + 8012d94: e0fffb0d sth r3,-20(fp) + 8012d98: 2007883a mov r3,r4 + 8012d9c: e0fffa05 stb r3,-24(fp) + 8012da0: e0bff90d sth r2,-28(fp) + OS_FLAG_NODE *pnode_next; + INT8U y; + + + OSTCBCur->OSTCBStat |= OS_STAT_FLAG; + 8012da4: d0a05817 ldw r2,-32416(gp) + 8012da8: 10c00c03 ldbu r3,48(r2) + 8012dac: d0a05817 ldw r2,-32416(gp) + 8012db0: 18c00814 ori r3,r3,32 + 8012db4: 10c00c05 stb r3,48(r2) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + 8012db8: d0a05817 ldw r2,-32416(gp) + 8012dbc: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBDly = timeout; /* Store timeout in task's TCB */ + 8012dc0: d0a05817 ldw r2,-32416(gp) + 8012dc4: e0fff90b ldhu r3,-28(fp) + 8012dc8: 10c00b8d sth r3,46(r2) +#if OS_TASK_DEL_EN > 0 + OSTCBCur->OSTCBFlagNode = pnode; /* TCB to link to node */ + 8012dcc: d0a05817 ldw r2,-32416(gp) + 8012dd0: e0fffc17 ldw r3,-16(fp) + 8012dd4: 10c00a15 stw r3,40(r2) +#endif + pnode->OSFlagNodeFlags = flags; /* Save the flags that we need to wait for */ + 8012dd8: e0bffc17 ldw r2,-16(fp) + 8012ddc: e0fffb0b ldhu r3,-20(fp) + 8012de0: 10c0040d sth r3,16(r2) + pnode->OSFlagNodeWaitType = wait_type; /* Save the type of wait we are doing */ + 8012de4: e0bffc17 ldw r2,-16(fp) + 8012de8: e0fffa03 ldbu r3,-24(fp) + 8012dec: 10c00485 stb r3,18(r2) + pnode->OSFlagNodeTCB = (void *)OSTCBCur; /* Link to task's TCB */ + 8012df0: d0e05817 ldw r3,-32416(gp) + 8012df4: e0bffc17 ldw r2,-16(fp) + 8012df8: 10c00215 stw r3,8(r2) + pnode->OSFlagNodeNext = pgrp->OSFlagWaitList; /* Add node at beginning of event flag wait list */ + 8012dfc: e0bffd17 ldw r2,-12(fp) + 8012e00: 10c00117 ldw r3,4(r2) + 8012e04: e0bffc17 ldw r2,-16(fp) + 8012e08: 10c00015 stw r3,0(r2) + pnode->OSFlagNodePrev = (void *)0; + 8012e0c: e0bffc17 ldw r2,-16(fp) + 8012e10: 10000115 stw zero,4(r2) + pnode->OSFlagNodeFlagGrp = (void *)pgrp; /* Link to Event Flag Group */ + 8012e14: e0bffc17 ldw r2,-16(fp) + 8012e18: e0fffd17 ldw r3,-12(fp) + 8012e1c: 10c00315 stw r3,12(r2) + pnode_next = (OS_FLAG_NODE *)pgrp->OSFlagWaitList; + 8012e20: e0bffd17 ldw r2,-12(fp) + 8012e24: 10800117 ldw r2,4(r2) + 8012e28: e0bfff15 stw r2,-4(fp) + if (pnode_next != (void *)0) { /* Is this the first NODE to insert? */ + 8012e2c: e0bfff17 ldw r2,-4(fp) + 8012e30: 10000326 beq r2,zero,8012e40 + pnode_next->OSFlagNodePrev = pnode; /* No, link in doubly linked list */ + 8012e34: e0bfff17 ldw r2,-4(fp) + 8012e38: e0fffc17 ldw r3,-16(fp) + 8012e3c: 10c00115 stw r3,4(r2) + } + pgrp->OSFlagWaitList = (void *)pnode; + 8012e40: e0bffd17 ldw r2,-12(fp) + 8012e44: e0fffc17 ldw r3,-16(fp) + 8012e48: 10c00115 stw r3,4(r2) + + y = OSTCBCur->OSTCBY; /* Suspend current task until flag(s) received */ + 8012e4c: d0a05817 ldw r2,-32416(gp) + 8012e50: 10800d03 ldbu r2,52(r2) + 8012e54: e0bffec5 stb r2,-5(fp) + OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX; + 8012e58: e0fffec3 ldbu r3,-5(fp) + 8012e5c: d0a05544 addi r2,gp,-32427 + 8012e60: 1885883a add r2,r3,r2 + 8012e64: 10800003 ldbu r2,0(r2) + 8012e68: 1007883a mov r3,r2 + 8012e6c: d0a05817 ldw r2,-32416(gp) + 8012e70: 10800d43 ldbu r2,53(r2) + 8012e74: 0084303a nor r2,zero,r2 + 8012e78: 1884703a and r2,r3,r2 + 8012e7c: e0fffec3 ldbu r3,-5(fp) + 8012e80: 1009883a mov r4,r2 + 8012e84: d0a05544 addi r2,gp,-32427 + 8012e88: 1885883a add r2,r3,r2 + 8012e8c: 11000005 stb r4,0(r2) + if (OSRdyTbl[y] == 0x00) { + 8012e90: e0fffec3 ldbu r3,-5(fp) + 8012e94: d0a05544 addi r2,gp,-32427 + 8012e98: 1885883a add r2,r3,r2 + 8012e9c: 10800003 ldbu r2,0(r2) + 8012ea0: 10803fcc andi r2,r2,255 + 8012ea4: 1000071e bne r2,zero,8012ec4 + OSRdyGrp &= ~OSTCBCur->OSTCBBitY; + 8012ea8: d0a05817 ldw r2,-32416(gp) + 8012eac: 10800d83 ldbu r2,54(r2) + 8012eb0: 0084303a nor r2,zero,r2 + 8012eb4: 1007883a mov r3,r2 + 8012eb8: d0a05503 ldbu r2,-32428(gp) + 8012ebc: 1884703a and r2,r3,r2 + 8012ec0: d0a05505 stb r2,-32428(gp) + } +} + 8012ec4: 0001883a nop + 8012ec8: e037883a mov sp,fp + 8012ecc: df000017 ldw fp,0(sp) + 8012ed0: dec00104 addi sp,sp,4 + 8012ed4: f800283a ret + +08012ed8 : +* WARNING : You MUST NOT call this function from your code. This is an INTERNAL function to uC/OS-II. +********************************************************************************************************* +*/ + +void OS_FlagInit (void) +{ + 8012ed8: defffb04 addi sp,sp,-20 + 8012edc: dfc00415 stw ra,16(sp) + 8012ee0: df000315 stw fp,12(sp) + 8012ee4: df000304 addi fp,sp,12 + INT16U i; + OS_FLAG_GRP *pgrp1; + OS_FLAG_GRP *pgrp2; + + + OS_MemClr((INT8U *)&OSFlagTbl[0], sizeof(OSFlagTbl)); /* Clear the flag group table */ + 8012ee8: 0140dc04 movi r5,880 + 8012eec: 010201b4 movhi r4,2054 + 8012ef0: 212b8b04 addi r4,r4,-20948 + 8012ef4: 80115b00 call 80115b0 + pgrp1 = &OSFlagTbl[0]; + 8012ef8: 008201b4 movhi r2,2054 + 8012efc: 10ab8b04 addi r2,r2,-20948 + 8012f00: e0bffe15 stw r2,-8(fp) + pgrp2 = &OSFlagTbl[1]; + 8012f04: 008201b4 movhi r2,2054 + 8012f08: 10ab9604 addi r2,r2,-20904 + 8012f0c: e0bffd15 stw r2,-12(fp) + for (i = 0; i < (OS_MAX_FLAGS - 1); i++) { /* Init. list of free EVENT FLAGS */ + 8012f10: e03fff8d sth zero,-2(fp) + 8012f14: 00001306 br 8012f64 + pgrp1->OSFlagType = OS_EVENT_TYPE_UNUSED; + 8012f18: e0bffe17 ldw r2,-8(fp) + 8012f1c: 10000005 stb zero,0(r2) + pgrp1->OSFlagWaitList = (void *)pgrp2; + 8012f20: e0bffe17 ldw r2,-8(fp) + 8012f24: e0fffd17 ldw r3,-12(fp) + 8012f28: 10c00115 stw r3,4(r2) +#if OS_FLAG_NAME_SIZE > 1 + pgrp1->OSFlagName[0] = '?'; /* Unknown name */ + 8012f2c: e0bffe17 ldw r2,-8(fp) + 8012f30: 00c00fc4 movi r3,63 + 8012f34: 10c00285 stb r3,10(r2) + pgrp1->OSFlagName[1] = OS_ASCII_NUL; + 8012f38: e0bffe17 ldw r2,-8(fp) + 8012f3c: 100002c5 stb zero,11(r2) +#endif + pgrp1++; + 8012f40: e0bffe17 ldw r2,-8(fp) + 8012f44: 10800b04 addi r2,r2,44 + 8012f48: e0bffe15 stw r2,-8(fp) + pgrp2++; + 8012f4c: e0bffd17 ldw r2,-12(fp) + 8012f50: 10800b04 addi r2,r2,44 + 8012f54: e0bffd15 stw r2,-12(fp) + for (i = 0; i < (OS_MAX_FLAGS - 1); i++) { /* Init. list of free EVENT FLAGS */ + 8012f58: e0bfff8b ldhu r2,-2(fp) + 8012f5c: 10800044 addi r2,r2,1 + 8012f60: e0bfff8d sth r2,-2(fp) + 8012f64: e0bfff8b ldhu r2,-2(fp) + 8012f68: 108004f0 cmpltui r2,r2,19 + 8012f6c: 103fea1e bne r2,zero,8012f18 + } + pgrp1->OSFlagType = OS_EVENT_TYPE_UNUSED; + 8012f70: e0bffe17 ldw r2,-8(fp) + 8012f74: 10000005 stb zero,0(r2) + pgrp1->OSFlagWaitList = (void *)0; + 8012f78: e0bffe17 ldw r2,-8(fp) + 8012f7c: 10000115 stw zero,4(r2) +#if OS_FLAG_NAME_SIZE > 1 + pgrp1->OSFlagName[0] = '?'; /* Unknown name */ + 8012f80: e0bffe17 ldw r2,-8(fp) + 8012f84: 00c00fc4 movi r3,63 + 8012f88: 10c00285 stb r3,10(r2) + pgrp1->OSFlagName[1] = OS_ASCII_NUL; + 8012f8c: e0bffe17 ldw r2,-8(fp) + 8012f90: 100002c5 stb zero,11(r2) +#endif + OSFlagFreeList = &OSFlagTbl[0]; + 8012f94: 008201b4 movhi r2,2054 + 8012f98: 10ab8b04 addi r2,r2,-20948 + 8012f9c: d0a05a15 stw r2,-32408(gp) +#endif +} + 8012fa0: 0001883a nop + 8012fa4: e037883a mov sp,fp + 8012fa8: dfc00117 ldw ra,4(sp) + 8012fac: df000017 ldw fp,0(sp) + 8012fb0: dec00204 addi sp,sp,8 + 8012fb4: f800283a ret + +08012fb8 : +* 2) This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +static BOOLEAN OS_FlagTaskRdy (OS_FLAG_NODE *pnode, OS_FLAGS flags_rdy) +{ + 8012fb8: defffa04 addi sp,sp,-24 + 8012fbc: dfc00515 stw ra,20(sp) + 8012fc0: df000415 stw fp,16(sp) + 8012fc4: df000404 addi fp,sp,16 + 8012fc8: e13ffd15 stw r4,-12(fp) + 8012fcc: 2805883a mov r2,r5 + 8012fd0: e0bffc0d sth r2,-16(fp) + OS_TCB *ptcb; + BOOLEAN sched; + + + ptcb = (OS_TCB *)pnode->OSFlagNodeTCB; /* Point to TCB of waiting task */ + 8012fd4: e0bffd17 ldw r2,-12(fp) + 8012fd8: 10800217 ldw r2,8(r2) + 8012fdc: e0bffe15 stw r2,-8(fp) + ptcb->OSTCBDly = 0; + 8012fe0: e0bffe17 ldw r2,-8(fp) + 8012fe4: 10000b8d sth zero,46(r2) + ptcb->OSTCBFlagsRdy = flags_rdy; + 8012fe8: e0bffe17 ldw r2,-8(fp) + 8012fec: e0fffc0b ldhu r3,-16(fp) + 8012ff0: 10c00b0d sth r3,44(r2) + ptcb->OSTCBStat &= ~(INT8U)OS_STAT_FLAG; + 8012ff4: e0bffe17 ldw r2,-8(fp) + 8012ff8: 10c00c03 ldbu r3,48(r2) + 8012ffc: 00bff7c4 movi r2,-33 + 8013000: 1884703a and r2,r3,r2 + 8013004: 1007883a mov r3,r2 + 8013008: e0bffe17 ldw r2,-8(fp) + 801300c: 10c00c05 stb r3,48(r2) + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; + 8013010: e0bffe17 ldw r2,-8(fp) + 8013014: 10000c45 stb zero,49(r2) + if (ptcb->OSTCBStat == OS_STAT_RDY) { /* Task now ready? */ + 8013018: e0bffe17 ldw r2,-8(fp) + 801301c: 10800c03 ldbu r2,48(r2) + 8013020: 10803fcc andi r2,r2,255 + 8013024: 1000181e bne r2,zero,8013088 + OSRdyGrp |= ptcb->OSTCBBitY; /* Put task into ready list */ + 8013028: e0bffe17 ldw r2,-8(fp) + 801302c: 10c00d83 ldbu r3,54(r2) + 8013030: d0a05503 ldbu r2,-32428(gp) + 8013034: 1884b03a or r2,r3,r2 + 8013038: d0a05505 stb r2,-32428(gp) + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + 801303c: e0bffe17 ldw r2,-8(fp) + 8013040: 10800d03 ldbu r2,52(r2) + 8013044: 10c03fcc andi r3,r2,255 + 8013048: d0a05544 addi r2,gp,-32427 + 801304c: 1885883a add r2,r3,r2 + 8013050: 11000003 ldbu r4,0(r2) + 8013054: e0bffe17 ldw r2,-8(fp) + 8013058: 10800d43 ldbu r2,53(r2) + 801305c: e0fffe17 ldw r3,-8(fp) + 8013060: 18c00d03 ldbu r3,52(r3) + 8013064: 18c03fcc andi r3,r3,255 + 8013068: 2084b03a or r2,r4,r2 + 801306c: 1009883a mov r4,r2 + 8013070: d0a05544 addi r2,gp,-32427 + 8013074: 1885883a add r2,r3,r2 + 8013078: 11000005 stb r4,0(r2) + sched = OS_TRUE; + 801307c: 00800044 movi r2,1 + 8013080: e0bfffc5 stb r2,-1(fp) + 8013084: 00000106 br 801308c + } else { + sched = OS_FALSE; + 8013088: e03fffc5 stb zero,-1(fp) + } + OS_FlagUnlink(pnode); + 801308c: e13ffd17 ldw r4,-12(fp) + 8013090: 80130ac0 call 80130ac + return (sched); + 8013094: e0bfffc3 ldbu r2,-1(fp) +} + 8013098: e037883a mov sp,fp + 801309c: dfc00117 ldw ra,4(sp) + 80130a0: df000017 ldw fp,0(sp) + 80130a4: dec00204 addi sp,sp,8 + 80130a8: f800283a ret + +080130ac : +* 2) This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +void OS_FlagUnlink (OS_FLAG_NODE *pnode) +{ + 80130ac: defffa04 addi sp,sp,-24 + 80130b0: df000515 stw fp,20(sp) + 80130b4: df000504 addi fp,sp,20 + 80130b8: e13ffb15 stw r4,-20(fp) + OS_FLAG_GRP *pgrp; + OS_FLAG_NODE *pnode_prev; + OS_FLAG_NODE *pnode_next; + + + pnode_prev = (OS_FLAG_NODE *)pnode->OSFlagNodePrev; + 80130bc: e0bffb17 ldw r2,-20(fp) + 80130c0: 10800117 ldw r2,4(r2) + 80130c4: e0bfff15 stw r2,-4(fp) + pnode_next = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; + 80130c8: e0bffb17 ldw r2,-20(fp) + 80130cc: 10800017 ldw r2,0(r2) + 80130d0: e0bffe15 stw r2,-8(fp) + if (pnode_prev == (OS_FLAG_NODE *)0) { /* Is it first node in wait list? */ + 80130d4: e0bfff17 ldw r2,-4(fp) + 80130d8: 10000b1e bne r2,zero,8013108 + pgrp = (OS_FLAG_GRP *)pnode->OSFlagNodeFlagGrp; + 80130dc: e0bffb17 ldw r2,-20(fp) + 80130e0: 10800317 ldw r2,12(r2) + 80130e4: e0bffd15 stw r2,-12(fp) + pgrp->OSFlagWaitList = (void *)pnode_next; /* Update list for new 1st node */ + 80130e8: e0bffd17 ldw r2,-12(fp) + 80130ec: e0fffe17 ldw r3,-8(fp) + 80130f0: 10c00115 stw r3,4(r2) + if (pnode_next != (OS_FLAG_NODE *)0) { + 80130f4: e0bffe17 ldw r2,-8(fp) + 80130f8: 10000b26 beq r2,zero,8013128 + pnode_next->OSFlagNodePrev = (OS_FLAG_NODE *)0; /* Link new 1st node PREV to NULL */ + 80130fc: e0bffe17 ldw r2,-8(fp) + 8013100: 10000115 stw zero,4(r2) + 8013104: 00000806 br 8013128 + } + } else { /* No, A node somewhere in the list */ + pnode_prev->OSFlagNodeNext = pnode_next; /* Link around the node to unlink */ + 8013108: e0bfff17 ldw r2,-4(fp) + 801310c: e0fffe17 ldw r3,-8(fp) + 8013110: 10c00015 stw r3,0(r2) + if (pnode_next != (OS_FLAG_NODE *)0) { /* Was this the LAST node? */ + 8013114: e0bffe17 ldw r2,-8(fp) + 8013118: 10000326 beq r2,zero,8013128 + pnode_next->OSFlagNodePrev = pnode_prev; /* No, Link around current node */ + 801311c: e0bffe17 ldw r2,-8(fp) + 8013120: e0ffff17 ldw r3,-4(fp) + 8013124: 10c00115 stw r3,4(r2) + } + } +#if OS_TASK_DEL_EN > 0 + ptcb = (OS_TCB *)pnode->OSFlagNodeTCB; + 8013128: e0bffb17 ldw r2,-20(fp) + 801312c: 10800217 ldw r2,8(r2) + 8013130: e0bffc15 stw r2,-16(fp) + ptcb->OSTCBFlagNode = (OS_FLAG_NODE *)0; + 8013134: e0bffc17 ldw r2,-16(fp) + 8013138: 10000a15 stw zero,40(r2) +#endif +} + 801313c: 0001883a nop + 8013140: e037883a mov sp,fp + 8013144: df000017 ldw fp,0(sp) + 8013148: dec00104 addi sp,sp,4 + 801314c: f800283a ret + +08013150 : +* free partition is available. +********************************************************************************************************* +*/ + +OS_MEM *OSMemCreate (void *addr, INT32U nblks, INT32U blksize, INT8U *perr) +{ + 8013150: defff404 addi sp,sp,-48 + 8013154: df000b15 stw fp,44(sp) + 8013158: df000b04 addi fp,sp,44 + 801315c: e13ff815 stw r4,-32(fp) + 8013160: e17ff715 stw r5,-36(fp) + 8013164: e1bff615 stw r6,-40(fp) + 8013168: e1fff515 stw r7,-44(fp) + OS_MEM *pmem; + INT8U *pblk; + void **plink; + INT32U i; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 801316c: e03ffc15 stw zero,-16(fp) + NIOS2_READ_STATUS (context); + 8013170: 0005303a rdctl r2,status + 8013174: e0bffa15 stw r2,-24(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8013178: e0fffa17 ldw r3,-24(fp) + 801317c: 00bfff84 movi r2,-2 + 8013180: 1884703a and r2,r3,r2 + 8013184: 1001703a wrctl status,r2 + return context; + 8013188: e0bffa17 ldw r2,-24(fp) + if (blksize < sizeof(void *)) { /* Must contain space for at least a pointer */ + *perr = OS_ERR_MEM_INVALID_SIZE; + return ((OS_MEM *)0); + } +#endif + OS_ENTER_CRITICAL(); + 801318c: e0bffc15 stw r2,-16(fp) + pmem = OSMemFreeList; /* Get next free memory partition */ + 8013190: d0a05217 ldw r2,-32440(gp) + 8013194: e0bffb15 stw r2,-20(fp) + if (OSMemFreeList != (OS_MEM *)0) { /* See if pool of free partitions was empty */ + 8013198: d0a05217 ldw r2,-32440(gp) + 801319c: 10000326 beq r2,zero,80131ac + OSMemFreeList = (OS_MEM *)OSMemFreeList->OSMemFreeList; + 80131a0: d0a05217 ldw r2,-32440(gp) + 80131a4: 10800117 ldw r2,4(r2) + 80131a8: d0a05215 stw r2,-32440(gp) + 80131ac: e0bffc17 ldw r2,-16(fp) + 80131b0: e0bff915 stw r2,-28(fp) + NIOS2_WRITE_STATUS (context); + 80131b4: e0bff917 ldw r2,-28(fp) + 80131b8: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + if (pmem == (OS_MEM *)0) { /* See if we have a memory partition */ + 80131bc: e0bffb17 ldw r2,-20(fp) + 80131c0: 1000051e bne r2,zero,80131d8 + *perr = OS_ERR_MEM_INVALID_PART; + 80131c4: e0bff517 ldw r2,-44(fp) + 80131c8: 00c01684 movi r3,90 + 80131cc: 10c00005 stb r3,0(r2) + return ((OS_MEM *)0); + 80131d0: 0005883a mov r2,zero + 80131d4: 00002c06 br 8013288 + } + plink = (void **)addr; /* Create linked list of free memory blocks */ + 80131d8: e0bff817 ldw r2,-32(fp) + 80131dc: e0bffe15 stw r2,-8(fp) + pblk = (INT8U *)((INT32U)addr + blksize); + 80131e0: e0fff817 ldw r3,-32(fp) + 80131e4: e0bff617 ldw r2,-40(fp) + 80131e8: 1885883a add r2,r3,r2 + 80131ec: e0bfff15 stw r2,-4(fp) + for (i = 0; i < (nblks - 1); i++) { + 80131f0: e03ffd15 stw zero,-12(fp) + 80131f4: 00000c06 br 8013228 + *plink = (void *)pblk; /* Save pointer to NEXT block in CURRENT block */ + 80131f8: e0bffe17 ldw r2,-8(fp) + 80131fc: e0ffff17 ldw r3,-4(fp) + 8013200: 10c00015 stw r3,0(r2) + plink = (void **)pblk; /* Position to NEXT block */ + 8013204: e0bfff17 ldw r2,-4(fp) + 8013208: e0bffe15 stw r2,-8(fp) + pblk = (INT8U *)((INT32U)pblk + blksize); /* Point to the FOLLOWING block */ + 801320c: e0ffff17 ldw r3,-4(fp) + 8013210: e0bff617 ldw r2,-40(fp) + 8013214: 1885883a add r2,r3,r2 + 8013218: e0bfff15 stw r2,-4(fp) + for (i = 0; i < (nblks - 1); i++) { + 801321c: e0bffd17 ldw r2,-12(fp) + 8013220: 10800044 addi r2,r2,1 + 8013224: e0bffd15 stw r2,-12(fp) + 8013228: e0bff717 ldw r2,-36(fp) + 801322c: 10bfffc4 addi r2,r2,-1 + 8013230: e0fffd17 ldw r3,-12(fp) + 8013234: 18bff036 bltu r3,r2,80131f8 + } + *plink = (void *)0; /* Last memory block points to NULL */ + 8013238: e0bffe17 ldw r2,-8(fp) + 801323c: 10000015 stw zero,0(r2) + pmem->OSMemAddr = addr; /* Store start address of memory partition */ + 8013240: e0bffb17 ldw r2,-20(fp) + 8013244: e0fff817 ldw r3,-32(fp) + 8013248: 10c00015 stw r3,0(r2) + pmem->OSMemFreeList = addr; /* Initialize pointer to pool of free blocks */ + 801324c: e0bffb17 ldw r2,-20(fp) + 8013250: e0fff817 ldw r3,-32(fp) + 8013254: 10c00115 stw r3,4(r2) + pmem->OSMemNFree = nblks; /* Store number of free blocks in MCB */ + 8013258: e0bffb17 ldw r2,-20(fp) + 801325c: e0fff717 ldw r3,-36(fp) + 8013260: 10c00415 stw r3,16(r2) + pmem->OSMemNBlks = nblks; + 8013264: e0bffb17 ldw r2,-20(fp) + 8013268: e0fff717 ldw r3,-36(fp) + 801326c: 10c00315 stw r3,12(r2) + pmem->OSMemBlkSize = blksize; /* Store block size of each memory blocks */ + 8013270: e0bffb17 ldw r2,-20(fp) + 8013274: e0fff617 ldw r3,-40(fp) + 8013278: 10c00215 stw r3,8(r2) + *perr = OS_ERR_NONE; + 801327c: e0bff517 ldw r2,-44(fp) + 8013280: 10000005 stb zero,0(r2) + return (pmem); + 8013284: e0bffb17 ldw r2,-20(fp) +} + 8013288: e037883a mov sp,fp + 801328c: df000017 ldw fp,0(sp) + 8013290: dec00104 addi sp,sp,4 + 8013294: f800283a ret + +08013298 : +* A pointer to NULL if an error is detected +********************************************************************************************************* +*/ + +void *OSMemGet (OS_MEM *pmem, INT8U *perr) +{ + 8013298: defff804 addi sp,sp,-32 + 801329c: df000715 stw fp,28(sp) + 80132a0: df000704 addi fp,sp,28 + 80132a4: e13ffa15 stw r4,-24(fp) + 80132a8: e17ff915 stw r5,-28(fp) + void *pblk; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 80132ac: e03fff15 stw zero,-4(fp) + NIOS2_READ_STATUS (context); + 80132b0: 0005303a rdctl r2,status + 80132b4: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 80132b8: e0fffd17 ldw r3,-12(fp) + 80132bc: 00bfff84 movi r2,-2 + 80132c0: 1884703a and r2,r3,r2 + 80132c4: 1001703a wrctl status,r2 + return context; + 80132c8: e0bffd17 ldw r2,-12(fp) + if (pmem == (OS_MEM *)0) { /* Must point to a valid memory partition */ + *perr = OS_ERR_MEM_INVALID_PMEM; + return ((void *)0); + } +#endif + OS_ENTER_CRITICAL(); + 80132cc: e0bfff15 stw r2,-4(fp) + if (pmem->OSMemNFree > 0) { /* See if there are any free memory blocks */ + 80132d0: e0bffa17 ldw r2,-24(fp) + 80132d4: 10800417 ldw r2,16(r2) + 80132d8: 10001426 beq r2,zero,801332c + pblk = pmem->OSMemFreeList; /* Yes, point to next free memory block */ + 80132dc: e0bffa17 ldw r2,-24(fp) + 80132e0: 10800117 ldw r2,4(r2) + 80132e4: e0bffe15 stw r2,-8(fp) + pmem->OSMemFreeList = *(void **)pblk; /* Adjust pointer to new free list */ + 80132e8: e0bffe17 ldw r2,-8(fp) + 80132ec: 10c00017 ldw r3,0(r2) + 80132f0: e0bffa17 ldw r2,-24(fp) + 80132f4: 10c00115 stw r3,4(r2) + pmem->OSMemNFree--; /* One less memory block in this partition */ + 80132f8: e0bffa17 ldw r2,-24(fp) + 80132fc: 10800417 ldw r2,16(r2) + 8013300: 10ffffc4 addi r3,r2,-1 + 8013304: e0bffa17 ldw r2,-24(fp) + 8013308: 10c00415 stw r3,16(r2) + 801330c: e0bfff17 ldw r2,-4(fp) + 8013310: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 8013314: e0bffc17 ldw r2,-16(fp) + 8013318: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; /* No error */ + 801331c: e0bff917 ldw r2,-28(fp) + 8013320: 10000005 stb zero,0(r2) + return (pblk); /* Return memory block to caller */ + 8013324: e0bffe17 ldw r2,-8(fp) + 8013328: 00000806 br 801334c + 801332c: e0bfff17 ldw r2,-4(fp) + 8013330: e0bffb15 stw r2,-20(fp) + 8013334: e0bffb17 ldw r2,-20(fp) + 8013338: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_MEM_NO_FREE_BLKS; /* No, Notify caller of empty memory partition */ + 801333c: e0bff917 ldw r2,-28(fp) + 8013340: 00c01744 movi r3,93 + 8013344: 10c00005 stb r3,0(r2) + return ((void *)0); /* Return NULL pointer to caller */ + 8013348: 0005883a mov r2,zero +} + 801334c: e037883a mov sp,fp + 8013350: df000017 ldw fp,0(sp) + 8013354: dec00104 addi sp,sp,4 + 8013358: f800283a ret + +0801335c : +********************************************************************************************************* +*/ + +#if OS_MEM_NAME_SIZE > 1 +INT8U OSMemNameGet (OS_MEM *pmem, INT8U *pname, INT8U *perr) +{ + 801335c: defff704 addi sp,sp,-36 + 8013360: dfc00815 stw ra,32(sp) + 8013364: df000715 stw fp,28(sp) + 8013368: df000704 addi fp,sp,28 + 801336c: e13ffb15 stw r4,-20(fp) + 8013370: e17ffa15 stw r5,-24(fp) + 8013374: e1bff915 stw r6,-28(fp) + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8013378: e03fff15 stw zero,-4(fp) + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + *perr = OS_ERR_PNAME_NULL; + return (0); + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 801337c: d0a05703 ldbu r2,-32420(gp) + 8013380: 10803fcc andi r2,r2,255 + 8013384: 10000526 beq r2,zero,801339c + *perr = OS_ERR_NAME_GET_ISR; + 8013388: e0bff917 ldw r2,-28(fp) + 801338c: 00c00444 movi r3,17 + 8013390: 10c00005 stb r3,0(r2) + return (0); + 8013394: 0005883a mov r2,zero + 8013398: 00001506 br 80133f0 + NIOS2_READ_STATUS (context); + 801339c: 0005303a rdctl r2,status + 80133a0: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 80133a4: e0fffc17 ldw r3,-16(fp) + 80133a8: 00bfff84 movi r2,-2 + 80133ac: 1884703a and r2,r3,r2 + 80133b0: 1001703a wrctl status,r2 + return context; + 80133b4: e0bffc17 ldw r2,-16(fp) + } + OS_ENTER_CRITICAL(); + 80133b8: e0bfff15 stw r2,-4(fp) + len = OS_StrCopy(pname, pmem->OSMemName); /* Copy name from OS_MEM */ + 80133bc: e0bffb17 ldw r2,-20(fp) + 80133c0: 10800504 addi r2,r2,20 + 80133c4: 100b883a mov r5,r2 + 80133c8: e13ffa17 ldw r4,-24(fp) + 80133cc: 80117a00 call 80117a0 + 80133d0: e0bffec5 stb r2,-5(fp) + 80133d4: e0bfff17 ldw r2,-4(fp) + 80133d8: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context); + 80133dc: e0bffd17 ldw r2,-12(fp) + 80133e0: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 80133e4: e0bff917 ldw r2,-28(fp) + 80133e8: 10000005 stb zero,0(r2) + return (len); + 80133ec: e0bffec3 ldbu r2,-5(fp) +} + 80133f0: e037883a mov sp,fp + 80133f4: dfc00117 ldw ra,4(sp) + 80133f8: df000017 ldw fp,0(sp) + 80133fc: dec00204 addi sp,sp,8 + 8013400: f800283a ret + +08013404 : +********************************************************************************************************* +*/ + +#if OS_MEM_NAME_SIZE > 1 +void OSMemNameSet (OS_MEM *pmem, INT8U *pname, INT8U *perr) +{ + 8013404: defff604 addi sp,sp,-40 + 8013408: dfc00915 stw ra,36(sp) + 801340c: df000815 stw fp,32(sp) + 8013410: df000804 addi fp,sp,32 + 8013414: e13ffa15 stw r4,-24(fp) + 8013418: e17ff915 stw r5,-28(fp) + 801341c: e1bff815 stw r6,-32(fp) + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8013420: e03fff15 stw zero,-4(fp) + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + *perr = OS_ERR_PNAME_NULL; + return; + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 8013424: d0a05703 ldbu r2,-32420(gp) + 8013428: 10803fcc andi r2,r2,255 + 801342c: 10000426 beq r2,zero,8013440 + *perr = OS_ERR_NAME_SET_ISR; + 8013430: e0bff817 ldw r2,-32(fp) + 8013434: 00c00484 movi r3,18 + 8013438: 10c00005 stb r3,0(r2) + return; + 801343c: 00002106 br 80134c4 + NIOS2_READ_STATUS (context); + 8013440: 0005303a rdctl r2,status + 8013444: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8013448: e0fffd17 ldw r3,-12(fp) + 801344c: 00bfff84 movi r2,-2 + 8013450: 1884703a and r2,r3,r2 + 8013454: 1001703a wrctl status,r2 + return context; + 8013458: e0bffd17 ldw r2,-12(fp) + } + OS_ENTER_CRITICAL(); + 801345c: e0bfff15 stw r2,-4(fp) + len = OS_StrLen(pname); /* Can we fit the string in the storage area? */ + 8013460: e13ff917 ldw r4,-28(fp) + 8013464: 80118140 call 8011814 + 8013468: e0bffec5 stb r2,-5(fp) + if (len > (OS_MEM_NAME_SIZE - 1)) { /* No */ + 801346c: e0bffec3 ldbu r2,-5(fp) + 8013470: 10800830 cmpltui r2,r2,32 + 8013474: 1000081e bne r2,zero,8013498 + 8013478: e0bfff17 ldw r2,-4(fp) + 801347c: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 8013480: e0bffc17 ldw r2,-16(fp) + 8013484: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_MEM_NAME_TOO_LONG; + 8013488: e0bff817 ldw r2,-32(fp) + 801348c: 00c018c4 movi r3,99 + 8013490: 10c00005 stb r3,0(r2) + return; + 8013494: 00000b06 br 80134c4 + } + (void)OS_StrCopy(pmem->OSMemName, pname); /* Yes, copy name to the memory partition header */ + 8013498: e0bffa17 ldw r2,-24(fp) + 801349c: 10800504 addi r2,r2,20 + 80134a0: e17ff917 ldw r5,-28(fp) + 80134a4: 1009883a mov r4,r2 + 80134a8: 80117a00 call 80117a0 + 80134ac: e0bfff17 ldw r2,-4(fp) + 80134b0: e0bffb15 stw r2,-20(fp) + 80134b4: e0bffb17 ldw r2,-20(fp) + 80134b8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 80134bc: e0bff817 ldw r2,-32(fp) + 80134c0: 10000005 stb zero,0(r2) +} + 80134c4: e037883a mov sp,fp + 80134c8: dfc00117 ldw ra,4(sp) + 80134cc: df000017 ldw fp,0(sp) + 80134d0: dec00204 addi sp,sp,8 + 80134d4: f800283a ret + +080134d8 : +* OS_ERR_MEM_INVALID_PBLK if you passed a NULL pointer for the block to release. +********************************************************************************************************* +*/ + +INT8U OSMemPut (OS_MEM *pmem, void *pblk) +{ + 80134d8: defff904 addi sp,sp,-28 + 80134dc: df000615 stw fp,24(sp) + 80134e0: df000604 addi fp,sp,24 + 80134e4: e13ffb15 stw r4,-20(fp) + 80134e8: e17ffa15 stw r5,-24(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 80134ec: e03fff15 stw zero,-4(fp) + NIOS2_READ_STATUS (context); + 80134f0: 0005303a rdctl r2,status + 80134f4: e0bffe15 stw r2,-8(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 80134f8: e0fffe17 ldw r3,-8(fp) + 80134fc: 00bfff84 movi r2,-2 + 8013500: 1884703a and r2,r3,r2 + 8013504: 1001703a wrctl status,r2 + return context; + 8013508: e0bffe17 ldw r2,-8(fp) + } + if (pblk == (void *)0) { /* Must release a valid block */ + return (OS_ERR_MEM_INVALID_PBLK); + } +#endif + OS_ENTER_CRITICAL(); + 801350c: e0bfff15 stw r2,-4(fp) + if (pmem->OSMemNFree >= pmem->OSMemNBlks) { /* Make sure all blocks not already returned */ + 8013510: e0bffb17 ldw r2,-20(fp) + 8013514: 10c00417 ldw r3,16(r2) + 8013518: e0bffb17 ldw r2,-20(fp) + 801351c: 10800317 ldw r2,12(r2) + 8013520: 18800636 bltu r3,r2,801353c + 8013524: e0bfff17 ldw r2,-4(fp) + 8013528: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context); + 801352c: e0bffd17 ldw r2,-12(fp) + 8013530: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_MEM_FULL); + 8013534: 00801784 movi r2,94 + 8013538: 00001106 br 8013580 + } + *(void **)pblk = pmem->OSMemFreeList; /* Insert released block into free block list */ + 801353c: e0bffb17 ldw r2,-20(fp) + 8013540: 10c00117 ldw r3,4(r2) + 8013544: e0bffa17 ldw r2,-24(fp) + 8013548: 10c00015 stw r3,0(r2) + pmem->OSMemFreeList = pblk; + 801354c: e0bffb17 ldw r2,-20(fp) + 8013550: e0fffa17 ldw r3,-24(fp) + 8013554: 10c00115 stw r3,4(r2) + pmem->OSMemNFree++; /* One more memory block in this partition */ + 8013558: e0bffb17 ldw r2,-20(fp) + 801355c: 10800417 ldw r2,16(r2) + 8013560: 10c00044 addi r3,r2,1 + 8013564: e0bffb17 ldw r2,-20(fp) + 8013568: 10c00415 stw r3,16(r2) + 801356c: e0bfff17 ldw r2,-4(fp) + 8013570: e0bffc15 stw r2,-16(fp) + 8013574: e0bffc17 ldw r2,-16(fp) + 8013578: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); /* Notify caller that memory block was released */ + 801357c: 0005883a mov r2,zero +} + 8013580: e037883a mov sp,fp + 8013584: df000017 ldw fp,0(sp) + 8013588: dec00104 addi sp,sp,4 + 801358c: f800283a ret + +08013590 : +********************************************************************************************************* +*/ + +#if OS_MEM_QUERY_EN > 0 +INT8U OSMemQuery (OS_MEM *pmem, OS_MEM_DATA *p_mem_data) +{ + 8013590: defffa04 addi sp,sp,-24 + 8013594: df000515 stw fp,20(sp) + 8013598: df000504 addi fp,sp,20 + 801359c: e13ffc15 stw r4,-16(fp) + 80135a0: e17ffb15 stw r5,-20(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 80135a4: e03fff15 stw zero,-4(fp) + NIOS2_READ_STATUS (context); + 80135a8: 0005303a rdctl r2,status + 80135ac: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 80135b0: e0fffd17 ldw r3,-12(fp) + 80135b4: 00bfff84 movi r2,-2 + 80135b8: 1884703a and r2,r3,r2 + 80135bc: 1001703a wrctl status,r2 + return context; + 80135c0: e0bffd17 ldw r2,-12(fp) + } + if (p_mem_data == (OS_MEM_DATA *)0) { /* Must release a valid storage area for the data */ + return (OS_ERR_MEM_INVALID_PDATA); + } +#endif + OS_ENTER_CRITICAL(); + 80135c4: e0bfff15 stw r2,-4(fp) + p_mem_data->OSAddr = pmem->OSMemAddr; + 80135c8: e0bffc17 ldw r2,-16(fp) + 80135cc: 10c00017 ldw r3,0(r2) + 80135d0: e0bffb17 ldw r2,-20(fp) + 80135d4: 10c00015 stw r3,0(r2) + p_mem_data->OSFreeList = pmem->OSMemFreeList; + 80135d8: e0bffc17 ldw r2,-16(fp) + 80135dc: 10c00117 ldw r3,4(r2) + 80135e0: e0bffb17 ldw r2,-20(fp) + 80135e4: 10c00115 stw r3,4(r2) + p_mem_data->OSBlkSize = pmem->OSMemBlkSize; + 80135e8: e0bffc17 ldw r2,-16(fp) + 80135ec: 10c00217 ldw r3,8(r2) + 80135f0: e0bffb17 ldw r2,-20(fp) + 80135f4: 10c00215 stw r3,8(r2) + p_mem_data->OSNBlks = pmem->OSMemNBlks; + 80135f8: e0bffc17 ldw r2,-16(fp) + 80135fc: 10c00317 ldw r3,12(r2) + 8013600: e0bffb17 ldw r2,-20(fp) + 8013604: 10c00315 stw r3,12(r2) + p_mem_data->OSNFree = pmem->OSMemNFree; + 8013608: e0bffc17 ldw r2,-16(fp) + 801360c: 10c00417 ldw r3,16(r2) + 8013610: e0bffb17 ldw r2,-20(fp) + 8013614: 10c00415 stw r3,16(r2) + 8013618: e0bfff17 ldw r2,-4(fp) + 801361c: e0bffe15 stw r2,-8(fp) + NIOS2_WRITE_STATUS (context); + 8013620: e0bffe17 ldw r2,-8(fp) + 8013624: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + p_mem_data->OSNUsed = p_mem_data->OSNBlks - p_mem_data->OSNFree; + 8013628: e0bffb17 ldw r2,-20(fp) + 801362c: 10c00317 ldw r3,12(r2) + 8013630: e0bffb17 ldw r2,-20(fp) + 8013634: 10800417 ldw r2,16(r2) + 8013638: 1887c83a sub r3,r3,r2 + 801363c: e0bffb17 ldw r2,-20(fp) + 8013640: 10c00515 stw r3,20(r2) + return (OS_ERR_NONE); + 8013644: 0005883a mov r2,zero +} + 8013648: e037883a mov sp,fp + 801364c: df000017 ldw fp,0(sp) + 8013650: dec00104 addi sp,sp,4 + 8013654: f800283a ret + +08013658 : +* Note(s) : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +void OS_MemInit (void) +{ + 8013658: defffc04 addi sp,sp,-16 + 801365c: dfc00315 stw ra,12(sp) + 8013660: df000215 stw fp,8(sp) + 8013664: df000204 addi fp,sp,8 +#if OS_MAX_MEM_PART >= 2 + OS_MEM *pmem; + INT16U i; + + + OS_MemClr((INT8U *)&OSMemTbl[0], sizeof(OSMemTbl)); /* Clear the memory partition table */ + 8013668: 01430c04 movi r5,3120 + 801366c: 010201b4 movhi r4,2054 + 8013670: 212c6704 addi r4,r4,-20068 + 8013674: 80115b00 call 80115b0 + pmem = &OSMemTbl[0]; /* Point to memory control block (MCB) */ + 8013678: 008201b4 movhi r2,2054 + 801367c: 10ac6704 addi r2,r2,-20068 + 8013680: e0bfff15 stw r2,-4(fp) + for (i = 0; i < (OS_MAX_MEM_PART - 1); i++) { /* Init. list of free memory partitions */ + 8013684: e03ffe8d sth zero,-6(fp) + 8013688: 00001306 br 80136d8 + pmem->OSMemFreeList = (void *)&OSMemTbl[i+1]; /* Chain list of free partitions */ + 801368c: e0bffe8b ldhu r2,-6(fp) + 8013690: 10800044 addi r2,r2,1 + 8013694: 10c00d24 muli r3,r2,52 + 8013698: 008201b4 movhi r2,2054 + 801369c: 10ac6704 addi r2,r2,-20068 + 80136a0: 1887883a add r3,r3,r2 + 80136a4: e0bfff17 ldw r2,-4(fp) + 80136a8: 10c00115 stw r3,4(r2) +#if OS_MEM_NAME_SIZE > 1 + pmem->OSMemName[0] = '?'; /* Unknown name */ + 80136ac: e0bfff17 ldw r2,-4(fp) + 80136b0: 00c00fc4 movi r3,63 + 80136b4: 10c00505 stb r3,20(r2) + pmem->OSMemName[1] = OS_ASCII_NUL; + 80136b8: e0bfff17 ldw r2,-4(fp) + 80136bc: 10000545 stb zero,21(r2) +#endif + pmem++; + 80136c0: e0bfff17 ldw r2,-4(fp) + 80136c4: 10800d04 addi r2,r2,52 + 80136c8: e0bfff15 stw r2,-4(fp) + for (i = 0; i < (OS_MAX_MEM_PART - 1); i++) { /* Init. list of free memory partitions */ + 80136cc: e0bffe8b ldhu r2,-6(fp) + 80136d0: 10800044 addi r2,r2,1 + 80136d4: e0bffe8d sth r2,-6(fp) + 80136d8: e0bffe8b ldhu r2,-6(fp) + 80136dc: 10800ef0 cmpltui r2,r2,59 + 80136e0: 103fea1e bne r2,zero,801368c + } + pmem->OSMemFreeList = (void *)0; /* Initialize last node */ + 80136e4: e0bfff17 ldw r2,-4(fp) + 80136e8: 10000115 stw zero,4(r2) +#if OS_MEM_NAME_SIZE > 1 + pmem->OSMemName[0] = '?'; /* Unknown name */ + 80136ec: e0bfff17 ldw r2,-4(fp) + 80136f0: 00c00fc4 movi r3,63 + 80136f4: 10c00505 stb r3,20(r2) + pmem->OSMemName[1] = OS_ASCII_NUL; + 80136f8: e0bfff17 ldw r2,-4(fp) + 80136fc: 10000545 stb zero,21(r2) +#endif + + OSMemFreeList = &OSMemTbl[0]; /* Point to beginning of free list */ + 8013700: 008201b4 movhi r2,2054 + 8013704: 10ac6704 addi r2,r2,-20068 + 8013708: d0a05215 stw r2,-32440(gp) +#endif +} + 801370c: 0001883a nop + 8013710: e037883a mov sp,fp + 8013714: dfc00117 ldw ra,4(sp) + 8013718: df000017 ldw fp,0(sp) + 801371c: dec00204 addi sp,sp,8 + 8013720: f800283a ret + +08013724 : +********************************************************************************************************* +*/ + +#if OS_MUTEX_ACCEPT_EN > 0 +BOOLEAN OSMutexAccept (OS_EVENT *pevent, INT8U *perr) +{ + 8013724: defff704 addi sp,sp,-36 + 8013728: df000815 stw fp,32(sp) + 801372c: df000804 addi fp,sp,32 + 8013730: e13ff915 stw r4,-28(fp) + 8013734: e17ff815 stw r5,-32(fp) + INT8U pip; /* Priority Inheritance Priority (PIP) */ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8013738: e03fff15 stw zero,-4(fp) + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return (OS_FALSE); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) { /* Validate event block type */ + 801373c: e0bff917 ldw r2,-28(fp) + 8013740: 10800003 ldbu r2,0(r2) + 8013744: 10803fcc andi r2,r2,255 + 8013748: 10800120 cmpeqi r2,r2,4 + 801374c: 1000051e bne r2,zero,8013764 + *perr = OS_ERR_EVENT_TYPE; + 8013750: e0bff817 ldw r2,-32(fp) + 8013754: 00c00044 movi r3,1 + 8013758: 10c00005 stb r3,0(r2) + return (OS_FALSE); + 801375c: 0005883a mov r2,zero + 8013760: 00004a06 br 801388c + } + if (OSIntNesting > 0) { /* Make sure it's not called from an ISR */ + 8013764: d0a05703 ldbu r2,-32420(gp) + 8013768: 10803fcc andi r2,r2,255 + 801376c: 10000526 beq r2,zero,8013784 + *perr = OS_ERR_PEND_ISR; + 8013770: e0bff817 ldw r2,-32(fp) + 8013774: 00c00084 movi r3,2 + 8013778: 10c00005 stb r3,0(r2) + return (OS_FALSE); + 801377c: 0005883a mov r2,zero + 8013780: 00004206 br 801388c + NIOS2_READ_STATUS (context); + 8013784: 0005303a rdctl r2,status + 8013788: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 801378c: e0fffd17 ldw r3,-12(fp) + 8013790: 00bfff84 movi r2,-2 + 8013794: 1884703a and r2,r3,r2 + 8013798: 1001703a wrctl status,r2 + return context; + 801379c: e0bffd17 ldw r2,-12(fp) + } + OS_ENTER_CRITICAL(); /* Get value (0 or 1) of Mutex */ + 80137a0: e0bfff15 stw r2,-4(fp) + pip = (INT8U)(pevent->OSEventCnt >> 8); /* Get PIP from mutex */ + 80137a4: e0bff917 ldw r2,-28(fp) + 80137a8: 1080020b ldhu r2,8(r2) + 80137ac: 10bfffcc andi r2,r2,65535 + 80137b0: 1004d23a srli r2,r2,8 + 80137b4: e0bffec5 stb r2,-5(fp) + if ((pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8) == OS_MUTEX_AVAILABLE) { + 80137b8: e0bff917 ldw r2,-28(fp) + 80137bc: 1080020b ldhu r2,8(r2) + 80137c0: 10bfffcc andi r2,r2,65535 + 80137c4: 10803fcc andi r2,r2,255 + 80137c8: 10803fd8 cmpnei r2,r2,255 + 80137cc: 1000281e bne r2,zero,8013870 + pevent->OSEventCnt &= OS_MUTEX_KEEP_UPPER_8; /* Mask off LSByte (Acquire Mutex) */ + 80137d0: e0bff917 ldw r2,-28(fp) + 80137d4: 10c0020b ldhu r3,8(r2) + 80137d8: 00bfc004 movi r2,-256 + 80137dc: 1884703a and r2,r3,r2 + 80137e0: 1007883a mov r3,r2 + 80137e4: e0bff917 ldw r2,-28(fp) + 80137e8: 10c0020d sth r3,8(r2) + pevent->OSEventCnt |= OSTCBCur->OSTCBPrio; /* Save current task priority in LSByte */ + 80137ec: e0bff917 ldw r2,-28(fp) + 80137f0: 10c0020b ldhu r3,8(r2) + 80137f4: d0a05817 ldw r2,-32416(gp) + 80137f8: 10800c83 ldbu r2,50(r2) + 80137fc: 10803fcc andi r2,r2,255 + 8013800: 1884b03a or r2,r3,r2 + 8013804: 1007883a mov r3,r2 + 8013808: e0bff917 ldw r2,-28(fp) + 801380c: 10c0020d sth r3,8(r2) + pevent->OSEventPtr = (void *)OSTCBCur; /* Link TCB of task owning Mutex */ + 8013810: d0e05817 ldw r3,-32416(gp) + 8013814: e0bff917 ldw r2,-28(fp) + 8013818: 10c00115 stw r3,4(r2) + if (OSTCBCur->OSTCBPrio <= pip) { /* PIP 'must' have a SMALLER prio ... */ + 801381c: d0a05817 ldw r2,-32416(gp) + 8013820: 10800c83 ldbu r2,50(r2) + 8013824: e0fffec3 ldbu r3,-5(fp) + 8013828: 10803fcc andi r2,r2,255 + 801382c: 18800836 bltu r3,r2,8013850 + 8013830: e0bfff17 ldw r2,-4(fp) + 8013834: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 8013838: e0bffc17 ldw r2,-16(fp) + 801383c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* ... than current task! */ + *perr = OS_ERR_PIP_LOWER; + 8013840: e0bff817 ldw r2,-32(fp) + 8013844: 00c01e04 movi r3,120 + 8013848: 10c00005 stb r3,0(r2) + 801384c: 00000606 br 8013868 + 8013850: e0bfff17 ldw r2,-4(fp) + 8013854: e0bffb15 stw r2,-20(fp) + 8013858: e0bffb17 ldw r2,-20(fp) + 801385c: 1001703a wrctl status,r2 + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 8013860: e0bff817 ldw r2,-32(fp) + 8013864: 10000005 stb zero,0(r2) + } + return (OS_TRUE); + 8013868: 00800044 movi r2,1 + 801386c: 00000706 br 801388c + 8013870: e0bfff17 ldw r2,-4(fp) + 8013874: e0bffa15 stw r2,-24(fp) + 8013878: e0bffa17 ldw r2,-24(fp) + 801387c: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 8013880: e0bff817 ldw r2,-32(fp) + 8013884: 10000005 stb zero,0(r2) + return (OS_FALSE); + 8013888: 0005883a mov r2,zero +} + 801388c: e037883a mov sp,fp + 8013890: df000017 ldw fp,0(sp) + 8013894: dec00104 addi sp,sp,4 + 8013898: f800283a ret + +0801389c : +* to use to reduce priority inversion. +********************************************************************************************************* +*/ + +OS_EVENT *OSMutexCreate (INT8U prio, INT8U *perr) +{ + 801389c: defff604 addi sp,sp,-40 + 80138a0: dfc00915 stw ra,36(sp) + 80138a4: df000815 stw fp,32(sp) + 80138a8: df000804 addi fp,sp,32 + 80138ac: 2005883a mov r2,r4 + 80138b0: e17ff815 stw r5,-32(fp) + 80138b4: e0bff905 stb r2,-28(fp) + OS_EVENT *pevent; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 80138b8: e03fff15 stw zero,-4(fp) + if (prio >= OS_LOWEST_PRIO) { /* Validate PIP */ + *perr = OS_ERR_PRIO_INVALID; + return ((OS_EVENT *)0); + } +#endif + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 80138bc: d0a05703 ldbu r2,-32420(gp) + 80138c0: 10803fcc andi r2,r2,255 + 80138c4: 10000526 beq r2,zero,80138dc + *perr = OS_ERR_CREATE_ISR; /* ... can't CREATE mutex from an ISR */ + 80138c8: e0bff817 ldw r2,-32(fp) + 80138cc: 00c00404 movi r3,16 + 80138d0: 10c00005 stb r3,0(r2) + return ((OS_EVENT *)0); + 80138d4: 0005883a mov r2,zero + 80138d8: 00004b06 br 8013a08 + NIOS2_READ_STATUS (context); + 80138dc: 0005303a rdctl r2,status + 80138e0: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 80138e4: e0fffd17 ldw r3,-12(fp) + 80138e8: 00bfff84 movi r2,-2 + 80138ec: 1884703a and r2,r3,r2 + 80138f0: 1001703a wrctl status,r2 + return context; + 80138f4: e0bffd17 ldw r2,-12(fp) + } + OS_ENTER_CRITICAL(); + 80138f8: e0bfff15 stw r2,-4(fp) + if (OSTCBPrioTbl[prio] != (OS_TCB *)0) { /* Mutex priority must not already exist */ + 80138fc: e0bff903 ldbu r2,-28(fp) + 8013900: 100690ba slli r3,r2,2 + 8013904: 008201b4 movhi r2,2054 + 8013908: 1885883a add r2,r3,r2 + 801390c: 10b55d17 ldw r2,-10892(r2) + 8013910: 10000926 beq r2,zero,8013938 + 8013914: e0bfff17 ldw r2,-4(fp) + 8013918: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 801391c: e0bffc17 ldw r2,-16(fp) + 8013920: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Task already exist at priority ... */ + *perr = OS_ERR_PRIO_EXIST; /* ... inheritance priority */ + 8013924: e0bff817 ldw r2,-32(fp) + 8013928: 00c00a04 movi r3,40 + 801392c: 10c00005 stb r3,0(r2) + return ((OS_EVENT *)0); + 8013930: 0005883a mov r2,zero + 8013934: 00003406 br 8013a08 + } + OSTCBPrioTbl[prio] = OS_TCB_RESERVED; /* Reserve the table entry */ + 8013938: e0bff903 ldbu r2,-28(fp) + 801393c: 100890ba slli r4,r2,2 + 8013940: 00c00044 movi r3,1 + 8013944: 008201b4 movhi r2,2054 + 8013948: 2085883a add r2,r4,r2 + 801394c: 10f55d15 stw r3,-10892(r2) + pevent = OSEventFreeList; /* Get next free event control block */ + 8013950: d0a05617 ldw r2,-32424(gp) + 8013954: e0bffe15 stw r2,-8(fp) + if (pevent == (OS_EVENT *)0) { /* See if an ECB was available */ + 8013958: e0bffe17 ldw r2,-8(fp) + 801395c: 10000e1e bne r2,zero,8013998 + OSTCBPrioTbl[prio] = (OS_TCB *)0; /* No, Release the table entry */ + 8013960: e0bff903 ldbu r2,-28(fp) + 8013964: 100690ba slli r3,r2,2 + 8013968: 008201b4 movhi r2,2054 + 801396c: 1885883a add r2,r3,r2 + 8013970: 10355d15 stw zero,-10892(r2) + 8013974: e0bfff17 ldw r2,-4(fp) + 8013978: e0bffb15 stw r2,-20(fp) + 801397c: e0bffb17 ldw r2,-20(fp) + 8013980: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_PEVENT_NULL; /* No more event control blocks */ + 8013984: e0bff817 ldw r2,-32(fp) + 8013988: 00c00104 movi r3,4 + 801398c: 10c00005 stb r3,0(r2) + return (pevent); + 8013990: e0bffe17 ldw r2,-8(fp) + 8013994: 00001c06 br 8013a08 + } + OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr; /* Adjust the free list */ + 8013998: d0a05617 ldw r2,-32424(gp) + 801399c: 10800117 ldw r2,4(r2) + 80139a0: d0a05615 stw r2,-32424(gp) + 80139a4: e0bfff17 ldw r2,-4(fp) + 80139a8: e0bffa15 stw r2,-24(fp) + 80139ac: e0bffa17 ldw r2,-24(fp) + 80139b0: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + pevent->OSEventType = OS_EVENT_TYPE_MUTEX; + 80139b4: e0bffe17 ldw r2,-8(fp) + 80139b8: 00c00104 movi r3,4 + 80139bc: 10c00005 stb r3,0(r2) + pevent->OSEventCnt = (INT16U)((INT16U)prio << 8) | OS_MUTEX_AVAILABLE; /* Resource is avail. */ + 80139c0: e0bff903 ldbu r2,-28(fp) + 80139c4: 1004923a slli r2,r2,8 + 80139c8: 10803fd4 ori r2,r2,255 + 80139cc: 1007883a mov r3,r2 + 80139d0: e0bffe17 ldw r2,-8(fp) + 80139d4: 10c0020d sth r3,8(r2) + pevent->OSEventPtr = (void *)0; /* No task owning the mutex */ + 80139d8: e0bffe17 ldw r2,-8(fp) + 80139dc: 10000115 stw zero,4(r2) +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; + 80139e0: e0bffe17 ldw r2,-8(fp) + 80139e4: 00c00fc4 movi r3,63 + 80139e8: 10c00385 stb r3,14(r2) + pevent->OSEventName[1] = OS_ASCII_NUL; + 80139ec: e0bffe17 ldw r2,-8(fp) + 80139f0: 100003c5 stb zero,15(r2) +#endif + OS_EventWaitListInit(pevent); + 80139f4: e13ffe17 ldw r4,-8(fp) + 80139f8: 80112580 call 8011258 + *perr = OS_ERR_NONE; + 80139fc: e0bff817 ldw r2,-32(fp) + 8013a00: 10000005 stb zero,0(r2) + return (pevent); + 8013a04: e0bffe17 ldw r2,-8(fp) +} + 8013a08: e037883a mov sp,fp + 8013a0c: dfc00117 ldw ra,4(sp) + 8013a10: df000017 ldw fp,0(sp) + 8013a14: dec00204 addi sp,sp,8 + 8013a18: f800283a ret + +08013a1c : +********************************************************************************************************* +*/ + +#if OS_MUTEX_DEL_EN +OS_EVENT *OSMutexDel (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + 8013a1c: defff104 addi sp,sp,-60 + 8013a20: dfc00e15 stw ra,56(sp) + 8013a24: df000d15 stw fp,52(sp) + 8013a28: df000d04 addi fp,sp,52 + 8013a2c: e13ff515 stw r4,-44(fp) + 8013a30: 2805883a mov r2,r5 + 8013a34: e1bff315 stw r6,-52(fp) + 8013a38: e0bff405 stb r2,-48(fp) + OS_EVENT *pevent_return; + INT8U pip; /* Priority inheritance priority */ + INT8U prio; + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8013a3c: e03ffd15 stw zero,-12(fp) + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return (pevent); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) { /* Validate event block type */ + 8013a40: e0bff517 ldw r2,-44(fp) + 8013a44: 10800003 ldbu r2,0(r2) + 8013a48: 10803fcc andi r2,r2,255 + 8013a4c: 10800120 cmpeqi r2,r2,4 + 8013a50: 1000051e bne r2,zero,8013a68 + *perr = OS_ERR_EVENT_TYPE; + 8013a54: e0bff317 ldw r2,-52(fp) + 8013a58: 00c00044 movi r3,1 + 8013a5c: 10c00005 stb r3,0(r2) + return (pevent); + 8013a60: e0bff517 ldw r2,-44(fp) + 8013a64: 00009806 br 8013cc8 + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 8013a68: d0a05703 ldbu r2,-32420(gp) + 8013a6c: 10803fcc andi r2,r2,255 + 8013a70: 10000526 beq r2,zero,8013a88 + *perr = OS_ERR_DEL_ISR; /* ... can't DELETE from an ISR */ + 8013a74: e0bff317 ldw r2,-52(fp) + 8013a78: 00c003c4 movi r3,15 + 8013a7c: 10c00005 stb r3,0(r2) + return (pevent); + 8013a80: e0bff517 ldw r2,-44(fp) + 8013a84: 00009006 br 8013cc8 + NIOS2_READ_STATUS (context); + 8013a88: 0005303a rdctl r2,status + 8013a8c: e0bffa15 stw r2,-24(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8013a90: e0fffa17 ldw r3,-24(fp) + 8013a94: 00bfff84 movi r2,-2 + 8013a98: 1884703a and r2,r3,r2 + 8013a9c: 1001703a wrctl status,r2 + return context; + 8013aa0: e0bffa17 ldw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + 8013aa4: e0bffd15 stw r2,-12(fp) + if (pevent->OSEventGrp != 0) { /* See if any tasks waiting on mutex */ + 8013aa8: e0bff517 ldw r2,-44(fp) + 8013aac: 10800283 ldbu r2,10(r2) + 8013ab0: 10803fcc andi r2,r2,255 + 8013ab4: 10000326 beq r2,zero,8013ac4 + tasks_waiting = OS_TRUE; /* Yes */ + 8013ab8: 00800044 movi r2,1 + 8013abc: e0bfffc5 stb r2,-1(fp) + 8013ac0: 00000106 br 8013ac8 + } else { + tasks_waiting = OS_FALSE; /* No */ + 8013ac4: e03fffc5 stb zero,-1(fp) + } + switch (opt) { + 8013ac8: e0bff403 ldbu r2,-48(fp) + 8013acc: 10000326 beq r2,zero,8013adc + 8013ad0: 10800060 cmpeqi r2,r2,1 + 8013ad4: 10002d1e bne r2,zero,8013b8c + 8013ad8: 00007006 br 8013c9c + case OS_DEL_NO_PEND: /* DELETE MUTEX ONLY IF NO TASK WAITING --- */ + if (tasks_waiting == OS_FALSE) { + 8013adc: e0bfffc3 ldbu r2,-1(fp) + 8013ae0: 1000201e bne r2,zero,8013b64 +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 8013ae4: e0bff517 ldw r2,-44(fp) + 8013ae8: 00c00fc4 movi r3,63 + 8013aec: 10c00385 stb r3,14(r2) + pevent->OSEventName[1] = OS_ASCII_NUL; + 8013af0: e0bff517 ldw r2,-44(fp) + 8013af4: 100003c5 stb zero,15(r2) +#endif + pip = (INT8U)(pevent->OSEventCnt >> 8); + 8013af8: e0bff517 ldw r2,-44(fp) + 8013afc: 1080020b ldhu r2,8(r2) + 8013b00: 10bfffcc andi r2,r2,65535 + 8013b04: 1004d23a srli r2,r2,8 + 8013b08: e0bffcc5 stb r2,-13(fp) + OSTCBPrioTbl[pip] = (OS_TCB *)0; /* Free up the PIP */ + 8013b0c: e0bffcc3 ldbu r2,-13(fp) + 8013b10: 100690ba slli r3,r2,2 + 8013b14: 008201b4 movhi r2,2054 + 8013b18: 1885883a add r2,r3,r2 + 8013b1c: 10355d15 stw zero,-10892(r2) + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + 8013b20: e0bff517 ldw r2,-44(fp) + 8013b24: 10000005 stb zero,0(r2) + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + 8013b28: d0e05617 ldw r3,-32424(gp) + 8013b2c: e0bff517 ldw r2,-44(fp) + 8013b30: 10c00115 stw r3,4(r2) + pevent->OSEventCnt = 0; + 8013b34: e0bff517 ldw r2,-44(fp) + 8013b38: 1000020d sth zero,8(r2) + OSEventFreeList = pevent; + 8013b3c: e0bff517 ldw r2,-44(fp) + 8013b40: d0a05615 stw r2,-32424(gp) + 8013b44: e0bffd17 ldw r2,-12(fp) + 8013b48: e0bff915 stw r2,-28(fp) + NIOS2_WRITE_STATUS (context); + 8013b4c: e0bff917 ldw r2,-28(fp) + 8013b50: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 8013b54: e0bff317 ldw r2,-52(fp) + 8013b58: 10000005 stb zero,0(r2) + pevent_return = (OS_EVENT *)0; /* Mutex has been deleted */ + 8013b5c: e03ffe15 stw zero,-8(fp) + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_WAITING; + pevent_return = pevent; + } + break; + 8013b60: 00005806 br 8013cc4 + 8013b64: e0bffd17 ldw r2,-12(fp) + 8013b68: e0bff815 stw r2,-32(fp) + 8013b6c: e0bff817 ldw r2,-32(fp) + 8013b70: 1001703a wrctl status,r2 + *perr = OS_ERR_TASK_WAITING; + 8013b74: e0bff317 ldw r2,-52(fp) + 8013b78: 00c01244 movi r3,73 + 8013b7c: 10c00005 stb r3,0(r2) + pevent_return = pevent; + 8013b80: e0bff517 ldw r2,-44(fp) + 8013b84: e0bffe15 stw r2,-8(fp) + break; + 8013b88: 00004e06 br 8013cc4 + + case OS_DEL_ALWAYS: /* ALWAYS DELETE THE MUTEX ---------------- */ + pip = (INT8U)(pevent->OSEventCnt >> 8); /* Get PIP of mutex */ + 8013b8c: e0bff517 ldw r2,-44(fp) + 8013b90: 1080020b ldhu r2,8(r2) + 8013b94: 10bfffcc andi r2,r2,65535 + 8013b98: 1004d23a srli r2,r2,8 + 8013b9c: e0bffcc5 stb r2,-13(fp) + prio = (INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8); /* Get owner's original prio */ + 8013ba0: e0bff517 ldw r2,-44(fp) + 8013ba4: 1080020b ldhu r2,8(r2) + 8013ba8: e0bffc85 stb r2,-14(fp) + ptcb = (OS_TCB *)pevent->OSEventPtr; + 8013bac: e0bff517 ldw r2,-44(fp) + 8013bb0: 10800117 ldw r2,4(r2) + 8013bb4: e0bffb15 stw r2,-20(fp) + if (ptcb != (OS_TCB *)0) { /* See if any task owns the mutex */ + 8013bb8: e0bffb17 ldw r2,-20(fp) + 8013bbc: 10000f26 beq r2,zero,8013bfc + if (ptcb->OSTCBPrio == pip) { /* See if original prio was changed */ + 8013bc0: e0bffb17 ldw r2,-20(fp) + 8013bc4: 10800c83 ldbu r2,50(r2) + 8013bc8: e0fffcc3 ldbu r3,-13(fp) + 8013bcc: 10803fcc andi r2,r2,255 + 8013bd0: 18800a1e bne r3,r2,8013bfc + OSMutex_RdyAtPrio(ptcb, prio); /* Yes, Restore the task's original prio */ + 8013bd4: e0bffc83 ldbu r2,-14(fp) + 8013bd8: 100b883a mov r5,r2 + 8013bdc: e13ffb17 ldw r4,-20(fp) + 8013be0: 801457c0 call 801457c + } + } + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for mutex */ + 8013be4: 00000506 br 8013bfc + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_MUTEX, OS_STAT_PEND_OK); + 8013be8: 000f883a mov r7,zero + 8013bec: 01800404 movi r6,16 + 8013bf0: 000b883a mov r5,zero + 8013bf4: e13ff517 ldw r4,-44(fp) + 8013bf8: 8010cd80 call 8010cd8 + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for mutex */ + 8013bfc: e0bff517 ldw r2,-44(fp) + 8013c00: 10800283 ldbu r2,10(r2) + 8013c04: 10803fcc andi r2,r2,255 + 8013c08: 103ff71e bne r2,zero,8013be8 + } +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 8013c0c: e0bff517 ldw r2,-44(fp) + 8013c10: 00c00fc4 movi r3,63 + 8013c14: 10c00385 stb r3,14(r2) + pevent->OSEventName[1] = OS_ASCII_NUL; + 8013c18: e0bff517 ldw r2,-44(fp) + 8013c1c: 100003c5 stb zero,15(r2) +#endif + pip = (INT8U)(pevent->OSEventCnt >> 8); + 8013c20: e0bff517 ldw r2,-44(fp) + 8013c24: 1080020b ldhu r2,8(r2) + 8013c28: 10bfffcc andi r2,r2,65535 + 8013c2c: 1004d23a srli r2,r2,8 + 8013c30: e0bffcc5 stb r2,-13(fp) + OSTCBPrioTbl[pip] = (OS_TCB *)0; /* Free up the PIP */ + 8013c34: e0bffcc3 ldbu r2,-13(fp) + 8013c38: 100690ba slli r3,r2,2 + 8013c3c: 008201b4 movhi r2,2054 + 8013c40: 1885883a add r2,r3,r2 + 8013c44: 10355d15 stw zero,-10892(r2) + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + 8013c48: e0bff517 ldw r2,-44(fp) + 8013c4c: 10000005 stb zero,0(r2) + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + 8013c50: d0e05617 ldw r3,-32424(gp) + 8013c54: e0bff517 ldw r2,-44(fp) + 8013c58: 10c00115 stw r3,4(r2) + pevent->OSEventCnt = 0; + 8013c5c: e0bff517 ldw r2,-44(fp) + 8013c60: 1000020d sth zero,8(r2) + OSEventFreeList = pevent; /* Get next free event control block */ + 8013c64: e0bff517 ldw r2,-44(fp) + 8013c68: d0a05615 stw r2,-32424(gp) + 8013c6c: e0bffd17 ldw r2,-12(fp) + 8013c70: e0bff715 stw r2,-36(fp) + 8013c74: e0bff717 ldw r2,-36(fp) + 8013c78: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (tasks_waiting == OS_TRUE) { /* Reschedule only if task(s) were waiting */ + 8013c7c: e0bfffc3 ldbu r2,-1(fp) + 8013c80: 10800058 cmpnei r2,r2,1 + 8013c84: 1000011e bne r2,zero,8013c8c + OS_Sched(); /* Find highest priority task ready to run */ + 8013c88: 801166c0 call 801166c + } + *perr = OS_ERR_NONE; + 8013c8c: e0bff317 ldw r2,-52(fp) + 8013c90: 10000005 stb zero,0(r2) + pevent_return = (OS_EVENT *)0; /* Mutex has been deleted */ + 8013c94: e03ffe15 stw zero,-8(fp) + break; + 8013c98: 00000a06 br 8013cc4 + 8013c9c: e0bffd17 ldw r2,-12(fp) + 8013ca0: e0bff615 stw r2,-40(fp) + 8013ca4: e0bff617 ldw r2,-40(fp) + 8013ca8: 1001703a wrctl status,r2 + + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_INVALID_OPT; + 8013cac: e0bff317 ldw r2,-52(fp) + 8013cb0: 00c001c4 movi r3,7 + 8013cb4: 10c00005 stb r3,0(r2) + pevent_return = pevent; + 8013cb8: e0bff517 ldw r2,-44(fp) + 8013cbc: e0bffe15 stw r2,-8(fp) + break; + 8013cc0: 0001883a nop + } + return (pevent_return); + 8013cc4: e0bffe17 ldw r2,-8(fp) +} + 8013cc8: e037883a mov sp,fp + 8013ccc: dfc00117 ldw ra,4(sp) + 8013cd0: df000017 ldw fp,0(sp) + 8013cd4: dec00204 addi sp,sp,8 + 8013cd8: f800283a ret + +08013cdc : +* 2) You MUST NOT change the priority of the task that owns the mutex +********************************************************************************************************* +*/ + +void OSMutexPend (OS_EVENT *pevent, INT16U timeout, INT8U *perr) +{ + 8013cdc: deffef04 addi sp,sp,-68 + 8013ce0: dfc01015 stw ra,64(sp) + 8013ce4: df000f15 stw fp,60(sp) + 8013ce8: df000f04 addi fp,sp,60 + 8013cec: e13ff315 stw r4,-52(fp) + 8013cf0: 2805883a mov r2,r5 + 8013cf4: e1bff115 stw r6,-60(fp) + 8013cf8: e0bff20d sth r2,-56(fp) + BOOLEAN rdy; /* Flag indicating task was ready */ + OS_TCB *ptcb; + OS_EVENT *pevent2; + INT8U y; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8013cfc: e03ffe15 stw zero,-8(fp) + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return; + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) { /* Validate event block type */ + 8013d00: e0bff317 ldw r2,-52(fp) + 8013d04: 10800003 ldbu r2,0(r2) + 8013d08: 10803fcc andi r2,r2,255 + 8013d0c: 10800120 cmpeqi r2,r2,4 + 8013d10: 1000041e bne r2,zero,8013d24 + *perr = OS_ERR_EVENT_TYPE; + 8013d14: e0bff117 ldw r2,-60(fp) + 8013d18: 00c00044 movi r3,1 + 8013d1c: 10c00005 stb r3,0(r2) + return; + 8013d20: 00014006 br 8014224 + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 8013d24: d0a05703 ldbu r2,-32420(gp) + 8013d28: 10803fcc andi r2,r2,255 + 8013d2c: 10000426 beq r2,zero,8013d40 + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + 8013d30: e0bff117 ldw r2,-60(fp) + 8013d34: 00c00084 movi r3,2 + 8013d38: 10c00005 stb r3,0(r2) + return; + 8013d3c: 00013906 br 8014224 + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + 8013d40: d0a04b03 ldbu r2,-32468(gp) + 8013d44: 10803fcc andi r2,r2,255 + 8013d48: 10000426 beq r2,zero,8013d5c + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + 8013d4c: e0bff117 ldw r2,-60(fp) + 8013d50: 00c00344 movi r3,13 + 8013d54: 10c00005 stb r3,0(r2) + return; + 8013d58: 00013206 br 8014224 + NIOS2_READ_STATUS (context); + 8013d5c: 0005303a rdctl r2,status + 8013d60: e0bff915 stw r2,-28(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8013d64: e0fff917 ldw r3,-28(fp) + 8013d68: 00bfff84 movi r2,-2 + 8013d6c: 1884703a and r2,r3,r2 + 8013d70: 1001703a wrctl status,r2 + return context; + 8013d74: e0bff917 ldw r2,-28(fp) + } +/*$PAGE*/ + OS_ENTER_CRITICAL(); + 8013d78: e0bffe15 stw r2,-8(fp) + pip = (INT8U)(pevent->OSEventCnt >> 8); /* Get PIP from mutex */ + 8013d7c: e0bff317 ldw r2,-52(fp) + 8013d80: 1080020b ldhu r2,8(r2) + 8013d84: 10bfffcc andi r2,r2,65535 + 8013d88: 1004d23a srli r2,r2,8 + 8013d8c: e0bffdc5 stb r2,-9(fp) + /* Is Mutex available? */ + if ((INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8) == OS_MUTEX_AVAILABLE) { + 8013d90: e0bff317 ldw r2,-52(fp) + 8013d94: 1080020b ldhu r2,8(r2) + 8013d98: 10803fcc andi r2,r2,255 + 8013d9c: 10803fd8 cmpnei r2,r2,255 + 8013da0: 1000271e bne r2,zero,8013e40 + pevent->OSEventCnt &= OS_MUTEX_KEEP_UPPER_8; /* Yes, Acquire the resource */ + 8013da4: e0bff317 ldw r2,-52(fp) + 8013da8: 10c0020b ldhu r3,8(r2) + 8013dac: 00bfc004 movi r2,-256 + 8013db0: 1884703a and r2,r3,r2 + 8013db4: 1007883a mov r3,r2 + 8013db8: e0bff317 ldw r2,-52(fp) + 8013dbc: 10c0020d sth r3,8(r2) + pevent->OSEventCnt |= OSTCBCur->OSTCBPrio; /* Save priority of owning task */ + 8013dc0: e0bff317 ldw r2,-52(fp) + 8013dc4: 10c0020b ldhu r3,8(r2) + 8013dc8: d0a05817 ldw r2,-32416(gp) + 8013dcc: 10800c83 ldbu r2,50(r2) + 8013dd0: 10803fcc andi r2,r2,255 + 8013dd4: 1884b03a or r2,r3,r2 + 8013dd8: 1007883a mov r3,r2 + 8013ddc: e0bff317 ldw r2,-52(fp) + 8013de0: 10c0020d sth r3,8(r2) + pevent->OSEventPtr = (void *)OSTCBCur; /* Point to owning task's OS_TCB */ + 8013de4: d0e05817 ldw r3,-32416(gp) + 8013de8: e0bff317 ldw r2,-52(fp) + 8013dec: 10c00115 stw r3,4(r2) + if (OSTCBCur->OSTCBPrio <= pip) { /* PIP 'must' have a SMALLER prio ... */ + 8013df0: d0a05817 ldw r2,-32416(gp) + 8013df4: 10800c83 ldbu r2,50(r2) + 8013df8: e0fffdc3 ldbu r3,-9(fp) + 8013dfc: 10803fcc andi r2,r2,255 + 8013e00: 18800836 bltu r3,r2,8013e24 + 8013e04: e0bffe17 ldw r2,-8(fp) + 8013e08: e0bff815 stw r2,-32(fp) + NIOS2_WRITE_STATUS (context); + 8013e0c: e0bff817 ldw r2,-32(fp) + 8013e10: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* ... than current task! */ + *perr = OS_ERR_PIP_LOWER; + 8013e14: e0bff117 ldw r2,-60(fp) + 8013e18: 00c01e04 movi r3,120 + 8013e1c: 10c00005 stb r3,0(r2) + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + } + return; + 8013e20: 00010006 br 8014224 + 8013e24: e0bffe17 ldw r2,-8(fp) + 8013e28: e0bff715 stw r2,-36(fp) + 8013e2c: e0bff717 ldw r2,-36(fp) + 8013e30: 1001703a wrctl status,r2 + *perr = OS_ERR_NONE; + 8013e34: e0bff117 ldw r2,-60(fp) + 8013e38: 10000005 stb zero,0(r2) + return; + 8013e3c: 0000f906 br 8014224 + } + mprio = (INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8); /* No, Get priority of mutex owner */ + 8013e40: e0bff317 ldw r2,-52(fp) + 8013e44: 1080020b ldhu r2,8(r2) + 8013e48: e0bffd85 stb r2,-10(fp) + ptcb = (OS_TCB *)(pevent->OSEventPtr); /* Point to TCB of mutex owner */ + 8013e4c: e0bff317 ldw r2,-52(fp) + 8013e50: 10800117 ldw r2,4(r2) + 8013e54: e0bffc15 stw r2,-16(fp) + if (ptcb->OSTCBPrio > pip) { /* Need to promote prio of owner?*/ + 8013e58: e0bffc17 ldw r2,-16(fp) + 8013e5c: 10800c83 ldbu r2,50(r2) + 8013e60: e0fffdc3 ldbu r3,-9(fp) + 8013e64: 10803fcc andi r2,r2,255 + 8013e68: 1880b32e bgeu r3,r2,8014138 + if (mprio > OSTCBCur->OSTCBPrio) { + 8013e6c: d0a05817 ldw r2,-32416(gp) + 8013e70: 10c00c83 ldbu r3,50(r2) + 8013e74: e0bffd83 ldbu r2,-10(fp) + 8013e78: 18c03fcc andi r3,r3,255 + 8013e7c: 1880ae2e bgeu r3,r2,8014138 + y = ptcb->OSTCBY; + 8013e80: e0bffc17 ldw r2,-16(fp) + 8013e84: 10800d03 ldbu r2,52(r2) + 8013e88: e0bffbc5 stb r2,-17(fp) + if ((OSRdyTbl[y] & ptcb->OSTCBBitX) != 0) { /* See if mutex owner is ready */ + 8013e8c: e0fffbc3 ldbu r3,-17(fp) + 8013e90: d0a05544 addi r2,gp,-32427 + 8013e94: 1885883a add r2,r3,r2 + 8013e98: 10c00003 ldbu r3,0(r2) + 8013e9c: e0bffc17 ldw r2,-16(fp) + 8013ea0: 10800d43 ldbu r2,53(r2) + 8013ea4: 1884703a and r2,r3,r2 + 8013ea8: 10803fcc andi r2,r2,255 + 8013eac: 10001e26 beq r2,zero,8013f28 + OSRdyTbl[y] &= ~ptcb->OSTCBBitX; /* Yes, Remove owner from Rdy ...*/ + 8013eb0: e0fffbc3 ldbu r3,-17(fp) + 8013eb4: d0a05544 addi r2,gp,-32427 + 8013eb8: 1885883a add r2,r3,r2 + 8013ebc: 10800003 ldbu r2,0(r2) + 8013ec0: 1007883a mov r3,r2 + 8013ec4: e0bffc17 ldw r2,-16(fp) + 8013ec8: 10800d43 ldbu r2,53(r2) + 8013ecc: 0084303a nor r2,zero,r2 + 8013ed0: 1884703a and r2,r3,r2 + 8013ed4: e0fffbc3 ldbu r3,-17(fp) + 8013ed8: 1009883a mov r4,r2 + 8013edc: d0a05544 addi r2,gp,-32427 + 8013ee0: 1885883a add r2,r3,r2 + 8013ee4: 11000005 stb r4,0(r2) + if (OSRdyTbl[y] == 0) { /* ... list at current prio */ + 8013ee8: e0fffbc3 ldbu r3,-17(fp) + 8013eec: d0a05544 addi r2,gp,-32427 + 8013ef0: 1885883a add r2,r3,r2 + 8013ef4: 10800003 ldbu r2,0(r2) + 8013ef8: 10803fcc andi r2,r2,255 + 8013efc: 1000071e bne r2,zero,8013f1c + OSRdyGrp &= ~ptcb->OSTCBBitY; + 8013f00: e0bffc17 ldw r2,-16(fp) + 8013f04: 10800d83 ldbu r2,54(r2) + 8013f08: 0084303a nor r2,zero,r2 + 8013f0c: 1007883a mov r3,r2 + 8013f10: d0a05503 ldbu r2,-32428(gp) + 8013f14: 1884703a and r2,r3,r2 + 8013f18: d0a05505 stb r2,-32428(gp) + } + rdy = OS_TRUE; + 8013f1c: 00800044 movi r2,1 + 8013f20: e0bfffc5 stb r2,-1(fp) + 8013f24: 00002806 br 8013fc8 + } else { + pevent2 = ptcb->OSTCBEventPtr; + 8013f28: e0bffc17 ldw r2,-16(fp) + 8013f2c: 10800717 ldw r2,28(r2) + 8013f30: e0bffa15 stw r2,-24(fp) + if (pevent2 != (OS_EVENT *)0) { /* Remove from event wait list */ + 8013f34: e0bffa17 ldw r2,-24(fp) + 8013f38: 10002226 beq r2,zero,8013fc4 + if ((pevent2->OSEventTbl[ptcb->OSTCBY] &= ~ptcb->OSTCBBitX) == 0) { + 8013f3c: e0bffc17 ldw r2,-16(fp) + 8013f40: 10800d03 ldbu r2,52(r2) + 8013f44: 10803fcc andi r2,r2,255 + 8013f48: e0fffa17 ldw r3,-24(fp) + 8013f4c: 1885883a add r2,r3,r2 + 8013f50: 108002c3 ldbu r2,11(r2) + 8013f54: 1007883a mov r3,r2 + 8013f58: e0bffc17 ldw r2,-16(fp) + 8013f5c: 10800d43 ldbu r2,53(r2) + 8013f60: 0084303a nor r2,zero,r2 + 8013f64: 1884703a and r2,r3,r2 + 8013f68: 1007883a mov r3,r2 + 8013f6c: e0bffc17 ldw r2,-16(fp) + 8013f70: 10800d03 ldbu r2,52(r2) + 8013f74: 10803fcc andi r2,r2,255 + 8013f78: 1809883a mov r4,r3 + 8013f7c: e0fffa17 ldw r3,-24(fp) + 8013f80: 1887883a add r3,r3,r2 + 8013f84: 190002c5 stb r4,11(r3) + 8013f88: e0fffa17 ldw r3,-24(fp) + 8013f8c: 1885883a add r2,r3,r2 + 8013f90: 108002c3 ldbu r2,11(r2) + 8013f94: 10803fcc andi r2,r2,255 + 8013f98: 10000a1e bne r2,zero,8013fc4 + pevent2->OSEventGrp &= ~ptcb->OSTCBBitY; + 8013f9c: e0bffa17 ldw r2,-24(fp) + 8013fa0: 10800283 ldbu r2,10(r2) + 8013fa4: 1007883a mov r3,r2 + 8013fa8: e0bffc17 ldw r2,-16(fp) + 8013fac: 10800d83 ldbu r2,54(r2) + 8013fb0: 0084303a nor r2,zero,r2 + 8013fb4: 1884703a and r2,r3,r2 + 8013fb8: 1007883a mov r3,r2 + 8013fbc: e0bffa17 ldw r2,-24(fp) + 8013fc0: 10c00285 stb r3,10(r2) + } + } + rdy = OS_FALSE; /* No */ + 8013fc4: e03fffc5 stb zero,-1(fp) + } + ptcb->OSTCBPrio = pip; /* Change owner task prio to PIP */ + 8013fc8: e0bffc17 ldw r2,-16(fp) + 8013fcc: e0fffdc3 ldbu r3,-9(fp) + 8013fd0: 10c00c85 stb r3,50(r2) +#if OS_LOWEST_PRIO <= 63 + ptcb->OSTCBY = (INT8U)( ptcb->OSTCBPrio >> 3); + 8013fd4: e0bffc17 ldw r2,-16(fp) + 8013fd8: 10800c83 ldbu r2,50(r2) + 8013fdc: 10803fcc andi r2,r2,255 + 8013fe0: 1004d0fa srli r2,r2,3 + 8013fe4: 1007883a mov r3,r2 + 8013fe8: e0bffc17 ldw r2,-16(fp) + 8013fec: 10c00d05 stb r3,52(r2) + ptcb->OSTCBX = (INT8U)( ptcb->OSTCBPrio & 0x07); + 8013ff0: e0bffc17 ldw r2,-16(fp) + 8013ff4: 10800c83 ldbu r2,50(r2) + 8013ff8: 108001cc andi r2,r2,7 + 8013ffc: 1007883a mov r3,r2 + 8014000: e0bffc17 ldw r2,-16(fp) + 8014004: 10c00cc5 stb r3,51(r2) + ptcb->OSTCBBitY = (INT8U)(1 << ptcb->OSTCBY); + 8014008: e0bffc17 ldw r2,-16(fp) + 801400c: 10800d03 ldbu r2,52(r2) + 8014010: 10803fcc andi r2,r2,255 + 8014014: 00c00044 movi r3,1 + 8014018: 1884983a sll r2,r3,r2 + 801401c: 1007883a mov r3,r2 + 8014020: e0bffc17 ldw r2,-16(fp) + 8014024: 10c00d85 stb r3,54(r2) + ptcb->OSTCBBitX = (INT8U)(1 << ptcb->OSTCBX); + 8014028: e0bffc17 ldw r2,-16(fp) + 801402c: 10800cc3 ldbu r2,51(r2) + 8014030: 10803fcc andi r2,r2,255 + 8014034: 00c00044 movi r3,1 + 8014038: 1884983a sll r2,r3,r2 + 801403c: 1007883a mov r3,r2 + 8014040: e0bffc17 ldw r2,-16(fp) + 8014044: 10c00d45 stb r3,53(r2) + ptcb->OSTCBY = (INT8U)((ptcb->OSTCBPrio >> 4) & 0xFF); + ptcb->OSTCBX = (INT8U)( ptcb->OSTCBPrio & 0x0F); + ptcb->OSTCBBitY = (INT16U)(1 << ptcb->OSTCBY); + ptcb->OSTCBBitX = (INT16U)(1 << ptcb->OSTCBX); +#endif + if (rdy == OS_TRUE) { /* If task was ready at owner's priority ...*/ + 8014048: e0bfffc3 ldbu r2,-1(fp) + 801404c: 10800058 cmpnei r2,r2,1 + 8014050: 1000161e bne r2,zero,80140ac + OSRdyGrp |= ptcb->OSTCBBitY; /* ... make it ready at new priority. */ + 8014054: e0bffc17 ldw r2,-16(fp) + 8014058: 10c00d83 ldbu r3,54(r2) + 801405c: d0a05503 ldbu r2,-32428(gp) + 8014060: 1884b03a or r2,r3,r2 + 8014064: d0a05505 stb r2,-32428(gp) + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + 8014068: e0bffc17 ldw r2,-16(fp) + 801406c: 10800d03 ldbu r2,52(r2) + 8014070: 10c03fcc andi r3,r2,255 + 8014074: d0a05544 addi r2,gp,-32427 + 8014078: 1885883a add r2,r3,r2 + 801407c: 11000003 ldbu r4,0(r2) + 8014080: e0bffc17 ldw r2,-16(fp) + 8014084: 10800d43 ldbu r2,53(r2) + 8014088: e0fffc17 ldw r3,-16(fp) + 801408c: 18c00d03 ldbu r3,52(r3) + 8014090: 18c03fcc andi r3,r3,255 + 8014094: 2084b03a or r2,r4,r2 + 8014098: 1009883a mov r4,r2 + 801409c: d0a05544 addi r2,gp,-32427 + 80140a0: 1885883a add r2,r3,r2 + 80140a4: 11000005 stb r4,0(r2) + 80140a8: 00001d06 br 8014120 + } else { + pevent2 = ptcb->OSTCBEventPtr; + 80140ac: e0bffc17 ldw r2,-16(fp) + 80140b0: 10800717 ldw r2,28(r2) + 80140b4: e0bffa15 stw r2,-24(fp) + if (pevent2 != (OS_EVENT *)0) { /* Add to event wait list */ + 80140b8: e0bffa17 ldw r2,-24(fp) + 80140bc: 10001826 beq r2,zero,8014120 + pevent2->OSEventGrp |= ptcb->OSTCBBitY; + 80140c0: e0bffa17 ldw r2,-24(fp) + 80140c4: 10c00283 ldbu r3,10(r2) + 80140c8: e0bffc17 ldw r2,-16(fp) + 80140cc: 10800d83 ldbu r2,54(r2) + 80140d0: 1884b03a or r2,r3,r2 + 80140d4: 1007883a mov r3,r2 + 80140d8: e0bffa17 ldw r2,-24(fp) + 80140dc: 10c00285 stb r3,10(r2) + pevent2->OSEventTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + 80140e0: e0bffc17 ldw r2,-16(fp) + 80140e4: 10800d03 ldbu r2,52(r2) + 80140e8: 10803fcc andi r2,r2,255 + 80140ec: e0fffa17 ldw r3,-24(fp) + 80140f0: 1885883a add r2,r3,r2 + 80140f4: 110002c3 ldbu r4,11(r2) + 80140f8: e0bffc17 ldw r2,-16(fp) + 80140fc: 10c00d43 ldbu r3,53(r2) + 8014100: e0bffc17 ldw r2,-16(fp) + 8014104: 10800d03 ldbu r2,52(r2) + 8014108: 10803fcc andi r2,r2,255 + 801410c: 20c6b03a or r3,r4,r3 + 8014110: 1809883a mov r4,r3 + 8014114: e0fffa17 ldw r3,-24(fp) + 8014118: 1885883a add r2,r3,r2 + 801411c: 110002c5 stb r4,11(r2) + } + } + OSTCBPrioTbl[pip] = ptcb; + 8014120: e0bffdc3 ldbu r2,-9(fp) + 8014124: 100890ba slli r4,r2,2 + 8014128: e0fffc17 ldw r3,-16(fp) + 801412c: 008201b4 movhi r2,2054 + 8014130: 2085883a add r2,r4,r2 + 8014134: 10f55d15 stw r3,-10892(r2) + } + } + OSTCBCur->OSTCBStat |= OS_STAT_MUTEX; /* Mutex not available, pend current task */ + 8014138: d0a05817 ldw r2,-32416(gp) + 801413c: 10c00c03 ldbu r3,48(r2) + 8014140: d0a05817 ldw r2,-32416(gp) + 8014144: 18c00414 ori r3,r3,16 + 8014148: 10c00c05 stb r3,48(r2) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + 801414c: d0a05817 ldw r2,-32416(gp) + 8014150: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBDly = timeout; /* Store timeout in current task's TCB */ + 8014154: d0a05817 ldw r2,-32416(gp) + 8014158: e0fff20b ldhu r3,-56(fp) + 801415c: 10c00b8d sth r3,46(r2) + OS_EventTaskWait(pevent); /* Suspend task until event or timeout occurs */ + 8014160: e13ff317 ldw r4,-52(fp) + 8014164: 8010e600 call 8010e60 + 8014168: e0bffe17 ldw r2,-8(fp) + 801416c: e0bff515 stw r2,-44(fp) + 8014170: e0bff517 ldw r2,-44(fp) + 8014174: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next highest priority task ready */ + 8014178: 801166c0 call 801166c + NIOS2_READ_STATUS (context); + 801417c: 0005303a rdctl r2,status + 8014180: e0bff615 stw r2,-40(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8014184: e0fff617 ldw r3,-40(fp) + 8014188: 00bfff84 movi r2,-2 + 801418c: 1884703a and r2,r3,r2 + 8014190: 1001703a wrctl status,r2 + return context; + 8014194: e0bff617 ldw r2,-40(fp) + OS_ENTER_CRITICAL(); + 8014198: e0bffe15 stw r2,-8(fp) + switch (OSTCBCur->OSTCBStatPend) { /* See if we timed-out or aborted */ + 801419c: d0a05817 ldw r2,-32416(gp) + 80141a0: 10800c43 ldbu r2,49(r2) + 80141a4: 10803fcc andi r2,r2,255 + 80141a8: 10000326 beq r2,zero,80141b8 + 80141ac: 108000a0 cmpeqi r2,r2,2 + 80141b0: 1000041e bne r2,zero,80141c4 + 80141b4: 00000706 br 80141d4 + case OS_STAT_PEND_OK: + *perr = OS_ERR_NONE; + 80141b8: e0bff117 ldw r2,-60(fp) + 80141bc: 10000005 stb zero,0(r2) + break; + 80141c0: 00000c06 br 80141f4 + + case OS_STAT_PEND_ABORT: + *perr = OS_ERR_PEND_ABORT; /* Indicate that we aborted getting mutex */ + 80141c4: e0bff117 ldw r2,-60(fp) + 80141c8: 00c00384 movi r3,14 + 80141cc: 10c00005 stb r3,0(r2) + break; + 80141d0: 00000806 br 80141f4 + + case OS_STAT_PEND_TO: + default: + OS_EventTaskRemove(OSTCBCur, pevent); + 80141d4: d0a05817 ldw r2,-32416(gp) + 80141d8: e17ff317 ldw r5,-52(fp) + 80141dc: 1009883a mov r4,r2 + 80141e0: 80110b00 call 80110b0 + *perr = OS_ERR_TIMEOUT; /* Indicate that we didn't get mutex within TO */ + 80141e4: e0bff117 ldw r2,-60(fp) + 80141e8: 00c00284 movi r3,10 + 80141ec: 10c00005 stb r3,0(r2) + break; + 80141f0: 0001883a nop + } + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Set task status to ready */ + 80141f4: d0a05817 ldw r2,-32416(gp) + 80141f8: 10000c05 stb zero,48(r2) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + 80141fc: d0a05817 ldw r2,-32416(gp) + 8014200: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; /* Clear event pointers */ + 8014204: d0a05817 ldw r2,-32416(gp) + 8014208: 10000715 stw zero,28(r2) +#if (OS_EVENT_MULTI_EN > 0) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0; + 801420c: d0a05817 ldw r2,-32416(gp) + 8014210: 10000815 stw zero,32(r2) + 8014214: e0bffe17 ldw r2,-8(fp) + 8014218: e0bff415 stw r2,-48(fp) + NIOS2_WRITE_STATUS (context); + 801421c: e0bff417 ldw r2,-48(fp) + 8014220: 1001703a wrctl status,r2 +#endif + OS_EXIT_CRITICAL(); +} + 8014224: e037883a mov sp,fp + 8014228: dfc00117 ldw ra,4(sp) + 801422c: df000017 ldw fp,0(sp) + 8014230: dec00204 addi sp,sp,8 + 8014234: f800283a ret + +08014238 : +* what tasks will be using the Mutex. +********************************************************************************************************* +*/ + +INT8U OSMutexPost (OS_EVENT *pevent) +{ + 8014238: defff604 addi sp,sp,-40 + 801423c: dfc00915 stw ra,36(sp) + 8014240: df000815 stw fp,32(sp) + 8014244: df000804 addi fp,sp,32 + 8014248: e13ff815 stw r4,-32(fp) + INT8U pip; /* Priority inheritance priority */ + INT8U prio; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 801424c: e03fff15 stw zero,-4(fp) +#endif + + + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 8014250: d0a05703 ldbu r2,-32420(gp) + 8014254: 10803fcc andi r2,r2,255 + 8014258: 10000226 beq r2,zero,8014264 + return (OS_ERR_POST_ISR); /* ... can't POST mutex from an ISR */ + 801425c: 00800144 movi r2,5 + 8014260: 00006e06 br 801441c +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) { /* Validate event block type */ + 8014264: e0bff817 ldw r2,-32(fp) + 8014268: 10800003 ldbu r2,0(r2) + 801426c: 10803fcc andi r2,r2,255 + 8014270: 10800120 cmpeqi r2,r2,4 + 8014274: 1000021e bne r2,zero,8014280 + return (OS_ERR_EVENT_TYPE); + 8014278: 00800044 movi r2,1 + 801427c: 00006706 br 801441c + NIOS2_READ_STATUS (context); + 8014280: 0005303a rdctl r2,status + 8014284: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8014288: e0fffd17 ldw r3,-12(fp) + 801428c: 00bfff84 movi r2,-2 + 8014290: 1884703a and r2,r3,r2 + 8014294: 1001703a wrctl status,r2 + return context; + 8014298: e0bffd17 ldw r2,-12(fp) + } + OS_ENTER_CRITICAL(); + 801429c: e0bfff15 stw r2,-4(fp) + pip = (INT8U)(pevent->OSEventCnt >> 8); /* Get priority inheritance priority of mutex */ + 80142a0: e0bff817 ldw r2,-32(fp) + 80142a4: 1080020b ldhu r2,8(r2) + 80142a8: 10bfffcc andi r2,r2,65535 + 80142ac: 1004d23a srli r2,r2,8 + 80142b0: e0bffec5 stb r2,-5(fp) + prio = (INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8); /* Get owner's original priority */ + 80142b4: e0bff817 ldw r2,-32(fp) + 80142b8: 1080020b ldhu r2,8(r2) + 80142bc: e0bffe85 stb r2,-6(fp) + if (OSTCBCur != (OS_TCB *)pevent->OSEventPtr) { /* See if posting task owns the MUTEX */ + 80142c0: e0bff817 ldw r2,-32(fp) + 80142c4: 10c00117 ldw r3,4(r2) + 80142c8: d0a05817 ldw r2,-32416(gp) + 80142cc: 18800626 beq r3,r2,80142e8 + 80142d0: e0bfff17 ldw r2,-4(fp) + 80142d4: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 80142d8: e0bffc17 ldw r2,-16(fp) + 80142dc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NOT_MUTEX_OWNER); + 80142e0: 00801904 movi r2,100 + 80142e4: 00004d06 br 801441c + } + if (OSTCBCur->OSTCBPrio == pip) { /* Did we have to raise current task's priority? */ + 80142e8: d0a05817 ldw r2,-32416(gp) + 80142ec: 10800c83 ldbu r2,50(r2) + 80142f0: e0fffec3 ldbu r3,-5(fp) + 80142f4: 10803fcc andi r2,r2,255 + 80142f8: 1880051e bne r3,r2,8014310 + OSMutex_RdyAtPrio(OSTCBCur, prio); /* Restore the task's original priority */ + 80142fc: d0a05817 ldw r2,-32416(gp) + 8014300: e0fffe83 ldbu r3,-6(fp) + 8014304: 180b883a mov r5,r3 + 8014308: 1009883a mov r4,r2 + 801430c: 801457c0 call 801457c + } + OSTCBPrioTbl[pip] = OS_TCB_RESERVED; /* Reserve table entry */ + 8014310: e0bffec3 ldbu r2,-5(fp) + 8014314: 100890ba slli r4,r2,2 + 8014318: 00c00044 movi r3,1 + 801431c: 008201b4 movhi r2,2054 + 8014320: 2085883a add r2,r4,r2 + 8014324: 10f55d15 stw r3,-10892(r2) + if (pevent->OSEventGrp != 0) { /* Any task waiting for the mutex? */ + 8014328: e0bff817 ldw r2,-32(fp) + 801432c: 10800283 ldbu r2,10(r2) + 8014330: 10803fcc andi r2,r2,255 + 8014334: 10002c26 beq r2,zero,80143e8 + /* Yes, Make HPT waiting for mutex ready */ + prio = OS_EventTaskRdy(pevent, (void *)0, OS_STAT_MUTEX, OS_STAT_PEND_OK); + 8014338: 000f883a mov r7,zero + 801433c: 01800404 movi r6,16 + 8014340: 000b883a mov r5,zero + 8014344: e13ff817 ldw r4,-32(fp) + 8014348: 8010cd80 call 8010cd8 + 801434c: e0bffe85 stb r2,-6(fp) + pevent->OSEventCnt &= OS_MUTEX_KEEP_UPPER_8; /* Save priority of mutex's new owner */ + 8014350: e0bff817 ldw r2,-32(fp) + 8014354: 10c0020b ldhu r3,8(r2) + 8014358: 00bfc004 movi r2,-256 + 801435c: 1884703a and r2,r3,r2 + 8014360: 1007883a mov r3,r2 + 8014364: e0bff817 ldw r2,-32(fp) + 8014368: 10c0020d sth r3,8(r2) + pevent->OSEventCnt |= prio; + 801436c: e0bff817 ldw r2,-32(fp) + 8014370: 10c0020b ldhu r3,8(r2) + 8014374: e0bffe83 ldbu r2,-6(fp) + 8014378: 1884b03a or r2,r3,r2 + 801437c: 1007883a mov r3,r2 + 8014380: e0bff817 ldw r2,-32(fp) + 8014384: 10c0020d sth r3,8(r2) + pevent->OSEventPtr = OSTCBPrioTbl[prio]; /* Link to new mutex owner's OS_TCB */ + 8014388: e0bffe83 ldbu r2,-6(fp) + 801438c: 100690ba slli r3,r2,2 + 8014390: 008201b4 movhi r2,2054 + 8014394: 1885883a add r2,r3,r2 + 8014398: 10f55d17 ldw r3,-10892(r2) + 801439c: e0bff817 ldw r2,-32(fp) + 80143a0: 10c00115 stw r3,4(r2) + if (prio <= pip) { /* PIP 'must' have a SMALLER prio ... */ + 80143a4: e0bffe83 ldbu r2,-6(fp) + 80143a8: e0fffec3 ldbu r3,-5(fp) + 80143ac: 18800736 bltu r3,r2,80143cc + 80143b0: e0bfff17 ldw r2,-4(fp) + 80143b4: e0bffb15 stw r2,-20(fp) + 80143b8: e0bffb17 ldw r2,-20(fp) + 80143bc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* ... than current task! */ + OS_Sched(); /* Find highest priority task ready to run */ + 80143c0: 801166c0 call 801166c + return (OS_ERR_PIP_LOWER); + 80143c4: 00801e04 movi r2,120 + 80143c8: 00001406 br 801441c + 80143cc: e0bfff17 ldw r2,-4(fp) + 80143d0: e0bffa15 stw r2,-24(fp) + 80143d4: e0bffa17 ldw r2,-24(fp) + 80143d8: 1001703a wrctl status,r2 + } else { + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find highest priority task ready to run */ + 80143dc: 801166c0 call 801166c + return (OS_ERR_NONE); + 80143e0: 0005883a mov r2,zero + 80143e4: 00000d06 br 801441c + } + } + pevent->OSEventCnt |= OS_MUTEX_AVAILABLE; /* No, Mutex is now available */ + 80143e8: e0bff817 ldw r2,-32(fp) + 80143ec: 1080020b ldhu r2,8(r2) + 80143f0: 10803fd4 ori r2,r2,255 + 80143f4: 1007883a mov r3,r2 + 80143f8: e0bff817 ldw r2,-32(fp) + 80143fc: 10c0020d sth r3,8(r2) + pevent->OSEventPtr = (void *)0; + 8014400: e0bff817 ldw r2,-32(fp) + 8014404: 10000115 stw zero,4(r2) + 8014408: e0bfff17 ldw r2,-4(fp) + 801440c: e0bff915 stw r2,-28(fp) + 8014410: e0bff917 ldw r2,-28(fp) + 8014414: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 8014418: 0005883a mov r2,zero +} + 801441c: e037883a mov sp,fp + 8014420: dfc00117 ldw ra,4(sp) + 8014424: df000017 ldw fp,0(sp) + 8014428: dec00204 addi sp,sp,8 + 801442c: f800283a ret + +08014430 : +********************************************************************************************************* +*/ + +#if OS_MUTEX_QUERY_EN > 0 +INT8U OSMutexQuery (OS_EVENT *pevent, OS_MUTEX_DATA *p_mutex_data) +{ + 8014430: defff704 addi sp,sp,-36 + 8014434: df000815 stw fp,32(sp) + 8014438: df000804 addi fp,sp,32 + 801443c: e13ff915 stw r4,-28(fp) + 8014440: e17ff815 stw r5,-32(fp) +#else + INT16U *psrc; + INT16U *pdest; +#endif +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8014444: e03ffc15 stw zero,-16(fp) +#endif + + + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 8014448: d0a05703 ldbu r2,-32420(gp) + 801444c: 10803fcc andi r2,r2,255 + 8014450: 10000226 beq r2,zero,801445c + return (OS_ERR_QUERY_ISR); /* ... can't QUERY mutex from an ISR */ + 8014454: 00800184 movi r2,6 + 8014458: 00004406 br 801456c + } + if (p_mutex_data == (OS_MUTEX_DATA *)0) { /* Validate 'p_mutex_data' */ + return (OS_ERR_PDATA_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) { /* Validate event block type */ + 801445c: e0bff917 ldw r2,-28(fp) + 8014460: 10800003 ldbu r2,0(r2) + 8014464: 10803fcc andi r2,r2,255 + 8014468: 10800120 cmpeqi r2,r2,4 + 801446c: 1000021e bne r2,zero,8014478 + return (OS_ERR_EVENT_TYPE); + 8014470: 00800044 movi r2,1 + 8014474: 00003d06 br 801456c + NIOS2_READ_STATUS (context); + 8014478: 0005303a rdctl r2,status + 801447c: e0bffb15 stw r2,-20(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8014480: e0fffb17 ldw r3,-20(fp) + 8014484: 00bfff84 movi r2,-2 + 8014488: 1884703a and r2,r3,r2 + 801448c: 1001703a wrctl status,r2 + return context; + 8014490: e0bffb17 ldw r2,-20(fp) + } + OS_ENTER_CRITICAL(); + 8014494: e0bffc15 stw r2,-16(fp) + p_mutex_data->OSMutexPIP = (INT8U)(pevent->OSEventCnt >> 8); + 8014498: e0bff917 ldw r2,-28(fp) + 801449c: 1080020b ldhu r2,8(r2) + 80144a0: 10bfffcc andi r2,r2,65535 + 80144a4: 1004d23a srli r2,r2,8 + 80144a8: 1007883a mov r3,r2 + 80144ac: e0bff817 ldw r2,-32(fp) + 80144b0: 10c00185 stb r3,6(r2) + p_mutex_data->OSOwnerPrio = (INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8); + 80144b4: e0bff917 ldw r2,-28(fp) + 80144b8: 1080020b ldhu r2,8(r2) + 80144bc: 1007883a mov r3,r2 + 80144c0: e0bff817 ldw r2,-32(fp) + 80144c4: 10c00145 stb r3,5(r2) + if (p_mutex_data->OSOwnerPrio == 0xFF) { + 80144c8: e0bff817 ldw r2,-32(fp) + 80144cc: 10800143 ldbu r2,5(r2) + 80144d0: 10803fcc andi r2,r2,255 + 80144d4: 10803fd8 cmpnei r2,r2,255 + 80144d8: 1000041e bne r2,zero,80144ec + p_mutex_data->OSValue = OS_TRUE; + 80144dc: e0bff817 ldw r2,-32(fp) + 80144e0: 00c00044 movi r3,1 + 80144e4: 10c00105 stb r3,4(r2) + 80144e8: 00000206 br 80144f4 + } else { + p_mutex_data->OSValue = OS_FALSE; + 80144ec: e0bff817 ldw r2,-32(fp) + 80144f0: 10000105 stb zero,4(r2) + } + p_mutex_data->OSEventGrp = pevent->OSEventGrp; /* Copy wait list */ + 80144f4: e0bff917 ldw r2,-28(fp) + 80144f8: 10c00283 ldbu r3,10(r2) + 80144fc: e0bff817 ldw r2,-32(fp) + 8014500: 10c000c5 stb r3,3(r2) + psrc = &pevent->OSEventTbl[0]; + 8014504: e0bff917 ldw r2,-28(fp) + 8014508: 108002c4 addi r2,r2,11 + 801450c: e0bffe15 stw r2,-8(fp) + pdest = &p_mutex_data->OSEventTbl[0]; + 8014510: e0bff817 ldw r2,-32(fp) + 8014514: e0bffd15 stw r2,-12(fp) + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 8014518: e03fffc5 stb zero,-1(fp) + 801451c: 00000b06 br 801454c + *pdest++ = *psrc++; + 8014520: e0fffe17 ldw r3,-8(fp) + 8014524: 18800044 addi r2,r3,1 + 8014528: e0bffe15 stw r2,-8(fp) + 801452c: e0bffd17 ldw r2,-12(fp) + 8014530: 11000044 addi r4,r2,1 + 8014534: e13ffd15 stw r4,-12(fp) + 8014538: 18c00003 ldbu r3,0(r3) + 801453c: 10c00005 stb r3,0(r2) + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 8014540: e0bfffc3 ldbu r2,-1(fp) + 8014544: 10800044 addi r2,r2,1 + 8014548: e0bfffc5 stb r2,-1(fp) + 801454c: e0bfffc3 ldbu r2,-1(fp) + 8014550: 108000f0 cmpltui r2,r2,3 + 8014554: 103ff21e bne r2,zero,8014520 + 8014558: e0bffc17 ldw r2,-16(fp) + 801455c: e0bffa15 stw r2,-24(fp) + NIOS2_WRITE_STATUS (context); + 8014560: e0bffa17 ldw r2,-24(fp) + 8014564: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 8014568: 0005883a mov r2,zero +} + 801456c: e037883a mov sp,fp + 8014570: df000017 ldw fp,0(sp) + 8014574: dec00104 addi sp,sp,4 + 8014578: f800283a ret + +0801457c : +* Returns : none +********************************************************************************************************* +*/ + +static void OSMutex_RdyAtPrio (OS_TCB *ptcb, INT8U prio) +{ + 801457c: defffc04 addi sp,sp,-16 + 8014580: df000315 stw fp,12(sp) + 8014584: df000304 addi fp,sp,12 + 8014588: e13ffe15 stw r4,-8(fp) + 801458c: 2805883a mov r2,r5 + 8014590: e0bffd05 stb r2,-12(fp) + INT8U y; + + + y = ptcb->OSTCBY; /* Remove owner from ready list at 'pip' */ + 8014594: e0bffe17 ldw r2,-8(fp) + 8014598: 10800d03 ldbu r2,52(r2) + 801459c: e0bfffc5 stb r2,-1(fp) + OSRdyTbl[y] &= ~ptcb->OSTCBBitX; + 80145a0: e0ffffc3 ldbu r3,-1(fp) + 80145a4: d0a05544 addi r2,gp,-32427 + 80145a8: 1885883a add r2,r3,r2 + 80145ac: 10800003 ldbu r2,0(r2) + 80145b0: 1007883a mov r3,r2 + 80145b4: e0bffe17 ldw r2,-8(fp) + 80145b8: 10800d43 ldbu r2,53(r2) + 80145bc: 0084303a nor r2,zero,r2 + 80145c0: 1884703a and r2,r3,r2 + 80145c4: e0ffffc3 ldbu r3,-1(fp) + 80145c8: 1009883a mov r4,r2 + 80145cc: d0a05544 addi r2,gp,-32427 + 80145d0: 1885883a add r2,r3,r2 + 80145d4: 11000005 stb r4,0(r2) + if (OSRdyTbl[y] == 0) { + 80145d8: e0ffffc3 ldbu r3,-1(fp) + 80145dc: d0a05544 addi r2,gp,-32427 + 80145e0: 1885883a add r2,r3,r2 + 80145e4: 10800003 ldbu r2,0(r2) + 80145e8: 10803fcc andi r2,r2,255 + 80145ec: 1000071e bne r2,zero,801460c + OSRdyGrp &= ~ptcb->OSTCBBitY; + 80145f0: e0bffe17 ldw r2,-8(fp) + 80145f4: 10800d83 ldbu r2,54(r2) + 80145f8: 0084303a nor r2,zero,r2 + 80145fc: 1007883a mov r3,r2 + 8014600: d0a05503 ldbu r2,-32428(gp) + 8014604: 1884703a and r2,r3,r2 + 8014608: d0a05505 stb r2,-32428(gp) + } + ptcb->OSTCBPrio = prio; + 801460c: e0bffe17 ldw r2,-8(fp) + 8014610: e0fffd03 ldbu r3,-12(fp) + 8014614: 10c00c85 stb r3,50(r2) +#if OS_LOWEST_PRIO <= 63 + ptcb->OSTCBY = (INT8U)((prio >> (INT8U)3) & (INT8U)0x07); + 8014618: e0bffd03 ldbu r2,-12(fp) + 801461c: 1004d0fa srli r2,r2,3 + 8014620: 108001cc andi r2,r2,7 + 8014624: 1007883a mov r3,r2 + 8014628: e0bffe17 ldw r2,-8(fp) + 801462c: 10c00d05 stb r3,52(r2) + ptcb->OSTCBX = (INT8U) (prio & (INT8U)0x07); + 8014630: e0bffd03 ldbu r2,-12(fp) + 8014634: 108001cc andi r2,r2,7 + 8014638: 1007883a mov r3,r2 + 801463c: e0bffe17 ldw r2,-8(fp) + 8014640: 10c00cc5 stb r3,51(r2) + ptcb->OSTCBBitY = (INT8U)(1 << ptcb->OSTCBY); + 8014644: e0bffe17 ldw r2,-8(fp) + 8014648: 10800d03 ldbu r2,52(r2) + 801464c: 10803fcc andi r2,r2,255 + 8014650: 00c00044 movi r3,1 + 8014654: 1884983a sll r2,r3,r2 + 8014658: 1007883a mov r3,r2 + 801465c: e0bffe17 ldw r2,-8(fp) + 8014660: 10c00d85 stb r3,54(r2) + ptcb->OSTCBBitX = (INT8U)(1 << ptcb->OSTCBX); + 8014664: e0bffe17 ldw r2,-8(fp) + 8014668: 10800cc3 ldbu r2,51(r2) + 801466c: 10803fcc andi r2,r2,255 + 8014670: 00c00044 movi r3,1 + 8014674: 1884983a sll r2,r3,r2 + 8014678: 1007883a mov r3,r2 + 801467c: e0bffe17 ldw r2,-8(fp) + 8014680: 10c00d45 stb r3,53(r2) + ptcb->OSTCBY = (INT8U)((prio >> (INT8U)4) & (INT8U)0x0F); + ptcb->OSTCBX = (INT8U) (prio & (INT8U)0x0F); + ptcb->OSTCBBitY = (INT16U)(1 << ptcb->OSTCBY); + ptcb->OSTCBBitX = (INT16U)(1 << ptcb->OSTCBX); +#endif + OSRdyGrp |= ptcb->OSTCBBitY; /* Make task ready at original priority */ + 8014684: e0bffe17 ldw r2,-8(fp) + 8014688: 10c00d83 ldbu r3,54(r2) + 801468c: d0a05503 ldbu r2,-32428(gp) + 8014690: 1884b03a or r2,r3,r2 + 8014694: d0a05505 stb r2,-32428(gp) + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + 8014698: e0bffe17 ldw r2,-8(fp) + 801469c: 10800d03 ldbu r2,52(r2) + 80146a0: 10c03fcc andi r3,r2,255 + 80146a4: d0a05544 addi r2,gp,-32427 + 80146a8: 1885883a add r2,r3,r2 + 80146ac: 11000003 ldbu r4,0(r2) + 80146b0: e0bffe17 ldw r2,-8(fp) + 80146b4: 10800d43 ldbu r2,53(r2) + 80146b8: e0fffe17 ldw r3,-8(fp) + 80146bc: 18c00d03 ldbu r3,52(r3) + 80146c0: 18c03fcc andi r3,r3,255 + 80146c4: 2084b03a or r2,r4,r2 + 80146c8: 1009883a mov r4,r2 + 80146cc: d0a05544 addi r2,gp,-32427 + 80146d0: 1885883a add r2,r3,r2 + 80146d4: 11000005 stb r4,0(r2) + OSTCBPrioTbl[prio] = ptcb; + 80146d8: e0bffd03 ldbu r2,-12(fp) + 80146dc: 100890ba slli r4,r2,2 + 80146e0: e0fffe17 ldw r3,-8(fp) + 80146e4: 008201b4 movhi r2,2054 + 80146e8: 2085883a add r2,r4,r2 + 80146ec: 10f55d15 stw r3,-10892(r2) +} + 80146f0: 0001883a nop + 80146f4: e037883a mov sp,fp + 80146f8: df000017 ldw fp,0(sp) + 80146fc: dec00104 addi sp,sp,4 + 8014700: f800283a ret + +08014704 : +********************************************************************************************************* +*/ + +#if OS_Q_ACCEPT_EN > 0 +void *OSQAccept (OS_EVENT *pevent, INT8U *perr) +{ + 8014704: defff804 addi sp,sp,-32 + 8014708: df000715 stw fp,28(sp) + 801470c: df000704 addi fp,sp,28 + 8014710: e13ffa15 stw r4,-24(fp) + 8014714: e17ff915 stw r5,-28(fp) + void *pmsg; + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8014718: e03ffe15 stw zero,-8(fp) + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return ((void *)0); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) {/* Validate event block type */ + 801471c: e0bffa17 ldw r2,-24(fp) + 8014720: 10800003 ldbu r2,0(r2) + 8014724: 10803fcc andi r2,r2,255 + 8014728: 108000a0 cmpeqi r2,r2,2 + 801472c: 1000051e bne r2,zero,8014744 + *perr = OS_ERR_EVENT_TYPE; + 8014730: e0bff917 ldw r2,-28(fp) + 8014734: 00c00044 movi r3,1 + 8014738: 10c00005 stb r3,0(r2) + return ((void *)0); + 801473c: 0005883a mov r2,zero + 8014740: 00003106 br 8014808 + NIOS2_READ_STATUS (context); + 8014744: 0005303a rdctl r2,status + 8014748: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 801474c: e0fffc17 ldw r3,-16(fp) + 8014750: 00bfff84 movi r2,-2 + 8014754: 1884703a and r2,r3,r2 + 8014758: 1001703a wrctl status,r2 + return context; + 801475c: e0bffc17 ldw r2,-16(fp) + } + OS_ENTER_CRITICAL(); + 8014760: e0bffe15 stw r2,-8(fp) + pq = (OS_Q *)pevent->OSEventPtr; /* Point at queue control block */ + 8014764: e0bffa17 ldw r2,-24(fp) + 8014768: 10800117 ldw r2,4(r2) + 801476c: e0bffd15 stw r2,-12(fp) + if (pq->OSQEntries > 0) { /* See if any messages in the queue */ + 8014770: e0bffd17 ldw r2,-12(fp) + 8014774: 1080058b ldhu r2,22(r2) + 8014778: 10bfffcc andi r2,r2,65535 + 801477c: 10001926 beq r2,zero,80147e4 + pmsg = *pq->OSQOut++; /* Yes, extract oldest message from the queue */ + 8014780: e0bffd17 ldw r2,-12(fp) + 8014784: 10800417 ldw r2,16(r2) + 8014788: 11000104 addi r4,r2,4 + 801478c: e0fffd17 ldw r3,-12(fp) + 8014790: 19000415 stw r4,16(r3) + 8014794: 10800017 ldw r2,0(r2) + 8014798: e0bfff15 stw r2,-4(fp) + pq->OSQEntries--; /* Update the number of entries in the queue */ + 801479c: e0bffd17 ldw r2,-12(fp) + 80147a0: 1080058b ldhu r2,22(r2) + 80147a4: 10bfffc4 addi r2,r2,-1 + 80147a8: 1007883a mov r3,r2 + 80147ac: e0bffd17 ldw r2,-12(fp) + 80147b0: 10c0058d sth r3,22(r2) + if (pq->OSQOut == pq->OSQEnd) { /* Wrap OUT pointer if we are at the end of the queue */ + 80147b4: e0bffd17 ldw r2,-12(fp) + 80147b8: 10c00417 ldw r3,16(r2) + 80147bc: e0bffd17 ldw r2,-12(fp) + 80147c0: 10800217 ldw r2,8(r2) + 80147c4: 1880041e bne r3,r2,80147d8 + pq->OSQOut = pq->OSQStart; + 80147c8: e0bffd17 ldw r2,-12(fp) + 80147cc: 10c00117 ldw r3,4(r2) + 80147d0: e0bffd17 ldw r2,-12(fp) + 80147d4: 10c00415 stw r3,16(r2) + } + *perr = OS_ERR_NONE; + 80147d8: e0bff917 ldw r2,-28(fp) + 80147dc: 10000005 stb zero,0(r2) + 80147e0: 00000406 br 80147f4 + } else { + *perr = OS_ERR_Q_EMPTY; + 80147e4: e0bff917 ldw r2,-28(fp) + 80147e8: 00c007c4 movi r3,31 + 80147ec: 10c00005 stb r3,0(r2) + pmsg = (void *)0; /* Queue is empty */ + 80147f0: e03fff15 stw zero,-4(fp) + 80147f4: e0bffe17 ldw r2,-8(fp) + 80147f8: e0bffb15 stw r2,-20(fp) + NIOS2_WRITE_STATUS (context); + 80147fc: e0bffb17 ldw r2,-20(fp) + 8014800: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (pmsg); /* Return message received (or NULL) */ + 8014804: e0bfff17 ldw r2,-4(fp) +} + 8014808: e037883a mov sp,fp + 801480c: df000017 ldw fp,0(sp) + 8014810: dec00104 addi sp,sp,4 + 8014814: f800283a ret + +08014818 : +* == (OS_EVENT *)0 if no event control blocks were available or an error was detected +********************************************************************************************************* +*/ + +OS_EVENT *OSQCreate (void **start, INT16U size) +{ + 8014818: defff404 addi sp,sp,-48 + 801481c: dfc00b15 stw ra,44(sp) + 8014820: df000a15 stw fp,40(sp) + 8014824: df000a04 addi fp,sp,40 + 8014828: e13ff715 stw r4,-36(fp) + 801482c: 2805883a mov r2,r5 + 8014830: e0bff60d sth r2,-40(fp) + OS_EVENT *pevent; + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8014834: e03ffe15 stw zero,-8(fp) +#endif + + + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 8014838: d0a05703 ldbu r2,-32420(gp) + 801483c: 10803fcc andi r2,r2,255 + 8014840: 10000226 beq r2,zero,801484c + return ((OS_EVENT *)0); /* ... can't CREATE from an ISR */ + 8014844: 0005883a mov r2,zero + 8014848: 00005706 br 80149a8 + NIOS2_READ_STATUS (context); + 801484c: 0005303a rdctl r2,status + 8014850: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8014854: e0fffc17 ldw r3,-16(fp) + 8014858: 00bfff84 movi r2,-2 + 801485c: 1884703a and r2,r3,r2 + 8014860: 1001703a wrctl status,r2 + return context; + 8014864: e0bffc17 ldw r2,-16(fp) + } + OS_ENTER_CRITICAL(); + 8014868: e0bffe15 stw r2,-8(fp) + pevent = OSEventFreeList; /* Get next free event control block */ + 801486c: d0a05617 ldw r2,-32424(gp) + 8014870: e0bfff15 stw r2,-4(fp) + if (OSEventFreeList != (OS_EVENT *)0) { /* See if pool of free ECB pool was empty */ + 8014874: d0a05617 ldw r2,-32424(gp) + 8014878: 10000326 beq r2,zero,8014888 + OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr; + 801487c: d0a05617 ldw r2,-32424(gp) + 8014880: 10800117 ldw r2,4(r2) + 8014884: d0a05615 stw r2,-32424(gp) + 8014888: e0bffe17 ldw r2,-8(fp) + 801488c: e0bffb15 stw r2,-20(fp) + NIOS2_WRITE_STATUS (context); + 8014890: e0bffb17 ldw r2,-20(fp) + 8014894: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + if (pevent != (OS_EVENT *)0) { /* See if we have an event control block */ + 8014898: e0bfff17 ldw r2,-4(fp) + 801489c: 10004126 beq r2,zero,80149a4 + NIOS2_READ_STATUS (context); + 80148a0: 0005303a rdctl r2,status + 80148a4: e0bffa15 stw r2,-24(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 80148a8: e0fffa17 ldw r3,-24(fp) + 80148ac: 00bfff84 movi r2,-2 + 80148b0: 1884703a and r2,r3,r2 + 80148b4: 1001703a wrctl status,r2 + return context; + 80148b8: e0bffa17 ldw r2,-24(fp) + OS_ENTER_CRITICAL(); + 80148bc: e0bffe15 stw r2,-8(fp) + pq = OSQFreeList; /* Get a free queue control block */ + 80148c0: d0a05417 ldw r2,-32432(gp) + 80148c4: e0bffd15 stw r2,-12(fp) + if (pq != (OS_Q *)0) { /* Were we able to get a queue control block ? */ + 80148c8: e0bffd17 ldw r2,-12(fp) + 80148cc: 10002b26 beq r2,zero,801497c + OSQFreeList = OSQFreeList->OSQPtr; /* Yes, Adjust free list pointer to next free*/ + 80148d0: d0a05417 ldw r2,-32432(gp) + 80148d4: 10800017 ldw r2,0(r2) + 80148d8: d0a05415 stw r2,-32432(gp) + 80148dc: e0bffe17 ldw r2,-8(fp) + 80148e0: e0bff915 stw r2,-28(fp) + NIOS2_WRITE_STATUS (context); + 80148e4: e0bff917 ldw r2,-28(fp) + 80148e8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + pq->OSQStart = start; /* Initialize the queue */ + 80148ec: e0bffd17 ldw r2,-12(fp) + 80148f0: e0fff717 ldw r3,-36(fp) + 80148f4: 10c00115 stw r3,4(r2) + pq->OSQEnd = &start[size]; + 80148f8: e0bff60b ldhu r2,-40(fp) + 80148fc: 100490ba slli r2,r2,2 + 8014900: e0fff717 ldw r3,-36(fp) + 8014904: 1887883a add r3,r3,r2 + 8014908: e0bffd17 ldw r2,-12(fp) + 801490c: 10c00215 stw r3,8(r2) + pq->OSQIn = start; + 8014910: e0bffd17 ldw r2,-12(fp) + 8014914: e0fff717 ldw r3,-36(fp) + 8014918: 10c00315 stw r3,12(r2) + pq->OSQOut = start; + 801491c: e0bffd17 ldw r2,-12(fp) + 8014920: e0fff717 ldw r3,-36(fp) + 8014924: 10c00415 stw r3,16(r2) + pq->OSQSize = size; + 8014928: e0bffd17 ldw r2,-12(fp) + 801492c: e0fff60b ldhu r3,-40(fp) + 8014930: 10c0050d sth r3,20(r2) + pq->OSQEntries = 0; + 8014934: e0bffd17 ldw r2,-12(fp) + 8014938: 1000058d sth zero,22(r2) + pevent->OSEventType = OS_EVENT_TYPE_Q; + 801493c: e0bfff17 ldw r2,-4(fp) + 8014940: 00c00084 movi r3,2 + 8014944: 10c00005 stb r3,0(r2) + pevent->OSEventCnt = 0; + 8014948: e0bfff17 ldw r2,-4(fp) + 801494c: 1000020d sth zero,8(r2) + pevent->OSEventPtr = pq; + 8014950: e0bfff17 ldw r2,-4(fp) + 8014954: e0fffd17 ldw r3,-12(fp) + 8014958: 10c00115 stw r3,4(r2) +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 801495c: e0bfff17 ldw r2,-4(fp) + 8014960: 00c00fc4 movi r3,63 + 8014964: 10c00385 stb r3,14(r2) + pevent->OSEventName[1] = OS_ASCII_NUL; + 8014968: e0bfff17 ldw r2,-4(fp) + 801496c: 100003c5 stb zero,15(r2) +#endif + OS_EventWaitListInit(pevent); /* Initalize the wait list */ + 8014970: e13fff17 ldw r4,-4(fp) + 8014974: 80112580 call 8011258 + 8014978: 00000a06 br 80149a4 + } else { + pevent->OSEventPtr = (void *)OSEventFreeList; /* No, Return event control block on error */ + 801497c: d0e05617 ldw r3,-32424(gp) + 8014980: e0bfff17 ldw r2,-4(fp) + 8014984: 10c00115 stw r3,4(r2) + OSEventFreeList = pevent; + 8014988: e0bfff17 ldw r2,-4(fp) + 801498c: d0a05615 stw r2,-32424(gp) + 8014990: e0bffe17 ldw r2,-8(fp) + 8014994: e0bff815 stw r2,-32(fp) + 8014998: e0bff817 ldw r2,-32(fp) + 801499c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + pevent = (OS_EVENT *)0; + 80149a0: e03fff15 stw zero,-4(fp) + } + } + return (pevent); + 80149a4: e0bfff17 ldw r2,-4(fp) +} + 80149a8: e037883a mov sp,fp + 80149ac: dfc00117 ldw ra,4(sp) + 80149b0: df000017 ldw fp,0(sp) + 80149b4: dec00204 addi sp,sp,8 + 80149b8: f800283a ret + +080149bc : +********************************************************************************************************* +*/ + +#if OS_Q_DEL_EN > 0 +OS_EVENT *OSQDel (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + 80149bc: defff204 addi sp,sp,-56 + 80149c0: dfc00d15 stw ra,52(sp) + 80149c4: df000c15 stw fp,48(sp) + 80149c8: df000c04 addi fp,sp,48 + 80149cc: e13ff615 stw r4,-40(fp) + 80149d0: 2805883a mov r2,r5 + 80149d4: e1bff415 stw r6,-48(fp) + 80149d8: e0bff505 stb r2,-44(fp) + BOOLEAN tasks_waiting; + OS_EVENT *pevent_return; + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 80149dc: e03ffd15 stw zero,-12(fp) + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return (pevent); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 80149e0: e0bff617 ldw r2,-40(fp) + 80149e4: 10800003 ldbu r2,0(r2) + 80149e8: 10803fcc andi r2,r2,255 + 80149ec: 108000a0 cmpeqi r2,r2,2 + 80149f0: 1000051e bne r2,zero,8014a08 + *perr = OS_ERR_EVENT_TYPE; + 80149f4: e0bff417 ldw r2,-48(fp) + 80149f8: 00c00044 movi r3,1 + 80149fc: 10c00005 stb r3,0(r2) + return (pevent); + 8014a00: e0bff617 ldw r2,-40(fp) + 8014a04: 00007d06 br 8014bfc + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 8014a08: d0a05703 ldbu r2,-32420(gp) + 8014a0c: 10803fcc andi r2,r2,255 + 8014a10: 10000526 beq r2,zero,8014a28 + *perr = OS_ERR_DEL_ISR; /* ... can't DELETE from an ISR */ + 8014a14: e0bff417 ldw r2,-48(fp) + 8014a18: 00c003c4 movi r3,15 + 8014a1c: 10c00005 stb r3,0(r2) + return (pevent); + 8014a20: e0bff617 ldw r2,-40(fp) + 8014a24: 00007506 br 8014bfc + NIOS2_READ_STATUS (context); + 8014a28: 0005303a rdctl r2,status + 8014a2c: e0bffb15 stw r2,-20(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8014a30: e0fffb17 ldw r3,-20(fp) + 8014a34: 00bfff84 movi r2,-2 + 8014a38: 1884703a and r2,r3,r2 + 8014a3c: 1001703a wrctl status,r2 + return context; + 8014a40: e0bffb17 ldw r2,-20(fp) + } + OS_ENTER_CRITICAL(); + 8014a44: e0bffd15 stw r2,-12(fp) + if (pevent->OSEventGrp != 0) { /* See if any tasks waiting on queue */ + 8014a48: e0bff617 ldw r2,-40(fp) + 8014a4c: 10800283 ldbu r2,10(r2) + 8014a50: 10803fcc andi r2,r2,255 + 8014a54: 10000326 beq r2,zero,8014a64 + tasks_waiting = OS_TRUE; /* Yes */ + 8014a58: 00800044 movi r2,1 + 8014a5c: e0bfffc5 stb r2,-1(fp) + 8014a60: 00000106 br 8014a68 + } else { + tasks_waiting = OS_FALSE; /* No */ + 8014a64: e03fffc5 stb zero,-1(fp) + } + switch (opt) { + 8014a68: e0bff503 ldbu r2,-44(fp) + 8014a6c: 10000326 beq r2,zero,8014a7c + 8014a70: 10800060 cmpeqi r2,r2,1 + 8014a74: 1000301e bne r2,zero,8014b38 + 8014a78: 00005506 br 8014bd0 + case OS_DEL_NO_PEND: /* Delete queue only if no task waiting */ + if (tasks_waiting == OS_FALSE) { + 8014a7c: e0bfffc3 ldbu r2,-1(fp) + 8014a80: 10001e1e bne r2,zero,8014afc +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 8014a84: e0bff617 ldw r2,-40(fp) + 8014a88: 00c00fc4 movi r3,63 + 8014a8c: 10c00385 stb r3,14(r2) + pevent->OSEventName[1] = OS_ASCII_NUL; + 8014a90: e0bff617 ldw r2,-40(fp) + 8014a94: 100003c5 stb zero,15(r2) +#endif + pq = (OS_Q *)pevent->OSEventPtr; /* Return OS_Q to free list */ + 8014a98: e0bff617 ldw r2,-40(fp) + 8014a9c: 10800117 ldw r2,4(r2) + 8014aa0: e0bffc15 stw r2,-16(fp) + pq->OSQPtr = OSQFreeList; + 8014aa4: d0e05417 ldw r3,-32432(gp) + 8014aa8: e0bffc17 ldw r2,-16(fp) + 8014aac: 10c00015 stw r3,0(r2) + OSQFreeList = pq; + 8014ab0: e0bffc17 ldw r2,-16(fp) + 8014ab4: d0a05415 stw r2,-32432(gp) + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + 8014ab8: e0bff617 ldw r2,-40(fp) + 8014abc: 10000005 stb zero,0(r2) + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + 8014ac0: d0e05617 ldw r3,-32424(gp) + 8014ac4: e0bff617 ldw r2,-40(fp) + 8014ac8: 10c00115 stw r3,4(r2) + pevent->OSEventCnt = 0; + 8014acc: e0bff617 ldw r2,-40(fp) + 8014ad0: 1000020d sth zero,8(r2) + OSEventFreeList = pevent; /* Get next free event control block */ + 8014ad4: e0bff617 ldw r2,-40(fp) + 8014ad8: d0a05615 stw r2,-32424(gp) + 8014adc: e0bffd17 ldw r2,-12(fp) + 8014ae0: e0bffa15 stw r2,-24(fp) + NIOS2_WRITE_STATUS (context); + 8014ae4: e0bffa17 ldw r2,-24(fp) + 8014ae8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 8014aec: e0bff417 ldw r2,-48(fp) + 8014af0: 10000005 stb zero,0(r2) + pevent_return = (OS_EVENT *)0; /* Queue has been deleted */ + 8014af4: e03ffe15 stw zero,-8(fp) + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_WAITING; + pevent_return = pevent; + } + break; + 8014af8: 00003f06 br 8014bf8 + 8014afc: e0bffd17 ldw r2,-12(fp) + 8014b00: e0bff915 stw r2,-28(fp) + 8014b04: e0bff917 ldw r2,-28(fp) + 8014b08: 1001703a wrctl status,r2 + *perr = OS_ERR_TASK_WAITING; + 8014b0c: e0bff417 ldw r2,-48(fp) + 8014b10: 00c01244 movi r3,73 + 8014b14: 10c00005 stb r3,0(r2) + pevent_return = pevent; + 8014b18: e0bff617 ldw r2,-40(fp) + 8014b1c: e0bffe15 stw r2,-8(fp) + break; + 8014b20: 00003506 br 8014bf8 + + case OS_DEL_ALWAYS: /* Always delete the queue */ + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for queue */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_OK); + 8014b24: 000f883a mov r7,zero + 8014b28: 01800104 movi r6,4 + 8014b2c: 000b883a mov r5,zero + 8014b30: e13ff617 ldw r4,-40(fp) + 8014b34: 8010cd80 call 8010cd8 + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for queue */ + 8014b38: e0bff617 ldw r2,-40(fp) + 8014b3c: 10800283 ldbu r2,10(r2) + 8014b40: 10803fcc andi r2,r2,255 + 8014b44: 103ff71e bne r2,zero,8014b24 + } +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 8014b48: e0bff617 ldw r2,-40(fp) + 8014b4c: 00c00fc4 movi r3,63 + 8014b50: 10c00385 stb r3,14(r2) + pevent->OSEventName[1] = OS_ASCII_NUL; + 8014b54: e0bff617 ldw r2,-40(fp) + 8014b58: 100003c5 stb zero,15(r2) +#endif + pq = (OS_Q *)pevent->OSEventPtr; /* Return OS_Q to free list */ + 8014b5c: e0bff617 ldw r2,-40(fp) + 8014b60: 10800117 ldw r2,4(r2) + 8014b64: e0bffc15 stw r2,-16(fp) + pq->OSQPtr = OSQFreeList; + 8014b68: d0e05417 ldw r3,-32432(gp) + 8014b6c: e0bffc17 ldw r2,-16(fp) + 8014b70: 10c00015 stw r3,0(r2) + OSQFreeList = pq; + 8014b74: e0bffc17 ldw r2,-16(fp) + 8014b78: d0a05415 stw r2,-32432(gp) + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + 8014b7c: e0bff617 ldw r2,-40(fp) + 8014b80: 10000005 stb zero,0(r2) + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + 8014b84: d0e05617 ldw r3,-32424(gp) + 8014b88: e0bff617 ldw r2,-40(fp) + 8014b8c: 10c00115 stw r3,4(r2) + pevent->OSEventCnt = 0; + 8014b90: e0bff617 ldw r2,-40(fp) + 8014b94: 1000020d sth zero,8(r2) + OSEventFreeList = pevent; /* Get next free event control block */ + 8014b98: e0bff617 ldw r2,-40(fp) + 8014b9c: d0a05615 stw r2,-32424(gp) + 8014ba0: e0bffd17 ldw r2,-12(fp) + 8014ba4: e0bff815 stw r2,-32(fp) + 8014ba8: e0bff817 ldw r2,-32(fp) + 8014bac: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (tasks_waiting == OS_TRUE) { /* Reschedule only if task(s) were waiting */ + 8014bb0: e0bfffc3 ldbu r2,-1(fp) + 8014bb4: 10800058 cmpnei r2,r2,1 + 8014bb8: 1000011e bne r2,zero,8014bc0 + OS_Sched(); /* Find highest priority task ready to run */ + 8014bbc: 801166c0 call 801166c + } + *perr = OS_ERR_NONE; + 8014bc0: e0bff417 ldw r2,-48(fp) + 8014bc4: 10000005 stb zero,0(r2) + pevent_return = (OS_EVENT *)0; /* Queue has been deleted */ + 8014bc8: e03ffe15 stw zero,-8(fp) + break; + 8014bcc: 00000a06 br 8014bf8 + 8014bd0: e0bffd17 ldw r2,-12(fp) + 8014bd4: e0bff715 stw r2,-36(fp) + 8014bd8: e0bff717 ldw r2,-36(fp) + 8014bdc: 1001703a wrctl status,r2 + + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_INVALID_OPT; + 8014be0: e0bff417 ldw r2,-48(fp) + 8014be4: 00c001c4 movi r3,7 + 8014be8: 10c00005 stb r3,0(r2) + pevent_return = pevent; + 8014bec: e0bff617 ldw r2,-40(fp) + 8014bf0: e0bffe15 stw r2,-8(fp) + break; + 8014bf4: 0001883a nop + } + return (pevent_return); + 8014bf8: e0bffe17 ldw r2,-8(fp) +} + 8014bfc: e037883a mov sp,fp + 8014c00: dfc00117 ldw ra,4(sp) + 8014c04: df000017 ldw fp,0(sp) + 8014c08: dec00204 addi sp,sp,8 + 8014c0c: f800283a ret + +08014c10 : +********************************************************************************************************* +*/ + +#if OS_Q_FLUSH_EN > 0 +INT8U OSQFlush (OS_EVENT *pevent) +{ + 8014c10: defffa04 addi sp,sp,-24 + 8014c14: df000515 stw fp,20(sp) + 8014c18: df000504 addi fp,sp,20 + 8014c1c: e13ffb15 stw r4,-20(fp) + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8014c20: e03fff15 stw zero,-4(fp) + NIOS2_READ_STATUS (context); + 8014c24: 0005303a rdctl r2,status + 8014c28: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8014c2c: e0fffc17 ldw r3,-16(fp) + 8014c30: 00bfff84 movi r2,-2 + 8014c34: 1884703a and r2,r3,r2 + 8014c38: 1001703a wrctl status,r2 + return context; + 8014c3c: e0bffc17 ldw r2,-16(fp) + } + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } +#endif + OS_ENTER_CRITICAL(); + 8014c40: e0bfff15 stw r2,-4(fp) + pq = (OS_Q *)pevent->OSEventPtr; /* Point to queue storage structure */ + 8014c44: e0bffb17 ldw r2,-20(fp) + 8014c48: 10800117 ldw r2,4(r2) + 8014c4c: e0bffe15 stw r2,-8(fp) + pq->OSQIn = pq->OSQStart; + 8014c50: e0bffe17 ldw r2,-8(fp) + 8014c54: 10c00117 ldw r3,4(r2) + 8014c58: e0bffe17 ldw r2,-8(fp) + 8014c5c: 10c00315 stw r3,12(r2) + pq->OSQOut = pq->OSQStart; + 8014c60: e0bffe17 ldw r2,-8(fp) + 8014c64: 10c00117 ldw r3,4(r2) + 8014c68: e0bffe17 ldw r2,-8(fp) + 8014c6c: 10c00415 stw r3,16(r2) + pq->OSQEntries = 0; + 8014c70: e0bffe17 ldw r2,-8(fp) + 8014c74: 1000058d sth zero,22(r2) + 8014c78: e0bfff17 ldw r2,-4(fp) + 8014c7c: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context); + 8014c80: e0bffd17 ldw r2,-12(fp) + 8014c84: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 8014c88: 0005883a mov r2,zero +} + 8014c8c: e037883a mov sp,fp + 8014c90: df000017 ldw fp,0(sp) + 8014c94: dec00104 addi sp,sp,4 + 8014c98: f800283a ret + +08014c9c : +* Note(s) : As of V2.60, this function allows you to receive NULL pointer messages. +********************************************************************************************************* +*/ + +void *OSQPend (OS_EVENT *pevent, INT16U timeout, INT8U *perr) +{ + 8014c9c: defff304 addi sp,sp,-52 + 8014ca0: dfc00c15 stw ra,48(sp) + 8014ca4: df000b15 stw fp,44(sp) + 8014ca8: df000b04 addi fp,sp,44 + 8014cac: e13ff715 stw r4,-36(fp) + 8014cb0: 2805883a mov r2,r5 + 8014cb4: e1bff515 stw r6,-44(fp) + 8014cb8: e0bff60d sth r2,-40(fp) + void *pmsg; + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8014cbc: e03ffe15 stw zero,-8(fp) + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return ((void *)0); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) {/* Validate event block type */ + 8014cc0: e0bff717 ldw r2,-36(fp) + 8014cc4: 10800003 ldbu r2,0(r2) + 8014cc8: 10803fcc andi r2,r2,255 + 8014ccc: 108000a0 cmpeqi r2,r2,2 + 8014cd0: 1000051e bne r2,zero,8014ce8 + *perr = OS_ERR_EVENT_TYPE; + 8014cd4: e0bff517 ldw r2,-44(fp) + 8014cd8: 00c00044 movi r3,1 + 8014cdc: 10c00005 stb r3,0(r2) + return ((void *)0); + 8014ce0: 0005883a mov r2,zero + 8014ce4: 00008006 br 8014ee8 + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 8014ce8: d0a05703 ldbu r2,-32420(gp) + 8014cec: 10803fcc andi r2,r2,255 + 8014cf0: 10000526 beq r2,zero,8014d08 + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + 8014cf4: e0bff517 ldw r2,-44(fp) + 8014cf8: 00c00084 movi r3,2 + 8014cfc: 10c00005 stb r3,0(r2) + return ((void *)0); + 8014d00: 0005883a mov r2,zero + 8014d04: 00007806 br 8014ee8 + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + 8014d08: d0a04b03 ldbu r2,-32468(gp) + 8014d0c: 10803fcc andi r2,r2,255 + 8014d10: 10000526 beq r2,zero,8014d28 + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + 8014d14: e0bff517 ldw r2,-44(fp) + 8014d18: 00c00344 movi r3,13 + 8014d1c: 10c00005 stb r3,0(r2) + return ((void *)0); + 8014d20: 0005883a mov r2,zero + 8014d24: 00007006 br 8014ee8 + NIOS2_READ_STATUS (context); + 8014d28: 0005303a rdctl r2,status + 8014d2c: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8014d30: e0fffc17 ldw r3,-16(fp) + 8014d34: 00bfff84 movi r2,-2 + 8014d38: 1884703a and r2,r3,r2 + 8014d3c: 1001703a wrctl status,r2 + return context; + 8014d40: e0bffc17 ldw r2,-16(fp) + } + OS_ENTER_CRITICAL(); + 8014d44: e0bffe15 stw r2,-8(fp) + pq = (OS_Q *)pevent->OSEventPtr; /* Point at queue control block */ + 8014d48: e0bff717 ldw r2,-36(fp) + 8014d4c: 10800117 ldw r2,4(r2) + 8014d50: e0bffd15 stw r2,-12(fp) + if (pq->OSQEntries > 0) { /* See if any messages in the queue */ + 8014d54: e0bffd17 ldw r2,-12(fp) + 8014d58: 1080058b ldhu r2,22(r2) + 8014d5c: 10bfffcc andi r2,r2,65535 + 8014d60: 10001e26 beq r2,zero,8014ddc + pmsg = *pq->OSQOut++; /* Yes, extract oldest message from the queue */ + 8014d64: e0bffd17 ldw r2,-12(fp) + 8014d68: 10800417 ldw r2,16(r2) + 8014d6c: 11000104 addi r4,r2,4 + 8014d70: e0fffd17 ldw r3,-12(fp) + 8014d74: 19000415 stw r4,16(r3) + 8014d78: 10800017 ldw r2,0(r2) + 8014d7c: e0bfff15 stw r2,-4(fp) + pq->OSQEntries--; /* Update the number of entries in the queue */ + 8014d80: e0bffd17 ldw r2,-12(fp) + 8014d84: 1080058b ldhu r2,22(r2) + 8014d88: 10bfffc4 addi r2,r2,-1 + 8014d8c: 1007883a mov r3,r2 + 8014d90: e0bffd17 ldw r2,-12(fp) + 8014d94: 10c0058d sth r3,22(r2) + if (pq->OSQOut == pq->OSQEnd) { /* Wrap OUT pointer if we are at the end of the queue */ + 8014d98: e0bffd17 ldw r2,-12(fp) + 8014d9c: 10c00417 ldw r3,16(r2) + 8014da0: e0bffd17 ldw r2,-12(fp) + 8014da4: 10800217 ldw r2,8(r2) + 8014da8: 1880041e bne r3,r2,8014dbc + pq->OSQOut = pq->OSQStart; + 8014dac: e0bffd17 ldw r2,-12(fp) + 8014db0: 10c00117 ldw r3,4(r2) + 8014db4: e0bffd17 ldw r2,-12(fp) + 8014db8: 10c00415 stw r3,16(r2) + 8014dbc: e0bffe17 ldw r2,-8(fp) + 8014dc0: e0bffb15 stw r2,-20(fp) + NIOS2_WRITE_STATUS (context); + 8014dc4: e0bffb17 ldw r2,-20(fp) + 8014dc8: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 8014dcc: e0bff517 ldw r2,-44(fp) + 8014dd0: 10000005 stb zero,0(r2) + return (pmsg); /* Return message received */ + 8014dd4: e0bfff17 ldw r2,-4(fp) + 8014dd8: 00004306 br 8014ee8 + } + OSTCBCur->OSTCBStat |= OS_STAT_Q; /* Task will have to pend for a message to be posted */ + 8014ddc: d0a05817 ldw r2,-32416(gp) + 8014de0: 10c00c03 ldbu r3,48(r2) + 8014de4: d0a05817 ldw r2,-32416(gp) + 8014de8: 18c00114 ori r3,r3,4 + 8014dec: 10c00c05 stb r3,48(r2) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + 8014df0: d0a05817 ldw r2,-32416(gp) + 8014df4: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBDly = timeout; /* Load timeout into TCB */ + 8014df8: d0a05817 ldw r2,-32416(gp) + 8014dfc: e0fff60b ldhu r3,-40(fp) + 8014e00: 10c00b8d sth r3,46(r2) + OS_EventTaskWait(pevent); /* Suspend task until event or timeout occurs */ + 8014e04: e13ff717 ldw r4,-36(fp) + 8014e08: 8010e600 call 8010e60 + 8014e0c: e0bffe17 ldw r2,-8(fp) + 8014e10: e0bff915 stw r2,-28(fp) + 8014e14: e0bff917 ldw r2,-28(fp) + 8014e18: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next highest priority task ready to run */ + 8014e1c: 801166c0 call 801166c + NIOS2_READ_STATUS (context); + 8014e20: 0005303a rdctl r2,status + 8014e24: e0bffa15 stw r2,-24(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8014e28: e0fffa17 ldw r3,-24(fp) + 8014e2c: 00bfff84 movi r2,-2 + 8014e30: 1884703a and r2,r3,r2 + 8014e34: 1001703a wrctl status,r2 + return context; + 8014e38: e0bffa17 ldw r2,-24(fp) + OS_ENTER_CRITICAL(); + 8014e3c: e0bffe15 stw r2,-8(fp) + switch (OSTCBCur->OSTCBStatPend) { /* See if we timed-out or aborted */ + 8014e40: d0a05817 ldw r2,-32416(gp) + 8014e44: 10800c43 ldbu r2,49(r2) + 8014e48: 10803fcc andi r2,r2,255 + 8014e4c: 10000326 beq r2,zero,8014e5c + 8014e50: 108000a0 cmpeqi r2,r2,2 + 8014e54: 1000071e bne r2,zero,8014e74 + 8014e58: 00000b06 br 8014e88 + case OS_STAT_PEND_OK: /* Extract message from TCB (Put there by QPost) */ + pmsg = OSTCBCur->OSTCBMsg; + 8014e5c: d0a05817 ldw r2,-32416(gp) + 8014e60: 10800917 ldw r2,36(r2) + 8014e64: e0bfff15 stw r2,-4(fp) + *perr = OS_ERR_NONE; + 8014e68: e0bff517 ldw r2,-44(fp) + 8014e6c: 10000005 stb zero,0(r2) + break; + 8014e70: 00000e06 br 8014eac + + case OS_STAT_PEND_ABORT: + pmsg = (void *)0; + 8014e74: e03fff15 stw zero,-4(fp) + *perr = OS_ERR_PEND_ABORT; /* Indicate that we aborted */ + 8014e78: e0bff517 ldw r2,-44(fp) + 8014e7c: 00c00384 movi r3,14 + 8014e80: 10c00005 stb r3,0(r2) + break; + 8014e84: 00000906 br 8014eac + + case OS_STAT_PEND_TO: + default: + OS_EventTaskRemove(OSTCBCur, pevent); + 8014e88: d0a05817 ldw r2,-32416(gp) + 8014e8c: e17ff717 ldw r5,-36(fp) + 8014e90: 1009883a mov r4,r2 + 8014e94: 80110b00 call 80110b0 + pmsg = (void *)0; + 8014e98: e03fff15 stw zero,-4(fp) + *perr = OS_ERR_TIMEOUT; /* Indicate that we didn't get event within TO */ + 8014e9c: e0bff517 ldw r2,-44(fp) + 8014ea0: 00c00284 movi r3,10 + 8014ea4: 10c00005 stb r3,0(r2) + break; + 8014ea8: 0001883a nop + } + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Set task status to ready */ + 8014eac: d0a05817 ldw r2,-32416(gp) + 8014eb0: 10000c05 stb zero,48(r2) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + 8014eb4: d0a05817 ldw r2,-32416(gp) + 8014eb8: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; /* Clear event pointers */ + 8014ebc: d0a05817 ldw r2,-32416(gp) + 8014ec0: 10000715 stw zero,28(r2) +#if (OS_EVENT_MULTI_EN > 0) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0; + 8014ec4: d0a05817 ldw r2,-32416(gp) + 8014ec8: 10000815 stw zero,32(r2) +#endif + OSTCBCur->OSTCBMsg = (void *)0; /* Clear received message */ + 8014ecc: d0a05817 ldw r2,-32416(gp) + 8014ed0: 10000915 stw zero,36(r2) + 8014ed4: e0bffe17 ldw r2,-8(fp) + 8014ed8: e0bff815 stw r2,-32(fp) + NIOS2_WRITE_STATUS (context); + 8014edc: e0bff817 ldw r2,-32(fp) + 8014ee0: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (pmsg); /* Return received message */ + 8014ee4: e0bfff17 ldw r2,-4(fp) +} + 8014ee8: e037883a mov sp,fp + 8014eec: dfc00117 ldw ra,4(sp) + 8014ef0: df000017 ldw fp,0(sp) + 8014ef4: dec00204 addi sp,sp,8 + 8014ef8: f800283a ret + +08014efc : +********************************************************************************************************* +*/ + +#if OS_Q_PEND_ABORT_EN > 0 +INT8U OSQPendAbort (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + 8014efc: defff604 addi sp,sp,-40 + 8014f00: dfc00915 stw ra,36(sp) + 8014f04: df000815 stw fp,32(sp) + 8014f08: df000804 addi fp,sp,32 + 8014f0c: e13ffa15 stw r4,-24(fp) + 8014f10: 2805883a mov r2,r5 + 8014f14: e1bff815 stw r6,-32(fp) + 8014f18: e0bff905 stb r2,-28(fp) + INT8U nbr_tasks; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8014f1c: e03ffe15 stw zero,-8(fp) + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return (0); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 8014f20: e0bffa17 ldw r2,-24(fp) + 8014f24: 10800003 ldbu r2,0(r2) + 8014f28: 10803fcc andi r2,r2,255 + 8014f2c: 108000a0 cmpeqi r2,r2,2 + 8014f30: 1000051e bne r2,zero,8014f48 + *perr = OS_ERR_EVENT_TYPE; + 8014f34: e0bff817 ldw r2,-32(fp) + 8014f38: 00c00044 movi r3,1 + 8014f3c: 10c00005 stb r3,0(r2) + return (0); + 8014f40: 0005883a mov r2,zero + 8014f44: 00003806 br 8015028 + NIOS2_READ_STATUS (context); + 8014f48: 0005303a rdctl r2,status + 8014f4c: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8014f50: e0fffd17 ldw r3,-12(fp) + 8014f54: 00bfff84 movi r2,-2 + 8014f58: 1884703a and r2,r3,r2 + 8014f5c: 1001703a wrctl status,r2 + return context; + 8014f60: e0bffd17 ldw r2,-12(fp) + } + OS_ENTER_CRITICAL(); + 8014f64: e0bffe15 stw r2,-8(fp) + if (pevent->OSEventGrp != 0) { /* See if any task waiting on queue? */ + 8014f68: e0bffa17 ldw r2,-24(fp) + 8014f6c: 10800283 ldbu r2,10(r2) + 8014f70: 10803fcc andi r2,r2,255 + 8014f74: 10002526 beq r2,zero,801500c + nbr_tasks = 0; + 8014f78: e03fffc5 stb zero,-1(fp) + switch (opt) { + 8014f7c: e0bff903 ldbu r2,-28(fp) + 8014f80: 10800058 cmpnei r2,r2,1 + 8014f84: 10000e1e bne r2,zero,8014fc0 + case OS_PEND_OPT_BROADCAST: /* Do we need to abort ALL waiting tasks? */ + while (pevent->OSEventGrp != 0) { /* Yes, ready ALL tasks waiting on queue */ + 8014f88: 00000806 br 8014fac + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_ABORT); + 8014f8c: 01c00084 movi r7,2 + 8014f90: 01800104 movi r6,4 + 8014f94: 000b883a mov r5,zero + 8014f98: e13ffa17 ldw r4,-24(fp) + 8014f9c: 8010cd80 call 8010cd8 + nbr_tasks++; + 8014fa0: e0bfffc3 ldbu r2,-1(fp) + 8014fa4: 10800044 addi r2,r2,1 + 8014fa8: e0bfffc5 stb r2,-1(fp) + while (pevent->OSEventGrp != 0) { /* Yes, ready ALL tasks waiting on queue */ + 8014fac: e0bffa17 ldw r2,-24(fp) + 8014fb0: 10800283 ldbu r2,10(r2) + 8014fb4: 10803fcc andi r2,r2,255 + 8014fb8: 103ff41e bne r2,zero,8014f8c + } + break; + 8014fbc: 00000906 br 8014fe4 + + case OS_PEND_OPT_NONE: + default: /* No, ready HPT waiting on queue */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_ABORT); + 8014fc0: 01c00084 movi r7,2 + 8014fc4: 01800104 movi r6,4 + 8014fc8: 000b883a mov r5,zero + 8014fcc: e13ffa17 ldw r4,-24(fp) + 8014fd0: 8010cd80 call 8010cd8 + nbr_tasks++; + 8014fd4: e0bfffc3 ldbu r2,-1(fp) + 8014fd8: 10800044 addi r2,r2,1 + 8014fdc: e0bfffc5 stb r2,-1(fp) + break; + 8014fe0: 0001883a nop + 8014fe4: e0bffe17 ldw r2,-8(fp) + 8014fe8: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 8014fec: e0bffc17 ldw r2,-16(fp) + 8014ff0: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find HPT ready to run */ + 8014ff4: 801166c0 call 801166c + *perr = OS_ERR_PEND_ABORT; + 8014ff8: e0bff817 ldw r2,-32(fp) + 8014ffc: 00c00384 movi r3,14 + 8015000: 10c00005 stb r3,0(r2) + return (nbr_tasks); + 8015004: e0bfffc3 ldbu r2,-1(fp) + 8015008: 00000706 br 8015028 + 801500c: e0bffe17 ldw r2,-8(fp) + 8015010: e0bffb15 stw r2,-20(fp) + 8015014: e0bffb17 ldw r2,-20(fp) + 8015018: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 801501c: e0bff817 ldw r2,-32(fp) + 8015020: 10000005 stb zero,0(r2) + return (0); /* No tasks waiting on queue */ + 8015024: 0005883a mov r2,zero +} + 8015028: e037883a mov sp,fp + 801502c: dfc00117 ldw ra,4(sp) + 8015030: df000017 ldw fp,0(sp) + 8015034: dec00204 addi sp,sp,8 + 8015038: f800283a ret + +0801503c : +********************************************************************************************************* +*/ + +#if OS_Q_POST_EN > 0 +INT8U OSQPost (OS_EVENT *pevent, void *pmsg) +{ + 801503c: defff604 addi sp,sp,-40 + 8015040: dfc00915 stw ra,36(sp) + 8015044: df000815 stw fp,32(sp) + 8015048: df000804 addi fp,sp,32 + 801504c: e13ff915 stw r4,-28(fp) + 8015050: e17ff815 stw r5,-32(fp) + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8015054: e03fff15 stw zero,-4(fp) +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 8015058: e0bff917 ldw r2,-28(fp) + 801505c: 10800003 ldbu r2,0(r2) + 8015060: 10803fcc andi r2,r2,255 + 8015064: 108000a0 cmpeqi r2,r2,2 + 8015068: 1000021e bne r2,zero,8015074 + return (OS_ERR_EVENT_TYPE); + 801506c: 00800044 movi r2,1 + 8015070: 00004306 br 8015180 + NIOS2_READ_STATUS (context); + 8015074: 0005303a rdctl r2,status + 8015078: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 801507c: e0fffd17 ldw r3,-12(fp) + 8015080: 00bfff84 movi r2,-2 + 8015084: 1884703a and r2,r3,r2 + 8015088: 1001703a wrctl status,r2 + return context; + 801508c: e0bffd17 ldw r2,-12(fp) + } + OS_ENTER_CRITICAL(); + 8015090: e0bfff15 stw r2,-4(fp) + if (pevent->OSEventGrp != 0) { /* See if any task pending on queue */ + 8015094: e0bff917 ldw r2,-28(fp) + 8015098: 10800283 ldbu r2,10(r2) + 801509c: 10803fcc andi r2,r2,255 + 80150a0: 10000c26 beq r2,zero,80150d4 + /* Ready highest priority task waiting on event */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + 80150a4: 000f883a mov r7,zero + 80150a8: 01800104 movi r6,4 + 80150ac: e17ff817 ldw r5,-32(fp) + 80150b0: e13ff917 ldw r4,-28(fp) + 80150b4: 8010cd80 call 8010cd8 + 80150b8: e0bfff17 ldw r2,-4(fp) + 80150bc: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 80150c0: e0bffc17 ldw r2,-16(fp) + 80150c4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find highest priority task ready to run */ + 80150c8: 801166c0 call 801166c + return (OS_ERR_NONE); + 80150cc: 0005883a mov r2,zero + 80150d0: 00002b06 br 8015180 + } + pq = (OS_Q *)pevent->OSEventPtr; /* Point to queue control block */ + 80150d4: e0bff917 ldw r2,-28(fp) + 80150d8: 10800117 ldw r2,4(r2) + 80150dc: e0bffe15 stw r2,-8(fp) + if (pq->OSQEntries >= pq->OSQSize) { /* Make sure queue is not full */ + 80150e0: e0bffe17 ldw r2,-8(fp) + 80150e4: 10c0058b ldhu r3,22(r2) + 80150e8: e0bffe17 ldw r2,-8(fp) + 80150ec: 1080050b ldhu r2,20(r2) + 80150f0: 18ffffcc andi r3,r3,65535 + 80150f4: 10bfffcc andi r2,r2,65535 + 80150f8: 18800636 bltu r3,r2,8015114 + 80150fc: e0bfff17 ldw r2,-4(fp) + 8015100: e0bffb15 stw r2,-20(fp) + 8015104: e0bffb17 ldw r2,-20(fp) + 8015108: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_Q_FULL); + 801510c: 00800784 movi r2,30 + 8015110: 00001b06 br 8015180 + } + *pq->OSQIn++ = pmsg; /* Insert message into queue */ + 8015114: e0bffe17 ldw r2,-8(fp) + 8015118: 10800317 ldw r2,12(r2) + 801511c: 11000104 addi r4,r2,4 + 8015120: e0fffe17 ldw r3,-8(fp) + 8015124: 19000315 stw r4,12(r3) + 8015128: e0fff817 ldw r3,-32(fp) + 801512c: 10c00015 stw r3,0(r2) + pq->OSQEntries++; /* Update the nbr of entries in the queue */ + 8015130: e0bffe17 ldw r2,-8(fp) + 8015134: 1080058b ldhu r2,22(r2) + 8015138: 10800044 addi r2,r2,1 + 801513c: 1007883a mov r3,r2 + 8015140: e0bffe17 ldw r2,-8(fp) + 8015144: 10c0058d sth r3,22(r2) + if (pq->OSQIn == pq->OSQEnd) { /* Wrap IN ptr if we are at end of queue */ + 8015148: e0bffe17 ldw r2,-8(fp) + 801514c: 10c00317 ldw r3,12(r2) + 8015150: e0bffe17 ldw r2,-8(fp) + 8015154: 10800217 ldw r2,8(r2) + 8015158: 1880041e bne r3,r2,801516c + pq->OSQIn = pq->OSQStart; + 801515c: e0bffe17 ldw r2,-8(fp) + 8015160: 10c00117 ldw r3,4(r2) + 8015164: e0bffe17 ldw r2,-8(fp) + 8015168: 10c00315 stw r3,12(r2) + 801516c: e0bfff17 ldw r2,-4(fp) + 8015170: e0bffa15 stw r2,-24(fp) + 8015174: e0bffa17 ldw r2,-24(fp) + 8015178: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 801517c: 0005883a mov r2,zero +} + 8015180: e037883a mov sp,fp + 8015184: dfc00117 ldw ra,4(sp) + 8015188: df000017 ldw fp,0(sp) + 801518c: dec00204 addi sp,sp,8 + 8015190: f800283a ret + +08015194 : +********************************************************************************************************* +*/ + +#if OS_Q_POST_FRONT_EN > 0 +INT8U OSQPostFront (OS_EVENT *pevent, void *pmsg) +{ + 8015194: defff604 addi sp,sp,-40 + 8015198: dfc00915 stw ra,36(sp) + 801519c: df000815 stw fp,32(sp) + 80151a0: df000804 addi fp,sp,32 + 80151a4: e13ff915 stw r4,-28(fp) + 80151a8: e17ff815 stw r5,-32(fp) + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 80151ac: e03fff15 stw zero,-4(fp) +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 80151b0: e0bff917 ldw r2,-28(fp) + 80151b4: 10800003 ldbu r2,0(r2) + 80151b8: 10803fcc andi r2,r2,255 + 80151bc: 108000a0 cmpeqi r2,r2,2 + 80151c0: 1000021e bne r2,zero,80151cc + return (OS_ERR_EVENT_TYPE); + 80151c4: 00800044 movi r2,1 + 80151c8: 00004506 br 80152e0 + NIOS2_READ_STATUS (context); + 80151cc: 0005303a rdctl r2,status + 80151d0: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 80151d4: e0fffd17 ldw r3,-12(fp) + 80151d8: 00bfff84 movi r2,-2 + 80151dc: 1884703a and r2,r3,r2 + 80151e0: 1001703a wrctl status,r2 + return context; + 80151e4: e0bffd17 ldw r2,-12(fp) + } + OS_ENTER_CRITICAL(); + 80151e8: e0bfff15 stw r2,-4(fp) + if (pevent->OSEventGrp != 0) { /* See if any task pending on queue */ + 80151ec: e0bff917 ldw r2,-28(fp) + 80151f0: 10800283 ldbu r2,10(r2) + 80151f4: 10803fcc andi r2,r2,255 + 80151f8: 10000c26 beq r2,zero,801522c + /* Ready highest priority task waiting on event */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + 80151fc: 000f883a mov r7,zero + 8015200: 01800104 movi r6,4 + 8015204: e17ff817 ldw r5,-32(fp) + 8015208: e13ff917 ldw r4,-28(fp) + 801520c: 8010cd80 call 8010cd8 + 8015210: e0bfff17 ldw r2,-4(fp) + 8015214: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 8015218: e0bffc17 ldw r2,-16(fp) + 801521c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find highest priority task ready to run */ + 8015220: 801166c0 call 801166c + return (OS_ERR_NONE); + 8015224: 0005883a mov r2,zero + 8015228: 00002d06 br 80152e0 + } + pq = (OS_Q *)pevent->OSEventPtr; /* Point to queue control block */ + 801522c: e0bff917 ldw r2,-28(fp) + 8015230: 10800117 ldw r2,4(r2) + 8015234: e0bffe15 stw r2,-8(fp) + if (pq->OSQEntries >= pq->OSQSize) { /* Make sure queue is not full */ + 8015238: e0bffe17 ldw r2,-8(fp) + 801523c: 10c0058b ldhu r3,22(r2) + 8015240: e0bffe17 ldw r2,-8(fp) + 8015244: 1080050b ldhu r2,20(r2) + 8015248: 18ffffcc andi r3,r3,65535 + 801524c: 10bfffcc andi r2,r2,65535 + 8015250: 18800636 bltu r3,r2,801526c + 8015254: e0bfff17 ldw r2,-4(fp) + 8015258: e0bffb15 stw r2,-20(fp) + 801525c: e0bffb17 ldw r2,-20(fp) + 8015260: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_Q_FULL); + 8015264: 00800784 movi r2,30 + 8015268: 00001d06 br 80152e0 + } + if (pq->OSQOut == pq->OSQStart) { /* Wrap OUT ptr if we are at the 1st queue entry */ + 801526c: e0bffe17 ldw r2,-8(fp) + 8015270: 10c00417 ldw r3,16(r2) + 8015274: e0bffe17 ldw r2,-8(fp) + 8015278: 10800117 ldw r2,4(r2) + 801527c: 1880041e bne r3,r2,8015290 + pq->OSQOut = pq->OSQEnd; + 8015280: e0bffe17 ldw r2,-8(fp) + 8015284: 10c00217 ldw r3,8(r2) + 8015288: e0bffe17 ldw r2,-8(fp) + 801528c: 10c00415 stw r3,16(r2) + } + pq->OSQOut--; + 8015290: e0bffe17 ldw r2,-8(fp) + 8015294: 10800417 ldw r2,16(r2) + 8015298: 10ffff04 addi r3,r2,-4 + 801529c: e0bffe17 ldw r2,-8(fp) + 80152a0: 10c00415 stw r3,16(r2) + *pq->OSQOut = pmsg; /* Insert message into queue */ + 80152a4: e0bffe17 ldw r2,-8(fp) + 80152a8: 10800417 ldw r2,16(r2) + 80152ac: e0fff817 ldw r3,-32(fp) + 80152b0: 10c00015 stw r3,0(r2) + pq->OSQEntries++; /* Update the nbr of entries in the queue */ + 80152b4: e0bffe17 ldw r2,-8(fp) + 80152b8: 1080058b ldhu r2,22(r2) + 80152bc: 10800044 addi r2,r2,1 + 80152c0: 1007883a mov r3,r2 + 80152c4: e0bffe17 ldw r2,-8(fp) + 80152c8: 10c0058d sth r3,22(r2) + 80152cc: e0bfff17 ldw r2,-4(fp) + 80152d0: e0bffa15 stw r2,-24(fp) + 80152d4: e0bffa17 ldw r2,-24(fp) + 80152d8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 80152dc: 0005883a mov r2,zero +} + 80152e0: e037883a mov sp,fp + 80152e4: dfc00117 ldw ra,4(sp) + 80152e8: df000017 ldw fp,0(sp) + 80152ec: dec00204 addi sp,sp,8 + 80152f0: f800283a ret + +080152f4 : +********************************************************************************************************* +*/ + +#if OS_Q_POST_OPT_EN > 0 +INT8U OSQPostOpt (OS_EVENT *pevent, void *pmsg, INT8U opt) +{ + 80152f4: defff504 addi sp,sp,-44 + 80152f8: dfc00a15 stw ra,40(sp) + 80152fc: df000915 stw fp,36(sp) + 8015300: df000904 addi fp,sp,36 + 8015304: e13ff915 stw r4,-28(fp) + 8015308: e17ff815 stw r5,-32(fp) + 801530c: 3005883a mov r2,r6 + 8015310: e0bff705 stb r2,-36(fp) + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8015314: e03fff15 stw zero,-4(fp) +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 8015318: e0bff917 ldw r2,-28(fp) + 801531c: 10800003 ldbu r2,0(r2) + 8015320: 10803fcc andi r2,r2,255 + 8015324: 108000a0 cmpeqi r2,r2,2 + 8015328: 1000021e bne r2,zero,8015334 + return (OS_ERR_EVENT_TYPE); + 801532c: 00800044 movi r2,1 + 8015330: 00006a06 br 80154dc + NIOS2_READ_STATUS (context); + 8015334: 0005303a rdctl r2,status + 8015338: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 801533c: e0fffd17 ldw r3,-12(fp) + 8015340: 00bfff84 movi r2,-2 + 8015344: 1884703a and r2,r3,r2 + 8015348: 1001703a wrctl status,r2 + return context; + 801534c: e0bffd17 ldw r2,-12(fp) + } + OS_ENTER_CRITICAL(); + 8015350: e0bfff15 stw r2,-4(fp) + if (pevent->OSEventGrp != 0x00) { /* See if any task pending on queue */ + 8015354: e0bff917 ldw r2,-28(fp) + 8015358: 10800283 ldbu r2,10(r2) + 801535c: 10803fcc andi r2,r2,255 + 8015360: 10001d26 beq r2,zero,80153d8 + if ((opt & OS_POST_OPT_BROADCAST) != 0x00) { /* Do we need to post msg to ALL waiting tasks ? */ + 8015364: e0bff703 ldbu r2,-36(fp) + 8015368: 1080004c andi r2,r2,1 + 801536c: 10000b26 beq r2,zero,801539c + while (pevent->OSEventGrp != 0) { /* Yes, Post to ALL tasks waiting on queue */ + 8015370: 00000506 br 8015388 + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + 8015374: 000f883a mov r7,zero + 8015378: 01800104 movi r6,4 + 801537c: e17ff817 ldw r5,-32(fp) + 8015380: e13ff917 ldw r4,-28(fp) + 8015384: 8010cd80 call 8010cd8 + while (pevent->OSEventGrp != 0) { /* Yes, Post to ALL tasks waiting on queue */ + 8015388: e0bff917 ldw r2,-28(fp) + 801538c: 10800283 ldbu r2,10(r2) + 8015390: 10803fcc andi r2,r2,255 + 8015394: 103ff71e bne r2,zero,8015374 + 8015398: 00000506 br 80153b0 + } + } else { /* No, Post to HPT waiting on queue */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + 801539c: 000f883a mov r7,zero + 80153a0: 01800104 movi r6,4 + 80153a4: e17ff817 ldw r5,-32(fp) + 80153a8: e13ff917 ldw r4,-28(fp) + 80153ac: 8010cd80 call 8010cd8 + 80153b0: e0bfff17 ldw r2,-4(fp) + 80153b4: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 80153b8: e0bffc17 ldw r2,-16(fp) + 80153bc: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + if ((opt & OS_POST_OPT_NO_SCHED) == 0) { /* See if scheduler needs to be invoked */ + 80153c0: e0bff703 ldbu r2,-36(fp) + 80153c4: 1080010c andi r2,r2,4 + 80153c8: 1000011e bne r2,zero,80153d0 + OS_Sched(); /* Find highest priority task ready to run */ + 80153cc: 801166c0 call 801166c + } + return (OS_ERR_NONE); + 80153d0: 0005883a mov r2,zero + 80153d4: 00004106 br 80154dc + } + pq = (OS_Q *)pevent->OSEventPtr; /* Point to queue control block */ + 80153d8: e0bff917 ldw r2,-28(fp) + 80153dc: 10800117 ldw r2,4(r2) + 80153e0: e0bffe15 stw r2,-8(fp) + if (pq->OSQEntries >= pq->OSQSize) { /* Make sure queue is not full */ + 80153e4: e0bffe17 ldw r2,-8(fp) + 80153e8: 10c0058b ldhu r3,22(r2) + 80153ec: e0bffe17 ldw r2,-8(fp) + 80153f0: 1080050b ldhu r2,20(r2) + 80153f4: 18ffffcc andi r3,r3,65535 + 80153f8: 10bfffcc andi r2,r2,65535 + 80153fc: 18800636 bltu r3,r2,8015418 + 8015400: e0bfff17 ldw r2,-4(fp) + 8015404: e0bffb15 stw r2,-20(fp) + 8015408: e0bffb17 ldw r2,-20(fp) + 801540c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_Q_FULL); + 8015410: 00800784 movi r2,30 + 8015414: 00003106 br 80154dc + } + if ((opt & OS_POST_OPT_FRONT) != 0x00) { /* Do we post to the FRONT of the queue? */ + 8015418: e0bff703 ldbu r2,-36(fp) + 801541c: 1080008c andi r2,r2,2 + 8015420: 10001326 beq r2,zero,8015470 + if (pq->OSQOut == pq->OSQStart) { /* Yes, Post as LIFO, Wrap OUT pointer if we ... */ + 8015424: e0bffe17 ldw r2,-8(fp) + 8015428: 10c00417 ldw r3,16(r2) + 801542c: e0bffe17 ldw r2,-8(fp) + 8015430: 10800117 ldw r2,4(r2) + 8015434: 1880041e bne r3,r2,8015448 + pq->OSQOut = pq->OSQEnd; /* ... are at the 1st queue entry */ + 8015438: e0bffe17 ldw r2,-8(fp) + 801543c: 10c00217 ldw r3,8(r2) + 8015440: e0bffe17 ldw r2,-8(fp) + 8015444: 10c00415 stw r3,16(r2) + } + pq->OSQOut--; + 8015448: e0bffe17 ldw r2,-8(fp) + 801544c: 10800417 ldw r2,16(r2) + 8015450: 10ffff04 addi r3,r2,-4 + 8015454: e0bffe17 ldw r2,-8(fp) + 8015458: 10c00415 stw r3,16(r2) + *pq->OSQOut = pmsg; /* Insert message into queue */ + 801545c: e0bffe17 ldw r2,-8(fp) + 8015460: 10800417 ldw r2,16(r2) + 8015464: e0fff817 ldw r3,-32(fp) + 8015468: 10c00015 stw r3,0(r2) + 801546c: 00001006 br 80154b0 + } else { /* No, Post as FIFO */ + *pq->OSQIn++ = pmsg; /* Insert message into queue */ + 8015470: e0bffe17 ldw r2,-8(fp) + 8015474: 10800317 ldw r2,12(r2) + 8015478: 11000104 addi r4,r2,4 + 801547c: e0fffe17 ldw r3,-8(fp) + 8015480: 19000315 stw r4,12(r3) + 8015484: e0fff817 ldw r3,-32(fp) + 8015488: 10c00015 stw r3,0(r2) + if (pq->OSQIn == pq->OSQEnd) { /* Wrap IN ptr if we are at end of queue */ + 801548c: e0bffe17 ldw r2,-8(fp) + 8015490: 10c00317 ldw r3,12(r2) + 8015494: e0bffe17 ldw r2,-8(fp) + 8015498: 10800217 ldw r2,8(r2) + 801549c: 1880041e bne r3,r2,80154b0 + pq->OSQIn = pq->OSQStart; + 80154a0: e0bffe17 ldw r2,-8(fp) + 80154a4: 10c00117 ldw r3,4(r2) + 80154a8: e0bffe17 ldw r2,-8(fp) + 80154ac: 10c00315 stw r3,12(r2) + } + } + pq->OSQEntries++; /* Update the nbr of entries in the queue */ + 80154b0: e0bffe17 ldw r2,-8(fp) + 80154b4: 1080058b ldhu r2,22(r2) + 80154b8: 10800044 addi r2,r2,1 + 80154bc: 1007883a mov r3,r2 + 80154c0: e0bffe17 ldw r2,-8(fp) + 80154c4: 10c0058d sth r3,22(r2) + 80154c8: e0bfff17 ldw r2,-4(fp) + 80154cc: e0bffa15 stw r2,-24(fp) + 80154d0: e0bffa17 ldw r2,-24(fp) + 80154d4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 80154d8: 0005883a mov r2,zero +} + 80154dc: e037883a mov sp,fp + 80154e0: dfc00117 ldw ra,4(sp) + 80154e4: df000017 ldw fp,0(sp) + 80154e8: dec00204 addi sp,sp,8 + 80154ec: f800283a ret + +080154f0 : +********************************************************************************************************* +*/ + +#if OS_Q_QUERY_EN > 0 +INT8U OSQQuery (OS_EVENT *pevent, OS_Q_DATA *p_q_data) +{ + 80154f0: defff604 addi sp,sp,-40 + 80154f4: df000915 stw fp,36(sp) + 80154f8: df000904 addi fp,sp,36 + 80154fc: e13ff815 stw r4,-32(fp) + 8015500: e17ff715 stw r5,-36(fp) +#else + INT16U *psrc; + INT16U *pdest; +#endif +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8015504: e03ffc15 stw zero,-16(fp) + } + if (p_q_data == (OS_Q_DATA *)0) { /* Validate 'p_q_data' */ + return (OS_ERR_PDATA_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 8015508: e0bff817 ldw r2,-32(fp) + 801550c: 10800003 ldbu r2,0(r2) + 8015510: 10803fcc andi r2,r2,255 + 8015514: 108000a0 cmpeqi r2,r2,2 + 8015518: 1000021e bne r2,zero,8015524 + return (OS_ERR_EVENT_TYPE); + 801551c: 00800044 movi r2,1 + 8015520: 00003e06 br 801561c + NIOS2_READ_STATUS (context); + 8015524: 0005303a rdctl r2,status + 8015528: e0bffa15 stw r2,-24(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 801552c: e0fffa17 ldw r3,-24(fp) + 8015530: 00bfff84 movi r2,-2 + 8015534: 1884703a and r2,r3,r2 + 8015538: 1001703a wrctl status,r2 + return context; + 801553c: e0bffa17 ldw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + 8015540: e0bffc15 stw r2,-16(fp) + p_q_data->OSEventGrp = pevent->OSEventGrp; /* Copy message queue wait list */ + 8015544: e0bff817 ldw r2,-32(fp) + 8015548: 10c00283 ldbu r3,10(r2) + 801554c: e0bff717 ldw r2,-36(fp) + 8015550: 10c002c5 stb r3,11(r2) + psrc = &pevent->OSEventTbl[0]; + 8015554: e0bff817 ldw r2,-32(fp) + 8015558: 108002c4 addi r2,r2,11 + 801555c: e0bffe15 stw r2,-8(fp) + pdest = &p_q_data->OSEventTbl[0]; + 8015560: e0bff717 ldw r2,-36(fp) + 8015564: 10800204 addi r2,r2,8 + 8015568: e0bffd15 stw r2,-12(fp) + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 801556c: e03fffc5 stb zero,-1(fp) + 8015570: 00000b06 br 80155a0 + *pdest++ = *psrc++; + 8015574: e0fffe17 ldw r3,-8(fp) + 8015578: 18800044 addi r2,r3,1 + 801557c: e0bffe15 stw r2,-8(fp) + 8015580: e0bffd17 ldw r2,-12(fp) + 8015584: 11000044 addi r4,r2,1 + 8015588: e13ffd15 stw r4,-12(fp) + 801558c: 18c00003 ldbu r3,0(r3) + 8015590: 10c00005 stb r3,0(r2) + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 8015594: e0bfffc3 ldbu r2,-1(fp) + 8015598: 10800044 addi r2,r2,1 + 801559c: e0bfffc5 stb r2,-1(fp) + 80155a0: e0bfffc3 ldbu r2,-1(fp) + 80155a4: 108000f0 cmpltui r2,r2,3 + 80155a8: 103ff21e bne r2,zero,8015574 + } + pq = (OS_Q *)pevent->OSEventPtr; + 80155ac: e0bff817 ldw r2,-32(fp) + 80155b0: 10800117 ldw r2,4(r2) + 80155b4: e0bffb15 stw r2,-20(fp) + if (pq->OSQEntries > 0) { + 80155b8: e0bffb17 ldw r2,-20(fp) + 80155bc: 1080058b ldhu r2,22(r2) + 80155c0: 10bfffcc andi r2,r2,65535 + 80155c4: 10000626 beq r2,zero,80155e0 + p_q_data->OSMsg = *pq->OSQOut; /* Get next message to return if available */ + 80155c8: e0bffb17 ldw r2,-20(fp) + 80155cc: 10800417 ldw r2,16(r2) + 80155d0: 10c00017 ldw r3,0(r2) + 80155d4: e0bff717 ldw r2,-36(fp) + 80155d8: 10c00015 stw r3,0(r2) + 80155dc: 00000206 br 80155e8 + } else { + p_q_data->OSMsg = (void *)0; + 80155e0: e0bff717 ldw r2,-36(fp) + 80155e4: 10000015 stw zero,0(r2) + } + p_q_data->OSNMsgs = pq->OSQEntries; + 80155e8: e0bffb17 ldw r2,-20(fp) + 80155ec: 10c0058b ldhu r3,22(r2) + 80155f0: e0bff717 ldw r2,-36(fp) + 80155f4: 10c0010d sth r3,4(r2) + p_q_data->OSQSize = pq->OSQSize; + 80155f8: e0bffb17 ldw r2,-20(fp) + 80155fc: 10c0050b ldhu r3,20(r2) + 8015600: e0bff717 ldw r2,-36(fp) + 8015604: 10c0018d sth r3,6(r2) + 8015608: e0bffc17 ldw r2,-16(fp) + 801560c: e0bff915 stw r2,-28(fp) + NIOS2_WRITE_STATUS (context); + 8015610: e0bff917 ldw r2,-28(fp) + 8015614: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 8015618: 0005883a mov r2,zero +} + 801561c: e037883a mov sp,fp + 8015620: df000017 ldw fp,0(sp) + 8015624: dec00104 addi sp,sp,4 + 8015628: f800283a ret + +0801562c : +* Note(s) : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +void OS_QInit (void) +{ + 801562c: defffb04 addi sp,sp,-20 + 8015630: dfc00415 stw ra,16(sp) + 8015634: df000315 stw fp,12(sp) + 8015638: df000304 addi fp,sp,12 + OS_Q *pq1; + OS_Q *pq2; + + + + OS_MemClr((INT8U *)&OSQTbl[0], sizeof(OSQTbl)); /* Clear the queue table */ + 801563c: 01407804 movi r5,480 + 8015640: 010201b4 movhi r4,2054 + 8015644: 212f7304 addi r4,r4,-16948 + 8015648: 80115b00 call 80115b0 + pq1 = &OSQTbl[0]; + 801564c: 008201b4 movhi r2,2054 + 8015650: 10af7304 addi r2,r2,-16948 + 8015654: e0bffe15 stw r2,-8(fp) + pq2 = &OSQTbl[1]; + 8015658: 008201b4 movhi r2,2054 + 801565c: 10af7904 addi r2,r2,-16924 + 8015660: e0bffd15 stw r2,-12(fp) + for (i = 0; i < (OS_MAX_QS - 1); i++) { /* Init. list of free QUEUE control blocks */ + 8015664: e03fff8d sth zero,-2(fp) + 8015668: 00000c06 br 801569c + pq1->OSQPtr = pq2; + 801566c: e0bffe17 ldw r2,-8(fp) + 8015670: e0fffd17 ldw r3,-12(fp) + 8015674: 10c00015 stw r3,0(r2) + pq1++; + 8015678: e0bffe17 ldw r2,-8(fp) + 801567c: 10800604 addi r2,r2,24 + 8015680: e0bffe15 stw r2,-8(fp) + pq2++; + 8015684: e0bffd17 ldw r2,-12(fp) + 8015688: 10800604 addi r2,r2,24 + 801568c: e0bffd15 stw r2,-12(fp) + for (i = 0; i < (OS_MAX_QS - 1); i++) { /* Init. list of free QUEUE control blocks */ + 8015690: e0bfff8b ldhu r2,-2(fp) + 8015694: 10800044 addi r2,r2,1 + 8015698: e0bfff8d sth r2,-2(fp) + 801569c: e0bfff8b ldhu r2,-2(fp) + 80156a0: 108004f0 cmpltui r2,r2,19 + 80156a4: 103ff11e bne r2,zero,801566c + } + pq1->OSQPtr = (OS_Q *)0; + 80156a8: e0bffe17 ldw r2,-8(fp) + 80156ac: 10000015 stw zero,0(r2) + OSQFreeList = &OSQTbl[0]; + 80156b0: 008201b4 movhi r2,2054 + 80156b4: 10af7304 addi r2,r2,-16948 + 80156b8: d0a05415 stw r2,-32432(gp) +#endif +} + 80156bc: 0001883a nop + 80156c0: e037883a mov sp,fp + 80156c4: dfc00117 ldw ra,4(sp) + 80156c8: df000017 ldw fp,0(sp) + 80156cc: dec00204 addi sp,sp,8 + 80156d0: f800283a ret + +080156d4 : +********************************************************************************************************* +*/ + +#if OS_SEM_ACCEPT_EN > 0 +INT16U OSSemAccept (OS_EVENT *pevent) +{ + 80156d4: defffa04 addi sp,sp,-24 + 80156d8: df000515 stw fp,20(sp) + 80156dc: df000504 addi fp,sp,20 + 80156e0: e13ffb15 stw r4,-20(fp) + INT16U cnt; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 80156e4: e03fff15 stw zero,-4(fp) +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (0); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 80156e8: e0bffb17 ldw r2,-20(fp) + 80156ec: 10800003 ldbu r2,0(r2) + 80156f0: 10803fcc andi r2,r2,255 + 80156f4: 108000e0 cmpeqi r2,r2,3 + 80156f8: 1000021e bne r2,zero,8015704 + return (0); + 80156fc: 0005883a mov r2,zero + 8015700: 00001806 br 8015764 + NIOS2_READ_STATUS (context); + 8015704: 0005303a rdctl r2,status + 8015708: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 801570c: e0fffd17 ldw r3,-12(fp) + 8015710: 00bfff84 movi r2,-2 + 8015714: 1884703a and r2,r3,r2 + 8015718: 1001703a wrctl status,r2 + return context; + 801571c: e0bffd17 ldw r2,-12(fp) + } + OS_ENTER_CRITICAL(); + 8015720: e0bfff15 stw r2,-4(fp) + cnt = pevent->OSEventCnt; + 8015724: e0bffb17 ldw r2,-20(fp) + 8015728: 1080020b ldhu r2,8(r2) + 801572c: e0bffe8d sth r2,-6(fp) + if (cnt > 0) { /* See if resource is available */ + 8015730: e0bffe8b ldhu r2,-6(fp) + 8015734: 10000626 beq r2,zero,8015750 + pevent->OSEventCnt--; /* Yes, decrement semaphore and notify caller */ + 8015738: e0bffb17 ldw r2,-20(fp) + 801573c: 1080020b ldhu r2,8(r2) + 8015740: 10bfffc4 addi r2,r2,-1 + 8015744: 1007883a mov r3,r2 + 8015748: e0bffb17 ldw r2,-20(fp) + 801574c: 10c0020d sth r3,8(r2) + 8015750: e0bfff17 ldw r2,-4(fp) + 8015754: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 8015758: e0bffc17 ldw r2,-16(fp) + 801575c: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (cnt); /* Return semaphore count */ + 8015760: e0bffe8b ldhu r2,-6(fp) +} + 8015764: e037883a mov sp,fp + 8015768: df000017 ldw fp,0(sp) + 801576c: dec00104 addi sp,sp,4 + 8015770: f800283a ret + +08015774 : +* == (void *)0 if no event control blocks were available +********************************************************************************************************* +*/ + +OS_EVENT *OSSemCreate (INT16U cnt) +{ + 8015774: defff904 addi sp,sp,-28 + 8015778: dfc00615 stw ra,24(sp) + 801577c: df000515 stw fp,20(sp) + 8015780: df000504 addi fp,sp,20 + 8015784: 2005883a mov r2,r4 + 8015788: e0bffb0d sth r2,-20(fp) + OS_EVENT *pevent; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 801578c: e03fff15 stw zero,-4(fp) +#endif + + + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 8015790: d0a05703 ldbu r2,-32420(gp) + 8015794: 10803fcc andi r2,r2,255 + 8015798: 10000226 beq r2,zero,80157a4 + return ((OS_EVENT *)0); /* ... can't CREATE from an ISR */ + 801579c: 0005883a mov r2,zero + 80157a0: 00002506 br 8015838 + NIOS2_READ_STATUS (context); + 80157a4: 0005303a rdctl r2,status + 80157a8: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 80157ac: e0fffd17 ldw r3,-12(fp) + 80157b0: 00bfff84 movi r2,-2 + 80157b4: 1884703a and r2,r3,r2 + 80157b8: 1001703a wrctl status,r2 + return context; + 80157bc: e0bffd17 ldw r2,-12(fp) + } + OS_ENTER_CRITICAL(); + 80157c0: e0bfff15 stw r2,-4(fp) + pevent = OSEventFreeList; /* Get next free event control block */ + 80157c4: d0a05617 ldw r2,-32424(gp) + 80157c8: e0bffe15 stw r2,-8(fp) + if (OSEventFreeList != (OS_EVENT *)0) { /* See if pool of free ECB pool was empty */ + 80157cc: d0a05617 ldw r2,-32424(gp) + 80157d0: 10000326 beq r2,zero,80157e0 + OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr; + 80157d4: d0a05617 ldw r2,-32424(gp) + 80157d8: 10800117 ldw r2,4(r2) + 80157dc: d0a05615 stw r2,-32424(gp) + 80157e0: e0bfff17 ldw r2,-4(fp) + 80157e4: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 80157e8: e0bffc17 ldw r2,-16(fp) + 80157ec: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + if (pevent != (OS_EVENT *)0) { /* Get an event control block */ + 80157f0: e0bffe17 ldw r2,-8(fp) + 80157f4: 10000f26 beq r2,zero,8015834 + pevent->OSEventType = OS_EVENT_TYPE_SEM; + 80157f8: e0bffe17 ldw r2,-8(fp) + 80157fc: 00c000c4 movi r3,3 + 8015800: 10c00005 stb r3,0(r2) + pevent->OSEventCnt = cnt; /* Set semaphore value */ + 8015804: e0bffe17 ldw r2,-8(fp) + 8015808: e0fffb0b ldhu r3,-20(fp) + 801580c: 10c0020d sth r3,8(r2) + pevent->OSEventPtr = (void *)0; /* Unlink from ECB free list */ + 8015810: e0bffe17 ldw r2,-8(fp) + 8015814: 10000115 stw zero,4(r2) +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 8015818: e0bffe17 ldw r2,-8(fp) + 801581c: 00c00fc4 movi r3,63 + 8015820: 10c00385 stb r3,14(r2) + pevent->OSEventName[1] = OS_ASCII_NUL; + 8015824: e0bffe17 ldw r2,-8(fp) + 8015828: 100003c5 stb zero,15(r2) +#endif + OS_EventWaitListInit(pevent); /* Initialize to 'nobody waiting' on sem. */ + 801582c: e13ffe17 ldw r4,-8(fp) + 8015830: 80112580 call 8011258 + } + return (pevent); + 8015834: e0bffe17 ldw r2,-8(fp) +} + 8015838: e037883a mov sp,fp + 801583c: dfc00117 ldw ra,4(sp) + 8015840: df000017 ldw fp,0(sp) + 8015844: dec00204 addi sp,sp,8 + 8015848: f800283a ret + +0801584c : +********************************************************************************************************* +*/ + +#if OS_SEM_DEL_EN > 0 +OS_EVENT *OSSemDel (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + 801584c: defff304 addi sp,sp,-52 + 8015850: dfc00c15 stw ra,48(sp) + 8015854: df000b15 stw fp,44(sp) + 8015858: df000b04 addi fp,sp,44 + 801585c: e13ff715 stw r4,-36(fp) + 8015860: 2805883a mov r2,r5 + 8015864: e1bff515 stw r6,-44(fp) + 8015868: e0bff605 stb r2,-40(fp) + BOOLEAN tasks_waiting; + OS_EVENT *pevent_return; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 801586c: e03ffd15 stw zero,-12(fp) + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return (pevent); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 8015870: e0bff717 ldw r2,-36(fp) + 8015874: 10800003 ldbu r2,0(r2) + 8015878: 10803fcc andi r2,r2,255 + 801587c: 108000e0 cmpeqi r2,r2,3 + 8015880: 1000051e bne r2,zero,8015898 + *perr = OS_ERR_EVENT_TYPE; + 8015884: e0bff517 ldw r2,-44(fp) + 8015888: 00c00044 movi r3,1 + 801588c: 10c00005 stb r3,0(r2) + return (pevent); + 8015890: e0bff717 ldw r2,-36(fp) + 8015894: 00006d06 br 8015a4c + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 8015898: d0a05703 ldbu r2,-32420(gp) + 801589c: 10803fcc andi r2,r2,255 + 80158a0: 10000526 beq r2,zero,80158b8 + *perr = OS_ERR_DEL_ISR; /* ... can't DELETE from an ISR */ + 80158a4: e0bff517 ldw r2,-44(fp) + 80158a8: 00c003c4 movi r3,15 + 80158ac: 10c00005 stb r3,0(r2) + return (pevent); + 80158b0: e0bff717 ldw r2,-36(fp) + 80158b4: 00006506 br 8015a4c + NIOS2_READ_STATUS (context); + 80158b8: 0005303a rdctl r2,status + 80158bc: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 80158c0: e0fffc17 ldw r3,-16(fp) + 80158c4: 00bfff84 movi r2,-2 + 80158c8: 1884703a and r2,r3,r2 + 80158cc: 1001703a wrctl status,r2 + return context; + 80158d0: e0bffc17 ldw r2,-16(fp) + } + OS_ENTER_CRITICAL(); + 80158d4: e0bffd15 stw r2,-12(fp) + if (pevent->OSEventGrp != 0) { /* See if any tasks waiting on semaphore */ + 80158d8: e0bff717 ldw r2,-36(fp) + 80158dc: 10800283 ldbu r2,10(r2) + 80158e0: 10803fcc andi r2,r2,255 + 80158e4: 10000326 beq r2,zero,80158f4 + tasks_waiting = OS_TRUE; /* Yes */ + 80158e8: 00800044 movi r2,1 + 80158ec: e0bfffc5 stb r2,-1(fp) + 80158f0: 00000106 br 80158f8 + } else { + tasks_waiting = OS_FALSE; /* No */ + 80158f4: e03fffc5 stb zero,-1(fp) + } + switch (opt) { + 80158f8: e0bff603 ldbu r2,-40(fp) + 80158fc: 10000326 beq r2,zero,801590c + 8015900: 10800060 cmpeqi r2,r2,1 + 8015904: 1000281e bne r2,zero,80159a8 + 8015908: 00004506 br 8015a20 + case OS_DEL_NO_PEND: /* Delete semaphore only if no task waiting */ + if (tasks_waiting == OS_FALSE) { + 801590c: e0bfffc3 ldbu r2,-1(fp) + 8015910: 1000161e bne r2,zero,801596c +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 8015914: e0bff717 ldw r2,-36(fp) + 8015918: 00c00fc4 movi r3,63 + 801591c: 10c00385 stb r3,14(r2) + pevent->OSEventName[1] = OS_ASCII_NUL; + 8015920: e0bff717 ldw r2,-36(fp) + 8015924: 100003c5 stb zero,15(r2) +#endif + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + 8015928: e0bff717 ldw r2,-36(fp) + 801592c: 10000005 stb zero,0(r2) + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + 8015930: d0e05617 ldw r3,-32424(gp) + 8015934: e0bff717 ldw r2,-36(fp) + 8015938: 10c00115 stw r3,4(r2) + pevent->OSEventCnt = 0; + 801593c: e0bff717 ldw r2,-36(fp) + 8015940: 1000020d sth zero,8(r2) + OSEventFreeList = pevent; /* Get next free event control block */ + 8015944: e0bff717 ldw r2,-36(fp) + 8015948: d0a05615 stw r2,-32424(gp) + 801594c: e0bffd17 ldw r2,-12(fp) + 8015950: e0bffb15 stw r2,-20(fp) + NIOS2_WRITE_STATUS (context); + 8015954: e0bffb17 ldw r2,-20(fp) + 8015958: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 801595c: e0bff517 ldw r2,-44(fp) + 8015960: 10000005 stb zero,0(r2) + pevent_return = (OS_EVENT *)0; /* Semaphore has been deleted */ + 8015964: e03ffe15 stw zero,-8(fp) + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_WAITING; + pevent_return = pevent; + } + break; + 8015968: 00003706 br 8015a48 + 801596c: e0bffd17 ldw r2,-12(fp) + 8015970: e0bffa15 stw r2,-24(fp) + 8015974: e0bffa17 ldw r2,-24(fp) + 8015978: 1001703a wrctl status,r2 + *perr = OS_ERR_TASK_WAITING; + 801597c: e0bff517 ldw r2,-44(fp) + 8015980: 00c01244 movi r3,73 + 8015984: 10c00005 stb r3,0(r2) + pevent_return = pevent; + 8015988: e0bff717 ldw r2,-36(fp) + 801598c: e0bffe15 stw r2,-8(fp) + break; + 8015990: 00002d06 br 8015a48 + + case OS_DEL_ALWAYS: /* Always delete the semaphore */ + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for semaphore */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_OK); + 8015994: 000f883a mov r7,zero + 8015998: 01800044 movi r6,1 + 801599c: 000b883a mov r5,zero + 80159a0: e13ff717 ldw r4,-36(fp) + 80159a4: 8010cd80 call 8010cd8 + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for semaphore */ + 80159a8: e0bff717 ldw r2,-36(fp) + 80159ac: 10800283 ldbu r2,10(r2) + 80159b0: 10803fcc andi r2,r2,255 + 80159b4: 103ff71e bne r2,zero,8015994 + } +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 80159b8: e0bff717 ldw r2,-36(fp) + 80159bc: 00c00fc4 movi r3,63 + 80159c0: 10c00385 stb r3,14(r2) + pevent->OSEventName[1] = OS_ASCII_NUL; + 80159c4: e0bff717 ldw r2,-36(fp) + 80159c8: 100003c5 stb zero,15(r2) +#endif + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + 80159cc: e0bff717 ldw r2,-36(fp) + 80159d0: 10000005 stb zero,0(r2) + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + 80159d4: d0e05617 ldw r3,-32424(gp) + 80159d8: e0bff717 ldw r2,-36(fp) + 80159dc: 10c00115 stw r3,4(r2) + pevent->OSEventCnt = 0; + 80159e0: e0bff717 ldw r2,-36(fp) + 80159e4: 1000020d sth zero,8(r2) + OSEventFreeList = pevent; /* Get next free event control block */ + 80159e8: e0bff717 ldw r2,-36(fp) + 80159ec: d0a05615 stw r2,-32424(gp) + 80159f0: e0bffd17 ldw r2,-12(fp) + 80159f4: e0bff915 stw r2,-28(fp) + 80159f8: e0bff917 ldw r2,-28(fp) + 80159fc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (tasks_waiting == OS_TRUE) { /* Reschedule only if task(s) were waiting */ + 8015a00: e0bfffc3 ldbu r2,-1(fp) + 8015a04: 10800058 cmpnei r2,r2,1 + 8015a08: 1000011e bne r2,zero,8015a10 + OS_Sched(); /* Find highest priority task ready to run */ + 8015a0c: 801166c0 call 801166c + } + *perr = OS_ERR_NONE; + 8015a10: e0bff517 ldw r2,-44(fp) + 8015a14: 10000005 stb zero,0(r2) + pevent_return = (OS_EVENT *)0; /* Semaphore has been deleted */ + 8015a18: e03ffe15 stw zero,-8(fp) + break; + 8015a1c: 00000a06 br 8015a48 + 8015a20: e0bffd17 ldw r2,-12(fp) + 8015a24: e0bff815 stw r2,-32(fp) + 8015a28: e0bff817 ldw r2,-32(fp) + 8015a2c: 1001703a wrctl status,r2 + + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_INVALID_OPT; + 8015a30: e0bff517 ldw r2,-44(fp) + 8015a34: 00c001c4 movi r3,7 + 8015a38: 10c00005 stb r3,0(r2) + pevent_return = pevent; + 8015a3c: e0bff717 ldw r2,-36(fp) + 8015a40: e0bffe15 stw r2,-8(fp) + break; + 8015a44: 0001883a nop + } + return (pevent_return); + 8015a48: e0bffe17 ldw r2,-8(fp) +} + 8015a4c: e037883a mov sp,fp + 8015a50: dfc00117 ldw ra,4(sp) + 8015a54: df000017 ldw fp,0(sp) + 8015a58: dec00204 addi sp,sp,8 + 8015a5c: f800283a ret + +08015a60 : +* Returns : none +********************************************************************************************************* +*/ +/*$PAGE*/ +void OSSemPend (OS_EVENT *pevent, INT16U timeout, INT8U *perr) +{ + 8015a60: defff504 addi sp,sp,-44 + 8015a64: dfc00a15 stw ra,40(sp) + 8015a68: df000915 stw fp,36(sp) + 8015a6c: df000904 addi fp,sp,36 + 8015a70: e13ff915 stw r4,-28(fp) + 8015a74: 2805883a mov r2,r5 + 8015a78: e1bff715 stw r6,-36(fp) + 8015a7c: e0bff80d sth r2,-32(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8015a80: e03fff15 stw zero,-4(fp) + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return; + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 8015a84: e0bff917 ldw r2,-28(fp) + 8015a88: 10800003 ldbu r2,0(r2) + 8015a8c: 10803fcc andi r2,r2,255 + 8015a90: 108000e0 cmpeqi r2,r2,3 + 8015a94: 1000041e bne r2,zero,8015aa8 + *perr = OS_ERR_EVENT_TYPE; + 8015a98: e0bff717 ldw r2,-36(fp) + 8015a9c: 00c00044 movi r3,1 + 8015aa0: 10c00005 stb r3,0(r2) + return; + 8015aa4: 00006206 br 8015c30 + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 8015aa8: d0a05703 ldbu r2,-32420(gp) + 8015aac: 10803fcc andi r2,r2,255 + 8015ab0: 10000426 beq r2,zero,8015ac4 + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + 8015ab4: e0bff717 ldw r2,-36(fp) + 8015ab8: 00c00084 movi r3,2 + 8015abc: 10c00005 stb r3,0(r2) + return; + 8015ac0: 00005b06 br 8015c30 + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + 8015ac4: d0a04b03 ldbu r2,-32468(gp) + 8015ac8: 10803fcc andi r2,r2,255 + 8015acc: 10000426 beq r2,zero,8015ae0 + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + 8015ad0: e0bff717 ldw r2,-36(fp) + 8015ad4: 00c00344 movi r3,13 + 8015ad8: 10c00005 stb r3,0(r2) + return; + 8015adc: 00005406 br 8015c30 + NIOS2_READ_STATUS (context); + 8015ae0: 0005303a rdctl r2,status + 8015ae4: e0bffe15 stw r2,-8(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8015ae8: e0fffe17 ldw r3,-8(fp) + 8015aec: 00bfff84 movi r2,-2 + 8015af0: 1884703a and r2,r3,r2 + 8015af4: 1001703a wrctl status,r2 + return context; + 8015af8: e0bffe17 ldw r2,-8(fp) + } + OS_ENTER_CRITICAL(); + 8015afc: e0bfff15 stw r2,-4(fp) + if (pevent->OSEventCnt > 0) { /* If sem. is positive, resource available ... */ + 8015b00: e0bff917 ldw r2,-28(fp) + 8015b04: 1080020b ldhu r2,8(r2) + 8015b08: 10bfffcc andi r2,r2,65535 + 8015b0c: 10000d26 beq r2,zero,8015b44 + pevent->OSEventCnt--; /* ... decrement semaphore only if positive. */ + 8015b10: e0bff917 ldw r2,-28(fp) + 8015b14: 1080020b ldhu r2,8(r2) + 8015b18: 10bfffc4 addi r2,r2,-1 + 8015b1c: 1007883a mov r3,r2 + 8015b20: e0bff917 ldw r2,-28(fp) + 8015b24: 10c0020d sth r3,8(r2) + 8015b28: e0bfff17 ldw r2,-4(fp) + 8015b2c: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context); + 8015b30: e0bffd17 ldw r2,-12(fp) + 8015b34: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 8015b38: e0bff717 ldw r2,-36(fp) + 8015b3c: 10000005 stb zero,0(r2) + return; + 8015b40: 00003b06 br 8015c30 + } + /* Otherwise, must wait until event occurs */ + OSTCBCur->OSTCBStat |= OS_STAT_SEM; /* Resource not available, pend on semaphore */ + 8015b44: d0a05817 ldw r2,-32416(gp) + 8015b48: 10c00c03 ldbu r3,48(r2) + 8015b4c: d0a05817 ldw r2,-32416(gp) + 8015b50: 18c00054 ori r3,r3,1 + 8015b54: 10c00c05 stb r3,48(r2) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + 8015b58: d0a05817 ldw r2,-32416(gp) + 8015b5c: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBDly = timeout; /* Store pend timeout in TCB */ + 8015b60: d0a05817 ldw r2,-32416(gp) + 8015b64: e0fff80b ldhu r3,-32(fp) + 8015b68: 10c00b8d sth r3,46(r2) + OS_EventTaskWait(pevent); /* Suspend task until event or timeout occurs */ + 8015b6c: e13ff917 ldw r4,-28(fp) + 8015b70: 8010e600 call 8010e60 + 8015b74: e0bfff17 ldw r2,-4(fp) + 8015b78: e0bffb15 stw r2,-20(fp) + 8015b7c: e0bffb17 ldw r2,-20(fp) + 8015b80: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next highest priority task ready */ + 8015b84: 801166c0 call 801166c + NIOS2_READ_STATUS (context); + 8015b88: 0005303a rdctl r2,status + 8015b8c: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8015b90: e0fffc17 ldw r3,-16(fp) + 8015b94: 00bfff84 movi r2,-2 + 8015b98: 1884703a and r2,r3,r2 + 8015b9c: 1001703a wrctl status,r2 + return context; + 8015ba0: e0bffc17 ldw r2,-16(fp) + OS_ENTER_CRITICAL(); + 8015ba4: e0bfff15 stw r2,-4(fp) + switch (OSTCBCur->OSTCBStatPend) { /* See if we timed-out or aborted */ + 8015ba8: d0a05817 ldw r2,-32416(gp) + 8015bac: 10800c43 ldbu r2,49(r2) + 8015bb0: 10803fcc andi r2,r2,255 + 8015bb4: 10000326 beq r2,zero,8015bc4 + 8015bb8: 108000a0 cmpeqi r2,r2,2 + 8015bbc: 1000041e bne r2,zero,8015bd0 + 8015bc0: 00000706 br 8015be0 + case OS_STAT_PEND_OK: + *perr = OS_ERR_NONE; + 8015bc4: e0bff717 ldw r2,-36(fp) + 8015bc8: 10000005 stb zero,0(r2) + break; + 8015bcc: 00000c06 br 8015c00 + + case OS_STAT_PEND_ABORT: + *perr = OS_ERR_PEND_ABORT; /* Indicate that we aborted */ + 8015bd0: e0bff717 ldw r2,-36(fp) + 8015bd4: 00c00384 movi r3,14 + 8015bd8: 10c00005 stb r3,0(r2) + break; + 8015bdc: 00000806 br 8015c00 + + case OS_STAT_PEND_TO: + default: + OS_EventTaskRemove(OSTCBCur, pevent); + 8015be0: d0a05817 ldw r2,-32416(gp) + 8015be4: e17ff917 ldw r5,-28(fp) + 8015be8: 1009883a mov r4,r2 + 8015bec: 80110b00 call 80110b0 + *perr = OS_ERR_TIMEOUT; /* Indicate that we didn't get event within TO */ + 8015bf0: e0bff717 ldw r2,-36(fp) + 8015bf4: 00c00284 movi r3,10 + 8015bf8: 10c00005 stb r3,0(r2) + break; + 8015bfc: 0001883a nop + } + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Set task status to ready */ + 8015c00: d0a05817 ldw r2,-32416(gp) + 8015c04: 10000c05 stb zero,48(r2) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + 8015c08: d0a05817 ldw r2,-32416(gp) + 8015c0c: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; /* Clear event pointers */ + 8015c10: d0a05817 ldw r2,-32416(gp) + 8015c14: 10000715 stw zero,28(r2) +#if (OS_EVENT_MULTI_EN > 0) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0; + 8015c18: d0a05817 ldw r2,-32416(gp) + 8015c1c: 10000815 stw zero,32(r2) + 8015c20: e0bfff17 ldw r2,-4(fp) + 8015c24: e0bffa15 stw r2,-24(fp) + NIOS2_WRITE_STATUS (context); + 8015c28: e0bffa17 ldw r2,-24(fp) + 8015c2c: 1001703a wrctl status,r2 +#endif + OS_EXIT_CRITICAL(); +} + 8015c30: e037883a mov sp,fp + 8015c34: dfc00117 ldw ra,4(sp) + 8015c38: df000017 ldw fp,0(sp) + 8015c3c: dec00204 addi sp,sp,8 + 8015c40: f800283a ret + +08015c44 : +********************************************************************************************************* +*/ + +#if OS_SEM_PEND_ABORT_EN > 0 +INT8U OSSemPendAbort (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + 8015c44: defff604 addi sp,sp,-40 + 8015c48: dfc00915 stw ra,36(sp) + 8015c4c: df000815 stw fp,32(sp) + 8015c50: df000804 addi fp,sp,32 + 8015c54: e13ffa15 stw r4,-24(fp) + 8015c58: 2805883a mov r2,r5 + 8015c5c: e1bff815 stw r6,-32(fp) + 8015c60: e0bff905 stb r2,-28(fp) + INT8U nbr_tasks; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8015c64: e03ffe15 stw zero,-8(fp) + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return (0); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 8015c68: e0bffa17 ldw r2,-24(fp) + 8015c6c: 10800003 ldbu r2,0(r2) + 8015c70: 10803fcc andi r2,r2,255 + 8015c74: 108000e0 cmpeqi r2,r2,3 + 8015c78: 1000051e bne r2,zero,8015c90 + *perr = OS_ERR_EVENT_TYPE; + 8015c7c: e0bff817 ldw r2,-32(fp) + 8015c80: 00c00044 movi r3,1 + 8015c84: 10c00005 stb r3,0(r2) + return (0); + 8015c88: 0005883a mov r2,zero + 8015c8c: 00003806 br 8015d70 + NIOS2_READ_STATUS (context); + 8015c90: 0005303a rdctl r2,status + 8015c94: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8015c98: e0fffd17 ldw r3,-12(fp) + 8015c9c: 00bfff84 movi r2,-2 + 8015ca0: 1884703a and r2,r3,r2 + 8015ca4: 1001703a wrctl status,r2 + return context; + 8015ca8: e0bffd17 ldw r2,-12(fp) + } + OS_ENTER_CRITICAL(); + 8015cac: e0bffe15 stw r2,-8(fp) + if (pevent->OSEventGrp != 0) { /* See if any task waiting on semaphore? */ + 8015cb0: e0bffa17 ldw r2,-24(fp) + 8015cb4: 10800283 ldbu r2,10(r2) + 8015cb8: 10803fcc andi r2,r2,255 + 8015cbc: 10002526 beq r2,zero,8015d54 + nbr_tasks = 0; + 8015cc0: e03fffc5 stb zero,-1(fp) + switch (opt) { + 8015cc4: e0bff903 ldbu r2,-28(fp) + 8015cc8: 10800058 cmpnei r2,r2,1 + 8015ccc: 10000e1e bne r2,zero,8015d08 + case OS_PEND_OPT_BROADCAST: /* Do we need to abort ALL waiting tasks? */ + while (pevent->OSEventGrp != 0) { /* Yes, ready ALL tasks waiting on semaphore */ + 8015cd0: 00000806 br 8015cf4 + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_ABORT); + 8015cd4: 01c00084 movi r7,2 + 8015cd8: 01800044 movi r6,1 + 8015cdc: 000b883a mov r5,zero + 8015ce0: e13ffa17 ldw r4,-24(fp) + 8015ce4: 8010cd80 call 8010cd8 + nbr_tasks++; + 8015ce8: e0bfffc3 ldbu r2,-1(fp) + 8015cec: 10800044 addi r2,r2,1 + 8015cf0: e0bfffc5 stb r2,-1(fp) + while (pevent->OSEventGrp != 0) { /* Yes, ready ALL tasks waiting on semaphore */ + 8015cf4: e0bffa17 ldw r2,-24(fp) + 8015cf8: 10800283 ldbu r2,10(r2) + 8015cfc: 10803fcc andi r2,r2,255 + 8015d00: 103ff41e bne r2,zero,8015cd4 + } + break; + 8015d04: 00000906 br 8015d2c + + case OS_PEND_OPT_NONE: + default: /* No, ready HPT waiting on semaphore */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_ABORT); + 8015d08: 01c00084 movi r7,2 + 8015d0c: 01800044 movi r6,1 + 8015d10: 000b883a mov r5,zero + 8015d14: e13ffa17 ldw r4,-24(fp) + 8015d18: 8010cd80 call 8010cd8 + nbr_tasks++; + 8015d1c: e0bfffc3 ldbu r2,-1(fp) + 8015d20: 10800044 addi r2,r2,1 + 8015d24: e0bfffc5 stb r2,-1(fp) + break; + 8015d28: 0001883a nop + 8015d2c: e0bffe17 ldw r2,-8(fp) + 8015d30: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 8015d34: e0bffc17 ldw r2,-16(fp) + 8015d38: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find HPT ready to run */ + 8015d3c: 801166c0 call 801166c + *perr = OS_ERR_PEND_ABORT; + 8015d40: e0bff817 ldw r2,-32(fp) + 8015d44: 00c00384 movi r3,14 + 8015d48: 10c00005 stb r3,0(r2) + return (nbr_tasks); + 8015d4c: e0bfffc3 ldbu r2,-1(fp) + 8015d50: 00000706 br 8015d70 + 8015d54: e0bffe17 ldw r2,-8(fp) + 8015d58: e0bffb15 stw r2,-20(fp) + 8015d5c: e0bffb17 ldw r2,-20(fp) + 8015d60: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 8015d64: e0bff817 ldw r2,-32(fp) + 8015d68: 10000005 stb zero,0(r2) + return (0); /* No tasks waiting on semaphore */ + 8015d6c: 0005883a mov r2,zero +} + 8015d70: e037883a mov sp,fp + 8015d74: dfc00117 ldw ra,4(sp) + 8015d78: df000017 ldw fp,0(sp) + 8015d7c: dec00204 addi sp,sp,8 + 8015d80: f800283a ret + +08015d84 : +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +********************************************************************************************************* +*/ + +INT8U OSSemPost (OS_EVENT *pevent) +{ + 8015d84: defff804 addi sp,sp,-32 + 8015d88: dfc00715 stw ra,28(sp) + 8015d8c: df000615 stw fp,24(sp) + 8015d90: df000604 addi fp,sp,24 + 8015d94: e13ffa15 stw r4,-24(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8015d98: e03fff15 stw zero,-4(fp) +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 8015d9c: e0bffa17 ldw r2,-24(fp) + 8015da0: 10800003 ldbu r2,0(r2) + 8015da4: 10803fcc andi r2,r2,255 + 8015da8: 108000e0 cmpeqi r2,r2,3 + 8015dac: 1000021e bne r2,zero,8015db8 + return (OS_ERR_EVENT_TYPE); + 8015db0: 00800044 movi r2,1 + 8015db4: 00002e06 br 8015e70 + NIOS2_READ_STATUS (context); + 8015db8: 0005303a rdctl r2,status + 8015dbc: e0bffe15 stw r2,-8(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8015dc0: e0fffe17 ldw r3,-8(fp) + 8015dc4: 00bfff84 movi r2,-2 + 8015dc8: 1884703a and r2,r3,r2 + 8015dcc: 1001703a wrctl status,r2 + return context; + 8015dd0: e0bffe17 ldw r2,-8(fp) + } + OS_ENTER_CRITICAL(); + 8015dd4: e0bfff15 stw r2,-4(fp) + if (pevent->OSEventGrp != 0) { /* See if any task waiting for semaphore */ + 8015dd8: e0bffa17 ldw r2,-24(fp) + 8015ddc: 10800283 ldbu r2,10(r2) + 8015de0: 10803fcc andi r2,r2,255 + 8015de4: 10000c26 beq r2,zero,8015e18 + /* Ready HPT waiting on event */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_OK); + 8015de8: 000f883a mov r7,zero + 8015dec: 01800044 movi r6,1 + 8015df0: 000b883a mov r5,zero + 8015df4: e13ffa17 ldw r4,-24(fp) + 8015df8: 8010cd80 call 8010cd8 + 8015dfc: e0bfff17 ldw r2,-4(fp) + 8015e00: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context); + 8015e04: e0bffd17 ldw r2,-12(fp) + 8015e08: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find HPT ready to run */ + 8015e0c: 801166c0 call 801166c + return (OS_ERR_NONE); + 8015e10: 0005883a mov r2,zero + 8015e14: 00001606 br 8015e70 + } + if (pevent->OSEventCnt < 65535u) { /* Make sure semaphore will not overflow */ + 8015e18: e0bffa17 ldw r2,-24(fp) + 8015e1c: 1080020b ldhu r2,8(r2) + 8015e20: 10ffffcc andi r3,r2,65535 + 8015e24: 00bfffd4 movui r2,65535 + 8015e28: 18800c26 beq r3,r2,8015e5c + pevent->OSEventCnt++; /* Increment semaphore count to register event */ + 8015e2c: e0bffa17 ldw r2,-24(fp) + 8015e30: 1080020b ldhu r2,8(r2) + 8015e34: 10800044 addi r2,r2,1 + 8015e38: 1007883a mov r3,r2 + 8015e3c: e0bffa17 ldw r2,-24(fp) + 8015e40: 10c0020d sth r3,8(r2) + 8015e44: e0bfff17 ldw r2,-4(fp) + 8015e48: e0bffc15 stw r2,-16(fp) + 8015e4c: e0bffc17 ldw r2,-16(fp) + 8015e50: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 8015e54: 0005883a mov r2,zero + 8015e58: 00000506 br 8015e70 + 8015e5c: e0bfff17 ldw r2,-4(fp) + 8015e60: e0bffb15 stw r2,-20(fp) + 8015e64: e0bffb17 ldw r2,-20(fp) + 8015e68: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); /* Semaphore value has reached its maximum */ + return (OS_ERR_SEM_OVF); + 8015e6c: 00800c84 movi r2,50 +} + 8015e70: e037883a mov sp,fp + 8015e74: dfc00117 ldw ra,4(sp) + 8015e78: df000017 ldw fp,0(sp) + 8015e7c: dec00204 addi sp,sp,8 + 8015e80: f800283a ret + +08015e84 : +********************************************************************************************************* +*/ + +#if OS_SEM_QUERY_EN > 0 +INT8U OSSemQuery (OS_EVENT *pevent, OS_SEM_DATA *p_sem_data) +{ + 8015e84: defff704 addi sp,sp,-36 + 8015e88: df000815 stw fp,32(sp) + 8015e8c: df000804 addi fp,sp,32 + 8015e90: e13ff915 stw r4,-28(fp) + 8015e94: e17ff815 stw r5,-32(fp) + INT16U *psrc; + INT16U *pdest; +#endif + INT8U i; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8015e98: e03ffc15 stw zero,-16(fp) + } + if (p_sem_data == (OS_SEM_DATA *)0) { /* Validate 'p_sem_data' */ + return (OS_ERR_PDATA_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 8015e9c: e0bff917 ldw r2,-28(fp) + 8015ea0: 10800003 ldbu r2,0(r2) + 8015ea4: 10803fcc andi r2,r2,255 + 8015ea8: 108000e0 cmpeqi r2,r2,3 + 8015eac: 1000021e bne r2,zero,8015eb8 + return (OS_ERR_EVENT_TYPE); + 8015eb0: 00800044 movi r2,1 + 8015eb4: 00002b06 br 8015f64 + NIOS2_READ_STATUS (context); + 8015eb8: 0005303a rdctl r2,status + 8015ebc: e0bffb15 stw r2,-20(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8015ec0: e0fffb17 ldw r3,-20(fp) + 8015ec4: 00bfff84 movi r2,-2 + 8015ec8: 1884703a and r2,r3,r2 + 8015ecc: 1001703a wrctl status,r2 + return context; + 8015ed0: e0bffb17 ldw r2,-20(fp) + } + OS_ENTER_CRITICAL(); + 8015ed4: e0bffc15 stw r2,-16(fp) + p_sem_data->OSEventGrp = pevent->OSEventGrp; /* Copy message mailbox wait list */ + 8015ed8: e0bff917 ldw r2,-28(fp) + 8015edc: 10c00283 ldbu r3,10(r2) + 8015ee0: e0bff817 ldw r2,-32(fp) + 8015ee4: 10c00145 stb r3,5(r2) + psrc = &pevent->OSEventTbl[0]; + 8015ee8: e0bff917 ldw r2,-28(fp) + 8015eec: 108002c4 addi r2,r2,11 + 8015ef0: e0bfff15 stw r2,-4(fp) + pdest = &p_sem_data->OSEventTbl[0]; + 8015ef4: e0bff817 ldw r2,-32(fp) + 8015ef8: 10800084 addi r2,r2,2 + 8015efc: e0bffe15 stw r2,-8(fp) + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 8015f00: e03ffdc5 stb zero,-9(fp) + 8015f04: 00000b06 br 8015f34 + *pdest++ = *psrc++; + 8015f08: e0ffff17 ldw r3,-4(fp) + 8015f0c: 18800044 addi r2,r3,1 + 8015f10: e0bfff15 stw r2,-4(fp) + 8015f14: e0bffe17 ldw r2,-8(fp) + 8015f18: 11000044 addi r4,r2,1 + 8015f1c: e13ffe15 stw r4,-8(fp) + 8015f20: 18c00003 ldbu r3,0(r3) + 8015f24: 10c00005 stb r3,0(r2) + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 8015f28: e0bffdc3 ldbu r2,-9(fp) + 8015f2c: 10800044 addi r2,r2,1 + 8015f30: e0bffdc5 stb r2,-9(fp) + 8015f34: e0bffdc3 ldbu r2,-9(fp) + 8015f38: 108000f0 cmpltui r2,r2,3 + 8015f3c: 103ff21e bne r2,zero,8015f08 + } + p_sem_data->OSCnt = pevent->OSEventCnt; /* Get semaphore count */ + 8015f40: e0bff917 ldw r2,-28(fp) + 8015f44: 10c0020b ldhu r3,8(r2) + 8015f48: e0bff817 ldw r2,-32(fp) + 8015f4c: 10c0000d sth r3,0(r2) + 8015f50: e0bffc17 ldw r2,-16(fp) + 8015f54: e0bffa15 stw r2,-24(fp) + NIOS2_WRITE_STATUS (context); + 8015f58: e0bffa17 ldw r2,-24(fp) + 8015f5c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 8015f60: 0005883a mov r2,zero +} + 8015f64: e037883a mov sp,fp + 8015f68: df000017 ldw fp,0(sp) + 8015f6c: dec00104 addi sp,sp,4 + 8015f70: f800283a ret + +08015f74 : +********************************************************************************************************* +*/ + +#if OS_SEM_SET_EN > 0 +void OSSemSet (OS_EVENT *pevent, INT16U cnt, INT8U *perr) +{ + 8015f74: defff904 addi sp,sp,-28 + 8015f78: df000615 stw fp,24(sp) + 8015f7c: df000604 addi fp,sp,24 + 8015f80: e13ffc15 stw r4,-16(fp) + 8015f84: 2805883a mov r2,r5 + 8015f88: e1bffa15 stw r6,-24(fp) + 8015f8c: e0bffb0d sth r2,-20(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8015f90: e03fff15 stw zero,-4(fp) + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return; + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 8015f94: e0bffc17 ldw r2,-16(fp) + 8015f98: 10800003 ldbu r2,0(r2) + 8015f9c: 10803fcc andi r2,r2,255 + 8015fa0: 108000e0 cmpeqi r2,r2,3 + 8015fa4: 1000041e bne r2,zero,8015fb8 + *perr = OS_ERR_EVENT_TYPE; + 8015fa8: e0bffa17 ldw r2,-24(fp) + 8015fac: 00c00044 movi r3,1 + 8015fb0: 10c00005 stb r3,0(r2) + return; + 8015fb4: 00002106 br 801603c + NIOS2_READ_STATUS (context); + 8015fb8: 0005303a rdctl r2,status + 8015fbc: e0bffe15 stw r2,-8(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8015fc0: e0fffe17 ldw r3,-8(fp) + 8015fc4: 00bfff84 movi r2,-2 + 8015fc8: 1884703a and r2,r3,r2 + 8015fcc: 1001703a wrctl status,r2 + return context; + 8015fd0: e0bffe17 ldw r2,-8(fp) + } + OS_ENTER_CRITICAL(); + 8015fd4: e0bfff15 stw r2,-4(fp) + *perr = OS_ERR_NONE; + 8015fd8: e0bffa17 ldw r2,-24(fp) + 8015fdc: 10000005 stb zero,0(r2) + if (pevent->OSEventCnt > 0) { /* See if semaphore already has a count */ + 8015fe0: e0bffc17 ldw r2,-16(fp) + 8015fe4: 1080020b ldhu r2,8(r2) + 8015fe8: 10bfffcc andi r2,r2,65535 + 8015fec: 10000426 beq r2,zero,8016000 + pevent->OSEventCnt = cnt; /* Yes, set it to the new value specified. */ + 8015ff0: e0bffc17 ldw r2,-16(fp) + 8015ff4: e0fffb0b ldhu r3,-20(fp) + 8015ff8: 10c0020d sth r3,8(r2) + 8015ffc: 00000b06 br 801602c + } else { /* No */ + if (pevent->OSEventGrp == 0) { /* See if task(s) waiting? */ + 8016000: e0bffc17 ldw r2,-16(fp) + 8016004: 10800283 ldbu r2,10(r2) + 8016008: 10803fcc andi r2,r2,255 + 801600c: 1000041e bne r2,zero,8016020 + pevent->OSEventCnt = cnt; /* No, OK to set the value */ + 8016010: e0bffc17 ldw r2,-16(fp) + 8016014: e0fffb0b ldhu r3,-20(fp) + 8016018: 10c0020d sth r3,8(r2) + 801601c: 00000306 br 801602c + } else { + *perr = OS_ERR_TASK_WAITING; + 8016020: e0bffa17 ldw r2,-24(fp) + 8016024: 00c01244 movi r3,73 + 8016028: 10c00005 stb r3,0(r2) + 801602c: e0bfff17 ldw r2,-4(fp) + 8016030: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context); + 8016034: e0bffd17 ldw r2,-12(fp) + 8016038: 1001703a wrctl status,r2 + } + } + OS_EXIT_CRITICAL(); +} + 801603c: e037883a mov sp,fp + 8016040: df000017 ldw fp,0(sp) + 8016044: dec00104 addi sp,sp,4 + 8016048: f800283a ret + +0801604c : +********************************************************************************************************* +*/ + +#if OS_TASK_CHANGE_PRIO_EN > 0 +INT8U OSTaskChangePrio (INT8U oldprio, INT8U newprio) +{ + 801604c: defff104 addi sp,sp,-60 + 8016050: dfc00e15 stw ra,56(sp) + 8016054: df000d15 stw fp,52(sp) + 8016058: df000d04 addi fp,sp,52 + 801605c: 2005883a mov r2,r4 + 8016060: 2807883a mov r3,r5 + 8016064: e0bff405 stb r2,-48(fp) + 8016068: 1805883a mov r2,r3 + 801606c: e0bff305 stb r2,-52(fp) + INT16U bitx_new; + INT16U bity_old; + INT16U bitx_old; +#endif +#if OS_CRITICAL_METHOD == 3 + OS_CPU_SR cpu_sr = 0; /* Storage for CPU status register */ + 8016070: e03ffd15 stw zero,-12(fp) + NIOS2_READ_STATUS (context); + 8016074: 0005303a rdctl r2,status + 8016078: e0bff915 stw r2,-28(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 801607c: e0fff917 ldw r3,-28(fp) + 8016080: 00bfff84 movi r2,-2 + 8016084: 1884703a and r2,r3,r2 + 8016088: 1001703a wrctl status,r2 + return context; + 801608c: e0bff917 ldw r2,-28(fp) + } + if (newprio >= OS_LOWEST_PRIO) { + return (OS_ERR_PRIO_INVALID); + } +#endif + OS_ENTER_CRITICAL(); + 8016090: e0bffd15 stw r2,-12(fp) + if (OSTCBPrioTbl[newprio] != (OS_TCB *)0) { /* New priority must not already exist */ + 8016094: e0bff303 ldbu r2,-52(fp) + 8016098: 100690ba slli r3,r2,2 + 801609c: 008201b4 movhi r2,2054 + 80160a0: 1885883a add r2,r3,r2 + 80160a4: 10b55d17 ldw r2,-10892(r2) + 80160a8: 10000626 beq r2,zero,80160c4 + 80160ac: e0bffd17 ldw r2,-12(fp) + 80160b0: e0bff815 stw r2,-32(fp) + NIOS2_WRITE_STATUS (context); + 80160b4: e0bff817 ldw r2,-32(fp) + 80160b8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_PRIO_EXIST); + 80160bc: 00800a04 movi r2,40 + 80160c0: 0000fd06 br 80164b8 + } + if (oldprio == OS_PRIO_SELF) { /* See if changing self */ + 80160c4: e0bff403 ldbu r2,-48(fp) + 80160c8: 10803fd8 cmpnei r2,r2,255 + 80160cc: 1000031e bne r2,zero,80160dc + oldprio = OSTCBCur->OSTCBPrio; /* Yes, get priority */ + 80160d0: d0a05817 ldw r2,-32416(gp) + 80160d4: 10800c83 ldbu r2,50(r2) + 80160d8: e0bff405 stb r2,-48(fp) + } + ptcb = OSTCBPrioTbl[oldprio]; + 80160dc: e0bff403 ldbu r2,-48(fp) + 80160e0: 100690ba slli r3,r2,2 + 80160e4: 008201b4 movhi r2,2054 + 80160e8: 1885883a add r2,r3,r2 + 80160ec: 10b55d17 ldw r2,-10892(r2) + 80160f0: e0bffc15 stw r2,-16(fp) + if (ptcb == (OS_TCB *)0) { /* Does task to change exist? */ + 80160f4: e0bffc17 ldw r2,-16(fp) + 80160f8: 1000061e bne r2,zero,8016114 + 80160fc: e0bffd17 ldw r2,-12(fp) + 8016100: e0bff715 stw r2,-36(fp) + 8016104: e0bff717 ldw r2,-36(fp) + 8016108: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* No, can't change its priority! */ + return (OS_ERR_PRIO); + 801610c: 00800a44 movi r2,41 + 8016110: 0000e906 br 80164b8 + } + if (ptcb == OS_TCB_RESERVED) { /* Is task assigned to Mutex */ + 8016114: e0bffc17 ldw r2,-16(fp) + 8016118: 10800058 cmpnei r2,r2,1 + 801611c: 1000061e bne r2,zero,8016138 + 8016120: e0bffd17 ldw r2,-12(fp) + 8016124: e0bff615 stw r2,-40(fp) + 8016128: e0bff617 ldw r2,-40(fp) + 801612c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* No, can't change its priority! */ + return (OS_ERR_TASK_NOT_EXIST); + 8016130: 008010c4 movi r2,67 + 8016134: 0000e006 br 80164b8 + } +#if OS_LOWEST_PRIO <= 63 + y_new = (INT8U)(newprio >> 3); /* Yes, compute new TCB fields */ + 8016138: e0bff303 ldbu r2,-52(fp) + 801613c: 1004d0fa srli r2,r2,3 + 8016140: e0bffbc5 stb r2,-17(fp) + x_new = (INT8U)(newprio & 0x07); + 8016144: e0bff303 ldbu r2,-52(fp) + 8016148: 108001cc andi r2,r2,7 + 801614c: e0bffb85 stb r2,-18(fp) + bity_new = (INT8U)(1 << y_new); + 8016150: e0bffbc3 ldbu r2,-17(fp) + 8016154: 00c00044 movi r3,1 + 8016158: 1884983a sll r2,r3,r2 + 801615c: e0bffb45 stb r2,-19(fp) + bitx_new = (INT8U)(1 << x_new); + 8016160: e0bffb83 ldbu r2,-18(fp) + 8016164: 00c00044 movi r3,1 + 8016168: 1884983a sll r2,r3,r2 + 801616c: e0bffb05 stb r2,-20(fp) + x_new = (INT8U)( newprio & 0x0F); + bity_new = (INT16U)(1 << y_new); + bitx_new = (INT16U)(1 << x_new); +#endif + + OSTCBPrioTbl[oldprio] = (OS_TCB *)0; /* Remove TCB from old priority */ + 8016170: e0bff403 ldbu r2,-48(fp) + 8016174: 100690ba slli r3,r2,2 + 8016178: 008201b4 movhi r2,2054 + 801617c: 1885883a add r2,r3,r2 + 8016180: 10355d15 stw zero,-10892(r2) + OSTCBPrioTbl[newprio] = ptcb; /* Place pointer to TCB @ new priority */ + 8016184: e0bff303 ldbu r2,-52(fp) + 8016188: 100890ba slli r4,r2,2 + 801618c: e0fffc17 ldw r3,-16(fp) + 8016190: 008201b4 movhi r2,2054 + 8016194: 2085883a add r2,r4,r2 + 8016198: 10f55d15 stw r3,-10892(r2) + y_old = ptcb->OSTCBY; + 801619c: e0bffc17 ldw r2,-16(fp) + 80161a0: 10800d03 ldbu r2,52(r2) + 80161a4: e0bffac5 stb r2,-21(fp) + bity_old = ptcb->OSTCBBitY; + 80161a8: e0bffc17 ldw r2,-16(fp) + 80161ac: 10800d83 ldbu r2,54(r2) + 80161b0: e0bffa85 stb r2,-22(fp) + bitx_old = ptcb->OSTCBBitX; + 80161b4: e0bffc17 ldw r2,-16(fp) + 80161b8: 10800d43 ldbu r2,53(r2) + 80161bc: e0bffa45 stb r2,-23(fp) + if ((OSRdyTbl[y_old] & bitx_old) != 0) { /* If task is ready make it not */ + 80161c0: e0fffac3 ldbu r3,-21(fp) + 80161c4: d0a05544 addi r2,gp,-32427 + 80161c8: 1885883a add r2,r3,r2 + 80161cc: 10800003 ldbu r2,0(r2) + 80161d0: e0fffa43 ldbu r3,-23(fp) + 80161d4: 1884703a and r2,r3,r2 + 80161d8: 10803fcc andi r2,r2,255 + 80161dc: 10002826 beq r2,zero,8016280 + OSRdyTbl[y_old] &= ~bitx_old; + 80161e0: e0fffac3 ldbu r3,-21(fp) + 80161e4: d0a05544 addi r2,gp,-32427 + 80161e8: 1885883a add r2,r3,r2 + 80161ec: 10800003 ldbu r2,0(r2) + 80161f0: 1007883a mov r3,r2 + 80161f4: e0bffa43 ldbu r2,-23(fp) + 80161f8: 0084303a nor r2,zero,r2 + 80161fc: 1884703a and r2,r3,r2 + 8016200: e0fffac3 ldbu r3,-21(fp) + 8016204: 1009883a mov r4,r2 + 8016208: d0a05544 addi r2,gp,-32427 + 801620c: 1885883a add r2,r3,r2 + 8016210: 11000005 stb r4,0(r2) + if (OSRdyTbl[y_old] == 0) { + 8016214: e0fffac3 ldbu r3,-21(fp) + 8016218: d0a05544 addi r2,gp,-32427 + 801621c: 1885883a add r2,r3,r2 + 8016220: 10800003 ldbu r2,0(r2) + 8016224: 10803fcc andi r2,r2,255 + 8016228: 1000061e bne r2,zero,8016244 + OSRdyGrp &= ~bity_old; + 801622c: e0bffa83 ldbu r2,-22(fp) + 8016230: 0084303a nor r2,zero,r2 + 8016234: 1007883a mov r3,r2 + 8016238: d0a05503 ldbu r2,-32428(gp) + 801623c: 1884703a and r2,r3,r2 + 8016240: d0a05505 stb r2,-32428(gp) + } + OSRdyGrp |= bity_new; /* Make new priority ready to run */ + 8016244: d0a05503 ldbu r2,-32428(gp) + 8016248: e0fffb43 ldbu r3,-19(fp) + 801624c: 1884b03a or r2,r3,r2 + 8016250: d0a05505 stb r2,-32428(gp) + OSRdyTbl[y_new] |= bitx_new; + 8016254: e0fffbc3 ldbu r3,-17(fp) + 8016258: d0a05544 addi r2,gp,-32427 + 801625c: 1885883a add r2,r3,r2 + 8016260: 10800003 ldbu r2,0(r2) + 8016264: e0fffbc3 ldbu r3,-17(fp) + 8016268: e13ffb03 ldbu r4,-20(fp) + 801626c: 2084b03a or r2,r4,r2 + 8016270: 1009883a mov r4,r2 + 8016274: d0a05544 addi r2,gp,-32427 + 8016278: 1885883a add r2,r3,r2 + 801627c: 11000005 stb r4,0(r2) + } + +#if (OS_EVENT_EN) + pevent = ptcb->OSTCBEventPtr; + 8016280: e0bffc17 ldw r2,-16(fp) + 8016284: 10800717 ldw r2,28(r2) + 8016288: e0bfff15 stw r2,-4(fp) + if (pevent != (OS_EVENT *)0) { + 801628c: e0bfff17 ldw r2,-4(fp) + 8016290: 10002f26 beq r2,zero,8016350 + pevent->OSEventTbl[y_old] &= ~bitx_old; /* Remove old task prio from wait list */ + 8016294: e0bffac3 ldbu r2,-21(fp) + 8016298: e0ffff17 ldw r3,-4(fp) + 801629c: 1885883a add r2,r3,r2 + 80162a0: 108002c3 ldbu r2,11(r2) + 80162a4: 1007883a mov r3,r2 + 80162a8: e0bffa43 ldbu r2,-23(fp) + 80162ac: 0084303a nor r2,zero,r2 + 80162b0: 1884703a and r2,r3,r2 + 80162b4: 1007883a mov r3,r2 + 80162b8: e0bffac3 ldbu r2,-21(fp) + 80162bc: 1809883a mov r4,r3 + 80162c0: e0ffff17 ldw r3,-4(fp) + 80162c4: 1885883a add r2,r3,r2 + 80162c8: 110002c5 stb r4,11(r2) + if (pevent->OSEventTbl[y_old] == 0) { + 80162cc: e0bffac3 ldbu r2,-21(fp) + 80162d0: e0ffff17 ldw r3,-4(fp) + 80162d4: 1885883a add r2,r3,r2 + 80162d8: 108002c3 ldbu r2,11(r2) + 80162dc: 10803fcc andi r2,r2,255 + 80162e0: 1000091e bne r2,zero,8016308 + pevent->OSEventGrp &= ~bity_old; + 80162e4: e0bfff17 ldw r2,-4(fp) + 80162e8: 10800283 ldbu r2,10(r2) + 80162ec: 1007883a mov r3,r2 + 80162f0: e0bffa83 ldbu r2,-22(fp) + 80162f4: 0084303a nor r2,zero,r2 + 80162f8: 1884703a and r2,r3,r2 + 80162fc: 1007883a mov r3,r2 + 8016300: e0bfff17 ldw r2,-4(fp) + 8016304: 10c00285 stb r3,10(r2) + } + pevent->OSEventGrp |= bity_new; /* Add new task prio to wait list */ + 8016308: e0bfff17 ldw r2,-4(fp) + 801630c: 10800283 ldbu r2,10(r2) + 8016310: e0fffb43 ldbu r3,-19(fp) + 8016314: 1884b03a or r2,r3,r2 + 8016318: 1007883a mov r3,r2 + 801631c: e0bfff17 ldw r2,-4(fp) + 8016320: 10c00285 stb r3,10(r2) + pevent->OSEventTbl[y_new] |= bitx_new; + 8016324: e0bffbc3 ldbu r2,-17(fp) + 8016328: e0ffff17 ldw r3,-4(fp) + 801632c: 1885883a add r2,r3,r2 + 8016330: 10c002c3 ldbu r3,11(r2) + 8016334: e0bffbc3 ldbu r2,-17(fp) + 8016338: e13ffb03 ldbu r4,-20(fp) + 801633c: 20c6b03a or r3,r4,r3 + 8016340: 1809883a mov r4,r3 + 8016344: e0ffff17 ldw r3,-4(fp) + 8016348: 1885883a add r2,r3,r2 + 801634c: 110002c5 stb r4,11(r2) + } +#if (OS_EVENT_MULTI_EN > 0) + if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) { + 8016350: e0bffc17 ldw r2,-16(fp) + 8016354: 10800817 ldw r2,32(r2) + 8016358: 10003e26 beq r2,zero,8016454 + pevents = ptcb->OSTCBEventMultiPtr; + 801635c: e0bffc17 ldw r2,-16(fp) + 8016360: 10800817 ldw r2,32(r2) + 8016364: e0bffe15 stw r2,-8(fp) + pevent = *pevents; + 8016368: e0bffe17 ldw r2,-8(fp) + 801636c: 10800017 ldw r2,0(r2) + 8016370: e0bfff15 stw r2,-4(fp) + while (pevent != (OS_EVENT *)0) { + 8016374: 00003506 br 801644c + pevent->OSEventTbl[y_old] &= ~bitx_old; /* Remove old task prio from wait lists */ + 8016378: e0bffac3 ldbu r2,-21(fp) + 801637c: e0ffff17 ldw r3,-4(fp) + 8016380: 1885883a add r2,r3,r2 + 8016384: 108002c3 ldbu r2,11(r2) + 8016388: 1007883a mov r3,r2 + 801638c: e0bffa43 ldbu r2,-23(fp) + 8016390: 0084303a nor r2,zero,r2 + 8016394: 1884703a and r2,r3,r2 + 8016398: 1007883a mov r3,r2 + 801639c: e0bffac3 ldbu r2,-21(fp) + 80163a0: 1809883a mov r4,r3 + 80163a4: e0ffff17 ldw r3,-4(fp) + 80163a8: 1885883a add r2,r3,r2 + 80163ac: 110002c5 stb r4,11(r2) + if (pevent->OSEventTbl[y_old] == 0) { + 80163b0: e0bffac3 ldbu r2,-21(fp) + 80163b4: e0ffff17 ldw r3,-4(fp) + 80163b8: 1885883a add r2,r3,r2 + 80163bc: 108002c3 ldbu r2,11(r2) + 80163c0: 10803fcc andi r2,r2,255 + 80163c4: 1000091e bne r2,zero,80163ec + pevent->OSEventGrp &= ~bity_old; + 80163c8: e0bfff17 ldw r2,-4(fp) + 80163cc: 10800283 ldbu r2,10(r2) + 80163d0: 1007883a mov r3,r2 + 80163d4: e0bffa83 ldbu r2,-22(fp) + 80163d8: 0084303a nor r2,zero,r2 + 80163dc: 1884703a and r2,r3,r2 + 80163e0: 1007883a mov r3,r2 + 80163e4: e0bfff17 ldw r2,-4(fp) + 80163e8: 10c00285 stb r3,10(r2) + } + pevent->OSEventGrp |= bity_new; /* Add new task prio to wait lists */ + 80163ec: e0bfff17 ldw r2,-4(fp) + 80163f0: 10800283 ldbu r2,10(r2) + 80163f4: e0fffb43 ldbu r3,-19(fp) + 80163f8: 1884b03a or r2,r3,r2 + 80163fc: 1007883a mov r3,r2 + 8016400: e0bfff17 ldw r2,-4(fp) + 8016404: 10c00285 stb r3,10(r2) + pevent->OSEventTbl[y_new] |= bitx_new; + 8016408: e0bffbc3 ldbu r2,-17(fp) + 801640c: e0ffff17 ldw r3,-4(fp) + 8016410: 1885883a add r2,r3,r2 + 8016414: 10c002c3 ldbu r3,11(r2) + 8016418: e0bffbc3 ldbu r2,-17(fp) + 801641c: e13ffb03 ldbu r4,-20(fp) + 8016420: 20c6b03a or r3,r4,r3 + 8016424: 1809883a mov r4,r3 + 8016428: e0ffff17 ldw r3,-4(fp) + 801642c: 1885883a add r2,r3,r2 + 8016430: 110002c5 stb r4,11(r2) + pevents++; + 8016434: e0bffe17 ldw r2,-8(fp) + 8016438: 10800104 addi r2,r2,4 + 801643c: e0bffe15 stw r2,-8(fp) + pevent = *pevents; + 8016440: e0bffe17 ldw r2,-8(fp) + 8016444: 10800017 ldw r2,0(r2) + 8016448: e0bfff15 stw r2,-4(fp) + while (pevent != (OS_EVENT *)0) { + 801644c: e0bfff17 ldw r2,-4(fp) + 8016450: 103fc91e bne r2,zero,8016378 + } + } +#endif +#endif + + ptcb->OSTCBPrio = newprio; /* Set new task priority */ + 8016454: e0bffc17 ldw r2,-16(fp) + 8016458: e0fff303 ldbu r3,-52(fp) + 801645c: 10c00c85 stb r3,50(r2) + ptcb->OSTCBY = y_new; + 8016460: e0bffc17 ldw r2,-16(fp) + 8016464: e0fffbc3 ldbu r3,-17(fp) + 8016468: 10c00d05 stb r3,52(r2) + ptcb->OSTCBX = x_new; + 801646c: e0bffc17 ldw r2,-16(fp) + 8016470: e0fffb83 ldbu r3,-18(fp) + 8016474: 10c00cc5 stb r3,51(r2) + ptcb->OSTCBBitY = bity_new; + 8016478: e0bffc17 ldw r2,-16(fp) + 801647c: e0fffb43 ldbu r3,-19(fp) + 8016480: 10c00d85 stb r3,54(r2) + ptcb->OSTCBBitX = bitx_new; + 8016484: e0bffc17 ldw r2,-16(fp) + 8016488: e0fffb03 ldbu r3,-20(fp) + 801648c: 10c00d45 stb r3,53(r2) + 8016490: e0bffd17 ldw r2,-12(fp) + 8016494: e0bff515 stw r2,-44(fp) + 8016498: e0bff517 ldw r2,-44(fp) + 801649c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (OSRunning == OS_TRUE) { + 80164a0: d0a04b43 ldbu r2,-32467(gp) + 80164a4: 10803fcc andi r2,r2,255 + 80164a8: 10800058 cmpnei r2,r2,1 + 80164ac: 1000011e bne r2,zero,80164b4 + OS_Sched(); /* Find new highest priority task */ + 80164b0: 801166c0 call 801166c + } + return (OS_ERR_NONE); + 80164b4: 0005883a mov r2,zero +} + 80164b8: e037883a mov sp,fp + 80164bc: dfc00117 ldw ra,4(sp) + 80164c0: df000017 ldw fp,0(sp) + 80164c4: dec00204 addi sp,sp,8 + 80164c8: f800283a ret + +080164cc : +********************************************************************************************************* +*/ + +#if OS_TASK_CREATE_EN > 0 +INT8U OSTaskCreate (void (*task)(void *p_arg), void *p_arg, OS_STK *ptos, INT8U prio) +{ + 80164cc: deffee04 addi sp,sp,-72 + 80164d0: dfc01115 stw ra,68(sp) + 80164d4: df001015 stw fp,64(sp) + 80164d8: df001004 addi fp,sp,64 + 80164dc: e13ff615 stw r4,-40(fp) + 80164e0: e17ff515 stw r5,-44(fp) + 80164e4: e1bff415 stw r6,-48(fp) + 80164e8: 3805883a mov r2,r7 + 80164ec: e0bff305 stb r2,-52(fp) + OS_STK *psp; + INT8U err; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 80164f0: e03fff15 stw zero,-4(fp) + NIOS2_READ_STATUS (context); + 80164f4: 0005303a rdctl r2,status + 80164f8: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 80164fc: e0fffc17 ldw r3,-16(fp) + 8016500: 00bfff84 movi r2,-2 + 8016504: 1884703a and r2,r3,r2 + 8016508: 1001703a wrctl status,r2 + return context; + 801650c: e0bffc17 ldw r2,-16(fp) +#if OS_ARG_CHK_EN > 0 + if (prio > OS_LOWEST_PRIO) { /* Make sure priority is within allowable range */ + return (OS_ERR_PRIO_INVALID); + } +#endif + OS_ENTER_CRITICAL(); + 8016510: e0bfff15 stw r2,-4(fp) + if (OSIntNesting > 0) { /* Make sure we don't create the task from within an ISR */ + 8016514: d0a05703 ldbu r2,-32420(gp) + 8016518: 10803fcc andi r2,r2,255 + 801651c: 10000626 beq r2,zero,8016538 + 8016520: e0bfff17 ldw r2,-4(fp) + 8016524: e0bffb15 stw r2,-20(fp) + NIOS2_WRITE_STATUS (context); + 8016528: e0bffb17 ldw r2,-20(fp) + 801652c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_CREATE_ISR); + 8016530: 00800f04 movi r2,60 + 8016534: 00004006 br 8016638 + } + if (OSTCBPrioTbl[prio] == (OS_TCB *)0) { /* Make sure task doesn't already exist at this priority */ + 8016538: e0bff303 ldbu r2,-52(fp) + 801653c: 100690ba slli r3,r2,2 + 8016540: 008201b4 movhi r2,2054 + 8016544: 1885883a add r2,r3,r2 + 8016548: 10b55d17 ldw r2,-10892(r2) + 801654c: 1000351e bne r2,zero,8016624 + OSTCBPrioTbl[prio] = OS_TCB_RESERVED;/* Reserve the priority to prevent others from doing ... */ + 8016550: e0bff303 ldbu r2,-52(fp) + 8016554: 100890ba slli r4,r2,2 + 8016558: 00c00044 movi r3,1 + 801655c: 008201b4 movhi r2,2054 + 8016560: 2085883a add r2,r4,r2 + 8016564: 10f55d15 stw r3,-10892(r2) + 8016568: e0bfff17 ldw r2,-4(fp) + 801656c: e0bffa15 stw r2,-24(fp) + 8016570: e0bffa17 ldw r2,-24(fp) + 8016574: 1001703a wrctl status,r2 + /* ... the same thing until task is created. */ + OS_EXIT_CRITICAL(); + psp = OSTaskStkInit(task, p_arg, ptos, 0); /* Initialize the task's stack */ + 8016578: 000f883a mov r7,zero + 801657c: e1bff417 ldw r6,-48(fp) + 8016580: e17ff517 ldw r5,-44(fp) + 8016584: e13ff617 ldw r4,-40(fp) + 8016588: 80384580 call 8038458 + 801658c: e0bffe15 stw r2,-8(fp) + err = OS_TCBInit(prio, psp, (OS_STK *)0, 0, 0, (void *)0, 0); + 8016590: e0bff303 ldbu r2,-52(fp) + 8016594: d8000215 stw zero,8(sp) + 8016598: d8000115 stw zero,4(sp) + 801659c: d8000015 stw zero,0(sp) + 80165a0: 000f883a mov r7,zero + 80165a4: 000d883a mov r6,zero + 80165a8: e17ffe17 ldw r5,-8(fp) + 80165ac: 1009883a mov r4,r2 + 80165b0: 80118c40 call 80118c4 + 80165b4: e0bffdc5 stb r2,-9(fp) + if (err == OS_ERR_NONE) { + 80165b8: e0bffdc3 ldbu r2,-9(fp) + 80165bc: 1000061e bne r2,zero,80165d8 + if (OSRunning == OS_TRUE) { /* Find highest priority task if multitasking has started */ + 80165c0: d0a04b43 ldbu r2,-32467(gp) + 80165c4: 10803fcc andi r2,r2,255 + 80165c8: 10800058 cmpnei r2,r2,1 + 80165cc: 1000131e bne r2,zero,801661c + OS_Sched(); + 80165d0: 801166c0 call 801166c + 80165d4: 00001106 br 801661c + NIOS2_READ_STATUS (context); + 80165d8: 0005303a rdctl r2,status + 80165dc: e0bff815 stw r2,-32(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 80165e0: e0fff817 ldw r3,-32(fp) + 80165e4: 00bfff84 movi r2,-2 + 80165e8: 1884703a and r2,r3,r2 + 80165ec: 1001703a wrctl status,r2 + return context; + 80165f0: e0bff817 ldw r2,-32(fp) + } + } else { + OS_ENTER_CRITICAL(); + 80165f4: e0bfff15 stw r2,-4(fp) + OSTCBPrioTbl[prio] = (OS_TCB *)0;/* Make this priority available to others */ + 80165f8: e0bff303 ldbu r2,-52(fp) + 80165fc: 100690ba slli r3,r2,2 + 8016600: 008201b4 movhi r2,2054 + 8016604: 1885883a add r2,r3,r2 + 8016608: 10355d15 stw zero,-10892(r2) + 801660c: e0bfff17 ldw r2,-4(fp) + 8016610: e0bff915 stw r2,-28(fp) + NIOS2_WRITE_STATUS (context); + 8016614: e0bff917 ldw r2,-28(fp) + 8016618: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + return (err); + 801661c: e0bffdc3 ldbu r2,-9(fp) + 8016620: 00000506 br 8016638 + 8016624: e0bfff17 ldw r2,-4(fp) + 8016628: e0bff715 stw r2,-36(fp) + 801662c: e0bff717 ldw r2,-36(fp) + 8016630: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (OS_ERR_PRIO_EXIST); + 8016634: 00800a04 movi r2,40 +} + 8016638: e037883a mov sp,fp + 801663c: dfc00117 ldw ra,4(sp) + 8016640: df000017 ldw fp,0(sp) + 8016644: dec00204 addi sp,sp,8 + 8016648: f800283a ret + +0801664c : + INT16U id, + OS_STK *pbos, + INT32U stk_size, + void *pext, + INT16U opt) +{ + 801664c: deffec04 addi sp,sp,-80 + 8016650: dfc01315 stw ra,76(sp) + 8016654: df001215 stw fp,72(sp) + 8016658: df001204 addi fp,sp,72 + 801665c: e13ff615 stw r4,-40(fp) + 8016660: e17ff515 stw r5,-44(fp) + 8016664: e1bff415 stw r6,-48(fp) + 8016668: 3809883a mov r4,r7 + 801666c: e0c00217 ldw r3,8(fp) + 8016670: e0800617 ldw r2,24(fp) + 8016674: e13ff305 stb r4,-52(fp) + 8016678: e0fff20d sth r3,-56(fp) + 801667c: e0bff10d sth r2,-60(fp) + OS_STK *psp; + INT8U err; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8016680: e03fff15 stw zero,-4(fp) + NIOS2_READ_STATUS (context); + 8016684: 0005303a rdctl r2,status + 8016688: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 801668c: e0fffc17 ldw r3,-16(fp) + 8016690: 00bfff84 movi r2,-2 + 8016694: 1884703a and r2,r3,r2 + 8016698: 1001703a wrctl status,r2 + return context; + 801669c: e0bffc17 ldw r2,-16(fp) +#if OS_ARG_CHK_EN > 0 + if (prio > OS_LOWEST_PRIO) { /* Make sure priority is within allowable range */ + return (OS_ERR_PRIO_INVALID); + } +#endif + OS_ENTER_CRITICAL(); + 80166a0: e0bfff15 stw r2,-4(fp) + if (OSIntNesting > 0) { /* Make sure we don't create the task from within an ISR */ + 80166a4: d0a05703 ldbu r2,-32420(gp) + 80166a8: 10803fcc andi r2,r2,255 + 80166ac: 10000626 beq r2,zero,80166c8 + 80166b0: e0bfff17 ldw r2,-4(fp) + 80166b4: e0bffb15 stw r2,-20(fp) + NIOS2_WRITE_STATUS (context); + 80166b8: e0bffb17 ldw r2,-20(fp) + 80166bc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_CREATE_ISR); + 80166c0: 00800f04 movi r2,60 + 80166c4: 00004506 br 80167dc + } + if (OSTCBPrioTbl[prio] == (OS_TCB *)0) { /* Make sure task doesn't already exist at this priority */ + 80166c8: e0bff303 ldbu r2,-52(fp) + 80166cc: 100690ba slli r3,r2,2 + 80166d0: 008201b4 movhi r2,2054 + 80166d4: 1885883a add r2,r3,r2 + 80166d8: 10b55d17 ldw r2,-10892(r2) + 80166dc: 10003a1e bne r2,zero,80167c8 + OSTCBPrioTbl[prio] = OS_TCB_RESERVED;/* Reserve the priority to prevent others from doing ... */ + 80166e0: e0bff303 ldbu r2,-52(fp) + 80166e4: 100890ba slli r4,r2,2 + 80166e8: 00c00044 movi r3,1 + 80166ec: 008201b4 movhi r2,2054 + 80166f0: 2085883a add r2,r4,r2 + 80166f4: 10f55d15 stw r3,-10892(r2) + 80166f8: e0bfff17 ldw r2,-4(fp) + 80166fc: e0bffa15 stw r2,-24(fp) + 8016700: e0bffa17 ldw r2,-24(fp) + 8016704: 1001703a wrctl status,r2 + +#if (OS_TASK_STAT_STK_CHK_EN > 0) + OS_TaskStkClr(pbos, stk_size, opt); /* Clear the task stack (if needed) */ +#endif + + psp = OSTaskStkInit(task, p_arg, ptos, opt); /* Initialize the task's stack */ + 8016708: e0bff10b ldhu r2,-60(fp) + 801670c: 100f883a mov r7,r2 + 8016710: e1bff417 ldw r6,-48(fp) + 8016714: e17ff517 ldw r5,-44(fp) + 8016718: e13ff617 ldw r4,-40(fp) + 801671c: 80384580 call 8038458 + 8016720: e0bffe15 stw r2,-8(fp) + err = OS_TCBInit(prio, psp, pbos, id, stk_size, pext, opt); + 8016724: e0fff303 ldbu r3,-52(fp) + 8016728: e13ff20b ldhu r4,-56(fp) + 801672c: e0bff10b ldhu r2,-60(fp) + 8016730: d8800215 stw r2,8(sp) + 8016734: e0800517 ldw r2,20(fp) + 8016738: d8800115 stw r2,4(sp) + 801673c: e0800417 ldw r2,16(fp) + 8016740: d8800015 stw r2,0(sp) + 8016744: 200f883a mov r7,r4 + 8016748: e1800317 ldw r6,12(fp) + 801674c: e17ffe17 ldw r5,-8(fp) + 8016750: 1809883a mov r4,r3 + 8016754: 80118c40 call 80118c4 + 8016758: e0bffdc5 stb r2,-9(fp) + if (err == OS_ERR_NONE) { + 801675c: e0bffdc3 ldbu r2,-9(fp) + 8016760: 1000061e bne r2,zero,801677c + if (OSRunning == OS_TRUE) { /* Find HPT if multitasking has started */ + 8016764: d0a04b43 ldbu r2,-32467(gp) + 8016768: 10803fcc andi r2,r2,255 + 801676c: 10800058 cmpnei r2,r2,1 + 8016770: 1000131e bne r2,zero,80167c0 + OS_Sched(); + 8016774: 801166c0 call 801166c + 8016778: 00001106 br 80167c0 + NIOS2_READ_STATUS (context); + 801677c: 0005303a rdctl r2,status + 8016780: e0bff815 stw r2,-32(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8016784: e0fff817 ldw r3,-32(fp) + 8016788: 00bfff84 movi r2,-2 + 801678c: 1884703a and r2,r3,r2 + 8016790: 1001703a wrctl status,r2 + return context; + 8016794: e0bff817 ldw r2,-32(fp) + } + } else { + OS_ENTER_CRITICAL(); + 8016798: e0bfff15 stw r2,-4(fp) + OSTCBPrioTbl[prio] = (OS_TCB *)0; /* Make this priority avail. to others */ + 801679c: e0bff303 ldbu r2,-52(fp) + 80167a0: 100690ba slli r3,r2,2 + 80167a4: 008201b4 movhi r2,2054 + 80167a8: 1885883a add r2,r3,r2 + 80167ac: 10355d15 stw zero,-10892(r2) + 80167b0: e0bfff17 ldw r2,-4(fp) + 80167b4: e0bff915 stw r2,-28(fp) + NIOS2_WRITE_STATUS (context); + 80167b8: e0bff917 ldw r2,-28(fp) + 80167bc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + return (err); + 80167c0: e0bffdc3 ldbu r2,-9(fp) + 80167c4: 00000506 br 80167dc + 80167c8: e0bfff17 ldw r2,-4(fp) + 80167cc: e0bff715 stw r2,-36(fp) + 80167d0: e0bff717 ldw r2,-36(fp) + 80167d4: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (OS_ERR_PRIO_EXIST); + 80167d8: 00800a04 movi r2,40 +} + 80167dc: e037883a mov sp,fp + 80167e0: dfc00117 ldw ra,4(sp) + 80167e4: df000017 ldw fp,0(sp) + 80167e8: dec00204 addi sp,sp,8 + 80167ec: f800283a ret + +080167f0 : +********************************************************************************************************* +*/ + +#if OS_TASK_DEL_EN > 0 +INT8U OSTaskDel (INT8U prio) +{ + 80167f0: defff404 addi sp,sp,-48 + 80167f4: dfc00b15 stw ra,44(sp) + 80167f8: df000a15 stw fp,40(sp) + 80167fc: df000a04 addi fp,sp,40 + 8016800: 2005883a mov r2,r4 + 8016804: e0bff605 stb r2,-40(fp) +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) + OS_FLAG_NODE *pnode; +#endif + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8016808: e03fff15 stw zero,-4(fp) +#endif + + + + if (OSIntNesting > 0) { /* See if trying to delete from ISR */ + 801680c: d0a05703 ldbu r2,-32420(gp) + 8016810: 10803fcc andi r2,r2,255 + 8016814: 10000226 beq r2,zero,8016820 + return (OS_ERR_TASK_DEL_ISR); + 8016818: 00801004 movi r2,64 + 801681c: 0000b406 br 8016af0 + } + if (prio == OS_TASK_IDLE_PRIO) { /* Not allowed to delete idle task */ + 8016820: e0bff603 ldbu r2,-40(fp) + 8016824: 10800518 cmpnei r2,r2,20 + 8016828: 1000021e bne r2,zero,8016834 + return (OS_ERR_TASK_DEL_IDLE); + 801682c: 00800f84 movi r2,62 + 8016830: 0000af06 br 8016af0 + NIOS2_READ_STATUS (context); + 8016834: 0005303a rdctl r2,status + 8016838: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 801683c: e0fffc17 ldw r3,-16(fp) + 8016840: 00bfff84 movi r2,-2 + 8016844: 1884703a and r2,r3,r2 + 8016848: 1001703a wrctl status,r2 + return context; + 801684c: e0bffc17 ldw r2,-16(fp) + } + } +#endif + +/*$PAGE*/ + OS_ENTER_CRITICAL(); + 8016850: e0bfff15 stw r2,-4(fp) + if (prio == OS_PRIO_SELF) { /* See if requesting to delete self */ + 8016854: e0bff603 ldbu r2,-40(fp) + 8016858: 10803fd8 cmpnei r2,r2,255 + 801685c: 1000031e bne r2,zero,801686c + prio = OSTCBCur->OSTCBPrio; /* Set priority to delete to current */ + 8016860: d0a05817 ldw r2,-32416(gp) + 8016864: 10800c83 ldbu r2,50(r2) + 8016868: e0bff605 stb r2,-40(fp) + } + ptcb = OSTCBPrioTbl[prio]; + 801686c: e0bff603 ldbu r2,-40(fp) + 8016870: 100690ba slli r3,r2,2 + 8016874: 008201b4 movhi r2,2054 + 8016878: 1885883a add r2,r3,r2 + 801687c: 10b55d17 ldw r2,-10892(r2) + 8016880: e0bffe15 stw r2,-8(fp) + if (ptcb == (OS_TCB *)0) { /* Task to delete must exist */ + 8016884: e0bffe17 ldw r2,-8(fp) + 8016888: 1000061e bne r2,zero,80168a4 + 801688c: e0bfff17 ldw r2,-4(fp) + 8016890: e0bffb15 stw r2,-20(fp) + NIOS2_WRITE_STATUS (context); + 8016894: e0bffb17 ldw r2,-20(fp) + 8016898: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + 801689c: 008010c4 movi r2,67 + 80168a0: 00009306 br 8016af0 + } + if (ptcb == OS_TCB_RESERVED) { /* Must not be assigned to Mutex */ + 80168a4: e0bffe17 ldw r2,-8(fp) + 80168a8: 10800058 cmpnei r2,r2,1 + 80168ac: 1000061e bne r2,zero,80168c8 + 80168b0: e0bfff17 ldw r2,-4(fp) + 80168b4: e0bffa15 stw r2,-24(fp) + 80168b8: e0bffa17 ldw r2,-24(fp) + 80168bc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_DEL); + 80168c0: 00800f44 movi r2,61 + 80168c4: 00008a06 br 8016af0 + } + + OSRdyTbl[ptcb->OSTCBY] &= ~ptcb->OSTCBBitX; + 80168c8: e0bffe17 ldw r2,-8(fp) + 80168cc: 10800d03 ldbu r2,52(r2) + 80168d0: 10c03fcc andi r3,r2,255 + 80168d4: d0a05544 addi r2,gp,-32427 + 80168d8: 1885883a add r2,r3,r2 + 80168dc: 10800003 ldbu r2,0(r2) + 80168e0: 1007883a mov r3,r2 + 80168e4: e0bffe17 ldw r2,-8(fp) + 80168e8: 10800d43 ldbu r2,53(r2) + 80168ec: 0084303a nor r2,zero,r2 + 80168f0: 1884703a and r2,r3,r2 + 80168f4: 1009883a mov r4,r2 + 80168f8: e0bffe17 ldw r2,-8(fp) + 80168fc: 10800d03 ldbu r2,52(r2) + 8016900: 10c03fcc andi r3,r2,255 + 8016904: d0a05544 addi r2,gp,-32427 + 8016908: 1885883a add r2,r3,r2 + 801690c: 11000005 stb r4,0(r2) + if (OSRdyTbl[ptcb->OSTCBY] == 0) { /* Make task not ready */ + 8016910: e0bffe17 ldw r2,-8(fp) + 8016914: 10800d03 ldbu r2,52(r2) + 8016918: 10c03fcc andi r3,r2,255 + 801691c: d0a05544 addi r2,gp,-32427 + 8016920: 1885883a add r2,r3,r2 + 8016924: 10800003 ldbu r2,0(r2) + 8016928: 10803fcc andi r2,r2,255 + 801692c: 1000071e bne r2,zero,801694c + OSRdyGrp &= ~ptcb->OSTCBBitY; + 8016930: e0bffe17 ldw r2,-8(fp) + 8016934: 10800d83 ldbu r2,54(r2) + 8016938: 0084303a nor r2,zero,r2 + 801693c: 1007883a mov r3,r2 + 8016940: d0a05503 ldbu r2,-32428(gp) + 8016944: 1884703a and r2,r3,r2 + 8016948: d0a05505 stb r2,-32428(gp) + } + +#if (OS_EVENT_EN) + if (ptcb->OSTCBEventPtr != (OS_EVENT *)0) { + 801694c: e0bffe17 ldw r2,-8(fp) + 8016950: 10800717 ldw r2,28(r2) + 8016954: 10000526 beq r2,zero,801696c + OS_EventTaskRemove(ptcb, ptcb->OSTCBEventPtr); /* Remove this task from any event wait list */ + 8016958: e0bffe17 ldw r2,-8(fp) + 801695c: 10800717 ldw r2,28(r2) + 8016960: 100b883a mov r5,r2 + 8016964: e13ffe17 ldw r4,-8(fp) + 8016968: 80110b00 call 80110b0 + } +#if (OS_EVENT_MULTI_EN > 0) + if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) { /* Remove this task from any events' wait lists*/ + 801696c: e0bffe17 ldw r2,-8(fp) + 8016970: 10800817 ldw r2,32(r2) + 8016974: 10000526 beq r2,zero,801698c + OS_EventTaskRemoveMulti(ptcb, ptcb->OSTCBEventMultiPtr); + 8016978: e0bffe17 ldw r2,-8(fp) + 801697c: 10800817 ldw r2,32(r2) + 8016980: 100b883a mov r5,r2 + 8016984: e13ffe17 ldw r4,-8(fp) + 8016988: 80111600 call 8011160 + } +#endif +#endif + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) + pnode = ptcb->OSTCBFlagNode; + 801698c: e0bffe17 ldw r2,-8(fp) + 8016990: 10800a17 ldw r2,40(r2) + 8016994: e0bffd15 stw r2,-12(fp) + if (pnode != (OS_FLAG_NODE *)0) { /* If task is waiting on event flag */ + 8016998: e0bffd17 ldw r2,-12(fp) + 801699c: 10000226 beq r2,zero,80169a8 + OS_FlagUnlink(pnode); /* Remove from wait list */ + 80169a0: e13ffd17 ldw r4,-12(fp) + 80169a4: 80130ac0 call 80130ac + } +#endif + + ptcb->OSTCBDly = 0; /* Prevent OSTimeTick() from updating */ + 80169a8: e0bffe17 ldw r2,-8(fp) + 80169ac: 10000b8d sth zero,46(r2) + ptcb->OSTCBStat = OS_STAT_RDY; /* Prevent task from being resumed */ + 80169b0: e0bffe17 ldw r2,-8(fp) + 80169b4: 10000c05 stb zero,48(r2) + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; + 80169b8: e0bffe17 ldw r2,-8(fp) + 80169bc: 10000c45 stb zero,49(r2) + if (OSLockNesting < 255u) { /* Make sure we don't context switch */ + 80169c0: d0a04b03 ldbu r2,-32468(gp) + 80169c4: 10803fcc andi r2,r2,255 + 80169c8: 10803fe0 cmpeqi r2,r2,255 + 80169cc: 1000031e bne r2,zero,80169dc + OSLockNesting++; + 80169d0: d0a04b03 ldbu r2,-32468(gp) + 80169d4: 10800044 addi r2,r2,1 + 80169d8: d0a04b05 stb r2,-32468(gp) + 80169dc: e0bfff17 ldw r2,-4(fp) + 80169e0: e0bff815 stw r2,-32(fp) + 80169e4: e0bff817 ldw r2,-32(fp) + 80169e8: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); /* Enabling INT. ignores next instruc. */ + OS_Dummy(); /* ... Dummy ensures that INTs will be */ + 80169ec: 8010cb80 call 8010cb8 + NIOS2_READ_STATUS (context); + 80169f0: 0005303a rdctl r2,status + 80169f4: e0bff915 stw r2,-28(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 80169f8: e0fff917 ldw r3,-28(fp) + 80169fc: 00bfff84 movi r2,-2 + 8016a00: 1884703a and r2,r3,r2 + 8016a04: 1001703a wrctl status,r2 + return context; + 8016a08: e0bff917 ldw r2,-28(fp) + OS_ENTER_CRITICAL(); /* ... disabled HERE! */ + 8016a0c: e0bfff15 stw r2,-4(fp) + if (OSLockNesting > 0) { /* Remove context switch lock */ + 8016a10: d0a04b03 ldbu r2,-32468(gp) + 8016a14: 10803fcc andi r2,r2,255 + 8016a18: 10000326 beq r2,zero,8016a28 + OSLockNesting--; + 8016a1c: d0a04b03 ldbu r2,-32468(gp) + 8016a20: 10bfffc4 addi r2,r2,-1 + 8016a24: d0a04b05 stb r2,-32468(gp) + } + OSTaskDelHook(ptcb); /* Call user defined hook */ + 8016a28: e13ffe17 ldw r4,-8(fp) + 8016a2c: 80385c80 call 80385c8 + OSTaskCtr--; /* One less task being managed */ + 8016a30: d0a05103 ldbu r2,-32444(gp) + 8016a34: 10bfffc4 addi r2,r2,-1 + 8016a38: d0a05105 stb r2,-32444(gp) + OSTCBPrioTbl[prio] = (OS_TCB *)0; /* Clear old priority entry */ + 8016a3c: e0bff603 ldbu r2,-40(fp) + 8016a40: 100690ba slli r3,r2,2 + 8016a44: 008201b4 movhi r2,2054 + 8016a48: 1885883a add r2,r3,r2 + 8016a4c: 10355d15 stw zero,-10892(r2) + if (ptcb->OSTCBPrev == (OS_TCB *)0) { /* Remove from TCB chain */ + 8016a50: e0bffe17 ldw r2,-8(fp) + 8016a54: 10800617 ldw r2,24(r2) + 8016a58: 1000071e bne r2,zero,8016a78 + ptcb->OSTCBNext->OSTCBPrev = (OS_TCB *)0; + 8016a5c: e0bffe17 ldw r2,-8(fp) + 8016a60: 10800517 ldw r2,20(r2) + 8016a64: 10000615 stw zero,24(r2) + OSTCBList = ptcb->OSTCBNext; + 8016a68: e0bffe17 ldw r2,-8(fp) + 8016a6c: 10800517 ldw r2,20(r2) + 8016a70: d0a04e15 stw r2,-32456(gp) + 8016a74: 00000a06 br 8016aa0 + } else { + ptcb->OSTCBPrev->OSTCBNext = ptcb->OSTCBNext; + 8016a78: e0bffe17 ldw r2,-8(fp) + 8016a7c: 10800617 ldw r2,24(r2) + 8016a80: e0fffe17 ldw r3,-8(fp) + 8016a84: 18c00517 ldw r3,20(r3) + 8016a88: 10c00515 stw r3,20(r2) + ptcb->OSTCBNext->OSTCBPrev = ptcb->OSTCBPrev; + 8016a8c: e0bffe17 ldw r2,-8(fp) + 8016a90: 10800517 ldw r2,20(r2) + 8016a94: e0fffe17 ldw r3,-8(fp) + 8016a98: 18c00617 ldw r3,24(r3) + 8016a9c: 10c00615 stw r3,24(r2) + } + ptcb->OSTCBNext = OSTCBFreeList; /* Return TCB to free TCB list */ + 8016aa0: d0e05017 ldw r3,-32448(gp) + 8016aa4: e0bffe17 ldw r2,-8(fp) + 8016aa8: 10c00515 stw r3,20(r2) + OSTCBFreeList = ptcb; + 8016aac: e0bffe17 ldw r2,-8(fp) + 8016ab0: d0a05015 stw r2,-32448(gp) +#if OS_TASK_NAME_SIZE > 1 + ptcb->OSTCBTaskName[0] = '?'; /* Unknown name */ + 8016ab4: e0bffe17 ldw r2,-8(fp) + 8016ab8: 00c00fc4 movi r3,63 + 8016abc: 10c01305 stb r3,76(r2) + ptcb->OSTCBTaskName[1] = OS_ASCII_NUL; + 8016ac0: e0bffe17 ldw r2,-8(fp) + 8016ac4: 10001345 stb zero,77(r2) + 8016ac8: e0bfff17 ldw r2,-4(fp) + 8016acc: e0bff715 stw r2,-36(fp) + NIOS2_WRITE_STATUS (context); + 8016ad0: e0bff717 ldw r2,-36(fp) + 8016ad4: 1001703a wrctl status,r2 +#endif + OS_EXIT_CRITICAL(); + if (OSRunning == OS_TRUE) { + 8016ad8: d0a04b43 ldbu r2,-32467(gp) + 8016adc: 10803fcc andi r2,r2,255 + 8016ae0: 10800058 cmpnei r2,r2,1 + 8016ae4: 1000011e bne r2,zero,8016aec + OS_Sched(); /* Find new highest priority task */ + 8016ae8: 801166c0 call 801166c + } + return (OS_ERR_NONE); + 8016aec: 0005883a mov r2,zero +} + 8016af0: e037883a mov sp,fp + 8016af4: dfc00117 ldw ra,4(sp) + 8016af8: df000017 ldw fp,0(sp) + 8016afc: dec00204 addi sp,sp,8 + 8016b00: f800283a ret + +08016b04 : +********************************************************************************************************* +*/ +/*$PAGE*/ +#if OS_TASK_DEL_EN > 0 +INT8U OSTaskDelReq (INT8U prio) +{ + 8016b04: defff504 addi sp,sp,-44 + 8016b08: df000a15 stw fp,40(sp) + 8016b0c: df000a04 addi fp,sp,40 + 8016b10: 2005883a mov r2,r4 + 8016b14: e0bff605 stb r2,-40(fp) + INT8U stat; + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8016b18: e03fff15 stw zero,-4(fp) +#endif + + + + if (prio == OS_TASK_IDLE_PRIO) { /* Not allowed to delete idle task */ + 8016b1c: e0bff603 ldbu r2,-40(fp) + 8016b20: 10800518 cmpnei r2,r2,20 + 8016b24: 1000021e bne r2,zero,8016b30 + return (OS_ERR_TASK_DEL_IDLE); + 8016b28: 00800f84 movi r2,62 + 8016b2c: 00003b06 br 8016c1c + if (prio != OS_PRIO_SELF) { + return (OS_ERR_PRIO_INVALID); + } + } +#endif + if (prio == OS_PRIO_SELF) { /* See if a task is requesting to ... */ + 8016b30: e0bff603 ldbu r2,-40(fp) + 8016b34: 10803fd8 cmpnei r2,r2,255 + 8016b38: 1000111e bne r2,zero,8016b80 + NIOS2_READ_STATUS (context); + 8016b3c: 0005303a rdctl r2,status + 8016b40: e0bffb15 stw r2,-20(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8016b44: e0fffb17 ldw r3,-20(fp) + 8016b48: 00bfff84 movi r2,-2 + 8016b4c: 1884703a and r2,r3,r2 + 8016b50: 1001703a wrctl status,r2 + return context; + 8016b54: e0bffb17 ldw r2,-20(fp) + OS_ENTER_CRITICAL(); /* ... this task to delete itself */ + 8016b58: e0bfff15 stw r2,-4(fp) + stat = OSTCBCur->OSTCBDelReq; /* Return request status to caller */ + 8016b5c: d0a05817 ldw r2,-32416(gp) + 8016b60: 10800dc3 ldbu r2,55(r2) + 8016b64: e0bffec5 stb r2,-5(fp) + 8016b68: e0bfff17 ldw r2,-4(fp) + 8016b6c: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 8016b70: e0bffc17 ldw r2,-16(fp) + 8016b74: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (stat); + 8016b78: e0bffec3 ldbu r2,-5(fp) + 8016b7c: 00002706 br 8016c1c + NIOS2_READ_STATUS (context); + 8016b80: 0005303a rdctl r2,status + 8016b84: e0bffa15 stw r2,-24(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8016b88: e0fffa17 ldw r3,-24(fp) + 8016b8c: 00bfff84 movi r2,-2 + 8016b90: 1884703a and r2,r3,r2 + 8016b94: 1001703a wrctl status,r2 + return context; + 8016b98: e0bffa17 ldw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + 8016b9c: e0bfff15 stw r2,-4(fp) + ptcb = OSTCBPrioTbl[prio]; + 8016ba0: e0bff603 ldbu r2,-40(fp) + 8016ba4: 100690ba slli r3,r2,2 + 8016ba8: 008201b4 movhi r2,2054 + 8016bac: 1885883a add r2,r3,r2 + 8016bb0: 10b55d17 ldw r2,-10892(r2) + 8016bb4: e0bffd15 stw r2,-12(fp) + if (ptcb == (OS_TCB *)0) { /* Task to delete must exist */ + 8016bb8: e0bffd17 ldw r2,-12(fp) + 8016bbc: 1000061e bne r2,zero,8016bd8 + 8016bc0: e0bfff17 ldw r2,-4(fp) + 8016bc4: e0bff915 stw r2,-28(fp) + NIOS2_WRITE_STATUS (context); + 8016bc8: e0bff917 ldw r2,-28(fp) + 8016bcc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); /* Task must already be deleted */ + 8016bd0: 008010c4 movi r2,67 + 8016bd4: 00001106 br 8016c1c + } + if (ptcb == OS_TCB_RESERVED) { /* Must NOT be assigned to a Mutex */ + 8016bd8: e0bffd17 ldw r2,-12(fp) + 8016bdc: 10800058 cmpnei r2,r2,1 + 8016be0: 1000061e bne r2,zero,8016bfc + 8016be4: e0bfff17 ldw r2,-4(fp) + 8016be8: e0bff815 stw r2,-32(fp) + 8016bec: e0bff817 ldw r2,-32(fp) + 8016bf0: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_DEL); + 8016bf4: 00800f44 movi r2,61 + 8016bf8: 00000806 br 8016c1c + } + ptcb->OSTCBDelReq = OS_ERR_TASK_DEL_REQ; /* Set flag indicating task to be DEL. */ + 8016bfc: e0bffd17 ldw r2,-12(fp) + 8016c00: 00c00fc4 movi r3,63 + 8016c04: 10c00dc5 stb r3,55(r2) + 8016c08: e0bfff17 ldw r2,-4(fp) + 8016c0c: e0bff715 stw r2,-36(fp) + 8016c10: e0bff717 ldw r2,-36(fp) + 8016c14: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 8016c18: 0005883a mov r2,zero +} + 8016c1c: e037883a mov sp,fp + 8016c20: df000017 ldw fp,0(sp) + 8016c24: dec00104 addi sp,sp,4 + 8016c28: f800283a ret + +08016c2c : +********************************************************************************************************* +*/ + +#if OS_TASK_NAME_SIZE > 1 +INT8U OSTaskNameGet (INT8U prio, INT8U *pname, INT8U *perr) +{ + 8016c2c: defff404 addi sp,sp,-48 + 8016c30: dfc00b15 stw ra,44(sp) + 8016c34: df000a15 stw fp,40(sp) + 8016c38: df000a04 addi fp,sp,40 + 8016c3c: 2005883a mov r2,r4 + 8016c40: e17ff715 stw r5,-36(fp) + 8016c44: e1bff615 stw r6,-40(fp) + 8016c48: e0bff805 stb r2,-32(fp) + OS_TCB *ptcb; + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8016c4c: e03fff15 stw zero,-4(fp) + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + *perr = OS_ERR_PNAME_NULL; /* Yes */ + return (0); + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 8016c50: d0a05703 ldbu r2,-32420(gp) + 8016c54: 10803fcc andi r2,r2,255 + 8016c58: 10000526 beq r2,zero,8016c70 + *perr = OS_ERR_NAME_GET_ISR; + 8016c5c: e0bff617 ldw r2,-40(fp) + 8016c60: 00c00444 movi r3,17 + 8016c64: 10c00005 stb r3,0(r2) + return (0); + 8016c68: 0005883a mov r2,zero + 8016c6c: 00003806 br 8016d50 + NIOS2_READ_STATUS (context); + 8016c70: 0005303a rdctl r2,status + 8016c74: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8016c78: e0fffc17 ldw r3,-16(fp) + 8016c7c: 00bfff84 movi r2,-2 + 8016c80: 1884703a and r2,r3,r2 + 8016c84: 1001703a wrctl status,r2 + return context; + 8016c88: e0bffc17 ldw r2,-16(fp) + } + OS_ENTER_CRITICAL(); + 8016c8c: e0bfff15 stw r2,-4(fp) + if (prio == OS_PRIO_SELF) { /* See if caller desires it's own name */ + 8016c90: e0bff803 ldbu r2,-32(fp) + 8016c94: 10803fd8 cmpnei r2,r2,255 + 8016c98: 1000031e bne r2,zero,8016ca8 + prio = OSTCBCur->OSTCBPrio; + 8016c9c: d0a05817 ldw r2,-32416(gp) + 8016ca0: 10800c83 ldbu r2,50(r2) + 8016ca4: e0bff805 stb r2,-32(fp) + } + ptcb = OSTCBPrioTbl[prio]; + 8016ca8: e0bff803 ldbu r2,-32(fp) + 8016cac: 100690ba slli r3,r2,2 + 8016cb0: 008201b4 movhi r2,2054 + 8016cb4: 1885883a add r2,r3,r2 + 8016cb8: 10b55d17 ldw r2,-10892(r2) + 8016cbc: e0bffe15 stw r2,-8(fp) + if (ptcb == (OS_TCB *)0) { /* Does task exist? */ + 8016cc0: e0bffe17 ldw r2,-8(fp) + 8016cc4: 1000091e bne r2,zero,8016cec + 8016cc8: e0bfff17 ldw r2,-4(fp) + 8016ccc: e0bffb15 stw r2,-20(fp) + NIOS2_WRITE_STATUS (context); + 8016cd0: e0bffb17 ldw r2,-20(fp) + 8016cd4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* No */ + *perr = OS_ERR_TASK_NOT_EXIST; + 8016cd8: e0bff617 ldw r2,-40(fp) + 8016cdc: 00c010c4 movi r3,67 + 8016ce0: 10c00005 stb r3,0(r2) + return (0); + 8016ce4: 0005883a mov r2,zero + 8016ce8: 00001906 br 8016d50 + } + if (ptcb == OS_TCB_RESERVED) { /* Task assigned to a Mutex? */ + 8016cec: e0bffe17 ldw r2,-8(fp) + 8016cf0: 10800058 cmpnei r2,r2,1 + 8016cf4: 1000091e bne r2,zero,8016d1c + 8016cf8: e0bfff17 ldw r2,-4(fp) + 8016cfc: e0bffa15 stw r2,-24(fp) + 8016d00: e0bffa17 ldw r2,-24(fp) + 8016d04: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Yes */ + *perr = OS_ERR_TASK_NOT_EXIST; + 8016d08: e0bff617 ldw r2,-40(fp) + 8016d0c: 00c010c4 movi r3,67 + 8016d10: 10c00005 stb r3,0(r2) + return (0); + 8016d14: 0005883a mov r2,zero + 8016d18: 00000d06 br 8016d50 + } + len = OS_StrCopy(pname, ptcb->OSTCBTaskName); /* Yes, copy name from TCB */ + 8016d1c: e0bffe17 ldw r2,-8(fp) + 8016d20: 10801304 addi r2,r2,76 + 8016d24: 100b883a mov r5,r2 + 8016d28: e13ff717 ldw r4,-36(fp) + 8016d2c: 80117a00 call 80117a0 + 8016d30: e0bffdc5 stb r2,-9(fp) + 8016d34: e0bfff17 ldw r2,-4(fp) + 8016d38: e0bff915 stw r2,-28(fp) + 8016d3c: e0bff917 ldw r2,-28(fp) + 8016d40: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 8016d44: e0bff617 ldw r2,-40(fp) + 8016d48: 10000005 stb zero,0(r2) + return (len); + 8016d4c: e0bffdc3 ldbu r2,-9(fp) +} + 8016d50: e037883a mov sp,fp + 8016d54: dfc00117 ldw ra,4(sp) + 8016d58: df000017 ldw fp,0(sp) + 8016d5c: dec00204 addi sp,sp,8 + 8016d60: f800283a ret + +08016d64 : +* Returns : None +********************************************************************************************************* +*/ +#if OS_TASK_NAME_SIZE > 1 +void OSTaskNameSet (INT8U prio, INT8U *pname, INT8U *perr) +{ + 8016d64: defff304 addi sp,sp,-52 + 8016d68: dfc00c15 stw ra,48(sp) + 8016d6c: df000b15 stw fp,44(sp) + 8016d70: df000b04 addi fp,sp,44 + 8016d74: 2005883a mov r2,r4 + 8016d78: e17ff615 stw r5,-40(fp) + 8016d7c: e1bff515 stw r6,-44(fp) + 8016d80: e0bff705 stb r2,-36(fp) + INT8U len; + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8016d84: e03fff15 stw zero,-4(fp) + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + *perr = OS_ERR_PNAME_NULL; /* Yes */ + return; + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 8016d88: d0a05703 ldbu r2,-32420(gp) + 8016d8c: 10803fcc andi r2,r2,255 + 8016d90: 10000426 beq r2,zero,8016da4 + *perr = OS_ERR_NAME_SET_ISR; + 8016d94: e0bff517 ldw r2,-44(fp) + 8016d98: 00c00484 movi r3,18 + 8016d9c: 10c00005 stb r3,0(r2) + return; + 8016da0: 00004206 br 8016eac + NIOS2_READ_STATUS (context); + 8016da4: 0005303a rdctl r2,status + 8016da8: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8016dac: e0fffc17 ldw r3,-16(fp) + 8016db0: 00bfff84 movi r2,-2 + 8016db4: 1884703a and r2,r3,r2 + 8016db8: 1001703a wrctl status,r2 + return context; + 8016dbc: e0bffc17 ldw r2,-16(fp) + } + OS_ENTER_CRITICAL(); + 8016dc0: e0bfff15 stw r2,-4(fp) + if (prio == OS_PRIO_SELF) { /* See if caller desires to set it's own name */ + 8016dc4: e0bff703 ldbu r2,-36(fp) + 8016dc8: 10803fd8 cmpnei r2,r2,255 + 8016dcc: 1000031e bne r2,zero,8016ddc + prio = OSTCBCur->OSTCBPrio; + 8016dd0: d0a05817 ldw r2,-32416(gp) + 8016dd4: 10800c83 ldbu r2,50(r2) + 8016dd8: e0bff705 stb r2,-36(fp) + } + ptcb = OSTCBPrioTbl[prio]; + 8016ddc: e0bff703 ldbu r2,-36(fp) + 8016de0: 100690ba slli r3,r2,2 + 8016de4: 008201b4 movhi r2,2054 + 8016de8: 1885883a add r2,r3,r2 + 8016dec: 10b55d17 ldw r2,-10892(r2) + 8016df0: e0bffe15 stw r2,-8(fp) + if (ptcb == (OS_TCB *)0) { /* Does task exist? */ + 8016df4: e0bffe17 ldw r2,-8(fp) + 8016df8: 1000081e bne r2,zero,8016e1c + 8016dfc: e0bfff17 ldw r2,-4(fp) + 8016e00: e0bffb15 stw r2,-20(fp) + NIOS2_WRITE_STATUS (context); + 8016e04: e0bffb17 ldw r2,-20(fp) + 8016e08: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* No */ + *perr = OS_ERR_TASK_NOT_EXIST; + 8016e0c: e0bff517 ldw r2,-44(fp) + 8016e10: 00c010c4 movi r3,67 + 8016e14: 10c00005 stb r3,0(r2) + return; + 8016e18: 00002406 br 8016eac + } + if (ptcb == OS_TCB_RESERVED) { /* Task assigned to a Mutex? */ + 8016e1c: e0bffe17 ldw r2,-8(fp) + 8016e20: 10800058 cmpnei r2,r2,1 + 8016e24: 1000081e bne r2,zero,8016e48 + 8016e28: e0bfff17 ldw r2,-4(fp) + 8016e2c: e0bffa15 stw r2,-24(fp) + 8016e30: e0bffa17 ldw r2,-24(fp) + 8016e34: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Yes */ + *perr = OS_ERR_TASK_NOT_EXIST; + 8016e38: e0bff517 ldw r2,-44(fp) + 8016e3c: 00c010c4 movi r3,67 + 8016e40: 10c00005 stb r3,0(r2) + return; + 8016e44: 00001906 br 8016eac + } + len = OS_StrLen(pname); /* Yes, Can we fit the string in the TCB? */ + 8016e48: e13ff617 ldw r4,-40(fp) + 8016e4c: 80118140 call 8011814 + 8016e50: e0bffdc5 stb r2,-9(fp) + if (len > (OS_TASK_NAME_SIZE - 1)) { /* No */ + 8016e54: e0bffdc3 ldbu r2,-9(fp) + 8016e58: 10800830 cmpltui r2,r2,32 + 8016e5c: 1000081e bne r2,zero,8016e80 + 8016e60: e0bfff17 ldw r2,-4(fp) + 8016e64: e0bff915 stw r2,-28(fp) + 8016e68: e0bff917 ldw r2,-28(fp) + 8016e6c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_NAME_TOO_LONG; + 8016e70: e0bff517 ldw r2,-44(fp) + 8016e74: 00c01044 movi r3,65 + 8016e78: 10c00005 stb r3,0(r2) + return; + 8016e7c: 00000b06 br 8016eac + } + (void)OS_StrCopy(ptcb->OSTCBTaskName, pname); /* Yes, copy to TCB */ + 8016e80: e0bffe17 ldw r2,-8(fp) + 8016e84: 10801304 addi r2,r2,76 + 8016e88: e17ff617 ldw r5,-40(fp) + 8016e8c: 1009883a mov r4,r2 + 8016e90: 80117a00 call 80117a0 + 8016e94: e0bfff17 ldw r2,-4(fp) + 8016e98: e0bff815 stw r2,-32(fp) + 8016e9c: e0bff817 ldw r2,-32(fp) + 8016ea0: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 8016ea4: e0bff517 ldw r2,-44(fp) + 8016ea8: 10000005 stb zero,0(r2) +} + 8016eac: e037883a mov sp,fp + 8016eb0: dfc00117 ldw ra,4(sp) + 8016eb4: df000017 ldw fp,0(sp) + 8016eb8: dec00204 addi sp,sp,8 + 8016ebc: f800283a ret + +08016ec0 : +********************************************************************************************************* +*/ + +#if OS_TASK_SUSPEND_EN > 0 +INT8U OSTaskResume (INT8U prio) +{ + 8016ec0: defff404 addi sp,sp,-48 + 8016ec4: dfc00b15 stw ra,44(sp) + 8016ec8: df000a15 stw fp,40(sp) + 8016ecc: df000a04 addi fp,sp,40 + 8016ed0: 2005883a mov r2,r4 + 8016ed4: e0bff605 stb r2,-40(fp) + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8016ed8: e03fff15 stw zero,-4(fp) + NIOS2_READ_STATUS (context); + 8016edc: 0005303a rdctl r2,status + 8016ee0: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8016ee4: e0fffd17 ldw r3,-12(fp) + 8016ee8: 00bfff84 movi r2,-2 + 8016eec: 1884703a and r2,r3,r2 + 8016ef0: 1001703a wrctl status,r2 + return context; + 8016ef4: e0bffd17 ldw r2,-12(fp) +#if OS_ARG_CHK_EN > 0 + if (prio >= OS_LOWEST_PRIO) { /* Make sure task priority is valid */ + return (OS_ERR_PRIO_INVALID); + } +#endif + OS_ENTER_CRITICAL(); + 8016ef8: e0bfff15 stw r2,-4(fp) + ptcb = OSTCBPrioTbl[prio]; + 8016efc: e0bff603 ldbu r2,-40(fp) + 8016f00: 100690ba slli r3,r2,2 + 8016f04: 008201b4 movhi r2,2054 + 8016f08: 1885883a add r2,r3,r2 + 8016f0c: 10b55d17 ldw r2,-10892(r2) + 8016f10: e0bffe15 stw r2,-8(fp) + if (ptcb == (OS_TCB *)0) { /* Task to suspend must exist */ + 8016f14: e0bffe17 ldw r2,-8(fp) + 8016f18: 1000061e bne r2,zero,8016f34 + 8016f1c: e0bfff17 ldw r2,-4(fp) + 8016f20: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 8016f24: e0bffc17 ldw r2,-16(fp) + 8016f28: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_RESUME_PRIO); + 8016f2c: 00801184 movi r2,70 + 8016f30: 00004c06 br 8017064 + } + if (ptcb == OS_TCB_RESERVED) { /* See if assigned to Mutex */ + 8016f34: e0bffe17 ldw r2,-8(fp) + 8016f38: 10800058 cmpnei r2,r2,1 + 8016f3c: 1000061e bne r2,zero,8016f58 + 8016f40: e0bfff17 ldw r2,-4(fp) + 8016f44: e0bffb15 stw r2,-20(fp) + 8016f48: e0bffb17 ldw r2,-20(fp) + 8016f4c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + 8016f50: 008010c4 movi r2,67 + 8016f54: 00004306 br 8017064 + } + if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) != OS_STAT_RDY) { /* Task must be suspended */ + 8016f58: e0bffe17 ldw r2,-8(fp) + 8016f5c: 10800c03 ldbu r2,48(r2) + 8016f60: 10803fcc andi r2,r2,255 + 8016f64: 1080020c andi r2,r2,8 + 8016f68: 10003926 beq r2,zero,8017050 + ptcb->OSTCBStat &= ~(INT8U)OS_STAT_SUSPEND; /* Remove suspension */ + 8016f6c: e0bffe17 ldw r2,-8(fp) + 8016f70: 10c00c03 ldbu r3,48(r2) + 8016f74: 00bffdc4 movi r2,-9 + 8016f78: 1884703a and r2,r3,r2 + 8016f7c: 1007883a mov r3,r2 + 8016f80: e0bffe17 ldw r2,-8(fp) + 8016f84: 10c00c05 stb r3,48(r2) + if (ptcb->OSTCBStat == OS_STAT_RDY) { /* See if task is now ready */ + 8016f88: e0bffe17 ldw r2,-8(fp) + 8016f8c: 10800c03 ldbu r2,48(r2) + 8016f90: 10803fcc andi r2,r2,255 + 8016f94: 1000281e bne r2,zero,8017038 + if (ptcb->OSTCBDly == 0) { + 8016f98: e0bffe17 ldw r2,-8(fp) + 8016f9c: 10800b8b ldhu r2,46(r2) + 8016fa0: 10bfffcc andi r2,r2,65535 + 8016fa4: 10001f1e bne r2,zero,8017024 + OSRdyGrp |= ptcb->OSTCBBitY; /* Yes, Make task ready to run */ + 8016fa8: e0bffe17 ldw r2,-8(fp) + 8016fac: 10c00d83 ldbu r3,54(r2) + 8016fb0: d0a05503 ldbu r2,-32428(gp) + 8016fb4: 1884b03a or r2,r3,r2 + 8016fb8: d0a05505 stb r2,-32428(gp) + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + 8016fbc: e0bffe17 ldw r2,-8(fp) + 8016fc0: 10800d03 ldbu r2,52(r2) + 8016fc4: 10c03fcc andi r3,r2,255 + 8016fc8: d0a05544 addi r2,gp,-32427 + 8016fcc: 1885883a add r2,r3,r2 + 8016fd0: 11000003 ldbu r4,0(r2) + 8016fd4: e0bffe17 ldw r2,-8(fp) + 8016fd8: 10800d43 ldbu r2,53(r2) + 8016fdc: e0fffe17 ldw r3,-8(fp) + 8016fe0: 18c00d03 ldbu r3,52(r3) + 8016fe4: 18c03fcc andi r3,r3,255 + 8016fe8: 2084b03a or r2,r4,r2 + 8016fec: 1009883a mov r4,r2 + 8016ff0: d0a05544 addi r2,gp,-32427 + 8016ff4: 1885883a add r2,r3,r2 + 8016ff8: 11000005 stb r4,0(r2) + 8016ffc: e0bfff17 ldw r2,-4(fp) + 8017000: e0bffa15 stw r2,-24(fp) + 8017004: e0bffa17 ldw r2,-24(fp) + 8017008: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (OSRunning == OS_TRUE) { + 801700c: d0a04b43 ldbu r2,-32467(gp) + 8017010: 10803fcc andi r2,r2,255 + 8017014: 10800058 cmpnei r2,r2,1 + 8017018: 10000b1e bne r2,zero,8017048 + OS_Sched(); /* Find new highest priority task */ + 801701c: 801166c0 call 801166c + 8017020: 00000906 br 8017048 + 8017024: e0bfff17 ldw r2,-4(fp) + 8017028: e0bff915 stw r2,-28(fp) + 801702c: e0bff917 ldw r2,-28(fp) + 8017030: 1001703a wrctl status,r2 + 8017034: 00000406 br 8017048 + 8017038: e0bfff17 ldw r2,-4(fp) + 801703c: e0bff815 stw r2,-32(fp) + 8017040: e0bff817 ldw r2,-32(fp) + 8017044: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + } else { /* Must be pending on event */ + OS_EXIT_CRITICAL(); + } + return (OS_ERR_NONE); + 8017048: 0005883a mov r2,zero + 801704c: 00000506 br 8017064 + 8017050: e0bfff17 ldw r2,-4(fp) + 8017054: e0bff715 stw r2,-36(fp) + 8017058: e0bff717 ldw r2,-36(fp) + 801705c: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_SUSPENDED); + 8017060: 00801104 movi r2,68 +} + 8017064: e037883a mov sp,fp + 8017068: dfc00117 ldw ra,4(sp) + 801706c: df000017 ldw fp,0(sp) + 8017070: dec00204 addi sp,sp,8 + 8017074: f800283a ret + +08017078 : +********************************************************************************************************* +*/ + +#if OS_TASK_SUSPEND_EN > 0 +INT8U OSTaskSuspend (INT8U prio) +{ + 8017078: defff504 addi sp,sp,-44 + 801707c: dfc00a15 stw ra,40(sp) + 8017080: df000915 stw fp,36(sp) + 8017084: df000904 addi fp,sp,36 + 8017088: 2005883a mov r2,r4 + 801708c: e0bff705 stb r2,-36(fp) + BOOLEAN self; + OS_TCB *ptcb; + INT8U y; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8017090: e03ffe15 stw zero,-8(fp) + NIOS2_READ_STATUS (context); + 8017094: 0005303a rdctl r2,status + 8017098: e0bffb15 stw r2,-20(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 801709c: e0fffb17 ldw r3,-20(fp) + 80170a0: 00bfff84 movi r2,-2 + 80170a4: 1884703a and r2,r3,r2 + 80170a8: 1001703a wrctl status,r2 + return context; + 80170ac: e0bffb17 ldw r2,-20(fp) + if (prio != OS_PRIO_SELF) { + return (OS_ERR_PRIO_INVALID); + } + } +#endif + OS_ENTER_CRITICAL(); + 80170b0: e0bffe15 stw r2,-8(fp) + if (prio == OS_PRIO_SELF) { /* See if suspend SELF */ + 80170b4: e0bff703 ldbu r2,-36(fp) + 80170b8: 10803fd8 cmpnei r2,r2,255 + 80170bc: 1000061e bne r2,zero,80170d8 + prio = OSTCBCur->OSTCBPrio; + 80170c0: d0a05817 ldw r2,-32416(gp) + 80170c4: 10800c83 ldbu r2,50(r2) + 80170c8: e0bff705 stb r2,-36(fp) + self = OS_TRUE; + 80170cc: 00800044 movi r2,1 + 80170d0: e0bfffc5 stb r2,-1(fp) + 80170d4: 00000906 br 80170fc + } else if (prio == OSTCBCur->OSTCBPrio) { /* See if suspending self */ + 80170d8: d0a05817 ldw r2,-32416(gp) + 80170dc: 10800c83 ldbu r2,50(r2) + 80170e0: e0fff703 ldbu r3,-36(fp) + 80170e4: 10803fcc andi r2,r2,255 + 80170e8: 1880031e bne r3,r2,80170f8 + self = OS_TRUE; + 80170ec: 00800044 movi r2,1 + 80170f0: e0bfffc5 stb r2,-1(fp) + 80170f4: 00000106 br 80170fc + } else { + self = OS_FALSE; /* No suspending another task */ + 80170f8: e03fffc5 stb zero,-1(fp) + } + ptcb = OSTCBPrioTbl[prio]; + 80170fc: e0bff703 ldbu r2,-36(fp) + 8017100: 100690ba slli r3,r2,2 + 8017104: 008201b4 movhi r2,2054 + 8017108: 1885883a add r2,r3,r2 + 801710c: 10b55d17 ldw r2,-10892(r2) + 8017110: e0bffd15 stw r2,-12(fp) + if (ptcb == (OS_TCB *)0) { /* Task to suspend must exist */ + 8017114: e0bffd17 ldw r2,-12(fp) + 8017118: 1000061e bne r2,zero,8017134 + 801711c: e0bffe17 ldw r2,-8(fp) + 8017120: e0bffa15 stw r2,-24(fp) + NIOS2_WRITE_STATUS (context); + 8017124: e0bffa17 ldw r2,-24(fp) + 8017128: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_SUSPEND_PRIO); + 801712c: 00801204 movi r2,72 + 8017130: 00003606 br 801720c + } + if (ptcb == OS_TCB_RESERVED) { /* See if assigned to Mutex */ + 8017134: e0bffd17 ldw r2,-12(fp) + 8017138: 10800058 cmpnei r2,r2,1 + 801713c: 1000061e bne r2,zero,8017158 + 8017140: e0bffe17 ldw r2,-8(fp) + 8017144: e0bff915 stw r2,-28(fp) + 8017148: e0bff917 ldw r2,-28(fp) + 801714c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + 8017150: 008010c4 movi r2,67 + 8017154: 00002d06 br 801720c + } + y = ptcb->OSTCBY; + 8017158: e0bffd17 ldw r2,-12(fp) + 801715c: 10800d03 ldbu r2,52(r2) + 8017160: e0bffcc5 stb r2,-13(fp) + OSRdyTbl[y] &= ~ptcb->OSTCBBitX; /* Make task not ready */ + 8017164: e0fffcc3 ldbu r3,-13(fp) + 8017168: d0a05544 addi r2,gp,-32427 + 801716c: 1885883a add r2,r3,r2 + 8017170: 10800003 ldbu r2,0(r2) + 8017174: 1007883a mov r3,r2 + 8017178: e0bffd17 ldw r2,-12(fp) + 801717c: 10800d43 ldbu r2,53(r2) + 8017180: 0084303a nor r2,zero,r2 + 8017184: 1884703a and r2,r3,r2 + 8017188: e0fffcc3 ldbu r3,-13(fp) + 801718c: 1009883a mov r4,r2 + 8017190: d0a05544 addi r2,gp,-32427 + 8017194: 1885883a add r2,r3,r2 + 8017198: 11000005 stb r4,0(r2) + if (OSRdyTbl[y] == 0) { + 801719c: e0fffcc3 ldbu r3,-13(fp) + 80171a0: d0a05544 addi r2,gp,-32427 + 80171a4: 1885883a add r2,r3,r2 + 80171a8: 10800003 ldbu r2,0(r2) + 80171ac: 10803fcc andi r2,r2,255 + 80171b0: 1000071e bne r2,zero,80171d0 + OSRdyGrp &= ~ptcb->OSTCBBitY; + 80171b4: e0bffd17 ldw r2,-12(fp) + 80171b8: 10800d83 ldbu r2,54(r2) + 80171bc: 0084303a nor r2,zero,r2 + 80171c0: 1007883a mov r3,r2 + 80171c4: d0a05503 ldbu r2,-32428(gp) + 80171c8: 1884703a and r2,r3,r2 + 80171cc: d0a05505 stb r2,-32428(gp) + } + ptcb->OSTCBStat |= OS_STAT_SUSPEND; /* Status of task is 'SUSPENDED' */ + 80171d0: e0bffd17 ldw r2,-12(fp) + 80171d4: 10800c03 ldbu r2,48(r2) + 80171d8: 10800214 ori r2,r2,8 + 80171dc: 1007883a mov r3,r2 + 80171e0: e0bffd17 ldw r2,-12(fp) + 80171e4: 10c00c05 stb r3,48(r2) + 80171e8: e0bffe17 ldw r2,-8(fp) + 80171ec: e0bff815 stw r2,-32(fp) + 80171f0: e0bff817 ldw r2,-32(fp) + 80171f4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (self == OS_TRUE) { /* Context switch only if SELF */ + 80171f8: e0bfffc3 ldbu r2,-1(fp) + 80171fc: 10800058 cmpnei r2,r2,1 + 8017200: 1000011e bne r2,zero,8017208 + OS_Sched(); /* Find new highest priority task */ + 8017204: 801166c0 call 801166c + } + return (OS_ERR_NONE); + 8017208: 0005883a mov r2,zero +} + 801720c: e037883a mov sp,fp + 8017210: dfc00117 ldw ra,4(sp) + 8017214: df000017 ldw fp,0(sp) + 8017218: dec00204 addi sp,sp,8 + 801721c: f800283a ret + +08017220 : +********************************************************************************************************* +*/ + +#if OS_TASK_QUERY_EN > 0 +INT8U OSTaskQuery (INT8U prio, OS_TCB *p_task_data) +{ + 8017220: defff604 addi sp,sp,-40 + 8017224: dfc00915 stw ra,36(sp) + 8017228: df000815 stw fp,32(sp) + 801722c: df000804 addi fp,sp,32 + 8017230: 2005883a mov r2,r4 + 8017234: e17ff815 stw r5,-32(fp) + 8017238: e0bff905 stb r2,-28(fp) + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 801723c: e03fff15 stw zero,-4(fp) + NIOS2_READ_STATUS (context); + 8017240: 0005303a rdctl r2,status + 8017244: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8017248: e0fffd17 ldw r3,-12(fp) + 801724c: 00bfff84 movi r2,-2 + 8017250: 1884703a and r2,r3,r2 + 8017254: 1001703a wrctl status,r2 + return context; + 8017258: e0bffd17 ldw r2,-12(fp) + } + if (p_task_data == (OS_TCB *)0) { /* Validate 'p_task_data' */ + return (OS_ERR_PDATA_NULL); + } +#endif + OS_ENTER_CRITICAL(); + 801725c: e0bfff15 stw r2,-4(fp) + if (prio == OS_PRIO_SELF) { /* See if suspend SELF */ + 8017260: e0bff903 ldbu r2,-28(fp) + 8017264: 10803fd8 cmpnei r2,r2,255 + 8017268: 1000031e bne r2,zero,8017278 + prio = OSTCBCur->OSTCBPrio; + 801726c: d0a05817 ldw r2,-32416(gp) + 8017270: 10800c83 ldbu r2,50(r2) + 8017274: e0bff905 stb r2,-28(fp) + } + ptcb = OSTCBPrioTbl[prio]; + 8017278: e0bff903 ldbu r2,-28(fp) + 801727c: 100690ba slli r3,r2,2 + 8017280: 008201b4 movhi r2,2054 + 8017284: 1885883a add r2,r3,r2 + 8017288: 10b55d17 ldw r2,-10892(r2) + 801728c: e0bffe15 stw r2,-8(fp) + if (ptcb == (OS_TCB *)0) { /* Task to query must exist */ + 8017290: e0bffe17 ldw r2,-8(fp) + 8017294: 1000061e bne r2,zero,80172b0 + 8017298: e0bfff17 ldw r2,-4(fp) + 801729c: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 80172a0: e0bffc17 ldw r2,-16(fp) + 80172a4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_PRIO); + 80172a8: 00800a44 movi r2,41 + 80172ac: 00001206 br 80172f8 + } + if (ptcb == OS_TCB_RESERVED) { /* Task to query must not be assigned to a Mutex */ + 80172b0: e0bffe17 ldw r2,-8(fp) + 80172b4: 10800058 cmpnei r2,r2,1 + 80172b8: 1000061e bne r2,zero,80172d4 + 80172bc: e0bfff17 ldw r2,-4(fp) + 80172c0: e0bffb15 stw r2,-20(fp) + 80172c4: e0bffb17 ldw r2,-20(fp) + 80172c8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + 80172cc: 008010c4 movi r2,67 + 80172d0: 00000906 br 80172f8 + } + /* Copy TCB into user storage area */ + OS_MemCopy((INT8U *)p_task_data, (INT8U *)ptcb, sizeof(OS_TCB)); + 80172d4: 01801b04 movi r6,108 + 80172d8: e17ffe17 ldw r5,-8(fp) + 80172dc: e13ff817 ldw r4,-32(fp) + 80172e0: 80116040 call 8011604 + 80172e4: e0bfff17 ldw r2,-4(fp) + 80172e8: e0bffa15 stw r2,-24(fp) + 80172ec: e0bffa17 ldw r2,-24(fp) + 80172f0: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 80172f4: 0005883a mov r2,zero +} + 80172f8: e037883a mov sp,fp + 80172fc: dfc00117 ldw ra,4(sp) + 8017300: df000017 ldw fp,0(sp) + 8017304: dec00204 addi sp,sp,8 + 8017308: f800283a ret + +0801730c : +* Returns : none +********************************************************************************************************* +*/ + +void OSTimeDly (INT16U ticks) +{ + 801730c: defff904 addi sp,sp,-28 + 8017310: dfc00615 stw ra,24(sp) + 8017314: df000515 stw fp,20(sp) + 8017318: df000504 addi fp,sp,20 + 801731c: 2005883a mov r2,r4 + 8017320: e0bffb0d sth r2,-20(fp) + INT8U y; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8017324: e03fff15 stw zero,-4(fp) +#endif + + + + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 8017328: d0a05703 ldbu r2,-32420(gp) + 801732c: 10803fcc andi r2,r2,255 + 8017330: 1000311e bne r2,zero,80173f8 + return; + } + if (ticks > 0) { /* 0 means no delay! */ + 8017334: e0bffb0b ldhu r2,-20(fp) + 8017338: 10003026 beq r2,zero,80173fc + NIOS2_READ_STATUS (context); + 801733c: 0005303a rdctl r2,status + 8017340: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8017344: e0fffd17 ldw r3,-12(fp) + 8017348: 00bfff84 movi r2,-2 + 801734c: 1884703a and r2,r3,r2 + 8017350: 1001703a wrctl status,r2 + return context; + 8017354: e0bffd17 ldw r2,-12(fp) + OS_ENTER_CRITICAL(); + 8017358: e0bfff15 stw r2,-4(fp) + y = OSTCBCur->OSTCBY; /* Delay current task */ + 801735c: d0a05817 ldw r2,-32416(gp) + 8017360: 10800d03 ldbu r2,52(r2) + 8017364: e0bffec5 stb r2,-5(fp) + OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX; + 8017368: e0fffec3 ldbu r3,-5(fp) + 801736c: d0a05544 addi r2,gp,-32427 + 8017370: 1885883a add r2,r3,r2 + 8017374: 10800003 ldbu r2,0(r2) + 8017378: 1007883a mov r3,r2 + 801737c: d0a05817 ldw r2,-32416(gp) + 8017380: 10800d43 ldbu r2,53(r2) + 8017384: 0084303a nor r2,zero,r2 + 8017388: 1884703a and r2,r3,r2 + 801738c: e0fffec3 ldbu r3,-5(fp) + 8017390: 1009883a mov r4,r2 + 8017394: d0a05544 addi r2,gp,-32427 + 8017398: 1885883a add r2,r3,r2 + 801739c: 11000005 stb r4,0(r2) + if (OSRdyTbl[y] == 0) { + 80173a0: e0fffec3 ldbu r3,-5(fp) + 80173a4: d0a05544 addi r2,gp,-32427 + 80173a8: 1885883a add r2,r3,r2 + 80173ac: 10800003 ldbu r2,0(r2) + 80173b0: 10803fcc andi r2,r2,255 + 80173b4: 1000071e bne r2,zero,80173d4 + OSRdyGrp &= ~OSTCBCur->OSTCBBitY; + 80173b8: d0a05817 ldw r2,-32416(gp) + 80173bc: 10800d83 ldbu r2,54(r2) + 80173c0: 0084303a nor r2,zero,r2 + 80173c4: 1007883a mov r3,r2 + 80173c8: d0a05503 ldbu r2,-32428(gp) + 80173cc: 1884703a and r2,r3,r2 + 80173d0: d0a05505 stb r2,-32428(gp) + } + OSTCBCur->OSTCBDly = ticks; /* Load ticks in TCB */ + 80173d4: d0a05817 ldw r2,-32416(gp) + 80173d8: e0fffb0b ldhu r3,-20(fp) + 80173dc: 10c00b8d sth r3,46(r2) + 80173e0: e0bfff17 ldw r2,-4(fp) + 80173e4: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 80173e8: e0bffc17 ldw r2,-16(fp) + 80173ec: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next task to run! */ + 80173f0: 801166c0 call 801166c + 80173f4: 00000106 br 80173fc + return; + 80173f8: 0001883a nop + } +} + 80173fc: e037883a mov sp,fp + 8017400: dfc00117 ldw ra,4(sp) + 8017404: df000017 ldw fp,0(sp) + 8017408: dec00204 addi sp,sp,8 + 801740c: f800283a ret + +08017410 : +********************************************************************************************************* +*/ + +#if OS_TIME_DLY_HMSM_EN > 0 +INT8U OSTimeDlyHMSM (INT8U hours, INT8U minutes, INT8U seconds, INT16U ms) +{ + 8017410: defff704 addi sp,sp,-36 + 8017414: dfc00815 stw ra,32(sp) + 8017418: df000715 stw fp,28(sp) + 801741c: dc000615 stw r16,24(sp) + 8017420: df000704 addi fp,sp,28 + 8017424: 2005883a mov r2,r4 + 8017428: 3009883a mov r4,r6 + 801742c: 3807883a mov r3,r7 + 8017430: e0bffc05 stb r2,-16(fp) + 8017434: 2805883a mov r2,r5 + 8017438: e0bffb05 stb r2,-20(fp) + 801743c: 2005883a mov r2,r4 + 8017440: e0bffa05 stb r2,-24(fp) + 8017444: 1805883a mov r2,r3 + 8017448: e0bff90d sth r2,-28(fp) + INT32U ticks; + INT16U loops; + + + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 801744c: d0a05703 ldbu r2,-32420(gp) + 8017450: 10803fcc andi r2,r2,255 + 8017454: 10000226 beq r2,zero,8017460 + return (OS_ERR_TIME_DLY_ISR); + 8017458: 00801544 movi r2,85 + 801745c: 00002506 br 80174f4 + return (OS_ERR_TIME_INVALID_MS); + } +#endif + /* Compute the total number of clock ticks required.. */ + /* .. (rounded to the nearest tick) */ + ticks = ((INT32U)hours * 3600L + (INT32U)minutes * 60L + (INT32U)seconds) * OS_TICKS_PER_SEC + 8017460: e0bffc03 ldbu r2,-16(fp) + 8017464: 10c38424 muli r3,r2,3600 + 8017468: e0bffb03 ldbu r2,-20(fp) + 801746c: 10800f24 muli r2,r2,60 + 8017470: 1887883a add r3,r3,r2 + 8017474: e0bffa03 ldbu r2,-24(fp) + 8017478: 1885883a add r2,r3,r2 + 801747c: 14001924 muli r16,r2,100 + + OS_TICKS_PER_SEC * ((INT32U)ms + 500L / OS_TICKS_PER_SEC) / 1000L; + 8017480: e0bff90b ldhu r2,-28(fp) + 8017484: 10801924 muli r2,r2,100 + 8017488: 10807d04 addi r2,r2,500 + 801748c: 0140fa04 movi r5,1000 + 8017490: 1009883a mov r4,r2 + 8017494: 800cff80 call 800cff8 <__udivsi3> + ticks = ((INT32U)hours * 3600L + (INT32U)minutes * 60L + (INT32U)seconds) * OS_TICKS_PER_SEC + 8017498: 8085883a add r2,r16,r2 + 801749c: e0bffd15 stw r2,-12(fp) + loops = (INT16U)(ticks >> 16); /* Compute the integral number of 65536 tick delays */ + 80174a0: e0bffd17 ldw r2,-12(fp) + 80174a4: 1004d43a srli r2,r2,16 + 80174a8: e0bffe8d sth r2,-6(fp) + ticks = ticks & 0xFFFFL; /* Obtain the fractional number of ticks */ + 80174ac: e0bffd17 ldw r2,-12(fp) + 80174b0: 10bfffcc andi r2,r2,65535 + 80174b4: e0bffd15 stw r2,-12(fp) + OSTimeDly((INT16U)ticks); + 80174b8: e0bffd17 ldw r2,-12(fp) + 80174bc: 10bfffcc andi r2,r2,65535 + 80174c0: 1009883a mov r4,r2 + 80174c4: 801730c0 call 801730c + while (loops > 0) { + 80174c8: 00000706 br 80174e8 + OSTimeDly((INT16U)32768u); + 80174cc: 01200014 movui r4,32768 + 80174d0: 801730c0 call 801730c + OSTimeDly((INT16U)32768u); + 80174d4: 01200014 movui r4,32768 + 80174d8: 801730c0 call 801730c + loops--; + 80174dc: e0bffe8b ldhu r2,-6(fp) + 80174e0: 10bfffc4 addi r2,r2,-1 + 80174e4: e0bffe8d sth r2,-6(fp) + while (loops > 0) { + 80174e8: e0bffe8b ldhu r2,-6(fp) + 80174ec: 103ff71e bne r2,zero,80174cc + } + return (OS_ERR_NONE); + 80174f0: 0005883a mov r2,zero +} + 80174f4: e6ffff04 addi sp,fp,-4 + 80174f8: dfc00217 ldw ra,8(sp) + 80174fc: df000117 ldw fp,4(sp) + 8017500: dc000017 ldw r16,0(sp) + 8017504: dec00304 addi sp,sp,12 + 8017508: f800283a ret + +0801750c : +********************************************************************************************************* +*/ + +#if OS_TIME_DLY_RESUME_EN > 0 +INT8U OSTimeDlyResume (INT8U prio) +{ + 801750c: defff504 addi sp,sp,-44 + 8017510: dfc00a15 stw ra,40(sp) + 8017514: df000915 stw fp,36(sp) + 8017518: df000904 addi fp,sp,36 + 801751c: 2005883a mov r2,r4 + 8017520: e0bff705 stb r2,-36(fp) + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8017524: e03fff15 stw zero,-4(fp) +#endif + + + + if (prio >= OS_LOWEST_PRIO) { + 8017528: e0bff703 ldbu r2,-36(fp) + 801752c: 10800530 cmpltui r2,r2,20 + 8017530: 1000021e bne r2,zero,801753c + return (OS_ERR_PRIO_INVALID); + 8017534: 00800a84 movi r2,42 + 8017538: 00006206 br 80176c4 + NIOS2_READ_STATUS (context); + 801753c: 0005303a rdctl r2,status + 8017540: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8017544: e0fffd17 ldw r3,-12(fp) + 8017548: 00bfff84 movi r2,-2 + 801754c: 1884703a and r2,r3,r2 + 8017550: 1001703a wrctl status,r2 + return context; + 8017554: e0bffd17 ldw r2,-12(fp) + } + OS_ENTER_CRITICAL(); + 8017558: e0bfff15 stw r2,-4(fp) + ptcb = OSTCBPrioTbl[prio]; /* Make sure that task exist */ + 801755c: e0bff703 ldbu r2,-36(fp) + 8017560: 100690ba slli r3,r2,2 + 8017564: 008201b4 movhi r2,2054 + 8017568: 1885883a add r2,r3,r2 + 801756c: 10b55d17 ldw r2,-10892(r2) + 8017570: e0bffe15 stw r2,-8(fp) + if (ptcb == (OS_TCB *)0) { + 8017574: e0bffe17 ldw r2,-8(fp) + 8017578: 1000061e bne r2,zero,8017594 + 801757c: e0bfff17 ldw r2,-4(fp) + 8017580: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 8017584: e0bffc17 ldw r2,-16(fp) + 8017588: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); /* The task does not exist */ + 801758c: 008010c4 movi r2,67 + 8017590: 00004c06 br 80176c4 + } + if (ptcb == OS_TCB_RESERVED) { + 8017594: e0bffe17 ldw r2,-8(fp) + 8017598: 10800058 cmpnei r2,r2,1 + 801759c: 1000061e bne r2,zero,80175b8 + 80175a0: e0bfff17 ldw r2,-4(fp) + 80175a4: e0bffb15 stw r2,-20(fp) + 80175a8: e0bffb17 ldw r2,-20(fp) + 80175ac: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); /* The task does not exist */ + 80175b0: 008010c4 movi r2,67 + 80175b4: 00004306 br 80176c4 + } + if (ptcb->OSTCBDly == 0) { /* See if task is delayed */ + 80175b8: e0bffe17 ldw r2,-8(fp) + 80175bc: 10800b8b ldhu r2,46(r2) + 80175c0: 10bfffcc andi r2,r2,65535 + 80175c4: 1000061e bne r2,zero,80175e0 + 80175c8: e0bfff17 ldw r2,-4(fp) + 80175cc: e0bffa15 stw r2,-24(fp) + 80175d0: e0bffa17 ldw r2,-24(fp) + 80175d4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TIME_NOT_DLY); /* Indicate that task was not delayed */ + 80175d8: 00801404 movi r2,80 + 80175dc: 00003906 br 80176c4 + } + + ptcb->OSTCBDly = 0; /* Clear the time delay */ + 80175e0: e0bffe17 ldw r2,-8(fp) + 80175e4: 10000b8d sth zero,46(r2) + if ((ptcb->OSTCBStat & OS_STAT_PEND_ANY) != OS_STAT_RDY) { + 80175e8: e0bffe17 ldw r2,-8(fp) + 80175ec: 10800c03 ldbu r2,48(r2) + 80175f0: 10803fcc andi r2,r2,255 + 80175f4: 10800dcc andi r2,r2,55 + 80175f8: 10000b26 beq r2,zero,8017628 + ptcb->OSTCBStat &= ~OS_STAT_PEND_ANY; /* Yes, Clear status flag */ + 80175fc: e0bffe17 ldw r2,-8(fp) + 8017600: 10c00c03 ldbu r3,48(r2) + 8017604: 00bff204 movi r2,-56 + 8017608: 1884703a and r2,r3,r2 + 801760c: 1007883a mov r3,r2 + 8017610: e0bffe17 ldw r2,-8(fp) + 8017614: 10c00c05 stb r3,48(r2) + ptcb->OSTCBStatPend = OS_STAT_PEND_TO; /* Indicate PEND timeout */ + 8017618: e0bffe17 ldw r2,-8(fp) + 801761c: 00c00044 movi r3,1 + 8017620: 10c00c45 stb r3,49(r2) + 8017624: 00000206 br 8017630 + } else { + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; + 8017628: e0bffe17 ldw r2,-8(fp) + 801762c: 10000c45 stb zero,49(r2) + } + if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) == OS_STAT_RDY) { /* Is task suspended? */ + 8017630: e0bffe17 ldw r2,-8(fp) + 8017634: 10800c03 ldbu r2,48(r2) + 8017638: 10803fcc andi r2,r2,255 + 801763c: 1080020c andi r2,r2,8 + 8017640: 10001b1e bne r2,zero,80176b0 + OSRdyGrp |= ptcb->OSTCBBitY; /* No, Make ready */ + 8017644: e0bffe17 ldw r2,-8(fp) + 8017648: 10c00d83 ldbu r3,54(r2) + 801764c: d0a05503 ldbu r2,-32428(gp) + 8017650: 1884b03a or r2,r3,r2 + 8017654: d0a05505 stb r2,-32428(gp) + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + 8017658: e0bffe17 ldw r2,-8(fp) + 801765c: 10800d03 ldbu r2,52(r2) + 8017660: 10c03fcc andi r3,r2,255 + 8017664: d0a05544 addi r2,gp,-32427 + 8017668: 1885883a add r2,r3,r2 + 801766c: 11000003 ldbu r4,0(r2) + 8017670: e0bffe17 ldw r2,-8(fp) + 8017674: 10800d43 ldbu r2,53(r2) + 8017678: e0fffe17 ldw r3,-8(fp) + 801767c: 18c00d03 ldbu r3,52(r3) + 8017680: 18c03fcc andi r3,r3,255 + 8017684: 2084b03a or r2,r4,r2 + 8017688: 1009883a mov r4,r2 + 801768c: d0a05544 addi r2,gp,-32427 + 8017690: 1885883a add r2,r3,r2 + 8017694: 11000005 stb r4,0(r2) + 8017698: e0bfff17 ldw r2,-4(fp) + 801769c: e0bff915 stw r2,-28(fp) + 80176a0: e0bff917 ldw r2,-28(fp) + 80176a4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* See if this is new highest priority */ + 80176a8: 801166c0 call 801166c + 80176ac: 00000406 br 80176c0 + 80176b0: e0bfff17 ldw r2,-4(fp) + 80176b4: e0bff815 stw r2,-32(fp) + 80176b8: e0bff817 ldw r2,-32(fp) + 80176bc: 1001703a wrctl status,r2 + } else { + OS_EXIT_CRITICAL(); /* Task may be suspended */ + } + return (OS_ERR_NONE); + 80176c0: 0005883a mov r2,zero +} + 80176c4: e037883a mov sp,fp + 80176c8: dfc00117 ldw ra,4(sp) + 80176cc: df000017 ldw fp,0(sp) + 80176d0: dec00204 addi sp,sp,8 + 80176d4: f800283a ret + +080176d8 : +********************************************************************************************************* +*/ + +#if OS_TIME_GET_SET_EN > 0 +INT32U OSTimeGet (void) +{ + 80176d8: defffb04 addi sp,sp,-20 + 80176dc: df000415 stw fp,16(sp) + 80176e0: df000404 addi fp,sp,16 + INT32U ticks; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 80176e4: e03fff15 stw zero,-4(fp) + NIOS2_READ_STATUS (context); + 80176e8: 0005303a rdctl r2,status + 80176ec: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 80176f0: e0fffc17 ldw r3,-16(fp) + 80176f4: 00bfff84 movi r2,-2 + 80176f8: 1884703a and r2,r3,r2 + 80176fc: 1001703a wrctl status,r2 + return context; + 8017700: e0bffc17 ldw r2,-16(fp) +#endif + + + + OS_ENTER_CRITICAL(); + 8017704: e0bfff15 stw r2,-4(fp) + ticks = OSTime; + 8017708: d0a05917 ldw r2,-32412(gp) + 801770c: e0bffe15 stw r2,-8(fp) + 8017710: e0bfff17 ldw r2,-4(fp) + 8017714: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context); + 8017718: e0bffd17 ldw r2,-12(fp) + 801771c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (ticks); + 8017720: e0bffe17 ldw r2,-8(fp) +} + 8017724: e037883a mov sp,fp + 8017728: df000017 ldw fp,0(sp) + 801772c: dec00104 addi sp,sp,4 + 8017730: f800283a ret + +08017734 : +********************************************************************************************************* +*/ + +#if OS_TIME_GET_SET_EN > 0 +void OSTimeSet (INT32U ticks) +{ + 8017734: defffb04 addi sp,sp,-20 + 8017738: df000415 stw fp,16(sp) + 801773c: df000404 addi fp,sp,16 + 8017740: e13ffc15 stw r4,-16(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 8017744: e03fff15 stw zero,-4(fp) + NIOS2_READ_STATUS (context); + 8017748: 0005303a rdctl r2,status + 801774c: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8017750: e0fffd17 ldw r3,-12(fp) + 8017754: 00bfff84 movi r2,-2 + 8017758: 1884703a and r2,r3,r2 + 801775c: 1001703a wrctl status,r2 + return context; + 8017760: e0bffd17 ldw r2,-12(fp) +#endif + + + + OS_ENTER_CRITICAL(); + 8017764: e0bfff15 stw r2,-4(fp) + OSTime = ticks; + 8017768: e0bffc17 ldw r2,-16(fp) + 801776c: d0a05915 stw r2,-32412(gp) + 8017770: e0bfff17 ldw r2,-4(fp) + 8017774: e0bffe15 stw r2,-8(fp) + NIOS2_WRITE_STATUS (context); + 8017778: e0bffe17 ldw r2,-8(fp) + 801777c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); +} + 8017780: 0001883a nop + 8017784: e037883a mov sp,fp + 8017788: df000017 ldw fp,0(sp) + 801778c: dec00104 addi sp,sp,4 + 8017790: f800283a ret + +08017794 : + */ + +extern int alt_fs_reg (alt_dev* dev); + +static ALT_INLINE int alt_dev_reg (alt_dev* dev) +{ + 8017794: defffd04 addi sp,sp,-12 + 8017798: dfc00215 stw ra,8(sp) + 801779c: df000115 stw fp,4(sp) + 80177a0: df000104 addi fp,sp,4 + 80177a4: e13fff15 stw r4,-4(fp) + extern alt_llist alt_dev_list; + + return alt_dev_llist_insert ((alt_dev_llist*) dev, &alt_dev_list); + 80177a8: d1602404 addi r5,gp,-32624 + 80177ac: e13fff17 ldw r4,-4(fp) + 80177b0: 80372a00 call 80372a0 +} + 80177b4: e037883a mov sp,fp + 80177b8: dfc00117 ldw ra,4(sp) + 80177bc: df000017 ldw fp,0(sp) + 80177c0: dec00204 addi sp,sp,8 + 80177c4: f800283a ret + +080177c8 : + * The "base" parameter is ignored and only + * present for backwards-compatibility. + */ + +void alt_irq_init ( const void* base ) +{ + 80177c8: defffd04 addi sp,sp,-12 + 80177cc: dfc00215 stw ra,8(sp) + 80177d0: df000115 stw fp,4(sp) + 80177d4: df000104 addi fp,sp,4 + 80177d8: e13fff15 stw r4,-4(fp) + ALTERA_NIOS2_GEN2_IRQ_INIT ( CPU, cpu); + 80177dc: 80383640 call 8038364 + NIOS2_WRITE_STATUS(NIOS2_STATUS_PIE_MSK + 80177e0: 00800044 movi r2,1 + 80177e4: 1001703a wrctl status,r2 + alt_irq_cpu_enable_interrupts(); +} + 80177e8: 0001883a nop + 80177ec: e037883a mov sp,fp + 80177f0: dfc00117 ldw ra,4(sp) + 80177f4: df000017 ldw fp,0(sp) + 80177f8: dec00204 addi sp,sp,8 + 80177fc: f800283a ret + +08017800 : + * Initialize the non-interrupt controller devices. + * Called after alt_irq_init(). + */ + +void alt_sys_init( void ) +{ + 8017800: defffa04 addi sp,sp,-24 + 8017804: dfc00515 stw ra,20(sp) + 8017808: df000415 stw fp,16(sp) + 801780c: df000404 addi fp,sp,16 + ALTERA_AVALON_TIMER_INIT ( FRAME_TIMER, frame_timer); + ALTERA_AVALON_TIMER_INIT ( SYS_CLK_TIMER, sys_clk_timer); + 8017810: 01c01904 movi r7,100 + 8017814: 000d883a mov r6,zero + 8017818: 000b883a mov r5,zero + 801781c: 01061034 movhi r4,6208 + 8017820: 210f1804 addi r4,r4,15456 + 8017824: 8017aa40 call 8017aa4 + ALTERA_AVALON_SYSID_QSYS_INIT ( SYSID, sysid); + 8017828: 0001883a nop + ALTERA_AVALON_UART_INIT ( DEBUG_UART, debug_uart); + 801782c: 01800104 movi r6,4 + 8017830: 000b883a mov r5,zero + 8017834: 01020174 movhi r4,2053 + 8017838: 21311204 addi r4,r4,-15288 + 801783c: 801cb500 call 801cb50 + 8017840: 01020174 movhi r4,2053 + 8017844: 21310804 addi r4,r4,-15328 + 8017848: 80177940 call 8017794 + ALTERA_ETH_TSE_INIT ( ETH_TSE, eth_tse); + 801784c: e03fff15 stw zero,-4(fp) + 8017850: 00800044 movi r2,1 + 8017854: e0bffe15 stw r2,-8(fp) + 8017858: e0bffe17 ldw r2,-8(fp) + 801785c: 00800216 blt zero,r2,8017868 + 8017860: 00800044 movi r2,1 + 8017864: e0bffe15 stw r2,-8(fp) + 8017868: e03fff15 stw zero,-4(fp) + 801786c: 00004e06 br 80179a8 + 8017870: e0bfff17 ldw r2,-4(fp) + 8017874: 10c00724 muli r3,r2,28 + 8017878: 008201b4 movhi r2,2054 + 801787c: 1885883a add r2,r3,r2 + 8017880: 10357215 stw zero,-10808(r2) + 8017884: e0bfff17 ldw r2,-4(fp) + 8017888: 10c00724 muli r3,r2,28 + 801788c: 008201b4 movhi r2,2054 + 8017890: 1885883a add r2,r3,r2 + 8017894: 10357315 stw zero,-10804(r2) + 8017898: d0e00917 ldw r3,-32732(gp) + 801789c: e0bfff17 ldw r2,-4(fp) + 80178a0: 11000724 muli r4,r2,28 + 80178a4: 008201b4 movhi r2,2054 + 80178a8: 2085883a add r2,r4,r2 + 80178ac: 10f57415 stw r3,-10800(r2) + 80178b0: e0bfff17 ldw r2,-4(fp) + 80178b4: 11000724 muli r4,r2,28 + 80178b8: 00c200b4 movhi r3,2050 + 80178bc: 18c43604 addi r3,r3,4312 + 80178c0: 008201b4 movhi r2,2054 + 80178c4: 2085883a add r2,r4,r2 + 80178c8: 10f57515 stw r3,-10796(r2) + 80178cc: e0bfff17 ldw r2,-4(fp) + 80178d0: 10c00724 muli r3,r2,28 + 80178d4: 008201b4 movhi r2,2054 + 80178d8: 10b57204 addi r2,r2,-10808 + 80178dc: 1885883a add r2,r3,r2 + 80178e0: d0e00f04 addi r3,gp,-32708 + 80178e4: e0fffd15 stw r3,-12(fp) + 80178e8: e0bffc15 stw r2,-16(fp) + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_insert(alt_llist* list, + alt_llist* entry) +{ + entry->previous = list; + 80178ec: e0bffc17 ldw r2,-16(fp) + 80178f0: e0fffd17 ldw r3,-12(fp) + 80178f4: 10c00115 stw r3,4(r2) + entry->next = list->next; + 80178f8: e0bffd17 ldw r2,-12(fp) + 80178fc: 10c00017 ldw r3,0(r2) + 8017900: e0bffc17 ldw r2,-16(fp) + 8017904: 10c00015 stw r3,0(r2) + + list->next->previous = entry; + 8017908: e0bffd17 ldw r2,-12(fp) + 801790c: 10800017 ldw r2,0(r2) + 8017910: e0fffc17 ldw r3,-16(fp) + 8017914: 10c00115 stw r3,4(r2) + list->next = entry; + 8017918: e0bffd17 ldw r2,-12(fp) + 801791c: e0fffc17 ldw r3,-16(fp) + 8017920: 10c00015 stw r3,0(r2) + 8017924: d0a05c03 ldbu r2,-32400(gp) + 8017928: 11003fcc andi r4,r2,255 + 801792c: e0bfff17 ldw r2,-4(fp) + 8017930: 10c00724 muli r3,r2,28 + 8017934: 008201b4 movhi r2,2054 + 8017938: 10b57204 addi r2,r2,-10808 + 801793c: 1887883a add r3,r3,r2 + 8017940: 21000324 muli r4,r4,12 + 8017944: 008201b4 movhi r2,2054 + 8017948: 2085883a add r2,r4,r2 + 801794c: 10f5b615 stw r3,-10536(r2) + 8017950: d0a05c03 ldbu r2,-32400(gp) + 8017954: 10803fcc andi r2,r2,255 + 8017958: 11000324 muli r4,r2,12 + 801795c: 00c61034 movhi r3,6208 + 8017960: 18cc0004 addi r3,r3,12288 + 8017964: 008201b4 movhi r2,2054 + 8017968: 2085883a add r2,r4,r2 + 801796c: 10f5b715 stw r3,-10532(r2) + 8017970: d0a05c03 ldbu r2,-32400(gp) + 8017974: 10803fcc andi r2,r2,255 + 8017978: e0ffff17 ldw r3,-4(fp) + 801797c: 1809883a mov r4,r3 + 8017980: 10c00324 muli r3,r2,12 + 8017984: 008201b4 movhi r2,2054 + 8017988: 1885883a add r2,r3,r2 + 801798c: 1135b805 stb r4,-10528(r2) + 8017990: d0a05c03 ldbu r2,-32400(gp) + 8017994: 10800044 addi r2,r2,1 + 8017998: d0a05c05 stb r2,-32400(gp) + 801799c: e0bfff17 ldw r2,-4(fp) + 80179a0: 10800044 addi r2,r2,1 + 80179a4: e0bfff15 stw r2,-4(fp) + 80179a8: e0ffff17 ldw r3,-4(fp) + 80179ac: e0bffe17 ldw r2,-8(fp) + 80179b0: 18bfaf16 blt r3,r2,8017870 + ALTERA_GENERIC_QUAD_SPI_CONTROLLER_INIT ( EXT_FLASH, ext_flash); + 80179b4: 01020174 movhi r4,2053 + 80179b8: 21313c04 addi r4,r4,-15120 + 80179bc: 801dd200 call 801dd20 + ALTERA_MSGDMA_INIT ( MSGDMA_RX, msgdma_rx); + 80179c0: 00820174 movhi r2,2053 + 80179c4: 10f17b17 ldw r3,-14868(r2) + 80179c8: 00820174 movhi r2,2053 + 80179cc: 10b17c17 ldw r2,-14864(r2) + 80179d0: 100d883a mov r6,r2 + 80179d4: 180b883a mov r5,r3 + 80179d8: 01020174 movhi r4,2053 + 80179dc: 21317404 addi r4,r4,-14896 + 80179e0: 801feec0 call 801feec + ALTERA_MSGDMA_INIT ( MSGDMA_TX, msgdma_tx); + 80179e4: 00820174 movhi r2,2053 + 80179e8: 10f19717 ldw r3,-14756(r2) + 80179ec: 00820174 movhi r2,2053 + 80179f0: 10b19817 ldw r2,-14752(r2) + 80179f4: 100d883a mov r6,r2 + 80179f8: 180b883a mov r5,r3 + 80179fc: 01020174 movhi r4,2053 + 8017a00: 21319004 addi r4,r4,-14784 + 8017a04: 801feec0 call 801feec + ALTERA_ONCHIP_FLASH_INIT ( ONCHIP_FLASH, onchip_flash); + 8017a08: 01020174 movhi r4,2053 + 8017a0c: 2131ac04 addi r4,r4,-14672 + 8017a10: 8020a800 call 8020a80 +} + 8017a14: 0001883a nop + 8017a18: e037883a mov sp,fp + 8017a1c: dfc00117 ldw ra,4(sp) + 8017a20: df000017 ldw fp,0(sp) + 8017a24: dec00204 addi sp,sp,8 + 8017a28: f800283a ret + +08017a2c : +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void alt_avalon_timer_sc_irq (void* base) +#else +static void alt_avalon_timer_sc_irq (void* base, alt_u32 id) +#endif +{ + 8017a2c: defffa04 addi sp,sp,-24 + 8017a30: dfc00515 stw ra,20(sp) + 8017a34: df000415 stw fp,16(sp) + 8017a38: df000404 addi fp,sp,16 + 8017a3c: e13ffc15 stw r4,-16(fp) + alt_irq_context cpu_sr; + + /* clear the interrupt */ + IOWR_ALTERA_AVALON_TIMER_STATUS (base, 0); + 8017a40: 0007883a mov r3,zero + 8017a44: e0bffc17 ldw r2,-16(fp) + 8017a48: 10c00035 stwio r3,0(r2) + /* + * Dummy read to ensure IRQ is negated before the ISR returns. + * The control register is read because reading the status + * register has side-effects per the register map documentation. + */ + IORD_ALTERA_AVALON_TIMER_CONTROL (base); + 8017a4c: e0bffc17 ldw r2,-16(fp) + 8017a50: 10800104 addi r2,r2,4 + 8017a54: 10800037 ldwio r2,0(r2) + NIOS2_READ_STATUS (context); + 8017a58: 0005303a rdctl r2,status + 8017a5c: e0bffd15 stw r2,-12(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8017a60: e0fffd17 ldw r3,-12(fp) + 8017a64: 00bfff84 movi r2,-2 + 8017a68: 1884703a and r2,r3,r2 + 8017a6c: 1001703a wrctl status,r2 + return context; + 8017a70: e0bffd17 ldw r2,-12(fp) + + /* + * Notify the system of a clock tick. disable interrupts + * during this time to safely support ISR preemption + */ + cpu_sr = alt_irq_disable_all(); + 8017a74: e0bfff15 stw r2,-4(fp) + alt_tick (); + 8017a78: 8037f580 call 8037f58 + 8017a7c: e0bfff17 ldw r2,-4(fp) + 8017a80: e0bffe15 stw r2,-8(fp) + NIOS2_WRITE_STATUS (context); + 8017a84: e0bffe17 ldw r2,-8(fp) + 8017a88: 1001703a wrctl status,r2 + alt_irq_enable_all(cpu_sr); +} + 8017a8c: 0001883a nop + 8017a90: e037883a mov sp,fp + 8017a94: dfc00117 ldw ra,4(sp) + 8017a98: df000017 ldw fp,0(sp) + 8017a9c: dec00204 addi sp,sp,8 + 8017aa0: f800283a ret + +08017aa4 : + * auto-generated alt_sys_init() function. + */ + +void alt_avalon_timer_sc_init (void* base, alt_u32 irq_controller_id, + alt_u32 irq, alt_u32 freq) +{ + 8017aa4: defff804 addi sp,sp,-32 + 8017aa8: dfc00715 stw ra,28(sp) + 8017aac: df000615 stw fp,24(sp) + 8017ab0: df000604 addi fp,sp,24 + 8017ab4: e13ffe15 stw r4,-8(fp) + 8017ab8: e17ffd15 stw r5,-12(fp) + 8017abc: e1bffc15 stw r6,-16(fp) + 8017ac0: e1fffb15 stw r7,-20(fp) + 8017ac4: e0bffb17 ldw r2,-20(fp) + 8017ac8: e0bfff15 stw r2,-4(fp) + * in order to initialise the value of the clock frequency. + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sysclk_init (alt_u32 nticks) +{ + if (! _alt_tick_rate) + 8017acc: d0a08d17 ldw r2,-32204(gp) + 8017ad0: 1000021e bne r2,zero,8017adc + { + _alt_tick_rate = nticks; + 8017ad4: e0bfff17 ldw r2,-4(fp) + 8017ad8: d0a08d15 stw r2,-32204(gp) + + alt_sysclk_init (freq); + + /* set to free running mode */ + + IOWR_ALTERA_AVALON_TIMER_CONTROL (base, + 8017adc: e0bffe17 ldw r2,-8(fp) + 8017ae0: 10800104 addi r2,r2,4 + 8017ae4: 00c001c4 movi r3,7 + 8017ae8: 10c00035 stwio r3,0(r2) + ALTERA_AVALON_TIMER_CONTROL_CONT_MSK | + ALTERA_AVALON_TIMER_CONTROL_START_MSK); + + /* register the interrupt handler, and enable the interrupt */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_ic_isr_register(irq_controller_id, irq, alt_avalon_timer_sc_irq, + 8017aec: d8000015 stw zero,0(sp) + 8017af0: e1fffe17 ldw r7,-8(fp) + 8017af4: 01820074 movhi r6,2049 + 8017af8: 319e8b04 addi r6,r6,31276 + 8017afc: e17ffc17 ldw r5,-16(fp) + 8017b00: e13ffd17 ldw r4,-12(fp) + 8017b04: 80374940 call 8037494 + base, NULL); +#else + alt_irq_register (irq, base, alt_avalon_timer_sc_irq); +#endif +} + 8017b08: 0001883a nop + 8017b0c: e037883a mov sp,fp + 8017b10: dfc00117 ldw ra,4(sp) + 8017b14: df000017 ldw fp,0(sp) + 8017b18: dec00204 addi sp,sp,8 + 8017b1c: f800283a ret + +08017b20 : +#include +#include +#include +#include + +void no_printf (char *fmt, ...) {} + 8017b20: defffb04 addi sp,sp,-20 + 8017b24: df000115 stw fp,4(sp) + 8017b28: df000104 addi fp,sp,4 + 8017b2c: e13fff15 stw r4,-4(fp) + 8017b30: e1400115 stw r5,4(fp) + 8017b34: e1800215 stw r6,8(fp) + 8017b38: e1c00315 stw r7,12(fp) + 8017b3c: 0001883a nop + 8017b40: e037883a mov sp,fp + 8017b44: df000017 ldw fp,0(sp) + 8017b48: dec00404 addi sp,sp,16 + 8017b4c: f800283a ret + +08017b50 : + +alt_32 tse_mac_initTransInfo2( tse_mac_trans_info *mi, + alt_u32 mac_base, + alt_32 tx_msgdma, + alt_32 rx_msgdma, + alt_32 cfgflags) { + 8017b50: defffb04 addi sp,sp,-20 + 8017b54: df000415 stw fp,16(sp) + 8017b58: df000404 addi fp,sp,16 + 8017b5c: e13fff15 stw r4,-4(fp) + 8017b60: e17ffe15 stw r5,-8(fp) + 8017b64: e1bffd15 stw r6,-12(fp) + 8017b68: e1fffc15 stw r7,-16(fp) + + mi->base = (np_tse_mac*)mac_base; + 8017b6c: e0fffe17 ldw r3,-8(fp) + 8017b70: e0bfff17 ldw r2,-4(fp) + 8017b74: 10c00015 stw r3,0(r2) + mi->tx_msgdma = (alt_msgdma_dev *)tx_msgdma; + 8017b78: e0fffd17 ldw r3,-12(fp) + 8017b7c: e0bfff17 ldw r2,-4(fp) + 8017b80: 10c00115 stw r3,4(r2) + mi->rx_msgdma = (alt_msgdma_dev *)rx_msgdma; + 8017b84: e0fffc17 ldw r3,-16(fp) + 8017b88: e0bfff17 ldw r2,-4(fp) + 8017b8c: 10c00215 stw r3,8(r2) + mi->cfgflags = cfgflags; + 8017b90: e0c00117 ldw r3,4(fp) + 8017b94: e0bfff17 ldw r2,-4(fp) + 8017b98: 10c00415 stw r3,16(r2) + return SUCCESS; + 8017b9c: 0005883a mov r2,zero +} + 8017ba0: e037883a mov sp,fp + 8017ba4: df000017 ldw fp,0(sp) + 8017ba8: dec00104 addi sp,sp,4 + 8017bac: f800283a ret + +08017bb0 : + * @param txDesc Pointer to the transmit MSGDMA descriptor + * @return actual bytes transferred if ok, else error (-1) + */ +alt_32 tse_mac_sTxWrite( tse_mac_trans_info *mi, + alt_msgdma_standard_descriptor *txDesc) +{ + 8017bb0: defffa04 addi sp,sp,-24 + 8017bb4: dfc00515 stw ra,20(sp) + 8017bb8: df000415 stw fp,16(sp) + 8017bbc: df000404 addi fp,sp,16 + 8017bc0: e13ffd15 stw r4,-12(fp) + 8017bc4: e17ffc15 stw r5,-16(fp) + + alt_32 timeout; + alt_u8 result = 0; + 8017bc8: e03ffec5 stb zero,-5(fp) + + // Make sure DMA controller is not busy from a former command + // and TX is able to accept data + timeout = 0; + 8017bcc: e03fff15 stw zero,-4(fp) + while ( (IORD_ALTERA_MSGDMA_CSR_STATUS(mi->tx_msgdma->csr_base) & + 8017bd0: 00000b06 br 8017c00 + ALTERA_MSGDMA_CSR_BUSY_MASK) ) { + if(timeout++ == ALTERA_TSE_MSGDMA_BUSY_TIME_OUT_CNT) { + 8017bd4: e0ffff17 ldw r3,-4(fp) + 8017bd8: 18800044 addi r2,r3,1 + 8017bdc: e0bfff15 stw r2,-4(fp) + 8017be0: 008003f4 movhi r2,15 + 8017be4: 10909004 addi r2,r2,16960 + 8017be8: 1880051e bne r3,r2,8017c00 + tse_dprintf(4, "WARNING : TX MSGDMA Timeout\n"); + 8017bec: 01020134 movhi r4,2052 + 8017bf0: 211e3404 addi r4,r4,30928 + 8017bf4: 8002d9c0 call 8002d9c + return ENP_RESOURCE; // avoid being stuck here + 8017bf8: 00bffa84 movi r2,-22 + 8017bfc: 00001906 br 8017c64 + while ( (IORD_ALTERA_MSGDMA_CSR_STATUS(mi->tx_msgdma->csr_base) & + 8017c00: e0bffd17 ldw r2,-12(fp) + 8017c04: 10800117 ldw r2,4(r2) + 8017c08: 10800317 ldw r2,12(r2) + 8017c0c: 10800037 ldwio r2,0(r2) + 8017c10: 1080004c andi r2,r2,1 + 8017c14: 103fef1e bne r2,zero,8017bd4 + } + } + + // Start MSGDMA (blocking call) + alt_dcache_flush(txDesc,sizeof(alt_msgdma_standard_descriptor)); + 8017c18: 01400404 movi r5,16 + 8017c1c: e13ffc17 ldw r4,-16(fp) + 8017c20: 80371c00 call 80371c0 + result = alt_msgdma_standard_descriptor_sync_transfer( + 8017c24: e0bffd17 ldw r2,-12(fp) + 8017c28: 10800117 ldw r2,4(r2) + 8017c2c: e17ffc17 ldw r5,-16(fp) + 8017c30: 1009883a mov r4,r2 + 8017c34: 80201600 call 8020160 + 8017c38: e0bffec5 stb r2,-5(fp) + mi->tx_msgdma, + txDesc); + + if (result != 0) { + 8017c3c: e0bffec3 ldbu r2,-5(fp) + 8017c40: 10000726 beq r2,zero,8017c60 + tse_dprintf(4, "WARNING :alt_msgdma_standard_descriptor_sync_transfer Error code 0x%x\n",result); + 8017c44: e0bffec3 ldbu r2,-5(fp) + 8017c48: 100b883a mov r5,r2 + 8017c4c: 01020134 movhi r4,2052 + 8017c50: 211e3b04 addi r4,r4,30956 + 8017c54: 8002c780 call 8002c78 + return -1; + 8017c58: 00bfffc4 movi r2,-1 + 8017c5c: 00000106 br 8017c64 + } + + return 0; + 8017c60: 0005883a mov r2,zero +} + 8017c64: e037883a mov sp,fp + 8017c68: dfc00117 ldw ra,4(sp) + 8017c6c: df000017 ldw fp,0(sp) + 8017c70: dec00204 addi sp,sp,8 + 8017c74: f800283a ret + +08017c78 : + * the actual bytes transferred for current descriptor + */ +alt_32 tse_mac_aRxRead( + tse_mac_trans_info *mi, + alt_msgdma_prefetcher_standard_descriptor *rxDesc) +{ + 8017c78: defff904 addi sp,sp,-28 + 8017c7c: dfc00615 stw ra,24(sp) + 8017c80: df000515 stw fp,20(sp) + 8017c84: df000504 addi fp,sp,20 + 8017c88: e13ffe15 stw r4,-8(fp) + 8017c8c: e17ffd15 stw r5,-12(fp) + alt_u8 result; + + result = alt_msgdma_start_prefetcher_with_std_desc_list( + 8017c90: e0bffe17 ldw r2,-8(fp) + 8017c94: 10c00217 ldw r3,8(r2) + 8017c98: 00800044 movi r2,1 + 8017c9c: d8800115 stw r2,4(sp) + 8017ca0: 00800044 movi r2,1 + 8017ca4: d8800015 stw r2,0(sp) + 8017ca8: 000f883a mov r7,zero + 8017cac: 000d883a mov r6,zero + 8017cb0: e17ffd17 ldw r5,-12(fp) + 8017cb4: 1809883a mov r4,r3 + 8017cb8: 801fd340 call 801fd34 + 8017cbc: e0bfffc5 stb r2,-1(fp) + mi->rx_msgdma, + rxDesc,0,0,1,1); + + if (result != 0) { return -1; } + 8017cc0: e0bfffc3 ldbu r2,-1(fp) + 8017cc4: 10000226 beq r2,zero,8017cd0 + 8017cc8: 00bfffc4 movi r2,-1 + 8017ccc: 00000106 br 8017cd4 + + return SUCCESS; + 8017cd0: 0005883a mov r2,zero +} + 8017cd4: e037883a mov sp,fp + 8017cd8: dfc00117 ldw ra,4(sp) + 8017cdc: df000017 ldw fp,0(sp) + 8017ce0: dec00204 addi sp,sp,8 + 8017ce4: f800283a ret + +08017ce8 : + * + */ +alt_32 tse_mac_aTxWrite( + tse_mac_trans_info *mi, + alt_msgdma_prefetcher_standard_descriptor *txDesc) +{ + 8017ce8: defff904 addi sp,sp,-28 + 8017cec: dfc00615 stw ra,24(sp) + 8017cf0: df000515 stw fp,20(sp) + 8017cf4: df000504 addi fp,sp,20 + 8017cf8: e13ffe15 stw r4,-8(fp) + 8017cfc: e17ffd15 stw r5,-12(fp) + alt_u8 result; + + result = alt_msgdma_start_prefetcher_with_std_desc_list( + 8017d00: e0bffe17 ldw r2,-8(fp) + 8017d04: 10c00117 ldw r3,4(r2) + 8017d08: 00800044 movi r2,1 + 8017d0c: d8800115 stw r2,4(sp) + 8017d10: 00800044 movi r2,1 + 8017d14: d8800015 stw r2,0(sp) + 8017d18: 000f883a mov r7,zero + 8017d1c: 000d883a mov r6,zero + 8017d20: e17ffd17 ldw r5,-12(fp) + 8017d24: 1809883a mov r4,r3 + 8017d28: 801fd340 call 801fd34 + 8017d2c: e0bfffc5 stb r2,-1(fp) + mi->tx_msgdma, + txDesc,0,0,1,1); + + if (result != 0) { return -1; } + 8017d30: e0bfffc3 ldbu r2,-1(fp) + 8017d34: 10000226 beq r2,zero,8017d40 + 8017d38: 00bfffc4 movi r2,-1 + 8017d3c: 00000106 br 8017d44 + + return SUCCESS; + 8017d40: 0005883a mov r2,zero +} + 8017d44: e037883a mov sp,fp + 8017d48: dfc00117 ldw ra,4(sp) + 8017d4c: df000017 ldw fp,0(sp) + 8017d50: dec00204 addi sp,sp,8 + 8017d54: f800283a ret + +08017d58 : + * COMMAND_CONFIG register is restored after reset. + * @API Type: Public + * @param pmac Pointer to the TSE MAC Control Interface Base address +*/ +alt_32 tse_mac_SwReset(np_tse_mac *pmac) +{ + 8017d58: defffc04 addi sp,sp,-16 + 8017d5c: df000315 stw fp,12(sp) + 8017d60: df000304 addi fp,sp,12 + 8017d64: e13ffd15 stw r4,-12(fp) + alt_32 timeout; + alt_32 cc; + + cc = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac); + 8017d68: e0bffd17 ldw r2,-12(fp) + 8017d6c: 10800204 addi r2,r2,8 + 8017d70: 10800037 ldwio r2,0(r2) + 8017d74: e0bffe15 stw r2,-8(fp) + + // set reset and Gig-Speed bits to make sure we have an incoming clock on + // tx side. If there is a 10/100 PHY, we will still have a valid clock on + // tx_clk no matter what setting we have here, but on a Gig phy the + // MII clock may be missing. + IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac,(ALTERA_TSEMAC_CMD_SW_RESET_MSK | ALTERA_TSEMAC_CMD_ETH_SPEED_MSK)); + 8017d78: e0bffd17 ldw r2,-12(fp) + 8017d7c: 10800204 addi r2,r2,8 + 8017d80: 00c80204 movi r3,8200 + 8017d84: 10c00035 stwio r3,0(r2) + + + // wait for completion with fallback in case there is no PHY or it is + // not connected and hence might not provide any clocks at all. + timeout=0; + 8017d88: e03fff15 stw zero,-4(fp) + while( (IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac) & ALTERA_TSEMAC_CMD_SW_RESET_MSK) != 0 && timeout < ALTERA_TSE_SW_RESET_TIME_OUT_CNT) timeout++; + 8017d8c: 00000306 br 8017d9c + 8017d90: e0bfff17 ldw r2,-4(fp) + 8017d94: 10800044 addi r2,r2,1 + 8017d98: e0bfff15 stw r2,-4(fp) + 8017d9c: e0bffd17 ldw r2,-12(fp) + 8017da0: 10800204 addi r2,r2,8 + 8017da4: 10800037 ldwio r2,0(r2) + 8017da8: 1088000c andi r2,r2,8192 + 8017dac: 10000326 beq r2,zero,8017dbc + 8017db0: e0bfff17 ldw r2,-4(fp) + 8017db4: 1089c410 cmplti r2,r2,10000 + 8017db8: 103ff51e bne r2,zero,8017d90 + + IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac,cc); // Restore + 8017dbc: e0bffd17 ldw r2,-12(fp) + 8017dc0: 10800204 addi r2,r2,8 + 8017dc4: e0fffe17 ldw r3,-8(fp) + 8017dc8: 10c00035 stwio r3,0(r2) + return SUCCESS; + 8017dcc: 0005883a mov r2,zero +} + 8017dd0: e037883a mov sp,fp + 8017dd4: df000017 ldw fp,0(sp) + 8017dd8: dec00104 addi sp,sp,4 + 8017ddc: f800283a ret + +08017de0 : + * COMMAND_CONFIG register is restored after reset. + * @API Type: Public + * @param pmac Pointer to the TSE MAC Control Interface Base address +*/ +alt_32 tse_mac_setMIImode(np_tse_mac *pmac) +{ + 8017de0: defffd04 addi sp,sp,-12 + 8017de4: df000215 stw fp,8(sp) + 8017de8: df000204 addi fp,sp,8 + 8017dec: e13ffe15 stw r4,-8(fp) + alt_32 helpvar; + + helpvar = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac); + 8017df0: e0bffe17 ldw r2,-8(fp) + 8017df4: 10800204 addi r2,r2,8 + 8017df8: 10800037 ldwio r2,0(r2) + 8017dfc: e0bfff15 stw r2,-4(fp) + helpvar &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; + 8017e00: e0ffff17 ldw r3,-4(fp) + 8017e04: 00bffdc4 movi r2,-9 + 8017e08: 1884703a and r2,r3,r2 + 8017e0c: e0bfff15 stw r2,-4(fp) + + IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac,helpvar); + 8017e10: e0bffe17 ldw r2,-8(fp) + 8017e14: 10800204 addi r2,r2,8 + 8017e18: e0ffff17 ldw r3,-4(fp) + 8017e1c: 10c00035 stwio r3,0(r2) + return SUCCESS; + 8017e20: 0005883a mov r2,zero +} + 8017e24: e037883a mov sp,fp + 8017e28: df000017 ldw fp,0(sp) + 8017e2c: dec00104 addi sp,sp,4 + 8017e30: f800283a ret + +08017e34 : + * COMMAND_CONFIG register is restored after reset. + * @API Type: Public + * @param pmac Pointer to the TSE MAC Control Interface Base address + */ +alt_32 tse_mac_setGMIImode(np_tse_mac *pmac) +{ + 8017e34: defffd04 addi sp,sp,-12 + 8017e38: df000215 stw fp,8(sp) + 8017e3c: df000204 addi fp,sp,8 + 8017e40: e13ffe15 stw r4,-8(fp) + alt_32 helpvar; + + helpvar = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac); + 8017e44: e0bffe17 ldw r2,-8(fp) + 8017e48: 10800204 addi r2,r2,8 + 8017e4c: 10800037 ldwio r2,0(r2) + 8017e50: e0bfff15 stw r2,-4(fp) + helpvar |= ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; + 8017e54: e0bfff17 ldw r2,-4(fp) + 8017e58: 10800214 ori r2,r2,8 + 8017e5c: e0bfff15 stw r2,-4(fp) + + IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac,helpvar); + 8017e60: e0bffe17 ldw r2,-8(fp) + 8017e64: 10800204 addi r2,r2,8 + 8017e68: e0ffff17 ldw r3,-4(fp) + 8017e6c: 10c00035 stwio r3,0(r2) + return SUCCESS; + 8017e70: 0005883a mov r2,zero +} + 8017e74: e037883a mov sp,fp + 8017e78: df000017 ldw fp,0(sp) + 8017e7c: dec00104 addi sp,sp,4 + 8017e80: f800283a ret + +08017e84 : + * @param phy pointer to alt_tse_phy_profile structure describing PHY registers + * @return index of PHY added in PHY profile on success, else return ALTERA_TSE_MALLOC_FAILED if memory allocation failed + * PHY which are currently supported by default : Marvell 88E1111, Marvell Quad PHY 88E1145, National DP83865, and National DP83848C + */ +alt_32 alt_tse_phy_add_profile(alt_tse_phy_profile *phy) +{ + 8017e84: defffb04 addi sp,sp,-20 + 8017e88: dfc00415 stw ra,16(sp) + 8017e8c: df000315 stw fp,12(sp) + 8017e90: dc000215 stw r16,8(sp) + 8017e94: df000304 addi fp,sp,12 + 8017e98: e13ffd15 stw r4,-12(fp) + alt_32 i; + + /* search PHY profile for same ID */ + for(i = 0; i < phy_profile_count; i++) + 8017e9c: e03ffe15 stw zero,-8(fp) + 8017ea0: 00002506 br 8017f38 + { + if(pphy_profiles[i]->oui == phy->oui && pphy_profiles[i]->model_number == phy->model_number) + 8017ea4: e0bffe17 ldw r2,-8(fp) + 8017ea8: 100690ba slli r3,r2,2 + 8017eac: 008201b4 movhi r2,2054 + 8017eb0: 1885883a add r2,r3,r2 + 8017eb4: 10b5ae17 ldw r2,-10568(r2) + 8017eb8: 10c01417 ldw r3,80(r2) + 8017ebc: e0bffd17 ldw r2,-12(fp) + 8017ec0: 10801417 ldw r2,80(r2) + 8017ec4: 1880191e bne r3,r2,8017f2c + 8017ec8: e0bffe17 ldw r2,-8(fp) + 8017ecc: 100690ba slli r3,r2,2 + 8017ed0: 008201b4 movhi r2,2054 + 8017ed4: 1885883a add r2,r3,r2 + 8017ed8: 10b5ae17 ldw r2,-10568(r2) + 8017edc: 10c01503 ldbu r3,84(r2) + 8017ee0: e0bffd17 ldw r2,-12(fp) + 8017ee4: 10801503 ldbu r2,84(r2) + 8017ee8: 18c03fcc andi r3,r3,255 + 8017eec: 10803fcc andi r2,r2,255 + 8017ef0: 18800e1e bne r3,r2,8017f2c + { + tse_dprintf(4, "WARNING : PHY OUI 0x%06x, PHY Model Number 0x%02x already exist in PHY profile\n", (int) phy->oui, phy->model_number); + 8017ef4: e0bffd17 ldw r2,-12(fp) + 8017ef8: 10801417 ldw r2,80(r2) + 8017efc: 1007883a mov r3,r2 + 8017f00: e0bffd17 ldw r2,-12(fp) + 8017f04: 10801503 ldbu r2,84(r2) + 8017f08: 10803fcc andi r2,r2,255 + 8017f0c: 100d883a mov r6,r2 + 8017f10: 180b883a mov r5,r3 + 8017f14: 01020134 movhi r4,2052 + 8017f18: 211e4d04 addi r4,r4,31028 + 8017f1c: 8002c780 call 8002c78 + tse_dprintf(4, "In case of same PHY OUI and PHY Model Number in profile, first added PHY setting will be used\n"); + 8017f20: 01020134 movhi r4,2052 + 8017f24: 211e6104 addi r4,r4,31108 + 8017f28: 8002d9c0 call 8002d9c + for(i = 0; i < phy_profile_count; i++) + 8017f2c: e0bffe17 ldw r2,-8(fp) + 8017f30: 10800044 addi r2,r2,1 + 8017f34: e0bffe15 stw r2,-8(fp) + 8017f38: d0a05b03 ldbu r2,-32404(gp) + 8017f3c: 10803fcc andi r2,r2,255 + 8017f40: e0fffe17 ldw r3,-8(fp) + 8017f44: 18bfd716 blt r3,r2,8017ea4 + } + } + + /* Allocate memory space to store the profile */ + pphy_profiles[phy_profile_count] = (alt_tse_phy_profile *) malloc(sizeof(alt_tse_phy_profile)); + 8017f48: d0a05b03 ldbu r2,-32404(gp) + 8017f4c: 14003fcc andi r16,r2,255 + 8017f50: 01001904 movi r4,100 + 8017f54: 8042c980 call 8042c98 + 8017f58: 1009883a mov r4,r2 + 8017f5c: 800690ba slli r3,r16,2 + 8017f60: 008201b4 movhi r2,2054 + 8017f64: 1885883a add r2,r3,r2 + 8017f68: 1135ae15 stw r4,-10568(r2) + if(!pphy_profiles[phy_profile_count]) { + 8017f6c: d0a05b03 ldbu r2,-32404(gp) + 8017f70: 10803fcc andi r2,r2,255 + 8017f74: 100690ba slli r3,r2,2 + 8017f78: 008201b4 movhi r2,2054 + 8017f7c: 1885883a add r2,r3,r2 + 8017f80: 10b5ae17 ldw r2,-10568(r2) + 8017f84: 1000081e bne r2,zero,8017fa8 + tse_dprintf(1, "ERROR : Unable to allocate memory for pphy_profile[%d]\n", phy_profile_count); + 8017f88: d0a05b03 ldbu r2,-32404(gp) + 8017f8c: 10803fcc andi r2,r2,255 + 8017f90: 100b883a mov r5,r2 + 8017f94: 01020134 movhi r4,2052 + 8017f98: 211e7904 addi r4,r4,31204 + 8017f9c: 8002c780 call 8002c78 + return ALTERA_TSE_MALLOC_FAILED; + 8017fa0: 00bfffc4 movi r2,-1 + 8017fa4: 00001e06 br 8018020 + } + + /* Store PHY information */ + *pphy_profiles[phy_profile_count] = *phy; + 8017fa8: d0a05b03 ldbu r2,-32404(gp) + 8017fac: 10803fcc andi r2,r2,255 + 8017fb0: 100690ba slli r3,r2,2 + 8017fb4: 008201b4 movhi r2,2054 + 8017fb8: 1885883a add r2,r3,r2 + 8017fbc: 10f5ae17 ldw r3,-10568(r2) + 8017fc0: e0bffd17 ldw r2,-12(fp) + 8017fc4: 1009883a mov r4,r2 + 8017fc8: 00801904 movi r2,100 + 8017fcc: 100d883a mov r6,r2 + 8017fd0: 200b883a mov r5,r4 + 8017fd4: 1809883a mov r4,r3 + 8017fd8: 80086b80 call 80086b8 + strcpy(pphy_profiles[phy_profile_count]->name, phy->name); + 8017fdc: d0a05b03 ldbu r2,-32404(gp) + 8017fe0: 10803fcc andi r2,r2,255 + 8017fe4: 100690ba slli r3,r2,2 + 8017fe8: 008201b4 movhi r2,2054 + 8017fec: 1885883a add r2,r3,r2 + 8017ff0: 10b5ae17 ldw r2,-10568(r2) + 8017ff4: 1007883a mov r3,r2 + 8017ff8: e0bffd17 ldw r2,-12(fp) + 8017ffc: 100b883a mov r5,r2 + 8018000: 1809883a mov r4,r3 + 8018004: 8042f600 call 8042f60 + + phy_profile_count++; + 8018008: d0a05b03 ldbu r2,-32404(gp) + 801800c: 10800044 addi r2,r2,1 + 8018010: d0a05b05 stb r2,-32404(gp) + + return phy_profile_count - 1; + 8018014: d0a05b03 ldbu r2,-32404(gp) + 8018018: 10803fcc andi r2,r2,255 + 801801c: 10bfffc4 addi r2,r2,-1 +} + 8018020: e6ffff04 addi sp,fp,-4 + 8018024: dfc00217 ldw ra,8(sp) + 8018028: df000117 ldw fp,4(sp) + 801802c: dc000017 ldw r16,0(sp) + 8018030: dec00304 addi sp,sp,12 + 8018034: f800283a ret + +08018038 : +alt_32 alt_tse_system_add_sys( + alt_tse_system_mac *psys_mac, + alt_tse_system_msgdma *psys_msgdma, + alt_tse_system_desc_mem *psys_mem, + alt_tse_system_shared_fifo *psys_shared_fifo, + alt_tse_system_phy *psys_phy ) { + 8018038: defff204 addi sp,sp,-56 + 801803c: dfc00d15 stw ra,52(sp) + 8018040: df000c15 stw fp,48(sp) + 8018044: dc000b15 stw r16,44(sp) + 8018048: df000c04 addi fp,sp,48 + 801804c: e13ff715 stw r4,-36(fp) + 8018050: e17ff615 stw r5,-40(fp) + 8018054: e1bff515 stw r6,-44(fp) + 8018058: e1fff415 stw r7,-48(fp) + + int i; + int loop_end; + + alt_tse_system_mac *pmac = psys_mac; + 801805c: e0bff717 ldw r2,-36(fp) + 8018060: e0bff815 stw r2,-32(fp) + alt_tse_system_msgdma *pmsgdma = psys_msgdma; + 8018064: e0bff617 ldw r2,-40(fp) + 8018068: e0bffb15 stw r2,-20(fp) + alt_tse_system_desc_mem *pmem = psys_mem; + 801806c: e0bff517 ldw r2,-44(fp) + 8018070: e0bffc15 stw r2,-16(fp) + alt_tse_system_shared_fifo *pfifo = psys_shared_fifo; + 8018074: e0bff417 ldw r2,-48(fp) + 8018078: e0bffe15 stw r2,-8(fp) + alt_tse_system_phy *pphy = psys_phy; + 801807c: e0800217 ldw r2,8(fp) + 8018080: e0bffd15 stw r2,-12(fp) + + static alt_8 tse_system_count = 0; + + /* Determine number of loop */ + /* Run at least one for non-multi-channel MAC */ + if(pmac->tse_num_of_channel == 0) { + 8018084: e0bff817 ldw r2,-32(fp) + 8018088: 10800303 ldbu r2,12(r2) + 801808c: 10803fcc andi r2,r2,255 + 8018090: 1000031e bne r2,zero,80180a0 + loop_end = 1; + 8018094: 00800044 movi r2,1 + 8018098: e0bff915 stw r2,-28(fp) + 801809c: 00000e06 br 80180d8 + } + else if(pmac->tse_num_of_channel > 0) { + 80180a0: e0bff817 ldw r2,-32(fp) + 80180a4: 10800303 ldbu r2,12(r2) + 80180a8: 10803fcc andi r2,r2,255 + 80180ac: 10000526 beq r2,zero,80180c4 + loop_end = pmac->tse_num_of_channel; + 80180b0: e0bff817 ldw r2,-32(fp) + 80180b4: 10800303 ldbu r2,12(r2) + 80180b8: 10803fcc andi r2,r2,255 + 80180bc: e0bff915 stw r2,-28(fp) + 80180c0: 00000506 br 80180d8 + } + else { + tse_dprintf(2, "ERROR : Invalid number of channel specified!\n"); + 80180c4: 01020134 movhi r4,2052 + 80180c8: 211e8804 addi r4,r4,31264 + 80180cc: 8002d9c0 call 8002d9c + return ALTERA_TSE_SYSTEM_DEF_ERROR; + 80180d0: 00bfffc4 movi r2,-1 + 80180d4: 00020306 br 80188e4 + } + + for(i = 0; i < loop_end; i++) { + 80180d8: e03ffa15 stw zero,-24(fp) + 80180dc: 0001fd06 br 80188d4 + + /* Make sure the boundary of array is not exceeded */ + if(tse_system_count >= MAXNETS) { + 80180e0: d0a05b83 ldbu r2,-32402(gp) + 80180e4: 10803fcc andi r2,r2,255 + 80180e8: 1080201c xori r2,r2,128 + 80180ec: 10bfe004 addi r2,r2,-128 + 80180f0: 10800110 cmplti r2,r2,4 + 80180f4: 10000c1e bne r2,zero,8018128 + tse_dprintf(2, "ERROR : Number of TSE System added exceed the size of array!\n"); + 80180f8: 01020134 movhi r4,2052 + 80180fc: 211e9404 addi r4,r4,31312 + 8018100: 8002d9c0 call 8002d9c + tse_dprintf(2, "ERROR : Size of array = %d, Number of TSE System = %d\n", MAXNETS, tse_system_count); + 8018104: d0a05b83 ldbu r2,-32402(gp) + 8018108: 10803fcc andi r2,r2,255 + 801810c: 1080201c xori r2,r2,128 + 8018110: 10bfe004 addi r2,r2,-128 + 8018114: 100d883a mov r6,r2 + 8018118: 01400104 movi r5,4 + 801811c: 01020134 movhi r4,2052 + 8018120: 211ea404 addi r4,r4,31376 + 8018124: 8002c780 call 8002c78 + } + + /* Add MAC info to alt_tse_system_info structure */ + if(pmac == 0) { + 8018128: e0bff817 ldw r2,-32(fp) + 801812c: 1000081e bne r2,zero,8018150 + tse_dprintf(2, "ERROR : MAC system structure == NULL\n"); + 8018130: 01020134 movhi r4,2052 + 8018134: 211eb304 addi r4,r4,31436 + 8018138: 8002d9c0 call 8002d9c + tse_dprintf(2, "ERROR : Please pass in correct pointer to alt_tse_system_add_sys()\n"); + 801813c: 01020134 movhi r4,2052 + 8018140: 211ebd04 addi r4,r4,31476 + 8018144: 8002d9c0 call 8002d9c + return ALTERA_TSE_SYSTEM_DEF_ERROR; + 8018148: 00bfffc4 movi r2,-1 + 801814c: 0001e506 br 80188e4 + } + + tse_mac_device[tse_system_count].tse_mac_base = pmac->tse_mac_base + (i * 0x400); + 8018150: e0bff817 ldw r2,-32(fp) + 8018154: 10c00017 ldw r3,0(r2) + 8018158: e0bffa17 ldw r2,-24(fp) + 801815c: 100492ba slli r2,r2,10 + 8018160: 1009883a mov r4,r2 + 8018164: d0a05b83 ldbu r2,-32402(gp) + 8018168: 10803fcc andi r2,r2,255 + 801816c: 1080201c xori r2,r2,128 + 8018170: 10bfe004 addi r2,r2,-128 + 8018174: 1907883a add r3,r3,r4 + 8018178: 11001324 muli r4,r2,76 + 801817c: 00820174 movhi r2,2053 + 8018180: 2085883a add r2,r4,r2 + 8018184: 10ee5415 stw r3,-18096(r2) + tse_mac_device[tse_system_count].tse_tx_depth = pmac->tse_tx_depth; + 8018188: e0bff817 ldw r2,-32(fp) + 801818c: 10c0010b ldhu r3,4(r2) + 8018190: d0a05b83 ldbu r2,-32402(gp) + 8018194: 10803fcc andi r2,r2,255 + 8018198: 1080201c xori r2,r2,128 + 801819c: 10bfe004 addi r2,r2,-128 + 80181a0: 18ffffcc andi r3,r3,65535 + 80181a4: 11001324 muli r4,r2,76 + 80181a8: 00820174 movhi r2,2053 + 80181ac: 2085883a add r2,r4,r2 + 80181b0: 10ee5515 stw r3,-18092(r2) + tse_mac_device[tse_system_count].tse_rx_depth = pmac->tse_rx_depth; + 80181b4: e0bff817 ldw r2,-32(fp) + 80181b8: 10c0018b ldhu r3,6(r2) + 80181bc: d0a05b83 ldbu r2,-32402(gp) + 80181c0: 10803fcc andi r2,r2,255 + 80181c4: 1080201c xori r2,r2,128 + 80181c8: 10bfe004 addi r2,r2,-128 + 80181cc: 18ffffcc andi r3,r3,65535 + 80181d0: 11001324 muli r4,r2,76 + 80181d4: 00820174 movhi r2,2053 + 80181d8: 2085883a add r2,r4,r2 + 80181dc: 10ee5615 stw r3,-18088(r2) + tse_mac_device[tse_system_count].tse_use_mdio = pmac->tse_use_mdio; + 80181e0: d0a05b83 ldbu r2,-32402(gp) + 80181e4: 10803fcc andi r2,r2,255 + 80181e8: 1080201c xori r2,r2,128 + 80181ec: 10bfe004 addi r2,r2,-128 + 80181f0: e0fff817 ldw r3,-32(fp) + 80181f4: 18c00203 ldbu r3,8(r3) + 80181f8: 11001324 muli r4,r2,76 + 80181fc: 00820174 movhi r2,2053 + 8018200: 2085883a add r2,r4,r2 + 8018204: 10ee5705 stb r3,-18084(r2) + tse_mac_device[tse_system_count].tse_en_maclite = pmac->tse_en_maclite; + 8018208: d0a05b83 ldbu r2,-32402(gp) + 801820c: 10803fcc andi r2,r2,255 + 8018210: 1080201c xori r2,r2,128 + 8018214: 10bfe004 addi r2,r2,-128 + 8018218: e0fff817 ldw r3,-32(fp) + 801821c: 18c00243 ldbu r3,9(r3) + 8018220: 11001324 muli r4,r2,76 + 8018224: 00820174 movhi r2,2053 + 8018228: 2085883a add r2,r4,r2 + 801822c: 10ee5745 stb r3,-18083(r2) + tse_mac_device[tse_system_count].tse_maclite_gige = pmac->tse_maclite_gige; + 8018230: d0a05b83 ldbu r2,-32402(gp) + 8018234: 10803fcc andi r2,r2,255 + 8018238: 1080201c xori r2,r2,128 + 801823c: 10bfe004 addi r2,r2,-128 + 8018240: e0fff817 ldw r3,-32(fp) + 8018244: 18c00283 ldbu r3,10(r3) + 8018248: 11001324 muli r4,r2,76 + 801824c: 00820174 movhi r2,2053 + 8018250: 2085883a add r2,r4,r2 + 8018254: 10ee5785 stb r3,-18082(r2) + tse_mac_device[tse_system_count].tse_multichannel_mac = pmac->tse_multichannel_mac; + 8018258: d0a05b83 ldbu r2,-32402(gp) + 801825c: 10803fcc andi r2,r2,255 + 8018260: 1080201c xori r2,r2,128 + 8018264: 10bfe004 addi r2,r2,-128 + 8018268: e0fff817 ldw r3,-32(fp) + 801826c: 18c002c3 ldbu r3,11(r3) + 8018270: 11001324 muli r4,r2,76 + 8018274: 00820174 movhi r2,2053 + 8018278: 2085883a add r2,r4,r2 + 801827c: 10ee57c5 stb r3,-18081(r2) + tse_mac_device[tse_system_count].tse_num_of_channel = pmac->tse_num_of_channel; + 8018280: d0a05b83 ldbu r2,-32402(gp) + 8018284: 10803fcc andi r2,r2,255 + 8018288: 1080201c xori r2,r2,128 + 801828c: 10bfe004 addi r2,r2,-128 + 8018290: e0fff817 ldw r3,-32(fp) + 8018294: 18c00303 ldbu r3,12(r3) + 8018298: 11001324 muli r4,r2,76 + 801829c: 00820174 movhi r2,2053 + 80182a0: 2085883a add r2,r4,r2 + 80182a4: 10ee5805 stb r3,-18080(r2) + tse_mac_device[tse_system_count].tse_mdio_shared = pmac->tse_mdio_shared; + 80182a8: d0a05b83 ldbu r2,-32402(gp) + 80182ac: 10803fcc andi r2,r2,255 + 80182b0: 1080201c xori r2,r2,128 + 80182b4: 10bfe004 addi r2,r2,-128 + 80182b8: e0fff817 ldw r3,-32(fp) + 80182bc: 18c00343 ldbu r3,13(r3) + 80182c0: 11001324 muli r4,r2,76 + 80182c4: 00820174 movhi r2,2053 + 80182c8: 2085883a add r2,r4,r2 + 80182cc: 10ee5845 stb r3,-18079(r2) + tse_mac_device[tse_system_count].tse_number_of_mac_mdio_shared = pmac->tse_number_of_mac_mdio_shared; + 80182d0: d0a05b83 ldbu r2,-32402(gp) + 80182d4: 10803fcc andi r2,r2,255 + 80182d8: 1080201c xori r2,r2,128 + 80182dc: 10bfe004 addi r2,r2,-128 + 80182e0: e0fff817 ldw r3,-32(fp) + 80182e4: 18c00383 ldbu r3,14(r3) + 80182e8: 11001324 muli r4,r2,76 + 80182ec: 00820174 movhi r2,2053 + 80182f0: 2085883a add r2,r4,r2 + 80182f4: 10ee5885 stb r3,-18078(r2) + tse_mac_device[tse_system_count].tse_pcs_ena = pmac->tse_pcs_ena; + 80182f8: d0a05b83 ldbu r2,-32402(gp) + 80182fc: 10803fcc andi r2,r2,255 + 8018300: 1080201c xori r2,r2,128 + 8018304: 10bfe004 addi r2,r2,-128 + 8018308: e0fff817 ldw r3,-32(fp) + 801830c: 18c003c3 ldbu r3,15(r3) + 8018310: 11001324 muli r4,r2,76 + 8018314: 00820174 movhi r2,2053 + 8018318: 2085883a add r2,r4,r2 + 801831c: 10ee58c5 stb r3,-18077(r2) + tse_mac_device[tse_system_count].tse_pcs_sgmii = pmac->tse_pcs_sgmii; + 8018320: d0a05b83 ldbu r2,-32402(gp) + 8018324: 10803fcc andi r2,r2,255 + 8018328: 1080201c xori r2,r2,128 + 801832c: 10bfe004 addi r2,r2,-128 + 8018330: e0fff817 ldw r3,-32(fp) + 8018334: 18c00403 ldbu r3,16(r3) + 8018338: 11001324 muli r4,r2,76 + 801833c: 00820174 movhi r2,2053 + 8018340: 2085883a add r2,r4,r2 + 8018344: 10ee5905 stb r3,-18076(r2) + + /* Add MSGDMA info to alt_tse_system_info structure */ + if(pmsgdma == 0) { + 8018348: e0bffb17 ldw r2,-20(fp) + 801834c: 10000d1e bne r2,zero,8018384 + tse_dprintf(2, "ERROR : MSGDMA system structure == NULL\n"); + 8018350: 01020134 movhi r4,2052 + 8018354: 211ecf04 addi r4,r4,31548 + 8018358: 8002d9c0 call 8002d9c + tse_dprintf(2, "ERROR : Please pass in correct pointer to alt_tse_system_add_sys() for tse_mac_device[%d]\n", tse_system_count); + 801835c: d0a05b83 ldbu r2,-32402(gp) + 8018360: 10803fcc andi r2,r2,255 + 8018364: 1080201c xori r2,r2,128 + 8018368: 10bfe004 addi r2,r2,-128 + 801836c: 100b883a mov r5,r2 + 8018370: 01020134 movhi r4,2052 + 8018374: 211eda04 addi r4,r4,31592 + 8018378: 8002c780 call 8002c78 + return ALTERA_TSE_SYSTEM_DEF_ERROR; + 801837c: 00bfffc4 movi r2,-1 + 8018380: 00015806 br 80188e4 + } + + tse_mac_device[tse_system_count].tse_msgdma_tx = (char *) malloc(strlen(pmsgdma->tse_msgdma_tx) + 1); + 8018384: e0bffb17 ldw r2,-20(fp) + 8018388: 10800017 ldw r2,0(r2) + 801838c: 1009883a mov r4,r2 + 8018390: 8002dac0 call 8002dac + 8018394: 10800044 addi r2,r2,1 + 8018398: d0e05b83 ldbu r3,-32402(gp) + 801839c: 1c003fcc andi r16,r3,255 + 80183a0: 8400201c xori r16,r16,128 + 80183a4: 843fe004 addi r16,r16,-128 + 80183a8: 1009883a mov r4,r2 + 80183ac: 8042c980 call 8042c98 + 80183b0: 1009883a mov r4,r2 + 80183b4: 80c01324 muli r3,r16,76 + 80183b8: 00820174 movhi r2,2053 + 80183bc: 1885883a add r2,r3,r2 + 80183c0: 112e5a15 stw r4,-18072(r2) + if(!tse_mac_device[tse_system_count].tse_msgdma_tx) { + 80183c4: d0a05b83 ldbu r2,-32402(gp) + 80183c8: 10803fcc andi r2,r2,255 + 80183cc: 1080201c xori r2,r2,128 + 80183d0: 10bfe004 addi r2,r2,-128 + 80183d4: 10c01324 muli r3,r2,76 + 80183d8: 00820174 movhi r2,2053 + 80183dc: 1885883a add r2,r3,r2 + 80183e0: 10ae5a17 ldw r2,-18072(r2) + 80183e4: 10000a1e bne r2,zero,8018410 + tse_dprintf(1, "ERROR : Unable to allocate memory for tse_mac_device[%d].tse_msgdma_tx\n", tse_system_count); + 80183e8: d0a05b83 ldbu r2,-32402(gp) + 80183ec: 10803fcc andi r2,r2,255 + 80183f0: 1080201c xori r2,r2,128 + 80183f4: 10bfe004 addi r2,r2,-128 + 80183f8: 100b883a mov r5,r2 + 80183fc: 01020134 movhi r4,2052 + 8018400: 211ef204 addi r4,r4,31688 + 8018404: 8002c780 call 8002c78 + return ALTERA_TSE_MALLOC_FAILED; + 8018408: 00bfffc4 movi r2,-1 + 801840c: 00013506 br 80188e4 + } + strcpy(tse_mac_device[tse_system_count].tse_msgdma_tx, pmsgdma->tse_msgdma_tx); + 8018410: d0a05b83 ldbu r2,-32402(gp) + 8018414: 10803fcc andi r2,r2,255 + 8018418: 1080201c xori r2,r2,128 + 801841c: 10bfe004 addi r2,r2,-128 + 8018420: 10c01324 muli r3,r2,76 + 8018424: 00820174 movhi r2,2053 + 8018428: 1885883a add r2,r3,r2 + 801842c: 10ee5a17 ldw r3,-18072(r2) + 8018430: e0bffb17 ldw r2,-20(fp) + 8018434: 10800017 ldw r2,0(r2) + 8018438: 100b883a mov r5,r2 + 801843c: 1809883a mov r4,r3 + 8018440: 8042f600 call 8042f60 + + tse_mac_device[tse_system_count].tse_msgdma_rx = (char *) malloc(strlen(pmsgdma->tse_msgdma_rx) + 1); + 8018444: e0bffb17 ldw r2,-20(fp) + 8018448: 10800117 ldw r2,4(r2) + 801844c: 1009883a mov r4,r2 + 8018450: 8002dac0 call 8002dac + 8018454: 10800044 addi r2,r2,1 + 8018458: d0e05b83 ldbu r3,-32402(gp) + 801845c: 1c003fcc andi r16,r3,255 + 8018460: 8400201c xori r16,r16,128 + 8018464: 843fe004 addi r16,r16,-128 + 8018468: 1009883a mov r4,r2 + 801846c: 8042c980 call 8042c98 + 8018470: 1009883a mov r4,r2 + 8018474: 80c01324 muli r3,r16,76 + 8018478: 00820174 movhi r2,2053 + 801847c: 1885883a add r2,r3,r2 + 8018480: 112e5b15 stw r4,-18068(r2) + if(!tse_mac_device[tse_system_count].tse_msgdma_rx) { + 8018484: d0a05b83 ldbu r2,-32402(gp) + 8018488: 10803fcc andi r2,r2,255 + 801848c: 1080201c xori r2,r2,128 + 8018490: 10bfe004 addi r2,r2,-128 + 8018494: 10c01324 muli r3,r2,76 + 8018498: 00820174 movhi r2,2053 + 801849c: 1885883a add r2,r3,r2 + 80184a0: 10ae5b17 ldw r2,-18068(r2) + 80184a4: 10000a1e bne r2,zero,80184d0 + tse_dprintf(1, "ERROR : Unable to allocate memory for tse_mac_device[%d].tse_msgdma_rx\n", tse_system_count); + 80184a8: d0a05b83 ldbu r2,-32402(gp) + 80184ac: 10803fcc andi r2,r2,255 + 80184b0: 1080201c xori r2,r2,128 + 80184b4: 10bfe004 addi r2,r2,-128 + 80184b8: 100b883a mov r5,r2 + 80184bc: 01020134 movhi r4,2052 + 80184c0: 211f0504 addi r4,r4,31764 + 80184c4: 8002c780 call 8002c78 + return ALTERA_TSE_MALLOC_FAILED; + 80184c8: 00bfffc4 movi r2,-1 + 80184cc: 00010506 br 80188e4 + } + strcpy(tse_mac_device[tse_system_count].tse_msgdma_rx, pmsgdma->tse_msgdma_rx); + 80184d0: d0a05b83 ldbu r2,-32402(gp) + 80184d4: 10803fcc andi r2,r2,255 + 80184d8: 1080201c xori r2,r2,128 + 80184dc: 10bfe004 addi r2,r2,-128 + 80184e0: 10c01324 muli r3,r2,76 + 80184e4: 00820174 movhi r2,2053 + 80184e8: 1885883a add r2,r3,r2 + 80184ec: 10ee5b17 ldw r3,-18068(r2) + 80184f0: e0bffb17 ldw r2,-20(fp) + 80184f4: 10800117 ldw r2,4(r2) + 80184f8: 100b883a mov r5,r2 + 80184fc: 1809883a mov r4,r3 + 8018500: 8042f600 call 8042f60 + + tse_mac_device[tse_system_count].tse_msgdma_rx_irq = pmsgdma->tse_msgdma_rx_irq; + 8018504: d0a05b83 ldbu r2,-32402(gp) + 8018508: 10803fcc andi r2,r2,255 + 801850c: 1080201c xori r2,r2,128 + 8018510: 10bfe004 addi r2,r2,-128 + 8018514: e0fffb17 ldw r3,-20(fp) + 8018518: 18c0020b ldhu r3,8(r3) + 801851c: 11001324 muli r4,r2,76 + 8018520: 00820174 movhi r2,2053 + 8018524: 2085883a add r2,r4,r2 + 8018528: 10ee5c0d sth r3,-18064(r2) + + /* Add descriptor memory info to alt_tse_system_info structure */ + if(pmem == 0) { + 801852c: e0bffc17 ldw r2,-16(fp) + 8018530: 1000111e bne r2,zero,8018578 + tse_mac_device[tse_system_count].ext_desc_mem = TSE_INT_DESC_MEM; + 8018534: d0a05b83 ldbu r2,-32402(gp) + 8018538: 10803fcc andi r2,r2,255 + 801853c: 1080201c xori r2,r2,128 + 8018540: 10bfe004 addi r2,r2,-128 + 8018544: 10c01324 muli r3,r2,76 + 8018548: 00820174 movhi r2,2053 + 801854c: 1885883a add r2,r3,r2 + 8018550: 102e5c85 stb zero,-18062(r2) + tse_mac_device[tse_system_count].desc_mem_base = TSE_INT_DESC_MEM; + 8018554: d0a05b83 ldbu r2,-32402(gp) + 8018558: 10803fcc andi r2,r2,255 + 801855c: 1080201c xori r2,r2,128 + 8018560: 10bfe004 addi r2,r2,-128 + 8018564: 10c01324 muli r3,r2,76 + 8018568: 00820174 movhi r2,2053 + 801856c: 1885883a add r2,r3,r2 + 8018570: 102e5d15 stw zero,-18060(r2) + 8018574: 00001406 br 80185c8 + } + else { + tse_mac_device[tse_system_count].ext_desc_mem = pmem->ext_desc_mem; + 8018578: d0a05b83 ldbu r2,-32402(gp) + 801857c: 10803fcc andi r2,r2,255 + 8018580: 1080201c xori r2,r2,128 + 8018584: 10bfe004 addi r2,r2,-128 + 8018588: e0fffc17 ldw r3,-16(fp) + 801858c: 18c00003 ldbu r3,0(r3) + 8018590: 11001324 muli r4,r2,76 + 8018594: 00820174 movhi r2,2053 + 8018598: 2085883a add r2,r4,r2 + 801859c: 10ee5c85 stb r3,-18062(r2) + tse_mac_device[tse_system_count].desc_mem_base = pmem->desc_mem_base; + 80185a0: d0a05b83 ldbu r2,-32402(gp) + 80185a4: 10803fcc andi r2,r2,255 + 80185a8: 1080201c xori r2,r2,128 + 80185ac: 10bfe004 addi r2,r2,-128 + 80185b0: e0fffc17 ldw r3,-16(fp) + 80185b4: 18c00117 ldw r3,4(r3) + 80185b8: 11001324 muli r4,r2,76 + 80185bc: 00820174 movhi r2,2053 + 80185c0: 2085883a add r2,r4,r2 + 80185c4: 10ee5d15 stw r3,-18060(r2) + } + + /* Add shared fifo info to alt_tse_system_info structure */ + if(pfifo == 0) { + 80185c8: e0bffe17 ldw r2,-8(fp) + 80185cc: 1000391e bne r2,zero,80186b4 + tse_mac_device[tse_system_count].use_shared_fifo = TSE_NO_SHARED_FIFO; + 80185d0: d0a05b83 ldbu r2,-32402(gp) + 80185d4: 10803fcc andi r2,r2,255 + 80185d8: 1080201c xori r2,r2,128 + 80185dc: 10bfe004 addi r2,r2,-128 + 80185e0: 10c01324 muli r3,r2,76 + 80185e4: 00820174 movhi r2,2053 + 80185e8: 1885883a add r2,r3,r2 + 80185ec: 102e5e05 stb zero,-18056(r2) + tse_mac_device[tse_system_count].tse_shared_fifo_tx_ctrl_base = TSE_NO_SHARED_FIFO; + 80185f0: d0a05b83 ldbu r2,-32402(gp) + 80185f4: 10803fcc andi r2,r2,255 + 80185f8: 1080201c xori r2,r2,128 + 80185fc: 10bfe004 addi r2,r2,-128 + 8018600: 10c01324 muli r3,r2,76 + 8018604: 00820174 movhi r2,2053 + 8018608: 1885883a add r2,r3,r2 + 801860c: 102e5f15 stw zero,-18052(r2) + tse_mac_device[tse_system_count].tse_shared_fifo_tx_stat_base = TSE_NO_SHARED_FIFO; + 8018610: d0a05b83 ldbu r2,-32402(gp) + 8018614: 10803fcc andi r2,r2,255 + 8018618: 1080201c xori r2,r2,128 + 801861c: 10bfe004 addi r2,r2,-128 + 8018620: 10c01324 muli r3,r2,76 + 8018624: 00820174 movhi r2,2053 + 8018628: 1885883a add r2,r3,r2 + 801862c: 102e6015 stw zero,-18048(r2) + tse_mac_device[tse_system_count].tse_shared_fifo_tx_depth = TSE_NO_SHARED_FIFO; + 8018630: d0a05b83 ldbu r2,-32402(gp) + 8018634: 10803fcc andi r2,r2,255 + 8018638: 1080201c xori r2,r2,128 + 801863c: 10bfe004 addi r2,r2,-128 + 8018640: 10c01324 muli r3,r2,76 + 8018644: 00820174 movhi r2,2053 + 8018648: 1885883a add r2,r3,r2 + 801864c: 102e6115 stw zero,-18044(r2) + + tse_mac_device[tse_system_count].tse_shared_fifo_rx_ctrl_base = TSE_NO_SHARED_FIFO; + 8018650: d0a05b83 ldbu r2,-32402(gp) + 8018654: 10803fcc andi r2,r2,255 + 8018658: 1080201c xori r2,r2,128 + 801865c: 10bfe004 addi r2,r2,-128 + 8018660: 10c01324 muli r3,r2,76 + 8018664: 00820174 movhi r2,2053 + 8018668: 1885883a add r2,r3,r2 + 801866c: 102e6215 stw zero,-18040(r2) + tse_mac_device[tse_system_count].tse_shared_fifo_rx_stat_base = TSE_NO_SHARED_FIFO; + 8018670: d0a05b83 ldbu r2,-32402(gp) + 8018674: 10803fcc andi r2,r2,255 + 8018678: 1080201c xori r2,r2,128 + 801867c: 10bfe004 addi r2,r2,-128 + 8018680: 10c01324 muli r3,r2,76 + 8018684: 00820174 movhi r2,2053 + 8018688: 1885883a add r2,r3,r2 + 801868c: 102e6315 stw zero,-18036(r2) + tse_mac_device[tse_system_count].tse_shared_fifo_rx_depth = TSE_NO_SHARED_FIFO; + 8018690: d0a05b83 ldbu r2,-32402(gp) + 8018694: 10803fcc andi r2,r2,255 + 8018698: 1080201c xori r2,r2,128 + 801869c: 10bfe004 addi r2,r2,-128 + 80186a0: 10c01324 muli r3,r2,76 + 80186a4: 00820174 movhi r2,2053 + 80186a8: 1885883a add r2,r3,r2 + 80186ac: 102e6415 stw zero,-18032(r2) + 80186b0: 00004606 br 80187cc + } + else { + tse_mac_device[tse_system_count].use_shared_fifo = pfifo->use_shared_fifo; + 80186b4: d0a05b83 ldbu r2,-32402(gp) + 80186b8: 10803fcc andi r2,r2,255 + 80186bc: 1080201c xori r2,r2,128 + 80186c0: 10bfe004 addi r2,r2,-128 + 80186c4: e0fffe17 ldw r3,-8(fp) + 80186c8: 18c00003 ldbu r3,0(r3) + 80186cc: 11001324 muli r4,r2,76 + 80186d0: 00820174 movhi r2,2053 + 80186d4: 2085883a add r2,r4,r2 + 80186d8: 10ee5e05 stb r3,-18056(r2) + tse_mac_device[tse_system_count].tse_shared_fifo_tx_ctrl_base = pfifo->tse_shared_fifo_tx_ctrl_base; + 80186dc: d0a05b83 ldbu r2,-32402(gp) + 80186e0: 10803fcc andi r2,r2,255 + 80186e4: 1080201c xori r2,r2,128 + 80186e8: 10bfe004 addi r2,r2,-128 + 80186ec: e0fffe17 ldw r3,-8(fp) + 80186f0: 18c00117 ldw r3,4(r3) + 80186f4: 11001324 muli r4,r2,76 + 80186f8: 00820174 movhi r2,2053 + 80186fc: 2085883a add r2,r4,r2 + 8018700: 10ee5f15 stw r3,-18052(r2) + tse_mac_device[tse_system_count].tse_shared_fifo_tx_stat_base = pfifo->tse_shared_fifo_tx_stat_base; + 8018704: d0a05b83 ldbu r2,-32402(gp) + 8018708: 10803fcc andi r2,r2,255 + 801870c: 1080201c xori r2,r2,128 + 8018710: 10bfe004 addi r2,r2,-128 + 8018714: e0fffe17 ldw r3,-8(fp) + 8018718: 18c00217 ldw r3,8(r3) + 801871c: 11001324 muli r4,r2,76 + 8018720: 00820174 movhi r2,2053 + 8018724: 2085883a add r2,r4,r2 + 8018728: 10ee6015 stw r3,-18048(r2) + tse_mac_device[tse_system_count].tse_shared_fifo_tx_depth = pfifo->tse_shared_fifo_tx_depth; + 801872c: d0a05b83 ldbu r2,-32402(gp) + 8018730: 10803fcc andi r2,r2,255 + 8018734: 1080201c xori r2,r2,128 + 8018738: 10bfe004 addi r2,r2,-128 + 801873c: e0fffe17 ldw r3,-8(fp) + 8018740: 18c00317 ldw r3,12(r3) + 8018744: 11001324 muli r4,r2,76 + 8018748: 00820174 movhi r2,2053 + 801874c: 2085883a add r2,r4,r2 + 8018750: 10ee6115 stw r3,-18044(r2) + + tse_mac_device[tse_system_count].tse_shared_fifo_rx_ctrl_base = pfifo->tse_shared_fifo_rx_ctrl_base; + 8018754: d0a05b83 ldbu r2,-32402(gp) + 8018758: 10803fcc andi r2,r2,255 + 801875c: 1080201c xori r2,r2,128 + 8018760: 10bfe004 addi r2,r2,-128 + 8018764: e0fffe17 ldw r3,-8(fp) + 8018768: 18c00417 ldw r3,16(r3) + 801876c: 11001324 muli r4,r2,76 + 8018770: 00820174 movhi r2,2053 + 8018774: 2085883a add r2,r4,r2 + 8018778: 10ee6215 stw r3,-18040(r2) + tse_mac_device[tse_system_count].tse_shared_fifo_rx_stat_base = pfifo->tse_shared_fifo_rx_stat_base; + 801877c: d0a05b83 ldbu r2,-32402(gp) + 8018780: 10803fcc andi r2,r2,255 + 8018784: 1080201c xori r2,r2,128 + 8018788: 10bfe004 addi r2,r2,-128 + 801878c: e0fffe17 ldw r3,-8(fp) + 8018790: 18c00517 ldw r3,20(r3) + 8018794: 11001324 muli r4,r2,76 + 8018798: 00820174 movhi r2,2053 + 801879c: 2085883a add r2,r4,r2 + 80187a0: 10ee6315 stw r3,-18036(r2) + tse_mac_device[tse_system_count].tse_shared_fifo_rx_depth = pfifo->tse_shared_fifo_rx_depth; + 80187a4: d0a05b83 ldbu r2,-32402(gp) + 80187a8: 10803fcc andi r2,r2,255 + 80187ac: 1080201c xori r2,r2,128 + 80187b0: 10bfe004 addi r2,r2,-128 + 80187b4: e0fffe17 ldw r3,-8(fp) + 80187b8: 18c00617 ldw r3,24(r3) + 80187bc: 11001324 muli r4,r2,76 + 80187c0: 00820174 movhi r2,2053 + 80187c4: 2085883a add r2,r4,r2 + 80187c8: 10ee6415 stw r3,-18032(r2) + } + + /* Add PHY info to alt_tse_system_info structure */ + if(pphy == 0) { + 80187cc: e0bffd17 ldw r2,-12(fp) + 80187d0: 1000121e bne r2,zero,801881c + tse_mac_device[tse_system_count].tse_phy_mdio_address = TSE_PHY_AUTO_ADDRESS; + 80187d4: d0a05b83 ldbu r2,-32402(gp) + 80187d8: 10803fcc andi r2,r2,255 + 80187dc: 1080201c xori r2,r2,128 + 80187e0: 10bfe004 addi r2,r2,-128 + 80187e4: 11001324 muli r4,r2,76 + 80187e8: 00ffffc4 movi r3,-1 + 80187ec: 00820174 movhi r2,2053 + 80187f0: 2085883a add r2,r4,r2 + 80187f4: 10ee6515 stw r3,-18028(r2) + tse_mac_device[tse_system_count].tse_phy_cfg = 0; + 80187f8: d0a05b83 ldbu r2,-32402(gp) + 80187fc: 10803fcc andi r2,r2,255 + 8018800: 1080201c xori r2,r2,128 + 8018804: 10bfe004 addi r2,r2,-128 + 8018808: 10c01324 muli r3,r2,76 + 801880c: 00820174 movhi r2,2053 + 8018810: 1885883a add r2,r3,r2 + 8018814: 102e6615 stw zero,-18024(r2) + 8018818: 00001406 br 801886c + } + else { + tse_mac_device[tse_system_count].tse_phy_mdio_address = pphy->tse_phy_mdio_address; + 801881c: d0a05b83 ldbu r2,-32402(gp) + 8018820: 10803fcc andi r2,r2,255 + 8018824: 1080201c xori r2,r2,128 + 8018828: 10bfe004 addi r2,r2,-128 + 801882c: e0fffd17 ldw r3,-12(fp) + 8018830: 18c00017 ldw r3,0(r3) + 8018834: 11001324 muli r4,r2,76 + 8018838: 00820174 movhi r2,2053 + 801883c: 2085883a add r2,r4,r2 + 8018840: 10ee6515 stw r3,-18028(r2) + tse_mac_device[tse_system_count].tse_phy_cfg = pphy->tse_phy_cfg; + 8018844: d0a05b83 ldbu r2,-32402(gp) + 8018848: 10803fcc andi r2,r2,255 + 801884c: 1080201c xori r2,r2,128 + 8018850: 10bfe004 addi r2,r2,-128 + 8018854: e0fffd17 ldw r3,-12(fp) + 8018858: 18c00117 ldw r3,4(r3) + 801885c: 11001324 muli r4,r2,76 + 8018860: 00820174 movhi r2,2053 + 8018864: 2085883a add r2,r4,r2 + 8018868: 10ee6615 stw r3,-18024(r2) + } + + /* Point to next structure */ + pmsgdma++; + 801886c: e0bffb17 ldw r2,-20(fp) + 8018870: 10800304 addi r2,r2,12 + 8018874: e0bffb15 stw r2,-20(fp) + if(pmem) pmem++; + 8018878: e0bffc17 ldw r2,-16(fp) + 801887c: 10000326 beq r2,zero,801888c + 8018880: e0bffc17 ldw r2,-16(fp) + 8018884: 10800204 addi r2,r2,8 + 8018888: e0bffc15 stw r2,-16(fp) + if(pfifo) pfifo++; + 801888c: e0bffe17 ldw r2,-8(fp) + 8018890: 10000326 beq r2,zero,80188a0 + 8018894: e0bffe17 ldw r2,-8(fp) + 8018898: 10800704 addi r2,r2,28 + 801889c: e0bffe15 stw r2,-8(fp) + if(pphy) pphy++; + 80188a0: e0bffd17 ldw r2,-12(fp) + 80188a4: 10000326 beq r2,zero,80188b4 + 80188a8: e0bffd17 ldw r2,-12(fp) + 80188ac: 10800204 addi r2,r2,8 + 80188b0: e0bffd15 stw r2,-12(fp) + + tse_system_count++; + 80188b4: d0a05b83 ldbu r2,-32402(gp) + 80188b8: 10800044 addi r2,r2,1 + 80188bc: d0a05b85 stb r2,-32402(gp) + max_mac_system = tse_system_count; + 80188c0: d0a05b83 ldbu r2,-32402(gp) + 80188c4: d0a00a05 stb r2,-32728(gp) + for(i = 0; i < loop_end; i++) { + 80188c8: e0bffa17 ldw r2,-24(fp) + 80188cc: 10800044 addi r2,r2,1 + 80188d0: e0bffa15 stw r2,-24(fp) + 80188d4: e0fffa17 ldw r3,-24(fp) + 80188d8: e0bff917 ldw r2,-28(fp) + 80188dc: 18be0016 blt r3,r2,80180e0 + } + + return SUCCESS; + 80188e0: 0005883a mov r2,zero + +} + 80188e4: e6ffff04 addi sp,fp,-4 + 80188e8: dfc00217 ldw ra,8(sp) + 80188ec: df000117 ldw fp,4(sp) + 80188f0: dc000017 ldw r16,0(sp) + 80188f4: dec00304 addi sp,sp,12 + 80188f8: f800283a ret + +080188fc : + * @param number_of_mac number of MAC sharing MDIO block + * @return SUCCESS on success + * ALTERA_TSE_SYSTEM_DEF_ERROR if definition of system incorrect or pointer == NULL + * Multi-channel MAC not supported + */ +alt_32 alt_tse_sys_enable_mdio_sharing(alt_tse_system_mac **psys_mac_list, alt_u8 number_of_mac) { + 80188fc: defff904 addi sp,sp,-28 + 8018900: dfc00615 stw ra,24(sp) + 8018904: df000515 stw fp,20(sp) + 8018908: df000504 addi fp,sp,20 + 801890c: e13ffc15 stw r4,-16(fp) + 8018910: 2805883a mov r2,r5 + 8018914: e0bffb05 stb r2,-20(fp) + alt_32 i; + alt_32 j; + + alt_tse_system_mac *psys_mac; + + for(i = 0; i < number_of_mac; i++) { + 8018918: e03fff15 stw zero,-4(fp) + 801891c: 00003f06 br 8018a1c + psys_mac = psys_mac_list[i]; + 8018920: e0bfff17 ldw r2,-4(fp) + 8018924: 100490ba slli r2,r2,2 + 8018928: e0fffc17 ldw r3,-16(fp) + 801892c: 1885883a add r2,r3,r2 + 8018930: 10800017 ldw r2,0(r2) + 8018934: e0bffd15 stw r2,-12(fp) + + if(psys_mac == 0) { + 8018938: e0bffd17 ldw r2,-12(fp) + 801893c: 1000081e bne r2,zero,8018960 + tse_dprintf(2, "ERROR : MAC system structure == NULL\n"); + 8018940: 01020134 movhi r4,2052 + 8018944: 211eb304 addi r4,r4,31436 + 8018948: 8002d9c0 call 8002d9c + tse_dprintf(2, "ERROR : Please pass in correct pointer to alt_tse_sys_enable_mdio_sharing()\n"); + 801894c: 01020134 movhi r4,2052 + 8018950: 211f1804 addi r4,r4,31840 + 8018954: 8002d9c0 call 8002d9c + return ALTERA_TSE_SYSTEM_DEF_ERROR; + 8018958: 00bfffc4 movi r2,-1 + 801895c: 00003306 br 8018a2c + } + + for(j = 0; j < max_mac_system; j++) { + 8018960: e03ffe15 stw zero,-8(fp) + 8018964: 00002606 br 8018a00 + + if(psys_mac->tse_mac_base == tse_mac_device[j].tse_mac_base) { + 8018968: e0bffd17 ldw r2,-12(fp) + 801896c: 10c00017 ldw r3,0(r2) + 8018970: e0bffe17 ldw r2,-8(fp) + 8018974: 11001324 muli r4,r2,76 + 8018978: 00820174 movhi r2,2053 + 801897c: 2085883a add r2,r4,r2 + 8018980: 10ae5417 ldw r2,-18096(r2) + 8018984: 18801b1e bne r3,r2,80189f4 + if(tse_mac_device[j].tse_multichannel_mac) { + 8018988: e0bffe17 ldw r2,-8(fp) + 801898c: 10c01324 muli r3,r2,76 + 8018990: 00820174 movhi r2,2053 + 8018994: 1885883a add r2,r3,r2 + 8018998: 10ae57c3 ldbu r2,-18081(r2) + 801899c: 10803fcc andi r2,r2,255 + 80189a0: 10000826 beq r2,zero,80189c4 + tse_dprintf(2, "ERROR : MDIO sharing supported by default for Multi-channel MAC\n"); + 80189a4: 01020134 movhi r4,2052 + 80189a8: 211f2c04 addi r4,r4,31920 + 80189ac: 8002d9c0 call 8002d9c + tse_dprintf(2, "ERROR : Do not include Multi-channel MAC in the MAC List\n"); + 80189b0: 01020134 movhi r4,2052 + 80189b4: 211f3d04 addi r4,r4,31988 + 80189b8: 8002d9c0 call 8002d9c + return ALTERA_TSE_SYSTEM_DEF_ERROR; + 80189bc: 00bfffc4 movi r2,-1 + 80189c0: 00001a06 br 8018a2c + } + + tse_mac_device[j].tse_mdio_shared = 1; + 80189c4: e0bffe17 ldw r2,-8(fp) + 80189c8: 11001324 muli r4,r2,76 + 80189cc: 00c00044 movi r3,1 + 80189d0: 00820174 movhi r2,2053 + 80189d4: 2085883a add r2,r4,r2 + 80189d8: 10ee5845 stb r3,-18079(r2) + tse_mac_device[j].tse_number_of_mac_mdio_shared = number_of_mac; + 80189dc: e0bffe17 ldw r2,-8(fp) + 80189e0: 11001324 muli r4,r2,76 + 80189e4: e0fffb03 ldbu r3,-20(fp) + 80189e8: 00820174 movhi r2,2053 + 80189ec: 2085883a add r2,r4,r2 + 80189f0: 10ee5885 stb r3,-18078(r2) + for(j = 0; j < max_mac_system; j++) { + 80189f4: e0bffe17 ldw r2,-8(fp) + 80189f8: 10800044 addi r2,r2,1 + 80189fc: e0bffe15 stw r2,-8(fp) + 8018a00: d0a00a03 ldbu r2,-32728(gp) + 8018a04: 10803fcc andi r2,r2,255 + 8018a08: e0fffe17 ldw r3,-8(fp) + 8018a0c: 18bfd616 blt r3,r2,8018968 + for(i = 0; i < number_of_mac; i++) { + 8018a10: e0bfff17 ldw r2,-4(fp) + 8018a14: 10800044 addi r2,r2,1 + 8018a18: e0bfff15 stw r2,-4(fp) + 8018a1c: e0bffb03 ldbu r2,-20(fp) + 8018a20: e0ffff17 ldw r3,-4(fp) + 8018a24: 18bfbe16 blt r3,r2,8018920 + } + } + } + + return SUCCESS; + 8018a28: 0005883a mov r2,zero +} + 8018a2c: e037883a mov sp,fp + 8018a30: dfc00117 ldw ra,4(sp) + 8018a34: df000017 ldw fp,0(sp) + 8018a38: dec00204 addi sp,sp,8 + 8018a3c: f800283a ret + +08018a40 : +/* @Function Description: Get the common speed supported by all PHYs connected to the MAC within the same group + * @API Type: Public + * @param pmac Pointer to the TSE MAC Control Interface Base address + * @return common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if no common speed found + */ +alt_32 alt_tse_mac_get_common_speed(np_tse_mac *pmac) { + 8018a40: defffc04 addi sp,sp,-16 + 8018a44: dfc00315 stw ra,12(sp) + 8018a48: df000215 stw fp,8(sp) + 8018a4c: df000204 addi fp,sp,8 + 8018a50: e13ffe15 stw r4,-8(fp) + alt_tse_mac_group *pmac_group = alt_tse_get_mac_info(pmac)->pmac_group; + 8018a54: e13ffe17 ldw r4,-8(fp) + 8018a58: 8018c1c0 call 8018c1c + 8018a5c: 10800317 ldw r2,12(r2) + 8018a60: e0bfff15 stw r2,-4(fp) + return alt_tse_phy_get_common_speed(pmac_group); + 8018a64: e13fff17 ldw r4,-4(fp) + 8018a68: 801bdb00 call 801bdb0 +} + 8018a6c: e037883a mov sp,fp + 8018a70: dfc00117 ldw ra,4(sp) + 8018a74: df000017 ldw fp,0(sp) + 8018a78: dec00204 addi sp,sp,8 + 8018a7c: f800283a ret + +08018a80 : + * @API Type: Public + * @param pmac Pointer to the TSE MAC Control Interface Base address + * common_speed common speed supported by all PHYs + * @return common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if invalid common speed specified + */ +alt_32 alt_tse_mac_set_common_speed(np_tse_mac *pmac, alt_32 common_speed) { + 8018a80: defffb04 addi sp,sp,-20 + 8018a84: dfc00415 stw ra,16(sp) + 8018a88: df000315 stw fp,12(sp) + 8018a8c: df000304 addi fp,sp,12 + 8018a90: e13ffe15 stw r4,-8(fp) + 8018a94: e17ffd15 stw r5,-12(fp) + alt_tse_mac_group *pmac_group = alt_tse_get_mac_info(pmac)->pmac_group; + 8018a98: e13ffe17 ldw r4,-8(fp) + 8018a9c: 8018c1c0 call 8018c1c + 8018aa0: 10800317 ldw r2,12(r2) + 8018aa4: e0bfff15 stw r2,-4(fp) + return alt_tse_phy_set_common_speed(pmac_group, common_speed); + 8018aa8: e17ffd17 ldw r5,-12(fp) + 8018aac: e13fff17 ldw r4,-4(fp) + 8018ab0: 801c0cc0 call 801c0cc +} + 8018ab4: e037883a mov sp,fp + 8018ab8: dfc00117 ldw ra,4(sp) + 8018abc: df000017 ldw fp,0(sp) + 8018ac0: dec00204 addi sp,sp,8 + 8018ac4: f800283a ret + +08018ac8 : +/* @Function Description: Get the index of alt_tse_system_info structure in tse_mac_device[] + * @API Type: Internal + * @param psys_info Pointer to the alt_tse_system_info structure + * @return Index of alt_tse_system_info structure in tse_mac_device[] + */ +alt_32 alt_tse_get_system_index(alt_tse_system_info *psys_info) { + 8018ac8: defffd04 addi sp,sp,-12 + 8018acc: df000215 stw fp,8(sp) + 8018ad0: df000204 addi fp,sp,8 + 8018ad4: e13ffe15 stw r4,-8(fp) + alt_32 i; + + for(i = 0; i < max_mac_system; i++) { + 8018ad8: e03fff15 stw zero,-4(fp) + 8018adc: 00000c06 br 8018b10 + if(psys_info == &tse_mac_device[i]) { + 8018ae0: e0bfff17 ldw r2,-4(fp) + 8018ae4: 10c01324 muli r3,r2,76 + 8018ae8: 00820174 movhi r2,2053 + 8018aec: 10ae5404 addi r2,r2,-18096 + 8018af0: 1885883a add r2,r3,r2 + 8018af4: e0fffe17 ldw r3,-8(fp) + 8018af8: 1880021e bne r3,r2,8018b04 + return i; + 8018afc: e0bfff17 ldw r2,-4(fp) + 8018b00: 00000806 br 8018b24 + for(i = 0; i < max_mac_system; i++) { + 8018b04: e0bfff17 ldw r2,-4(fp) + 8018b08: 10800044 addi r2,r2,1 + 8018b0c: e0bfff15 stw r2,-4(fp) + 8018b10: d0a00a03 ldbu r2,-32728(gp) + 8018b14: 10803fcc andi r2,r2,255 + 8018b18: e0ffff17 ldw r3,-4(fp) + 8018b1c: 18bff016 blt r3,r2,8018ae0 + } + } + return ALTERA_TSE_NO_INDEX_FOUND; + 8018b20: 00bfffc4 movi r2,-1 +} + 8018b24: e037883a mov sp,fp + 8018b28: df000017 ldw fp,0(sp) + 8018b2c: dec00104 addi sp,sp,4 + 8018b30: f800283a ret + +08018b34 : +/* @Function Description: Get the index of alt_tse_mac_group structure in pmac_groups[] + * @API Type: Internal + * @param pmac_group Pointer to the alt_tse_mac_group structure + * @return Index of alt_tse_mac_group structure in pmac_groups[] + */ +alt_32 alt_tse_get_mac_group_index(alt_tse_mac_group *pmac_group) { + 8018b34: defffd04 addi sp,sp,-12 + 8018b38: df000215 stw fp,8(sp) + 8018b3c: df000204 addi fp,sp,8 + 8018b40: e13ffe15 stw r4,-8(fp) + alt_32 i; + + for(i = 0; i < mac_group_count; i++) { + 8018b44: e03fff15 stw zero,-4(fp) + 8018b48: 00000c06 br 8018b7c + if(pmac_group == pmac_groups[i]) { + 8018b4c: e0bfff17 ldw r2,-4(fp) + 8018b50: 100690ba slli r3,r2,2 + 8018b54: 008201b4 movhi r2,2054 + 8018b58: 1885883a add r2,r3,r2 + 8018b5c: 10b5aa17 ldw r2,-10584(r2) + 8018b60: e0fffe17 ldw r3,-8(fp) + 8018b64: 1880021e bne r3,r2,8018b70 + return i; + 8018b68: e0bfff17 ldw r2,-4(fp) + 8018b6c: 00000806 br 8018b90 + for(i = 0; i < mac_group_count; i++) { + 8018b70: e0bfff17 ldw r2,-4(fp) + 8018b74: 10800044 addi r2,r2,1 + 8018b78: e0bfff15 stw r2,-4(fp) + 8018b7c: d0a05b43 ldbu r2,-32403(gp) + 8018b80: 10803fcc andi r2,r2,255 + 8018b84: e0ffff17 ldw r3,-4(fp) + 8018b88: 18bff016 blt r3,r2,8018b4c + } + } + return ALTERA_TSE_NO_INDEX_FOUND; + 8018b8c: 00bfffc4 movi r2,-1 +} + 8018b90: e037883a mov sp,fp + 8018b94: df000017 ldw fp,0(sp) + 8018b98: dec00104 addi sp,sp,4 + 8018b9c: f800283a ret + +08018ba0 : +/* @Function Description: Get the index of alt_tse_mac_info structure in pmac_groups[]->pmac_info[] + * @API Type: Internal + * @param pmac_group Pointer to the alt_tse_mac_info structure + * @return Index of alt_tse_mac_info structure in pmac_groups[]->pmac_info[] + */ +alt_32 alt_tse_get_mac_info_index(alt_tse_mac_info *pmac_info) { + 8018ba0: defffd04 addi sp,sp,-12 + 8018ba4: df000215 stw fp,8(sp) + 8018ba8: df000204 addi fp,sp,8 + 8018bac: e13ffe15 stw r4,-8(fp) + alt_32 i; + + for(i = 0; i < pmac_info->pmac_group->channel; i++) { + 8018bb0: e03fff15 stw zero,-4(fp) + 8018bb4: 00000e06 br 8018bf0 + if(pmac_info == pmac_info->pmac_group->pmac_info[i]) { + 8018bb8: e0bffe17 ldw r2,-8(fp) + 8018bbc: 10c00317 ldw r3,12(r2) + 8018bc0: e0bfff17 ldw r2,-4(fp) + 8018bc4: 10800044 addi r2,r2,1 + 8018bc8: 100490ba slli r2,r2,2 + 8018bcc: 1885883a add r2,r3,r2 + 8018bd0: 10800017 ldw r2,0(r2) + 8018bd4: e0fffe17 ldw r3,-8(fp) + 8018bd8: 1880021e bne r3,r2,8018be4 + return i; + 8018bdc: e0bfff17 ldw r2,-4(fp) + 8018be0: 00000a06 br 8018c0c + for(i = 0; i < pmac_info->pmac_group->channel; i++) { + 8018be4: e0bfff17 ldw r2,-4(fp) + 8018be8: 10800044 addi r2,r2,1 + 8018bec: e0bfff15 stw r2,-4(fp) + 8018bf0: e0bffe17 ldw r2,-8(fp) + 8018bf4: 10800317 ldw r2,12(r2) + 8018bf8: 10800003 ldbu r2,0(r2) + 8018bfc: 10803fcc andi r2,r2,255 + 8018c00: e0ffff17 ldw r3,-4(fp) + 8018c04: 18bfec16 blt r3,r2,8018bb8 + } + } + + return ALTERA_TSE_NO_INDEX_FOUND; + 8018c08: 00bfffc4 movi r2,-1 +} + 8018c0c: e037883a mov sp,fp + 8018c10: df000017 ldw fp,0(sp) + 8018c14: dec00104 addi sp,sp,4 + 8018c18: f800283a ret + +08018c1c : +/* @Function Description: Get the pointer of alt_tse_mac_info structure in pmac_groups[]->pmac_info[] + * @API Type: Internal + * @param pmac Pointer to the TSE MAC Control Interface Base address + * @return Pointer to alt_tse_mac_info structure in pmac_groups[]->pmac_info[] + */ +alt_tse_mac_info *alt_tse_get_mac_info(np_tse_mac *pmac) { + 8018c1c: defffa04 addi sp,sp,-24 + 8018c20: df000515 stw fp,20(sp) + 8018c24: df000504 addi fp,sp,20 + 8018c28: e13ffb15 stw r4,-20(fp) + alt_32 i; + alt_32 j; + alt_tse_mac_group *pmac_group = 0; + 8018c2c: e03ffd15 stw zero,-12(fp) + alt_tse_mac_info *pmac_info = 0; + 8018c30: e03ffc15 stw zero,-16(fp) + + for(i = 0; i < mac_group_count; i++) { + 8018c34: e03fff15 stw zero,-4(fp) + 8018c38: 00002206 br 8018cc4 + pmac_group = pmac_groups[i]; + 8018c3c: e0bfff17 ldw r2,-4(fp) + 8018c40: 100690ba slli r3,r2,2 + 8018c44: 008201b4 movhi r2,2054 + 8018c48: 1885883a add r2,r3,r2 + 8018c4c: 10b5aa17 ldw r2,-10584(r2) + 8018c50: e0bffd15 stw r2,-12(fp) + for(j = 0; j < pmac_group->channel; j++) { + 8018c54: e03ffe15 stw zero,-8(fp) + 8018c58: 00001206 br 8018ca4 + pmac_info = pmac_group->pmac_info[j]; + 8018c5c: e0fffd17 ldw r3,-12(fp) + 8018c60: e0bffe17 ldw r2,-8(fp) + 8018c64: 10800044 addi r2,r2,1 + 8018c68: 100490ba slli r2,r2,2 + 8018c6c: 1885883a add r2,r3,r2 + 8018c70: 10800017 ldw r2,0(r2) + 8018c74: e0bffc15 stw r2,-16(fp) + if(((np_tse_mac *) pmac_info->psys_info->tse_mac_base) == pmac) { + 8018c78: e0bffc17 ldw r2,-16(fp) + 8018c7c: 10800217 ldw r2,8(r2) + 8018c80: 10800017 ldw r2,0(r2) + 8018c84: 1007883a mov r3,r2 + 8018c88: e0bffb17 ldw r2,-20(fp) + 8018c8c: 10c0021e bne r2,r3,8018c98 + return pmac_info; + 8018c90: e0bffc17 ldw r2,-16(fp) + 8018c94: 00001006 br 8018cd8 + for(j = 0; j < pmac_group->channel; j++) { + 8018c98: e0bffe17 ldw r2,-8(fp) + 8018c9c: 10800044 addi r2,r2,1 + 8018ca0: e0bffe15 stw r2,-8(fp) + 8018ca4: e0bffd17 ldw r2,-12(fp) + 8018ca8: 10800003 ldbu r2,0(r2) + 8018cac: 10803fcc andi r2,r2,255 + 8018cb0: e0fffe17 ldw r3,-8(fp) + 8018cb4: 18bfe916 blt r3,r2,8018c5c + for(i = 0; i < mac_group_count; i++) { + 8018cb8: e0bfff17 ldw r2,-4(fp) + 8018cbc: 10800044 addi r2,r2,1 + 8018cc0: e0bfff15 stw r2,-4(fp) + 8018cc4: d0a05b43 ldbu r2,-32403(gp) + 8018cc8: 10803fcc andi r2,r2,255 + 8018ccc: e0ffff17 ldw r3,-4(fp) + 8018cd0: 18bfda16 blt r3,r2,8018c3c + } + } + } + + return 0; + 8018cd4: 0005883a mov r2,zero +} + 8018cd8: e037883a mov sp,fp + 8018cdc: df000017 ldw fp,0(sp) + 8018ce0: dec00104 addi sp,sp,4 + 8018ce4: f800283a ret + +08018ce8 : + * @param pmac Pointer to the TSE MAC Control Interface Base address + * @param speed 2 = 1000 Mbps, 1 = 100 Mbps, 0 = 10 Mbps + * @return ENP_PARAM if invalid speed specified, else return SUCCESS + */ +alt_32 alt_tse_mac_set_speed(np_tse_mac *pmac, alt_u8 speed) +{ + 8018ce8: defffc04 addi sp,sp,-16 + 8018cec: df000315 stw fp,12(sp) + 8018cf0: df000304 addi fp,sp,12 + 8018cf4: e13ffe15 stw r4,-8(fp) + 8018cf8: 2805883a mov r2,r5 + 8018cfc: e0bffd05 stb r2,-12(fp) + alt_32 helpvar; + + helpvar = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac); + 8018d00: e0bffe17 ldw r2,-8(fp) + 8018d04: 10800204 addi r2,r2,8 + 8018d08: 10800037 ldwio r2,0(r2) + 8018d0c: e0bfff15 stw r2,-4(fp) + + /* 1000 Mbps */ + if(speed == TSE_PHY_SPEED_1000) { + 8018d10: e0bffd03 ldbu r2,-12(fp) + 8018d14: 10800098 cmpnei r2,r2,2 + 8018d18: 1000091e bne r2,zero,8018d40 + helpvar |= ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; + 8018d1c: e0bfff17 ldw r2,-4(fp) + 8018d20: 10800214 ori r2,r2,8 + 8018d24: e0bfff15 stw r2,-4(fp) + helpvar &= ~ALTERA_TSEMAC_CMD_ENA_10_MSK; + 8018d28: e0ffff17 ldw r3,-4(fp) + 8018d2c: 00bf8034 movhi r2,65024 + 8018d30: 10bfffc4 addi r2,r2,-1 + 8018d34: 1884703a and r2,r3,r2 + 8018d38: e0bfff15 stw r2,-4(fp) + 8018d3c: 00001906 br 8018da4 + } + /* 100 Mbps */ + else if(speed == TSE_PHY_SPEED_100) { + 8018d40: e0bffd03 ldbu r2,-12(fp) + 8018d44: 10800058 cmpnei r2,r2,1 + 8018d48: 10000a1e bne r2,zero,8018d74 + helpvar &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; + 8018d4c: e0ffff17 ldw r3,-4(fp) + 8018d50: 00bffdc4 movi r2,-9 + 8018d54: 1884703a and r2,r3,r2 + 8018d58: e0bfff15 stw r2,-4(fp) + helpvar &= ~ALTERA_TSEMAC_CMD_ENA_10_MSK; + 8018d5c: e0ffff17 ldw r3,-4(fp) + 8018d60: 00bf8034 movhi r2,65024 + 8018d64: 10bfffc4 addi r2,r2,-1 + 8018d68: 1884703a and r2,r3,r2 + 8018d6c: e0bfff15 stw r2,-4(fp) + 8018d70: 00000c06 br 8018da4 + } + /* 10 Mbps */ + else if(speed == TSE_PHY_SPEED_10) { + 8018d74: e0bffd03 ldbu r2,-12(fp) + 8018d78: 1000081e bne r2,zero,8018d9c + helpvar &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; + 8018d7c: e0ffff17 ldw r3,-4(fp) + 8018d80: 00bffdc4 movi r2,-9 + 8018d84: 1884703a and r2,r3,r2 + 8018d88: e0bfff15 stw r2,-4(fp) + helpvar |= ALTERA_TSEMAC_CMD_ENA_10_MSK; + 8018d8c: e0bfff17 ldw r2,-4(fp) + 8018d90: 10808034 orhi r2,r2,512 + 8018d94: e0bfff15 stw r2,-4(fp) + 8018d98: 00000206 br 8018da4 + } + else { + return ENP_PARAM; + 8018d9c: 00bffd84 movi r2,-10 + 8018da0: 00000506 br 8018db8 + } + + IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac, helpvar); + 8018da4: e0bffe17 ldw r2,-8(fp) + 8018da8: 10800204 addi r2,r2,8 + 8018dac: e0ffff17 ldw r3,-4(fp) + 8018db0: 10c00035 stwio r3,0(r2) + return SUCCESS; + 8018db4: 0005883a mov r2,zero +} + 8018db8: e037883a mov sp,fp + 8018dbc: df000017 ldw fp,0(sp) + 8018dc0: dec00104 addi sp,sp,4 + 8018dc4: f800283a ret + +08018dc8 : + * @param pmac Pointer to the TSE MAC Control Interface Base address + * @param duplex 1 = Full Duplex, 0 = Half Duplex + * @return ENP_PARAM if invalid duplex specified, else return SUCCESS + */ +alt_32 alt_tse_mac_set_duplex(np_tse_mac *pmac, alt_u8 duplex) +{ + 8018dc8: defffc04 addi sp,sp,-16 + 8018dcc: df000315 stw fp,12(sp) + 8018dd0: df000304 addi fp,sp,12 + 8018dd4: e13ffe15 stw r4,-8(fp) + 8018dd8: 2805883a mov r2,r5 + 8018ddc: e0bffd05 stb r2,-12(fp) + alt_32 helpvar; + + helpvar = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac); + 8018de0: e0bffe17 ldw r2,-8(fp) + 8018de4: 10800204 addi r2,r2,8 + 8018de8: 10800037 ldwio r2,0(r2) + 8018dec: e0bfff15 stw r2,-4(fp) + + /* Half Duplex */ + if(duplex == TSE_PHY_DUPLEX_HALF) { + 8018df0: e0bffd03 ldbu r2,-12(fp) + 8018df4: 1000041e bne r2,zero,8018e08 + helpvar |= ALTERA_TSEMAC_CMD_HD_ENA_MSK; + 8018df8: e0bfff17 ldw r2,-4(fp) + 8018dfc: 10810014 ori r2,r2,1024 + 8018e00: e0bfff15 stw r2,-4(fp) + 8018e04: 00000a06 br 8018e30 + } + /* Full Duplex */ + else if(duplex == TSE_PHY_DUPLEX_FULL) { + 8018e08: e0bffd03 ldbu r2,-12(fp) + 8018e0c: 10800058 cmpnei r2,r2,1 + 8018e10: 1000051e bne r2,zero,8018e28 + helpvar &= ~ALTERA_TSEMAC_CMD_HD_ENA_MSK; + 8018e14: e0ffff17 ldw r3,-4(fp) + 8018e18: 00beffc4 movi r2,-1025 + 8018e1c: 1884703a and r2,r3,r2 + 8018e20: e0bfff15 stw r2,-4(fp) + 8018e24: 00000206 br 8018e30 + } + else { + return ENP_PARAM; + 8018e28: 00bffd84 movi r2,-10 + 8018e2c: 00000506 br 8018e44 + } + + IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac, helpvar); + 8018e30: e0bffe17 ldw r2,-8(fp) + 8018e34: 10800204 addi r2,r2,8 + 8018e38: e0ffff17 ldw r3,-4(fp) + 8018e3c: 10c00035 stwio r3,0(r2) + return SUCCESS; + 8018e40: 0005883a mov r2,zero + +} + 8018e44: e037883a mov sp,fp + 8018e48: df000017 ldw fp,0(sp) + 8018e4c: dec00104 addi sp,sp,4 + 8018e50: f800283a ret + +08018e54 : + (((speed == TSE_PHY_SPEED_1000) ? 1 : 0) << 1) | \ + (((speed == TSE_PHY_SPEED_100) ? 1 : 0) << 2) | \ + (((speed == TSE_PHY_SPEED_10) ? 1 : 0) << 3) | \ + ((speed == TSE_PHY_SPEED_INVALID) ? ALT_TSE_E_INVALID_SPEED : 0)) + +alt_32 getPHYSpeed(np_tse_mac *pmac) { + 8018e54: defff404 addi sp,sp,-48 + 8018e58: dfc00b15 stw ra,44(sp) + 8018e5c: df000a15 stw fp,40(sp) + 8018e60: df000a04 addi fp,sp,40 + 8018e64: e13ff715 stw r4,-36(fp) + + alt_u8 speed = ALTERA_TSE_MAC_SPEED_DEFAULT; + 8018e68: 00800044 movi r2,1 + 8018e6c: e0bffec5 stb r2,-5(fp) + alt_u8 duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT; /* 1 = full ; 0 = half*/ + 8018e70: 00800044 movi r2,1 + 8018e74: e0bffe85 stb r2,-6(fp) + alt_32 result = ALT_TSE_SPEED_DUPLEX(speed, duplex); + 8018e78: e0bffe83 ldbu r2,-6(fp) + 8018e7c: 10c0004c andi r3,r2,1 + 8018e80: e0bffec3 ldbu r2,-5(fp) + 8018e84: 10800098 cmpnei r2,r2,2 + 8018e88: 1000021e bne r2,zero,8018e94 + 8018e8c: 00800084 movi r2,2 + 8018e90: 00000106 br 8018e98 + 8018e94: 0005883a mov r2,zero + 8018e98: 10c6b03a or r3,r2,r3 + 8018e9c: e0bffec3 ldbu r2,-5(fp) + 8018ea0: 10800058 cmpnei r2,r2,1 + 8018ea4: 1000021e bne r2,zero,8018eb0 + 8018ea8: 00800104 movi r2,4 + 8018eac: 00000106 br 8018eb4 + 8018eb0: 0005883a mov r2,zero + 8018eb4: 10c6b03a or r3,r2,r3 + 8018eb8: e0bffec3 ldbu r2,-5(fp) + 8018ebc: 1000021e bne r2,zero,8018ec8 + 8018ec0: 00800204 movi r2,8 + 8018ec4: 00000106 br 8018ecc + 8018ec8: 0005883a mov r2,zero + 8018ecc: 10c6b03a or r3,r2,r3 + 8018ed0: e0bffec3 ldbu r2,-5(fp) + 8018ed4: 108000d8 cmpnei r2,r2,3 + 8018ed8: 1000021e bne r2,zero,8018ee4 + 8018edc: 00800074 movhi r2,1 + 8018ee0: 00000106 br 8018ee8 + 8018ee4: 0005883a mov r2,zero + 8018ee8: 10c4b03a or r2,r2,r3 + 8018eec: e0bfff15 stw r2,-4(fp) + + alt_tse_phy_info *pphy = 0; + 8018ef0: e03ffd15 stw zero,-12(fp) + alt_tse_mac_info *pmac_info = 0; + 8018ef4: e03ffc15 stw zero,-16(fp) + alt_tse_mac_group *pmac_group = 0; + 8018ef8: e03ffb15 stw zero,-20(fp) + alt_tse_system_info *psys = 0; + 8018efc: e03ffa15 stw zero,-24(fp) + + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = 0; + 8018f00: e03ff9c5 stb zero,-25(fp) + alt_8 mac_group_index = 0; + 8018f04: e03ff985 stb zero,-26(fp) + + /* initialized PHYs only once */ + static alt_u8 is_init = 0; + if(is_init == 0) { + 8018f08: d0a05bc3 ldbu r2,-32401(gp) + 8018f0c: 10803fcc andi r2,r2,255 + 8018f10: 1000031e bne r2,zero,8018f20 + alt_tse_phy_init(); + 8018f14: 801ae0c0 call 801ae0c + is_init = 1; + 8018f18: 00800044 movi r2,1 + 8018f1c: d0a05bc5 stb r2,-32401(gp) + } + + /* Look for pmac_group and pmac_info structure based on pmac or iface */ + pmac_info = alt_tse_get_mac_info(pmac); + 8018f20: e13ff717 ldw r4,-36(fp) + 8018f24: 8018c1c0 call 8018c1c + 8018f28: e0bffc15 stw r2,-16(fp) + + if(pmac_info == 0) { + 8018f2c: e0bffc17 ldw r2,-16(fp) + 8018f30: 1000481e bne r2,zero,8019054 + speed = ALTERA_TSE_MAC_SPEED_DEFAULT; + 8018f34: 00800044 movi r2,1 + 8018f38: e0bffec5 stb r2,-5(fp) + duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT; + 8018f3c: 00800044 movi r2,1 + 8018f40: e0bffe85 stb r2,-6(fp) + result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_NO_PMAC_FOUND; + 8018f44: e0bffe83 ldbu r2,-6(fp) + 8018f48: 10c0004c andi r3,r2,1 + 8018f4c: e0bffec3 ldbu r2,-5(fp) + 8018f50: 10800098 cmpnei r2,r2,2 + 8018f54: 1000021e bne r2,zero,8018f60 + 8018f58: 00800084 movi r2,2 + 8018f5c: 00000106 br 8018f64 + 8018f60: 0005883a mov r2,zero + 8018f64: 10c6b03a or r3,r2,r3 + 8018f68: e0bffec3 ldbu r2,-5(fp) + 8018f6c: 10800058 cmpnei r2,r2,1 + 8018f70: 1000021e bne r2,zero,8018f7c + 8018f74: 00800104 movi r2,4 + 8018f78: 00000106 br 8018f80 + 8018f7c: 0005883a mov r2,zero + 8018f80: 10c6b03a or r3,r2,r3 + 8018f84: e0bffec3 ldbu r2,-5(fp) + 8018f88: 1000021e bne r2,zero,8018f94 + 8018f8c: 00800204 movi r2,8 + 8018f90: 00000106 br 8018f98 + 8018f94: 0005883a mov r2,zero + 8018f98: 10c6b03a or r3,r2,r3 + 8018f9c: e0bffec3 ldbu r2,-5(fp) + 8018fa0: 108000d8 cmpnei r2,r2,3 + 8018fa4: 1000021e bne r2,zero,8018fb0 + 8018fa8: 00800074 movhi r2,1 + 8018fac: 00000106 br 8018fb4 + 8018fb0: 0005883a mov r2,zero + 8018fb4: 10c4b03a or r2,r2,r3 + 8018fb8: 10802034 orhi r2,r2,128 + 8018fbc: e0bfff15 stw r2,-4(fp) + tse_dprintf(2, "ERROR : [getPHYSpeed] pmac not found from list of pmac_info[]! Speed = %s Mbps, Duplex = %s\n", speed == TSE_PHY_SPEED_1000 ? "1000" : + 8018fc0: e0bffec3 ldbu r2,-5(fp) + 8018fc4: 108000a0 cmpeqi r2,r2,2 + 8018fc8: 10000e1e bne r2,zero,8019004 + 8018fcc: e0bffec3 ldbu r2,-5(fp) + 8018fd0: 10800060 cmpeqi r2,r2,1 + 8018fd4: 1000081e bne r2,zero,8018ff8 + 8018fd8: e0bffec3 ldbu r2,-5(fp) + 8018fdc: 1000031e bne r2,zero,8018fec + 8018fe0: 00820134 movhi r2,2052 + 8018fe4: 109f4c04 addi r2,r2,32048 + 8018fe8: 00000806 br 801900c + 8018fec: 00820134 movhi r2,2052 + 8018ff0: 109f4d04 addi r2,r2,32052 + 8018ff4: 00000506 br 801900c + 8018ff8: 00820134 movhi r2,2052 + 8018ffc: 109f4f04 addi r2,r2,32060 + 8019000: 00000206 br 801900c + 8019004: 00820134 movhi r2,2052 + 8019008: 109f5004 addi r2,r2,32064 + 801900c: e0fffe83 ldbu r3,-6(fp) + 8019010: 18c00058 cmpnei r3,r3,1 + 8019014: 1800031e bne r3,zero,8019024 + 8019018: 00c20134 movhi r3,2052 + 801901c: 18df5204 addi r3,r3,32072 + 8019020: 00000206 br 801902c + 8019024: 00c20134 movhi r3,2052 + 8019028: 18df5404 addi r3,r3,32080 + 801902c: 180d883a mov r6,r3 + 8019030: 100b883a mov r5,r2 + 8019034: 01020134 movhi r4,2052 + 8019038: 211f5604 addi r4,r4,32088 + 801903c: 8002c780 call 8002c78 + speed == TSE_PHY_SPEED_100 ? "100" : + speed == TSE_PHY_SPEED_10 ? "10" : "Unknown", + duplex == 1 ? "Full" : "Half"); + tse_dprintf(2, "ERROR : [getPHYSpeed] Please define tse_mac_device[] correctly\n"); + 8019040: 01020134 movhi r4,2052 + 8019044: 211f6e04 addi r4,r4,32184 + 8019048: 8002d9c0 call 8002d9c + return result; + 801904c: e0bfff17 ldw r2,-4(fp) + 8019050: 00021906 br 80198b8 + } + + pphy = pmac_info->pphy_info; + 8019054: e0bffc17 ldw r2,-16(fp) + 8019058: 10800117 ldw r2,4(r2) + 801905c: e0bffd15 stw r2,-12(fp) + pmac_group = pmac_info->pmac_group; + 8019060: e0bffc17 ldw r2,-16(fp) + 8019064: 10800317 ldw r2,12(r2) + 8019068: e0bffb15 stw r2,-20(fp) + psys = pmac_info->psys_info; + 801906c: e0bffc17 ldw r2,-16(fp) + 8019070: 10800217 ldw r2,8(r2) + 8019074: e0bffa15 stw r2,-24(fp) + + mac_info_index = alt_tse_get_mac_info_index(pmac_info); + 8019078: e13ffc17 ldw r4,-16(fp) + 801907c: 8018ba00 call 8018ba0 + 8019080: e0bff9c5 stb r2,-25(fp) + mac_group_index = alt_tse_get_mac_group_index(pmac_group); + 8019084: e13ffb17 ldw r4,-20(fp) + 8019088: 8018b340 call 8018b34 + 801908c: e0bff985 stb r2,-26(fp) + + /* MDIO is not used */ + if (pmac_group->pmac_info[0]->psys_info->tse_use_mdio == 0) + 8019090: e0bffb17 ldw r2,-20(fp) + 8019094: 10800117 ldw r2,4(r2) + 8019098: 10800217 ldw r2,8(r2) + 801909c: 10800303 ldbu r2,12(r2) + 80190a0: 10803fcc andi r2,r2,255 + 80190a4: 10005a1e bne r2,zero,8019210 + { + speed = ALTERA_TSE_MAC_SPEED_DEFAULT; + 80190a8: 00800044 movi r2,1 + 80190ac: e0bffec5 stb r2,-5(fp) + duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT; + 80190b0: 00800044 movi r2,1 + 80190b4: e0bffe85 stb r2,-6(fp) + result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_NO_MDIO; + 80190b8: e0bffe83 ldbu r2,-6(fp) + 80190bc: 10c0004c andi r3,r2,1 + 80190c0: e0bffec3 ldbu r2,-5(fp) + 80190c4: 10800098 cmpnei r2,r2,2 + 80190c8: 1000021e bne r2,zero,80190d4 + 80190cc: 00800084 movi r2,2 + 80190d0: 00000106 br 80190d8 + 80190d4: 0005883a mov r2,zero + 80190d8: 10c6b03a or r3,r2,r3 + 80190dc: e0bffec3 ldbu r2,-5(fp) + 80190e0: 10800058 cmpnei r2,r2,1 + 80190e4: 1000021e bne r2,zero,80190f0 + 80190e8: 00800104 movi r2,4 + 80190ec: 00000106 br 80190f4 + 80190f0: 0005883a mov r2,zero + 80190f4: 10c6b03a or r3,r2,r3 + 80190f8: e0bffec3 ldbu r2,-5(fp) + 80190fc: 1000021e bne r2,zero,8019108 + 8019100: 00800204 movi r2,8 + 8019104: 00000106 br 801910c + 8019108: 0005883a mov r2,zero + 801910c: 10c6b03a or r3,r2,r3 + 8019110: e0bffec3 ldbu r2,-5(fp) + 8019114: 108000d8 cmpnei r2,r2,3 + 8019118: 1000021e bne r2,zero,8019124 + 801911c: 00800074 movhi r2,1 + 8019120: 00000106 br 8019128 + 8019124: 0005883a mov r2,zero + 8019128: 10c4b03a or r2,r2,r3 + 801912c: 10801034 orhi r2,r2,64 + 8019130: e0bfff15 stw r2,-4(fp) + usleep(ALTERA_NOMDIO_TIMEOUT_THRESHOLD); + 8019134: 010003f4 movhi r4,15 + 8019138: 21109004 addi r4,r4,16960 + 801913c: 803811c0 call 803811c + if(psys->tse_phy_cfg) { + 8019140: e0bffa17 ldw r2,-24(fp) + 8019144: 10801217 ldw r2,72(r2) + 8019148: 10000d26 beq r2,zero,8019180 + tse_dprintf(4, "WARNING : PHY[%d.%d] - MDIO not enabled! Running user configuration...\n", mac_group_index, mac_info_index); + 801914c: e0bff987 ldb r2,-26(fp) + 8019150: e0fff9c7 ldb r3,-25(fp) + 8019154: 180d883a mov r6,r3 + 8019158: 100b883a mov r5,r2 + 801915c: 01020134 movhi r4,2052 + 8019160: 211f7f04 addi r4,r4,32252 + 8019164: 8002c780 call 8002c78 + result = psys->tse_phy_cfg(pmac); + 8019168: e0bffa17 ldw r2,-24(fp) + 801916c: 10801217 ldw r2,72(r2) + 8019170: e13ff717 ldw r4,-36(fp) + 8019174: 103ee83a callr r2 + 8019178: e0bfff15 stw r2,-4(fp) + 801917c: 00002206 br 8019208 + } + else { + tse_dprintf(4, "WARNING : MAC Group[%d] - MDIO not enabled! Speed = %s, Duplex = %s\n", mac_group_index, speed == TSE_PHY_SPEED_1000 ? "1000" : + 8019180: e13ff987 ldb r4,-26(fp) + 8019184: e0bffec3 ldbu r2,-5(fp) + 8019188: 108000a0 cmpeqi r2,r2,2 + 801918c: 10000e1e bne r2,zero,80191c8 + 8019190: e0bffec3 ldbu r2,-5(fp) + 8019194: 10800060 cmpeqi r2,r2,1 + 8019198: 1000081e bne r2,zero,80191bc + 801919c: e0bffec3 ldbu r2,-5(fp) + 80191a0: 1000031e bne r2,zero,80191b0 + 80191a4: 00820134 movhi r2,2052 + 80191a8: 109f4c04 addi r2,r2,32048 + 80191ac: 00000806 br 80191d0 + 80191b0: 00820134 movhi r2,2052 + 80191b4: 109f4d04 addi r2,r2,32052 + 80191b8: 00000506 br 80191d0 + 80191bc: 00820134 movhi r2,2052 + 80191c0: 109f4f04 addi r2,r2,32060 + 80191c4: 00000206 br 80191d0 + 80191c8: 00820134 movhi r2,2052 + 80191cc: 109f5004 addi r2,r2,32064 + 80191d0: e0fffe83 ldbu r3,-6(fp) + 80191d4: 18c00058 cmpnei r3,r3,1 + 80191d8: 1800031e bne r3,zero,80191e8 + 80191dc: 00c20134 movhi r3,2052 + 80191e0: 18df5204 addi r3,r3,32072 + 80191e4: 00000206 br 80191f0 + 80191e8: 00c20134 movhi r3,2052 + 80191ec: 18df5404 addi r3,r3,32080 + 80191f0: 180f883a mov r7,r3 + 80191f4: 100d883a mov r6,r2 + 80191f8: 200b883a mov r5,r4 + 80191fc: 01020134 movhi r4,2052 + 8019200: 211f9104 addi r4,r4,32324 + 8019204: 8002c780 call 8002c78 + speed == TSE_PHY_SPEED_100 ? "100" : + speed == TSE_PHY_SPEED_10 ? "10" : "Unknown", + duplex == 1 ? "Full" : "Half"); + } + return result; + 8019208: e0bfff17 ldw r2,-4(fp) + 801920c: 0001aa06 br 80198b8 + + /* Not running simulation */ + #ifndef ALT_SIM_OPTIMIZE + + /* These variables declaration are here to avoid "warning: unused variable" message when compile for simulation */ + np_tse_mac *pmac_group_base = (np_tse_mac *) pmac_group->pmac_info[0]->psys_info->tse_mac_base; + 8019210: e0bffb17 ldw r2,-20(fp) + 8019214: 10800117 ldw r2,4(r2) + 8019218: 10800217 ldw r2,8(r2) + 801921c: 10800017 ldw r2,0(r2) + 8019220: e0bff815 stw r2,-32(fp) + + /* if no PHY connected to the MAC */ + if(pphy == 0) { + 8019224: e0bffd17 ldw r2,-12(fp) + 8019228: 1000491e bne r2,zero,8019350 + speed = ALTERA_TSE_MAC_SPEED_DEFAULT; + 801922c: 00800044 movi r2,1 + 8019230: e0bffec5 stb r2,-5(fp) + duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT; + 8019234: 00800044 movi r2,1 + 8019238: e0bffe85 stb r2,-6(fp) + result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_NO_PHY; + 801923c: e0bffe83 ldbu r2,-6(fp) + 8019240: 10c0004c andi r3,r2,1 + 8019244: e0bffec3 ldbu r2,-5(fp) + 8019248: 10800098 cmpnei r2,r2,2 + 801924c: 1000021e bne r2,zero,8019258 + 8019250: 00800084 movi r2,2 + 8019254: 00000106 br 801925c + 8019258: 0005883a mov r2,zero + 801925c: 10c6b03a or r3,r2,r3 + 8019260: e0bffec3 ldbu r2,-5(fp) + 8019264: 10800058 cmpnei r2,r2,1 + 8019268: 1000021e bne r2,zero,8019274 + 801926c: 00800104 movi r2,4 + 8019270: 00000106 br 8019278 + 8019274: 0005883a mov r2,zero + 8019278: 10c6b03a or r3,r2,r3 + 801927c: e0bffec3 ldbu r2,-5(fp) + 8019280: 1000021e bne r2,zero,801928c + 8019284: 00800204 movi r2,8 + 8019288: 00000106 br 8019290 + 801928c: 0005883a mov r2,zero + 8019290: 10c6b03a or r3,r2,r3 + 8019294: e0bffec3 ldbu r2,-5(fp) + 8019298: 108000d8 cmpnei r2,r2,3 + 801929c: 1000021e bne r2,zero,80192a8 + 80192a0: 00800074 movhi r2,1 + 80192a4: 00000106 br 80192ac + 80192a8: 0005883a mov r2,zero + 80192ac: 10c4b03a or r2,r2,r3 + 80192b0: 10800834 orhi r2,r2,32 + 80192b4: e0bfff15 stw r2,-4(fp) + tse_dprintf(2, "ERROR : PHY[%d.%d] - No PHY connected! Speed = %s, Duplex = %s\n", mac_group_index, mac_info_index, speed == TSE_PHY_SPEED_1000 ? "1000" : + 80192b8: e13ff987 ldb r4,-26(fp) + 80192bc: e17ff9c7 ldb r5,-25(fp) + 80192c0: e0bffec3 ldbu r2,-5(fp) + 80192c4: 108000a0 cmpeqi r2,r2,2 + 80192c8: 10000e1e bne r2,zero,8019304 + 80192cc: e0bffec3 ldbu r2,-5(fp) + 80192d0: 10800060 cmpeqi r2,r2,1 + 80192d4: 1000081e bne r2,zero,80192f8 + 80192d8: e0bffec3 ldbu r2,-5(fp) + 80192dc: 1000031e bne r2,zero,80192ec + 80192e0: 00820134 movhi r2,2052 + 80192e4: 109f4c04 addi r2,r2,32048 + 80192e8: 00000806 br 801930c + 80192ec: 00820134 movhi r2,2052 + 80192f0: 109f4d04 addi r2,r2,32052 + 80192f4: 00000506 br 801930c + 80192f8: 00820134 movhi r2,2052 + 80192fc: 109f4f04 addi r2,r2,32060 + 8019300: 00000206 br 801930c + 8019304: 00820134 movhi r2,2052 + 8019308: 109f5004 addi r2,r2,32064 + 801930c: e0fffe83 ldbu r3,-6(fp) + 8019310: 18c00058 cmpnei r3,r3,1 + 8019314: 1800031e bne r3,zero,8019324 + 8019318: 00c20134 movhi r3,2052 + 801931c: 18df5204 addi r3,r3,32072 + 8019320: 00000206 br 801932c + 8019324: 00c20134 movhi r3,2052 + 8019328: 18df5404 addi r3,r3,32080 + 801932c: d8c00015 stw r3,0(sp) + 8019330: 100f883a mov r7,r2 + 8019334: 280d883a mov r6,r5 + 8019338: 200b883a mov r5,r4 + 801933c: 01020134 movhi r4,2052 + 8019340: 211fa304 addi r4,r4,32396 + 8019344: 8002c780 call 8002c78 + speed == TSE_PHY_SPEED_100 ? "100" : + speed == TSE_PHY_SPEED_10 ? "10" : "Unknown", + duplex == 1 ? "Full" : "Half"); + return result; + 8019348: e0bfff17 ldw r2,-4(fp) + 801934c: 00015a06 br 80198b8 + } + + /* Small MAC */ + if(pmac_info->mac_type == ALTERA_TSE_MACLITE_10_100) { + 8019350: e0bffc17 ldw r2,-16(fp) + 8019354: 10800003 ldbu r2,0(r2) + 8019358: 10803fcc andi r2,r2,255 + 801935c: 10800058 cmpnei r2,r2,1 + 8019360: 1000071e bne r2,zero,8019380 + alt_tse_phy_set_adv_1000(pphy, 0); + 8019364: 000b883a mov r5,zero + 8019368: e13ffd17 ldw r4,-12(fp) + 801936c: 801b7f00 call 801b7f0 + alt_tse_phy_restart_an(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD); + 8019370: 01427104 movi r5,2500 + 8019374: e13ffd17 ldw r4,-12(fp) + 8019378: 801af180 call 801af18 + 801937c: 00000e06 br 80193b8 + } + else if(pmac_info->mac_type == ALTERA_TSE_MACLITE_1000) { + 8019380: e0bffc17 ldw r2,-16(fp) + 8019384: 10800003 ldbu r2,0(r2) + 8019388: 10803fcc andi r2,r2,255 + 801938c: 10800098 cmpnei r2,r2,2 + 8019390: 1000091e bne r2,zero,80193b8 + alt_tse_phy_set_adv_100(pphy, 0); + 8019394: 000b883a mov r5,zero + 8019398: e13ffd17 ldw r4,-12(fp) + 801939c: 801b9b40 call 801b9b4 + alt_tse_phy_set_adv_10(pphy, 0); + 80193a0: 000b883a mov r5,zero + 80193a4: e13ffd17 ldw r4,-12(fp) + 80193a8: 801bc080 call 801bc08 + alt_tse_phy_restart_an(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD); + 80193ac: 01427104 movi r5,2500 + 80193b0: e13ffd17 ldw r4,-12(fp) + 80193b4: 801af180 call 801af18 + } + + /* check link connection for this PHY */ + if(alt_tse_phy_check_link(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD) == TSE_PHY_AN_NOT_COMPLETE) { + 80193b8: 01427104 movi r5,2500 + 80193bc: e13ffd17 ldw r4,-12(fp) + 80193c0: 801b0dc0 call 801b0dc + 80193c4: 10bfffd8 cmpnei r2,r2,-1 + 80193c8: 1000491e bne r2,zero,80194f0 + speed = ALTERA_TSE_MAC_SPEED_DEFAULT; + 80193cc: 00800044 movi r2,1 + 80193d0: e0bffec5 stb r2,-5(fp) + duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT; + 80193d4: 00800044 movi r2,1 + 80193d8: e0bffe85 stb r2,-6(fp) + result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_AN_NOT_COMPLETE; + 80193dc: e0bffe83 ldbu r2,-6(fp) + 80193e0: 10c0004c andi r3,r2,1 + 80193e4: e0bffec3 ldbu r2,-5(fp) + 80193e8: 10800098 cmpnei r2,r2,2 + 80193ec: 1000021e bne r2,zero,80193f8 + 80193f0: 00800084 movi r2,2 + 80193f4: 00000106 br 80193fc + 80193f8: 0005883a mov r2,zero + 80193fc: 10c6b03a or r3,r2,r3 + 8019400: e0bffec3 ldbu r2,-5(fp) + 8019404: 10800058 cmpnei r2,r2,1 + 8019408: 1000021e bne r2,zero,8019414 + 801940c: 00800104 movi r2,4 + 8019410: 00000106 br 8019418 + 8019414: 0005883a mov r2,zero + 8019418: 10c6b03a or r3,r2,r3 + 801941c: e0bffec3 ldbu r2,-5(fp) + 8019420: 1000021e bne r2,zero,801942c + 8019424: 00800204 movi r2,8 + 8019428: 00000106 br 8019430 + 801942c: 0005883a mov r2,zero + 8019430: 10c6b03a or r3,r2,r3 + 8019434: e0bffec3 ldbu r2,-5(fp) + 8019438: 108000d8 cmpnei r2,r2,3 + 801943c: 1000021e bne r2,zero,8019448 + 8019440: 00800074 movhi r2,1 + 8019444: 00000106 br 801944c + 8019448: 0005883a mov r2,zero + 801944c: 10c4b03a or r2,r2,r3 + 8019450: 10800234 orhi r2,r2,8 + 8019454: e0bfff15 stw r2,-4(fp) + tse_dprintf(3, "WARNING : PHY[%d.%d] - Auto-Negotiation not completed! Speed = %s, Duplex = %s\n", mac_group_index, mac_info_index, speed == TSE_PHY_SPEED_1000 ? "1000" : + 8019458: e13ff987 ldb r4,-26(fp) + 801945c: e17ff9c7 ldb r5,-25(fp) + 8019460: e0bffec3 ldbu r2,-5(fp) + 8019464: 108000a0 cmpeqi r2,r2,2 + 8019468: 10000e1e bne r2,zero,80194a4 + 801946c: e0bffec3 ldbu r2,-5(fp) + 8019470: 10800060 cmpeqi r2,r2,1 + 8019474: 1000081e bne r2,zero,8019498 + 8019478: e0bffec3 ldbu r2,-5(fp) + 801947c: 1000031e bne r2,zero,801948c + 8019480: 00820134 movhi r2,2052 + 8019484: 109f4c04 addi r2,r2,32048 + 8019488: 00000806 br 80194ac + 801948c: 00820134 movhi r2,2052 + 8019490: 109f4d04 addi r2,r2,32052 + 8019494: 00000506 br 80194ac + 8019498: 00820134 movhi r2,2052 + 801949c: 109f4f04 addi r2,r2,32060 + 80194a0: 00000206 br 80194ac + 80194a4: 00820134 movhi r2,2052 + 80194a8: 109f5004 addi r2,r2,32064 + 80194ac: e0fffe83 ldbu r3,-6(fp) + 80194b0: 18c00058 cmpnei r3,r3,1 + 80194b4: 1800031e bne r3,zero,80194c4 + 80194b8: 00c20134 movhi r3,2052 + 80194bc: 18df5204 addi r3,r3,32072 + 80194c0: 00000206 br 80194cc + 80194c4: 00c20134 movhi r3,2052 + 80194c8: 18df5404 addi r3,r3,32080 + 80194cc: d8c00015 stw r3,0(sp) + 80194d0: 100f883a mov r7,r2 + 80194d4: 280d883a mov r6,r5 + 80194d8: 200b883a mov r5,r4 + 80194dc: 01020134 movhi r4,2052 + 80194e0: 211fb404 addi r4,r4,32464 + 80194e4: 8002c780 call 8002c78 + speed == TSE_PHY_SPEED_100 ? "100" : + speed == TSE_PHY_SPEED_10 ? "10" : "Unknown", + duplex == 1 ? "Full" : "Half"); + return result; + 80194e8: e0bfff17 ldw r2,-4(fp) + 80194ec: 0000f206 br 80198b8 + } + + IOWR(&pmac_group_base->MDIO_ADDR1, 0, pphy->mdio_address); + 80194f0: e0bff817 ldw r2,-32(fp) + 80194f4: 10801004 addi r2,r2,64 + 80194f8: e0fffd17 ldw r3,-12(fp) + 80194fc: 18c00003 ldbu r3,0(r3) + 8019500: 18c03fcc andi r3,r3,255 + 8019504: 10c00035 stwio r3,0(r2) + /* To enable PHY loopback */ + #if ENABLE_PHY_LOOPBACK + tse_dprintf(5, "INFO : PHY[%d.%d] - Putting PHY in loopback\n", mac_group_index, mac_info_index); + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_LOOPBACK, 1, 1); // enable PHY loopback + #else + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_LOOPBACK, 1, 0); // disable PHY loopback + 8019508: d8000015 stw zero,0(sp) + 801950c: 01c00044 movi r7,1 + 8019510: 01800384 movi r6,14 + 8019514: 000b883a mov r5,zero + 8019518: e13ffd17 ldw r4,-12(fp) + 801951c: 801996c0 call 801996c + #endif + + /* if PHY not found in profile */ + if(pphy->pphy_profile == 0) { + 8019520: e0bffd17 ldw r2,-12(fp) + 8019524: 10800517 ldw r2,20(r2) + 8019528: 10002b1e bne r2,zero,80195d8 + tse_dprintf(3, "WARNING : PHY[%d.%d] - PHY not found in PHY profile\n", mac_group_index, mac_info_index); + 801952c: e0bff987 ldb r2,-26(fp) + 8019530: e0fff9c7 ldb r3,-25(fp) + 8019534: 180d883a mov r6,r3 + 8019538: 100b883a mov r5,r2 + 801953c: 01020134 movhi r4,2052 + 8019540: 211fc804 addi r4,r4,32544 + 8019544: 8002c780 call 8002c78 + speed = ALTERA_TSE_MAC_SPEED_DEFAULT; + 8019548: 00800044 movi r2,1 + 801954c: e0bffec5 stb r2,-5(fp) + duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT; + 8019550: 00800044 movi r2,1 + 8019554: e0bffe85 stb r2,-6(fp) + result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_NO_PHY_PROFILE; + 8019558: e0bffe83 ldbu r2,-6(fp) + 801955c: 10c0004c andi r3,r2,1 + 8019560: e0bffec3 ldbu r2,-5(fp) + 8019564: 10800098 cmpnei r2,r2,2 + 8019568: 1000021e bne r2,zero,8019574 + 801956c: 00800084 movi r2,2 + 8019570: 00000106 br 8019578 + 8019574: 0005883a mov r2,zero + 8019578: 10c6b03a or r3,r2,r3 + 801957c: e0bffec3 ldbu r2,-5(fp) + 8019580: 10800058 cmpnei r2,r2,1 + 8019584: 1000021e bne r2,zero,8019590 + 8019588: 00800104 movi r2,4 + 801958c: 00000106 br 8019594 + 8019590: 0005883a mov r2,zero + 8019594: 10c6b03a or r3,r2,r3 + 8019598: e0bffec3 ldbu r2,-5(fp) + 801959c: 1000021e bne r2,zero,80195a8 + 80195a0: 00800204 movi r2,8 + 80195a4: 00000106 br 80195ac + 80195a8: 0005883a mov r2,zero + 80195ac: 10c6b03a or r3,r2,r3 + 80195b0: e0bffec3 ldbu r2,-5(fp) + 80195b4: 108000d8 cmpnei r2,r2,3 + 80195b8: 1000021e bne r2,zero,80195c4 + 80195bc: 00800074 movhi r2,1 + 80195c0: 00000106 br 80195c8 + 80195c4: 0005883a mov r2,zero + 80195c8: 10c4b03a or r2,r2,r3 + 80195cc: 10800134 orhi r2,r2,4 + 80195d0: e0bfff15 stw r2,-4(fp) + 80195d4: 00009306 br 8019824 + } + // retrieve duplex information from PHY + else + { + if(pphy->pphy_profile->link_status_read) + 80195d8: e0bffd17 ldw r2,-12(fp) + 80195dc: 10800517 ldw r2,20(r2) + 80195e0: 10801817 ldw r2,96(r2) + 80195e4: 10002526 beq r2,zero,801967c + { + result = pphy->pphy_profile->link_status_read(pmac_group_base); + 80195e8: e0bffd17 ldw r2,-12(fp) + 80195ec: 10800517 ldw r2,20(r2) + 80195f0: 10801817 ldw r2,96(r2) + 80195f4: e13ff817 ldw r4,-32(fp) + 80195f8: 103ee83a callr r2 + 80195fc: e0bfff15 stw r2,-4(fp) + speed = (result & 0x02) ? TSE_PHY_SPEED_1000 : + 8019600: e0bfff17 ldw r2,-4(fp) + 8019604: 1080008c andi r2,r2,2 + 8019608: 10000c1e bne r2,zero,801963c + (result & 0x04) ? TSE_PHY_SPEED_100 : + 801960c: e0bfff17 ldw r2,-4(fp) + 8019610: 1080010c andi r2,r2,4 + speed = (result & 0x02) ? TSE_PHY_SPEED_1000 : + 8019614: 1000071e bne r2,zero,8019634 + (result & 0x08) ? TSE_PHY_SPEED_10 : TSE_PHY_SPEED_INVALID; + 8019618: e0bfff17 ldw r2,-4(fp) + 801961c: 1080020c andi r2,r2,8 + speed = (result & 0x02) ? TSE_PHY_SPEED_1000 : + 8019620: 10000226 beq r2,zero,801962c + 8019624: 0005883a mov r2,zero + 8019628: 00000506 br 8019640 + 801962c: 008000c4 movi r2,3 + 8019630: 00000306 br 8019640 + 8019634: 00800044 movi r2,1 + 8019638: 00000106 br 8019640 + 801963c: 00800084 movi r2,2 + 8019640: e0bffec5 stb r2,-5(fp) + duplex = (result & 0x01) ? TSE_PHY_DUPLEX_FULL : TSE_PHY_DUPLEX_HALF; + 8019644: e0bfff17 ldw r2,-4(fp) + 8019648: 1080004c andi r2,r2,1 + 801964c: e0bffe85 stb r2,-6(fp) + + if(result & ALT_TSE_E_INVALID_SPEED) + 8019650: e0bfff17 ldw r2,-4(fp) + 8019654: 1080006c andhi r2,r2,1 + 8019658: 10007226 beq r2,zero,8019824 + { + tse_dprintf(3, "WARNING : PHY[%d.%d] - Invalid speed read from PHY\n", mac_group_index, mac_info_index); + 801965c: e0bff987 ldb r2,-26(fp) + 8019660: e0fff9c7 ldb r3,-25(fp) + 8019664: 180d883a mov r6,r3 + 8019668: 100b883a mov r5,r2 + 801966c: 01020134 movhi r4,2052 + 8019670: 211fd604 addi r4,r4,32600 + 8019674: 8002c780 call 8002c78 + 8019678: 00006a06 br 8019824 + } + } + else if(pphy->pphy_profile->status_reg_location == 0) + 801967c: e0bffd17 ldw r2,-12(fp) + 8019680: 10800517 ldw r2,20(r2) + 8019684: 10801583 ldbu r2,86(r2) + 8019688: 10803fcc andi r2,r2,255 + 801968c: 10002b1e bne r2,zero,801973c + { + tse_dprintf(3, "WARNING : PHY[%d.%d] - PHY Specific Status register information not provided in profile\n", mac_group_index, mac_info_index); + 8019690: e0bff987 ldb r2,-26(fp) + 8019694: e0fff9c7 ldb r3,-25(fp) + 8019698: 180d883a mov r6,r3 + 801969c: 100b883a mov r5,r2 + 80196a0: 01020134 movhi r4,2052 + 80196a4: 211fe304 addi r4,r4,32652 + 80196a8: 8002c780 call 8002c78 + speed = ALTERA_TSE_MAC_SPEED_DEFAULT; + 80196ac: 00800044 movi r2,1 + 80196b0: e0bffec5 stb r2,-5(fp) + duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT; + 80196b4: 00800044 movi r2,1 + 80196b8: e0bffe85 stb r2,-6(fp) + result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_PROFILE_INCORRECT_DEFINED; + 80196bc: e0bffe83 ldbu r2,-6(fp) + 80196c0: 10c0004c andi r3,r2,1 + 80196c4: e0bffec3 ldbu r2,-5(fp) + 80196c8: 10800098 cmpnei r2,r2,2 + 80196cc: 1000021e bne r2,zero,80196d8 + 80196d0: 00800084 movi r2,2 + 80196d4: 00000106 br 80196dc + 80196d8: 0005883a mov r2,zero + 80196dc: 10c6b03a or r3,r2,r3 + 80196e0: e0bffec3 ldbu r2,-5(fp) + 80196e4: 10800058 cmpnei r2,r2,1 + 80196e8: 1000021e bne r2,zero,80196f4 + 80196ec: 00800104 movi r2,4 + 80196f0: 00000106 br 80196f8 + 80196f4: 0005883a mov r2,zero + 80196f8: 10c6b03a or r3,r2,r3 + 80196fc: e0bffec3 ldbu r2,-5(fp) + 8019700: 1000021e bne r2,zero,801970c + 8019704: 00800204 movi r2,8 + 8019708: 00000106 br 8019710 + 801970c: 0005883a mov r2,zero + 8019710: 10c6b03a or r3,r2,r3 + 8019714: e0bffec3 ldbu r2,-5(fp) + 8019718: 108000d8 cmpnei r2,r2,3 + 801971c: 1000021e bne r2,zero,8019728 + 8019720: 00800074 movhi r2,1 + 8019724: 00000106 br 801972c + 8019728: 0005883a mov r2,zero + 801972c: 10c4b03a or r2,r2,r3 + 8019730: 108000b4 orhi r2,r2,2 + 8019734: e0bfff15 stw r2,-4(fp) + 8019738: 00003a06 br 8019824 + } + else + { + /* extract connection speed and duplex information */ + speed = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->speed_lsb_location, 2); + 801973c: e0bffd17 ldw r2,-12(fp) + 8019740: 10800517 ldw r2,20(r2) + 8019744: 10801583 ldbu r2,86(r2) + 8019748: 10c03fcc andi r3,r2,255 + 801974c: e0bffd17 ldw r2,-12(fp) + 8019750: 10800517 ldw r2,20(r2) + 8019754: 108015c3 ldbu r2,87(r2) + 8019758: 10803fcc andi r2,r2,255 + 801975c: 01c00084 movi r7,2 + 8019760: 100d883a mov r6,r2 + 8019764: 180b883a mov r5,r3 + 8019768: e13ffd17 ldw r4,-12(fp) + 801976c: 8019a980 call 8019a98 + 8019770: e0bffec5 stb r2,-5(fp) + duplex = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->duplex_bit_location, 1); + 8019774: e0bffd17 ldw r2,-12(fp) + 8019778: 10800517 ldw r2,20(r2) + 801977c: 10801583 ldbu r2,86(r2) + 8019780: 10c03fcc andi r3,r2,255 + 8019784: e0bffd17 ldw r2,-12(fp) + 8019788: 10800517 ldw r2,20(r2) + 801978c: 10801603 ldbu r2,88(r2) + 8019790: 10803fcc andi r2,r2,255 + 8019794: 01c00044 movi r7,1 + 8019798: 100d883a mov r6,r2 + 801979c: 180b883a mov r5,r3 + 80197a0: e13ffd17 ldw r4,-12(fp) + 80197a4: 8019a980 call 8019a98 + 80197a8: e0bffe85 stb r2,-6(fp) + + result = ALT_TSE_SPEED_DUPLEX(speed, duplex); + 80197ac: e0bffe83 ldbu r2,-6(fp) + 80197b0: 10c0004c andi r3,r2,1 + 80197b4: e0bffec3 ldbu r2,-5(fp) + 80197b8: 10800098 cmpnei r2,r2,2 + 80197bc: 1000021e bne r2,zero,80197c8 + 80197c0: 00800084 movi r2,2 + 80197c4: 00000106 br 80197cc + 80197c8: 0005883a mov r2,zero + 80197cc: 10c6b03a or r3,r2,r3 + 80197d0: e0bffec3 ldbu r2,-5(fp) + 80197d4: 10800058 cmpnei r2,r2,1 + 80197d8: 1000021e bne r2,zero,80197e4 + 80197dc: 00800104 movi r2,4 + 80197e0: 00000106 br 80197e8 + 80197e4: 0005883a mov r2,zero + 80197e8: 10c6b03a or r3,r2,r3 + 80197ec: e0bffec3 ldbu r2,-5(fp) + 80197f0: 1000021e bne r2,zero,80197fc + 80197f4: 00800204 movi r2,8 + 80197f8: 00000106 br 8019800 + 80197fc: 0005883a mov r2,zero + 8019800: 10c6b03a or r3,r2,r3 + 8019804: e0bffec3 ldbu r2,-5(fp) + 8019808: 108000d8 cmpnei r2,r2,3 + 801980c: 1000021e bne r2,zero,8019818 + 8019810: 00800074 movhi r2,1 + 8019814: 00000106 br 801981c + 8019818: 0005883a mov r2,zero + 801981c: 10c4b03a or r2,r2,r3 + 8019820: e0bfff15 stw r2,-4(fp) + /* for simulation purpose, default to gigabit mode */ + speed = 1; + duplex = 1; + #endif + + tse_dprintf(5, "INFO : PHY[%d.%d] - Speed = %s, Duplex = %s\n", mac_group_index, mac_info_index, speed == TSE_PHY_SPEED_1000 ? "1000" : + 8019824: e13ff987 ldb r4,-26(fp) + 8019828: e17ff9c7 ldb r5,-25(fp) + 801982c: e0bffec3 ldbu r2,-5(fp) + 8019830: 108000a0 cmpeqi r2,r2,2 + 8019834: 10000e1e bne r2,zero,8019870 + 8019838: e0bffec3 ldbu r2,-5(fp) + 801983c: 10800060 cmpeqi r2,r2,1 + 8019840: 1000081e bne r2,zero,8019864 + 8019844: e0bffec3 ldbu r2,-5(fp) + 8019848: 1000031e bne r2,zero,8019858 + 801984c: 00820134 movhi r2,2052 + 8019850: 109f4c04 addi r2,r2,32048 + 8019854: 00000806 br 8019878 + 8019858: 00820134 movhi r2,2052 + 801985c: 109f4d04 addi r2,r2,32052 + 8019860: 00000506 br 8019878 + 8019864: 00820134 movhi r2,2052 + 8019868: 109f4f04 addi r2,r2,32060 + 801986c: 00000206 br 8019878 + 8019870: 00820134 movhi r2,2052 + 8019874: 109f5004 addi r2,r2,32064 + 8019878: e0fffe83 ldbu r3,-6(fp) + 801987c: 18c00058 cmpnei r3,r3,1 + 8019880: 1800031e bne r3,zero,8019890 + 8019884: 00c20134 movhi r3,2052 + 8019888: 18df5204 addi r3,r3,32072 + 801988c: 00000206 br 8019898 + 8019890: 00c20134 movhi r3,2052 + 8019894: 18df5404 addi r3,r3,32080 + 8019898: d8c00015 stw r3,0(sp) + 801989c: 100f883a mov r7,r2 + 80198a0: 280d883a mov r6,r5 + 80198a4: 200b883a mov r5,r4 + 80198a8: 01020134 movhi r4,2052 + 80198ac: 211ffa04 addi r4,r4,32744 + 80198b0: 8002c780 call 8002c78 + speed == TSE_PHY_SPEED_100 ? "100" : + speed == TSE_PHY_SPEED_10 ? "10" : "Unknown", + duplex == 1 ? "Full" : "Half"); + + return result; + 80198b4: e0bfff17 ldw r2,-4(fp) +} + 80198b8: e037883a mov sp,fp + 80198bc: dfc00117 ldw ra,4(sp) + 80198c0: df000017 ldw fp,0(sp) + 80198c4: dec00204 addi sp,sp,8 + 80198c8: f800283a ret + +080198cc : +/* @Function Description: Read MDIO address from the MDIO address1 register of first MAC within MAC group + * @API Type: Internal + * @param pmac Pointer to the alt_tse_phy_info structure + * @return return SUCCESS + */ +alt_32 alt_tse_phy_rd_mdio_addr(alt_tse_phy_info *pphy) { + 80198cc: defffd04 addi sp,sp,-12 + 80198d0: df000215 stw fp,8(sp) + 80198d4: df000204 addi fp,sp,8 + 80198d8: e13ffe15 stw r4,-8(fp) + np_tse_mac *pmac_group_base = (np_tse_mac *) pphy->pmac_info->pmac_group->pmac_info[0]->psys_info->tse_mac_base; + 80198dc: e0bffe17 ldw r2,-8(fp) + 80198e0: 10800617 ldw r2,24(r2) + 80198e4: 10800317 ldw r2,12(r2) + 80198e8: 10800117 ldw r2,4(r2) + 80198ec: 10800217 ldw r2,8(r2) + 80198f0: 10800017 ldw r2,0(r2) + 80198f4: e0bfff15 stw r2,-4(fp) + return IORD(&pmac_group_base->MDIO_ADDR1, 0); + 80198f8: e0bfff17 ldw r2,-4(fp) + 80198fc: 10801004 addi r2,r2,64 + 8019900: 10800037 ldwio r2,0(r2) +} + 8019904: e037883a mov sp,fp + 8019908: df000017 ldw fp,0(sp) + 801990c: dec00104 addi sp,sp,4 + 8019910: f800283a ret + +08019914 : + * @API Type: Internal + * @param pmac Pointer to the alt_tse_phy_info structure + * @param mdio_address MDIO address to be written + * @return return SUCCESS + */ +alt_32 alt_tse_phy_wr_mdio_addr(alt_tse_phy_info *pphy, alt_u8 mdio_address) { + 8019914: defffc04 addi sp,sp,-16 + 8019918: df000315 stw fp,12(sp) + 801991c: df000304 addi fp,sp,12 + 8019920: e13ffe15 stw r4,-8(fp) + 8019924: 2805883a mov r2,r5 + 8019928: e0bffd05 stb r2,-12(fp) + np_tse_mac *pmac_group_base = (np_tse_mac *) pphy->pmac_info->pmac_group->pmac_info[0]->psys_info->tse_mac_base; + 801992c: e0bffe17 ldw r2,-8(fp) + 8019930: 10800617 ldw r2,24(r2) + 8019934: 10800317 ldw r2,12(r2) + 8019938: 10800117 ldw r2,4(r2) + 801993c: 10800217 ldw r2,8(r2) + 8019940: 10800017 ldw r2,0(r2) + 8019944: e0bfff15 stw r2,-4(fp) + IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdio_address); + 8019948: e0bfff17 ldw r2,-4(fp) + 801994c: 10801004 addi r2,r2,64 + 8019950: e0fffd03 ldbu r3,-12(fp) + 8019954: 10c00035 stwio r3,0(r2) + + return SUCCESS; + 8019958: 0005883a mov r2,zero +} + 801995c: e037883a mov sp,fp + 8019960: df000017 ldw fp,0(sp) + 8019964: dec00104 addi sp,sp,4 + 8019968: f800283a ret + +0801996c : + * @param bit_length number of bits to be written to the register. + * @param data data to be written to the register at specific bit location of register. + * @return SUCCESS + */ +alt_32 alt_tse_phy_wr_mdio_reg(alt_tse_phy_info *pphy, alt_u8 reg_num, alt_u8 lsb_num, alt_u8 bit_length, alt_u16 data) +{ + 801996c: defff604 addi sp,sp,-40 + 8019970: df000915 stw fp,36(sp) + 8019974: df000904 addi fp,sp,36 + 8019978: e13ffb15 stw r4,-20(fp) + 801997c: 2807883a mov r3,r5 + 8019980: 300b883a mov r5,r6 + 8019984: 3809883a mov r4,r7 + 8019988: e0800117 ldw r2,4(fp) + 801998c: e0fffa05 stb r3,-24(fp) + 8019990: 2807883a mov r3,r5 + 8019994: e0fff905 stb r3,-28(fp) + 8019998: 2007883a mov r3,r4 + 801999c: e0fff805 stb r3,-32(fp) + 80199a0: e0bff70d sth r2,-36(fp) + + alt_u16 temp_data; + alt_u16 bit_mask; + alt_32 i; + np_tse_mac *pmac = (np_tse_mac *) pphy->pmac_info->pmac_group->pmac_info[0]->psys_info->tse_mac_base; + 80199a4: e0bffb17 ldw r2,-20(fp) + 80199a8: 10800617 ldw r2,24(r2) + 80199ac: 10800317 ldw r2,12(r2) + 80199b0: 10800117 ldw r2,4(r2) + 80199b4: 10800217 ldw r2,8(r2) + 80199b8: 10800017 ldw r2,0(r2) + 80199bc: e0bffd15 stw r2,-12(fp) + + bit_mask = 0x00; + 80199c0: e03fff8d sth zero,-2(fp) + /* generate mask consist of bit_length number of 1 + * eg: bit_length = 3, bit_mask = 0b0000 0000 0000 0111 + */ + for(i = 0; i < bit_length; i++) + 80199c4: e03ffe15 stw zero,-8(fp) + 80199c8: 00000906 br 80199f0 + { + bit_mask <<= 1; + 80199cc: e0bfff8b ldhu r2,-2(fp) + 80199d0: 1085883a add r2,r2,r2 + 80199d4: e0bfff8d sth r2,-2(fp) + bit_mask |= 0x01; + 80199d8: e0bfff8b ldhu r2,-2(fp) + 80199dc: 10800054 ori r2,r2,1 + 80199e0: e0bfff8d sth r2,-2(fp) + for(i = 0; i < bit_length; i++) + 80199e4: e0bffe17 ldw r2,-8(fp) + 80199e8: 10800044 addi r2,r2,1 + 80199ec: e0bffe15 stw r2,-8(fp) + 80199f0: e0bff803 ldbu r2,-32(fp) + 80199f4: e0fffe17 ldw r3,-8(fp) + 80199f8: 18bff416 blt r3,r2,80199cc + } + + /* shifting mask to left by bit_num */ + bit_mask <<= lsb_num; + 80199fc: e0ffff8b ldhu r3,-2(fp) + 8019a00: e0bff903 ldbu r2,-28(fp) + 8019a04: 1884983a sll r2,r3,r2 + 8019a08: e0bfff8d sth r2,-2(fp) + + /* read register data */ + temp_data = IORD(&pmac->mdio1, reg_num); + 8019a0c: e0bffd17 ldw r2,-12(fp) + 8019a10: 1080a004 addi r2,r2,640 + 8019a14: e0fffa03 ldbu r3,-24(fp) + 8019a18: 180690ba slli r3,r3,2 + 8019a1c: 10c5883a add r2,r2,r3 + 8019a20: 10800037 ldwio r2,0(r2) + 8019a24: e0bffc8d sth r2,-14(fp) + + /* clear bits to be written */ + temp_data &= ~bit_mask; + 8019a28: e0bfff8b ldhu r2,-2(fp) + 8019a2c: 0084303a nor r2,zero,r2 + 8019a30: 1007883a mov r3,r2 + 8019a34: e0bffc8b ldhu r2,-14(fp) + 8019a38: 1884703a and r2,r3,r2 + 8019a3c: e0bffc8d sth r2,-14(fp) + + /* OR-ed together corresponding bits data */ + temp_data |= ((data << lsb_num) & bit_mask); + 8019a40: e0fff70b ldhu r3,-36(fp) + 8019a44: e0bff903 ldbu r2,-28(fp) + 8019a48: 1884983a sll r2,r3,r2 + 8019a4c: 1007883a mov r3,r2 + 8019a50: e0bfff8b ldhu r2,-2(fp) + 8019a54: 1884703a and r2,r3,r2 + 8019a58: 1007883a mov r3,r2 + 8019a5c: e0bffc8b ldhu r2,-14(fp) + 8019a60: 1884b03a or r2,r3,r2 + 8019a64: e0bffc8d sth r2,-14(fp) + + /* write data to MDIO register */ + IOWR(&pmac->mdio1, reg_num, temp_data); + 8019a68: e0bffd17 ldw r2,-12(fp) + 8019a6c: 1080a004 addi r2,r2,640 + 8019a70: e0fffa03 ldbu r3,-24(fp) + 8019a74: 180690ba slli r3,r3,2 + 8019a78: 10c5883a add r2,r2,r3 + 8019a7c: e0fffc8b ldhu r3,-14(fp) + 8019a80: 10c00035 stwio r3,0(r2) + + return SUCCESS; + 8019a84: 0005883a mov r2,zero + +} + 8019a88: e037883a mov sp,fp + 8019a8c: df000017 ldw fp,0(sp) + 8019a90: dec00104 addi sp,sp,4 + 8019a94: f800283a ret + +08019a98 : + * @param bit_length number of bits to be read from the register. + * @return data read from MDIO register + */ + +alt_u32 alt_tse_phy_rd_mdio_reg(alt_tse_phy_info *pphy, alt_u8 reg_num, alt_u8 lsb_num, alt_u8 bit_length) +{ + 8019a98: defff704 addi sp,sp,-36 + 8019a9c: df000815 stw fp,32(sp) + 8019aa0: df000804 addi fp,sp,32 + 8019aa4: e13ffb15 stw r4,-20(fp) + 8019aa8: 2805883a mov r2,r5 + 8019aac: 3009883a mov r4,r6 + 8019ab0: 3807883a mov r3,r7 + 8019ab4: e0bffa05 stb r2,-24(fp) + 8019ab8: 2005883a mov r2,r4 + 8019abc: e0bff905 stb r2,-28(fp) + 8019ac0: 1805883a mov r2,r3 + 8019ac4: e0bff805 stb r2,-32(fp) + alt_u16 temp_data; + alt_u32 bit_mask; + alt_32 i; + np_tse_mac *pmac = (np_tse_mac *) pphy->pmac_info->pmac_group->pmac_info[0]->psys_info->tse_mac_base; + 8019ac8: e0bffb17 ldw r2,-20(fp) + 8019acc: 10800617 ldw r2,24(r2) + 8019ad0: 10800317 ldw r2,12(r2) + 8019ad4: 10800117 ldw r2,4(r2) + 8019ad8: 10800217 ldw r2,8(r2) + 8019adc: 10800017 ldw r2,0(r2) + 8019ae0: e0bffd15 stw r2,-12(fp) + + bit_mask = 0x00; + 8019ae4: e03fff15 stw zero,-4(fp) + /* generate mask consist of bit_length number of 1 + * eg: bit_length = 3, bit_mask = 0b0000 0000 0000 0111 + */ + for(i = 0; i < bit_length; i++) + 8019ae8: e03ffe15 stw zero,-8(fp) + 8019aec: 00000906 br 8019b14 + { + bit_mask <<= 1; + 8019af0: e0bfff17 ldw r2,-4(fp) + 8019af4: 1085883a add r2,r2,r2 + 8019af8: e0bfff15 stw r2,-4(fp) + bit_mask |= 0x01; + 8019afc: e0bfff17 ldw r2,-4(fp) + 8019b00: 10800054 ori r2,r2,1 + 8019b04: e0bfff15 stw r2,-4(fp) + for(i = 0; i < bit_length; i++) + 8019b08: e0bffe17 ldw r2,-8(fp) + 8019b0c: 10800044 addi r2,r2,1 + 8019b10: e0bffe15 stw r2,-8(fp) + 8019b14: e0bff803 ldbu r2,-32(fp) + 8019b18: e0fffe17 ldw r3,-8(fp) + 8019b1c: 18bff416 blt r3,r2,8019af0 + } + + /* read register data */ + temp_data = IORD(&pmac->mdio1, reg_num); + 8019b20: e0bffd17 ldw r2,-12(fp) + 8019b24: 1080a004 addi r2,r2,640 + 8019b28: e0fffa03 ldbu r3,-24(fp) + 8019b2c: 180690ba slli r3,r3,2 + 8019b30: 10c5883a add r2,r2,r3 + 8019b34: 10800037 ldwio r2,0(r2) + 8019b38: e0bffc8d sth r2,-14(fp) + + /* shifting read data */ + temp_data >>= lsb_num; + 8019b3c: e0fffc8b ldhu r3,-14(fp) + 8019b40: e0bff903 ldbu r2,-28(fp) + 8019b44: 1885d83a sra r2,r3,r2 + 8019b48: e0bffc8d sth r2,-14(fp) + + return (temp_data & bit_mask); + 8019b4c: e0fffc8b ldhu r3,-14(fp) + 8019b50: e0bfff17 ldw r2,-4(fp) + 8019b54: 1884703a and r2,r3,r2 +} + 8019b58: e037883a mov sp,fp + 8019b5c: df000017 ldw fp,0(sp) + 8019b60: dec00104 addi sp,sp,4 + 8019b64: f800283a ret + +08019b68 : + * @param pmac N/A + * @return Number of PHY in profile + * + * User might add their own PHY by calling alt_tse_phy_add_profile() + */ +alt_32 alt_tse_phy_add_profile_default() { + 8019b68: deff8104 addi sp,sp,-508 + 8019b6c: dfc07e15 stw ra,504(sp) + 8019b70: df007d15 stw fp,500(sp) + 8019b74: df007d04 addi fp,sp,500 + + /* ------------------------------ */ + /* Marvell PHY on PHYWORKX board */ + /* ------------------------------ */ + + alt_tse_phy_profile MV88E1111 = {"Marvell 88E1111", /* Marvell 88E1111 */ + 8019b78: e0bfe704 addi r2,fp,-100 + 8019b7c: 00c01904 movi r3,100 + 8019b80: 180d883a mov r6,r3 + 8019b84: 000b883a mov r5,zero + 8019b88: 1009883a mov r4,r2 + 8019b8c: 80088e40 call 80088e4 + 8019b90: 009d9cb4 movhi r2,30322 + 8019b94: 10985344 addi r2,r2,24909 + 8019b98: e0bfe715 stw r2,-100(fp) + 8019b9c: 00881b34 movhi r2,8300 + 8019ba0: 109b1944 addi r2,r2,27749 + 8019ba4: e0bfe815 stw r2,-96(fp) + 8019ba8: 008c5174 movhi r2,12613 + 8019bac: 108e0e04 addi r2,r2,14392 + 8019bb0: e0bfe915 stw r2,-92(fp) + 8019bb4: 00800c74 movhi r2,49 + 8019bb8: 108c4c44 addi r2,r2,12593 + 8019bbc: e0bfea15 stw r2,-88(fp) + 8019bc0: e0bfeb04 addi r2,fp,-84 + 8019bc4: 00c01004 movi r3,64 + 8019bc8: 180d883a mov r6,r3 + 8019bcc: 000b883a mov r5,zero + 8019bd0: 1009883a mov r4,r2 + 8019bd4: 80088e40 call 80088e4 + 8019bd8: 009410c4 movi r2,20547 + 8019bdc: e0bffb15 stw r2,-20(fp) + 8019be0: 00800304 movi r2,12 + 8019be4: e0bffc05 stb r2,-16(fp) + 8019be8: 00800084 movi r2,2 + 8019bec: e0bffc45 stb r2,-15(fp) + 8019bf0: 00800444 movi r2,17 + 8019bf4: e0bffc85 stb r2,-14(fp) + 8019bf8: 00800384 movi r2,14 + 8019bfc: e0bffcc5 stb r2,-13(fp) + 8019c00: 00800344 movi r2,13 + 8019c04: e0bffd05 stb r2,-12(fp) + 8019c08: 00800284 movi r2,10 + 8019c0c: e0bffd45 stb r2,-11(fp) + 8019c10: 008200b4 movhi r2,2050 + 8019c14: 10b15f04 addi r2,r2,-14980 + 8019c18: e0bffe15 stw r2,-8(fp) + + /* ---------------------------------- */ + /* Marvell Quad PHY on PHYWORKX board */ + /* ---------------------------------- */ + + alt_tse_phy_profile MV88E1145 = {"Marvell Quad PHY 88E1145", /* Marvell 88E1145 */ + 8019c1c: e0bfce04 addi r2,fp,-200 + 8019c20: 00c01904 movi r3,100 + 8019c24: 180d883a mov r6,r3 + 8019c28: 000b883a mov r5,zero + 8019c2c: 1009883a mov r4,r2 + 8019c30: 80088e40 call 80088e4 + 8019c34: 009d9cb4 movhi r2,30322 + 8019c38: 10985344 addi r2,r2,24909 + 8019c3c: e0bfce15 stw r2,-200(fp) + 8019c40: 00881b34 movhi r2,8300 + 8019c44: 109b1944 addi r2,r2,27749 + 8019c48: e0bfcf15 stw r2,-196(fp) + 8019c4c: 00991874 movhi r2,25697 + 8019c50: 109d5444 addi r2,r2,30033 + 8019c54: e0bfd015 stw r2,-192(fp) + 8019c58: 00965234 movhi r2,22856 + 8019c5c: 10940804 addi r2,r2,20512 + 8019c60: e0bfd115 stw r2,-188(fp) + 8019c64: 00914e34 movhi r2,17720 + 8019c68: 108e0804 addi r2,r2,14368 + 8019c6c: e0bfd215 stw r2,-184(fp) + 8019c70: 008d4d34 movhi r2,13620 + 8019c74: 108c4c44 addi r2,r2,12593 + 8019c78: e0bfd315 stw r2,-180(fp) + 8019c7c: e03fd415 stw zero,-176(fp) + 8019c80: e03fd515 stw zero,-172(fp) + 8019c84: e03fd615 stw zero,-168(fp) + 8019c88: e03fd715 stw zero,-164(fp) + 8019c8c: e03fd815 stw zero,-160(fp) + 8019c90: e03fd915 stw zero,-156(fp) + 8019c94: e03fda15 stw zero,-152(fp) + 8019c98: e03fdb15 stw zero,-148(fp) + 8019c9c: e03fdc15 stw zero,-144(fp) + 8019ca0: e03fdd15 stw zero,-140(fp) + 8019ca4: e03fde15 stw zero,-136(fp) + 8019ca8: e03fdf15 stw zero,-132(fp) + 8019cac: e03fe015 stw zero,-128(fp) + 8019cb0: e03fe115 stw zero,-124(fp) + 8019cb4: 009410c4 movi r2,20547 + 8019cb8: e0bfe215 stw r2,-120(fp) + 8019cbc: 00800344 movi r2,13 + 8019cc0: e0bfe305 stb r2,-116(fp) + 8019cc4: 00800084 movi r2,2 + 8019cc8: e0bfe345 stb r2,-115(fp) + 8019ccc: 00800444 movi r2,17 + 8019cd0: e0bfe385 stb r2,-114(fp) + 8019cd4: 00800384 movi r2,14 + 8019cd8: e0bfe3c5 stb r2,-113(fp) + 8019cdc: 00800344 movi r2,13 + 8019ce0: e0bfe405 stb r2,-112(fp) + 8019ce4: 00800284 movi r2,10 + 8019ce8: e0bfe445 stb r2,-111(fp) + 8019cec: 008200b4 movhi r2,2050 + 8019cf0: 10b15f04 addi r2,r2,-14980 + 8019cf4: e0bfe515 stw r2,-108(fp) + + /* ------------------------------ */ + /* National PHY on PHYWORKX board */ + /* ------------------------------ */ + + alt_tse_phy_profile DP83865 = {"National DP83865", /* National DP83865 */ + 8019cf8: e0bfb504 addi r2,fp,-300 + 8019cfc: 00c01904 movi r3,100 + 8019d00: 180d883a mov r6,r3 + 8019d04: 000b883a mov r5,zero + 8019d08: 1009883a mov r4,r2 + 8019d0c: 80088e40 call 80088e4 + 8019d10: 009a5d34 movhi r2,26996 + 8019d14: 10985384 addi r2,r2,24910 + 8019d18: e0bfb515 stw r2,-300(fp) + 8019d1c: 009b1874 movhi r2,27745 + 8019d20: 109b9bc4 addi r2,r2,28271 + 8019d24: e0bfb615 stw r2,-296(fp) + 8019d28: 008e1434 movhi r2,14416 + 8019d2c: 10910804 addi r2,r2,17440 + 8019d30: e0bfb715 stw r2,-292(fp) + 8019d34: 008d4db4 movhi r2,13622 + 8019d38: 108e0cc4 addi r2,r2,14387 + 8019d3c: e0bfb815 stw r2,-288(fp) + 8019d40: e03fb915 stw zero,-284(fp) + 8019d44: e0bfba04 addi r2,fp,-280 + 8019d48: 00c00f04 movi r3,60 + 8019d4c: 180d883a mov r6,r3 + 8019d50: 000b883a mov r5,zero + 8019d54: 1009883a mov r4,r2 + 8019d58: 80088e40 call 80088e4 + 8019d5c: 00800234 movhi r2,8 + 8019d60: 108005c4 addi r2,r2,23 + 8019d64: e0bfc915 stw r2,-220(fp) + 8019d68: 008001c4 movi r2,7 + 8019d6c: e0bfca05 stb r2,-216(fp) + 8019d70: 00800284 movi r2,10 + 8019d74: e0bfca45 stb r2,-215(fp) + 8019d78: 00800444 movi r2,17 + 8019d7c: e0bfca85 stb r2,-214(fp) + 8019d80: 008000c4 movi r2,3 + 8019d84: e0bfcac5 stb r2,-213(fp) + 8019d88: 00800044 movi r2,1 + 8019d8c: e0bfcb05 stb r2,-212(fp) + 8019d90: 00800084 movi r2,2 + 8019d94: e0bfcb45 stb r2,-211(fp) + + /* -------------------------------------- */ + /* National 10/100 PHY on PHYWORKX board */ + /* -------------------------------------- */ + + alt_tse_phy_profile DP83848C = {"National DP83848C", /* National DP83848C */ + 8019d98: e0ff9c04 addi r3,fp,-400 + 8019d9c: 00820174 movhi r2,2053 + 8019da0: 10a00604 addi r2,r2,-32744 + 8019da4: 01001904 movi r4,100 + 8019da8: 200d883a mov r6,r4 + 8019dac: 100b883a mov r5,r2 + 8019db0: 1809883a mov r4,r3 + 8019db4: 80086b80 call 80086b8 + + /* -------------------------------------- */ + /* Intel PHY on C10LP EVA board */ + /* -------------------------------------- */ + + alt_tse_phy_profile PEF7071 = {"Intel PEF7071", /* National DP83848C */ + 8019db8: e0ff8304 addi r3,fp,-500 + 8019dbc: 00820174 movhi r2,2053 + 8019dc0: 10a01f04 addi r2,r2,-32644 + 8019dc4: 01001904 movi r4,100 + 8019dc8: 200d883a mov r6,r4 + 8019dcc: 100b883a mov r5,r2 + 8019dd0: 1809883a mov r4,r3 + 8019dd4: 80086b80 call 80086b8 + &PEF7071_config, /* configure PEF7071 */ + &PEF7071_link_status_read /* Function pointer to read from PHY specific status register */ + }; + + /* add supported PHY to profile */ + alt_tse_phy_add_profile(&MV88E1111); + 8019dd8: e0bfe704 addi r2,fp,-100 + 8019ddc: 1009883a mov r4,r2 + 8019de0: 8017e840 call 8017e84 + alt_tse_phy_add_profile(&MV88E1145); + 8019de4: e0bfce04 addi r2,fp,-200 + 8019de8: 1009883a mov r4,r2 + 8019dec: 8017e840 call 8017e84 + alt_tse_phy_add_profile(&DP83865); + 8019df0: e0bfb504 addi r2,fp,-300 + 8019df4: 1009883a mov r4,r2 + 8019df8: 8017e840 call 8017e84 + alt_tse_phy_add_profile(&DP83848C); + 8019dfc: e0bf9c04 addi r2,fp,-400 + 8019e00: 1009883a mov r4,r2 + 8019e04: 8017e840 call 8017e84 + alt_tse_phy_add_profile(&PEF7071); + 8019e08: e0bf8304 addi r2,fp,-500 + 8019e0c: 1009883a mov r4,r2 + 8019e10: 8017e840 call 8017e84 + + + return phy_profile_count; + 8019e14: d0a05b03 ldbu r2,-32404(gp) + 8019e18: 10803fcc andi r2,r2,255 +} + 8019e1c: e037883a mov sp,fp + 8019e20: dfc00117 ldw ra,4(sp) + 8019e24: df000017 ldw fp,0(sp) + 8019e28: dec00204 addi sp,sp,8 + 8019e2c: f800283a ret + +08019e30 : +/* @Function Description: Display PHYs available in profile + * @API Type: Internal + * @param pmac N/A + * @return Number of PHY in profile + */ +alt_32 alt_tse_phy_print_profile() { + 8019e30: defffd04 addi sp,sp,-12 + 8019e34: dfc00215 stw ra,8(sp) + 8019e38: df000115 stw fp,4(sp) + 8019e3c: df000104 addi fp,sp,4 + + alt_8 i; + /* display PHY in profile */ + tse_dprintf(6, "List of PHY profiles supported (Total profiles = %d)...\n", phy_profile_count); + 8019e40: d0a05b03 ldbu r2,-32404(gp) + 8019e44: 10803fcc andi r2,r2,255 + 8019e48: 100b883a mov r5,r2 + 8019e4c: 01020174 movhi r4,2053 + 8019e50: 21203804 addi r4,r4,-32544 + 8019e54: 8002c780 call 8002c78 + + for(i = 0; i < phy_profile_count; i++) + 8019e58: e03fffc5 stb zero,-1(fp) + 8019e5c: 00005d06 br 8019fd4 + { + tse_dprintf(6, "Profile No.%2d :\n", i); + 8019e60: e0bfffc7 ldb r2,-1(fp) + 8019e64: 100b883a mov r5,r2 + 8019e68: 01020174 movhi r4,2053 + 8019e6c: 21204704 addi r4,r4,-32484 + 8019e70: 8002c780 call 8002c78 + tse_dprintf(6, "PHY Name : %s\n", pphy_profiles[i]->name); + 8019e74: e0bfffc7 ldb r2,-1(fp) + 8019e78: 100690ba slli r3,r2,2 + 8019e7c: 008201b4 movhi r2,2054 + 8019e80: 1885883a add r2,r3,r2 + 8019e84: 10b5ae17 ldw r2,-10568(r2) + 8019e88: 100b883a mov r5,r2 + 8019e8c: 01020174 movhi r4,2053 + 8019e90: 21204c04 addi r4,r4,-32464 + 8019e94: 8002c780 call 8002c78 + + tse_dprintf(6, "PHY OUI : 0x%06x\n", (int)pphy_profiles[i]->oui); + 8019e98: e0bfffc7 ldb r2,-1(fp) + 8019e9c: 100690ba slli r3,r2,2 + 8019ea0: 008201b4 movhi r2,2054 + 8019ea4: 1885883a add r2,r3,r2 + 8019ea8: 10b5ae17 ldw r2,-10568(r2) + 8019eac: 10801417 ldw r2,80(r2) + 8019eb0: 100b883a mov r5,r2 + 8019eb4: 01020174 movhi r4,2053 + 8019eb8: 21205204 addi r4,r4,-32440 + 8019ebc: 8002c780 call 8002c78 + tse_dprintf(6, "PHY Model Num. : 0x%02x\n", pphy_profiles[i]->model_number); + 8019ec0: e0bfffc7 ldb r2,-1(fp) + 8019ec4: 100690ba slli r3,r2,2 + 8019ec8: 008201b4 movhi r2,2054 + 8019ecc: 1885883a add r2,r3,r2 + 8019ed0: 10b5ae17 ldw r2,-10568(r2) + 8019ed4: 10801503 ldbu r2,84(r2) + 8019ed8: 10803fcc andi r2,r2,255 + 8019edc: 100b883a mov r5,r2 + 8019ee0: 01020174 movhi r4,2053 + 8019ee4: 21205904 addi r4,r4,-32412 + 8019ee8: 8002c780 call 8002c78 + tse_dprintf(6, "PHY Rev. Num. : 0x%02x\n", pphy_profiles[i]->revision_number); + 8019eec: e0bfffc7 ldb r2,-1(fp) + 8019ef0: 100690ba slli r3,r2,2 + 8019ef4: 008201b4 movhi r2,2054 + 8019ef8: 1885883a add r2,r3,r2 + 8019efc: 10b5ae17 ldw r2,-10568(r2) + 8019f00: 10801543 ldbu r2,85(r2) + 8019f04: 10803fcc andi r2,r2,255 + 8019f08: 100b883a mov r5,r2 + 8019f0c: 01020174 movhi r4,2053 + 8019f10: 21206004 addi r4,r4,-32384 + 8019f14: 8002c780 call 8002c78 + + tse_dprintf(6, "Status Register : 0x%02x\n", pphy_profiles[i]->status_reg_location); + 8019f18: e0bfffc7 ldb r2,-1(fp) + 8019f1c: 100690ba slli r3,r2,2 + 8019f20: 008201b4 movhi r2,2054 + 8019f24: 1885883a add r2,r3,r2 + 8019f28: 10b5ae17 ldw r2,-10568(r2) + 8019f2c: 10801583 ldbu r2,86(r2) + 8019f30: 10803fcc andi r2,r2,255 + 8019f34: 100b883a mov r5,r2 + 8019f38: 01020174 movhi r4,2053 + 8019f3c: 21206704 addi r4,r4,-32356 + 8019f40: 8002c780 call 8002c78 + + tse_dprintf(6, "Speed Bit : %d\n", pphy_profiles[i]->speed_lsb_location); + 8019f44: e0bfffc7 ldb r2,-1(fp) + 8019f48: 100690ba slli r3,r2,2 + 8019f4c: 008201b4 movhi r2,2054 + 8019f50: 1885883a add r2,r3,r2 + 8019f54: 10b5ae17 ldw r2,-10568(r2) + 8019f58: 108015c3 ldbu r2,87(r2) + 8019f5c: 10803fcc andi r2,r2,255 + 8019f60: 100b883a mov r5,r2 + 8019f64: 01020174 movhi r4,2053 + 8019f68: 21206e04 addi r4,r4,-32328 + 8019f6c: 8002c780 call 8002c78 + + tse_dprintf(6, "Duplex Bit : %d\n", pphy_profiles[i]->duplex_bit_location); + 8019f70: e0bfffc7 ldb r2,-1(fp) + 8019f74: 100690ba slli r3,r2,2 + 8019f78: 008201b4 movhi r2,2054 + 8019f7c: 1885883a add r2,r3,r2 + 8019f80: 10b5ae17 ldw r2,-10568(r2) + 8019f84: 10801603 ldbu r2,88(r2) + 8019f88: 10803fcc andi r2,r2,255 + 8019f8c: 100b883a mov r5,r2 + 8019f90: 01020174 movhi r4,2053 + 8019f94: 21207404 addi r4,r4,-32304 + 8019f98: 8002c780 call 8002c78 + + tse_dprintf(6, "Link Bit : %d\n\n", pphy_profiles[i]->link_bit_location); + 8019f9c: e0bfffc7 ldb r2,-1(fp) + 8019fa0: 100690ba slli r3,r2,2 + 8019fa4: 008201b4 movhi r2,2054 + 8019fa8: 1885883a add r2,r3,r2 + 8019fac: 10b5ae17 ldw r2,-10568(r2) + 8019fb0: 10801643 ldbu r2,89(r2) + 8019fb4: 10803fcc andi r2,r2,255 + 8019fb8: 100b883a mov r5,r2 + 8019fbc: 01020174 movhi r4,2053 + 8019fc0: 21207a04 addi r4,r4,-32280 + 8019fc4: 8002c780 call 8002c78 + for(i = 0; i < phy_profile_count; i++) + 8019fc8: e0bfffc3 ldbu r2,-1(fp) + 8019fcc: 10800044 addi r2,r2,1 + 8019fd0: e0bfffc5 stb r2,-1(fp) + 8019fd4: e0ffffc7 ldb r3,-1(fp) + 8019fd8: d0a05b03 ldbu r2,-32404(gp) + 8019fdc: 10803fcc andi r2,r2,255 + 8019fe0: 18bf9f16 blt r3,r2,8019e60 + + } + + return phy_profile_count; + 8019fe4: d0a05b03 ldbu r2,-32404(gp) + 8019fe8: 10803fcc andi r2,r2,255 +} + 8019fec: e037883a mov sp,fp + 8019ff0: dfc00117 ldw ra,4(sp) + 8019ff4: df000017 ldw fp,0(sp) + 8019ff8: dec00204 addi sp,sp,8 + 8019ffc: f800283a ret + +0801a000 : + * @API Type: Internal + * @param pmac N/A + * @return return SUCCESS + * return ALTERA_TSE_SYSTEM_DEF_ERROR if alt_tse_system_info structure definition error + */ +alt_32 alt_tse_mac_group_init() { + 801a000: defffa04 addi sp,sp,-24 + 801a004: dfc00515 stw ra,20(sp) + 801a008: df000415 stw fp,16(sp) + 801a00c: df000404 addi fp,sp,16 + + alt_8 i; + alt_8 j; + + alt_tse_mac_group *pmac_group = 0; + 801a010: e03ffd15 stw zero,-12(fp) + alt_tse_mac_info *pmac_info = 0; + 801a014: e03fff15 stw zero,-4(fp) + alt_tse_system_info *psys = 0; + 801a018: e03ffc15 stw zero,-16(fp) + + /* reset number of MAC group */ + mac_group_count = 0; + 801a01c: d0205b45 stb zero,-32403(gp) + + /* loop through every alt_tse_system_info structure */ + for(i = 0; i < max_mac_system; i++) { + 801a020: e03ffec5 stb zero,-5(fp) + 801a024: 00019206 br 801a670 + psys = &tse_mac_device[i]; + 801a028: e0bffec7 ldb r2,-5(fp) + 801a02c: 10c01324 muli r3,r2,76 + 801a030: 00820174 movhi r2,2053 + 801a034: 10ae5404 addi r2,r2,-18096 + 801a038: 1885883a add r2,r3,r2 + 801a03c: e0bffc15 stw r2,-16(fp) + + if((psys->tse_msgdma_tx != 0) && (psys->tse_msgdma_rx != 0)) { + 801a040: e0bffc17 ldw r2,-16(fp) + 801a044: 10800617 ldw r2,24(r2) + 801a048: 10018626 beq r2,zero,801a664 + 801a04c: e0bffc17 ldw r2,-16(fp) + 801a050: 10800717 ldw r2,28(r2) + 801a054: 10018326 beq r2,zero,801a664 + tse_dprintf(5, "INFO : TSE MAC %d found at address 0x%08x\n", mac_group_count, (int) psys->tse_mac_base); + 801a058: d0a05b43 ldbu r2,-32403(gp) + 801a05c: 10c03fcc andi r3,r2,255 + 801a060: e0bffc17 ldw r2,-16(fp) + 801a064: 10800017 ldw r2,0(r2) + 801a068: 100d883a mov r6,r2 + 801a06c: 180b883a mov r5,r3 + 801a070: 01020174 movhi r4,2053 + 801a074: 21208004 addi r4,r4,-32256 + 801a078: 8002c780 call 8002c78 + + /* Allocate memory for the structure */ + pmac_group = (alt_tse_mac_group *) malloc(sizeof(alt_tse_mac_group)); + 801a07c: 01000504 movi r4,20 + 801a080: 8042c980 call 8042c98 + 801a084: e0bffd15 stw r2,-12(fp) + if(!pmac_group) { + 801a088: e0bffd17 ldw r2,-12(fp) + 801a08c: 1000081e bne r2,zero,801a0b0 + tse_dprintf(1, "ERROR : Unable to allocate memory for MAC Group[%d]\n", mac_group_count); + 801a090: d0a05b43 ldbu r2,-32403(gp) + 801a094: 10803fcc andi r2,r2,255 + 801a098: 100b883a mov r5,r2 + 801a09c: 01020174 movhi r4,2053 + 801a0a0: 21208c04 addi r4,r4,-32208 + 801a0a4: 8002c780 call 8002c78 + return ALTERA_TSE_MALLOC_FAILED; + 801a0a8: 00bfffc4 movi r2,-1 + 801a0ac: 00017506 br 801a684 + } + + /* Non-multi-channel MAC considered as 1 channel */ + if(psys->tse_multichannel_mac) { + 801a0b0: e0bffc17 ldw r2,-16(fp) + 801a0b4: 108003c3 ldbu r2,15(r2) + 801a0b8: 10803fcc andi r2,r2,255 + 801a0bc: 10001226 beq r2,zero,801a108 + pmac_group->channel = psys->tse_num_of_channel; + 801a0c0: e0bffc17 ldw r2,-16(fp) + 801a0c4: 10c00403 ldbu r3,16(r2) + 801a0c8: e0bffd17 ldw r2,-12(fp) + 801a0cc: 10c00005 stb r3,0(r2) + tse_dprintf(6, "INFO : Multi Channel = Yes\n"); + 801a0d0: 01020174 movhi r4,2053 + 801a0d4: 21209a04 addi r4,r4,-32152 + 801a0d8: 8002d9c0 call 8002d9c + tse_dprintf(6, "INFO : Number of channel = %d\n", pmac_group->channel); + 801a0dc: e0bffd17 ldw r2,-12(fp) + 801a0e0: 10800003 ldbu r2,0(r2) + 801a0e4: 10803fcc andi r2,r2,255 + 801a0e8: 100b883a mov r5,r2 + 801a0ec: 01020174 movhi r4,2053 + 801a0f0: 2120a504 addi r4,r4,-32108 + 801a0f4: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : MDIO Shared = Yes\n"); + 801a0f8: 01020174 movhi r4,2053 + 801a0fc: 2120b004 addi r4,r4,-32064 + 801a100: 8002d9c0 call 8002d9c + 801a104: 00001f06 br 801a184 + } + else if(psys->tse_mdio_shared) { + 801a108: e0bffc17 ldw r2,-16(fp) + 801a10c: 10800443 ldbu r2,17(r2) + 801a110: 10803fcc andi r2,r2,255 + 801a114: 10001226 beq r2,zero,801a160 + pmac_group->channel = psys->tse_number_of_mac_mdio_shared; + 801a118: e0bffc17 ldw r2,-16(fp) + 801a11c: 10c00483 ldbu r3,18(r2) + 801a120: e0bffd17 ldw r2,-12(fp) + 801a124: 10c00005 stb r3,0(r2) + tse_dprintf(6, "INFO : Multi Channel = No\n"); + 801a128: 01020174 movhi r4,2053 + 801a12c: 2120bb04 addi r4,r4,-32020 + 801a130: 8002d9c0 call 8002d9c + tse_dprintf(6, "INFO : MDIO Shared = Yes\n"); + 801a134: 01020174 movhi r4,2053 + 801a138: 2120b004 addi r4,r4,-32064 + 801a13c: 8002d9c0 call 8002d9c + tse_dprintf(6, "INFO : Number of MAC Share MDIO = %d\n", pmac_group->channel); + 801a140: e0bffd17 ldw r2,-12(fp) + 801a144: 10800003 ldbu r2,0(r2) + 801a148: 10803fcc andi r2,r2,255 + 801a14c: 100b883a mov r5,r2 + 801a150: 01020174 movhi r4,2053 + 801a154: 2120c504 addi r4,r4,-31980 + 801a158: 8002c780 call 8002c78 + 801a15c: 00000906 br 801a184 + } + else { + pmac_group->channel = 1; + 801a160: e0bffd17 ldw r2,-12(fp) + 801a164: 00c00044 movi r3,1 + 801a168: 10c00005 stb r3,0(r2) + tse_dprintf(6, "INFO : Multi Channel = No\n"); + 801a16c: 01020174 movhi r4,2053 + 801a170: 2120bb04 addi r4,r4,-32020 + 801a174: 8002d9c0 call 8002d9c + tse_dprintf(6, "INFO : MDIO Shared = No\n"); + 801a178: 01020174 movhi r4,2053 + 801a17c: 2120d004 addi r4,r4,-31936 + 801a180: 8002d9c0 call 8002d9c + } + + for(j = 0; j < pmac_group->channel; j++) { + 801a184: e03ffe85 stb zero,-6(fp) + 801a188: 00012106 br 801a610 + /* Allocate memory for the structure */ + pmac_info = (alt_tse_mac_info *) malloc(sizeof(alt_tse_mac_info)); + 801a18c: 01000404 movi r4,16 + 801a190: 8042c980 call 8042c98 + 801a194: e0bfff15 stw r2,-4(fp) + if(!pmac_info) { + 801a198: e0bfff17 ldw r2,-4(fp) + 801a19c: 10000a1e bne r2,zero,801a1c8 + tse_dprintf(1, "ERROR : Unable to allocate memory for MAC Group[%d]->pmac_info[%d]\n", mac_group_count, j); + 801a1a0: d0a05b43 ldbu r2,-32403(gp) + 801a1a4: 10803fcc andi r2,r2,255 + 801a1a8: e0fffe87 ldb r3,-6(fp) + 801a1ac: 180d883a mov r6,r3 + 801a1b0: 100b883a mov r5,r2 + 801a1b4: 01020174 movhi r4,2053 + 801a1b8: 2120da04 addi r4,r4,-31896 + 801a1bc: 8002c780 call 8002c78 + return ALTERA_TSE_MALLOC_FAILED; + 801a1c0: 00bfffc4 movi r2,-1 + 801a1c4: 00012f06 br 801a684 + } + + pmac_info->pmac_group = pmac_group; + 801a1c8: e0bfff17 ldw r2,-4(fp) + 801a1cc: e0fffd17 ldw r3,-12(fp) + 801a1d0: 10c00315 stw r3,12(r2) + + pmac_info->pphy_info = 0; + 801a1d4: e0bfff17 ldw r2,-4(fp) + 801a1d8: 10000115 stw zero,4(r2) + + pmac_info->psys_info = &tse_mac_device[i + j]; + 801a1dc: e0fffec7 ldb r3,-5(fp) + 801a1e0: e0bffe87 ldb r2,-6(fp) + 801a1e4: 1885883a add r2,r3,r2 + 801a1e8: 10c01324 muli r3,r2,76 + 801a1ec: 00820174 movhi r2,2053 + 801a1f0: 10ae5404 addi r2,r2,-18096 + 801a1f4: 1887883a add r3,r3,r2 + 801a1f8: e0bfff17 ldw r2,-4(fp) + 801a1fc: 10c00215 stw r3,8(r2) + + /* check to make sure the alt_tse_system_info defined correctly or has been defined */ + if((pmac_info->psys_info->tse_msgdma_tx == 0) || (pmac_info->psys_info->tse_msgdma_rx == 0)){ + 801a200: e0bfff17 ldw r2,-4(fp) + 801a204: 10800217 ldw r2,8(r2) + 801a208: 10800617 ldw r2,24(r2) + 801a20c: 10000426 beq r2,zero,801a220 + 801a210: e0bfff17 ldw r2,-4(fp) + 801a214: 10800217 ldw r2,8(r2) + 801a218: 10800717 ldw r2,28(r2) + 801a21c: 1000091e bne r2,zero,801a244 + tse_dprintf(2, "ERROR : tse_mac_device[%d] does not defined correctly!\n", i + j); + 801a220: e0fffec7 ldb r3,-5(fp) + 801a224: e0bffe87 ldb r2,-6(fp) + 801a228: 1885883a add r2,r3,r2 + 801a22c: 100b883a mov r5,r2 + 801a230: 01020174 movhi r4,2053 + 801a234: 2120ec04 addi r4,r4,-31824 + 801a238: 8002c780 call 8002c78 + return ALTERA_TSE_SYSTEM_DEF_ERROR; + 801a23c: 00bfffc4 movi r2,-1 + 801a240: 00011006 br 801a684 + } + + /* MAC type detection */ + if(pmac_info->psys_info->tse_en_maclite) { + 801a244: e0bfff17 ldw r2,-4(fp) + 801a248: 10800217 ldw r2,8(r2) + 801a24c: 10800343 ldbu r2,13(r2) + 801a250: 10803fcc andi r2,r2,255 + 801a254: 10000d26 beq r2,zero,801a28c + if(pmac_info->psys_info->tse_maclite_gige) { + 801a258: e0bfff17 ldw r2,-4(fp) + 801a25c: 10800217 ldw r2,8(r2) + 801a260: 10800383 ldbu r2,14(r2) + 801a264: 10803fcc andi r2,r2,255 + 801a268: 10000426 beq r2,zero,801a27c + pmac_info->mac_type = ALTERA_TSE_MACLITE_1000; + 801a26c: e0bfff17 ldw r2,-4(fp) + 801a270: 00c00084 movi r3,2 + 801a274: 10c00005 stb r3,0(r2) + 801a278: 00000606 br 801a294 + } + else { + pmac_info->mac_type = ALTERA_TSE_MACLITE_10_100; + 801a27c: e0bfff17 ldw r2,-4(fp) + 801a280: 00c00044 movi r3,1 + 801a284: 10c00005 stb r3,0(r2) + 801a288: 00000206 br 801a294 + } + } + else { + pmac_info->mac_type = ALTERA_TSE_FULL_MAC; + 801a28c: e0bfff17 ldw r2,-4(fp) + 801a290: 10000005 stb zero,0(r2) + } + + if((pmac_info->psys_info->tse_mdio_shared) && (!pmac_info->psys_info->tse_multichannel_mac)){ + 801a294: e0bfff17 ldw r2,-4(fp) + 801a298: 10800217 ldw r2,8(r2) + 801a29c: 10800443 ldbu r2,17(r2) + 801a2a0: 10803fcc andi r2,r2,255 + 801a2a4: 10006626 beq r2,zero,801a440 + 801a2a8: e0bfff17 ldw r2,-4(fp) + 801a2ac: 10800217 ldw r2,8(r2) + 801a2b0: 108003c3 ldbu r2,15(r2) + 801a2b4: 10803fcc andi r2,r2,255 + 801a2b8: 1000611e bne r2,zero,801a440 + tse_dprintf(6, "INFO : MAC %2d Address = 0x%08x\n", j, (int) pmac_info->psys_info->tse_mac_base); + 801a2bc: e0fffe87 ldb r3,-6(fp) + 801a2c0: e0bfff17 ldw r2,-4(fp) + 801a2c4: 10800217 ldw r2,8(r2) + 801a2c8: 10800017 ldw r2,0(r2) + 801a2cc: 100d883a mov r6,r2 + 801a2d0: 180b883a mov r5,r3 + 801a2d4: 01020174 movhi r4,2053 + 801a2d8: 2120fb04 addi r4,r4,-31764 + 801a2dc: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : MAC %2d Device = tse_mac_device[%d]\n", j, i + j); + 801a2e0: e13ffe87 ldb r4,-6(fp) + 801a2e4: e0fffec7 ldb r3,-5(fp) + 801a2e8: e0bffe87 ldb r2,-6(fp) + 801a2ec: 1885883a add r2,r3,r2 + 801a2f0: 100d883a mov r6,r2 + 801a2f4: 200b883a mov r5,r4 + 801a2f8: 01020174 movhi r4,2053 + 801a2fc: 21210704 addi r4,r4,-31716 + 801a300: 8002c780 call 8002c78 + + switch(pmac_info->mac_type) { + 801a304: e0bfff17 ldw r2,-4(fp) + 801a308: 10800003 ldbu r2,0(r2) + 801a30c: 10803fcc andi r2,r2,255 + 801a310: 10c00060 cmpeqi r3,r2,1 + 801a314: 18000c1e bne r3,zero,801a348 + 801a318: 10c000a0 cmpeqi r3,r2,2 + 801a31c: 1800021e bne r3,zero,801a328 + 801a320: 10001126 beq r2,zero,801a368 + 801a324: 00001806 br 801a388 + case ALTERA_TSE_MACLITE_1000: + tse_dprintf(6, "INFO : MAC %2d Type = %s\n", j, "1000 Mbps Small MAC"); + 801a328: e0bffe87 ldb r2,-6(fp) + 801a32c: 01820174 movhi r6,2053 + 801a330: 31a11604 addi r6,r6,-31656 + 801a334: 100b883a mov r5,r2 + 801a338: 01020174 movhi r4,2053 + 801a33c: 21211b04 addi r4,r4,-31636 + 801a340: 8002c780 call 8002c78 + break; + 801a344: 00001806 br 801a3a8 + case ALTERA_TSE_MACLITE_10_100: + tse_dprintf(6, "INFO : MAC %2d Type = %s\n", j, "10/100 Mbps Small MAC"); + 801a348: e0bffe87 ldb r2,-6(fp) + 801a34c: 01820174 movhi r6,2053 + 801a350: 31a12604 addi r6,r6,-31592 + 801a354: 100b883a mov r5,r2 + 801a358: 01020174 movhi r4,2053 + 801a35c: 21211b04 addi r4,r4,-31636 + 801a360: 8002c780 call 8002c78 + break; + 801a364: 00001006 br 801a3a8 + case ALTERA_TSE_FULL_MAC: + tse_dprintf(6, "INFO : MAC %2d Type = %s\n", j, "10/100/1000 Ethernet MAC"); + 801a368: e0bffe87 ldb r2,-6(fp) + 801a36c: 01820174 movhi r6,2053 + 801a370: 31a12c04 addi r6,r6,-31568 + 801a374: 100b883a mov r5,r2 + 801a378: 01020174 movhi r4,2053 + 801a37c: 21211b04 addi r4,r4,-31636 + 801a380: 8002c780 call 8002c78 + break; + 801a384: 00000806 br 801a3a8 + default : + tse_dprintf(6, "INFO : MAC %2d Type = %s\n", j, "Unknown"); + 801a388: e0bffe87 ldb r2,-6(fp) + 801a38c: 01820134 movhi r6,2052 + 801a390: 319f4d04 addi r6,r6,32052 + 801a394: 100b883a mov r5,r2 + 801a398: 01020174 movhi r4,2053 + 801a39c: 21211b04 addi r4,r4,-31636 + 801a3a0: 8002c780 call 8002c78 + break; + 801a3a4: 0001883a nop + } + + if(pmac_info->psys_info->tse_pcs_ena) { + 801a3a8: e0bfff17 ldw r2,-4(fp) + 801a3ac: 10800217 ldw r2,8(r2) + 801a3b0: 108004c3 ldbu r2,19(r2) + 801a3b4: 10803fcc andi r2,r2,255 + 801a3b8: 10008b26 beq r2,zero,801a5e8 + tse_dprintf(6, "INFO : PCS %2d Enable = %s\n", j, pmac_info->psys_info->tse_pcs_ena ? "Yes" : "No"); + 801a3bc: e0fffe87 ldb r3,-6(fp) + 801a3c0: e0bfff17 ldw r2,-4(fp) + 801a3c4: 10800217 ldw r2,8(r2) + 801a3c8: 108004c3 ldbu r2,19(r2) + 801a3cc: 10803fcc andi r2,r2,255 + 801a3d0: 10000326 beq r2,zero,801a3e0 + 801a3d4: 00820174 movhi r2,2053 + 801a3d8: 10a13304 addi r2,r2,-31540 + 801a3dc: 00000206 br 801a3e8 + 801a3e0: 00820174 movhi r2,2053 + 801a3e4: 10a13404 addi r2,r2,-31536 + 801a3e8: 100d883a mov r6,r2 + 801a3ec: 180b883a mov r5,r3 + 801a3f0: 01020174 movhi r4,2053 + 801a3f4: 21213504 addi r4,r4,-31532 + 801a3f8: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : PCS %2d SGMII Enable = %s\n", j, pmac_info->psys_info->tse_pcs_sgmii ? "Yes" : "No"); + 801a3fc: e0fffe87 ldb r3,-6(fp) + 801a400: e0bfff17 ldw r2,-4(fp) + 801a404: 10800217 ldw r2,8(r2) + 801a408: 10800503 ldbu r2,20(r2) + 801a40c: 10803fcc andi r2,r2,255 + 801a410: 10000326 beq r2,zero,801a420 + 801a414: 00820174 movhi r2,2053 + 801a418: 10a13304 addi r2,r2,-31540 + 801a41c: 00000206 br 801a428 + 801a420: 00820174 movhi r2,2053 + 801a424: 10a13404 addi r2,r2,-31536 + 801a428: 100d883a mov r6,r2 + 801a42c: 180b883a mov r5,r3 + 801a430: 01020174 movhi r4,2053 + 801a434: 21214004 addi r4,r4,-31488 + 801a438: 8002c780 call 8002c78 + if(pmac_info->psys_info->tse_pcs_ena) { + 801a43c: 00006a06 br 801a5e8 + } + } + else { + /* display only once for all MAC, except shared MDIO MACs */ + if(j == 0) { + 801a440: e0bffe87 ldb r2,-6(fp) + 801a444: 1000421e bne r2,zero,801a550 + switch(pmac_info->mac_type) { + 801a448: e0bfff17 ldw r2,-4(fp) + 801a44c: 10800003 ldbu r2,0(r2) + 801a450: 10803fcc andi r2,r2,255 + 801a454: 10c00060 cmpeqi r3,r2,1 + 801a458: 18000a1e bne r3,zero,801a484 + 801a45c: 10c000a0 cmpeqi r3,r2,2 + 801a460: 1800021e bne r3,zero,801a46c + 801a464: 10000d26 beq r2,zero,801a49c + 801a468: 00001206 br 801a4b4 + case ALTERA_TSE_MACLITE_1000: + tse_dprintf(6, "INFO : MAC Type = %s\n", "1000 Mbps Small MAC"); + 801a46c: 01420174 movhi r5,2053 + 801a470: 29611604 addi r5,r5,-31656 + 801a474: 01020174 movhi r4,2053 + 801a478: 21214b04 addi r4,r4,-31444 + 801a47c: 8002c780 call 8002c78 + break; + 801a480: 00001206 br 801a4cc + case ALTERA_TSE_MACLITE_10_100: + tse_dprintf(6, "INFO : MAC Type = %s\n", "10/100 Mbps Small MAC"); + 801a484: 01420174 movhi r5,2053 + 801a488: 29612604 addi r5,r5,-31592 + 801a48c: 01020174 movhi r4,2053 + 801a490: 21214b04 addi r4,r4,-31444 + 801a494: 8002c780 call 8002c78 + break; + 801a498: 00000c06 br 801a4cc + case ALTERA_TSE_FULL_MAC: + tse_dprintf(6, "INFO : MAC Type = %s\n", "10/100/1000 Ethernet MAC"); + 801a49c: 01420174 movhi r5,2053 + 801a4a0: 29612c04 addi r5,r5,-31568 + 801a4a4: 01020174 movhi r4,2053 + 801a4a8: 21214b04 addi r4,r4,-31444 + 801a4ac: 8002c780 call 8002c78 + break; + 801a4b0: 00000606 br 801a4cc + default : + tse_dprintf(6, "INFO : MAC Type = %s\n", "Unknown"); + 801a4b4: 01420134 movhi r5,2052 + 801a4b8: 295f4d04 addi r5,r5,32052 + 801a4bc: 01020174 movhi r4,2053 + 801a4c0: 21214b04 addi r4,r4,-31444 + 801a4c4: 8002c780 call 8002c78 + break; + 801a4c8: 0001883a nop + } + + if(pmac_info->psys_info->tse_pcs_ena) { + 801a4cc: e0bfff17 ldw r2,-4(fp) + 801a4d0: 10800217 ldw r2,8(r2) + 801a4d4: 108004c3 ldbu r2,19(r2) + 801a4d8: 10803fcc andi r2,r2,255 + 801a4dc: 10001c26 beq r2,zero,801a550 + tse_dprintf(6, "INFO : PCS Enable = %s\n", pmac_info->psys_info->tse_pcs_ena ? "Yes" : "No"); + 801a4e0: e0bfff17 ldw r2,-4(fp) + 801a4e4: 10800217 ldw r2,8(r2) + 801a4e8: 108004c3 ldbu r2,19(r2) + 801a4ec: 10803fcc andi r2,r2,255 + 801a4f0: 10000326 beq r2,zero,801a500 + 801a4f4: 00820174 movhi r2,2053 + 801a4f8: 10a13304 addi r2,r2,-31540 + 801a4fc: 00000206 br 801a508 + 801a500: 00820174 movhi r2,2053 + 801a504: 10a13404 addi r2,r2,-31536 + 801a508: 100b883a mov r5,r2 + 801a50c: 01020174 movhi r4,2053 + 801a510: 21215604 addi r4,r4,-31400 + 801a514: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : PCS SGMII Enable = %s\n", pmac_info->psys_info->tse_pcs_sgmii ? "Yes" : "No"); + 801a518: e0bfff17 ldw r2,-4(fp) + 801a51c: 10800217 ldw r2,8(r2) + 801a520: 10800503 ldbu r2,20(r2) + 801a524: 10803fcc andi r2,r2,255 + 801a528: 10000326 beq r2,zero,801a538 + 801a52c: 00820174 movhi r2,2053 + 801a530: 10a13304 addi r2,r2,-31540 + 801a534: 00000206 br 801a540 + 801a538: 00820174 movhi r2,2053 + 801a53c: 10a13404 addi r2,r2,-31536 + 801a540: 100b883a mov r5,r2 + 801a544: 01020174 movhi r4,2053 + 801a548: 21216104 addi r4,r4,-31356 + 801a54c: 8002c780 call 8002c78 + } + } + + if(pmac_info->psys_info->tse_multichannel_mac) { + 801a550: e0bfff17 ldw r2,-4(fp) + 801a554: 10800217 ldw r2,8(r2) + 801a558: 108003c3 ldbu r2,15(r2) + 801a55c: 10803fcc andi r2,r2,255 + 801a560: 10001326 beq r2,zero,801a5b0 + tse_dprintf(6, "INFO : Channel %2d Address = 0x%08x\n", j, (int) pmac_info->psys_info->tse_mac_base); + 801a564: e0fffe87 ldb r3,-6(fp) + 801a568: e0bfff17 ldw r2,-4(fp) + 801a56c: 10800217 ldw r2,8(r2) + 801a570: 10800017 ldw r2,0(r2) + 801a574: 100d883a mov r6,r2 + 801a578: 180b883a mov r5,r3 + 801a57c: 01020174 movhi r4,2053 + 801a580: 21216c04 addi r4,r4,-31312 + 801a584: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : Channel %2d Device = tse_mac_device[%d]\n", j, i + j); + 801a588: e13ffe87 ldb r4,-6(fp) + 801a58c: e0fffec7 ldb r3,-5(fp) + 801a590: e0bffe87 ldb r2,-6(fp) + 801a594: 1885883a add r2,r3,r2 + 801a598: 100d883a mov r6,r2 + 801a59c: 200b883a mov r5,r4 + 801a5a0: 01020174 movhi r4,2053 + 801a5a4: 21217804 addi r4,r4,-31264 + 801a5a8: 8002c780 call 8002c78 + 801a5ac: 00000e06 br 801a5e8 + } + else { + tse_dprintf(6, "INFO : MAC Address = 0x%08x\n", (int) pmac_info->psys_info->tse_mac_base); + 801a5b0: e0bfff17 ldw r2,-4(fp) + 801a5b4: 10800217 ldw r2,8(r2) + 801a5b8: 10800017 ldw r2,0(r2) + 801a5bc: 100b883a mov r5,r2 + 801a5c0: 01020174 movhi r4,2053 + 801a5c4: 21218704 addi r4,r4,-31204 + 801a5c8: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : MAC Device = tse_mac_device[%d]\n", i + j); + 801a5cc: e0fffec7 ldb r3,-5(fp) + 801a5d0: e0bffe87 ldb r2,-6(fp) + 801a5d4: 1885883a add r2,r3,r2 + 801a5d8: 100b883a mov r5,r2 + 801a5dc: 01020174 movhi r4,2053 + 801a5e0: 21219304 addi r4,r4,-31156 + 801a5e4: 8002c780 call 8002c78 + } + } + + /* store the pointer in MAC group variable for the detected channel */ + pmac_group->pmac_info[j] = pmac_info; + 801a5e8: e0bffe87 ldb r2,-6(fp) + 801a5ec: e0fffd17 ldw r3,-12(fp) + 801a5f0: 10800044 addi r2,r2,1 + 801a5f4: 100490ba slli r2,r2,2 + 801a5f8: 1885883a add r2,r3,r2 + 801a5fc: e0ffff17 ldw r3,-4(fp) + 801a600: 10c00015 stw r3,0(r2) + for(j = 0; j < pmac_group->channel; j++) { + 801a604: e0bffe83 ldbu r2,-6(fp) + 801a608: 10800044 addi r2,r2,1 + 801a60c: e0bffe85 stb r2,-6(fp) + 801a610: e0fffe87 ldb r3,-6(fp) + 801a614: e0bffd17 ldw r2,-12(fp) + 801a618: 10800003 ldbu r2,0(r2) + 801a61c: 10803fcc andi r2,r2,255 + 801a620: 18beda16 blt r3,r2,801a18c + } + + /* store the pointer in global variable */ + pmac_groups[mac_group_count] = pmac_group; + 801a624: d0a05b43 ldbu r2,-32403(gp) + 801a628: 10803fcc andi r2,r2,255 + 801a62c: 100890ba slli r4,r2,2 + 801a630: e0fffd17 ldw r3,-12(fp) + 801a634: 008201b4 movhi r2,2054 + 801a638: 2085883a add r2,r4,r2 + 801a63c: 10f5aa15 stw r3,-10584(r2) + + mac_group_count++; + 801a640: d0a05b43 ldbu r2,-32403(gp) + 801a644: 10800044 addi r2,r2,1 + 801a648: d0a05b45 stb r2,-32403(gp) + + /* skip for subsequent Multi-channel MAC */ + i += (pmac_group->channel - 1); + 801a64c: e0bffd17 ldw r2,-12(fp) + 801a650: 10c00003 ldbu r3,0(r2) + 801a654: e0bffec3 ldbu r2,-5(fp) + 801a658: 1885883a add r2,r3,r2 + 801a65c: 10bfffc4 addi r2,r2,-1 + 801a660: e0bffec5 stb r2,-5(fp) + for(i = 0; i < max_mac_system; i++) { + 801a664: e0bffec3 ldbu r2,-5(fp) + 801a668: 10800044 addi r2,r2,1 + 801a66c: e0bffec5 stb r2,-5(fp) + 801a670: e0fffec7 ldb r3,-5(fp) + 801a674: d0a00a03 ldbu r2,-32728(gp) + 801a678: 10803fcc andi r2,r2,255 + 801a67c: 18be6a16 blt r3,r2,801a028 + + } + } + return SUCCESS; + 801a680: 0005883a mov r2,zero +} + 801a684: e037883a mov sp,fp + 801a688: dfc00117 ldw ra,4(sp) + 801a68c: df000017 ldw fp,0(sp) + 801a690: dec00204 addi sp,sp,8 + 801a694: f800283a ret + +0801a698 : +/* @Function Description: Store information of all the PHYs connected to MAC to phy_list + * @API Type: Internal + * @param pmac_group Pointer to the TSE MAC grouping structure + * @return Number of PHY not in profile, return ALTERA_TSE_MALLOC_FAILED if memory allocation failed + */ +alt_32 alt_tse_mac_get_phy(alt_tse_mac_group *pmac_group) { + 801a698: deffed04 addi sp,sp,-76 + 801a69c: dfc01215 stw ra,72(sp) + 801a6a0: df001115 stw fp,68(sp) + 801a6a4: df001104 addi fp,sp,68 + 801a6a8: e13ff015 stw r4,-64(fp) + + alt_32 phyid; + alt_32 phyid2 = 0; + 801a6ac: e03fff15 stw zero,-4(fp) + alt_u8 revision_number; + + alt_32 i; + + alt_u8 is_phy_in_profile; + alt_32 return_value = 0; + 801a6b0: e03ffd15 stw zero,-12(fp) + + alt_8 phy_info_count = 0; + 801a6b4: e03ffec5 stb zero,-5(fp) + + alt_tse_phy_info *pphy = 0; + 801a6b8: e03ff915 stw zero,-28(fp) + alt_tse_mac_info *pmac_info = 0; + 801a6bc: e03ff815 stw zero,-32(fp) + alt_tse_system_info *psys = 0; + 801a6c0: e03ff715 stw zero,-36(fp) + + np_tse_mac *pmac_group_base = (np_tse_mac *) pmac_group->pmac_info[0]->psys_info->tse_mac_base; + 801a6c4: e0bff017 ldw r2,-64(fp) + 801a6c8: 10800117 ldw r2,4(r2) + 801a6cc: 10800217 ldw r2,8(r2) + 801a6d0: 10800017 ldw r2,0(r2) + 801a6d4: e0bff615 stw r2,-40(fp) + + /* Record previous MDIO address, to be restored at the end of function */ + alt_32 mdioadd_prev = IORD(&pmac_group_base->MDIO_ADDR1, 0); + 801a6d8: e0bff617 ldw r2,-40(fp) + 801a6dc: 10801004 addi r2,r2,64 + 801a6e0: 10800037 ldwio r2,0(r2) + 801a6e4: e0bff515 stw r2,-44(fp) + + /* get index of the pointers in pointer array list */ + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + 801a6e8: e13ff017 ldw r4,-64(fp) + 801a6ec: 8018b340 call 8018b34 + 801a6f0: e0bff4c5 stb r2,-45(fp) + + /* loop all valid PHY address to look for connected PHY */ + for (phyadd = 0x00; phyadd < pmac_group->channel /*0x20*/; phyadd++) //M.D. 2019-08-05: don't look at unused PHYs + 801a6f4: e03ffcc5 stb zero,-13(fp) + 801a6f8: 0000c106 br 801aa00 + { + IOWR(&pmac_group_base->MDIO_ADDR1, 0, phyadd); + 801a6fc: e0bff617 ldw r2,-40(fp) + 801a700: 10801004 addi r2,r2,64 + 801a704: e0fffcc3 ldbu r3,-13(fp) + 801a708: 10c00035 stwio r3,0(r2) + phyid = IORD(&pmac_group_base->mdio1.PHY_ID1,0); // read PHY ID + 801a70c: e0bff617 ldw r2,-40(fp) + 801a710: 1080a204 addi r2,r2,648 + 801a714: 10800037 ldwio r2,0(r2) + 801a718: e0bff315 stw r2,-52(fp) + phyid2 = IORD(&pmac_group_base->mdio1.PHY_ID2,0); // read PHY ID + 801a71c: e0bff617 ldw r2,-40(fp) + 801a720: 1080a304 addi r2,r2,652 + 801a724: 10800037 ldwio r2,0(r2) + 801a728: e0bfff15 stw r2,-4(fp) + + /* PHY found */ + if (phyid != phyid2) + 801a72c: e0fff317 ldw r3,-52(fp) + 801a730: e0bfff17 ldw r2,-4(fp) + 801a734: 1880af26 beq r3,r2,801a9f4 + { + pphy = (alt_tse_phy_info *) malloc(sizeof(alt_tse_phy_info)); + 801a738: 01000704 movi r4,28 + 801a73c: 8042c980 call 8042c98 + 801a740: e0bff915 stw r2,-28(fp) + if(!pphy) { + 801a744: e0bff917 ldw r2,-28(fp) + 801a748: 1000091e bne r2,zero,801a770 + tse_dprintf(1, "ERROR : Unable to allocate memory for phy_info[%d.%d]\n", mac_group_index, phy_info_count); + 801a74c: e0bff4c7 ldb r2,-45(fp) + 801a750: e0fffec7 ldb r3,-5(fp) + 801a754: 180d883a mov r6,r3 + 801a758: 100b883a mov r5,r2 + 801a75c: 01020174 movhi r4,2053 + 801a760: 2121a204 addi r4,r4,-31096 + 801a764: 8002c780 call 8002c78 + return ALTERA_TSE_MALLOC_FAILED; + 801a768: 00bfffc4 movi r2,-1 + 801a76c: 0000c806 br 801aa90 + } + + /* store PHY address */ + pphy->mdio_address = phyadd; + 801a770: e0bff917 ldw r2,-28(fp) + 801a774: e0fffcc3 ldbu r3,-13(fp) + 801a778: 10c00005 stb r3,0(r2) + + /* get oui, model number, and revision number from PHYID and PHYID2 */ + oui = (phyid << 6) | ((phyid2 >> 10) & 0x3f); + 801a77c: e0bff317 ldw r2,-52(fp) + 801a780: 100691ba slli r3,r2,6 + 801a784: e0bfff17 ldw r2,-4(fp) + 801a788: 1005d2ba srai r2,r2,10 + 801a78c: 10800fcc andi r2,r2,63 + 801a790: 1884b03a or r2,r3,r2 + 801a794: e0bff215 stw r2,-56(fp) + model_number = (phyid2 >> 4) & 0x3f; + 801a798: e0bfff17 ldw r2,-4(fp) + 801a79c: 1005d13a srai r2,r2,4 + 801a7a0: 10800fcc andi r2,r2,63 + 801a7a4: e0bff1c5 stb r2,-57(fp) + revision_number = phyid2 & 0x0f; + 801a7a8: e0bfff17 ldw r2,-4(fp) + 801a7ac: 108003cc andi r2,r2,15 + 801a7b0: e0bff185 stb r2,-58(fp) + + /* map the PHY with PHY in profile */ + is_phy_in_profile = 0; + 801a7b4: e03ffac5 stb zero,-21(fp) + for(i = 0; i < phy_profile_count; i++) { + 801a7b8: e03ffb15 stw zero,-20(fp) + 801a7bc: 00002c06 br 801a870 + + /* if PHY match with PHY in profile */ + if((pphy_profiles[i]->oui == oui) && (pphy_profiles[i]->model_number == model_number)) + 801a7c0: e0bffb17 ldw r2,-20(fp) + 801a7c4: 100690ba slli r3,r2,2 + 801a7c8: 008201b4 movhi r2,2054 + 801a7cc: 1885883a add r2,r3,r2 + 801a7d0: 10b5ae17 ldw r2,-10568(r2) + 801a7d4: 10801417 ldw r2,80(r2) + 801a7d8: e0fff217 ldw r3,-56(fp) + 801a7dc: 1880211e bne r3,r2,801a864 + 801a7e0: e0bffb17 ldw r2,-20(fp) + 801a7e4: 100690ba slli r3,r2,2 + 801a7e8: 008201b4 movhi r2,2054 + 801a7ec: 1885883a add r2,r3,r2 + 801a7f0: 10b5ae17 ldw r2,-10568(r2) + 801a7f4: 10801503 ldbu r2,84(r2) + 801a7f8: e0fff1c3 ldbu r3,-57(fp) + 801a7fc: 10803fcc andi r2,r2,255 + 801a800: 1880181e bne r3,r2,801a864 + { + pphy->pphy_profile = pphy_profiles[i]; + 801a804: e0bffb17 ldw r2,-20(fp) + 801a808: 100690ba slli r3,r2,2 + 801a80c: 008201b4 movhi r2,2054 + 801a810: 1885883a add r2,r3,r2 + 801a814: 10f5ae17 ldw r3,-10568(r2) + 801a818: e0bff917 ldw r2,-28(fp) + 801a81c: 10c00515 stw r3,20(r2) + + /* PHY found, add it to phy_list */ + tse_dprintf(5, "INFO : PHY %s found at PHY address 0x%02x of MAC Group[%d]\n", pphy_profiles[i]->name, phyadd, mac_group_index); + 801a820: e0bffb17 ldw r2,-20(fp) + 801a824: 100690ba slli r3,r2,2 + 801a828: 008201b4 movhi r2,2054 + 801a82c: 1885883a add r2,r3,r2 + 801a830: 10b5ae17 ldw r2,-10568(r2) + 801a834: 1009883a mov r4,r2 + 801a838: e0bffcc3 ldbu r2,-13(fp) + 801a83c: e0fff4c7 ldb r3,-45(fp) + 801a840: 180f883a mov r7,r3 + 801a844: 100d883a mov r6,r2 + 801a848: 200b883a mov r5,r4 + 801a84c: 01020174 movhi r4,2053 + 801a850: 2121b104 addi r4,r4,-31036 + 801a854: 8002c780 call 8002c78 + is_phy_in_profile = 1; + 801a858: 00800044 movi r2,1 + 801a85c: e0bffac5 stb r2,-21(fp) + break; + 801a860: 00000706 br 801a880 + for(i = 0; i < phy_profile_count; i++) { + 801a864: e0bffb17 ldw r2,-20(fp) + 801a868: 10800044 addi r2,r2,1 + 801a86c: e0bffb15 stw r2,-20(fp) + 801a870: d0a05b03 ldbu r2,-32404(gp) + 801a874: 10803fcc andi r2,r2,255 + 801a878: e0fffb17 ldw r3,-20(fp) + 801a87c: 18bfd016 blt r3,r2,801a7c0 + } + } + /* PHY not found in PHY profile */ + if(is_phy_in_profile == 0) { + 801a880: e0bffac3 ldbu r2,-21(fp) + 801a884: 10000f1e bne r2,zero,801a8c4 + pphy->pphy_profile = 0; + 801a888: e0bff917 ldw r2,-28(fp) + 801a88c: 10000515 stw zero,20(r2) + tse_dprintf(3, "WARNING : Unknown PHY found at PHY address 0x%02x of MAC Group[%d]\n", phyadd, mac_group_index); + 801a890: e0bffcc3 ldbu r2,-13(fp) + 801a894: e0fff4c7 ldb r3,-45(fp) + 801a898: 180d883a mov r6,r3 + 801a89c: 100b883a mov r5,r2 + 801a8a0: 01020174 movhi r4,2053 + 801a8a4: 2121c104 addi r4,r4,-30972 + 801a8a8: 8002c780 call 8002c78 + tse_dprintf(3, "WARNING : Please add PHY information to PHY profile\n"); + 801a8ac: 01020174 movhi r4,2053 + 801a8b0: 2121d204 addi r4,r4,-30904 + 801a8b4: 8002d9c0 call 8002d9c + return_value++; + 801a8b8: e0bffd17 ldw r2,-12(fp) + 801a8bc: 10800044 addi r2,r2,1 + 801a8c0: e0bffd15 stw r2,-12(fp) + } + + tse_dprintf(6, "INFO : PHY OUI = 0x%06x\n", (int) oui); + 801a8c4: e0bff217 ldw r2,-56(fp) + 801a8c8: 100b883a mov r5,r2 + 801a8cc: 01020174 movhi r4,2053 + 801a8d0: 2121df04 addi r4,r4,-30852 + 801a8d4: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : PHY Model Number = 0x%02x\n", model_number); + 801a8d8: e0bff1c3 ldbu r2,-57(fp) + 801a8dc: 100b883a mov r5,r2 + 801a8e0: 01020174 movhi r4,2053 + 801a8e4: 2121ea04 addi r4,r4,-30808 + 801a8e8: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : PHY Revision Number = 0x%01x\n", revision_number); + 801a8ec: e0bff183 ldbu r2,-58(fp) + 801a8f0: 100b883a mov r5,r2 + 801a8f4: 01020174 movhi r4,2053 + 801a8f8: 2121f504 addi r4,r4,-30764 + 801a8fc: 8002c780 call 8002c78 + + /* map the detected PHY to connected MAC */ + if(alt_tse_mac_associate_phy(pmac_group, pphy) == TSE_PHY_MAP_SUCCESS) { + 801a900: e17ff917 ldw r5,-28(fp) + 801a904: e13ff017 ldw r4,-64(fp) + 801a908: 801aaa40 call 801aaa4 + 801a90c: 1000341e bne r2,zero,801a9e0 + + pmac_info = pphy->pmac_info; + 801a910: e0bff917 ldw r2,-28(fp) + 801a914: 10800617 ldw r2,24(r2) + 801a918: e0bff815 stw r2,-32(fp) + psys = pmac_info->psys_info; + 801a91c: e0bff817 ldw r2,-32(fp) + 801a920: 10800217 ldw r2,8(r2) + 801a924: e0bff715 stw r2,-36(fp) + + /* Disable PHY loopback to allow Auto-Negotiation completed */ + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_LOOPBACK, 1, 0); // disable PHY loopback + 801a928: d8000015 stw zero,0(sp) + 801a92c: 01c00044 movi r7,1 + 801a930: 01800384 movi r6,14 + 801a934: 000b883a mov r5,zero + 801a938: e13ff917 ldw r4,-28(fp) + 801a93c: 801996c0 call 801996c + + /* Reset auto-negotiation advertisement */ + alt_tse_phy_set_adv_1000(pphy, 1); + 801a940: 01400044 movi r5,1 + 801a944: e13ff917 ldw r4,-28(fp) + 801a948: 801b7f00 call 801b7f0 + alt_tse_phy_set_adv_100(pphy, 1); + 801a94c: 01400044 movi r5,1 + 801a950: e13ff917 ldw r4,-28(fp) + 801a954: 801b9b40 call 801b9b4 + alt_tse_phy_set_adv_10(pphy, 1); + 801a958: 01400044 movi r5,1 + 801a95c: e13ff917 ldw r4,-28(fp) + 801a960: 801bc080 call 801bc08 + + /* check link connection for this PHY */ + alt_tse_phy_restart_an(pphy, ALTERA_CHECKLINK_TIMEOUT_THRESHOLD); + 801a964: 0149c404 movi r5,10000 + 801a968: e13ff917 ldw r4,-28(fp) + 801a96c: 801af180 call 801af18 + + /* Perform additional setting if there is any */ + /* Profile specific */ + if(pphy->pphy_profile) { + 801a970: e0bff917 ldw r2,-28(fp) + 801a974: 10800517 ldw r2,20(r2) + 801a978: 10000f26 beq r2,zero,801a9b8 + if(pphy->pphy_profile->phy_cfg) { + 801a97c: e0bff917 ldw r2,-28(fp) + 801a980: 10800517 ldw r2,20(r2) + 801a984: 10801717 ldw r2,92(r2) + 801a988: 10000b26 beq r2,zero,801a9b8 + tse_dprintf(6, "INFO : Applying additional PHY configuration of %s\n", pphy->pphy_profile->name); + 801a98c: e0bff917 ldw r2,-28(fp) + 801a990: 10800517 ldw r2,20(r2) + 801a994: 100b883a mov r5,r2 + 801a998: 01020174 movhi r4,2053 + 801a99c: 21220004 addi r4,r4,-30720 + 801a9a0: 8002c780 call 8002c78 + pphy->pphy_profile->phy_cfg(pmac_group_base); + 801a9a4: e0bff917 ldw r2,-28(fp) + 801a9a8: 10800517 ldw r2,20(r2) + 801a9ac: 10801717 ldw r2,92(r2) + 801a9b0: e13ff617 ldw r4,-40(fp) + 801a9b4: 103ee83a callr r2 + } + } + + /* Initialize PHY, call user's function pointer in alt_tse_system_info structure */ + /* Individual PHY specific */ + if(psys->tse_phy_cfg) { + 801a9b8: e0bff717 ldw r2,-36(fp) + 801a9bc: 10801217 ldw r2,72(r2) + 801a9c0: 10000726 beq r2,zero,801a9e0 + tse_dprintf(6, "INFO : Applying additional user PHY configuration\n"); + 801a9c4: 01020174 movhi r4,2053 + 801a9c8: 21220e04 addi r4,r4,-30664 + 801a9cc: 8002d9c0 call 8002d9c + psys->tse_phy_cfg(pmac_group_base); + 801a9d0: e0bff717 ldw r2,-36(fp) + 801a9d4: 10801217 ldw r2,72(r2) + 801a9d8: e13ff617 ldw r4,-40(fp) + 801a9dc: 103ee83a callr r2 + } + } + + tse_dprintf(6, "\n"); + 801a9e0: 01000284 movi r4,10 + 801a9e4: 8002cb80 call 8002cb8 + + phy_info_count++; + 801a9e8: e0bffec3 ldbu r2,-5(fp) + 801a9ec: 10800044 addi r2,r2,1 + 801a9f0: e0bffec5 stb r2,-5(fp) + for (phyadd = 0x00; phyadd < pmac_group->channel /*0x20*/; phyadd++) //M.D. 2019-08-05: don't look at unused PHYs + 801a9f4: e0bffcc3 ldbu r2,-13(fp) + 801a9f8: 10800044 addi r2,r2,1 + 801a9fc: e0bffcc5 stb r2,-13(fp) + 801aa00: e0bff017 ldw r2,-64(fp) + 801aa04: 10800003 ldbu r2,0(r2) + 801aa08: e0fffcc3 ldbu r3,-13(fp) + 801aa0c: 10803fcc andi r2,r2,255 + 801aa10: 18bf3a36 bltu r3,r2,801a6fc + } + } + + TK_SLEEP(100); //Wait a little bit for PHY reset after specific configuration + 801aa14: 01001944 movi r4,101 + 801aa18: 801730c0 call 801730c + + + /* check to verify the number of connected PHY match the number of channel */ + if(pmac_group->channel != phy_info_count) { + 801aa1c: e0bff017 ldw r2,-64(fp) + 801aa20: 10800003 ldbu r2,0(r2) + 801aa24: 10c03fcc andi r3,r2,255 + 801aa28: e0bffec7 ldb r2,-5(fp) + 801aa2c: 18801326 beq r3,r2,801aa7c + if(phy_info_count == 0) { + 801aa30: e0bffec7 ldb r2,-5(fp) + 801aa34: 1000061e bne r2,zero,801aa50 + tse_dprintf(2, "ERROR : MAC Group[%d] - No PHY connected!\n", mac_group_index); + 801aa38: e0bff4c7 ldb r2,-45(fp) + 801aa3c: 100b883a mov r5,r2 + 801aa40: 01020174 movhi r4,2053 + 801aa44: 21221c04 addi r4,r4,-30608 + 801aa48: 8002c780 call 8002c78 + 801aa4c: 00000b06 br 801aa7c + } + else { + tse_dprintf(3, "WARNING : MAC Group[%d] - Number of PHY connected is not equal to the number of channel, Number of PHY : %d, Channel : %d\n", mac_group_index, phy_info_count, pmac_group->channel); + 801aa50: e0fff4c7 ldb r3,-45(fp) + 801aa54: e13ffec7 ldb r4,-5(fp) + 801aa58: e0bff017 ldw r2,-64(fp) + 801aa5c: 10800003 ldbu r2,0(r2) + 801aa60: 10803fcc andi r2,r2,255 + 801aa64: 100f883a mov r7,r2 + 801aa68: 200d883a mov r6,r4 + 801aa6c: 180b883a mov r5,r3 + 801aa70: 01020174 movhi r4,2053 + 801aa74: 21222804 addi r4,r4,-30560 + 801aa78: 8002c780 call 8002c78 + } + } + + /* Restore previous MDIO address */ + IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdioadd_prev); + 801aa7c: e0bff617 ldw r2,-40(fp) + 801aa80: 10801004 addi r2,r2,64 + 801aa84: e0fff517 ldw r3,-44(fp) + 801aa88: 10c00035 stwio r3,0(r2) + + return return_value; + 801aa8c: e0bffd17 ldw r2,-12(fp) +} + 801aa90: e037883a mov sp,fp + 801aa94: dfc00117 ldw ra,4(sp) + 801aa98: df000017 ldw fp,0(sp) + 801aa9c: dec00204 addi sp,sp,8 + 801aaa0: f800283a ret + +0801aaa4 : + * @param pmac_group Pointer to the TSE MAC grouping structure + * @param pphy Pointer to the TSE PHY info structure which hold information of PHY + * @return return TSE_PHY_MAP_ERROR if mapping error + * return TSE_PHY_MAP_SUCCESS otherwise + */ +alt_32 alt_tse_mac_associate_phy(alt_tse_mac_group *pmac_group, alt_tse_phy_info *pphy) { + 801aaa4: defff604 addi sp,sp,-40 + 801aaa8: dfc00915 stw ra,36(sp) + 801aaac: df000815 stw fp,32(sp) + 801aab0: df000804 addi fp,sp,32 + 801aab4: e13ff915 stw r4,-28(fp) + 801aab8: e17ff815 stw r5,-32(fp) + + alt_32 i; + alt_32 return_value = TSE_PHY_MAP_SUCCESS; + 801aabc: e03ffd15 stw zero,-12(fp) + + alt_u8 is_mapped; + + alt_tse_system_info *psys = 0; + 801aac0: e03ffc15 stw zero,-16(fp) + alt_tse_mac_info *pmac_info = 0; + 801aac4: e03ffb15 stw zero,-20(fp) + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = 0; + 801aac8: e03ffac5 stb zero,-21(fp) + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + 801aacc: e13ff917 ldw r4,-28(fp) + 801aad0: 8018b340 call 8018b34 + 801aad4: e0bffa85 stb r2,-22(fp) + alt_8 sys_info_index = 0; + 801aad8: e03ffa45 stb zero,-23(fp) + + is_mapped = 0; + 801aadc: e03fffc5 stb zero,-1(fp) + + for(i = 0; i < pmac_group->channel; i++) { + 801aae0: e03ffe15 stw zero,-8(fp) + 801aae4: 00002b06 br 801ab94 + pmac_info = pmac_group->pmac_info[i]; + 801aae8: e0fff917 ldw r3,-28(fp) + 801aaec: e0bffe17 ldw r2,-8(fp) + 801aaf0: 10800044 addi r2,r2,1 + 801aaf4: 100490ba slli r2,r2,2 + 801aaf8: 1885883a add r2,r3,r2 + 801aafc: 10800017 ldw r2,0(r2) + 801ab00: e0bffb15 stw r2,-20(fp) + psys = pmac_info->psys_info; + 801ab04: e0bffb17 ldw r2,-20(fp) + 801ab08: 10800217 ldw r2,8(r2) + 801ab0c: e0bffc15 stw r2,-16(fp) + + /* map according to the PHY address in alt_tse_system_info.h */ + if(psys->tse_phy_mdio_address == pphy->mdio_address) { + 801ab10: e0bffc17 ldw r2,-16(fp) + 801ab14: 10c01117 ldw r3,68(r2) + 801ab18: e0bff817 ldw r2,-32(fp) + 801ab1c: 10800003 ldbu r2,0(r2) + 801ab20: 10803fcc andi r2,r2,255 + 801ab24: 1880181e bne r3,r2,801ab88 + mac_info_index = alt_tse_get_mac_info_index(pmac_info); + 801ab28: e13ffb17 ldw r4,-20(fp) + 801ab2c: 8018ba00 call 8018ba0 + 801ab30: e0bffac5 stb r2,-21(fp) + sys_info_index = alt_tse_get_system_index(psys); + 801ab34: e13ffc17 ldw r4,-16(fp) + 801ab38: 8018ac80 call 8018ac8 + 801ab3c: e0bffa45 stb r2,-23(fp) + + pmac_info->pphy_info = pphy; + 801ab40: e0bffb17 ldw r2,-20(fp) + 801ab44: e0fff817 ldw r3,-32(fp) + 801ab48: 10c00115 stw r3,4(r2) + pphy->pmac_info = pmac_info; + 801ab4c: e0bff817 ldw r2,-32(fp) + 801ab50: e0fffb17 ldw r3,-20(fp) + 801ab54: 10c00615 stw r3,24(r2) + tse_dprintf(5, "INFO : PHY[%d.%d] - Explicitly mapped to tse_mac_device[%d]\n", mac_group_index, mac_info_index, sys_info_index); + 801ab58: e0bffa87 ldb r2,-22(fp) + 801ab5c: e0fffac7 ldb r3,-21(fp) + 801ab60: e13ffa47 ldb r4,-23(fp) + 801ab64: 200f883a mov r7,r4 + 801ab68: 180d883a mov r6,r3 + 801ab6c: 100b883a mov r5,r2 + 801ab70: 01020174 movhi r4,2053 + 801ab74: 21224704 addi r4,r4,-30436 + 801ab78: 8002c780 call 8002c78 + is_mapped = 1; + 801ab7c: 00800044 movi r2,1 + 801ab80: e0bfffc5 stb r2,-1(fp) + break; + 801ab84: 00000806 br 801aba8 + for(i = 0; i < pmac_group->channel; i++) { + 801ab88: e0bffe17 ldw r2,-8(fp) + 801ab8c: 10800044 addi r2,r2,1 + 801ab90: e0bffe15 stw r2,-8(fp) + 801ab94: e0bff917 ldw r2,-28(fp) + 801ab98: 10800003 ldbu r2,0(r2) + 801ab9c: 10803fcc andi r2,r2,255 + 801aba0: e0fffe17 ldw r3,-8(fp) + 801aba4: 18bfd016 blt r3,r2,801aae8 + } + } + + /* if not yet map, it will automatically mapped to the first TSE device encountered with tse_phy_mdio_address = TSE_PHY_AUTO_ADDRESS */ + if(is_mapped == 0) { + 801aba8: e0bfffc3 ldbu r2,-1(fp) + 801abac: 10003c1e bne r2,zero,801aca0 + for(i = 0; i < pmac_group->channel; i++) { + 801abb0: e03ffe15 stw zero,-8(fp) + 801abb4: 00003506 br 801ac8c + pmac_info = pmac_group->pmac_info[i]; + 801abb8: e0fff917 ldw r3,-28(fp) + 801abbc: e0bffe17 ldw r2,-8(fp) + 801abc0: 10800044 addi r2,r2,1 + 801abc4: 100490ba slli r2,r2,2 + 801abc8: 1885883a add r2,r3,r2 + 801abcc: 10800017 ldw r2,0(r2) + 801abd0: e0bffb15 stw r2,-20(fp) + psys = pmac_info->psys_info; + 801abd4: e0bffb17 ldw r2,-20(fp) + 801abd8: 10800217 ldw r2,8(r2) + 801abdc: e0bffc15 stw r2,-16(fp) + + /* alt_tse_system_info structure definition error */ + if((psys->tse_msgdma_tx == 0) || (psys->tse_msgdma_rx == 0)){ + 801abe0: e0bffc17 ldw r2,-16(fp) + 801abe4: 10800617 ldw r2,24(r2) + 801abe8: 10002426 beq r2,zero,801ac7c + 801abec: e0bffc17 ldw r2,-16(fp) + 801abf0: 10800717 ldw r2,28(r2) + 801abf4: 10002126 beq r2,zero,801ac7c + continue; + } + + if(psys->tse_phy_mdio_address == TSE_PHY_AUTO_ADDRESS) { + 801abf8: e0bffc17 ldw r2,-16(fp) + 801abfc: 10801117 ldw r2,68(r2) + 801ac00: 10bfffd8 cmpnei r2,r2,-1 + 801ac04: 10001e1e bne r2,zero,801ac80 + mac_info_index = alt_tse_get_mac_info_index(pmac_info); + 801ac08: e13ffb17 ldw r4,-20(fp) + 801ac0c: 8018ba00 call 8018ba0 + 801ac10: e0bffac5 stb r2,-21(fp) + sys_info_index = alt_tse_get_system_index(psys); + 801ac14: e13ffc17 ldw r4,-16(fp) + 801ac18: 8018ac80 call 8018ac8 + 801ac1c: e0bffa45 stb r2,-23(fp) + + pmac_info->pphy_info = pphy; + 801ac20: e0bffb17 ldw r2,-20(fp) + 801ac24: e0fff817 ldw r3,-32(fp) + 801ac28: 10c00115 stw r3,4(r2) + pphy->pmac_info = pmac_info; + 801ac2c: e0bff817 ldw r2,-32(fp) + 801ac30: e0fffb17 ldw r3,-20(fp) + 801ac34: 10c00615 stw r3,24(r2) + psys->tse_phy_mdio_address = pphy->mdio_address; + 801ac38: e0bff817 ldw r2,-32(fp) + 801ac3c: 10800003 ldbu r2,0(r2) + 801ac40: 10c03fcc andi r3,r2,255 + 801ac44: e0bffc17 ldw r2,-16(fp) + 801ac48: 10c01115 stw r3,68(r2) + tse_dprintf(5, "INFO : PHY[%d.%d] - Automatically mapped to tse_mac_device[%d]\n", mac_group_index, mac_info_index, sys_info_index); + 801ac4c: e0bffa87 ldb r2,-22(fp) + 801ac50: e0fffac7 ldb r3,-21(fp) + 801ac54: e13ffa47 ldb r4,-23(fp) + 801ac58: 200f883a mov r7,r4 + 801ac5c: 180d883a mov r6,r3 + 801ac60: 100b883a mov r5,r2 + 801ac64: 01020174 movhi r4,2053 + 801ac68: 21225704 addi r4,r4,-30372 + 801ac6c: 8002c780 call 8002c78 + is_mapped = 1; + 801ac70: 00800044 movi r2,1 + 801ac74: e0bfffc5 stb r2,-1(fp) + break; + 801ac78: 00000906 br 801aca0 + continue; + 801ac7c: 0001883a nop + for(i = 0; i < pmac_group->channel; i++) { + 801ac80: e0bffe17 ldw r2,-8(fp) + 801ac84: 10800044 addi r2,r2,1 + 801ac88: e0bffe15 stw r2,-8(fp) + 801ac8c: e0bff917 ldw r2,-28(fp) + 801ac90: 10800003 ldbu r2,0(r2) + 801ac94: 10803fcc andi r2,r2,255 + 801ac98: e0fffe17 ldw r3,-8(fp) + 801ac9c: 18bfc616 blt r3,r2,801abb8 + } + } + } + + /* Still cannot find any matched MAC-PHY */ + if(is_mapped == 0) { + 801aca0: e0bfffc3 ldbu r2,-1(fp) + 801aca4: 1000091e bne r2,zero,801accc + pphy->pmac_info = 0; + 801aca8: e0bff817 ldw r2,-32(fp) + 801acac: 10000615 stw zero,24(r2) + tse_dprintf(2, "WARNING : PHY[%d.X] - Mapping of PHY to MAC failed! Make sure the PHY address is defined correctly in tse_mac_device[] structure, and number of PHYs connected is equivalent to number of channel\n", mac_group_index); + 801acb0: e0bffa87 ldb r2,-22(fp) + 801acb4: 100b883a mov r5,r2 + 801acb8: 01020174 movhi r4,2053 + 801acbc: 21226804 addi r4,r4,-30304 + 801acc0: 8002c780 call 8002c78 + return_value = TSE_PHY_MAP_ERROR; + 801acc4: 00bfffc4 movi r2,-1 + 801acc8: e0bffd15 stw r2,-12(fp) + } + + return return_value; + 801accc: e0bffd17 ldw r2,-12(fp) +} + 801acd0: e037883a mov sp,fp + 801acd4: dfc00117 ldw ra,4(sp) + 801acd8: df000017 ldw fp,0(sp) + 801acdc: dec00204 addi sp,sp,8 + 801ace0: f800283a ret + +0801ace4 : +/* @Function Description: Configure operating mode of Altera PCS if available + * @API Type: Internal + * @param pmac_info pointer to MAC info variable + * @return return SUCCESS + */ +alt_32 alt_tse_phy_cfg_pcs(alt_tse_mac_info *pmac_info) { + 801ace4: defff804 addi sp,sp,-32 + 801ace8: dfc00715 stw ra,28(sp) + 801acec: df000615 stw fp,24(sp) + 801acf0: df000604 addi fp,sp,24 + 801acf4: e13ffa15 stw r4,-24(fp) + + alt_tse_system_info *psys = pmac_info->psys_info; + 801acf8: e0bffa17 ldw r2,-24(fp) + 801acfc: 10800217 ldw r2,8(r2) + 801ad00: e0bffd15 stw r2,-12(fp) + np_tse_mac *pmac = (np_tse_mac *) psys->tse_mac_base; + 801ad04: e0bffd17 ldw r2,-12(fp) + 801ad08: 10800017 ldw r2,0(r2) + 801ad0c: e0bfff15 stw r2,-4(fp) + alt_tse_mac_group *pmac_group = pmac_info->pmac_group; + 801ad10: e0bffa17 ldw r2,-24(fp) + 801ad14: 10800317 ldw r2,12(r2) + 801ad18: e0bffe15 stw r2,-8(fp) + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info); + 801ad1c: e13ffa17 ldw r4,-24(fp) + 801ad20: 8018ba00 call 8018ba0 + 801ad24: e0bffcc5 stb r2,-13(fp) + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + 801ad28: e13ffe17 ldw r4,-8(fp) + 801ad2c: 8018b340 call 8018b34 + 801ad30: e0bffc85 stb r2,-14(fp) + + if(psys->tse_pcs_ena) { + 801ad34: e0bffd17 ldw r2,-12(fp) + 801ad38: 108004c3 ldbu r2,19(r2) + 801ad3c: 10803fcc andi r2,r2,255 + 801ad40: 10002c26 beq r2,zero,801adf4 + tse_dprintf(5, "INFO : PCS[%d.%d] - Configuring PCS operating mode\n", mac_group_index, mac_info_index); + 801ad44: e0bffc87 ldb r2,-14(fp) + 801ad48: e0fffcc7 ldb r3,-13(fp) + 801ad4c: 180d883a mov r6,r3 + 801ad50: 100b883a mov r5,r2 + 801ad54: 01020174 movhi r4,2053 + 801ad58: 21229904 addi r4,r4,-30108 + 801ad5c: 8002c780 call 8002c78 + + alt_32 data = IORD(&pmac->mdio0.CONTROL, ALTERA_TSE_PCS_IF_MODE); + 801ad60: e0bfff17 ldw r2,-4(fp) + 801ad64: 10808004 addi r2,r2,512 + 801ad68: 10801404 addi r2,r2,80 + 801ad6c: 10800037 ldwio r2,0(r2) + 801ad70: e0bffb15 stw r2,-20(fp) + + if(psys->tse_pcs_sgmii) { + 801ad74: e0bffd17 ldw r2,-12(fp) + 801ad78: 10800503 ldbu r2,20(r2) + 801ad7c: 10803fcc andi r2,r2,255 + 801ad80: 10000e26 beq r2,zero,801adbc + tse_dprintf(5, "INFO : PCS[%d.%d] - PCS SGMII mode enabled\n", mac_group_index, mac_info_index); + 801ad84: e0bffc87 ldb r2,-14(fp) + 801ad88: e0fffcc7 ldb r3,-13(fp) + 801ad8c: 180d883a mov r6,r3 + 801ad90: 100b883a mov r5,r2 + 801ad94: 01020174 movhi r4,2053 + 801ad98: 2122a704 addi r4,r4,-30052 + 801ad9c: 8002c780 call 8002c78 + IOWR(&pmac->mdio0.CONTROL, ALTERA_TSE_PCS_IF_MODE, data | 0x03); + 801ada0: e0bfff17 ldw r2,-4(fp) + 801ada4: 10808004 addi r2,r2,512 + 801ada8: 10801404 addi r2,r2,80 + 801adac: e0fffb17 ldw r3,-20(fp) + 801adb0: 18c000d4 ori r3,r3,3 + 801adb4: 10c00035 stwio r3,0(r2) + 801adb8: 00000e06 br 801adf4 + } + else { + tse_dprintf(5, "INFO : PCS[%d.%d] - PCS SGMII mode disabled\n", mac_group_index, mac_info_index); + 801adbc: e0bffc87 ldb r2,-14(fp) + 801adc0: e0fffcc7 ldb r3,-13(fp) + 801adc4: 180d883a mov r6,r3 + 801adc8: 100b883a mov r5,r2 + 801adcc: 01020174 movhi r4,2053 + 801add0: 2122b304 addi r4,r4,-30004 + 801add4: 8002c780 call 8002c78 + IOWR(&pmac->mdio0.CONTROL, ALTERA_TSE_PCS_IF_MODE, data & ~0x03); + 801add8: e0bfff17 ldw r2,-4(fp) + 801addc: 10808004 addi r2,r2,512 + 801ade0: 10801404 addi r2,r2,80 + 801ade4: e13ffb17 ldw r4,-20(fp) + 801ade8: 00ffff04 movi r3,-4 + 801adec: 20c6703a and r3,r4,r3 + 801adf0: 10c00035 stwio r3,0(r2) + } + } + + return SUCCESS; + 801adf4: 0005883a mov r2,zero +} + 801adf8: e037883a mov sp,fp + 801adfc: dfc00117 ldw ra,4(sp) + 801ae00: df000017 ldw fp,0(sp) + 801ae04: dec00204 addi sp,sp,8 + 801ae08: f800283a ret + +0801ae0c : +/* @Function Description: Detect and initialize all the PHYs connected + * @API Type: Internal + * @param pmac N/A + * @return SUCCESS + */ +alt_32 alt_tse_phy_init() { + 801ae0c: defffb04 addi sp,sp,-20 + 801ae10: dfc00415 stw ra,16(sp) + 801ae14: df000315 stw fp,12(sp) + 801ae18: df000304 addi fp,sp,12 + alt_8 i = 0; + 801ae1c: e03fffc5 stb zero,-1(fp) + alt_8 j = 0; + 801ae20: e03fff85 stb zero,-2(fp) + + alt_tse_mac_group *pmac_group = 0; + 801ae24: e03ffe15 stw zero,-8(fp) + alt_tse_mac_info *pmac_info = 0; + 801ae28: e03ffd15 stw zero,-12(fp) + + /* add supported PHYs */ + alt_tse_phy_add_profile_default(); + 801ae2c: 8019b680 call 8019b68 + + /* display PHY in profile */ + alt_tse_phy_print_profile(); + 801ae30: 8019e300 call 8019e30 + + alt_tse_mac_group_init(); + 801ae34: 801a0000 call 801a000 + + /* initialize for each TSE MAC */ + /* run once only for multi-channel MAC */ + for(i = 0; i < mac_group_count; i++) { + 801ae38: e03fffc5 stb zero,-1(fp) + 801ae3c: 00002c06 br 801aef0 + pmac_group = pmac_groups[i]; + 801ae40: e0bfffc7 ldb r2,-1(fp) + 801ae44: 100690ba slli r3,r2,2 + 801ae48: 008201b4 movhi r2,2054 + 801ae4c: 1885883a add r2,r3,r2 + 801ae50: 10b5aa17 ldw r2,-10584(r2) + 801ae54: e0bffe15 stw r2,-8(fp) + + if(pmac_group->pmac_info[0]->psys_info->tse_use_mdio) { + 801ae58: e0bffe17 ldw r2,-8(fp) + 801ae5c: 10800117 ldw r2,4(r2) + 801ae60: 10800217 ldw r2,8(r2) + 801ae64: 10800303 ldbu r2,12(r2) + 801ae68: 10803fcc andi r2,r2,255 + 801ae6c: 10000326 beq r2,zero,801ae7c + + /* get connected PHYs */ + alt_tse_mac_get_phy(pmac_group); + 801ae70: e13ffe17 ldw r4,-8(fp) + 801ae74: 801a6980 call 801a698 + 801ae78: 00000706 br 801ae98 + } + else { + tse_dprintf(3, "WARNING : MAC Groups[%d]->pmac_info[%d] MDIO is not used, unable to run PHY detection\n", i, j); + 801ae7c: e0bfffc7 ldb r2,-1(fp) + 801ae80: e0ffff87 ldb r3,-2(fp) + 801ae84: 180d883a mov r6,r3 + 801ae88: 100b883a mov r5,r2 + 801ae8c: 01020174 movhi r4,2053 + 801ae90: 2122bf04 addi r4,r4,-29956 + 801ae94: 8002c780 call 8002c78 + } + + /* Configure PCS mode if MAC+PCS system is used */ + for(j = 0; j < pmac_group->channel; j++) { + 801ae98: e03fff85 stb zero,-2(fp) + 801ae9c: 00000c06 br 801aed0 + pmac_info = pmac_group->pmac_info[j]; + 801aea0: e0bfff87 ldb r2,-2(fp) + 801aea4: e0fffe17 ldw r3,-8(fp) + 801aea8: 10800044 addi r2,r2,1 + 801aeac: 100490ba slli r2,r2,2 + 801aeb0: 1885883a add r2,r3,r2 + 801aeb4: 10800017 ldw r2,0(r2) + 801aeb8: e0bffd15 stw r2,-12(fp) + + alt_tse_phy_cfg_pcs(pmac_info); + 801aebc: e13ffd17 ldw r4,-12(fp) + 801aec0: 801ace40 call 801ace4 + for(j = 0; j < pmac_group->channel; j++) { + 801aec4: e0bfff83 ldbu r2,-2(fp) + 801aec8: 10800044 addi r2,r2,1 + 801aecc: e0bfff85 stb r2,-2(fp) + 801aed0: e0ffff87 ldb r3,-2(fp) + 801aed4: e0bffe17 ldw r2,-8(fp) + 801aed8: 10800003 ldbu r2,0(r2) + 801aedc: 10803fcc andi r2,r2,255 + 801aee0: 18bfef16 blt r3,r2,801aea0 + for(i = 0; i < mac_group_count; i++) { + 801aee4: e0bfffc3 ldbu r2,-1(fp) + 801aee8: 10800044 addi r2,r2,1 + 801aeec: e0bfffc5 stb r2,-1(fp) + 801aef0: e0ffffc7 ldb r3,-1(fp) + 801aef4: d0a05b43 ldbu r2,-32403(gp) + 801aef8: 10803fcc andi r2,r2,255 + 801aefc: 18bfd016 blt r3,r2,801ae40 + } + } + + return SUCCESS; + 801af00: 0005883a mov r2,zero +} + 801af04: e037883a mov sp,fp + 801af08: dfc00117 ldw ra,4(sp) + 801af0c: df000017 ldw fp,0(sp) + 801af10: dec00204 addi sp,sp,8 + 801af14: f800283a ret + +0801af18 : + * timeout_threshold timeout value of Auto-Negotiation + * @return return TSE_PHY_AN_COMPLETE if success + * return TSE_PHY_AN_NOT_COMPLETE if auto-negotiation not completed + * return TSE_PHY_AN_NOT_CAPABLE if the PHY not capable for AN + */ +alt_32 alt_tse_phy_restart_an(alt_tse_phy_info *pphy, alt_u32 timeout_threshold) { + 801af18: defff704 addi sp,sp,-36 + 801af1c: dfc00815 stw ra,32(sp) + 801af20: df000715 stw fp,28(sp) + 801af24: df000704 addi fp,sp,28 + 801af28: e13ffb15 stw r4,-20(fp) + 801af2c: e17ffa15 stw r5,-24(fp) + + /* pointer to MAC associated and MAC group */ + alt_tse_mac_info *pmac_info = pphy->pmac_info; + 801af30: e0bffb17 ldw r2,-20(fp) + 801af34: 10800617 ldw r2,24(r2) + 801af38: e0bfff15 stw r2,-4(fp) + alt_tse_mac_group *pmac_group = pmac_info->pmac_group; + 801af3c: e0bfff17 ldw r2,-4(fp) + 801af40: 10800317 ldw r2,12(r2) + 801af44: e0bffe15 stw r2,-8(fp) + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info); + 801af48: e13fff17 ldw r4,-4(fp) + 801af4c: 8018ba00 call 8018ba0 + 801af50: e0bffcc5 stb r2,-13(fp) + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + 801af54: e13ffe17 ldw r4,-8(fp) + 801af58: 8018b340 call 8018b34 + 801af5c: e0bffc85 stb r2,-14(fp) + + /* Record previous MDIO address, to be restored at the end of function */ + alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); + 801af60: e13ffb17 ldw r4,-20(fp) + 801af64: 80198cc0 call 80198cc + 801af68: e0bffc45 stb r2,-15(fp) + + /* write PHY address to MDIO to access the i-th PHY */ + alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address); + 801af6c: e0bffb17 ldw r2,-20(fp) + 801af70: 10800003 ldbu r2,0(r2) + 801af74: 10803fcc andi r2,r2,255 + 801af78: 100b883a mov r5,r2 + 801af7c: e13ffb17 ldw r4,-20(fp) + 801af80: 80199140 call 8019914 + + if(!alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_ABILITY, 1)) { + 801af84: 01c00044 movi r7,1 + 801af88: 018000c4 movi r6,3 + 801af8c: 01400044 movi r5,1 + 801af90: e13ffb17 ldw r4,-20(fp) + 801af94: 8019a980 call 8019a98 + 801af98: 10000d1e bne r2,zero,801afd0 + tse_dprintf(3, "WARNING : PHY[%d.%d] - PHY not capable for Auto-Negotiation\n", mac_group_index, mac_info_index); + 801af9c: e0bffc87 ldb r2,-14(fp) + 801afa0: e0fffcc7 ldb r3,-13(fp) + 801afa4: 180d883a mov r6,r3 + 801afa8: 100b883a mov r5,r2 + 801afac: 01020174 movhi r4,2053 + 801afb0: 2122d504 addi r4,r4,-29868 + 801afb4: 8002c780 call 8002c78 + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + 801afb8: e0bffc43 ldbu r2,-15(fp) + 801afbc: 100b883a mov r5,r2 + 801afc0: e13ffb17 ldw r4,-20(fp) + 801afc4: 80199140 call 8019914 + + return TSE_PHY_AN_NOT_CAPABLE; + 801afc8: 00bfff84 movi r2,-2 + 801afcc: 00003e06 br 801b0c8 + } + + /* enable Auto-Negotiation */ + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_AN_ENA, 1, 1); + 801afd0: 00800044 movi r2,1 + 801afd4: d8800015 stw r2,0(sp) + 801afd8: 01c00044 movi r7,1 + 801afdc: 01800304 movi r6,12 + 801afe0: 000b883a mov r5,zero + 801afe4: e13ffb17 ldw r4,-20(fp) + 801afe8: 801996c0 call 801996c + + /* send PHY reset command */ + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_RESTART_AN, 1, 1); + 801afec: 00800044 movi r2,1 + 801aff0: d8800015 stw r2,0(sp) + 801aff4: 01c00044 movi r7,1 + 801aff8: 01800244 movi r6,9 + 801affc: 000b883a mov r5,zero + 801b000: e13ffb17 ldw r4,-20(fp) + 801b004: 801996c0 call 801996c + tse_dprintf(5, "INFO : PHY[%d.%d] - Restart Auto-Negotiation, checking PHY link...\n", mac_group_index, mac_info_index); + 801b008: e0bffc87 ldb r2,-14(fp) + 801b00c: e0fffcc7 ldb r3,-13(fp) + 801b010: 180d883a mov r6,r3 + 801b014: 100b883a mov r5,r2 + 801b018: 01020174 movhi r4,2053 + 801b01c: 2122e504 addi r4,r4,-29804 + 801b020: 8002c780 call 8002c78 + + alt_32 timeout = 0; + 801b024: e03ffd15 stw zero,-12(fp) + while(alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_COMPLETE, 1) == 0 ){ + 801b028: 00001506 br 801b080 + if(timeout++ > timeout_threshold) { + 801b02c: e0bffd17 ldw r2,-12(fp) + 801b030: 10c00044 addi r3,r2,1 + 801b034: e0fffd15 stw r3,-12(fp) + 801b038: 1007883a mov r3,r2 + 801b03c: e0bffa17 ldw r2,-24(fp) + 801b040: 10c00d2e bgeu r2,r3,801b078 + tse_dprintf(4, "WARNING : PHY[%d.%d] - Auto-Negotiation FAILED\n", mac_group_index, mac_info_index); + 801b044: e0bffc87 ldb r2,-14(fp) + 801b048: e0fffcc7 ldb r3,-13(fp) + 801b04c: 180d883a mov r6,r3 + 801b050: 100b883a mov r5,r2 + 801b054: 01020174 movhi r4,2053 + 801b058: 2122f704 addi r4,r4,-29732 + 801b05c: 8002c780 call 8002c78 + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + 801b060: e0bffc43 ldbu r2,-15(fp) + 801b064: 100b883a mov r5,r2 + 801b068: e13ffb17 ldw r4,-20(fp) + 801b06c: 80199140 call 8019914 + + return TSE_PHY_AN_NOT_COMPLETE; + 801b070: 00bfffc4 movi r2,-1 + 801b074: 00001406 br 801b0c8 + } + usleep(1000); + 801b078: 0100fa04 movi r4,1000 + 801b07c: 803811c0 call 803811c + while(alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_COMPLETE, 1) == 0 ){ + 801b080: 01c00044 movi r7,1 + 801b084: 01800144 movi r6,5 + 801b088: 01400044 movi r5,1 + 801b08c: e13ffb17 ldw r4,-20(fp) + 801b090: 8019a980 call 8019a98 + 801b094: 103fe526 beq r2,zero,801b02c + } + tse_dprintf(5, "INFO : PHY[%d.%d] - Auto-Negotiation PASSED\n", mac_group_index, mac_info_index); + 801b098: e0bffc87 ldb r2,-14(fp) + 801b09c: e0fffcc7 ldb r3,-13(fp) + 801b0a0: 180d883a mov r6,r3 + 801b0a4: 100b883a mov r5,r2 + 801b0a8: 01020174 movhi r4,2053 + 801b0ac: 21230304 addi r4,r4,-29684 + 801b0b0: 8002c780 call 8002c78 + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + 801b0b4: e0bffc43 ldbu r2,-15(fp) + 801b0b8: 100b883a mov r5,r2 + 801b0bc: e13ffb17 ldw r4,-20(fp) + 801b0c0: 80199140 call 8019914 + + return TSE_PHY_AN_COMPLETE; + 801b0c4: 0005883a mov r2,zero +} + 801b0c8: e037883a mov sp,fp + 801b0cc: dfc00117 ldw ra,4(sp) + 801b0d0: df000017 ldw fp,0(sp) + 801b0d4: dec00204 addi sp,sp,8 + 801b0d8: f800283a ret + +0801b0dc : + * timeout_threshold timeout value of Auto-Negotiation + * @return return TSE_PHY_AN_COMPLETE if success + * return TSE_PHY_AN_NOT_COMPLETE if auto-negotiation not completed + */ +alt_32 alt_tse_phy_check_link(alt_tse_phy_info *pphy, alt_u32 timeout_threshold) +{ + 801b0dc: defff804 addi sp,sp,-32 + 801b0e0: dfc00715 stw ra,28(sp) + 801b0e4: df000615 stw fp,24(sp) + 801b0e8: df000604 addi fp,sp,24 + 801b0ec: e13ffb15 stw r4,-20(fp) + 801b0f0: e17ffa15 stw r5,-24(fp) + alt_32 timeout=0; + 801b0f4: e03fff15 stw zero,-4(fp) + + /* pointer to MAC associated and MAC group */ + alt_tse_mac_info *pmac_info = pphy->pmac_info; + 801b0f8: e0bffb17 ldw r2,-20(fp) + 801b0fc: 10800617 ldw r2,24(r2) + 801b100: e0bffe15 stw r2,-8(fp) + alt_tse_mac_group *pmac_group = pmac_info->pmac_group; + 801b104: e0bffe17 ldw r2,-8(fp) + 801b108: 10800317 ldw r2,12(r2) + 801b10c: e0bffd15 stw r2,-12(fp) + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info); + 801b110: e13ffe17 ldw r4,-8(fp) + 801b114: 8018ba00 call 8018ba0 + 801b118: e0bffcc5 stb r2,-13(fp) + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + 801b11c: e13ffd17 ldw r4,-12(fp) + 801b120: 8018b340 call 8018b34 + 801b124: e0bffc85 stb r2,-14(fp) + + /* Record previous MDIO address, to be restored at the end of function */ + alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); + 801b128: e13ffb17 ldw r4,-20(fp) + 801b12c: 80198cc0 call 80198cc + 801b130: e0bffc45 stb r2,-15(fp) + + /* write PHY address to MDIO to access the i-th PHY */ + alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address); + 801b134: e0bffb17 ldw r2,-20(fp) + 801b138: 10800003 ldbu r2,0(r2) + 801b13c: 10803fcc andi r2,r2,255 + 801b140: 100b883a mov r5,r2 + 801b144: e13ffb17 ldw r4,-20(fp) + 801b148: 80199140 call 8019914 + /* Issue a PHY reset here and wait for the link + * autonegotiation complete again... this takes several SECONDS(!) + * so be very careful not to do it frequently + * perform this when PHY is configured in loopback or has no link yet. + */ + tse_dprintf(5, "INFO : PHY[%d.%d] - Checking link...\n", mac_group_index, mac_info_index); + 801b14c: e0bffc87 ldb r2,-14(fp) + 801b150: e0fffcc7 ldb r3,-13(fp) + 801b154: 180d883a mov r6,r3 + 801b158: 100b883a mov r5,r2 + 801b15c: 01020174 movhi r4,2053 + 801b160: 21230f04 addi r4,r4,-29636 + 801b164: 8002c780 call 8002c78 + while( ((alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_LOOPBACK, 1)) != 0) || + 801b168: 00002106 br 801b1f0 + ((alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_COMPLETE, 1)) == 0) ) + { + if (timeout++ > timeout_threshold) + 801b16c: e0bfff17 ldw r2,-4(fp) + 801b170: 10c00044 addi r3,r2,1 + 801b174: e0ffff15 stw r3,-4(fp) + 801b178: 1007883a mov r3,r2 + 801b17c: e0bffa17 ldw r2,-24(fp) + 801b180: 10c0192e bgeu r2,r3,801b1e8 + { + tse_dprintf(5, "INFO : PHY[%d.%d] - Link not yet established, restart auto-negotiation...\n", mac_group_index, mac_info_index); + 801b184: e0bffc87 ldb r2,-14(fp) + 801b188: e0fffcc7 ldb r3,-13(fp) + 801b18c: 180d883a mov r6,r3 + 801b190: 100b883a mov r5,r2 + 801b194: 01020174 movhi r4,2053 + 801b198: 21231a04 addi r4,r4,-29592 + 801b19c: 8002c780 call 8002c78 + /* restart Auto-Negotiation */ + /* if Auto-Negotiation still cannot complete, then go to next PHY */ + if(alt_tse_phy_restart_an(pphy, timeout_threshold) == TSE_PHY_AN_NOT_COMPLETE) + 801b1a0: e17ffa17 ldw r5,-24(fp) + 801b1a4: e13ffb17 ldw r4,-20(fp) + 801b1a8: 801af180 call 801af18 + 801b1ac: 10bfffd8 cmpnei r2,r2,-1 + 801b1b0: 10000d1e bne r2,zero,801b1e8 + { + tse_dprintf(3, "WARNING : PHY[%d.%d] - Link could not established\n", mac_group_index, mac_info_index); + 801b1b4: e0bffc87 ldb r2,-14(fp) + 801b1b8: e0fffcc7 ldb r3,-13(fp) + 801b1bc: 180d883a mov r6,r3 + 801b1c0: 100b883a mov r5,r2 + 801b1c4: 01020174 movhi r4,2053 + 801b1c8: 21232e04 addi r4,r4,-29512 + 801b1cc: 8002c780 call 8002c78 + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + 801b1d0: e0bffc43 ldbu r2,-15(fp) + 801b1d4: 100b883a mov r5,r2 + 801b1d8: e13ffb17 ldw r4,-20(fp) + 801b1dc: 80199140 call 8019914 + + return TSE_PHY_AN_NOT_COMPLETE; + 801b1e0: 00bfffc4 movi r2,-1 + 801b1e4: 00001a06 br 801b250 + } + } + usleep(1000); + 801b1e8: 0100fa04 movi r4,1000 + 801b1ec: 803811c0 call 803811c + while( ((alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_LOOPBACK, 1)) != 0) || + 801b1f0: 01c00044 movi r7,1 + 801b1f4: 01800384 movi r6,14 + 801b1f8: 000b883a mov r5,zero + 801b1fc: e13ffb17 ldw r4,-20(fp) + 801b200: 8019a980 call 8019a98 + 801b204: 103fd91e bne r2,zero,801b16c + ((alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_COMPLETE, 1)) == 0) ) + 801b208: 01c00044 movi r7,1 + 801b20c: 01800144 movi r6,5 + 801b210: 01400044 movi r5,1 + 801b214: e13ffb17 ldw r4,-20(fp) + 801b218: 8019a980 call 8019a98 + while( ((alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_LOOPBACK, 1)) != 0) || + 801b21c: 103fd326 beq r2,zero,801b16c + } + tse_dprintf(5, "INFO : PHY[%d.%d] - Link established\n", mac_group_index, mac_info_index); + 801b220: e0bffc87 ldb r2,-14(fp) + 801b224: e0fffcc7 ldb r3,-13(fp) + 801b228: 180d883a mov r6,r3 + 801b22c: 100b883a mov r5,r2 + 801b230: 01020174 movhi r4,2053 + 801b234: 21233b04 addi r4,r4,-29460 + 801b238: 8002c780 call 8002c78 + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + 801b23c: e0bffc43 ldbu r2,-15(fp) + 801b240: 100b883a mov r5,r2 + 801b244: e13ffb17 ldw r4,-20(fp) + 801b248: 80199140 call 8019914 + + return TSE_PHY_AN_COMPLETE; + 801b24c: 0005883a mov r2,zero +} + 801b250: e037883a mov sp,fp + 801b254: dfc00117 ldw ra,4(sp) + 801b258: df000017 ldw fp,0(sp) + 801b25c: dec00204 addi sp,sp,8 + 801b260: f800283a ret + +0801b264 : + * @param pmac Pointer to the alt_tse_phy_info structure + * @return return TSE_PHY_AN_COMPLETE if success + * return TSE_PHY_AN_NOT_COMPLETE if auto-negotiation not completed + * return TSE_PHY_AN_NOT_CAPABLE if the PHY not capable for AN + */ +alt_32 alt_tse_phy_get_cap(alt_tse_phy_info *pphy) { + 801b264: defff904 addi sp,sp,-28 + 801b268: dfc00615 stw ra,24(sp) + 801b26c: df000515 stw fp,20(sp) + 801b270: df000504 addi fp,sp,20 + 801b274: e13ffb15 stw r4,-20(fp) + alt_32 return_value = TSE_PHY_AN_COMPLETE; + 801b278: e03fff15 stw zero,-4(fp) + + /* pointer to MAC associated and MAC group */ + alt_tse_mac_info *pmac_info = pphy->pmac_info; + 801b27c: e0bffb17 ldw r2,-20(fp) + 801b280: 10800617 ldw r2,24(r2) + 801b284: e0bffd15 stw r2,-12(fp) + alt_tse_mac_group *pmac_group = pmac_info->pmac_group; + 801b288: e0bffd17 ldw r2,-12(fp) + 801b28c: 10800317 ldw r2,12(r2) + 801b290: e0bffc15 stw r2,-16(fp) + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info); + 801b294: e13ffd17 ldw r4,-12(fp) + 801b298: 8018ba00 call 8018ba0 + 801b29c: e0bffe45 stb r2,-7(fp) + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + 801b2a0: e13ffc17 ldw r4,-16(fp) + 801b2a4: 8018b340 call 8018b34 + 801b2a8: e0bffe85 stb r2,-6(fp) + + /* Record previous MDIO address, to be restored at the end of function */ + alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); + 801b2ac: e13ffb17 ldw r4,-20(fp) + 801b2b0: 80198cc0 call 80198cc + 801b2b4: e0bffec5 stb r2,-5(fp) + + /* write PHY address to MDIO to access the i-th PHY */ + alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address); + 801b2b8: e0bffb17 ldw r2,-20(fp) + 801b2bc: 10800003 ldbu r2,0(r2) + 801b2c0: 10803fcc andi r2,r2,255 + 801b2c4: 100b883a mov r5,r2 + 801b2c8: e13ffb17 ldw r4,-20(fp) + 801b2cc: 80199140 call 8019914 + + if(!alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_ABILITY, 1)) { + 801b2d0: 01c00044 movi r7,1 + 801b2d4: 018000c4 movi r6,3 + 801b2d8: 01400044 movi r5,1 + 801b2dc: e13ffb17 ldw r4,-20(fp) + 801b2e0: 8019a980 call 8019a98 + 801b2e4: 10000d1e bne r2,zero,801b31c + tse_dprintf(3, "WARNING : PHY[%d.%d] - PHY not capable for Auto-Negotiation\n", mac_group_index, mac_info_index); + 801b2e8: e0bffe87 ldb r2,-6(fp) + 801b2ec: e0fffe47 ldb r3,-7(fp) + 801b2f0: 180d883a mov r6,r3 + 801b2f4: 100b883a mov r5,r2 + 801b2f8: 01020174 movhi r4,2053 + 801b2fc: 2122d504 addi r4,r4,-29868 + 801b300: 8002c780 call 8002c78 + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + 801b304: e0bffec3 ldbu r2,-5(fp) + 801b308: 100b883a mov r5,r2 + 801b30c: e13ffb17 ldw r4,-20(fp) + 801b310: 80199140 call 8019914 + + return TSE_PHY_AN_NOT_CAPABLE; + 801b314: 00bfff84 movi r2,-2 + 801b318: 00013006 br 801b7dc + } + + /* check whether link has been established */ + alt_tse_phy_restart_an(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD); + 801b31c: 01427104 movi r5,2500 + 801b320: e13ffb17 ldw r4,-20(fp) + 801b324: 801af180 call 801af18 + + if(alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_COMPLETE, 1) == 0) { + 801b328: 01c00044 movi r7,1 + 801b32c: 01800144 movi r6,5 + 801b330: 01400044 movi r5,1 + 801b334: e13ffb17 ldw r4,-20(fp) + 801b338: 8019a980 call 8019a98 + 801b33c: 1000021e bne r2,zero,801b348 + return_value = TSE_PHY_AN_NOT_COMPLETE; + 801b340: 00bfffc4 movi r2,-1 + 801b344: e0bfff15 stw r2,-4(fp) + } + + /* get PHY capabilities */ + pphy->link_capability.cap_1000_base_x_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_X_FULL, 1); + 801b348: 01c00044 movi r7,1 + 801b34c: 018003c4 movi r6,15 + 801b350: 014003c4 movi r5,15 + 801b354: e13ffb17 ldw r4,-20(fp) + 801b358: 8019a980 call 8019a98 + 801b35c: 1007883a mov r3,r2 + 801b360: e0bffb17 ldw r2,-20(fp) + 801b364: 10c00045 stb r3,1(r2) + pphy->link_capability.cap_1000_base_x_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_X_HALF, 1); + 801b368: 01c00044 movi r7,1 + 801b36c: 01800384 movi r6,14 + 801b370: 014003c4 movi r5,15 + 801b374: e13ffb17 ldw r4,-20(fp) + 801b378: 8019a980 call 8019a98 + 801b37c: 1007883a mov r3,r2 + 801b380: e0bffb17 ldw r2,-20(fp) + 801b384: 10c00085 stb r3,2(r2) + pphy->link_capability.cap_1000_base_t_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_T_FULL, 1); + 801b388: 01c00044 movi r7,1 + 801b38c: 01800344 movi r6,13 + 801b390: 014003c4 movi r5,15 + 801b394: e13ffb17 ldw r4,-20(fp) + 801b398: 8019a980 call 8019a98 + 801b39c: 1007883a mov r3,r2 + 801b3a0: e0bffb17 ldw r2,-20(fp) + 801b3a4: 10c000c5 stb r3,3(r2) + pphy->link_capability.cap_1000_base_t_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_T_HALF, 1); + 801b3a8: 01c00044 movi r7,1 + 801b3ac: 01800304 movi r6,12 + 801b3b0: 014003c4 movi r5,15 + 801b3b4: e13ffb17 ldw r4,-20(fp) + 801b3b8: 8019a980 call 8019a98 + 801b3bc: 1007883a mov r3,r2 + 801b3c0: e0bffb17 ldw r2,-20(fp) + 801b3c4: 10c00105 stb r3,4(r2) + + pphy->link_capability.cap_100_base_t4 = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_T4, 1); + 801b3c8: 01c00044 movi r7,1 + 801b3cc: 018003c4 movi r6,15 + 801b3d0: 01400044 movi r5,1 + 801b3d4: e13ffb17 ldw r4,-20(fp) + 801b3d8: 8019a980 call 8019a98 + 801b3dc: 1007883a mov r3,r2 + 801b3e0: e0bffb17 ldw r2,-20(fp) + 801b3e4: 10c00145 stb r3,5(r2) + pphy->link_capability.cap_100_base_x_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_X_FULL, 1); + 801b3e8: 01c00044 movi r7,1 + 801b3ec: 01800384 movi r6,14 + 801b3f0: 01400044 movi r5,1 + 801b3f4: e13ffb17 ldw r4,-20(fp) + 801b3f8: 8019a980 call 8019a98 + 801b3fc: 1007883a mov r3,r2 + 801b400: e0bffb17 ldw r2,-20(fp) + 801b404: 10c00185 stb r3,6(r2) + pphy->link_capability.cap_100_base_x_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_X_HALF, 1); + 801b408: 01c00044 movi r7,1 + 801b40c: 01800344 movi r6,13 + 801b410: 01400044 movi r5,1 + 801b414: e13ffb17 ldw r4,-20(fp) + 801b418: 8019a980 call 8019a98 + 801b41c: 1007883a mov r3,r2 + 801b420: e0bffb17 ldw r2,-20(fp) + 801b424: 10c001c5 stb r3,7(r2) + pphy->link_capability.cap_100_base_t2_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_T2_FULL, 1); + 801b428: 01c00044 movi r7,1 + 801b42c: 01800284 movi r6,10 + 801b430: 01400044 movi r5,1 + 801b434: e13ffb17 ldw r4,-20(fp) + 801b438: 8019a980 call 8019a98 + 801b43c: 1007883a mov r3,r2 + 801b440: e0bffb17 ldw r2,-20(fp) + 801b444: 10c00205 stb r3,8(r2) + pphy->link_capability.cap_100_base_t2_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_T2_HALF, 1); + 801b448: 01c00044 movi r7,1 + 801b44c: 01800244 movi r6,9 + 801b450: 01400044 movi r5,1 + 801b454: e13ffb17 ldw r4,-20(fp) + 801b458: 8019a980 call 8019a98 + 801b45c: 1007883a mov r3,r2 + 801b460: e0bffb17 ldw r2,-20(fp) + 801b464: 10c00245 stb r3,9(r2) + pphy->link_capability.cap_10_base_t_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_10BASE_T_FULL, 1); + 801b468: 01c00044 movi r7,1 + 801b46c: 01800304 movi r6,12 + 801b470: 01400044 movi r5,1 + 801b474: e13ffb17 ldw r4,-20(fp) + 801b478: 8019a980 call 8019a98 + 801b47c: 1007883a mov r3,r2 + 801b480: e0bffb17 ldw r2,-20(fp) + 801b484: 10c00285 stb r3,10(r2) + pphy->link_capability.cap_10_base_t_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_10BASE_T_HALF, 1); + 801b488: 01c00044 movi r7,1 + 801b48c: 018002c4 movi r6,11 + 801b490: 01400044 movi r5,1 + 801b494: e13ffb17 ldw r4,-20(fp) + 801b498: 8019a980 call 8019a98 + 801b49c: 1007883a mov r3,r2 + 801b4a0: e0bffb17 ldw r2,-20(fp) + 801b4a4: 10c002c5 stb r3,11(r2) + + /* get link partner capability */ + pphy->link_capability.lp_1000_base_t_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_STATUS, TSE_PHY_MDIO_1000BASE_T_STATUS_LP_FULL_ADV, 1); + 801b4a8: 01c00044 movi r7,1 + 801b4ac: 018002c4 movi r6,11 + 801b4b0: 01400284 movi r5,10 + 801b4b4: e13ffb17 ldw r4,-20(fp) + 801b4b8: 8019a980 call 8019a98 + 801b4bc: 1007883a mov r3,r2 + 801b4c0: e0bffb17 ldw r2,-20(fp) + 801b4c4: 10c00305 stb r3,12(r2) + pphy->link_capability.lp_1000_base_t_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_STATUS, TSE_PHY_MDIO_1000BASE_T_STATUS_LP_HALF_ADV, 1); + 801b4c8: 01c00044 movi r7,1 + 801b4cc: 01800284 movi r6,10 + 801b4d0: 01400284 movi r5,10 + 801b4d4: e13ffb17 ldw r4,-20(fp) + 801b4d8: 8019a980 call 8019a98 + 801b4dc: 1007883a mov r3,r2 + 801b4e0: e0bffb17 ldw r2,-20(fp) + 801b4e4: 10c00345 stb r3,13(r2) + + pphy->link_capability.lp_100_base_t4 = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_100BASE_T4, 1); + 801b4e8: 01c00044 movi r7,1 + 801b4ec: 01800244 movi r6,9 + 801b4f0: 01400144 movi r5,5 + 801b4f4: e13ffb17 ldw r4,-20(fp) + 801b4f8: 8019a980 call 8019a98 + 801b4fc: 1007883a mov r3,r2 + 801b500: e0bffb17 ldw r2,-20(fp) + 801b504: 10c00385 stb r3,14(r2) + pphy->link_capability.lp_100_base_tx_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_100BASE_TX_FULL, 1); + 801b508: 01c00044 movi r7,1 + 801b50c: 01800204 movi r6,8 + 801b510: 01400144 movi r5,5 + 801b514: e13ffb17 ldw r4,-20(fp) + 801b518: 8019a980 call 8019a98 + 801b51c: 1007883a mov r3,r2 + 801b520: e0bffb17 ldw r2,-20(fp) + 801b524: 10c003c5 stb r3,15(r2) + pphy->link_capability.lp_100_base_tx_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_100BASE_TX_HALF, 1); + 801b528: 01c00044 movi r7,1 + 801b52c: 018001c4 movi r6,7 + 801b530: 01400144 movi r5,5 + 801b534: e13ffb17 ldw r4,-20(fp) + 801b538: 8019a980 call 8019a98 + 801b53c: 1007883a mov r3,r2 + 801b540: e0bffb17 ldw r2,-20(fp) + 801b544: 10c00405 stb r3,16(r2) + pphy->link_capability.lp_10_base_tx_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_10BASE_TX_FULL, 1); + 801b548: 01c00044 movi r7,1 + 801b54c: 01800184 movi r6,6 + 801b550: 01400144 movi r5,5 + 801b554: e13ffb17 ldw r4,-20(fp) + 801b558: 8019a980 call 8019a98 + 801b55c: 1007883a mov r3,r2 + 801b560: e0bffb17 ldw r2,-20(fp) + 801b564: 10c00445 stb r3,17(r2) + pphy->link_capability.lp_10_base_tx_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_10BASE_TX_HALF, 1); + 801b568: 01c00044 movi r7,1 + 801b56c: 01800144 movi r6,5 + 801b570: 01400144 movi r5,5 + 801b574: e13ffb17 ldw r4,-20(fp) + 801b578: 8019a980 call 8019a98 + 801b57c: 1007883a mov r3,r2 + 801b580: e0bffb17 ldw r2,-20(fp) + 801b584: 10c00485 stb r3,18(r2) + + tse_dprintf(6, "INFO : PHY[%d.%d] - Capability of PHY :\n", mac_group_index, mac_info_index); + 801b588: e0bffe87 ldb r2,-6(fp) + 801b58c: e0fffe47 ldb r3,-7(fp) + 801b590: 180d883a mov r6,r3 + 801b594: 100b883a mov r5,r2 + 801b598: 01020174 movhi r4,2053 + 801b59c: 21234604 addi r4,r4,-29416 + 801b5a0: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : 1000 Base-X Full Duplex = %d\n", pphy->link_capability.cap_1000_base_x_full); + 801b5a4: e0bffb17 ldw r2,-20(fp) + 801b5a8: 10800043 ldbu r2,1(r2) + 801b5ac: 10803fcc andi r2,r2,255 + 801b5b0: 100b883a mov r5,r2 + 801b5b4: 01020174 movhi r4,2053 + 801b5b8: 21235104 addi r4,r4,-29372 + 801b5bc: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : 1000 Base-X Half Duplex = %d\n", pphy->link_capability.cap_1000_base_x_half); + 801b5c0: e0bffb17 ldw r2,-20(fp) + 801b5c4: 10800083 ldbu r2,2(r2) + 801b5c8: 10803fcc andi r2,r2,255 + 801b5cc: 100b883a mov r5,r2 + 801b5d0: 01020174 movhi r4,2053 + 801b5d4: 21235b04 addi r4,r4,-29332 + 801b5d8: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : 1000 Base-T Full Duplex = %d\n", pphy->link_capability.cap_1000_base_t_full); + 801b5dc: e0bffb17 ldw r2,-20(fp) + 801b5e0: 108000c3 ldbu r2,3(r2) + 801b5e4: 10803fcc andi r2,r2,255 + 801b5e8: 100b883a mov r5,r2 + 801b5ec: 01020174 movhi r4,2053 + 801b5f0: 21236504 addi r4,r4,-29292 + 801b5f4: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : 1000 Base-T Half Duplex = %d\n", pphy->link_capability.cap_1000_base_t_half); + 801b5f8: e0bffb17 ldw r2,-20(fp) + 801b5fc: 10800103 ldbu r2,4(r2) + 801b600: 10803fcc andi r2,r2,255 + 801b604: 100b883a mov r5,r2 + 801b608: 01020174 movhi r4,2053 + 801b60c: 21236f04 addi r4,r4,-29252 + 801b610: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : 100 Base-T4 = %d\n", pphy->link_capability.cap_100_base_t4); + 801b614: e0bffb17 ldw r2,-20(fp) + 801b618: 10800143 ldbu r2,5(r2) + 801b61c: 10803fcc andi r2,r2,255 + 801b620: 100b883a mov r5,r2 + 801b624: 01020174 movhi r4,2053 + 801b628: 21237904 addi r4,r4,-29212 + 801b62c: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : 100 Base-X Full Duplex = %d\n", pphy->link_capability.cap_100_base_x_full); + 801b630: e0bffb17 ldw r2,-20(fp) + 801b634: 10800183 ldbu r2,6(r2) + 801b638: 10803fcc andi r2,r2,255 + 801b63c: 100b883a mov r5,r2 + 801b640: 01020174 movhi r4,2053 + 801b644: 21238304 addi r4,r4,-29172 + 801b648: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : 100 Base-X Half Duplex = %d\n", pphy->link_capability.cap_100_base_x_half); + 801b64c: e0bffb17 ldw r2,-20(fp) + 801b650: 108001c3 ldbu r2,7(r2) + 801b654: 10803fcc andi r2,r2,255 + 801b658: 100b883a mov r5,r2 + 801b65c: 01020174 movhi r4,2053 + 801b660: 21238d04 addi r4,r4,-29132 + 801b664: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : 100 Base-T2 Full Duplex = %d\n", pphy->link_capability.cap_100_base_t2_full); + 801b668: e0bffb17 ldw r2,-20(fp) + 801b66c: 10800203 ldbu r2,8(r2) + 801b670: 10803fcc andi r2,r2,255 + 801b674: 100b883a mov r5,r2 + 801b678: 01020174 movhi r4,2053 + 801b67c: 21239704 addi r4,r4,-29092 + 801b680: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : 100 Base-T2 Half Duplex = %d\n", pphy->link_capability.cap_100_base_t2_half); + 801b684: e0bffb17 ldw r2,-20(fp) + 801b688: 10800243 ldbu r2,9(r2) + 801b68c: 10803fcc andi r2,r2,255 + 801b690: 100b883a mov r5,r2 + 801b694: 01020174 movhi r4,2053 + 801b698: 2123a104 addi r4,r4,-29052 + 801b69c: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : 10 Base-T Full Duplex = %d\n", pphy->link_capability.cap_10_base_t_full); + 801b6a0: e0bffb17 ldw r2,-20(fp) + 801b6a4: 10800283 ldbu r2,10(r2) + 801b6a8: 10803fcc andi r2,r2,255 + 801b6ac: 100b883a mov r5,r2 + 801b6b0: 01020174 movhi r4,2053 + 801b6b4: 2123ab04 addi r4,r4,-29012 + 801b6b8: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : 10 Base-T Half Duplex = %d\n", pphy->link_capability.cap_10_base_t_half); + 801b6bc: e0bffb17 ldw r2,-20(fp) + 801b6c0: 108002c3 ldbu r2,11(r2) + 801b6c4: 10803fcc andi r2,r2,255 + 801b6c8: 100b883a mov r5,r2 + 801b6cc: 01020174 movhi r4,2053 + 801b6d0: 2123b504 addi r4,r4,-28972 + 801b6d4: 8002c780 call 8002c78 + tse_dprintf(6, "\n"); + 801b6d8: 01000284 movi r4,10 + 801b6dc: 8002cb80 call 8002cb8 + + tse_dprintf(6, "INFO : PHY[%d.%d] - Link Partner Capability :\n", mac_group_index, mac_info_index); + 801b6e0: e0bffe87 ldb r2,-6(fp) + 801b6e4: e0fffe47 ldb r3,-7(fp) + 801b6e8: 180d883a mov r6,r3 + 801b6ec: 100b883a mov r5,r2 + 801b6f0: 01020174 movhi r4,2053 + 801b6f4: 2123bf04 addi r4,r4,-28932 + 801b6f8: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : 1000 Base-T Full Duplex = %d\n", pphy->link_capability.lp_1000_base_t_full); + 801b6fc: e0bffb17 ldw r2,-20(fp) + 801b700: 10800303 ldbu r2,12(r2) + 801b704: 10803fcc andi r2,r2,255 + 801b708: 100b883a mov r5,r2 + 801b70c: 01020174 movhi r4,2053 + 801b710: 21236504 addi r4,r4,-29292 + 801b714: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : 1000 Base-T Half Duplex = %d\n", pphy->link_capability.lp_1000_base_t_half); + 801b718: e0bffb17 ldw r2,-20(fp) + 801b71c: 10800343 ldbu r2,13(r2) + 801b720: 10803fcc andi r2,r2,255 + 801b724: 100b883a mov r5,r2 + 801b728: 01020174 movhi r4,2053 + 801b72c: 21236f04 addi r4,r4,-29252 + 801b730: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : 100 Base-T4 = %d\n", pphy->link_capability.lp_100_base_t4); + 801b734: e0bffb17 ldw r2,-20(fp) + 801b738: 10800383 ldbu r2,14(r2) + 801b73c: 10803fcc andi r2,r2,255 + 801b740: 100b883a mov r5,r2 + 801b744: 01020174 movhi r4,2053 + 801b748: 21237904 addi r4,r4,-29212 + 801b74c: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : 100 Base-TX Full Duplex = %d\n", pphy->link_capability.lp_100_base_tx_full); + 801b750: e0bffb17 ldw r2,-20(fp) + 801b754: 108003c3 ldbu r2,15(r2) + 801b758: 10803fcc andi r2,r2,255 + 801b75c: 100b883a mov r5,r2 + 801b760: 01020174 movhi r4,2053 + 801b764: 2123cc04 addi r4,r4,-28880 + 801b768: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : 100 Base-TX Half Duplex = %d\n", pphy->link_capability.lp_100_base_tx_half); + 801b76c: e0bffb17 ldw r2,-20(fp) + 801b770: 10800403 ldbu r2,16(r2) + 801b774: 10803fcc andi r2,r2,255 + 801b778: 100b883a mov r5,r2 + 801b77c: 01020174 movhi r4,2053 + 801b780: 2123d604 addi r4,r4,-28840 + 801b784: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : 10 Base-TX Full Duplex = %d\n", pphy->link_capability.lp_10_base_tx_full); + 801b788: e0bffb17 ldw r2,-20(fp) + 801b78c: 10800443 ldbu r2,17(r2) + 801b790: 10803fcc andi r2,r2,255 + 801b794: 100b883a mov r5,r2 + 801b798: 01020174 movhi r4,2053 + 801b79c: 2123e004 addi r4,r4,-28800 + 801b7a0: 8002c780 call 8002c78 + tse_dprintf(6, "INFO : 10 Base-TX Half Duplex = %d\n", pphy->link_capability.lp_10_base_tx_half); + 801b7a4: e0bffb17 ldw r2,-20(fp) + 801b7a8: 10800483 ldbu r2,18(r2) + 801b7ac: 10803fcc andi r2,r2,255 + 801b7b0: 100b883a mov r5,r2 + 801b7b4: 01020174 movhi r4,2053 + 801b7b8: 2123ea04 addi r4,r4,-28760 + 801b7bc: 8002c780 call 8002c78 + tse_dprintf(6, "\n"); + 801b7c0: 01000284 movi r4,10 + 801b7c4: 8002cb80 call 8002cb8 + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + 801b7c8: e0bffec3 ldbu r2,-5(fp) + 801b7cc: 100b883a mov r5,r2 + 801b7d0: e13ffb17 ldw r4,-20(fp) + 801b7d4: 80199140 call 8019914 + + return return_value; + 801b7d8: e0bfff17 ldw r2,-4(fp) + +} + 801b7dc: e037883a mov sp,fp + 801b7e0: dfc00117 ldw ra,4(sp) + 801b7e4: df000017 ldw fp,0(sp) + 801b7e8: dec00204 addi sp,sp,8 + 801b7ec: f800283a ret + +0801b7f0 : + * @param pmac Pointer to the alt_tse_phy_info structure + * enable set Enable = 1 to advertise this speed if the PHY capable + * set Enable = 0 to disable advertise of this speed + * @return return SUCCESS + */ +alt_32 alt_tse_phy_set_adv_1000(alt_tse_phy_info *pphy, alt_u8 enable) { + 801b7f0: defff604 addi sp,sp,-40 + 801b7f4: dfc00915 stw ra,36(sp) + 801b7f8: df000815 stw fp,32(sp) + 801b7fc: df000804 addi fp,sp,32 + 801b800: e13ffa15 stw r4,-24(fp) + 801b804: 2805883a mov r2,r5 + 801b808: e0bff905 stb r2,-28(fp) + alt_u8 cap; + + /* pointer to MAC associated and MAC group */ + alt_tse_mac_info *pmac_info = pphy->pmac_info; + 801b80c: e0bffa17 ldw r2,-24(fp) + 801b810: 10800617 ldw r2,24(r2) + 801b814: e0bffc15 stw r2,-16(fp) + alt_tse_mac_group *pmac_group = pmac_info->pmac_group; + 801b818: e0bffc17 ldw r2,-16(fp) + 801b81c: 10800317 ldw r2,12(r2) + 801b820: e0bffe15 stw r2,-8(fp) + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info); + 801b824: e13ffc17 ldw r4,-16(fp) + 801b828: 8018ba00 call 8018ba0 + 801b82c: e0bffdc5 stb r2,-9(fp) + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + 801b830: e13ffe17 ldw r4,-8(fp) + 801b834: 8018b340 call 8018b34 + 801b838: e0bfffc5 stb r2,-1(fp) + + /* Record previous MDIO address, to be restored at the end of function */ + alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); + 801b83c: e13ffa17 ldw r4,-24(fp) + 801b840: 80198cc0 call 80198cc + 801b844: e0bffbc5 stb r2,-17(fp) + + /* write PHY address to MDIO to access the i-th PHY */ + alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address); + 801b848: e0bffa17 ldw r2,-24(fp) + 801b84c: 10800003 ldbu r2,0(r2) + 801b850: 10803fcc andi r2,r2,255 + 801b854: 100b883a mov r5,r2 + 801b858: e13ffa17 ldw r4,-24(fp) + 801b85c: 80199140 call 8019914 + + /* if enable = 1, set advertisement based on PHY capability */ + if(enable) { + 801b860: e0bff903 ldbu r2,-28(fp) + 801b864: 10002d26 beq r2,zero,801b91c + cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_T_FULL, 1); + 801b868: 01c00044 movi r7,1 + 801b86c: 01800344 movi r6,13 + 801b870: 014003c4 movi r5,15 + 801b874: e13ffa17 ldw r4,-24(fp) + 801b878: 8019a980 call 8019a98 + 801b87c: e0bffb85 stb r2,-18(fp) + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_CTRL, TSE_PHY_MDIO_1000BASE_T_CTRL_FULL_ADV, 1, cap); + 801b880: e0bffb83 ldbu r2,-18(fp) + 801b884: d8800015 stw r2,0(sp) + 801b888: 01c00044 movi r7,1 + 801b88c: 01800244 movi r6,9 + 801b890: 01400244 movi r5,9 + 801b894: e13ffa17 ldw r4,-24(fp) + 801b898: 801996c0 call 801996c + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 1000 Base-T Full Duplex set to %d\n", mac_group_index, mac_info_index, cap); + 801b89c: e0bfffc7 ldb r2,-1(fp) + 801b8a0: e0fffdc7 ldb r3,-9(fp) + 801b8a4: e13ffb83 ldbu r4,-18(fp) + 801b8a8: 200f883a mov r7,r4 + 801b8ac: 180d883a mov r6,r3 + 801b8b0: 100b883a mov r5,r2 + 801b8b4: 01020174 movhi r4,2053 + 801b8b8: 2123f404 addi r4,r4,-28720 + 801b8bc: 8002c780 call 8002c78 + + /* 1000 Mbps Half duplex not supported by TSE MAC */ + cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_T_HALF, 1); + 801b8c0: 01c00044 movi r7,1 + 801b8c4: 01800304 movi r6,12 + 801b8c8: 014003c4 movi r5,15 + 801b8cc: e13ffa17 ldw r4,-24(fp) + 801b8d0: 8019a980 call 8019a98 + 801b8d4: e0bffb85 stb r2,-18(fp) + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_CTRL, TSE_PHY_MDIO_1000BASE_T_CTRL_HALF_ADV, 1, cap); + 801b8d8: e0bffb83 ldbu r2,-18(fp) + 801b8dc: d8800015 stw r2,0(sp) + 801b8e0: 01c00044 movi r7,1 + 801b8e4: 01800204 movi r6,8 + 801b8e8: 01400244 movi r5,9 + 801b8ec: e13ffa17 ldw r4,-24(fp) + 801b8f0: 801996c0 call 801996c + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 1000 Base-T Half Duplex set to %d\n", mac_group_index, mac_info_index, cap); + 801b8f4: e0bfffc7 ldb r2,-1(fp) + 801b8f8: e0fffdc7 ldb r3,-9(fp) + 801b8fc: e13ffb83 ldbu r4,-18(fp) + 801b900: 200f883a mov r7,r4 + 801b904: 180d883a mov r6,r3 + 801b908: 100b883a mov r5,r2 + 801b90c: 01020174 movhi r4,2053 + 801b910: 21240704 addi r4,r4,-28644 + 801b914: 8002c780 call 8002c78 + 801b918: 00001c06 br 801b98c + } + /* else disable advertisement of this speed */ + else { + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_CTRL, TSE_PHY_MDIO_1000BASE_T_CTRL_FULL_ADV, 1, 0); + 801b91c: d8000015 stw zero,0(sp) + 801b920: 01c00044 movi r7,1 + 801b924: 01800244 movi r6,9 + 801b928: 01400244 movi r5,9 + 801b92c: e13ffa17 ldw r4,-24(fp) + 801b930: 801996c0 call 801996c + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 1000 Base-T Full Duplex set to %d\n", mac_group_index, mac_info_index, 0); + 801b934: e0bfffc7 ldb r2,-1(fp) + 801b938: e0fffdc7 ldb r3,-9(fp) + 801b93c: 000f883a mov r7,zero + 801b940: 180d883a mov r6,r3 + 801b944: 100b883a mov r5,r2 + 801b948: 01020174 movhi r4,2053 + 801b94c: 2123f404 addi r4,r4,-28720 + 801b950: 8002c780 call 8002c78 + + /* 1000 Mbps Half duplex not supported by TSE MAC */ + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_CTRL, TSE_PHY_MDIO_1000BASE_T_CTRL_HALF_ADV, 1, 0); + 801b954: d8000015 stw zero,0(sp) + 801b958: 01c00044 movi r7,1 + 801b95c: 01800204 movi r6,8 + 801b960: 01400244 movi r5,9 + 801b964: e13ffa17 ldw r4,-24(fp) + 801b968: 801996c0 call 801996c + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement 1000 Base-T half Duplex set to %d\n", mac_group_index, mac_info_index, 0); + 801b96c: e0bfffc7 ldb r2,-1(fp) + 801b970: e0fffdc7 ldb r3,-9(fp) + 801b974: 000f883a mov r7,zero + 801b978: 180d883a mov r6,r3 + 801b97c: 100b883a mov r5,r2 + 801b980: 01020174 movhi r4,2053 + 801b984: 21241a04 addi r4,r4,-28568 + 801b988: 8002c780 call 8002c78 + } + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + 801b98c: e0bffbc3 ldbu r2,-17(fp) + 801b990: 100b883a mov r5,r2 + 801b994: e13ffa17 ldw r4,-24(fp) + 801b998: 80199140 call 8019914 + + return SUCCESS; + 801b99c: 0005883a mov r2,zero +} + 801b9a0: e037883a mov sp,fp + 801b9a4: dfc00117 ldw ra,4(sp) + 801b9a8: df000017 ldw fp,0(sp) + 801b9ac: dec00204 addi sp,sp,8 + 801b9b0: f800283a ret + +0801b9b4 : + * @param pmac Pointer to the alt_tse_phy_info structure + * enable set Enable = 1 to advertise this speed if the PHY capable + * set Enable = 0 to disable advertise of this speed + * @return return SUCCESS + */ +alt_32 alt_tse_phy_set_adv_100(alt_tse_phy_info *pphy, alt_u8 enable) { + 801b9b4: defff804 addi sp,sp,-32 + 801b9b8: dfc00715 stw ra,28(sp) + 801b9bc: df000615 stw fp,24(sp) + 801b9c0: df000604 addi fp,sp,24 + 801b9c4: e13ffc15 stw r4,-16(fp) + 801b9c8: 2805883a mov r2,r5 + 801b9cc: e0bffb05 stb r2,-20(fp) + alt_u8 cap; + + /* pointer to MAC associated and MAC group */ + alt_tse_mac_info *pmac_info = pphy->pmac_info; + 801b9d0: e0bffc17 ldw r2,-16(fp) + 801b9d4: 10800617 ldw r2,24(r2) + 801b9d8: e0bffd15 stw r2,-12(fp) + alt_tse_mac_group *pmac_group = pmac_info->pmac_group; + 801b9dc: e0bffd17 ldw r2,-12(fp) + 801b9e0: 10800317 ldw r2,12(r2) + 801b9e4: e0bffe15 stw r2,-8(fp) + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info); + 801b9e8: e13ffd17 ldw r4,-12(fp) + 801b9ec: 8018ba00 call 8018ba0 + 801b9f0: e0bfff45 stb r2,-3(fp) + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + 801b9f4: e13ffe17 ldw r4,-8(fp) + 801b9f8: 8018b340 call 8018b34 + 801b9fc: e0bfff05 stb r2,-4(fp) + + /* Record previous MDIO address, to be restored at the end of function */ + alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); + 801ba00: e13ffc17 ldw r4,-16(fp) + 801ba04: 80198cc0 call 80198cc + 801ba08: e0bfff85 stb r2,-2(fp) + + /* write PHY address to MDIO to access the i-th PHY */ + alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address); + 801ba0c: e0bffc17 ldw r2,-16(fp) + 801ba10: 10800003 ldbu r2,0(r2) + 801ba14: 10803fcc andi r2,r2,255 + 801ba18: 100b883a mov r5,r2 + 801ba1c: e13ffc17 ldw r4,-16(fp) + 801ba20: 80199140 call 8019914 + + /* if enable = 1, set advertisement based on PHY capability */ + if(enable) { + 801ba24: e0bffb03 ldbu r2,-20(fp) + 801ba28: 10004326 beq r2,zero,801bb38 + cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_T4, 1); + 801ba2c: 01c00044 movi r7,1 + 801ba30: 018003c4 movi r6,15 + 801ba34: 01400044 movi r5,1 + 801ba38: e13ffc17 ldw r4,-16(fp) + 801ba3c: 8019a980 call 8019a98 + 801ba40: e0bfffc5 stb r2,-1(fp) + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_T4, 1, cap); + 801ba44: e0bfffc3 ldbu r2,-1(fp) + 801ba48: d8800015 stw r2,0(sp) + 801ba4c: 01c00044 movi r7,1 + 801ba50: 01800244 movi r6,9 + 801ba54: 01400104 movi r5,4 + 801ba58: e13ffc17 ldw r4,-16(fp) + 801ba5c: 801996c0 call 801996c + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 100 Base-T4 set to %d\n", mac_group_index, mac_info_index, cap); + 801ba60: e0bfff07 ldb r2,-4(fp) + 801ba64: e0ffff47 ldb r3,-3(fp) + 801ba68: e13fffc3 ldbu r4,-1(fp) + 801ba6c: 200f883a mov r7,r4 + 801ba70: 180d883a mov r6,r3 + 801ba74: 100b883a mov r5,r2 + 801ba78: 01020174 movhi r4,2053 + 801ba7c: 21242c04 addi r4,r4,-28496 + 801ba80: 8002c780 call 8002c78 + + cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_X_FULL, 1); + 801ba84: 01c00044 movi r7,1 + 801ba88: 01800384 movi r6,14 + 801ba8c: 01400044 movi r5,1 + 801ba90: e13ffc17 ldw r4,-16(fp) + 801ba94: 8019a980 call 8019a98 + 801ba98: e0bfffc5 stb r2,-1(fp) + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_TX_FULL, 1, cap); + 801ba9c: e0bfffc3 ldbu r2,-1(fp) + 801baa0: d8800015 stw r2,0(sp) + 801baa4: 01c00044 movi r7,1 + 801baa8: 01800204 movi r6,8 + 801baac: 01400104 movi r5,4 + 801bab0: e13ffc17 ldw r4,-16(fp) + 801bab4: 801996c0 call 801996c + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 100 Base-TX Full Duplex set to %d\n", mac_group_index, mac_info_index, cap); + 801bab8: e0bfff07 ldb r2,-4(fp) + 801babc: e0ffff47 ldb r3,-3(fp) + 801bac0: e13fffc3 ldbu r4,-1(fp) + 801bac4: 200f883a mov r7,r4 + 801bac8: 180d883a mov r6,r3 + 801bacc: 100b883a mov r5,r2 + 801bad0: 01020174 movhi r4,2053 + 801bad4: 21243c04 addi r4,r4,-28432 + 801bad8: 8002c780 call 8002c78 + + cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_X_HALF, 1); + 801badc: 01c00044 movi r7,1 + 801bae0: 01800344 movi r6,13 + 801bae4: 01400044 movi r5,1 + 801bae8: e13ffc17 ldw r4,-16(fp) + 801baec: 8019a980 call 8019a98 + 801baf0: e0bfffc5 stb r2,-1(fp) + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_TX_HALF, 1, cap); + 801baf4: e0bfffc3 ldbu r2,-1(fp) + 801baf8: d8800015 stw r2,0(sp) + 801bafc: 01c00044 movi r7,1 + 801bb00: 018001c4 movi r6,7 + 801bb04: 01400104 movi r5,4 + 801bb08: e13ffc17 ldw r4,-16(fp) + 801bb0c: 801996c0 call 801996c + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 100 Base-TX Half Duplex set to %d\n", mac_group_index, mac_info_index, cap); + 801bb10: e0bfff07 ldb r2,-4(fp) + 801bb14: e0ffff47 ldb r3,-3(fp) + 801bb18: e13fffc3 ldbu r4,-1(fp) + 801bb1c: 200f883a mov r7,r4 + 801bb20: 180d883a mov r6,r3 + 801bb24: 100b883a mov r5,r2 + 801bb28: 01020174 movhi r4,2053 + 801bb2c: 21244f04 addi r4,r4,-28356 + 801bb30: 8002c780 call 8002c78 + 801bb34: 00002a06 br 801bbe0 + } + /* else disable advertisement of this speed */ + else { + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_T4, 1, 0); + 801bb38: d8000015 stw zero,0(sp) + 801bb3c: 01c00044 movi r7,1 + 801bb40: 01800244 movi r6,9 + 801bb44: 01400104 movi r5,4 + 801bb48: e13ffc17 ldw r4,-16(fp) + 801bb4c: 801996c0 call 801996c + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 100 Base-T4 set to %d\n", mac_group_index, mac_info_index, 0); + 801bb50: e0bfff07 ldb r2,-4(fp) + 801bb54: e0ffff47 ldb r3,-3(fp) + 801bb58: 000f883a mov r7,zero + 801bb5c: 180d883a mov r6,r3 + 801bb60: 100b883a mov r5,r2 + 801bb64: 01020174 movhi r4,2053 + 801bb68: 21242c04 addi r4,r4,-28496 + 801bb6c: 8002c780 call 8002c78 + + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_TX_FULL, 1, 0); + 801bb70: d8000015 stw zero,0(sp) + 801bb74: 01c00044 movi r7,1 + 801bb78: 01800204 movi r6,8 + 801bb7c: 01400104 movi r5,4 + 801bb80: e13ffc17 ldw r4,-16(fp) + 801bb84: 801996c0 call 801996c + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 100 Base-TX Full Duplex set to %d\n", mac_group_index, mac_info_index, 0); + 801bb88: e0bfff07 ldb r2,-4(fp) + 801bb8c: e0ffff47 ldb r3,-3(fp) + 801bb90: 000f883a mov r7,zero + 801bb94: 180d883a mov r6,r3 + 801bb98: 100b883a mov r5,r2 + 801bb9c: 01020174 movhi r4,2053 + 801bba0: 21243c04 addi r4,r4,-28432 + 801bba4: 8002c780 call 8002c78 + + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_TX_HALF, 1, 0); + 801bba8: d8000015 stw zero,0(sp) + 801bbac: 01c00044 movi r7,1 + 801bbb0: 018001c4 movi r6,7 + 801bbb4: 01400104 movi r5,4 + 801bbb8: e13ffc17 ldw r4,-16(fp) + 801bbbc: 801996c0 call 801996c + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 100 Base-TX Half Duplex set to %d\n", mac_group_index, mac_info_index, 0); + 801bbc0: e0bfff07 ldb r2,-4(fp) + 801bbc4: e0ffff47 ldb r3,-3(fp) + 801bbc8: 000f883a mov r7,zero + 801bbcc: 180d883a mov r6,r3 + 801bbd0: 100b883a mov r5,r2 + 801bbd4: 01020174 movhi r4,2053 + 801bbd8: 21244f04 addi r4,r4,-28356 + 801bbdc: 8002c780 call 8002c78 + } + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + 801bbe0: e0bfff83 ldbu r2,-2(fp) + 801bbe4: 100b883a mov r5,r2 + 801bbe8: e13ffc17 ldw r4,-16(fp) + 801bbec: 80199140 call 8019914 + + return SUCCESS; + 801bbf0: 0005883a mov r2,zero +} + 801bbf4: e037883a mov sp,fp + 801bbf8: dfc00117 ldw ra,4(sp) + 801bbfc: df000017 ldw fp,0(sp) + 801bc00: dec00204 addi sp,sp,8 + 801bc04: f800283a ret + +0801bc08 : + * @param pmac Pointer to the alt_tse_phy_info structure + * enable set Enable = 1 to advertise this speed if the PHY capable + * set Enable = 0 to disable advertise of this speed + * @return return SUCCESS + */ +alt_32 alt_tse_phy_set_adv_10(alt_tse_phy_info *pphy, alt_u8 enable) { + 801bc08: defff504 addi sp,sp,-44 + 801bc0c: dfc00a15 stw ra,40(sp) + 801bc10: df000915 stw fp,36(sp) + 801bc14: df000904 addi fp,sp,36 + 801bc18: e13ff915 stw r4,-28(fp) + 801bc1c: 2805883a mov r2,r5 + 801bc20: e0bff805 stb r2,-32(fp) + alt_u8 cap; + + /* pointer to MAC associated and MAC group */ + alt_tse_mac_info *pmac_info = pphy->pmac_info; + 801bc24: e0bff917 ldw r2,-28(fp) + 801bc28: 10800617 ldw r2,24(r2) + 801bc2c: e0bfff15 stw r2,-4(fp) + alt_tse_mac_group *pmac_group = pmac_info->pmac_group; + 801bc30: e0bfff17 ldw r2,-4(fp) + 801bc34: 10800317 ldw r2,12(r2) + 801bc38: e0bffe15 stw r2,-8(fp) + + /* get index of the pointers in pointer array list */ + int mac_info_index = alt_tse_get_mac_info_index(pmac_info); + 801bc3c: e13fff17 ldw r4,-4(fp) + 801bc40: 8018ba00 call 8018ba0 + 801bc44: e0bffd15 stw r2,-12(fp) + int mac_group_index = alt_tse_get_mac_group_index(pmac_group); + 801bc48: e13ffe17 ldw r4,-8(fp) + 801bc4c: 8018b340 call 8018b34 + 801bc50: e0bffc15 stw r2,-16(fp) + + /* Record previous MDIO address, to be restored at the end of function */ + int mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); + 801bc54: e13ff917 ldw r4,-28(fp) + 801bc58: 80198cc0 call 80198cc + 801bc5c: e0bffb15 stw r2,-20(fp) + + /* write PHY address to MDIO to access the i-th PHY */ + alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address); + 801bc60: e0bff917 ldw r2,-28(fp) + 801bc64: 10800003 ldbu r2,0(r2) + 801bc68: 10803fcc andi r2,r2,255 + 801bc6c: 100b883a mov r5,r2 + 801bc70: e13ff917 ldw r4,-28(fp) + 801bc74: 80199140 call 8019914 + + /* if enable = 1, set advertisement based on PHY capability */ + if(enable) { + 801bc78: e0bff803 ldbu r2,-32(fp) + 801bc7c: 10002926 beq r2,zero,801bd24 + cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_10BASE_T_FULL, 1); + 801bc80: 01c00044 movi r7,1 + 801bc84: 01800304 movi r6,12 + 801bc88: 01400044 movi r5,1 + 801bc8c: e13ff917 ldw r4,-28(fp) + 801bc90: 8019a980 call 8019a98 + 801bc94: e0bffac5 stb r2,-21(fp) + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_10BASE_TX_FULL, 1, cap); + 801bc98: e0bffac3 ldbu r2,-21(fp) + 801bc9c: d8800015 stw r2,0(sp) + 801bca0: 01c00044 movi r7,1 + 801bca4: 01800184 movi r6,6 + 801bca8: 01400104 movi r5,4 + 801bcac: e13ff917 ldw r4,-28(fp) + 801bcb0: 801996c0 call 801996c + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 10 Base-TX Full Duplex set to %d\n", mac_group_index, mac_info_index, cap); + 801bcb4: e0bffac3 ldbu r2,-21(fp) + 801bcb8: 100f883a mov r7,r2 + 801bcbc: e1bffd17 ldw r6,-12(fp) + 801bcc0: e17ffc17 ldw r5,-16(fp) + 801bcc4: 01020174 movhi r4,2053 + 801bcc8: 21246204 addi r4,r4,-28280 + 801bccc: 8002c780 call 8002c78 + + cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_10BASE_T_HALF, 1); + 801bcd0: 01c00044 movi r7,1 + 801bcd4: 018002c4 movi r6,11 + 801bcd8: 01400044 movi r5,1 + 801bcdc: e13ff917 ldw r4,-28(fp) + 801bce0: 8019a980 call 8019a98 + 801bce4: e0bffac5 stb r2,-21(fp) + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_10BASE_TX_HALF, 1, cap); + 801bce8: e0bffac3 ldbu r2,-21(fp) + 801bcec: d8800015 stw r2,0(sp) + 801bcf0: 01c00044 movi r7,1 + 801bcf4: 01800144 movi r6,5 + 801bcf8: 01400104 movi r5,4 + 801bcfc: e13ff917 ldw r4,-28(fp) + 801bd00: 801996c0 call 801996c + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 10 Base-TX Half Duplex set to %d\n", mac_group_index, mac_info_index, cap); + 801bd04: e0bffac3 ldbu r2,-21(fp) + 801bd08: 100f883a mov r7,r2 + 801bd0c: e1bffd17 ldw r6,-12(fp) + 801bd10: e17ffc17 ldw r5,-16(fp) + 801bd14: 01020174 movhi r4,2053 + 801bd18: 21247504 addi r4,r4,-28204 + 801bd1c: 8002c780 call 8002c78 + 801bd20: 00001806 br 801bd84 + } + /* else disable advertisement of this speed */ + else { + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_10BASE_TX_FULL, 1, 0); + 801bd24: d8000015 stw zero,0(sp) + 801bd28: 01c00044 movi r7,1 + 801bd2c: 01800184 movi r6,6 + 801bd30: 01400104 movi r5,4 + 801bd34: e13ff917 ldw r4,-28(fp) + 801bd38: 801996c0 call 801996c + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 10 Base-TX Full Duplex set to %d\n", mac_group_index, mac_info_index, 0); + 801bd3c: 000f883a mov r7,zero + 801bd40: e1bffd17 ldw r6,-12(fp) + 801bd44: e17ffc17 ldw r5,-16(fp) + 801bd48: 01020174 movhi r4,2053 + 801bd4c: 21246204 addi r4,r4,-28280 + 801bd50: 8002c780 call 8002c78 + + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_10BASE_TX_HALF, 1, 0); + 801bd54: d8000015 stw zero,0(sp) + 801bd58: 01c00044 movi r7,1 + 801bd5c: 01800144 movi r6,5 + 801bd60: 01400104 movi r5,4 + 801bd64: e13ff917 ldw r4,-28(fp) + 801bd68: 801996c0 call 801996c + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 10 Base-TX Half Duplex set to %d\n", mac_group_index, mac_info_index, 0); + 801bd6c: 000f883a mov r7,zero + 801bd70: e1bffd17 ldw r6,-12(fp) + 801bd74: e17ffc17 ldw r5,-16(fp) + 801bd78: 01020174 movhi r4,2053 + 801bd7c: 21247504 addi r4,r4,-28204 + 801bd80: 8002c780 call 8002c78 + } + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + 801bd84: e0bffb17 ldw r2,-20(fp) + 801bd88: 10803fcc andi r2,r2,255 + 801bd8c: 100b883a mov r5,r2 + 801bd90: e13ff917 ldw r4,-28(fp) + 801bd94: 80199140 call 8019914 + + return SUCCESS; + 801bd98: 0005883a mov r2,zero +} + 801bd9c: e037883a mov sp,fp + 801bda0: dfc00117 ldw ra,4(sp) + 801bda4: df000017 ldw fp,0(sp) + 801bda8: dec00204 addi sp,sp,8 + 801bdac: f800283a ret + +0801bdb0 : +/* @Function Description: Get the common speed supported by all PHYs connected to the MAC within the same group + * @API Type: Internal + * @param pmac_group Pointer to the TSE MAC Group structure which group all the MACs that should use the same speed + * @return common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if no common speed found + */ +alt_32 alt_tse_phy_get_common_speed(alt_tse_mac_group *pmac_group) { + 801bdb0: defff504 addi sp,sp,-44 + 801bdb4: dfc00a15 stw ra,40(sp) + 801bdb8: df000915 stw fp,36(sp) + 801bdbc: df000904 addi fp,sp,36 + 801bdc0: e13ff715 stw r4,-36(fp) + + alt_32 i; + alt_u8 common_1000 = 1; + 801bdc4: 00800044 movi r2,1 + 801bdc8: e0bfffc5 stb r2,-1(fp) + alt_u8 common_100 = 1; + 801bdcc: 00800044 movi r2,1 + 801bdd0: e0bffdc5 stb r2,-9(fp) + alt_u8 common_10 = 1; + 801bdd4: 00800044 movi r2,1 + 801bdd8: e0bffd85 stb r2,-10(fp) + + alt_32 common_speed; + + alt_u8 none_an_complete = 1; + 801bddc: 00800044 movi r2,1 + 801bde0: e0bffbc5 stb r2,-17(fp) + + alt_tse_mac_info *pmac_info = 0; + 801bde4: e03ffa15 stw zero,-24(fp) + alt_tse_phy_info *pphy = 0; + 801bde8: e03ff915 stw zero,-28(fp) + + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + 801bdec: e13ff717 ldw r4,-36(fp) + 801bdf0: 8018b340 call 8018b34 + 801bdf4: e0bff8c5 stb r2,-29(fp) + + /* reset Auto-Negotiation advertisement */ + for(i = 0; i < pmac_group->channel; i++) { + 801bdf8: e03ffe15 stw zero,-8(fp) + 801bdfc: 00001a06 br 801be68 + pmac_info = pmac_group->pmac_info[i]; + 801be00: e0fff717 ldw r3,-36(fp) + 801be04: e0bffe17 ldw r2,-8(fp) + 801be08: 10800044 addi r2,r2,1 + 801be0c: 100490ba slli r2,r2,2 + 801be10: 1885883a add r2,r3,r2 + 801be14: 10800017 ldw r2,0(r2) + 801be18: e0bffa15 stw r2,-24(fp) + pphy = pmac_info->pphy_info; + 801be1c: e0bffa17 ldw r2,-24(fp) + 801be20: 10800117 ldw r2,4(r2) + 801be24: e0bff915 stw r2,-28(fp) + + /* run only if PHY connected */ + if(pphy) { + 801be28: e0bff917 ldw r2,-28(fp) + 801be2c: 10000926 beq r2,zero,801be54 + alt_tse_phy_set_adv_1000(pphy, 1); + 801be30: 01400044 movi r5,1 + 801be34: e13ff917 ldw r4,-28(fp) + 801be38: 801b7f00 call 801b7f0 + alt_tse_phy_set_adv_100(pphy, 1); + 801be3c: 01400044 movi r5,1 + 801be40: e13ff917 ldw r4,-28(fp) + 801be44: 801b9b40 call 801b9b4 + alt_tse_phy_set_adv_10(pphy, 1); + 801be48: 01400044 movi r5,1 + 801be4c: e13ff917 ldw r4,-28(fp) + 801be50: 801bc080 call 801bc08 + } + tse_dprintf(6, "\n"); + 801be54: 01000284 movi r4,10 + 801be58: 8002cb80 call 8002cb8 + for(i = 0; i < pmac_group->channel; i++) { + 801be5c: e0bffe17 ldw r2,-8(fp) + 801be60: 10800044 addi r2,r2,1 + 801be64: e0bffe15 stw r2,-8(fp) + 801be68: e0bff717 ldw r2,-36(fp) + 801be6c: 10800003 ldbu r2,0(r2) + 801be70: 10803fcc andi r2,r2,255 + 801be74: e0fffe17 ldw r3,-8(fp) + 801be78: 18bfe116 blt r3,r2,801be00 + } + + /* loop through every PHY connected */ + for(i = 0; i < pmac_group->channel; i++) { + 801be7c: e03ffe15 stw zero,-8(fp) + 801be80: 00005506 br 801bfd8 + + pmac_info = pmac_group->pmac_info[i]; + 801be84: e0fff717 ldw r3,-36(fp) + 801be88: e0bffe17 ldw r2,-8(fp) + 801be8c: 10800044 addi r2,r2,1 + 801be90: 100490ba slli r2,r2,2 + 801be94: 1885883a add r2,r3,r2 + 801be98: 10800017 ldw r2,0(r2) + 801be9c: e0bffa15 stw r2,-24(fp) + pphy = pmac_info->pphy_info; + 801bea0: e0bffa17 ldw r2,-24(fp) + 801bea4: 10800117 ldw r2,4(r2) + 801bea8: e0bff915 stw r2,-28(fp) + + /* if no PHY connected */ + if(!pphy) { + 801beac: e0bff917 ldw r2,-28(fp) + 801beb0: 10004326 beq r2,zero,801bfc0 + continue; + } + + /* get PHY capability */ + /* skip for PHY with Auto-Negotiation not completed */ + if(alt_tse_phy_get_cap(pphy) != TSE_PHY_AN_COMPLETE) { + 801beb4: e13ff917 ldw r4,-28(fp) + 801beb8: 801b2640 call 801b264 + 801bebc: 1000421e bne r2,zero,801bfc8 + continue; + } + + none_an_complete = 0; + 801bec0: e03ffbc5 stb zero,-17(fp) + + /* Small MAC */ + if(pmac_info->mac_type == ALTERA_TSE_MACLITE_10_100) { + 801bec4: e0bffa17 ldw r2,-24(fp) + 801bec8: 10800003 ldbu r2,0(r2) + 801becc: 10803fcc andi r2,r2,255 + 801bed0: 10800058 cmpnei r2,r2,1 + 801bed4: 1000021e bne r2,zero,801bee0 + common_1000 = 0; + 801bed8: e03fffc5 stb zero,-1(fp) + 801bedc: 00000706 br 801befc + } + else if(pmac_info->mac_type == ALTERA_TSE_MACLITE_1000) { + 801bee0: e0bffa17 ldw r2,-24(fp) + 801bee4: 10800003 ldbu r2,0(r2) + 801bee8: 10803fcc andi r2,r2,255 + 801beec: 10800098 cmpnei r2,r2,2 + 801bef0: 1000021e bne r2,zero,801befc + common_100 = 0; + 801bef4: e03ffdc5 stb zero,-9(fp) + common_10 = 0; + 801bef8: e03ffd85 stb zero,-10(fp) + } + + /* get common capabilities for all PHYs and link partners */ + common_1000 &= ((pphy->link_capability.cap_1000_base_t_full & pphy->link_capability.lp_1000_base_t_full)); + 801befc: e0bff917 ldw r2,-28(fp) + 801bf00: 10c000c3 ldbu r3,3(r2) + 801bf04: e0bff917 ldw r2,-28(fp) + 801bf08: 10800303 ldbu r2,12(r2) + 801bf0c: 1884703a and r2,r3,r2 + 801bf10: 1007883a mov r3,r2 + 801bf14: e0bfffc3 ldbu r2,-1(fp) + 801bf18: 10c4703a and r2,r2,r3 + 801bf1c: e0bfffc5 stb r2,-1(fp) + //(pphy->link_capability.cap_1000_base_t_half & pphy->link_capability.lp_1000_base_t_half)); + common_100 &= ((pphy->link_capability.cap_100_base_x_full & pphy->link_capability.lp_100_base_tx_full) | + 801bf20: e0bff917 ldw r2,-28(fp) + 801bf24: 10c00183 ldbu r3,6(r2) + 801bf28: e0bff917 ldw r2,-28(fp) + 801bf2c: 108003c3 ldbu r2,15(r2) + 801bf30: 1884703a and r2,r3,r2 + 801bf34: 1009883a mov r4,r2 + (pphy->link_capability.cap_100_base_x_half & pphy->link_capability.lp_100_base_tx_half) | + 801bf38: e0bff917 ldw r2,-28(fp) + 801bf3c: 10c001c3 ldbu r3,7(r2) + 801bf40: e0bff917 ldw r2,-28(fp) + 801bf44: 10800403 ldbu r2,16(r2) + common_100 &= ((pphy->link_capability.cap_100_base_x_full & pphy->link_capability.lp_100_base_tx_full) | + 801bf48: 1884703a and r2,r3,r2 + 801bf4c: 2084b03a or r2,r4,r2 + 801bf50: 1009883a mov r4,r2 + (pphy->link_capability.cap_100_base_t4 & pphy->link_capability.lp_100_base_t4)); + 801bf54: e0bff917 ldw r2,-28(fp) + 801bf58: 10c00143 ldbu r3,5(r2) + 801bf5c: e0bff917 ldw r2,-28(fp) + 801bf60: 10800383 ldbu r2,14(r2) + common_100 &= ((pphy->link_capability.cap_100_base_x_full & pphy->link_capability.lp_100_base_tx_full) | + 801bf64: 1884703a and r2,r3,r2 + 801bf68: 2084b03a or r2,r4,r2 + 801bf6c: 1007883a mov r3,r2 + 801bf70: e0bffdc3 ldbu r2,-9(fp) + 801bf74: 10c4703a and r2,r2,r3 + 801bf78: e0bffdc5 stb r2,-9(fp) + common_10 &= ((pphy->link_capability.cap_10_base_t_full & pphy->link_capability.lp_10_base_tx_full) | + 801bf7c: e0bff917 ldw r2,-28(fp) + 801bf80: 10c00283 ldbu r3,10(r2) + 801bf84: e0bff917 ldw r2,-28(fp) + 801bf88: 10800443 ldbu r2,17(r2) + 801bf8c: 1884703a and r2,r3,r2 + 801bf90: 1009883a mov r4,r2 + (pphy->link_capability.cap_10_base_t_half & pphy->link_capability.lp_10_base_tx_half)); + 801bf94: e0bff917 ldw r2,-28(fp) + 801bf98: 10c002c3 ldbu r3,11(r2) + 801bf9c: e0bff917 ldw r2,-28(fp) + 801bfa0: 10800483 ldbu r2,18(r2) + common_10 &= ((pphy->link_capability.cap_10_base_t_full & pphy->link_capability.lp_10_base_tx_full) | + 801bfa4: 1884703a and r2,r3,r2 + 801bfa8: 2084b03a or r2,r4,r2 + 801bfac: 1007883a mov r3,r2 + 801bfb0: e0bffd83 ldbu r2,-10(fp) + 801bfb4: 10c4703a and r2,r2,r3 + 801bfb8: e0bffd85 stb r2,-10(fp) + 801bfbc: 00000306 br 801bfcc + continue; + 801bfc0: 0001883a nop + 801bfc4: 00000106 br 801bfcc + continue; + 801bfc8: 0001883a nop + for(i = 0; i < pmac_group->channel; i++) { + 801bfcc: e0bffe17 ldw r2,-8(fp) + 801bfd0: 10800044 addi r2,r2,1 + 801bfd4: e0bffe15 stw r2,-8(fp) + 801bfd8: e0bff717 ldw r2,-36(fp) + 801bfdc: 10800003 ldbu r2,0(r2) + 801bfe0: 10803fcc andi r2,r2,255 + 801bfe4: e0fffe17 ldw r3,-8(fp) + 801bfe8: 18bfa616 blt r3,r2,801be84 + + } + + /* get common speed based on capabilities */ + if(none_an_complete == 1) { + 801bfec: e0bffbc3 ldbu r2,-17(fp) + 801bff0: 10800058 cmpnei r2,r2,1 + 801bff4: 1000081e bne r2,zero,801c018 + common_speed = TSE_PHY_SPEED_NO_COMMON; + 801bff8: 00bfffc4 movi r2,-1 + 801bffc: e0bffc15 stw r2,-16(fp) + tse_dprintf(2, "ERROR : MAC Group[%d] - None of the PHYs Auto-Negotiation completed!\n", mac_group_index); + 801c000: e0bff8c7 ldb r2,-29(fp) + 801c004: 100b883a mov r5,r2 + 801c008: 01020174 movhi r4,2053 + 801c00c: 21248804 addi r4,r4,-28128 + 801c010: 8002c780 call 8002c78 + 801c014: 00002706 br 801c0b4 + } + else if(common_1000) { + 801c018: e0bfffc3 ldbu r2,-1(fp) + 801c01c: 10000926 beq r2,zero,801c044 + common_speed = TSE_PHY_SPEED_1000; + 801c020: 00800084 movi r2,2 + 801c024: e0bffc15 stw r2,-16(fp) + tse_dprintf(5, "INFO : MAC Group[%d] - Common Speed : %d Mbps\n", mac_group_index, 1000); + 801c028: e0bff8c7 ldb r2,-29(fp) + 801c02c: 0180fa04 movi r6,1000 + 801c030: 100b883a mov r5,r2 + 801c034: 01020174 movhi r4,2053 + 801c038: 21249a04 addi r4,r4,-28056 + 801c03c: 8002c780 call 8002c78 + 801c040: 00001c06 br 801c0b4 + } + else if(common_100) { + 801c044: e0bffdc3 ldbu r2,-9(fp) + 801c048: 10000926 beq r2,zero,801c070 + common_speed = TSE_PHY_SPEED_100; + 801c04c: 00800044 movi r2,1 + 801c050: e0bffc15 stw r2,-16(fp) + tse_dprintf(5, "INFO : MAC Group[%d] - Common Speed : %d Mbps\n", mac_group_index, 100); + 801c054: e0bff8c7 ldb r2,-29(fp) + 801c058: 01801904 movi r6,100 + 801c05c: 100b883a mov r5,r2 + 801c060: 01020174 movhi r4,2053 + 801c064: 21249a04 addi r4,r4,-28056 + 801c068: 8002c780 call 8002c78 + 801c06c: 00001106 br 801c0b4 + } + else if(common_10) { + 801c070: e0bffd83 ldbu r2,-10(fp) + 801c074: 10000826 beq r2,zero,801c098 + common_speed = TSE_PHY_SPEED_10; + 801c078: e03ffc15 stw zero,-16(fp) + tse_dprintf(5, "INFO : MAC Group[%d] - Common Speed : %d Mbps\n", mac_group_index, 10); + 801c07c: e0bff8c7 ldb r2,-29(fp) + 801c080: 01800284 movi r6,10 + 801c084: 100b883a mov r5,r2 + 801c088: 01020174 movhi r4,2053 + 801c08c: 21249a04 addi r4,r4,-28056 + 801c090: 8002c780 call 8002c78 + 801c094: 00000706 br 801c0b4 + } + else { + common_speed = TSE_PHY_SPEED_NO_COMMON; + 801c098: 00bfffc4 movi r2,-1 + 801c09c: e0bffc15 stw r2,-16(fp) + tse_dprintf(2, "ERROR : MAC Group[%d] - No common speed at all!\n", mac_group_index); } + 801c0a0: e0bff8c7 ldb r2,-29(fp) + 801c0a4: 100b883a mov r5,r2 + 801c0a8: 01020174 movhi r4,2053 + 801c0ac: 2124a704 addi r4,r4,-28004 + 801c0b0: 8002c780 call 8002c78 + + return common_speed; + 801c0b4: e0bffc17 ldw r2,-16(fp) +} + 801c0b8: e037883a mov sp,fp + 801c0bc: dfc00117 ldw ra,4(sp) + 801c0c0: df000017 ldw fp,0(sp) + 801c0c4: dec00204 addi sp,sp,8 + 801c0c8: f800283a ret + +0801c0cc : + * @API Type: Internal + * @param pmac_group Pointer to the TSE MAC Group structure which group all the MACs that should use the same speed + * common_speed common speed supported by all PHYs + * @return common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if invalid common speed specified + */ +alt_32 alt_tse_phy_set_common_speed(alt_tse_mac_group *pmac_group, alt_32 common_speed) { + 801c0cc: defff004 addi sp,sp,-64 + 801c0d0: dfc00f15 stw ra,60(sp) + 801c0d4: df000e15 stw fp,56(sp) + 801c0d8: dc400d15 stw r17,52(sp) + 801c0dc: dc000c15 stw r16,48(sp) + 801c0e0: df000e04 addi fp,sp,56 + 801c0e4: e13ff415 stw r4,-48(fp) + 801c0e8: e17ff315 stw r5,-52(fp) + alt_u8 speed; + alt_u8 duplex; + + alt_u8 gb_capable; + + alt_tse_phy_info *pphy = 0; + 801c0ec: e03ffb15 stw zero,-20(fp) + alt_tse_mac_info *pmac_info = 0; + 801c0f0: e03ffa15 stw zero,-24(fp) + alt_tse_system_info *psys = 0; + 801c0f4: e03ff915 stw zero,-28(fp) + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = 0; + 801c0f8: e03ff8c5 stb zero,-29(fp) + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + 801c0fc: e13ff417 ldw r4,-48(fp) + 801c100: 8018b340 call 8018b34 + 801c104: e0bff885 stb r2,-30(fp) + + /* Record previous MDIO address, to be restored at the end of function */ + np_tse_mac *pmac_group_base = (np_tse_mac *)pmac_group->pmac_info[0]->psys_info->tse_mac_base; + 801c108: e0bff417 ldw r2,-48(fp) + 801c10c: 10800117 ldw r2,4(r2) + 801c110: 10800217 ldw r2,8(r2) + 801c114: 10800017 ldw r2,0(r2) + 801c118: e0bff715 stw r2,-36(fp) + alt_32 mdioadd_prev = IORD(&pmac_group_base->MDIO_ADDR1, 0); + 801c11c: e0bff717 ldw r2,-36(fp) + 801c120: 10801004 addi r2,r2,64 + 801c124: 10800037 ldwio r2,0(r2) + 801c128: e0bff615 stw r2,-40(fp) + + if((common_speed < TSE_PHY_SPEED_10) || (common_speed > TSE_PHY_SPEED_1000)) { + 801c12c: e0bff317 ldw r2,-52(fp) + 801c130: 10000316 blt r2,zero,801c140 + 801c134: e0bff317 ldw r2,-52(fp) + 801c138: 108000d0 cmplti r2,r2,3 + 801c13c: 10000c1e bne r2,zero,801c170 + tse_dprintf(2, "ERROR : MAC Group[%d] - Invalid common speed specified! common speed = %d\n", mac_group_index, (int)common_speed); + 801c140: e0bff887 ldb r2,-30(fp) + 801c144: e1bff317 ldw r6,-52(fp) + 801c148: 100b883a mov r5,r2 + 801c14c: 01020174 movhi r4,2053 + 801c150: 2124b404 addi r4,r4,-27952 + 801c154: 8002c780 call 8002c78 + /* Restore previous MDIO address */ + IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdioadd_prev); + 801c158: e0bff717 ldw r2,-36(fp) + 801c15c: 10801004 addi r2,r2,64 + 801c160: e0fff617 ldw r3,-40(fp) + 801c164: 10c00035 stwio r3,0(r2) + return TSE_PHY_SPEED_NO_COMMON; + 801c168: 00bfffc4 movi r2,-1 + 801c16c: 0000fc06 br 801c560 + } + + /* loop through every PHY connected */ + for(i = 0; i < pmac_group->channel; i++) { + 801c170: e03ffc15 stw zero,-16(fp) + 801c174: 0000da06 br 801c4e0 + pmac_info = pmac_group->pmac_info[i]; + 801c178: e0fff417 ldw r3,-48(fp) + 801c17c: e0bffc17 ldw r2,-16(fp) + 801c180: 10800044 addi r2,r2,1 + 801c184: 100490ba slli r2,r2,2 + 801c188: 1885883a add r2,r3,r2 + 801c18c: 10800017 ldw r2,0(r2) + 801c190: e0bffa15 stw r2,-24(fp) + mac_info_index = alt_tse_get_mac_info_index(pmac_info); + 801c194: e13ffa17 ldw r4,-24(fp) + 801c198: 8018ba00 call 8018ba0 + 801c19c: e0bff8c5 stb r2,-29(fp) + + pphy = pmac_info->pphy_info; + 801c1a0: e0bffa17 ldw r2,-24(fp) + 801c1a4: 10800117 ldw r2,4(r2) + 801c1a8: e0bffb15 stw r2,-20(fp) + + /* if no PHY connected */ + if(!pphy) { + 801c1ac: e0bffb17 ldw r2,-20(fp) + 801c1b0: 1000c726 beq r2,zero,801c4d0 + continue; + } + + psys = pmac_info->psys_info; + 801c1b4: e0bffa17 ldw r2,-24(fp) + 801c1b8: 10800217 ldw r2,8(r2) + 801c1bc: e0bff915 stw r2,-28(fp) + + /* write PHY address to MDIO to access the i-th PHY */ + alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address); + 801c1c0: e0bffb17 ldw r2,-20(fp) + 801c1c4: 10800003 ldbu r2,0(r2) + 801c1c8: 10803fcc andi r2,r2,255 + 801c1cc: 100b883a mov r5,r2 + 801c1d0: e13ffb17 ldw r4,-20(fp) + 801c1d4: 80199140 call 8019914 + + /* capability of PHY supports 1000 Mbps */ + gb_capable = pphy->link_capability.cap_1000_base_t_full || pphy->link_capability.cap_1000_base_t_half || + 801c1d8: e0bffb17 ldw r2,-20(fp) + 801c1dc: 108000c3 ldbu r2,3(r2) + pphy->link_capability.cap_1000_base_x_full || pphy->link_capability.cap_1000_base_x_half; + 801c1e0: 10803fcc andi r2,r2,255 + 801c1e4: 10000c1e bne r2,zero,801c218 + gb_capable = pphy->link_capability.cap_1000_base_t_full || pphy->link_capability.cap_1000_base_t_half || + 801c1e8: e0bffb17 ldw r2,-20(fp) + 801c1ec: 10800103 ldbu r2,4(r2) + 801c1f0: 10803fcc andi r2,r2,255 + 801c1f4: 1000081e bne r2,zero,801c218 + pphy->link_capability.cap_1000_base_x_full || pphy->link_capability.cap_1000_base_x_half; + 801c1f8: e0bffb17 ldw r2,-20(fp) + 801c1fc: 10800043 ldbu r2,1(r2) + gb_capable = pphy->link_capability.cap_1000_base_t_full || pphy->link_capability.cap_1000_base_t_half || + 801c200: 10803fcc andi r2,r2,255 + 801c204: 1000041e bne r2,zero,801c218 + pphy->link_capability.cap_1000_base_x_full || pphy->link_capability.cap_1000_base_x_half; + 801c208: e0bffb17 ldw r2,-20(fp) + 801c20c: 10800083 ldbu r2,2(r2) + 801c210: 10803fcc andi r2,r2,255 + 801c214: 10000226 beq r2,zero,801c220 + 801c218: 00800044 movi r2,1 + 801c21c: 00000106 br 801c224 + 801c220: 0005883a mov r2,zero + gb_capable = pphy->link_capability.cap_1000_base_t_full || pphy->link_capability.cap_1000_base_t_half || + 801c224: e0bff5c5 stb r2,-41(fp) + + /* if PHY does not supports 1000 Mbps, and common speed is 1000 Mbps */ + if((!gb_capable) && (common_speed == TSE_PHY_SPEED_1000)) { + 801c228: e0bff5c3 ldbu r2,-41(fp) + 801c22c: 1000101e bne r2,zero,801c270 + 801c230: e0bff317 ldw r2,-52(fp) + 801c234: 10800098 cmpnei r2,r2,2 + 801c238: 10000d1e bne r2,zero,801c270 + tse_dprintf(2, "ERROR : PHY[%d.%d] - PHY does not support 1000 Mbps, please specify valid common speed\n", mac_group_index, mac_info_index); + 801c23c: e0bff887 ldb r2,-30(fp) + 801c240: e0fff8c7 ldb r3,-29(fp) + 801c244: 180d883a mov r6,r3 + 801c248: 100b883a mov r5,r2 + 801c24c: 01020174 movhi r4,2053 + 801c250: 2124c804 addi r4,r4,-27872 + 801c254: 8002c780 call 8002c78 + /* Restore previous MDIO address */ + IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdioadd_prev); + 801c258: e0bff717 ldw r2,-36(fp) + 801c25c: 10801004 addi r2,r2,64 + 801c260: e0fff617 ldw r3,-40(fp) + 801c264: 10c00035 stwio r3,0(r2) + return TSE_PHY_SPEED_NO_COMMON; + 801c268: 00bfffc4 movi r2,-1 + 801c26c: 0000bc06 br 801c560 + } + + /* if PHY is not Auto-Negotiation capable */ + if(!alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_ABILITY, 1)) { + 801c270: 01c00044 movi r7,1 + 801c274: 018000c4 movi r6,3 + 801c278: 01400044 movi r5,1 + 801c27c: e13ffb17 ldw r4,-20(fp) + 801c280: 8019a980 call 8019a98 + 801c284: 1000141e bne r2,zero,801c2d8 + + /* if PHY supports 1000 Mbps, write msb of speed */ + if(gb_capable) { + 801c288: e0bff5c3 ldbu r2,-41(fp) + 801c28c: 10000926 beq r2,zero,801c2b4 + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_SPEED_MSB, 1, common_speed >> 1); + 801c290: e0bff317 ldw r2,-52(fp) + 801c294: 1005d07a srai r2,r2,1 + 801c298: 10bfffcc andi r2,r2,65535 + 801c29c: d8800015 stw r2,0(sp) + 801c2a0: 01c00044 movi r7,1 + 801c2a4: 01800184 movi r6,6 + 801c2a8: 000b883a mov r5,zero + 801c2ac: e13ffb17 ldw r4,-20(fp) + 801c2b0: 801996c0 call 801996c + } + /* write lsb of speed */ + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_SPEED_LSB, 1, common_speed); + 801c2b4: e0bff317 ldw r2,-52(fp) + 801c2b8: 10bfffcc andi r2,r2,65535 + 801c2bc: d8800015 stw r2,0(sp) + 801c2c0: 01c00044 movi r7,1 + 801c2c4: 01800344 movi r6,13 + 801c2c8: 000b883a mov r5,zero + 801c2cc: e13ffb17 ldw r4,-20(fp) + 801c2d0: 801996c0 call 801996c + + /* continue to next PHY */ + continue; + 801c2d4: 00007f06 br 801c4d4 + } + + /* set Auto-Negotiation advertisement based on common speed */ + if(common_speed == TSE_PHY_SPEED_1000) { + 801c2d8: e0bff317 ldw r2,-52(fp) + 801c2dc: 10800098 cmpnei r2,r2,2 + 801c2e0: 10000a1e bne r2,zero,801c30c + alt_tse_phy_set_adv_1000(pphy, 1); + 801c2e4: 01400044 movi r5,1 + 801c2e8: e13ffb17 ldw r4,-20(fp) + 801c2ec: 801b7f00 call 801b7f0 + alt_tse_phy_set_adv_100(pphy, 1); + 801c2f0: 01400044 movi r5,1 + 801c2f4: e13ffb17 ldw r4,-20(fp) + 801c2f8: 801b9b40 call 801b9b4 + alt_tse_phy_set_adv_10(pphy, 1); + 801c2fc: 01400044 movi r5,1 + 801c300: e13ffb17 ldw r4,-20(fp) + 801c304: 801bc080 call 801bc08 + 801c308: 00002206 br 801c394 + } + else if(common_speed == TSE_PHY_SPEED_100) { + 801c30c: e0bff317 ldw r2,-52(fp) + 801c310: 10800058 cmpnei r2,r2,1 + 801c314: 10000a1e bne r2,zero,801c340 + alt_tse_phy_set_adv_1000(pphy, 0); + 801c318: 000b883a mov r5,zero + 801c31c: e13ffb17 ldw r4,-20(fp) + 801c320: 801b7f00 call 801b7f0 + alt_tse_phy_set_adv_100(pphy, 1); + 801c324: 01400044 movi r5,1 + 801c328: e13ffb17 ldw r4,-20(fp) + 801c32c: 801b9b40 call 801b9b4 + alt_tse_phy_set_adv_10(pphy, 1); + 801c330: 01400044 movi r5,1 + 801c334: e13ffb17 ldw r4,-20(fp) + 801c338: 801bc080 call 801bc08 + 801c33c: 00001506 br 801c394 + } + else if(common_speed == TSE_PHY_SPEED_10) { + 801c340: e0bff317 ldw r2,-52(fp) + 801c344: 10000a1e bne r2,zero,801c370 + alt_tse_phy_set_adv_1000(pphy, 0); + 801c348: 000b883a mov r5,zero + 801c34c: e13ffb17 ldw r4,-20(fp) + 801c350: 801b7f00 call 801b7f0 + alt_tse_phy_set_adv_100(pphy, 0); + 801c354: 000b883a mov r5,zero + 801c358: e13ffb17 ldw r4,-20(fp) + 801c35c: 801b9b40 call 801b9b4 + alt_tse_phy_set_adv_10(pphy, 1); + 801c360: 01400044 movi r5,1 + 801c364: e13ffb17 ldw r4,-20(fp) + 801c368: 801bc080 call 801bc08 + 801c36c: 00000906 br 801c394 + } + else { + alt_tse_phy_set_adv_1000(pphy, 0); + 801c370: 000b883a mov r5,zero + 801c374: e13ffb17 ldw r4,-20(fp) + 801c378: 801b7f00 call 801b7f0 + alt_tse_phy_set_adv_100(pphy, 0); + 801c37c: 000b883a mov r5,zero + 801c380: e13ffb17 ldw r4,-20(fp) + 801c384: 801b9b40 call 801b9b4 + alt_tse_phy_set_adv_10(pphy, 0); + 801c388: 000b883a mov r5,zero + 801c38c: e13ffb17 ldw r4,-20(fp) + 801c390: 801bc080 call 801bc08 + } + + /* if PHY Auto-Negotiation is completed */ + if(alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_COMPLETE, 1) == 1) { + 801c394: 01c00044 movi r7,1 + 801c398: 01800144 movi r6,5 + 801c39c: 01400044 movi r5,1 + 801c3a0: e13ffb17 ldw r4,-20(fp) + 801c3a4: 8019a980 call 8019a98 + 801c3a8: 10800058 cmpnei r2,r2,1 + 801c3ac: 10003a1e bne r2,zero,801c498 + + /* read both msb and lsb of speed bits if PHY support 1000 Mbps */ + if(gb_capable) { + 801c3b0: e0bff5c3 ldbu r2,-41(fp) + 801c3b4: 10000f26 beq r2,zero,801c3f4 + + /* get speed information after Auto-Negotiation */ + speed = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->speed_lsb_location, 2); + 801c3b8: e0bffb17 ldw r2,-20(fp) + 801c3bc: 10800517 ldw r2,20(r2) + 801c3c0: 10801583 ldbu r2,86(r2) + 801c3c4: 10c03fcc andi r3,r2,255 + 801c3c8: e0bffb17 ldw r2,-20(fp) + 801c3cc: 10800517 ldw r2,20(r2) + 801c3d0: 108015c3 ldbu r2,87(r2) + 801c3d4: 10803fcc andi r2,r2,255 + 801c3d8: 01c00084 movi r7,2 + 801c3dc: 100d883a mov r6,r2 + 801c3e0: 180b883a mov r5,r3 + 801c3e4: e13ffb17 ldw r4,-20(fp) + 801c3e8: 8019a980 call 8019a98 + 801c3ec: e0bffdc5 stb r2,-9(fp) + 801c3f0: 00000e06 br 801c42c + } + + /* read lsb of speed only if PHY support only 10/100 Mbps */ + else { + /* get speed and link information after Auto-Negotiation */ + speed = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->speed_lsb_location, 1); + 801c3f4: e0bffb17 ldw r2,-20(fp) + 801c3f8: 10800517 ldw r2,20(r2) + 801c3fc: 10801583 ldbu r2,86(r2) + 801c400: 10c03fcc andi r3,r2,255 + 801c404: e0bffb17 ldw r2,-20(fp) + 801c408: 10800517 ldw r2,20(r2) + 801c40c: 108015c3 ldbu r2,87(r2) + 801c410: 10803fcc andi r2,r2,255 + 801c414: 01c00044 movi r7,1 + 801c418: 100d883a mov r6,r2 + 801c41c: 180b883a mov r5,r3 + 801c420: e13ffb17 ldw r4,-20(fp) + 801c424: 8019a980 call 8019a98 + 801c428: e0bffdc5 stb r2,-9(fp) + } + + /* if current speed != common speed, then restart Auto-Negotiation */ + if(speed != common_speed) { + 801c42c: e0bffdc3 ldbu r2,-9(fp) + 801c430: e0fff317 ldw r3,-52(fp) + 801c434: 18800326 beq r3,r2,801c444 + alt_tse_phy_restart_an(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD); + 801c438: 01427104 movi r5,2500 + 801c43c: e13ffb17 ldw r4,-20(fp) + 801c440: 801af180 call 801af18 + } + + /* get speed information after Auto-Negotiation */ + duplex = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->duplex_bit_location, 1); + 801c444: e0bffb17 ldw r2,-20(fp) + 801c448: 10800517 ldw r2,20(r2) + 801c44c: 10801583 ldbu r2,86(r2) + 801c450: 10c03fcc andi r3,r2,255 + 801c454: e0bffb17 ldw r2,-20(fp) + 801c458: 10800517 ldw r2,20(r2) + 801c45c: 10801603 ldbu r2,88(r2) + 801c460: 10803fcc andi r2,r2,255 + 801c464: 01c00044 movi r7,1 + 801c468: 100d883a mov r6,r2 + 801c46c: 180b883a mov r5,r3 + 801c470: e13ffb17 ldw r4,-20(fp) + 801c474: 8019a980 call 8019a98 + 801c478: e0bff585 stb r2,-42(fp) + + /* Set MAC duplex register */ + alt_tse_mac_set_duplex((np_tse_mac *)psys->tse_mac_base, duplex); + 801c47c: e0bff917 ldw r2,-28(fp) + 801c480: 10800017 ldw r2,0(r2) + 801c484: 1007883a mov r3,r2 + 801c488: e0bff583 ldbu r2,-42(fp) + 801c48c: 100b883a mov r5,r2 + 801c490: 1809883a mov r4,r3 + 801c494: 8018dc80 call 8018dc8 + + } + tse_dprintf(5, "INFO : PHY[%d.%d] - PHY STATUS = 0x%04x\n\n", mac_group_index, mac_info_index, (int) alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, 0, 16)); + 801c498: e43ff887 ldb r16,-30(fp) + 801c49c: e47ff8c7 ldb r17,-29(fp) + 801c4a0: 01c00404 movi r7,16 + 801c4a4: 000d883a mov r6,zero + 801c4a8: 01400044 movi r5,1 + 801c4ac: e13ffb17 ldw r4,-20(fp) + 801c4b0: 8019a980 call 8019a98 + 801c4b4: 100f883a mov r7,r2 + 801c4b8: 880d883a mov r6,r17 + 801c4bc: 800b883a mov r5,r16 + 801c4c0: 01020174 movhi r4,2053 + 801c4c4: 2124df04 addi r4,r4,-27780 + 801c4c8: 8002c780 call 8002c78 + 801c4cc: 00000106 br 801c4d4 + continue; + 801c4d0: 0001883a nop + for(i = 0; i < pmac_group->channel; i++) { + 801c4d4: e0bffc17 ldw r2,-16(fp) + 801c4d8: 10800044 addi r2,r2,1 + 801c4dc: e0bffc15 stw r2,-16(fp) + 801c4e0: e0bff417 ldw r2,-48(fp) + 801c4e4: 10800003 ldbu r2,0(r2) + 801c4e8: 10803fcc andi r2,r2,255 + 801c4ec: e0fffc17 ldw r3,-16(fp) + 801c4f0: 18bf2116 blt r3,r2,801c178 + } + tse_dprintf(5, "INFO : MAC Group[%d] - All PHYs set to common speed : %d Mbps\n", mac_group_index, (common_speed == TSE_PHY_SPEED_1000) ? 1000 : ((common_speed == TSE_PHY_SPEED_100) ? 100 : 10)); + 801c4f4: e0fff887 ldb r3,-30(fp) + 801c4f8: e0bff317 ldw r2,-52(fp) + 801c4fc: 108000a0 cmpeqi r2,r2,2 + 801c500: 1000071e bne r2,zero,801c520 + 801c504: e0bff317 ldw r2,-52(fp) + 801c508: 10800058 cmpnei r2,r2,1 + 801c50c: 1000021e bne r2,zero,801c518 + 801c510: 00801904 movi r2,100 + 801c514: 00000306 br 801c524 + 801c518: 00800284 movi r2,10 + 801c51c: 00000106 br 801c524 + 801c520: 0080fa04 movi r2,1000 + 801c524: 100d883a mov r6,r2 + 801c528: 180b883a mov r5,r3 + 801c52c: 01020174 movhi r4,2053 + 801c530: 2124eb04 addi r4,r4,-27732 + 801c534: 8002c780 call 8002c78 + + /* Set MAC speed register */ + alt_tse_mac_set_speed(pmac_group_base, common_speed); + 801c538: e0bff317 ldw r2,-52(fp) + 801c53c: 10803fcc andi r2,r2,255 + 801c540: 100b883a mov r5,r2 + 801c544: e13ff717 ldw r4,-36(fp) + 801c548: 8018ce80 call 8018ce8 + + /* Restore previous MDIO address */ + IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdioadd_prev); + 801c54c: e0bff717 ldw r2,-36(fp) + 801c550: 10801004 addi r2,r2,64 + 801c554: e0fff617 ldw r3,-40(fp) + 801c558: 10c00035 stwio r3,0(r2) + + return common_speed; + 801c55c: e0bff317 ldw r2,-52(fp) +} + 801c560: e6fffe04 addi sp,fp,-8 + 801c564: dfc00317 ldw ra,12(sp) + 801c568: df000217 ldw fp,8(sp) + 801c56c: dc400117 ldw r17,4(sp) + 801c570: dc000017 ldw r16,0(sp) + 801c574: dec00404 addi sp,sp,16 + 801c578: f800283a ret + +0801c57c : + +/* @Function Description: Additional configuration for Marvell PHY + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address of MAC group + */ +alt_32 marvell_phy_cfg(np_tse_mac *pmac) { + 801c57c: defffc04 addi sp,sp,-16 + 801c580: dfc00315 stw ra,12(sp) + 801c584: df000215 stw fp,8(sp) + 801c588: df000204 addi fp,sp,8 + 801c58c: e13ffe15 stw r4,-8(fp) + + alt_u16 dat; + + /* If there is no link yet, we enable auto crossover and reset the PHY */ + if((IORD(&pmac->mdio1.STATUS, 0) & PCS_ST_an_done) == 0) { + 801c590: e0bffe17 ldw r2,-8(fp) + 801c594: 1080a104 addi r2,r2,644 + 801c598: 10800037 ldwio r2,0(r2) + 801c59c: 1080080c andi r2,r2,32 + 801c5a0: 1000161e bne r2,zero,801c5fc + tse_dprintf(5, "MARVELL : Enabling auto crossover\n"); + 801c5a4: 01020174 movhi r4,2053 + 801c5a8: 2124fc04 addi r4,r4,-27664 + 801c5ac: 8002d9c0 call 8002d9c + IOWR(&pmac->mdio1.CONTROL, 16, 0x0078); + 801c5b0: e0bffe17 ldw r2,-8(fp) + 801c5b4: 1080a004 addi r2,r2,640 + 801c5b8: 10801004 addi r2,r2,64 + 801c5bc: 00c01e04 movi r3,120 + 801c5c0: 10c00035 stwio r3,0(r2) + tse_dprintf(5, "MARVELL : PHY reset\n"); + 801c5c4: 01020174 movhi r4,2053 + 801c5c8: 21250504 addi r4,r4,-27628 + 801c5cc: 8002d9c0 call 8002d9c + dat = IORD(&pmac->mdio1.CONTROL, 0); + 801c5d0: e0bffe17 ldw r2,-8(fp) + 801c5d4: 1080a004 addi r2,r2,640 + 801c5d8: 10800037 ldwio r2,0(r2) + 801c5dc: e0bfff8d sth r2,-2(fp) + IOWR(&pmac->mdio1.CONTROL, 0, dat | PCS_CTL_sw_reset); + 801c5e0: e0bffe17 ldw r2,-8(fp) + 801c5e4: 1080a004 addi r2,r2,640 + 801c5e8: e13fff8b ldhu r4,-2(fp) + 801c5ec: 00e00004 movi r3,-32768 + 801c5f0: 20c6b03a or r3,r4,r3 + 801c5f4: 18ffffcc andi r3,r3,65535 + 801c5f8: 10c00035 stwio r3,0(r2) + } + + return 0; + 801c5fc: 0005883a mov r2,zero +} + 801c600: e037883a mov sp,fp + 801c604: dfc00117 ldw ra,4(sp) + 801c608: df000017 ldw fp,0(sp) + 801c60c: dec00204 addi sp,sp,8 + 801c610: f800283a ret + +0801c614 : + +/* @Function Description: Change operating mode of Marvell PHY to GMII + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group + */ +alt_32 marvell_cfg_gmii(np_tse_mac *pmac) { + 801c614: defffc04 addi sp,sp,-16 + 801c618: dfc00315 stw ra,12(sp) + 801c61c: df000215 stw fp,8(sp) + 801c620: df000204 addi fp,sp,8 + 801c624: e13ffe15 stw r4,-8(fp) + + alt_u16 dat = IORD(&pmac->mdio1.reg1b, 0); + 801c628: e0bffe17 ldw r2,-8(fp) + 801c62c: 1080bb04 addi r2,r2,748 + 801c630: 10800037 ldwio r2,0(r2) + 801c634: e0bfff8d sth r2,-2(fp) + dat &= 0xfff0; + 801c638: e0ffff8b ldhu r3,-2(fp) + 801c63c: 00bffc04 movi r2,-16 + 801c640: 1884703a and r2,r3,r2 + 801c644: e0bfff8d sth r2,-2(fp) + + tse_dprintf(5, "MARVELL : Mode changed to GMII to copper mode\n"); + 801c648: 01020174 movhi r4,2053 + 801c64c: 21250a04 addi r4,r4,-27608 + 801c650: 8002d9c0 call 8002d9c + IOWR(&pmac->mdio1.reg1b, 0, dat | 0xf); + 801c654: e0bffe17 ldw r2,-8(fp) + 801c658: 1080bb04 addi r2,r2,748 + 801c65c: e0ffff8b ldhu r3,-2(fp) + 801c660: 18c003d4 ori r3,r3,15 + 801c664: 18ffffcc andi r3,r3,65535 + 801c668: 10c00035 stwio r3,0(r2) + + tse_dprintf(5, "MARVELL : Disable RGMII Timing Control\n"); + 801c66c: 01020174 movhi r4,2053 + 801c670: 21251604 addi r4,r4,-27560 + 801c674: 8002d9c0 call 8002d9c + dat = IORD(&pmac->mdio1.reg14, 0); + 801c678: e0bffe17 ldw r2,-8(fp) + 801c67c: 1080b404 addi r2,r2,720 + 801c680: 10800037 ldwio r2,0(r2) + 801c684: e0bfff8d sth r2,-2(fp) + dat &= ~0x82; + 801c688: e0ffff8b ldhu r3,-2(fp) + 801c68c: 00bfdf44 movi r2,-131 + 801c690: 1884703a and r2,r3,r2 + 801c694: e0bfff8d sth r2,-2(fp) + IOWR(&pmac->mdio1.reg14, 0, dat); + 801c698: e0bffe17 ldw r2,-8(fp) + 801c69c: 1080b404 addi r2,r2,720 + 801c6a0: e0ffff8b ldhu r3,-2(fp) + 801c6a4: 10c00035 stwio r3,0(r2) + + tse_dprintf(5, "MARVELL : PHY reset\n"); + 801c6a8: 01020174 movhi r4,2053 + 801c6ac: 21250504 addi r4,r4,-27628 + 801c6b0: 8002d9c0 call 8002d9c + dat = IORD(&pmac->mdio1.CONTROL, 0); + 801c6b4: e0bffe17 ldw r2,-8(fp) + 801c6b8: 1080a004 addi r2,r2,640 + 801c6bc: 10800037 ldwio r2,0(r2) + 801c6c0: e0bfff8d sth r2,-2(fp) + IOWR(&pmac->mdio1.CONTROL, 0, dat | PCS_CTL_sw_reset); + 801c6c4: e0bffe17 ldw r2,-8(fp) + 801c6c8: 1080a004 addi r2,r2,640 + 801c6cc: e13fff8b ldhu r4,-2(fp) + 801c6d0: 00e00004 movi r3,-32768 + 801c6d4: 20c6b03a or r3,r4,r3 + 801c6d8: 18ffffcc andi r3,r3,65535 + 801c6dc: 10c00035 stwio r3,0(r2) + + return 1; + 801c6e0: 00800044 movi r2,1 +} + 801c6e4: e037883a mov sp,fp + 801c6e8: dfc00117 ldw ra,4(sp) + 801c6ec: df000017 ldw fp,0(sp) + 801c6f0: dec00204 addi sp,sp,8 + 801c6f4: f800283a ret + +0801c6f8 : + +/* @Function Description: Change operating mode of Marvell PHY to SGMII + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group + */ +alt_32 marvell_cfg_sgmii(np_tse_mac *pmac) { + 801c6f8: defffc04 addi sp,sp,-16 + 801c6fc: dfc00315 stw ra,12(sp) + 801c700: df000215 stw fp,8(sp) + 801c704: df000204 addi fp,sp,8 + 801c708: e13ffe15 stw r4,-8(fp) + + alt_u16 dat = IORD(&pmac->mdio1.reg1b, 0); + 801c70c: e0bffe17 ldw r2,-8(fp) + 801c710: 1080bb04 addi r2,r2,748 + 801c714: 10800037 ldwio r2,0(r2) + 801c718: e0bfff8d sth r2,-2(fp) + dat &= 0xfff0; + 801c71c: e0ffff8b ldhu r3,-2(fp) + 801c720: 00bffc04 movi r2,-16 + 801c724: 1884703a and r2,r3,r2 + 801c728: e0bfff8d sth r2,-2(fp) + + tse_dprintf(5, "MARVELL : Mode changed to SGMII without clock with SGMII Auto-Neg to copper mode\n"); + 801c72c: 01020174 movhi r4,2053 + 801c730: 21252004 addi r4,r4,-27520 + 801c734: 8002d9c0 call 8002d9c + IOWR(&pmac->mdio1.reg1b, 0, dat | 0x4); + 801c738: e0bffe17 ldw r2,-8(fp) + 801c73c: 1080bb04 addi r2,r2,748 + 801c740: e0ffff8b ldhu r3,-2(fp) + 801c744: 18c00114 ori r3,r3,4 + 801c748: 18ffffcc andi r3,r3,65535 + 801c74c: 10c00035 stwio r3,0(r2) + + tse_dprintf(5, "MARVELL : Disable RGMII Timing Control\n"); + 801c750: 01020174 movhi r4,2053 + 801c754: 21251604 addi r4,r4,-27560 + 801c758: 8002d9c0 call 8002d9c + dat = IORD(&pmac->mdio1.reg14, 0); + 801c75c: e0bffe17 ldw r2,-8(fp) + 801c760: 1080b404 addi r2,r2,720 + 801c764: 10800037 ldwio r2,0(r2) + 801c768: e0bfff8d sth r2,-2(fp) + dat &= ~0x82; + 801c76c: e0ffff8b ldhu r3,-2(fp) + 801c770: 00bfdf44 movi r2,-131 + 801c774: 1884703a and r2,r3,r2 + 801c778: e0bfff8d sth r2,-2(fp) + IOWR(&pmac->mdio1.reg14, 0, dat); + 801c77c: e0bffe17 ldw r2,-8(fp) + 801c780: 1080b404 addi r2,r2,720 + 801c784: e0ffff8b ldhu r3,-2(fp) + 801c788: 10c00035 stwio r3,0(r2) + + tse_dprintf(5, "MARVELL : PHY reset\n"); + 801c78c: 01020174 movhi r4,2053 + 801c790: 21250504 addi r4,r4,-27628 + 801c794: 8002d9c0 call 8002d9c + dat = IORD(&pmac->mdio1.CONTROL, 0); + 801c798: e0bffe17 ldw r2,-8(fp) + 801c79c: 1080a004 addi r2,r2,640 + 801c7a0: 10800037 ldwio r2,0(r2) + 801c7a4: e0bfff8d sth r2,-2(fp) + IOWR(&pmac->mdio1.CONTROL, 0, dat | PCS_CTL_sw_reset); + 801c7a8: e0bffe17 ldw r2,-8(fp) + 801c7ac: 1080a004 addi r2,r2,640 + 801c7b0: e13fff8b ldhu r4,-2(fp) + 801c7b4: 00e00004 movi r3,-32768 + 801c7b8: 20c6b03a or r3,r4,r3 + 801c7bc: 18ffffcc andi r3,r3,65535 + 801c7c0: 10c00035 stwio r3,0(r2) + + return 1; + 801c7c4: 00800044 movi r2,1 +} + 801c7c8: e037883a mov sp,fp + 801c7cc: dfc00117 ldw ra,4(sp) + 801c7d0: df000017 ldw fp,0(sp) + 801c7d4: dec00204 addi sp,sp,8 + 801c7d8: f800283a ret + +0801c7dc : + +/* @Function Description: Change operating mode of Marvell PHY to RGMII + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group + */ +alt_32 marvell_cfg_rgmii(np_tse_mac *pmac) { + 801c7dc: defffc04 addi sp,sp,-16 + 801c7e0: dfc00315 stw ra,12(sp) + 801c7e4: df000215 stw fp,8(sp) + 801c7e8: df000204 addi fp,sp,8 + 801c7ec: e13ffe15 stw r4,-8(fp) + + + alt_u16 dat = IORD(&pmac->mdio1.reg1b, 0); + 801c7f0: e0bffe17 ldw r2,-8(fp) + 801c7f4: 1080bb04 addi r2,r2,748 + 801c7f8: 10800037 ldwio r2,0(r2) + 801c7fc: e0bfff8d sth r2,-2(fp) + dat &= 0xfff0; + 801c800: e0ffff8b ldhu r3,-2(fp) + 801c804: 00bffc04 movi r2,-16 + 801c808: 1884703a and r2,r3,r2 + 801c80c: e0bfff8d sth r2,-2(fp) + + tse_dprintf(5, "MARVELL : Mode changed to RGMII/Modified MII to Copper mode\n"); + 801c810: 01020174 movhi r4,2053 + 801c814: 21253504 addi r4,r4,-27436 + 801c818: 8002d9c0 call 8002d9c + IOWR(&pmac->mdio1.reg1b, 0, dat | 0xb); + 801c81c: e0bffe17 ldw r2,-8(fp) + 801c820: 1080bb04 addi r2,r2,748 + 801c824: e0ffff8b ldhu r3,-2(fp) + 801c828: 18c002d4 ori r3,r3,11 + 801c82c: 18ffffcc andi r3,r3,65535 + 801c830: 10c00035 stwio r3,0(r2) + + tse_dprintf(5, "MARVELL : Enable RGMII Timing Control\n"); + 801c834: 01020174 movhi r4,2053 + 801c838: 21254404 addi r4,r4,-27376 + 801c83c: 8002d9c0 call 8002d9c + dat = IORD(&pmac->mdio1.reg14, 0); + 801c840: e0bffe17 ldw r2,-8(fp) + 801c844: 1080b404 addi r2,r2,720 + 801c848: 10800037 ldwio r2,0(r2) + 801c84c: e0bfff8d sth r2,-2(fp) + dat &= ~0x82; + 801c850: e0ffff8b ldhu r3,-2(fp) + 801c854: 00bfdf44 movi r2,-131 + 801c858: 1884703a and r2,r3,r2 + 801c85c: e0bfff8d sth r2,-2(fp) + dat |= 0x82; + 801c860: e0bfff8b ldhu r2,-2(fp) + 801c864: 10802094 ori r2,r2,130 + 801c868: e0bfff8d sth r2,-2(fp) + IOWR(&pmac->mdio1.reg14, 0, dat); + 801c86c: e0bffe17 ldw r2,-8(fp) + 801c870: 1080b404 addi r2,r2,720 + 801c874: e0ffff8b ldhu r3,-2(fp) + 801c878: 10c00035 stwio r3,0(r2) + + tse_dprintf(5, "MARVELL : PHY reset\n"); + 801c87c: 01020174 movhi r4,2053 + 801c880: 21250504 addi r4,r4,-27628 + 801c884: 8002d9c0 call 8002d9c + dat = IORD(&pmac->mdio1.CONTROL, 0); + 801c888: e0bffe17 ldw r2,-8(fp) + 801c88c: 1080a004 addi r2,r2,640 + 801c890: 10800037 ldwio r2,0(r2) + 801c894: e0bfff8d sth r2,-2(fp) + IOWR(&pmac->mdio1.CONTROL, 0, dat | PCS_CTL_sw_reset); + 801c898: e0bffe17 ldw r2,-8(fp) + 801c89c: 1080a004 addi r2,r2,640 + 801c8a0: e13fff8b ldhu r4,-2(fp) + 801c8a4: 00e00004 movi r3,-32768 + 801c8a8: 20c6b03a or r3,r4,r3 + 801c8ac: 18ffffcc andi r3,r3,65535 + 801c8b0: 10c00035 stwio r3,0(r2) + + return 1; + 801c8b4: 00800044 movi r2,1 + +} + 801c8b8: e037883a mov sp,fp + 801c8bc: dfc00117 ldw ra,4(sp) + 801c8c0: df000017 ldw fp,0(sp) + 801c8c4: dec00204 addi sp,sp,8 + 801c8c8: f800283a ret + +0801c8cc : + +/* @Function Description: Read link status from PHY specific status register of DP83848C + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group + */ +alt_u32 DP83848C_link_status_read(np_tse_mac *pmac) { + 801c8cc: defffc04 addi sp,sp,-16 + 801c8d0: df000315 stw fp,12(sp) + 801c8d4: df000304 addi fp,sp,12 + 801c8d8: e13ffd15 stw r4,-12(fp) + alt_u32 link_status = 0; + 801c8dc: e03fff15 stw zero,-4(fp) + alt_u32 reg_status = IORD(&pmac->mdio1.reg10, 0); + 801c8e0: e0bffd17 ldw r2,-12(fp) + 801c8e4: 1080b004 addi r2,r2,704 + 801c8e8: 10800037 ldwio r2,0(r2) + 801c8ec: e0bffe15 stw r2,-8(fp) + + /* If speed == 10 Mbps */ + if(reg_status & 0x2) { + 801c8f0: e0bffe17 ldw r2,-8(fp) + 801c8f4: 1080008c andi r2,r2,2 + 801c8f8: 10000426 beq r2,zero,801c90c + link_status |= 0x8; + 801c8fc: e0bfff17 ldw r2,-4(fp) + 801c900: 10800214 ori r2,r2,8 + 801c904: e0bfff15 stw r2,-4(fp) + 801c908: 00000306 br 801c918 + } + /* Else speed = 100 Mbps */ + else { + link_status |= 0x4; + 801c90c: e0bfff17 ldw r2,-4(fp) + 801c910: 10800114 ori r2,r2,4 + 801c914: e0bfff15 stw r2,-4(fp) + } + + /* If duplex == Full */ + if(reg_status & 0x4) { + 801c918: e0bffe17 ldw r2,-8(fp) + 801c91c: 1080010c andi r2,r2,4 + 801c920: 10000326 beq r2,zero,801c930 + link_status |= 0x1; + 801c924: e0bfff17 ldw r2,-4(fp) + 801c928: 10800054 ori r2,r2,1 + 801c92c: e0bfff15 stw r2,-4(fp) + } + + return link_status; + 801c930: e0bfff17 ldw r2,-4(fp) +} + 801c934: e037883a mov sp,fp + 801c938: df000017 ldw fp,0(sp) + 801c93c: dec00104 addi sp,sp,4 + 801c940: f800283a ret + +0801c944 : +/* @Function Description: Additional configuration for PEF7071 Phy + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group + */ +alt_32 PEF7071_config(np_tse_mac *pmac) +{ + 801c944: defffd04 addi sp,sp,-12 + 801c948: df000215 stw fp,8(sp) + 801c94c: df000204 addi fp,sp,8 + 801c950: e13ffe15 stw r4,-8(fp) + alt_u16 dat; + + dat = IORD(&pmac->mdio1.reg14, 0); + 801c954: e0bffe17 ldw r2,-8(fp) + 801c958: 1080b404 addi r2,r2,720 + 801c95c: 10800037 ldwio r2,0(r2) + 801c960: e0bfff8d sth r2,-2(fp) + dat &= 0x3FFF; + 801c964: e0bfff8b ldhu r2,-2(fp) + 801c968: 108fffcc andi r2,r2,16383 + 801c96c: e0bfff8d sth r2,-2(fp) + dat |= 0x0100; + 801c970: e0bfff8b ldhu r2,-2(fp) + 801c974: 10804014 ori r2,r2,256 + 801c978: e0bfff8d sth r2,-2(fp) + IOWR(&pmac->mdio1.reg14, 0, dat); + 801c97c: e0bffe17 ldw r2,-8(fp) + 801c980: 1080b404 addi r2,r2,720 + 801c984: e0ffff8b ldhu r3,-2(fp) + 801c988: 10c00035 stwio r3,0(r2) + + return 0; + 801c98c: 0005883a mov r2,zero + +} + 801c990: e037883a mov sp,fp + 801c994: df000017 ldw fp,0(sp) + 801c998: dec00104 addi sp,sp,4 + 801c99c: f800283a ret + +0801c9a0 : +/* @Function Description: Read link status from PHY specific status register of PEF7071 + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group + */ +alt_u32 PEF7071_link_status_read(np_tse_mac *pmac) +{ + 801c9a0: defffc04 addi sp,sp,-16 + 801c9a4: df000315 stw fp,12(sp) + 801c9a8: df000304 addi fp,sp,12 + 801c9ac: e13ffd15 stw r4,-12(fp) + alt_u32 link_status = 0; + 801c9b0: e03fff15 stw zero,-4(fp) + alt_u32 reg18 = IORD(&pmac->mdio1.reg18, 0); + 801c9b4: e0bffd17 ldw r2,-12(fp) + 801c9b8: 1080b804 addi r2,r2,736 + 801c9bc: 10800037 ldwio r2,0(r2) + 801c9c0: e0bffe15 stw r2,-8(fp) + + if ((reg18 & 0x3)==0) { link_status |= 0x8; } /* If speed == 10 Mbps */ + 801c9c4: e0bffe17 ldw r2,-8(fp) + 801c9c8: 108000cc andi r2,r2,3 + 801c9cc: 1000031e bne r2,zero,801c9dc + 801c9d0: e0bfff17 ldw r2,-4(fp) + 801c9d4: 10800214 ori r2,r2,8 + 801c9d8: e0bfff15 stw r2,-4(fp) + if ((reg18 & 0x3)==1) { link_status |= 0x4; } /* Else speed = 100 Mbps */ + 801c9dc: e0bffe17 ldw r2,-8(fp) + 801c9e0: 108000cc andi r2,r2,3 + 801c9e4: 10800058 cmpnei r2,r2,1 + 801c9e8: 1000031e bne r2,zero,801c9f8 + 801c9ec: e0bfff17 ldw r2,-4(fp) + 801c9f0: 10800114 ori r2,r2,4 + 801c9f4: e0bfff15 stw r2,-4(fp) + if ((reg18 & 0x3)==2) { link_status |= 0x2; } /* Else speed = 1000 Mbps */ + 801c9f8: e0bffe17 ldw r2,-8(fp) + 801c9fc: 108000cc andi r2,r2,3 + 801ca00: 10800098 cmpnei r2,r2,2 + 801ca04: 1000031e bne r2,zero,801ca14 + 801ca08: e0bfff17 ldw r2,-4(fp) + 801ca0c: 10800094 ori r2,r2,2 + 801ca10: e0bfff15 stw r2,-4(fp) + + /* If duplex == Full */ + if(reg18 & 0x8) { + 801ca14: e0bffe17 ldw r2,-8(fp) + 801ca18: 1080020c andi r2,r2,8 + 801ca1c: 10000326 beq r2,zero,801ca2c + link_status |= 0x1; + 801ca20: e0bfff17 ldw r2,-4(fp) + 801ca24: 10800054 ori r2,r2,1 + 801ca28: e0bfff15 stw r2,-4(fp) + } + + return link_status; + 801ca2c: e0bfff17 ldw r2,-4(fp) +} + 801ca30: e037883a mov sp,fp + 801ca34: df000017 ldw fp,0(sp) + 801ca38: dec00104 addi sp,sp,4 + 801ca3c: f800283a ret + +0801ca40 : + * + */ + +int +altera_avalon_uart_read_fd(alt_fd* fd, char* buffer, int space) +{ + 801ca40: defffa04 addi sp,sp,-24 + 801ca44: dfc00515 stw ra,20(sp) + 801ca48: df000415 stw fp,16(sp) + 801ca4c: df000404 addi fp,sp,16 + 801ca50: e13ffe15 stw r4,-8(fp) + 801ca54: e17ffd15 stw r5,-12(fp) + 801ca58: e1bffc15 stw r6,-16(fp) + altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; + 801ca5c: e0bffe17 ldw r2,-8(fp) + 801ca60: 10800017 ldw r2,0(r2) + 801ca64: e0bfff15 stw r2,-4(fp) + + return altera_avalon_uart_read(&dev->state, buffer, space, + 801ca68: e0bfff17 ldw r2,-4(fp) + 801ca6c: 10c00a04 addi r3,r2,40 + 801ca70: e0bffe17 ldw r2,-8(fp) + 801ca74: 10800217 ldw r2,8(r2) + 801ca78: 100f883a mov r7,r2 + 801ca7c: e1bffc17 ldw r6,-16(fp) + 801ca80: e17ffd17 ldw r5,-12(fp) + 801ca84: 1809883a mov r4,r3 + 801ca88: 801d0b00 call 801d0b0 + fd->fd_flags); +} + 801ca8c: e037883a mov sp,fp + 801ca90: dfc00117 ldw ra,4(sp) + 801ca94: df000017 ldw fp,0(sp) + 801ca98: dec00204 addi sp,sp,8 + 801ca9c: f800283a ret + +0801caa0 : + +int +altera_avalon_uart_write_fd(alt_fd* fd, const char* buffer, int space) +{ + 801caa0: defffa04 addi sp,sp,-24 + 801caa4: dfc00515 stw ra,20(sp) + 801caa8: df000415 stw fp,16(sp) + 801caac: df000404 addi fp,sp,16 + 801cab0: e13ffe15 stw r4,-8(fp) + 801cab4: e17ffd15 stw r5,-12(fp) + 801cab8: e1bffc15 stw r6,-16(fp) + altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; + 801cabc: e0bffe17 ldw r2,-8(fp) + 801cac0: 10800017 ldw r2,0(r2) + 801cac4: e0bfff15 stw r2,-4(fp) + + return altera_avalon_uart_write(&dev->state, buffer, space, + 801cac8: e0bfff17 ldw r2,-4(fp) + 801cacc: 10c00a04 addi r3,r2,40 + 801cad0: e0bffe17 ldw r2,-8(fp) + 801cad4: 10800217 ldw r2,8(r2) + 801cad8: 100f883a mov r7,r2 + 801cadc: e1bffc17 ldw r6,-16(fp) + 801cae0: e17ffd17 ldw r5,-12(fp) + 801cae4: 1809883a mov r4,r3 + 801cae8: 801d3540 call 801d354 + fd->fd_flags); +} + 801caec: e037883a mov sp,fp + 801caf0: dfc00117 ldw ra,4(sp) + 801caf4: df000017 ldw fp,0(sp) + 801caf8: dec00204 addi sp,sp,8 + 801cafc: f800283a ret + +0801cb00 : + +#endif /* ALTERA_AVALON_UART_USE_IOCTL */ + +int +altera_avalon_uart_close_fd(alt_fd* fd) +{ + 801cb00: defffc04 addi sp,sp,-16 + 801cb04: dfc00315 stw ra,12(sp) + 801cb08: df000215 stw fp,8(sp) + 801cb0c: df000204 addi fp,sp,8 + 801cb10: e13ffe15 stw r4,-8(fp) + altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; + 801cb14: e0bffe17 ldw r2,-8(fp) + 801cb18: 10800017 ldw r2,0(r2) + 801cb1c: e0bfff15 stw r2,-4(fp) + + return altera_avalon_uart_close(&dev->state, fd->fd_flags); + 801cb20: e0bfff17 ldw r2,-4(fp) + 801cb24: 10c00a04 addi r3,r2,40 + 801cb28: e0bffe17 ldw r2,-8(fp) + 801cb2c: 10800217 ldw r2,8(r2) + 801cb30: 100b883a mov r5,r2 + 801cb34: 1809883a mov r4,r3 + 801cb38: 801d0200 call 801d020 +} + 801cb3c: e037883a mov sp,fp + 801cb40: dfc00117 ldw ra,4(sp) + 801cb44: df000017 ldw fp,0(sp) + 801cb48: dec00204 addi sp,sp,8 + 801cb4c: f800283a ret + +0801cb50 : + alt_u32 status); + +void +altera_avalon_uart_init(altera_avalon_uart_state* sp, + alt_u32 irq_controller_id, alt_u32 irq) +{ + 801cb50: defff204 addi sp,sp,-56 + 801cb54: dfc00d15 stw ra,52(sp) + 801cb58: df000c15 stw fp,48(sp) + 801cb5c: df000c04 addi fp,sp,48 + 801cb60: e13ff715 stw r4,-36(fp) + 801cb64: e17ff615 stw r5,-40(fp) + 801cb68: e1bff515 stw r6,-44(fp) + void* base = sp->base; + 801cb6c: e0bff717 ldw r2,-36(fp) + 801cb70: 10800017 ldw r2,0(r2) + 801cb74: e0bfff15 stw r2,-4(fp) + /* + * Initialise the read and write flags and the semaphores used to + * protect access to the circular buffers when running in a multi-threaded + * environment. + */ + error = ALT_FLAG_CREATE (&sp->events, 0) || + 801cb78: e0bff717 ldw r2,-36(fp) + 801cb7c: 10800704 addi r2,r2,28 + 801cb80: e0bffd15 stw r2,-12(fp) + 801cb84: e03ffc8d sth zero,-14(fp) + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_flag_create (OS_FLAG_GRP** pgroup, + OS_FLAGS flags) +{ + INT8U err; + *pgroup = OSFlagCreate (flags, &err); + 801cb88: e0bffc8b ldhu r2,-14(fp) + 801cb8c: e0fff844 addi r3,fp,-31 + 801cb90: 180b883a mov r5,r3 + 801cb94: 1009883a mov r4,r2 + 801cb98: 8011e780 call 8011e78 + 801cb9c: 1007883a mov r3,r2 + 801cba0: e0bffd17 ldw r2,-12(fp) + 801cba4: 10c00015 stw r3,0(r2) + return err; + 801cba8: e0bff843 ldbu r2,-31(fp) + 801cbac: 10803fcc andi r2,r2,255 + ALT_SEM_CREATE (&sp->read_lock, 1) || + 801cbb0: 1000241e bne r2,zero,801cc44 + 801cbb4: e0bff717 ldw r2,-36(fp) + 801cbb8: 10800804 addi r2,r2,32 + 801cbbc: e0bffb15 stw r2,-20(fp) + 801cbc0: 00800044 movi r2,1 + 801cbc4: e0bffa8d sth r2,-22(fp) + 801cbc8: e0bffa8b ldhu r2,-22(fp) + 801cbcc: 1009883a mov r4,r2 + 801cbd0: 80157740 call 8015774 + 801cbd4: 1007883a mov r3,r2 + 801cbd8: e0bffb17 ldw r2,-20(fp) + 801cbdc: 10c00015 stw r3,0(r2) + return *sem ? 0 : -1; + 801cbe0: e0bffb17 ldw r2,-20(fp) + 801cbe4: 10800017 ldw r2,0(r2) + 801cbe8: 10000226 beq r2,zero,801cbf4 + 801cbec: 0005883a mov r2,zero + 801cbf0: 00000106 br 801cbf8 + 801cbf4: 00bfffc4 movi r2,-1 + error = ALT_FLAG_CREATE (&sp->events, 0) || + 801cbf8: 1000121e bne r2,zero,801cc44 + ALT_SEM_CREATE (&sp->write_lock, 1); + 801cbfc: e0bff717 ldw r2,-36(fp) + 801cc00: 10800904 addi r2,r2,36 + 801cc04: e0bff915 stw r2,-28(fp) + 801cc08: 00800044 movi r2,1 + 801cc0c: e0bff88d sth r2,-30(fp) + *sem = OSSemCreate (value); + 801cc10: e0bff88b ldhu r2,-30(fp) + 801cc14: 1009883a mov r4,r2 + 801cc18: 80157740 call 8015774 + 801cc1c: 1007883a mov r3,r2 + 801cc20: e0bff917 ldw r2,-28(fp) + 801cc24: 10c00015 stw r3,0(r2) + return *sem ? 0 : -1; + 801cc28: e0bff917 ldw r2,-28(fp) + 801cc2c: 10800017 ldw r2,0(r2) + 801cc30: 10000226 beq r2,zero,801cc3c + 801cc34: 0005883a mov r2,zero + 801cc38: 00000106 br 801cc40 + 801cc3c: 00bfffc4 movi r2,-1 + ALT_SEM_CREATE (&sp->read_lock, 1) || + 801cc40: 10000226 beq r2,zero,801cc4c + 801cc44: 00800044 movi r2,1 + 801cc48: 00000106 br 801cc50 + 801cc4c: 0005883a mov r2,zero + error = ALT_FLAG_CREATE (&sp->events, 0) || + 801cc50: e0bffe15 stw r2,-8(fp) + + if (!error) + 801cc54: e0bffe17 ldw r2,-8(fp) + 801cc58: 10000f1e bne r2,zero,801cc98 + { + /* enable interrupts at the device */ + sp->ctrl = ALTERA_AVALON_UART_CONTROL_RTS_MSK | + 801cc5c: e0bff717 ldw r2,-36(fp) + 801cc60: 00c32004 movi r3,3200 + 801cc64: 10c00115 stw r3,4(r2) + ALTERA_AVALON_UART_CONTROL_RRDY_MSK | + ALTERA_AVALON_UART_CONTROL_DCTS_MSK; + + IOWR_ALTERA_AVALON_UART_CONTROL(base, sp->ctrl); + 801cc68: e0bfff17 ldw r2,-4(fp) + 801cc6c: 10800304 addi r2,r2,12 + 801cc70: e0fff717 ldw r3,-36(fp) + 801cc74: 18c00117 ldw r3,4(r3) + 801cc78: 10c00035 stwio r3,0(r2) + + /* register the interrupt handler */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_ic_isr_register(irq_controller_id, irq, altera_avalon_uart_irq, sp, + 801cc7c: d8000015 stw zero,0(sp) + 801cc80: e1fff717 ldw r7,-36(fp) + 801cc84: 018200b4 movhi r6,2050 + 801cc88: 31b32c04 addi r6,r6,-13136 + 801cc8c: e17ff517 ldw r5,-44(fp) + 801cc90: e13ff617 ldw r4,-40(fp) + 801cc94: 80374940 call 8037494 + 0x0); +#else + alt_irq_register (irq, sp, altera_avalon_uart_irq); +#endif + } +} + 801cc98: 0001883a nop + 801cc9c: e037883a mov sp,fp + 801cca0: dfc00117 ldw ra,4(sp) + 801cca4: df000017 ldw fp,0(sp) + 801cca8: dec00204 addi sp,sp,8 + 801ccac: f800283a ret + +0801ccb0 : +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void altera_avalon_uart_irq(void* context) +#else +static void altera_avalon_uart_irq(void* context, alt_u32 id) +#endif +{ + 801ccb0: defffa04 addi sp,sp,-24 + 801ccb4: dfc00515 stw ra,20(sp) + 801ccb8: df000415 stw fp,16(sp) + 801ccbc: df000404 addi fp,sp,16 + 801ccc0: e13ffc15 stw r4,-16(fp) + alt_u32 status; + + altera_avalon_uart_state* sp = (altera_avalon_uart_state*) context; + 801ccc4: e0bffc17 ldw r2,-16(fp) + 801ccc8: e0bfff15 stw r2,-4(fp) + void* base = sp->base; + 801cccc: e0bfff17 ldw r2,-4(fp) + 801ccd0: 10800017 ldw r2,0(r2) + 801ccd4: e0bffe15 stw r2,-8(fp) + /* + * Read the status register in order to determine the cause of the + * interrupt. + */ + + status = IORD_ALTERA_AVALON_UART_STATUS(base); + 801ccd8: e0bffe17 ldw r2,-8(fp) + 801ccdc: 10800204 addi r2,r2,8 + 801cce0: 10800037 ldwio r2,0(r2) + 801cce4: e0bffd15 stw r2,-12(fp) + + /* Clear any error flags set at the device */ + IOWR_ALTERA_AVALON_UART_STATUS(base, 0); + 801cce8: e0bffe17 ldw r2,-8(fp) + 801ccec: 10800204 addi r2,r2,8 + 801ccf0: 0007883a mov r3,zero + 801ccf4: 10c00035 stwio r3,0(r2) + + /* Dummy read to ensure IRQ is negated before ISR returns */ + IORD_ALTERA_AVALON_UART_STATUS(base); + 801ccf8: e0bffe17 ldw r2,-8(fp) + 801ccfc: 10800204 addi r2,r2,8 + 801cd00: 10800037 ldwio r2,0(r2) + + /* process a read irq */ + if (status & ALTERA_AVALON_UART_STATUS_RRDY_MSK) + 801cd04: e0bffd17 ldw r2,-12(fp) + 801cd08: 1080200c andi r2,r2,128 + 801cd0c: 10000326 beq r2,zero,801cd1c + { + altera_avalon_uart_rxirq(sp, status); + 801cd10: e17ffd17 ldw r5,-12(fp) + 801cd14: e13fff17 ldw r4,-4(fp) + 801cd18: 801cd4c0 call 801cd4c + } + + /* process a write irq */ + if (status & (ALTERA_AVALON_UART_STATUS_TRDY_MSK | + 801cd1c: e0bffd17 ldw r2,-12(fp) + 801cd20: 1081100c andi r2,r2,1088 + 801cd24: 10000326 beq r2,zero,801cd34 + ALTERA_AVALON_UART_STATUS_DCTS_MSK)) + { + altera_avalon_uart_txirq(sp, status); + 801cd28: e17ffd17 ldw r5,-12(fp) + 801cd2c: e13fff17 ldw r4,-4(fp) + 801cd30: 801ce800 call 801ce80 + } + + +} + 801cd34: 0001883a nop + 801cd38: e037883a mov sp,fp + 801cd3c: dfc00117 ldw ra,4(sp) + 801cd40: df000017 ldw fp,0(sp) + 801cd44: dec00204 addi sp,sp,8 + 801cd48: f800283a ret + +0801cd4c : + * the receive circular buffer, and sets the apropriate flags to indicate + * that there is data ready to be processed. + */ +static void +altera_avalon_uart_rxirq(altera_avalon_uart_state* sp, alt_u32 status) +{ + 801cd4c: defff904 addi sp,sp,-28 + 801cd50: dfc00615 stw ra,24(sp) + 801cd54: df000515 stw fp,20(sp) + 801cd58: df000504 addi fp,sp,20 + 801cd5c: e13ffc15 stw r4,-16(fp) + 801cd60: e17ffb15 stw r5,-20(fp) + alt_u32 next; + + /* If there was an error, discard the data */ + + if (status & (ALTERA_AVALON_UART_STATUS_PE_MSK | + 801cd64: e0bffb17 ldw r2,-20(fp) + 801cd68: 108000cc andi r2,r2,3 + 801cd6c: 10003e1e bne r2,zero,801ce68 + * In a multi-threaded environment, set the read event flag to indicate + * that there is data ready. This is only done if the circular buffer was + * previously empty. + */ + + if (sp->rx_end == sp->rx_start) + 801cd70: e0bffc17 ldw r2,-16(fp) + 801cd74: 10c00317 ldw r3,12(r2) + 801cd78: e0bffc17 ldw r2,-16(fp) + 801cd7c: 10800217 ldw r2,8(r2) + 801cd80: 1880121e bne r3,r2,801cdcc + { + ALT_FLAG_POST (sp->events, ALT_UART_READ_RDY, OS_FLAG_SET); + 801cd84: e0bffc17 ldw r2,-16(fp) + 801cd88: 10800717 ldw r2,28(r2) + 801cd8c: e0bffe15 stw r2,-8(fp) + 801cd90: 00800044 movi r2,1 + 801cd94: e0bffd8d sth r2,-10(fp) + 801cd98: 00800044 movi r2,1 + 801cd9c: e0bffd45 stb r2,-11(fp) + OS_FLAGS flags, + INT8U opt) +{ + INT8U err; + + if (OSRunning) + 801cda0: d0a04b43 ldbu r2,-32467(gp) + 801cda4: 10803fcc andi r2,r2,255 + 801cda8: 10000826 beq r2,zero,801cdcc + { + OSFlagPost (group, flags, opt, &err); + 801cdac: e0bffd8b ldhu r2,-10(fp) + 801cdb0: e0fffd43 ldbu r3,-11(fp) + 801cdb4: e13ffd04 addi r4,fp,-12 + 801cdb8: 200f883a mov r7,r4 + 801cdbc: 180d883a mov r6,r3 + 801cdc0: 100b883a mov r5,r2 + 801cdc4: e13ffe17 ldw r4,-8(fp) + 801cdc8: 80129700 call 8012970 + } + + /* Determine which slot to use next in the circular buffer */ + + next = (sp->rx_end + 1) & ALT_AVALON_UART_BUF_MSK; + 801cdcc: e0bffc17 ldw r2,-16(fp) + 801cdd0: 10800317 ldw r2,12(r2) + 801cdd4: 10800044 addi r2,r2,1 + 801cdd8: 10800fcc andi r2,r2,63 + 801cddc: e0bfff15 stw r2,-4(fp) + + /* Transfer data from the device to the circular buffer */ + + sp->rx_buf[sp->rx_end] = IORD_ALTERA_AVALON_UART_RXDATA(sp->base); + 801cde0: e0bffc17 ldw r2,-16(fp) + 801cde4: 10800017 ldw r2,0(r2) + 801cde8: 10c00037 ldwio r3,0(r2) + 801cdec: e0bffc17 ldw r2,-16(fp) + 801cdf0: 10800317 ldw r2,12(r2) + 801cdf4: 1809883a mov r4,r3 + 801cdf8: e0fffc17 ldw r3,-16(fp) + 801cdfc: 1885883a add r2,r3,r2 + 801ce00: 11000a05 stb r4,40(r2) + + sp->rx_end = next; + 801ce04: e0bffc17 ldw r2,-16(fp) + 801ce08: e0ffff17 ldw r3,-4(fp) + 801ce0c: 10c00315 stw r3,12(r2) + + next = (sp->rx_end + 1) & ALT_AVALON_UART_BUF_MSK; + 801ce10: e0bffc17 ldw r2,-16(fp) + 801ce14: 10800317 ldw r2,12(r2) + 801ce18: 10800044 addi r2,r2,1 + 801ce1c: 10800fcc andi r2,r2,63 + 801ce20: e0bfff15 stw r2,-4(fp) + /* + * If the cicular buffer was full, disable interrupts. Interrupts will be + * re-enabled when data is removed from the buffer. + */ + + if (next == sp->rx_start) + 801ce24: e0bffc17 ldw r2,-16(fp) + 801ce28: 10800217 ldw r2,8(r2) + 801ce2c: e0ffff17 ldw r3,-4(fp) + 801ce30: 18800e1e bne r3,r2,801ce6c + { + sp->ctrl &= ~ALTERA_AVALON_UART_CONTROL_RRDY_MSK; + 801ce34: e0bffc17 ldw r2,-16(fp) + 801ce38: 10c00117 ldw r3,4(r2) + 801ce3c: 00bfdfc4 movi r2,-129 + 801ce40: 1886703a and r3,r3,r2 + 801ce44: e0bffc17 ldw r2,-16(fp) + 801ce48: 10c00115 stw r3,4(r2) + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + 801ce4c: e0bffc17 ldw r2,-16(fp) + 801ce50: 10800017 ldw r2,0(r2) + 801ce54: 10800304 addi r2,r2,12 + 801ce58: e0fffc17 ldw r3,-16(fp) + 801ce5c: 18c00117 ldw r3,4(r3) + 801ce60: 10c00035 stwio r3,0(r2) + 801ce64: 00000106 br 801ce6c + return; + 801ce68: 0001883a nop + } +} + 801ce6c: e037883a mov sp,fp + 801ce70: dfc00117 ldw ra,4(sp) + 801ce74: df000017 ldw fp,0(sp) + 801ce78: dec00204 addi sp,sp,8 + 801ce7c: f800283a ret + +0801ce80 : + * buffer to the device, and sets the apropriate flags to indicate that + * there is data ready to be processed. + */ +static void +altera_avalon_uart_txirq(altera_avalon_uart_state* sp, alt_u32 status) +{ + 801ce80: defffa04 addi sp,sp,-24 + 801ce84: dfc00515 stw ra,20(sp) + 801ce88: df000415 stw fp,16(sp) + 801ce8c: df000404 addi fp,sp,16 + 801ce90: e13ffd15 stw r4,-12(fp) + 801ce94: e17ffc15 stw r5,-16(fp) + /* Transfer data if there is some ready to be transfered */ + + if (sp->tx_start != sp->tx_end) + 801ce98: e0bffd17 ldw r2,-12(fp) + 801ce9c: 10c00417 ldw r3,16(r2) + 801cea0: e0bffd17 ldw r2,-12(fp) + 801cea4: 10800517 ldw r2,20(r2) + 801cea8: 18804626 beq r3,r2,801cfc4 + /* + * If the device is using flow control (i.e. RTS/CTS), then the + * transmitter is required to throttle if CTS is high. + */ + + if (!(sp->flags & ALT_AVALON_UART_FC) || + 801ceac: e0bffd17 ldw r2,-12(fp) + 801ceb0: 10800617 ldw r2,24(r2) + 801ceb4: 1080008c andi r2,r2,2 + 801ceb8: 10000326 beq r2,zero,801cec8 + (status & ALTERA_AVALON_UART_STATUS_CTS_MSK)) + 801cebc: e0bffc17 ldw r2,-16(fp) + 801cec0: 1082000c andi r2,r2,2048 + if (!(sp->flags & ALT_AVALON_UART_FC) || + 801cec4: 10003126 beq r2,zero,801cf8c + * In a multi-threaded environment, set the write event flag to indicate + * that there is space in the circular buffer. This is only done if the + * buffer was previously empty. + */ + + if (sp->tx_start == ((sp->tx_end + 1) & ALT_AVALON_UART_BUF_MSK)) + 801cec8: e0bffd17 ldw r2,-12(fp) + 801cecc: 10c00417 ldw r3,16(r2) + 801ced0: e0bffd17 ldw r2,-12(fp) + 801ced4: 10800517 ldw r2,20(r2) + 801ced8: 10800044 addi r2,r2,1 + 801cedc: 10800fcc andi r2,r2,63 + 801cee0: 1880121e bne r3,r2,801cf2c + { + ALT_FLAG_POST (sp->events, + 801cee4: e0bffd17 ldw r2,-12(fp) + 801cee8: 10800717 ldw r2,28(r2) + 801ceec: e0bfff15 stw r2,-4(fp) + 801cef0: 00800084 movi r2,2 + 801cef4: e0bffe8d sth r2,-6(fp) + 801cef8: 00800044 movi r2,1 + 801cefc: e0bffe45 stb r2,-7(fp) + if (OSRunning) + 801cf00: d0a04b43 ldbu r2,-32467(gp) + 801cf04: 10803fcc andi r2,r2,255 + 801cf08: 10000826 beq r2,zero,801cf2c + OSFlagPost (group, flags, opt, &err); + 801cf0c: e0bffe8b ldhu r2,-6(fp) + 801cf10: e0fffe43 ldbu r3,-7(fp) + 801cf14: e13ffe04 addi r4,fp,-8 + 801cf18: 200f883a mov r7,r4 + 801cf1c: 180d883a mov r6,r3 + 801cf20: 100b883a mov r5,r2 + 801cf24: e13fff17 ldw r4,-4(fp) + 801cf28: 80129700 call 8012970 + OS_FLAG_SET); + } + + /* Write the data to the device */ + + IOWR_ALTERA_AVALON_UART_TXDATA(sp->base, sp->tx_buf[sp->tx_start]); + 801cf2c: e0bffd17 ldw r2,-12(fp) + 801cf30: 10800017 ldw r2,0(r2) + 801cf34: 10800104 addi r2,r2,4 + 801cf38: e0fffd17 ldw r3,-12(fp) + 801cf3c: 18c00417 ldw r3,16(r3) + 801cf40: e13ffd17 ldw r4,-12(fp) + 801cf44: 20c7883a add r3,r4,r3 + 801cf48: 18c01a03 ldbu r3,104(r3) + 801cf4c: 18c03fcc andi r3,r3,255 + 801cf50: 10c00035 stwio r3,0(r2) + + sp->tx_start = (++sp->tx_start) & ALT_AVALON_UART_BUF_MSK; + 801cf54: e0bffd17 ldw r2,-12(fp) + 801cf58: 10800417 ldw r2,16(r2) + 801cf5c: 10800044 addi r2,r2,1 + 801cf60: e0fffd17 ldw r3,-12(fp) + 801cf64: 18800415 stw r2,16(r3) + 801cf68: 10c00fcc andi r3,r2,63 + 801cf6c: e0bffd17 ldw r2,-12(fp) + 801cf70: 10c00415 stw r3,16(r2) + /* + * In case the tranmit interrupt had previously been disabled by + * detecting a low value on CTS, it is reenabled here. + */ + + sp->ctrl |= ALTERA_AVALON_UART_CONTROL_TRDY_MSK; + 801cf74: e0bffd17 ldw r2,-12(fp) + 801cf78: 10800117 ldw r2,4(r2) + 801cf7c: 10c01014 ori r3,r2,64 + 801cf80: e0bffd17 ldw r2,-12(fp) + 801cf84: 10c00115 stw r3,4(r2) + 801cf88: 00000e06 br 801cfc4 + * the last write to the status register. To avoid this resulting in + * deadlock, it's necessary to re-check the status register here + * before throttling. + */ + + status = IORD_ALTERA_AVALON_UART_STATUS(sp->base); + 801cf8c: e0bffd17 ldw r2,-12(fp) + 801cf90: 10800017 ldw r2,0(r2) + 801cf94: 10800204 addi r2,r2,8 + 801cf98: 10800037 ldwio r2,0(r2) + 801cf9c: e0bffc15 stw r2,-16(fp) + + if (!(status & ALTERA_AVALON_UART_STATUS_CTS_MSK)) + 801cfa0: e0bffc17 ldw r2,-16(fp) + 801cfa4: 1082000c andi r2,r2,2048 + 801cfa8: 1000061e bne r2,zero,801cfc4 + { + sp->ctrl &= ~ALTERA_AVALON_UART_CONTROL_TRDY_MSK; + 801cfac: e0bffd17 ldw r2,-12(fp) + 801cfb0: 10c00117 ldw r3,4(r2) + 801cfb4: 00bfefc4 movi r2,-65 + 801cfb8: 1886703a and r3,r3,r2 + 801cfbc: e0bffd17 ldw r2,-12(fp) + 801cfc0: 10c00115 stw r3,4(r2) + /* + * If the circular buffer is empty, disable the interrupt. This will be + * re-enabled when new data is placed in the buffer. + */ + + if (sp->tx_start == sp->tx_end) + 801cfc4: e0bffd17 ldw r2,-12(fp) + 801cfc8: 10c00417 ldw r3,16(r2) + 801cfcc: e0bffd17 ldw r2,-12(fp) + 801cfd0: 10800517 ldw r2,20(r2) + 801cfd4: 1880061e bne r3,r2,801cff0 + { + sp->ctrl &= ~(ALTERA_AVALON_UART_CONTROL_TRDY_MSK | + 801cfd8: e0bffd17 ldw r2,-12(fp) + 801cfdc: 10c00117 ldw r3,4(r2) + 801cfe0: 00beefc4 movi r2,-1089 + 801cfe4: 1886703a and r3,r3,r2 + 801cfe8: e0bffd17 ldw r2,-12(fp) + 801cfec: 10c00115 stw r3,4(r2) + ALTERA_AVALON_UART_CONTROL_DCTS_MSK); + } + + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + 801cff0: e0bffd17 ldw r2,-12(fp) + 801cff4: 10800017 ldw r2,0(r2) + 801cff8: 10800304 addi r2,r2,12 + 801cffc: e0fffd17 ldw r3,-12(fp) + 801d000: 18c00117 ldw r3,4(r3) + 801d004: 10c00035 stwio r3,0(r2) +} + 801d008: 0001883a nop + 801d00c: e037883a mov sp,fp + 801d010: dfc00117 ldw ra,4(sp) + 801d014: df000017 ldw fp,0(sp) + 801d018: dec00204 addi sp,sp,8 + 801d01c: f800283a ret + +0801d020 : + * The close routine is not implemented for the small driver; instead it will + * map to null. This is because the small driver simply waits while characters + * are transmitted; there is no interrupt-serviced buffer to empty + */ +int altera_avalon_uart_close(altera_avalon_uart_state* sp, int flags) +{ + 801d020: defffd04 addi sp,sp,-12 + 801d024: df000215 stw fp,8(sp) + 801d028: df000204 addi fp,sp,8 + 801d02c: e13fff15 stw r4,-4(fp) + 801d030: e17ffe15 stw r5,-8(fp) + /* + * Wait for all transmit data to be emptied by the UART ISR. + */ + while (sp->tx_start != sp->tx_end) { + 801d034: 00000506 br 801d04c + if (flags & O_NONBLOCK) { + 801d038: e0bffe17 ldw r2,-8(fp) + 801d03c: 1090000c andi r2,r2,16384 + 801d040: 10000226 beq r2,zero,801d04c + return -EWOULDBLOCK; + 801d044: 00bffd44 movi r2,-11 + 801d048: 00000606 br 801d064 + while (sp->tx_start != sp->tx_end) { + 801d04c: e0bfff17 ldw r2,-4(fp) + 801d050: 10c00417 ldw r3,16(r2) + 801d054: e0bfff17 ldw r2,-4(fp) + 801d058: 10800517 ldw r2,20(r2) + 801d05c: 18bff61e bne r3,r2,801d038 + } + } + + return 0; + 801d060: 0005883a mov r2,zero +} + 801d064: e037883a mov sp,fp + 801d068: df000017 ldw fp,0(sp) + 801d06c: dec00104 addi sp,sp,4 + 801d070: f800283a ret + +0801d074 : +{ + 801d074: defffe04 addi sp,sp,-8 + 801d078: dfc00115 stw ra,4(sp) + 801d07c: df000015 stw fp,0(sp) + 801d080: d839883a mov fp,sp + return ((alt_errno) ? alt_errno() : &errno); + 801d084: d0a02717 ldw r2,-32612(gp) + 801d088: 10000326 beq r2,zero,801d098 + 801d08c: d0a02717 ldw r2,-32612(gp) + 801d090: 103ee83a callr r2 + 801d094: 00000106 br 801d09c + 801d098: d0a04204 addi r2,gp,-32504 +} + 801d09c: e037883a mov sp,fp + 801d0a0: dfc00117 ldw ra,4(sp) + 801d0a4: df000017 ldw fp,0(sp) + 801d0a8: dec00204 addi sp,sp,8 + 801d0ac: f800283a ret + +0801d0b0 : + */ + +int +altera_avalon_uart_read(altera_avalon_uart_state* sp, char* ptr, int len, + int flags) +{ + 801d0b0: deffeb04 addi sp,sp,-84 + 801d0b4: dfc01415 stw ra,80(sp) + 801d0b8: df001315 stw fp,76(sp) + 801d0bc: df001304 addi fp,sp,76 + 801d0c0: e13ff115 stw r4,-60(fp) + 801d0c4: e17ff015 stw r5,-64(fp) + 801d0c8: e1bfef15 stw r6,-68(fp) + 801d0cc: e1ffee15 stw r7,-72(fp) + alt_irq_context context; + int block; + alt_u8 read_would_block = 0; + 801d0d0: e03fffc5 stb zero,-1(fp) + int count = 0; + 801d0d4: e03ffe15 stw zero,-8(fp) + /* + * Construct a flag to indicate whether the device is being accessed in + * blocking or non-blocking mode. + */ + + block = !(flags & O_NONBLOCK); + 801d0d8: e0bfee17 ldw r2,-72(fp) + 801d0dc: 1090000c andi r2,r2,16384 + 801d0e0: 1005003a cmpeq r2,r2,zero + 801d0e4: 10803fcc andi r2,r2,255 + 801d0e8: e0bffd15 stw r2,-12(fp) + /* + * When running in a multi threaded environment, obtain the "read_lock" + * semaphore. This ensures that reading from the device is thread-safe. + */ + + ALT_SEM_PEND (sp->read_lock, 0); + 801d0ec: e0bff117 ldw r2,-60(fp) + 801d0f0: 10800817 ldw r2,32(r2) + 801d0f4: e0bffb15 stw r2,-20(fp) + 801d0f8: e03ffa8d sth zero,-22(fp) + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sem_pend (OS_EVENT* sem, + INT16U timeout) +{ + INT8U err; + OSSemPend (sem, timeout, &err); + 801d0fc: e0bffa8b ldhu r2,-22(fp) + 801d100: e0fff284 addi r3,fp,-54 + 801d104: 180d883a mov r6,r3 + 801d108: 100b883a mov r5,r2 + 801d10c: e13ffb17 ldw r4,-20(fp) + 801d110: 8015a600 call 8015a60 + /* + * Read the required amount of data, until the circular buffer runs + * empty + */ + + while ((count < len) && (sp->rx_start != sp->rx_end)) + 801d114: 00001306 br 801d164 + { + count++; + 801d118: e0bffe17 ldw r2,-8(fp) + 801d11c: 10800044 addi r2,r2,1 + 801d120: e0bffe15 stw r2,-8(fp) + *ptr++ = sp->rx_buf[sp->rx_start]; + 801d124: e0bff117 ldw r2,-60(fp) + 801d128: 10800217 ldw r2,8(r2) + 801d12c: e0fff117 ldw r3,-60(fp) + 801d130: 1885883a add r2,r3,r2 + 801d134: 11000a03 ldbu r4,40(r2) + 801d138: e0bff017 ldw r2,-64(fp) + 801d13c: 10c00044 addi r3,r2,1 + 801d140: e0fff015 stw r3,-64(fp) + 801d144: 2007883a mov r3,r4 + 801d148: 10c00005 stb r3,0(r2) + + sp->rx_start = (sp->rx_start+1) & ALT_AVALON_UART_BUF_MSK; + 801d14c: e0bff117 ldw r2,-60(fp) + 801d150: 10800217 ldw r2,8(r2) + 801d154: 10800044 addi r2,r2,1 + 801d158: 10c00fcc andi r3,r2,63 + 801d15c: e0bff117 ldw r2,-60(fp) + 801d160: 10c00215 stw r3,8(r2) + while ((count < len) && (sp->rx_start != sp->rx_end)) + 801d164: e0fffe17 ldw r3,-8(fp) + 801d168: e0bfef17 ldw r2,-68(fp) + 801d16c: 1880050e bge r3,r2,801d184 + 801d170: e0bff117 ldw r2,-60(fp) + 801d174: 10c00217 ldw r3,8(r2) + 801d178: e0bff117 ldw r2,-60(fp) + 801d17c: 10800317 ldw r2,12(r2) + 801d180: 18bfe51e bne r3,r2,801d118 + /* + * If no data has been transferred, the circular buffer is empty, and + * this is not a non-blocking access, block waiting for data to arrive. + */ + + if (!count && (sp->rx_start == sp->rx_end)) + 801d184: e0bffe17 ldw r2,-8(fp) + 801d188: 10003a1e bne r2,zero,801d274 + 801d18c: e0bff117 ldw r2,-60(fp) + 801d190: 10c00217 ldw r3,8(r2) + 801d194: e0bff117 ldw r2,-60(fp) + 801d198: 10800317 ldw r2,12(r2) + 801d19c: 1880351e bne r3,r2,801d274 + { + if (!block) + 801d1a0: e0bffd17 ldw r2,-12(fp) + 801d1a4: 1000071e bne r2,zero,801d1c4 + { + /* Set errno to indicate the reason we're not returning any data */ + + ALT_ERRNO = EWOULDBLOCK; + 801d1a8: 801d0740 call 801d074 + 801d1ac: 1007883a mov r3,r2 + 801d1b0: 008002c4 movi r2,11 + 801d1b4: 18800015 stw r2,0(r3) + read_would_block = 1; + 801d1b8: 00800044 movi r2,1 + 801d1bc: e0bfffc5 stb r2,-1(fp) + break; + 801d1c0: 00003006 br 801d284 + NIOS2_READ_STATUS (context); + 801d1c4: 0005303a rdctl r2,status + 801d1c8: e0bff515 stw r2,-44(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 801d1cc: e0fff517 ldw r3,-44(fp) + 801d1d0: 00bfff84 movi r2,-2 + 801d1d4: 1884703a and r2,r3,r2 + 801d1d8: 1001703a wrctl status,r2 + return context; + 801d1dc: e0bff517 ldw r2,-44(fp) + { + /* Block waiting for some data to arrive */ + + /* First, ensure read interrupts are enabled to avoid deadlock */ + + context = alt_irq_disable_all (); + 801d1e0: e0bffc15 stw r2,-16(fp) + sp->ctrl |= ALTERA_AVALON_UART_CONTROL_RRDY_MSK; + 801d1e4: e0bff117 ldw r2,-60(fp) + 801d1e8: 10800117 ldw r2,4(r2) + 801d1ec: 10c02014 ori r3,r2,128 + 801d1f0: e0bff117 ldw r2,-60(fp) + 801d1f4: 10c00115 stw r3,4(r2) + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + 801d1f8: e0bff117 ldw r2,-60(fp) + 801d1fc: 10800017 ldw r2,0(r2) + 801d200: 10800304 addi r2,r2,12 + 801d204: e0fff117 ldw r3,-60(fp) + 801d208: 18c00117 ldw r3,4(r3) + 801d20c: 10c00035 stwio r3,0(r2) + 801d210: e0bffc17 ldw r2,-16(fp) + 801d214: e0bff615 stw r2,-40(fp) + NIOS2_WRITE_STATUS (context); + 801d218: e0bff617 ldw r2,-40(fp) + 801d21c: 1001703a wrctl status,r2 + * flag set in the interrupt service routine. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something more + * profitable elsewhere. + */ + + ALT_FLAG_PEND (sp->events, + 801d220: e0bff117 ldw r2,-60(fp) + 801d224: 10800717 ldw r2,28(r2) + 801d228: e0bff915 stw r2,-28(fp) + 801d22c: 00800044 movi r2,1 + 801d230: e0bff88d sth r2,-30(fp) + 801d234: 00bfe0c4 movi r2,-125 + 801d238: e0bff845 stb r2,-31(fp) + 801d23c: e03ff78d sth zero,-34(fp) + if (OSRunning) + 801d240: d0a04b43 ldbu r2,-32467(gp) + 801d244: 10803fcc andi r2,r2,255 + 801d248: 10000a26 beq r2,zero,801d274 + OSFlagPend (group, flags, wait_type, timeout, &err); + 801d24c: e0fff88b ldhu r3,-30(fp) + 801d250: e13ff843 ldbu r4,-31(fp) + 801d254: e17ff78b ldhu r5,-34(fp) + 801d258: e0bff2c4 addi r2,fp,-53 + 801d25c: d8800015 stw r2,0(sp) + 801d260: 280f883a mov r7,r5 + 801d264: 200d883a mov r6,r4 + 801d268: 180b883a mov r5,r3 + 801d26c: e13ff917 ldw r4,-28(fp) + 801d270: 80123780 call 8012378 + OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, + 0); + } + } + } + while (!count && len); + 801d274: e0bffe17 ldw r2,-8(fp) + 801d278: 1000021e bne r2,zero,801d284 + 801d27c: e0bfef17 ldw r2,-68(fp) + 801d280: 103fb81e bne r2,zero,801d164 + /* + * Now that access to the circular buffer is complete, release the read + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->read_lock); + 801d284: e0bff117 ldw r2,-60(fp) + 801d288: 10800817 ldw r2,32(r2) + 801d28c: 1009883a mov r4,r2 + 801d290: 8015d840 call 8015d84 + NIOS2_READ_STATUS (context); + 801d294: 0005303a rdctl r2,status + 801d298: e0bff315 stw r2,-52(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 801d29c: e0fff317 ldw r3,-52(fp) + 801d2a0: 00bfff84 movi r2,-2 + 801d2a4: 1884703a and r2,r3,r2 + 801d2a8: 1001703a wrctl status,r2 + return context; + 801d2ac: e0bff317 ldw r2,-52(fp) + /* + * Ensure that interrupts are enabled, so that the circular buffer can + * re-fill. + */ + + context = alt_irq_disable_all (); + 801d2b0: e0bffc15 stw r2,-16(fp) + sp->ctrl |= ALTERA_AVALON_UART_CONTROL_RRDY_MSK; + 801d2b4: e0bff117 ldw r2,-60(fp) + 801d2b8: 10800117 ldw r2,4(r2) + 801d2bc: 10c02014 ori r3,r2,128 + 801d2c0: e0bff117 ldw r2,-60(fp) + 801d2c4: 10c00115 stw r3,4(r2) + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + 801d2c8: e0bff117 ldw r2,-60(fp) + 801d2cc: 10800017 ldw r2,0(r2) + 801d2d0: 10800304 addi r2,r2,12 + 801d2d4: e0fff117 ldw r3,-60(fp) + 801d2d8: 18c00117 ldw r3,4(r3) + 801d2dc: 10c00035 stwio r3,0(r2) + 801d2e0: e0bffc17 ldw r2,-16(fp) + 801d2e4: e0bff415 stw r2,-48(fp) + NIOS2_WRITE_STATUS (context); + 801d2e8: e0bff417 ldw r2,-48(fp) + 801d2ec: 1001703a wrctl status,r2 + alt_irq_enable_all (context); + + /* Return the number of bytes read */ + if(read_would_block) { + 801d2f0: e0bfffc3 ldbu r2,-1(fp) + 801d2f4: 10000226 beq r2,zero,801d300 + return -EWOULDBLOCK; + 801d2f8: 00bffd44 movi r2,-11 + 801d2fc: 00000106 br 801d304 + } + else { + return count; + 801d300: e0bffe17 ldw r2,-8(fp) + } +} + 801d304: e037883a mov sp,fp + 801d308: dfc00117 ldw ra,4(sp) + 801d30c: df000017 ldw fp,0(sp) + 801d310: dec00204 addi sp,sp,8 + 801d314: f800283a ret + +0801d318 : +{ + 801d318: defffe04 addi sp,sp,-8 + 801d31c: dfc00115 stw ra,4(sp) + 801d320: df000015 stw fp,0(sp) + 801d324: d839883a mov fp,sp + return ((alt_errno) ? alt_errno() : &errno); + 801d328: d0a02717 ldw r2,-32612(gp) + 801d32c: 10000326 beq r2,zero,801d33c + 801d330: d0a02717 ldw r2,-32612(gp) + 801d334: 103ee83a callr r2 + 801d338: 00000106 br 801d340 + 801d33c: d0a04204 addi r2,gp,-32504 +} + 801d340: e037883a mov sp,fp + 801d344: dfc00117 ldw ra,4(sp) + 801d348: df000017 ldw fp,0(sp) + 801d34c: dec00204 addi sp,sp,8 + 801d350: f800283a ret + +0801d354 : + */ + +int +altera_avalon_uart_write(altera_avalon_uart_state* sp, const char* ptr, int len, + int flags) +{ + 801d354: deffeb04 addi sp,sp,-84 + 801d358: dfc01415 stw ra,80(sp) + 801d35c: df001315 stw fp,76(sp) + 801d360: df001304 addi fp,sp,76 + 801d364: e13ff115 stw r4,-60(fp) + 801d368: e17ff015 stw r5,-64(fp) + 801d36c: e1bfef15 stw r6,-68(fp) + 801d370: e1ffee15 stw r7,-72(fp) + alt_irq_context context; + int no_block; + alt_u32 next; + int count = len; + 801d374: e0bfef17 ldw r2,-68(fp) + 801d378: e0bfff15 stw r2,-4(fp) + /* + * Construct a flag to indicate whether the device is being accessed in + * blocking or non-blocking mode. + */ + + no_block = (flags & O_NONBLOCK); + 801d37c: e0bfee17 ldw r2,-72(fp) + 801d380: 1090000c andi r2,r2,16384 + 801d384: e0bffe15 stw r2,-8(fp) + /* + * When running in a multi threaded environment, obtain the "write_lock" + * semaphore. This ensures that writing to the device is thread-safe. + */ + + ALT_SEM_PEND (sp->write_lock, 0); + 801d388: e0bff117 ldw r2,-60(fp) + 801d38c: 10800917 ldw r2,36(r2) + 801d390: e0bffb15 stw r2,-20(fp) + 801d394: e03ffa8d sth zero,-22(fp) + 801d398: e0bffa8b ldhu r2,-22(fp) + 801d39c: e0fff284 addi r3,fp,-54 + 801d3a0: 180d883a mov r6,r3 + 801d3a4: 100b883a mov r5,r2 + 801d3a8: e13ffb17 ldw r4,-20(fp) + 801d3ac: 8015a600 call 8015a60 + * Loop transferring data from the input buffer to the transmit circular + * buffer. The loop is terminated once all the data has been transferred, + * or, (if in non-blocking mode) the buffer becomes full. + */ + + while (count) + 801d3b0: 00005006 br 801d4f4 + { + /* Determine the next slot in the buffer to access */ + + next = (sp->tx_end + 1) & ALT_AVALON_UART_BUF_MSK; + 801d3b4: e0bff117 ldw r2,-60(fp) + 801d3b8: 10800517 ldw r2,20(r2) + 801d3bc: 10800044 addi r2,r2,1 + 801d3c0: 10800fcc andi r2,r2,63 + 801d3c4: e0bffd15 stw r2,-12(fp) + + /* block waiting for space if necessary */ + + if (next == sp->tx_start) + 801d3c8: e0bff117 ldw r2,-60(fp) + 801d3cc: 10800417 ldw r2,16(r2) + 801d3d0: e0fffd17 ldw r3,-12(fp) + 801d3d4: 1880371e bne r3,r2,801d4b4 + { + if (no_block) + 801d3d8: e0bffe17 ldw r2,-8(fp) + 801d3dc: 10000526 beq r2,zero,801d3f4 + { + /* Set errno to indicate why this function returned early */ + + ALT_ERRNO = EWOULDBLOCK; + 801d3e0: 801d3180 call 801d318 + 801d3e4: 1007883a mov r3,r2 + 801d3e8: 008002c4 movi r2,11 + 801d3ec: 18800015 stw r2,0(r3) + break; + 801d3f0: 00004206 br 801d4fc + NIOS2_READ_STATUS (context); + 801d3f4: 0005303a rdctl r2,status + 801d3f8: e0bff815 stw r2,-32(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 801d3fc: e0fff817 ldw r3,-32(fp) + 801d400: 00bfff84 movi r2,-2 + 801d404: 1884703a and r2,r3,r2 + 801d408: 1001703a wrctl status,r2 + return context; + 801d40c: e0bff817 ldw r2,-32(fp) + { + /* Block waiting for space in the circular buffer */ + + /* First, ensure transmit interrupts are enabled to avoid deadlock */ + + context = alt_irq_disable_all (); + 801d410: e0bffc15 stw r2,-16(fp) + sp->ctrl |= (ALTERA_AVALON_UART_CONTROL_TRDY_MSK | + 801d414: e0bff117 ldw r2,-60(fp) + 801d418: 10800117 ldw r2,4(r2) + 801d41c: 10c11014 ori r3,r2,1088 + 801d420: e0bff117 ldw r2,-60(fp) + 801d424: 10c00115 stw r3,4(r2) + ALTERA_AVALON_UART_CONTROL_DCTS_MSK); + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + 801d428: e0bff117 ldw r2,-60(fp) + 801d42c: 10800017 ldw r2,0(r2) + 801d430: 10800304 addi r2,r2,12 + 801d434: e0fff117 ldw r3,-60(fp) + 801d438: 18c00117 ldw r3,4(r3) + 801d43c: 10c00035 stwio r3,0(r2) + 801d440: e0bffc17 ldw r2,-16(fp) + 801d444: e0bff915 stw r2,-28(fp) + NIOS2_WRITE_STATUS (context); + 801d448: e0bff917 ldw r2,-28(fp) + 801d44c: 1001703a wrctl status,r2 + * flag set in the interrupt service routine. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something + * more profitable elsewhere. + */ + + ALT_FLAG_PEND (sp->events, + 801d450: e0bff117 ldw r2,-60(fp) + 801d454: 10800717 ldw r2,28(r2) + 801d458: e0bff715 stw r2,-36(fp) + 801d45c: 00800084 movi r2,2 + 801d460: e0bff68d sth r2,-38(fp) + 801d464: 00bfe0c4 movi r2,-125 + 801d468: e0bff645 stb r2,-39(fp) + 801d46c: e03ff58d sth zero,-42(fp) + if (OSRunning) + 801d470: d0a04b43 ldbu r2,-32467(gp) + 801d474: 10803fcc andi r2,r2,255 + 801d478: 10000a26 beq r2,zero,801d4a4 + OSFlagPend (group, flags, wait_type, timeout, &err); + 801d47c: e0fff68b ldhu r3,-38(fp) + 801d480: e13ff643 ldbu r4,-39(fp) + 801d484: e17ff58b ldhu r5,-42(fp) + 801d488: e0bff2c4 addi r2,fp,-53 + 801d48c: d8800015 stw r2,0(sp) + 801d490: 280f883a mov r7,r5 + 801d494: 200d883a mov r6,r4 + 801d498: 180b883a mov r5,r3 + 801d49c: e13ff717 ldw r4,-36(fp) + 801d4a0: 80123780 call 8012378 + ALT_UART_WRITE_RDY, + OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, + 0); + } + while ((next == sp->tx_start)); + 801d4a4: e0bff117 ldw r2,-60(fp) + 801d4a8: 10800417 ldw r2,16(r2) + 801d4ac: e0fffd17 ldw r3,-12(fp) + 801d4b0: 18bfe726 beq r3,r2,801d450 + } + } + + count--; + 801d4b4: e0bfff17 ldw r2,-4(fp) + 801d4b8: 10bfffc4 addi r2,r2,-1 + 801d4bc: e0bfff15 stw r2,-4(fp) + + /* Add the next character to the transmit buffer */ + + sp->tx_buf[sp->tx_end] = *ptr++; + 801d4c0: e0bff017 ldw r2,-64(fp) + 801d4c4: 10c00044 addi r3,r2,1 + 801d4c8: e0fff015 stw r3,-64(fp) + 801d4cc: 10c00003 ldbu r3,0(r2) + 801d4d0: e0bff117 ldw r2,-60(fp) + 801d4d4: 10800517 ldw r2,20(r2) + 801d4d8: 1809883a mov r4,r3 + 801d4dc: e0fff117 ldw r3,-60(fp) + 801d4e0: 1885883a add r2,r3,r2 + 801d4e4: 11001a05 stb r4,104(r2) + sp->tx_end = next; + 801d4e8: e0bff117 ldw r2,-60(fp) + 801d4ec: e0fffd17 ldw r3,-12(fp) + 801d4f0: 10c00515 stw r3,20(r2) + while (count) + 801d4f4: e0bfff17 ldw r2,-4(fp) + 801d4f8: 103fae1e bne r2,zero,801d3b4 + /* + * Now that access to the circular buffer is complete, release the write + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->write_lock); + 801d4fc: e0bff117 ldw r2,-60(fp) + 801d500: 10800917 ldw r2,36(r2) + 801d504: 1009883a mov r4,r2 + 801d508: 8015d840 call 8015d84 + NIOS2_READ_STATUS (context); + 801d50c: 0005303a rdctl r2,status + 801d510: e0bff315 stw r2,-52(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 801d514: e0fff317 ldw r3,-52(fp) + 801d518: 00bfff84 movi r2,-2 + 801d51c: 1884703a and r2,r3,r2 + 801d520: 1001703a wrctl status,r2 + return context; + 801d524: e0bff317 ldw r2,-52(fp) + /* + * Ensure that interrupts are enabled, so that the circular buffer can + * drain. + */ + + context = alt_irq_disable_all (); + 801d528: e0bffc15 stw r2,-16(fp) + sp->ctrl |= ALTERA_AVALON_UART_CONTROL_TRDY_MSK | + 801d52c: e0bff117 ldw r2,-60(fp) + 801d530: 10800117 ldw r2,4(r2) + 801d534: 10c11014 ori r3,r2,1088 + 801d538: e0bff117 ldw r2,-60(fp) + 801d53c: 10c00115 stw r3,4(r2) + ALTERA_AVALON_UART_CONTROL_DCTS_MSK; + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + 801d540: e0bff117 ldw r2,-60(fp) + 801d544: 10800017 ldw r2,0(r2) + 801d548: 10800304 addi r2,r2,12 + 801d54c: e0fff117 ldw r3,-60(fp) + 801d550: 18c00117 ldw r3,4(r3) + 801d554: 10c00035 stwio r3,0(r2) + 801d558: e0bffc17 ldw r2,-16(fp) + 801d55c: e0bff415 stw r2,-48(fp) + NIOS2_WRITE_STATUS (context); + 801d560: e0bff417 ldw r2,-48(fp) + 801d564: 1001703a wrctl status,r2 + alt_irq_enable_all (context); + + /* return the number of bytes written */ + + return (len - count); + 801d568: e0ffef17 ldw r3,-68(fp) + 801d56c: e0bfff17 ldw r2,-4(fp) + 801d570: 1885c83a sub r2,r3,r2 +} + 801d574: e037883a mov sp,fp + 801d578: dfc00117 ldw ra,4(sp) + 801d57c: df000017 ldw fp,0(sp) + 801d580: dec00204 addi sp,sp,8 + 801d584: f800283a ret + +0801d588 : + +typedef struct alt_flash_dev alt_flash_dev; +typedef alt_flash_dev alt_flash_fd; + +static ALT_INLINE int alt_flash_device_register( alt_flash_fd* fd) +{ + 801d588: defffd04 addi sp,sp,-12 + 801d58c: dfc00215 stw ra,8(sp) + 801d590: df000115 stw fp,4(sp) + 801d594: df000104 addi fp,sp,4 + 801d598: e13fff15 stw r4,-4(fp) + extern alt_llist alt_flash_dev_list; + + return alt_dev_llist_insert ((alt_dev_llist*) fd, &alt_flash_dev_list); + 801d59c: d1600404 addi r5,gp,-32752 + 801d5a0: e13fff17 ldw r4,-4(fp) + 801d5a4: 80372a00 call 80372a0 +} + 801d5a8: e037883a mov sp,fp + 801d5ac: dfc00117 ldw ra,4(sp) + 801d5b0: df000017 ldw fp,0(sp) + 801d5b4: dec00204 addi sp,sp,8 + 801d5b8: f800283a ret + +0801d5bc : + * -EINVAL -> Invalid arguments + * -ETIME -> Time out and skipping the looping after 0.7 sec. + * -ENOLCK -> Sectors lock failed. +**/ +int alt_qspi_controller_lock(alt_flash_dev *flash_info, alt_u32 sectors_to_lock) +{ + 801d5bc: defff804 addi sp,sp,-32 + 801d5c0: dfc00715 stw ra,28(sp) + 801d5c4: df000615 stw fp,24(sp) + 801d5c8: df000604 addi fp,sp,24 + 801d5cc: e13ffb15 stw r4,-20(fp) + 801d5d0: e17ffa15 stw r5,-24(fp) + alt_u32 mem_op_value = 0; /* value to write to EPCQ_MEM_OP register */ + 801d5d4: e03fff15 stw zero,-4(fp) + alt_qspi_controller_dev* qspi_flash_info = NULL; + 801d5d8: e03ffe15 stw zero,-8(fp) + alt_u32 result = 0; + 801d5dc: e03ffd15 stw zero,-12(fp) + alt_32 status = 0; + 801d5e0: e03ffc15 stw zero,-16(fp) + + /* return -EINVAL if flash_info is NULL */ + if(NULL == flash_info || 0 > sectors_to_lock) + 801d5e4: e0bffb17 ldw r2,-20(fp) + 801d5e8: 1000021e bne r2,zero,801d5f4 + { + return -EINVAL; + 801d5ec: 00bffa84 movi r2,-22 + 801d5f0: 00003106 br 801d6b8 + } + + qspi_flash_info = (alt_qspi_controller_dev*)flash_info; + 801d5f4: e0bffb17 ldw r2,-20(fp) + 801d5f8: e0bffe15 stw r2,-8(fp) + + /* sector value should occupy bits 17:8 */ + mem_op_value = sectors_to_lock << 8; + 801d5fc: e0bffa17 ldw r2,-24(fp) + 801d600: 1004923a slli r2,r2,8 + 801d604: e0bfff15 stw r2,-4(fp) + + /* sector protect commands 0b11 occupies lower 2 bits */ + mem_op_value |= ALTERA_QSPI_CONTROLLER_MEM_OP_SECTOR_PROTECT_CMD; + 801d608: e0bfff17 ldw r2,-4(fp) + 801d60c: 108000d4 ori r2,r2,3 + 801d610: e0bfff15 stw r2,-4(fp) + + /* write sector protect command to QSPI_MEM_OP register to protect sectors */ + IOWR_ALTERA_QSPI_CONTROLLER_MEM_OP(qspi_flash_info->csr_base, mem_op_value); + 801d614: e0bffe17 ldw r2,-8(fp) + 801d618: 10803017 ldw r2,192(r2) + 801d61c: 10800304 addi r2,r2,12 + 801d620: 1007883a mov r3,r2 + 801d624: e0bfff17 ldw r2,-4(fp) + 801d628: 18800035 stwio r2,0(r3) + + /* poll write in progress to make sure no operation is in progress */ + status = alt_qspi_poll_for_write_in_progress(qspi_flash_info); + 801d62c: e13ffe17 ldw r4,-8(fp) + 801d630: 801e0100 call 801e010 + 801d634: e0bffc15 stw r2,-16(fp) + if(status != 0) + 801d638: e0bffc17 ldw r2,-16(fp) + 801d63c: 10000226 beq r2,zero,801d648 + { + return status; + 801d640: e0bffc17 ldw r2,-16(fp) + 801d644: 00001c06 br 801d6b8 + } + + status = IORD_ALTERA_QSPI_CONTROLLER_STATUS(qspi_flash_info->csr_base); + 801d648: e0bffe17 ldw r2,-8(fp) + 801d64c: 10803017 ldw r2,192(r2) + 801d650: 10800037 ldwio r2,0(r2) + 801d654: e0bffc15 stw r2,-16(fp) + result |= (status >> 2) & 0x07; /* extract out BP3 - BP0 */ + 801d658: e0bffc17 ldw r2,-16(fp) + 801d65c: 1005d0ba srai r2,r2,2 + 801d660: 108001cc andi r2,r2,7 + 801d664: e0fffd17 ldw r3,-12(fp) + 801d668: 1884b03a or r2,r3,r2 + 801d66c: e0bffd15 stw r2,-12(fp) + result |= (status >> 3) & 0x08; /* extract out BP4 */ + 801d670: e0bffc17 ldw r2,-16(fp) + 801d674: 1005d0fa srai r2,r2,3 + 801d678: 1080020c andi r2,r2,8 + 801d67c: e0fffd17 ldw r3,-12(fp) + 801d680: 1884b03a or r2,r3,r2 + 801d684: e0bffd15 stw r2,-12(fp) + result |= (status >> 1) & 0x10; /* extract out TOP/BOTTOM bit */ + 801d688: e0bffc17 ldw r2,-16(fp) + 801d68c: 1005d07a srai r2,r2,1 + 801d690: 1080040c andi r2,r2,16 + 801d694: e0fffd17 ldw r3,-12(fp) + 801d698: 1884b03a or r2,r3,r2 + 801d69c: e0bffd15 stw r2,-12(fp) + + if(result != sectors_to_lock) + 801d6a0: e0fffd17 ldw r3,-12(fp) + 801d6a4: e0bffa17 ldw r2,-24(fp) + 801d6a8: 18800226 beq r3,r2,801d6b4 + { + return -ENOLCK; + 801d6ac: 00bff484 movi r2,-46 + 801d6b0: 00000106 br 801d6b8 + } + + return 0; + 801d6b4: 0005883a mov r2,zero +} + 801d6b8: e037883a mov sp,fp + 801d6bc: dfc00117 ldw ra,4(sp) + 801d6c0: df000017 ldw fp,0(sp) + 801d6c4: dec00204 addi sp,sp,8 + 801d6c8: f800283a ret + +0801d6cc : +( + alt_flash_fd *fd, /** flash device descriptor */ + flash_region **info, /** pointer to flash_region will be stored here */ + int *number_of_regions /** number of regions will be stored here */ +) +{ + 801d6cc: defffb04 addi sp,sp,-20 + 801d6d0: df000415 stw fp,16(sp) + 801d6d4: df000404 addi fp,sp,16 + 801d6d8: e13ffe15 stw r4,-8(fp) + 801d6dc: e17ffd15 stw r5,-12(fp) + 801d6e0: e1bffc15 stw r6,-16(fp) + alt_flash_dev* flash = NULL; + 801d6e4: e03fff15 stw zero,-4(fp) + + /* return -EINVAL if fd,info and number_of_regions are NULL */ + if(NULL == fd || NULL == info || NULL == number_of_regions) + 801d6e8: e0bffe17 ldw r2,-8(fp) + 801d6ec: 10000426 beq r2,zero,801d700 + 801d6f0: e0bffd17 ldw r2,-12(fp) + 801d6f4: 10000226 beq r2,zero,801d700 + 801d6f8: e0bffc17 ldw r2,-16(fp) + 801d6fc: 1000021e bne r2,zero,801d708 + { + return -EINVAL; + 801d700: 00bffa84 movi r2,-22 + 801d704: 00001006 br 801d748 + } + + flash = (alt_flash_dev*)fd; + 801d708: e0bffe17 ldw r2,-8(fp) + 801d70c: e0bfff15 stw r2,-4(fp) + + *number_of_regions = flash->number_of_regions; + 801d710: e0bfff17 ldw r2,-4(fp) + 801d714: 10c00c17 ldw r3,48(r2) + 801d718: e0bffc17 ldw r2,-16(fp) + 801d71c: 10c00015 stw r3,0(r2) + + if (!flash->number_of_regions) + 801d720: e0bfff17 ldw r2,-4(fp) + 801d724: 10800c17 ldw r2,48(r2) + 801d728: 1000021e bne r2,zero,801d734 + { + return -EIO; + 801d72c: 00bffec4 movi r2,-5 + 801d730: 00000506 br 801d748 + } + else + { + *info = &flash->region_info[0]; + 801d734: e0bfff17 ldw r2,-4(fp) + 801d738: 10c00d04 addi r3,r2,52 + 801d73c: e0bffd17 ldw r2,-12(fp) + 801d740: 10c00015 stw r3,0(r2) + } + + return 0; + 801d744: 0005883a mov r2,zero +} + 801d748: e037883a mov sp,fp + 801d74c: df000017 ldw fp,0(sp) + 801d750: dec00104 addi sp,sp,4 + 801d754: f800283a ret + +0801d758 : + * 0 -> success + * -EINVAL -> Invalid arguments + * -EIO -> write failed, sector might be protected +**/ +int alt_qspi_controller_erase_block(alt_flash_dev *flash_info, int block_offset) +{ + 801d758: defff804 addi sp,sp,-32 + 801d75c: dfc00715 stw ra,28(sp) + 801d760: df000615 stw fp,24(sp) + 801d764: df000604 addi fp,sp,24 + 801d768: e13ffb15 stw r4,-20(fp) + 801d76c: e17ffa15 stw r5,-24(fp) + alt_32 ret_code = 0; + 801d770: e03fff15 stw zero,-4(fp) + alt_u32 mem_op_value = 0; /* value to write to EPCQ_MEM_OP register */ + 801d774: e03ffe15 stw zero,-8(fp) + alt_qspi_controller_dev* qspi_flash_info = NULL; + 801d778: e03ffd15 stw zero,-12(fp) + alt_u32 sector_number = 0; + 801d77c: e03ffc15 stw zero,-16(fp) + + /* return -EINVAL if flash_info is NULL */ + if(NULL == flash_info) + 801d780: e0bffb17 ldw r2,-20(fp) + 801d784: 1000021e bne r2,zero,801d790 + { + return -EINVAL; + 801d788: 00bffa84 movi r2,-22 + 801d78c: 00003606 br 801d868 + } + + qspi_flash_info = (alt_qspi_controller_dev*)flash_info; + 801d790: e0bffb17 ldw r2,-20(fp) + 801d794: e0bffd15 stw r2,-12(fp) + /* + * Sanity checks that block_offset is within the flash memory span and that the + * block offset is sector aligned. + * + */ + if((block_offset < 0) + 801d798: e0bffa17 ldw r2,-24(fp) + 801d79c: 10000a16 blt r2,zero,801d7c8 + || (block_offset >= qspi_flash_info->size_in_bytes) + 801d7a0: e0bffd17 ldw r2,-12(fp) + 801d7a4: 10803117 ldw r2,196(r2) + 801d7a8: e0fffa17 ldw r3,-24(fp) + 801d7ac: 1880062e bgeu r3,r2,801d7c8 + || (block_offset & (qspi_flash_info->sector_size - 1)) != 0) + 801d7b0: e0bffd17 ldw r2,-12(fp) + 801d7b4: 10803417 ldw r2,208(r2) + 801d7b8: 10ffffc4 addi r3,r2,-1 + 801d7bc: e0bffa17 ldw r2,-24(fp) + 801d7c0: 1884703a and r2,r3,r2 + 801d7c4: 10000226 beq r2,zero,801d7d0 + { + return -EINVAL; + 801d7c8: 00bffa84 movi r2,-22 + 801d7cc: 00002606 br 801d868 + } + + /* calculate current sector/block number */ + sector_number = (block_offset/(qspi_flash_info->sector_size)); + 801d7d0: e0fffa17 ldw r3,-24(fp) + 801d7d4: e0bffd17 ldw r2,-12(fp) + 801d7d8: 10803417 ldw r2,208(r2) + 801d7dc: 100b883a mov r5,r2 + 801d7e0: 1809883a mov r4,r3 + 801d7e4: 800cff80 call 800cff8 <__udivsi3> + 801d7e8: e0bffc15 stw r2,-16(fp) + + /* sector value should occupy bits 23:8 */ + mem_op_value = (sector_number << 8) & ALTERA_QSPI_CONTROLLER_MEM_OP_SECTOR_VALUE_MASK; + 801d7ec: e0bffc17 ldw r2,-16(fp) + 801d7f0: 1006923a slli r3,r2,8 + 801d7f4: 00804034 movhi r2,256 + 801d7f8: 10bfc004 addi r2,r2,-256 + 801d7fc: 1884703a and r2,r3,r2 + 801d800: e0bffe15 stw r2,-8(fp) + + /* sector erase commands 0b10 occupies lower 2 bits */ + mem_op_value |= ALTERA_QSPI_CONTROLLER_MEM_OP_SECTOR_ERASE_CMD; + 801d804: e0bffe17 ldw r2,-8(fp) + 801d808: 10800094 ori r2,r2,2 + 801d80c: e0bffe15 stw r2,-8(fp) + + /* write sector erase command to QSPI_MEM_OP register to erase sector "sector_number" */ + IOWR_ALTERA_QSPI_CONTROLLER_MEM_OP(qspi_flash_info->csr_base, mem_op_value); + 801d810: e0bffd17 ldw r2,-12(fp) + 801d814: 10803017 ldw r2,192(r2) + 801d818: 10800304 addi r2,r2,12 + 801d81c: 1007883a mov r3,r2 + 801d820: e0bffe17 ldw r2,-8(fp) + 801d824: 18800035 stwio r2,0(r3) + + /* check whether erase triggered a illegal erase interrupt */ + if((IORD_ALTERA_QSPI_CONTROLLER_ISR(qspi_flash_info->csr_base) & + 801d828: e0bffd17 ldw r2,-12(fp) + 801d82c: 10803017 ldw r2,192(r2) + 801d830: 10800404 addi r2,r2,16 + 801d834: 10800037 ldwio r2,0(r2) + 801d838: 1080004c andi r2,r2,1 + 801d83c: 10800058 cmpnei r2,r2,1 + 801d840: 1000081e bne r2,zero,801d864 + ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_ERASE_MASK) == + ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_ERASE_ACTIVE) + { + /* clear register */ + /* QSPI_ISR access is write one to clear (W1C) */ + IOWR_ALTERA_QSPI_CONTROLLER_ISR(qspi_flash_info->csr_base, + 801d844: e0bffd17 ldw r2,-12(fp) + 801d848: 10803017 ldw r2,192(r2) + 801d84c: 10800404 addi r2,r2,16 + 801d850: 1007883a mov r3,r2 + 801d854: 00800044 movi r2,1 + 801d858: 18800035 stwio r2,0(r3) + ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_ERASE_MASK ); + return -EIO; /* erase failed, sector might be protected */ + 801d85c: 00bffec4 movi r2,-5 + 801d860: 00000106 br 801d868 + } + + return ret_code; + 801d864: e0bfff17 ldw r2,-4(fp) +} + 801d868: e037883a mov sp,fp + 801d86c: dfc00117 ldw ra,4(sp) + 801d870: df000017 ldw fp,0(sp) + 801d874: dec00204 addi sp,sp,8 + 801d878: f800283a ret + +0801d87c : + int block_offset, /** sector/block offset in byte addressing */ + int data_offset, /** offset of write from base address */ + const void *data, /** data to be written */ + int length /** bytes of data to be written, >0 */ +) +{ + 801d87c: defff304 addi sp,sp,-52 + 801d880: dfc00c15 stw ra,48(sp) + 801d884: df000b15 stw fp,44(sp) + 801d888: df000b04 addi fp,sp,44 + 801d88c: e13ff815 stw r4,-32(fp) + 801d890: e17ff715 stw r5,-36(fp) + 801d894: e1bff615 stw r6,-40(fp) + 801d898: e1fff515 stw r7,-44(fp) + alt_u32 buffer_offset = 0; /** offset into data buffer to get write data */ + 801d89c: e03fff15 stw zero,-4(fp) + alt_u32 remaining_length = length; /** length left to write */ + 801d8a0: e0800217 ldw r2,8(fp) + 801d8a4: e0bffe15 stw r2,-8(fp) + alt_u32 write_offset = data_offset; /** offset into flash to write too */ + 801d8a8: e0bff617 ldw r2,-40(fp) + 801d8ac: e0bffd15 stw r2,-12(fp) + + alt_qspi_controller_dev *qspi_flash_info = (alt_qspi_controller_dev*)flash_info; + 801d8b0: e0bff817 ldw r2,-32(fp) + 801d8b4: e0bffa15 stw r2,-24(fp) + /* + * Sanity checks that data offset is not larger then a sector, that block offset is + * sector aligned and within the valid flash memory range and a write doesn't spill into + * the adjacent flash sector. + */ + if(block_offset < 0 + 801d8b8: e0bff717 ldw r2,-36(fp) + 801d8bc: 10001e16 blt r2,zero,801d938 + || data_offset < 0 + 801d8c0: e0bff617 ldw r2,-40(fp) + 801d8c4: 10001c16 blt r2,zero,801d938 + || NULL == flash_info + 801d8c8: e0bff817 ldw r2,-32(fp) + 801d8cc: 10001a26 beq r2,zero,801d938 + || NULL == data + 801d8d0: e0bff517 ldw r2,-44(fp) + 801d8d4: 10001826 beq r2,zero,801d938 + || data_offset >= qspi_flash_info->size_in_bytes + 801d8d8: e0bffa17 ldw r2,-24(fp) + 801d8dc: 10803117 ldw r2,196(r2) + 801d8e0: e0fff617 ldw r3,-40(fp) + 801d8e4: 1880142e bgeu r3,r2,801d938 + || block_offset >= qspi_flash_info->size_in_bytes + 801d8e8: e0bffa17 ldw r2,-24(fp) + 801d8ec: 10803117 ldw r2,196(r2) + 801d8f0: e0fff717 ldw r3,-36(fp) + 801d8f4: 1880102e bgeu r3,r2,801d938 + || length > (qspi_flash_info->sector_size - (data_offset - block_offset)) + 801d8f8: e0bffa17 ldw r2,-24(fp) + 801d8fc: 10803417 ldw r2,208(r2) + 801d900: e13ff617 ldw r4,-40(fp) + 801d904: e0fff717 ldw r3,-36(fp) + 801d908: 20c7c83a sub r3,r4,r3 + 801d90c: 10c7c83a sub r3,r2,r3 + 801d910: e0800217 ldw r2,8(fp) + 801d914: 18800836 bltu r3,r2,801d938 + || length < 0 + 801d918: e0800217 ldw r2,8(fp) + 801d91c: 10000616 blt r2,zero,801d938 + || (block_offset & (qspi_flash_info->sector_size - 1)) != 0) + 801d920: e0bffa17 ldw r2,-24(fp) + 801d924: 10803417 ldw r2,208(r2) + 801d928: 10ffffc4 addi r3,r2,-1 + 801d92c: e0bff717 ldw r2,-36(fp) + 801d930: 1884703a and r2,r3,r2 + 801d934: 10004d26 beq r2,zero,801da6c + { + return -EINVAL; + 801d938: 00bffa84 movi r2,-22 + 801d93c: 00004e06 br 801da78 + * We need to make sure that we pad the first few bytes so they're word aligned if they are + * not already. + */ + while (remaining_length > 0) + { + alt_u32 word_to_write = 0xFFFFFFFF; /** initialize word to write to blank word */ + 801d940: 00bfffc4 movi r2,-1 + 801d944: e0bff915 stw r2,-28(fp) + alt_u32 padding = 0; /** bytes to pad the next word that is written */ + 801d948: e03ffc15 stw zero,-16(fp) + alt_u32 bytes_to_copy = sizeof(alt_u32); /** number of bytes from source to copy */ + 801d94c: 00800104 movi r2,4 + 801d950: e0bffb15 stw r2,-20(fp) + + /* + * we need to make sure the write is word aligned + * this should only be true at most 1 time + */ + if (0 != (write_offset & (sizeof(alt_u32) - 1))) + 801d954: e0bffd17 ldw r2,-12(fp) + 801d958: 108000cc andi r2,r2,3 + 801d95c: 10001526 beq r2,zero,801d9b4 + { + /* + * data is not word aligned + * calculate padding bytes need to add before start of a data offset + */ + padding = write_offset & (sizeof(alt_u32) - 1); + 801d960: e0bffd17 ldw r2,-12(fp) + 801d964: 108000cc andi r2,r2,3 + 801d968: e0bffc15 stw r2,-16(fp) + + /* update variables to account for padding being added */ + bytes_to_copy -= padding; + 801d96c: e0fffb17 ldw r3,-20(fp) + 801d970: e0bffc17 ldw r2,-16(fp) + 801d974: 1885c83a sub r2,r3,r2 + 801d978: e0bffb15 stw r2,-20(fp) + + if(bytes_to_copy > remaining_length) + 801d97c: e0bffb17 ldw r2,-20(fp) + 801d980: e0fffe17 ldw r3,-8(fp) + 801d984: 1880022e bgeu r3,r2,801d990 + { + bytes_to_copy = remaining_length; + 801d988: e0bffe17 ldw r2,-8(fp) + 801d98c: e0bffb15 stw r2,-20(fp) + } + + write_offset = write_offset - padding; + 801d990: e0fffd17 ldw r3,-12(fp) + 801d994: e0bffc17 ldw r2,-16(fp) + 801d998: 1885c83a sub r2,r3,r2 + 801d99c: e0bffd15 stw r2,-12(fp) + if(0 != (write_offset & (sizeof(alt_u32) - 1))) + 801d9a0: e0bffd17 ldw r2,-12(fp) + 801d9a4: 108000cc andi r2,r2,3 + 801d9a8: 10000726 beq r2,zero,801d9c8 + { + return -EINVAL; + 801d9ac: 00bffa84 movi r2,-22 + 801d9b0: 00003106 br 801da78 + } + } + else + { + if(bytes_to_copy > remaining_length) + 801d9b4: e0bffb17 ldw r2,-20(fp) + 801d9b8: e0fffe17 ldw r3,-8(fp) + 801d9bc: 1880022e bgeu r3,r2,801d9c8 + { + bytes_to_copy = remaining_length; + 801d9c0: e0bffe17 ldw r2,-8(fp) + 801d9c4: e0bffb15 stw r2,-20(fp) + } + } + + /* prepare the word to be written */ + memcpy((((void*)&word_to_write)) + padding, ((void*)data) + buffer_offset, bytes_to_copy); + 801d9c8: e0fff904 addi r3,fp,-28 + 801d9cc: e0bffc17 ldw r2,-16(fp) + 801d9d0: 1889883a add r4,r3,r2 + 801d9d4: e0fff517 ldw r3,-44(fp) + 801d9d8: e0bfff17 ldw r2,-4(fp) + 801d9dc: 1885883a add r2,r3,r2 + 801d9e0: e1bffb17 ldw r6,-20(fp) + 801d9e4: 100b883a mov r5,r2 + 801d9e8: 80086b80 call 80086b8 + + /* update offset and length variables */ + buffer_offset += bytes_to_copy; + 801d9ec: e0ffff17 ldw r3,-4(fp) + 801d9f0: e0bffb17 ldw r2,-20(fp) + 801d9f4: 1885883a add r2,r3,r2 + 801d9f8: e0bfff15 stw r2,-4(fp) + remaining_length -= bytes_to_copy; + 801d9fc: e0fffe17 ldw r3,-8(fp) + 801da00: e0bffb17 ldw r2,-20(fp) + 801da04: 1885c83a sub r2,r3,r2 + 801da08: e0bffe15 stw r2,-8(fp) + + /* write to flash 32 bits at a time */ + IOWR_32DIRECT(qspi_flash_info->data_base, write_offset, word_to_write); + 801da0c: e0bffa17 ldw r2,-24(fp) + 801da10: 10c02e17 ldw r3,184(r2) + 801da14: e0bffd17 ldw r2,-12(fp) + 801da18: 1885883a add r2,r3,r2 + 801da1c: e0fff917 ldw r3,-28(fp) + 801da20: 10c00035 stwio r3,0(r2) + + /* check whether write triggered a illegal write interrupt */ + if((IORD_ALTERA_QSPI_CONTROLLER_ISR(qspi_flash_info->csr_base) & + 801da24: e0bffa17 ldw r2,-24(fp) + 801da28: 10803017 ldw r2,192(r2) + 801da2c: 10800404 addi r2,r2,16 + 801da30: 10800037 ldwio r2,0(r2) + 801da34: 1080008c andi r2,r2,2 + 801da38: 10800098 cmpnei r2,r2,2 + 801da3c: 1000081e bne r2,zero,801da60 + ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_WRITE_MASK) == + ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_WRITE_ACTIVE) + { + /* clear register */ + IOWR_ALTERA_QSPI_CONTROLLER_ISR(qspi_flash_info->csr_base, + 801da40: e0bffa17 ldw r2,-24(fp) + 801da44: 10803017 ldw r2,192(r2) + 801da48: 10800404 addi r2,r2,16 + 801da4c: 1007883a mov r3,r2 + 801da50: 00800084 movi r2,2 + 801da54: 18800035 stwio r2,0(r3) + ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_WRITE_MASK ); + return -EIO; /** write failed, sector might be protected */ + 801da58: 00bffec4 movi r2,-5 + 801da5c: 00000606 br 801da78 + } + + /* update current offset */ + write_offset = write_offset + sizeof(alt_u32); + 801da60: e0bffd17 ldw r2,-12(fp) + 801da64: 10800104 addi r2,r2,4 + 801da68: e0bffd15 stw r2,-12(fp) + while (remaining_length > 0) + 801da6c: e0bffe17 ldw r2,-8(fp) + 801da70: 103fb31e bne r2,zero,801d940 + } + + return 0; + 801da74: 0005883a mov r2,zero +} + 801da78: e037883a mov sp,fp + 801da7c: dfc00117 ldw ra,4(sp) + 801da80: df000017 ldw fp,0(sp) + 801da84: dec00204 addi sp,sp,8 + 801da88: f800283a ret + +0801da8c : + alt_flash_dev *flash_info, /** device info */ + int offset, /** offset of write from base address */ + const void *src_addr, /** source buffer */ + int length /** size of writing */ +) +{ + 801da8c: defff004 addi sp,sp,-64 + 801da90: dfc00f15 stw ra,60(sp) + 801da94: df000e15 stw fp,56(sp) + 801da98: df000e04 addi fp,sp,56 + 801da9c: e13ff615 stw r4,-40(fp) + 801daa0: e17ff515 stw r5,-44(fp) + 801daa4: e1bff415 stw r6,-48(fp) + 801daa8: e1fff315 stw r7,-52(fp) + alt_32 ret_code = 0; + 801daac: e03fff15 stw zero,-4(fp) + + alt_qspi_controller_dev *qspi_flash_info = NULL; + 801dab0: e03ff915 stw zero,-28(fp) + + alt_u32 write_offset = offset; /** address of next byte to write */ + 801dab4: e0bff517 ldw r2,-44(fp) + 801dab8: e0bffe15 stw r2,-8(fp) + alt_u32 remaining_length = length; /** length of write data left to be written */ + 801dabc: e0bff317 ldw r2,-52(fp) + 801dac0: e0bffd15 stw r2,-12(fp) + alt_u32 buffer_offset = 0; /** offset into source buffer to get write data */ + 801dac4: e03ffc15 stw zero,-16(fp) + alt_u32 i = 0; + 801dac8: e03ffb15 stw zero,-20(fp) + + /* return -EINVAL if flash_info and src_addr are NULL */ + if(NULL == flash_info || NULL == src_addr) + 801dacc: e0bff617 ldw r2,-40(fp) + 801dad0: 10000226 beq r2,zero,801dadc + 801dad4: e0bff417 ldw r2,-48(fp) + 801dad8: 1000021e bne r2,zero,801dae4 + { + return -EINVAL; + 801dadc: 00bffa84 movi r2,-22 + 801dae0: 00005f06 br 801dc60 + } + + qspi_flash_info = (alt_qspi_controller_dev*)flash_info; + 801dae4: e0bff617 ldw r2,-40(fp) + 801dae8: e0bff915 stw r2,-28(fp) + + /* make sure the write parameters are within the bounds of the flash */ + ret_code = alt_qspi_validate_read_write_arguments(qspi_flash_info, offset, length); + 801daec: e0bff517 ldw r2,-44(fp) + 801daf0: e0fff317 ldw r3,-52(fp) + 801daf4: 180d883a mov r6,r3 + 801daf8: 100b883a mov r5,r2 + 801dafc: e13ff917 ldw r4,-28(fp) + 801db00: 801df740 call 801df74 + 801db04: e0bfff15 stw r2,-4(fp) + + if(0 != ret_code) + 801db08: e0bfff17 ldw r2,-4(fp) + 801db0c: 10000226 beq r2,zero,801db18 + { + return ret_code; + 801db10: e0bfff17 ldw r2,-4(fp) + 801db14: 00005206 br 801dc60 + + /* + * This loop erases and writes data one sector at a time. We check for write completion + * before starting the next sector. + */ + for(i = offset/qspi_flash_info->sector_size ; i < qspi_flash_info->number_of_sectors; i++) + 801db18: e0fff517 ldw r3,-44(fp) + 801db1c: e0bff917 ldw r2,-28(fp) + 801db20: 10803417 ldw r2,208(r2) + 801db24: 100b883a mov r5,r2 + 801db28: 1809883a mov r4,r3 + 801db2c: 800cff80 call 800cff8 <__udivsi3> + 801db30: e0bffb15 stw r2,-20(fp) + 801db34: 00004306 br 801dc44 + { + alt_u32 block_offset = 0; /** block offset in byte addressing */ + 801db38: e03ff815 stw zero,-32(fp) + alt_u32 offset_within_current_sector = 0; /** offset into current sector to write */ + 801db3c: e03ffa15 stw zero,-24(fp) + alt_u32 length_to_write = 0; /** length to write to current sector */ + 801db40: e03ff715 stw zero,-36(fp) + + if(0 >= remaining_length) + 801db44: e0bffd17 ldw r2,-12(fp) + 801db48: 10004326 beq r2,zero,801dc58 + { + break; /* out of data to write */ + } + + /* calculate current sector/block offset in byte addressing */ + block_offset = write_offset & ~(qspi_flash_info->sector_size - 1); + 801db4c: e0bff917 ldw r2,-28(fp) + 801db50: 10803417 ldw r2,208(r2) + 801db54: 0085c83a sub r2,zero,r2 + 801db58: e0fffe17 ldw r3,-8(fp) + 801db5c: 1884703a and r2,r3,r2 + 801db60: e0bff815 stw r2,-32(fp) + + /* calculate offset into sector/block if there is one */ + if(block_offset != write_offset) + 801db64: e0fff817 ldw r3,-32(fp) + 801db68: e0bffe17 ldw r2,-8(fp) + 801db6c: 18800426 beq r3,r2,801db80 + { + offset_within_current_sector = write_offset - block_offset; + 801db70: e0fffe17 ldw r3,-8(fp) + 801db74: e0bff817 ldw r2,-32(fp) + 801db78: 1885c83a sub r2,r3,r2 + 801db7c: e0bffa15 stw r2,-24(fp) + } + + /* erase sector */ + ret_code = alt_qspi_controller_erase_block(flash_info, block_offset); + 801db80: e0bff817 ldw r2,-32(fp) + 801db84: 100b883a mov r5,r2 + 801db88: e13ff617 ldw r4,-40(fp) + 801db8c: 801d7580 call 801d758 + 801db90: e0bfff15 stw r2,-4(fp) + + if(0 != ret_code) + 801db94: e0bfff17 ldw r2,-4(fp) + 801db98: 10000226 beq r2,zero,801dba4 + { + return ret_code; + 801db9c: e0bfff17 ldw r2,-4(fp) + 801dba0: 00002f06 br 801dc60 + } + + /* calculate the byte size of data to be written in a sector */ + length_to_write = MIN(qspi_flash_info->sector_size - offset_within_current_sector, + 801dba4: e0bff917 ldw r2,-28(fp) + 801dba8: 10c03417 ldw r3,208(r2) + 801dbac: e0bffa17 ldw r2,-24(fp) + 801dbb0: 1887c83a sub r3,r3,r2 + 801dbb4: e0bffd17 ldw r2,-12(fp) + 801dbb8: 1880012e bgeu r3,r2,801dbc0 + 801dbbc: 1805883a mov r2,r3 + 801dbc0: e0bff715 stw r2,-36(fp) + remaining_length); + + /* write data to erased block */ + ret_code = alt_qspi_controller_write_block(flash_info, block_offset, write_offset, + 801dbc4: e13ff817 ldw r4,-32(fp) + 801dbc8: e17ffe17 ldw r5,-8(fp) + 801dbcc: e0fff417 ldw r3,-48(fp) + 801dbd0: e0bffc17 ldw r2,-16(fp) + 801dbd4: 1887883a add r3,r3,r2 + 801dbd8: e0bff717 ldw r2,-36(fp) + 801dbdc: d8800015 stw r2,0(sp) + 801dbe0: 180f883a mov r7,r3 + 801dbe4: 280d883a mov r6,r5 + 801dbe8: 200b883a mov r5,r4 + 801dbec: e13ff617 ldw r4,-40(fp) + 801dbf0: 801d87c0 call 801d87c + 801dbf4: e0bfff15 stw r2,-4(fp) + src_addr + buffer_offset, length_to_write); + + + if(0 != ret_code) + 801dbf8: e0bfff17 ldw r2,-4(fp) + 801dbfc: 10000226 beq r2,zero,801dc08 + { + return ret_code; + 801dc00: e0bfff17 ldw r2,-4(fp) + 801dc04: 00001606 br 801dc60 + } + + /* update remaining length and buffer_offset pointer */ + remaining_length -= length_to_write; + 801dc08: e0fffd17 ldw r3,-12(fp) + 801dc0c: e0bff717 ldw r2,-36(fp) + 801dc10: 1885c83a sub r2,r3,r2 + 801dc14: e0bffd15 stw r2,-12(fp) + buffer_offset += length_to_write; + 801dc18: e0fffc17 ldw r3,-16(fp) + 801dc1c: e0bff717 ldw r2,-36(fp) + 801dc20: 1885883a add r2,r3,r2 + 801dc24: e0bffc15 stw r2,-16(fp) + write_offset += length_to_write; + 801dc28: e0fffe17 ldw r3,-8(fp) + 801dc2c: e0bff717 ldw r2,-36(fp) + 801dc30: 1885883a add r2,r3,r2 + 801dc34: e0bffe15 stw r2,-8(fp) + for(i = offset/qspi_flash_info->sector_size ; i < qspi_flash_info->number_of_sectors; i++) + 801dc38: e0bffb17 ldw r2,-20(fp) + 801dc3c: 10800044 addi r2,r2,1 + 801dc40: e0bffb15 stw r2,-20(fp) + 801dc44: e0bff917 ldw r2,-28(fp) + 801dc48: 10803317 ldw r2,204(r2) + 801dc4c: e0fffb17 ldw r3,-20(fp) + 801dc50: 18bfb936 bltu r3,r2,801db38 + 801dc54: 00000106 br 801dc5c + break; /* out of data to write */ + 801dc58: 0001883a nop + } + + return ret_code; + 801dc5c: e0bfff17 ldw r2,-4(fp) +} + 801dc60: e037883a mov sp,fp + 801dc64: dfc00117 ldw ra,4(sp) + 801dc68: df000017 ldw fp,0(sp) + 801dc6c: dec00204 addi sp,sp,8 + 801dc70: f800283a ret + +0801dc74 : + alt_flash_dev *flash_info, /** device info */ + int offset, /** offset of read from base address */ + void *dest_addr, /** destination buffer */ + int length /** size of read */ +) +{ + 801dc74: defff804 addi sp,sp,-32 + 801dc78: dfc00715 stw ra,28(sp) + 801dc7c: df000615 stw fp,24(sp) + 801dc80: df000604 addi fp,sp,24 + 801dc84: e13ffd15 stw r4,-12(fp) + 801dc88: e17ffc15 stw r5,-16(fp) + 801dc8c: e1bffb15 stw r6,-20(fp) + 801dc90: e1fffa15 stw r7,-24(fp) + alt_32 ret_code = 0; + 801dc94: e03fff15 stw zero,-4(fp) + alt_qspi_controller_dev *qspi_flash_info = NULL; + 801dc98: e03ffe15 stw zero,-8(fp) + + /* return -EINVAL if flash_info and dest_addr are NULL */ + if(NULL == flash_info || NULL == dest_addr) + 801dc9c: e0bffd17 ldw r2,-12(fp) + 801dca0: 10000226 beq r2,zero,801dcac + 801dca4: e0bffb17 ldw r2,-20(fp) + 801dca8: 1000021e bne r2,zero,801dcb4 + { + return -EINVAL; + 801dcac: 00bffa84 movi r2,-22 + 801dcb0: 00001606 br 801dd0c + } + + qspi_flash_info = (alt_qspi_controller_dev*)flash_info; + 801dcb4: e0bffd17 ldw r2,-12(fp) + 801dcb8: e0bffe15 stw r2,-8(fp) + + /* validate arguments */ + ret_code = alt_qspi_validate_read_write_arguments(qspi_flash_info, offset, length); + 801dcbc: e0bffc17 ldw r2,-16(fp) + 801dcc0: e0fffa17 ldw r3,-24(fp) + 801dcc4: 180d883a mov r6,r3 + 801dcc8: 100b883a mov r5,r2 + 801dccc: e13ffe17 ldw r4,-8(fp) + 801dcd0: 801df740 call 801df74 + 801dcd4: e0bfff15 stw r2,-4(fp) + + /* copy data from flash to destination address */ + if(0 == ret_code) + 801dcd8: e0bfff17 ldw r2,-4(fp) + 801dcdc: 10000a1e bne r2,zero,801dd08 + { + memcpy(dest_addr, (alt_u8*)qspi_flash_info->data_base + offset, length); + 801dce0: e0bffe17 ldw r2,-8(fp) + 801dce4: 10c02e17 ldw r3,184(r2) + 801dce8: e0bffc17 ldw r2,-16(fp) + 801dcec: 1885883a add r2,r3,r2 + 801dcf0: 1007883a mov r3,r2 + 801dcf4: e0bffa17 ldw r2,-24(fp) + 801dcf8: 100d883a mov r6,r2 + 801dcfc: 180b883a mov r5,r3 + 801dd00: e13ffb17 ldw r4,-20(fp) + 801dd04: 80086b80 call 80086b8 + } + + return ret_code; + 801dd08: e0bfff17 ldw r2,-4(fp) +} + 801dd0c: e037883a mov sp,fp + 801dd10: dfc00117 ldw ra,4(sp) + 801dd14: df000017 ldw fp,0(sp) + 801dd18: dec00204 addi sp,sp,8 + 801dd1c: f800283a ret + +0801dd20 : + * 0 -> success + * -EINVAL -> Invalid arguments. + * -ENODEV -> System is configured incorrectly. +**/ +alt_32 altera_qspi_controller_init(alt_qspi_controller_dev *flash) +{ + 801dd20: defffa04 addi sp,sp,-24 + 801dd24: dfc00515 stw ra,20(sp) + 801dd28: df000415 stw fp,16(sp) + 801dd2c: df000404 addi fp,sp,16 + 801dd30: e13ffc15 stw r4,-16(fp) + alt_u32 silicon_id = 0; + 801dd34: e03fff15 stw zero,-4(fp) + alt_u32 size_in_bytes = 0; + 801dd38: e03ffd15 stw zero,-12(fp) + alt_u32 number_of_sectors = 0; + 801dd3c: e03ffe15 stw zero,-8(fp) + + /* return -EINVAL if flash is NULL */ + if(NULL == flash) + 801dd40: e0bffc17 ldw r2,-16(fp) + 801dd44: 1000021e bne r2,zero,801dd50 + { + return -EINVAL; + 801dd48: 00bffa84 movi r2,-22 + 801dd4c: 00008406 br 801df60 + } + + /* return -ENODEV if CSR slave is not attached */ + if(NULL == (void *)flash->csr_base) + 801dd50: e0bffc17 ldw r2,-16(fp) + 801dd54: 10803017 ldw r2,192(r2) + 801dd58: 1000021e bne r2,zero,801dd64 + { + return -ENODEV; + 801dd5c: 00bffb44 movi r2,-19 + 801dd60: 00007f06 br 801df60 + * + * In both cases, we can determine the number of sectors, which we can use + * to calculate a size. We compare that size to the system.h value to make sure + * the QSPI soft IP was configured correctly. + */ + if(0 == flash->is_epcs) + 801dd64: e0bffc17 ldw r2,-16(fp) + 801dd68: 10803217 ldw r2,200(r2) + 801dd6c: 1000351e bne r2,zero,801de44 + { + /* If we're an EPCQ or QSPI, we read QSPI_RD_RDID for the silicon ID */ + silicon_id = IORD_ALTERA_QSPI_CONTROLLER_RDID(flash->csr_base); + 801dd70: e0bffc17 ldw r2,-16(fp) + 801dd74: 10803017 ldw r2,192(r2) + 801dd78: 10800204 addi r2,r2,8 + 801dd7c: 10800037 ldwio r2,0(r2) + 801dd80: e0bfff15 stw r2,-4(fp) + silicon_id &= ALTERA_QSPI_CONTROLLER_RDID_MASK; + 801dd84: e0bfff17 ldw r2,-4(fp) + 801dd88: 10803fcc andi r2,r2,255 + 801dd8c: e0bfff15 stw r2,-4(fp) + + /* Determine which EPCQ/QSPI device so we can figure out the number of sectors */ + /*EPCQ and QSPI share the same ID for the same capacity*/ + switch(silicon_id) + 801dd90: e0bfff17 ldw r2,-4(fp) + 801dd94: 10bffac4 addi r2,r2,-21 + 801dd98: 10c00368 cmpgeui r3,r2,13 + 801dd9c: 1800271e bne r3,zero,801de3c + 801dda0: 100690ba slli r3,r2,2 + 801dda4: 008200b4 movhi r2,2050 + 801dda8: 1885883a add r2,r3,r2 + 801ddac: 10b76d17 ldw r2,-8780(r2) + 801ddb0: 1000683a jmp r2 + 801ddb4: 0801dde8 cmpgeui zero,at,1911 + 801ddb8: 0801ddf4 orhi zero,at,1911 + 801ddbc: 0801de00 call 801de0 + 801ddc0: 0801de0c andi zero,at,1912 + 801ddc4: 0801de18 cmpnei zero,at,1912 + 801ddc8: 0801de3c xorhi zero,at,1912 + 801ddcc: 0801de3c xorhi zero,at,1912 + 801ddd0: 0801de3c xorhi zero,at,1912 + 801ddd4: 0801de3c xorhi zero,at,1912 + 801ddd8: 0801de3c xorhi zero,at,1912 + 801dddc: 0801de3c xorhi zero,at,1912 + 801dde0: 0801de24 muli zero,at,1912 + 801dde4: 0801de30 cmpltui zero,at,1912 + { + case ALTERA_QSPI_CONTROLLER_RDID_QSPI16: + { + number_of_sectors = 32; + 801dde8: 00800804 movi r2,32 + 801ddec: e0bffe15 stw r2,-8(fp) + break; + 801ddf0: 00003006 br 801deb4 + } + case ALTERA_QSPI_CONTROLLER_RDID_QSPI32: + { + number_of_sectors = 64; + 801ddf4: 00801004 movi r2,64 + 801ddf8: e0bffe15 stw r2,-8(fp) + break; + 801ddfc: 00002d06 br 801deb4 + } + case ALTERA_QSPI_CONTROLLER_RDID_QSPI64: + { + number_of_sectors = 128; + 801de00: 00802004 movi r2,128 + 801de04: e0bffe15 stw r2,-8(fp) + break; + 801de08: 00002a06 br 801deb4 + } + case ALTERA_QSPI_CONTROLLER_RDID_QSPI128: + { + number_of_sectors = 256; + 801de0c: 00804004 movi r2,256 + 801de10: e0bffe15 stw r2,-8(fp) + break; + 801de14: 00002706 br 801deb4 + } + case ALTERA_QSPI_CONTROLLER_RDID_QSPI256: + { + number_of_sectors = 512; + 801de18: 00808004 movi r2,512 + 801de1c: e0bffe15 stw r2,-8(fp) + break; + 801de20: 00002406 br 801deb4 + } + case ALTERA_QSPI_CONTROLLER_RDID_QSPI512: + { + number_of_sectors = 1024; + 801de24: 00810004 movi r2,1024 + 801de28: e0bffe15 stw r2,-8(fp) + break; + 801de2c: 00002106 br 801deb4 + } + case ALTERA_QSPI_CONTROLLER_RDID_QSPI1024: + { + number_of_sectors = 2048; + 801de30: 00820004 movi r2,2048 + 801de34: e0bffe15 stw r2,-8(fp) + break; + 801de38: 00001e06 br 801deb4 + } + default: + { + return -ENODEV; + 801de3c: 00bffb44 movi r2,-19 + 801de40: 00004706 br 801df60 + } + } + } + else { + /* If we're an EPCS, we read QSPI_RD_SID for the silicon ID */ + silicon_id = IORD_ALTERA_QSPI_CONTROLLER_SID(flash->csr_base); + 801de44: e0bffc17 ldw r2,-16(fp) + 801de48: 10803017 ldw r2,192(r2) + 801de4c: 10800104 addi r2,r2,4 + 801de50: 10800037 ldwio r2,0(r2) + 801de54: e0bfff15 stw r2,-4(fp) + silicon_id &= ALTERA_QSPI_CONTROLLER_SID_MASK; + 801de58: e0bfff17 ldw r2,-4(fp) + 801de5c: 10803fcc andi r2,r2,255 + 801de60: e0bfff15 stw r2,-4(fp) + + /* Determine which EPCS device so we can figure out various properties */ + switch(silicon_id) + 801de64: e0bfff17 ldw r2,-4(fp) + 801de68: 108005a0 cmpeqi r2,r2,22 + 801de6c: 1000091e bne r2,zero,801de94 + 801de70: e0bfff17 ldw r2,-4(fp) + 801de74: 10800620 cmpeqi r2,r2,24 + 801de78: 1000091e bne r2,zero,801dea0 + 801de7c: e0bfff17 ldw r2,-4(fp) + 801de80: 10800518 cmpnei r2,r2,20 + 801de84: 1000091e bne r2,zero,801deac + { + case ALTERA_QSPI_CONTROLLER_SID_EPCS16: + { + number_of_sectors = 32; + 801de88: 00800804 movi r2,32 + 801de8c: e0bffe15 stw r2,-8(fp) + break; + 801de90: 00000806 br 801deb4 + } + case ALTERA_QSPI_CONTROLLER_SID_EPCS64: + { + number_of_sectors = 128; + 801de94: 00802004 movi r2,128 + 801de98: e0bffe15 stw r2,-8(fp) + break; + 801de9c: 00000506 br 801deb4 + } + case ALTERA_QSPI_CONTROLLER_SID_EPCS128: + { + number_of_sectors = 256; + 801dea0: 00804004 movi r2,256 + 801dea4: e0bffe15 stw r2,-8(fp) + break; + 801dea8: 00000206 br 801deb4 + } + default: + { + return -ENODEV; + 801deac: 00bffb44 movi r2,-19 + 801deb0: 00002b06 br 801df60 + } + } + } + + /* Calculate size of flash based on number of sectors */ + size_in_bytes = number_of_sectors * flash->sector_size; + 801deb4: e0bffc17 ldw r2,-16(fp) + 801deb8: 10803417 ldw r2,208(r2) + 801debc: e0fffe17 ldw r3,-8(fp) + 801dec0: 1885383a mul r2,r3,r2 + 801dec4: e0bffd15 stw r2,-12(fp) + /* + * Make sure calculated size is the same size given in system.h + * Also check number of sectors is the same number given in system.h + * Otherwise the QSPI IP was not configured correctly + */ + if( size_in_bytes != flash->size_in_bytes || + 801dec8: e0bffc17 ldw r2,-16(fp) + 801decc: 10803117 ldw r2,196(r2) + 801ded0: e0fffd17 ldw r3,-12(fp) + 801ded4: 1880041e bne r3,r2,801dee8 + number_of_sectors != flash->number_of_sectors) + 801ded8: e0bffc17 ldw r2,-16(fp) + 801dedc: 10803317 ldw r2,204(r2) + if( size_in_bytes != flash->size_in_bytes || + 801dee0: e0fffe17 ldw r3,-8(fp) + 801dee4: 18800426 beq r3,r2,801def8 + { + flash->dev.number_of_regions = 0; + 801dee8: e0bffc17 ldw r2,-16(fp) + 801deec: 10000c15 stw zero,48(r2) + return -ENODEV; + 801def0: 00bffb44 movi r2,-19 + 801def4: 00001a06 br 801df60 + } + else + { + flash->silicon_id = silicon_id; + 801def8: e0bffc17 ldw r2,-16(fp) + 801defc: e0ffff17 ldw r3,-4(fp) + 801df00: 10c03615 stw r3,216(r2) + flash->number_of_sectors = number_of_sectors; + 801df04: e0bffc17 ldw r2,-16(fp) + 801df08: e0fffe17 ldw r3,-8(fp) + 801df0c: 10c03315 stw r3,204(r2) + + /* + * populate fields of region_info required to conform to HAL API + * create 1 region that composed of "number_of_sectors" blocks + */ + flash->dev.number_of_regions = 1; + 801df10: e0bffc17 ldw r2,-16(fp) + 801df14: 00c00044 movi r3,1 + 801df18: 10c00c15 stw r3,48(r2) + flash->dev.region_info[0].offset = 0; + 801df1c: e0bffc17 ldw r2,-16(fp) + 801df20: 10000d15 stw zero,52(r2) + flash->dev.region_info[0].region_size = size_in_bytes; + 801df24: e0fffd17 ldw r3,-12(fp) + 801df28: e0bffc17 ldw r2,-16(fp) + 801df2c: 10c00e15 stw r3,56(r2) + flash->dev.region_info[0].number_of_blocks = number_of_sectors; + 801df30: e0fffe17 ldw r3,-8(fp) + 801df34: e0bffc17 ldw r2,-16(fp) + 801df38: 10c00f15 stw r3,60(r2) + flash->dev.region_info[0].block_size = flash->sector_size; + 801df3c: e0bffc17 ldw r2,-16(fp) + 801df40: 10803417 ldw r2,208(r2) + 801df44: 1007883a mov r3,r2 + 801df48: e0bffc17 ldw r2,-16(fp) + 801df4c: 10c01015 stw r3,64(r2) + /* + * Register this device as a valid flash device type + * + * Only register the device if it's configured correctly. + */ + alt_flash_device_register(&(flash->dev)); + 801df50: e0bffc17 ldw r2,-16(fp) + 801df54: 1009883a mov r4,r2 + 801df58: 801d5880 call 801d588 + + + return 0; + 801df5c: 0005883a mov r2,zero +} + 801df60: e037883a mov sp,fp + 801df64: dfc00117 ldw ra,4(sp) + 801df68: df000017 ldw fp,0(sp) + 801df6c: dec00204 addi sp,sp,8 + 801df70: f800283a ret + +0801df74 : +( + alt_qspi_controller_dev *flash_info, /** device info */ + alt_u32 offset, /** offset of read/write */ + alt_u32 length /** length of read/write */ +) +{ + 801df74: defff904 addi sp,sp,-28 + 801df78: df000615 stw fp,24(sp) + 801df7c: df000604 addi fp,sp,24 + 801df80: e13ffc15 stw r4,-16(fp) + 801df84: e17ffb15 stw r5,-20(fp) + 801df88: e1bffa15 stw r6,-24(fp) + alt_qspi_controller_dev *qspi_flash_info = NULL; + 801df8c: e03fff15 stw zero,-4(fp) + alt_u32 start_address = 0; + 801df90: e03ffe15 stw zero,-8(fp) + alt_32 end_address = 0; + 801df94: e03ffd15 stw zero,-12(fp) + + /* return -EINVAL if flash_info is NULL */ + if(NULL == flash_info) + 801df98: e0bffc17 ldw r2,-16(fp) + 801df9c: 1000021e bne r2,zero,801dfa8 + { + return -EINVAL; + 801dfa0: 00bffa84 movi r2,-22 + 801dfa4: 00001606 br 801e000 + } + + qspi_flash_info = (alt_qspi_controller_dev*)flash_info; + 801dfa8: e0bffc17 ldw r2,-16(fp) + 801dfac: e0bfff15 stw r2,-4(fp) + + start_address = qspi_flash_info->data_base + offset; /** first address of read or write */ + 801dfb0: e0bfff17 ldw r2,-4(fp) + 801dfb4: 10802e17 ldw r2,184(r2) + 801dfb8: e0fffb17 ldw r3,-20(fp) + 801dfbc: 1885883a add r2,r3,r2 + 801dfc0: e0bffe15 stw r2,-8(fp) + end_address = start_address + length; /** last address of read or write (not inclusive) */ + 801dfc4: e0fffe17 ldw r3,-8(fp) + 801dfc8: e0bffa17 ldw r2,-24(fp) + 801dfcc: 1885883a add r2,r3,r2 + 801dfd0: e0bffd15 stw r2,-12(fp) + + /* make sure start and end address is less then the end address of the flash */ + if( + start_address >= qspi_flash_info->data_end || + 801dfd4: e0bfff17 ldw r2,-4(fp) + 801dfd8: 10802f17 ldw r2,188(r2) + if( + 801dfdc: e0fffe17 ldw r3,-8(fp) + 801dfe0: 1880042e bgeu r3,r2,801dff4 + end_address >= qspi_flash_info->data_end || + 801dfe4: e0bfff17 ldw r2,-4(fp) + 801dfe8: 10802f17 ldw r2,188(r2) + 801dfec: e0fffd17 ldw r3,-12(fp) + offset < 0 || + 801dff0: 18800236 bltu r3,r2,801dffc + length < 0 + ) + { + return -EINVAL; + 801dff4: 00bffa84 movi r2,-22 + 801dff8: 00000106 br 801e000 + } + + return 0; + 801dffc: 0005883a mov r2,zero +} + 801e000: e037883a mov sp,fp + 801e004: df000017 ldw fp,0(sp) + 801e008: dec00104 addi sp,sp,4 + 801e00c: f800283a ret + +0801e010 : + * 0 -> success + * -EINVAL -> Invalid arguments + * -ETIME -> Time out and skipping the looping after 0.7 sec. + */ +alt_32 static alt_qspi_poll_for_write_in_progress(alt_qspi_controller_dev* qspi_flash_info) +{ + 801e010: defffb04 addi sp,sp,-20 + 801e014: dfc00415 stw ra,16(sp) + 801e018: df000315 stw fp,12(sp) + 801e01c: df000304 addi fp,sp,12 + 801e020: e13ffd15 stw r4,-12(fp) + /* we'll want to implement timeout if a timeout value is specified */ +#if ALTERA_QSPI_CONTROLLER_1US_TIMEOUT_VALUE > 0 + alt_u32 timeout = ALTERA_QSPI_CONTROLLER_1US_TIMEOUT_VALUE; + 801e024: 008002f4 movhi r2,11 + 801e028: 10ab9804 addi r2,r2,-20896 + 801e02c: e0bffe15 stw r2,-8(fp) + alt_u16 counter = 0; + 801e030: e03fff8d sth zero,-2(fp) +#endif + + /* return -EINVAL if qspi_flash_info is NULL */ + if(NULL == qspi_flash_info) + 801e034: e0bffd17 ldw r2,-12(fp) + 801e038: 10000c1e bne r2,zero,801e06c + { + return -EINVAL; + 801e03c: 00bffa84 movi r2,-22 + 801e040: 00001106 br 801e088 + /* while Write in Progress bit is set, we wait */ + while((IORD_ALTERA_QSPI_CONTROLLER_STATUS(qspi_flash_info->csr_base) & + ALTERA_QSPI_CONTROLLER_STATUS_WIP_MASK) == + ALTERA_QSPI_CONTROLLER_STATUS_WIP_BUSY) + { + alt_busy_sleep(1); /* delay 1us */ + 801e044: 01000044 movi r4,1 + 801e048: 8036f5c0 call 8036f5c +#if ALTERA_QSPI_CONTROLLER_1US_TIMEOUT_VALUE > 0 + if(timeout <= counter ) + 801e04c: e0ffff8b ldhu r3,-2(fp) + 801e050: e0bffe17 ldw r2,-8(fp) + 801e054: 18800236 bltu r3,r2,801e060 + { + return -ETIME; + 801e058: 00bff084 movi r2,-62 + 801e05c: 00000a06 br 801e088 + } + + counter++; + 801e060: e0bfff8b ldhu r2,-2(fp) + 801e064: 10800044 addi r2,r2,1 + 801e068: e0bfff8d sth r2,-2(fp) + while((IORD_ALTERA_QSPI_CONTROLLER_STATUS(qspi_flash_info->csr_base) & + 801e06c: e0bffd17 ldw r2,-12(fp) + 801e070: 10803017 ldw r2,192(r2) + 801e074: 10800037 ldwio r2,0(r2) + 801e078: 1080004c andi r2,r2,1 + 801e07c: 10800060 cmpeqi r2,r2,1 + 801e080: 103ff01e bne r2,zero,801e044 +#endif + + } + + return 0; + 801e084: 0005883a mov r2,zero +} + 801e088: e037883a mov sp,fp + 801e08c: dfc00117 ldw ra,4(sp) + 801e090: df000017 ldw fp,0(sp) + 801e094: dec00204 addi sp,sp,8 + 801e098: f800283a ret + +0801e09c : +{ + 801e09c: defffe04 addi sp,sp,-8 + 801e0a0: dfc00115 stw ra,4(sp) + 801e0a4: df000015 stw fp,0(sp) + 801e0a8: d839883a mov fp,sp + return ((alt_errno) ? alt_errno() : &errno); + 801e0ac: d0a02717 ldw r2,-32612(gp) + 801e0b0: 10000326 beq r2,zero,801e0c0 + 801e0b4: d0a02717 ldw r2,-32612(gp) + 801e0b8: 103ee83a callr r2 + 801e0bc: 00000106 br 801e0c4 + 801e0c0: d0a04204 addi r2,gp,-32504 +} + 801e0c4: e037883a mov sp,fp + 801e0c8: dfc00117 ldw ra,4(sp) + 801e0cc: df000017 ldw fp,0(sp) + 801e0d0: dec00204 addi sp,sp,8 + 801e0d4: f800283a ret + +0801e0d8 : + */ +static int alt_msgdma_write_standard_descriptor ( + alt_u32 *csr_base, + alt_u32 *descriptor_base, + alt_msgdma_standard_descriptor *descriptor) +{ + 801e0d8: defffc04 addi sp,sp,-16 + 801e0dc: df000315 stw fp,12(sp) + 801e0e0: df000304 addi fp,sp,12 + 801e0e4: e13fff15 stw r4,-4(fp) + 801e0e8: e17ffe15 stw r5,-8(fp) + 801e0ec: e1bffd15 stw r6,-12(fp) + if (0 != (IORD_ALTERA_MSGDMA_CSR_STATUS(csr_base) & + 801e0f0: e0bfff17 ldw r2,-4(fp) + 801e0f4: 10800037 ldwio r2,0(r2) + 801e0f8: 1080010c andi r2,r2,4 + 801e0fc: 10000226 beq r2,zero,801e108 + ALTERA_MSGDMA_CSR_DESCRIPTOR_BUFFER_FULL_MASK)) + { + /*at least one descriptor buffer is full, returning so that this function + is non-blocking*/ + return -ENOSPC; + 801e100: 00bff904 movi r2,-28 + 801e104: 00001506 br 801e15c + } + + IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS(descriptor_base, + 801e108: e0bffd17 ldw r2,-12(fp) + 801e10c: 10800017 ldw r2,0(r2) + 801e110: 1007883a mov r3,r2 + 801e114: e0bffe17 ldw r2,-8(fp) + 801e118: 10c00035 stwio r3,0(r2) + (alt_u32)descriptor->read_address); + IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS(descriptor_base, + 801e11c: e0bffe17 ldw r2,-8(fp) + 801e120: 10800104 addi r2,r2,4 + 801e124: e0fffd17 ldw r3,-12(fp) + 801e128: 18c00117 ldw r3,4(r3) + 801e12c: 10c00035 stwio r3,0(r2) + ( alt_u32)descriptor->write_address); + IOWR_ALTERA_MSGDMA_DESCRIPTOR_LENGTH(descriptor_base, + 801e130: e0bffe17 ldw r2,-8(fp) + 801e134: 10800204 addi r2,r2,8 + 801e138: e0fffd17 ldw r3,-12(fp) + 801e13c: 18c00217 ldw r3,8(r3) + 801e140: 10c00035 stwio r3,0(r2) + descriptor->transfer_length); + IOWR_ALTERA_MSGDMA_DESCRIPTOR_CONTROL_STANDARD(descriptor_base, + 801e144: e0bffe17 ldw r2,-8(fp) + 801e148: 10800304 addi r2,r2,12 + 801e14c: e0fffd17 ldw r3,-12(fp) + 801e150: 18c00317 ldw r3,12(r3) + 801e154: 10c00035 stwio r3,0(r2) + descriptor->control); + return 0; + 801e158: 0005883a mov r2,zero +} + 801e15c: e037883a mov sp,fp + 801e160: df000017 ldw fp,0(sp) + 801e164: dec00104 addi sp,sp,4 + 801e168: f800283a ret + +0801e16c : + */ +static int alt_msgdma_write_extended_descriptor ( + alt_u32 *csr_base, + alt_u32 *descriptor_base, + alt_msgdma_extended_descriptor *descriptor) +{ + 801e16c: defffc04 addi sp,sp,-16 + 801e170: df000315 stw fp,12(sp) + 801e174: df000304 addi fp,sp,12 + 801e178: e13fff15 stw r4,-4(fp) + 801e17c: e17ffe15 stw r5,-8(fp) + 801e180: e1bffd15 stw r6,-12(fp) + if (0 != (IORD_ALTERA_MSGDMA_CSR_STATUS(csr_base) & + 801e184: e0bfff17 ldw r2,-4(fp) + 801e188: 10800037 ldwio r2,0(r2) + 801e18c: 1080010c andi r2,r2,4 + 801e190: 10000226 beq r2,zero,801e19c + ALTERA_MSGDMA_CSR_DESCRIPTOR_BUFFER_FULL_MASK)) + { + /*at least one descriptor buffer is full, returning so that this function + is non-blocking*/ + return -ENOSPC; + 801e194: 00bff904 movi r2,-28 + 801e198: 00003b06 br 801e288 + } + + IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS( + 801e19c: e0bffd17 ldw r2,-12(fp) + 801e1a0: 10800017 ldw r2,0(r2) + 801e1a4: 1007883a mov r3,r2 + 801e1a8: e0bffe17 ldw r2,-8(fp) + 801e1ac: 10c00035 stwio r3,0(r2) + descriptor_base, + (alt_u32)descriptor->read_address_low); + IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS( + 801e1b0: e0bffe17 ldw r2,-8(fp) + 801e1b4: 10800104 addi r2,r2,4 + 801e1b8: e0fffd17 ldw r3,-12(fp) + 801e1bc: 18c00117 ldw r3,4(r3) + 801e1c0: 10c00035 stwio r3,0(r2) + descriptor_base, + (alt_u32)descriptor->write_address_low); + IOWR_ALTERA_MSGDMA_DESCRIPTOR_LENGTH( + 801e1c4: e0bffe17 ldw r2,-8(fp) + 801e1c8: 10800204 addi r2,r2,8 + 801e1cc: e0fffd17 ldw r3,-12(fp) + 801e1d0: 18c00217 ldw r3,8(r3) + 801e1d4: 10c00035 stwio r3,0(r2) + descriptor_base, + descriptor->transfer_length); + IOWR_ALTERA_MSGDMA_DESCRIPTOR_SEQUENCE_NUMBER( + 801e1d8: e0bffe17 ldw r2,-8(fp) + 801e1dc: 10800304 addi r2,r2,12 + 801e1e0: e0fffd17 ldw r3,-12(fp) + 801e1e4: 18c0030b ldhu r3,12(r3) + 801e1e8: 18ffffcc andi r3,r3,65535 + 801e1ec: 10c0002d sthio r3,0(r2) + descriptor_base, + descriptor->sequence_number); + IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_BURST( + 801e1f0: e0bffe17 ldw r2,-8(fp) + 801e1f4: 10800384 addi r2,r2,14 + 801e1f8: e0fffd17 ldw r3,-12(fp) + 801e1fc: 18c00383 ldbu r3,14(r3) + 801e200: 18c03fcc andi r3,r3,255 + 801e204: 10c00025 stbio r3,0(r2) + descriptor_base, + descriptor->read_burst_count); + IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_BURST( + 801e208: e0bffe17 ldw r2,-8(fp) + 801e20c: 108003c4 addi r2,r2,15 + 801e210: e0fffd17 ldw r3,-12(fp) + 801e214: 18c003c3 ldbu r3,15(r3) + 801e218: 18c03fcc andi r3,r3,255 + 801e21c: 10c00025 stbio r3,0(r2) + descriptor_base, + descriptor->write_burst_count); + IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_STRIDE( + 801e220: e0bffe17 ldw r2,-8(fp) + 801e224: 10800404 addi r2,r2,16 + 801e228: e0fffd17 ldw r3,-12(fp) + 801e22c: 18c0040b ldhu r3,16(r3) + 801e230: 18ffffcc andi r3,r3,65535 + 801e234: 10c0002d sthio r3,0(r2) + descriptor_base, + descriptor->read_stride); + IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_STRIDE( + 801e238: e0bffe17 ldw r2,-8(fp) + 801e23c: 10800484 addi r2,r2,18 + 801e240: e0fffd17 ldw r3,-12(fp) + 801e244: 18c0048b ldhu r3,18(r3) + 801e248: 18ffffcc andi r3,r3,65535 + 801e24c: 10c0002d sthio r3,0(r2) + descriptor_base, + descriptor->write_stride); + IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS_HIGH(descriptor_base, 0); + 801e250: e0bffe17 ldw r2,-8(fp) + 801e254: 10800504 addi r2,r2,20 + 801e258: 0007883a mov r3,zero + 801e25c: 10c00035 stwio r3,0(r2) + IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS_HIGH(descriptor_base, 0); + 801e260: e0bffe17 ldw r2,-8(fp) + 801e264: 10800604 addi r2,r2,24 + 801e268: 0007883a mov r3,zero + 801e26c: 10c00035 stwio r3,0(r2) + IOWR_ALTERA_MSGDMA_DESCRIPTOR_CONTROL_ENHANCED( + 801e270: e0bffe17 ldw r2,-8(fp) + 801e274: 10800704 addi r2,r2,28 + 801e278: e0fffd17 ldw r3,-12(fp) + 801e27c: 18c00717 ldw r3,28(r3) + 801e280: 10c00035 stwio r3,0(r2) + descriptor_base, + descriptor->control); + return 0; + 801e284: 0005883a mov r2,zero +} + 801e288: e037883a mov sp,fp + 801e28c: df000017 ldw fp,0(sp) + 801e290: dec00104 addi sp,sp,4 + 801e294: f800283a ret + +0801e298 : + * alt_msgdma_irq() + * + * Interrupt handler for the Modular Scatter-Gather DMA controller. + */ +static void alt_msgdma_irq(void *context) +{ + 801e298: defff804 addi sp,sp,-32 + 801e29c: dfc00715 stw ra,28(sp) + 801e2a0: df000615 stw fp,24(sp) + 801e2a4: df000604 addi fp,sp,24 + 801e2a8: e13ffa15 stw r4,-24(fp) + alt_msgdma_dev *dev = (alt_msgdma_dev *) context; + 801e2ac: e0bffa17 ldw r2,-24(fp) + 801e2b0: e0bfff15 stw r2,-4(fp) + alt_irq_context cpu_sr; + alt_u32 temporary_control; + + + /* disable global interrupt*/ + if (dev->prefetcher_enable) + 801e2b4: e0bfff17 ldw r2,-4(fp) + 801e2b8: 10801783 ldbu r2,94(r2) + 801e2bc: 10803fcc andi r2,r2,255 + 801e2c0: 10001126 beq r2,zero,801e308 + { + temporary_control = + IORD_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base) + 801e2c4: e0bfff17 ldw r2,-4(fp) + 801e2c8: 10800617 ldw r2,24(r2) + 801e2cc: 10800037 ldwio r2,0(r2) + & ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_CLR_MASK; + 801e2d0: 1007883a mov r3,r2 + temporary_control = + 801e2d4: 00bffdc4 movi r2,-9 + 801e2d8: 1884703a and r2,r3,r2 + 801e2dc: e0bffe15 stw r2,-8(fp) + + IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, + 801e2e0: e0bfff17 ldw r2,-4(fp) + 801e2e4: 10800617 ldw r2,24(r2) + 801e2e8: e0fffe17 ldw r3,-8(fp) + 801e2ec: 10c00035 stwio r3,0(r2) + temporary_control); + + /* clear the IRQ status- W1C */ + IOWR_ALT_MSGDMA_PREFETCHER_STATUS(dev->prefetcher_base, + 801e2f0: e0bfff17 ldw r2,-4(fp) + 801e2f4: 10800617 ldw r2,24(r2) + 801e2f8: 10800404 addi r2,r2,16 + 801e2fc: 00c00044 movi r3,1 + 801e300: 10c00035 stwio r3,0(r2) + 801e304: 00001106 br 801e34c + ALT_MSGDMA_PREFETCHER_STATUS_IRQ_SET_MASK); + } + else + { + temporary_control = IORD_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base) + 801e308: e0bfff17 ldw r2,-4(fp) + 801e30c: 10800317 ldw r2,12(r2) + 801e310: 10800104 addi r2,r2,4 + 801e314: 10800037 ldwio r2,0(r2) + & (~ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK); + 801e318: 1007883a mov r3,r2 + temporary_control = IORD_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base) + 801e31c: 00bffbc4 movi r2,-17 + 801e320: 1884703a and r2,r3,r2 + 801e324: e0bffe15 stw r2,-8(fp) + + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, temporary_control); + 801e328: e0bfff17 ldw r2,-4(fp) + 801e32c: 10800317 ldw r2,12(r2) + 801e330: 10800104 addi r2,r2,4 + 801e334: e0fffe17 ldw r3,-8(fp) + 801e338: 10c00035 stwio r3,0(r2) + /* clear the IRQ status */ + IOWR_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base, + 801e33c: e0bfff17 ldw r2,-4(fp) + 801e340: 10800317 ldw r2,12(r2) + 801e344: 00c08004 movi r3,512 + 801e348: 10c00035 stwio r3,0(r2) + * Other interrupts are explicitly disabled if callbacks + * are registered because there is no guarantee that they are + * pre-emption-safe. This allows the driver to support + * interrupt pre-emption. + */ + if(dev->callback) + 801e34c: e0bfff17 ldw r2,-4(fp) + 801e350: 10800b17 ldw r2,44(r2) + 801e354: 10001226 beq r2,zero,801e3a0 + NIOS2_READ_STATUS (context); + 801e358: 0005303a rdctl r2,status + 801e35c: e0bffb15 stw r2,-20(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 801e360: e0fffb17 ldw r3,-20(fp) + 801e364: 00bfff84 movi r2,-2 + 801e368: 1884703a and r2,r3,r2 + 801e36c: 1001703a wrctl status,r2 + return context; + 801e370: e0bffb17 ldw r2,-20(fp) + { + cpu_sr = alt_irq_disable_all(); + 801e374: e0bffd15 stw r2,-12(fp) + dev->callback (dev->callback_context); + 801e378: e0bfff17 ldw r2,-4(fp) + 801e37c: 10800b17 ldw r2,44(r2) + 801e380: e0ffff17 ldw r3,-4(fp) + 801e384: 18c00c17 ldw r3,48(r3) + 801e388: 1809883a mov r4,r3 + 801e38c: 103ee83a callr r2 + 801e390: e0bffd17 ldw r2,-12(fp) + 801e394: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 801e398: e0bffc17 ldw r2,-16(fp) + 801e39c: 1001703a wrctl status,r2 + alt_irq_enable_all(cpu_sr); + } + + /* enable global interrupt */ + if (dev->prefetcher_enable) + 801e3a0: e0bfff17 ldw r2,-4(fp) + 801e3a4: 10801783 ldbu r2,94(r2) + 801e3a8: 10803fcc andi r2,r2,255 + 801e3ac: 10000a26 beq r2,zero,801e3d8 + { + temporary_control = + IORD_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base) + 801e3b0: e0bfff17 ldw r2,-4(fp) + 801e3b4: 10800617 ldw r2,24(r2) + 801e3b8: 10800037 ldwio r2,0(r2) + | ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_SET_MASK; + 801e3bc: 10800214 ori r2,r2,8 + temporary_control = + 801e3c0: e0bffe15 stw r2,-8(fp) + + IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, + 801e3c4: e0bfff17 ldw r2,-4(fp) + 801e3c8: 10800617 ldw r2,24(r2) + 801e3cc: e0fffe17 ldw r3,-8(fp) + 801e3d0: 10c00035 stwio r3,0(r2) + | (ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK); + + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, temporary_control); + } + + return; + 801e3d4: 00000c06 br 801e408 + temporary_control = IORD_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base) + 801e3d8: e0bfff17 ldw r2,-4(fp) + 801e3dc: 10800317 ldw r2,12(r2) + 801e3e0: 10800104 addi r2,r2,4 + 801e3e4: 10800037 ldwio r2,0(r2) + | (ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK); + 801e3e8: 10800414 ori r2,r2,16 + temporary_control = IORD_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base) + 801e3ec: e0bffe15 stw r2,-8(fp) + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, temporary_control); + 801e3f0: e0bfff17 ldw r2,-4(fp) + 801e3f4: 10800317 ldw r2,12(r2) + 801e3f8: 10800104 addi r2,r2,4 + 801e3fc: e0fffe17 ldw r3,-8(fp) + 801e400: 10c00035 stwio r3,0(r2) + return; + 801e404: 0001883a nop +} + 801e408: e037883a mov sp,fp + 801e40c: dfc00117 ldw ra,4(sp) + 801e410: df000017 ldw fp,0(sp) + 801e414: dec00204 addi sp,sp,8 + 801e418: f800283a ret + +0801e41c : + alt_msgdma_standard_descriptor *descriptor, + alt_u32 *read_address, + alt_u32 *write_address, + alt_u32 length, + alt_u32 control) +{ + 801e41c: defffb04 addi sp,sp,-20 + 801e420: df000415 stw fp,16(sp) + 801e424: df000404 addi fp,sp,16 + 801e428: e13fff15 stw r4,-4(fp) + 801e42c: e17ffe15 stw r5,-8(fp) + 801e430: e1bffd15 stw r6,-12(fp) + 801e434: e1fffc15 stw r7,-16(fp) + if(dev->max_byte < length || + 801e438: e0bfff17 ldw r2,-4(fp) + 801e43c: 10c01217 ldw r3,72(r2) + 801e440: e0800117 ldw r2,4(fp) + 801e444: 18800436 bltu r3,r2,801e458 + dev->enhanced_features != 0 + 801e448: e0bfff17 ldw r2,-4(fp) + 801e44c: 10801703 ldbu r2,92(r2) + if(dev->max_byte < length || + 801e450: 10803fcc andi r2,r2,255 + 801e454: 10000226 beq r2,zero,801e460 + ) + { + return -EINVAL; + 801e458: 00bffa84 movi r2,-22 + 801e45c: 00000e06 br 801e498 + } + descriptor->read_address = read_address; + 801e460: e0bffe17 ldw r2,-8(fp) + 801e464: e0fffd17 ldw r3,-12(fp) + 801e468: 10c00015 stw r3,0(r2) + descriptor->write_address = write_address; + 801e46c: e0bffe17 ldw r2,-8(fp) + 801e470: e0fffc17 ldw r3,-16(fp) + 801e474: 10c00115 stw r3,4(r2) + descriptor->transfer_length = length; + 801e478: e0bffe17 ldw r2,-8(fp) + 801e47c: e0c00117 ldw r3,4(fp) + 801e480: 10c00215 stw r3,8(r2) + descriptor->control = control | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK; + 801e484: e0800217 ldw r2,8(fp) + 801e488: 10e00034 orhi r3,r2,32768 + 801e48c: e0bffe17 ldw r2,-8(fp) + 801e490: 10c00315 stw r3,12(r2) + + return 0; + 801e494: 0005883a mov r2,zero +} + 801e498: e037883a mov sp,fp + 801e49c: df000017 ldw fp,0(sp) + 801e4a0: dec00104 addi sp,sp,4 + 801e4a4: f800283a ret + +0801e4a8 : + alt_u16 sequence_number, + alt_u8 read_burst_count, + alt_u8 write_burst_count, + alt_u16 read_stride, + alt_u16 write_stride) +{ + 801e4a8: defff604 addi sp,sp,-40 + 801e4ac: df000915 stw fp,36(sp) + 801e4b0: df000904 addi fp,sp,36 + 801e4b4: e13fff15 stw r4,-4(fp) + 801e4b8: e17ffe15 stw r5,-8(fp) + 801e4bc: e1bffd15 stw r6,-12(fp) + 801e4c0: e1fffc15 stw r7,-16(fp) + 801e4c4: e1800317 ldw r6,12(fp) + 801e4c8: e1400417 ldw r5,16(fp) + 801e4cc: e1000517 ldw r4,20(fp) + 801e4d0: e0c00617 ldw r3,24(fp) + 801e4d4: e0800717 ldw r2,28(fp) + 801e4d8: e1bffb0d sth r6,-20(fp) + 801e4dc: e17ffa05 stb r5,-24(fp) + 801e4e0: e13ff905 stb r4,-28(fp) + 801e4e4: e0fff80d sth r3,-32(fp) + 801e4e8: e0bff70d sth r2,-36(fp) + if(dev->max_byte < length || + 801e4ec: e0bfff17 ldw r2,-4(fp) + 801e4f0: 10c01217 ldw r3,72(r2) + 801e4f4: e0800117 ldw r2,4(fp) + 801e4f8: 18801936 bltu r3,r2,801e560 + dev->max_stride < read_stride || + 801e4fc: e13fff17 ldw r4,-4(fp) + 801e500: 20801317 ldw r2,76(r4) + 801e504: 20c01417 ldw r3,80(r4) + 801e508: e13ff80b ldhu r4,-32(fp) + 801e50c: 213fffcc andi r4,r4,65535 + 801e510: 2015883a mov r10,r4 + 801e514: 0017883a mov r11,zero + if(dev->max_byte < length || + 801e518: 1ac01136 bltu r3,r11,801e560 + 801e51c: 58c0011e bne r11,r3,801e524 + 801e520: 12800f36 bltu r2,r10,801e560 + dev->max_stride < write_stride || + 801e524: e13fff17 ldw r4,-4(fp) + 801e528: 20801317 ldw r2,76(r4) + 801e52c: 20c01417 ldw r3,80(r4) + 801e530: e13ff70b ldhu r4,-36(fp) + 801e534: 213fffcc andi r4,r4,65535 + 801e538: 2011883a mov r8,r4 + 801e53c: 0013883a mov r9,zero + dev->max_stride < read_stride || + 801e540: 1a400736 bltu r3,r9,801e560 + 801e544: 48c0011e bne r9,r3,801e54c + 801e548: 12000536 bltu r2,r8,801e560 + dev->enhanced_features != 1 + 801e54c: e0bfff17 ldw r2,-4(fp) + 801e550: 10801703 ldbu r2,92(r2) + dev->max_stride < write_stride || + 801e554: 10803fcc andi r2,r2,255 + 801e558: 10800060 cmpeqi r2,r2,1 + 801e55c: 1000021e bne r2,zero,801e568 + ) + { + return -EINVAL; + 801e560: 00bffa84 movi r2,-22 + 801e564: 00002106 br 801e5ec + } + + descriptor->read_address_low = read_address; + 801e568: e0bffe17 ldw r2,-8(fp) + 801e56c: e0fffd17 ldw r3,-12(fp) + 801e570: 10c00015 stw r3,0(r2) + descriptor->write_address_low = write_address; + 801e574: e0bffe17 ldw r2,-8(fp) + 801e578: e0fffc17 ldw r3,-16(fp) + 801e57c: 10c00115 stw r3,4(r2) + descriptor->transfer_length = length; + 801e580: e0bffe17 ldw r2,-8(fp) + 801e584: e0c00117 ldw r3,4(fp) + 801e588: 10c00215 stw r3,8(r2) + descriptor->sequence_number = sequence_number; + 801e58c: e0bffe17 ldw r2,-8(fp) + 801e590: e0fffb0b ldhu r3,-20(fp) + 801e594: 10c0030d sth r3,12(r2) + descriptor->read_burst_count = read_burst_count; + 801e598: e0bffe17 ldw r2,-8(fp) + 801e59c: e0fffa03 ldbu r3,-24(fp) + 801e5a0: 10c00385 stb r3,14(r2) + descriptor->write_burst_count = write_burst_count; + 801e5a4: e0bffe17 ldw r2,-8(fp) + 801e5a8: e0fff903 ldbu r3,-28(fp) + 801e5ac: 10c003c5 stb r3,15(r2) + descriptor->read_stride = read_stride; + 801e5b0: e0bffe17 ldw r2,-8(fp) + 801e5b4: e0fff80b ldhu r3,-32(fp) + 801e5b8: 10c0040d sth r3,16(r2) + descriptor->write_stride = write_stride; + 801e5bc: e0bffe17 ldw r2,-8(fp) + 801e5c0: e0fff70b ldhu r3,-36(fp) + 801e5c4: 10c0048d sth r3,18(r2) + descriptor->read_address_high = NULL; + 801e5c8: e0bffe17 ldw r2,-8(fp) + 801e5cc: 10000515 stw zero,20(r2) + descriptor->write_address_high = NULL; + 801e5d0: e0bffe17 ldw r2,-8(fp) + 801e5d4: 10000615 stw zero,24(r2) + descriptor->control = control | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK; + 801e5d8: e0800217 ldw r2,8(fp) + 801e5dc: 10e00034 orhi r3,r2,32768 + 801e5e0: e0bffe17 ldw r2,-8(fp) + 801e5e4: 10c00715 stw r3,28(r2) + + return 0 ; + 801e5e8: 0005883a mov r2,zero + +} + 801e5ec: e037883a mov sp,fp + 801e5f0: df000017 ldw fp,0(sp) + 801e5f4: dec00104 addi sp,sp,4 + 801e5f8: f800283a ret + +0801e5fc : + */ +static int alt_msgdma_descriptor_async_transfer ( + alt_msgdma_dev *dev, + alt_msgdma_standard_descriptor *standard_desc, + alt_msgdma_extended_descriptor *extended_desc) +{ + 801e5fc: deffed04 addi sp,sp,-76 + 801e600: dfc01215 stw ra,72(sp) + 801e604: df001115 stw fp,68(sp) + 801e608: df001104 addi fp,sp,68 + 801e60c: e13ff115 stw r4,-60(fp) + 801e610: e17ff015 stw r5,-64(fp) + 801e614: e1bfef15 stw r6,-68(fp) + alt_u32 control = 0; + 801e618: e03ffe15 stw zero,-8(fp) + alt_irq_context context = 0; + 801e61c: e03ffd15 stw zero,-12(fp) + alt_u16 counter = 0; + 801e620: e03fff8d sth zero,-2(fp) + alt_u32 fifo_read_fill_level = ( + IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(dev->csr_base) & + 801e624: e0bff117 ldw r2,-60(fp) + 801e628: 10800317 ldw r2,12(r2) + 801e62c: 10800204 addi r2,r2,8 + 801e630: 10800037 ldwio r2,0(r2) + alt_u32 fifo_read_fill_level = ( + 801e634: 10bfffcc andi r2,r2,65535 + 801e638: e0bffc15 stw r2,-16(fp) + ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_MASK) >> + ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_OFFSET; + alt_u32 fifo_write_fill_level = ( + IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(dev->csr_base) & + 801e63c: e0bff117 ldw r2,-60(fp) + 801e640: 10800317 ldw r2,12(r2) + 801e644: 10800204 addi r2,r2,8 + 801e648: 10800037 ldwio r2,0(r2) + ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_MASK) >> + 801e64c: 1004d43a srli r2,r2,16 + alt_u32 fifo_write_fill_level = ( + 801e650: 10bfffcc andi r2,r2,65535 + 801e654: e0bffb15 stw r2,-20(fp) + ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_OFFSET; + + /* Return with error immediately if one of read/write buffer is full */ + if((dev->descriptor_fifo_depth <= fifo_write_fill_level) || + 801e658: e0bff117 ldw r2,-60(fp) + 801e65c: 10800917 ldw r2,36(r2) + 801e660: e0fffb17 ldw r3,-20(fp) + 801e664: 1880042e bgeu r3,r2,801e678 + (dev->descriptor_fifo_depth <= fifo_read_fill_level)) + 801e668: e0bff117 ldw r2,-60(fp) + 801e66c: 10800917 ldw r2,36(r2) + if((dev->descriptor_fifo_depth <= fifo_write_fill_level) || + 801e670: e0fffc17 ldw r3,-16(fp) + 801e674: 18800236 bltu r3,r2,801e680 + { + /*at least one write or read FIFO descriptor buffer is full, + returning so that this function is non-blocking*/ + return -ENOSPC; + 801e678: 00bff904 movi r2,-28 + 801e67c: 0000a906 br 801e924 + + /* + * When running in a multi threaded environment, obtain the "regs_lock" + * semaphore. This ensures that accessing registers is thread-safe. + */ + ALT_SEM_PEND (dev->regs_lock, 0); + 801e680: e0bff117 ldw r2,-60(fp) + 801e684: 10801817 ldw r2,96(r2) + 801e688: e0bff815 stw r2,-32(fp) + 801e68c: e03ff78d sth zero,-34(fp) + 801e690: e0bff78b ldhu r2,-34(fp) + 801e694: e0fff2c4 addi r3,fp,-53 + 801e698: 180d883a mov r6,r3 + 801e69c: 100b883a mov r5,r2 + 801e6a0: e13ff817 ldw r4,-32(fp) + 801e6a4: 8015a600 call 8015a60 + + /* Stop the msgdma dispatcher from issuing more descriptors to the + read or write masters */ + /* stop issuing more descriptors */ + control = ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK; + 801e6a8: 00800804 movi r2,32 + 801e6ac: e0bffe15 stw r2,-8(fp) + NIOS2_READ_STATUS (context); + 801e6b0: 0005303a rdctl r2,status + 801e6b4: e0bff915 stw r2,-28(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 801e6b8: e0fff917 ldw r3,-28(fp) + 801e6bc: 00bfff84 movi r2,-2 + 801e6c0: 1884703a and r2,r3,r2 + 801e6c4: 1001703a wrctl status,r2 + return context; + 801e6c8: e0bff917 ldw r2,-28(fp) + /* making sure the read-modify-write below can't be pre-empted */ + context = alt_irq_disable_all(); + 801e6cc: e0bffd15 stw r2,-12(fp) + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, control); + 801e6d0: e0bff117 ldw r2,-60(fp) + 801e6d4: 10800317 ldw r2,12(r2) + 801e6d8: 10800104 addi r2,r2,4 + 801e6dc: e0fffe17 ldw r3,-8(fp) + 801e6e0: 10c00035 stwio r3,0(r2) + /* + * Clear any (previous) status register information + * that might occlude our error checking later. + */ + IOWR_ALTERA_MSGDMA_CSR_STATUS( + 801e6e4: e0bff117 ldw r2,-60(fp) + 801e6e8: 10800317 ldw r2,12(r2) + 801e6ec: e0fff117 ldw r3,-60(fp) + 801e6f0: 18c00317 ldw r3,12(r3) + 801e6f4: 18c00037 ldwio r3,0(r3) + 801e6f8: 10c00035 stwio r3,0(r2) + 801e6fc: e0bffd17 ldw r2,-12(fp) + 801e700: e0bffa15 stw r2,-24(fp) + NIOS2_WRITE_STATUS (context); + 801e704: e0bffa17 ldw r2,-24(fp) + 801e708: 1001703a wrctl status,r2 + dev->csr_base, + IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base)); + alt_irq_enable_all(context); + + if (NULL != standard_desc && NULL == extended_desc) + 801e70c: e0bff017 ldw r2,-64(fp) + 801e710: 10001e26 beq r2,zero,801e78c + 801e714: e0bfef17 ldw r2,-68(fp) + 801e718: 10001c1e bne r2,zero,801e78c + { + /*writing descriptor structure to the dispatcher, wait until descriptor + write is succeed*/ + while(0 != alt_msgdma_write_standard_descriptor ( + 801e71c: 00001106 br 801e764 + dev->csr_base, dev->descriptor_base, standard_desc)) + { + alt_busy_sleep(1); /* delay 1us */ + 801e720: 01000044 movi r4,1 + 801e724: 8036f5c0 call 8036f5c + if(5000 <= counter) /* time_out if waiting longer than 5 msec */ + 801e728: e0bfff8b ldhu r2,-2(fp) + 801e72c: 1084e230 cmpltui r2,r2,5000 + 801e730: 1000091e bne r2,zero,801e758 + { + alt_printf("time out after 5 msec while waiting" + 801e734: 01020174 movhi r4,2053 + 801e738: 21254e04 addi r4,r4,-27336 + 801e73c: 8037a9c0 call 8037a9c + /* + * Now that access to the registers is complete, release the + * registers semaphore so that other threads can access the + * registers. + */ + ALT_SEM_POST (dev->regs_lock); + 801e740: e0bff117 ldw r2,-60(fp) + 801e744: 10801817 ldw r2,96(r2) + 801e748: 1009883a mov r4,r2 + 801e74c: 8015d840 call 8015d84 + + return -ETIME; + 801e750: 00bff084 movi r2,-62 + 801e754: 00007306 br 801e924 + } + counter++; + 801e758: e0bfff8b ldhu r2,-2(fp) + 801e75c: 10800044 addi r2,r2,1 + 801e760: e0bfff8d sth r2,-2(fp) + while(0 != alt_msgdma_write_standard_descriptor ( + 801e764: e0bff117 ldw r2,-60(fp) + 801e768: 10c00317 ldw r3,12(r2) + 801e76c: e0bff117 ldw r2,-60(fp) + 801e770: 10800417 ldw r2,16(r2) + 801e774: e1bff017 ldw r6,-64(fp) + 801e778: 100b883a mov r5,r2 + 801e77c: 1809883a mov r4,r3 + 801e780: 801e0d80 call 801e0d8 + 801e784: 103fe61e bne r2,zero,801e720 + if (NULL != standard_desc && NULL == extended_desc) + 801e788: 00002706 br 801e828 + } + } + else if (NULL == standard_desc && NULL != extended_desc) + 801e78c: e0bff017 ldw r2,-64(fp) + 801e790: 10001f1e bne r2,zero,801e810 + 801e794: e0bfef17 ldw r2,-68(fp) + 801e798: 10001d26 beq r2,zero,801e810 + { + counter = 0; /* reset counter */ + 801e79c: e03fff8d sth zero,-2(fp) + /*writing descriptor structure to the dispatcher, wait until descriptor + write is succeed*/ + while(0 != alt_msgdma_write_extended_descriptor ( + 801e7a0: 00001106 br 801e7e8 + dev->csr_base, + dev->descriptor_base, + extended_desc)) + { + alt_busy_sleep(1); /* delay 1us */ + 801e7a4: 01000044 movi r4,1 + 801e7a8: 8036f5c0 call 8036f5c + if(5000 <= counter) /* time_out if waiting longer than 5 msec */ + 801e7ac: e0bfff8b ldhu r2,-2(fp) + 801e7b0: 1084e230 cmpltui r2,r2,5000 + 801e7b4: 1000091e bne r2,zero,801e7dc + { + alt_printf("time out after 5 msec while waiting free FIFO buffer" + 801e7b8: 01020174 movhi r4,2053 + 801e7bc: 21256404 addi r4,r4,-27248 + 801e7c0: 8037a9c0 call 8037a9c + /* + * Now that access to the registers is complete, release the + * registers semaphore so that other threads can access the + * registers. + */ + ALT_SEM_POST (dev->regs_lock); + 801e7c4: e0bff117 ldw r2,-60(fp) + 801e7c8: 10801817 ldw r2,96(r2) + 801e7cc: 1009883a mov r4,r2 + 801e7d0: 8015d840 call 8015d84 + + return -ETIME; + 801e7d4: 00bff084 movi r2,-62 + 801e7d8: 00005206 br 801e924 + } + counter++; + 801e7dc: e0bfff8b ldhu r2,-2(fp) + 801e7e0: 10800044 addi r2,r2,1 + 801e7e4: e0bfff8d sth r2,-2(fp) + while(0 != alt_msgdma_write_extended_descriptor ( + 801e7e8: e0bff117 ldw r2,-60(fp) + 801e7ec: 10c00317 ldw r3,12(r2) + 801e7f0: e0bff117 ldw r2,-60(fp) + 801e7f4: 10800417 ldw r2,16(r2) + 801e7f8: e1bfef17 ldw r6,-68(fp) + 801e7fc: 100b883a mov r5,r2 + 801e800: 1809883a mov r4,r3 + 801e804: 801e16c0 call 801e16c + 801e808: 103fe61e bne r2,zero,801e7a4 + else if (NULL == standard_desc && NULL != extended_desc) + 801e80c: 00000606 br 801e828 + { + /* + * Now that access to the registers is complete, release the registers + * semaphore so that other threads can access the registers. + */ + ALT_SEM_POST (dev->regs_lock); + 801e810: e0bff117 ldw r2,-60(fp) + 801e814: 10801817 ldw r2,96(r2) + 801e818: 1009883a mov r4,r2 + 801e81c: 8015d840 call 8015d84 + + /* operation not permitted due to descriptor type conflict */ + return -EPERM; + 801e820: 00bfffc4 movi r2,-1 + 801e824: 00003f06 br 801e924 + * If a callback routine has been previously registered which will be + * called from the msgdma ISR. Set up controller to: + * - Run + * - Stop on an error with any particular descriptor + */ + if(dev->callback) + 801e828: e0bff117 ldw r2,-60(fp) + 801e82c: 10800b17 ldw r2,44(r2) + 801e830: 10001c26 beq r2,zero,801e8a4 + { + + control |= (dev->control | + 801e834: e0bff117 ldw r2,-60(fp) + 801e838: 10c00d17 ldw r3,52(r2) + 801e83c: e0bffe17 ldw r2,-8(fp) + 801e840: 1884b03a or r2,r3,r2 + 801e844: 10800514 ori r2,r2,20 + 801e848: e0bffe15 stw r2,-8(fp) + ALTERA_MSGDMA_CSR_STOP_ON_ERROR_MASK | + ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK ); + control &= (~ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK); + 801e84c: e0fffe17 ldw r3,-8(fp) + 801e850: 00bff7c4 movi r2,-33 + 801e854: 1884703a and r2,r3,r2 + 801e858: e0bffe15 stw r2,-8(fp) + NIOS2_READ_STATUS (context); + 801e85c: 0005303a rdctl r2,status + 801e860: e0bff515 stw r2,-44(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 801e864: e0fff517 ldw r3,-44(fp) + 801e868: 00bfff84 movi r2,-2 + 801e86c: 1884703a and r2,r3,r2 + 801e870: 1001703a wrctl status,r2 + return context; + 801e874: e0bff517 ldw r2,-44(fp) + /* making sure the read-modify-write below can't be pre-empted */ + context = alt_irq_disable_all(); + 801e878: e0bffd15 stw r2,-12(fp) + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, control); + 801e87c: e0bff117 ldw r2,-60(fp) + 801e880: 10800317 ldw r2,12(r2) + 801e884: 10800104 addi r2,r2,4 + 801e888: e0fffe17 ldw r3,-8(fp) + 801e88c: 10c00035 stwio r3,0(r2) + 801e890: e0bffd17 ldw r2,-12(fp) + 801e894: e0bff615 stw r2,-40(fp) + NIOS2_WRITE_STATUS (context); + 801e898: e0bff617 ldw r2,-40(fp) + 801e89c: 1001703a wrctl status,r2 + 801e8a0: 00001b06 br 801e910 + * - Stop on an error with any particular descriptor + * - Disable interrupt generation + */ + else + { + control |= (dev->control | + 801e8a4: e0bff117 ldw r2,-60(fp) + 801e8a8: 10c00d17 ldw r3,52(r2) + 801e8ac: e0bffe17 ldw r2,-8(fp) + 801e8b0: 1884b03a or r2,r3,r2 + 801e8b4: 10800114 ori r2,r2,4 + 801e8b8: e0bffe15 stw r2,-8(fp) + ALTERA_MSGDMA_CSR_STOP_ON_ERROR_MASK ); + control &= (~ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK) & + 801e8bc: e0fffe17 ldw r3,-8(fp) + 801e8c0: 00bff3c4 movi r2,-49 + 801e8c4: 1884703a and r2,r3,r2 + 801e8c8: e0bffe15 stw r2,-8(fp) + NIOS2_READ_STATUS (context); + 801e8cc: 0005303a rdctl r2,status + 801e8d0: e0bff315 stw r2,-52(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 801e8d4: e0fff317 ldw r3,-52(fp) + 801e8d8: 00bfff84 movi r2,-2 + 801e8dc: 1884703a and r2,r3,r2 + 801e8e0: 1001703a wrctl status,r2 + return context; + 801e8e4: e0bff317 ldw r2,-52(fp) + (~ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK); + /* making sure the read-modify-write below can't be pre-empted */ + context = alt_irq_disable_all(); + 801e8e8: e0bffd15 stw r2,-12(fp) + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, control); + 801e8ec: e0bff117 ldw r2,-60(fp) + 801e8f0: 10800317 ldw r2,12(r2) + 801e8f4: 10800104 addi r2,r2,4 + 801e8f8: e0fffe17 ldw r3,-8(fp) + 801e8fc: 10c00035 stwio r3,0(r2) + 801e900: e0bffd17 ldw r2,-12(fp) + 801e904: e0bff415 stw r2,-48(fp) + NIOS2_WRITE_STATUS (context); + 801e908: e0bff417 ldw r2,-48(fp) + 801e90c: 1001703a wrctl status,r2 + + /* + * Now that access to the registers is complete, release the registers + * semaphore so that other threads can access the registers. + */ + ALT_SEM_POST (dev->regs_lock); + 801e910: e0bff117 ldw r2,-60(fp) + 801e914: 10801817 ldw r2,96(r2) + 801e918: 1009883a mov r4,r2 + 801e91c: 8015d840 call 8015d84 + + return 0; + 801e920: 0005883a mov r2,zero +} + 801e924: e037883a mov sp,fp + 801e928: dfc00117 ldw ra,4(sp) + 801e92c: df000017 ldw fp,0(sp) + 801e930: dec00204 addi sp,sp,8 + 801e934: f800283a ret + +0801e938 : + */ +static int alt_msgdma_descriptor_sync_transfer ( + alt_msgdma_dev *dev, + alt_msgdma_standard_descriptor *standard_desc, + alt_msgdma_extended_descriptor *extended_desc) +{ + 801e938: deffed04 addi sp,sp,-76 + 801e93c: dfc01215 stw ra,72(sp) + 801e940: df001115 stw fp,68(sp) + 801e944: df001104 addi fp,sp,68 + 801e948: e13ff115 stw r4,-60(fp) + 801e94c: e17ff015 stw r5,-64(fp) + 801e950: e1bfef15 stw r6,-68(fp) + alt_u32 control=0; + 801e954: e03ffb15 stw zero,-20(fp) + alt_irq_context context=0; + 801e958: e03ffa15 stw zero,-24(fp) + alt_u32 csr_status = 0; + 801e95c: e03fff15 stw zero,-4(fp) + alt_u16 counter = 0; + 801e960: e03ffe8d sth zero,-6(fp) + alt_u32 fifo_read_fill_level = ( + IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(dev->csr_base) & + 801e964: e0bff117 ldw r2,-60(fp) + 801e968: 10800317 ldw r2,12(r2) + 801e96c: 10800204 addi r2,r2,8 + 801e970: 10800037 ldwio r2,0(r2) + alt_u32 fifo_read_fill_level = ( + 801e974: 10bfffcc andi r2,r2,65535 + 801e978: e0bffd15 stw r2,-12(fp) + ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_MASK) >> + ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_OFFSET; + alt_u32 fifo_write_fill_level = ( + IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(dev->csr_base) & + 801e97c: e0bff117 ldw r2,-60(fp) + 801e980: 10800317 ldw r2,12(r2) + 801e984: 10800204 addi r2,r2,8 + 801e988: 10800037 ldwio r2,0(r2) + ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_MASK) >> + 801e98c: 1004d43a srli r2,r2,16 + alt_u32 fifo_write_fill_level = ( + 801e990: 10bfffcc andi r2,r2,65535 + 801e994: e0bffc15 stw r2,-16(fp) + ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_OFFSET; + alt_u32 error = ALTERA_MSGDMA_CSR_STOPPED_ON_ERROR_MASK | + 801e998: 00807804 movi r2,480 + 801e99c: e0bff915 stw r2,-28(fp) + ALTERA_MSGDMA_CSR_STOPPED_ON_EARLY_TERMINATION_MASK | + ALTERA_MSGDMA_CSR_STOP_STATE_MASK | + ALTERA_MSGDMA_CSR_RESET_STATE_MASK; + + /* Wait for available FIFO buffer to store new descriptor*/ + while ((dev->descriptor_fifo_depth <= fifo_write_fill_level) || + 801e9a0: 00001a06 br 801ea0c + (dev->descriptor_fifo_depth <= fifo_read_fill_level)) + { + alt_busy_sleep(1); /* delay 1us */ + 801e9a4: 01000044 movi r4,1 + 801e9a8: 8036f5c0 call 8036f5c + if(5000 <= counter) /* time_out if waiting longer than 5 msec */ + 801e9ac: e0bffe8b ldhu r2,-6(fp) + 801e9b0: 1084e230 cmpltui r2,r2,5000 + 801e9b4: 1000051e bne r2,zero,801e9cc + { + alt_printf("time out after 5 msec while waiting free FIFO buffer" + 801e9b8: 01020174 movhi r4,2053 + 801e9bc: 21257a04 addi r4,r4,-27160 + 801e9c0: 8037a9c0 call 8037a9c + " for storing descriptor\n"); + return -ETIME; + 801e9c4: 00bff084 movi r2,-62 + 801e9c8: 0000d806 br 801ed2c + } + counter++; + 801e9cc: e0bffe8b ldhu r2,-6(fp) + 801e9d0: 10800044 addi r2,r2,1 + 801e9d4: e0bffe8d sth r2,-6(fp) + fifo_read_fill_level = ( + IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(dev->csr_base) & + 801e9d8: e0bff117 ldw r2,-60(fp) + 801e9dc: 10800317 ldw r2,12(r2) + 801e9e0: 10800204 addi r2,r2,8 + 801e9e4: 10800037 ldwio r2,0(r2) + fifo_read_fill_level = ( + 801e9e8: 10bfffcc andi r2,r2,65535 + 801e9ec: e0bffd15 stw r2,-12(fp) + ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_MASK) >> + ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_OFFSET; + fifo_write_fill_level = ( + IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(dev->csr_base) & + 801e9f0: e0bff117 ldw r2,-60(fp) + 801e9f4: 10800317 ldw r2,12(r2) + 801e9f8: 10800204 addi r2,r2,8 + 801e9fc: 10800037 ldwio r2,0(r2) + ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_MASK) >> + 801ea00: 1004d43a srli r2,r2,16 + fifo_write_fill_level = ( + 801ea04: 10bfffcc andi r2,r2,65535 + 801ea08: e0bffc15 stw r2,-16(fp) + while ((dev->descriptor_fifo_depth <= fifo_write_fill_level) || + 801ea0c: e0bff117 ldw r2,-60(fp) + 801ea10: 10800917 ldw r2,36(r2) + 801ea14: e0fffc17 ldw r3,-16(fp) + 801ea18: 18bfe22e bgeu r3,r2,801e9a4 + (dev->descriptor_fifo_depth <= fifo_read_fill_level)) + 801ea1c: e0bff117 ldw r2,-60(fp) + 801ea20: 10800917 ldw r2,36(r2) + while ((dev->descriptor_fifo_depth <= fifo_write_fill_level) || + 801ea24: e0fffd17 ldw r3,-12(fp) + 801ea28: 18bfde2e bgeu r3,r2,801e9a4 + + /* + * When running in a multi threaded environment, obtain the "regs_lock" + * semaphore. This ensures that accessing registers is thread-safe. + */ + ALT_SEM_PEND (dev->regs_lock, 0); + 801ea2c: e0bff117 ldw r2,-60(fp) + 801ea30: 10801817 ldw r2,96(r2) + 801ea34: e0bff715 stw r2,-36(fp) + 801ea38: e03ff68d sth zero,-38(fp) + 801ea3c: e0bff68b ldhu r2,-38(fp) + 801ea40: e0fff2c4 addi r3,fp,-53 + 801ea44: 180d883a mov r6,r3 + 801ea48: 100b883a mov r5,r2 + 801ea4c: e13ff717 ldw r4,-36(fp) + 801ea50: 8015a600 call 8015a60 + NIOS2_READ_STATUS (context); + 801ea54: 0005303a rdctl r2,status + 801ea58: e0bff815 stw r2,-32(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 801ea5c: e0fff817 ldw r3,-32(fp) + 801ea60: 00bfff84 movi r2,-2 + 801ea64: 1884703a and r2,r3,r2 + 801ea68: 1001703a wrctl status,r2 + return context; + 801ea6c: e0bff817 ldw r2,-32(fp) + + /* Stop the msgdma dispatcher from issuing more descriptors to the + read or write masters */ + /* making sure the read-modify-write below can't be pre-empted */ + context = alt_irq_disable_all(); + 801ea70: e0bffa15 stw r2,-24(fp) + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, + 801ea74: e0bff117 ldw r2,-60(fp) + 801ea78: 10800317 ldw r2,12(r2) + 801ea7c: 10800104 addi r2,r2,4 + 801ea80: 00c00804 movi r3,32 + 801ea84: 10c00035 stwio r3,0(r2) + ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK); + /* + * Clear any (previous) status register information + * that might occlude our error checking later. + */ + IOWR_ALTERA_MSGDMA_CSR_STATUS( + 801ea88: e0bff117 ldw r2,-60(fp) + 801ea8c: 10800317 ldw r2,12(r2) + 801ea90: e0fff117 ldw r3,-60(fp) + 801ea94: 18c00317 ldw r3,12(r3) + 801ea98: 18c00037 ldwio r3,0(r3) + 801ea9c: 10c00035 stwio r3,0(r2) + dev->csr_base, + IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base)); + + if (NULL != standard_desc && NULL == extended_desc) + 801eaa0: e0bff017 ldw r2,-64(fp) + 801eaa4: 10001f26 beq r2,zero,801eb24 + 801eaa8: e0bfef17 ldw r2,-68(fp) + 801eaac: 10001d1e bne r2,zero,801eb24 + { + counter = 0; /* reset counter */ + 801eab0: e03ffe8d sth zero,-6(fp) + /*writing descriptor structure to the dispatcher, wait until descriptor + write is succeed*/ + while(0 != alt_msgdma_write_standard_descriptor ( + 801eab4: 00001106 br 801eafc + dev->csr_base, dev->descriptor_base, standard_desc)) + { + alt_busy_sleep(1); /* delay 1us */ + 801eab8: 01000044 movi r4,1 + 801eabc: 8036f5c0 call 8036f5c + if(5000 <= counter) /* time_out if waiting longer than 5 msec */ + 801eac0: e0bffe8b ldhu r2,-6(fp) + 801eac4: 1084e230 cmpltui r2,r2,5000 + 801eac8: 1000091e bne r2,zero,801eaf0 + { + alt_printf("time out after 5 msec while writing standard" + 801eacc: 01020174 movhi r4,2053 + 801ead0: 21258e04 addi r4,r4,-27080 + 801ead4: 8037a9c0 call 8037a9c + /* + * Now that access to the registers is complete, release the + * registers semaphore so that other threads can access the + * registers. + */ + ALT_SEM_POST (dev->regs_lock); + 801ead8: e0bff117 ldw r2,-60(fp) + 801eadc: 10801817 ldw r2,96(r2) + 801eae0: 1009883a mov r4,r2 + 801eae4: 8015d840 call 8015d84 + + return -ETIME; + 801eae8: 00bff084 movi r2,-62 + 801eaec: 00008f06 br 801ed2c + } + counter++; + 801eaf0: e0bffe8b ldhu r2,-6(fp) + 801eaf4: 10800044 addi r2,r2,1 + 801eaf8: e0bffe8d sth r2,-6(fp) + while(0 != alt_msgdma_write_standard_descriptor ( + 801eafc: e0bff117 ldw r2,-60(fp) + 801eb00: 10c00317 ldw r3,12(r2) + 801eb04: e0bff117 ldw r2,-60(fp) + 801eb08: 10800417 ldw r2,16(r2) + 801eb0c: e1bff017 ldw r6,-64(fp) + 801eb10: 100b883a mov r5,r2 + 801eb14: 1809883a mov r4,r3 + 801eb18: 801e0d80 call 801e0d8 + 801eb1c: 103fe61e bne r2,zero,801eab8 + if (NULL != standard_desc && NULL == extended_desc) + 801eb20: 00002706 br 801ebc0 + } + } + else if (NULL == standard_desc && NULL != extended_desc) + 801eb24: e0bff017 ldw r2,-64(fp) + 801eb28: 10001f1e bne r2,zero,801eba8 + 801eb2c: e0bfef17 ldw r2,-68(fp) + 801eb30: 10001d26 beq r2,zero,801eba8 + { + counter = 0; /* reset counter */ + 801eb34: e03ffe8d sth zero,-6(fp) + /*writing descriptor structure to the dispatcher, wait until descriptor + write is succeed*/ + while(0 != alt_msgdma_write_extended_descriptor ( + 801eb38: 00001106 br 801eb80 + dev->csr_base, dev->descriptor_base, extended_desc)) + { + alt_busy_sleep(1); /* delay 1us */ + 801eb3c: 01000044 movi r4,1 + 801eb40: 8036f5c0 call 8036f5c + if(5000 <= counter) /* time_out if waiting longer than 5 msec */ + 801eb44: e0bffe8b ldhu r2,-6(fp) + 801eb48: 1084e230 cmpltui r2,r2,5000 + 801eb4c: 1000091e bne r2,zero,801eb74 + { + alt_printf("time out after 5 msec while writing extended" + 801eb50: 01020174 movhi r4,2053 + 801eb54: 21259f04 addi r4,r4,-27012 + 801eb58: 8037a9c0 call 8037a9c + /* + * Now that access to the registers is complete, release the + * registers semaphore so that other threads can access the + * registers. + */ + ALT_SEM_POST (dev->regs_lock); + 801eb5c: e0bff117 ldw r2,-60(fp) + 801eb60: 10801817 ldw r2,96(r2) + 801eb64: 1009883a mov r4,r2 + 801eb68: 8015d840 call 8015d84 + + return -ETIME; + 801eb6c: 00bff084 movi r2,-62 + 801eb70: 00006e06 br 801ed2c + } + counter++; + 801eb74: e0bffe8b ldhu r2,-6(fp) + 801eb78: 10800044 addi r2,r2,1 + 801eb7c: e0bffe8d sth r2,-6(fp) + while(0 != alt_msgdma_write_extended_descriptor ( + 801eb80: e0bff117 ldw r2,-60(fp) + 801eb84: 10c00317 ldw r3,12(r2) + 801eb88: e0bff117 ldw r2,-60(fp) + 801eb8c: 10800417 ldw r2,16(r2) + 801eb90: e1bfef17 ldw r6,-68(fp) + 801eb94: 100b883a mov r5,r2 + 801eb98: 1809883a mov r4,r3 + 801eb9c: 801e16c0 call 801e16c + 801eba0: 103fe61e bne r2,zero,801eb3c + else if (NULL == standard_desc && NULL != extended_desc) + 801eba4: 00000606 br 801ebc0 + { + /* + * Now that access to the registers is complete, release the registers + * semaphore so that other threads can access the registers. + */ + ALT_SEM_POST (dev->regs_lock); + 801eba8: e0bff117 ldw r2,-60(fp) + 801ebac: 10801817 ldw r2,96(r2) + 801ebb0: 1009883a mov r4,r2 + 801ebb4: 8015d840 call 8015d84 + + /* operation not permitted due to descriptor type conflict */ + return -EPERM; + 801ebb8: 00bfffc4 movi r2,-1 + 801ebbc: 00005b06 br 801ed2c + * Set up msgdma controller to: + * - Disable interrupt generation + * - Run once a valid descriptor is written to controller + * - Stop on an error with any particular descriptor + */ + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, + 801ebc0: e0bff117 ldw r2,-60(fp) + 801ebc4: 10800317 ldw r2,12(r2) + 801ebc8: 10800104 addi r2,r2,4 + 801ebcc: e0fff117 ldw r3,-60(fp) + 801ebd0: 19000d17 ldw r4,52(r3) + 801ebd4: 00fff2c4 movi r3,-53 + 801ebd8: 20c6703a and r3,r4,r3 + 801ebdc: 18c00114 ori r3,r3,4 + 801ebe0: 10c00035 stwio r3,0(r2) + 801ebe4: e0bffa17 ldw r2,-24(fp) + 801ebe8: e0bff515 stw r2,-44(fp) + NIOS2_WRITE_STATUS (context); + 801ebec: e0bff517 ldw r2,-44(fp) + 801ebf0: 1001703a wrctl status,r2 + (~ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK) & + (~ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK)) ; + + alt_irq_enable_all(context); + + counter = 0; /* reset counter */ + 801ebf4: e03ffe8d sth zero,-6(fp) + + csr_status = IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base); + 801ebf8: e0bff117 ldw r2,-60(fp) + 801ebfc: 10800317 ldw r2,12(r2) + 801ec00: 10800037 ldwio r2,0(r2) + 801ec04: e0bfff15 stw r2,-4(fp) + + /* Wait for any pending transfers to complete or checking any errors or + conditions causing descriptor to stop dispatching */ + while (!(csr_status & error) && (csr_status & ALTERA_MSGDMA_CSR_BUSY_MASK)) + 801ec08: 00001506 br 801ec60 + { + alt_busy_sleep(1); /* delay 1us */ + 801ec0c: 01000044 movi r4,1 + 801ec10: 8036f5c0 call 8036f5c + if(5000 <= counter) /* time_out if waiting longer than 5 msec */ + 801ec14: e0bffe8b ldhu r2,-6(fp) + 801ec18: 1084e230 cmpltui r2,r2,5000 + 801ec1c: 1000091e bne r2,zero,801ec44 + { + alt_printf("time out after 5 msec while waiting for any pending" + 801ec20: 01020174 movhi r4,2053 + 801ec24: 2125b004 addi r4,r4,-26944 + 801ec28: 8037a9c0 call 8037a9c + + /* + * Now that access to the registers is complete, release the registers + * semaphore so that other threads can access the registers. + */ + ALT_SEM_POST (dev->regs_lock); + 801ec2c: e0bff117 ldw r2,-60(fp) + 801ec30: 10801817 ldw r2,96(r2) + 801ec34: 1009883a mov r4,r2 + 801ec38: 8015d840 call 8015d84 + + return -ETIME; + 801ec3c: 00bff084 movi r2,-62 + 801ec40: 00003a06 br 801ed2c + } + counter++; + 801ec44: e0bffe8b ldhu r2,-6(fp) + 801ec48: 10800044 addi r2,r2,1 + 801ec4c: e0bffe8d sth r2,-6(fp) + csr_status = IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base); + 801ec50: e0bff117 ldw r2,-60(fp) + 801ec54: 10800317 ldw r2,12(r2) + 801ec58: 10800037 ldwio r2,0(r2) + 801ec5c: e0bfff15 stw r2,-4(fp) + while (!(csr_status & error) && (csr_status & ALTERA_MSGDMA_CSR_BUSY_MASK)) + 801ec60: e0ffff17 ldw r3,-4(fp) + 801ec64: e0bff917 ldw r2,-28(fp) + 801ec68: 1884703a and r2,r3,r2 + 801ec6c: 1000031e bne r2,zero,801ec7c + 801ec70: e0bfff17 ldw r2,-4(fp) + 801ec74: 1080004c andi r2,r2,1 + 801ec78: 103fe41e bne r2,zero,801ec0c + } + + + /*Errors or conditions causing the dispatcher stopping issuing read/write + commands to masters*/ + if(0 != (csr_status & error)) + 801ec7c: e0ffff17 ldw r3,-4(fp) + 801ec80: e0bff917 ldw r2,-28(fp) + 801ec84: 1884703a and r2,r3,r2 + 801ec88: 10000626 beq r2,zero,801eca4 + { + /* + * Now that access to the registers is complete, release the registers + * semaphore so that other threads can access the registers. + */ + ALT_SEM_POST (dev->regs_lock); + 801ec8c: e0bff117 ldw r2,-60(fp) + 801ec90: 10801817 ldw r2,96(r2) + 801ec94: 1009883a mov r4,r2 + 801ec98: 8015d840 call 8015d84 + + return error; + 801ec9c: e0bff917 ldw r2,-28(fp) + 801eca0: 00002206 br 801ed2c + } + + /* Stop the msgdma dispatcher from issuing more descriptors to the + read or write masters */ + /* stop issuing more descriptors */ + control = IORD_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base) | + 801eca4: e0bff117 ldw r2,-60(fp) + 801eca8: 10800317 ldw r2,12(r2) + 801ecac: 10800104 addi r2,r2,4 + 801ecb0: 10800037 ldwio r2,0(r2) + 801ecb4: 10800814 ori r2,r2,32 + 801ecb8: e0bffb15 stw r2,-20(fp) + NIOS2_READ_STATUS (context); + 801ecbc: 0005303a rdctl r2,status + 801ecc0: e0bff315 stw r2,-52(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 801ecc4: e0fff317 ldw r3,-52(fp) + 801ecc8: 00bfff84 movi r2,-2 + 801eccc: 1884703a and r2,r3,r2 + 801ecd0: 1001703a wrctl status,r2 + return context; + 801ecd4: e0bff317 ldw r2,-52(fp) + ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK; + /* making sure the read-modify-write below can't be pre-empted */ + context = alt_irq_disable_all(); + 801ecd8: e0bffa15 stw r2,-24(fp) + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, control); + 801ecdc: e0bff117 ldw r2,-60(fp) + 801ece0: 10800317 ldw r2,12(r2) + 801ece4: 10800104 addi r2,r2,4 + 801ece8: e0fffb17 ldw r3,-20(fp) + 801ecec: 10c00035 stwio r3,0(r2) + /* + * Clear any (previous) status register information + * that might occlude our error checking later. + */ + IOWR_ALTERA_MSGDMA_CSR_STATUS( + 801ecf0: e0bff117 ldw r2,-60(fp) + 801ecf4: 10800317 ldw r2,12(r2) + 801ecf8: e0fff117 ldw r3,-60(fp) + 801ecfc: 18c00317 ldw r3,12(r3) + 801ed00: 18c00037 ldwio r3,0(r3) + 801ed04: 10c00035 stwio r3,0(r2) + 801ed08: e0bffa17 ldw r2,-24(fp) + 801ed0c: e0bff415 stw r2,-48(fp) + NIOS2_WRITE_STATUS (context); + 801ed10: e0bff417 ldw r2,-48(fp) + 801ed14: 1001703a wrctl status,r2 + + /* + * Now that access to the registers is complete, release the registers + * semaphore so that other threads can access the registers. + */ + ALT_SEM_POST (dev->regs_lock); + 801ed18: e0bff117 ldw r2,-60(fp) + 801ed1c: 10801817 ldw r2,96(r2) + 801ed20: 1009883a mov r4,r2 + 801ed24: 8015d840 call 8015d84 + + return 0; + 801ed28: 0005883a mov r2,zero + +} + 801ed2c: e037883a mov sp,fp + 801ed30: dfc00117 ldw ra,4(sp) + 801ed34: df000017 ldw fp,0(sp) + 801ed38: dec00204 addi sp,sp,8 + 801ed3c: f800283a ret + +0801ed40 : + */ +int alt_msgdma_construct_standard_st_to_mm_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_standard_descriptor *descriptor, + alt_u32 *write_address, alt_u32 length, alt_u32 control) +{ + 801ed40: defff804 addi sp,sp,-32 + 801ed44: dfc00715 stw ra,28(sp) + 801ed48: df000615 stw fp,24(sp) + 801ed4c: df000604 addi fp,sp,24 + 801ed50: e13fff15 stw r4,-4(fp) + 801ed54: e17ffe15 stw r5,-8(fp) + 801ed58: e1bffd15 stw r6,-12(fp) + 801ed5c: e1fffc15 stw r7,-16(fp) + return alt_msgdma_construct_standard_descriptor(dev, descriptor, NULL, + 801ed60: e0800217 ldw r2,8(fp) + 801ed64: d8800115 stw r2,4(sp) + 801ed68: e0bffc17 ldw r2,-16(fp) + 801ed6c: d8800015 stw r2,0(sp) + 801ed70: e1fffd17 ldw r7,-12(fp) + 801ed74: 000d883a mov r6,zero + 801ed78: e17ffe17 ldw r5,-8(fp) + 801ed7c: e13fff17 ldw r4,-4(fp) + 801ed80: 801e41c0 call 801e41c + write_address, length, control); +} + 801ed84: e037883a mov sp,fp + 801ed88: dfc00117 ldw ra,4(sp) + 801ed8c: df000017 ldw fp,0(sp) + 801ed90: dec00204 addi sp,sp,8 + 801ed94: f800283a ret + +0801ed98 : + alt_msgdma_dev *dev, + alt_msgdma_standard_descriptor *descriptor, + alt_u32 *read_address, + alt_u32 length, + alt_u32 control) +{ + 801ed98: defff804 addi sp,sp,-32 + 801ed9c: dfc00715 stw ra,28(sp) + 801eda0: df000615 stw fp,24(sp) + 801eda4: df000604 addi fp,sp,24 + 801eda8: e13fff15 stw r4,-4(fp) + 801edac: e17ffe15 stw r5,-8(fp) + 801edb0: e1bffd15 stw r6,-12(fp) + 801edb4: e1fffc15 stw r7,-16(fp) + return alt_msgdma_construct_standard_descriptor(dev, descriptor, read_address, + 801edb8: e0800217 ldw r2,8(fp) + 801edbc: d8800115 stw r2,4(sp) + 801edc0: e0bffc17 ldw r2,-16(fp) + 801edc4: d8800015 stw r2,0(sp) + 801edc8: 000f883a mov r7,zero + 801edcc: e1bffd17 ldw r6,-12(fp) + 801edd0: e17ffe17 ldw r5,-8(fp) + 801edd4: e13fff17 ldw r4,-4(fp) + 801edd8: 801e41c0 call 801e41c + NULL, length, control); + +} + 801eddc: e037883a mov sp,fp + 801ede0: dfc00117 ldw ra,4(sp) + 801ede4: df000017 ldw fp,0(sp) + 801ede8: dec00204 addi sp,sp,8 + 801edec: f800283a ret + +0801edf0 : + alt_msgdma_standard_descriptor *descriptor, + alt_u32 *read_address, + alt_u32 *write_address, + alt_u32 length, + alt_u32 control) +{ + 801edf0: defff804 addi sp,sp,-32 + 801edf4: dfc00715 stw ra,28(sp) + 801edf8: df000615 stw fp,24(sp) + 801edfc: df000604 addi fp,sp,24 + 801ee00: e13fff15 stw r4,-4(fp) + 801ee04: e17ffe15 stw r5,-8(fp) + 801ee08: e1bffd15 stw r6,-12(fp) + 801ee0c: e1fffc15 stw r7,-16(fp) + return alt_msgdma_construct_standard_descriptor(dev, descriptor, read_address, + 801ee10: e0800317 ldw r2,12(fp) + 801ee14: d8800115 stw r2,4(sp) + 801ee18: e0800217 ldw r2,8(fp) + 801ee1c: d8800015 stw r2,0(sp) + 801ee20: e1fffc17 ldw r7,-16(fp) + 801ee24: e1bffd17 ldw r6,-12(fp) + 801ee28: e17ffe17 ldw r5,-8(fp) + 801ee2c: e13fff17 ldw r4,-4(fp) + 801ee30: 801e41c0 call 801e41c + write_address, length, control); +} + 801ee34: e037883a mov sp,fp + 801ee38: dfc00117 ldw ra,4(sp) + 801ee3c: df000017 ldw fp,0(sp) + 801ee40: dec00204 addi sp,sp,8 + 801ee44: f800283a ret + +0801ee48 : + alt_u32 length, + alt_u32 control, + alt_u16 sequence_number, + alt_u8 write_burst_count, + alt_u16 write_stride) +{ + 801ee48: defff004 addi sp,sp,-64 + 801ee4c: dfc00f15 stw ra,60(sp) + 801ee50: df000e15 stw fp,56(sp) + 801ee54: df000e04 addi fp,sp,56 + 801ee58: e13fff15 stw r4,-4(fp) + 801ee5c: e17ffe15 stw r5,-8(fp) + 801ee60: e1bffd15 stw r6,-12(fp) + 801ee64: e1fffc15 stw r7,-16(fp) + 801ee68: e1000317 ldw r4,12(fp) + 801ee6c: e0c00417 ldw r3,16(fp) + 801ee70: e0800517 ldw r2,20(fp) + 801ee74: e13ffb0d sth r4,-20(fp) + 801ee78: e0fffa05 stb r3,-24(fp) + 801ee7c: e0bff90d sth r2,-28(fp) + return alt_msgdma_construct_extended_descriptor(dev, descriptor, + 801ee80: e0bffb0b ldhu r2,-20(fp) + 801ee84: e0fffa03 ldbu r3,-24(fp) + 801ee88: e13ff90b ldhu r4,-28(fp) + 801ee8c: d9000615 stw r4,24(sp) + 801ee90: d8000515 stw zero,20(sp) + 801ee94: d8c00415 stw r3,16(sp) + 801ee98: d8000315 stw zero,12(sp) + 801ee9c: d8800215 stw r2,8(sp) + 801eea0: e0800217 ldw r2,8(fp) + 801eea4: d8800115 stw r2,4(sp) + 801eea8: e0bffc17 ldw r2,-16(fp) + 801eeac: d8800015 stw r2,0(sp) + 801eeb0: e1fffd17 ldw r7,-12(fp) + 801eeb4: 000d883a mov r6,zero + 801eeb8: e17ffe17 ldw r5,-8(fp) + 801eebc: e13fff17 ldw r4,-4(fp) + 801eec0: 801e4a80 call 801e4a8 + NULL, write_address, length, control, sequence_number, 0, + write_burst_count, 0, write_stride); +} + 801eec4: e037883a mov sp,fp + 801eec8: dfc00117 ldw ra,4(sp) + 801eecc: df000017 ldw fp,0(sp) + 801eed0: dec00204 addi sp,sp,8 + 801eed4: f800283a ret + +0801eed8 : + alt_u32 length, + alt_u32 control, + alt_u16 sequence_number, + alt_u8 read_burst_count, + alt_u16 read_stride) +{ + 801eed8: defff004 addi sp,sp,-64 + 801eedc: dfc00f15 stw ra,60(sp) + 801eee0: df000e15 stw fp,56(sp) + 801eee4: df000e04 addi fp,sp,56 + 801eee8: e13fff15 stw r4,-4(fp) + 801eeec: e17ffe15 stw r5,-8(fp) + 801eef0: e1bffd15 stw r6,-12(fp) + 801eef4: e1fffc15 stw r7,-16(fp) + 801eef8: e1000317 ldw r4,12(fp) + 801eefc: e0c00417 ldw r3,16(fp) + 801ef00: e0800517 ldw r2,20(fp) + 801ef04: e13ffb0d sth r4,-20(fp) + 801ef08: e0fffa05 stb r3,-24(fp) + 801ef0c: e0bff90d sth r2,-28(fp) + return alt_msgdma_construct_extended_descriptor(dev, descriptor, read_address, + 801ef10: e0bffb0b ldhu r2,-20(fp) + 801ef14: e0fffa03 ldbu r3,-24(fp) + 801ef18: e13ff90b ldhu r4,-28(fp) + 801ef1c: d8000615 stw zero,24(sp) + 801ef20: d9000515 stw r4,20(sp) + 801ef24: d8000415 stw zero,16(sp) + 801ef28: d8c00315 stw r3,12(sp) + 801ef2c: d8800215 stw r2,8(sp) + 801ef30: e0800217 ldw r2,8(fp) + 801ef34: d8800115 stw r2,4(sp) + 801ef38: e0bffc17 ldw r2,-16(fp) + 801ef3c: d8800015 stw r2,0(sp) + 801ef40: 000f883a mov r7,zero + 801ef44: e1bffd17 ldw r6,-12(fp) + 801ef48: e17ffe17 ldw r5,-8(fp) + 801ef4c: e13fff17 ldw r4,-4(fp) + 801ef50: 801e4a80 call 801e4a8 + NULL, length, control, sequence_number, read_burst_count, 0, + read_stride, 0); + +} + 801ef54: e037883a mov sp,fp + 801ef58: dfc00117 ldw ra,4(sp) + 801ef5c: df000017 ldw fp,0(sp) + 801ef60: dec00204 addi sp,sp,8 + 801ef64: f800283a ret + +0801ef68 : + alt_u16 sequence_number, + alt_u8 read_burst_count, + alt_u8 write_burst_count, + alt_u16 read_stride, + alt_u16 write_stride) +{ + 801ef68: deffee04 addi sp,sp,-72 + 801ef6c: dfc01115 stw ra,68(sp) + 801ef70: df001015 stw fp,64(sp) + 801ef74: df001004 addi fp,sp,64 + 801ef78: e13fff15 stw r4,-4(fp) + 801ef7c: e17ffe15 stw r5,-8(fp) + 801ef80: e1bffd15 stw r6,-12(fp) + 801ef84: e1fffc15 stw r7,-16(fp) + 801ef88: e1800417 ldw r6,16(fp) + 801ef8c: e1400517 ldw r5,20(fp) + 801ef90: e1000617 ldw r4,24(fp) + 801ef94: e0c00717 ldw r3,28(fp) + 801ef98: e0800817 ldw r2,32(fp) + 801ef9c: e1bffb0d sth r6,-20(fp) + 801efa0: e17ffa05 stb r5,-24(fp) + 801efa4: e13ff905 stb r4,-28(fp) + 801efa8: e0fff80d sth r3,-32(fp) + 801efac: e0bff70d sth r2,-36(fp) + return alt_msgdma_construct_extended_descriptor(dev, descriptor, + 801efb0: e0bffb0b ldhu r2,-20(fp) + 801efb4: e0fffa03 ldbu r3,-24(fp) + 801efb8: e13ff903 ldbu r4,-28(fp) + 801efbc: e17ff80b ldhu r5,-32(fp) + 801efc0: e1bff70b ldhu r6,-36(fp) + 801efc4: d9800615 stw r6,24(sp) + 801efc8: d9400515 stw r5,20(sp) + 801efcc: d9000415 stw r4,16(sp) + 801efd0: d8c00315 stw r3,12(sp) + 801efd4: d8800215 stw r2,8(sp) + 801efd8: e0800317 ldw r2,12(fp) + 801efdc: d8800115 stw r2,4(sp) + 801efe0: e0800217 ldw r2,8(fp) + 801efe4: d8800015 stw r2,0(sp) + 801efe8: e1fffc17 ldw r7,-16(fp) + 801efec: e1bffd17 ldw r6,-12(fp) + 801eff0: e17ffe17 ldw r5,-8(fp) + 801eff4: e13fff17 ldw r4,-4(fp) + 801eff8: 801e4a80 call 801e4a8 + read_address, write_address, length, control, sequence_number, + read_burst_count, write_burst_count, read_stride, write_stride); + +} + 801effc: e037883a mov sp,fp + 801f000: dfc00117 ldw ra,4(sp) + 801f004: df000017 ldw fp,0(sp) + 801f008: dec00204 addi sp,sp,8 + 801f00c: f800283a ret + +0801f010 : + alt_msgdma_prefetcher_standard_descriptor *descriptor, + alt_u32 read_address, + alt_u32 write_address, + alt_u32 length, + alt_u32 control) +{ + 801f010: defffb04 addi sp,sp,-20 + 801f014: df000415 stw fp,16(sp) + 801f018: df000404 addi fp,sp,16 + 801f01c: e13fff15 stw r4,-4(fp) + 801f020: e17ffe15 stw r5,-8(fp) + 801f024: e1bffd15 stw r6,-12(fp) + 801f028: e1fffc15 stw r7,-16(fp) + if(dev->max_byte < length || + 801f02c: e0bfff17 ldw r2,-4(fp) + 801f030: 10c01217 ldw r3,72(r2) + 801f034: e0800117 ldw r2,4(fp) + 801f038: 18800436 bltu r3,r2,801f04c + dev->enhanced_features != 0 + 801f03c: e0bfff17 ldw r2,-4(fp) + 801f040: 10801703 ldbu r2,92(r2) + if(dev->max_byte < length || + 801f044: 10803fcc andi r2,r2,255 + 801f048: 10000226 beq r2,zero,801f054 + ) + { + return -EINVAL; + 801f04c: 00bffa84 movi r2,-22 + 801f050: 00001406 br 801f0a4 + } + descriptor->read_address = read_address; + 801f054: e0bffe17 ldw r2,-8(fp) + 801f058: e0fffd17 ldw r3,-12(fp) + 801f05c: 10c00015 stw r3,0(r2) + descriptor->write_address = write_address; + 801f060: e0bffe17 ldw r2,-8(fp) + 801f064: e0fffc17 ldw r3,-16(fp) + 801f068: 10c00115 stw r3,4(r2) + descriptor->transfer_length = length; + 801f06c: e0bffe17 ldw r2,-8(fp) + 801f070: e0c00117 ldw r3,4(fp) + 801f074: 10c00215 stw r3,8(r2) + /* have descriptor point to itself for park_mode */ + descriptor->next_desc_ptr = (alt_u32)descriptor; + 801f078: e0fffe17 ldw r3,-8(fp) + 801f07c: e0bffe17 ldw r2,-8(fp) + 801f080: 10c00315 stw r3,12(r2) + + /* clear control own_by_hw bit field (SW owns this descriptor)*/ + descriptor->control = (control + & ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_CLR_MASK) + | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK; + 801f084: e0c00217 ldw r3,8(fp) + 801f088: 00900034 movhi r2,16384 + 801f08c: 10bfffc4 addi r2,r2,-1 + 801f090: 1884703a and r2,r3,r2 + 801f094: 10e00034 orhi r3,r2,32768 + descriptor->control = (control + 801f098: e0bffe17 ldw r2,-8(fp) + 801f09c: 10c00715 stw r3,28(r2) + + return 0; + 801f0a0: 0005883a mov r2,zero +} + 801f0a4: e037883a mov sp,fp + 801f0a8: df000017 ldw fp,0(sp) + 801f0ac: dec00104 addi sp,sp,4 + 801f0b0: f800283a ret + +0801f0b4 : + alt_u16 sequence_number, + alt_u8 read_burst_count, + alt_u8 write_burst_count, + alt_u16 read_stride, + alt_u16 write_stride) +{ + 801f0b4: defff404 addi sp,sp,-48 + 801f0b8: df000b15 stw fp,44(sp) + 801f0bc: df000b04 addi fp,sp,44 + 801f0c0: e13ffd15 stw r4,-12(fp) + 801f0c4: e17ffc15 stw r5,-16(fp) + 801f0c8: e1bffb15 stw r6,-20(fp) + 801f0cc: e1fffa15 stw r7,-24(fp) + 801f0d0: e1800517 ldw r6,20(fp) + 801f0d4: e1400617 ldw r5,24(fp) + 801f0d8: e1000717 ldw r4,28(fp) + 801f0dc: e0c00817 ldw r3,32(fp) + 801f0e0: e0800917 ldw r2,36(fp) + 801f0e4: e1bff90d sth r6,-28(fp) + 801f0e8: e17ff805 stb r5,-32(fp) + 801f0ec: e13ff705 stb r4,-36(fp) + 801f0f0: e0fff60d sth r3,-40(fp) + 801f0f4: e0bff50d sth r2,-44(fp) + msgdma_addr64 node_addr; + + if(dev->max_byte < length || + 801f0f8: e0bffd17 ldw r2,-12(fp) + 801f0fc: 10c01217 ldw r3,72(r2) + 801f100: e0800317 ldw r2,12(fp) + 801f104: 18801936 bltu r3,r2,801f16c + dev->max_stride < read_stride || + 801f108: e13ffd17 ldw r4,-12(fp) + 801f10c: 20801317 ldw r2,76(r4) + 801f110: 20c01417 ldw r3,80(r4) + 801f114: e13ff60b ldhu r4,-40(fp) + 801f118: 213fffcc andi r4,r4,65535 + 801f11c: 2015883a mov r10,r4 + 801f120: 0017883a mov r11,zero + if(dev->max_byte < length || + 801f124: 1ac01136 bltu r3,r11,801f16c + 801f128: 58c0011e bne r11,r3,801f130 + 801f12c: 12800f36 bltu r2,r10,801f16c + dev->max_stride < write_stride || + 801f130: e13ffd17 ldw r4,-12(fp) + 801f134: 20801317 ldw r2,76(r4) + 801f138: 20c01417 ldw r3,80(r4) + 801f13c: e13ff50b ldhu r4,-44(fp) + 801f140: 213fffcc andi r4,r4,65535 + 801f144: 2011883a mov r8,r4 + 801f148: 0013883a mov r9,zero + dev->max_stride < read_stride || + 801f14c: 1a400736 bltu r3,r9,801f16c + 801f150: 48c0011e bne r9,r3,801f158 + 801f154: 12000536 bltu r2,r8,801f16c + dev->enhanced_features != 1 + 801f158: e0bffd17 ldw r2,-12(fp) + 801f15c: 10801703 ldbu r2,92(r2) + dev->max_stride < write_stride || + 801f160: 10803fcc andi r2,r2,255 + 801f164: 10800060 cmpeqi r2,r2,1 + 801f168: 1000021e bne r2,zero,801f174 + ) + { + return -EINVAL; + 801f16c: 00bffa84 movi r2,-22 + 801f170: 00003106 br 801f238 + } + + descriptor->read_address_high = read_address_high; + 801f174: e0bffc17 ldw r2,-16(fp) + 801f178: e0fffb17 ldw r3,-20(fp) + 801f17c: 10c00915 stw r3,36(r2) + descriptor->read_address_low = read_address_low; + 801f180: e0bffc17 ldw r2,-16(fp) + 801f184: e0fffa17 ldw r3,-24(fp) + 801f188: 10c00015 stw r3,0(r2) + descriptor->write_address_high = write_address_high; + 801f18c: e0bffc17 ldw r2,-16(fp) + 801f190: e0c00117 ldw r3,4(fp) + 801f194: 10c00a15 stw r3,40(r2) + descriptor->write_address_low = write_address_low; + 801f198: e0bffc17 ldw r2,-16(fp) + 801f19c: e0c00217 ldw r3,8(fp) + 801f1a0: 10c00115 stw r3,4(r2) + descriptor->transfer_length = length; + 801f1a4: e0bffc17 ldw r2,-16(fp) + 801f1a8: e0c00317 ldw r3,12(fp) + 801f1ac: 10c00215 stw r3,8(r2) + descriptor->sequence_number = sequence_number; + 801f1b0: e0bffc17 ldw r2,-16(fp) + 801f1b4: e0fff90b ldhu r3,-28(fp) + 801f1b8: 10c0070d sth r3,28(r2) + descriptor->read_burst_count = read_burst_count; + 801f1bc: e0bffc17 ldw r2,-16(fp) + 801f1c0: e0fff803 ldbu r3,-32(fp) + 801f1c4: 10c00785 stb r3,30(r2) + descriptor->write_burst_count = write_burst_count; + 801f1c8: e0bffc17 ldw r2,-16(fp) + 801f1cc: e0fff703 ldbu r3,-36(fp) + 801f1d0: 10c007c5 stb r3,31(r2) + descriptor->read_stride = read_stride; + 801f1d4: e0bffc17 ldw r2,-16(fp) + 801f1d8: e0fff60b ldhu r3,-40(fp) + 801f1dc: 10c0080d sth r3,32(r2) + descriptor->write_stride = write_stride; + 801f1e0: e0bffc17 ldw r2,-16(fp) + 801f1e4: e0fff50b ldhu r3,-44(fp) + 801f1e8: 10c0088d sth r3,34(r2) + /* have descriptor point to itself */ + node_addr.u64 = (uintptr_t)descriptor; + 801f1ec: e0bffc17 ldw r2,-16(fp) + 801f1f0: 1019883a mov r12,r2 + 801f1f4: 001b883a mov r13,zero + 801f1f8: e33ffe15 stw r12,-8(fp) + 801f1fc: e37fff15 stw r13,-4(fp) + descriptor->next_desc_ptr_low = node_addr.u32[0]; + 801f200: e0fffe17 ldw r3,-8(fp) + 801f204: e0bffc17 ldw r2,-16(fp) + 801f208: 10c00315 stw r3,12(r2) + descriptor->next_desc_ptr_high = node_addr.u32[1]; + 801f20c: e0ffff17 ldw r3,-4(fp) + 801f210: e0bffc17 ldw r2,-16(fp) + 801f214: 10c00b15 stw r3,44(r2) + + /* clear control own_by_hw bit field (SW still owns this descriptor). */ + descriptor->control = (control + & ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_CLR_MASK) + | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK; + 801f218: e0c00417 ldw r3,16(fp) + 801f21c: 00900034 movhi r2,16384 + 801f220: 10bfffc4 addi r2,r2,-1 + 801f224: 1884703a and r2,r3,r2 + 801f228: 10e00034 orhi r3,r2,32768 + descriptor->control = (control + 801f22c: e0bffc17 ldw r2,-16(fp) + 801f230: 10c00f15 stw r3,60(r2) + + return 0 ; + 801f234: 0005883a mov r2,zero +} + 801f238: e037883a mov sp,fp + 801f23c: df000017 ldw fp,0(sp) + 801f240: dec00104 addi sp,sp,4 + 801f244: f800283a ret + +0801f248 : + alt_msgdma_prefetcher_standard_descriptor *descriptor, + alt_u32 read_address, + alt_u32 write_address, + alt_u32 length, + alt_u32 control) +{ + 801f248: defff804 addi sp,sp,-32 + 801f24c: dfc00715 stw ra,28(sp) + 801f250: df000615 stw fp,24(sp) + 801f254: df000604 addi fp,sp,24 + 801f258: e13fff15 stw r4,-4(fp) + 801f25c: e17ffe15 stw r5,-8(fp) + 801f260: e1bffd15 stw r6,-12(fp) + 801f264: e1fffc15 stw r7,-16(fp) + return alt_msgdma_construct_prefetcher_standard_descriptor(dev, descriptor, + 801f268: e0800317 ldw r2,12(fp) + 801f26c: d8800115 stw r2,4(sp) + 801f270: e0800217 ldw r2,8(fp) + 801f274: d8800015 stw r2,0(sp) + 801f278: e1fffc17 ldw r7,-16(fp) + 801f27c: e1bffd17 ldw r6,-12(fp) + 801f280: e17ffe17 ldw r5,-8(fp) + 801f284: e13fff17 ldw r4,-4(fp) + 801f288: 801f0100 call 801f010 + read_address, write_address, length, control); +} + 801f28c: e037883a mov sp,fp + 801f290: dfc00117 ldw ra,4(sp) + 801f294: df000017 ldw fp,0(sp) + 801f298: dec00204 addi sp,sp,8 + 801f29c: f800283a ret + +0801f2a0 : + alt_msgdma_dev *dev, + alt_msgdma_prefetcher_standard_descriptor *descriptor, + alt_u32 write_address, + alt_u32 length, + alt_u32 control) +{ + 801f2a0: defff804 addi sp,sp,-32 + 801f2a4: dfc00715 stw ra,28(sp) + 801f2a8: df000615 stw fp,24(sp) + 801f2ac: df000604 addi fp,sp,24 + 801f2b0: e13fff15 stw r4,-4(fp) + 801f2b4: e17ffe15 stw r5,-8(fp) + 801f2b8: e1bffd15 stw r6,-12(fp) + 801f2bc: e1fffc15 stw r7,-16(fp) + return alt_msgdma_construct_prefetcher_standard_descriptor(dev, descriptor, + 801f2c0: e0800217 ldw r2,8(fp) + 801f2c4: d8800115 stw r2,4(sp) + 801f2c8: e0bffc17 ldw r2,-16(fp) + 801f2cc: d8800015 stw r2,0(sp) + 801f2d0: e1fffd17 ldw r7,-12(fp) + 801f2d4: 000d883a mov r6,zero + 801f2d8: e17ffe17 ldw r5,-8(fp) + 801f2dc: e13fff17 ldw r4,-4(fp) + 801f2e0: 801f0100 call 801f010 + 0, write_address, length, control); +} + 801f2e4: e037883a mov sp,fp + 801f2e8: dfc00117 ldw ra,4(sp) + 801f2ec: df000017 ldw fp,0(sp) + 801f2f0: dec00204 addi sp,sp,8 + 801f2f4: f800283a ret + +0801f2f8 : + alt_msgdma_dev *dev, + alt_msgdma_prefetcher_standard_descriptor *descriptor, + alt_u32 read_address, + alt_u32 length, + alt_u32 control) +{ + 801f2f8: defff804 addi sp,sp,-32 + 801f2fc: dfc00715 stw ra,28(sp) + 801f300: df000615 stw fp,24(sp) + 801f304: df000604 addi fp,sp,24 + 801f308: e13fff15 stw r4,-4(fp) + 801f30c: e17ffe15 stw r5,-8(fp) + 801f310: e1bffd15 stw r6,-12(fp) + 801f314: e1fffc15 stw r7,-16(fp) + return alt_msgdma_construct_prefetcher_standard_descriptor(dev, descriptor, + 801f318: e0800217 ldw r2,8(fp) + 801f31c: d8800115 stw r2,4(sp) + 801f320: e0bffc17 ldw r2,-16(fp) + 801f324: d8800015 stw r2,0(sp) + 801f328: 000f883a mov r7,zero + 801f32c: e1bffd17 ldw r6,-12(fp) + 801f330: e17ffe17 ldw r5,-8(fp) + 801f334: e13fff17 ldw r4,-4(fp) + 801f338: 801f0100 call 801f010 + read_address, 0, length, control); +} + 801f33c: e037883a mov sp,fp + 801f340: dfc00117 ldw ra,4(sp) + 801f344: df000017 ldw fp,0(sp) + 801f348: dec00204 addi sp,sp,8 + 801f34c: f800283a ret + +0801f350 : + alt_u32 length, + alt_u32 control, + alt_u16 sequence_number, + alt_u8 write_burst_count, + alt_u16 write_stride) +{ + 801f350: deffee04 addi sp,sp,-72 + 801f354: dfc01115 stw ra,68(sp) + 801f358: df001015 stw fp,64(sp) + 801f35c: df001004 addi fp,sp,64 + 801f360: e13fff15 stw r4,-4(fp) + 801f364: e17ffe15 stw r5,-8(fp) + 801f368: e1bffd15 stw r6,-12(fp) + 801f36c: e1fffc15 stw r7,-16(fp) + 801f370: e1000417 ldw r4,16(fp) + 801f374: e0c00517 ldw r3,20(fp) + 801f378: e0800617 ldw r2,24(fp) + 801f37c: e13ffb0d sth r4,-20(fp) + 801f380: e0fffa05 stb r3,-24(fp) + 801f384: e0bff90d sth r2,-28(fp) + return alt_msgdma_construct_prefetcher_extended_descriptor(dev, descriptor, + 801f388: e0bffb0b ldhu r2,-20(fp) + 801f38c: e0fffa03 ldbu r3,-24(fp) + 801f390: e13ff90b ldhu r4,-28(fp) + 801f394: d9000815 stw r4,32(sp) + 801f398: d8000715 stw zero,28(sp) + 801f39c: d8c00615 stw r3,24(sp) + 801f3a0: d8000515 stw zero,20(sp) + 801f3a4: d8800415 stw r2,16(sp) + 801f3a8: e0800317 ldw r2,12(fp) + 801f3ac: d8800315 stw r2,12(sp) + 801f3b0: e0800217 ldw r2,8(fp) + 801f3b4: d8800215 stw r2,8(sp) + 801f3b8: e0bffc17 ldw r2,-16(fp) + 801f3bc: d8800115 stw r2,4(sp) + 801f3c0: e0bffd17 ldw r2,-12(fp) + 801f3c4: d8800015 stw r2,0(sp) + 801f3c8: 000f883a mov r7,zero + 801f3cc: 000d883a mov r6,zero + 801f3d0: e17ffe17 ldw r5,-8(fp) + 801f3d4: e13fff17 ldw r4,-4(fp) + 801f3d8: 801f0b40 call 801f0b4 + 0, 0, write_address_high, write_address_low, length, control, + sequence_number, 0, write_burst_count, 0, write_stride); +} + 801f3dc: e037883a mov sp,fp + 801f3e0: dfc00117 ldw ra,4(sp) + 801f3e4: df000017 ldw fp,0(sp) + 801f3e8: dec00204 addi sp,sp,8 + 801f3ec: f800283a ret + +0801f3f0 : + alt_u32 length, + alt_u32 control, + alt_u16 sequence_number, + alt_u8 read_burst_count, + alt_u16 read_stride) +{ + 801f3f0: deffee04 addi sp,sp,-72 + 801f3f4: dfc01115 stw ra,68(sp) + 801f3f8: df001015 stw fp,64(sp) + 801f3fc: df001004 addi fp,sp,64 + 801f400: e13fff15 stw r4,-4(fp) + 801f404: e17ffe15 stw r5,-8(fp) + 801f408: e1bffd15 stw r6,-12(fp) + 801f40c: e1fffc15 stw r7,-16(fp) + 801f410: e1000417 ldw r4,16(fp) + 801f414: e0c00517 ldw r3,20(fp) + 801f418: e0800617 ldw r2,24(fp) + 801f41c: e13ffb0d sth r4,-20(fp) + 801f420: e0fffa05 stb r3,-24(fp) + 801f424: e0bff90d sth r2,-28(fp) + return alt_msgdma_construct_prefetcher_extended_descriptor(dev, descriptor, + 801f428: e0bffb0b ldhu r2,-20(fp) + 801f42c: e0fffa03 ldbu r3,-24(fp) + 801f430: e13ff90b ldhu r4,-28(fp) + 801f434: d8000815 stw zero,32(sp) + 801f438: d9000715 stw r4,28(sp) + 801f43c: d8000615 stw zero,24(sp) + 801f440: d8c00515 stw r3,20(sp) + 801f444: d8800415 stw r2,16(sp) + 801f448: e0800317 ldw r2,12(fp) + 801f44c: d8800315 stw r2,12(sp) + 801f450: e0800217 ldw r2,8(fp) + 801f454: d8800215 stw r2,8(sp) + 801f458: d8000115 stw zero,4(sp) + 801f45c: d8000015 stw zero,0(sp) + 801f460: e1fffc17 ldw r7,-16(fp) + 801f464: e1bffd17 ldw r6,-12(fp) + 801f468: e17ffe17 ldw r5,-8(fp) + 801f46c: e13fff17 ldw r4,-4(fp) + 801f470: 801f0b40 call 801f0b4 + read_address_high, read_address_low, 0, 0, length, control, + sequence_number, read_burst_count, 0, read_stride, 0); +} + 801f474: e037883a mov sp,fp + 801f478: dfc00117 ldw ra,4(sp) + 801f47c: df000017 ldw fp,0(sp) + 801f480: dec00204 addi sp,sp,8 + 801f484: f800283a ret + +0801f488 : + alt_u16 sequence_number, + alt_u8 read_burst_count, + alt_u8 write_burst_count, + alt_u16 read_stride, + alt_u16 write_stride) +{ + 801f488: deffec04 addi sp,sp,-80 + 801f48c: dfc01315 stw ra,76(sp) + 801f490: df001215 stw fp,72(sp) + 801f494: df001204 addi fp,sp,72 + 801f498: e13fff15 stw r4,-4(fp) + 801f49c: e17ffe15 stw r5,-8(fp) + 801f4a0: e1bffd15 stw r6,-12(fp) + 801f4a4: e1fffc15 stw r7,-16(fp) + 801f4a8: e1800617 ldw r6,24(fp) + 801f4ac: e1400717 ldw r5,28(fp) + 801f4b0: e1000817 ldw r4,32(fp) + 801f4b4: e0c00917 ldw r3,36(fp) + 801f4b8: e0800a17 ldw r2,40(fp) + 801f4bc: e1bffb0d sth r6,-20(fp) + 801f4c0: e17ffa05 stb r5,-24(fp) + 801f4c4: e13ff905 stb r4,-28(fp) + 801f4c8: e0fff80d sth r3,-32(fp) + 801f4cc: e0bff70d sth r2,-36(fp) + return alt_msgdma_construct_prefetcher_extended_descriptor(dev, descriptor, + 801f4d0: e0bffb0b ldhu r2,-20(fp) + 801f4d4: e0fffa03 ldbu r3,-24(fp) + 801f4d8: e13ff903 ldbu r4,-28(fp) + 801f4dc: e17ff80b ldhu r5,-32(fp) + 801f4e0: e1bff70b ldhu r6,-36(fp) + 801f4e4: d9800815 stw r6,32(sp) + 801f4e8: d9400715 stw r5,28(sp) + 801f4ec: d9000615 stw r4,24(sp) + 801f4f0: d8c00515 stw r3,20(sp) + 801f4f4: d8800415 stw r2,16(sp) + 801f4f8: e0800517 ldw r2,20(fp) + 801f4fc: d8800315 stw r2,12(sp) + 801f500: e0800417 ldw r2,16(fp) + 801f504: d8800215 stw r2,8(sp) + 801f508: e0800317 ldw r2,12(fp) + 801f50c: d8800115 stw r2,4(sp) + 801f510: e0800217 ldw r2,8(fp) + 801f514: d8800015 stw r2,0(sp) + 801f518: e1fffc17 ldw r7,-16(fp) + 801f51c: e1bffd17 ldw r6,-12(fp) + 801f520: e17ffe17 ldw r5,-8(fp) + 801f524: e13fff17 ldw r4,-4(fp) + 801f528: 801f0b40 call 801f0b4 + read_address_high, read_address_low, write_address_high, + write_address_low, length, control, sequence_number, + read_burst_count, write_burst_count, read_stride, write_stride); + +} + 801f52c: e037883a mov sp,fp + 801f530: dfc00117 ldw ra,4(sp) + 801f534: df000017 ldw fp,0(sp) + 801f538: dec00204 addi sp,sp,8 + 801f53c: f800283a ret + +0801f540 : + * descriptor.next_ptr not pointing back to itslef) + */ +int alt_msgdma_prefetcher_add_standard_desc_to_list ( + alt_msgdma_prefetcher_standard_descriptor** list, + alt_msgdma_prefetcher_standard_descriptor* descriptor) +{ + 801f540: defffc04 addi sp,sp,-16 + 801f544: df000315 stw fp,12(sp) + 801f548: df000304 addi fp,sp,12 + 801f54c: e13ffe15 stw r4,-8(fp) + 801f550: e17ffd15 stw r5,-12(fp) + alt_msgdma_prefetcher_standard_descriptor *last_descr_ptr; + + if (descriptor == NULL) + 801f554: e0bffd17 ldw r2,-12(fp) + 801f558: 1000021e bne r2,zero,801f564 + { + return -EINVAL; /* this descriptor cannot be NULL */ + 801f55c: 00bffa84 movi r2,-22 + 801f560: 00002f06 br 801f620 + } + if (descriptor->next_desc_ptr != (alt_u32)descriptor) + 801f564: e0bffd17 ldw r2,-12(fp) + 801f568: 10c00317 ldw r3,12(r2) + 801f56c: e0bffd17 ldw r2,-12(fp) + 801f570: 18800226 beq r3,r2,801f57c + { + return -EINVAL; /* descriptor.next_ptr must point to itself */ + 801f574: 00bffa84 movi r2,-22 + 801f578: 00002906 br 801f620 + } + if (*list == NULL) + 801f57c: e0bffe17 ldw r2,-8(fp) + 801f580: 10800017 ldw r2,0(r2) + 801f584: 1000051e bne r2,zero,801f59c + { + *list = descriptor; /* make this root-node if list is empty */ + 801f588: e0bffe17 ldw r2,-8(fp) + 801f58c: e0fffd17 ldw r3,-12(fp) + 801f590: 10c00015 stw r3,0(r2) + return 0; /* successfully added */ + 801f594: 0005883a mov r2,zero + 801f598: 00002106 br 801f620 + } + if (*list == descriptor) + 801f59c: e0bffe17 ldw r2,-8(fp) + 801f5a0: 10800017 ldw r2,0(r2) + 801f5a4: e0fffd17 ldw r3,-12(fp) + 801f5a8: 1880021e bne r3,r2,801f5b4 + { + return -EINVAL; /* this descriptor cannot already be root-node */ + 801f5ac: 00bffa84 movi r2,-22 + 801f5b0: 00001b06 br 801f620 + } + + /* get to last node in the list */ + last_descr_ptr = *list; /* start at list root-node */ + 801f5b4: e0bffe17 ldw r2,-8(fp) + 801f5b8: 10800017 ldw r2,0(r2) + 801f5bc: e0bfff15 stw r2,-4(fp) + /* traverse list until you get the last node */ + while (last_descr_ptr->next_desc_ptr != (alt_u32)*list) + 801f5c0: 00000906 br 801f5e8 + { + if (last_descr_ptr->next_desc_ptr == (alt_u32)descriptor) + 801f5c4: e0bfff17 ldw r2,-4(fp) + 801f5c8: 10c00317 ldw r3,12(r2) + 801f5cc: e0bffd17 ldw r2,-12(fp) + 801f5d0: 1880021e bne r3,r2,801f5dc + { + return -EINVAL; /* descriptor cannot already be in the list */ + 801f5d4: 00bffa84 movi r2,-22 + 801f5d8: 00001106 br 801f620 + } + last_descr_ptr = + (alt_msgdma_prefetcher_standard_descriptor*)(last_descr_ptr->next_desc_ptr); + 801f5dc: e0bfff17 ldw r2,-4(fp) + 801f5e0: 10800317 ldw r2,12(r2) + last_descr_ptr = + 801f5e4: e0bfff15 stw r2,-4(fp) + while (last_descr_ptr->next_desc_ptr != (alt_u32)*list) + 801f5e8: e0bfff17 ldw r2,-4(fp) + 801f5ec: 10800317 ldw r2,12(r2) + 801f5f0: e0fffe17 ldw r3,-8(fp) + 801f5f4: 18c00017 ldw r3,0(r3) + 801f5f8: 10fff21e bne r2,r3,801f5c4 + } + /* add this descriptor to end of list */ + last_descr_ptr->next_desc_ptr = (alt_u32)((uintptr_t)descriptor); + 801f5fc: e0fffd17 ldw r3,-12(fp) + 801f600: e0bfff17 ldw r2,-4(fp) + 801f604: 10c00315 stw r3,12(r2) + /* ensure new last pointer points the start of the list */ + descriptor->next_desc_ptr = (alt_u32)((uintptr_t)*list); + 801f608: e0bffe17 ldw r2,-8(fp) + 801f60c: 10800017 ldw r2,0(r2) + 801f610: 1007883a mov r3,r2 + 801f614: e0bffd17 ldw r2,-12(fp) + 801f618: 10c00315 stw r3,12(r2) + return 0; /* successfully added */ + 801f61c: 0005883a mov r2,zero +} + 801f620: e037883a mov sp,fp + 801f624: df000017 ldw fp,0(sp) + 801f628: dec00104 addi sp,sp,4 + 801f62c: f800283a ret + +0801f630 : + +int alt_msgdma_prefetcher_add_extended_desc_to_list ( + alt_msgdma_prefetcher_extended_descriptor** list, + alt_msgdma_prefetcher_extended_descriptor* descriptor) +{ + 801f630: defff804 addi sp,sp,-32 + 801f634: df000715 stw fp,28(sp) + 801f638: df000704 addi fp,sp,28 + 801f63c: e13ffa15 stw r4,-24(fp) + 801f640: e17ff915 stw r5,-28(fp) + alt_msgdma_prefetcher_extended_descriptor *last_descr_ptr; + msgdma_addr64 root_node_addr, next_node_addr; + + if (descriptor == NULL) + 801f644: e13ff917 ldw r4,-28(fp) + 801f648: 2000021e bne r4,zero,801f654 + { + return -EINVAL; /* this descriptor cannot be NULL */ + 801f64c: 00bffa84 movi r2,-22 + 801f650: 00005906 br 801f7b8 + } + + next_node_addr.u64 = (uintptr_t)descriptor; + 801f654: e13ff917 ldw r4,-28(fp) + 801f658: 2015883a mov r10,r4 + 801f65c: 0017883a mov r11,zero + 801f660: e2bffb15 stw r10,-20(fp) + 801f664: e2fffc15 stw r11,-16(fp) + if( (descriptor->next_desc_ptr_low != next_node_addr.u32[0]) || + 801f668: e13ff917 ldw r4,-28(fp) + 801f66c: 21400317 ldw r5,12(r4) + 801f670: e13ffb17 ldw r4,-20(fp) + 801f674: 2900041e bne r5,r4,801f688 + (descriptor->next_desc_ptr_high != next_node_addr.u32[1])) + 801f678: e13ff917 ldw r4,-28(fp) + 801f67c: 21400b17 ldw r5,44(r4) + 801f680: e13ffc17 ldw r4,-16(fp) + if( (descriptor->next_desc_ptr_low != next_node_addr.u32[0]) || + 801f684: 29000226 beq r5,r4,801f690 + { + return -EINVAL; /* descriptor.next_ptr must point to itself */ + 801f688: 00bffa84 movi r2,-22 + 801f68c: 00004a06 br 801f7b8 + } + + if (*list == NULL) + 801f690: e13ffa17 ldw r4,-24(fp) + 801f694: 21000017 ldw r4,0(r4) + 801f698: 2000051e bne r4,zero,801f6b0 + { + *list = descriptor; /* make this the root-node if list is empty */ + 801f69c: e0bffa17 ldw r2,-24(fp) + 801f6a0: e0fff917 ldw r3,-28(fp) + 801f6a4: 10c00015 stw r3,0(r2) + return 0; + 801f6a8: 0005883a mov r2,zero + 801f6ac: 00004206 br 801f7b8 + } + if (*list == descriptor) + 801f6b0: e13ffa17 ldw r4,-24(fp) + 801f6b4: 21000017 ldw r4,0(r4) + 801f6b8: e17ff917 ldw r5,-28(fp) + 801f6bc: 2900021e bne r5,r4,801f6c8 + { + return -EINVAL; /* this descriptor cannot already be root-node */ + 801f6c0: 00bffa84 movi r2,-22 + 801f6c4: 00003c06 br 801f7b8 + } + + /* get to last node in the list */ + last_descr_ptr = *list; /* start at list root-node */ + 801f6c8: e13ffa17 ldw r4,-24(fp) + 801f6cc: 21000017 ldw r4,0(r4) + 801f6d0: e13fff15 stw r4,-4(fp) + /* the last nodes next ptr should point to the root node*/ + root_node_addr.u64 = (uintptr_t)*list; + 801f6d4: e13ffa17 ldw r4,-24(fp) + 801f6d8: 21000017 ldw r4,0(r4) + 801f6dc: 2011883a mov r8,r4 + 801f6e0: 0013883a mov r9,zero + 801f6e4: e23ffd15 stw r8,-12(fp) + 801f6e8: e27ffe15 stw r9,-8(fp) + + /* traverse list until you get the last node */ + while ((last_descr_ptr->next_desc_ptr_low != root_node_addr.u32[0]) + 801f6ec: 00001806 br 801f750 + || (last_descr_ptr->next_desc_ptr_high != root_node_addr.u32[1])) + { + /* first check if descriptor already in the list */ + next_node_addr.u64 = (uintptr_t)descriptor; + 801f6f0: e13ff917 ldw r4,-28(fp) + 801f6f4: 200d883a mov r6,r4 + 801f6f8: 000f883a mov r7,zero + 801f6fc: e1bffb15 stw r6,-20(fp) + 801f700: e1fffc15 stw r7,-16(fp) + if ((last_descr_ptr->next_desc_ptr_low == next_node_addr.u32[0]) + 801f704: e13fff17 ldw r4,-4(fp) + 801f708: 21400317 ldw r5,12(r4) + 801f70c: e13ffb17 ldw r4,-20(fp) + 801f710: 2900061e bne r5,r4,801f72c + && (last_descr_ptr->next_desc_ptr_high == next_node_addr.u32[1])) + 801f714: e13fff17 ldw r4,-4(fp) + 801f718: 21400b17 ldw r5,44(r4) + 801f71c: e13ffc17 ldw r4,-16(fp) + 801f720: 2900021e bne r5,r4,801f72c + { + return -EINVAL; /* descriptor cannot already be in the list */ + 801f724: 00bffa84 movi r2,-22 + 801f728: 00002306 br 801f7b8 + } + /* go to next node in list, using 64 bit address */ + next_node_addr.u32[0] = last_descr_ptr->next_desc_ptr_low; + 801f72c: e13fff17 ldw r4,-4(fp) + 801f730: 21000317 ldw r4,12(r4) + 801f734: e13ffb15 stw r4,-20(fp) + next_node_addr.u32[1] = last_descr_ptr->next_desc_ptr_high; + 801f738: e13fff17 ldw r4,-4(fp) + 801f73c: 21000b17 ldw r4,44(r4) + 801f740: e13ffc15 stw r4,-16(fp) + last_descr_ptr = + (alt_msgdma_prefetcher_extended_descriptor*)((uintptr_t)next_node_addr.u64); + 801f744: e13ffb17 ldw r4,-20(fp) + 801f748: e17ffc17 ldw r5,-16(fp) + last_descr_ptr = + 801f74c: e13fff15 stw r4,-4(fp) + while ((last_descr_ptr->next_desc_ptr_low != root_node_addr.u32[0]) + 801f750: e13fff17 ldw r4,-4(fp) + 801f754: 21400317 ldw r5,12(r4) + 801f758: e13ffd17 ldw r4,-12(fp) + 801f75c: 293fe41e bne r5,r4,801f6f0 + || (last_descr_ptr->next_desc_ptr_high != root_node_addr.u32[1])) + 801f760: e13fff17 ldw r4,-4(fp) + 801f764: 21400b17 ldw r5,44(r4) + 801f768: e13ffe17 ldw r4,-8(fp) + 801f76c: 293fe01e bne r5,r4,801f6f0 + } + /* add this descriptor to end of list */ + next_node_addr.u64 = (uintptr_t)descriptor; + 801f770: e13ff917 ldw r4,-28(fp) + 801f774: 2005883a mov r2,r4 + 801f778: 0007883a mov r3,zero + 801f77c: e0bffb15 stw r2,-20(fp) + 801f780: e0fffc15 stw r3,-16(fp) + last_descr_ptr->next_desc_ptr_low = next_node_addr.u32[0]; + 801f784: e0fffb17 ldw r3,-20(fp) + 801f788: e0bfff17 ldw r2,-4(fp) + 801f78c: 10c00315 stw r3,12(r2) + last_descr_ptr->next_desc_ptr_high = next_node_addr.u32[1]; + 801f790: e0fffc17 ldw r3,-16(fp) + 801f794: e0bfff17 ldw r2,-4(fp) + 801f798: 10c00b15 stw r3,44(r2) + /* ensure new last pointer points the beginning of the list */ + descriptor->next_desc_ptr_low = root_node_addr.u32[0]; + 801f79c: e0fffd17 ldw r3,-12(fp) + 801f7a0: e0bff917 ldw r2,-28(fp) + 801f7a4: 10c00315 stw r3,12(r2) + descriptor->next_desc_ptr_high = root_node_addr.u32[1]; + 801f7a8: e0fffe17 ldw r3,-8(fp) + 801f7ac: e0bff917 ldw r2,-28(fp) + 801f7b0: 10c00b15 stw r3,44(r2) + return 0; + 801f7b4: 0005883a mov r2,zero +} + 801f7b8: e037883a mov sp,fp + 801f7bc: df000017 ldw fp,0(sp) + 801f7c0: dec00104 addi sp,sp,4 + 801f7c4: f800283a ret + +0801f7c8 : + */ +int alt_msgdma_prefetcher_set_std_list_own_by_hw_bits ( + alt_msgdma_prefetcher_standard_descriptor *list, + alt_u8 last_desc_owned_by_sw, + alt_u8 dcache_flush_desc_list) +{ + 801f7c8: defff804 addi sp,sp,-32 + 801f7cc: dfc00715 stw ra,28(sp) + 801f7d0: df000615 stw fp,24(sp) + 801f7d4: df000604 addi fp,sp,24 + 801f7d8: e13ffc15 stw r4,-16(fp) + 801f7dc: 2805883a mov r2,r5 + 801f7e0: 3007883a mov r3,r6 + 801f7e4: e0bffb05 stb r2,-20(fp) + 801f7e8: 1805883a mov r2,r3 + 801f7ec: e0bffa05 stb r2,-24(fp) + alt_u32 descriptor_control_field = 0; + 801f7f0: e03ffd15 stw zero,-12(fp) + alt_msgdma_prefetcher_standard_descriptor *last_descr_ptr; + alt_u32 descriptor_count = 0; + 801f7f4: e03ffe15 stw zero,-8(fp) + + if (list == NULL) + 801f7f8: e0bffc17 ldw r2,-16(fp) + 801f7fc: 1000021e bne r2,zero,801f808 + { + return -EINVAL; /* this list cannot be empty */ + 801f800: 00bffa84 movi r2,-22 + 801f804: 00002f06 br 801f8c4 + } + + /* update all nodes in the list */ + last_descr_ptr = list; /* start at list root-node */ + 801f808: e0bffc17 ldw r2,-16(fp) + 801f80c: e0bfff15 stw r2,-4(fp) + /* traverse list to update all of the nodes */ + while (last_descr_ptr->next_desc_ptr != (alt_u32)list) + 801f810: 00000d06 br 801f848 + { + /* get current value */ + descriptor_control_field = last_descr_ptr->control; + 801f814: e0bfff17 ldw r2,-4(fp) + 801f818: 10800717 ldw r2,28(r2) + 801f81c: e0bffd15 stw r2,-12(fp) + /* update own_by_hw bit only */ + last_descr_ptr->control = descriptor_control_field + | ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET_MASK; + 801f820: e0bffd17 ldw r2,-12(fp) + 801f824: 10d00034 orhi r3,r2,16384 + last_descr_ptr->control = descriptor_control_field + 801f828: e0bfff17 ldw r2,-4(fp) + 801f82c: 10c00715 stw r3,28(r2) + /* go to next node in list */ + last_descr_ptr = + (alt_msgdma_prefetcher_standard_descriptor*)(last_descr_ptr->next_desc_ptr); + 801f830: e0bfff17 ldw r2,-4(fp) + 801f834: 10800317 ldw r2,12(r2) + last_descr_ptr = + 801f838: e0bfff15 stw r2,-4(fp) + + descriptor_count++; + 801f83c: e0bffe17 ldw r2,-8(fp) + 801f840: 10800044 addi r2,r2,1 + 801f844: e0bffe15 stw r2,-8(fp) + while (last_descr_ptr->next_desc_ptr != (alt_u32)list) + 801f848: e0bfff17 ldw r2,-4(fp) + 801f84c: 10c00317 ldw r3,12(r2) + 801f850: e0bffc17 ldw r2,-16(fp) + 801f854: 18bfef1e bne r3,r2,801f814 + } + /* update the last node in the list, currently last_descr_ptr after while loop */ + descriptor_control_field = last_descr_ptr->control; /* get current value */ + 801f858: e0bfff17 ldw r2,-4(fp) + 801f85c: 10800717 ldw r2,28(r2) + 801f860: e0bffd15 stw r2,-12(fp) + /* update own_by_hw bit only */ + if (last_desc_owned_by_sw) + 801f864: e0bffb03 ldbu r2,-20(fp) + 801f868: 10000726 beq r2,zero,801f888 + { + last_descr_ptr->control = descriptor_control_field + & ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_CLR_MASK; + 801f86c: e0fffd17 ldw r3,-12(fp) + 801f870: 00b00034 movhi r2,49152 + 801f874: 10bfffc4 addi r2,r2,-1 + 801f878: 1886703a and r3,r3,r2 + last_descr_ptr->control = descriptor_control_field + 801f87c: e0bfff17 ldw r2,-4(fp) + 801f880: 10c00715 stw r3,28(r2) + 801f884: 00000406 br 801f898 + } + else { + last_descr_ptr->control = descriptor_control_field + | ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET_MASK; + 801f888: e0bffd17 ldw r2,-12(fp) + 801f88c: 10d00034 orhi r3,r2,16384 + last_descr_ptr->control = descriptor_control_field + 801f890: e0bfff17 ldw r2,-4(fp) + 801f894: 10c00715 stw r3,28(r2) + } + + descriptor_count++; + 801f898: e0bffe17 ldw r2,-8(fp) + 801f89c: 10800044 addi r2,r2,1 + 801f8a0: e0bffe15 stw r2,-8(fp) + + if (dcache_flush_desc_list) + 801f8a4: e0bffa03 ldbu r2,-24(fp) + 801f8a8: 10000526 beq r2,zero,801f8c0 + { + alt_dcache_flush(list,sizeof(alt_msgdma_prefetcher_standard_descriptor) * descriptor_count); + 801f8ac: e0bffe17 ldw r2,-8(fp) + 801f8b0: 1004917a slli r2,r2,5 + 801f8b4: 100b883a mov r5,r2 + 801f8b8: e13ffc17 ldw r4,-16(fp) + 801f8bc: 80371c00 call 80371c0 + } + + return 0; + 801f8c0: 0005883a mov r2,zero +} + 801f8c4: e037883a mov sp,fp + 801f8c8: dfc00117 ldw ra,4(sp) + 801f8cc: df000017 ldw fp,0(sp) + 801f8d0: dec00204 addi sp,sp,8 + 801f8d4: f800283a ret + +0801f8d8 : + */ +int alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits ( + alt_msgdma_prefetcher_extended_descriptor *list, + alt_u8 last_desc_owned_by_sw, + alt_u8 dcache_flush_desc_list) +{ + 801f8d8: defff404 addi sp,sp,-48 + 801f8dc: dfc00b15 stw ra,44(sp) + 801f8e0: df000a15 stw fp,40(sp) + 801f8e4: df000a04 addi fp,sp,40 + 801f8e8: e13ff815 stw r4,-32(fp) + 801f8ec: 2809883a mov r4,r5 + 801f8f0: 300b883a mov r5,r6 + 801f8f4: e13ff705 stb r4,-36(fp) + 801f8f8: 2809883a mov r4,r5 + 801f8fc: e13ff605 stb r4,-40(fp) + alt_u32 descriptor_control_field = 0; + 801f900: e03ffd15 stw zero,-12(fp) + msgdma_addr64 root_node_addr, next_node_addr; + alt_msgdma_prefetcher_extended_descriptor *last_descr_ptr; + alt_u32 descriptor_count = 0; + 801f904: e03ffe15 stw zero,-8(fp) + + if (list == NULL) + 801f908: e13ff817 ldw r4,-32(fp) + 801f90c: 2000021e bne r4,zero,801f918 + { + return -EINVAL; /* this list cannot be empty */ + 801f910: 00bffa84 movi r2,-22 + 801f914: 00003e06 br 801fa10 + } + + /* update all nodes in the list */ + last_descr_ptr = list; /* start at list root-node */ + 801f918: e13ff817 ldw r4,-32(fp) + 801f91c: e13fff15 stw r4,-4(fp) + /* the last nodes next ptr should point to the root node*/ + root_node_addr.u64 = (uintptr_t)list; + 801f920: e13ff817 ldw r4,-32(fp) + 801f924: 2005883a mov r2,r4 + 801f928: 0007883a mov r3,zero + 801f92c: e0bffb15 stw r2,-20(fp) + 801f930: e0fffc15 stw r3,-16(fp) + + /* traverse list until you get the last node */ + while ((last_descr_ptr->next_desc_ptr_low != root_node_addr.u32[0]) + 801f934: 00001306 br 801f984 + || (last_descr_ptr->next_desc_ptr_high != root_node_addr.u32[1])) + { + /* start with current value */ + descriptor_control_field = last_descr_ptr->control; + 801f938: e0bfff17 ldw r2,-4(fp) + 801f93c: 10800f17 ldw r2,60(r2) + 801f940: e0bffd15 stw r2,-12(fp) + /* update own_by_hw bit only */ + last_descr_ptr->control = descriptor_control_field + | ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET_MASK; + 801f944: e0bffd17 ldw r2,-12(fp) + 801f948: 10d00034 orhi r3,r2,16384 + last_descr_ptr->control = descriptor_control_field + 801f94c: e0bfff17 ldw r2,-4(fp) + 801f950: 10c00f15 stw r3,60(r2) + /* go to next node in list, using 64 bit address */ + next_node_addr.u32[0] = last_descr_ptr->next_desc_ptr_low; + 801f954: e0bfff17 ldw r2,-4(fp) + 801f958: 10800317 ldw r2,12(r2) + 801f95c: e0bff915 stw r2,-28(fp) + next_node_addr.u32[1] = last_descr_ptr->next_desc_ptr_high; + 801f960: e0bfff17 ldw r2,-4(fp) + 801f964: 10800b17 ldw r2,44(r2) + 801f968: e0bffa15 stw r2,-24(fp) + last_descr_ptr = + (alt_msgdma_prefetcher_extended_descriptor*)((uintptr_t)next_node_addr.u64); + 801f96c: e0bff917 ldw r2,-28(fp) + 801f970: e0fffa17 ldw r3,-24(fp) + last_descr_ptr = + 801f974: e0bfff15 stw r2,-4(fp) + descriptor_count++; + 801f978: e0bffe17 ldw r2,-8(fp) + 801f97c: 10800044 addi r2,r2,1 + 801f980: e0bffe15 stw r2,-8(fp) + while ((last_descr_ptr->next_desc_ptr_low != root_node_addr.u32[0]) + 801f984: e0bfff17 ldw r2,-4(fp) + 801f988: 10c00317 ldw r3,12(r2) + 801f98c: e0bffb17 ldw r2,-20(fp) + 801f990: 18bfe91e bne r3,r2,801f938 + || (last_descr_ptr->next_desc_ptr_high != root_node_addr.u32[1])) + 801f994: e0bfff17 ldw r2,-4(fp) + 801f998: 10c00b17 ldw r3,44(r2) + 801f99c: e0bffc17 ldw r2,-16(fp) + 801f9a0: 18bfe51e bne r3,r2,801f938 + } + /* update the last node in the list, currently last_descr_ptr after while loop */ + descriptor_control_field = last_descr_ptr->control; /* start with current value */ + 801f9a4: e0bfff17 ldw r2,-4(fp) + 801f9a8: 10800f17 ldw r2,60(r2) + 801f9ac: e0bffd15 stw r2,-12(fp) + /* update own_by_hw bit only */ + if (last_desc_owned_by_sw) + 801f9b0: e0bff703 ldbu r2,-36(fp) + 801f9b4: 10000726 beq r2,zero,801f9d4 + { + last_descr_ptr->control = descriptor_control_field + & ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_CLR_MASK; + 801f9b8: e0fffd17 ldw r3,-12(fp) + 801f9bc: 00b00034 movhi r2,49152 + 801f9c0: 10bfffc4 addi r2,r2,-1 + 801f9c4: 1886703a and r3,r3,r2 + last_descr_ptr->control = descriptor_control_field + 801f9c8: e0bfff17 ldw r2,-4(fp) + 801f9cc: 10c00f15 stw r3,60(r2) + 801f9d0: 00000406 br 801f9e4 + } + else { + last_descr_ptr->control = descriptor_control_field + | ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET_MASK; + 801f9d4: e0bffd17 ldw r2,-12(fp) + 801f9d8: 10d00034 orhi r3,r2,16384 + last_descr_ptr->control = descriptor_control_field + 801f9dc: e0bfff17 ldw r2,-4(fp) + 801f9e0: 10c00f15 stw r3,60(r2) + } + + descriptor_count++; + 801f9e4: e0bffe17 ldw r2,-8(fp) + 801f9e8: 10800044 addi r2,r2,1 + 801f9ec: e0bffe15 stw r2,-8(fp) + + if (dcache_flush_desc_list) + 801f9f0: e0bff603 ldbu r2,-40(fp) + 801f9f4: 10000526 beq r2,zero,801fa0c + { + alt_dcache_flush(list,sizeof(alt_msgdma_prefetcher_extended_descriptor) * descriptor_count); + 801f9f8: e0bffe17 ldw r2,-8(fp) + 801f9fc: 100491ba slli r2,r2,6 + 801fa00: 100b883a mov r5,r2 + 801fa04: e13ff817 ldw r4,-32(fp) + 801fa08: 80371c00 call 80371c0 + } + + return 0; + 801fa0c: 0005883a mov r2,zero +} + 801fa10: e037883a mov sp,fp + 801fa14: dfc00117 ldw ra,4(sp) + 801fa18: df000017 ldw fp,0(sp) + 801fa1c: dec00204 addi sp,sp,8 + 801fa20: f800283a ret + +0801fa24 : +int alt_msgdma_start_prefetcher_with_list_addr ( + alt_msgdma_dev *dev, + alt_u64 list_addr, + alt_u8 park_mode_en, + alt_u8 poll_en) +{ + 801fa24: deffeb04 addi sp,sp,-84 + 801fa28: dfc01415 stw ra,80(sp) + 801fa2c: df001315 stw fp,76(sp) + 801fa30: df001304 addi fp,sp,76 + 801fa34: e13ff115 stw r4,-60(fp) + 801fa38: e17fef15 stw r5,-68(fp) + 801fa3c: e1bff015 stw r6,-64(fp) + 801fa40: 3807883a mov r3,r7 + 801fa44: e0800217 ldw r2,8(fp) + 801fa48: e0ffee05 stb r3,-72(fp) + 801fa4c: e0bfed05 stb r2,-76(fp) + alt_u32 prefetcher_ctl = 0; + 801fa50: e03fff15 stw zero,-4(fp) + alt_u32 dispatcher_ctl = 0; + 801fa54: e03ffe15 stw zero,-8(fp) + alt_irq_context context = 0; + 801fa58: e03ffd15 stw zero,-12(fp) + + /* use helper struct to get easy access to hi/low address */ + msgdma_addr64 root_node_addr; + root_node_addr.u64 = list_addr; + 801fa5c: e0bfef17 ldw r2,-68(fp) + 801fa60: e0bff315 stw r2,-52(fp) + 801fa64: e0bff017 ldw r2,-64(fp) + 801fa68: e0bff415 stw r2,-48(fp) + + /* + * When running in a multi threaded environment, obtain the "regs_lock" + * semaphore. This ensures that accessing registers is thread-safe. + */ + ALT_SEM_PEND (dev->regs_lock, 0); + 801fa6c: e0bff117 ldw r2,-60(fp) + 801fa70: 10801817 ldw r2,96(r2) + 801fa74: e0bffc15 stw r2,-16(fp) + 801fa78: e03ffb8d sth zero,-18(fp) + 801fa7c: e0bffb8b ldhu r2,-18(fp) + 801fa80: e0fff2c4 addi r3,fp,-53 + 801fa84: 180d883a mov r6,r3 + 801fa88: 100b883a mov r5,r2 + 801fa8c: e13ffc17 ldw r4,-16(fp) + 801fa90: 8015a600 call 8015a60 + + /* case where prefetcher already started, return busy error */ + prefetcher_ctl = IORD_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base); + 801fa94: e0bff117 ldw r2,-60(fp) + 801fa98: 10800617 ldw r2,24(r2) + 801fa9c: 10800037 ldwio r2,0(r2) + 801faa0: e0bfff15 stw r2,-4(fp) + if(ALT_MSGDMA_PREFETCHER_CTRL_RUN_GET(prefetcher_ctl)){ + 801faa4: e0bfff17 ldw r2,-4(fp) + 801faa8: 1080004c andi r2,r2,1 + 801faac: 10000626 beq r2,zero,801fac8 + /* release the registers semaphore */ + ALT_SEM_POST (dev->regs_lock); + 801fab0: e0bff117 ldw r2,-60(fp) + 801fab4: 10801817 ldw r2,96(r2) + 801fab8: 1009883a mov r4,r2 + 801fabc: 8015d840 call 8015d84 + return -EBUSY; + 801fac0: 00bffc04 movi r2,-16 + 801fac4: 00009606 br 801fd20 + } + + /* Stop the msgdma dispatcher from issuing more descriptors to the + read or write masters */ + /* stop issuing more descriptors */ + dispatcher_ctl = ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK; + 801fac8: 00800804 movi r2,32 + 801facc: e0bffe15 stw r2,-8(fp) + NIOS2_READ_STATUS (context); + 801fad0: 0005303a rdctl r2,status + 801fad4: e0bff915 stw r2,-28(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 801fad8: e0fff917 ldw r3,-28(fp) + 801fadc: 00bfff84 movi r2,-2 + 801fae0: 1884703a and r2,r3,r2 + 801fae4: 1001703a wrctl status,r2 + return context; + 801fae8: e0bff917 ldw r2,-28(fp) + + /* making sure the read-modify-write below can't be pre-empted */ + context = alt_irq_disable_all(); + 801faec: e0bffd15 stw r2,-12(fp) + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, dispatcher_ctl); + 801faf0: e0bff117 ldw r2,-60(fp) + 801faf4: 10800317 ldw r2,12(r2) + 801faf8: 10800104 addi r2,r2,4 + 801fafc: e0fffe17 ldw r3,-8(fp) + 801fb00: 10c00035 stwio r3,0(r2) + /* + * Clear any (previous) status register information + * that might occlude our error checking later. + */ + IOWR_ALTERA_MSGDMA_CSR_STATUS( dev->csr_base, + 801fb04: e0bff117 ldw r2,-60(fp) + 801fb08: 10800317 ldw r2,12(r2) + 801fb0c: e0fff117 ldw r3,-60(fp) + 801fb10: 18c00317 ldw r3,12(r3) + 801fb14: 18c00037 ldwio r3,0(r3) + 801fb18: 10c00035 stwio r3,0(r2) + 801fb1c: e0bffd17 ldw r2,-12(fp) + 801fb20: e0bffa15 stw r2,-24(fp) + NIOS2_WRITE_STATUS (context); + 801fb24: e0bffa17 ldw r2,-24(fp) + 801fb28: 1001703a wrctl status,r2 + * If a callback routine has been previously registered which will be + * called from the msgdma ISR. Set up dispatcher to: + * - Run + * - Stop on an error with any particular descriptor + */ + if(dev->callback) + 801fb2c: e0bff117 ldw r2,-60(fp) + 801fb30: 10800b17 ldw r2,44(r2) + 801fb34: 10002326 beq r2,zero,801fbc4 + { + dispatcher_ctl |= (dev->control | ALTERA_MSGDMA_CSR_STOP_ON_ERROR_MASK + 801fb38: e0bff117 ldw r2,-60(fp) + 801fb3c: 10c00d17 ldw r3,52(r2) + 801fb40: e0bffe17 ldw r2,-8(fp) + 801fb44: 1884b03a or r2,r3,r2 + 801fb48: 10800514 ori r2,r2,20 + 801fb4c: e0bffe15 stw r2,-8(fp) + | ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK ); + dispatcher_ctl &= (~ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK); + 801fb50: e0fffe17 ldw r3,-8(fp) + 801fb54: 00bff7c4 movi r2,-33 + 801fb58: 1884703a and r2,r3,r2 + 801fb5c: e0bffe15 stw r2,-8(fp) + + prefetcher_ctl |= ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_SET_MASK; + 801fb60: e0bfff17 ldw r2,-4(fp) + 801fb64: 10800214 ori r2,r2,8 + 801fb68: e0bfff15 stw r2,-4(fp) + NIOS2_READ_STATUS (context); + 801fb6c: 0005303a rdctl r2,status + 801fb70: e0bff715 stw r2,-36(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 801fb74: e0fff717 ldw r3,-36(fp) + 801fb78: 00bfff84 movi r2,-2 + 801fb7c: 1884703a and r2,r3,r2 + 801fb80: 1001703a wrctl status,r2 + return context; + 801fb84: e0bff717 ldw r2,-36(fp) + /* making sure the read-modify-write below can't be pre-empted */ + context = alt_irq_disable_all(); + 801fb88: e0bffd15 stw r2,-12(fp) + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, dispatcher_ctl); + 801fb8c: e0bff117 ldw r2,-60(fp) + 801fb90: 10800317 ldw r2,12(r2) + 801fb94: 10800104 addi r2,r2,4 + 801fb98: e0fffe17 ldw r3,-8(fp) + 801fb9c: 10c00035 stwio r3,0(r2) + IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, prefetcher_ctl); + 801fba0: e0bff117 ldw r2,-60(fp) + 801fba4: 10800617 ldw r2,24(r2) + 801fba8: e0ffff17 ldw r3,-4(fp) + 801fbac: 10c00035 stwio r3,0(r2) + 801fbb0: e0bffd17 ldw r2,-12(fp) + 801fbb4: e0bff815 stw r2,-32(fp) + NIOS2_WRITE_STATUS (context); + 801fbb8: e0bff817 ldw r2,-32(fp) + 801fbbc: 1001703a wrctl status,r2 + 801fbc0: 00002306 br 801fc50 + * - Stop on an error with any particular descriptor + * - Disable interrupt generation + */ + else + { + dispatcher_ctl |= (dev->control | ALTERA_MSGDMA_CSR_STOP_ON_ERROR_MASK); + 801fbc4: e0bff117 ldw r2,-60(fp) + 801fbc8: 10c00d17 ldw r3,52(r2) + 801fbcc: e0bffe17 ldw r2,-8(fp) + 801fbd0: 1884b03a or r2,r3,r2 + 801fbd4: 10800114 ori r2,r2,4 + 801fbd8: e0bffe15 stw r2,-8(fp) + dispatcher_ctl &= (~ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK) + 801fbdc: e0fffe17 ldw r3,-8(fp) + 801fbe0: 00bff3c4 movi r2,-49 + 801fbe4: 1884703a and r2,r3,r2 + 801fbe8: e0bffe15 stw r2,-8(fp) + & (~ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK); + prefetcher_ctl &= ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_CLR_MASK; + 801fbec: e0ffff17 ldw r3,-4(fp) + 801fbf0: 00bffdc4 movi r2,-9 + 801fbf4: 1884703a and r2,r3,r2 + 801fbf8: e0bfff15 stw r2,-4(fp) + NIOS2_READ_STATUS (context); + 801fbfc: 0005303a rdctl r2,status + 801fc00: e0bff515 stw r2,-44(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 801fc04: e0fff517 ldw r3,-44(fp) + 801fc08: 00bfff84 movi r2,-2 + 801fc0c: 1884703a and r2,r3,r2 + 801fc10: 1001703a wrctl status,r2 + return context; + 801fc14: e0bff517 ldw r2,-44(fp) + /* making sure the read-modify-write below can't be pre-empted */ + context = alt_irq_disable_all(); + 801fc18: e0bffd15 stw r2,-12(fp) + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, dispatcher_ctl); + 801fc1c: e0bff117 ldw r2,-60(fp) + 801fc20: 10800317 ldw r2,12(r2) + 801fc24: 10800104 addi r2,r2,4 + 801fc28: e0fffe17 ldw r3,-8(fp) + 801fc2c: 10c00035 stwio r3,0(r2) + IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, prefetcher_ctl); + 801fc30: e0bff117 ldw r2,-60(fp) + 801fc34: 10800617 ldw r2,24(r2) + 801fc38: e0ffff17 ldw r3,-4(fp) + 801fc3c: 10c00035 stwio r3,0(r2) + 801fc40: e0bffd17 ldw r2,-12(fp) + 801fc44: e0bff615 stw r2,-40(fp) + NIOS2_WRITE_STATUS (context); + 801fc48: e0bff617 ldw r2,-40(fp) + 801fc4c: 1001703a wrctl status,r2 + alt_irq_enable_all(context); + } + + /* set next descriptor registers to point to the list root-node */ + IOWR_ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW(dev->prefetcher_base, + 801fc50: e0bff117 ldw r2,-60(fp) + 801fc54: 10800617 ldw r2,24(r2) + 801fc58: 10800104 addi r2,r2,4 + 801fc5c: e0fff317 ldw r3,-52(fp) + 801fc60: 10c00035 stwio r3,0(r2) + root_node_addr.u32[0]); + IOWR_ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH(dev->prefetcher_base, + 801fc64: e0bff117 ldw r2,-60(fp) + 801fc68: 10800617 ldw r2,24(r2) + 801fc6c: 10800204 addi r2,r2,8 + 801fc70: e0fff417 ldw r3,-48(fp) + 801fc74: 10c00035 stwio r3,0(r2) + root_node_addr.u32[1]); + + /* set park-mode */ + if (park_mode_en){ + 801fc78: e0bfee03 ldbu r2,-72(fp) + 801fc7c: 10000426 beq r2,zero,801fc90 + prefetcher_ctl |= ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE_SET_MASK; + 801fc80: e0bfff17 ldw r2,-4(fp) + 801fc84: 10800414 ori r2,r2,16 + 801fc88: e0bfff15 stw r2,-4(fp) + 801fc8c: 00000406 br 801fca0 + } + else { + prefetcher_ctl &= ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE_CLR_MASK; + 801fc90: e0ffff17 ldw r3,-4(fp) + 801fc94: 00bffbc4 movi r2,-17 + 801fc98: 1884703a and r2,r3,r2 + 801fc9c: e0bfff15 stw r2,-4(fp) + } + + /* set poll-en */ + if (poll_en){ + 801fca0: e0bfed03 ldbu r2,-76(fp) + 801fca4: 10000e26 beq r2,zero,801fce0 + prefetcher_ctl |= ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN_MASK; + 801fca8: e0bfff17 ldw r2,-4(fp) + 801fcac: 10800094 ori r2,r2,2 + 801fcb0: e0bfff15 stw r2,-4(fp) + if(IORD_ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLLING_FREQ( + 801fcb4: e0bff117 ldw r2,-60(fp) + 801fcb8: 10800617 ldw r2,24(r2) + 801fcbc: 10800304 addi r2,r2,12 + 801fcc0: 10800037 ldwio r2,0(r2) + 801fcc4: 10000a1e bne r2,zero,801fcf0 + dev->prefetcher_base) == 0){ + /* set poll frequency to some non-zero default value */ + IOWR_ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLLING_FREQ( + 801fcc8: e0bff117 ldw r2,-60(fp) + 801fccc: 10800617 ldw r2,24(r2) + 801fcd0: 10800304 addi r2,r2,12 + 801fcd4: 00c03fc4 movi r3,255 + 801fcd8: 10c00035 stwio r3,0(r2) + 801fcdc: 00000406 br 801fcf0 + dev->prefetcher_base, 0xFF); + } + } + else { + prefetcher_ctl &= ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN_CLR_MASK; + 801fce0: e0ffff17 ldw r3,-4(fp) + 801fce4: 00bfff44 movi r2,-3 + 801fce8: 1884703a and r2,r3,r2 + 801fcec: e0bfff15 stw r2,-4(fp) + } + + /* set the prefetcher run bit */ + prefetcher_ctl |= ALT_MSGDMA_PREFETCHER_CTRL_RUN_SET_MASK; + 801fcf0: e0bfff17 ldw r2,-4(fp) + 801fcf4: 10800054 ori r2,r2,1 + 801fcf8: e0bfff15 stw r2,-4(fp) + /* start the dma since run bit is set */ + IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, prefetcher_ctl); + 801fcfc: e0bff117 ldw r2,-60(fp) + 801fd00: 10800617 ldw r2,24(r2) + 801fd04: e0ffff17 ldw r3,-4(fp) + 801fd08: 10c00035 stwio r3,0(r2) + + /* + * Now that access to the registers is complete, release the registers + * semaphore so that other threads can access the registers. + */ + ALT_SEM_POST (dev->regs_lock); + 801fd0c: e0bff117 ldw r2,-60(fp) + 801fd10: 10801817 ldw r2,96(r2) + 801fd14: 1009883a mov r4,r2 + 801fd18: 8015d840 call 8015d84 + + return 0; + 801fd1c: 0005883a mov r2,zero +} + 801fd20: e037883a mov sp,fp + 801fd24: dfc00117 ldw ra,4(sp) + 801fd28: df000017 ldw fp,0(sp) + 801fd2c: dec00204 addi sp,sp,8 + 801fd30: f800283a ret + +0801fd34 : + alt_msgdma_prefetcher_standard_descriptor *list, + alt_u8 park_mode_en, + alt_u8 poll_en, + alt_u8 last_desc_owned_by_sw, + alt_u8 dcache_flush_desc_list) +{ + 801fd34: defff504 addi sp,sp,-44 + 801fd38: dfc00a15 stw ra,40(sp) + 801fd3c: df000915 stw fp,36(sp) + 801fd40: dc400815 stw r17,32(sp) + 801fd44: dc000715 stw r16,28(sp) + 801fd48: df000904 addi fp,sp,36 + 801fd4c: e13ffd15 stw r4,-12(fp) + 801fd50: e17ffc15 stw r5,-16(fp) + 801fd54: 3009883a mov r4,r6 + 801fd58: 380b883a mov r5,r7 + 801fd5c: e0c00217 ldw r3,8(fp) + 801fd60: e0800317 ldw r2,12(fp) + 801fd64: e13ffb05 stb r4,-20(fp) + 801fd68: 2809883a mov r4,r5 + 801fd6c: e13ffa05 stb r4,-24(fp) + 801fd70: e0fff905 stb r3,-28(fp) + 801fd74: e0bff805 stb r2,-32(fp) + if (alt_msgdma_prefetcher_set_std_list_own_by_hw_bits(list,last_desc_owned_by_sw,dcache_flush_desc_list) != 0) + 801fd78: e0bff903 ldbu r2,-28(fp) + 801fd7c: e0fff803 ldbu r3,-32(fp) + 801fd80: 180d883a mov r6,r3 + 801fd84: 100b883a mov r5,r2 + 801fd88: e13ffc17 ldw r4,-16(fp) + 801fd8c: 801f7c80 call 801f7c8 + 801fd90: 10000226 beq r2,zero,801fd9c + { + return -EINVAL; + 801fd94: 00bffa84 movi r2,-22 + 801fd98: 00000b06 br 801fdc8 + } + + return alt_msgdma_start_prefetcher_with_list_addr (dev, (uintptr_t)list, + 801fd9c: e0bffc17 ldw r2,-16(fp) + 801fda0: 1021883a mov r16,r2 + 801fda4: 0023883a mov r17,zero + 801fda8: e0fffb03 ldbu r3,-20(fp) + 801fdac: e0bffa03 ldbu r2,-24(fp) + 801fdb0: d8800015 stw r2,0(sp) + 801fdb4: 180f883a mov r7,r3 + 801fdb8: 800b883a mov r5,r16 + 801fdbc: 880d883a mov r6,r17 + 801fdc0: e13ffd17 ldw r4,-12(fp) + 801fdc4: 801fa240 call 801fa24 + park_mode_en, poll_en); +} + 801fdc8: e6fffe04 addi sp,fp,-8 + 801fdcc: dfc00317 ldw ra,12(sp) + 801fdd0: df000217 ldw fp,8(sp) + 801fdd4: dc400117 ldw r17,4(sp) + 801fdd8: dc000017 ldw r16,0(sp) + 801fddc: dec00404 addi sp,sp,16 + 801fde0: f800283a ret + +0801fde4 : + alt_msgdma_prefetcher_extended_descriptor *list, + alt_u8 park_mode_en, + alt_u8 poll_en, + alt_u8 last_desc_owned_by_sw, + alt_u8 dcache_flush_desc_list) +{ + 801fde4: defff504 addi sp,sp,-44 + 801fde8: dfc00a15 stw ra,40(sp) + 801fdec: df000915 stw fp,36(sp) + 801fdf0: dc400815 stw r17,32(sp) + 801fdf4: dc000715 stw r16,28(sp) + 801fdf8: df000904 addi fp,sp,36 + 801fdfc: e13ffd15 stw r4,-12(fp) + 801fe00: e17ffc15 stw r5,-16(fp) + 801fe04: 3009883a mov r4,r6 + 801fe08: 380b883a mov r5,r7 + 801fe0c: e0c00217 ldw r3,8(fp) + 801fe10: e0800317 ldw r2,12(fp) + 801fe14: e13ffb05 stb r4,-20(fp) + 801fe18: 2809883a mov r4,r5 + 801fe1c: e13ffa05 stb r4,-24(fp) + 801fe20: e0fff905 stb r3,-28(fp) + 801fe24: e0bff805 stb r2,-32(fp) + + if (alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits(list,last_desc_owned_by_sw,dcache_flush_desc_list) != 0) + 801fe28: e0bff903 ldbu r2,-28(fp) + 801fe2c: e0fff803 ldbu r3,-32(fp) + 801fe30: 180d883a mov r6,r3 + 801fe34: 100b883a mov r5,r2 + 801fe38: e13ffc17 ldw r4,-16(fp) + 801fe3c: 801f8d80 call 801f8d8 + 801fe40: 10000226 beq r2,zero,801fe4c + { + return -EINVAL; + 801fe44: 00bffa84 movi r2,-22 + 801fe48: 00000b06 br 801fe78 + } + + return alt_msgdma_start_prefetcher_with_list_addr (dev, (uintptr_t)list, + 801fe4c: e0bffc17 ldw r2,-16(fp) + 801fe50: 1021883a mov r16,r2 + 801fe54: 0023883a mov r17,zero + 801fe58: e0fffb03 ldbu r3,-20(fp) + 801fe5c: e0bffa03 ldbu r2,-24(fp) + 801fe60: d8800015 stw r2,0(sp) + 801fe64: 180f883a mov r7,r3 + 801fe68: 800b883a mov r5,r16 + 801fe6c: 880d883a mov r6,r17 + 801fe70: e13ffd17 ldw r4,-12(fp) + 801fe74: 801fa240 call 801fa24 + park_mode_en, poll_en); +} + 801fe78: e6fffe04 addi sp,fp,-8 + 801fe7c: dfc00317 ldw ra,12(sp) + 801fe80: df000217 ldw fp,8(sp) + 801fe84: dc400117 ldw r17,4(sp) + 801fe88: dc000017 ldw r16,0(sp) + 801fe8c: dec00404 addi sp,sp,16 + 801fe90: f800283a ret + +0801fe94 : + * Returns: + * - Pointer to msgdma device instance structure, or null if the device + * could not be opened. + */ +alt_msgdma_dev* alt_msgdma_open (const char* name) +{ + 801fe94: defffc04 addi sp,sp,-16 + 801fe98: dfc00315 stw ra,12(sp) + 801fe9c: df000215 stw fp,8(sp) + 801fea0: df000204 addi fp,sp,8 + 801fea4: e13ffe15 stw r4,-8(fp) + alt_msgdma_dev* dev = NULL; + 801fea8: e03fff15 stw zero,-4(fp) + + dev = (alt_msgdma_dev*) alt_find_dev (name, &alt_msgdma_list); + 801feac: d1600b04 addi r5,gp,-32724 + 801feb0: e13ffe17 ldw r4,-8(fp) + 801feb4: 80374040 call 8037404 + 801feb8: e0bfff15 stw r2,-4(fp) + + if (NULL == dev) + 801febc: e0bfff17 ldw r2,-4(fp) + 801fec0: 1000041e bne r2,zero,801fed4 + { + ALT_ERRNO = ENODEV; + 801fec4: 801e09c0 call 801e09c + 801fec8: 1007883a mov r3,r2 + 801fecc: 008004c4 movi r2,19 + 801fed0: 18800015 stw r2,0(r3) + } + + return dev; + 801fed4: e0bfff17 ldw r2,-4(fp) +} + 801fed8: e037883a mov sp,fp + 801fedc: dfc00117 ldw ra,4(sp) + 801fee0: df000017 ldw fp,0(sp) + 801fee4: dec00204 addi sp,sp,8 + 801fee8: f800283a ret + +0801feec : + * This routine disables interrupts, descriptor processing, + * registers a specific instance of the device with the HAL, + * and installs an interrupt handler for the device. + */ +void alt_msgdma_init (alt_msgdma_dev *dev, alt_u32 ic_id, alt_u32 irq) +{ + 801feec: defff604 addi sp,sp,-40 + 801fef0: dfc00915 stw ra,36(sp) + 801fef4: df000815 stw fp,32(sp) + 801fef8: df000804 addi fp,sp,32 + 801fefc: e13ffb15 stw r4,-20(fp) + 801ff00: e17ffa15 stw r5,-24(fp) + 801ff04: e1bff915 stw r6,-28(fp) + extern alt_llist alt_msgdma_list; + alt_u32 temporary_control; + int error; + + if (dev->prefetcher_enable) + 801ff08: e0bffb17 ldw r2,-20(fp) + 801ff0c: 10801783 ldbu r2,94(r2) + 801ff10: 10803fcc andi r2,r2,255 + 801ff14: 10000a26 beq r2,zero,801ff40 + { + /* start prefetcher reset sequence */ + IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, + 801ff18: e0bffb17 ldw r2,-20(fp) + 801ff1c: 10800617 ldw r2,24(r2) + 801ff20: 00c00104 movi r3,4 + 801ff24: 10c00035 stwio r3,0(r2) + ALT_MSGDMA_PREFETCHER_CTRL_RESET_SET_MASK); + /* wait until hw clears the bit */ + while(ALT_MSGDMA_PREFETCHER_CTRL_RESET_GET( + 801ff28: 0001883a nop + 801ff2c: e0bffb17 ldw r2,-20(fp) + 801ff30: 10800617 ldw r2,24(r2) + 801ff34: 10800037 ldwio r2,0(r2) + 801ff38: 1080010c andi r2,r2,4 + 801ff3c: 103ffb1e bne r2,zero,801ff2c + } + + /* Reset the registers and FIFOs of the dispatcher and master modules */ + /* set the reset bit, no need to read the control register first since + this write is going to clear it out */ + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, ALTERA_MSGDMA_CSR_RESET_MASK); + 801ff40: e0bffb17 ldw r2,-20(fp) + 801ff44: 10800317 ldw r2,12(r2) + 801ff48: 10800104 addi r2,r2,4 + 801ff4c: 00c00084 movi r3,2 + 801ff50: 10c00035 stwio r3,0(r2) + while(0 != (IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base) + 801ff54: 0001883a nop + 801ff58: e0bffb17 ldw r2,-20(fp) + 801ff5c: 10800317 ldw r2,12(r2) + 801ff60: 10800037 ldwio r2,0(r2) + & ALTERA_MSGDMA_CSR_RESET_STATE_MASK)); + 801ff64: 1080100c andi r2,r2,64 + while(0 != (IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base) + 801ff68: 103ffb1e bne r2,zero,801ff58 + * Disable interrupts, halt descriptor processing, + * and clear status register content + */ + + /* disable global interrupt */ + temporary_control = IORD_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base) + 801ff6c: e0bffb17 ldw r2,-20(fp) + 801ff70: 10800317 ldw r2,12(r2) + 801ff74: 10800104 addi r2,r2,4 + 801ff78: 10800037 ldwio r2,0(r2) + & (~ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK); + 801ff7c: 1007883a mov r3,r2 + temporary_control = IORD_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base) + 801ff80: 00bffbc4 movi r2,-17 + 801ff84: 1884703a and r2,r3,r2 + 801ff88: e0bfff15 stw r2,-4(fp) + /* stopping descriptor */ + temporary_control |= ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK; + 801ff8c: e0bfff17 ldw r2,-4(fp) + 801ff90: 10800814 ori r2,r2,32 + 801ff94: e0bfff15 stw r2,-4(fp) + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, temporary_control); + 801ff98: e0bffb17 ldw r2,-20(fp) + 801ff9c: 10800317 ldw r2,12(r2) + 801ffa0: 10800104 addi r2,r2,4 + 801ffa4: e0ffff17 ldw r3,-4(fp) + 801ffa8: 10c00035 stwio r3,0(r2) + + /* clear the CSR status register */ + IOWR_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base, + 801ffac: e0bffb17 ldw r2,-20(fp) + 801ffb0: 10800317 ldw r2,12(r2) + 801ffb4: e0fffb17 ldw r3,-20(fp) + 801ffb8: 18c00317 ldw r3,12(r3) + 801ffbc: 18c00037 ldwio r3,0(r3) + 801ffc0: 10c00035 stwio r3,0(r2) + IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base)); + + if (dev->prefetcher_enable) + 801ffc4: e0bffb17 ldw r2,-20(fp) + 801ffc8: 10801783 ldbu r2,94(r2) + 801ffcc: 10803fcc andi r2,r2,255 + 801ffd0: 10000826 beq r2,zero,801fff4 + { + /* clear all status bits that are set, since theyre W1C */ + IOWR_ALT_MSGDMA_PREFETCHER_STATUS(dev->prefetcher_base, + 801ffd4: e0bffb17 ldw r2,-20(fp) + 801ffd8: 10800617 ldw r2,24(r2) + 801ffdc: 10800404 addi r2,r2,16 + 801ffe0: e0fffb17 ldw r3,-20(fp) + 801ffe4: 18c00617 ldw r3,24(r3) + 801ffe8: 18c00404 addi r3,r3,16 + 801ffec: 18c00037 ldwio r3,0(r3) + 801fff0: 10c00035 stwio r3,0(r2) + IORD_ALT_MSGDMA_PREFETCHER_STATUS(dev->prefetcher_base)); + } + + /* Register this instance of the msgdma controller with HAL */ + alt_dev_llist_insert((alt_dev_llist*) dev, &alt_msgdma_list); + 801fff4: d1600b04 addi r5,gp,-32724 + 801fff8: e13ffb17 ldw r4,-20(fp) + 801fffc: 80372a00 call 80372a0 + + /* + * Creating semaphores used to protect access to the registers + * when running in a multi-threaded environment. + */ + error = ALT_SEM_CREATE (&dev->regs_lock, 1); + 8020000: e0bffb17 ldw r2,-20(fp) + 8020004: 10801804 addi r2,r2,96 + 8020008: e0bffd15 stw r2,-12(fp) + 802000c: 00800044 movi r2,1 + 8020010: e0bffc8d sth r2,-14(fp) + *sem = OSSemCreate (value); + 8020014: e0bffc8b ldhu r2,-14(fp) + 8020018: 1009883a mov r4,r2 + 802001c: 80157740 call 8015774 + 8020020: 1007883a mov r3,r2 + 8020024: e0bffd17 ldw r2,-12(fp) + 8020028: 10c00015 stw r3,0(r2) + return *sem ? 0 : -1; + 802002c: e0bffd17 ldw r2,-12(fp) + 8020030: 10800017 ldw r2,0(r2) + 8020034: 10000226 beq r2,zero,8020040 + 8020038: 0005883a mov r2,zero + 802003c: 00000106 br 8020044 + 8020040: 00bfffc4 movi r2,-1 + 8020044: e0bffe15 stw r2,-8(fp) + + if (!error) + 8020048: e0bffe17 ldw r2,-8(fp) + 802004c: 1000081e bne r2,zero,8020070 + { + /* Install IRQ handler */ + alt_ic_isr_register(ic_id, irq, alt_msgdma_irq, dev, 0x0); + 8020050: d8000015 stw zero,0(sp) + 8020054: e1fffb17 ldw r7,-20(fp) + 8020058: 018200b4 movhi r6,2050 + 802005c: 31b8a604 addi r6,r6,-7528 + 8020060: e17ff917 ldw r5,-28(fp) + 8020064: e13ffa17 ldw r4,-24(fp) + 8020068: 80374940 call 8037494 + else + { + alt_printf("failed to create semaphores\n"); + } + + return; + 802006c: 00000406 br 8020080 + alt_printf("failed to create semaphores\n"); + 8020070: 01020174 movhi r4,2053 + 8020074: 2125c204 addi r4,r4,-26872 + 8020078: 8037a9c0 call 8037a9c + return; + 802007c: 0001883a nop + +} + 8020080: e037883a mov sp,fp + 8020084: dfc00117 ldw ra,4(sp) + 8020088: df000017 ldw fp,0(sp) + 802008c: dec00204 addi sp,sp,8 + 8020090: f800283a ret + +08020094 : +void alt_msgdma_register_callback( + alt_msgdma_dev *dev, + alt_msgdma_callback callback, + alt_u32 control, + void *context) +{ + 8020094: defffb04 addi sp,sp,-20 + 8020098: df000415 stw fp,16(sp) + 802009c: df000404 addi fp,sp,16 + 80200a0: e13fff15 stw r4,-4(fp) + 80200a4: e17ffe15 stw r5,-8(fp) + 80200a8: e1bffd15 stw r6,-12(fp) + 80200ac: e1fffc15 stw r7,-16(fp) + dev->callback = callback; + 80200b0: e0bfff17 ldw r2,-4(fp) + 80200b4: e0fffe17 ldw r3,-8(fp) + 80200b8: 10c00b15 stw r3,44(r2) + dev->callback_context = context; + 80200bc: e0bfff17 ldw r2,-4(fp) + 80200c0: e0fffc17 ldw r3,-16(fp) + 80200c4: 10c00c15 stw r3,48(r2) + dev->control = control; + 80200c8: e0bfff17 ldw r2,-4(fp) + 80200cc: e0fffd17 ldw r3,-12(fp) + 80200d0: 10c00d15 stw r3,52(r2) + + return ; + 80200d4: 0001883a nop +} + 80200d8: e037883a mov sp,fp + 80200dc: df000017 ldw fp,0(sp) + 80200e0: dec00104 addi sp,sp,4 + 80200e4: f800283a ret + +080200e8 : + * -ETIME -> Time out and skipping the looping after 5 msec. + */ +int alt_msgdma_standard_descriptor_async_transfer( + alt_msgdma_dev *dev, + alt_msgdma_standard_descriptor *desc) +{ + 80200e8: defffc04 addi sp,sp,-16 + 80200ec: dfc00315 stw ra,12(sp) + 80200f0: df000215 stw fp,8(sp) + 80200f4: df000204 addi fp,sp,8 + 80200f8: e13fff15 stw r4,-4(fp) + 80200fc: e17ffe15 stw r5,-8(fp) + /* + * Error detection/handling should be performed at the application + * or callback level as appropriate. + */ + return alt_msgdma_descriptor_async_transfer(dev, desc, NULL); + 8020100: 000d883a mov r6,zero + 8020104: e17ffe17 ldw r5,-8(fp) + 8020108: e13fff17 ldw r4,-4(fp) + 802010c: 801e5fc0 call 801e5fc + +} + 8020110: e037883a mov sp,fp + 8020114: dfc00117 ldw ra,4(sp) + 8020118: df000017 ldw fp,0(sp) + 802011c: dec00204 addi sp,sp,8 + 8020120: f800283a ret + +08020124 : + * -ETIME -> Time out and skipping the looping after 5 msec. + */ +int alt_msgdma_extended_descriptor_async_transfer( + alt_msgdma_dev *dev, + alt_msgdma_extended_descriptor *desc) +{ + 8020124: defffc04 addi sp,sp,-16 + 8020128: dfc00315 stw ra,12(sp) + 802012c: df000215 stw fp,8(sp) + 8020130: df000204 addi fp,sp,8 + 8020134: e13fff15 stw r4,-4(fp) + 8020138: e17ffe15 stw r5,-8(fp) + /* + * Error detection/handling should be performed at the application + * or callback level as appropriate. + */ + return alt_msgdma_descriptor_async_transfer(dev, NULL, desc); + 802013c: e1bffe17 ldw r6,-8(fp) + 8020140: 000b883a mov r5,zero + 8020144: e13fff17 ldw r4,-4(fp) + 8020148: 801e5fc0 call 801e5fc +} + 802014c: e037883a mov sp,fp + 8020150: dfc00117 ldw ra,4(sp) + 8020154: df000017 ldw fp,0(sp) + 8020158: dec00204 addi sp,sp,8 + 802015c: f800283a ret + +08020160 : + * return -ETIME (Time out and skipping the looping after 5 msec) + */ +int alt_msgdma_standard_descriptor_sync_transfer( + alt_msgdma_dev *dev, + alt_msgdma_standard_descriptor *desc) +{ + 8020160: defffc04 addi sp,sp,-16 + 8020164: dfc00315 stw ra,12(sp) + 8020168: df000215 stw fp,8(sp) + 802016c: df000204 addi fp,sp,8 + 8020170: e13fff15 stw r4,-4(fp) + 8020174: e17ffe15 stw r5,-8(fp) + return alt_msgdma_descriptor_sync_transfer(dev, desc, NULL); + 8020178: 000d883a mov r6,zero + 802017c: e17ffe17 ldw r5,-8(fp) + 8020180: e13fff17 ldw r4,-4(fp) + 8020184: 801e9380 call 801e938 +} + 8020188: e037883a mov sp,fp + 802018c: dfc00117 ldw ra,4(sp) + 8020190: df000017 ldw fp,0(sp) + 8020194: dec00204 addi sp,sp,8 + 8020198: f800283a ret + +0802019c : + * return -ETIME (Time out and skipping the looping after 5 msec) + */ +int alt_msgdma_extended_descriptor_sync_transfer( + alt_msgdma_dev *dev, + alt_msgdma_extended_descriptor *desc) +{ + 802019c: defffc04 addi sp,sp,-16 + 80201a0: dfc00315 stw ra,12(sp) + 80201a4: df000215 stw fp,8(sp) + 80201a8: df000204 addi fp,sp,8 + 80201ac: e13fff15 stw r4,-4(fp) + 80201b0: e17ffe15 stw r5,-8(fp) + return alt_msgdma_descriptor_sync_transfer(dev, NULL, desc); + 80201b4: e1bffe17 ldw r6,-8(fp) + 80201b8: 000b883a mov r5,zero + 80201bc: e13fff17 ldw r4,-4(fp) + 80201c0: 801e9380 call 801e938 +} + 80201c4: e037883a mov sp,fp + 80201c8: dfc00117 ldw ra,4(sp) + 80201cc: df000017 ldw fp,0(sp) + 80201d0: dec00204 addi sp,sp,8 + 80201d4: f800283a ret + +080201d8 : +{ + 80201d8: defffd04 addi sp,sp,-12 + 80201dc: dfc00215 stw ra,8(sp) + 80201e0: df000115 stw fp,4(sp) + 80201e4: df000104 addi fp,sp,4 + 80201e8: e13fff15 stw r4,-4(fp) + return alt_dev_llist_insert ((alt_dev_llist*) fd, &alt_flash_dev_list); + 80201ec: d1600404 addi r5,gp,-32752 + 80201f0: e13fff17 ldw r4,-4(fp) + 80201f4: 80372a00 call 80372a0 +} + 80201f8: e037883a mov sp,fp + 80201fc: dfc00117 ldw ra,4(sp) + 8020200: df000017 ldw fp,0(sp) + 8020204: dec00204 addi sp,sp,8 + 8020208: f800283a ret + +0802020c : + alt_flash_dev *flash_info, + int offset, + void *dest_addr, + int length +) +{ + 802020c: defff704 addi sp,sp,-36 + 8020210: dfc00815 stw ra,32(sp) + 8020214: df000715 stw fp,28(sp) + 8020218: df000704 addi fp,sp,28 + 802021c: e13ffc15 stw r4,-16(fp) + 8020220: e17ffb15 stw r5,-20(fp) + 8020224: e1bffa15 stw r6,-24(fp) + 8020228: e1fff915 stw r7,-28(fp) + int ret_code = 0; + 802022c: e03fff15 stw zero,-4(fp) + alt_onchip_flash_dev* flash = (alt_onchip_flash_dev*)flash_info; + 8020230: e0bffc17 ldw r2,-16(fp) + 8020234: e0bffe15 stw r2,-8(fp) + + /* Make sure the input parameters is not outside of this device's range. */ + if ((offset >= flash->dev.length) || ((offset+length) > flash->dev.length)) { + 8020238: e0bffe17 ldw r2,-8(fp) + 802023c: 10800b17 ldw r2,44(r2) + 8020240: e0fffb17 ldw r3,-20(fp) + 8020244: 1880060e bge r3,r2,8020260 + 8020248: e0fffb17 ldw r3,-20(fp) + 802024c: e0bff917 ldw r2,-28(fp) + 8020250: 1885883a add r2,r3,r2 + 8020254: e0fffe17 ldw r3,-8(fp) + 8020258: 18c00b17 ldw r3,44(r3) + 802025c: 1880020e bge r3,r2,8020268 + return -EFAULT; + 8020260: 00bffc84 movi r2,-14 + 8020264: 00001706 br 80202c4 + } + + memcpy(dest_addr, (alt_u8*)flash->dev.base_addr+offset, length); + 8020268: e0bffe17 ldw r2,-8(fp) + 802026c: 10c00a17 ldw r3,40(r2) + 8020270: e0bffb17 ldw r2,-20(fp) + 8020274: 1885883a add r2,r3,r2 + 8020278: e0fff917 ldw r3,-28(fp) + 802027c: 180d883a mov r6,r3 + 8020280: 100b883a mov r5,r2 + 8020284: e13ffa17 ldw r4,-24(fp) + 8020288: 80086b80 call 80086b8 + + if (NULL != flash->csr_base) { + 802028c: e0bffe17 ldw r2,-8(fp) + 8020290: 10802f17 ldw r2,188(r2) + 8020294: 10000a26 beq r2,zero,80202c0 + int read_status = IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & ALTERA_ONCHIP_FLASH_STATUS_READ_MSK; + 8020298: e0bffe17 ldw r2,-8(fp) + 802029c: 10802f17 ldw r2,188(r2) + 80202a0: 10800037 ldwio r2,0(r2) + 80202a4: 1080010c andi r2,r2,4 + 80202a8: e0bffd15 stw r2,-12(fp) + if (read_status != ALTERA_ONCHIP_FLASH_STATUS_READ_PASSED) { + 80202ac: e0bffd17 ldw r2,-12(fp) + 80202b0: 10800120 cmpeqi r2,r2,4 + 80202b4: 1000021e bne r2,zero,80202c0 + /* Read failed. Return error.*/ + ret_code = -EIO; + 80202b8: 00bffec4 movi r2,-5 + 80202bc: e0bfff15 stw r2,-4(fp) + } + } + return ret_code; + 80202c0: e0bfff17 ldw r2,-4(fp) +} + 80202c4: e037883a mov sp,fp + 80202c8: dfc00117 ldw ra,4(sp) + 80202cc: df000017 ldw fp,0(sp) + 80202d0: dec00204 addi sp,sp,8 + 80202d4: f800283a ret + +080202d8 : +( + alt_flash_fd *fd, + flash_region **info, + int *number_of_regions +) +{ + 80202d8: defffa04 addi sp,sp,-24 + 80202dc: df000515 stw fp,20(sp) + 80202e0: df000504 addi fp,sp,20 + 80202e4: e13ffd15 stw r4,-12(fp) + 80202e8: e17ffc15 stw r5,-16(fp) + 80202ec: e1bffb15 stw r6,-20(fp) + int ret_code = 0; + 80202f0: e03fff15 stw zero,-4(fp) + + alt_flash_dev* flash = (alt_flash_dev*)fd; + 80202f4: e0bffd17 ldw r2,-12(fp) + 80202f8: e0bffe15 stw r2,-8(fp) + + if (NULL != number_of_regions) + 80202fc: e0bffb17 ldw r2,-20(fp) + 8020300: 10000426 beq r2,zero,8020314 + { + /* Pass the number of region to user */ + *number_of_regions = flash->number_of_regions; + 8020304: e0bffe17 ldw r2,-8(fp) + 8020308: 10c00c17 ldw r3,48(r2) + 802030c: e0bffb17 ldw r2,-20(fp) + 8020310: 10c00015 stw r3,0(r2) + } + + if (!flash->number_of_regions) + 8020314: e0bffe17 ldw r2,-8(fp) + 8020318: 10800c17 ldw r2,48(r2) + 802031c: 1000031e bne r2,zero,802032c + { + ret_code = -ENOMEM; + 8020320: 00bffd04 movi r2,-12 + 8020324: e0bfff15 stw r2,-4(fp) + 8020328: 00000d06 br 8020360 + } + else if (flash->number_of_regions > ALT_MAX_NUMBER_OF_FLASH_REGIONS) + 802032c: e0bffe17 ldw r2,-8(fp) + 8020330: 10800c17 ldw r2,48(r2) + 8020334: 10800250 cmplti r2,r2,9 + 8020338: 1000031e bne r2,zero,8020348 + { + ret_code = -EFAULT; + 802033c: 00bffc84 movi r2,-14 + 8020340: e0bfff15 stw r2,-4(fp) + 8020344: 00000606 br 8020360 + } + else + { + if (NULL != info) + 8020348: e0bffc17 ldw r2,-16(fp) + 802034c: 10000426 beq r2,zero,8020360 + { + /* Pass the table of erase blocks to user */ + *info = &flash->region_info[0]; + 8020350: e0bffe17 ldw r2,-8(fp) + 8020354: 10c00d04 addi r3,r2,52 + 8020358: e0bffc17 ldw r2,-16(fp) + 802035c: 10c00015 stw r3,0(r2) + } + } + + return ret_code; + 8020360: e0bfff17 ldw r2,-4(fp) +} + 8020364: e037883a mov sp,fp + 8020368: df000017 ldw fp,0(sp) + 802036c: dec00104 addi sp,sp,4 + 8020370: f800283a ret + +08020374 : +int alt_onchip_flash_erase_block +( + alt_flash_dev *flash_info, + int block_offset +) +{ + 8020374: defff904 addi sp,sp,-28 + 8020378: dfc00615 stw ra,24(sp) + 802037c: df000515 stw fp,20(sp) + 8020380: df000504 addi fp,sp,20 + 8020384: e13ffc15 stw r4,-16(fp) + 8020388: e17ffb15 stw r5,-20(fp) + int ret_code = 0; + 802038c: e03fff15 stw zero,-4(fp) + alt_onchip_flash_dev *flash = (alt_onchip_flash_dev*)flash_info; + 8020390: e0bffc17 ldw r2,-16(fp) + 8020394: e0bffe15 stw r2,-8(fp) + int page_address; + + /* Make sure the input parameters is not outside of this device's range. */ + if (block_offset >= flash->dev.length) { + 8020398: e0bffe17 ldw r2,-8(fp) + 802039c: 10800b17 ldw r2,44(r2) + 80203a0: e0fffb17 ldw r3,-20(fp) + 80203a4: 18800216 blt r3,r2,80203b0 + return -EFAULT; + 80203a8: 00bffc84 movi r2,-14 + 80203ac: 00004606 br 80204c8 + } + + /* Make sure IP support write and erase operation */ + if ((flash->csr_base == NULL) || (flash->is_read_only)) { + 80203b0: e0bffe17 ldw r2,-8(fp) + 80203b4: 10802f17 ldw r2,188(r2) + 80203b8: 10000326 beq r2,zero,80203c8 + 80203bc: e0bffe17 ldw r2,-8(fp) + 80203c0: 10802e17 ldw r2,184(r2) + 80203c4: 10000226 beq r2,zero,80203d0 + return -ENODEV; + 80203c8: 00bffb44 movi r2,-19 + 80203cc: 00003e06 br 80204c8 + } + + /* The block_offset must be page size aligned */ + if ((block_offset & (flash->page_size - 1)) != 0) + 80203d0: e0bffe17 ldw r2,-8(fp) + 80203d4: 10803f17 ldw r2,252(r2) + 80203d8: 10ffffc4 addi r3,r2,-1 + 80203dc: e0bffb17 ldw r2,-20(fp) + 80203e0: 1884703a and r2,r3,r2 + 80203e4: 10000226 beq r2,zero,80203f0 + { + /* The address is not aligned */ + return -EINVAL; + 80203e8: 00bffa84 movi r2,-22 + 80203ec: 00003606 br 80204c8 + } + + /* Wait until flash controller idle */ + ret_code = alt_onchip_flash_poll_for_status_to_go_idle(flash); + 80203f0: e13ffe17 ldw r4,-8(fp) + 80203f4: 8020f200 call 8020f20 + 80203f8: e0bfff15 stw r2,-4(fp) + if (ret_code != 0) + 80203fc: e0bfff17 ldw r2,-4(fp) + 8020400: 10000226 beq r2,zero,802040c + { + return ret_code; + 8020404: e0bfff17 ldw r2,-4(fp) + 8020408: 00002f06 br 80204c8 + } + + /* Enable write and erase operation */ + ALTERA_ONCHIP_FLASH_ENABLE_WRITE_AND_ERASE_OPERATION(flash->csr_base); + 802040c: e0bffe17 ldw r2,-8(fp) + 8020410: 10802f17 ldw r2,188(r2) + 8020414: 10c00104 addi r3,r2,4 + 8020418: e0bffe17 ldw r2,-8(fp) + 802041c: 10802f17 ldw r2,188(r2) + 8020420: 10800104 addi r2,r2,4 + 8020424: 10800037 ldwio r2,0(r2) + 8020428: 113c002c andhi r4,r2,61440 + 802042c: 00802034 movhi r2,128 + 8020430: 10bfffc4 addi r2,r2,-1 + 8020434: 2084b03a or r2,r4,r2 + 8020438: 18800035 stwio r2,0(r3) + + /* Calculate Page erase address, it is 32bit word addressing*/ + page_address = block_offset / 4; + 802043c: e0bffb17 ldw r2,-20(fp) + 8020440: 1000010e bge r2,zero,8020448 + 8020444: 108000c4 addi r2,r2,3 + 8020448: 1005d0ba srai r2,r2,2 + 802044c: e0bffd15 stw r2,-12(fp) + + /* Perform Page erase operation */ + ALTERA_ONCHIP_FLASH_PAGE_ERASE(flash->csr_base, page_address); + 8020450: e0bffe17 ldw r2,-8(fp) + 8020454: 10802f17 ldw r2,188(r2) + 8020458: 10800104 addi r2,r2,4 + 802045c: e0fffe17 ldw r3,-8(fp) + 8020460: 18c02f17 ldw r3,188(r3) + 8020464: 18c00104 addi r3,r3,4 + 8020468: 18c00037 ldwio r3,0(r3) + 802046c: 193c002c andhi r4,r3,61440 + 8020470: e0fffd17 ldw r3,-12(fp) + 8020474: 18c01c34 orhi r3,r3,112 + 8020478: 20c6b03a or r3,r4,r3 + 802047c: 10c00035 stwio r3,0(r2) + + /* Wait until flash controller idle */ + ret_code = alt_onchip_flash_poll_for_status_to_go_idle(flash); + 8020480: e13ffe17 ldw r4,-8(fp) + 8020484: 8020f200 call 8020f20 + 8020488: e0bfff15 stw r2,-4(fp) + + /* Wait until flash controller indicate erase passed */ + ret_code = alt_onchip_flash_poll_for_status_erase_passed(flash); + 802048c: e13ffe17 ldw r4,-8(fp) + 8020490: 8020fb00 call 8020fb0 + 8020494: e0bfff15 stw r2,-4(fp) + + /* Disable write and erase operation */ + ALTERA_ONCHIP_FLASH_DISABLE_WRITE_AND_ERASE_OPERATION(flash->csr_base); + 8020498: e0bffe17 ldw r2,-8(fp) + 802049c: 10802f17 ldw r2,188(r2) + 80204a0: 10c00104 addi r3,r2,4 + 80204a4: e0bffe17 ldw r2,-8(fp) + 80204a8: 10802f17 ldw r2,188(r2) + 80204ac: 10800104 addi r2,r2,4 + 80204b0: 11000037 ldwio r4,0(r2) + 80204b4: 00840034 movhi r2,4096 + 80204b8: 10bfffc4 addi r2,r2,-1 + 80204bc: 2084b03a or r2,r4,r2 + 80204c0: 18800035 stwio r2,0(r3) + + return ret_code; + 80204c4: e0bfff17 ldw r2,-4(fp) +} + 80204c8: e037883a mov sp,fp + 80204cc: dfc00117 ldw ra,4(sp) + 80204d0: df000017 ldw fp,0(sp) + 80204d4: dec00204 addi sp,sp,8 + 80204d8: f800283a ret + +080204dc : + int block_offset, + int data_offset, + const void *data, + int length +) +{ + 80204dc: defff204 addi sp,sp,-56 + 80204e0: dfc00d15 stw ra,52(sp) + 80204e4: df000c15 stw fp,48(sp) + 80204e8: df000c04 addi fp,sp,48 + 80204ec: e13ff715 stw r4,-36(fp) + 80204f0: e17ff615 stw r5,-40(fp) + 80204f4: e1bff515 stw r6,-44(fp) + 80204f8: e1fff415 stw r7,-48(fp) + int ret_code = 0; + 80204fc: e03fff15 stw zero,-4(fp) + alt_onchip_flash_dev *flash = (alt_onchip_flash_dev*)flash_info; + 8020500: e0bff717 ldw r2,-36(fp) + 8020504: e0bffb15 stw r2,-20(fp) + int buffer_offset = 0; + 8020508: e03ffe15 stw zero,-8(fp) + int length_of_current_write; + int current_data_offset = data_offset; + 802050c: e0bff517 ldw r2,-44(fp) + 8020510: e0bffd15 stw r2,-12(fp) + int next_data_offset; + alt_u32 chunk_of_data; + + /* Make sure the input parameters is not outside of this device's range. */ + if ( + (block_offset >= flash->dev.length) || + 8020514: e0bffb17 ldw r2,-20(fp) + 8020518: 10800b17 ldw r2,44(r2) + if ( + 802051c: e0fff617 ldw r3,-40(fp) + 8020520: 18800a0e bge r3,r2,802054c + (data_offset >= flash->dev.length) || + 8020524: e0bffb17 ldw r2,-20(fp) + 8020528: 10800b17 ldw r2,44(r2) + (block_offset >= flash->dev.length) || + 802052c: e0fff517 ldw r3,-44(fp) + 8020530: 1880060e bge r3,r2,802054c + (length > (flash->dev.length - data_offset)) + 8020534: e0bffb17 ldw r2,-20(fp) + 8020538: 10c00b17 ldw r3,44(r2) + 802053c: e0bff517 ldw r2,-44(fp) + 8020540: 1887c83a sub r3,r3,r2 + (data_offset >= flash->dev.length) || + 8020544: e0800217 ldw r2,8(fp) + 8020548: 1880020e bge r3,r2,8020554 + ) { + return -EFAULT; + 802054c: 00bffc84 movi r2,-14 + 8020550: 00009306 br 80207a0 + } + + /* Make sure IP support support write and erase operation */ + if ((flash->csr_base == NULL) || (flash->is_read_only != 0)) { + 8020554: e0bffb17 ldw r2,-20(fp) + 8020558: 10802f17 ldw r2,188(r2) + 802055c: 10000326 beq r2,zero,802056c + 8020560: e0bffb17 ldw r2,-20(fp) + 8020564: 10802e17 ldw r2,184(r2) + 8020568: 10000226 beq r2,zero,8020574 + return -ENODEV; + 802056c: 00bffb44 movi r2,-19 + 8020570: 00008b06 br 80207a0 + } + + /* Wait until flash controller idle */ + ret_code = alt_onchip_flash_poll_for_status_to_go_idle(flash); + 8020574: e13ffb17 ldw r4,-20(fp) + 8020578: 8020f200 call 8020f20 + 802057c: e0bfff15 stw r2,-4(fp) + if (ret_code != 0) + 8020580: e0bfff17 ldw r2,-4(fp) + 8020584: 10000226 beq r2,zero,8020590 + { + return ret_code; + 8020588: e0bfff17 ldw r2,-4(fp) + 802058c: 00008406 br 80207a0 + } + + /* Enable write and erase operation */ + ALTERA_ONCHIP_FLASH_ENABLE_WRITE_AND_ERASE_OPERATION(flash->csr_base); + 8020590: e0bffb17 ldw r2,-20(fp) + 8020594: 10802f17 ldw r2,188(r2) + 8020598: 10c00104 addi r3,r2,4 + 802059c: e0bffb17 ldw r2,-20(fp) + 80205a0: 10802f17 ldw r2,188(r2) + 80205a4: 10800104 addi r2,r2,4 + 80205a8: 10800037 ldwio r2,0(r2) + 80205ac: 113c002c andhi r4,r2,61440 + 80205b0: 00802034 movhi r2,128 + 80205b4: 10bfffc4 addi r2,r2,-1 + 80205b8: 2084b03a or r2,r4,r2 + 80205bc: 18800035 stwio r2,0(r3) + + /* Check data length */ + while (length) + 80205c0: 00006506 br 8020758 + { + /* Minimum write size to onchip flash is 32 bits of data */ + chunk_of_data = 0xFFFFFFFF; + 80205c4: 00bfffc4 movi r2,-1 + 80205c8: e0bff815 stw r2,-32(fp) + + /* The start of data_offset must be 4 bytes (32 bits) aligned */ + if ((current_data_offset & (ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE - 1)) == 0) + 80205cc: e0bffd17 ldw r2,-12(fp) + 80205d0: 108000cc andi r2,r2,3 + 80205d4: 10001e1e bne r2,zero,8020650 + { + /* The address is 4-byte aligned here */ + next_data_offset = (current_data_offset + ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE) & ~(ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE - 1); + 80205d8: e0bffd17 ldw r2,-12(fp) + 80205dc: 10c00104 addi r3,r2,4 + 80205e0: 00bfff04 movi r2,-4 + 80205e4: 1884703a and r2,r3,r2 + 80205e8: e0bffc15 stw r2,-16(fp) + length_of_current_write = MIN(length, next_data_offset - current_data_offset); + 80205ec: e0fffc17 ldw r3,-16(fp) + 80205f0: e0bffd17 ldw r2,-12(fp) + 80205f4: 1887c83a sub r3,r3,r2 + 80205f8: e0800217 ldw r2,8(fp) + 80205fc: 1880010e bge r3,r2,8020604 + 8020600: 1805883a mov r2,r3 + 8020604: e0bffa15 stw r2,-24(fp) + /* Prepare the 4 bytes chunk of data to be written */ + memcpy(&chunk_of_data, &((alt_u8*)data)[buffer_offset], length_of_current_write); + 8020608: e0bffe17 ldw r2,-8(fp) + 802060c: e0fff417 ldw r3,-48(fp) + 8020610: 1887883a add r3,r3,r2 + 8020614: e13ffa17 ldw r4,-24(fp) + 8020618: e0bff804 addi r2,fp,-32 + 802061c: 200d883a mov r6,r4 + 8020620: 180b883a mov r5,r3 + 8020624: 1009883a mov r4,r2 + 8020628: 80086b80 call 80086b8 + buffer_offset += length_of_current_write; + 802062c: e0fffe17 ldw r3,-8(fp) + 8020630: e0bffa17 ldw r2,-24(fp) + 8020634: 1885883a add r2,r3,r2 + 8020638: e0bffe15 stw r2,-8(fp) + length -= length_of_current_write; + 802063c: e0c00217 ldw r3,8(fp) + 8020640: e0bffa17 ldw r2,-24(fp) + 8020644: 1885c83a sub r2,r3,r2 + 8020648: e0800215 stw r2,8(fp) + 802064c: 00003006 br 8020710 + } else { + /* Calculate how many padding bytes need to be added before the start of a data offset */ + int padding = current_data_offset & (ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE - 1); + 8020650: e0bffd17 ldw r2,-12(fp) + 8020654: 108000cc andi r2,r2,3 + 8020658: e0bff915 stw r2,-28(fp) + + /* Calculate new 4-byte aligned data offset */ + current_data_offset = current_data_offset - padding; + 802065c: e0fffd17 ldw r3,-12(fp) + 8020660: e0bff917 ldw r2,-28(fp) + 8020664: 1885c83a sub r2,r3,r2 + 8020668: e0bffd15 stw r2,-12(fp) + next_data_offset = (current_data_offset + ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE) & ~(ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE - 1); + 802066c: e0bffd17 ldw r2,-12(fp) + 8020670: 10c00104 addi r3,r2,4 + 8020674: 00bfff04 movi r2,-4 + 8020678: 1884703a and r2,r3,r2 + 802067c: e0bffc15 stw r2,-16(fp) + length_of_current_write = MIN(length + padding, next_data_offset - current_data_offset); + 8020680: e0fffc17 ldw r3,-16(fp) + 8020684: e0bffd17 ldw r2,-12(fp) + 8020688: 1889c83a sub r4,r3,r2 + 802068c: e0c00217 ldw r3,8(fp) + 8020690: e0bff917 ldw r2,-28(fp) + 8020694: 1887883a add r3,r3,r2 + 8020698: 2005883a mov r2,r4 + 802069c: 1880010e bge r3,r2,80206a4 + 80206a0: 1805883a mov r2,r3 + 80206a4: e0bffa15 stw r2,-24(fp) + /* Prepare the 4 bytes chunk of data to be written */ + memcpy((void *)(((int)&chunk_of_data) + (int)padding), &((alt_u8*)data)[buffer_offset], length_of_current_write - padding); + 80206a8: e0fff804 addi r3,fp,-32 + 80206ac: e0bff917 ldw r2,-28(fp) + 80206b0: 1885883a add r2,r3,r2 + 80206b4: 100f883a mov r7,r2 + 80206b8: e0bffe17 ldw r2,-8(fp) + 80206bc: e0fff417 ldw r3,-48(fp) + 80206c0: 1889883a add r4,r3,r2 + 80206c4: e0fffa17 ldw r3,-24(fp) + 80206c8: e0bff917 ldw r2,-28(fp) + 80206cc: 1885c83a sub r2,r3,r2 + 80206d0: 100d883a mov r6,r2 + 80206d4: 200b883a mov r5,r4 + 80206d8: 3809883a mov r4,r7 + 80206dc: 80086b80 call 80086b8 + buffer_offset += length_of_current_write - padding; + 80206e0: e0fffa17 ldw r3,-24(fp) + 80206e4: e0bff917 ldw r2,-28(fp) + 80206e8: 1885c83a sub r2,r3,r2 + 80206ec: e0fffe17 ldw r3,-8(fp) + 80206f0: 1885883a add r2,r3,r2 + 80206f4: e0bffe15 stw r2,-8(fp) + length -= length_of_current_write - padding; + 80206f8: e0fffa17 ldw r3,-24(fp) + 80206fc: e0bff917 ldw r2,-28(fp) + 8020700: 1885c83a sub r2,r3,r2 + 8020704: e0c00217 ldw r3,8(fp) + 8020708: 1885c83a sub r2,r3,r2 + 802070c: e0800215 stw r2,8(fp) + } + + /* Writing to flash via IO 32 bits at a time */ + IOWR_32DIRECT(flash->dev.base_addr, current_data_offset, chunk_of_data); + 8020710: e0bffb17 ldw r2,-20(fp) + 8020714: 10c00a17 ldw r3,40(r2) + 8020718: e0bffd17 ldw r2,-12(fp) + 802071c: 1885883a add r2,r3,r2 + 8020720: e0fff817 ldw r3,-32(fp) + 8020724: 10c00035 stwio r3,0(r2) + + /* Wait until flash controller idle */ + ret_code = alt_onchip_flash_poll_for_status_to_go_idle(flash); + 8020728: e13ffb17 ldw r4,-20(fp) + 802072c: 8020f200 call 8020f20 + 8020730: e0bfff15 stw r2,-4(fp) + if (ret_code != 0) + 8020734: e0bfff17 ldw r2,-4(fp) + 8020738: 10000a1e bne r2,zero,8020764 + { + break; + } + + /* Wait until flash controller indicate write passed */ + ret_code = alt_onchip_flash_poll_for_status_write_passed(flash); + 802073c: e13ffb17 ldw r4,-20(fp) + 8020740: 80210440 call 8021044 + 8020744: e0bfff15 stw r2,-4(fp) + if (ret_code != 0) + 8020748: e0bfff17 ldw r2,-4(fp) + 802074c: 1000071e bne r2,zero,802076c + { + break; + } + + /* Prepare to write next 4 bytes */ + current_data_offset = next_data_offset; + 8020750: e0bffc17 ldw r2,-16(fp) + 8020754: e0bffd15 stw r2,-12(fp) + while (length) + 8020758: e0800217 ldw r2,8(fp) + 802075c: 103f991e bne r2,zero,80205c4 + 8020760: 00000306 br 8020770 + break; + 8020764: 0001883a nop + 8020768: 00000106 br 8020770 + break; + 802076c: 0001883a nop + } + + /* Disable write and erase operation */ + ALTERA_ONCHIP_FLASH_DISABLE_WRITE_AND_ERASE_OPERATION(flash->csr_base); + 8020770: e0bffb17 ldw r2,-20(fp) + 8020774: 10802f17 ldw r2,188(r2) + 8020778: 10c00104 addi r3,r2,4 + 802077c: e0bffb17 ldw r2,-20(fp) + 8020780: 10802f17 ldw r2,188(r2) + 8020784: 10800104 addi r2,r2,4 + 8020788: 11000037 ldwio r4,0(r2) + 802078c: 00840034 movhi r2,4096 + 8020790: 10bfffc4 addi r2,r2,-1 + 8020794: 2084b03a or r2,r4,r2 + 8020798: 18800035 stwio r2,0(r3) + + return ret_code; + 802079c: e0bfff17 ldw r2,-4(fp) +} + 80207a0: e037883a mov sp,fp + 80207a4: dfc00117 ldw ra,4(sp) + 80207a8: df000017 ldw fp,0(sp) + 80207ac: dec00204 addi sp,sp,8 + 80207b0: f800283a ret + +080207b4 : + alt_flash_dev *flash_info, + int offset, + const void *src_addr, + int length +) +{ + 80207b4: defff104 addi sp,sp,-60 + 80207b8: dfc00e15 stw ra,56(sp) + 80207bc: df000d15 stw fp,52(sp) + 80207c0: df000d04 addi fp,sp,52 + 80207c4: e13ff715 stw r4,-36(fp) + 80207c8: e17ff615 stw r5,-40(fp) + 80207cc: e1bff515 stw r6,-44(fp) + 80207d0: e1fff415 stw r7,-48(fp) + int ret_code = 0; + 80207d4: e03fff15 stw zero,-4(fp) + int i,j; + int data_to_write; + int current_offset; + int full_length = length; + 80207d8: e0bff417 ldw r2,-48(fp) + 80207dc: e0bffb15 stw r2,-20(fp) + int start_offset = offset; + 80207e0: e0bff617 ldw r2,-40(fp) + 80207e4: e0bffa15 stw r2,-24(fp) + alt_onchip_flash_dev* flash = (alt_onchip_flash_dev*)flash_info; + 80207e8: e0bff717 ldw r2,-36(fp) + 80207ec: e0bff915 stw r2,-28(fp) + + /* Make sure the input parameters is not outside of this device's range. */ + if ((offset >= flash->dev.length) || (length > (flash->dev.length - offset))) + 80207f0: e0bff917 ldw r2,-28(fp) + 80207f4: 10800b17 ldw r2,44(r2) + 80207f8: e0fff617 ldw r3,-40(fp) + 80207fc: 1880060e bge r3,r2,8020818 + 8020800: e0bff917 ldw r2,-28(fp) + 8020804: 10c00b17 ldw r3,44(r2) + 8020808: e0bff617 ldw r2,-40(fp) + 802080c: 1887c83a sub r3,r3,r2 + 8020810: e0bff417 ldw r2,-48(fp) + 8020814: 1880020e bge r3,r2,8020820 + { + return -EFAULT; + 8020818: 00bffc84 movi r2,-14 + 802081c: 00009306 br 8020a6c + } + + /* + * First and foremost which sectors are affected? + */ + for(i=0;idev.number_of_regions;i++) + 8020820: e03ffe15 stw zero,-8(fp) + 8020824: 00008206 br 8020a30 + { + /* Is it in this erase block region?*/ + if((offset >= flash->dev.region_info[i].offset) && + 8020828: e0fff917 ldw r3,-28(fp) + 802082c: e0bffe17 ldw r2,-8(fp) + 8020830: 1004913a slli r2,r2,4 + 8020834: 1885883a add r2,r3,r2 + 8020838: 10800d17 ldw r2,52(r2) + 802083c: e0fff617 ldw r3,-40(fp) + 8020840: 18807816 blt r3,r2,8020a24 + (offset < (flash->dev.region_info[i].offset + + 8020844: e0fff917 ldw r3,-28(fp) + 8020848: e0bffe17 ldw r2,-8(fp) + 802084c: 1004913a slli r2,r2,4 + 8020850: 1885883a add r2,r3,r2 + 8020854: 10c00d17 ldw r3,52(r2) + flash->dev.region_info[i].region_size))) + 8020858: e13ff917 ldw r4,-28(fp) + 802085c: e0bffe17 ldw r2,-8(fp) + 8020860: 1004913a slli r2,r2,4 + 8020864: 2085883a add r2,r4,r2 + 8020868: 10800e17 ldw r2,56(r2) + (offset < (flash->dev.region_info[i].offset + + 802086c: 1885883a add r2,r3,r2 + if((offset >= flash->dev.region_info[i].offset) && + 8020870: e0fff617 ldw r3,-40(fp) + 8020874: 18806b0e bge r3,r2,8020a24 + { + current_offset = flash->dev.region_info[i].offset; + 8020878: e0fff917 ldw r3,-28(fp) + 802087c: e0bffe17 ldw r2,-8(fp) + 8020880: 1004913a slli r2,r2,4 + 8020884: 1885883a add r2,r3,r2 + 8020888: 10800d17 ldw r2,52(r2) + 802088c: e0bffc15 stw r2,-16(fp) + + for(j=0;jdev.region_info[i].number_of_blocks;j++) + 8020890: e03ffd15 stw zero,-12(fp) + 8020894: 00005c06 br 8020a08 + { + if ((offset >= current_offset ) && + 8020898: e0fff617 ldw r3,-40(fp) + 802089c: e0bffc17 ldw r2,-16(fp) + 80208a0: 18804d16 blt r3,r2,80209d8 + (offset < (current_offset + + flash->dev.region_info[i].block_size))) + 80208a4: e0fff917 ldw r3,-28(fp) + 80208a8: e0bffe17 ldw r2,-8(fp) + 80208ac: 10800104 addi r2,r2,4 + 80208b0: 1004913a slli r2,r2,4 + 80208b4: 1885883a add r2,r3,r2 + 80208b8: 10c00017 ldw r3,0(r2) + (offset < (current_offset + + 80208bc: e0bffc17 ldw r2,-16(fp) + 80208c0: 1885883a add r2,r3,r2 + if ((offset >= current_offset ) && + 80208c4: e0fff617 ldw r3,-40(fp) + 80208c8: 1880430e bge r3,r2,80209d8 + { + /* + * Check if the contents of the block are different + * from the data we wish to put there + */ + data_to_write = (current_offset + flash->dev.region_info[i].block_size - offset); + 80208cc: e0fff917 ldw r3,-28(fp) + 80208d0: e0bffe17 ldw r2,-8(fp) + 80208d4: 10800104 addi r2,r2,4 + 80208d8: 1004913a slli r2,r2,4 + 80208dc: 1885883a add r2,r3,r2 + 80208e0: 10c00017 ldw r3,0(r2) + 80208e4: e0bffc17 ldw r2,-16(fp) + 80208e8: 1887883a add r3,r3,r2 + 80208ec: e0bff617 ldw r2,-40(fp) + 80208f0: 1885c83a sub r2,r3,r2 + 80208f4: e0bff815 stw r2,-32(fp) + data_to_write = MIN(data_to_write, length); + 80208f8: e0fff817 ldw r3,-32(fp) + 80208fc: e0bff417 ldw r2,-48(fp) + 8020900: 1880010e bge r3,r2,8020908 + 8020904: 1805883a mov r2,r3 + 8020908: e0bff815 stw r2,-32(fp) + if(memcmp(src_addr, (alt_u8*)flash->dev.base_addr+offset, data_to_write)) + 802090c: e0bff917 ldw r2,-28(fp) + 8020910: 10c00a17 ldw r3,40(r2) + 8020914: e0bff617 ldw r2,-40(fp) + 8020918: 1885883a add r2,r3,r2 + 802091c: e0fff817 ldw r3,-32(fp) + 8020920: 180d883a mov r6,r3 + 8020924: 100b883a mov r5,r2 + 8020928: e13ff517 ldw r4,-44(fp) + 802092c: 8042cb80 call 8042cb8 + 8020930: 10001326 beq r2,zero,8020980 + { + ret_code = (*flash->dev.erase_block)(&flash->dev, current_offset); + 8020934: e0bff917 ldw r2,-28(fp) + 8020938: 10800817 ldw r2,32(r2) + 802093c: e0fff917 ldw r3,-28(fp) + 8020940: e17ffc17 ldw r5,-16(fp) + 8020944: 1809883a mov r4,r3 + 8020948: 103ee83a callr r2 + 802094c: e0bfff15 stw r2,-4(fp) + + if (!ret_code) + 8020950: e0bfff17 ldw r2,-4(fp) + 8020954: 10000a1e bne r2,zero,8020980 + { + ret_code = (*flash->dev.write_block)( + 8020958: e0bff917 ldw r2,-28(fp) + 802095c: 10800917 ldw r2,36(r2) + 8020960: e13ff917 ldw r4,-28(fp) + 8020964: e0fff817 ldw r3,-32(fp) + 8020968: d8c00015 stw r3,0(sp) + 802096c: e1fff517 ldw r7,-44(fp) + 8020970: e1bff617 ldw r6,-40(fp) + 8020974: e17ffc17 ldw r5,-16(fp) + 8020978: 103ee83a callr r2 + 802097c: e0bfff15 stw r2,-4(fp) + data_to_write); + } + } + + /* Was this the last block? */ + if ((length == data_to_write) || ret_code) + 8020980: e0fff417 ldw r3,-48(fp) + 8020984: e0bff817 ldw r2,-32(fp) + 8020988: 18802e26 beq r3,r2,8020a44 + 802098c: e0bfff17 ldw r2,-4(fp) + 8020990: 10002c1e bne r2,zero,8020a44 + { + goto finished; + } + + length -= data_to_write; + 8020994: e0fff417 ldw r3,-48(fp) + 8020998: e0bff817 ldw r2,-32(fp) + 802099c: 1885c83a sub r2,r3,r2 + 80209a0: e0bff415 stw r2,-48(fp) + offset = current_offset + flash->dev.region_info[i].block_size; + 80209a4: e0fff917 ldw r3,-28(fp) + 80209a8: e0bffe17 ldw r2,-8(fp) + 80209ac: 10800104 addi r2,r2,4 + 80209b0: 1004913a slli r2,r2,4 + 80209b4: 1885883a add r2,r3,r2 + 80209b8: 10800017 ldw r2,0(r2) + 80209bc: e0fffc17 ldw r3,-16(fp) + 80209c0: 1885883a add r2,r3,r2 + 80209c4: e0bff615 stw r2,-40(fp) + src_addr = (alt_u8*)src_addr + data_to_write; + 80209c8: e0bff817 ldw r2,-32(fp) + 80209cc: e0fff517 ldw r3,-44(fp) + 80209d0: 1885883a add r2,r3,r2 + 80209d4: e0bff515 stw r2,-44(fp) + } + current_offset += flash->dev.region_info[i].block_size; + 80209d8: e0fff917 ldw r3,-28(fp) + 80209dc: e0bffe17 ldw r2,-8(fp) + 80209e0: 10800104 addi r2,r2,4 + 80209e4: 1004913a slli r2,r2,4 + 80209e8: 1885883a add r2,r3,r2 + 80209ec: 10800017 ldw r2,0(r2) + 80209f0: e0fffc17 ldw r3,-16(fp) + 80209f4: 1885883a add r2,r3,r2 + 80209f8: e0bffc15 stw r2,-16(fp) + for(j=0;jdev.region_info[i].number_of_blocks;j++) + 80209fc: e0bffd17 ldw r2,-12(fp) + 8020a00: 10800044 addi r2,r2,1 + 8020a04: e0bffd15 stw r2,-12(fp) + 8020a08: e0fff917 ldw r3,-28(fp) + 8020a0c: e0bffe17 ldw r2,-8(fp) + 8020a10: 1004913a slli r2,r2,4 + 8020a14: 1885883a add r2,r3,r2 + 8020a18: 10800f17 ldw r2,60(r2) + 8020a1c: e0fffd17 ldw r3,-12(fp) + 8020a20: 18bf9d16 blt r3,r2,8020898 + for(i=0;idev.number_of_regions;i++) + 8020a24: e0bffe17 ldw r2,-8(fp) + 8020a28: 10800044 addi r2,r2,1 + 8020a2c: e0bffe15 stw r2,-8(fp) + 8020a30: e0bff917 ldw r2,-28(fp) + 8020a34: 10800c17 ldw r2,48(r2) + 8020a38: e0fffe17 ldw r3,-8(fp) + 8020a3c: 18bf7a16 blt r3,r2,8020828 + } + } + } + +finished: + 8020a40: 00000106 br 8020a48 + goto finished; + 8020a44: 0001883a nop + alt_dcache_flush((alt_u8*)flash->dev.base_addr+start_offset, full_length); + 8020a48: e0bff917 ldw r2,-28(fp) + 8020a4c: 10c00a17 ldw r3,40(r2) + 8020a50: e0bffa17 ldw r2,-24(fp) + 8020a54: 1885883a add r2,r3,r2 + 8020a58: e0fffb17 ldw r3,-20(fp) + 8020a5c: 180b883a mov r5,r3 + 8020a60: 1009883a mov r4,r2 + 8020a64: 80371c00 call 80371c0 + return ret_code; + 8020a68: e0bfff17 ldw r2,-4(fp) +} + 8020a6c: e037883a mov sp,fp + 8020a70: dfc00117 ldw ra,4(sp) + 8020a74: df000017 ldw fp,0(sp) + 8020a78: dec00204 addi sp,sp,8 + 8020a7c: f800283a ret + +08020a80 : +**/ +void altera_onchip_flash_init +( + alt_onchip_flash_dev *flash +) +{ + 8020a80: defff504 addi sp,sp,-44 + 8020a84: dfc00a15 stw ra,40(sp) + 8020a88: df000915 stw fp,36(sp) + 8020a8c: dc000815 stw r16,32(sp) + 8020a90: df000904 addi fp,sp,36 + 8020a94: e13ff715 stw r4,-36(fp) + /* A region is a sector of the onchip flash */ + int number_of_regions; + flash_region* region_info; + int sector1_status = ALTERA_ONCHIP_FLASH_STATUS_SECTOR1_AVAILABLE; + 8020a98: e03ffd15 stw zero,-12(fp) + int sector2_status = ALTERA_ONCHIP_FLASH_STATUS_SECTOR2_AVAILABLE; + 8020a9c: e03ffc15 stw zero,-16(fp) + int sector3_status = ALTERA_ONCHIP_FLASH_STATUS_SECTOR3_AVAILABLE; + 8020aa0: e03ffb15 stw zero,-20(fp) + int sector4_status = ALTERA_ONCHIP_FLASH_STATUS_SECTOR4_AVAILABLE; + 8020aa4: e03ffa15 stw zero,-24(fp) + int sector5_status = ALTERA_ONCHIP_FLASH_STATUS_SECTOR5_AVAILABLE; + 8020aa8: e03ff915 stw zero,-28(fp) + + /* Set up flash_region data structures. */ + number_of_regions = 0; + 8020aac: e03ffe15 stw zero,-8(fp) + region_info = &flash->dev.region_info[0]; + 8020ab0: e0bff717 ldw r2,-36(fp) + 8020ab4: 10800d04 addi r2,r2,52 + 8020ab8: e0bff815 stw r2,-32(fp) + + if (flash->csr_base != NULL) { + 8020abc: e0bff717 ldw r2,-36(fp) + 8020ac0: 10802f17 ldw r2,188(r2) + 8020ac4: 10001926 beq r2,zero,8020b2c + sector1_status = IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & ALTERA_ONCHIP_FLASH_STATUS_SECTOR1_MSK; + 8020ac8: e0bff717 ldw r2,-36(fp) + 8020acc: 10802f17 ldw r2,188(r2) + 8020ad0: 10800037 ldwio r2,0(r2) + 8020ad4: 1080080c andi r2,r2,32 + 8020ad8: e0bffd15 stw r2,-12(fp) + sector2_status = IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & ALTERA_ONCHIP_FLASH_STATUS_SECTOR2_MSK; + 8020adc: e0bff717 ldw r2,-36(fp) + 8020ae0: 10802f17 ldw r2,188(r2) + 8020ae4: 10800037 ldwio r2,0(r2) + 8020ae8: 1080100c andi r2,r2,64 + 8020aec: e0bffc15 stw r2,-16(fp) + sector3_status = IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & ALTERA_ONCHIP_FLASH_STATUS_SECTOR3_MSK; + 8020af0: e0bff717 ldw r2,-36(fp) + 8020af4: 10802f17 ldw r2,188(r2) + 8020af8: 10800037 ldwio r2,0(r2) + 8020afc: 1080200c andi r2,r2,128 + 8020b00: e0bffb15 stw r2,-20(fp) + sector4_status = IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & ALTERA_ONCHIP_FLASH_STATUS_SECTOR4_MSK; + 8020b04: e0bff717 ldw r2,-36(fp) + 8020b08: 10802f17 ldw r2,188(r2) + 8020b0c: 10800037 ldwio r2,0(r2) + 8020b10: 1080400c andi r2,r2,256 + 8020b14: e0bffa15 stw r2,-24(fp) + sector5_status = IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & ALTERA_ONCHIP_FLASH_STATUS_SECTOR5_MSK; + 8020b18: e0bff717 ldw r2,-36(fp) + 8020b1c: 10802f17 ldw r2,188(r2) + 8020b20: 10800037 ldwio r2,0(r2) + 8020b24: 1080800c andi r2,r2,512 + 8020b28: e0bff915 stw r2,-28(fp) + } + + if ((flash->sector1_enabled == 1) && (sector1_status != ALTERA_ONCHIP_FLASH_STATUS_SECTOR1_UNAVAILABLE)) { + 8020b2c: e0bff717 ldw r2,-36(fp) + 8020b30: 10803017 ldw r2,192(r2) + 8020b34: 10800058 cmpnei r2,r2,1 + 8020b38: 10002c1e bne r2,zero,8020bec + 8020b3c: e0bffd17 ldw r2,-12(fp) + 8020b40: 10800820 cmpeqi r2,r2,32 + 8020b44: 1000291e bne r2,zero,8020bec + + region_info[number_of_regions].offset = flash->sector1_start_addr; + 8020b48: e0bffe17 ldw r2,-8(fp) + 8020b4c: 1004913a slli r2,r2,4 + 8020b50: e0fff817 ldw r3,-32(fp) + 8020b54: 1885883a add r2,r3,r2 + 8020b58: e0fff717 ldw r3,-36(fp) + 8020b5c: 18c03117 ldw r3,196(r3) + 8020b60: 10c00015 stw r3,0(r2) + region_info[number_of_regions].region_size = flash->sector1_end_addr - flash->sector1_start_addr + 1; + 8020b64: e0bff717 ldw r2,-36(fp) + 8020b68: 10c03217 ldw r3,200(r2) + 8020b6c: e0bff717 ldw r2,-36(fp) + 8020b70: 10803117 ldw r2,196(r2) + 8020b74: 1887c83a sub r3,r3,r2 + 8020b78: e0bffe17 ldw r2,-8(fp) + 8020b7c: 1004913a slli r2,r2,4 + 8020b80: e13ff817 ldw r4,-32(fp) + 8020b84: 2085883a add r2,r4,r2 + 8020b88: 18c00044 addi r3,r3,1 + 8020b8c: 10c00115 stw r3,4(r2) + region_info[number_of_regions].number_of_blocks = flash->dev.region_info[number_of_regions].region_size / flash->page_size; + 8020b90: e0fff717 ldw r3,-36(fp) + 8020b94: e0bffe17 ldw r2,-8(fp) + 8020b98: 1004913a slli r2,r2,4 + 8020b9c: 1885883a add r2,r3,r2 + 8020ba0: 11000e17 ldw r4,56(r2) + 8020ba4: e0bff717 ldw r2,-36(fp) + 8020ba8: 11403f17 ldw r5,252(r2) + 8020bac: e0bffe17 ldw r2,-8(fp) + 8020bb0: 1004913a slli r2,r2,4 + 8020bb4: e0fff817 ldw r3,-32(fp) + 8020bb8: 18a1883a add r16,r3,r2 + 8020bbc: 800cf000 call 800cf00 <__divsi3> + 8020bc0: 80800215 stw r2,8(r16) + region_info[number_of_regions].block_size = flash->page_size; + 8020bc4: e0bffe17 ldw r2,-8(fp) + 8020bc8: 1004913a slli r2,r2,4 + 8020bcc: e0fff817 ldw r3,-32(fp) + 8020bd0: 1885883a add r2,r3,r2 + 8020bd4: e0fff717 ldw r3,-36(fp) + 8020bd8: 18c03f17 ldw r3,252(r3) + 8020bdc: 10c00315 stw r3,12(r2) + + number_of_regions++; + 8020be0: e0bffe17 ldw r2,-8(fp) + 8020be4: 10800044 addi r2,r2,1 + 8020be8: e0bffe15 stw r2,-8(fp) + } + + if ((flash->sector2_enabled == 1) && (sector2_status != ALTERA_ONCHIP_FLASH_STATUS_SECTOR2_UNAVAILABLE)) { + 8020bec: e0bff717 ldw r2,-36(fp) + 8020bf0: 10803317 ldw r2,204(r2) + 8020bf4: 10800058 cmpnei r2,r2,1 + 8020bf8: 10002c1e bne r2,zero,8020cac + 8020bfc: e0bffc17 ldw r2,-16(fp) + 8020c00: 10801020 cmpeqi r2,r2,64 + 8020c04: 1000291e bne r2,zero,8020cac + + region_info[number_of_regions].offset = flash->sector2_start_addr; + 8020c08: e0bffe17 ldw r2,-8(fp) + 8020c0c: 1004913a slli r2,r2,4 + 8020c10: e0fff817 ldw r3,-32(fp) + 8020c14: 1885883a add r2,r3,r2 + 8020c18: e0fff717 ldw r3,-36(fp) + 8020c1c: 18c03417 ldw r3,208(r3) + 8020c20: 10c00015 stw r3,0(r2) + region_info[number_of_regions].region_size = flash->sector2_end_addr - flash->sector2_start_addr + 1; + 8020c24: e0bff717 ldw r2,-36(fp) + 8020c28: 10c03517 ldw r3,212(r2) + 8020c2c: e0bff717 ldw r2,-36(fp) + 8020c30: 10803417 ldw r2,208(r2) + 8020c34: 1887c83a sub r3,r3,r2 + 8020c38: e0bffe17 ldw r2,-8(fp) + 8020c3c: 1004913a slli r2,r2,4 + 8020c40: e13ff817 ldw r4,-32(fp) + 8020c44: 2085883a add r2,r4,r2 + 8020c48: 18c00044 addi r3,r3,1 + 8020c4c: 10c00115 stw r3,4(r2) + region_info[number_of_regions].number_of_blocks = flash->dev.region_info[number_of_regions].region_size / flash->page_size; + 8020c50: e0fff717 ldw r3,-36(fp) + 8020c54: e0bffe17 ldw r2,-8(fp) + 8020c58: 1004913a slli r2,r2,4 + 8020c5c: 1885883a add r2,r3,r2 + 8020c60: 11000e17 ldw r4,56(r2) + 8020c64: e0bff717 ldw r2,-36(fp) + 8020c68: 11403f17 ldw r5,252(r2) + 8020c6c: e0bffe17 ldw r2,-8(fp) + 8020c70: 1004913a slli r2,r2,4 + 8020c74: e0fff817 ldw r3,-32(fp) + 8020c78: 18a1883a add r16,r3,r2 + 8020c7c: 800cf000 call 800cf00 <__divsi3> + 8020c80: 80800215 stw r2,8(r16) + region_info[number_of_regions].block_size = flash->page_size; + 8020c84: e0bffe17 ldw r2,-8(fp) + 8020c88: 1004913a slli r2,r2,4 + 8020c8c: e0fff817 ldw r3,-32(fp) + 8020c90: 1885883a add r2,r3,r2 + 8020c94: e0fff717 ldw r3,-36(fp) + 8020c98: 18c03f17 ldw r3,252(r3) + 8020c9c: 10c00315 stw r3,12(r2) + + number_of_regions++; + 8020ca0: e0bffe17 ldw r2,-8(fp) + 8020ca4: 10800044 addi r2,r2,1 + 8020ca8: e0bffe15 stw r2,-8(fp) + } + + if ((flash->sector3_enabled == 1) && (sector3_status != ALTERA_ONCHIP_FLASH_STATUS_SECTOR3_UNAVAILABLE)) { + 8020cac: e0bff717 ldw r2,-36(fp) + 8020cb0: 10803617 ldw r2,216(r2) + 8020cb4: 10800058 cmpnei r2,r2,1 + 8020cb8: 10002c1e bne r2,zero,8020d6c + 8020cbc: e0bffb17 ldw r2,-20(fp) + 8020cc0: 10802020 cmpeqi r2,r2,128 + 8020cc4: 1000291e bne r2,zero,8020d6c + + region_info[number_of_regions].offset = flash->sector3_start_addr; + 8020cc8: e0bffe17 ldw r2,-8(fp) + 8020ccc: 1004913a slli r2,r2,4 + 8020cd0: e0fff817 ldw r3,-32(fp) + 8020cd4: 1885883a add r2,r3,r2 + 8020cd8: e0fff717 ldw r3,-36(fp) + 8020cdc: 18c03717 ldw r3,220(r3) + 8020ce0: 10c00015 stw r3,0(r2) + region_info[number_of_regions].region_size = flash->sector3_end_addr - flash->sector3_start_addr + 1; + 8020ce4: e0bff717 ldw r2,-36(fp) + 8020ce8: 10c03817 ldw r3,224(r2) + 8020cec: e0bff717 ldw r2,-36(fp) + 8020cf0: 10803717 ldw r2,220(r2) + 8020cf4: 1887c83a sub r3,r3,r2 + 8020cf8: e0bffe17 ldw r2,-8(fp) + 8020cfc: 1004913a slli r2,r2,4 + 8020d00: e13ff817 ldw r4,-32(fp) + 8020d04: 2085883a add r2,r4,r2 + 8020d08: 18c00044 addi r3,r3,1 + 8020d0c: 10c00115 stw r3,4(r2) + region_info[number_of_regions].number_of_blocks = flash->dev.region_info[number_of_regions].region_size / flash->page_size; + 8020d10: e0fff717 ldw r3,-36(fp) + 8020d14: e0bffe17 ldw r2,-8(fp) + 8020d18: 1004913a slli r2,r2,4 + 8020d1c: 1885883a add r2,r3,r2 + 8020d20: 11000e17 ldw r4,56(r2) + 8020d24: e0bff717 ldw r2,-36(fp) + 8020d28: 11403f17 ldw r5,252(r2) + 8020d2c: e0bffe17 ldw r2,-8(fp) + 8020d30: 1004913a slli r2,r2,4 + 8020d34: e0fff817 ldw r3,-32(fp) + 8020d38: 18a1883a add r16,r3,r2 + 8020d3c: 800cf000 call 800cf00 <__divsi3> + 8020d40: 80800215 stw r2,8(r16) + region_info[number_of_regions].block_size = flash->page_size; + 8020d44: e0bffe17 ldw r2,-8(fp) + 8020d48: 1004913a slli r2,r2,4 + 8020d4c: e0fff817 ldw r3,-32(fp) + 8020d50: 1885883a add r2,r3,r2 + 8020d54: e0fff717 ldw r3,-36(fp) + 8020d58: 18c03f17 ldw r3,252(r3) + 8020d5c: 10c00315 stw r3,12(r2) + + number_of_regions++; + 8020d60: e0bffe17 ldw r2,-8(fp) + 8020d64: 10800044 addi r2,r2,1 + 8020d68: e0bffe15 stw r2,-8(fp) + } + + if ((flash->sector4_enabled == 1) && (sector4_status != ALTERA_ONCHIP_FLASH_STATUS_SECTOR4_UNAVAILABLE)) { + 8020d6c: e0bff717 ldw r2,-36(fp) + 8020d70: 10803917 ldw r2,228(r2) + 8020d74: 10800058 cmpnei r2,r2,1 + 8020d78: 10002c1e bne r2,zero,8020e2c + 8020d7c: e0bffa17 ldw r2,-24(fp) + 8020d80: 10804020 cmpeqi r2,r2,256 + 8020d84: 1000291e bne r2,zero,8020e2c + + region_info[number_of_regions].offset = flash->sector4_start_addr; + 8020d88: e0bffe17 ldw r2,-8(fp) + 8020d8c: 1004913a slli r2,r2,4 + 8020d90: e0fff817 ldw r3,-32(fp) + 8020d94: 1885883a add r2,r3,r2 + 8020d98: e0fff717 ldw r3,-36(fp) + 8020d9c: 18c03a17 ldw r3,232(r3) + 8020da0: 10c00015 stw r3,0(r2) + region_info[number_of_regions].region_size = flash->sector4_end_addr - flash->sector4_start_addr + 1; + 8020da4: e0bff717 ldw r2,-36(fp) + 8020da8: 10c03b17 ldw r3,236(r2) + 8020dac: e0bff717 ldw r2,-36(fp) + 8020db0: 10803a17 ldw r2,232(r2) + 8020db4: 1887c83a sub r3,r3,r2 + 8020db8: e0bffe17 ldw r2,-8(fp) + 8020dbc: 1004913a slli r2,r2,4 + 8020dc0: e13ff817 ldw r4,-32(fp) + 8020dc4: 2085883a add r2,r4,r2 + 8020dc8: 18c00044 addi r3,r3,1 + 8020dcc: 10c00115 stw r3,4(r2) + region_info[number_of_regions].number_of_blocks = flash->dev.region_info[number_of_regions].region_size / flash->page_size; + 8020dd0: e0fff717 ldw r3,-36(fp) + 8020dd4: e0bffe17 ldw r2,-8(fp) + 8020dd8: 1004913a slli r2,r2,4 + 8020ddc: 1885883a add r2,r3,r2 + 8020de0: 11000e17 ldw r4,56(r2) + 8020de4: e0bff717 ldw r2,-36(fp) + 8020de8: 11403f17 ldw r5,252(r2) + 8020dec: e0bffe17 ldw r2,-8(fp) + 8020df0: 1004913a slli r2,r2,4 + 8020df4: e0fff817 ldw r3,-32(fp) + 8020df8: 18a1883a add r16,r3,r2 + 8020dfc: 800cf000 call 800cf00 <__divsi3> + 8020e00: 80800215 stw r2,8(r16) + region_info[number_of_regions].block_size = flash->page_size; + 8020e04: e0bffe17 ldw r2,-8(fp) + 8020e08: 1004913a slli r2,r2,4 + 8020e0c: e0fff817 ldw r3,-32(fp) + 8020e10: 1885883a add r2,r3,r2 + 8020e14: e0fff717 ldw r3,-36(fp) + 8020e18: 18c03f17 ldw r3,252(r3) + 8020e1c: 10c00315 stw r3,12(r2) + + number_of_regions++; + 8020e20: e0bffe17 ldw r2,-8(fp) + 8020e24: 10800044 addi r2,r2,1 + 8020e28: e0bffe15 stw r2,-8(fp) + } + + if ((flash->sector5_enabled == 1) && (sector5_status != ALTERA_ONCHIP_FLASH_STATUS_SECTOR5_UNAVAILABLE)) { + 8020e2c: e0bff717 ldw r2,-36(fp) + 8020e30: 10803c17 ldw r2,240(r2) + 8020e34: 10800058 cmpnei r2,r2,1 + 8020e38: 10002c1e bne r2,zero,8020eec + 8020e3c: e0bff917 ldw r2,-28(fp) + 8020e40: 10808020 cmpeqi r2,r2,512 + 8020e44: 1000291e bne r2,zero,8020eec + + region_info[number_of_regions].offset = flash->sector5_start_addr; + 8020e48: e0bffe17 ldw r2,-8(fp) + 8020e4c: 1004913a slli r2,r2,4 + 8020e50: e0fff817 ldw r3,-32(fp) + 8020e54: 1885883a add r2,r3,r2 + 8020e58: e0fff717 ldw r3,-36(fp) + 8020e5c: 18c03d17 ldw r3,244(r3) + 8020e60: 10c00015 stw r3,0(r2) + region_info[number_of_regions].region_size = flash->sector5_end_addr - flash->sector5_start_addr + 1; + 8020e64: e0bff717 ldw r2,-36(fp) + 8020e68: 10c03e17 ldw r3,248(r2) + 8020e6c: e0bff717 ldw r2,-36(fp) + 8020e70: 10803d17 ldw r2,244(r2) + 8020e74: 1887c83a sub r3,r3,r2 + 8020e78: e0bffe17 ldw r2,-8(fp) + 8020e7c: 1004913a slli r2,r2,4 + 8020e80: e13ff817 ldw r4,-32(fp) + 8020e84: 2085883a add r2,r4,r2 + 8020e88: 18c00044 addi r3,r3,1 + 8020e8c: 10c00115 stw r3,4(r2) + region_info[number_of_regions].number_of_blocks = flash->dev.region_info[number_of_regions].region_size / flash->page_size; + 8020e90: e0fff717 ldw r3,-36(fp) + 8020e94: e0bffe17 ldw r2,-8(fp) + 8020e98: 1004913a slli r2,r2,4 + 8020e9c: 1885883a add r2,r3,r2 + 8020ea0: 11000e17 ldw r4,56(r2) + 8020ea4: e0bff717 ldw r2,-36(fp) + 8020ea8: 11403f17 ldw r5,252(r2) + 8020eac: e0bffe17 ldw r2,-8(fp) + 8020eb0: 1004913a slli r2,r2,4 + 8020eb4: e0fff817 ldw r3,-32(fp) + 8020eb8: 18a1883a add r16,r3,r2 + 8020ebc: 800cf000 call 800cf00 <__divsi3> + 8020ec0: 80800215 stw r2,8(r16) + region_info[number_of_regions].block_size = flash->page_size; + 8020ec4: e0bffe17 ldw r2,-8(fp) + 8020ec8: 1004913a slli r2,r2,4 + 8020ecc: e0fff817 ldw r3,-32(fp) + 8020ed0: 1885883a add r2,r3,r2 + 8020ed4: e0fff717 ldw r3,-36(fp) + 8020ed8: 18c03f17 ldw r3,252(r3) + 8020edc: 10c00315 stw r3,12(r2) + + number_of_regions++; + 8020ee0: e0bffe17 ldw r2,-8(fp) + 8020ee4: 10800044 addi r2,r2,1 + 8020ee8: e0bffe15 stw r2,-8(fp) + } + + /* Update number of regions. */ + flash->dev.number_of_regions = number_of_regions; + 8020eec: e0bff717 ldw r2,-36(fp) + 8020ef0: e0fffe17 ldw r3,-8(fp) + 8020ef4: 10c00c15 stw r3,48(r2) + + /* + * Register this device as a valid flash device type + */ + alt_flash_device_register(&(flash->dev)); + 8020ef8: e0bff717 ldw r2,-36(fp) + 8020efc: 1009883a mov r4,r2 + 8020f00: 80201d80 call 80201d8 +} + 8020f04: 0001883a nop + 8020f08: e6ffff04 addi sp,fp,-4 + 8020f0c: dfc00217 ldw ra,8(sp) + 8020f10: df000117 ldw fp,4(sp) + 8020f14: dc000017 ldw r16,0(sp) + 8020f18: dec00304 addi sp,sp,12 + 8020f1c: f800283a ret + +08020f20 : +**/ +int alt_onchip_flash_poll_for_status_to_go_idle +( + alt_onchip_flash_dev *flash +) +{ + 8020f20: defffa04 addi sp,sp,-24 + 8020f24: dfc00515 stw ra,20(sp) + 8020f28: df000415 stw fp,16(sp) + 8020f2c: df000404 addi fp,sp,16 + 8020f30: e13ffc15 stw r4,-16(fp) + int ret_code = 0; + 8020f34: e03fff15 stw zero,-4(fp) + int timeout = ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE; + 8020f38: 008002f4 movhi r2,11 + 8020f3c: 10ab9804 addi r2,r2,-20896 + 8020f40: e0bffd15 stw r2,-12(fp) + int count_down = ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE; + 8020f44: 008002f4 movhi r2,11 + 8020f48: 10ab9804 addi r2,r2,-20896 + 8020f4c: e0bffe15 stw r2,-8(fp) + + while ( + 8020f50: 00000c06 br 8020f84 + (IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & + ALTERA_ONCHIP_FLASH_STATUS_BUSY_MSK + ) != ALTERA_ONCHIP_FLASH_STATUS_BUSY_IDLE + ) { + + alt_busy_sleep(1); /* delay 1us */ + 8020f54: 01000044 movi r4,1 + 8020f58: 8036f5c0 call 8036f5c + + /* If timeout value is zero, it will never timeout. */ + if (timeout != 0) { + 8020f5c: e0bffd17 ldw r2,-12(fp) + 8020f60: 10000826 beq r2,zero,8020f84 + count_down--; + 8020f64: e0bffe17 ldw r2,-8(fp) + 8020f68: 10bfffc4 addi r2,r2,-1 + 8020f6c: e0bffe15 stw r2,-8(fp) + if (count_down == 0) { + 8020f70: e0bffe17 ldw r2,-8(fp) + 8020f74: 1000031e bne r2,zero,8020f84 + /* Timeout */ + ret_code = -ETIMEDOUT; + 8020f78: 00bfe304 movi r2,-116 + 8020f7c: e0bfff15 stw r2,-4(fp) + break; + 8020f80: 00000506 br 8020f98 + (IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & + 8020f84: e0bffc17 ldw r2,-16(fp) + 8020f88: 10802f17 ldw r2,188(r2) + 8020f8c: 10800037 ldwio r2,0(r2) + 8020f90: 108000cc andi r2,r2,3 + while ( + 8020f94: 103fef1e bne r2,zero,8020f54 + } + } + } + + return ret_code; + 8020f98: e0bfff17 ldw r2,-4(fp) +} + 8020f9c: e037883a mov sp,fp + 8020fa0: dfc00117 ldw ra,4(sp) + 8020fa4: df000017 ldw fp,0(sp) + 8020fa8: dec00204 addi sp,sp,8 + 8020fac: f800283a ret + +08020fb0 : +**/ +int alt_onchip_flash_poll_for_status_erase_passed +( + alt_onchip_flash_dev *flash +) +{ + 8020fb0: defffa04 addi sp,sp,-24 + 8020fb4: dfc00515 stw ra,20(sp) + 8020fb8: df000415 stw fp,16(sp) + 8020fbc: df000404 addi fp,sp,16 + 8020fc0: e13ffc15 stw r4,-16(fp) + int ret_code = 0; + 8020fc4: e03fff15 stw zero,-4(fp) + int timeout = ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE; + 8020fc8: 008002f4 movhi r2,11 + 8020fcc: 10ab9804 addi r2,r2,-20896 + 8020fd0: e0bffd15 stw r2,-12(fp) + int count_down = ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE; + 8020fd4: 008002f4 movhi r2,11 + 8020fd8: 10ab9804 addi r2,r2,-20896 + 8020fdc: e0bffe15 stw r2,-8(fp) + + while ( + 8020fe0: 00000c06 br 8021014 + (IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & + ALTERA_ONCHIP_FLASH_STATUS_ERASE_MSK + ) != ALTERA_ONCHIP_FLASH_STATUS_ERASE_PASSED + ) { + + alt_busy_sleep(1); /* delay 1us */ + 8020fe4: 01000044 movi r4,1 + 8020fe8: 8036f5c0 call 8036f5c + + /* If timeout value is zero, it will never timeout. */ + if (timeout != 0) { + 8020fec: e0bffd17 ldw r2,-12(fp) + 8020ff0: 10000826 beq r2,zero,8021014 + count_down--; + 8020ff4: e0bffe17 ldw r2,-8(fp) + 8020ff8: 10bfffc4 addi r2,r2,-1 + 8020ffc: e0bffe15 stw r2,-8(fp) + if (count_down == 0) { + 8021000: e0bffe17 ldw r2,-8(fp) + 8021004: 1000031e bne r2,zero,8021014 + /* Timeout */ + ret_code = -ETIMEDOUT; + 8021008: 00bfe304 movi r2,-116 + 802100c: e0bfff15 stw r2,-4(fp) + break; + 8021010: 00000606 br 802102c + (IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & + 8021014: e0bffc17 ldw r2,-16(fp) + 8021018: 10802f17 ldw r2,188(r2) + 802101c: 10800037 ldwio r2,0(r2) + 8021020: 1080040c andi r2,r2,16 + while ( + 8021024: 10800418 cmpnei r2,r2,16 + 8021028: 103fee1e bne r2,zero,8020fe4 + } + } + } + + return ret_code; + 802102c: e0bfff17 ldw r2,-4(fp) +} + 8021030: e037883a mov sp,fp + 8021034: dfc00117 ldw ra,4(sp) + 8021038: df000017 ldw fp,0(sp) + 802103c: dec00204 addi sp,sp,8 + 8021040: f800283a ret + +08021044 : +**/ +int alt_onchip_flash_poll_for_status_write_passed +( + alt_onchip_flash_dev *flash +) +{ + 8021044: defffa04 addi sp,sp,-24 + 8021048: dfc00515 stw ra,20(sp) + 802104c: df000415 stw fp,16(sp) + 8021050: df000404 addi fp,sp,16 + 8021054: e13ffc15 stw r4,-16(fp) + int ret_code = 0; + 8021058: e03fff15 stw zero,-4(fp) + int timeout = ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE; + 802105c: 008002f4 movhi r2,11 + 8021060: 10ab9804 addi r2,r2,-20896 + 8021064: e0bffd15 stw r2,-12(fp) + int count_down = ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE; + 8021068: 008002f4 movhi r2,11 + 802106c: 10ab9804 addi r2,r2,-20896 + 8021070: e0bffe15 stw r2,-8(fp) + + while ( + 8021074: 00000c06 br 80210a8 + (IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & + ALTERA_ONCHIP_FLASH_STATUS_WRITE_MSK + ) != ALTERA_ONCHIP_FLASH_STATUS_WRITE_PASSED + ) { + + alt_busy_sleep(1); /* delay 1us */ + 8021078: 01000044 movi r4,1 + 802107c: 8036f5c0 call 8036f5c + + /* If timeout value is zero, it will never timeout. */ + if (timeout != 0) { + 8021080: e0bffd17 ldw r2,-12(fp) + 8021084: 10000826 beq r2,zero,80210a8 + count_down--; + 8021088: e0bffe17 ldw r2,-8(fp) + 802108c: 10bfffc4 addi r2,r2,-1 + 8021090: e0bffe15 stw r2,-8(fp) + if (count_down == 0) { + 8021094: e0bffe17 ldw r2,-8(fp) + 8021098: 1000031e bne r2,zero,80210a8 + /* Timeout */ + ret_code = -ETIMEDOUT; + 802109c: 00bfe304 movi r2,-116 + 80210a0: e0bfff15 stw r2,-4(fp) + break; + 80210a4: 00000606 br 80210c0 + (IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & + 80210a8: e0bffc17 ldw r2,-16(fp) + 80210ac: 10802f17 ldw r2,188(r2) + 80210b0: 10800037 ldwio r2,0(r2) + 80210b4: 1080020c andi r2,r2,8 + while ( + 80210b8: 10800218 cmpnei r2,r2,8 + 80210bc: 103fee1e bne r2,zero,8021078 + } + } + } + + return ret_code; + 80210c0: e0bfff17 ldw r2,-4(fp) +} + 80210c4: e037883a mov sp,fp + 80210c8: dfc00117 ldw ra,4(sp) + 80210cc: df000017 ldw fp,0(sp) + 80210d0: dec00204 addi sp,sp,8 + 80210d4: f800283a ret + +080210d8 : + * @Return ENP_HARDWARE on error, otherwise return SUCCESS + */ + +error_t altera_eth_tse_init( + alt_iniche_dev *p_dev) +{ + 80210d8: defffa04 addi sp,sp,-24 + 80210dc: dfc00515 stw ra,20(sp) + 80210e0: df000415 stw fp,16(sp) + 80210e4: df000404 addi fp,sp,16 + 80210e8: e13ffc15 stw r4,-16(fp) + int i; + + alt_tse_iniche_dev_driver_data *p_driver_data = 0; + 80210ec: e03ffe15 stw zero,-8(fp) + alt_tse_system_info *psys_info = 0; + 80210f0: e03ffd15 stw zero,-12(fp) + + dprintf("altera_eth_tse_init %d\n", p_dev->if_num); + 80210f4: e0bffc17 ldw r2,-16(fp) + 80210f8: 10800517 ldw r2,20(r2) + 80210fc: 100b883a mov r5,r2 + 8021100: 01020174 movhi r4,2053 + 8021104: 2125ca04 addi r4,r4,-26840 + 8021108: 8002c780 call 8002c78 + + /* Get the pointer to the alt_tse_iniche_dev_driver_data structure from the global array */ + for(i = 0; i < number_of_tse_mac; i++) { + 802110c: e03fff15 stw zero,-4(fp) + 8021110: 00001006 br 8021154 + if(tse_iniche_dev_driver_data[i].p_dev == p_dev) { + 8021114: e0bfff17 ldw r2,-4(fp) + 8021118: 10c00324 muli r3,r2,12 + 802111c: 008201b4 movhi r2,2054 + 8021120: 1885883a add r2,r3,r2 + 8021124: 10b5b617 ldw r2,-10536(r2) + 8021128: e0fffc17 ldw r3,-16(fp) + 802112c: 1880061e bne r3,r2,8021148 + p_driver_data = &tse_iniche_dev_driver_data[i]; + 8021130: e0bfff17 ldw r2,-4(fp) + 8021134: 10c00324 muli r3,r2,12 + 8021138: 008201b4 movhi r2,2054 + 802113c: 10b5b604 addi r2,r2,-10536 + 8021140: 1885883a add r2,r3,r2 + 8021144: e0bffe15 stw r2,-8(fp) + for(i = 0; i < number_of_tse_mac; i++) { + 8021148: e0bfff17 ldw r2,-4(fp) + 802114c: 10800044 addi r2,r2,1 + 8021150: e0bfff15 stw r2,-4(fp) + 8021154: d0a05c03 ldbu r2,-32400(gp) + 8021158: 10803fcc andi r2,r2,255 + 802115c: e0ffff17 ldw r3,-4(fp) + 8021160: 18bfec16 blt r3,r2,8021114 + } + } + /* If pointer could not found */ + if(p_driver_data == 0) { + 8021164: e0bffe17 ldw r2,-8(fp) + 8021168: 1000021e bne r2,zero,8021174 + return ENP_HARDWARE; + 802116c: 00bff744 movi r2,-35 + 8021170: 00002606 br 802120c + } + + /* Get the pointer to the alt_tse_system_info structure from the global array */ + for(i = 0; i < max_mac_system; i++) { + 8021174: e03fff15 stw zero,-4(fp) + 8021178: 00001106 br 80211c0 + if(tse_mac_device[i].tse_mac_base == p_driver_data->hw_mac_base_addr) { + 802117c: e0bfff17 ldw r2,-4(fp) + 8021180: 10c01324 muli r3,r2,76 + 8021184: 00820174 movhi r2,2053 + 8021188: 1885883a add r2,r3,r2 + 802118c: 10ee5417 ldw r3,-18096(r2) + 8021190: e0bffe17 ldw r2,-8(fp) + 8021194: 10800117 ldw r2,4(r2) + 8021198: 1880061e bne r3,r2,80211b4 + psys_info = &tse_mac_device[i]; + 802119c: e0bfff17 ldw r2,-4(fp) + 80211a0: 10c01324 muli r3,r2,76 + 80211a4: 00820174 movhi r2,2053 + 80211a8: 10ae5404 addi r2,r2,-18096 + 80211ac: 1885883a add r2,r3,r2 + 80211b0: e0bffd15 stw r2,-12(fp) + for(i = 0; i < max_mac_system; i++) { + 80211b4: e0bfff17 ldw r2,-4(fp) + 80211b8: 10800044 addi r2,r2,1 + 80211bc: e0bfff15 stw r2,-4(fp) + 80211c0: d0a00a03 ldbu r2,-32728(gp) + 80211c4: 10803fcc andi r2,r2,255 + 80211c8: e0ffff17 ldw r3,-4(fp) + 80211cc: 18bfeb16 blt r3,r2,802117c + } + } + /* If pointer could not found */ + if(psys_info == 0) { + 80211d0: e0bffd17 ldw r2,-12(fp) + 80211d4: 1000021e bne r2,zero,80211e0 + return ENP_HARDWARE; + 80211d8: 00bff744 movi r2,-35 + 80211dc: 00000b06 br 802120c + } + + prep_tse_mac(p_dev->if_num, psys_info + p_driver_data->hw_channel_number); + 80211e0: e0bffc17 ldw r2,-16(fp) + 80211e4: 11000517 ldw r4,20(r2) + 80211e8: e0bffe17 ldw r2,-8(fp) + 80211ec: 10800203 ldbu r2,8(r2) + 80211f0: 10803fcc andi r2,r2,255 + 80211f4: 10801324 muli r2,r2,76 + 80211f8: e0fffd17 ldw r3,-12(fp) + 80211fc: 1885883a add r2,r3,r2 + 8021200: 100b883a mov r5,r2 + 8021204: 80212200 call 8021220 + + return SUCCESS; + 8021208: 0005883a mov r2,zero +} + 802120c: e037883a mov sp,fp + 8021210: dfc00117 ldw ra,4(sp) + 8021214: df000017 ldw fp,0(sp) + 8021218: dec00204 addi sp,sp,8 + 802121c: f800283a ret + +08021220 : + * @Param index index of the NET structure associated with TSE instance + * @Param psys_info pointer to the TSE hardware info structure + * @Return next index of NET + */ +int prep_tse_mac(int index, alt_tse_system_info *psys_info) +{ + 8021220: defffb04 addi sp,sp,-20 + 8021224: dfc00415 stw ra,16(sp) + 8021228: df000315 stw fp,12(sp) + 802122c: df000304 addi fp,sp,12 + 8021230: e13ffe15 stw r4,-8(fp) + 8021234: e17ffd15 stw r5,-12(fp) + NET ifp; + dprintf("prep_tse_mac %d\n", index); + 8021238: e17ffe17 ldw r5,-8(fp) + 802123c: 01020174 movhi r4,2053 + 8021240: 2125d004 addi r4,r4,-26816 + 8021244: 8002c780 call 8002c78 + { + tse[index].sem = 0; /*Tx IDLE*/ + 8021248: e0bffe17 ldw r2,-8(fp) + 802124c: 10c02924 muli r3,r2,164 + 8021250: 008201b4 movhi r2,2054 + 8021254: 1885883a add r2,r3,r2 + 8021258: 1035cd15 stw zero,-10444(r2) + tse[index].tse = (void *)psys_info; + 802125c: e0bffe17 ldw r2,-8(fp) + 8021260: 11002924 muli r4,r2,164 + 8021264: e0fffd17 ldw r3,-12(fp) + 8021268: 008201b4 movhi r2,2054 + 802126c: 2085883a add r2,r4,r2 + 8021270: 10f5ea15 stw r3,-10328(r2) + + ifp = nets[index]; + 8021274: e0bffe17 ldw r2,-8(fp) + 8021278: 100690ba slli r3,r2,2 + 802127c: 008201b4 movhi r2,2054 + 8021280: 1885883a add r2,r3,r2 + 8021284: 10b77017 ldw r2,-8768(r2) + 8021288: e0bfff15 stw r2,-4(fp) + ifp->n_mib->ifAdminStatus = ALTERA_TSE_ADMIN_STATUS_DOWN; /* status = down */ + 802128c: e0bfff17 ldw r2,-4(fp) + 8021290: 10802717 ldw r2,156(r2) + 8021294: 00c00084 movi r3,2 + 8021298: 10c00615 stw r3,24(r2) + ifp->n_mib->ifOperStatus = ALTERA_TSE_ADMIN_STATUS_DOWN; + 802129c: e0bfff17 ldw r2,-4(fp) + 80212a0: 10802717 ldw r2,156(r2) + 80212a4: 00c00084 movi r3,2 + 80212a8: 10c00715 stw r3,28(r2) + ifp->n_mib->ifLastChange = cticks * (100/TPS); + 80212ac: e0bfff17 ldw r2,-4(fp) + 80212b0: 10802717 ldw r2,156(r2) + 80212b4: d0e07d17 ldw r3,-32268(gp) + 80212b8: 10c00815 stw r3,32(r2) + ifp->n_mib->ifPhysAddress = (u_char*)tse[index].mac_addr; + 80212bc: e0bfff17 ldw r2,-4(fp) + 80212c0: 10c02717 ldw r3,156(r2) + 80212c4: e0bffe17 ldw r2,-8(fp) + 80212c8: 10802924 muli r2,r2,164 + 80212cc: 11000604 addi r4,r2,24 + 80212d0: 008201b4 movhi r2,2054 + 80212d4: 10b5c204 addi r2,r2,-10488 + 80212d8: 2085883a add r2,r4,r2 + 80212dc: 18800515 stw r2,20(r3) + ifp->n_mib->ifDescr = "Altera TSE MAC ethernet"; + 80212e0: e0bfff17 ldw r2,-4(fp) + 80212e4: 10c02717 ldw r3,156(r2) + 80212e8: 00820174 movhi r2,2053 + 80212ec: 10a5d504 addi r2,r2,-26796 + 80212f0: 18800115 stw r2,4(r3) + ifp->n_lnh = ETHHDR_SIZE; /* ethernet header size. was:14 */ + 80212f4: e0bfff17 ldw r2,-4(fp) + 80212f8: 00c00404 movi r3,16 + 80212fc: 10c00815 stw r3,32(r2) + ifp->n_hal = ALTERA_TSE_HAL_ADDR_LEN; /* hardware address length */ + 8021300: e0bfff17 ldw r2,-4(fp) + 8021304: 00c00184 movi r3,6 + 8021308: 10c01115 stw r3,68(r2) + ifp->n_mib->ifType = ETHERNET; /* device type */ + 802130c: e0bfff17 ldw r2,-4(fp) + 8021310: 10802717 ldw r2,156(r2) + 8021314: 00c00184 movi r3,6 + 8021318: 10c00215 stw r3,8(r2) + ifp->n_mtu = ALTERA_TSE_MAX_MTU_SIZE; /* max frame size */ + 802131c: e0bfff17 ldw r2,-4(fp) + 8021320: 00c17a84 movi r3,1514 + 8021324: 10c00915 stw r3,36(r2) + + /* install our hardware driver routines */ + ifp->n_init = tse_mac_init; + 8021328: e0ffff17 ldw r3,-4(fp) + 802132c: 008200b4 movhi r2,2050 + 8021330: 10853104 addi r2,r2,5316 + 8021334: 18800215 stw r2,8(r3) + ifp->pkt_send = NULL; + 8021338: e0bfff17 ldw r2,-4(fp) + 802133c: 10000415 stw zero,16(r2) + ifp->raw_send = tse_mac_raw_send; + 8021340: e0ffff17 ldw r3,-4(fp) + 8021344: 008200b4 movhi r2,2050 + 8021348: 10881204 addi r2,r2,8264 + 802134c: 18800315 stw r2,12(r3) + ifp->n_close = tse_mac_close; + 8021350: e0ffff17 ldw r3,-4(fp) + 8021354: 008200b4 movhi r2,2050 + 8021358: 108a6104 addi r2,r2,10628 + 802135c: 18800515 stw r2,20(r3) + ifp->n_stats = (void(*)(void *, int))tse_mac_stats; + 8021360: e0ffff17 ldw r3,-4(fp) + 8021364: 008200b4 movhi r2,2050 + 8021368: 108a5104 addi r2,r2,10564 + 802136c: 18800715 stw r2,28(r3) + + #ifdef IP_V6 + ifp->n_flags |= (NF_NBPROT | NF_IPV6); + #else + ifp->n_flags |= NF_NBPROT; + 8021370: e0bfff17 ldw r2,-4(fp) + 8021374: 10802a17 ldw r2,168(r2) + 8021378: 10c00214 ori r3,r2,8 + 802137c: e0bfff17 ldw r2,-4(fp) + 8021380: 10c02a15 stw r3,168(r2) + #endif + + nets[index]->n_mib->ifPhysAddress = (u_char*)tse[index].mac_addr; /* ptr to MAC address */ + 8021384: e0bffe17 ldw r2,-8(fp) + 8021388: 100690ba slli r3,r2,2 + 802138c: 008201b4 movhi r2,2054 + 8021390: 1885883a add r2,r3,r2 + 8021394: 10b77017 ldw r2,-8768(r2) + 8021398: 10c02717 ldw r3,156(r2) + 802139c: e0bffe17 ldw r2,-8(fp) + 80213a0: 10802924 muli r2,r2,164 + 80213a4: 11000604 addi r4,r2,24 + 80213a8: 008201b4 movhi r2,2054 + 80213ac: 10b5c204 addi r2,r2,-10488 + 80213b0: 2085883a add r2,r4,r2 + 80213b4: 18800515 stw r2,20(r3) + + #ifdef ALT_INICHE + /* get the MAC address. */ + get_mac_addr(ifp, (unsigned char *)tse[index].mac_addr); + 80213b8: e0bffe17 ldw r2,-8(fp) + 80213bc: 10802924 muli r2,r2,164 + 80213c0: 10c00604 addi r3,r2,24 + 80213c4: 008201b4 movhi r2,2054 + 80213c8: 10b5c204 addi r2,r2,-10488 + 80213cc: 1885883a add r2,r3,r2 + 80213d0: 100b883a mov r5,r2 + 80213d4: e13fff17 ldw r4,-4(fp) + 80213d8: 80011e80 call 80011e8 + #endif /* ALT_INICHE */ + + /* set cross-pointers between iface and tse structs */ + tse[index].index = index; + 80213dc: e0bffe17 ldw r2,-8(fp) + 80213e0: 11002924 muli r4,r2,164 + 80213e4: e0fffe17 ldw r3,-8(fp) + 80213e8: 008201b4 movhi r2,2054 + 80213ec: 2085883a add r2,r4,r2 + 80213f0: 10f5c215 stw r3,-10488(r2) + tse[index].netp = ifp; + 80213f4: e0bffe17 ldw r2,-8(fp) + 80213f8: 11002924 muli r4,r2,164 + 80213fc: e0ffff17 ldw r3,-4(fp) + 8021400: 008201b4 movhi r2,2054 + 8021404: 2085883a add r2,r4,r2 + 8021408: 10f5ca15 stw r3,-10456(r2) + ifp->n_local = (void*)(&tse[index]); + 802140c: e0bffe17 ldw r2,-8(fp) + 8021410: 10c02924 muli r3,r2,164 + 8021414: 008201b4 movhi r2,2054 + 8021418: 10b5c204 addi r2,r2,-10488 + 802141c: 1887883a add r3,r3,r2 + 8021420: e0bfff17 ldw r2,-4(fp) + 8021424: 10c02815 stw r3,160(r2) + + index++; + 8021428: e0bffe17 ldw r2,-8(fp) + 802142c: 10800044 addi r2,r2,1 + 8021430: e0bffe15 stw r2,-8(fp) + } + + return index; + 8021434: e0bffe17 ldw r2,-8(fp) +} + 8021438: e037883a mov sp,fp + 802143c: dfc00117 ldw ra,4(sp) + 8021440: df000017 ldw fp,0(sp) + 8021444: dec00204 addi sp,sp,8 + 8021448: f800283a ret + +0802144c : + +//temporary code for msgdma hw workaround +void msgdma_reset(alt_msgdma_dev * dev) +{ + 802144c: defffe04 addi sp,sp,-8 + 8021450: df000115 stw fp,4(sp) + 8021454: df000104 addi fp,sp,4 + 8021458: e13fff15 stw r4,-4(fp) + + /* start prefetcher reset sequence */ + IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, + 802145c: e0bfff17 ldw r2,-4(fp) + 8021460: 10800617 ldw r2,24(r2) + 8021464: 00c00104 movi r3,4 + 8021468: 10c00035 stwio r3,0(r2) + ALT_MSGDMA_PREFETCHER_CTRL_RESET_SET_MASK); + /* wait until hw clears the bit */ + while(ALT_MSGDMA_PREFETCHER_CTRL_RESET_GET( + 802146c: 0001883a nop + 8021470: e0bfff17 ldw r2,-4(fp) + 8021474: 10800617 ldw r2,24(r2) + 8021478: 10800037 ldwio r2,0(r2) + 802147c: 1080010c andi r2,r2,4 + 8021480: 103ffb1e bne r2,zero,8021470 + */ + + /* Reset the registers and FIFOs of the dispatcher and master modules */ + /* set the reset bit, no need to read the control register first since + this write is going to clear it out */ + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, ALTERA_MSGDMA_CSR_RESET_MASK); + 8021484: e0bfff17 ldw r2,-4(fp) + 8021488: 10800317 ldw r2,12(r2) + 802148c: 10800104 addi r2,r2,4 + 8021490: 00c00084 movi r3,2 + 8021494: 10c00035 stwio r3,0(r2) + while(0 != (IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base) + 8021498: 0001883a nop + 802149c: e0bfff17 ldw r2,-4(fp) + 80214a0: 10800317 ldw r2,12(r2) + 80214a4: 10800037 ldwio r2,0(r2) + & ALTERA_MSGDMA_CSR_RESET_STATE_MASK)); + 80214a8: 1080100c andi r2,r2,64 + while(0 != (IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base) + 80214ac: 103ffb1e bne r2,zero,802149c + +} + 80214b0: 0001883a nop + 80214b4: e037883a mov sp,fp + 80214b8: df000017 ldw fp,0(sp) + 80214bc: dec00104 addi sp,sp,4 + 80214c0: f800283a ret + +080214c4 : + * @API TYPE: Internal + * @Param iface index of the NET structure associated with TSE instance + * @Return 0 if ok, else -1 if error + */ +int tse_mac_init(int iface) +{ + 80214c4: defff104 addi sp,sp,-60 + 80214c8: dfc00e15 stw ra,56(sp) + 80214cc: df000d15 stw fp,52(sp) + 80214d0: df000d04 addi fp,sp,52 + 80214d4: e13ff415 stw r4,-48(fp) + int dat; + int speed, duplex, result, x; + int status = SUCCESS; + 80214d8: e03ffd15 stw zero,-12(fp) + + alt_msgdma_dev *msgdma_tx_dev; + alt_msgdma_dev *msgdma_rx_dev; + alt_tse_system_info* tse_hw = (alt_tse_system_info *) tse[iface].tse; + 80214dc: e0bff417 ldw r2,-48(fp) + 80214e0: 10c02924 muli r3,r2,164 + 80214e4: 008201b4 movhi r2,2054 + 80214e8: 1885883a add r2,r3,r2 + 80214ec: 10b5ea17 ldw r2,-10328(r2) + 80214f0: e0bffa15 stw r2,-24(fp) + + dprintf("tse_mac_init %d\n", iface); + 80214f4: e17ff417 ldw r5,-48(fp) + 80214f8: 01020174 movhi r4,2053 + 80214fc: 2125db04 addi r4,r4,-26772 + 8021500: 8002c780 call 8002c78 + + if (tse_hw->ext_desc_mem == 1) { + 8021504: e0bffa17 ldw r2,-24(fp) + 8021508: 10800883 ldbu r2,34(r2) + 802150c: 10803fcc andi r2,r2,255 + 8021510: 10800058 cmpnei r2,r2,1 + 8021514: 10001b1e bne r2,zero,8021584 + tse[iface].rxdesc[0] = (alt_msgdma_prefetcher_standard_descriptor *) tse_hw->desc_mem_base; + 8021518: e0bffa17 ldw r2,-24(fp) + 802151c: 10800917 ldw r2,36(r2) + 8021520: 1009883a mov r4,r2 + 8021524: e0bff417 ldw r2,-48(fp) + 8021528: 10c02924 muli r3,r2,164 + 802152c: 008201b4 movhi r2,2054 + 8021530: 1885883a add r2,r3,r2 + 8021534: 1135d315 stw r4,-10420(r2) + tse[iface].rxdesc[1] = (alt_msgdma_prefetcher_standard_descriptor *) + (tse_hw->desc_mem_base + ((1+ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE)*(sizeof(alt_msgdma_prefetcher_standard_descriptor)))); + 8021538: e0bffa17 ldw r2,-24(fp) + 802153c: 10800917 ldw r2,36(r2) + 8021540: 10805004 addi r2,r2,320 + tse[iface].rxdesc[1] = (alt_msgdma_prefetcher_standard_descriptor *) + 8021544: 1009883a mov r4,r2 + 8021548: e0bff417 ldw r2,-48(fp) + 802154c: 10c02924 muli r3,r2,164 + 8021550: 008201b4 movhi r2,2054 + 8021554: 1885883a add r2,r3,r2 + 8021558: 1135d415 stw r4,-10416(r2) + tse[iface].txdesc = (alt_msgdma_prefetcher_standard_descriptor *) + (tse_hw->desc_mem_base + ((1+ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE+1+ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE)*(sizeof(alt_msgdma_prefetcher_standard_descriptor)))); + 802155c: e0bffa17 ldw r2,-24(fp) + 8021560: 10800917 ldw r2,36(r2) + 8021564: 1080a004 addi r2,r2,640 + tse[iface].txdesc = (alt_msgdma_prefetcher_standard_descriptor *) + 8021568: 1009883a mov r4,r2 + 802156c: e0bff417 ldw r2,-48(fp) + 8021570: 10c02924 muli r3,r2,164 + 8021574: 008201b4 movhi r2,2054 + 8021578: 1885883a add r2,r3,r2 + 802157c: 1135d015 stw r4,-10432(r2) + 8021580: 00005106 br 80216c8 + } + else { + tse[iface].rxdesc[0] = (alt_msgdma_prefetcher_standard_descriptor *)alt_uncached_malloc((1+ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE)*(sizeof(alt_msgdma_prefetcher_standard_descriptor))); + 8021584: 01005004 movi r4,320 + 8021588: 80380a40 call 80380a4 + 802158c: 1009883a mov r4,r2 + 8021590: e0bff417 ldw r2,-48(fp) + 8021594: 10c02924 muli r3,r2,164 + 8021598: 008201b4 movhi r2,2054 + 802159c: 1885883a add r2,r3,r2 + 80215a0: 1135d315 stw r4,-10420(r2) + while ((((alt_u32)tse[iface].rxdesc[0]) % sizeof(alt_msgdma_prefetcher_standard_descriptor)) != 0) + 80215a4: 00000b06 br 80215d4 + tse[iface].rxdesc[0]++; //boundary + 80215a8: e0bff417 ldw r2,-48(fp) + 80215ac: 10c02924 muli r3,r2,164 + 80215b0: 008201b4 movhi r2,2054 + 80215b4: 1885883a add r2,r3,r2 + 80215b8: 10b5d317 ldw r2,-10420(r2) + 80215bc: 10c00804 addi r3,r2,32 + 80215c0: e0bff417 ldw r2,-48(fp) + 80215c4: 11002924 muli r4,r2,164 + 80215c8: 008201b4 movhi r2,2054 + 80215cc: 2085883a add r2,r4,r2 + 80215d0: 10f5d315 stw r3,-10420(r2) + while ((((alt_u32)tse[iface].rxdesc[0]) % sizeof(alt_msgdma_prefetcher_standard_descriptor)) != 0) + 80215d4: e0bff417 ldw r2,-48(fp) + 80215d8: 10c02924 muli r3,r2,164 + 80215dc: 008201b4 movhi r2,2054 + 80215e0: 1885883a add r2,r3,r2 + 80215e4: 10b5d317 ldw r2,-10420(r2) + 80215e8: 108007cc andi r2,r2,31 + 80215ec: 103fee1e bne r2,zero,80215a8 + + tse[iface].rxdesc[1] = (alt_msgdma_prefetcher_standard_descriptor *)alt_uncached_malloc((1+ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE)*(sizeof(alt_msgdma_prefetcher_standard_descriptor))); + 80215f0: 01005004 movi r4,320 + 80215f4: 80380a40 call 80380a4 + 80215f8: 1009883a mov r4,r2 + 80215fc: e0bff417 ldw r2,-48(fp) + 8021600: 10c02924 muli r3,r2,164 + 8021604: 008201b4 movhi r2,2054 + 8021608: 1885883a add r2,r3,r2 + 802160c: 1135d415 stw r4,-10416(r2) + while ((((alt_u32)tse[iface].rxdesc[1]) % sizeof(alt_msgdma_prefetcher_standard_descriptor)) != 0) + 8021610: 00000b06 br 8021640 + tse[iface].rxdesc[1]++; //boundary + 8021614: e0bff417 ldw r2,-48(fp) + 8021618: 10c02924 muli r3,r2,164 + 802161c: 008201b4 movhi r2,2054 + 8021620: 1885883a add r2,r3,r2 + 8021624: 10b5d417 ldw r2,-10416(r2) + 8021628: 10c00804 addi r3,r2,32 + 802162c: e0bff417 ldw r2,-48(fp) + 8021630: 11002924 muli r4,r2,164 + 8021634: 008201b4 movhi r2,2054 + 8021638: 2085883a add r2,r4,r2 + 802163c: 10f5d415 stw r3,-10416(r2) + while ((((alt_u32)tse[iface].rxdesc[1]) % sizeof(alt_msgdma_prefetcher_standard_descriptor)) != 0) + 8021640: e0bff417 ldw r2,-48(fp) + 8021644: 10c02924 muli r3,r2,164 + 8021648: 008201b4 movhi r2,2054 + 802164c: 1885883a add r2,r3,r2 + 8021650: 10b5d417 ldw r2,-10416(r2) + 8021654: 108007cc andi r2,r2,31 + 8021658: 103fee1e bne r2,zero,8021614 + + tse[iface].txdesc = (alt_msgdma_prefetcher_standard_descriptor *)alt_uncached_malloc((1+ALTERA_TSE_MSGDMA_TX_DESC_CHAIN_SIZE)*(sizeof(alt_msgdma_prefetcher_standard_descriptor))); + 802165c: 01001804 movi r4,96 + 8021660: 80380a40 call 80380a4 + 8021664: 1009883a mov r4,r2 + 8021668: e0bff417 ldw r2,-48(fp) + 802166c: 10c02924 muli r3,r2,164 + 8021670: 008201b4 movhi r2,2054 + 8021674: 1885883a add r2,r3,r2 + 8021678: 1135d015 stw r4,-10432(r2) + while ((((alt_u32)tse[iface].txdesc) % sizeof(alt_msgdma_prefetcher_standard_descriptor)) != 0) + 802167c: 00000b06 br 80216ac + tse[iface].txdesc++; //boundary + 8021680: e0bff417 ldw r2,-48(fp) + 8021684: 10c02924 muli r3,r2,164 + 8021688: 008201b4 movhi r2,2054 + 802168c: 1885883a add r2,r3,r2 + 8021690: 10b5d017 ldw r2,-10432(r2) + 8021694: 10c00804 addi r3,r2,32 + 8021698: e0bff417 ldw r2,-48(fp) + 802169c: 11002924 muli r4,r2,164 + 80216a0: 008201b4 movhi r2,2054 + 80216a4: 2085883a add r2,r4,r2 + 80216a8: 10f5d015 stw r3,-10432(r2) + while ((((alt_u32)tse[iface].txdesc) % sizeof(alt_msgdma_prefetcher_standard_descriptor)) != 0) + 80216ac: e0bff417 ldw r2,-48(fp) + 80216b0: 10c02924 muli r3,r2,164 + 80216b4: 008201b4 movhi r2,2054 + 80216b8: 1885883a add r2,r3,r2 + 80216bc: 10b5d017 ldw r2,-10432(r2) + 80216c0: 108007cc andi r2,r2,31 + 80216c4: 103fee1e bne r2,zero,8021680 + } + + /* Get the Rx and Tx MSGDMA addresses */ + msgdma_tx_dev = alt_msgdma_open(tse_hw->tse_msgdma_tx); + 80216c8: e0bffa17 ldw r2,-24(fp) + 80216cc: 10800617 ldw r2,24(r2) + 80216d0: 1009883a mov r4,r2 + 80216d4: 801fe940 call 801fe94 + 80216d8: e0bff915 stw r2,-28(fp) + + if(!msgdma_tx_dev) { + 80216dc: e0bff917 ldw r2,-28(fp) + 80216e0: 1000051e bne r2,zero,80216f8 + dprintf("[altera_eth_tse_init] Error opening TX MSGDMA\n"); + 80216e4: 01020174 movhi r4,2053 + 80216e8: 2125e004 addi r4,r4,-26752 + 80216ec: 8002d9c0 call 8002d9c + return ENP_RESOURCE; + 80216f0: 00bffa84 movi r2,-22 + 80216f4: 00020706 br 8021f14 + } + + msgdma_rx_dev = alt_msgdma_open(tse_hw->tse_msgdma_rx); + 80216f8: e0bffa17 ldw r2,-24(fp) + 80216fc: 10800717 ldw r2,28(r2) + 8021700: 1009883a mov r4,r2 + 8021704: 801fe940 call 801fe94 + 8021708: e0bff815 stw r2,-32(fp) + if(!msgdma_rx_dev) { + 802170c: e0bff817 ldw r2,-32(fp) + 8021710: 1000051e bne r2,zero,8021728 + dprintf("[altera_eth_tse_init] Error opening RX MSGDMA\n"); + 8021714: 01020174 movhi r4,2053 + 8021718: 2125ec04 addi r4,r4,-26704 + 802171c: 8002d9c0 call 8002d9c + return ENP_RESOURCE; + 8021720: 00bffa84 movi r2,-22 + 8021724: 0001fb06 br 8021f14 + } + + /* Initialize mtip_mac_trans_info structure with values from */ + tse_mac_initTransInfo2(&tse[iface].mi, (int)tse_hw->tse_mac_base, + 8021728: e0bff417 ldw r2,-48(fp) + 802172c: 10802924 muli r2,r2,164 + 8021730: 10c00104 addi r3,r2,4 + 8021734: 008201b4 movhi r2,2054 + 8021738: 10b5c204 addi r2,r2,-10488 + 802173c: 1887883a add r3,r3,r2 + 8021740: e0bffa17 ldw r2,-24(fp) + 8021744: 10800017 ldw r2,0(r2) + 8021748: e13ff917 ldw r4,-28(fp) + 802174c: e17ff817 ldw r5,-32(fp) + 8021750: d8000015 stw zero,0(sp) + 8021754: 280f883a mov r7,r5 + 8021758: 200d883a mov r6,r4 + 802175c: 100b883a mov r5,r2 + 8021760: 1809883a mov r4,r3 + 8021764: 8017b500 call 8017b50 + (unsigned int)msgdma_tx_dev, + (unsigned int)msgdma_rx_dev, + 0); + + /* reset the PHY if necessary */ + result = getPHYSpeed(tse[iface].mi.base); + 8021768: e0bff417 ldw r2,-48(fp) + 802176c: 10c02924 muli r3,r2,164 + 8021770: 008201b4 movhi r2,2054 + 8021774: 1885883a add r2,r3,r2 + 8021778: 10b5c317 ldw r2,-10484(r2) + 802177c: 1009883a mov r4,r2 + 8021780: 8018e540 call 8018e54 + 8021784: e0bff715 stw r2,-36(fp) + speed = (result >> 1) & 0x07; + 8021788: e0bff717 ldw r2,-36(fp) + 802178c: 1005d07a srai r2,r2,1 + 8021790: 108001cc andi r2,r2,7 + 8021794: e0bff615 stw r2,-40(fp) + duplex = result & 0x01; + 8021798: e0bff717 ldw r2,-36(fp) + 802179c: 1080004c andi r2,r2,1 + 80217a0: e0bff515 stw r2,-44(fp) + + /* reset the mac */ + IOWR_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base, + 80217a4: e0bff417 ldw r2,-48(fp) + 80217a8: 10c02924 muli r3,r2,164 + 80217ac: 008201b4 movhi r2,2054 + 80217b0: 1885883a add r2,r3,r2 + 80217b4: 10b5c317 ldw r2,-10484(r2) + 80217b8: 10800204 addi r2,r2,8 + 80217bc: 00c800c4 movi r3,8195 + 80217c0: 10c00035 stwio r3,0(r2) + mmac_cc_SW_RESET_mask | + mmac_cc_TX_ENA_mask | + mmac_cc_RX_ENA_mask); + + x=0; + 80217c4: e03ffe15 stw zero,-8(fp) + while(IORD_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base) & + 80217c8: 00000506 br 80217e0 + ALTERA_TSEMAC_CMD_SW_RESET_MSK) { + if( x++ > 10000 ) { + 80217cc: e0bffe17 ldw r2,-8(fp) + 80217d0: 10c00044 addi r3,r2,1 + 80217d4: e0fffe15 stw r3,-8(fp) + 80217d8: 1089c450 cmplti r2,r2,10001 + 80217dc: 10000a26 beq r2,zero,8021808 + while(IORD_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base) & + 80217e0: e0bff417 ldw r2,-48(fp) + 80217e4: 10c02924 muli r3,r2,164 + 80217e8: 008201b4 movhi r2,2054 + 80217ec: 1885883a add r2,r3,r2 + 80217f0: 10b5c317 ldw r2,-10484(r2) + 80217f4: 10800204 addi r2,r2,8 + 80217f8: 10800037 ldwio r2,0(r2) + 80217fc: 1088000c andi r2,r2,8192 + 8021800: 103ff21e bne r2,zero,80217cc + 8021804: 00000106 br 802180c + break; + 8021808: 0001883a nop + } + } + if(x >= 10000) { + 802180c: e0bffe17 ldw r2,-8(fp) + 8021810: 1089c410 cmplti r2,r2,10000 + 8021814: 1000031e bne r2,zero,8021824 + dprintf("TSEMAC SW reset bit never cleared!\n"); + 8021818: 01020174 movhi r4,2053 + 802181c: 2125f804 addi r4,r4,-26656 + 8021820: 8002d9c0 call 8002d9c + } + + dat = IORD_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base); + 8021824: e0bff417 ldw r2,-48(fp) + 8021828: 10c02924 muli r3,r2,164 + 802182c: 008201b4 movhi r2,2054 + 8021830: 1885883a add r2,r3,r2 + 8021834: 10b5c317 ldw r2,-10484(r2) + 8021838: 10800204 addi r2,r2,8 + 802183c: 10800037 ldwio r2,0(r2) + 8021840: e0bfff15 stw r2,-4(fp) + if( (dat & 0x03) != 0 ) { + 8021844: e0bfff17 ldw r2,-4(fp) + 8021848: 108000cc andi r2,r2,3 + 802184c: 10000526 beq r2,zero,8021864 + dprintf("WARN: RX/TX not disabled after reset... missing PHY clock? CMD_CONFIG=0x%08x\n", dat); + 8021850: e17fff17 ldw r5,-4(fp) + 8021854: 01020174 movhi r4,2053 + 8021858: 21260104 addi r4,r4,-26620 + 802185c: 8002c780 call 8002c78 + 8021860: 00000506 br 8021878 + } + else { + dprintf("OK, x=%d, CMD_CONFIG=0x%08x\n", x, dat); + 8021864: e1bfff17 ldw r6,-4(fp) + 8021868: e17ffe17 ldw r5,-8(fp) + 802186c: 01020174 movhi r4,2053 + 8021870: 21261504 addi r4,r4,-26540 + 8021874: 8002c780 call 8002c78 + + /* Hack code to determine the Channel number <- Someone please fix this ugly code in the future */ + extern alt_u8 mac_group_count; + extern alt_tse_mac_group *pmac_groups[TSE_MAX_MAC_IN_SYSTEM]; + + if(tse_hw->use_shared_fifo == 1) { + 8021878: e0bffa17 ldw r2,-24(fp) + 802187c: 10800a03 ldbu r2,40(r2) + 8021880: 10803fcc andi r2,r2,255 + 8021884: 10800058 cmpnei r2,r2,1 + 8021888: 10002c1e bne r2,zero,802193c + int channel_loop = 0; + 802188c: e03ffc15 stw zero,-16(fp) + int mac_loop = 0; + 8021890: e03ffb15 stw zero,-20(fp) + + for (channel_loop = 0; channel_loop < mac_group_count; channel_loop ++) { + 8021894: e03ffc15 stw zero,-16(fp) + 8021898: 00002406 br 802192c + for (mac_loop = 0; mac_loop < pmac_groups[channel_loop]->channel; mac_loop ++) { + 802189c: e03ffb15 stw zero,-20(fp) + 80218a0: 00001606 br 80218fc + if (pmac_groups[channel_loop]->pmac_info[mac_loop]->psys_info == tse_hw) { + 80218a4: e0bffc17 ldw r2,-16(fp) + 80218a8: 100690ba slli r3,r2,2 + 80218ac: 008201b4 movhi r2,2054 + 80218b0: 1885883a add r2,r3,r2 + 80218b4: 10f5aa17 ldw r3,-10584(r2) + 80218b8: e0bffb17 ldw r2,-20(fp) + 80218bc: 10800044 addi r2,r2,1 + 80218c0: 100490ba slli r2,r2,2 + 80218c4: 1885883a add r2,r3,r2 + 80218c8: 10800017 ldw r2,0(r2) + 80218cc: 10800217 ldw r2,8(r2) + 80218d0: e0fffa17 ldw r3,-24(fp) + 80218d4: 1880061e bne r3,r2,80218f0 + tse[iface].channel = mac_loop; + 80218d8: e0bff417 ldw r2,-48(fp) + 80218dc: 11002924 muli r4,r2,164 + 80218e0: e0fffb17 ldw r3,-20(fp) + 80218e4: 008201b4 movhi r2,2054 + 80218e8: 2085883a add r2,r4,r2 + 80218ec: 10f5ce15 stw r3,-10440(r2) + for (mac_loop = 0; mac_loop < pmac_groups[channel_loop]->channel; mac_loop ++) { + 80218f0: e0bffb17 ldw r2,-20(fp) + 80218f4: 10800044 addi r2,r2,1 + 80218f8: e0bffb15 stw r2,-20(fp) + 80218fc: e0bffc17 ldw r2,-16(fp) + 8021900: 100690ba slli r3,r2,2 + 8021904: 008201b4 movhi r2,2054 + 8021908: 1885883a add r2,r3,r2 + 802190c: 10b5aa17 ldw r2,-10584(r2) + 8021910: 10800003 ldbu r2,0(r2) + 8021914: 10803fcc andi r2,r2,255 + 8021918: e0fffb17 ldw r3,-20(fp) + 802191c: 18bfe116 blt r3,r2,80218a4 + for (channel_loop = 0; channel_loop < mac_group_count; channel_loop ++) { + 8021920: e0bffc17 ldw r2,-16(fp) + 8021924: 10800044 addi r2,r2,1 + 8021928: e0bffc15 stw r2,-16(fp) + 802192c: d0a05b43 ldbu r2,-32403(gp) + 8021930: 10803fcc andi r2,r2,255 + 8021934: e0fffc17 ldw r3,-16(fp) + 8021938: 18bfd816 blt r3,r2,802189c + } + } + } + /* End of Hack code */ + + if(tse_hw->use_shared_fifo == 1) { + 802193c: e0bffa17 ldw r2,-24(fp) + 8021940: 10800a03 ldbu r2,40(r2) + 8021944: 10803fcc andi r2,r2,255 + 8021948: 10800058 cmpnei r2,r2,1 + 802194c: 10000f1e bne r2,zero,802198c + IOWR_ALTERA_MULTI_CHAN_FIFO_SEC_FULL_THRESHOLD(tse_hw->tse_shared_fifo_rx_ctrl_base,tse_hw->tse_shared_fifo_rx_depth); + 8021950: e0bffa17 ldw r2,-24(fp) + 8021954: 10800e17 ldw r2,56(r2) + 8021958: 1007883a mov r3,r2 + 802195c: e0bffa17 ldw r2,-24(fp) + 8021960: 10801017 ldw r2,64(r2) + 8021964: 18800035 stwio r2,0(r3) + IOWR_ALTERA_MULTI_CHAN_FIFO_ALMOST_FULL_THRESHOLD(tse_hw->tse_shared_fifo_rx_ctrl_base,((tse_hw->tse_shared_fifo_rx_depth) - 140)); + 8021968: e0bffa17 ldw r2,-24(fp) + 802196c: 10800e17 ldw r2,56(r2) + 8021970: 10800204 addi r2,r2,8 + 8021974: 1007883a mov r3,r2 + 8021978: e0bffa17 ldw r2,-24(fp) + 802197c: 10801017 ldw r2,64(r2) + 8021980: 10bfdd04 addi r2,r2,-140 + 8021984: 18800035 stwio r2,0(r3) + 8021988: 00004c06 br 8021abc + } + else { + /* Initialize MAC registers */ + IOWR_ALTERA_TSEMAC_FRM_LENGTH(tse[iface].mi.base, ALTERA_TSE_MAC_MAX_FRAME_LENGTH); + 802198c: e0bff417 ldw r2,-48(fp) + 8021990: 10c02924 muli r3,r2,164 + 8021994: 008201b4 movhi r2,2054 + 8021998: 1885883a add r2,r3,r2 + 802199c: 10b5c317 ldw r2,-10484(r2) + 80219a0: 10800504 addi r2,r2,20 + 80219a4: 00c17b84 movi r3,1518 + 80219a8: 10c00035 stwio r3,0(r2) + IOWR_ALTERA_TSEMAC_RX_ALMOST_EMPTY(tse[iface].mi.base, 8); + 80219ac: e0bff417 ldw r2,-48(fp) + 80219b0: 10c02924 muli r3,r2,164 + 80219b4: 008201b4 movhi r2,2054 + 80219b8: 1885883a add r2,r3,r2 + 80219bc: 10b5c317 ldw r2,-10484(r2) + 80219c0: 10800b04 addi r2,r2,44 + 80219c4: 00c00204 movi r3,8 + 80219c8: 10c00035 stwio r3,0(r2) + IOWR_ALTERA_TSEMAC_RX_ALMOST_FULL(tse[iface].mi.base, 8); + 80219cc: e0bff417 ldw r2,-48(fp) + 80219d0: 10c02924 muli r3,r2,164 + 80219d4: 008201b4 movhi r2,2054 + 80219d8: 1885883a add r2,r3,r2 + 80219dc: 10b5c317 ldw r2,-10484(r2) + 80219e0: 10800c04 addi r2,r2,48 + 80219e4: 00c00204 movi r3,8 + 80219e8: 10c00035 stwio r3,0(r2) + IOWR_ALTERA_TSEMAC_TX_ALMOST_EMPTY(tse[iface].mi.base, 8); + 80219ec: e0bff417 ldw r2,-48(fp) + 80219f0: 10c02924 muli r3,r2,164 + 80219f4: 008201b4 movhi r2,2054 + 80219f8: 1885883a add r2,r3,r2 + 80219fc: 10b5c317 ldw r2,-10484(r2) + 8021a00: 10800d04 addi r2,r2,52 + 8021a04: 00c00204 movi r3,8 + 8021a08: 10c00035 stwio r3,0(r2) + IOWR_ALTERA_TSEMAC_TX_ALMOST_FULL(tse[iface].mi.base, 3); + 8021a0c: e0bff417 ldw r2,-48(fp) + 8021a10: 10c02924 muli r3,r2,164 + 8021a14: 008201b4 movhi r2,2054 + 8021a18: 1885883a add r2,r3,r2 + 8021a1c: 10b5c317 ldw r2,-10484(r2) + 8021a20: 10800e04 addi r2,r2,56 + 8021a24: 00c000c4 movi r3,3 + 8021a28: 10c00035 stwio r3,0(r2) + IOWR_ALTERA_TSEMAC_TX_SECTION_EMPTY(tse[iface].mi.base, tse_hw->tse_tx_depth - 16); //1024/4; + 8021a2c: e0bff417 ldw r2,-48(fp) + 8021a30: 10c02924 muli r3,r2,164 + 8021a34: 008201b4 movhi r2,2054 + 8021a38: 1885883a add r2,r3,r2 + 8021a3c: 10b5c317 ldw r2,-10484(r2) + 8021a40: 10800904 addi r2,r2,36 + 8021a44: e0fffa17 ldw r3,-24(fp) + 8021a48: 18c00117 ldw r3,4(r3) + 8021a4c: 18fffc04 addi r3,r3,-16 + 8021a50: 10c00035 stwio r3,0(r2) + IOWR_ALTERA_TSEMAC_TX_SECTION_FULL(tse[iface].mi.base, 0); //32/4; // start transmit when there are 48 bytes + 8021a54: e0bff417 ldw r2,-48(fp) + 8021a58: 10c02924 muli r3,r2,164 + 8021a5c: 008201b4 movhi r2,2054 + 8021a60: 1885883a add r2,r3,r2 + 8021a64: 10b5c317 ldw r2,-10484(r2) + 8021a68: 10800a04 addi r2,r2,40 + 8021a6c: 0007883a mov r3,zero + 8021a70: 10c00035 stwio r3,0(r2) + IOWR_ALTERA_TSEMAC_RX_SECTION_EMPTY(tse[iface].mi.base, tse_hw->tse_rx_depth - 16); //4000/4); + 8021a74: e0bff417 ldw r2,-48(fp) + 8021a78: 10c02924 muli r3,r2,164 + 8021a7c: 008201b4 movhi r2,2054 + 8021a80: 1885883a add r2,r3,r2 + 8021a84: 10b5c317 ldw r2,-10484(r2) + 8021a88: 10800704 addi r2,r2,28 + 8021a8c: e0fffa17 ldw r3,-24(fp) + 8021a90: 18c00217 ldw r3,8(r3) + 8021a94: 18fffc04 addi r3,r3,-16 + 8021a98: 10c00035 stwio r3,0(r2) + IOWR_ALTERA_TSEMAC_RX_SECTION_FULL(tse[iface].mi.base, 0); + 8021a9c: e0bff417 ldw r2,-48(fp) + 8021aa0: 10c02924 muli r3,r2,164 + 8021aa4: 008201b4 movhi r2,2054 + 8021aa8: 1885883a add r2,r3,r2 + 8021aac: 10b5c317 ldw r2,-10484(r2) + 8021ab0: 10800804 addi r2,r2,32 + 8021ab4: 0007883a mov r3,zero + 8021ab8: 10c00035 stwio r3,0(r2) + tse[iface].rxShift16OK = 0; + } + } /* if(ETHHDR_BIAS == 0) */ + + if(ETHHDR_BIAS == 2) { + IOWR_ALTERA_TSEMAC_TX_CMD_STAT(tse[iface].mi.base,ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_MSK); + 8021abc: e0bff417 ldw r2,-48(fp) + 8021ac0: 10c02924 muli r3,r2,164 + 8021ac4: 008201b4 movhi r2,2054 + 8021ac8: 1885883a add r2,r3,r2 + 8021acc: 10b5c317 ldw r2,-10484(r2) + 8021ad0: 10803a04 addi r2,r2,232 + 8021ad4: 00c00134 movhi r3,4 + 8021ad8: 10c00035 stwio r3,0(r2) + + /* + * check if the MAC supports the 16-bit shift option allowing us + * to send BIASed frames without copying. Used by the send function later. + */ + if(IORD_ALTERA_TSEMAC_TX_CMD_STAT(tse[iface].mi.base) & + 8021adc: e0bff417 ldw r2,-48(fp) + 8021ae0: 10c02924 muli r3,r2,164 + 8021ae4: 008201b4 movhi r2,2054 + 8021ae8: 1885883a add r2,r3,r2 + 8021aec: 10b5c317 ldw r2,-10484(r2) + 8021af0: 10803a04 addi r2,r2,232 + 8021af4: 10800037 ldwio r2,0(r2) + 8021af8: 1080012c andhi r2,r2,4 + 8021afc: 10001826 beq r2,zero,8021b60 + ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_MSK) { + tse[iface].txShift16OK = 1; + 8021b00: e0bff417 ldw r2,-48(fp) + 8021b04: 11002924 muli r4,r2,164 + 8021b08: 00c00044 movi r3,1 + 8021b0c: 008201b4 movhi r2,2054 + 8021b10: 2085883a add r2,r4,r2 + 8021b14: 10f5cb15 stw r3,-10452(r2) + dprintf("[tse_mac_init] Error: Incompatible %d value with TX_CMD_STAT register return TxShift16 value. \n",ETHHDR_BIAS); + return ENP_LOGIC; + } + + /* Enable RX shift 16 for alignment of all received frames on 16-bit start address */ + IOWR_ALTERA_TSEMAC_RX_CMD_STAT(tse[iface].mi.base,ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_MSK); + 8021b18: e0bff417 ldw r2,-48(fp) + 8021b1c: 10c02924 muli r3,r2,164 + 8021b20: 008201b4 movhi r2,2054 + 8021b24: 1885883a add r2,r3,r2 + 8021b28: 10b5c317 ldw r2,-10484(r2) + 8021b2c: 10803b04 addi r2,r2,236 + 8021b30: 00c08034 movhi r3,512 + 8021b34: 10c00035 stwio r3,0(r2) + + /* check if the MAC supports the 16-bit shift option at the RX CMD STATUS Register */ + if(IORD_ALTERA_TSEMAC_RX_CMD_STAT(tse[iface].mi.base) & ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_MSK) + 8021b38: e0bff417 ldw r2,-48(fp) + 8021b3c: 10c02924 muli r3,r2,164 + 8021b40: 008201b4 movhi r2,2054 + 8021b44: 1885883a add r2,r3,r2 + 8021b48: 10b5c317 ldw r2,-10484(r2) + 8021b4c: 10803b04 addi r2,r2,236 + 8021b50: 10800037 ldwio r2,0(r2) + 8021b54: 1080802c andhi r2,r2,512 + 8021b58: 10001926 beq r2,zero,8021bc0 + 8021b5c: 00000b06 br 8021b8c + tse[iface].txShift16OK = 0; + 8021b60: e0bff417 ldw r2,-48(fp) + 8021b64: 10c02924 muli r3,r2,164 + 8021b68: 008201b4 movhi r2,2054 + 8021b6c: 1885883a add r2,r3,r2 + 8021b70: 1035cb15 stw zero,-10452(r2) + dprintf("[tse_mac_init] Error: Incompatible %d value with TX_CMD_STAT register return TxShift16 value. \n",ETHHDR_BIAS); + 8021b74: 01400084 movi r5,2 + 8021b78: 01020174 movhi r4,2053 + 8021b7c: 21261d04 addi r4,r4,-26508 + 8021b80: 8002c780 call 8002c78 + return ENP_LOGIC; + 8021b84: 00bffd44 movi r2,-11 + 8021b88: 0000e206 br 8021f14 + { + tse[iface].rxShift16OK = 1; + 8021b8c: e0bff417 ldw r2,-48(fp) + 8021b90: 11002924 muli r4,r2,164 + 8021b94: 00c00044 movi r3,1 + 8021b98: 008201b4 movhi r2,2054 + 8021b9c: 2085883a add r2,r4,r2 + 8021ba0: 10f5cc15 stw r3,-10448(r2) + return ENP_LOGIC; + } + } /* if(ETHHDR_BIAS == 2) */ + + /* enable MAC */ + dat = ALTERA_TSEMAC_CMD_TX_ENA_MSK | + 8021ba4: 00810034 movhi r2,1024 + 8021ba8: 108080c4 addi r2,r2,515 + 8021bac: e0bfff15 stw r2,-4(fp) + ALTERA_TSEMAC_CMD_TX_ADDR_INS_MSK | + ALTERA_TSEMAC_CMD_RX_ERR_DISC_MSK; /* automatically discard frames with CRC errors */ + + + /* 1000 Mbps */ + if(speed == 0x01) { + 8021bb0: e0bff617 ldw r2,-40(fp) + 8021bb4: 10800058 cmpnei r2,r2,1 + 8021bb8: 1000151e bne r2,zero,8021c10 + 8021bbc: 00000b06 br 8021bec + tse[iface].rxShift16OK = 0; + 8021bc0: e0bff417 ldw r2,-48(fp) + 8021bc4: 10c02924 muli r3,r2,164 + 8021bc8: 008201b4 movhi r2,2054 + 8021bcc: 1885883a add r2,r3,r2 + 8021bd0: 1035cc15 stw zero,-10448(r2) + dprintf("[tse_mac_init] Error: Incompatible %d value with RX_CMD_STAT register return RxShift16 value. \n",ETHHDR_BIAS); + 8021bd4: 01400084 movi r5,2 + 8021bd8: 01020174 movhi r4,2053 + 8021bdc: 21263504 addi r4,r4,-26412 + 8021be0: 8002c780 call 8002c78 + return ENP_LOGIC; + 8021be4: 00bffd44 movi r2,-11 + 8021be8: 0000ca06 br 8021f14 + dat |= ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; + 8021bec: e0bfff17 ldw r2,-4(fp) + 8021bf0: 10800214 ori r2,r2,8 + 8021bf4: e0bfff15 stw r2,-4(fp) + dat &= ~ALTERA_TSEMAC_CMD_ENA_10_MSK; + 8021bf8: e0ffff17 ldw r3,-4(fp) + 8021bfc: 00bf8034 movhi r2,65024 + 8021c00: 10bfffc4 addi r2,r2,-1 + 8021c04: 1884703a and r2,r3,r2 + 8021c08: e0bfff15 stw r2,-4(fp) + 8021c0c: 00002106 br 8021c94 + } + /* 100 Mbps */ + else if(speed == 0x02) { + 8021c10: e0bff617 ldw r2,-40(fp) + 8021c14: 10800098 cmpnei r2,r2,2 + 8021c18: 10000a1e bne r2,zero,8021c44 + dat &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; + 8021c1c: e0ffff17 ldw r3,-4(fp) + 8021c20: 00bffdc4 movi r2,-9 + 8021c24: 1884703a and r2,r3,r2 + 8021c28: e0bfff15 stw r2,-4(fp) + dat &= ~ALTERA_TSEMAC_CMD_ENA_10_MSK; + 8021c2c: e0ffff17 ldw r3,-4(fp) + 8021c30: 00bf8034 movhi r2,65024 + 8021c34: 10bfffc4 addi r2,r2,-1 + 8021c38: 1884703a and r2,r3,r2 + 8021c3c: e0bfff15 stw r2,-4(fp) + 8021c40: 00001406 br 8021c94 + } + /* 10 Mbps */ + else if(speed == 0x04) { + 8021c44: e0bff617 ldw r2,-40(fp) + 8021c48: 10800118 cmpnei r2,r2,4 + 8021c4c: 1000081e bne r2,zero,8021c70 + dat &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; + 8021c50: e0ffff17 ldw r3,-4(fp) + 8021c54: 00bffdc4 movi r2,-9 + 8021c58: 1884703a and r2,r3,r2 + 8021c5c: e0bfff15 stw r2,-4(fp) + dat |= ALTERA_TSEMAC_CMD_ENA_10_MSK; + 8021c60: e0bfff17 ldw r2,-4(fp) + 8021c64: 10808034 orhi r2,r2,512 + 8021c68: e0bfff15 stw r2,-4(fp) + 8021c6c: 00000906 br 8021c94 + } + /* default to 100 Mbps if returned invalid speed */ + else { + dat &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; + 8021c70: e0ffff17 ldw r3,-4(fp) + 8021c74: 00bffdc4 movi r2,-9 + 8021c78: 1884703a and r2,r3,r2 + 8021c7c: e0bfff15 stw r2,-4(fp) + dat &= ~ALTERA_TSEMAC_CMD_ENA_10_MSK; + 8021c80: e0ffff17 ldw r3,-4(fp) + 8021c84: 00bf8034 movhi r2,65024 + 8021c88: 10bfffc4 addi r2,r2,-1 + 8021c8c: 1884703a and r2,r3,r2 + 8021c90: e0bfff15 stw r2,-4(fp) + } + + /* Half Duplex */ + if(duplex == TSE_PHY_DUPLEX_HALF) { + 8021c94: e0bff517 ldw r2,-44(fp) + 8021c98: 1000041e bne r2,zero,8021cac + dat |= ALTERA_TSEMAC_CMD_HD_ENA_MSK; + 8021c9c: e0bfff17 ldw r2,-4(fp) + 8021ca0: 10810014 ori r2,r2,1024 + 8021ca4: e0bfff15 stw r2,-4(fp) + 8021ca8: 00000406 br 8021cbc + } + /* Full Duplex */ + else { + dat &= ~ALTERA_TSEMAC_CMD_HD_ENA_MSK; + 8021cac: e0ffff17 ldw r3,-4(fp) + 8021cb0: 00beffc4 movi r2,-1025 + 8021cb4: 1884703a and r2,r3,r2 + 8021cb8: e0bfff15 stw r2,-4(fp) + } + + IOWR_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base, dat); + 8021cbc: e0bff417 ldw r2,-48(fp) + 8021cc0: 10c02924 muli r3,r2,164 + 8021cc4: 008201b4 movhi r2,2054 + 8021cc8: 1885883a add r2,r3,r2 + 8021ccc: 10b5c317 ldw r2,-10484(r2) + 8021cd0: 10800204 addi r2,r2,8 + 8021cd4: e0ffff17 ldw r3,-4(fp) + 8021cd8: 10c00035 stwio r3,0(r2) + dprintf("\nMAC post-initialization: CMD_CONFIG=0x%08x\n", + IORD_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base)); + 8021cdc: e0bff417 ldw r2,-48(fp) + 8021ce0: 10c02924 muli r3,r2,164 + 8021ce4: 008201b4 movhi r2,2054 + 8021ce8: 1885883a add r2,r3,r2 + 8021cec: 10b5c317 ldw r2,-10484(r2) + dprintf("\nMAC post-initialization: CMD_CONFIG=0x%08x\n", + 8021cf0: 10800204 addi r2,r2,8 + 8021cf4: 10800037 ldwio r2,0(r2) + 8021cf8: 100b883a mov r5,r2 + 8021cfc: 01020174 movhi r4,2053 + 8021d00: 21264d04 addi r4,r4,-26316 + 8021d04: 8002c780 call 8002c78 + + +#ifdef ALT_INICHE + /* Set the MAC address */ + IOWR_ALTERA_TSEMAC_MAC_0(tse[iface].mi.base, + 8021d08: e0bff417 ldw r2,-48(fp) + 8021d0c: 10c02924 muli r3,r2,164 + 8021d10: 008201b4 movhi r2,2054 + 8021d14: 1885883a add r2,r3,r2 + 8021d18: 10b5c317 ldw r2,-10484(r2) + 8021d1c: 10c00304 addi r3,r2,12 + 8021d20: e0bff417 ldw r2,-48(fp) + 8021d24: 11002924 muli r4,r2,164 + 8021d28: 008201b4 movhi r2,2054 + 8021d2c: 2085883a add r2,r4,r2 + 8021d30: 10b5c803 ldbu r2,-10464(r2) + 8021d34: 11003fcc andi r4,r2,255 + 8021d38: e0bff417 ldw r2,-48(fp) + 8021d3c: 11402924 muli r5,r2,164 + 8021d40: 008201b4 movhi r2,2054 + 8021d44: 2885883a add r2,r5,r2 + 8021d48: 10b5c843 ldbu r2,-10463(r2) + 8021d4c: 10803fcc andi r2,r2,255 + 8021d50: 1004923a slli r2,r2,8 + 8021d54: 2088b03a or r4,r4,r2 + 8021d58: e0bff417 ldw r2,-48(fp) + 8021d5c: 11402924 muli r5,r2,164 + 8021d60: 008201b4 movhi r2,2054 + 8021d64: 2885883a add r2,r5,r2 + 8021d68: 10b5c883 ldbu r2,-10462(r2) + 8021d6c: 10803fcc andi r2,r2,255 + 8021d70: 1004943a slli r2,r2,16 + 8021d74: 2088b03a or r4,r4,r2 + 8021d78: e0bff417 ldw r2,-48(fp) + 8021d7c: 11402924 muli r5,r2,164 + 8021d80: 008201b4 movhi r2,2054 + 8021d84: 2885883a add r2,r5,r2 + 8021d88: 10b5c8c3 ldbu r2,-10461(r2) + 8021d8c: 10803fcc andi r2,r2,255 + 8021d90: 1004963a slli r2,r2,24 + 8021d94: 2084b03a or r2,r4,r2 + 8021d98: 18800035 stwio r2,0(r3) + ((int)((unsigned char) tse[iface].mac_addr[0]) | + (int)((unsigned char) tse[iface].mac_addr[1] << 8) | + (int)((unsigned char) tse[iface].mac_addr[2] << 16) | + (int)((unsigned char) tse[iface].mac_addr[3] << 24))); + + IOWR_ALTERA_TSEMAC_MAC_1(tse[iface].mi.base, + 8021d9c: e0bff417 ldw r2,-48(fp) + 8021da0: 10c02924 muli r3,r2,164 + 8021da4: 008201b4 movhi r2,2054 + 8021da8: 1885883a add r2,r3,r2 + 8021dac: 10b5c317 ldw r2,-10484(r2) + 8021db0: 10c00404 addi r3,r2,16 + 8021db4: e0bff417 ldw r2,-48(fp) + 8021db8: 11002924 muli r4,r2,164 + 8021dbc: 008201b4 movhi r2,2054 + 8021dc0: 2085883a add r2,r4,r2 + 8021dc4: 10b5c903 ldbu r2,-10460(r2) + 8021dc8: 11003fcc andi r4,r2,255 + 8021dcc: e0bff417 ldw r2,-48(fp) + 8021dd0: 11402924 muli r5,r2,164 + 8021dd4: 008201b4 movhi r2,2054 + 8021dd8: 2885883a add r2,r5,r2 + 8021ddc: 10b5c943 ldbu r2,-10459(r2) + 8021de0: 10803fcc andi r2,r2,255 + 8021de4: 1004923a slli r2,r2,8 + 8021de8: 2084b03a or r2,r4,r2 + 8021dec: 10bfffcc andi r2,r2,65535 + 8021df0: 18800035 stwio r2,0(r3) + tse[iface].mac_addr[5] = 0xBA; + +#endif /* not ALT_INICHE */ + + /* status = UP */ + nets[iface]->n_mib->ifAdminStatus = ALTERA_TSE_ADMIN_STATUS_UP; + 8021df4: e0bff417 ldw r2,-48(fp) + 8021df8: 100690ba slli r3,r2,2 + 8021dfc: 008201b4 movhi r2,2054 + 8021e00: 1885883a add r2,r3,r2 + 8021e04: 10b77017 ldw r2,-8768(r2) + 8021e08: 10802717 ldw r2,156(r2) + 8021e0c: 00c00044 movi r3,1 + 8021e10: 10c00615 stw r3,24(r2) + nets[iface]->n_mib->ifOperStatus = ALTERA_TSE_ADMIN_STATUS_UP; + 8021e14: e0bff417 ldw r2,-48(fp) + 8021e18: 100690ba slli r3,r2,2 + 8021e1c: 008201b4 movhi r2,2054 + 8021e20: 1885883a add r2,r3,r2 + 8021e24: 10b77017 ldw r2,-8768(r2) + 8021e28: 10802717 ldw r2,156(r2) + 8021e2c: 00c00044 movi r3,1 + 8021e30: 10c00715 stw r3,28(r2) + + /* Install MSGDMA (RX) interrupt handler */ + alt_msgdma_register_callback( + 8021e34: e0bff417 ldw r2,-48(fp) + 8021e38: 10c02924 muli r3,r2,164 + 8021e3c: 008201b4 movhi r2,2054 + 8021e40: 1885883a add r2,r3,r2 + 8021e44: 1135c517 ldw r4,-10476(r2) + tse[iface].mi.rx_msgdma, + (alt_msgdma_callback)&tse_msgdmaRx_isr, + 0, + (void*)(&tse[iface])); + 8021e48: e0bff417 ldw r2,-48(fp) + 8021e4c: 10c02924 muli r3,r2,164 + 8021e50: 008201b4 movhi r2,2054 + 8021e54: 10b5c204 addi r2,r2,-10488 + 8021e58: 1885883a add r2,r3,r2 + alt_msgdma_register_callback( + 8021e5c: 100f883a mov r7,r2 + 8021e60: 000d883a mov r6,zero + 8021e64: 014200b4 movhi r5,2050 + 8021e68: 29488404 addi r5,r5,8720 + 8021e6c: 80200940 call 8020094 + + /* Install MSGDMA (TX) interrupt handler */ + alt_msgdma_register_callback( + 8021e70: e0bff417 ldw r2,-48(fp) + 8021e74: 10c02924 muli r3,r2,164 + 8021e78: 008201b4 movhi r2,2054 + 8021e7c: 1885883a add r2,r3,r2 + 8021e80: 1135c417 ldw r4,-10480(r2) + tse[iface].mi.tx_msgdma, + (alt_msgdma_callback)&tse_msgdmaTx_isr, + 0, + (void*)(&tse[iface])); + 8021e84: e0bff417 ldw r2,-48(fp) + 8021e88: 10c02924 muli r3,r2,164 + 8021e8c: 008201b4 movhi r2,2054 + 8021e90: 10b5c204 addi r2,r2,-10488 + 8021e94: 1885883a add r2,r3,r2 + alt_msgdma_register_callback( + 8021e98: 100f883a mov r7,r2 + 8021e9c: 000d883a mov r6,zero + 8021ea0: 014200b4 movhi r5,2050 + 8021ea4: 2948ea04 addi r5,r5,9128 + 8021ea8: 80200940 call 8020094 + + status = tse_msgdma_read_init(&tse[iface]); + 8021eac: e0bff417 ldw r2,-48(fp) + 8021eb0: 10c02924 muli r3,r2,164 + 8021eb4: 008201b4 movhi r2,2054 + 8021eb8: 10b5c204 addi r2,r2,-10488 + 8021ebc: 1885883a add r2,r3,r2 + 8021ec0: 1009883a mov r4,r2 + 8021ec4: 80224080 call 8022408 + 8021ec8: e0bffd15 stw r2,-12(fp) + if (status == 0 ) status = tse_msgdma_write_init(&tse[iface],0,0); + 8021ecc: e0bffd17 ldw r2,-12(fp) + 8021ed0: 10000a1e bne r2,zero,8021efc + 8021ed4: e0bff417 ldw r2,-48(fp) + 8021ed8: 10c02924 muli r3,r2,164 + 8021edc: 008201b4 movhi r2,2054 + 8021ee0: 10b5c204 addi r2,r2,-10488 + 8021ee4: 1885883a add r2,r3,r2 + 8021ee8: 000d883a mov r6,zero + 8021eec: 000b883a mov r5,zero + 8021ef0: 1009883a mov r4,r2 + 8021ef4: 8021f280 call 8021f28 + 8021ef8: e0bffd15 stw r2,-12(fp) + + if (status!=0) dprintf("TSE_MAC_INIT error\n"); + 8021efc: e0bffd17 ldw r2,-12(fp) + 8021f00: 10000326 beq r2,zero,8021f10 + 8021f04: 01020174 movhi r4,2053 + 8021f08: 21265904 addi r4,r4,-26268 + 8021f0c: 8002d9c0 call 8002d9c + + return status; + 8021f10: e0bffd17 ldw r2,-12(fp) +} + 8021f14: e037883a mov sp,fp + 8021f18: dfc00117 ldw ra,4(sp) + 8021f1c: df000017 ldw fp,0(sp) + 8021f20: dec00204 addi sp,sp,8 + 8021f24: f800283a ret + +08021f28 : + * + * @API TYPE - Internal + * @return SUCCESS on success + */ +int tse_msgdma_write_init(ins_tse_info* tse_ptr,unsigned int * ActualData,unsigned int len) +{ + 8021f28: defff704 addi sp,sp,-36 + 8021f2c: dfc00815 stw ra,32(sp) + 8021f30: df000715 stw fp,28(sp) + 8021f34: df000704 addi fp,sp,28 + 8021f38: e13ffc15 stw r4,-16(fp) + 8021f3c: e17ffb15 stw r5,-20(fp) + 8021f40: e1bffa15 stw r6,-24(fp) + alt_u32 control = 0; + 8021f44: e03fff15 stw zero,-4(fp) + int desc_index; + int rc; + + tse_ptr->txdesc_list = NULL; + 8021f48: e0bffc17 ldw r2,-16(fp) + 8021f4c: 10000d15 stw zero,52(r2) + + for(desc_index = 0; desc_index < (ALTERA_TSE_MSGDMA_TX_DESC_CHAIN_SIZE); desc_index++) + 8021f50: e03ffe15 stw zero,-8(fp) + 8021f54: 00003306 br 8022024 + { + + /* trigger interrupt when transfer complete */ + control = ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GENERATE_SOP_MASK | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MASK; + 8021f58: 0080c004 movi r2,768 + 8021f5c: e0bfff15 stw r2,-4(fp) + + if (desc_index >= ( ALTERA_TSE_MSGDMA_TX_DESC_CHAIN_SIZE - 2)) control |= ALTERA_MSGDMA_DESCRIPTOR_CONTROL_TRANSFER_COMPLETE_IRQ_MASK; + 8021f60: e0bffe17 ldw r2,-8(fp) + 8021f64: 10000416 blt r2,zero,8021f78 + 8021f68: e0bfff17 ldw r2,-4(fp) + 8021f6c: 10900014 ori r2,r2,16384 + 8021f70: e0bfff15 stw r2,-4(fp) + 8021f74: 00000306 br 8021f84 + else control |= ALTERA_MSGDMA_DESCRIPTOR_CONTROL_EARLY_DONE_ENABLE_MASK; + 8021f78: e0bfff17 ldw r2,-4(fp) + 8021f7c: 10804034 orhi r2,r2,256 + 8021f80: e0bfff15 stw r2,-4(fp) + + rc=alt_msgdma_construct_prefetcher_standard_mm_to_st_descriptor( + 8021f84: e0bffc17 ldw r2,-16(fp) + 8021f88: 11000217 ldw r4,8(r2) + tse_ptr->mi.tx_msgdma, + (alt_msgdma_prefetcher_standard_descriptor *) &tse_ptr->txdesc[desc_index], + 8021f8c: e0bffc17 ldw r2,-16(fp) + 8021f90: 10c00e17 ldw r3,56(r2) + 8021f94: e0bffe17 ldw r2,-8(fp) + 8021f98: 1004917a slli r2,r2,5 + rc=alt_msgdma_construct_prefetcher_standard_mm_to_st_descriptor( + 8021f9c: 1887883a add r3,r3,r2 + 8021fa0: e17ffb17 ldw r5,-20(fp) + 8021fa4: e0bfff17 ldw r2,-4(fp) + 8021fa8: d8800015 stw r2,0(sp) + 8021fac: e1fffa17 ldw r7,-24(fp) + 8021fb0: 280d883a mov r6,r5 + 8021fb4: 180b883a mov r5,r3 + 8021fb8: 801f2f80 call 801f2f8 + 8021fbc: e0bffd15 stw r2,-12(fp) + (int)ActualData, + len, + control); + if (rc!=0) return -1; + 8021fc0: e0bffd17 ldw r2,-12(fp) + 8021fc4: 10000226 beq r2,zero,8021fd0 + 8021fc8: 00bfffc4 movi r2,-1 + 8021fcc: 00001906 br 8022034 + + if (desc_index==0) tse_ptr->txdesc_list = NULL; + 8021fd0: e0bffe17 ldw r2,-8(fp) + 8021fd4: 1000021e bne r2,zero,8021fe0 + 8021fd8: e0bffc17 ldw r2,-16(fp) + 8021fdc: 10000d15 stw zero,52(r2) + + rc=alt_msgdma_prefetcher_add_standard_desc_to_list( + 8021fe0: e0bffc17 ldw r2,-16(fp) + 8021fe4: 11000d04 addi r4,r2,52 + &tse_ptr->txdesc_list, + &tse_ptr->txdesc[desc_index] ); + 8021fe8: e0bffc17 ldw r2,-16(fp) + 8021fec: 10c00e17 ldw r3,56(r2) + 8021ff0: e0bffe17 ldw r2,-8(fp) + 8021ff4: 1004917a slli r2,r2,5 + rc=alt_msgdma_prefetcher_add_standard_desc_to_list( + 8021ff8: 1885883a add r2,r3,r2 + 8021ffc: 100b883a mov r5,r2 + 8022000: 801f5400 call 801f540 + 8022004: e0bffd15 stw r2,-12(fp) + if (rc!=0) return -1; + 8022008: e0bffd17 ldw r2,-12(fp) + 802200c: 10000226 beq r2,zero,8022018 + 8022010: 00bfffc4 movi r2,-1 + 8022014: 00000706 br 8022034 + for(desc_index = 0; desc_index < (ALTERA_TSE_MSGDMA_TX_DESC_CHAIN_SIZE); desc_index++) + 8022018: e0bffe17 ldw r2,-8(fp) + 802201c: 10800044 addi r2,r2,1 + 8022020: e0bffe15 stw r2,-8(fp) + 8022024: e0bffe17 ldw r2,-8(fp) + 8022028: 10800090 cmplti r2,r2,2 + 802202c: 103fca1e bne r2,zero,8021f58 + + } + + return 0; + 8022030: 0005883a mov r2,zero +} + 8022034: e037883a mov sp,fp + 8022038: dfc00117 ldw ra,4(sp) + 802203c: df000017 ldw fp,0(sp) + 8022040: dec00204 addi sp,sp,8 + 8022044: f800283a ret + +08022048 : + * @param data - pointer to the data payload + * @param data_bytes - number of bytes of the data payload to be sent to the MAC + * @return SUCCESS if success, else a negative value + */ +int tse_mac_raw_send(NET net, char * data, unsigned int data_bytes) +{ + 8022048: defff104 addi sp,sp,-60 + 802204c: dfc00e15 stw ra,56(sp) + 8022050: df000d15 stw fp,52(sp) + 8022054: df000d04 addi fp,sp,52 + 8022058: e13ff515 stw r4,-44(fp) + 802205c: e17ff415 stw r5,-48(fp) + 8022060: e1bff315 stw r6,-52(fp) + unsigned int len = data_bytes; + 8022064: e0bff317 ldw r2,-52(fp) + 8022068: e0bfff15 stw r2,-4(fp) + int rc; + + ins_tse_info* tse_ptr = (ins_tse_info*) net->n_local; + 802206c: e0bff517 ldw r2,-44(fp) + 8022070: 10802817 ldw r2,160(r2) + 8022074: e0bffe15 stw r2,-8(fp) + NIOS2_READ_STATUS (context); + 8022078: 0005303a rdctl r2,status + 802207c: e0bff915 stw r2,-28(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8022080: e0fff917 ldw r3,-28(fp) + 8022084: 00bfff84 movi r2,-2 + 8022088: 1884703a and r2,r3,r2 + 802208c: 1001703a wrctl status,r2 + return context; + 8022090: e0bff917 ldw r2,-28(fp) + tse_mac_trans_info *mi; + unsigned int* ActualData; + int cpu_sr; + + OS_ENTER_CRITICAL(); + 8022094: e0bffd15 stw r2,-12(fp) + mi = &tse_ptr->mi; + 8022098: e0bffe17 ldw r2,-8(fp) + 802209c: 10800104 addi r2,r2,4 + 80220a0: e0bffc15 stw r2,-16(fp) + + if(tse_ptr->sem!=0) /* Tx is busy*/ + 80220a4: e0bffe17 ldw r2,-8(fp) + 80220a8: 10800b17 ldw r2,44(r2) + 80220ac: 10000926 beq r2,zero,80220d4 + { + dprintf("raw_send CALLED AGAIN!!!\n"); + 80220b0: 01020174 movhi r4,2053 + 80220b4: 21265e04 addi r4,r4,-26248 + 80220b8: 8002d9c0 call 8002d9c + 80220bc: e0bffd17 ldw r2,-12(fp) + 80220c0: e0bff815 stw r2,-32(fp) + NIOS2_WRITE_STATUS (context); + 80220c4: e0bff817 ldw r2,-32(fp) + 80220c8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return ENP_RESOURCE; + 80220cc: 00bffa84 movi r2,-22 + 80220d0: 00004a06 br 80221fc + } + + tse_ptr->sem = 1; + 80220d4: e0bffe17 ldw r2,-8(fp) + 80220d8: 00c00044 movi r3,1 + 80220dc: 10c00b15 stw r3,44(r2) + + // clear bit-31 before passing it to MSGDMA Driver + ActualData = (unsigned int*)alt_remap_cached ((volatile void*) data, 4); + 80220e0: 01400104 movi r5,4 + 80220e4: e13ff417 ldw r4,-48(fp) + 80220e8: 8037e880 call 8037e88 + 80220ec: e0bffb15 stw r2,-20(fp) + dprintf("tse_msgdma_write_init bad return\n"); + OS_EXIT_CRITICAL(); + return -1; + } + #else + tse_ptr->txdesc[0].read_address = (alt_u32)ActualData; + 80220f0: e0bffe17 ldw r2,-8(fp) + 80220f4: 10800e17 ldw r2,56(r2) + 80220f8: e0fffb17 ldw r3,-20(fp) + 80220fc: 10c00015 stw r3,0(r2) + tse_ptr->txdesc[0].transfer_length = len; + 8022100: e0bffe17 ldw r2,-8(fp) + 8022104: 10800e17 ldw r2,56(r2) + 8022108: e0ffff17 ldw r3,-4(fp) + 802210c: 10c00215 stw r3,8(r2) + tse_ptr->txdesc[0].control = (tse_ptr->txdesc[0].control + 8022110: e0bffe17 ldw r2,-8(fp) + 8022114: 10800e17 ldw r2,56(r2) + 8022118: 10c00717 ldw r3,28(r2) + & ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_CLR_MASK) + | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK; + 802211c: 00900034 movhi r2,16384 + 8022120: 10bfffc4 addi r2,r2,-1 + 8022124: 1886703a and r3,r3,r2 + tse_ptr->txdesc[0].control = (tse_ptr->txdesc[0].control + 8022128: e0bffe17 ldw r2,-8(fp) + 802212c: 10800e17 ldw r2,56(r2) + | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK; + 8022130: 18e00034 orhi r3,r3,32768 + tse_ptr->txdesc[0].control = (tse_ptr->txdesc[0].control + 8022134: 10c00715 stw r3,28(r2) + #endif + + alt_dcache_flush(ActualData,len); + 8022138: e17fff17 ldw r5,-4(fp) + 802213c: e13ffb17 ldw r4,-20(fp) + 8022140: 80371c00 call 80371c0 + rc = tse_mac_aTxWrite(mi,tse_ptr->txdesc); + 8022144: e0bffe17 ldw r2,-8(fp) + 8022148: 10800e17 ldw r2,56(r2) + 802214c: 100b883a mov r5,r2 + 8022150: e13ffc17 ldw r4,-16(fp) + 8022154: 8017ce80 call 8017ce8 + 8022158: e0bffa15 stw r2,-24(fp) + if(rc < 0) /* MSGDMA not available */ + 802215c: e0bffa17 ldw r2,-24(fp) + 8022160: 1000120e bge r2,zero,80221ac + { + dprintf("raw_send() MSGDMA not available, ret=%d, len=%d\n",rc, len); + 8022164: e1bfff17 ldw r6,-4(fp) + 8022168: e17ffa17 ldw r5,-24(fp) + 802216c: 01020174 movhi r4,2053 + 8022170: 21266504 addi r4,r4,-26220 + 8022174: 8002c780 call 8002c78 + net->n_mib->ifOutDiscards++; + 8022178: e0bff517 ldw r2,-44(fp) + 802217c: 10802717 ldw r2,156(r2) + 8022180: 10c01217 ldw r3,72(r2) + 8022184: 18c00044 addi r3,r3,1 + 8022188: 10c01215 stw r3,72(r2) + tse_ptr->sem = 0; + 802218c: e0bffe17 ldw r2,-8(fp) + 8022190: 10000b15 stw zero,44(r2) + 8022194: e0bffd17 ldw r2,-12(fp) + 8022198: e0bff715 stw r2,-36(fp) + 802219c: e0bff717 ldw r2,-36(fp) + 80221a0: 1001703a wrctl status,r2 + + OS_EXIT_CRITICAL(); + return SEND_DROPPED; /* ENP_RESOURCE and SEND_DROPPED have the same value! */ + 80221a4: 00bffa84 movi r2,-22 + 80221a8: 00001406 br 80221fc + } + else /* = 0, success */ + { + net->n_mib->ifOutOctets += data_bytes; + 80221ac: e0bff517 ldw r2,-44(fp) + 80221b0: 10802717 ldw r2,156(r2) + 80221b4: 11000f17 ldw r4,60(r2) + 80221b8: e0bff517 ldw r2,-44(fp) + 80221bc: 10802717 ldw r2,156(r2) + 80221c0: e0fff317 ldw r3,-52(fp) + 80221c4: 20c7883a add r3,r4,r3 + 80221c8: 10c00f15 stw r3,60(r2) + /* we dont know whether it was unicast or not, we count both in */ + net->n_mib->ifOutUcastPkts++; + 80221cc: e0bff517 ldw r2,-44(fp) + 80221d0: 10802717 ldw r2,156(r2) + 80221d4: 10c01017 ldw r3,64(r2) + 80221d8: 18c00044 addi r3,r3,1 + 80221dc: 10c01015 stw r3,64(r2) + tse_ptr->sem = 0; + 80221e0: e0bffe17 ldw r2,-8(fp) + 80221e4: 10000b15 stw zero,44(r2) + 80221e8: e0bffd17 ldw r2,-12(fp) + 80221ec: e0bff615 stw r2,-40(fp) + 80221f0: e0bff617 ldw r2,-40(fp) + 80221f4: 1001703a wrctl status,r2 + + OS_EXIT_CRITICAL(); + return SUCCESS; /*success */ + 80221f8: 0005883a mov r2,zero + } +} + 80221fc: e037883a mov sp,fp + 8022200: dfc00117 ldw ra,4(sp) + 8022204: df000017 ldw fp,0(sp) + 8022208: dec00204 addi sp,sp,8 + 802220c: f800283a ret + +08022210 : + * @API TYPE - callback + * @param context - context of the TSE MAC instance + * @param intnum - temporary storage + */ +void tse_msgdmaRx_isr(void * context) +{ + 8022210: defff804 addi sp,sp,-32 + 8022214: dfc00715 stw ra,28(sp) + 8022218: df000615 stw fp,24(sp) + 802221c: df000604 addi fp,sp,24 + 8022220: e13ffa15 stw r4,-24(fp) + ins_tse_info* tse_ptr = (ins_tse_info *) context; + 8022224: e0bffa17 ldw r2,-24(fp) + 8022228: e0bffe15 stw r2,-8(fp) + alt_u32 msgdma_status; + alt_u32 i,control; + + /* Capture current rcv queue length */ + int initial_rcvdq_len = rcvdq.q_len; + 802222c: 008201b4 movhi r2,2054 + 8022230: 10b6ad17 ldw r2,-9548(r2) + 8022234: e0bffd15 stw r2,-12(fp) + + /* reenable global interrupts so we don't miss one that occurs during the + processing of this ISR */ + IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(tse_ptr->mi.rx_msgdma->prefetcher_base, + 8022238: e0bffe17 ldw r2,-8(fp) + 802223c: 10800317 ldw r2,12(r2) + 8022240: 10800617 ldw r2,24(r2) + 8022244: e0fffe17 ldw r3,-8(fp) + 8022248: 18c00317 ldw r3,12(r3) + 802224c: 18c00617 ldw r3,24(r3) + 8022250: 18c00037 ldwio r3,0(r3) + 8022254: 18c00214 ori r3,r3,8 + 8022258: 10c00035 stwio r3,0(r2) + IORD_ALT_MSGDMA_PREFETCHER_CONTROL(tse_ptr->mi.rx_msgdma->prefetcher_base) + | ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_SET_MASK); + + msgdma_status = IORD_ALTERA_MSGDMA_CSR_STATUS(tse_ptr->mi.rx_msgdma->csr_base); + 802225c: e0bffe17 ldw r2,-8(fp) + 8022260: 10800317 ldw r2,12(r2) + 8022264: 10800317 ldw r2,12(r2) + 8022268: 10800037 ldwio r2,0(r2) + 802226c: e0bffc15 stw r2,-16(fp) + + if ((msgdma_status & ALTERA_MSGDMA_CSR_STOPPED_ON_ERROR_MASK)==0) + 8022270: e0bffc17 ldw r2,-16(fp) + 8022274: 1080200c andi r2,r2,128 + 8022278: 1000421e bne r2,zero,8022384 + { + /* Handle received packet */ + tse_mac_rcv(tse_ptr); + 802227c: e13ffe17 ldw r4,-8(fp) + 8022280: 80227f80 call 80227f8 + + /* read the control field of the last descriptor in the chain */ + control = IORD_32DIRECT(&tse_ptr->rxdesc[tse_ptr->rx_chain][ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE-2],0x1c); + 8022284: e0bffe17 ldw r2,-8(fp) + 8022288: 10801317 ldw r2,76(r2) + 802228c: e0fffe17 ldw r3,-8(fp) + 8022290: 10800444 addi r2,r2,17 + 8022294: 100490ba slli r2,r2,2 + 8022298: 1885883a add r2,r3,r2 + 802229c: 10800017 ldw r2,0(r2) + 80222a0: 10803804 addi r2,r2,224 + 80222a4: 10800704 addi r2,r2,28 + 80222a8: 10800037 ldwio r2,0(r2) + 80222ac: e0bffb15 stw r2,-20(fp) + + //if the chain is completed then start a new chain + if ((control & ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET_MASK)==0) + 80222b0: e0bffb17 ldw r2,-20(fp) + 80222b4: 1090002c andhi r2,r2,16384 + 80222b8: 10002a1e bne r2,zero,8022364 + { + /* process any unprocessed descriptors */ + for (i=(tse_ptr->rx_descriptor_index);i<(ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE-1);i++) + 80222bc: e0bffe17 ldw r2,-8(fp) + 80222c0: 10801417 ldw r2,80(r2) + 80222c4: e0bfff15 stw r2,-4(fp) + 80222c8: 00000506 br 80222e0 + { + tse_mac_rcv(tse_ptr); + 80222cc: e13ffe17 ldw r4,-8(fp) + 80222d0: 80227f80 call 80227f8 + for (i=(tse_ptr->rx_descriptor_index);i<(ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE-1);i++) + 80222d4: e0bfff17 ldw r2,-4(fp) + 80222d8: 10800044 addi r2,r2,1 + 80222dc: e0bfff15 stw r2,-4(fp) + 80222e0: e0bfff17 ldw r2,-4(fp) + 80222e4: 10800230 cmpltui r2,r2,8 + 80222e8: 103ff81e bne r2,zero,80222cc + } + + /* cancel any pending ints */ + /* the chain could have been completed and int generated during the processing of this ISR */ + /* But we are handling that in this ISR, so cancel any pending interrupt */ + IOWR_ALT_MSGDMA_PREFETCHER_STATUS(tse_ptr->mi.rx_msgdma->prefetcher_base,1); + 80222ec: e0bffe17 ldw r2,-8(fp) + 80222f0: 10800317 ldw r2,12(r2) + 80222f4: 10800617 ldw r2,24(r2) + 80222f8: 10800404 addi r2,r2,16 + 80222fc: 00c00044 movi r3,1 + 8022300: 10c00035 stwio r3,0(r2) + + /* switch chains */ + tse_ptr->rx_descriptor_index = 0; + 8022304: e0bffe17 ldw r2,-8(fp) + 8022308: 10001415 stw zero,80(r2) + if (tse->rx_chain == 0) tse->rx_chain=1; else tse->rx_chain=0; + 802230c: 008201b4 movhi r2,2054 + 8022310: 10b5d517 ldw r2,-10412(r2) + 8022314: 1000041e bne r2,zero,8022328 + 8022318: 00c00044 movi r3,1 + 802231c: 008201b4 movhi r2,2054 + 8022320: 10f5d515 stw r3,-10412(r2) + 8022324: 00000206 br 8022330 + 8022328: 008201b4 movhi r2,2054 + 802232c: 1035d515 stw zero,-10412(r2) + + /* start new chain */ + tse_mac_aRxRead(&tse_ptr->mi, tse_ptr->rxdesc_list[tse->rx_chain]); + 8022330: e0bffe17 ldw r2,-8(fp) + 8022334: 11000104 addi r4,r2,4 + 8022338: 008201b4 movhi r2,2054 + 802233c: 10b5d517 ldw r2,-10412(r2) + 8022340: e0fffe17 ldw r3,-8(fp) + 8022344: 108003c4 addi r2,r2,15 + 8022348: 100490ba slli r2,r2,2 + 802234c: 1885883a add r2,r3,r2 + 8022350: 10800017 ldw r2,0(r2) + 8022354: 100b883a mov r5,r2 + 8022358: 8017c780 call 8017c78 + + /* allocate storage for the non active chain */ + allocate_rx_descriptor_chain(tse_ptr); + 802235c: e13ffe17 ldw r4,-8(fp) + 8022360: 80226c00 call 80226c0 + } + + /* Wake up Niche stack if there are new packets are on queue */ + if ((rcvdq.q_len) > initial_rcvdq_len) { + 8022364: 008201b4 movhi r2,2054 + 8022368: 10b6ad17 ldw r2,-9548(r2) + 802236c: e0fffd17 ldw r3,-12(fp) + 8022370: 1880070e bge r3,r2,8022390 + SignalPktDemux(); + 8022374: d0a08017 ldw r2,-32256(gp) + 8022378: 1009883a mov r4,r2 + 802237c: 8015d840 call 8015d84 + } + } /* if (no error) */ + else { dprintf("RX ERROR\n"); } + +} + 8022380: 00000306 br 8022390 + else { dprintf("RX ERROR\n"); } + 8022384: 01020174 movhi r4,2053 + 8022388: 21267204 addi r4,r4,-26168 + 802238c: 8002d9c0 call 8002d9c +} + 8022390: 0001883a nop + 8022394: e037883a mov sp,fp + 8022398: dfc00117 ldw ra,4(sp) + 802239c: df000017 ldw fp,0(sp) + 80223a0: dec00204 addi sp,sp,8 + 80223a4: f800283a ret + +080223a8 : + * + * @API TYPE - callback + * @param context - context of the TSE MAC instance + */ +void tse_msgdmaTx_isr(void * context) +{ + 80223a8: defffb04 addi sp,sp,-20 + 80223ac: dfc00415 stw ra,16(sp) + 80223b0: df000315 stw fp,12(sp) + 80223b4: df000304 addi fp,sp,12 + 80223b8: e13ffd15 stw r4,-12(fp) + ins_tse_info* tse_ptr = (ins_tse_info *) context; + 80223bc: e0bffd17 ldw r2,-12(fp) + 80223c0: e0bfff15 stw r2,-4(fp) + * IO read to peripheral that generated the IRQ is done after IO write + * to negate the interrupt request. This ensures at the IO write reaches + * the peripheral (through any high-latency hardware in the system) + * before the ISR exits. + */ + msgdma_status = IORD_ALTERA_MSGDMA_CSR_STATUS(tse_ptr->mi.tx_msgdma->csr_base); + 80223c4: e0bfff17 ldw r2,-4(fp) + 80223c8: 10800217 ldw r2,8(r2) + 80223cc: 10800317 ldw r2,12(r2) + 80223d0: 10800037 ldwio r2,0(r2) + 80223d4: e0bffe15 stw r2,-8(fp) + + if ((msgdma_status & ALTERA_MSGDMA_CSR_STOPPED_ON_ERROR_MASK)!=0) + 80223d8: e0bffe17 ldw r2,-8(fp) + 80223dc: 1080200c andi r2,r2,128 + 80223e0: 10000326 beq r2,zero,80223f0 + dprintf("TX STOPPED\n"); + 80223e4: 01020174 movhi r4,2053 + 80223e8: 21267504 addi r4,r4,-26156 + 80223ec: 8002d9c0 call 8002d9c + +} + 80223f0: 0001883a nop + 80223f4: e037883a mov sp,fp + 80223f8: dfc00117 ldw ra,4(sp) + 80223fc: df000017 ldw fp,0(sp) + 8022400: dec00204 addi sp,sp,8 + 8022404: f800283a ret + +08022408 : + * + * @API TYPE - Internal + * @return SUCCESS on success + */ +int tse_msgdma_read_init(ins_tse_info* tse_ptr) +{ + 8022408: defff604 addi sp,sp,-40 + 802240c: dfc00915 stw ra,36(sp) + 8022410: df000815 stw fp,32(sp) + 8022414: df000804 addi fp,sp,32 + 8022418: e13ff915 stw r4,-28(fp) + alt_u32 *uncached_packet_payload; + alt_u32 control = 0; + 802241c: e03ffb15 stw zero,-20(fp) + int desc_index; + int chain_index; + int rc; + int max_transfer_size=0xffff; + 8022420: 00bfffd4 movui r2,65535 + 8022424: e0bffc15 stw r2,-16(fp) + + if (tse_ptr->mi.rx_msgdma->max_byte < max_transfer_size) { max_transfer_size = tse_ptr->mi.rx_msgdma->max_byte; } + 8022428: e0bff917 ldw r2,-28(fp) + 802242c: 10800317 ldw r2,12(r2) + 8022430: 10c01217 ldw r3,72(r2) + 8022434: e0bffc17 ldw r2,-16(fp) + 8022438: 1880042e bgeu r3,r2,802244c + 802243c: e0bff917 ldw r2,-28(fp) + 8022440: 10800317 ldw r2,12(r2) + 8022444: 10801217 ldw r2,72(r2) + 8022448: e0bffc15 stw r2,-16(fp) + + for (chain_index=0;chain_index<2;chain_index++) + 802244c: e03ffd15 stw zero,-12(fp) + 8022450: 00007f06 br 8022650 + { + tse_ptr->rxdesc_list[chain_index] = NULL; + 8022454: e0fff917 ldw r3,-28(fp) + 8022458: e0bffd17 ldw r2,-12(fp) + 802245c: 108003c4 addi r2,r2,15 + 8022460: 100490ba slli r2,r2,2 + 8022464: 1885883a add r2,r3,r2 + 8022468: 10000015 stw zero,0(r2) + + for(desc_index = 0; desc_index < ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE; desc_index++) + 802246c: e03ffe15 stw zero,-8(fp) + 8022470: 00007106 br 8022638 + { + uncached_packet_payload = NULL; + 8022474: e03fff15 stw zero,-4(fp) + + if ((desc_index < (ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE-1))) { + 8022478: e0bffe17 ldw r2,-8(fp) + 802247c: 10800208 cmpgei r2,r2,8 + 8022480: 1000321e bne r2,zero,802254c + tse_ptr->pkt_array_rx[chain_index][desc_index] = pk_alloc(ALTERA_TSE_PKT_INIT_LEN); + 8022484: 01017e04 movi r4,1528 + 8022488: 80284340 call 8028434 + 802248c: 100b883a mov r5,r2 + 8022490: e0fff917 ldw r3,-28(fp) + 8022494: e0bffd17 ldw r2,-12(fp) + 8022498: 11000264 muli r4,r2,9 + 802249c: e0bffe17 ldw r2,-8(fp) + 80224a0: 2085883a add r2,r4,r2 + 80224a4: 10800584 addi r2,r2,22 + 80224a8: 100490ba slli r2,r2,2 + 80224ac: 1885883a add r2,r3,r2 + 80224b0: 11400015 stw r5,0(r2) + + if (!tse_ptr->pkt_array_rx[chain_index][desc_index]) /* couldn't get a free buffer for rx */ + 80224b4: e0fff917 ldw r3,-28(fp) + 80224b8: e0bffd17 ldw r2,-12(fp) + 80224bc: 11000264 muli r4,r2,9 + 80224c0: e0bffe17 ldw r2,-8(fp) + 80224c4: 2085883a add r2,r4,r2 + 80224c8: 10800584 addi r2,r2,22 + 80224cc: 100490ba slli r2,r2,2 + 80224d0: 1885883a add r2,r3,r2 + 80224d4: 10800017 ldw r2,0(r2) + 80224d8: 10000b1e bne r2,zero,8022508 + { + dprintf("[tse_msgdma_read_init] Fatal error: No free packet buffers for RX\n"); + 80224dc: 01020174 movhi r4,2053 + 80224e0: 21267804 addi r4,r4,-26144 + 80224e4: 8002d9c0 call 8002d9c + tse_ptr->netp->n_mib->ifInDiscards++; + 80224e8: e0bff917 ldw r2,-28(fp) + 80224ec: 10800817 ldw r2,32(r2) + 80224f0: 10802717 ldw r2,156(r2) + 80224f4: 10c00c17 ldw r3,48(r2) + 80224f8: 18c00044 addi r3,r3,1 + 80224fc: 10c00c15 stw r3,48(r2) + + return ENP_NOBUFFER; + 8022500: 00bffac4 movi r2,-21 + 8022504: 00006906 br 80226ac + } + + // ensure bit-31 of tse_ptr->pkt_array_rx[desc_index]->nb_buff is clear before passing + // to MSGDMA Driver + uncached_packet_payload = (alt_u32 *)alt_remap_cached ((volatile void*) tse_ptr->pkt_array_rx[chain_index][desc_index]->nb_buff, 4); + 8022508: e0fff917 ldw r3,-28(fp) + 802250c: e0bffd17 ldw r2,-12(fp) + 8022510: 11000264 muli r4,r2,9 + 8022514: e0bffe17 ldw r2,-8(fp) + 8022518: 2085883a add r2,r4,r2 + 802251c: 10800584 addi r2,r2,22 + 8022520: 100490ba slli r2,r2,2 + 8022524: 1885883a add r2,r3,r2 + 8022528: 10800017 ldw r2,0(r2) + 802252c: 10800117 ldw r2,4(r2) + 8022530: 01400104 movi r5,4 + 8022534: 1009883a mov r4,r2 + 8022538: 8037e880 call 8037e88 + 802253c: e0bfff15 stw r2,-4(fp) + alt_dcache_flush((void *) uncached_packet_payload, ALTERA_TSE_PKT_INIT_LEN); + 8022540: 01417e04 movi r5,1528 + 8022544: e13fff17 ldw r4,-4(fp) + 8022548: 80371c00 call 80371c0 + } + + /* trigger interrupt when transfer complete */ + control = ALTERA_MSGDMA_DESCRIPTOR_CONTROL_TRANSFER_COMPLETE_IRQ_MASK | + 802254c: 00803ff4 movhi r2,255 + 8022550: 10940004 addi r2,r2,20480 + 8022554: e0bffb15 stw r2,-20(fp) + ALTERA_MSGDMA_DESCRIPTOR_CONTROL_ERROR_IRQ_MASK | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_END_ON_EOP_MASK; + + rc=alt_msgdma_construct_prefetcher_standard_st_to_mm_descriptor( + 8022558: e0bff917 ldw r2,-28(fp) + 802255c: 11000317 ldw r4,12(r2) + tse_ptr->mi.rx_msgdma, + (alt_msgdma_prefetcher_standard_descriptor *) &tse_ptr->rxdesc[chain_index][desc_index], + 8022560: e0fff917 ldw r3,-28(fp) + 8022564: e0bffd17 ldw r2,-12(fp) + 8022568: 10800444 addi r2,r2,17 + 802256c: 100490ba slli r2,r2,2 + 8022570: 1885883a add r2,r3,r2 + 8022574: 10c00017 ldw r3,0(r2) + 8022578: e0bffe17 ldw r2,-8(fp) + 802257c: 1004917a slli r2,r2,5 + rc=alt_msgdma_construct_prefetcher_standard_st_to_mm_descriptor( + 8022580: 1887883a add r3,r3,r2 + 8022584: e17fff17 ldw r5,-4(fp) + 8022588: e1bffc17 ldw r6,-16(fp) + 802258c: e0bffb17 ldw r2,-20(fp) + 8022590: d8800015 stw r2,0(sp) + 8022594: 300f883a mov r7,r6 + 8022598: 280d883a mov r6,r5 + 802259c: 180b883a mov r5,r3 + 80225a0: 801f2a00 call 801f2a0 + 80225a4: e0bffa15 stw r2,-24(fp) + (alt_u32)uncached_packet_payload, + max_transfer_size, + control); + if (rc!=0) return -1; + 80225a8: e0bffa17 ldw r2,-24(fp) + 80225ac: 10000226 beq r2,zero,80225b8 + 80225b0: 00bfffc4 movi r2,-1 + 80225b4: 00003d06 br 80226ac + + if (desc_index==0) tse_ptr->rxdesc_list[chain_index] = NULL; + 80225b8: e0bffe17 ldw r2,-8(fp) + 80225bc: 1000061e bne r2,zero,80225d8 + 80225c0: e0fff917 ldw r3,-28(fp) + 80225c4: e0bffd17 ldw r2,-12(fp) + 80225c8: 108003c4 addi r2,r2,15 + 80225cc: 100490ba slli r2,r2,2 + 80225d0: 1885883a add r2,r3,r2 + 80225d4: 10000015 stw zero,0(r2) + + rc=alt_msgdma_prefetcher_add_standard_desc_to_list( + 80225d8: e0bffd17 ldw r2,-12(fp) + 80225dc: 108003c4 addi r2,r2,15 + 80225e0: 100490ba slli r2,r2,2 + 80225e4: e0fff917 ldw r3,-28(fp) + 80225e8: 1889883a add r4,r3,r2 + &tse_ptr->rxdesc_list[chain_index], + &tse_ptr->rxdesc[chain_index][desc_index] ); + 80225ec: e0fff917 ldw r3,-28(fp) + 80225f0: e0bffd17 ldw r2,-12(fp) + 80225f4: 10800444 addi r2,r2,17 + 80225f8: 100490ba slli r2,r2,2 + 80225fc: 1885883a add r2,r3,r2 + 8022600: 10c00017 ldw r3,0(r2) + 8022604: e0bffe17 ldw r2,-8(fp) + 8022608: 1004917a slli r2,r2,5 + rc=alt_msgdma_prefetcher_add_standard_desc_to_list( + 802260c: 1885883a add r2,r3,r2 + 8022610: 100b883a mov r5,r2 + 8022614: 801f5400 call 801f540 + 8022618: e0bffa15 stw r2,-24(fp) + if (rc!=0) return -1; + 802261c: e0bffa17 ldw r2,-24(fp) + 8022620: 10000226 beq r2,zero,802262c + 8022624: 00bfffc4 movi r2,-1 + 8022628: 00002006 br 80226ac + for(desc_index = 0; desc_index < ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE; desc_index++) + 802262c: e0bffe17 ldw r2,-8(fp) + 8022630: 10800044 addi r2,r2,1 + 8022634: e0bffe15 stw r2,-8(fp) + 8022638: e0bffe17 ldw r2,-8(fp) + 802263c: 10800250 cmplti r2,r2,9 + 8022640: 103f8c1e bne r2,zero,8022474 + for (chain_index=0;chain_index<2;chain_index++) + 8022644: e0bffd17 ldw r2,-12(fp) + 8022648: 10800044 addi r2,r2,1 + 802264c: e0bffd15 stw r2,-12(fp) + 8022650: e0bffd17 ldw r2,-12(fp) + 8022654: 10800090 cmplti r2,r2,2 + 8022658: 103f7e1e bne r2,zero,8022454 + } + + } + + dprintf("[tse_msgdma_read_init] RX descriptor chain desc (%d depth) created\n", desc_index); + 802265c: e17ffe17 ldw r5,-8(fp) + 8022660: 01020174 movhi r4,2053 + 8022664: 21268904 addi r4,r4,-26076 + 8022668: 8002c780 call 8002c78 + + tse_ptr->rx_descriptor_index=0; //for processing completed rx descriptors + 802266c: e0bff917 ldw r2,-28(fp) + 8022670: 10001415 stw zero,80(r2) + tse_ptr->rx_chain=0; + 8022674: e0bff917 ldw r2,-28(fp) + 8022678: 10001315 stw zero,76(r2) + tse_mac_aRxRead( &tse_ptr->mi, tse_ptr->rxdesc_list[tse_ptr->rx_chain]); + 802267c: e0bff917 ldw r2,-28(fp) + 8022680: 11000104 addi r4,r2,4 + 8022684: e0bff917 ldw r2,-28(fp) + 8022688: 10801317 ldw r2,76(r2) + 802268c: e0fff917 ldw r3,-28(fp) + 8022690: 108003c4 addi r2,r2,15 + 8022694: 100490ba slli r2,r2,2 + 8022698: 1885883a add r2,r3,r2 + 802269c: 10800017 ldw r2,0(r2) + 80226a0: 100b883a mov r5,r2 + 80226a4: 8017c780 call 8017c78 + + return SUCCESS; + 80226a8: 0005883a mov r2,zero +} + 80226ac: e037883a mov sp,fp + 80226b0: dfc00117 ldw ra,4(sp) + 80226b4: df000017 ldw fp,0(sp) + 80226b8: dec00204 addi sp,sp,8 + 80226bc: f800283a ret + +080226c0 : + +/* allocate the storage for the non active rx descriptor chain + update the write pointers in each descriptor to point + to the allocated storage. */ +int allocate_rx_descriptor_chain(ins_tse_info* tse_ptr) +{ + 80226c0: defff904 addi sp,sp,-28 + 80226c4: dfc00615 stw ra,24(sp) + 80226c8: df000515 stw fp,20(sp) + 80226cc: df000504 addi fp,sp,20 + 80226d0: e13ffb15 stw r4,-20(fp) + PACKET replacement_pkt; + alt_u32 *uncached_packet_payload; + alt_msgdma_prefetcher_standard_descriptor *rxDesc; + int i; + + for (i=0;i<(ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE-1);i++) + 80226d4: e03fff15 stw zero,-4(fp) + 80226d8: 00003e06 br 80227d4 + { + replacement_pkt = pk_alloc(ALTERA_TSE_PKT_INIT_LEN); + 80226dc: 01017e04 movi r4,1528 + 80226e0: 80284340 call 8028434 + 80226e4: e0bffe15 stw r2,-8(fp) + if (!replacement_pkt) { /* couldn't get a free buffer for rx */ + 80226e8: e0bffe17 ldw r2,-8(fp) + 80226ec: 1000051e bne r2,zero,8022704 + dprintf("No free buffers for rx\n"); + 80226f0: 01020174 movhi r4,2053 + 80226f4: 21269a04 addi r4,r4,-26008 + 80226f8: 8002d9c0 call 8002d9c + return 1; + 80226fc: 00800044 movi r2,1 + 8022700: 00003806 br 80227e4 + } + else + { + rxDesc = &tse_ptr->rxdesc[!tse_ptr->rx_chain][i]; + 8022704: e0bffb17 ldw r2,-20(fp) + 8022708: 10801317 ldw r2,76(r2) + 802270c: 1005003a cmpeq r2,r2,zero + 8022710: 10803fcc andi r2,r2,255 + 8022714: e0fffb17 ldw r3,-20(fp) + 8022718: 10800444 addi r2,r2,17 + 802271c: 100490ba slli r2,r2,2 + 8022720: 1885883a add r2,r3,r2 + 8022724: 10c00017 ldw r3,0(r2) + 8022728: e0bfff17 ldw r2,-4(fp) + 802272c: 1004917a slli r2,r2,5 + 8022730: 1885883a add r2,r3,r2 + 8022734: e0bffd15 stw r2,-12(fp) + tse_ptr->pkt_array_rx[!tse_ptr->rx_chain][i] = replacement_pkt; + 8022738: e0bffb17 ldw r2,-20(fp) + 802273c: 10801317 ldw r2,76(r2) + 8022740: 1005003a cmpeq r2,r2,zero + 8022744: 10803fcc andi r2,r2,255 + 8022748: e0fffb17 ldw r3,-20(fp) + 802274c: 11000264 muli r4,r2,9 + 8022750: e0bfff17 ldw r2,-4(fp) + 8022754: 2085883a add r2,r4,r2 + 8022758: 10800584 addi r2,r2,22 + 802275c: 100490ba slli r2,r2,2 + 8022760: 1885883a add r2,r3,r2 + 8022764: e0fffe17 ldw r3,-8(fp) + 8022768: 10c00015 stw r3,0(r2) + uncached_packet_payload = (alt_u32 *)alt_remap_cached(tse_ptr->pkt_array_rx[!tse_ptr->rx_chain][i]->nb_buff, 4); + 802276c: e0bffb17 ldw r2,-20(fp) + 8022770: 10801317 ldw r2,76(r2) + 8022774: 1005003a cmpeq r2,r2,zero + 8022778: 10803fcc andi r2,r2,255 + 802277c: e0fffb17 ldw r3,-20(fp) + 8022780: 11000264 muli r4,r2,9 + 8022784: e0bfff17 ldw r2,-4(fp) + 8022788: 2085883a add r2,r4,r2 + 802278c: 10800584 addi r2,r2,22 + 8022790: 100490ba slli r2,r2,2 + 8022794: 1885883a add r2,r3,r2 + 8022798: 10800017 ldw r2,0(r2) + 802279c: 10800117 ldw r2,4(r2) + 80227a0: 01400104 movi r5,4 + 80227a4: 1009883a mov r4,r2 + 80227a8: 8037e880 call 8037e88 + 80227ac: e0bffc15 stw r2,-16(fp) + alt_dcache_flush((void *) uncached_packet_payload, ALTERA_TSE_PKT_INIT_LEN); + 80227b0: 01417e04 movi r5,1528 + 80227b4: e13ffc17 ldw r4,-16(fp) + 80227b8: 80371c00 call 80371c0 + rxDesc->write_address = (alt_u32)(uncached_packet_payload); + 80227bc: e0fffc17 ldw r3,-16(fp) + 80227c0: e0bffd17 ldw r2,-12(fp) + 80227c4: 10c00115 stw r3,4(r2) + for (i=0;i<(ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE-1);i++) + 80227c8: e0bfff17 ldw r2,-4(fp) + 80227cc: 10800044 addi r2,r2,1 + 80227d0: e0bfff15 stw r2,-4(fp) + 80227d4: e0bfff17 ldw r2,-4(fp) + 80227d8: 10800210 cmplti r2,r2,8 + 80227dc: 103fbf1e bne r2,zero,80226dc + } + } + + return 0; + 80227e0: 0005883a mov r2,zero +} + 80227e4: e037883a mov sp,fp + 80227e8: dfc00117 ldw ra,4(sp) + 80227ec: df000017 ldw fp,0(sp) + 80227f0: dec00204 addi sp,sp,8 + 80227f4: f800283a ret + +080227f8 : + * @API TYPE - callback internal function + * @return SUCCESS on success + */ + +void tse_mac_rcv(ins_tse_info* tse_ptr) +{ + 80227f8: defffa04 addi sp,sp,-24 + 80227fc: dfc00515 stw ra,20(sp) + 8022800: df000415 stw fp,16(sp) + 8022804: df000404 addi fp,sp,16 + 8022808: e13ffc15 stw r4,-16(fp) + struct ethhdr * eth; + int pklen; + PACKET rx_packet; + + /* Correct frame length to actual (this is different from TX side) */ + pklen = IORD_32DIRECT(&tse_ptr->rxdesc[tse_ptr->rx_chain][tse_ptr->rx_descriptor_index].bytes_transfered,0) - 2; + 802280c: e0bffc17 ldw r2,-16(fp) + 8022810: 10801317 ldw r2,76(r2) + 8022814: e0fffc17 ldw r3,-16(fp) + 8022818: 10800444 addi r2,r2,17 + 802281c: 100490ba slli r2,r2,2 + 8022820: 1885883a add r2,r3,r2 + 8022824: 10c00017 ldw r3,0(r2) + 8022828: e0bffc17 ldw r2,-16(fp) + 802282c: 10801417 ldw r2,80(r2) + 8022830: 1004917a slli r2,r2,5 + 8022834: 1885883a add r2,r3,r2 + 8022838: 10800404 addi r2,r2,16 + 802283c: 10800037 ldwio r2,0(r2) + 8022840: 10bfff84 addi r2,r2,-2 + 8022844: e0bfff15 stw r2,-4(fp) + + tse_ptr->netp->n_mib->ifInOctets += (u_long)pklen; + 8022848: e0bffc17 ldw r2,-16(fp) + 802284c: 10800817 ldw r2,32(r2) + 8022850: 10802717 ldw r2,156(r2) + 8022854: 11000917 ldw r4,36(r2) + 8022858: e0ffff17 ldw r3,-4(fp) + 802285c: e0bffc17 ldw r2,-16(fp) + 8022860: 10800817 ldw r2,32(r2) + 8022864: 10802717 ldw r2,156(r2) + 8022868: 20c7883a add r3,r4,r3 + 802286c: 10c00915 stw r3,36(r2) + + rx_packet = tse_ptr->pkt_array_rx[tse_ptr->rx_chain][tse_ptr->rx_descriptor_index]; + 8022870: e0bffc17 ldw r2,-16(fp) + 8022874: 11001317 ldw r4,76(r2) + 8022878: e0bffc17 ldw r2,-16(fp) + 802287c: 10801417 ldw r2,80(r2) + 8022880: e0fffc17 ldw r3,-16(fp) + 8022884: 21000264 muli r4,r4,9 + 8022888: 2085883a add r2,r4,r2 + 802288c: 10800584 addi r2,r2,22 + 8022890: 100490ba slli r2,r2,2 + 8022894: 1885883a add r2,r3,r2 + 8022898: 10800017 ldw r2,0(r2) + 802289c: e0bffe15 stw r2,-8(fp) + rx_packet->nb_prot = rx_packet->nb_buff + ETHHDR_SIZE; + 80228a0: e0bffe17 ldw r2,-8(fp) + 80228a4: 10800117 ldw r2,4(r2) + 80228a8: 10c00404 addi r3,r2,16 + 80228ac: e0bffe17 ldw r2,-8(fp) + 80228b0: 10c00315 stw r3,12(r2) + rx_packet->nb_plen = pklen - 14; + 80228b4: e0bfff17 ldw r2,-4(fp) + 80228b8: 10bffc84 addi r2,r2,-14 + 80228bc: 1007883a mov r3,r2 + 80228c0: e0bffe17 ldw r2,-8(fp) + 80228c4: 10c00415 stw r3,16(r2) + rx_packet->nb_tstamp = cticks; + 80228c8: d0a07d17 ldw r2,-32268(gp) + 80228cc: 1007883a mov r3,r2 + 80228d0: e0bffe17 ldw r2,-8(fp) + 80228d4: 10c00515 stw r3,20(r2) + rx_packet->net = tse_ptr->netp; + 80228d8: e0bffc17 ldw r2,-16(fp) + 80228dc: 10c00817 ldw r3,32(r2) + 80228e0: e0bffe17 ldw r2,-8(fp) + 80228e4: 10c00615 stw r3,24(r2) + + // set packet type for demux routine + eth = (struct ethhdr *)(rx_packet->nb_buff + ETHHDR_BIAS); + 80228e8: e0bffe17 ldw r2,-8(fp) + 80228ec: 10800117 ldw r2,4(r2) + 80228f0: 10800084 addi r2,r2,2 + 80228f4: e0bffd15 stw r2,-12(fp) + rx_packet->type = eth->e_type; + 80228f8: e0bffd17 ldw r2,-12(fp) + 80228fc: 10c0030b ldhu r3,12(r2) + 8022900: e0bffe17 ldw r2,-8(fp) + 8022904: 10c0080d sth r3,32(r2) + + putq(&rcvdq, rx_packet); + 8022908: e17ffe17 ldw r5,-8(fp) + 802290c: 010201b4 movhi r4,2054 + 8022910: 2136ab04 addi r4,r4,-9556 + 8022914: 80289900 call 8028990 + + tse_ptr->rx_descriptor_index++; + 8022918: e0bffc17 ldw r2,-16(fp) + 802291c: 10801417 ldw r2,80(r2) + 8022920: 10c00044 addi r3,r2,1 + 8022924: e0bffc17 ldw r2,-16(fp) + 8022928: 10c01415 stw r3,80(r2) +} + 802292c: 0001883a nop + 8022930: e037883a mov sp,fp + 8022934: dfc00117 ldw ra,4(sp) + 8022938: df000017 ldw fp,0(sp) + 802293c: dec00204 addi sp,sp,8 + 8022940: f800283a ret + +08022944 : + +int tse_mac_stats(void * pio, int iface) +{ + 8022944: defffc04 addi sp,sp,-16 + 8022948: dfc00315 stw ra,12(sp) + 802294c: df000215 stw fp,8(sp) + 8022950: df000204 addi fp,sp,8 + 8022954: e13fff15 stw r4,-4(fp) + 8022958: e17ffe15 stw r5,-8(fp) + ns_printf(pio, "tse_mac_stats(), stats will be added later!\n"); + 802295c: 01420174 movhi r5,2053 + 8022960: 2966a004 addi r5,r5,-25984 + 8022964: e13fff17 ldw r4,-4(fp) + 8022968: 80273900 call 8027390 + return SUCCESS; + 802296c: 0005883a mov r2,zero +} + 8022970: e037883a mov sp,fp + 8022974: dfc00117 ldw ra,4(sp) + 8022978: df000017 ldw fp,0(sp) + 802297c: dec00204 addi sp,sp,8 + 8022980: f800283a ret + +08022984 : + * @API TYPE - Public + * @param iface index of the NET interface associated with the TSE MAC. + * @return SUCCESS + */ +int tse_mac_close(int iface) +{ + 8022984: defffc04 addi sp,sp,-16 + 8022988: dfc00315 stw ra,12(sp) + 802298c: df000215 stw fp,8(sp) + 8022990: df000204 addi fp,sp,8 + 8022994: e13ffe15 stw r4,-8(fp) + int state; + + /* status = down */ + nets[iface]->n_mib->ifAdminStatus = ALTERA_TSE_ADMIN_STATUS_DOWN; + 8022998: e0bffe17 ldw r2,-8(fp) + 802299c: 100690ba slli r3,r2,2 + 80229a0: 008201b4 movhi r2,2054 + 80229a4: 1885883a add r2,r3,r2 + 80229a8: 10b77017 ldw r2,-8768(r2) + 80229ac: 10802717 ldw r2,156(r2) + 80229b0: 00c00084 movi r3,2 + 80229b4: 10c00615 stw r3,24(r2) + + /* disable the interrupt in the OS*/ + alt_msgdma_register_callback(tse[iface].mi.rx_msgdma, 0, 0, 0); + 80229b8: e0bffe17 ldw r2,-8(fp) + 80229bc: 10c02924 muli r3,r2,164 + 80229c0: 008201b4 movhi r2,2054 + 80229c4: 1885883a add r2,r3,r2 + 80229c8: 10b5c517 ldw r2,-10476(r2) + 80229cc: 000f883a mov r7,zero + 80229d0: 000d883a mov r6,zero + 80229d4: 000b883a mov r5,zero + 80229d8: 1009883a mov r4,r2 + 80229dc: 80200940 call 8020094 + + /* Disable Receive path on the device*/ + state = IORD_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base); + 80229e0: e0bffe17 ldw r2,-8(fp) + 80229e4: 10c02924 muli r3,r2,164 + 80229e8: 008201b4 movhi r2,2054 + 80229ec: 1885883a add r2,r3,r2 + 80229f0: 10b5c317 ldw r2,-10484(r2) + 80229f4: 10800204 addi r2,r2,8 + 80229f8: 10800037 ldwio r2,0(r2) + 80229fc: e0bfff15 stw r2,-4(fp) + IOWR_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base,state & ~ALTERA_TSEMAC_CMD_RX_ENA_MSK); + 8022a00: e0bffe17 ldw r2,-8(fp) + 8022a04: 10c02924 muli r3,r2,164 + 8022a08: 008201b4 movhi r2,2054 + 8022a0c: 1885883a add r2,r3,r2 + 8022a10: 10b5c317 ldw r2,-10484(r2) + 8022a14: 10800204 addi r2,r2,8 + 8022a18: e13fff17 ldw r4,-4(fp) + 8022a1c: 00ffff44 movi r3,-3 + 8022a20: 20c6703a and r3,r4,r3 + 8022a24: 10c00035 stwio r3,0(r2) + + /* status = down */ + nets[iface]->n_mib->ifOperStatus = ALTERA_TSE_ADMIN_STATUS_DOWN; + 8022a28: e0bffe17 ldw r2,-8(fp) + 8022a2c: 100690ba slli r3,r2,2 + 8022a30: 008201b4 movhi r2,2054 + 8022a34: 1885883a add r2,r3,r2 + 8022a38: 10b77017 ldw r2,-8768(r2) + 8022a3c: 10802717 ldw r2,156(r2) + 8022a40: 00c00084 movi r3,2 + 8022a44: 10c00715 stw r3,28(r2) + + return SUCCESS; + 8022a48: 0005883a mov r2,zero +} + 8022a4c: e037883a mov sp,fp + 8022a50: dfc00117 ldw ra,4(sp) + 8022a54: df000017 ldw fp,0(sp) + 8022a58: dec00204 addi sp,sp,8 + 8022a5c: f800283a ret + +08022a60 : + * (for files and device drivers) or the InterNiche soclose() function for + * sockets. + */ + +int close (int fd) +{ + 8022a60: defffd04 addi sp,sp,-12 + 8022a64: dfc00215 stw ra,8(sp) + 8022a68: df000115 stw fp,4(sp) + 8022a6c: df000104 addi fp,sp,4 + 8022a70: e13fff15 stw r4,-4(fp) + return (fd < ALT_MAX_FD) ? alt_close (fd) : t_socketclose ((long) fd); + 8022a74: e0bfff17 ldw r2,-4(fp) + 8022a78: 10800408 cmpgei r2,r2,16 + 8022a7c: 1000031e bne r2,zero,8022a8c + 8022a80: e13fff17 ldw r4,-4(fp) + 8022a84: 80370f00 call 80370f0 + 8022a88: 00000206 br 8022a94 + 8022a8c: e13fff17 ldw r4,-4(fp) + 8022a90: 802ce700 call 802ce70 +} + 8022a94: e037883a mov sp,fp + 8022a98: dfc00117 ldw ra,4(sp) + 8022a9c: df000017 ldw fp,0(sp) + 8022aa0: dec00204 addi sp,sp,8 + 8022aa4: f800283a ret + +08022aa8 : + * total number of interfaces after initialization. + */ + +int iniche_devices_init( + int if_count) +{ + 8022aa8: defff504 addi sp,sp,-44 + 8022aac: dfc00a15 stw ra,40(sp) + 8022ab0: df000915 stw fp,36(sp) + 8022ab4: df000904 addi fp,sp,36 + 8022ab8: e13ff815 stw r4,-32(fp) + netmask, + gw; + int use_dhcp; + + /* Get the InterNiche device list. */ + p_dev = (alt_iniche_dev *) (alt_iniche_dev_list.next); + 8022abc: d0a00f17 ldw r2,-32708(gp) + 8022ac0: e0bfff15 stw r2,-4(fp) + p_dev_list_end = (alt_iniche_dev *) (&(alt_iniche_dev_list.next)); + 8022ac4: d0a00f04 addi r2,gp,-32708 + 8022ac8: e0bffe15 stw r2,-8(fp) + + /* Initialize each InterNiche device. */ + while (p_dev != p_dev_list_end) + 8022acc: 00003606 br 8022ba8 + { + /* Initialize the InterNiche device data record. */ + p_dev->p_driver_data = p_dev; + 8022ad0: e0bfff17 ldw r2,-4(fp) + 8022ad4: e0ffff17 ldw r3,-4(fp) + 8022ad8: 10c00415 stw r3,16(r2) + p_dev->if_num = if_count; + 8022adc: e0bfff17 ldw r2,-4(fp) + 8022ae0: e0fff817 ldw r3,-32(fp) + 8022ae4: 10c00515 stw r3,20(r2) + p_dev->p_net = nets[p_dev->if_num]; + 8022ae8: e0bfff17 ldw r2,-4(fp) + 8022aec: 10800517 ldw r2,20(r2) + 8022af0: 100690ba slli r3,r2,2 + 8022af4: 008201b4 movhi r2,2054 + 8022af8: 1885883a add r2,r3,r2 + 8022afc: 10f77017 ldw r3,-8768(r2) + 8022b00: e0bfff17 ldw r2,-4(fp) + 8022b04: 10c00615 stw r3,24(r2) + + /* Perform device specific initialization. */ + (*(p_dev->init_func))(p_dev); + 8022b08: e0bfff17 ldw r2,-4(fp) + 8022b0c: 10800317 ldw r2,12(r2) + 8022b10: e13fff17 ldw r4,-4(fp) + 8022b14: 103ee83a callr r2 + + /* Get the interface IP address. */ + p_net = p_dev->p_net; + 8022b18: e0bfff17 ldw r2,-4(fp) + 8022b1c: 10800617 ldw r2,24(r2) + 8022b20: e0bffd15 stw r2,-12(fp) + + if (get_ip_addr(p_dev, &ipaddr, &netmask, &gw, &use_dhcp)) + 8022b24: e17ffa04 addi r5,fp,-24 + 8022b28: e13ffb04 addi r4,fp,-20 + 8022b2c: e0fffc04 addi r3,fp,-16 + 8022b30: e0bff904 addi r2,fp,-28 + 8022b34: d8800015 stw r2,0(sp) + 8022b38: 280f883a mov r7,r5 + 8022b3c: 200d883a mov r6,r4 + 8022b40: 180b883a mov r5,r3 + 8022b44: e13fff17 ldw r4,-4(fp) + 8022b48: 800123c0 call 800123c + 8022b4c: 10001026 beq r2,zero,8022b90 + */ + if (use_dhcp) { + p_net->n_flags |= NF_DHCPC; + } +#endif + p_net->n_ipaddr = ipaddr; + 8022b50: e0fffc17 ldw r3,-16(fp) + 8022b54: e0bffd17 ldw r2,-12(fp) + 8022b58: 10c00a15 stw r3,40(r2) + p_net->snmask = netmask; + 8022b5c: e0fffb17 ldw r3,-20(fp) + 8022b60: e0bffd17 ldw r2,-12(fp) + 8022b64: 10c00c15 stw r3,48(r2) + p_net->n_defgw = gw; + 8022b68: e0fffa17 ldw r3,-24(fp) + 8022b6c: e0bffd17 ldw r2,-12(fp) + 8022b70: 10c00d15 stw r3,52(r2) +#ifdef IP_MULTICAST + p_net->n_mcastlist = mcastlist; + 8022b74: e0fffd17 ldw r3,-12(fp) + 8022b78: 00820134 movhi r2,2052 + 8022b7c: 10a28e04 addi r2,r2,-30152 + 8022b80: 18802b15 stw r2,172(r3) +#if defined (IGMP_V1) || defined (IGMP_V2) + p_net->igmp_oper_mode = IGMP_MODE_DEFAULT; + 8022b84: e0bffd17 ldw r2,-12(fp) + 8022b88: 00c00084 movi r3,2 + 8022b8c: 10c02f05 stb r3,188(r2) +#endif /* IGMPv1 or IGMPv2 */ +#endif /* IP_MULTICAST */ + } + + /* Initialize next device. */ + if_count++; + 8022b90: e0bff817 ldw r2,-32(fp) + 8022b94: 10800044 addi r2,r2,1 + 8022b98: e0bff815 stw r2,-32(fp) + p_dev = (alt_iniche_dev *) p_dev->llist.next; + 8022b9c: e0bfff17 ldw r2,-4(fp) + 8022ba0: 10800017 ldw r2,0(r2) + 8022ba4: e0bfff15 stw r2,-4(fp) + while (p_dev != p_dev_list_end) + 8022ba8: e0ffff17 ldw r3,-4(fp) + 8022bac: e0bffe17 ldw r2,-8(fp) + 8022bb0: 18bfc71e bne r3,r2,8022ad0 + } + + return (if_count); + 8022bb4: e0bff817 ldw r2,-32(fp) +} + 8022bb8: e037883a mov sp,fp + 8022bbc: dfc00117 ldw ra,4(sp) + 8022bc0: df000017 ldw fp,0(sp) + 8022bc4: dec00204 addi sp,sp,8 + 8022bc8: f800283a ret + +08022bcc : + * (for files and device drivers) or the InterNiche recvfrom() function for + * sockets. + */ + +int read (int fd, void *ptr, size_t len) +{ + 8022bcc: defff904 addi sp,sp,-28 + 8022bd0: dfc00615 stw ra,24(sp) + 8022bd4: df000515 stw fp,20(sp) + 8022bd8: df000504 addi fp,sp,20 + 8022bdc: e13fff15 stw r4,-4(fp) + 8022be0: e17ffe15 stw r5,-8(fp) + 8022be4: e1bffd15 stw r6,-12(fp) + return (fd < ALT_MAX_FD) ? alt_read (fd, ptr, len) + : recvfrom(fd, ptr, len, 0, NULL, NULL); + 8022be8: e0bfff17 ldw r2,-4(fp) + 8022bec: 10800408 cmpgei r2,r2,16 + 8022bf0: 1000051e bne r2,zero,8022c08 + return (fd < ALT_MAX_FD) ? alt_read (fd, ptr, len) + 8022bf4: e1bffd17 ldw r6,-12(fp) + 8022bf8: e17ffe17 ldw r5,-8(fp) + 8022bfc: e13fff17 ldw r4,-4(fp) + 8022c00: 8037d340 call 8037d34 + : recvfrom(fd, ptr, len, 0, NULL, NULL); + 8022c04: 00000806 br 8022c28 + 8022c08: e0bffd17 ldw r2,-12(fp) + 8022c0c: d8000115 stw zero,4(sp) + 8022c10: d8000015 stw zero,0(sp) + 8022c14: 000f883a mov r7,zero + 8022c18: 100d883a mov r6,r2 + 8022c1c: e17ffe17 ldw r5,-8(fp) + 8022c20: e13fff17 ldw r4,-4(fp) + 8022c24: 80269300 call 8026930 +} + 8022c28: e037883a mov sp,fp + 8022c2c: dfc00117 ldw ra,4(sp) + 8022c30: df000017 ldw fp,0(sp) + 8022c34: dec00204 addi sp,sp,8 + 8022c38: f800283a ret + +08022c3c : + * This implementation vectors requests to either the HAL alt_write() function + * (for files and device drivers) or the InterNiche send() function for sockets. + */ + +int write (int fd, const void *ptr, size_t len) +{ + 8022c3c: defffb04 addi sp,sp,-20 + 8022c40: dfc00415 stw ra,16(sp) + 8022c44: df000315 stw fp,12(sp) + 8022c48: df000304 addi fp,sp,12 + 8022c4c: e13fff15 stw r4,-4(fp) + 8022c50: e17ffe15 stw r5,-8(fp) + 8022c54: e1bffd15 stw r6,-12(fp) + if (fd < ALT_MAX_FD) + 8022c58: e0bfff17 ldw r2,-4(fp) + 8022c5c: 10800408 cmpgei r2,r2,16 + 8022c60: 1000051e bne r2,zero,8022c78 + { + return alt_write (fd, ptr, len); + 8022c64: e1bffd17 ldw r6,-12(fp) + 8022c68: e17ffe17 ldw r5,-8(fp) + 8022c6c: e13fff17 ldw r4,-4(fp) + 8022c70: 803826c0 call 803826c + 8022c74: 00000606 br 8022c90 + } + else + { + return send (fd, (void*) ptr, len, 0); + 8022c78: e0bffd17 ldw r2,-12(fp) + 8022c7c: 000f883a mov r7,zero + 8022c80: 100d883a mov r6,r2 + 8022c84: e17ffe17 ldw r5,-8(fp) + 8022c88: e13fff17 ldw r4,-4(fp) + 8022c8c: 802cb9c0 call 802cb9c + } +} + 8022c90: e037883a mov sp,fp + 8022c94: dfc00117 ldw ra,4(sp) + 8022c98: df000017 ldw fp,0(sp) + 8022c9c: dec00204 addi sp,sp,8 + 8022ca0: f800283a ret + +08022ca4 : + * RETURNS: int 0 if OK, else nonzero + */ + +int +etainit(void) +{ + 8022ca4: defffe04 addi sp,sp,-8 + 8022ca8: dfc00115 stw ra,4(sp) + 8022cac: df000015 stw fp,0(sp) + 8022cb0: d839883a mov fp,sp + /* register ARP type with the Net Driver */ + if (reg_type(ET_ARP) != 0) + 8022cb4: 01018204 movi r4,1544 + 8022cb8: 80241c80 call 80241c8 + 8022cbc: 10000526 beq r2,zero,8022cd4 + { +#ifdef NPDEBUG + dprintf("ARP: unable to register type with MAC Driver\n"); + 8022cc0: 01020174 movhi r4,2053 + 8022cc4: 2126ac04 addi r4,r4,-25936 + 8022cc8: 8002d9c0 call 8002d9c +#endif + return (1); + 8022ccc: 00800044 movi r2,1 + 8022cd0: 00000106 br 8022cd8 + } + return (0); + 8022cd4: 0005883a mov r2,zero +} + 8022cd8: e037883a mov sp,fp + 8022cdc: dfc00117 ldw ra,4(sp) + 8022ce0: df000017 ldw fp,0(sp) + 8022ce4: dec00204 addi sp,sp,8 + 8022ce8: f800283a ret + +08022cec : + * and MIB info in the packet header. + */ + +int +et_send(PACKET pkt, struct arptabent *tp) +{ + 8022cec: defff904 addi sp,sp,-28 + 8022cf0: dfc00615 stw ra,24(sp) + 8022cf4: df000515 stw fp,20(sp) + 8022cf8: df000504 addi fp,sp,20 + 8022cfc: e13ffc15 stw r4,-16(fp) + 8022d00: e17ffb15 stw r5,-20(fp) + char *ethhdr; + IFMIB etif = pkt->net->n_mib; /* mib info for this ethernet interface */ + 8022d04: e0bffc17 ldw r2,-16(fp) + 8022d08: 10800617 ldw r2,24(r2) + 8022d0c: 10802717 ldw r2,156(r2) + 8022d10: e0bffe15 stw r2,-8(fp) + int err; + + tp->lasttime = cticks; + 8022d14: d0e07d17 ldw r3,-32268(gp) + 8022d18: e0bffb17 ldw r2,-20(fp) + 8022d1c: 10c00615 stw r3,24(r2) + pkt->nb_prot -= ETHHDR_SIZE; /* prepare for prepending ethernet header */ + 8022d20: e0bffc17 ldw r2,-16(fp) + 8022d24: 10800317 ldw r2,12(r2) + 8022d28: 10fffc04 addi r3,r2,-16 + 8022d2c: e0bffc17 ldw r2,-16(fp) + 8022d30: 10c00315 stw r3,12(r2) + pkt->nb_plen += ETHHDR_SIZE; + 8022d34: e0bffc17 ldw r2,-16(fp) + 8022d38: 10800417 ldw r2,16(r2) + 8022d3c: 10c00404 addi r3,r2,16 + 8022d40: e0bffc17 ldw r2,-16(fp) + 8022d44: 10c00415 stw r3,16(r2) + ethhdr = pkt->nb_prot + ETHHDR_BIAS; + 8022d48: e0bffc17 ldw r2,-16(fp) + 8022d4c: 10800317 ldw r2,12(r2) + 8022d50: 10800084 addi r2,r2,2 + 8022d54: e0bffd15 stw r2,-12(fp) + MEMMOVE(snap, snapdata, 6); + snap->type = ARPIP; + } +#endif /* IEEE_802_3 */ + + if (ethhdr < pkt->nb_buff) /* sanity check pointer */ + 8022d58: e0bffc17 ldw r2,-16(fp) + 8022d5c: 10800117 ldw r2,4(r2) + 8022d60: e0fffd17 ldw r3,-12(fp) + 8022d64: 1880032e bgeu r3,r2,8022d74 + panic("et_send: prepend"); + 8022d68: 01020174 movhi r4,2053 + 8022d6c: 2126b804 addi r4,r4,-25888 + 8022d70: 80271780 call 8027178 + + MEMMOVE(ethhdr + ET_DSTOFF, tp->t_phy_addr, 6); /* set pkt's MAC dst addr */ + 8022d74: e0bffb17 ldw r2,-20(fp) + 8022d78: 10800104 addi r2,r2,4 + 8022d7c: 01800184 movi r6,6 + 8022d80: 100b883a mov r5,r2 + 8022d84: e13ffd17 ldw r4,-12(fp) + 8022d88: 80087b80 call 80087b8 + MEMMOVE(ethhdr + ET_SRCOFF, etif->ifPhysAddress, 6); /* MAC src */ + 8022d8c: e0bffd17 ldw r2,-12(fp) + 8022d90: 10c00184 addi r3,r2,6 + 8022d94: e0bffe17 ldw r2,-8(fp) + 8022d98: 10800517 ldw r2,20(r2) + 8022d9c: 01800184 movi r6,6 + 8022da0: 100b883a mov r5,r2 + 8022da4: 1809883a mov r4,r3 + 8022da8: 80087b80 call 80087b8 + + /* nice clean ethernet II header */ + if ((tp->flags & (ET_ETH2|ET_SNAP)) != ET_SNAP) + 8022dac: e0bffb17 ldw r2,-20(fp) + 8022db0: 1080070b ldhu r2,28(r2) + 8022db4: 10bfffcc andi r2,r2,65535 + 8022db8: 108000cc andi r2,r2,3 + 8022dbc: 108000a0 cmpeqi r2,r2,2 + 8022dc0: 1000041e bne r2,zero,8022dd4 + ET_TYPE_SET(ethhdr, ntohs(ARPIP)); + 8022dc4: e0bffd17 ldw r2,-12(fp) + 8022dc8: 10800304 addi r2,r2,12 + 8022dcc: 00c00204 movi r3,8 + 8022dd0: 10c00005 stb r3,0(r2) + 8022dd4: e0bffd17 ldw r2,-12(fp) + 8022dd8: 10800344 addi r2,r2,13 + 8022ddc: 10000005 stb zero,0(r2) + ET_TYPE_SET(ethhdr, len8023); + } +#endif /* IEEE_802_3 */ + + /* if a packet oriented send exists, use it: */ + if (pkt->net->pkt_send) + 8022de0: e0bffc17 ldw r2,-16(fp) + 8022de4: 10800617 ldw r2,24(r2) + 8022de8: 10800417 ldw r2,16(r2) + 8022dec: 10000726 beq r2,zero,8022e0c + err = pkt->net->pkt_send(pkt); /* send packet to media */ + 8022df0: e0bffc17 ldw r2,-16(fp) + 8022df4: 10800617 ldw r2,24(r2) + 8022df8: 10800417 ldw r2,16(r2) + 8022dfc: e13ffc17 ldw r4,-16(fp) + 8022e00: 103ee83a callr r2 + 8022e04: e0bfff15 stw r2,-4(fp) + 8022e08: 00001206 br 8022e54 + else /* else use older raw_send routine */ + { + /* sent to media */ + err = pkt->net->raw_send(pkt->net, pkt->nb_prot, pkt->nb_plen); + 8022e0c: e0bffc17 ldw r2,-16(fp) + 8022e10: 10800617 ldw r2,24(r2) + 8022e14: 10800317 ldw r2,12(r2) + 8022e18: e0fffc17 ldw r3,-16(fp) + 8022e1c: 19000617 ldw r4,24(r3) + 8022e20: e0fffc17 ldw r3,-16(fp) + 8022e24: 19400317 ldw r5,12(r3) + 8022e28: e0fffc17 ldw r3,-16(fp) + 8022e2c: 18c00417 ldw r3,16(r3) + 8022e30: 180d883a mov r6,r3 + 8022e34: 103ee83a callr r2 + 8022e38: e0bfff15 stw r2,-4(fp) + LOCK_NET_RESOURCE(FREEQ_RESID); + 8022e3c: 01000084 movi r4,2 + 8022e40: 8028f380 call 8028f38 + pk_free(pkt); + 8022e44: e13ffc17 ldw r4,-16(fp) + 8022e48: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8022e4c: 01000084 movi r4,2 + 8022e50: 8028ff40 call 8028ff4 + } + + return (err); + 8022e54: e0bfff17 ldw r2,-4(fp) +} + 8022e58: e037883a mov sp,fp + 8022e5c: dfc00117 ldw ra,4(sp) + 8022e60: df000017 ldw fp,0(sp) + 8022e64: dec00204 addi sp,sp,8 + 8022e68: f800283a ret + +08022e6c : + * and mark the entry "unused". + */ + +void +arp_free_pending(struct arptabent *entry) +{ + 8022e6c: defffb04 addi sp,sp,-20 + 8022e70: dfc00415 stw ra,16(sp) + 8022e74: df000315 stw fp,12(sp) + 8022e78: df000304 addi fp,sp,12 + 8022e7c: e13ffd15 stw r4,-12(fp) + PACKET tmppkt; + PACKET nextpkt; + + /* entry->pending has the linked list of all pending packets */ + tmppkt = entry->pending; + 8022e80: e0bffd17 ldw r2,-12(fp) + 8022e84: 10800417 ldw r2,16(r2) + 8022e88: e0bfff15 stw r2,-4(fp) + entry->pending = (PACKET)NULL; + 8022e8c: e0bffd17 ldw r2,-12(fp) + 8022e90: 10000415 stw zero,16(r2) + + LOCK_NET_RESOURCE(FREEQ_RESID); + 8022e94: 01000084 movi r4,2 + 8022e98: 8028f380 call 8028f38 + + /* free all pending packets */ + while (tmppkt) + 8022e9c: 00000906 br 8022ec4 + { + nextpkt = tmppkt->next; /* save the next packet in list */ + 8022ea0: e0bfff17 ldw r2,-4(fp) + 8022ea4: 10800017 ldw r2,0(r2) + 8022ea8: e0bffe15 stw r2,-8(fp) + tmppkt->next = (PACKET)NULL; + 8022eac: e0bfff17 ldw r2,-4(fp) + 8022eb0: 10000015 stw zero,0(r2) + pk_free(tmppkt); /* free current packet */ + 8022eb4: e13fff17 ldw r4,-4(fp) + 8022eb8: 80287480 call 8028748 + tmppkt = nextpkt; /* process the next packet */ + 8022ebc: e0bffe17 ldw r2,-8(fp) + 8022ec0: e0bfff15 stw r2,-4(fp) + while (tmppkt) + 8022ec4: e0bfff17 ldw r2,-4(fp) + 8022ec8: 103ff51e bne r2,zero,8022ea0 + } + + entry->t_pro_addr = 0; /* mark the entry "unused" */ + 8022ecc: e0bffd17 ldw r2,-12(fp) + 8022ed0: 10000015 stw zero,0(r2) + + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8022ed4: 01000084 movi r4,2 + 8022ed8: 8028ff40 call 8028ff4 +} + 8022edc: 0001883a nop + 8022ee0: e037883a mov sp,fp + 8022ee4: dfc00117 ldw ra,4(sp) + 8022ee8: df000017 ldw fp,0(sp) + 8022eec: dec00204 addi sp,sp,8 + 8022ef0: f800283a ret + +08022ef4 : + * Clear the list (entry->pending) after sending the packets. + */ + +void +arp_send_pending(struct arptabent *entry) +{ + 8022ef4: defffc04 addi sp,sp,-16 + 8022ef8: dfc00315 stw ra,12(sp) + 8022efc: df000215 stw fp,8(sp) + 8022f00: df000204 addi fp,sp,8 + 8022f04: e13ffe15 stw r4,-8(fp) + PACKET tmppkt = entry->pending; + 8022f08: e0bffe17 ldw r2,-8(fp) + 8022f0c: 10800417 ldw r2,16(r2) + 8022f10: e0bfff15 stw r2,-4(fp) + + /* entry->pending has the linked list of all pending packets */ + + /* send all pending packets */ + while ((tmppkt = entry->pending) != (PACKET)NULL) + 8022f14: 00000906 br 8022f3c + { + entry->pending = tmppkt->next; /* unlink the next packet */ + 8022f18: e0bfff17 ldw r2,-4(fp) + 8022f1c: 10c00017 ldw r3,0(r2) + 8022f20: e0bffe17 ldw r2,-8(fp) + 8022f24: 10c00415 stw r3,16(r2) + tmppkt->next = (PACKET)NULL; + 8022f28: e0bfff17 ldw r2,-4(fp) + 8022f2c: 10000015 stw zero,0(r2) + et_send(tmppkt, entry); /* try send again */ + 8022f30: e17ffe17 ldw r5,-8(fp) + 8022f34: e13fff17 ldw r4,-4(fp) + 8022f38: 8022cec0 call 8022cec + while ((tmppkt = entry->pending) != (PACKET)NULL) + 8022f3c: e0bffe17 ldw r2,-8(fp) + 8022f40: 10800417 ldw r2,16(r2) + 8022f44: e0bfff15 stw r2,-4(fp) + 8022f48: e0bfff17 ldw r2,-4(fp) + 8022f4c: 103ff21e bne r2,zero,8022f18 + } +} + 8022f50: 0001883a nop + 8022f54: e037883a mov sp,fp + 8022f58: dfc00117 ldw ra,4(sp) + 8022f5c: df000017 ldw fp,0(sp) + 8022f60: dec00204 addi sp,sp,8 + 8022f64: f800283a ret + +08022f68 : + * timeout will eventually free packet. + */ + +int +send_arp(PACKET pkt, ip_addr dest_ip) +{ + 8022f68: defff404 addi sp,sp,-48 + 8022f6c: dfc00b15 stw ra,44(sp) + 8022f70: df000a15 stw fp,40(sp) + 8022f74: df000a04 addi fp,sp,40 + 8022f78: e13ff715 stw r4,-36(fp) + 8022f7c: e17ff615 stw r5,-40(fp) + struct arptabent * oldest; + char * ethhdr; + NET net = pkt->net; + 8022f80: e0bff717 ldw r2,-36(fp) + 8022f84: 10800617 ldw r2,24(r2) + 8022f88: e0bfff15 stw r2,-4(fp) + struct arp_hdr * arphdr; + IFMIB etif = pkt->net->n_mib; /* mib info for this ethernet interface */ + 8022f8c: e0bff717 ldw r2,-36(fp) + 8022f90: 10800617 ldw r2,24(r2) + 8022f94: 10802717 ldw r2,156(r2) + 8022f98: e0bffe15 stw r2,-8(fp) + } dest_ip_ptr; +#endif /* ETHMCAST */ + + + /* If we are broadcasting or multicasting ... */ + if ((dest_ip == 0xFFFFFFFF) || + 8022f9c: e0bff617 ldw r2,-40(fp) + 8022fa0: 10bfffe0 cmpeqi r2,r2,-1 + 8022fa4: 1000191e bne r2,zero,802300c + ((dest_ip & ~(net->snmask)) == (0xFFFFFFFF & ~(net->snmask))) + 8022fa8: e0bfff17 ldw r2,-4(fp) + 8022fac: 10800c17 ldw r2,48(r2) + 8022fb0: 0086303a nor r3,zero,r2 + 8022fb4: e0bff617 ldw r2,-40(fp) + 8022fb8: 1886703a and r3,r3,r2 + 8022fbc: e0bfff17 ldw r2,-4(fp) + 8022fc0: 10800c17 ldw r2,48(r2) + 8022fc4: 0084303a nor r2,zero,r2 + if ((dest_ip == 0xFFFFFFFF) || + 8022fc8: 18801026 beq r3,r2,802300c + || (IN_MULTICAST(ntohl(dest_ip)) )) + 8022fcc: e0bff617 ldw r2,-40(fp) + 8022fd0: 1006d63a srli r3,r2,24 + 8022fd4: e0bff617 ldw r2,-40(fp) + 8022fd8: 1004d23a srli r2,r2,8 + 8022fdc: 10bfc00c andi r2,r2,65280 + 8022fe0: 1886b03a or r3,r3,r2 + 8022fe4: e0bff617 ldw r2,-40(fp) + 8022fe8: 1004923a slli r2,r2,8 + 8022fec: 10803fec andhi r2,r2,255 + 8022ff0: 1886b03a or r3,r3,r2 + 8022ff4: e0bff617 ldw r2,-40(fp) + 8022ff8: 1004963a slli r2,r2,24 + 8022ffc: 1884b03a or r2,r3,r2 + 8023000: 10fc002c andhi r3,r2,61440 + 8023004: 00b80034 movhi r2,57344 + 8023008: 1880391e bne r3,r2,80230f0 + ((dest_ip & ~(net->snmask)) == (0xFFFFFFFF & ~(net->snmask)))) + +#endif /* IP_MULTICAST */ + { + /* get unused or oldest entry in table */ + oldest = make_arp_entry(dest_ip, pkt->net); + 802300c: e0bff717 ldw r2,-36(fp) + 8023010: 10800617 ldw r2,24(r2) + 8023014: 100b883a mov r5,r2 + 8023018: e13ff617 ldw r4,-40(fp) + 802301c: 80235280 call 8023528 + 8023020: e0bffc15 stw r2,-16(fp) + + /* set MAC destination to ethernet broadcast (all FFs) */ + MEMSET(oldest->t_phy_addr, 0xFF, 6); + 8023024: e0bffc17 ldw r2,-16(fp) + 8023028: 10800104 addi r2,r2,4 + 802302c: 01800184 movi r6,6 + 8023030: 01403fc4 movi r5,255 + 8023034: 1009883a mov r4,r2 + 8023038: 80088e40 call 80088e4 +#ifdef IP_MULTICAST + /* If n_mcastlist routine is defined in the net structure, + map IP mcast to Ether multicast */ + +#ifdef ETHMCAST + if ((pkt->net->n_mcastlist) && (IN_MULTICAST(ntohl(dest_ip)))) + 802303c: e0bff717 ldw r2,-36(fp) + 8023040: 10800617 ldw r2,24(r2) + 8023044: 10802b17 ldw r2,172(r2) + 8023048: 10002526 beq r2,zero,80230e0 + 802304c: e0bff617 ldw r2,-40(fp) + 8023050: 1006d63a srli r3,r2,24 + 8023054: e0bff617 ldw r2,-40(fp) + 8023058: 1004d23a srli r2,r2,8 + 802305c: 10bfc00c andi r2,r2,65280 + 8023060: 1886b03a or r3,r3,r2 + 8023064: e0bff617 ldw r2,-40(fp) + 8023068: 1004923a slli r2,r2,8 + 802306c: 10803fec andhi r2,r2,255 + 8023070: 1886b03a or r3,r3,r2 + 8023074: e0bff617 ldw r2,-40(fp) + 8023078: 1004963a slli r2,r2,24 + 802307c: 1884b03a or r2,r3,r2 + 8023080: 10fc002c andhi r3,r2,61440 + 8023084: 00b80034 movhi r2,57344 + 8023088: 1880151e bne r3,r2,80230e0 + { + /* If IP mcast to be mapped to Ethernet multicast */ + dest_ip_ptr.l = dest_ip; + 802308c: e0bff617 ldw r2,-40(fp) + 8023090: e0bff815 stw r2,-32(fp) + oldest->t_phy_addr[0] = 0x01; + 8023094: e0bffc17 ldw r2,-16(fp) + 8023098: 00c00044 movi r3,1 + 802309c: 10c00105 stb r3,4(r2) + oldest->t_phy_addr[1] = 0x00; + 80230a0: e0bffc17 ldw r2,-16(fp) + 80230a4: 10000145 stb zero,5(r2) + oldest->t_phy_addr[2] = 0x5e; + 80230a8: e0bffc17 ldw r2,-16(fp) + 80230ac: 00c01784 movi r3,94 + 80230b0: 10c00185 stb r3,6(r2) + oldest->t_phy_addr[3] = (u_char )(dest_ip_ptr.c[1] & 0x7f); + 80230b4: e0bff843 ldbu r2,-31(fp) + 80230b8: 10801fcc andi r2,r2,127 + 80230bc: 1007883a mov r3,r2 + 80230c0: e0bffc17 ldw r2,-16(fp) + 80230c4: 10c001c5 stb r3,7(r2) + oldest->t_phy_addr[4] = (u_char )dest_ip_ptr.c[2]; + 80230c8: e0fff883 ldbu r3,-30(fp) + 80230cc: e0bffc17 ldw r2,-16(fp) + 80230d0: 10c00205 stb r3,8(r2) + oldest->t_phy_addr[5] = (u_char )dest_ip_ptr.c[3]; + 80230d4: e0fff8c3 ldbu r3,-29(fp) + 80230d8: e0bffc17 ldw r2,-16(fp) + 80230dc: 10c00245 stb r3,9(r2) + } +#endif /* ETHMCAST */ +#endif /* IP_MULTICAST */ + return (et_send(pkt, oldest)); + 80230e0: e17ffc17 ldw r5,-16(fp) + 80230e4: e13ff717 ldw r4,-36(fp) + 80230e8: 8022cec0 call 8022cec + 80230ec: 0000ae06 br 80233a8 + + /* If packet is addressed to this Ethernet interface, and + * it's not a loopback address, then don't send it on the wire. + * Instead, free the packet and return ENP_NO_ROUTE + */ + if ((pkt->fhost == pkt->net->n_ipaddr) && + 80230f0: e0bff717 ldw r2,-36(fp) + 80230f4: 10c00717 ldw r3,28(r2) + 80230f8: e0bff717 ldw r2,-36(fp) + 80230fc: 10800617 ldw r2,24(r2) + 8023100: 10800a17 ldw r2,40(r2) + 8023104: 18800d1e bne r3,r2,802313c + ((pkt->fhost & htonl(0xFF000000)) != htonl(0x7F000000))) + 8023108: e0bff717 ldw r2,-36(fp) + 802310c: 10800717 ldw r2,28(r2) + 8023110: 10803fcc andi r2,r2,255 + if ((pkt->fhost == pkt->net->n_ipaddr) && + 8023114: 10801fe0 cmpeqi r2,r2,127 + 8023118: 1000081e bne r2,zero,802313c + { + LOCK_NET_RESOURCE(FREEQ_RESID); + 802311c: 01000084 movi r4,2 + 8023120: 8028f380 call 8028f38 + pk_free(pkt); + 8023124: e13ff717 ldw r4,-36(fp) + 8023128: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 802312c: 01000084 movi r4,2 + 8023130: 8028ff40 call 8028ff4 + return ENP_NO_ROUTE; + 8023134: 00bff7c4 movi r2,-33 + 8023138: 00009b06 br 80233a8 + } + + /* not broadcasting, so get a packet for an ARP request */ + LOCK_NET_RESOURCE(FREEQ_RESID); + 802313c: 01000084 movi r4,2 + 8023140: 8028f380 call 8028f38 + arppkt = pk_alloc(arpsize); + 8023144: 01000c04 movi r4,48 + 8023148: 80284340 call 8028434 + 802314c: e0bffd15 stw r2,-12(fp) + if (!arppkt) + 8023150: e0bffd17 ldw r2,-12(fp) + 8023154: 1000061e bne r2,zero,8023170 + { + pk_free(pkt); + 8023158: e13ff717 ldw r4,-36(fp) + 802315c: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8023160: 01000084 movi r4,2 + 8023164: 8028ff40 call 8028ff4 + return ENP_RESOURCE; + 8023168: 00bffa84 movi r2,-22 + 802316c: 00008e06 br 80233a8 + } + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8023170: 01000084 movi r4,2 + 8023174: 8028ff40 call 8028ff4 + arppkt->nb_prot = arppkt->nb_buff; + 8023178: e0bffd17 ldw r2,-12(fp) + 802317c: 10c00117 ldw r3,4(r2) + 8023180: e0bffd17 ldw r2,-12(fp) + 8023184: 10c00315 stw r3,12(r2) + arppkt->nb_plen = arpsize; + 8023188: e0bffd17 ldw r2,-12(fp) + 802318c: 00c00c04 movi r3,48 + 8023190: 10c00415 stw r3,16(r2) + arppkt->net = pkt->net; + 8023194: e0bff717 ldw r2,-36(fp) + 8023198: 10c00617 ldw r3,24(r2) + 802319c: e0bffd17 ldw r2,-12(fp) + 80231a0: 10c00615 stw r3,24(r2) + + /* get unused or oldest entry in table */ + oldest = make_arp_entry(dest_ip, pkt->net); + 80231a4: e0bff717 ldw r2,-36(fp) + 80231a8: 10800617 ldw r2,24(r2) + 80231ac: 100b883a mov r5,r2 + 80231b0: e13ff617 ldw r4,-40(fp) + 80231b4: 80235280 call 8023528 + 80231b8: e0bffc15 stw r2,-16(fp) + + oldest->pending = pkt; /* packet is "pended", not pk_free()d */ + 80231bc: e0bffc17 ldw r2,-16(fp) + 80231c0: e0fff717 ldw r3,-36(fp) + 80231c4: 10c00415 stw r3,16(r2) + + /* build arp request packet */ + ethhdr = arppkt->nb_buff + ETHHDR_BIAS; /* ethernet header at start of buffer */ + 80231c8: e0bffd17 ldw r2,-12(fp) + 80231cc: 10800117 ldw r2,4(r2) + 80231d0: 10800084 addi r2,r2,2 + 80231d4: e0bffb15 stw r2,-20(fp) + arphdr = (struct arp_hdr *)(arppkt->nb_buff + ETHHDR_SIZE); /* arp header follows */ + 80231d8: e0bffd17 ldw r2,-12(fp) + 80231dc: 10800117 ldw r2,4(r2) + 80231e0: 10800404 addi r2,r2,16 + 80231e4: e0bffa15 stw r2,-24(fp) + +#ifdef IEEE_802_3 + arphdr->ar_hd = ARP8023HW; /* net endian 802.3 arp hardware type (ethernet) */ +#else + arphdr->ar_hd = ARPHW; /* net endian Ethernet arp hardware type (ethernet) */ + 80231e8: e0bffa17 ldw r2,-24(fp) + 80231ec: 00c04004 movi r3,256 + 80231f0: 10c0000d sth r3,0(r2) +#endif /* IEEE_802_3 */ + + arphdr->ar_pro = ARPIP; + 80231f4: e0bffa17 ldw r2,-24(fp) + 80231f8: 00c00204 movi r3,8 + 80231fc: 10c0008d sth r3,2(r2) + arphdr->ar_hln = 6; + 8023200: e0bffa17 ldw r2,-24(fp) + 8023204: 00c00184 movi r3,6 + 8023208: 10c00105 stb r3,4(r2) + arphdr->ar_pln = 4; + 802320c: e0bffa17 ldw r2,-24(fp) + 8023210: 00c00104 movi r3,4 + 8023214: 10c00145 stb r3,5(r2) + arphdr->ar_op = ARREQ; + 8023218: e0bffa17 ldw r2,-24(fp) + 802321c: 00c04004 movi r3,256 + 8023220: 10c0018d sth r3,6(r2) + arphdr->ar_tpa = dest_ip; /* target's IP address */ + 8023224: e0bffa17 ldw r2,-24(fp) + 8023228: e0fff617 ldw r3,-40(fp) + 802322c: 10c00715 stw r3,28(r2) + arphdr->ar_spa = pkt->net->n_ipaddr; /* my IP address */ + 8023230: e0bff717 ldw r2,-36(fp) + 8023234: 10800617 ldw r2,24(r2) + 8023238: 10c00a17 ldw r3,40(r2) + 802323c: e0bffa17 ldw r2,-24(fp) + 8023240: 10c00415 stw r3,16(r2) + MEMMOVE(arphdr->ar_sha, etif->ifPhysAddress, 6); + 8023244: e0bffa17 ldw r2,-24(fp) + 8023248: 10c00204 addi r3,r2,8 + 802324c: e0bffe17 ldw r2,-8(fp) + 8023250: 10800517 ldw r2,20(r2) + 8023254: 01800184 movi r6,6 + 8023258: 100b883a mov r5,r2 + 802325c: 1809883a mov r4,r3 + 8023260: 80087b80 call 80087b8 + MEMSET(ethhdr + ET_DSTOFF, 0xFF, 6); /* destination to broadcast (all FFs) */ + 8023264: 01800184 movi r6,6 + 8023268: 01403fc4 movi r5,255 + 802326c: e13ffb17 ldw r4,-20(fp) + 8023270: 80088e40 call 80088e4 + MEMMOVE(ethhdr + ET_SRCOFF, etif->ifPhysAddress, 6); + 8023274: e0bffb17 ldw r2,-20(fp) + 8023278: 10c00184 addi r3,r2,6 + 802327c: e0bffe17 ldw r2,-8(fp) + 8023280: 10800517 ldw r2,20(r2) + 8023284: 01800184 movi r6,6 + 8023288: 100b883a mov r5,r2 + 802328c: 1809883a mov r4,r3 + 8023290: 80087b80 call 80087b8 + ET_TYPE_SET(ethhdr, ntohs(ET_ARP)); + 8023294: e0bffb17 ldw r2,-20(fp) + 8023298: 10800304 addi r2,r2,12 + 802329c: 00c00204 movi r3,8 + 80232a0: 10c00005 stb r3,0(r2) + 80232a4: e0bffb17 ldw r2,-20(fp) + 80232a8: 10800344 addi r2,r2,13 + 80232ac: 00c00184 movi r3,6 + 80232b0: 10c00005 stb r3,0(r2) + +#ifdef NO_CC_PACKING /* move ARP fields to proper network boundaries */ + { + struct arp_wire * arwp = (struct arp_wire *)arphdr; + 80232b4: e0bffa17 ldw r2,-24(fp) + 80232b8: e0bff915 stw r2,-28(fp) + MEMMOVE(&arwp->data[AR_SHA], arphdr->ar_sha, 6); + 80232bc: e0bff917 ldw r2,-28(fp) + 80232c0: 10c00204 addi r3,r2,8 + 80232c4: e0bffa17 ldw r2,-24(fp) + 80232c8: 10800204 addi r2,r2,8 + 80232cc: 01800184 movi r6,6 + 80232d0: 100b883a mov r5,r2 + 80232d4: 1809883a mov r4,r3 + 80232d8: 80087b80 call 80087b8 + MEMMOVE(&arwp->data[AR_SPA], &arphdr->ar_spa, 4); + 80232dc: e0bff917 ldw r2,-28(fp) + 80232e0: 10c00384 addi r3,r2,14 + 80232e4: e0bffa17 ldw r2,-24(fp) + 80232e8: 10800404 addi r2,r2,16 + 80232ec: 01800104 movi r6,4 + 80232f0: 100b883a mov r5,r2 + 80232f4: 1809883a mov r4,r3 + 80232f8: 80087b80 call 80087b8 + MEMMOVE(&arwp->data[AR_THA], arphdr->ar_tha, 6); + 80232fc: e0bff917 ldw r2,-28(fp) + 8023300: 10c00484 addi r3,r2,18 + 8023304: e0bffa17 ldw r2,-24(fp) + 8023308: 10800504 addi r2,r2,20 + 802330c: 01800184 movi r6,6 + 8023310: 100b883a mov r5,r2 + 8023314: 1809883a mov r4,r3 + 8023318: 80087b80 call 80087b8 + MEMMOVE(&arwp->data[AR_TPA], &arphdr->ar_tpa, 4); + 802331c: e0bff917 ldw r2,-28(fp) + 8023320: 10c00604 addi r3,r2,24 + 8023324: e0bffa17 ldw r2,-24(fp) + 8023328: 10800704 addi r2,r2,28 + 802332c: 01800104 movi r6,4 + 8023330: 100b883a mov r5,r2 + 8023334: 1809883a mov r4,r3 + 8023338: 80087b80 call 80087b8 + } +#endif /* IEEE_802_3 */ + +#ifndef IEEE_802_3_ONLY + /* send arp request - if a packet oriented send exists, use it: */ + if (net->pkt_send) + 802333c: e0bfff17 ldw r2,-4(fp) + 8023340: 10800417 ldw r2,16(r2) + 8023344: 10000526 beq r2,zero,802335c + net->pkt_send(arppkt); /* driver should free arppkt later */ + 8023348: e0bfff17 ldw r2,-4(fp) + 802334c: 10800417 ldw r2,16(r2) + 8023350: e13ffd17 ldw r4,-12(fp) + 8023354: 103ee83a callr r2 + 8023358: 00000f06 br 8023398 + else /* use old raw send */ + { + net->raw_send(arppkt->net, arppkt->nb_buff, arpsize); + 802335c: e0bfff17 ldw r2,-4(fp) + 8023360: 10800317 ldw r2,12(r2) + 8023364: e0fffd17 ldw r3,-12(fp) + 8023368: 19000617 ldw r4,24(r3) + 802336c: e0fffd17 ldw r3,-12(fp) + 8023370: 18c00117 ldw r3,4(r3) + 8023374: 01800c04 movi r6,48 + 8023378: 180b883a mov r5,r3 + 802337c: 103ee83a callr r2 + LOCK_NET_RESOURCE(FREEQ_RESID); + 8023380: 01000084 movi r4,2 + 8023384: 8028f380 call 8028f38 + pk_free(arppkt); + 8023388: e13ffd17 ldw r4,-12(fp) + 802338c: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8023390: 01000084 movi r4,2 + 8023394: 8028ff40 call 8028ff4 + } + arpReqsOut++; + 8023398: d0a06117 ldw r2,-32380(gp) + 802339c: 10800044 addi r2,r2,1 + 80233a0: d0a06115 stw r2,-32380(gp) + LOCK_NET_RESOURCE(FREEQ_RESID); + pk_free(arppkt); + UNLOCK_NET_RESOURCE(FREEQ_RESID); +#endif /* IEEE_802_3_ONLY */ + + return ENP_SEND_PENDING; + 80233a4: 00800044 movi r2,1 +} + 80233a8: e037883a mov sp,fp + 80233ac: dfc00117 ldw ra,4(sp) + 80233b0: df000017 ldw fp,0(sp) + 80233b4: dec00204 addi sp,sp,8 + 80233b8: f800283a ret + +080233bc : + * Old entries are removed from the table. + */ + +struct arptabent * +find_oldest_arp(ip_addr dest_ip) +{ + 80233bc: defff804 addi sp,sp,-32 + 80233c0: dfc00715 stw ra,28(sp) + 80233c4: df000615 stw fp,24(sp) + 80233c8: df000604 addi fp,sp,24 + 80233cc: e13ffa15 stw r4,-24(fp) + struct arptabent *tp; + struct arptabent *exact = (struct arptabent *)NULL; + 80233d0: e03ffe15 stw zero,-8(fp) + struct arptabent *oldest = (struct arptabent *)NULL; + 80233d4: e03ffd15 stw zero,-12(fp) + struct arptabent *empty = (struct arptabent *)NULL; + 80233d8: e03ffc15 stw zero,-16(fp) + unsigned long lticks = cticks; + 80233dc: d0a07d17 ldw r2,-32268(gp) + 80233e0: e0bffb15 stw r2,-20(fp) + + /* find lru (or free) entry */ + for (tp = &arp_table[0]; tp < &arp_table[MAXARPS]; tp++) + 80233e4: 008201b4 movhi r2,2054 + 80233e8: 10b66604 addi r2,r2,-9832 + 80233ec: e0bfff15 stw r2,-4(fp) + 80233f0: 00003b06 br 80234e0 + { + /* age out old, pending entries */ + if (tp->pending) + 80233f4: e0bfff17 ldw r2,-4(fp) + 80233f8: 10800417 ldw r2,16(r2) + 80233fc: 10000b26 beq r2,zero,802342c + { + /* purge if pending for more than one second */ + if ((lticks - tp->createtime) > TPS) + 8023400: e0bfff17 ldw r2,-4(fp) + 8023404: 10800517 ldw r2,20(r2) + 8023408: e0fffb17 ldw r3,-20(fp) + 802340c: 1885c83a sub r2,r3,r2 + 8023410: 10801970 cmpltui r2,r2,101 + 8023414: 1000171e bne r2,zero,8023474 + { + arp_free_pending(tp); /* free pending packets */ + 8023418: e13fff17 ldw r4,-4(fp) + 802341c: 8022e6c0 call 8022e6c + tp->t_pro_addr = 0; /* mark entry as "unused" */ + 8023420: e0bfff17 ldw r2,-4(fp) + 8023424: 10000015 stw zero,0(r2) + 8023428: 00001206 br 8023474 + } + } + else if ((tp->t_pro_addr != 0) && + 802342c: e0bfff17 ldw r2,-4(fp) + 8023430: 10800017 ldw r2,0(r2) + 8023434: 10000f26 beq r2,zero,8023474 + ((int)(lticks - tp->createtime) >= arp_ageout) && + 8023438: e0bfff17 ldw r2,-4(fp) + 802343c: 10800517 ldw r2,20(r2) + 8023440: e0fffb17 ldw r3,-20(fp) + 8023444: 1885c83a sub r2,r3,r2 + 8023448: 1007883a mov r3,r2 + 802344c: d0a01117 ldw r2,-32700(gp) + else if ((tp->t_pro_addr != 0) && + 8023450: 18800816 blt r3,r2,8023474 + ((int)(lticks - tp->lasttime) >= TPS)) + 8023454: e0bfff17 ldw r2,-4(fp) + 8023458: 10800617 ldw r2,24(r2) + 802345c: e0fffb17 ldw r3,-20(fp) + 8023460: 1885c83a sub r2,r3,r2 + ((int)(lticks - tp->createtime) >= arp_ageout) && + 8023464: 10801910 cmplti r2,r2,100 + 8023468: 1000021e bne r2,zero,8023474 + { + /* entry has "expired" and has not been reference in 1 sec. */ + tp->t_pro_addr = 0; /* mark entry as "unused" */ + 802346c: e0bfff17 ldw r2,-4(fp) + 8023470: 10000015 stw zero,0(r2) + } + + if (tp->t_pro_addr == dest_ip) /* ip addr already has entry */ + 8023474: e0bfff17 ldw r2,-4(fp) + 8023478: 10800017 ldw r2,0(r2) + 802347c: e0fffa17 ldw r3,-24(fp) + 8023480: 1880031e bne r3,r2,8023490 + { + exact = tp; + 8023484: e0bfff17 ldw r2,-4(fp) + 8023488: e0bffe15 stw r2,-8(fp) + 802348c: 00001106 br 80234d4 + } + else if (tp->t_pro_addr != 0) + 8023490: e0bfff17 ldw r2,-4(fp) + 8023494: 10800017 ldw r2,0(r2) + 8023498: 10000a26 beq r2,zero,80234c4 + { + if (!oldest || (tp->lasttime < oldest->lasttime)) + 802349c: e0bffd17 ldw r2,-12(fp) + 80234a0: 10000526 beq r2,zero,80234b8 + 80234a4: e0bfff17 ldw r2,-4(fp) + 80234a8: 10c00617 ldw r3,24(r2) + 80234ac: e0bffd17 ldw r2,-12(fp) + 80234b0: 10800617 ldw r2,24(r2) + 80234b4: 1880072e bgeu r3,r2,80234d4 + oldest = tp; + 80234b8: e0bfff17 ldw r2,-4(fp) + 80234bc: e0bffd15 stw r2,-12(fp) + 80234c0: 00000406 br 80234d4 + } + else if (!empty) + 80234c4: e0bffc17 ldw r2,-16(fp) + 80234c8: 1000021e bne r2,zero,80234d4 + empty = tp; /* grab first empty slot */ + 80234cc: e0bfff17 ldw r2,-4(fp) + 80234d0: e0bffc15 stw r2,-16(fp) + for (tp = &arp_table[0]; tp < &arp_table[MAXARPS]; tp++) + 80234d4: e0bfff17 ldw r2,-4(fp) + 80234d8: 10800804 addi r2,r2,32 + 80234dc: e0bfff15 stw r2,-4(fp) + 80234e0: e0ffff17 ldw r3,-4(fp) + 80234e4: 008201b4 movhi r2,2054 + 80234e8: 10b6a604 addi r2,r2,-9576 + 80234ec: 18bfc136 bltu r3,r2,80233f4 + } + + return ((exact) ? exact : ((empty) ? empty : oldest)); + 80234f0: e0bffe17 ldw r2,-8(fp) + 80234f4: 1000061e bne r2,zero,8023510 + 80234f8: e0bffc17 ldw r2,-16(fp) + 80234fc: 10000226 beq r2,zero,8023508 + 8023500: e0bffc17 ldw r2,-16(fp) + 8023504: 00000306 br 8023514 + 8023508: e0bffd17 ldw r2,-12(fp) + 802350c: 00000106 br 8023514 + 8023510: e0bffe17 ldw r2,-8(fp) +} + 8023514: e037883a mov sp,fp + 8023518: dfc00117 ldw ra,4(sp) + 802351c: df000017 ldw fp,0(sp) + 8023520: dec00204 addi sp,sp,8 + 8023524: f800283a ret + +08023528 : + * active. + */ + +struct arptabent * +make_arp_entry(ip_addr dest_ip, NET net) +{ + 8023528: defffa04 addi sp,sp,-24 + 802352c: dfc00515 stw ra,20(sp) + 8023530: df000415 stw fp,16(sp) + 8023534: df000404 addi fp,sp,16 + 8023538: e13ffd15 stw r4,-12(fp) + 802353c: e17ffc15 stw r5,-16(fp) + struct arptabent *oldest; + unsigned long lticks = cticks; + 8023540: d0a07d17 ldw r2,-32268(gp) + 8023544: e0bfff15 stw r2,-4(fp) + + /* find usable (or existing) ARP table entry */ + oldest = find_oldest_arp(dest_ip); + 8023548: e13ffd17 ldw r4,-12(fp) + 802354c: 80233bc0 call 80233bc + 8023550: e0bffe15 stw r2,-8(fp) + + /* If recycling entry, don't leak packets which may be stuck here */ + if (oldest->pending && (oldest->t_pro_addr != dest_ip)) + 8023554: e0bffe17 ldw r2,-8(fp) + 8023558: 10800417 ldw r2,16(r2) + 802355c: 10000626 beq r2,zero,8023578 + 8023560: e0bffe17 ldw r2,-8(fp) + 8023564: 10800017 ldw r2,0(r2) + 8023568: e0fffd17 ldw r3,-12(fp) + 802356c: 18800226 beq r3,r2,8023578 + { + arp_free_pending(oldest); + 8023570: e13ffe17 ldw r4,-8(fp) + 8023574: 8022e6c0 call 8022e6c + } + + /* partially fill in arp entry */ + oldest->t_pro_addr = dest_ip; + 8023578: e0bffe17 ldw r2,-8(fp) + 802357c: e0fffd17 ldw r3,-12(fp) + 8023580: 10c00015 stw r3,0(r2) + oldest->net = net; + 8023584: e0bffe17 ldw r2,-8(fp) + 8023588: e0fffc17 ldw r3,-16(fp) + 802358c: 10c00315 stw r3,12(r2) + oldest->flags = 0; + 8023590: e0bffe17 ldw r2,-8(fp) + 8023594: 1000070d sth zero,28(r2) + MEMSET(oldest->t_phy_addr, '\0', 6); /* clear mac address */ + 8023598: e0bffe17 ldw r2,-8(fp) + 802359c: 10800104 addi r2,r2,4 + 80235a0: 01800184 movi r6,6 + 80235a4: 000b883a mov r5,zero + 80235a8: 1009883a mov r4,r2 + 80235ac: 80088e40 call 80088e4 + oldest->createtime = oldest->lasttime = lticks; + 80235b0: e0bffe17 ldw r2,-8(fp) + 80235b4: e0ffff17 ldw r3,-4(fp) + 80235b8: 10c00615 stw r3,24(r2) + 80235bc: e0bffe17 ldw r2,-8(fp) + 80235c0: 10c00617 ldw r3,24(r2) + 80235c4: e0bffe17 ldw r2,-8(fp) + 80235c8: 10c00515 stw r3,20(r2) + + /* start a ARP timer if there isn't one already */ + /* update the timeout value if there is a timer */ + /* time is specified in milliseconds */ + if (arp_timer == 0) + 80235cc: d0a05d17 ldw r2,-32396(gp) + 80235d0: 1000071e bne r2,zero,80235f0 + { + arp_timer = in_timerset(&cb_arpent_tmo, ARPENT_TMO * 1000, 0); + 80235d4: 000d883a mov r6,zero + 80235d8: 0149c404 movi r5,10000 + 80235dc: 010200b4 movhi r4,2050 + 80235e0: 210f3104 addi r4,r4,15556 + 80235e4: 8038c740 call 8038c74 + 80235e8: d0a05d15 stw r2,-32396(gp) + 80235ec: 00000706 br 802360c + } + else + { + ((struct intimer *)arp_timer)->tmo = + ((struct intimer *)arp_timer)->interval + lticks; + 80235f0: d0a05d17 ldw r2,-32396(gp) + 80235f4: 10c00217 ldw r3,8(r2) + ((struct intimer *)arp_timer)->tmo = + 80235f8: d0a05d17 ldw r2,-32396(gp) + 80235fc: 1009883a mov r4,r2 + ((struct intimer *)arp_timer)->interval + lticks; + 8023600: e0bfff17 ldw r2,-4(fp) + 8023604: 1885883a add r2,r3,r2 + ((struct intimer *)arp_timer)->tmo = + 8023608: 20800315 stw r2,12(r4) + } + + return oldest; + 802360c: e0bffe17 ldw r2,-8(fp) +} + 8023610: e037883a mov sp,fp + 8023614: dfc00117 ldw ra,4(sp) + 8023618: df000017 ldw fp,0(sp) + 802361c: dec00204 addi sp,sp,8 + 8023620: f800283a ret + +08023624 : + * must be freed (or reused) herein. + */ + +void +arpReply(PACKET pkt) +{ + 8023624: defff704 addi sp,sp,-36 + 8023628: dfc00815 stw ra,32(sp) + 802362c: df000715 stw fp,28(sp) + 8023630: df000704 addi fp,sp,28 + 8023634: e13ff915 stw r4,-28(fp) + struct arp_hdr *in; + struct arp_hdr *out; + char *ethout; + char *ethin; + + LOCK_NET_RESOURCE(FREEQ_RESID); + 8023638: 01000084 movi r4,2 + 802363c: 8028f380 call 8028f38 + outpkt = pk_alloc(arpsize); + 8023640: 01000c04 movi r4,48 + 8023644: 80284340 call 8028434 + 8023648: e0bfff15 stw r2,-4(fp) + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 802364c: 01000084 movi r4,2 + 8023650: 8028ff40 call 8028ff4 + + if (!outpkt) + 8023654: e0bfff17 ldw r2,-4(fp) + 8023658: 1000021e bne r2,zero,8023664 + { + dtrap(); + 802365c: 8028cd40 call 8028cd4 + return; + 8023660: 00009b06 br 80238d0 + } + + outpkt->net = pkt->net; /* send back out the iface it came from */ + 8023664: e0bff917 ldw r2,-28(fp) + 8023668: 10c00617 ldw r3,24(r2) + 802366c: e0bfff17 ldw r2,-4(fp) + 8023670: 10c00615 stw r3,24(r2) + + ethin = pkt->nb_prot - (ETHHDR_SIZE - ETHHDR_BIAS); + 8023674: e0bff917 ldw r2,-28(fp) + 8023678: 10800317 ldw r2,12(r2) + 802367c: 10bffc84 addi r2,r2,-14 + 8023680: e0bffe15 stw r2,-8(fp) + ethout = outpkt->nb_buff + ETHHDR_BIAS; + 8023684: e0bfff17 ldw r2,-4(fp) + 8023688: 10800117 ldw r2,4(r2) + 802368c: 10800084 addi r2,r2,2 + 8023690: e0bffd15 stw r2,-12(fp) + snap->type = ET_ARP; + } + else +#endif /* IEEE_802_3 */ + { + ET_TYPE_SET(ethout, ntohs(ET_ARP)); /* 0x0806 - ARP type on ethernet */ + 8023694: e0bffd17 ldw r2,-12(fp) + 8023698: 10800304 addi r2,r2,12 + 802369c: 00c00204 movi r3,8 + 80236a0: 10c00005 stb r3,0(r2) + 80236a4: e0bffd17 ldw r2,-12(fp) + 80236a8: 10800344 addi r2,r2,13 + 80236ac: 00c00184 movi r3,6 + 80236b0: 10c00005 stb r3,0(r2) + in = (struct arp_hdr *)(pkt->nb_prot); + 80236b4: e0bff917 ldw r2,-28(fp) + 80236b8: 10800317 ldw r2,12(r2) + 80236bc: e0bffc15 stw r2,-16(fp) + out = (struct arp_hdr *)(outpkt->nb_buff + ETHHDR_SIZE); + 80236c0: e0bfff17 ldw r2,-4(fp) + 80236c4: 10800117 ldw r2,4(r2) + 80236c8: 10800404 addi r2,r2,16 + 80236cc: e0bffb15 stw r2,-20(fp) + outpkt->nb_plen = arpsize; + 80236d0: e0bfff17 ldw r2,-4(fp) + 80236d4: 00c00c04 movi r3,48 + 80236d8: 10c00415 stw r3,16(r2) + + /* prepare outgoing arp packet */ +#ifdef IEEE_802_3 + out->ar_hd = ARP8023HW; /* net endian 802.3 arp hardware type (ethernet) */ +#else + out->ar_hd = ARPHW; /* net endian Ethernet arp hardware type (ethernet) */ + 80236dc: e0bffb17 ldw r2,-20(fp) + 80236e0: 00c04004 movi r3,256 + 80236e4: 10c0000d sth r3,0(r2) +#endif /* IEEE_802_3 */ + + out->ar_pro = ARPIP; + 80236e8: e0bffb17 ldw r2,-20(fp) + 80236ec: 00c00204 movi r3,8 + 80236f0: 10c0008d sth r3,2(r2) + out->ar_hln = 6; + 80236f4: e0bffb17 ldw r2,-20(fp) + 80236f8: 00c00184 movi r3,6 + 80236fc: 10c00105 stb r3,4(r2) + out->ar_pln = 4; + 8023700: e0bffb17 ldw r2,-20(fp) + 8023704: 00c00104 movi r3,4 + 8023708: 10c00145 stb r3,5(r2) + out->ar_op = ARREP; + 802370c: e0bffb17 ldw r2,-20(fp) + 8023710: 00c08004 movi r3,512 + 8023714: 10c0018d sth r3,6(r2) + out->ar_tpa = in->ar_spa; /* swap IP addresses */ + 8023718: e0bffc17 ldw r2,-16(fp) + 802371c: 10c00417 ldw r3,16(r2) + 8023720: e0bffb17 ldw r2,-20(fp) + 8023724: 10c00715 stw r3,28(r2) + out->ar_spa = in->ar_tpa; + 8023728: e0bffc17 ldw r2,-16(fp) + 802372c: 10c00717 ldw r3,28(r2) + 8023730: e0bffb17 ldw r2,-20(fp) + 8023734: 10c00415 stw r3,16(r2) + MEMMOVE(out->ar_tha, in->ar_sha, 6); /* move his MAC address */ + 8023738: e0bffb17 ldw r2,-20(fp) + 802373c: 10c00504 addi r3,r2,20 + 8023740: e0bffc17 ldw r2,-16(fp) + 8023744: 10800204 addi r2,r2,8 + 8023748: 01800184 movi r6,6 + 802374c: 100b883a mov r5,r2 + 8023750: 1809883a mov r4,r3 + 8023754: 80087b80 call 80087b8 + MEMMOVE(out->ar_sha, outpkt->net->n_mib->ifPhysAddress, 6); /* fill in our mac address */ + 8023758: e0bffb17 ldw r2,-20(fp) + 802375c: 10c00204 addi r3,r2,8 + 8023760: e0bfff17 ldw r2,-4(fp) + 8023764: 10800617 ldw r2,24(r2) + 8023768: 10802717 ldw r2,156(r2) + 802376c: 10800517 ldw r2,20(r2) + 8023770: 01800184 movi r6,6 + 8023774: 100b883a mov r5,r2 + 8023778: 1809883a mov r4,r3 + 802377c: 80087b80 call 80087b8 + + /* prepend ethernet unicast header to arp reply */ + MEMMOVE(ethout + ET_DSTOFF, ethin + ET_SRCOFF, 6); + 8023780: e0bffe17 ldw r2,-8(fp) + 8023784: 10800184 addi r2,r2,6 + 8023788: 01800184 movi r6,6 + 802378c: 100b883a mov r5,r2 + 8023790: e13ffd17 ldw r4,-12(fp) + 8023794: 80087b80 call 80087b8 + MEMMOVE(ethout + ET_SRCOFF, outpkt->net->n_mib->ifPhysAddress, 6); + 8023798: e0bffd17 ldw r2,-12(fp) + 802379c: 10c00184 addi r3,r2,6 + 80237a0: e0bfff17 ldw r2,-4(fp) + 80237a4: 10800617 ldw r2,24(r2) + 80237a8: 10802717 ldw r2,156(r2) + 80237ac: 10800517 ldw r2,20(r2) + 80237b0: 01800184 movi r6,6 + 80237b4: 100b883a mov r5,r2 + 80237b8: 1809883a mov r4,r3 + 80237bc: 80087b80 call 80087b8 + +#ifdef NO_CC_PACKING /* move ARP fields to proper network boundaries */ + { + struct arp_wire * arwp = (struct arp_wire *)out; + 80237c0: e0bffb17 ldw r2,-20(fp) + 80237c4: e0bffa15 stw r2,-24(fp) + MEMMOVE(&arwp->data[AR_SHA], out->ar_sha, 6); + 80237c8: e0bffa17 ldw r2,-24(fp) + 80237cc: 10c00204 addi r3,r2,8 + 80237d0: e0bffb17 ldw r2,-20(fp) + 80237d4: 10800204 addi r2,r2,8 + 80237d8: 01800184 movi r6,6 + 80237dc: 100b883a mov r5,r2 + 80237e0: 1809883a mov r4,r3 + 80237e4: 80087b80 call 80087b8 + MEMMOVE(&arwp->data[AR_SPA], &out->ar_spa, 4); + 80237e8: e0bffa17 ldw r2,-24(fp) + 80237ec: 10c00384 addi r3,r2,14 + 80237f0: e0bffb17 ldw r2,-20(fp) + 80237f4: 10800404 addi r2,r2,16 + 80237f8: 01800104 movi r6,4 + 80237fc: 100b883a mov r5,r2 + 8023800: 1809883a mov r4,r3 + 8023804: 80087b80 call 80087b8 + MEMMOVE(&arwp->data[AR_THA], out->ar_tha, 6); + 8023808: e0bffa17 ldw r2,-24(fp) + 802380c: 10c00484 addi r3,r2,18 + 8023810: e0bffb17 ldw r2,-20(fp) + 8023814: 10800504 addi r2,r2,20 + 8023818: 01800184 movi r6,6 + 802381c: 100b883a mov r5,r2 + 8023820: 1809883a mov r4,r3 + 8023824: 80087b80 call 80087b8 + MEMMOVE(&arwp->data[AR_TPA], &out->ar_tpa, 4); + 8023828: e0bffa17 ldw r2,-24(fp) + 802382c: 10c00604 addi r3,r2,24 + 8023830: e0bffb17 ldw r2,-20(fp) + 8023834: 10800704 addi r2,r2,28 + 8023838: 01800104 movi r6,4 + 802383c: 100b883a mov r5,r2 + 8023840: 1809883a mov r4,r3 + 8023844: 80087b80 call 80087b8 + } +#endif /* NO_CC_PACKING */ + + /* if a packet oriented send exists, use it: */ + if (outpkt->net->pkt_send) + 8023848: e0bfff17 ldw r2,-4(fp) + 802384c: 10800617 ldw r2,24(r2) + 8023850: 10800417 ldw r2,16(r2) + 8023854: 10000a26 beq r2,zero,8023880 + { + outpkt->nb_prot = outpkt->nb_buff; + 8023858: e0bfff17 ldw r2,-4(fp) + 802385c: 10c00117 ldw r3,4(r2) + 8023860: e0bfff17 ldw r2,-4(fp) + 8023864: 10c00315 stw r3,12(r2) + outpkt->net->pkt_send(outpkt); + 8023868: e0bfff17 ldw r2,-4(fp) + 802386c: 10800617 ldw r2,24(r2) + 8023870: 10800417 ldw r2,16(r2) + 8023874: e13fff17 ldw r4,-4(fp) + 8023878: 103ee83a callr r2 + 802387c: 00001106 br 80238c4 + } + else + { + outpkt->net->raw_send(pkt->net, outpkt->nb_buff, outpkt->nb_plen); + 8023880: e0bfff17 ldw r2,-4(fp) + 8023884: 10800617 ldw r2,24(r2) + 8023888: 10800317 ldw r2,12(r2) + 802388c: e0fff917 ldw r3,-28(fp) + 8023890: 19000617 ldw r4,24(r3) + 8023894: e0ffff17 ldw r3,-4(fp) + 8023898: 19400117 ldw r5,4(r3) + 802389c: e0ffff17 ldw r3,-4(fp) + 80238a0: 18c00417 ldw r3,16(r3) + 80238a4: 180d883a mov r6,r3 + 80238a8: 103ee83a callr r2 + LOCK_NET_RESOURCE(FREEQ_RESID); + 80238ac: 01000084 movi r4,2 + 80238b0: 8028f380 call 8028f38 + pk_free(outpkt); + 80238b4: e13fff17 ldw r4,-4(fp) + 80238b8: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 80238bc: 01000084 movi r4,2 + 80238c0: 8028ff40 call 8028ff4 + } + /* input 'pkt' will be freed by caller */ + arpRepsOut++; + 80238c4: d0a06317 ldw r2,-32372(gp) + 80238c8: 10800044 addi r2,r2,1 + 80238cc: d0a06315 stw r2,-32372(gp) +} + 80238d0: e037883a mov sp,fp + 80238d4: dfc00117 ldw ra,4(sp) + 80238d8: df000017 ldw fp,0(sp) + 80238dc: dec00204 addi sp,sp,8 + 80238e0: f800283a ret + +080238e4 : + * else a negative error code. + */ + +int +arprcv(PACKET pkt) +{ + 80238e4: defff904 addi sp,sp,-28 + 80238e8: dfc00615 stw ra,24(sp) + 80238ec: df000515 stw fp,20(sp) + 80238f0: df000504 addi fp,sp,20 + 80238f4: e13ffb15 stw r4,-20(fp) + char *eth; +#ifdef IEEE_802_3 + int ieee = FALSE; /* TRUE if received packet is 802.3 */ +#endif + + eth = pkt->nb_prot - (ETHHDR_SIZE - ETHHDR_BIAS); + 80238f8: e0bffb17 ldw r2,-20(fp) + 80238fc: 10800317 ldw r2,12(r2) + 8023900: 10bffc84 addi r2,r2,-14 + 8023904: e0bffe15 stw r2,-8(fp) + arphdr = (struct arp_hdr *)(pkt->nb_prot); + 8023908: e0bffb17 ldw r2,-20(fp) + 802390c: 10800317 ldw r2,12(r2) + 8023910: e0bffd15 stw r2,-12(fp) +#endif /* IEEE_802_3_ONLY */ +#endif /* IEEE_802_3 */ + +#ifdef NO_CC_PACKING /* force ARP fields to local CPU valid boundaries */ + { + struct arp_wire * arwp = (struct arp_wire *)arphdr; + 8023914: e0bffd17 ldw r2,-12(fp) + 8023918: e0bffc15 stw r2,-16(fp) + MEMMOVE(&arphdr->ar_tpa, &arwp->data[AR_TPA], 4); + 802391c: e0bffd17 ldw r2,-12(fp) + 8023920: 10c00704 addi r3,r2,28 + 8023924: e0bffc17 ldw r2,-16(fp) + 8023928: 10800604 addi r2,r2,24 + 802392c: 01800104 movi r6,4 + 8023930: 100b883a mov r5,r2 + 8023934: 1809883a mov r4,r3 + 8023938: 80087b80 call 80087b8 + MEMMOVE(arphdr->ar_tha, &arwp->data[AR_THA], 6); + 802393c: e0bffd17 ldw r2,-12(fp) + 8023940: 10c00504 addi r3,r2,20 + 8023944: e0bffc17 ldw r2,-16(fp) + 8023948: 10800484 addi r2,r2,18 + 802394c: 01800184 movi r6,6 + 8023950: 100b883a mov r5,r2 + 8023954: 1809883a mov r4,r3 + 8023958: 80087b80 call 80087b8 + MEMMOVE(&arphdr->ar_spa, &arwp->data[AR_SPA], 4); + 802395c: e0bffd17 ldw r2,-12(fp) + 8023960: 10c00404 addi r3,r2,16 + 8023964: e0bffc17 ldw r2,-16(fp) + 8023968: 10800384 addi r2,r2,14 + 802396c: 01800104 movi r6,4 + 8023970: 100b883a mov r5,r2 + 8023974: 1809883a mov r4,r3 + 8023978: 80087b80 call 80087b8 + MEMMOVE(arphdr->ar_sha, &arwp->data[AR_SHA], 6); + 802397c: e0bffd17 ldw r2,-12(fp) + 8023980: 10c00204 addi r3,r2,8 + 8023984: e0bffc17 ldw r2,-16(fp) + 8023988: 10800204 addi r2,r2,8 + 802398c: 01800184 movi r6,6 + 8023990: 100b883a mov r5,r2 + 8023994: 1809883a mov r4,r3 + 8023998: 80087b80 call 80087b8 +#endif + USE_ARG(eth); + + /* check ARP's target IP against our net's: */ +#ifdef IP_MULTICAST + if ((arphdr->ar_tpa != pkt->net->n_ipaddr) && /* if it's not for me.... */ + 802399c: e0bffd17 ldw r2,-12(fp) + 80239a0: 10c00717 ldw r3,28(r2) + 80239a4: e0bffb17 ldw r2,-20(fp) + 80239a8: 10800617 ldw r2,24(r2) + 80239ac: 10800a17 ldw r2,40(r2) + 80239b0: 18801c26 beq r3,r2,8023a24 + (!IN_MULTICAST(ntohl(arphdr->ar_tpa)))) + 80239b4: e0bffd17 ldw r2,-12(fp) + 80239b8: 10800717 ldw r2,28(r2) + 80239bc: 1006d63a srli r3,r2,24 + 80239c0: e0bffd17 ldw r2,-12(fp) + 80239c4: 10800717 ldw r2,28(r2) + 80239c8: 1004d23a srli r2,r2,8 + 80239cc: 10bfc00c andi r2,r2,65280 + 80239d0: 1886b03a or r3,r3,r2 + 80239d4: e0bffd17 ldw r2,-12(fp) + 80239d8: 10800717 ldw r2,28(r2) + 80239dc: 1004923a slli r2,r2,8 + 80239e0: 10803fec andhi r2,r2,255 + 80239e4: 1886b03a or r3,r3,r2 + 80239e8: e0bffd17 ldw r2,-12(fp) + 80239ec: 10800717 ldw r2,28(r2) + 80239f0: 1004963a slli r2,r2,24 + 80239f4: 1884b03a or r2,r3,r2 + 80239f8: 10fc002c andhi r3,r2,61440 + if ((arphdr->ar_tpa != pkt->net->n_ipaddr) && /* if it's not for me.... */ + 80239fc: 00b80034 movhi r2,57344 + 8023a00: 18800826 beq r3,r2,8023a24 +#else + if (arphdr->ar_tpa != pkt->net->n_ipaddr) +#endif /* IP_MULTICAST */ + { + LOCK_NET_RESOURCE(FREEQ_RESID); + 8023a04: 01000084 movi r4,2 + 8023a08: 8028f380 call 8028f38 + pk_free(pkt); /* not for us, dump & ret (proxy here later?) */ + 8023a0c: e13ffb17 ldw r4,-20(fp) + 8023a10: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8023a14: 01000084 movi r4,2 + 8023a18: 8028ff40 call 8028ff4 + return (ENP_NOT_MINE); + 8023a1c: 00800084 movi r2,2 + 8023a20: 00004406 br 8023b34 + } + + if (arphdr->ar_op == ARREQ) /* is it an arp request? */ + 8023a24: e0bffd17 ldw r2,-12(fp) + 8023a28: 1080018b ldhu r2,6(r2) + 8023a2c: 10bfffcc andi r2,r2,65535 + 8023a30: 10804018 cmpnei r2,r2,256 + 8023a34: 10000d1e bne r2,zero,8023a6c + { + arpReqsIn++; /* count these */ + 8023a38: d0a06017 ldw r2,-32384(gp) + 8023a3c: 10800044 addi r2,r2,1 + 8023a40: d0a06015 stw r2,-32384(gp) + arpReply(pkt); /* send arp reply */ + 8023a44: e13ffb17 ldw r4,-20(fp) + 8023a48: 80236240 call 8023624 + /* make partial ARP table entry */ + make_arp_entry(arphdr->ar_spa, pkt->net); + 8023a4c: e0bffd17 ldw r2,-12(fp) + 8023a50: 10c00417 ldw r3,16(r2) + 8023a54: e0bffb17 ldw r2,-20(fp) + 8023a58: 10800617 ldw r2,24(r2) + 8023a5c: 100b883a mov r5,r2 + 8023a60: 1809883a mov r4,r3 + 8023a64: 80235280 call 8023528 + 8023a68: 00000306 br 8023a78 + /* fall thru to arp reply logic to finish our table entry */ + } + else /* ARP reply, count and fall thru to logic to update table */ + { + arpRepsIn++; + 8023a6c: d0a06217 ldw r2,-32376(gp) + 8023a70: 10800044 addi r2,r2,1 + 8023a74: d0a06215 stw r2,-32376(gp) + } + + /* scan table for matching entry */ + /* check this for default gateway situations later, JB */ + for (tp = &arp_table[0]; tp < &arp_table[MAXARPS]; tp++) + 8023a78: 008201b4 movhi r2,2054 + 8023a7c: 10b66604 addi r2,r2,-9832 + 8023a80: e0bfff15 stw r2,-4(fp) + 8023a84: 00002006 br 8023b08 + { + if (tp->t_pro_addr == arphdr->ar_spa) /* we found IP address, update entry */ + 8023a88: e0bfff17 ldw r2,-4(fp) + 8023a8c: 10c00017 ldw r3,0(r2) + 8023a90: e0bffd17 ldw r2,-12(fp) + 8023a94: 10800417 ldw r2,16(r2) + 8023a98: 1880181e bne r3,r2,8023afc + tp->flags |= ET_SNAP; + else + tp->flags |= ET_ETH2; /* else it's ethernet II */ +#endif /* IEEE_802_3 */ + + MEMMOVE(tp->t_phy_addr, arphdr->ar_sha, 6); /* update MAC adddress */ + 8023a9c: e0bfff17 ldw r2,-4(fp) + 8023aa0: 10c00104 addi r3,r2,4 + 8023aa4: e0bffd17 ldw r2,-12(fp) + 8023aa8: 10800204 addi r2,r2,8 + 8023aac: 01800184 movi r6,6 + 8023ab0: 100b883a mov r5,r2 + 8023ab4: 1809883a mov r4,r3 + 8023ab8: 80087b80 call 80087b8 + tp->lasttime = cticks; + 8023abc: d0e07d17 ldw r3,-32268(gp) + 8023ac0: e0bfff17 ldw r2,-4(fp) + 8023ac4: 10c00615 stw r3,24(r2) + if (tp->pending) /* packet waiting for this IP entry? */ + 8023ac8: e0bfff17 ldw r2,-4(fp) + 8023acc: 10800417 ldw r2,16(r2) + 8023ad0: 10000226 beq r2,zero,8023adc + { + arp_send_pending(tp); + 8023ad4: e13fff17 ldw r4,-4(fp) + 8023ad8: 8022ef40 call 8022ef4 + } + LOCK_NET_RESOURCE(FREEQ_RESID); + 8023adc: 01000084 movi r4,2 + 8023ae0: 8028f380 call 8028f38 + pk_free(pkt); + 8023ae4: e13ffb17 ldw r4,-20(fp) + 8023ae8: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8023aec: 01000084 movi r4,2 + 8023af0: 8028ff40 call 8028ff4 + + return (0); + 8023af4: 0005883a mov r2,zero + 8023af8: 00000e06 br 8023b34 + for (tp = &arp_table[0]; tp < &arp_table[MAXARPS]; tp++) + 8023afc: e0bfff17 ldw r2,-4(fp) + 8023b00: 10800804 addi r2,r2,32 + 8023b04: e0bfff15 stw r2,-4(fp) + 8023b08: e0ffff17 ldw r3,-4(fp) + 8023b0c: 008201b4 movhi r2,2054 + 8023b10: 10b6a604 addi r2,r2,-9576 + 8023b14: 18bfdc36 bltu r3,r2,8023a88 + +#ifdef IEEE_802_3_ONLY +drop: +#endif /* IEEE_802_3_ONLY */ + /* fall to here if packet is not in table */ + LOCK_NET_RESOURCE(FREEQ_RESID); + 8023b18: 01000084 movi r4,2 + 8023b1c: 8028f380 call 8028f38 + pk_free(pkt); + 8023b20: e13ffb17 ldw r4,-20(fp) + 8023b24: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8023b28: 01000084 movi r4,2 + 8023b2c: 8028ff40 call 8028ff4 + + return ENP_NOT_MINE; + 8023b30: 00800084 movi r2,2 +} + 8023b34: e037883a mov sp,fp + 8023b38: dfc00117 ldw ra,4(sp) + 8023b3c: df000017 ldw fp,0(sp) + 8023b40: dec00204 addi sp,sp,8 + 8023b44: f800283a ret + +08023b48 : + * change the PC's IP address. + */ + +int +send_via_arp(PACKET pkt, ip_addr dest_ip) +{ + 8023b48: defff804 addi sp,sp,-32 + 8023b4c: dfc00715 stw ra,28(sp) + 8023b50: df000615 stw fp,24(sp) + 8023b54: df000604 addi fp,sp,24 + 8023b58: e13ffb15 stw r4,-20(fp) + 8023b5c: e17ffa15 stw r5,-24(fp) + struct arptabent *tp; + unsigned long lticks = cticks; + 8023b60: d0a07d17 ldw r2,-32268(gp) + 8023b64: e0bffc15 stw r2,-16(fp) + int err; + + /* don't allow zero dest */ + if (dest_ip == 0) + 8023b68: e0bffa17 ldw r2,-24(fp) + 8023b6c: 1000081e bne r2,zero,8023b90 + { + LOCK_NET_RESOURCE(FREEQ_RESID); + 8023b70: 01000084 movi r4,2 + 8023b74: 8028f380 call 8028f38 + pk_free(pkt); + 8023b78: e13ffb17 ldw r4,-20(fp) + 8023b7c: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8023b80: 01000084 movi r4,2 + 8023b84: 8028ff40 call 8028ff4 + return SEND_DROPPED; + 8023b88: 00bffa84 movi r2,-22 + 8023b8c: 00004806 br 8023cb0 + } + + /* Force refresh of cache once a second */ + if ((lticks - cachetime) > TPS) + 8023b90: d0a05f17 ldw r2,-32388(gp) + 8023b94: e0fffc17 ldw r3,-16(fp) + 8023b98: 1885c83a sub r2,r3,r2 + 8023b9c: 10801970 cmpltui r2,r2,101 + 8023ba0: 1000011e bne r2,zero,8023ba8 + arpcache = (struct arptabent *)NULL; + 8023ba4: d0205e15 stw zero,-32392(gp) + + /* look at the last ARP entry used. Good chance it's ours: */ + if (arpcache && (arpcache->t_pro_addr == dest_ip)) + 8023ba8: d0a05e17 ldw r2,-32392(gp) + 8023bac: 10000726 beq r2,zero,8023bcc + 8023bb0: d0a05e17 ldw r2,-32392(gp) + 8023bb4: 10800017 ldw r2,0(r2) + 8023bb8: e0fffa17 ldw r3,-24(fp) + 8023bbc: 1880031e bne r3,r2,8023bcc + tp = arpcache; + 8023bc0: d0a05e17 ldw r2,-32392(gp) + 8023bc4: e0bfff15 stw r2,-4(fp) + 8023bc8: 00000306 br 8023bd8 + else + { + /* scan arp table for an existing entry */ + tp = find_oldest_arp(dest_ip); + 8023bcc: e13ffa17 ldw r4,-24(fp) + 8023bd0: 80233bc0 call 80233bc + 8023bd4: e0bfff15 stw r2,-4(fp) + } + + if (tp->t_pro_addr == dest_ip) /* we found our entry */ + 8023bd8: e0bfff17 ldw r2,-4(fp) + 8023bdc: 10800017 ldw r2,0(r2) + 8023be0: e0fffa17 ldw r3,-24(fp) + 8023be4: 18802d1e bne r3,r2,8023c9c + { + if (tp->pending) /* arp already pending for this IP? */ + 8023be8: e0bfff17 ldw r2,-4(fp) + 8023bec: 10800417 ldw r2,16(r2) + 8023bf0: 10002126 beq r2,zero,8023c78 + { + if (lilfreeq.q_len < 2) + 8023bf4: 008201b4 movhi r2,2054 + 8023bf8: 10b79817 ldw r2,-8608(r2) + 8023bfc: 10800088 cmpgei r2,r2,2 + 8023c00: 1000091e bne r2,zero,8023c28 + { + /* system is depleted of resources - free the + * pkt instead of queueing it - so that we are in a + * position to receive an arp reply + */ + LOCK_NET_RESOURCE(FREEQ_RESID); + 8023c04: 01000084 movi r4,2 + 8023c08: 8028f380 call 8028f38 + pk_free(pkt); /* sorry, we have to dump this one.. */ + 8023c0c: e13ffb17 ldw r4,-20(fp) + 8023c10: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8023c14: 01000084 movi r4,2 + 8023c18: 8028ff40 call 8028ff4 + err = SEND_DROPPED; /* pkts already waiting for this IP entry */ + 8023c1c: 00bffa84 movi r2,-22 + 8023c20: e0bffe15 stw r2,-8(fp) + 8023c24: 00002106 br 8023cac + } + else + { + PACKET tmppkt=tp->pending; + 8023c28: e0bfff17 ldw r2,-4(fp) + 8023c2c: 10800417 ldw r2,16(r2) + 8023c30: e0bffd15 stw r2,-12(fp) + + /* queue the packet in pending list */ + while (tmppkt->next) /* traverse to the last packet */ + 8023c34: 00000306 br 8023c44 + tmppkt = tmppkt->next; + 8023c38: e0bffd17 ldw r2,-12(fp) + 8023c3c: 10800017 ldw r2,0(r2) + 8023c40: e0bffd15 stw r2,-12(fp) + while (tmppkt->next) /* traverse to the last packet */ + 8023c44: e0bffd17 ldw r2,-12(fp) + 8023c48: 10800017 ldw r2,0(r2) + 8023c4c: 103ffa1e bne r2,zero,8023c38 + tmppkt->next = pkt; /* add new pkt to end of list */ + 8023c50: e0bffd17 ldw r2,-12(fp) + 8023c54: e0fffb17 ldw r3,-20(fp) + 8023c58: 10c00015 stw r3,0(r2) + if (pkt->next) + 8023c5c: e0bffb17 ldw r2,-20(fp) + 8023c60: 10800017 ldw r2,0(r2) + 8023c64: 10000126 beq r2,zero,8023c6c + { + dtrap(); /* chain of pkts to be sent ??? */ + 8023c68: 8028cd40 call 8028cd4 + } + err = ENP_SEND_PENDING; /* packet queued pending ARP reply */ + 8023c6c: 00800044 movi r2,1 + 8023c70: e0bffe15 stw r2,-8(fp) + 8023c74: 00000d06 br 8023cac + } + } + else /* just send it */ + { + arpcache = tp; /* cache this entry */ + 8023c78: e0bfff17 ldw r2,-4(fp) + 8023c7c: d0a05e15 stw r2,-32392(gp) + cachetime = lticks; /* mark time we cached */ + 8023c80: e0bffc17 ldw r2,-16(fp) + 8023c84: d0a05f15 stw r2,-32388(gp) + err = et_send(pkt, tp); + 8023c88: e17fff17 ldw r5,-4(fp) + 8023c8c: e13ffb17 ldw r4,-20(fp) + 8023c90: 8022cec0 call 8022cec + 8023c94: e0bffe15 stw r2,-8(fp) + 8023c98: 00000406 br 8023cac + } + } + else + /* start the ARP process for this IP address */ + err = send_arp(pkt, dest_ip); + 8023c9c: e17ffa17 ldw r5,-24(fp) + 8023ca0: e13ffb17 ldw r4,-20(fp) + 8023ca4: 8022f680 call 8022f68 + 8023ca8: e0bffe15 stw r2,-8(fp) + + return (err); + 8023cac: e0bffe17 ldw r2,-8(fp) +} + 8023cb0: e037883a mov sp,fp + 8023cb4: dfc00117 ldw ra,4(sp) + 8023cb8: df000017 ldw fp,0(sp) + 8023cbc: dec00204 addi sp,sp,8 + 8023cc0: f800283a ret + +08023cc4 : + * + * If there are no more unresolved entries, cancel the timer. + */ +void +cb_arpent_tmo(long arg) +{ + 8023cc4: defffa04 addi sp,sp,-24 + 8023cc8: dfc00515 stw ra,20(sp) + 8023ccc: df000415 stw fp,16(sp) + 8023cd0: df000404 addi fp,sp,16 + 8023cd4: e13ffc15 stw r4,-16(fp) + struct arptabent *tp; + int arp_count = 0; + 8023cd8: e03ffe15 stw zero,-8(fp) + unsigned long lticks = cticks; + 8023cdc: d0a07d17 ldw r2,-32268(gp) + 8023ce0: e0bffd15 stw r2,-12(fp) + + for (tp = &arp_table[0]; tp < &arp_table[MAXARPS]; tp++) + 8023ce4: 008201b4 movhi r2,2054 + 8023ce8: 10b66604 addi r2,r2,-9832 + 8023cec: e0bfff15 stw r2,-4(fp) + 8023cf0: 00002706 br 8023d90 + { + if (tp->t_pro_addr != 0) + 8023cf4: e0bfff17 ldw r2,-4(fp) + 8023cf8: 10800017 ldw r2,0(r2) + 8023cfc: 10002126 beq r2,zero,8023d84 + { + /* age out old, pending entries */ + if (tp->pending && ((lticks - tp->createtime) > TPS)) + 8023d00: e0bfff17 ldw r2,-4(fp) + 8023d04: 10800417 ldw r2,16(r2) + 8023d08: 10000b26 beq r2,zero,8023d38 + 8023d0c: e0bfff17 ldw r2,-4(fp) + 8023d10: 10800517 ldw r2,20(r2) + 8023d14: e0fffd17 ldw r3,-12(fp) + 8023d18: 1885c83a sub r2,r3,r2 + 8023d1c: 10801970 cmpltui r2,r2,101 + 8023d20: 1000051e bne r2,zero,8023d38 + { + /* purge if pending for more than one second */ + arp_free_pending(tp); /* free pending packets */ + 8023d24: e13fff17 ldw r4,-4(fp) + 8023d28: 8022e6c0 call 8022e6c + tp->t_pro_addr = 0; /* mark entry as "unused" */ + 8023d2c: e0bfff17 ldw r2,-4(fp) + 8023d30: 10000015 stw zero,0(r2) + 8023d34: 00001306 br 8023d84 + } + else if (((int)(lticks - tp->createtime) >= arp_ageout) && + 8023d38: e0bfff17 ldw r2,-4(fp) + 8023d3c: 10800517 ldw r2,20(r2) + 8023d40: e0fffd17 ldw r3,-12(fp) + 8023d44: 1885c83a sub r2,r3,r2 + 8023d48: 1007883a mov r3,r2 + 8023d4c: d0a01117 ldw r2,-32700(gp) + 8023d50: 18800916 blt r3,r2,8023d78 + ((int)(lticks - tp->lasttime) >= TPS)) + 8023d54: e0bfff17 ldw r2,-4(fp) + 8023d58: 10800617 ldw r2,24(r2) + 8023d5c: e0fffd17 ldw r3,-12(fp) + 8023d60: 1885c83a sub r2,r3,r2 + else if (((int)(lticks - tp->createtime) >= arp_ageout) && + 8023d64: 10801910 cmplti r2,r2,100 + 8023d68: 1000031e bne r2,zero,8023d78 + { + /* entry has "expired" and has not been reference in 1 sec. */ + tp->t_pro_addr = 0; /* mark entry as "unused" */ + 8023d6c: e0bfff17 ldw r2,-4(fp) + 8023d70: 10000015 stw zero,0(r2) + 8023d74: 00000306 br 8023d84 + } + else + arp_count++; + 8023d78: e0bffe17 ldw r2,-8(fp) + 8023d7c: 10800044 addi r2,r2,1 + 8023d80: e0bffe15 stw r2,-8(fp) + for (tp = &arp_table[0]; tp < &arp_table[MAXARPS]; tp++) + 8023d84: e0bfff17 ldw r2,-4(fp) + 8023d88: 10800804 addi r2,r2,32 + 8023d8c: e0bfff15 stw r2,-4(fp) + 8023d90: e0ffff17 ldw r3,-4(fp) + 8023d94: 008201b4 movhi r2,2054 + 8023d98: 10b6a604 addi r2,r2,-9576 + 8023d9c: 18bfd536 bltu r3,r2,8023cf4 + } + } + + /* if there are no more "pending" entries, kill the timer */ + if (arp_count == 0) + 8023da0: e0bffe17 ldw r2,-8(fp) + 8023da4: 1000041e bne r2,zero,8023db8 + { + in_timerkill(arp_timer); + 8023da8: d0a05d17 ldw r2,-32396(gp) + 8023dac: 1009883a mov r4,r2 + 8023db0: 8038da00 call 8038da0 + arp_timer = 0; + 8023db4: d0205d15 stw zero,-32396(gp) + } + + USE_ARG(arg); +} + 8023db8: 0001883a nop + 8023dbc: e037883a mov sp,fp + 8023dc0: dfc00117 ldw ra,4(sp) + 8023dc4: df000017 ldw fp,0(sp) + 8023dc8: dec00204 addi sp,sp,8 + 8023dcc: f800283a ret + +08023dd0 : + * RETURNS: Returns 0 if OK, or the usual ENP_ errors + */ + +int +grat_arp(NET net, int flag) +{ + 8023dd0: defff704 addi sp,sp,-36 + 8023dd4: dfc00815 stw ra,32(sp) + 8023dd8: df000715 stw fp,28(sp) + 8023ddc: df000704 addi fp,sp,28 + 8023de0: e13ffa15 stw r4,-24(fp) + 8023de4: e17ff915 stw r5,-28(fp) + char * ethhdr; + struct arp_hdr * arphdr; + IFMIB etif = net->n_mib; /* mib info for this ethernet interface */ + 8023de8: e0bffa17 ldw r2,-24(fp) + 8023dec: 10802717 ldw r2,156(r2) + 8023df0: e0bfff15 stw r2,-4(fp) + PACKET arppkt; + + /* get a packet for an ARP request */ + LOCK_NET_RESOURCE(FREEQ_RESID); + 8023df4: 01000084 movi r4,2 + 8023df8: 8028f380 call 8028f38 + arppkt = pk_alloc(arpsize); + 8023dfc: 01000c04 movi r4,48 + 8023e00: 80284340 call 8028434 + 8023e04: e0bffe15 stw r2,-8(fp) + if (!arppkt) + 8023e08: e0bffe17 ldw r2,-8(fp) + 8023e0c: 1000041e bne r2,zero,8023e20 + { + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8023e10: 01000084 movi r4,2 + 8023e14: 8028ff40 call 8028ff4 + return ENP_RESOURCE; + 8023e18: 00bffa84 movi r2,-22 + 8023e1c: 00009506 br 8024074 + } + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8023e20: 01000084 movi r4,2 + 8023e24: 8028ff40 call 8028ff4 + arppkt->nb_prot = arppkt->nb_buff; + 8023e28: e0bffe17 ldw r2,-8(fp) + 8023e2c: 10c00117 ldw r3,4(r2) + 8023e30: e0bffe17 ldw r2,-8(fp) + 8023e34: 10c00315 stw r3,12(r2) + arppkt->nb_plen = arpsize; + 8023e38: e0bffe17 ldw r2,-8(fp) + 8023e3c: 00c00c04 movi r3,48 + 8023e40: 10c00415 stw r3,16(r2) + arppkt->net = net; + 8023e44: e0bffe17 ldw r2,-8(fp) + 8023e48: e0fffa17 ldw r3,-24(fp) + 8023e4c: 10c00615 stw r3,24(r2) + + /* build arp request packet */ + ethhdr = arppkt->nb_buff + ETHHDR_BIAS; /* ethernet header at start of buffer */ + 8023e50: e0bffe17 ldw r2,-8(fp) + 8023e54: 10800117 ldw r2,4(r2) + 8023e58: 10800084 addi r2,r2,2 + 8023e5c: e0bffd15 stw r2,-12(fp) + arphdr = (struct arp_hdr *)(arppkt->nb_buff + ETHHDR_SIZE); /* arp header follows */ + 8023e60: e0bffe17 ldw r2,-8(fp) + 8023e64: 10800117 ldw r2,4(r2) + 8023e68: 10800404 addi r2,r2,16 + 8023e6c: e0bffc15 stw r2,-16(fp) + +#ifdef IEEE_802_3 + arphdr->ar_hd = ARP8023HW; /* net endian 802.3 arp hardware type (ethernet) */ +#else + arphdr->ar_hd = ARPHW; /* net endian Ethernet arp hardware type (ethernet) */ + 8023e70: e0bffc17 ldw r2,-16(fp) + 8023e74: 00c04004 movi r3,256 + 8023e78: 10c0000d sth r3,0(r2) +#endif /* IEEE_802_3 */ + + arphdr->ar_pro = ARPIP; + 8023e7c: e0bffc17 ldw r2,-16(fp) + 8023e80: 00c00204 movi r3,8 + 8023e84: 10c0008d sth r3,2(r2) + arphdr->ar_hln = 6; + 8023e88: e0bffc17 ldw r2,-16(fp) + 8023e8c: 00c00184 movi r3,6 + 8023e90: 10c00105 stb r3,4(r2) + arphdr->ar_pln = 4; + 8023e94: e0bffc17 ldw r2,-16(fp) + 8023e98: 00c00104 movi r3,4 + 8023e9c: 10c00145 stb r3,5(r2) + + /* ARP req? */ + if (flag == 0) + 8023ea0: e0bff917 ldw r2,-28(fp) + 8023ea4: 1000041e bne r2,zero,8023eb8 + /* yup */ + arphdr->ar_op = ARREQ; + 8023ea8: e0bffc17 ldw r2,-16(fp) + 8023eac: 00c04004 movi r3,256 + 8023eb0: 10c0018d sth r3,6(r2) + 8023eb4: 00000306 br 8023ec4 + else + /* nope */ + arphdr->ar_op = ARREP; + 8023eb8: e0bffc17 ldw r2,-16(fp) + 8023ebc: 00c08004 movi r3,512 + 8023ec0: 10c0018d sth r3,6(r2) + + arphdr->ar_tpa = net->n_ipaddr; /* target's IP address */ + 8023ec4: e0bffa17 ldw r2,-24(fp) + 8023ec8: 10c00a17 ldw r3,40(r2) + 8023ecc: e0bffc17 ldw r2,-16(fp) + 8023ed0: 10c00715 stw r3,28(r2) + arphdr->ar_spa = net->n_ipaddr; /* my IP address */ + 8023ed4: e0bffa17 ldw r2,-24(fp) + 8023ed8: 10c00a17 ldw r3,40(r2) + 8023edc: e0bffc17 ldw r2,-16(fp) + 8023ee0: 10c00415 stw r3,16(r2) + MEMMOVE(arphdr->ar_sha, etif->ifPhysAddress, 6); + 8023ee4: e0bffc17 ldw r2,-16(fp) + 8023ee8: 10c00204 addi r3,r2,8 + 8023eec: e0bfff17 ldw r2,-4(fp) + 8023ef0: 10800517 ldw r2,20(r2) + 8023ef4: 01800184 movi r6,6 + 8023ef8: 100b883a mov r5,r2 + 8023efc: 1809883a mov r4,r3 + 8023f00: 80087b80 call 80087b8 + MEMSET(ethhdr + ET_DSTOFF, 0xFF, 6); /* destination to broadcast (all FFs) */ + 8023f04: 01800184 movi r6,6 + 8023f08: 01403fc4 movi r5,255 + 8023f0c: e13ffd17 ldw r4,-12(fp) + 8023f10: 80088e40 call 80088e4 + MEMMOVE(ethhdr + ET_SRCOFF, etif->ifPhysAddress, 6); + 8023f14: e0bffd17 ldw r2,-12(fp) + 8023f18: 10c00184 addi r3,r2,6 + 8023f1c: e0bfff17 ldw r2,-4(fp) + 8023f20: 10800517 ldw r2,20(r2) + 8023f24: 01800184 movi r6,6 + 8023f28: 100b883a mov r5,r2 + 8023f2c: 1809883a mov r4,r3 + 8023f30: 80087b80 call 80087b8 + ET_TYPE_SET(ethhdr, ntohs(ET_ARP)); + 8023f34: e0bffd17 ldw r2,-12(fp) + 8023f38: 10800304 addi r2,r2,12 + 8023f3c: 00c00204 movi r3,8 + 8023f40: 10c00005 stb r3,0(r2) + 8023f44: e0bffd17 ldw r2,-12(fp) + 8023f48: 10800344 addi r2,r2,13 + 8023f4c: 00c00184 movi r3,6 + 8023f50: 10c00005 stb r3,0(r2) + +#ifdef NO_CC_PACKING /* move ARP fields to proper network boundaries */ + { + struct arp_wire * arwp = (struct arp_wire *)arphdr; + 8023f54: e0bffc17 ldw r2,-16(fp) + 8023f58: e0bffb15 stw r2,-20(fp) + MEMMOVE(&arwp->data[AR_SHA], arphdr->ar_sha, 6); + 8023f5c: e0bffb17 ldw r2,-20(fp) + 8023f60: 10c00204 addi r3,r2,8 + 8023f64: e0bffc17 ldw r2,-16(fp) + 8023f68: 10800204 addi r2,r2,8 + 8023f6c: 01800184 movi r6,6 + 8023f70: 100b883a mov r5,r2 + 8023f74: 1809883a mov r4,r3 + 8023f78: 80087b80 call 80087b8 + MEMMOVE(&arwp->data[AR_SPA], &arphdr->ar_spa, 4); + 8023f7c: e0bffb17 ldw r2,-20(fp) + 8023f80: 10c00384 addi r3,r2,14 + 8023f84: e0bffc17 ldw r2,-16(fp) + 8023f88: 10800404 addi r2,r2,16 + 8023f8c: 01800104 movi r6,4 + 8023f90: 100b883a mov r5,r2 + 8023f94: 1809883a mov r4,r3 + 8023f98: 80087b80 call 80087b8 + + /* ARP req? */ + if (flag == 0) + 8023f9c: e0bff917 ldw r2,-28(fp) + 8023fa0: 1000091e bne r2,zero,8023fc8 + /* yup */ + MEMMOVE(&arwp->data[AR_THA], arphdr->ar_tha, 6); + 8023fa4: e0bffb17 ldw r2,-20(fp) + 8023fa8: 10c00484 addi r3,r2,18 + 8023fac: e0bffc17 ldw r2,-16(fp) + 8023fb0: 10800504 addi r2,r2,20 + 8023fb4: 01800184 movi r6,6 + 8023fb8: 100b883a mov r5,r2 + 8023fbc: 1809883a mov r4,r3 + 8023fc0: 80087b80 call 80087b8 + 8023fc4: 00000806 br 8023fe8 + else + /* nope */ + MEMMOVE(&arwp->data[AR_THA], arphdr->ar_sha, 6); + 8023fc8: e0bffb17 ldw r2,-20(fp) + 8023fcc: 10c00484 addi r3,r2,18 + 8023fd0: e0bffc17 ldw r2,-16(fp) + 8023fd4: 10800204 addi r2,r2,8 + 8023fd8: 01800184 movi r6,6 + 8023fdc: 100b883a mov r5,r2 + 8023fe0: 1809883a mov r4,r3 + 8023fe4: 80087b80 call 80087b8 + + MEMMOVE(&arwp->data[AR_TPA], &arphdr->ar_tpa, 4); + 8023fe8: e0bffb17 ldw r2,-20(fp) + 8023fec: 10c00604 addi r3,r2,24 + 8023ff0: e0bffc17 ldw r2,-16(fp) + 8023ff4: 10800704 addi r2,r2,28 + 8023ff8: 01800104 movi r6,4 + 8023ffc: 100b883a mov r5,r2 + 8024000: 1809883a mov r4,r3 + 8024004: 80087b80 call 80087b8 + } +#endif /* IEEE_802_3 */ + +#ifndef IEEE_802_3_ONLY + /* send arp request - if a packet oriented send exists, use it: */ + if (net->pkt_send) + 8024008: e0bffa17 ldw r2,-24(fp) + 802400c: 10800417 ldw r2,16(r2) + 8024010: 10000526 beq r2,zero,8024028 + net->pkt_send(arppkt); /* driver should free arppkt later */ + 8024014: e0bffa17 ldw r2,-24(fp) + 8024018: 10800417 ldw r2,16(r2) + 802401c: e13ffe17 ldw r4,-8(fp) + 8024020: 103ee83a callr r2 + 8024024: 00000f06 br 8024064 + else /* use old raw send */ + { + net->raw_send(arppkt->net, arppkt->nb_buff, arpsize); + 8024028: e0bffa17 ldw r2,-24(fp) + 802402c: 10800317 ldw r2,12(r2) + 8024030: e0fffe17 ldw r3,-8(fp) + 8024034: 19000617 ldw r4,24(r3) + 8024038: e0fffe17 ldw r3,-8(fp) + 802403c: 18c00117 ldw r3,4(r3) + 8024040: 01800c04 movi r6,48 + 8024044: 180b883a mov r5,r3 + 8024048: 103ee83a callr r2 + LOCK_NET_RESOURCE(FREEQ_RESID); + 802404c: 01000084 movi r4,2 + 8024050: 8028f380 call 8028f38 + pk_free(arppkt); + 8024054: e13ffe17 ldw r4,-8(fp) + 8024058: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 802405c: 01000084 movi r4,2 + 8024060: 8028ff40 call 8028ff4 + } + arpReqsOut++; + 8024064: d0a06117 ldw r2,-32380(gp) + 8024068: 10800044 addi r2,r2,1 + 802406c: d0a06115 stw r2,-32380(gp) + LOCK_NET_RESOURCE(FREEQ_RESID); + pk_free(arppkt); + UNLOCK_NET_RESOURCE(FREEQ_RESID); +#endif /* IEEE_802_3_ONLY */ + + return ENP_SEND_PENDING; + 8024070: 00800044 movi r2,1 +} + 8024074: e037883a mov sp,fp + 8024078: dfc00117 ldw ra,4(sp) + 802407c: df000017 ldw fp,0(sp) + 8024080: dec00204 addi sp,sp,8 + 8024084: f800283a ret + +08024088 : + * RETURNS: Returns NET pointer, or NULL if out of range + */ + +NET +if_getbynum(int ifnum) +{ + 8024088: defffc04 addi sp,sp,-16 + 802408c: dfc00315 stw ra,12(sp) + 8024090: df000215 stw fp,8(sp) + 8024094: df000204 addi fp,sp,8 + 8024098: e13ffe15 stw r4,-8(fp) + NET ifp; + for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next) + 802409c: 008201b4 movhi r2,2054 + 80240a0: 10b6a617 ldw r2,-9576(r2) + 80240a4: e0bfff15 stw r2,-4(fp) + 80240a8: 00000906 br 80240d0 + { + if(ifnum-- == 0) + 80240ac: e0bffe17 ldw r2,-8(fp) + 80240b0: 10ffffc4 addi r3,r2,-1 + 80240b4: e0fffe15 stw r3,-8(fp) + 80240b8: 1000021e bne r2,zero,80240c4 + return ifp; + 80240bc: e0bfff17 ldw r2,-4(fp) + 80240c0: 00000706 br 80240e0 + for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next) + 80240c4: e0bfff17 ldw r2,-4(fp) + 80240c8: 10800017 ldw r2,0(r2) + 80240cc: e0bfff15 stw r2,-4(fp) + 80240d0: e0bfff17 ldw r2,-4(fp) + 80240d4: 103ff51e bne r2,zero,80240ac + } + dtrap(); + 80240d8: 8028cd40 call 8028cd4 + return NULL; /* list is not long enough */ + 80240dc: 0005883a mov r2,zero +} + 80240e0: e037883a mov sp,fp + 80240e4: dfc00117 ldw ra,4(sp) + 80240e8: df000017 ldw fp,0(sp) + 80240ec: dec00204 addi sp,sp,8 + 80240f0: f800283a ret + +080240f4 : + * RETURNS: Returns TRUE if broadcast, else false. + */ + +int +isbcast(NET ifc, unsigned char * addr) +{ + 80240f4: defffd04 addi sp,sp,-12 + 80240f8: df000215 stw fp,8(sp) + 80240fc: df000204 addi fp,sp,8 + 8024100: e13fff15 stw r4,-4(fp) + 8024104: e17ffe15 stw r5,-8(fp) +#if (ALIGN_TYPE > 2) + /* On systems with 32bit alignment requirements we have to make + * sure our tests are aligned. Specifically, this results in "data + * abort" errors on the Samsung/ARM port. + */ + if((u_long)addr & (ALIGN_TYPE - 1)) + 8024108: e0bffe17 ldw r2,-8(fp) + 802410c: 108000cc andi r2,r2,3 + 8024110: 10000e26 beq r2,zero,802414c + { + /* check first two bytes */ + if ((u_short)*(u_short*)(addr) != 0xFFFF) + 8024114: e0bffe17 ldw r2,-8(fp) + 8024118: 1080000b ldhu r2,0(r2) + 802411c: 10ffffcc andi r3,r2,65535 + 8024120: 00bfffd4 movui r2,65535 + 8024124: 18800226 beq r3,r2,8024130 + return(FALSE); + 8024128: 0005883a mov r2,zero + 802412c: 00002206 br 80241b8 + if ((u_long)(*(u_long*)(addr + 2)) != 0xFFFFFFFF) + 8024130: e0bffe17 ldw r2,-8(fp) + 8024134: 10800084 addi r2,r2,2 + 8024138: 10800017 ldw r2,0(r2) + 802413c: 10bfffe0 cmpeqi r2,r2,-1 + 8024140: 1000101e bne r2,zero,8024184 + return FALSE; + 8024144: 0005883a mov r2,zero + 8024148: 00001b06 br 80241b8 +#endif /* ALIGN_TYPE > 4 */ + { + /* check first four bytes for all ones. Since this is the fastest + * test, do it first + */ + if ((u_long)(*(u_long*)addr) != 0xFFFFFFFF) + 802414c: e0bffe17 ldw r2,-8(fp) + 8024150: 10800017 ldw r2,0(r2) + 8024154: 10bfffe0 cmpeqi r2,r2,-1 + 8024158: 1000021e bne r2,zero,8024164 + return FALSE; + 802415c: 0005883a mov r2,zero + 8024160: 00001506 br 80241b8 + + /* check last two bytes */ + if ((u_short)*(u_short*)(addr+4) != 0xFFFF) + 8024164: e0bffe17 ldw r2,-8(fp) + 8024168: 10800104 addi r2,r2,4 + 802416c: 1080000b ldhu r2,0(r2) + 8024170: 10ffffcc andi r3,r2,65535 + 8024174: 00bfffd4 movui r2,65535 + 8024178: 18800226 beq r3,r2,8024184 + return(FALSE); + 802417c: 0005883a mov r2,zero + 8024180: 00000d06 br 80241b8 + } + + /* now reject any line type packets which don't support broadcast */ + if ((ifc->n_mib->ifType == PPP) || + 8024184: e0bfff17 ldw r2,-4(fp) + 8024188: 10802717 ldw r2,156(r2) + 802418c: 10800217 ldw r2,8(r2) + 8024190: 108005e0 cmpeqi r2,r2,23 + 8024194: 1000051e bne r2,zero,80241ac + (ifc->n_mib->ifType == SLIP)) + 8024198: e0bfff17 ldw r2,-4(fp) + 802419c: 10802717 ldw r2,156(r2) + 80241a0: 10800217 ldw r2,8(r2) + if ((ifc->n_mib->ifType == PPP) || + 80241a4: 10800718 cmpnei r2,r2,28 + 80241a8: 1000021e bne r2,zero,80241b4 + { + return FALSE; + 80241ac: 0005883a mov r2,zero + 80241b0: 00000106 br 80241b8 + } + + /* passed all tests, must be broadcast */ + return(TRUE); + 80241b4: 00800044 movi r2,1 +} + 80241b8: e037883a mov sp,fp + 80241bc: df000017 ldw fp,0(sp) + 80241c0: dec00104 addi sp,sp,4 + 80241c4: f800283a ret + +080241c8 : + * RETURNS: Returns 0 if OK, else non-zero error code. + */ + +int +reg_type(unshort type) +{ + 80241c8: defffb04 addi sp,sp,-20 + 80241cc: dfc00415 stw ra,16(sp) + 80241d0: df000315 stw fp,12(sp) + 80241d4: df000304 addi fp,sp,12 + 80241d8: 2005883a mov r2,r4 + 80241dc: e0bffd0d sth r2,-12(fp) + if (i >= PLLISTLEN) + return ENP_RESOURCE; +#endif /* DYNAMIC_IFACES */ + + /* loop thru list of nets, making them all look at new type */ + for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next) + 80241e0: 008201b4 movhi r2,2054 + 80241e4: 10b6a617 ldw r2,-9576(r2) + 80241e8: e0bfff15 stw r2,-4(fp) + 80241ec: 00001106 br 8024234 + { + if (ifp->n_reg_type) /* make sure call exists */ + 80241f0: e0bfff17 ldw r2,-4(fp) + 80241f4: 10800617 ldw r2,24(r2) + 80241f8: 10000b26 beq r2,zero,8024228 + { + e = (ifp->n_reg_type)(type, ifp); + 80241fc: e0bfff17 ldw r2,-4(fp) + 8024200: 10800617 ldw r2,24(r2) + 8024204: e0fffd0b ldhu r3,-12(fp) + 8024208: e17fff17 ldw r5,-4(fp) + 802420c: 1809883a mov r4,r3 + 8024210: 103ee83a callr r2 + 8024214: e0bffe15 stw r2,-8(fp) + if (e) + 8024218: e0bffe17 ldw r2,-8(fp) + 802421c: 10000226 beq r2,zero,8024228 + return e; /* bails out if error */ + 8024220: e0bffe17 ldw r2,-8(fp) + 8024224: 00000606 br 8024240 + for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next) + 8024228: e0bfff17 ldw r2,-4(fp) + 802422c: 10800017 ldw r2,0(r2) + 8024230: e0bfff15 stw r2,-4(fp) + 8024234: e0bfff17 ldw r2,-4(fp) + 8024238: 103fed1e bne r2,zero,80241f0 + } + } + return 0; /* OK code */ + 802423c: 0005883a mov r2,zero +} + 8024240: e037883a mov sp,fp + 8024244: dfc00117 ldw ra,4(sp) + 8024248: df000017 ldw fp,0(sp) + 802424c: dec00204 addi sp,sp,8 + 8024250: f800283a ret + +08024254 : + */ + + /* kill this NETs sockets */ +void +if_killsocks(NET ifp) +{ + 8024254: defffa04 addi sp,sp,-24 + 8024258: dfc00515 stw ra,20(sp) + 802425c: df000415 stw fp,16(sp) + 8024260: df000404 addi fp,sp,16 + 8024264: e13ffc15 stw r4,-16(fp) + struct socket * so; + struct socket * next; + NET so_ifp; /* interface of sockets in list */ + + /* reset any sockets with this iface IP address */ + so = (struct socket *)(soq.q_head); + 8024268: 008201b4 movhi r2,2054 + 802426c: 10b87117 ldw r2,-7740(r2) + 8024270: e0bfff15 stw r2,-4(fp) + while(so) + 8024274: 00001306 br 80242c4 + { + if(so->so_pcb) + 8024278: e0bfff17 ldw r2,-4(fp) + 802427c: 10800117 ldw r2,4(r2) + 8024280: 10000526 beq r2,zero,8024298 + so_ifp = so->so_pcb->ifp; + 8024284: e0bfff17 ldw r2,-4(fp) + 8024288: 10800117 ldw r2,4(r2) + 802428c: 10800a17 ldw r2,40(r2) + 8024290: e0bffe15 stw r2,-8(fp) + 8024294: 00000106 br 802429c + else + so_ifp = NULL; + 8024298: e03ffe15 stw zero,-8(fp) + next = (struct socket *)so->next; + 802429c: e0bfff17 ldw r2,-4(fp) + 80242a0: 10800017 ldw r2,0(r2) + 80242a4: e0bffd15 stw r2,-12(fp) + if (so_ifp == ifp) + 80242a8: e0fffe17 ldw r3,-8(fp) + 80242ac: e0bffc17 ldw r2,-16(fp) + 80242b0: 1880021e bne r3,r2,80242bc + { + /* this is a direct heavy-handed close. A reset is sent + * and all data is lost. The user should really have closed + * all the sockets gracfully first.... + */ + soabort(so); + 80242b4: e13fff17 ldw r4,-4(fp) + 80242b8: 802d6fc0 call 802d6fc + } + so = next; + 80242bc: e0bffd17 ldw r2,-12(fp) + 80242c0: e0bfff15 stw r2,-4(fp) + while(so) + 80242c4: e0bfff17 ldw r2,-4(fp) + 80242c8: 103feb1e bne r2,zero,8024278 + } +} + 80242cc: 0001883a nop + 80242d0: e037883a mov sp,fp + 80242d4: dfc00117 ldw ra,4(sp) + 80242d8: df000017 ldw fp,0(sp) + 80242dc: dec00204 addi sp,sp,8 + 80242e0: f800283a ret + +080242e4 : + * a non-zero error code + */ + +int +Netinit() +{ + 80242e4: defffc04 addi sp,sp,-16 + 80242e8: dfc00315 stw ra,12(sp) + 80242ec: df000215 stw fp,8(sp) + 80242f0: df000204 addi fp,sp,8 +#ifndef MULTI_HOMED + ifNumber = 1; /* prevents weird behavior below... */ +#endif + + /* set our largest header size and frames size */ + for (i = 0; i < (int)ifNumber; i++) + 80242f4: e03fff15 stw zero,-4(fp) + 80242f8: 00003c06 br 80243ec + { + /* sanity check on mtu, et.al. We added this because earlier + * drivers were sloppy about setting them, but new + * logic depends on these sizes. + */ + if (nets[i]->n_mib->ifType == ETHERNET) /* ethernet? */ + 80242fc: e0bfff17 ldw r2,-4(fp) + 8024300: 100690ba slli r3,r2,2 + 8024304: 008201b4 movhi r2,2054 + 8024308: 1885883a add r2,r3,r2 + 802430c: 10b77017 ldw r2,-8768(r2) + 8024310: 10802717 ldw r2,156(r2) + 8024314: 10800217 ldw r2,8(r2) + 8024318: 10800198 cmpnei r2,r2,6 + 802431c: 10001c1e bne r2,zero,8024390 + { + if (nets[i]->n_mtu == 0) /* let device code override */ + 8024320: e0bfff17 ldw r2,-4(fp) + 8024324: 100690ba slli r3,r2,2 + 8024328: 008201b4 movhi r2,2054 + 802432c: 1885883a add r2,r3,r2 + 8024330: 10b77017 ldw r2,-8768(r2) + 8024334: 10800917 ldw r2,36(r2) + 8024338: 1000071e bne r2,zero,8024358 + nets[i]->n_mtu = 1514; + 802433c: e0bfff17 ldw r2,-4(fp) + 8024340: 100690ba slli r3,r2,2 + 8024344: 008201b4 movhi r2,2054 + 8024348: 1885883a add r2,r3,r2 + 802434c: 10b77017 ldw r2,-8768(r2) + 8024350: 00c17a84 movi r3,1514 + 8024354: 10c00915 stw r3,36(r2) + + if (nets[i]->n_lnh == 0) + 8024358: e0bfff17 ldw r2,-4(fp) + 802435c: 100690ba slli r3,r2,2 + 8024360: 008201b4 movhi r2,2054 + 8024364: 1885883a add r2,r3,r2 + 8024368: 10b77017 ldw r2,-8768(r2) + 802436c: 10800817 ldw r2,32(r2) + 8024370: 1000071e bne r2,zero,8024390 + { +#ifdef IEEE_802_3 + nets[i]->n_lnh = ETHHDR_SIZE + sizeof(struct snap_hdr); +#else + nets[i]->n_lnh = ETHHDR_SIZE; + 8024374: e0bfff17 ldw r2,-4(fp) + 8024378: 100690ba slli r3,r2,2 + 802437c: 008201b4 movhi r2,2054 + 8024380: 1885883a add r2,r3,r2 + 8024384: 10b77017 ldw r2,-8768(r2) + 8024388: 00c00404 movi r3,16 + 802438c: 10c00815 stw r3,32(r2) + { + continue; + } +#endif /* IP_V6 */ + + MaxLnh = max(MaxLnh, nets[i]->n_lnh); + 8024390: e0bfff17 ldw r2,-4(fp) + 8024394: 100690ba slli r3,r2,2 + 8024398: 008201b4 movhi r2,2054 + 802439c: 1885883a add r2,r3,r2 + 80243a0: 10b77017 ldw r2,-8768(r2) + 80243a4: 10800817 ldw r2,32(r2) + 80243a8: d0e06417 ldw r3,-32368(gp) + 80243ac: 10c0010e bge r2,r3,80243b4 + 80243b0: 1805883a mov r2,r3 + 80243b4: d0a06415 stw r2,-32368(gp) + MaxMtu = max(MaxMtu, nets[i]->n_mtu); + 80243b8: e0bfff17 ldw r2,-4(fp) + 80243bc: 100690ba slli r3,r2,2 + 80243c0: 008201b4 movhi r2,2054 + 80243c4: 1885883a add r2,r3,r2 + 80243c8: 10b77017 ldw r2,-8768(r2) + 80243cc: 10800917 ldw r2,36(r2) + 80243d0: d0e06517 ldw r3,-32364(gp) + 80243d4: 10c0010e bge r2,r3,80243dc + 80243d8: 1805883a mov r2,r3 + 80243dc: d0a06515 stw r2,-32364(gp) + for (i = 0; i < (int)ifNumber; i++) + 80243e0: e0bfff17 ldw r2,-4(fp) + 80243e4: 10800044 addi r2,r2,1 + 80243e8: e0bfff15 stw r2,-4(fp) + 80243ec: d0a06717 ldw r2,-32356(gp) + 80243f0: 1007883a mov r3,r2 + 80243f4: e0bfff17 ldw r2,-4(fp) + 80243f8: 10ffc016 blt r2,r3,80242fc + } + + /* set up the received packet queue */ + rcvdq.q_head = rcvdq.q_tail = NULL; + 80243fc: 008201b4 movhi r2,2054 + 8024400: 1036ac15 stw zero,-9552(r2) + 8024404: 008201b4 movhi r2,2054 + 8024408: 10f6ac17 ldw r3,-9552(r2) + 802440c: 008201b4 movhi r2,2054 + 8024410: 10f6ab15 stw r3,-9556(r2) + rcvdq.q_max = rcvdq.q_min = rcvdq.q_len = 0; + 8024414: 008201b4 movhi r2,2054 + 8024418: 1036ad15 stw zero,-9548(r2) + 802441c: 008201b4 movhi r2,2054 + 8024420: 10f6ad17 ldw r3,-9548(r2) + 8024424: 008201b4 movhi r2,2054 + 8024428: 10f6af15 stw r3,-9540(r2) + 802442c: 008201b4 movhi r2,2054 + 8024430: 10f6af17 ldw r3,-9540(r2) + 8024434: 008201b4 movhi r2,2054 + 8024438: 10f6ae15 stw r3,-9544(r2) + + /* initialize freeq */ + LOCK_NET_RESOURCE(FREEQ_RESID); + 802443c: 01000084 movi r4,2 + 8024440: 8028f380 call 8028f38 + e = pk_init(); + 8024444: 80281a80 call 80281a8 + 8024448: e0bffe15 stw r2,-8(fp) + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 802444c: 01000084 movi r4,2 + 8024450: 8028ff40 call 8028ff4 + if (e) /* report error (memory ran out?) */ + 8024454: e0bffe17 ldw r2,-8(fp) + 8024458: 10000226 beq r2,zero,8024464 + return e; + 802445c: e0bffe17 ldw r2,-8(fp) + 8024460: 0000cf06 br 80247a0 + + /* packet buffers in freeq are now all set. */ + exit_hook(netclose); /* Clean up nets when we are unloaded */ + 8024464: 010200b4 movhi r4,2050 + 8024468: 21123904 addi r4,r4,18660 + 802446c: 80251e40 call 80251e4 + + /* now do the per-IP interface initializations */ + for (i = 0; i < (int)ifNumber; i++) + 8024470: e03fff15 stw zero,-4(fp) + 8024474: 0000c506 br 802478c + { + if (nets[i]->n_init != NULL) /* If iface has init routine... */ + 8024478: e0bfff17 ldw r2,-4(fp) + 802447c: 100690ba slli r3,r2,2 + 8024480: 008201b4 movhi r2,2054 + 8024484: 1885883a add r2,r3,r2 + 8024488: 10b77017 ldw r2,-8768(r2) + 802448c: 10800217 ldw r2,8(r2) + 8024490: 10007726 beq r2,zero,8024670 + { + if ((e = (*nets[i]->n_init)(i)) != 0) /* call init routine */ + 8024494: e0bfff17 ldw r2,-4(fp) + 8024498: 100690ba slli r3,r2,2 + 802449c: 008201b4 movhi r2,2054 + 80244a0: 1885883a add r2,r3,r2 + 80244a4: 10b77017 ldw r2,-8768(r2) + 80244a8: 10800217 ldw r2,8(r2) + 80244ac: e13fff17 ldw r4,-4(fp) + 80244b0: 103ee83a callr r2 + 80244b4: e0bffe15 stw r2,-8(fp) + 80244b8: e0bffe17 ldw r2,-8(fp) + 80244bc: 10000e26 beq r2,zero,80244f8 + { + dprintf("init error %d on net[%d]\n", e, i); + 80244c0: e1bfff17 ldw r6,-4(fp) + 80244c4: e17ffe17 ldw r5,-8(fp) + 80244c8: 01020174 movhi r4,2053 + 80244cc: 2126bd04 addi r4,r4,-25868 + 80244d0: 8002c780 call 8002c78 + nets[i]->n_mib->ifOperStatus = NI_DOWN; + 80244d4: e0bfff17 ldw r2,-4(fp) + 80244d8: 100690ba slli r3,r2,2 + 80244dc: 008201b4 movhi r2,2054 + 80244e0: 1885883a add r2,r3,r2 + 80244e4: 10b77017 ldw r2,-8768(r2) + 80244e8: 10802717 ldw r2,156(r2) + 80244ec: 00c00084 movi r3,2 + 80244f0: 10c00715 stw r3,28(r2) + continue; /* ignore ifaces which fail */ + 80244f4: 0000a206 br 8024780 + } + /* If interface is ethernet, set bcast flag bit. This + * should really be done by the init routine, but we handle it + * here to support MAC drivers which predate the flags field. + */ + if(nets[i]->n_mib->ifType == ETHERNET) + 80244f8: e0bfff17 ldw r2,-4(fp) + 80244fc: 100690ba slli r3,r2,2 + 8024500: 008201b4 movhi r2,2054 + 8024504: 1885883a add r2,r3,r2 + 8024508: 10b77017 ldw r2,-8768(r2) + 802450c: 10802717 ldw r2,156(r2) + 8024510: 10800217 ldw r2,8(r2) + 8024514: 10800198 cmpnei r2,r2,6 + 8024518: 10000d1e bne r2,zero,8024550 + nets[i]->n_flags |= NF_BCAST; + 802451c: e0bfff17 ldw r2,-4(fp) + 8024520: 100690ba slli r3,r2,2 + 8024524: 008201b4 movhi r2,2054 + 8024528: 1885883a add r2,r3,r2 + 802452c: 10b77017 ldw r2,-8768(r2) + 8024530: 10c02a17 ldw r3,168(r2) + 8024534: e0bfff17 ldw r2,-4(fp) + 8024538: 100890ba slli r4,r2,2 + 802453c: 008201b4 movhi r2,2054 + 8024540: 2085883a add r2,r4,r2 + 8024544: 10b77017 ldw r2,-8768(r2) + 8024548: 18c00054 ori r3,r3,1 + 802454c: 10c02a15 stw r3,168(r2) + + /* set ifAdminStatus in case init() routine forgot to. IfOperStatus + * is not nessecarily up at this point, as in the case of a modem which + * is now in autoanswer mode. + */ + nets[i]->n_mib->ifAdminStatus = NI_UP; + 8024550: e0bfff17 ldw r2,-4(fp) + 8024554: 100690ba slli r3,r2,2 + 8024558: 008201b4 movhi r2,2054 + 802455c: 1885883a add r2,r3,r2 + 8024560: 10b77017 ldw r2,-8768(r2) + 8024564: 10802717 ldw r2,156(r2) + 8024568: 00c00044 movi r3,1 + 802456c: 10c00615 stw r3,24(r2) + + /* assign default names to unnamed ifaces */ + if(nets[i]->name[0] == 0) /* no name set by prep or init */ + 8024570: e0bfff17 ldw r2,-4(fp) + 8024574: 100690ba slli r3,r2,2 + 8024578: 008201b4 movhi r2,2054 + 802457c: 1885883a add r2,r3,r2 + 8024580: 10b77017 ldw r2,-8768(r2) + 8024584: 10800103 ldbu r2,4(r2) + 8024588: 10803fcc andi r2,r2,255 + 802458c: 1080201c xori r2,r2,128 + 8024590: 10bfe004 addi r2,r2,-128 + 8024594: 1000361e bne r2,zero,8024670 + { + if(nets[i]->n_mib->ifType == ETHERNET) + 8024598: e0bfff17 ldw r2,-4(fp) + 802459c: 100690ba slli r3,r2,2 + 80245a0: 008201b4 movhi r2,2054 + 80245a4: 1885883a add r2,r3,r2 + 80245a8: 10b77017 ldw r2,-8768(r2) + 80245ac: 10802717 ldw r2,156(r2) + 80245b0: 10800217 ldw r2,8(r2) + 80245b4: 10800198 cmpnei r2,r2,6 + 80245b8: 10000f1e bne r2,zero,80245f8 + { + nets[i]->name[0] = 'e'; /* "et1", "et2", etc. */ + 80245bc: e0bfff17 ldw r2,-4(fp) + 80245c0: 100690ba slli r3,r2,2 + 80245c4: 008201b4 movhi r2,2054 + 80245c8: 1885883a add r2,r3,r2 + 80245cc: 10b77017 ldw r2,-8768(r2) + 80245d0: 00c01944 movi r3,101 + 80245d4: 10c00105 stb r3,4(r2) + nets[i]->name[1] = 't'; + 80245d8: e0bfff17 ldw r2,-4(fp) + 80245dc: 100690ba slli r3,r2,2 + 80245e0: 008201b4 movhi r2,2054 + 80245e4: 1885883a add r2,r3,r2 + 80245e8: 10b77017 ldw r2,-8768(r2) + 80245ec: 00c01d04 movi r3,116 + 80245f0: 10c00145 stb r3,5(r2) + 80245f4: 00000e06 br 8024630 + } + else + { + nets[i]->name[0] = 'i'; /* "if1", "if2", etc. */ + 80245f8: e0bfff17 ldw r2,-4(fp) + 80245fc: 100690ba slli r3,r2,2 + 8024600: 008201b4 movhi r2,2054 + 8024604: 1885883a add r2,r3,r2 + 8024608: 10b77017 ldw r2,-8768(r2) + 802460c: 00c01a44 movi r3,105 + 8024610: 10c00105 stb r3,4(r2) + nets[i]->name[1] = 'f'; + 8024614: e0bfff17 ldw r2,-4(fp) + 8024618: 100690ba slli r3,r2,2 + 802461c: 008201b4 movhi r2,2054 + 8024620: 1885883a add r2,r3,r2 + 8024624: 10b77017 ldw r2,-8768(r2) + 8024628: 00c01984 movi r3,102 + 802462c: 10c00145 stb r3,5(r2) + } + nets[i]->name[2] = (char)(i + '1'); + 8024630: e0bfff17 ldw r2,-4(fp) + 8024634: 10800c44 addi r2,r2,49 + 8024638: 1009883a mov r4,r2 + 802463c: e0bfff17 ldw r2,-4(fp) + 8024640: 100690ba slli r3,r2,2 + 8024644: 008201b4 movhi r2,2054 + 8024648: 1885883a add r2,r3,r2 + 802464c: 10b77017 ldw r2,-8768(r2) + 8024650: 2007883a mov r3,r4 + 8024654: 10c00185 stb r3,6(r2) + nets[i]->name[3] = '\0'; + 8024658: e0bfff17 ldw r2,-4(fp) + 802465c: 100690ba slli r3,r2,2 + 8024660: 008201b4 movhi r2,2054 + 8024664: 1885883a add r2,r3,r2 + 8024668: 10b77017 ldw r2,-8768(r2) + 802466c: 100001c5 stb zero,7(r2) + } + } + /* check on subnet routing - if no mask then make one */ + fixup_subnet_mask(i); /* make mask for this net */ + 8024670: e13fff17 ldw r4,-4(fp) + 8024674: 80247b40 call 80247b4 + + /* build broadcast addresses */ + if(nets[i]->n_ipaddr != 0) + 8024678: e0bfff17 ldw r2,-4(fp) + 802467c: 100690ba slli r3,r2,2 + 8024680: 008201b4 movhi r2,2054 + 8024684: 1885883a add r2,r3,r2 + 8024688: 10b77017 ldw r2,-8768(r2) + 802468c: 10800a17 ldw r2,40(r2) + 8024690: 10003b26 beq r2,zero,8024780 + { + nets[i]->n_netbr = nets[i]->n_ipaddr | ~nets[i]->snmask; + 8024694: e0bfff17 ldw r2,-4(fp) + 8024698: 100690ba slli r3,r2,2 + 802469c: 008201b4 movhi r2,2054 + 80246a0: 1885883a add r2,r3,r2 + 80246a4: 10b77017 ldw r2,-8768(r2) + 80246a8: 11000a17 ldw r4,40(r2) + 80246ac: e0bfff17 ldw r2,-4(fp) + 80246b0: 100690ba slli r3,r2,2 + 80246b4: 008201b4 movhi r2,2054 + 80246b8: 1885883a add r2,r3,r2 + 80246bc: 10b77017 ldw r2,-8768(r2) + 80246c0: 10800c17 ldw r2,48(r2) + 80246c4: 0086303a nor r3,zero,r2 + 80246c8: e0bfff17 ldw r2,-4(fp) + 80246cc: 100a90ba slli r5,r2,2 + 80246d0: 008201b4 movhi r2,2054 + 80246d4: 2885883a add r2,r5,r2 + 80246d8: 10b77017 ldw r2,-8768(r2) + 80246dc: 20c6b03a or r3,r4,r3 + 80246e0: 10c00e15 stw r3,56(r2) + nets[i]->n_netbr42 = nets[i]->n_ipaddr & nets[i]->snmask; + 80246e4: e0bfff17 ldw r2,-4(fp) + 80246e8: 100690ba slli r3,r2,2 + 80246ec: 008201b4 movhi r2,2054 + 80246f0: 1885883a add r2,r3,r2 + 80246f4: 10b77017 ldw r2,-8768(r2) + 80246f8: 11000a17 ldw r4,40(r2) + 80246fc: e0bfff17 ldw r2,-4(fp) + 8024700: 100690ba slli r3,r2,2 + 8024704: 008201b4 movhi r2,2054 + 8024708: 1885883a add r2,r3,r2 + 802470c: 10b77017 ldw r2,-8768(r2) + 8024710: 10c00c17 ldw r3,48(r2) + 8024714: e0bfff17 ldw r2,-4(fp) + 8024718: 100a90ba slli r5,r2,2 + 802471c: 008201b4 movhi r2,2054 + 8024720: 2885883a add r2,r5,r2 + 8024724: 10b77017 ldw r2,-8768(r2) + 8024728: 20c6703a and r3,r4,r3 + 802472c: 10c00f15 stw r3,60(r2) + nets[i]->n_subnetbr = nets[i]->n_ipaddr | ~nets[i]->snmask; + 8024730: e0bfff17 ldw r2,-4(fp) + 8024734: 100690ba slli r3,r2,2 + 8024738: 008201b4 movhi r2,2054 + 802473c: 1885883a add r2,r3,r2 + 8024740: 10b77017 ldw r2,-8768(r2) + 8024744: 11000a17 ldw r4,40(r2) + 8024748: e0bfff17 ldw r2,-4(fp) + 802474c: 100690ba slli r3,r2,2 + 8024750: 008201b4 movhi r2,2054 + 8024754: 1885883a add r2,r3,r2 + 8024758: 10b77017 ldw r2,-8768(r2) + 802475c: 10800c17 ldw r2,48(r2) + 8024760: 0086303a nor r3,zero,r2 + 8024764: e0bfff17 ldw r2,-4(fp) + 8024768: 100a90ba slli r5,r2,2 + 802476c: 008201b4 movhi r2,2054 + 8024770: 2885883a add r2,r5,r2 + 8024774: 10b77017 ldw r2,-8768(r2) + 8024778: 20c6b03a or r3,r4,r3 + 802477c: 10c01015 stw r3,64(r2) + for (i = 0; i < (int)ifNumber; i++) + 8024780: e0bfff17 ldw r2,-4(fp) + 8024784: 10800044 addi r2,r2,1 + 8024788: e0bfff15 stw r2,-4(fp) + 802478c: d0a06717 ldw r2,-32356(gp) + 8024790: 1007883a mov r3,r2 + 8024794: e0bfff17 ldw r2,-4(fp) + 8024798: 10ff3716 blt r2,r3,8024478 +#if defined(DYNAMIC_IFACES) && defined(IN_MENUS) + /* Install dynamic iface menu */ + install_menu(&dynif_menu[0]); +#endif /* DYNAMIC_IFACES && IN_MENUS */ + + return(0); + 802479c: 0005883a mov r2,zero +} + 80247a0: e037883a mov sp,fp + 80247a4: dfc00117 ldw ra,4(sp) + 80247a8: df000017 ldw fp,0(sp) + 80247ac: dec00204 addi sp,sp,8 + 80247b0: f800283a ret + +080247b4 : + * RETURNS: + */ + +void +fixup_subnet_mask(int netnum) /* which of the nets[] to do. */ +{ + 80247b4: defffc04 addi sp,sp,-16 + 80247b8: dfc00315 stw ra,12(sp) + 80247bc: df000215 stw fp,8(sp) + 80247c0: df000204 addi fp,sp,8 + 80247c4: e13ffe15 stw r4,-8(fp) + u_long smask; + + if (nets[netnum]->snmask) /* if mask is already set, don't bother */ + 80247c8: e0bffe17 ldw r2,-8(fp) + 80247cc: 100690ba slli r3,r2,2 + 80247d0: 008201b4 movhi r2,2054 + 80247d4: 1885883a add r2,r3,r2 + 80247d8: 10b77017 ldw r2,-8768(r2) + 80247dc: 10800c17 ldw r2,48(r2) + 80247e0: 10003a1e bne r2,zero,80248cc + return; + + /* things depending on IP address class: */ + if ((nets[netnum]->n_ipaddr & AMASK) == AADDR) + 80247e4: e0bffe17 ldw r2,-8(fp) + 80247e8: 100690ba slli r3,r2,2 + 80247ec: 008201b4 movhi r2,2054 + 80247f0: 1885883a add r2,r3,r2 + 80247f4: 10b77017 ldw r2,-8768(r2) + 80247f8: 10800a17 ldw r2,40(r2) + 80247fc: 1080200c andi r2,r2,128 + 8024800: 1000031e bne r2,zero,8024810 + smask = 0xFF000000L; + 8024804: 00bfc034 movhi r2,65280 + 8024808: e0bfff15 stw r2,-4(fp) + 802480c: 00001b06 br 802487c + else if((nets[netnum]->n_ipaddr & BMASK) == BADDR) + 8024810: e0bffe17 ldw r2,-8(fp) + 8024814: 100690ba slli r3,r2,2 + 8024818: 008201b4 movhi r2,2054 + 802481c: 1885883a add r2,r3,r2 + 8024820: 10b77017 ldw r2,-8768(r2) + 8024824: 10800a17 ldw r2,40(r2) + 8024828: 1080300c andi r2,r2,192 + 802482c: 10802018 cmpnei r2,r2,128 + 8024830: 1000031e bne r2,zero,8024840 + smask = 0xFFFF0000L; + 8024834: 00bffff4 movhi r2,65535 + 8024838: e0bfff15 stw r2,-4(fp) + 802483c: 00000f06 br 802487c + else if((nets[netnum]->n_ipaddr & CMASK) == CADDR) + 8024840: e0bffe17 ldw r2,-8(fp) + 8024844: 100690ba slli r3,r2,2 + 8024848: 008201b4 movhi r2,2054 + 802484c: 1885883a add r2,r3,r2 + 8024850: 10b77017 ldw r2,-8768(r2) + 8024854: 10800a17 ldw r2,40(r2) + 8024858: 1080380c andi r2,r2,224 + 802485c: 10803018 cmpnei r2,r2,192 + 8024860: 1000031e bne r2,zero,8024870 + smask = 0xFFFFFF00L; + 8024864: 00bfc004 movi r2,-256 + 8024868: e0bfff15 stw r2,-4(fp) + 802486c: 00000306 br 802487c + else + { + dtrap(); /* bad logic or setup values */ + 8024870: 8028cd40 call 8028cd4 + smask = 0xFFFFFF00L; + 8024874: 00bfc004 movi r2,-256 + 8024878: e0bfff15 stw r2,-4(fp) + } + nets[netnum]->snmask = htonl(smask); + 802487c: e0bfff17 ldw r2,-4(fp) + 8024880: 1006d63a srli r3,r2,24 + 8024884: e0bfff17 ldw r2,-4(fp) + 8024888: 1004d23a srli r2,r2,8 + 802488c: 10bfc00c andi r2,r2,65280 + 8024890: 1886b03a or r3,r3,r2 + 8024894: e0bfff17 ldw r2,-4(fp) + 8024898: 1004923a slli r2,r2,8 + 802489c: 10803fec andhi r2,r2,255 + 80248a0: 1888b03a or r4,r3,r2 + 80248a4: e0bfff17 ldw r2,-4(fp) + 80248a8: 1006963a slli r3,r2,24 + 80248ac: e0bffe17 ldw r2,-8(fp) + 80248b0: 100a90ba slli r5,r2,2 + 80248b4: 008201b4 movhi r2,2054 + 80248b8: 2885883a add r2,r5,r2 + 80248bc: 10b77017 ldw r2,-8768(r2) + 80248c0: 20c6b03a or r3,r4,r3 + 80248c4: 10c00c15 stw r3,48(r2) + 80248c8: 00000106 br 80248d0 + return; + 80248cc: 0001883a nop +} + 80248d0: e037883a mov sp,fp + 80248d4: dfc00117 ldw ra,4(sp) + 80248d8: df000017 ldw fp,0(sp) + 80248dc: dec00204 addi sp,sp,8 + 80248e0: f800283a ret + +080248e4 : + * RETURNS: + */ + +void +netclose() +{ + 80248e4: defffc04 addi sp,sp,-16 + 80248e8: dfc00315 stw ra,12(sp) + 80248ec: df000215 stw fp,8(sp) + 80248f0: df000204 addi fp,sp,8 + NET ifp; + int index = 0; + 80248f4: e03ffe15 stw zero,-8(fp) + +#ifdef NPDEBUG + if (NDEBUG & INFOMSG) dprintf("netclose() called\n"); + 80248f8: d0a06617 ldw r2,-32360(gp) + 80248fc: 1080010c andi r2,r2,4 + 8024900: 10000326 beq r2,zero,8024910 + 8024904: 01020174 movhi r4,2053 + 8024908: 2126c404 addi r4,r4,-25840 + 802490c: 8002d9c0 call 8002d9c +#endif + + for (ifp = (NET)netlist.q_head; ifp; ifp = ifp->n_next) + 8024910: 008201b4 movhi r2,2054 + 8024914: 10b6a617 ldw r2,-9576(r2) + 8024918: e0bfff15 stw r2,-4(fp) + 802491c: 00002106 br 80249a4 + { + if (ifp->n_close) + 8024920: e0bfff17 ldw r2,-4(fp) + 8024924: 10800517 ldw r2,20(r2) + 8024928: 10000f26 beq r2,zero,8024968 + { + dprintf("netclose: closing iface %s\n", ifp->n_mib->ifDescr); + 802492c: e0bfff17 ldw r2,-4(fp) + 8024930: 10802717 ldw r2,156(r2) + 8024934: 10800117 ldw r2,4(r2) + 8024938: 100b883a mov r5,r2 + 802493c: 01020174 movhi r4,2053 + 8024940: 2126c904 addi r4,r4,-25820 + 8024944: 8002c780 call 8002c78 + (*(ifp->n_close))(index++); + 8024948: e0bfff17 ldw r2,-4(fp) + 802494c: 10c00517 ldw r3,20(r2) + 8024950: e0bffe17 ldw r2,-8(fp) + 8024954: 11000044 addi r4,r2,1 + 8024958: e13ffe15 stw r4,-8(fp) + 802495c: 1009883a mov r4,r2 + 8024960: 183ee83a callr r3 + 8024964: 00000c06 br 8024998 + } + else + { +#ifdef NPDEBUG + if (NDEBUG & INFOMSG) dprintf("net %s: no close routine!\n", ifp->name); + 8024968: d0a06617 ldw r2,-32360(gp) + 802496c: 1080010c andi r2,r2,4 + 8024970: 10000626 beq r2,zero,802498c + 8024974: e0bfff17 ldw r2,-4(fp) + 8024978: 10800104 addi r2,r2,4 + 802497c: 100b883a mov r5,r2 + 8024980: 01020174 movhi r4,2053 + 8024984: 2126d004 addi r4,r4,-25792 + 8024988: 8002c780 call 8002c78 +#endif + index++; + 802498c: e0bffe17 ldw r2,-8(fp) + 8024990: 10800044 addi r2,r2,1 + 8024994: e0bffe15 stw r2,-8(fp) + for (ifp = (NET)netlist.q_head; ifp; ifp = ifp->n_next) + 8024998: e0bfff17 ldw r2,-4(fp) + 802499c: 10800017 ldw r2,0(r2) + 80249a0: e0bfff15 stw r2,-4(fp) + 80249a4: e0bfff17 ldw r2,-4(fp) + 80249a8: 103fdd1e bne r2,zero,8024920 + } + } +} + 80249ac: 0001883a nop + 80249b0: e037883a mov sp,fp + 80249b4: dfc00117 ldw ra,4(sp) + 80249b8: df000017 ldw fp,0(sp) + 80249bc: dec00204 addi sp,sp,8 + 80249c0: f800283a ret + +080249c4 : + * RETURNS: void + */ + +void +pktdemux() +{ + 80249c4: defff904 addi sp,sp,-28 + 80249c8: dfc00615 stw ra,24(sp) + 80249cc: df000515 stw fp,20(sp) + 80249d0: df000504 addi fp,sp,20 + NET ifc; /* interface packet came from */ + IFMIB mib; + int pkts; + char * eth; + + pkts = 0; /* packets per loop */ + 80249d4: e03fff15 stw zero,-4(fp) + + while (rcvdq.q_len) + 80249d8: 0000d906 br 8024d40 + { + /* If we are low on free packets, don't hog CPU cycles */ + if (pkts++ > bigfreeq.q_len) + 80249dc: e0bfff17 ldw r2,-4(fp) + 80249e0: 10c00044 addi r3,r2,1 + 80249e4: e0ffff15 stw r3,-4(fp) + 80249e8: 00c201b4 movhi r3,2054 + 80249ec: 18f7dd17 ldw r3,-8332(r3) + 80249f0: 1880020e bge r3,r2,80249fc + { +#ifdef SUPERLOOP + return; /* don't hog stack on superloop */ +#else /* SUPERLOOP */ + tk_yield(); /* let application tasks process received packets */ + 80249f4: 8027ce40 call 8027ce4 + pkts = 0; /* reset counter */ + 80249f8: e03fff15 stw zero,-4(fp) +#endif /* SUPERLOOP else */ + } + + /* If we get receive interupt from the net during this + lock, the MAC driver needs to wait or reschedule */ + LOCK_NET_RESOURCE(RXQ_RESID); + 80249fc: 01000044 movi r4,1 + 8024a00: 8028f380 call 8028f38 + pkt = (PACKET)q_deq(&rcvdq); + 8024a04: 010201b4 movhi r4,2054 + 8024a08: 2136ab04 addi r4,r4,-9556 + 8024a0c: 80288d80 call 80288d8 + 8024a10: e0bffe15 stw r2,-8(fp) + UNLOCK_NET_RESOURCE(RXQ_RESID); + 8024a14: 01000044 movi r4,1 + 8024a18: 8028ff40 call 8028ff4 + if (!pkt) panic("pktdemux: got null pkt"); + 8024a1c: e0bffe17 ldw r2,-8(fp) + 8024a20: 1000031e bne r2,zero,8024a30 + 8024a24: 01020174 movhi r4,2053 + 8024a28: 2126d704 addi r4,r4,-25764 + 8024a2c: 80271780 call 8027178 + ifc = pkt->net; + 8024a30: e0bffe17 ldw r2,-8(fp) + 8024a34: 10800617 ldw r2,24(r2) + 8024a38: e0bffd15 stw r2,-12(fp) + + mib = ifc->n_mib; + 8024a3c: e0bffd17 ldw r2,-12(fp) + 8024a40: 10802717 ldw r2,156(r2) + 8024a44: e0bffc15 stw r2,-16(fp) + /* maintain mib stats for unicast and broadcast */ + if (isbcast(ifc, (u_char*)pkt->nb_buff + ETHHDR_BIAS)) + 8024a48: e0bffe17 ldw r2,-8(fp) + 8024a4c: 10800117 ldw r2,4(r2) + 8024a50: 10800084 addi r2,r2,2 + 8024a54: 100b883a mov r5,r2 + 8024a58: e13ffd17 ldw r4,-12(fp) + 8024a5c: 80240f40 call 80240f4 + 8024a60: 10000626 beq r2,zero,8024a7c + mib->ifInNUcastPkts++; + 8024a64: e0bffc17 ldw r2,-16(fp) + 8024a68: 10800b17 ldw r2,44(r2) + 8024a6c: 10c00044 addi r3,r2,1 + 8024a70: e0bffc17 ldw r2,-16(fp) + 8024a74: 10c00b15 stw r3,44(r2) + 8024a78: 00000506 br 8024a90 + else + mib->ifInUcastPkts++; + 8024a7c: e0bffc17 ldw r2,-16(fp) + 8024a80: 10800a17 ldw r2,40(r2) + 8024a84: 10c00044 addi r3,r2,1 + 8024a88: e0bffc17 ldw r2,-16(fp) + 8024a8c: 10c00a15 stw r3,40(r2) + + if(mib->ifAdminStatus == NI_DOWN) + 8024a90: e0bffc17 ldw r2,-16(fp) + 8024a94: 10800617 ldw r2,24(r2) + 8024a98: 10800098 cmpnei r2,r2,2 + 8024a9c: 10000c1e bne r2,zero,8024ad0 + { + LOCK_NET_RESOURCE(FREEQ_RESID); + 8024aa0: 01000084 movi r4,2 + 8024aa4: 8028f380 call 8028f38 + pk_free(pkt); /* dump packet from downed interface */ + 8024aa8: e13ffe17 ldw r4,-8(fp) + 8024aac: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8024ab0: 01000084 movi r4,2 + 8024ab4: 8028ff40 call 8028ff4 + mib->ifInDiscards++; + 8024ab8: e0bffc17 ldw r2,-16(fp) + 8024abc: 10800c17 ldw r2,48(r2) + 8024ac0: 10c00044 addi r3,r2,1 + 8024ac4: e0bffc17 ldw r2,-16(fp) + 8024ac8: 10c00c15 stw r3,48(r2) + continue; /* next packet */ + 8024acc: 00009c06 br 8024d40 + } + +#ifdef NPDEBUG + if (*(pkt->nb_buff - ALIGN_TYPE) != 'M' || + 8024ad0: e0bffe17 ldw r2,-8(fp) + 8024ad4: 10800117 ldw r2,4(r2) + 8024ad8: 10bfff04 addi r2,r2,-4 + 8024adc: 10800003 ldbu r2,0(r2) + 8024ae0: 10803fcc andi r2,r2,255 + 8024ae4: 1080201c xori r2,r2,128 + 8024ae8: 10bfe004 addi r2,r2,-128 + 8024aec: 10801358 cmpnei r2,r2,77 + 8024af0: 10000b1e bne r2,zero,8024b20 + *(pkt->nb_buff + pkt->nb_blen) != 'M') + 8024af4: e0bffe17 ldw r2,-8(fp) + 8024af8: 10c00117 ldw r3,4(r2) + 8024afc: e0bffe17 ldw r2,-8(fp) + 8024b00: 10800217 ldw r2,8(r2) + 8024b04: 1885883a add r2,r3,r2 + 8024b08: 10800003 ldbu r2,0(r2) + if (*(pkt->nb_buff - ALIGN_TYPE) != 'M' || + 8024b0c: 10803fcc andi r2,r2,255 + 8024b10: 1080201c xori r2,r2,128 + 8024b14: 10bfe004 addi r2,r2,-128 + 8024b18: 10801360 cmpeqi r2,r2,77 + 8024b1c: 1000041e bne r2,zero,8024b30 + { + dtrap(); + 8024b20: 8028cd40 call 8028cd4 + panic("pktdemux: corrupt pkt"); + 8024b24: 01020174 movhi r4,2053 + 8024b28: 2126dd04 addi r4,r4,-25740 + 8024b2c: 80271780 call 8027178 + } + } +#endif /* LOSSY_IO */ + + /* see if driver set pkt->nb_prot and pkt->type */ + if((ifc->n_flags & NF_NBPROT) == 0) + 8024b30: e0bffd17 ldw r2,-12(fp) + 8024b34: 10802a17 ldw r2,168(r2) + 8024b38: 1080020c andi r2,r2,8 + 8024b3c: 1000491e bne r2,zero,8024c64 + * probably the right thing to do, but because of this historic + * inconsistency we don't try to fix it here - the longer size + * turns out to be harmless since the IP layer fixes the size + * based on the IP header length field. + */ + switch(ifc->n_mib->ifType) + 8024b40: e0bffd17 ldw r2,-12(fp) + 8024b44: 10802717 ldw r2,156(r2) + 8024b48: 10800217 ldw r2,8(r2) + 8024b4c: 10800198 cmpnei r2,r2,6 + 8024b50: 1000361e bne r2,zero,8024c2c + { + case ETHERNET: + /* get pointer to ethernet header */ + eth = (pkt->nb_buff + ETHHDR_BIAS); + 8024b54: e0bffe17 ldw r2,-8(fp) + 8024b58: 10800117 ldw r2,4(r2) + 8024b5c: 10800084 addi r2,r2,2 + 8024b60: e0bffb15 stw r2,-20(fp) + { + pkt->type = htons((unshort)ET_TYPE_GET(eth)); + pkt->nb_prot = pkt->nb_buff + ETHHDR_SIZE; + } +#else + pkt->type = htons((unshort)ET_TYPE_GET(eth)); + 8024b64: e0bffb17 ldw r2,-20(fp) + 8024b68: 10800304 addi r2,r2,12 + 8024b6c: 10800003 ldbu r2,0(r2) + 8024b70: 10803fcc andi r2,r2,255 + 8024b74: 1080201c xori r2,r2,128 + 8024b78: 10bfe004 addi r2,r2,-128 + 8024b7c: 1004923a slli r2,r2,8 + 8024b80: 1007883a mov r3,r2 + 8024b84: e0bffb17 ldw r2,-20(fp) + 8024b88: 10800344 addi r2,r2,13 + 8024b8c: 10800003 ldbu r2,0(r2) + 8024b90: 10803fcc andi r2,r2,255 + 8024b94: 1080201c xori r2,r2,128 + 8024b98: 10bfe004 addi r2,r2,-128 + 8024b9c: 10803fcc andi r2,r2,255 + 8024ba0: 1885883a add r2,r3,r2 + 8024ba4: 10bfffcc andi r2,r2,65535 + 8024ba8: 1004d23a srli r2,r2,8 + 8024bac: 1007883a mov r3,r2 + 8024bb0: e0bffb17 ldw r2,-20(fp) + 8024bb4: 10800304 addi r2,r2,12 + 8024bb8: 10800003 ldbu r2,0(r2) + 8024bbc: 10803fcc andi r2,r2,255 + 8024bc0: 1080201c xori r2,r2,128 + 8024bc4: 10bfe004 addi r2,r2,-128 + 8024bc8: 1004923a slli r2,r2,8 + 8024bcc: 1009883a mov r4,r2 + 8024bd0: e0bffb17 ldw r2,-20(fp) + 8024bd4: 10800344 addi r2,r2,13 + 8024bd8: 10800003 ldbu r2,0(r2) + 8024bdc: 10803fcc andi r2,r2,255 + 8024be0: 1080201c xori r2,r2,128 + 8024be4: 10bfe004 addi r2,r2,-128 + 8024be8: 10803fcc andi r2,r2,255 + 8024bec: 2085883a add r2,r4,r2 + 8024bf0: 10bfffcc andi r2,r2,65535 + 8024bf4: 1004923a slli r2,r2,8 + 8024bf8: 1884b03a or r2,r3,r2 + 8024bfc: 1007883a mov r3,r2 + 8024c00: e0bffe17 ldw r2,-8(fp) + 8024c04: 10c0080d sth r3,32(r2) + pkt->nb_prot = pkt->nb_buff + pkt->net->n_lnh; + 8024c08: e0bffe17 ldw r2,-8(fp) + 8024c0c: 10800117 ldw r2,4(r2) + 8024c10: e0fffe17 ldw r3,-8(fp) + 8024c14: 18c00617 ldw r3,24(r3) + 8024c18: 18c00817 ldw r3,32(r3) + 8024c1c: 10c7883a add r3,r2,r3 + 8024c20: e0bffe17 ldw r2,-8(fp) + 8024c24: 10c00315 stw r3,12(r2) +#endif /* IEEE_802_3 */ + break; + 8024c28: 00000f06 br 8024c68 + case PPPOE: + /* do not change type yet, for PPPoE */ + break; +#endif /* USE_PPPOE */ + default: /* driver bug? */ + dprintf("pktdemux: bad Iface type %ld\n",ifc->n_mib->ifType); + 8024c2c: e0bffd17 ldw r2,-12(fp) + 8024c30: 10802717 ldw r2,156(r2) + 8024c34: 10800217 ldw r2,8(r2) + 8024c38: 100b883a mov r5,r2 + 8024c3c: 01020174 movhi r4,2053 + 8024c40: 2126e304 addi r4,r4,-25716 + 8024c44: 8002c780 call 8002c78 + LOCK_NET_RESOURCE(FREEQ_RESID); + 8024c48: 01000084 movi r4,2 + 8024c4c: 8028f380 call 8028f38 + pk_free(pkt); + 8024c50: e13ffe17 ldw r4,-8(fp) + 8024c54: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8024c58: 01000084 movi r4,2 + 8024c5c: 8028ff40 call 8028ff4 + continue; + 8024c60: 00003706 br 8024d40 + } + } + 8024c64: 0001883a nop + + /* pkt->nb_prot and pkt->type are now set. pass pkt to upper layer */ + switch(pkt->type) + 8024c68: e0bffe17 ldw r2,-8(fp) + 8024c6c: 1080080b ldhu r2,32(r2) + 8024c70: 10bfffcc andi r2,r2,65535 + 8024c74: 10c00220 cmpeqi r3,r2,8 + 8024c78: 1800031e bne r3,zero,8024c88 + 8024c7c: 10818220 cmpeqi r2,r2,1544 + 8024c80: 1000081e bne r2,zero,8024ca4 + 8024c84: 00000e06 br 8024cc0 + { + case IPTP: /* IP type */ + LOCK_NET_RESOURCE(NET_RESID); + 8024c88: 0009883a mov r4,zero + 8024c8c: 8028f380 call 8028f38 +#ifdef SHARED_IPADDRS + add_share_route(pkt); +#endif /* SHARED_IPADDRS */ +#ifdef IP_V4 + ip_rcv(pkt); + 8024c90: e13ffe17 ldw r4,-8(fp) + 8024c94: 803b6680 call 803b668 + /* don't care, it's IPv4 */ + LOCK_NET_RESOURCE(FREEQ_RESID); + pk_free(pkt); + UNLOCK_NET_RESOURCE(FREEQ_RESID); +#endif + UNLOCK_NET_RESOURCE(NET_RESID); + 8024c98: 0009883a mov r4,zero + 8024c9c: 8028ff40 call 8028ff4 + break; + 8024ca0: 00002606 br 8024d3c +#ifdef INCLUDE_ARP + case ARPTP: /* ARP type */ + LOCK_NET_RESOURCE(NET_RESID); + 8024ca4: 0009883a mov r4,zero + 8024ca8: 8028f380 call 8028f38 + arprcv(pkt); + 8024cac: e13ffe17 ldw r4,-8(fp) + 8024cb0: 80238e40 call 80238e4 + UNLOCK_NET_RESOURCE(NET_RESID); + 8024cb4: 0009883a mov r4,zero + 8024cb8: 8028ff40 call 8028ff4 + break; + 8024cbc: 00001f06 br 8024d3c + UNLOCK_NET_RESOURCE(NET_RESID); + break; +#endif + default: +#ifdef NPDEBUG + if (NDEBUG & UPCTRACE) + 8024cc0: d0a06617 ldw r2,-32360(gp) + 8024cc4: 1081000c andi r2,r2,1024 + 8024cc8: 10001026 beq r2,zero,8024d0c + dprintf("pktdemux: bad pkt type 0x%04x\n", ntohs(pkt->type)); + 8024ccc: e0bffe17 ldw r2,-8(fp) + 8024cd0: 1080080b ldhu r2,32(r2) + 8024cd4: 10bfffcc andi r2,r2,65535 + 8024cd8: 1004d23a srli r2,r2,8 + 8024cdc: 10bfffcc andi r2,r2,65535 + 8024ce0: 10c03fcc andi r3,r2,255 + 8024ce4: e0bffe17 ldw r2,-8(fp) + 8024ce8: 1080080b ldhu r2,32(r2) + 8024cec: 10bfffcc andi r2,r2,65535 + 8024cf0: 1004923a slli r2,r2,8 + 8024cf4: 10bfffcc andi r2,r2,65535 + 8024cf8: 1884b03a or r2,r3,r2 + 8024cfc: 100b883a mov r5,r2 + 8024d00: 01020174 movhi r4,2053 + 8024d04: 2126eb04 addi r4,r4,-25684 + 8024d08: 8002c780 call 8002c78 +#endif /* NPDEBUG */ + ifc->n_mib->ifInUnknownProtos++; + 8024d0c: e0bffd17 ldw r2,-12(fp) + 8024d10: 10802717 ldw r2,156(r2) + 8024d14: 10c00e17 ldw r3,56(r2) + 8024d18: 18c00044 addi r3,r3,1 + 8024d1c: 10c00e15 stw r3,56(r2) + LOCK_NET_RESOURCE(FREEQ_RESID); + 8024d20: 01000084 movi r4,2 + 8024d24: 8028f380 call 8028f38 + pk_free(pkt); /* return to free buffer */ + 8024d28: e13ffe17 ldw r4,-8(fp) + 8024d2c: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8024d30: 01000084 movi r4,2 + 8024d34: 8028ff40 call 8028ff4 + break; + 8024d38: 0001883a nop + } + continue; + 8024d3c: 0001883a nop + while (rcvdq.q_len) + 8024d40: 008201b4 movhi r2,2054 + 8024d44: 10b6ad17 ldw r2,-9548(r2) + 8024d48: 103f241e bne r2,zero,80249dc + } +} + 8024d4c: 0001883a nop + 8024d50: e037883a mov sp,fp + 8024d54: dfc00117 ldw ra,4(sp) + 8024d58: df000017 ldw fp,0(sp) + 8024d5c: dec00204 addi sp,sp,8 + 8024d60: f800283a ret + +08024d64 : + * RETURNS: the older of the two passed tick counts + */ + +u_long +c_older(u_long ct1, u_long ct2) +{ + 8024d64: defffd04 addi sp,sp,-12 + 8024d68: df000215 stw fp,8(sp) + 8024d6c: df000204 addi fp,sp,8 + 8024d70: e13fff15 stw r4,-4(fp) + 8024d74: e17ffe15 stw r5,-8(fp) + + if (!(cticks & 0x80000000) || /* cticks has not wrapped recently, or */ + 8024d78: d0a07d17 ldw r2,-32268(gp) + 8024d7c: 10000c0e bge r2,zero,8024db0 + (ct1 <= cticks && ct2 <= cticks) || /* both are below cticks or */ + 8024d80: d0e07d17 ldw r3,-32268(gp) + if (!(cticks & 0x80000000) || /* cticks has not wrapped recently, or */ + 8024d84: e0bfff17 ldw r2,-4(fp) + 8024d88: 18800336 bltu r3,r2,8024d98 + (ct1 <= cticks && ct2 <= cticks) || /* both are below cticks or */ + 8024d8c: d0e07d17 ldw r3,-32268(gp) + 8024d90: e0bffe17 ldw r2,-8(fp) + 8024d94: 1880062e bgeu r3,r2,8024db0 + (ct1 >= cticks && ct2 >= cticks)) /* both are above cticks */ + 8024d98: d0a07d17 ldw r2,-32268(gp) + (ct1 <= cticks && ct2 <= cticks) || /* both are below cticks or */ + 8024d9c: e0ffff17 ldw r3,-4(fp) + 8024da0: 18800a36 bltu r3,r2,8024dcc + (ct1 >= cticks && ct2 >= cticks)) /* both are above cticks */ + 8024da4: d0a07d17 ldw r2,-32268(gp) + 8024da8: e0fffe17 ldw r3,-8(fp) + 8024dac: 18800736 bltu r3,r2,8024dcc + { + if (ct1 < ct2) + 8024db0: e0ffff17 ldw r3,-4(fp) + 8024db4: e0bffe17 ldw r2,-8(fp) + 8024db8: 1880022e bgeu r3,r2,8024dc4 + return(ct1); /* then smaller is oldest */ + 8024dbc: e0bfff17 ldw r2,-4(fp) + 8024dc0: 00000806 br 8024de4 + else + return(ct2); + 8024dc4: e0bffe17 ldw r2,-8(fp) + 8024dc8: 00000606 br 8024de4 + } + + /* else one is less than cticks, and one is greater. + the larger value is then the oldest */ + if (ct1 >= ct2) + 8024dcc: e0ffff17 ldw r3,-4(fp) + 8024dd0: e0bffe17 ldw r2,-8(fp) + 8024dd4: 18800236 bltu r3,r2,8024de0 + return(ct1); + 8024dd8: e0bfff17 ldw r2,-4(fp) + 8024ddc: 00000106 br 8024de4 + else + return(ct2); + 8024de0: e0bffe17 ldw r2,-8(fp) +} + 8024de4: e037883a mov sp,fp + 8024de8: df000017 ldw fp,0(sp) + 8024dec: dec00104 addi sp,sp,4 + 8024df0: f800283a ret + +08024df4 : + */ + +int +ip2mac(PACKET pkt, /* the packet itself, all set but for dest MAC address */ + ip_addr dest_ip) /* the IP host or gateway to get MAC addr for */ +{ + 8024df4: defffb04 addi sp,sp,-20 + 8024df8: dfc00415 stw ra,16(sp) + 8024dfc: df000315 stw fp,12(sp) + 8024e00: df000304 addi fp,sp,12 + 8024e04: e13ffe15 stw r4,-8(fp) + 8024e08: e17ffd15 stw r5,-12(fp) + IFMIB ifmib = pkt->net->n_mib; /* mib info for this interface */ + 8024e0c: e0bffe17 ldw r2,-8(fp) + 8024e10: 10800617 ldw r2,24(r2) + 8024e14: 10802717 ldw r2,156(r2) + 8024e18: e0bfff15 stw r2,-4(fp) + + /* Always punt if iface ifAdminStatus is DOWN. ifOperStatus may + * be down too, but our packet may be the event required to bring + * it up - so don't worry about ifOperStatus here. + */ + if(ifmib->ifAdminStatus == NI_DOWN) + 8024e1c: e0bfff17 ldw r2,-4(fp) + 8024e20: 10800617 ldw r2,24(r2) + 8024e24: 10800098 cmpnei r2,r2,2 + 8024e28: 1000081e bne r2,zero,8024e4c + { + LOCK_NET_RESOURCE(FREEQ_RESID); + 8024e2c: 01000084 movi r4,2 + 8024e30: 8028f380 call 8028f38 + pk_free(pkt); + 8024e34: e13ffe17 ldw r4,-8(fp) + 8024e38: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8024e3c: 01000084 movi r4,2 + 8024e40: 8028ff40 call 8028ff4 + return(ENP_NO_ROUTE); + 8024e44: 00bff7c4 movi r2,-33 + 8024e48: 00004806 br 8024f6c + return ENP_NOBUFFER; + } +#endif /* LINKED_PKTS */ + + /* some interfaces (ie SLIP) just get the raw IP frame - no ARP needed */ + if ((pkt->net->n_lnh == 0) || /* no MAC header */ + 8024e4c: e0bffe17 ldw r2,-8(fp) + 8024e50: 10800617 ldw r2,24(r2) + 8024e54: 10800817 ldw r2,32(r2) + 8024e58: 10000826 beq r2,zero,8024e7c + (ifmib->ifType == PPP) || /* or PPP or SLIP... */ + 8024e5c: e0bfff17 ldw r2,-4(fp) + 8024e60: 10800217 ldw r2,8(r2) + if ((pkt->net->n_lnh == 0) || /* no MAC header */ + 8024e64: 108005e0 cmpeqi r2,r2,23 + 8024e68: 1000041e bne r2,zero,8024e7c + (ifmib->ifType == SLIP)) + 8024e6c: e0bfff17 ldw r2,-4(fp) + 8024e70: 10800217 ldw r2,8(r2) + (ifmib->ifType == PPP) || /* or PPP or SLIP... */ + 8024e74: 10800718 cmpnei r2,r2,28 + 8024e78: 1000291e bne r2,zero,8024f20 + { + ifmib->ifOutUcastPkts++; /* maintain MIB counters */ + 8024e7c: e0bfff17 ldw r2,-4(fp) + 8024e80: 10801017 ldw r2,64(r2) + 8024e84: 10c00044 addi r3,r2,1 + 8024e88: e0bfff17 ldw r2,-4(fp) + 8024e8c: 10c01015 stw r3,64(r2) + ifmib->ifOutOctets += pkt->nb_plen; + 8024e90: e0bfff17 ldw r2,-4(fp) + 8024e94: 10c00f17 ldw r3,60(r2) + 8024e98: e0bffe17 ldw r2,-8(fp) + 8024e9c: 10800417 ldw r2,16(r2) + 8024ea0: 1887883a add r3,r3,r2 + 8024ea4: e0bfff17 ldw r2,-4(fp) + 8024ea8: 10c00f15 stw r3,60(r2) + + /* send packet on media */ + if (pkt->net->pkt_send) /* favor using packet send */ + 8024eac: e0bffe17 ldw r2,-8(fp) + 8024eb0: 10800617 ldw r2,24(r2) + 8024eb4: 10800417 ldw r2,16(r2) + 8024eb8: 10000626 beq r2,zero,8024ed4 + pkt->net->pkt_send(pkt); /* pkt will be freed by MAC code */ + 8024ebc: e0bffe17 ldw r2,-8(fp) + 8024ec0: 10800617 ldw r2,24(r2) + 8024ec4: 10800417 ldw r2,16(r2) + 8024ec8: e13ffe17 ldw r4,-8(fp) + 8024ecc: 103ee83a callr r2 + 8024ed0: 00001106 br 8024f18 + else /* no packet send; try raw send */ + { + pkt->net->raw_send(pkt->net, pkt->nb_prot, pkt->nb_plen); + 8024ed4: e0bffe17 ldw r2,-8(fp) + 8024ed8: 10800617 ldw r2,24(r2) + 8024edc: 10800317 ldw r2,12(r2) + 8024ee0: e0fffe17 ldw r3,-8(fp) + 8024ee4: 19000617 ldw r4,24(r3) + 8024ee8: e0fffe17 ldw r3,-8(fp) + 8024eec: 19400317 ldw r5,12(r3) + 8024ef0: e0fffe17 ldw r3,-8(fp) + 8024ef4: 18c00417 ldw r3,16(r3) + 8024ef8: 180d883a mov r6,r3 + 8024efc: 103ee83a callr r2 + LOCK_NET_RESOURCE(FREEQ_RESID); + 8024f00: 01000084 movi r4,2 + 8024f04: 8028f380 call 8028f38 + pk_free(pkt); + 8024f08: e13ffe17 ldw r4,-8(fp) + 8024f0c: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8024f10: 01000084 movi r4,2 + 8024f14: 8028ff40 call 8028ff4 + } + return(SUCCESS); + 8024f18: 0005883a mov r2,zero + 8024f1c: 00001306 br 8024f6c + } + + /* don't allow unicast sends if NIC iface has no IP address. This + * is to prevent DHCP clients from sending prior to assignment. + */ + if (pkt->net->n_ipaddr == 0L) + 8024f20: e0bffe17 ldw r2,-8(fp) + 8024f24: 10800617 ldw r2,24(r2) + 8024f28: 10800a17 ldw r2,40(r2) + 8024f2c: 10000c1e bne r2,zero,8024f60 + { + if (pkt->fhost != 0xFFFFFFFF) /* check for broadcast packet */ + 8024f30: e0bffe17 ldw r2,-8(fp) + 8024f34: 10800717 ldw r2,28(r2) + 8024f38: 10bfffe0 cmpeqi r2,r2,-1 + 8024f3c: 1000081e bne r2,zero,8024f60 + { + LOCK_NET_RESOURCE(FREEQ_RESID); + 8024f40: 01000084 movi r4,2 + 8024f44: 8028f380 call 8028f38 + pk_free(pkt); + 8024f48: e13ffe17 ldw r4,-8(fp) + 8024f4c: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8024f50: 01000084 movi r4,2 + 8024f54: 8028ff40 call 8028ff4 + return ENP_SENDERR; + 8024f58: 00bff884 movi r2,-30 + 8024f5c: 00000306 br 8024f6c + } + } + +#ifdef INCLUDE_ARP /* must be ethernet or token ring */ + return(send_via_arp(pkt, dest_ip)); + 8024f60: e17ffd17 ldw r5,-12(fp) + 8024f64: e13ffe17 ldw r4,-8(fp) + 8024f68: 8023b480 call 8023b48 +#else + dtrap(); /* Bad option combination? */ + return ENP_NO_IFACE; /* sent to unknown interface type */ +#endif /* INCLUDE_ARP */ +} + 8024f6c: e037883a mov sp,fp + 8024f70: dfc00117 ldw ra,4(sp) + 8024f74: df000017 ldw fp,0(sp) + 8024f78: dec00204 addi sp,sp,8 + 8024f7c: f800283a ret + +08024f80 : + * RETURNS: returns NULL if OK, or text of an error message + */ + +char * +ip_startup() +{ + 8024f80: defffc04 addi sp,sp,-16 + 8024f84: dfc00315 stw ra,12(sp) + 8024f88: df000215 stw fp,8(sp) + 8024f8c: df000204 addi fp,sp,8 + int e; /* error holder */ + int i; + + /* thread nets[] and attach mib data to nets[] arrays */ + for (i = 0; i < STATIC_NETS; i++) + 8024f90: e03fff15 stw zero,-4(fp) + 8024f94: 00002206 br 8025020 + { + nets[i] = &netstatic[i]; /* set up array of pointers */ + 8024f98: e0bfff17 ldw r2,-4(fp) + 8024f9c: 10c03024 muli r3,r2,192 + 8024fa0: 008201b4 movhi r2,2054 + 8024fa4: 10b6b004 addi r2,r2,-9536 + 8024fa8: 1887883a add r3,r3,r2 + 8024fac: e0bfff17 ldw r2,-4(fp) + 8024fb0: 100890ba slli r4,r2,2 + 8024fb4: 008201b4 movhi r2,2054 + 8024fb8: 2085883a add r2,r4,r2 + 8024fbc: 10f77015 stw r3,-8768(r2) + nets[i]->n_mib = &nets[i]->mib; /* set mib pointer */ + 8024fc0: e0bfff17 ldw r2,-4(fp) + 8024fc4: 100690ba slli r3,r2,2 + 8024fc8: 008201b4 movhi r2,2054 + 8024fcc: 1885883a add r2,r3,r2 + 8024fd0: 10f77017 ldw r3,-8768(r2) + 8024fd4: e0bfff17 ldw r2,-4(fp) + 8024fd8: 100890ba slli r4,r2,2 + 8024fdc: 008201b4 movhi r2,2054 + 8024fe0: 2085883a add r2,r4,r2 + 8024fe4: 10b77017 ldw r2,-8768(r2) + 8024fe8: 18c01204 addi r3,r3,72 + 8024fec: 10c02715 stw r3,156(r2) + + /* add static iface to end of nets list */ + putq(&netlist, nets[i]); + 8024ff0: e0bfff17 ldw r2,-4(fp) + 8024ff4: 100690ba slli r3,r2,2 + 8024ff8: 008201b4 movhi r2,2054 + 8024ffc: 1885883a add r2,r3,r2 + 8025000: 10b77017 ldw r2,-8768(r2) + 8025004: 100b883a mov r5,r2 + 8025008: 010201b4 movhi r4,2054 + 802500c: 2136a604 addi r4,r4,-9576 + 8025010: 80289900 call 8028990 + for (i = 0; i < STATIC_NETS; i++) + 8025014: e0bfff17 ldw r2,-4(fp) + 8025018: 10800044 addi r2,r2,1 + 802501c: e0bfff15 stw r2,-4(fp) + 8025020: e0bfff17 ldw r2,-4(fp) + 8025024: 10800110 cmplti r2,r2,4 + 8025028: 103fdb1e bne r2,zero,8024f98 + } + + /* call port routine to locate and init network interfaces. */ + ifNumber = (unsigned)prep_ifaces(ifNumber); + 802502c: d0a06717 ldw r2,-32356(gp) + 8025030: 1009883a mov r4,r2 + 8025034: 803c5680 call 803c568 + 8025038: d0a06715 stw r2,-32356(gp) + + if (ifNumber < 1) /* no static interfaces? */ + 802503c: d0a06717 ldw r2,-32356(gp) + 8025040: 1000031e bne r2,zero,8025050 +#ifdef DYNAMIC_IFACES + /* print a debug message and hope user knows what he's doing */ + dprintf("unable to find any working interfaces"); +#else /* static ifaces only */ + /* no static and no dynamic interfaces is probably a bug... */ + return("unable to find any working interfaces"); + 8025044: 00820174 movhi r2,2053 + 8025048: 10a6fc04 addi r2,r2,-25616 + 802504c: 00006006 br 80251d0 +#endif /* DYNAMIC_IFACES */ + } + + /* throw away any unused static nets */ + for (i = ifNumber; i < STATIC_NETS; i++) + 8025050: d0a06717 ldw r2,-32356(gp) + 8025054: e0bfff15 stw r2,-4(fp) + 8025058: 00001106 br 80250a0 + { + qdel(&netlist, (qp)nets[i]); /* remove from queue */ + 802505c: e0bfff17 ldw r2,-4(fp) + 8025060: 100690ba slli r3,r2,2 + 8025064: 008201b4 movhi r2,2054 + 8025068: 1885883a add r2,r3,r2 + 802506c: 10b77017 ldw r2,-8768(r2) + 8025070: 100b883a mov r5,r2 + 8025074: 010201b4 movhi r4,2054 + 8025078: 2136a604 addi r4,r4,-9576 + 802507c: 8028a400 call 8028a40 + nets[i] = NULL; /* remove from array */ + 8025080: e0bfff17 ldw r2,-4(fp) + 8025084: 100690ba slli r3,r2,2 + 8025088: 008201b4 movhi r2,2054 + 802508c: 1885883a add r2,r3,r2 + 8025090: 10377015 stw zero,-8768(r2) + for (i = ifNumber; i < STATIC_NETS; i++) + 8025094: e0bfff17 ldw r2,-4(fp) + 8025098: 10800044 addi r2,r2,1 + 802509c: e0bfff15 stw r2,-4(fp) + 80250a0: e0bfff17 ldw r2,-4(fp) + 80250a4: 10800110 cmplti r2,r2,4 + 80250a8: 103fec1e bne r2,zero,802505c + /* The sequence of events when initing the net & interface systems + * is very important. Be very carefull about altering the order of + * the following statements. + */ + /* once these are done, we should call ip_exit before quiting IP */ + clock_init(); /* start clock system */ + 80250ac: 8028de00 call 8028de0 + exit_hook(clock_c); + 80250b0: 010200f4 movhi r4,2051 + 80250b4: 21238604 addi r4,r4,-29160 + 80250b8: 80251e40 call 80251e4 + + e = Netinit(); /* start net interface(s) */ + 80250bc: 80242e40 call 80242e4 + 80250c0: e0bffe15 stw r2,-8(fp) + if (e) + 80250c4: e0bffe17 ldw r2,-8(fp) + 80250c8: 10000326 beq r2,zero,80250d8 + { + return("unable to initialize net"); + 80250cc: 00820174 movhi r2,2053 + 80250d0: 10a70604 addi r2,r2,-25576 + 80250d4: 00003e06 br 80251d0 + } + +#ifdef INCLUDE_ARP + e = etainit(); /* startup ARP layer */ + 80250d8: 8022ca40 call 8022ca4 + 80250dc: e0bffe15 stw r2,-8(fp) + if (e) + 80250e0: e0bffe17 ldw r2,-8(fp) + 80250e4: 10000426 beq r2,zero,80250f8 + { + ip_exit(); + 80250e8: 802524c0 call 802524c + return("unable to initialize arp"); + 80250ec: 00820174 movhi r2,2053 + 80250f0: 10a70d04 addi r2,r2,-25548 + 80250f4: 00003606 br 80251d0 + } +#endif + +#ifdef IP_V4 + e = ip_init(); /* start up IP layer */ + 80250f8: 803a0700 call 803a070 + 80250fc: e0bffe15 stw r2,-8(fp) + if (e) + 8025100: e0bffe17 ldw r2,-8(fp) + 8025104: 10000426 beq r2,zero,8025118 + { + ip_exit(); + 8025108: 802524c0 call 802524c + return("unable to initialize IP"); + 802510c: 00820174 movhi r2,2053 + 8025110: 10a71404 addi r2,r2,-25520 + 8025114: 00002e06 br 80251d0 + +#if defined (IP_MULTICAST) && (defined (IGMP_V1) || defined (IGMP_V2)) + /* Join the All hosts group on every interface that IP multicast is + * supported + */ + e = igmp_init(); /* Initialize igmp */ + 8025118: 802537c0 call 802537c + 802511c: e0bffe15 stw r2,-8(fp) + if (e) + 8025120: e0bffe17 ldw r2,-8(fp) + 8025124: 10000326 beq r2,zero,8025134 + { + ip_exit(); + 8025128: 802524c0 call 802524c + return(ipmcfail_str); + 802512c: d0a01217 ldw r2,-32696(gp) + 8025130: 00002706 br 80251d0 + } + + for (i = 0; i < (int)ifNumber; i++) + 8025134: e03fff15 stw zero,-4(fp) + 8025138: 00001706 br 8025198 + { + if (nets[i]->n_mcastlist != NULL) + 802513c: e0bfff17 ldw r2,-4(fp) + 8025140: 100690ba slli r3,r2,2 + 8025144: 008201b4 movhi r2,2054 + 8025148: 1885883a add r2,r3,r2 + 802514c: 10b77017 ldw r2,-8768(r2) + 8025150: 10802b17 ldw r2,172(r2) + 8025154: 10000d26 beq r2,zero,802518c + if ((in_addmulti(&igmp_all_hosts_group, nets[i], 4) == NULL)) + 8025158: e0bfff17 ldw r2,-4(fp) + 802515c: 100690ba slli r3,r2,2 + 8025160: 008201b4 movhi r2,2054 + 8025164: 1885883a add r2,r3,r2 + 8025168: 10b77017 ldw r2,-8768(r2) + 802516c: 01800104 movi r6,4 + 8025170: 100b883a mov r5,r2 + 8025174: d1206b04 addi r4,gp,-32340 + 8025178: 803c2ac0 call 803c2ac + 802517c: 1000031e bne r2,zero,802518c + { + ip_exit(); + 8025180: 802524c0 call 802524c + return(ipmcfail_str); + 8025184: d0a01217 ldw r2,-32696(gp) + 8025188: 00001106 br 80251d0 + for (i = 0; i < (int)ifNumber; i++) + 802518c: e0bfff17 ldw r2,-4(fp) + 8025190: 10800044 addi r2,r2,1 + 8025194: e0bfff15 stw r2,-4(fp) + 8025198: d0a06717 ldw r2,-32356(gp) + 802519c: 1007883a mov r3,r2 + 80251a0: e0bfff17 ldw r2,-4(fp) + 80251a4: 10ffe516 blt r2,r3,802513c + } + } +#endif /* IP_MULTICAST and (IGMPv1 or IGMPv2) */ + +#ifdef INCLUDE_TCP + e = tcpinit(); + 80251a8: 803637c0 call 803637c + 80251ac: e0bffe15 stw r2,-8(fp) + if (e) + 80251b0: e0bffe17 ldw r2,-8(fp) + 80251b4: 10000426 beq r2,zero,80251c8 + { + ip_exit(); + 80251b8: 802524c0 call 802524c + return("unable to initialize TCP"); + 80251bc: 00820174 movhi r2,2053 + 80251c0: 10a71a04 addi r2,r2,-25496 + 80251c4: 00000206 br 80251d0 + /* setup event map for (UDP and TCP) socket library's events (such as + * those used by tcp_sleep () and tcp_wakeup ()). These events either + * map into operating system primitives such as events or semaphores, + * or into task suspend and task resume mechanisms. + */ + evtmap_setup (); + 80251c8: 803c6100 call 803c610 + return("unable to initialize IP Filter table"); + else + exit_hook(ipf_cleanup); +#endif + + return(NULL); /* we got through with no errors */ + 80251cc: 0005883a mov r2,zero +} + 80251d0: e037883a mov sp,fp + 80251d4: dfc00117 ldw ra,4(sp) + 80251d8: df000017 ldw fp,0(sp) + 80251dc: dec00204 addi sp,sp,8 + 80251e0: f800283a ret + +080251e4 : + * RETURNS: + */ + +void +exit_hook(void (*func)(void)) +{ + 80251e4: defffd04 addi sp,sp,-12 + 80251e8: dfc00215 stw ra,8(sp) + 80251ec: df000115 stw fp,4(sp) + 80251f0: df000104 addi fp,sp,4 + 80251f4: e13fff15 stw r4,-4(fp) + if (nclosers >= (NUMCLOSERS-1)) + 80251f8: d0a06817 ldw r2,-32352(gp) + 80251fc: 10800390 cmplti r2,r2,14 + 8025200: 1000031e bne r2,zero,8025210 + panic("exit_hook"); + 8025204: 01020174 movhi r4,2053 + 8025208: 21272104 addi r4,r4,-25468 + 802520c: 80271780 call 8027178 + + closers[++nclosers] = func; + 8025210: d0a06817 ldw r2,-32352(gp) + 8025214: 10800044 addi r2,r2,1 + 8025218: d0a06815 stw r2,-32352(gp) + 802521c: d0a06817 ldw r2,-32352(gp) + 8025220: 100890ba slli r4,r2,2 + 8025224: e0ffff17 ldw r3,-4(fp) + 8025228: 00820174 movhi r2,2053 + 802522c: 2085883a add r2,r4,r2 + 8025230: 10f36e15 stw r3,-12872(r2) +} + 8025234: 0001883a nop + 8025238: e037883a mov sp,fp + 802523c: dfc00117 ldw ra,4(sp) + 8025240: df000017 ldw fp,0(sp) + 8025244: dec00204 addi sp,sp,8 + 8025248: f800283a ret + +0802524c : + * RETURNS: void + */ + +void +ip_exit() +{ + 802524c: defffd04 addi sp,sp,-12 + 8025250: dfc00215 stw ra,8(sp) + 8025254: df000115 stw fp,4(sp) + 8025258: df000104 addi fp,sp,4 + int n; + + for (n=nclosers; n; n--) + 802525c: d0a06817 ldw r2,-32352(gp) + 8025260: e0bfff15 stw r2,-4(fp) + 8025264: 00001d06 br 80252dc + { +#ifdef NPDEBUG + dprintf("ip_exit: calling func %p\n", closers[n]); + 8025268: e0bfff17 ldw r2,-4(fp) + 802526c: 100690ba slli r3,r2,2 + 8025270: 00820174 movhi r2,2053 + 8025274: 1885883a add r2,r3,r2 + 8025278: 10b36e17 ldw r2,-12872(r2) + 802527c: 100b883a mov r5,r2 + 8025280: 01020174 movhi r4,2053 + 8025284: 21272404 addi r4,r4,-25456 + 8025288: 8002c780 call 8002c78 +#endif + if(closers[n]) + 802528c: e0bfff17 ldw r2,-4(fp) + 8025290: 100690ba slli r3,r2,2 + 8025294: 00820174 movhi r2,2053 + 8025298: 1885883a add r2,r3,r2 + 802529c: 10b36e17 ldw r2,-12872(r2) + 80252a0: 10000b26 beq r2,zero,80252d0 + { + (*closers[n])(); + 80252a4: e0bfff17 ldw r2,-4(fp) + 80252a8: 100690ba slli r3,r2,2 + 80252ac: 00820174 movhi r2,2053 + 80252b0: 1885883a add r2,r3,r2 + 80252b4: 10b36e17 ldw r2,-12872(r2) + 80252b8: 103ee83a callr r2 + closers[n] = NULL; + 80252bc: e0bfff17 ldw r2,-4(fp) + 80252c0: 100690ba slli r3,r2,2 + 80252c4: 00820174 movhi r2,2053 + 80252c8: 1885883a add r2,r3,r2 + 80252cc: 10336e15 stw zero,-12872(r2) + for (n=nclosers; n; n--) + 80252d0: e0bfff17 ldw r2,-4(fp) + 80252d4: 10bfffc4 addi r2,r2,-1 + 80252d8: e0bfff15 stw r2,-4(fp) + 80252dc: e0bfff17 ldw r2,-4(fp) + 80252e0: 103fe11e bne r2,zero,8025268 + } + } +} + 80252e4: 0001883a nop + 80252e8: e037883a mov sp,fp + 80252ec: dfc00117 ldw ra,4(sp) + 80252f0: df000017 ldw fp,0(sp) + 80252f4: dec00204 addi sp,sp,8 + 80252f8: f800283a ret + +080252fc : + * RETURNS: net index for passed net pointer + */ + +int +if_netnumber(NET nptr) +{ + 80252fc: defffb04 addi sp,sp,-20 + 8025300: dfc00415 stw ra,16(sp) + 8025304: df000315 stw fp,12(sp) + 8025308: df000304 addi fp,sp,12 + 802530c: e13ffd15 stw r4,-12(fp) + unsigned i; + NET ifp; + + for(ifp = (NET)(netlist.q_head), i = 0; ifp; ifp = ifp->n_next, i++) + 8025310: 008201b4 movhi r2,2054 + 8025314: 10b6a617 ldw r2,-9576(r2) + 8025318: e0bffe15 stw r2,-8(fp) + 802531c: e03fff15 stw zero,-4(fp) + 8025320: 00000b06 br 8025350 + { + if(ifp == nptr) + 8025324: e0fffe17 ldw r3,-8(fp) + 8025328: e0bffd17 ldw r2,-12(fp) + 802532c: 1880021e bne r3,r2,8025338 + return (int)i; + 8025330: e0bfff17 ldw r2,-4(fp) + 8025334: 00000c06 br 8025368 + for(ifp = (NET)(netlist.q_head), i = 0; ifp; ifp = ifp->n_next, i++) + 8025338: e0bffe17 ldw r2,-8(fp) + 802533c: 10800017 ldw r2,0(r2) + 8025340: e0bffe15 stw r2,-8(fp) + 8025344: e0bfff17 ldw r2,-4(fp) + 8025348: 10800044 addi r2,r2,1 + 802534c: e0bfff15 stw r2,-4(fp) + 8025350: e0bffe17 ldw r2,-8(fp) + 8025354: 103ff31e bne r2,zero,8025324 + } + + panic("bad net ptr"); + 8025358: 01020174 movhi r4,2053 + 802535c: 21272b04 addi r4,r4,-25428 + 8025360: 80271780 call 8027178 + return 0; + 8025364: 0005883a mov r2,zero +} + 8025368: e037883a mov sp,fp + 802536c: dfc00117 ldw ra,4(sp) + 8025370: df000017 ldw fp,0(sp) + 8025374: dec00204 addi sp,sp,8 + 8025378: f800283a ret + +0802537c : + * + * OUTPUT: None. + */ + +int igmp_init(void) +{ + 802537c: defffe04 addi sp,sp,-8 + 8025380: df000115 stw fp,4(sp) + 8025384: df000104 addi fp,sp,4 + NET ifp; + + /* + * To avoid byte-swapping the same value over and over again. + */ + igmp_all_hosts_group = htonl(INADDR_ALLHOSTS_GROUP); + 8025388: 00804034 movhi r2,256 + 802538c: 10803804 addi r2,r2,224 + 8025390: d0a06b15 stw r2,-32340(gp) + igmp_all_rtrs_group = htonl(INADDR_ALLRTRS_GROUP); + 8025394: 00808034 movhi r2,512 + 8025398: 10803804 addi r2,r2,224 + 802539c: d0a06c15 stw r2,-32336(gp) + /* note that the IGMP operational mode configuration for a + * given link (i.e., whether it should run IGMPv1 or IGMPv2) + * has already been validated, so no additional checks are + * required here. + */ + for (ifp = (NET) netlist.q_head; ifp; ifp = ifp->n_next) + 80253a0: 008201b4 movhi r2,2054 + 80253a4: 10b6a617 ldw r2,-9576(r2) + 80253a8: e0bfff15 stw r2,-4(fp) + 80253ac: 00001006 br 80253f0 + { + if (ifp->igmp_oper_mode == IGMP_MODE_V1) + 80253b0: e0bfff17 ldw r2,-4(fp) + 80253b4: 10802f03 ldbu r2,188(r2) + 80253b8: 10803fcc andi r2,r2,255 + 80253bc: 10800058 cmpnei r2,r2,1 + 80253c0: 1000041e bne r2,zero,80253d4 + { + ifp->igmpv1_rtr_present = 1; + 80253c4: e0bfff17 ldw r2,-4(fp) + 80253c8: 00c00044 movi r3,1 + 80253cc: 10c02d05 stb r3,180(r2) + 80253d0: 00000406 br 80253e4 + } + else + { + ifp->igmpv1_rtr_present = 0; + 80253d4: e0bfff17 ldw r2,-4(fp) + 80253d8: 10002d05 stb zero,180(r2) + /* not really required, only referred to if IGMPv1 router is + * "present" */ + ifp->igmpv1_query_rcvd_time = 0; + 80253dc: e0bfff17 ldw r2,-4(fp) + 80253e0: 10002e15 stw zero,184(r2) + for (ifp = (NET) netlist.q_head; ifp; ifp = ifp->n_next) + 80253e4: e0bfff17 ldw r2,-4(fp) + 80253e8: 10800017 ldw r2,0(r2) + 80253ec: e0bfff15 stw r2,-4(fp) + 80253f0: e0bfff17 ldw r2,-4(fp) + 80253f4: 103fee1e bne r2,zero,80253b0 + } + + /* + * Call igmp_fasttimo PR_FASTHZ (5) times per second + */ + igmp_cticks = cticks + TPS/PR_FASTHZ; + 80253f8: d0a07d17 ldw r2,-32268(gp) + 80253fc: 10800504 addi r2,r2,20 + 8025400: d0a06a15 stw r2,-32344(gp) + + /* there are no timers running initially */ + igmp_timers_are_running = 0; + 8025404: d0206915 stw zero,-32348(gp) + + return IGMP_OK; + 8025408: 0005883a mov r2,zero +} + 802540c: e037883a mov sp,fp + 8025410: df000017 ldw fp,0(sp) + 8025414: dec00104 addi sp,sp,4 + 8025418: f800283a ret + +0802541c : + * returned if the operating mode is not correctly configured + * to a valid IGMP operating mode. + */ + +int igmp_input (PACKET p) +{ + 802541c: defffb04 addi sp,sp,-20 + 8025420: dfc00415 stw ra,16(sp) + 8025424: df000315 stw fp,12(sp) + 8025428: df000304 addi fp,sp,12 + 802542c: e13ffd15 stw r4,-12(fp) + u_char mode; + int rc; + + ++igmpstats.igmp_total_rcvd; + 8025430: 008201b4 movhi r2,2054 + 8025434: 10b77417 ldw r2,-8752(r2) + 8025438: 10c00044 addi r3,r2,1 + 802543c: 008201b4 movhi r2,2054 + 8025440: 10f77415 stw r3,-8752(r2) + + /* validate the received packet; if validation fails, + * drop the packet and return */ + if ((rc = igmp_validate (p)) != IGMP_OK) goto end; + 8025444: e13ffd17 ldw r4,-12(fp) + 8025448: 8025b840 call 8025b84 + 802544c: e0bfff15 stw r2,-4(fp) + 8025450: e0bfff17 ldw r2,-4(fp) + 8025454: 1000181e bne r2,zero,80254b8 + + /* determine the operating mode for IGMP on the ingress link */ + mode = p->net->igmp_oper_mode; + 8025458: e0bffd17 ldw r2,-12(fp) + 802545c: 10800617 ldw r2,24(r2) + 8025460: 10802f03 ldbu r2,188(r2) + 8025464: e0bffec5 stb r2,-5(fp) + + /* feed packet to IGMPv1 or IGMPv2 code based on the operating + * mode of the ingress link */ + switch (mode) + 8025468: e0bffec3 ldbu r2,-5(fp) + 802546c: 10c00060 cmpeqi r3,r2,1 + 8025470: 1800031e bne r3,zero,8025480 + 8025474: 108000a0 cmpeqi r2,r2,2 + 8025478: 1000041e bne r2,zero,802548c + 802547c: 00000606 br 8025498 + { +#ifdef IGMP_V1 + case IGMP_MODE_V1: + return (igmpv1_input (p)); + 8025480: e13ffd17 ldw r4,-12(fp) + 8025484: 803ddfc0 call 803ddfc + 8025488: 00001306 br 80254d8 +#endif +#ifdef IGMP_V2 + case IGMP_MODE_V2: + return (igmpv2_input (p)); + 802548c: e13ffd17 ldw r4,-12(fp) + 8025490: 803e0640 call 803e064 + 8025494: 00001006 br 80254d8 +#endif + default: + ++igmpstats.igmp_bad_oper_mode; + 8025498: 008201b4 movhi r2,2054 + 802549c: 10b78117 ldw r2,-8700(r2) + 80254a0: 10c00044 addi r3,r2,1 + 80254a4: 008201b4 movhi r2,2054 + 80254a8: 10f78115 stw r3,-8700(r2) + rc = IGMP_ERR; + 80254ac: 00bfffc4 movi r2,-1 + 80254b0: e0bfff15 stw r2,-4(fp) + break; + 80254b4: 00000106 br 80254bc + if ((rc = igmp_validate (p)) != IGMP_OK) goto end; + 80254b8: 0001883a nop + } + +end: + /* return packet buffer back to free pool */ + LOCK_NET_RESOURCE(FREEQ_RESID); + 80254bc: 01000084 movi r4,2 + 80254c0: 8028f380 call 8028f38 + pk_free(p); + 80254c4: e13ffd17 ldw r4,-12(fp) + 80254c8: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 80254cc: 01000084 movi r4,2 + 80254d0: 8028ff40 call 8028ff4 + + return rc; + 80254d4: e0bfff17 ldw r2,-4(fp) +} + 80254d8: e037883a mov sp,fp + 80254dc: dfc00117 ldw ra,4(sp) + 80254e0: df000017 ldw fp,0(sp) + 80254e4: dec00204 addi sp,sp,8 + 80254e8: f800283a ret + +080254ec : + * + * OUTPUT: None. + */ + +void igmp_fasttimo (void) +{ + 80254ec: defffc04 addi sp,sp,-16 + 80254f0: dfc00315 stw ra,12(sp) + 80254f4: df000215 stw fp,8(sp) + 80254f8: df000204 addi fp,sp,8 + struct in_multi * inm; + NET ifp; + + LOCK_NET_RESOURCE (NET_RESID); + 80254fc: 0009883a mov r4,zero + 8025500: 8028f380 call 8028f38 + + /* + * Quick check to see if any work needs to be done, in order + * to minimize the overhead of fasttimo processing. + */ + if (!igmp_timers_are_running) + 8025504: d0a06917 ldw r2,-32348(gp) + 8025508: 1000031e bne r2,zero,8025518 + { + UNLOCK_NET_RESOURCE (NET_RESID); + 802550c: 0009883a mov r4,zero + 8025510: 8028ff40 call 8028ff4 + return; + 8025514: 00004c06 br 8025648 + } + + for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next) + 8025518: 008201b4 movhi r2,2054 + 802551c: 10b6a617 ldw r2,-9576(r2) + 8025520: e0bffe15 stw r2,-8(fp) + 8025524: 00004006 br 8025628 + { + for (inm = ifp->mc_list; inm; inm = inm->inm_next) + 8025528: e0bffe17 ldw r2,-8(fp) + 802552c: 10802c17 ldw r2,176(r2) + 8025530: e0bfff15 stw r2,-4(fp) + 8025534: 00003706 br 8025614 + { + /* skip IPv6 entries */ + if (inm->inm_addr == 0) + 8025538: e0bfff17 ldw r2,-4(fp) + 802553c: 10800017 ldw r2,0(r2) + 8025540: 10003026 beq r2,zero,8025604 + continue; + + if (inm->inm_timer == 0) /* timer not set */ + 8025544: e0bfff17 ldw r2,-4(fp) + 8025548: 10800317 ldw r2,12(r2) + 802554c: 10002e26 beq r2,zero,8025608 + { + /* do nothing */ + } + else if (--inm->inm_timer == 0) /* timer expired */ + 8025550: e0bfff17 ldw r2,-4(fp) + 8025554: 10800317 ldw r2,12(r2) + 8025558: 10ffffc4 addi r3,r2,-1 + 802555c: e0bfff17 ldw r2,-4(fp) + 8025560: 10c00315 stw r3,12(r2) + 8025564: e0bfff17 ldw r2,-4(fp) + 8025568: 10800317 ldw r2,12(r2) + 802556c: 1000261e bne r2,zero,8025608 + { + /* send membership report in appropriate format */ + if (ifp->igmpv1_rtr_present) + 8025570: e0bffe17 ldw r2,-8(fp) + 8025574: 10802d03 ldbu r2,180(r2) + 8025578: 10803fcc andi r2,r2,255 + 802557c: 10000426 beq r2,zero,8025590 + { + /* always true for IGMPv1, may be true for IGMPv2 */ + igmp_send (IGMP_HOST_MEMBERSHIP_REPORT, inm); + 8025580: e17fff17 ldw r5,-4(fp) + 8025584: 01000484 movi r4,18 + 8025588: 802565c0 call 802565c + 802558c: 00000306 br 802559c + } + else + { + igmp_send (IGMPv2_MEMBERSHIP_REPORT, inm); + 8025590: e17fff17 ldw r5,-4(fp) + 8025594: 01000584 movi r4,22 + 8025598: 802565c0 call 802565c + + /* for IGMPv2, indicate that we were the last to send + * a Report for this multicast group (relevant for + * IGMPv2 only). also check to see if we should mark + * the IGMPv1 router as "absent". */ + if (ifp->igmp_oper_mode == IGMP_MODE_V2) + 802559c: e0bffe17 ldw r2,-8(fp) + 80255a0: 10802f03 ldbu r2,188(r2) + 80255a4: 10803fcc andi r2,r2,255 + 80255a8: 10800098 cmpnei r2,r2,2 + 80255ac: 1000111e bne r2,zero,80255f4 + { + inm->last2send_report = IGMP_TRUE; + 80255b0: e0bfff17 ldw r2,-4(fp) + 80255b4: 00c00044 movi r3,1 + 80255b8: 10c00405 stb r3,16(r2) + + if (ifp->igmpv1_rtr_present) + 80255bc: e0bffe17 ldw r2,-8(fp) + 80255c0: 10802d03 ldbu r2,180(r2) + 80255c4: 10803fcc andi r2,r2,255 + 80255c8: 10000a26 beq r2,zero,80255f4 + { + if (cticks > (ifp->igmpv1_query_rcvd_time + (IGMPv1_RTR_PRESENT_TMO * TPS))) + 80255cc: e0bffe17 ldw r2,-8(fp) + 80255d0: 10c02e17 ldw r3,184(r2) + 80255d4: 00a71014 movui r2,40000 + 80255d8: 1887883a add r3,r3,r2 + 80255dc: d0a07d17 ldw r2,-32268(gp) + 80255e0: 1880042e bgeu r3,r2,80255f4 + /* we haven't heard from the IGMPv1 router for a duration + * greater than or equal to Version 1 Router Present Timeout + * (400 seconds), and will now update the igmpv1_rtr_present + * variable to reflect that. + */ + ifp->igmpv1_rtr_present = IGMP_FALSE; + 80255e4: e0bffe17 ldw r2,-8(fp) + 80255e8: 10002d05 stb zero,180(r2) + ifp->igmpv1_query_rcvd_time = 0; + 80255ec: e0bffe17 ldw r2,-8(fp) + 80255f0: 10002e15 stw zero,184(r2) + } + } + } + + /* decrement the count of running IGMP timers */ + --igmp_timers_are_running; + 80255f4: d0a06917 ldw r2,-32348(gp) + 80255f8: 10bfffc4 addi r2,r2,-1 + 80255fc: d0a06915 stw r2,-32348(gp) + 8025600: 00000106 br 8025608 + continue; + 8025604: 0001883a nop + for (inm = ifp->mc_list; inm; inm = inm->inm_next) + 8025608: e0bfff17 ldw r2,-4(fp) + 802560c: 10800517 ldw r2,20(r2) + 8025610: e0bfff15 stw r2,-4(fp) + 8025614: e0bfff17 ldw r2,-4(fp) + 8025618: 103fc71e bne r2,zero,8025538 + for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next) + 802561c: e0bffe17 ldw r2,-8(fp) + 8025620: 10800017 ldw r2,0(r2) + 8025624: e0bffe15 stw r2,-8(fp) + 8025628: e0bffe17 ldw r2,-8(fp) + 802562c: 103fbe1e bne r2,zero,8025528 + } + } + + /* Setup time for the next call into igmp_fasttimo () + * (200 ms later). */ + igmp_cticks = cticks + TPS/PR_FASTHZ; + 8025630: d0a07d17 ldw r2,-32268(gp) + 8025634: 10800504 addi r2,r2,20 + 8025638: d0a06a15 stw r2,-32344(gp) + + UNLOCK_NET_RESOURCE (NET_RESID); + 802563c: 0009883a mov r4,zero + 8025640: 8028ff40 call 8028ff4 + + return; + 8025644: 0001883a nop +} + 8025648: e037883a mov sp,fp + 802564c: dfc00117 ldw ra,4(sp) + 8025650: df000017 ldw fp,0(sp) + 8025654: dec00204 addi sp,sp,8 + 8025658: f800283a ret + +0802565c : + * + * OUTPUT: None. + */ + +void igmp_send (u_char type, struct in_multi * inm) +{ + 802565c: deffde04 addi sp,sp,-136 + 8025660: dfc02115 stw ra,132(sp) + 8025664: df002015 stw fp,128(sp) + 8025668: df002004 addi fp,sp,128 + 802566c: 2005883a mov r2,r4 + 8025670: e17fe015 stw r5,-128(fp) + 8025674: e0bfe105 stb r2,-124(fp) + struct igmp * igmp; + struct ip_moptions * imop; + struct ip_moptions simo; + struct ip * pip; + u_char * tmpp; + u_char opts [2] = {IP_RTR_ALERT_OPT, EOL_OPT}; + 8025678: 00800504 movi r2,20 + 802567c: e0bfe285 stb r2,-118(fp) + 8025680: e03fe2c5 stb zero,-117(fp) + u_char reqd_len; + + /* compute length of buffer required for outgoing packet. + * also account for the length of the IP Router Alert + * option, if required. */ + reqd_len = MaxLnh + sizeof (struct ip) + sizeof (struct igmp); + 8025684: d0a06417 ldw r2,-32368(gp) + 8025688: 10800704 addi r2,r2,28 + 802568c: e0bffdc5 stb r2,-9(fp) + if ((type == IGMPv2_LEAVE_GROUP) || + 8025690: e0bfe103 ldbu r2,-124(fp) + 8025694: 108005e0 cmpeqi r2,r2,23 + 8025698: 1000031e bne r2,zero,80256a8 + 802569c: e0bfe103 ldbu r2,-124(fp) + 80256a0: 10800598 cmpnei r2,r2,22 + 80256a4: 1000031e bne r2,zero,80256b4 + (type == IGMPv2_MEMBERSHIP_REPORT)) + { + reqd_len += IP_RTR_ALERT_OPT_SIZE; + 80256a8: e0bffdc3 ldbu r2,-9(fp) + 80256ac: 10800104 addi r2,r2,4 + 80256b0: e0bffdc5 stb r2,-9(fp) + } + + /* obtain a packet to send the IGMP message */ + LOCK_NET_RESOURCE (FREEQ_RESID); + 80256b4: 01000084 movi r4,2 + 80256b8: 8028f380 call 8028f38 + p = pk_alloc (reqd_len); + 80256bc: e0bffdc3 ldbu r2,-9(fp) + 80256c0: 1009883a mov r4,r2 + 80256c4: 80284340 call 8028434 + 80256c8: e0bffc15 stw r2,-16(fp) + UNLOCK_NET_RESOURCE (FREEQ_RESID); + 80256cc: 01000084 movi r4,2 + 80256d0: 8028ff40 call 8028ff4 + + /* log an error and return if the allocation fails */ + if (!p) + 80256d4: e0bffc17 ldw r2,-16(fp) + 80256d8: 1000061e bne r2,zero,80256f4 + { + ++igmpstats.igmp_pkt_alloc_fail; + 80256dc: 008201b4 movhi r2,2054 + 80256e0: 10b78017 ldw r2,-8704(r2) + 80256e4: 10c00044 addi r3,r2,1 + 80256e8: 008201b4 movhi r2,2054 + 80256ec: 10f78015 stw r3,-8704(r2) + 80256f0: 00007406 br 80258c4 + return; + } + + /* Need to fill in the source and destination ip addresses */ + pip = (struct ip *) p->nb_prot; + 80256f4: e0bffc17 ldw r2,-16(fp) + 80256f8: 10800317 ldw r2,12(r2) + 80256fc: e0bffb15 stw r2,-20(fp) + pip->ip_src = inm->inm_netp->n_ipaddr; + 8025700: e0bfe017 ldw r2,-128(fp) + 8025704: 10800117 ldw r2,4(r2) + 8025708: 10c00a17 ldw r3,40(r2) + 802570c: e0bffb17 ldw r2,-20(fp) + 8025710: 10c00315 stw r3,12(r2) + /* Leave Group messages are sent to the all-routers multicast group */ + if (type == IGMPv2_LEAVE_GROUP) + 8025714: e0bfe103 ldbu r2,-124(fp) + 8025718: 108005d8 cmpnei r2,r2,23 + 802571c: 1000041e bne r2,zero,8025730 + { + /* igmp_all_rtrs_group is already in network byte order */ + pip->ip_dest = igmp_all_rtrs_group; + 8025720: d0e06c17 ldw r3,-32336(gp) + 8025724: e0bffb17 ldw r2,-20(fp) + 8025728: 10c00415 stw r3,16(r2) + 802572c: 00000406 br 8025740 + } + else + pip->ip_dest = inm->inm_addr; + 8025730: e0bfe017 ldw r2,-128(fp) + 8025734: 10c00017 ldw r3,0(r2) + 8025738: e0bffb17 ldw r2,-20(fp) + 802573c: 10c00415 stw r3,16(r2) + + p->fhost = pip->ip_dest; + 8025740: e0bffb17 ldw r2,-20(fp) + 8025744: 10c00417 ldw r3,16(r2) + 8025748: e0bffc17 ldw r2,-16(fp) + 802574c: 10c00715 stw r3,28(r2) + + tmpp = (((u_char *) p->nb_prot) + sizeof (struct ip)); + 8025750: e0bffc17 ldw r2,-16(fp) + 8025754: 10800317 ldw r2,12(r2) + 8025758: 10800504 addi r2,r2,20 + 802575c: e0bfff15 stw r2,-4(fp) + + /* when transmitting an IGMP packet, our IGMP module will insert + * data for the Router Alert option in the following types of + * packets: Version 2 Membership Report (0x16) and Leave Group + * (0x17) */ + if ((type == IGMPv2_LEAVE_GROUP) || + 8025760: e0bfe103 ldbu r2,-124(fp) + 8025764: 108005e0 cmpeqi r2,r2,23 + 8025768: 1000031e bne r2,zero,8025778 + 802576c: e0bfe103 ldbu r2,-124(fp) + 8025770: 10800598 cmpnei r2,r2,22 + 8025774: 1000061e bne r2,zero,8025790 + (type == IGMPv2_MEMBERSHIP_REPORT)) + { + /* provide space for ip_write2 () to write option-related data */ + tmpp += IP_RTR_ALERT_OPT_SIZE; + 8025778: e0bfff17 ldw r2,-4(fp) + 802577c: 10800104 addi r2,r2,4 + 8025780: e0bfff15 stw r2,-4(fp) + optp = &(opts [0]); /* one option (IP Router Alert) */ + 8025784: e0bfe284 addi r2,fp,-118 + 8025788: e0bffe15 stw r2,-8(fp) + 802578c: 00000306 br 802579c + } + /* outgoing packet does not require any options */ + else + optp = &(opts [1]); + 8025790: e0bfe284 addi r2,fp,-118 + 8025794: 10800044 addi r2,r2,1 + 8025798: e0bffe15 stw r2,-8(fp) + /* point to the start of the IGMP header */ + igmp = (struct igmp *) tmpp; + 802579c: e0bfff17 ldw r2,-4(fp) + 80257a0: e0bffa15 stw r2,-24(fp) + + igmp->igmp_type = type; + 80257a4: e0bffa17 ldw r2,-24(fp) + 80257a8: e0ffe103 ldbu r3,-124(fp) + 80257ac: 10c00005 stb r3,0(r2) + igmp->igmp_code = 0; + 80257b0: e0bffa17 ldw r2,-24(fp) + 80257b4: 10000045 stb zero,1(r2) + + /* all messages (Report or Leave) have Group Address field + * set to the group being reported or left */ + igmp->igmp_group = inm->inm_addr; + 80257b8: e0bfe017 ldw r2,-128(fp) + 80257bc: 10c00017 ldw r3,0(r2) + 80257c0: e0bffa17 ldw r2,-24(fp) + 80257c4: 10c00115 stw r3,4(r2) + igmp->igmp_cksum = 0; + 80257c8: e0bffa17 ldw r2,-24(fp) + 80257cc: 1000008d sth zero,2(r2) + igmp->igmp_cksum = ~cksum((void*)igmp, IGMP_MINLEN>>1); + 80257d0: 01400104 movi r5,4 + 80257d4: e13ffa17 ldw r4,-24(fp) + 80257d8: 8026d7c0 call 8026d7c + 80257dc: 0084303a nor r2,zero,r2 + 80257e0: 1007883a mov r3,r2 + 80257e4: e0bffa17 ldw r2,-24(fp) + 80257e8: 10c0008d sth r3,2(r2) + + imop = &simo; + 80257ec: e0bfe304 addi r2,fp,-116 + 80257f0: e0bff915 stw r2,-28(fp) + MEMSET(imop, 0, sizeof(simo)); + 80257f4: 01801604 movi r6,88 + 80257f8: 000b883a mov r5,zero + 80257fc: e13ff917 ldw r4,-28(fp) + 8025800: 80088e40 call 80088e4 + imop->imo_multicast_netp = inm->inm_netp; + 8025804: e0bfe017 ldw r2,-128(fp) + 8025808: 10c00117 ldw r3,4(r2) + 802580c: e0bff917 ldw r2,-28(fp) + 8025810: 10c00015 stw r3,0(r2) + imop->imo_multicast_ttl = 1; + 8025814: e0bff917 ldw r2,-28(fp) + 8025818: 00c00044 movi r3,1 + 802581c: 10c00105 stb r3,4(r2) + /* we do not want our own reports to be looped back */ + imop->imo_multicast_loop = 0; + 8025820: e0bff917 ldw r2,-28(fp) + 8025824: 10000145 stb zero,5(r2) + + /* set nb_prot to point to the beginning of the IGMP data, + * and nb_plen to the length of the IGMP data, and attach + * the multicast options structure to the outgoing packet */ + p->nb_prot = (char *) tmpp; + 8025828: e0bffc17 ldw r2,-16(fp) + 802582c: e0ffff17 ldw r3,-4(fp) + 8025830: 10c00315 stw r3,12(r2) + p->nb_plen = sizeof(struct igmp); + 8025834: e0bffc17 ldw r2,-16(fp) + 8025838: 00c00204 movi r3,8 + 802583c: 10c00415 stw r3,16(r2) + p->imo = imop; + 8025840: e0bffc17 ldw r2,-16(fp) + 8025844: e0fff917 ldw r3,-28(fp) + 8025848: 10c00b15 stw r3,44(r2) + + ip_write2 (IGMP_PROT, p, optp); + 802584c: e1bffe17 ldw r6,-8(fp) + 8025850: e17ffc17 ldw r5,-16(fp) + 8025854: 01000084 movi r4,2 + 8025858: 803abf80 call 803abf8 + + if (type == IGMPv2_LEAVE_GROUP) + 802585c: e0bfe103 ldbu r2,-124(fp) + 8025860: 108005d8 cmpnei r2,r2,23 + 8025864: 1000061e bne r2,zero,8025880 + ++igmpstats.igmpv2mode_v2_leave_msgs_sent; + 8025868: 008201b4 movhi r2,2054 + 802586c: 10b78b17 ldw r2,-8660(r2) + 8025870: 10c00044 addi r3,r2,1 + 8025874: 008201b4 movhi r2,2054 + 8025878: 10f78b15 stw r3,-8660(r2) + 802587c: 00001106 br 80258c4 + else if (type == IGMPv2_MEMBERSHIP_REPORT) + 8025880: e0bfe103 ldbu r2,-124(fp) + 8025884: 10800598 cmpnei r2,r2,22 + 8025888: 1000061e bne r2,zero,80258a4 + ++igmpstats.igmpv2mode_v2_reports_sent; + 802588c: 008201b4 movhi r2,2054 + 8025890: 10b78c17 ldw r2,-8656(r2) + 8025894: 10c00044 addi r3,r2,1 + 8025898: 008201b4 movhi r2,2054 + 802589c: 10f78c15 stw r3,-8656(r2) + 80258a0: 00000806 br 80258c4 + else if (type == IGMP_HOST_MEMBERSHIP_REPORT) + 80258a4: e0bfe103 ldbu r2,-124(fp) + 80258a8: 10800498 cmpnei r2,r2,18 + 80258ac: 1000051e bne r2,zero,80258c4 + ++igmpstats.igmp_v1_reports_sent; + 80258b0: 008201b4 movhi r2,2054 + 80258b4: 10b78a17 ldw r2,-8664(r2) + 80258b8: 10c00044 addi r3,r2,1 + 80258bc: 008201b4 movhi r2,2054 + 80258c0: 10f78a15 stw r3,-8664(r2) +} + 80258c4: e037883a mov sp,fp + 80258c8: dfc00117 ldw ra,4(sp) + 80258cc: df000017 ldw fp,0(sp) + 80258d0: dec00204 addi sp,sp,8 + 80258d4: f800283a ret + +080258d8 : + * + * OUTPUT: None. + */ + +void igmp_joingroup(struct in_multi * inm) +{ + 80258d8: defffc04 addi sp,sp,-16 + 80258dc: dfc00315 stw ra,12(sp) + 80258e0: df000215 stw fp,8(sp) + 80258e4: df000204 addi fp,sp,8 + 80258e8: e13ffe15 stw r4,-8(fp) + NET ifp; + + /* extract the network interface to which this multicast + * address is "attached" */ + ifp = inm->inm_netp; + 80258ec: e0bffe17 ldw r2,-8(fp) + 80258f0: 10800117 ldw r2,4(r2) + 80258f4: e0bfff15 stw r2,-4(fp) + + if (inm->inm_addr == igmp_all_hosts_group) + 80258f8: e0bffe17 ldw r2,-8(fp) + 80258fc: 10c00017 ldw r3,0(r2) + 8025900: d0a06b17 ldw r2,-32340(gp) + 8025904: 1880031e bne r3,r2,8025914 + { + inm->inm_timer = 0; + 8025908: e0bffe17 ldw r2,-8(fp) + 802590c: 10000315 stw zero,12(r2) + } + + ++igmp_timers_are_running; + } + + return; + 8025910: 00007706 br 8025af0 + if (ifp->igmpv1_rtr_present) + 8025914: e0bfff17 ldw r2,-4(fp) + 8025918: 10802d03 ldbu r2,180(r2) + 802591c: 10803fcc andi r2,r2,255 + 8025920: 10003426 beq r2,zero,80259f4 + igmp_send (IGMP_HOST_MEMBERSHIP_REPORT, inm); + 8025924: e17ffe17 ldw r5,-8(fp) + 8025928: 01000484 movi r4,18 + 802592c: 802565c0 call 802565c + inm->inm_timer = (unsigned) IGMP_RANDOM_DELAY(inm->inm_addr); + 8025930: 008201b4 movhi r2,2054 + 8025934: 10f95117 ldw r3,-6844(r2) + 8025938: 008201b4 movhi r2,2054 + 802593c: 10b77017 ldw r2,-8768(r2) + 8025940: 10800a17 ldw r2,40(r2) + 8025944: 1008d63a srli r4,r2,24 + 8025948: 008201b4 movhi r2,2054 + 802594c: 10b77017 ldw r2,-8768(r2) + 8025950: 10800a17 ldw r2,40(r2) + 8025954: 1004d23a srli r2,r2,8 + 8025958: 10bfc00c andi r2,r2,65280 + 802595c: 2088b03a or r4,r4,r2 + 8025960: 008201b4 movhi r2,2054 + 8025964: 10b77017 ldw r2,-8768(r2) + 8025968: 10800a17 ldw r2,40(r2) + 802596c: 1004923a slli r2,r2,8 + 8025970: 10803fec andhi r2,r2,255 + 8025974: 2088b03a or r4,r4,r2 + 8025978: 008201b4 movhi r2,2054 + 802597c: 10b77017 ldw r2,-8768(r2) + 8025980: 10800a17 ldw r2,40(r2) + 8025984: 1004963a slli r2,r2,24 + 8025988: 2084b03a or r2,r4,r2 + 802598c: 1887883a add r3,r3,r2 + 8025990: e0bffe17 ldw r2,-8(fp) + 8025994: 10800017 ldw r2,0(r2) + 8025998: 1008d63a srli r4,r2,24 + 802599c: e0bffe17 ldw r2,-8(fp) + 80259a0: 10800017 ldw r2,0(r2) + 80259a4: 1004d23a srli r2,r2,8 + 80259a8: 10bfc00c andi r2,r2,65280 + 80259ac: 2088b03a or r4,r4,r2 + 80259b0: e0bffe17 ldw r2,-8(fp) + 80259b4: 10800017 ldw r2,0(r2) + 80259b8: 1004923a slli r2,r2,8 + 80259bc: 10803fec andhi r2,r2,255 + 80259c0: 2088b03a or r4,r4,r2 + 80259c4: e0bffe17 ldw r2,-8(fp) + 80259c8: 10800017 ldw r2,0(r2) + 80259cc: 1004963a slli r2,r2,24 + 80259d0: 2084b03a or r2,r4,r2 + 80259d4: 1885883a add r2,r3,r2 + 80259d8: 01400c84 movi r5,50 + 80259dc: 1009883a mov r4,r2 + 80259e0: 800d05c0 call 800d05c <__umodsi3> + 80259e4: 10c00044 addi r3,r2,1 + 80259e8: e0bffe17 ldw r2,-8(fp) + 80259ec: 10c00315 stw r3,12(r2) + 80259f0: 00003306 br 8025ac0 + igmp_send (IGMPv2_MEMBERSHIP_REPORT, inm); + 80259f4: e17ffe17 ldw r5,-8(fp) + 80259f8: 01000584 movi r4,22 + 80259fc: 802565c0 call 802565c + inm->inm_timer = (unsigned) IGMPv2_RANDOM_DELAY ((UNSOLIC_RPT_INTERVAL * PR_FASTHZ), inm->inm_addr); + 8025a00: 008201b4 movhi r2,2054 + 8025a04: 10f95117 ldw r3,-6844(r2) + 8025a08: 008201b4 movhi r2,2054 + 8025a0c: 10b77017 ldw r2,-8768(r2) + 8025a10: 10800a17 ldw r2,40(r2) + 8025a14: 1008d63a srli r4,r2,24 + 8025a18: 008201b4 movhi r2,2054 + 8025a1c: 10b77017 ldw r2,-8768(r2) + 8025a20: 10800a17 ldw r2,40(r2) + 8025a24: 1004d23a srli r2,r2,8 + 8025a28: 10bfc00c andi r2,r2,65280 + 8025a2c: 2088b03a or r4,r4,r2 + 8025a30: 008201b4 movhi r2,2054 + 8025a34: 10b77017 ldw r2,-8768(r2) + 8025a38: 10800a17 ldw r2,40(r2) + 8025a3c: 1004923a slli r2,r2,8 + 8025a40: 10803fec andhi r2,r2,255 + 8025a44: 2088b03a or r4,r4,r2 + 8025a48: 008201b4 movhi r2,2054 + 8025a4c: 10b77017 ldw r2,-8768(r2) + 8025a50: 10800a17 ldw r2,40(r2) + 8025a54: 1004963a slli r2,r2,24 + 8025a58: 2084b03a or r2,r4,r2 + 8025a5c: 1887883a add r3,r3,r2 + 8025a60: e0bffe17 ldw r2,-8(fp) + 8025a64: 10800017 ldw r2,0(r2) + 8025a68: 1008d63a srli r4,r2,24 + 8025a6c: e0bffe17 ldw r2,-8(fp) + 8025a70: 10800017 ldw r2,0(r2) + 8025a74: 1004d23a srli r2,r2,8 + 8025a78: 10bfc00c andi r2,r2,65280 + 8025a7c: 2088b03a or r4,r4,r2 + 8025a80: e0bffe17 ldw r2,-8(fp) + 8025a84: 10800017 ldw r2,0(r2) + 8025a88: 1004923a slli r2,r2,8 + 8025a8c: 10803fec andhi r2,r2,255 + 8025a90: 2088b03a or r4,r4,r2 + 8025a94: e0bffe17 ldw r2,-8(fp) + 8025a98: 10800017 ldw r2,0(r2) + 8025a9c: 1004963a slli r2,r2,24 + 8025aa0: 2084b03a or r2,r4,r2 + 8025aa4: 1885883a add r2,r3,r2 + 8025aa8: 01400c84 movi r5,50 + 8025aac: 1009883a mov r4,r2 + 8025ab0: 800d05c0 call 800d05c <__umodsi3> + 8025ab4: 10c00044 addi r3,r2,1 + 8025ab8: e0bffe17 ldw r2,-8(fp) + 8025abc: 10c00315 stw r3,12(r2) + if (ifp->igmp_oper_mode == IGMP_MODE_V2) + 8025ac0: e0bfff17 ldw r2,-4(fp) + 8025ac4: 10802f03 ldbu r2,188(r2) + 8025ac8: 10803fcc andi r2,r2,255 + 8025acc: 10800098 cmpnei r2,r2,2 + 8025ad0: 1000031e bne r2,zero,8025ae0 + inm->last2send_report = IGMP_TRUE; + 8025ad4: e0bffe17 ldw r2,-8(fp) + 8025ad8: 00c00044 movi r3,1 + 8025adc: 10c00405 stb r3,16(r2) + ++igmp_timers_are_running; + 8025ae0: d0a06917 ldw r2,-32348(gp) + 8025ae4: 10800044 addi r2,r2,1 + 8025ae8: d0a06915 stw r2,-32348(gp) + return; + 8025aec: 0001883a nop +} + 8025af0: e037883a mov sp,fp + 8025af4: dfc00117 ldw ra,4(sp) + 8025af8: df000017 ldw fp,0(sp) + 8025afc: dec00204 addi sp,sp,8 + 8025b00: f800283a ret + +08025b04 : + * + * OUTPUT: None. + */ + +void igmp_leavegroup (struct in_multi * inm) +{ + 8025b04: defffc04 addi sp,sp,-16 + 8025b08: dfc00315 stw ra,12(sp) + 8025b0c: df000215 stw fp,8(sp) + 8025b10: df000204 addi fp,sp,8 + 8025b14: e13ffe15 stw r4,-8(fp) + NET ifp; + + ifp = inm->inm_netp; + 8025b18: e0bffe17 ldw r2,-8(fp) + 8025b1c: 10800117 ldw r2,4(r2) + 8025b20: e0bfff15 stw r2,-4(fp) + + if ((ifp->igmp_oper_mode == IGMP_MODE_V2) && + 8025b24: e0bfff17 ldw r2,-4(fp) + 8025b28: 10802f03 ldbu r2,188(r2) + 8025b2c: 10803fcc andi r2,r2,255 + 8025b30: 10800098 cmpnei r2,r2,2 + 8025b34: 10000d1e bne r2,zero,8025b6c + !ifp->igmpv1_rtr_present) + 8025b38: e0bfff17 ldw r2,-4(fp) + 8025b3c: 10802d03 ldbu r2,180(r2) + if ((ifp->igmp_oper_mode == IGMP_MODE_V2) && + 8025b40: 10803fcc andi r2,r2,255 + 8025b44: 1000091e bne r2,zero,8025b6c + { + if (inm->last2send_report == IGMP_TRUE) + 8025b48: e0bffe17 ldw r2,-8(fp) + 8025b4c: 10800403 ldbu r2,16(r2) + 8025b50: 10803fcc andi r2,r2,255 + 8025b54: 10800058 cmpnei r2,r2,1 + 8025b58: 1000041e bne r2,zero,8025b6c + igmp_send (IGMPv2_LEAVE_GROUP, inm); + 8025b5c: e17ffe17 ldw r5,-8(fp) + 8025b60: 010005c4 movi r4,23 + 8025b64: 802565c0 call 802565c + } + + return; + 8025b68: 0001883a nop + 8025b6c: 0001883a nop +} + 8025b70: e037883a mov sp,fp + 8025b74: dfc00117 ldw ra,4(sp) + 8025b78: df000017 ldw fp,0(sp) + 8025b7c: dec00204 addi sp,sp,8 + 8025b80: f800283a ret + +08025b84 : + * validation fails; otherwise, it returns + * IGMP_OK. + */ + +int igmp_validate (PACKET p) +{ + 8025b84: defff604 addi sp,sp,-40 + 8025b88: dfc00915 stw ra,36(sp) + 8025b8c: df000815 stw fp,32(sp) + 8025b90: df000804 addi fp,sp,32 + 8025b94: e13ff815 stw r4,-32(fp) + u_short xsum; + u_char type; + ip_addr mcgrp_addr; + u_char resp_time; + + pip = ip_head (p); + 8025b98: e0bff817 ldw r2,-32(fp) + 8025b9c: 10800317 ldw r2,12(r2) + 8025ba0: e0bfff15 stw r2,-4(fp) + + /* compute length of IGMP packet (after accounting for IP header, + * including the IP Router Alert option (if present)) */ + igmplen = p->nb_plen - ip_hlen (pip); + 8025ba4: e0bff817 ldw r2,-32(fp) + 8025ba8: 10c00417 ldw r3,16(r2) + 8025bac: e0bfff17 ldw r2,-4(fp) + 8025bb0: 10800003 ldbu r2,0(r2) + 8025bb4: 10803fcc andi r2,r2,255 + 8025bb8: 100490ba slli r2,r2,2 + 8025bbc: 10800f0c andi r2,r2,60 + 8025bc0: 1885c83a sub r2,r3,r2 + 8025bc4: e0bffe15 stw r2,-8(fp) + + /* validate length (IGMP_MINLEN is 8 bytes) */ + if (igmplen != IGMP_MINLEN) + 8025bc8: e0bffe17 ldw r2,-8(fp) + 8025bcc: 10800220 cmpeqi r2,r2,8 + 8025bd0: 1000071e bne r2,zero,8025bf0 + { + ++igmpstats.igmp_badlen_rcvd; + 8025bd4: 008201b4 movhi r2,2054 + 8025bd8: 10b77e17 ldw r2,-8712(r2) + 8025bdc: 10c00044 addi r3,r2,1 + 8025be0: 008201b4 movhi r2,2054 + 8025be4: 10f77e15 stw r3,-8712(r2) + return ENP_BAD_HEADER; + 8025be8: 00bff804 movi r2,-32 + 8025bec: 00009706 br 8025e4c + } + + /* validate checksum */ + igmp = (struct igmp *) (ip_data (pip)); + 8025bf0: e0bfff17 ldw r2,-4(fp) + 8025bf4: 10800003 ldbu r2,0(r2) + 8025bf8: 10803fcc andi r2,r2,255 + 8025bfc: 100490ba slli r2,r2,2 + 8025c00: 10800f0c andi r2,r2,60 + 8025c04: e0ffff17 ldw r3,-4(fp) + 8025c08: 1885883a add r2,r3,r2 + 8025c0c: e0bffd15 stw r2,-12(fp) + osum = igmp->igmp_cksum; + 8025c10: e0bffd17 ldw r2,-12(fp) + 8025c14: 1080008b ldhu r2,2(r2) + 8025c18: e0bffc8d sth r2,-14(fp) + igmp->igmp_cksum = 0; + 8025c1c: e0bffd17 ldw r2,-12(fp) + 8025c20: 1000008d sth zero,2(r2) + xsum = ~cksum(igmp, igmplen>>1); + 8025c24: e0bffe17 ldw r2,-8(fp) + 8025c28: 1005d07a srai r2,r2,1 + 8025c2c: 100b883a mov r5,r2 + 8025c30: e13ffd17 ldw r4,-12(fp) + 8025c34: 8026d7c0 call 8026d7c + 8025c38: 0084303a nor r2,zero,r2 + 8025c3c: e0bffc0d sth r2,-16(fp) + if (xsum != osum) + 8025c40: e0fffc0b ldhu r3,-16(fp) + 8025c44: e0bffc8b ldhu r2,-14(fp) + 8025c48: 18800a26 beq r3,r2,8025c74 + { + igmp->igmp_cksum = osum; + 8025c4c: e0bffd17 ldw r2,-12(fp) + 8025c50: e0fffc8b ldhu r3,-14(fp) + 8025c54: 10c0008d sth r3,2(r2) + ++igmpstats.igmp_badsum_rcvd; + 8025c58: 008201b4 movhi r2,2054 + 8025c5c: 10b77f17 ldw r2,-8708(r2) + 8025c60: 10c00044 addi r3,r2,1 + 8025c64: 008201b4 movhi r2,2054 + 8025c68: 10f77f15 stw r3,-8708(r2) + return ENP_BAD_HEADER; + 8025c6c: 00bff804 movi r2,-32 + 8025c70: 00007606 br 8025e4c + } + + /* extract the IGMP packet type, Group Address, and Max Response Time + * (unused for IGMPv1) fields from received packet */ + type = igmp->igmp_type; + 8025c74: e0bffd17 ldw r2,-12(fp) + 8025c78: 10800003 ldbu r2,0(r2) + 8025c7c: e0bffbc5 stb r2,-17(fp) + mcgrp_addr = ntohl(igmp->igmp_group); + 8025c80: e0bffd17 ldw r2,-12(fp) + 8025c84: 10800117 ldw r2,4(r2) + 8025c88: 1006d63a srli r3,r2,24 + 8025c8c: e0bffd17 ldw r2,-12(fp) + 8025c90: 10800117 ldw r2,4(r2) + 8025c94: 1004d23a srli r2,r2,8 + 8025c98: 10bfc00c andi r2,r2,65280 + 8025c9c: 1886b03a or r3,r3,r2 + 8025ca0: e0bffd17 ldw r2,-12(fp) + 8025ca4: 10800117 ldw r2,4(r2) + 8025ca8: 1004923a slli r2,r2,8 + 8025cac: 10803fec andhi r2,r2,255 + 8025cb0: 1886b03a or r3,r3,r2 + 8025cb4: e0bffd17 ldw r2,-12(fp) + 8025cb8: 10800117 ldw r2,4(r2) + 8025cbc: 1004963a slli r2,r2,24 + 8025cc0: 1884b03a or r2,r3,r2 + 8025cc4: e0bffa15 stw r2,-24(fp) + resp_time = igmp->igmp_code; + 8025cc8: e0bffd17 ldw r2,-12(fp) + 8025ccc: 10800043 ldbu r2,1(r2) + 8025cd0: e0bff9c5 stb r2,-25(fp) + + if (type == IGMP_HOST_MEMBERSHIP_QUERY) + 8025cd4: e0bffbc3 ldbu r2,-17(fp) + 8025cd8: 10800458 cmpnei r2,r2,17 + 8025cdc: 10002c1e bne r2,zero,8025d90 + { + if ((resp_time == 0) || /* IGMPv1 Query */ + 8025ce0: e0bff9c3 ldbu r2,-25(fp) + 8025ce4: 10000426 beq r2,zero,8025cf8 + 8025ce8: e0bff9c3 ldbu r2,-25(fp) + 8025cec: 10000d26 beq r2,zero,8025d24 + ((resp_time > 0) && (mcgrp_addr == 0))) /* IGMPv2 General Query */ + 8025cf0: e0bffa17 ldw r2,-24(fp) + 8025cf4: 10000b1e bne r2,zero,8025d24 + { + /* if this is a IGMPv1 Host Membership Query or a IGMPv2 + * General Query, it must be addressed to the all-hosts + * group */ + if (pip->ip_dest != igmp_all_hosts_group) + 8025cf8: e0bfff17 ldw r2,-4(fp) + 8025cfc: 10c00417 ldw r3,16(r2) + 8025d00: d0a06b17 ldw r2,-32340(gp) + 8025d04: 18800726 beq r3,r2,8025d24 + { + ++igmpstats.igmp_bad_queries_rcvd; + 8025d08: 008201b4 movhi r2,2054 + 8025d0c: 10b78217 ldw r2,-8696(r2) + 8025d10: 10c00044 addi r3,r2,1 + 8025d14: 008201b4 movhi r2,2054 + 8025d18: 10f78215 stw r3,-8696(r2) + return ENP_BAD_HEADER; + 8025d1c: 00bff804 movi r2,-32 + 8025d20: 00004a06 br 8025e4c + } + } + + if ((resp_time > 0) && (mcgrp_addr != 0)) + 8025d24: e0bff9c3 ldbu r2,-25(fp) + 8025d28: 10001926 beq r2,zero,8025d90 + 8025d2c: e0bffa17 ldw r2,-24(fp) + 8025d30: 10001726 beq r2,zero,8025d90 + { + /* this is a IGMPv2 Group-Specific Query. */ + if (p->net->igmp_oper_mode == IGMP_MODE_V1) + 8025d34: e0bff817 ldw r2,-32(fp) + 8025d38: 10800617 ldw r2,24(r2) + 8025d3c: 10802f03 ldbu r2,188(r2) + 8025d40: 10803fcc andi r2,r2,255 + 8025d44: 10800058 cmpnei r2,r2,1 + 8025d48: 1000021e bne r2,zero,8025d54 + { + /* IGMPv1 code does not understand a IGMPv2 Group- + * Specific Query */ + return ENP_BAD_HEADER; + 8025d4c: 00bff804 movi r2,-32 + 8025d50: 00003e06 br 8025e4c + /* check to make sure that the group address field carries + * a valid multicast address; if it doesn't, we + * drop the packet. Also drop packets that + * carry the multicast address for the all-hosts + * group. */ + if ((!IN_MULTICAST(mcgrp_addr)) || + 8025d54: e0bffa17 ldw r2,-24(fp) + 8025d58: 10fc002c andhi r3,r2,61440 + 8025d5c: 00b80034 movhi r2,57344 + 8025d60: 1880041e bne r3,r2,8025d74 + /* igmp_all_hosts_group is already in network byte order */ + (igmp->igmp_group == igmp_all_hosts_group)) + 8025d64: e0bffd17 ldw r2,-12(fp) + 8025d68: 10c00117 ldw r3,4(r2) + 8025d6c: d0a06b17 ldw r2,-32340(gp) + if ((!IN_MULTICAST(mcgrp_addr)) || + 8025d70: 1880071e bne r3,r2,8025d90 + { + ++igmpstats.igmpv2mode_v2_bad_grp_specific_queries_rcvd; + 8025d74: 008201b4 movhi r2,2054 + 8025d78: 10b78517 ldw r2,-8684(r2) + 8025d7c: 10c00044 addi r3,r2,1 + 8025d80: 008201b4 movhi r2,2054 + 8025d84: 10f78515 stw r3,-8684(r2) + /* caller will free received packet */ + return ENP_BAD_HEADER; + 8025d88: 00bff804 movi r2,-32 + 8025d8c: 00002f06 br 8025e4c + + /* check to ensure that a received IGMPv1 or v2 Report has the + * same IP host group address in its IP destination field and + * its IGMP group address field, and that the group address is + * a valid multicast address */ + if ((type == IGMP_HOST_MEMBERSHIP_REPORT) || + 8025d90: e0bffbc3 ldbu r2,-17(fp) + 8025d94: 108004a0 cmpeqi r2,r2,18 + 8025d98: 1000031e bne r2,zero,8025da8 + 8025d9c: e0bffbc3 ldbu r2,-17(fp) + 8025da0: 10800598 cmpnei r2,r2,22 + 8025da4: 1000101e bne r2,zero,8025de8 + (type == IGMPv2_MEMBERSHIP_REPORT)) + { + if ((igmp->igmp_group != pip->ip_dest) || + 8025da8: e0bffd17 ldw r2,-12(fp) + 8025dac: 10c00117 ldw r3,4(r2) + 8025db0: e0bfff17 ldw r2,-4(fp) + 8025db4: 10800417 ldw r2,16(r2) + 8025db8: 1880041e bne r3,r2,8025dcc + (!IN_MULTICAST(mcgrp_addr))) + 8025dbc: e0bffa17 ldw r2,-24(fp) + 8025dc0: 10fc002c andhi r3,r2,61440 + if ((igmp->igmp_group != pip->ip_dest) || + 8025dc4: 00b80034 movhi r2,57344 + 8025dc8: 18800726 beq r3,r2,8025de8 + { + ++igmpstats.igmp_bad_reports_rcvd; + 8025dcc: 008201b4 movhi r2,2054 + 8025dd0: 10b78317 ldw r2,-8692(r2) + 8025dd4: 10c00044 addi r3,r2,1 + 8025dd8: 008201b4 movhi r2,2054 + 8025ddc: 10f78315 stw r3,-8692(r2) + return ENP_BAD_HEADER; + 8025de0: 00bff804 movi r2,-32 + 8025de4: 00001906 br 8025e4c + + * Version 1 Host Membership Reports and Version 1 Host Membership Query + * packets will not be checked for the IP Router Alert option. + */ +#ifdef IGMP_V2 + if ((type == IGMPv2_LEAVE_GROUP) || + 8025de8: e0bffbc3 ldbu r2,-17(fp) + 8025dec: 108005e0 cmpeqi r2,r2,23 + 8025df0: 10000a1e bne r2,zero,8025e1c + 8025df4: e0bffbc3 ldbu r2,-17(fp) + 8025df8: 108005a0 cmpeqi r2,r2,22 + 8025dfc: 1000071e bne r2,zero,8025e1c + (type == IGMPv2_MEMBERSHIP_REPORT) || + 8025e00: e0bffbc3 ldbu r2,-17(fp) + 8025e04: 10800458 cmpnei r2,r2,17 + 8025e08: 10000f1e bne r2,zero,8025e48 + ((type == IGMP_HOST_MEMBERSHIP_QUERY) && (igmp->igmp_code > 0))) + 8025e0c: e0bffd17 ldw r2,-12(fp) + 8025e10: 10800043 ldbu r2,1(r2) + 8025e14: 10803fcc andi r2,r2,255 + 8025e18: 10000b26 beq r2,zero,8025e48 + + { + if (!igmpv2_chk4_rtr_alert_opt (pip)) + 8025e1c: e13fff17 ldw r4,-4(fp) + 8025e20: 803e5740 call 803e574 + 8025e24: 10803fcc andi r2,r2,255 + 8025e28: 1000071e bne r2,zero,8025e48 + { + ++igmpstats.igmpv2mode_v2_rtr_alert_missing; + 8025e2c: 008201b4 movhi r2,2054 + 8025e30: 10b78817 ldw r2,-8672(r2) + 8025e34: 10c00044 addi r3,r2,1 + 8025e38: 008201b4 movhi r2,2054 + 8025e3c: 10f78815 stw r3,-8672(r2) + return ENP_BAD_HEADER; + 8025e40: 00bff804 movi r2,-32 + 8025e44: 00000106 br 8025e4c + } + } +#endif + + /* validation successful */ + return IGMP_OK; + 8025e48: 0005883a mov r2,zero +} + 8025e4c: e037883a mov sp,fp + 8025e50: dfc00117 ldw ra,4(sp) + 8025e54: df000017 ldw fp,0(sp) + 8025e58: dec00204 addi sp,sp,8 + 8025e5c: f800283a ret + +08025e60 : + * + * OUTPUT: This function always returns IGMP_OK. + */ + +int igmp_print_stats (void * pio) +{ + 8025e60: defffa04 addi sp,sp,-24 + 8025e64: dfc00515 stw ra,20(sp) + 8025e68: df000415 stw fp,16(sp) + 8025e6c: df000404 addi fp,sp,16 + 8025e70: e13ffe15 stw r4,-8(fp) + NET ifp; + + for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next) + 8025e74: 008201b4 movhi r2,2054 + 8025e78: 10b6a617 ldw r2,-9576(r2) + 8025e7c: e0bfff15 stw r2,-4(fp) + 8025e80: 00003b06 br 8025f70 + { + ns_printf (pio, "%s: mode: %u [%s] ", + ifp->name, + 8025e84: e0bfff17 ldw r2,-4(fp) + 8025e88: 10c00104 addi r3,r2,4 + ifp->igmp_oper_mode, + 8025e8c: e0bfff17 ldw r2,-4(fp) + 8025e90: 10802f03 ldbu r2,188(r2) + ns_printf (pio, "%s: mode: %u [%s] ", + 8025e94: 11003fcc andi r4,r2,255 + ((ifp->igmp_oper_mode == IGMP_MODE_V1)? "v1":"v2")); + 8025e98: e0bfff17 ldw r2,-4(fp) + 8025e9c: 10802f03 ldbu r2,188(r2) + ns_printf (pio, "%s: mode: %u [%s] ", + 8025ea0: 10803fcc andi r2,r2,255 + 8025ea4: 10800058 cmpnei r2,r2,1 + 8025ea8: 1000031e bne r2,zero,8025eb8 + 8025eac: 00820174 movhi r2,2053 + 8025eb0: 10a72e04 addi r2,r2,-25416 + 8025eb4: 00000206 br 8025ec0 + 8025eb8: 00820174 movhi r2,2053 + 8025ebc: 10a72f04 addi r2,r2,-25412 + 8025ec0: d8800015 stw r2,0(sp) + 8025ec4: 200f883a mov r7,r4 + 8025ec8: 180d883a mov r6,r3 + 8025ecc: 01420174 movhi r5,2053 + 8025ed0: 29673004 addi r5,r5,-25408 + 8025ed4: e13ffe17 ldw r4,-8(fp) + 8025ed8: 80273900 call 8027390 + /* if a link has been configured for IGMPv2, display the status + * of the v1 router-related variables too */ + if (ifp->igmp_oper_mode == IGMP_MODE_V2) + 8025edc: e0bfff17 ldw r2,-4(fp) + 8025ee0: 10802f03 ldbu r2,188(r2) + 8025ee4: 10803fcc andi r2,r2,255 + 8025ee8: 10800098 cmpnei r2,r2,2 + 8025eec: 1000191e bne r2,zero,8025f54 + { + ns_printf (pio, "v1 rtr: %u [%s] v1 last query: %x [now %x]\n", + ifp->igmpv1_rtr_present, + 8025ef0: e0bfff17 ldw r2,-4(fp) + 8025ef4: 10802d03 ldbu r2,180(r2) + ns_printf (pio, "v1 rtr: %u [%s] v1 last query: %x [now %x]\n", + 8025ef8: 11403fcc andi r5,r2,255 + ((ifp->igmpv1_rtr_present == IGMP_TRUE)? "present" : "absent"), + 8025efc: e0bfff17 ldw r2,-4(fp) + 8025f00: 10802d03 ldbu r2,180(r2) + ns_printf (pio, "v1 rtr: %u [%s] v1 last query: %x [now %x]\n", + 8025f04: 10803fcc andi r2,r2,255 + 8025f08: 10800058 cmpnei r2,r2,1 + 8025f0c: 1000031e bne r2,zero,8025f1c + 8025f10: 00820174 movhi r2,2053 + 8025f14: 10a73504 addi r2,r2,-25388 + 8025f18: 00000206 br 8025f24 + 8025f1c: 00820174 movhi r2,2053 + 8025f20: 10a73704 addi r2,r2,-25380 + 8025f24: e0ffff17 ldw r3,-4(fp) + 8025f28: 18c02e17 ldw r3,184(r3) + 8025f2c: d1207d17 ldw r4,-32268(gp) + 8025f30: d9000115 stw r4,4(sp) + 8025f34: d8c00015 stw r3,0(sp) + 8025f38: 100f883a mov r7,r2 + 8025f3c: 280d883a mov r6,r5 + 8025f40: 01420174 movhi r5,2053 + 8025f44: 29673904 addi r5,r5,-25372 + 8025f48: e13ffe17 ldw r4,-8(fp) + 8025f4c: 80273900 call 8027390 + 8025f50: 00000406 br 8025f64 + ifp->igmpv1_query_rcvd_time, + cticks); + } + else ns_printf (pio, "\n"); + 8025f54: 01420174 movhi r5,2053 + 8025f58: 29674404 addi r5,r5,-25328 + 8025f5c: e13ffe17 ldw r4,-8(fp) + 8025f60: 80273900 call 8027390 + for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next) + 8025f64: e0bfff17 ldw r2,-4(fp) + 8025f68: 10800017 ldw r2,0(r2) + 8025f6c: e0bfff15 stw r2,-4(fp) + 8025f70: e0bfff17 ldw r2,-4(fp) + 8025f74: 103fc31e bne r2,zero,8025e84 + } + + /* rx and timer statistics */ + ns_printf (pio, "[Rx ] IGMP messages rcvd: %lu, timers running: %lu\n", igmpstats.igmp_total_rcvd, igmp_timers_are_running); + 8025f78: 008201b4 movhi r2,2054 + 8025f7c: 10b77417 ldw r2,-8752(r2) + 8025f80: d0e06917 ldw r3,-32348(gp) + 8025f84: 180f883a mov r7,r3 + 8025f88: 100d883a mov r6,r2 + 8025f8c: 01420174 movhi r5,2053 + 8025f90: 29674504 addi r5,r5,-25324 + 8025f94: e13ffe17 ldw r4,-8(fp) + 8025f98: 80273900 call 8027390 + + ns_printf (pio, "[Rx ] IGMPv1 Host Membership Queries rcvd (by v1-mode links): %lu\n", igmpstats.igmpv1mode_v1_queries_rcvd); + 8025f9c: 008201b4 movhi r2,2054 + 8025fa0: 10b77517 ldw r2,-8748(r2) + 8025fa4: 100d883a mov r6,r2 + 8025fa8: 01420174 movhi r5,2053 + 8025fac: 29675204 addi r5,r5,-25272 + 8025fb0: e13ffe17 ldw r4,-8(fp) + 8025fb4: 80273900 call 8027390 + ns_printf (pio, "[Rx ] IGMPv1 Host Membership Reports rcvd: %lu\n", igmpstats.igmpv1mode_v1_reports_rcvd); + 8025fb8: 008201b4 movhi r2,2054 + 8025fbc: 10b77617 ldw r2,-8744(r2) + 8025fc0: 100d883a mov r6,r2 + 8025fc4: 01420174 movhi r5,2053 + 8025fc8: 29676304 addi r5,r5,-25204 + 8025fcc: e13ffe17 ldw r4,-8(fp) + 8025fd0: 80273900 call 8027390 + ns_printf (pio, "[Rx ] IGMP Host Membership Reports rcvd causing timer cancellation: %lu\n", igmpstats.igmpv1mode_v1_reports_rcvd_canceled_timer); + 8025fd4: 008201b4 movhi r2,2054 + 8025fd8: 10b77717 ldw r2,-8740(r2) + 8025fdc: 100d883a mov r6,r2 + 8025fe0: 01420174 movhi r5,2053 + 8025fe4: 29676f04 addi r5,r5,-25156 + 8025fe8: e13ffe17 ldw r4,-8(fp) + 8025fec: 80273900 call 8027390 + + ns_printf (pio, "[Rx ] IGMPv1 Host Membership Queries rcvd (by v2-mode links): %lu\n", igmpstats.igmpv2mode_v1_queries_rcvd); + 8025ff0: 008201b4 movhi r2,2054 + 8025ff4: 10b77817 ldw r2,-8736(r2) + 8025ff8: 100d883a mov r6,r2 + 8025ffc: 01420174 movhi r5,2053 + 8026000: 29678204 addi r5,r5,-25080 + 8026004: e13ffe17 ldw r4,-8(fp) + 8026008: 80273900 call 8027390 + ns_printf (pio, "[Rx ] IGMPv2 General Queries rcvd: %lu, Group-Specific Queries rcvd: %lu\n", igmpstats.igmpv2mode_v2_general_queries_rcvd, igmpstats.igmpv2mode_v2_grp_specific_queries_rcvd); + 802600c: 008201b4 movhi r2,2054 + 8026010: 10f77917 ldw r3,-8732(r2) + 8026014: 008201b4 movhi r2,2054 + 8026018: 10b77a17 ldw r2,-8728(r2) + 802601c: 100f883a mov r7,r2 + 8026020: 180d883a mov r6,r3 + 8026024: 01420174 movhi r5,2053 + 8026028: 29679304 addi r5,r5,-25012 + 802602c: e13ffe17 ldw r4,-8(fp) + 8026030: 80273900 call 8027390 + ns_printf (pio, "[Rx ] IGMP Host Membership Reports rcvd causing timer cancellation: %lu\n", igmpstats.igmpv2mode_v12_reports_rcvd_canceled_timer); + 8026034: 008201b4 movhi r2,2054 + 8026038: 10b77b17 ldw r2,-8724(r2) + 802603c: 100d883a mov r6,r2 + 8026040: 01420174 movhi r5,2053 + 8026044: 29676f04 addi r5,r5,-25156 + 8026048: e13ffe17 ldw r4,-8(fp) + 802604c: 80273900 call 8027390 + ns_printf (pio, "[Rx ] IGMP Host Membership Reports rcvd with no local timer: %lu\n", igmpstats.igmpv2mode_v12_reports_rcvd_no_timer); + 8026050: 008201b4 movhi r2,2054 + 8026054: 10b77c17 ldw r2,-8720(r2) + 8026058: 100d883a mov r6,r2 + 802605c: 01420174 movhi r5,2053 + 8026060: 2967a604 addi r5,r5,-24936 + 8026064: e13ffe17 ldw r4,-8(fp) + 8026068: 80273900 call 8027390 + ns_printf (pio, "[Rx ] IGMPv2 Leave Group messages rcvd: %lu\n", igmpstats.igmpv2mode_v2_leave_msgs_rcvd); + 802606c: 008201b4 movhi r2,2054 + 8026070: 10b77d17 ldw r2,-8716(r2) + 8026074: 100d883a mov r6,r2 + 8026078: 01420174 movhi r5,2053 + 802607c: 2967b704 addi r5,r5,-24868 + 8026080: e13ffe17 ldw r4,-8(fp) + 8026084: 80273900 call 8027390 + + /* tx statistics */ + ns_printf (pio, "[Tx ] IGMPv2 Leave Group messages sent: %lu, Membership Reports sent: %lu\n", igmpstats.igmpv2mode_v2_leave_msgs_sent, igmpstats.igmpv2mode_v2_reports_sent); + 8026088: 008201b4 movhi r2,2054 + 802608c: 10f78b17 ldw r3,-8660(r2) + 8026090: 008201b4 movhi r2,2054 + 8026094: 10b78c17 ldw r2,-8656(r2) + 8026098: 100f883a mov r7,r2 + 802609c: 180d883a mov r6,r3 + 80260a0: 01420174 movhi r5,2053 + 80260a4: 2967c304 addi r5,r5,-24820 + 80260a8: e13ffe17 ldw r4,-8(fp) + 80260ac: 80273900 call 8027390 + ns_printf (pio, "[Tx ] IGMPv1 Host Membership Reports sent: %lu\n", igmpstats.igmp_v1_reports_sent); + 80260b0: 008201b4 movhi r2,2054 + 80260b4: 10b78a17 ldw r2,-8664(r2) + 80260b8: 100d883a mov r6,r2 + 80260bc: 01420174 movhi r5,2053 + 80260c0: 2967d604 addi r5,r5,-24744 + 80260c4: e13ffe17 ldw r4,-8(fp) + 80260c8: 80273900 call 8027390 + + /* error statistics */ + ns_printf (pio, "[Err] IGMP packets rcvd with bad length: %lu\n", igmpstats.igmp_badlen_rcvd); + 80260cc: 008201b4 movhi r2,2054 + 80260d0: 10b77e17 ldw r2,-8712(r2) + 80260d4: 100d883a mov r6,r2 + 80260d8: 01420174 movhi r5,2053 + 80260dc: 2967e204 addi r5,r5,-24696 + 80260e0: e13ffe17 ldw r4,-8(fp) + 80260e4: 80273900 call 8027390 + ns_printf (pio, "[Err] IGMP packets rcvd with bad checksum: %lu\n", igmpstats.igmp_badsum_rcvd); + 80260e8: 008201b4 movhi r2,2054 + 80260ec: 10b77f17 ldw r2,-8708(r2) + 80260f0: 100d883a mov r6,r2 + 80260f4: 01420174 movhi r5,2053 + 80260f8: 2967ee04 addi r5,r5,-24648 + 80260fc: e13ffe17 ldw r4,-8(fp) + 8026100: 80273900 call 8027390 + ns_printf (pio, "[Err] Packet buffer allocation failures: %lu, Bad IGMP Oper Mode config: %lu\n",igmpstats.igmp_pkt_alloc_fail, igmpstats.igmp_bad_oper_mode); + 8026104: 008201b4 movhi r2,2054 + 8026108: 10f78017 ldw r3,-8704(r2) + 802610c: 008201b4 movhi r2,2054 + 8026110: 10b78117 ldw r2,-8700(r2) + 8026114: 100f883a mov r7,r2 + 8026118: 180d883a mov r6,r3 + 802611c: 01420174 movhi r5,2053 + 8026120: 2967fa04 addi r5,r5,-24600 + 8026124: e13ffe17 ldw r4,-8(fp) + 8026128: 80273900 call 8027390 + ns_printf (pio, "[Err] Bad IGMP Queries rcvd: %lu, Bad IGMP Reports rcvd: %lu\n", igmpstats.igmp_bad_queries_rcvd, igmpstats.igmp_bad_reports_rcvd); + 802612c: 008201b4 movhi r2,2054 + 8026130: 10f78217 ldw r3,-8696(r2) + 8026134: 008201b4 movhi r2,2054 + 8026138: 10b78317 ldw r2,-8692(r2) + 802613c: 100f883a mov r7,r2 + 8026140: 180d883a mov r6,r3 + 8026144: 01420174 movhi r5,2053 + 8026148: 29680e04 addi r5,r5,-24520 + 802614c: e13ffe17 ldw r4,-8(fp) + 8026150: 80273900 call 8027390 + ns_printf (pio, "[Err] Bad IGMPv2 Group-Specific Queries rcvd: %lu\n", igmpstats.igmpv2mode_v2_bad_grp_specific_queries_rcvd); + 8026154: 008201b4 movhi r2,2054 + 8026158: 10b78517 ldw r2,-8684(r2) + 802615c: 100d883a mov r6,r2 + 8026160: 01420174 movhi r5,2053 + 8026164: 29681e04 addi r5,r5,-24456 + 8026168: e13ffe17 ldw r4,-8(fp) + 802616c: 80273900 call 8027390 + ns_printf (pio, "[Err] IGMPv2 Group-Specific Queries rcvd with unknown Group Address: %lu\n", igmpstats.igmpv2mode_v2_unknown_grp_specific_queries_rcvd); + 8026170: 008201b4 movhi r2,2054 + 8026174: 10b78617 ldw r2,-8680(r2) + 8026178: 100d883a mov r6,r2 + 802617c: 01420174 movhi r5,2053 + 8026180: 29682b04 addi r5,r5,-24404 + 8026184: e13ffe17 ldw r4,-8(fp) + 8026188: 80273900 call 8027390 + ns_printf (pio, "[Err] IGMP Membership Reports rcvd with unknown Group Address: %lu\n", igmpstats.igmpv2mode_v12_unknown_grp_reports_rcvd); + 802618c: 008201b4 movhi r2,2054 + 8026190: 10b78717 ldw r2,-8676(r2) + 8026194: 100d883a mov r6,r2 + 8026198: 01420174 movhi r5,2053 + 802619c: 29683e04 addi r5,r5,-24328 + 80261a0: e13ffe17 ldw r4,-8(fp) + 80261a4: 80273900 call 8027390 + ns_printf (pio, "[Err] Number of IGMPv2 messages rcvd without Router Alert option: %lu\n", igmpstats.igmpv2mode_v2_rtr_alert_missing); + 80261a8: 008201b4 movhi r2,2054 + 80261ac: 10b78817 ldw r2,-8672(r2) + 80261b0: 100d883a mov r6,r2 + 80261b4: 01420174 movhi r5,2053 + 80261b8: 29684f04 addi r5,r5,-24260 + 80261bc: e13ffe17 ldw r4,-8(fp) + 80261c0: 80273900 call 8027390 + ns_printf (pio, "[Err] IGMP packets of unknown type rcvd by v1-mode links: %lu\n", igmpstats.igmpv1mode_unknown_pkttype); + 80261c4: 008201b4 movhi r2,2054 + 80261c8: 10b78417 ldw r2,-8688(r2) + 80261cc: 100d883a mov r6,r2 + 80261d0: 01420174 movhi r5,2053 + 80261d4: 29686104 addi r5,r5,-24188 + 80261d8: e13ffe17 ldw r4,-8(fp) + 80261dc: 80273900 call 8027390 + ns_printf (pio, "[Err] IGMP packets of unknown type rcvd by v2-mode links: %lu\n", igmpstats.igmpv2mode_unknown_pkttype); + 80261e0: 008201b4 movhi r2,2054 + 80261e4: 10b78917 ldw r2,-8668(r2) + 80261e8: 100d883a mov r6,r2 + 80261ec: 01420174 movhi r5,2053 + 80261f0: 29687104 addi r5,r5,-24124 + 80261f4: e13ffe17 ldw r4,-8(fp) + 80261f8: 80273900 call 8027390 + + return IGMP_OK; + 80261fc: 0005883a mov r2,zero +} + 8026200: e037883a mov sp,fp + 8026204: dfc00117 ldw ra,4(sp) + 8026208: df000017 ldw fp,0(sp) + 802620c: dec00204 addi sp,sp,8 + 8026210: f800283a ret + +08026214 : + * The error is available via bsd_errno(s). + */ +BSD_SOCKET +bsd_accept(BSD_SOCKET s, + struct sockaddr * addr, int * addrlen) +{ + 8026214: defff404 addi sp,sp,-48 + 8026218: dfc00b15 stw ra,44(sp) + 802621c: df000a15 stw fp,40(sp) + 8026220: df000a04 addi fp,sp,40 + 8026224: e13ff815 stw r4,-32(fp) + 8026228: e17ff715 stw r5,-36(fp) + 802622c: e1bff615 stw r6,-40(fp) + struct socket * so; + struct sockaddr laddr; + long lret; + + so = LONG2SO(s); + 8026230: e0bff817 ldw r2,-32(fp) + 8026234: 10bffc04 addi r2,r2,-16 + 8026238: 100490ba slli r2,r2,2 + 802623c: e0bffe15 stw r2,-8(fp) + SOC_CHECK(so); + 8026240: 008201b4 movhi r2,2054 + 8026244: 10b87104 addi r2,r2,-7740 + 8026248: e0bfff15 stw r2,-4(fp) + 802624c: 00000606 br 8026268 + 8026250: e0ffff17 ldw r3,-4(fp) + 8026254: e0bffe17 ldw r2,-8(fp) + 8026258: 18800626 beq r3,r2,8026274 + 802625c: e0bfff17 ldw r2,-4(fp) + 8026260: 10800017 ldw r2,0(r2) + 8026264: e0bfff15 stw r2,-4(fp) + 8026268: e0bfff17 ldw r2,-4(fp) + 802626c: 103ff81e bne r2,zero,8026250 + 8026270: 00000106 br 8026278 + 8026274: 0001883a nop + 8026278: e0ffff17 ldw r3,-4(fp) + 802627c: e0bffe17 ldw r2,-8(fp) + 8026280: 18800326 beq r3,r2,8026290 + 8026284: 8028cd40 call 8028cd4 + 8026288: 00bfffc4 movi r2,-1 + 802628c: 00002406 br 8026320 + + /* if we were given a buffer for the peer's address, also get the + * buffer's length + */ + if (addr != NULL) + 8026290: e0bff717 ldw r2,-36(fp) + 8026294: 10000726 beq r2,zero,80262b4 + { + if (addrlen == 0) + 8026298: e0bff617 ldw r2,-40(fp) + 802629c: 1000051e bne r2,zero,80262b4 + { + so->so_error = EFAULT; + 80262a0: e0bffe17 ldw r2,-8(fp) + 80262a4: 00c00384 movi r3,14 + 80262a8: 10c00615 stw r3,24(r2) + return -1; + 80262ac: 00bfffc4 movi r2,-1 + 80262b0: 00001b06 br 8026320 + } + } + + lret = t_accept(s, &laddr, addrlen); + 80262b4: e0bff904 addi r2,fp,-28 + 80262b8: e1bff617 ldw r6,-40(fp) + 80262bc: 100b883a mov r5,r2 + 80262c0: e13ff817 ldw r4,-32(fp) + 80262c4: 802bd240 call 802bd24 + 80262c8: e0bffd15 stw r2,-12(fp) + * address: copy the peer's address back into the buffer, but limit + * the copy to the lesser of the buffer's length and sizeof(struct + * sockaddr_in), which is all that t_accept() can return as a peer + * address. + */ + if ((lret != -1) && (addr != NULL)) + 80262cc: e0bffd17 ldw r2,-12(fp) + 80262d0: 10bfffe0 cmpeqi r2,r2,-1 + 80262d4: 1000111e bne r2,zero,802631c + 80262d8: e0bff717 ldw r2,-36(fp) + 80262dc: 10000f26 beq r2,zero,802631c + { + if (*addrlen > sizeof(struct sockaddr_in)) + 80262e0: e0bff617 ldw r2,-40(fp) + 80262e4: 10800017 ldw r2,0(r2) + 80262e8: 10800470 cmpltui r2,r2,17 + 80262ec: 1000031e bne r2,zero,80262fc + *addrlen = sizeof(struct sockaddr_in); + 80262f0: e0bff617 ldw r2,-40(fp) + 80262f4: 00c00404 movi r3,16 + 80262f8: 10c00015 stw r3,0(r2) + MEMCPY(addr, &laddr, *addrlen); + 80262fc: e0bff617 ldw r2,-40(fp) + 8026300: 10800017 ldw r2,0(r2) + 8026304: 1007883a mov r3,r2 + 8026308: e0bff904 addi r2,fp,-28 + 802630c: 180d883a mov r6,r3 + 8026310: 100b883a mov r5,r2 + 8026314: e13ff717 ldw r4,-36(fp) + 8026318: 80086b80 call 80086b8 + } + + return lret; + 802631c: e0bffd17 ldw r2,-12(fp) +} + 8026320: e037883a mov sp,fp + 8026324: dfc00117 ldw ra,4(sp) + 8026328: df000017 ldw fp,0(sp) + 802632c: dec00204 addi sp,sp,8 + 8026330: f800283a ret + +08026334 : + * available via bsd_errno(s). + */ +int +bsd_getpeername(BSD_SOCKET s, + struct sockaddr * name, int * namelen) +{ + 8026334: defff304 addi sp,sp,-52 + 8026338: dfc00c15 stw ra,48(sp) + 802633c: df000b15 stw fp,44(sp) + 8026340: df000b04 addi fp,sp,44 + 8026344: e13ff715 stw r4,-36(fp) + 8026348: e17ff615 stw r5,-40(fp) + 802634c: e1bff515 stw r6,-44(fp) + struct socket * so; + struct sockaddr lname; + int lnamelen; + int lret; + + so = LONG2SO(s); + 8026350: e0bff717 ldw r2,-36(fp) + 8026354: 10bffc04 addi r2,r2,-16 + 8026358: 100490ba slli r2,r2,2 + 802635c: e0bffe15 stw r2,-8(fp) + SOC_CHECK(so); + 8026360: 008201b4 movhi r2,2054 + 8026364: 10b87104 addi r2,r2,-7740 + 8026368: e0bfff15 stw r2,-4(fp) + 802636c: 00000606 br 8026388 + 8026370: e0ffff17 ldw r3,-4(fp) + 8026374: e0bffe17 ldw r2,-8(fp) + 8026378: 18800626 beq r3,r2,8026394 + 802637c: e0bfff17 ldw r2,-4(fp) + 8026380: 10800017 ldw r2,0(r2) + 8026384: e0bfff15 stw r2,-4(fp) + 8026388: e0bfff17 ldw r2,-4(fp) + 802638c: 103ff81e bne r2,zero,8026370 + 8026390: 00000106 br 8026398 + 8026394: 0001883a nop + 8026398: e0ffff17 ldw r3,-4(fp) + 802639c: e0bffe17 ldw r2,-8(fp) + 80263a0: 18800326 beq r3,r2,80263b0 + 80263a4: 8028cd40 call 8028cd4 + 80263a8: 00bfffc4 movi r2,-1 + 80263ac: 00002406 br 8026440 + + /* if the buffer length is bogus, fail */ + if (namelen == NULL) + 80263b0: e0bff517 ldw r2,-44(fp) + 80263b4: 1000051e bne r2,zero,80263cc + { + so->so_error = EFAULT; + 80263b8: e0bffe17 ldw r2,-8(fp) + 80263bc: 00c00384 movi r3,14 + 80263c0: 10c00615 stw r3,24(r2) + return -1; + 80263c4: 00bfffc4 movi r2,-1 + 80263c8: 00001d06 br 8026440 + } + lnamelen = *namelen; + 80263cc: e0bff517 ldw r2,-44(fp) + 80263d0: 10800017 ldw r2,0(r2) + 80263d4: e0bff815 stw r2,-32(fp) + + lret = t_getpeername(s, &lname, &lnamelen); + 80263d8: e0fff804 addi r3,fp,-32 + 80263dc: e0bff904 addi r2,fp,-28 + 80263e0: 180d883a mov r6,r3 + 80263e4: 100b883a mov r5,r2 + 80263e8: e13ff717 ldw r4,-36(fp) + 80263ec: 802c1e40 call 802c1e4 + 80263f0: e0bffd15 stw r2,-12(fp) + * t_getpeername() can return as a peer address, and pass the + * copied length back to the caller. + * For IPV6 addresses, or for dual IPV4/IPV6 stack, + * the max size is sizeof(struct sockaddr_in6) + */ + if (lret != -1) + 80263f4: e0bffd17 ldw r2,-12(fp) + 80263f8: 10bfffe0 cmpeqi r2,r2,-1 + 80263fc: 10000f1e bne r2,zero,802643c + { +#ifndef IP_V6 + if (lnamelen > sizeof(struct sockaddr_in)) + 8026400: e0bff817 ldw r2,-32(fp) + 8026404: 10800470 cmpltui r2,r2,17 + 8026408: 1000021e bne r2,zero,8026414 + lnamelen = sizeof(struct sockaddr_in); + 802640c: 00800404 movi r2,16 + 8026410: e0bff815 stw r2,-32(fp) +#else + if (lnamelen > sizeof(struct sockaddr_in6)) + lnamelen = sizeof(struct sockaddr_in6); + +#endif + MEMCPY(name, &lname, lnamelen); + 8026414: e0bff817 ldw r2,-32(fp) + 8026418: 1007883a mov r3,r2 + 802641c: e0bff904 addi r2,fp,-28 + 8026420: 180d883a mov r6,r3 + 8026424: 100b883a mov r5,r2 + 8026428: e13ff617 ldw r4,-40(fp) + 802642c: 80086b80 call 80086b8 + *namelen = lnamelen; + 8026430: e0fff817 ldw r3,-32(fp) + 8026434: e0bff517 ldw r2,-44(fp) + 8026438: 10c00015 stw r3,0(r2) + } + + return lret; + 802643c: e0bffd17 ldw r2,-12(fp) +} + 8026440: e037883a mov sp,fp + 8026444: dfc00117 ldw ra,4(sp) + 8026448: df000017 ldw fp,0(sp) + 802644c: dec00204 addi sp,sp,8 + 8026450: f800283a ret + +08026454 : + * available via bsd_errno(s). + */ +int +bsd_getsockname(BSD_SOCKET s, + struct sockaddr * name, int * namelen) +{ + 8026454: defff304 addi sp,sp,-52 + 8026458: dfc00c15 stw ra,48(sp) + 802645c: df000b15 stw fp,44(sp) + 8026460: df000b04 addi fp,sp,44 + 8026464: e13ff715 stw r4,-36(fp) + 8026468: e17ff615 stw r5,-40(fp) + 802646c: e1bff515 stw r6,-44(fp) + struct socket * so; + struct sockaddr lname; + int lnamelen; + int lret; + + so = LONG2SO(s); + 8026470: e0bff717 ldw r2,-36(fp) + 8026474: 10bffc04 addi r2,r2,-16 + 8026478: 100490ba slli r2,r2,2 + 802647c: e0bffe15 stw r2,-8(fp) + SOC_CHECK(so); + 8026480: 008201b4 movhi r2,2054 + 8026484: 10b87104 addi r2,r2,-7740 + 8026488: e0bfff15 stw r2,-4(fp) + 802648c: 00000606 br 80264a8 + 8026490: e0ffff17 ldw r3,-4(fp) + 8026494: e0bffe17 ldw r2,-8(fp) + 8026498: 18800626 beq r3,r2,80264b4 + 802649c: e0bfff17 ldw r2,-4(fp) + 80264a0: 10800017 ldw r2,0(r2) + 80264a4: e0bfff15 stw r2,-4(fp) + 80264a8: e0bfff17 ldw r2,-4(fp) + 80264ac: 103ff81e bne r2,zero,8026490 + 80264b0: 00000106 br 80264b8 + 80264b4: 0001883a nop + 80264b8: e0ffff17 ldw r3,-4(fp) + 80264bc: e0bffe17 ldw r2,-8(fp) + 80264c0: 18800326 beq r3,r2,80264d0 + 80264c4: 8028cd40 call 8028cd4 + 80264c8: 00bfffc4 movi r2,-1 + 80264cc: 00002406 br 8026560 + + /* if the buffer length is bogus, fail */ + if (namelen == NULL) + 80264d0: e0bff517 ldw r2,-44(fp) + 80264d4: 1000051e bne r2,zero,80264ec + { + so->so_error = EFAULT; + 80264d8: e0bffe17 ldw r2,-8(fp) + 80264dc: 00c00384 movi r3,14 + 80264e0: 10c00615 stw r3,24(r2) + return -1; + 80264e4: 00bfffc4 movi r2,-1 + 80264e8: 00001d06 br 8026560 + } + lnamelen = *namelen; + 80264ec: e0bff517 ldw r2,-44(fp) + 80264f0: 10800017 ldw r2,0(r2) + 80264f4: e0bff815 stw r2,-32(fp) + + lret = t_getsockname(s, &lname, &lnamelen); + 80264f8: e0fff804 addi r3,fp,-32 + 80264fc: e0bff904 addi r2,fp,-28 + 8026500: 180d883a mov r6,r3 + 8026504: 100b883a mov r5,r2 + 8026508: e13ff717 ldw r4,-36(fp) + 802650c: 802c2280 call 802c228 + 8026510: e0bffd15 stw r2,-12(fp) + * copied length back to the caller. + * For IPV6 addresses, or for a dual IPV4/IPV6 stack, + * the max size copied is sizeof(struct sockaddr_in6) + * + */ + if (lret != -1) + 8026514: e0bffd17 ldw r2,-12(fp) + 8026518: 10bfffe0 cmpeqi r2,r2,-1 + 802651c: 10000f1e bne r2,zero,802655c + { +#ifndef IP_V6 + if (lnamelen > sizeof(struct sockaddr_in)) + 8026520: e0bff817 ldw r2,-32(fp) + 8026524: 10800470 cmpltui r2,r2,17 + 8026528: 1000021e bne r2,zero,8026534 + lnamelen = sizeof(struct sockaddr_in); + 802652c: 00800404 movi r2,16 + 8026530: e0bff815 stw r2,-32(fp) +#else + if (lnamelen > sizeof(struct sockaddr_in6)) + lnamelen = sizeof(struct sockaddr_in6); +#endif + MEMCPY(name, &lname, lnamelen); + 8026534: e0bff817 ldw r2,-32(fp) + 8026538: 1007883a mov r3,r2 + 802653c: e0bff904 addi r2,fp,-28 + 8026540: 180d883a mov r6,r3 + 8026544: 100b883a mov r5,r2 + 8026548: e13ff617 ldw r4,-40(fp) + 802654c: 80086b80 call 80086b8 + *namelen = lnamelen; + 8026550: e0fff817 ldw r3,-32(fp) + 8026554: e0bff517 ldw r2,-44(fp) + 8026558: 10c00015 stw r3,0(r2) + } + + return lret; + 802655c: e0bffd17 ldw r2,-12(fp) +} + 8026560: e037883a mov sp,fp + 8026564: dfc00117 ldw ra,4(sp) + 8026568: df000017 ldw fp,0(sp) + 802656c: dec00204 addi sp,sp,8 + 8026570: f800283a ret + +08026574 : + * RETURNS: minimum length of the named socket option, in bytes + */ +int +bsd_i_sockoptlen(int level, + int name) +{ + 8026574: defffd04 addi sp,sp,-12 + 8026578: df000215 stw fp,8(sp) + 802657c: df000204 addi fp,sp,8 + 8026580: e13fff15 stw r4,-4(fp) + 8026584: e17ffe15 stw r5,-8(fp) + USE_ARG(level); + + switch (name) + 8026588: e0bffe17 ldw r2,-8(fp) + 802658c: 10802020 cmpeqi r2,r2,128 + 8026590: 1000491e bne r2,zero,80266b8 + 8026594: e0bffe17 ldw r2,-8(fp) + 8026598: 10802048 cmpgei r2,r2,129 + 802659c: 1000251e bne r2,zero,8026634 + 80265a0: e0bffe17 ldw r2,-8(fp) + 80265a4: 10800308 cmpgei r2,r2,12 + 80265a8: 1000141e bne r2,zero,80265fc + 80265ac: e0bffe17 ldw r2,-8(fp) + 80265b0: 10800288 cmpgei r2,r2,10 + 80265b4: 1000481e bne r2,zero,80266d8 + 80265b8: e0bffe17 ldw r2,-8(fp) + 80265bc: 10800120 cmpeqi r2,r2,4 + 80265c0: 1000411e bne r2,zero,80266c8 + 80265c4: e0bffe17 ldw r2,-8(fp) + 80265c8: 10800148 cmpgei r2,r2,5 + 80265cc: 1000041e bne r2,zero,80265e0 + 80265d0: e0bffe17 ldw r2,-8(fp) + 80265d4: 108000e0 cmpeqi r2,r2,3 + 80265d8: 1000431e bne r2,zero,80266e8 + 80265dc: 00004406 br 80266f0 + 80265e0: e0bffe17 ldw r2,-8(fp) + 80265e4: 10800220 cmpeqi r2,r2,8 + 80265e8: 1000371e bne r2,zero,80266c8 + 80265ec: e0bffe17 ldw r2,-8(fp) + 80265f0: 10800260 cmpeqi r2,r2,9 + 80265f4: 1000361e bne r2,zero,80266d0 + 80265f8: 00003d06 br 80266f0 + 80265fc: e0bffe17 ldw r2,-8(fp) + 8026600: 10800420 cmpeqi r2,r2,16 + 8026604: 1000301e bne r2,zero,80266c8 + 8026608: e0bffe17 ldw r2,-8(fp) + 802660c: 10800448 cmpgei r2,r2,17 + 8026610: 1000041e bne r2,zero,8026624 + 8026614: e0bffe17 ldw r2,-8(fp) + 8026618: 10800388 cmpgei r2,r2,14 + 802661c: 1000341e bne r2,zero,80266f0 + 8026620: 00002f06 br 80266e0 + 8026624: e0bffe17 ldw r2,-8(fp) + 8026628: 10800820 cmpeqi r2,r2,32 + 802662c: 1000261e bne r2,zero,80266c8 + 8026630: 00002f06 br 80266f0 + 8026634: e0bffe17 ldw r2,-8(fp) + 8026638: 108401c8 cmpgei r2,r2,4103 + 802663c: 10000e1e bne r2,zero,8026678 + 8026640: e0bffe17 ldw r2,-8(fp) + 8026644: 10840148 cmpgei r2,r2,4101 + 8026648: 10001d1e bne r2,zero,80266c0 + 802664c: e0bffe17 ldw r2,-8(fp) + 8026650: 10804020 cmpeqi r2,r2,256 + 8026654: 10001c1e bne r2,zero,80266c8 + 8026658: e0bffe17 ldw r2,-8(fp) + 802665c: 10804010 cmplti r2,r2,256 + 8026660: 1000231e bne r2,zero,80266f0 + 8026664: e0bffe17 ldw r2,-8(fp) + 8026668: 10bbffc4 addi r2,r2,-4097 + 802666c: 108000a8 cmpgeui r2,r2,2 + 8026670: 10001f1e bne r2,zero,80266f0 + 8026674: 00001406 br 80266c8 + 8026678: e0bffe17 ldw r2,-8(fp) + 802667c: 10840588 cmpgei r2,r2,4118 + 8026680: 1000071e bne r2,zero,80266a0 + 8026684: e0bffe17 ldw r2,-8(fp) + 8026688: 10840508 cmpgei r2,r2,4116 + 802668c: 1000081e bne r2,zero,80266b0 + 8026690: e0bffe17 ldw r2,-8(fp) + 8026694: 10840248 cmpgei r2,r2,4105 + 8026698: 1000151e bne r2,zero,80266f0 + 802669c: 00000a06 br 80266c8 + 80266a0: e0bffe17 ldw r2,-8(fp) + 80266a4: 108405a0 cmpeqi r2,r2,4118 + 80266a8: 1000071e bne r2,zero,80266c8 + 80266ac: 00001006 br 80266f0 + { + case SO_BIO: + case SO_NBIO: + /* these don't use an option value */ + return 0; + 80266b0: 0005883a mov r2,zero + 80266b4: 00000f06 br 80266f4 + case SO_LINGER: + /* this option is a struct linger */ + return sizeof(struct linger); + 80266b8: 00800204 movi r2,8 + 80266bc: 00000d06 br 80266f4 + case SO_RCVTIMEO: + case SO_SNDTIMEO: + /* these options are type short */ + return sizeof(short); + 80266c0: 00800084 movi r2,2 + 80266c4: 00000b06 br 80266f4 + case SO_RCVBUF: + case SO_NONBLOCK: + case SO_ERROR: + case SO_TYPE: + /* these options are type int */ + return sizeof(int); + 80266c8: 00800104 movi r2,4 + 80266cc: 00000906 br 80266f4 + return sizeof(int (*)()); +#endif /* TCP_ZEROCOPY */ +#ifdef IP_MULTICAST + case IP_MULTICAST_IF: + /* this option is type ip_addr */ + return sizeof(ip_addr); + 80266d0: 00800104 movi r2,4 + 80266d4: 00000706 br 80266f4 + case IP_MULTICAST_TTL: + case IP_MULTICAST_LOOP: + /* these options are type u_char */ + return sizeof(u_char); + 80266d8: 00800044 movi r2,1 + 80266dc: 00000506 br 80266f4 + case IP_ADD_MEMBERSHIP: + case IP_DROP_MEMBERSHIP: + /* these options are struct ip_mreq */ + return sizeof(struct ip_mreq); + 80266e0: 00800204 movi r2,8 + 80266e4: 00000306 br 80266f4 + * IP_TTL_OPT == SOREUSEADDR. This causes a build erro + * due to duplicate cases. Removing this one. They both + * return the same value (sizeof(int)). + */ + // case IP_TTL_OPT: + return sizeof(int); + 80266e8: 00800104 movi r2,4 + 80266ec: 00000106 br 80266f4 + default: + /* we don't know what type these options are */ + return 0; + 80266f0: 0005883a mov r2,zero + } + +} + 80266f4: e037883a mov sp,fp + 80266f8: df000017 ldw fp,0(sp) + 80266fc: dec00104 addi sp,sp,4 + 8026700: f800283a ret + +08026704 : +int +bsd_getsockopt(BSD_SOCKET s, + int level, + int name, + void * opt, int * optlen) +{ + 8026704: defff504 addi sp,sp,-44 + 8026708: dfc00a15 stw ra,40(sp) + 802670c: df000915 stw fp,36(sp) + 8026710: df000904 addi fp,sp,36 + 8026714: e13ffb15 stw r4,-20(fp) + 8026718: e17ffa15 stw r5,-24(fp) + 802671c: e1bff915 stw r6,-28(fp) + 8026720: e1fff815 stw r7,-32(fp) + struct socket * so; + int loptlen; + int e; + + so = LONG2SO(s); + 8026724: e0bffb17 ldw r2,-20(fp) + 8026728: 10bffc04 addi r2,r2,-16 + 802672c: 100490ba slli r2,r2,2 + 8026730: e0bffe15 stw r2,-8(fp) + SOC_CHECK(so); + 8026734: 008201b4 movhi r2,2054 + 8026738: 10b87104 addi r2,r2,-7740 + 802673c: e0bfff15 stw r2,-4(fp) + 8026740: 00000606 br 802675c + 8026744: e0ffff17 ldw r3,-4(fp) + 8026748: e0bffe17 ldw r2,-8(fp) + 802674c: 18800626 beq r3,r2,8026768 + 8026750: e0bfff17 ldw r2,-4(fp) + 8026754: 10800017 ldw r2,0(r2) + 8026758: e0bfff15 stw r2,-4(fp) + 802675c: e0bfff17 ldw r2,-4(fp) + 8026760: 103ff81e bne r2,zero,8026744 + 8026764: 00000106 br 802676c + 8026768: 0001883a nop + 802676c: e0ffff17 ldw r3,-4(fp) + 8026770: e0bffe17 ldw r2,-8(fp) + 8026774: 18800326 beq r3,r2,8026784 + 8026778: 8028cd40 call 8028cd4 + 802677c: 00bfffc4 movi r2,-1 + 8026780: 00001d06 br 80267f8 + + /* make sure supplied option value is big enough for the + * named option, else fail w/error EFAULT + */ + loptlen = bsd_i_sockoptlen(level, name); + 8026784: e17ff917 ldw r5,-28(fp) + 8026788: e13ffa17 ldw r4,-24(fp) + 802678c: 80265740 call 8026574 + 8026790: e0bffd15 stw r2,-12(fp) + if ((optlen == NULL) || (*optlen < loptlen)) + 8026794: e0800217 ldw r2,8(fp) + 8026798: 10000426 beq r2,zero,80267ac + 802679c: e0800217 ldw r2,8(fp) + 80267a0: 10c00017 ldw r3,0(r2) + 80267a4: e0bffd17 ldw r2,-12(fp) + 80267a8: 1880050e bge r3,r2,80267c0 + { + so->so_error = EFAULT; + 80267ac: e0bffe17 ldw r2,-8(fp) + 80267b0: 00c00384 movi r3,14 + 80267b4: 10c00615 stw r3,24(r2) + return -1; + 80267b8: 00bfffc4 movi r2,-1 + 80267bc: 00000e06 br 80267f8 + } + + e = t_getsockopt(s, level, name, opt, loptlen); + 80267c0: e0bffd17 ldw r2,-12(fp) + 80267c4: d8800015 stw r2,0(sp) + 80267c8: e1fff817 ldw r7,-32(fp) + 80267cc: e1bff917 ldw r6,-28(fp) + 80267d0: e17ffa17 ldw r5,-24(fp) + 80267d4: e13ffb17 ldw r4,-20(fp) + 80267d8: 802c60c0 call 802c60c + 80267dc: e0bffc15 stw r2,-16(fp) + + /* if it worked, copy the option length back for the caller's use */ + if (e == 0) + 80267e0: e0bffc17 ldw r2,-16(fp) + 80267e4: 1000031e bne r2,zero,80267f4 + { + *optlen = loptlen; + 80267e8: e0800217 ldw r2,8(fp) + 80267ec: e0fffd17 ldw r3,-12(fp) + 80267f0: 10c00015 stw r3,0(r2) + } + + return e; + 80267f4: e0bffc17 ldw r2,-16(fp) + +} + 80267f8: e037883a mov sp,fp + 80267fc: dfc00117 ldw ra,4(sp) + 8026800: df000017 ldw fp,0(sp) + 8026804: dec00204 addi sp,sp,8 + 8026808: f800283a ret + +0802680c : + * available via bsd_errno(s). + */ +int +bsd_ioctl(BSD_SOCKET s, + unsigned long request, ...) +{ + 802680c: defff504 addi sp,sp,-44 + 8026810: dfc00815 stw ra,32(sp) + 8026814: df000715 stw fp,28(sp) + 8026818: df000704 addi fp,sp,28 + 802681c: e13ffb15 stw r4,-20(fp) + 8026820: e17ffa15 stw r5,-24(fp) + 8026824: e1800215 stw r6,8(fp) + 8026828: e1c00315 stw r7,12(fp) + struct socket * so; + va_list argptr; + int iarg; + + so = LONG2SO(s); + 802682c: e0bffb17 ldw r2,-20(fp) + 8026830: 10bffc04 addi r2,r2,-16 + 8026834: 100490ba slli r2,r2,2 + 8026838: e0bffe15 stw r2,-8(fp) + SOC_CHECK(so); + 802683c: 008201b4 movhi r2,2054 + 8026840: 10b87104 addi r2,r2,-7740 + 8026844: e0bfff15 stw r2,-4(fp) + 8026848: 00000606 br 8026864 + 802684c: e0ffff17 ldw r3,-4(fp) + 8026850: e0bffe17 ldw r2,-8(fp) + 8026854: 18800626 beq r3,r2,8026870 + 8026858: e0bfff17 ldw r2,-4(fp) + 802685c: 10800017 ldw r2,0(r2) + 8026860: e0bfff15 stw r2,-4(fp) + 8026864: e0bfff17 ldw r2,-4(fp) + 8026868: 103ff81e bne r2,zero,802684c + 802686c: 00000106 br 8026874 + 8026870: 0001883a nop + 8026874: e0ffff17 ldw r3,-4(fp) + 8026878: e0bffe17 ldw r2,-8(fp) + 802687c: 18800326 beq r3,r2,802688c + 8026880: 8028cd40 call 8028cd4 + 8026884: 00bfffc4 movi r2,-1 + 8026888: 00001706 br 80268e8 + + va_start(argptr, request); + 802688c: e0800204 addi r2,fp,8 + 8026890: e0bffd15 stw r2,-12(fp) + + switch (request) + 8026894: e0bffa17 ldw r2,-24(fp) + 8026898: 10840598 cmpnei r2,r2,4118 + 802689c: 10000e1e bne r2,zero,80268d8 + { + case FIONBIO: + iarg = va_arg(argptr, int); + 80268a0: e0bffd17 ldw r2,-12(fp) + 80268a4: 10c00104 addi r3,r2,4 + 80268a8: e0fffd15 stw r3,-12(fp) + 80268ac: 10800017 ldw r2,0(r2) + 80268b0: e0bffc15 stw r2,-16(fp) + va_end(argptr); + return t_setsockopt(s, SOL_SOCKET, SO_NONBLOCK, &iarg, sizeof(iarg)); + 80268b4: e0fffc04 addi r3,fp,-16 + 80268b8: 00800104 movi r2,4 + 80268bc: d8800015 stw r2,0(sp) + 80268c0: 180f883a mov r7,r3 + 80268c4: 01840584 movi r6,4118 + 80268c8: 017fffc4 movi r5,-1 + 80268cc: e13ffb17 ldw r4,-20(fp) + 80268d0: 802c44c0 call 802c44c + 80268d4: 00000406 br 80268e8 + default: + so->so_error = EINVAL; + 80268d8: e0bffe17 ldw r2,-8(fp) + 80268dc: 00c00584 movi r3,22 + 80268e0: 10c00615 stw r3,24(r2) + return -1; + 80268e4: 00bfffc4 movi r2,-1 + } +} + 80268e8: e037883a mov sp,fp + 80268ec: dfc00117 ldw ra,4(sp) + 80268f0: df000017 ldw fp,0(sp) + 80268f4: dec00404 addi sp,sp,16 + 80268f8: f800283a ret + +080268fc : + * RETURNS: pointer to null-terminated string containing dotted-decimal + * printable representation of in + */ +char * +bsd_inet_ntoa(struct in_addr in) +{ + 80268fc: defffd04 addi sp,sp,-12 + 8026900: dfc00215 stw ra,8(sp) + 8026904: df000115 stw fp,4(sp) + 8026908: df000104 addi fp,sp,4 + 802690c: e13fff15 stw r4,-4(fp) + return print_ipad(in.s_addr); + 8026910: e0bfff17 ldw r2,-4(fp) + 8026914: 1009883a mov r4,r2 + 8026918: 8026fbc0 call 8026fbc +} + 802691c: e037883a mov sp,fp + 8026920: dfc00117 ldw ra,4(sp) + 8026924: df000017 ldw fp,0(sp) + 8026928: dec00204 addi sp,sp,8 + 802692c: f800283a ret + +08026930 : +bsd_recvfrom(BSD_SOCKET s, + void * buf, + BSD_SIZE_T len, + int flags, + struct sockaddr * from, int * fromlen) +{ + 8026930: defff004 addi sp,sp,-64 + 8026934: dfc00f15 stw ra,60(sp) + 8026938: df000e15 stw fp,56(sp) + 802693c: df000e04 addi fp,sp,56 + 8026940: e13ff715 stw r4,-36(fp) + 8026944: e17ff615 stw r5,-40(fp) + 8026948: e1bff515 stw r6,-44(fp) + 802694c: e1fff415 stw r7,-48(fp) + struct socket * so; + struct sockaddr lfrom; + int lfromlen = 0; + 8026950: e03ff815 stw zero,-32(fp) + int lret; + + so = LONG2SO(s); + 8026954: e0bff717 ldw r2,-36(fp) + 8026958: 10bffc04 addi r2,r2,-16 + 802695c: 100490ba slli r2,r2,2 + 8026960: e0bffe15 stw r2,-8(fp) + SOC_CHECK(so); + 8026964: 008201b4 movhi r2,2054 + 8026968: 10b87104 addi r2,r2,-7740 + 802696c: e0bfff15 stw r2,-4(fp) + 8026970: 00000606 br 802698c + 8026974: e0ffff17 ldw r3,-4(fp) + 8026978: e0bffe17 ldw r2,-8(fp) + 802697c: 18800626 beq r3,r2,8026998 + 8026980: e0bfff17 ldw r2,-4(fp) + 8026984: 10800017 ldw r2,0(r2) + 8026988: e0bfff15 stw r2,-4(fp) + 802698c: e0bfff17 ldw r2,-4(fp) + 8026990: 103ff81e bne r2,zero,8026974 + 8026994: 00000106 br 802699c + 8026998: 0001883a nop + 802699c: e0ffff17 ldw r3,-4(fp) + 80269a0: e0bffe17 ldw r2,-8(fp) + 80269a4: 18800326 beq r3,r2,80269b4 + 80269a8: 8028cd40 call 8028cd4 + 80269ac: 00bfffc4 movi r2,-1 + 80269b0: 00002b06 br 8026a60 + + /* if we were given a buffer for the peer's address, also get the + * buffer's length + */ + if (from != NULL) + 80269b4: e0800217 ldw r2,8(fp) + 80269b8: 10000a26 beq r2,zero,80269e4 + { + if (fromlen == NULL) + 80269bc: e0800317 ldw r2,12(fp) + 80269c0: 1000051e bne r2,zero,80269d8 + { + so->so_error = EFAULT; + 80269c4: e0bffe17 ldw r2,-8(fp) + 80269c8: 00c00384 movi r3,14 + 80269cc: 10c00615 stw r3,24(r2) + return -1; + 80269d0: 00bfffc4 movi r2,-1 + 80269d4: 00002206 br 8026a60 + } + lfromlen = *fromlen; + 80269d8: e0800317 ldw r2,12(fp) + 80269dc: 10800017 ldw r2,0(r2) + 80269e0: e0bff815 stw r2,-32(fp) + } + + lret = t_recvfrom(s, (char *)buf, len, flags, &lfrom, &lfromlen ); + 80269e4: e0bff804 addi r2,fp,-32 + 80269e8: d8800115 stw r2,4(sp) + 80269ec: e0bff904 addi r2,fp,-28 + 80269f0: d8800015 stw r2,0(sp) + 80269f4: e1fff417 ldw r7,-48(fp) + 80269f8: e1bff517 ldw r6,-44(fp) + 80269fc: e17ff617 ldw r5,-40(fp) + 8026a00: e13ff717 ldw r4,-36(fp) + 8026a04: 802c8700 call 802c870 + 8026a08: e0bffd15 stw r2,-12(fp) + * sockaddr_in), which is all that t_recvfrom() can return as a peer + * name. + * For IPV6 addresses or dual IPV4/IPV6 stack, the max size copied + * is sizeof(struct sockaddr_in6) + */ + if ((lret != -1) && (from != NULL)) + 8026a0c: e0bffd17 ldw r2,-12(fp) + 8026a10: 10bfffe0 cmpeqi r2,r2,-1 + 8026a14: 1000111e bne r2,zero,8026a5c + 8026a18: e0800217 ldw r2,8(fp) + 8026a1c: 10000f26 beq r2,zero,8026a5c + { +#ifndef IP_V6 + if (lfromlen > sizeof(struct sockaddr_in)) + 8026a20: e0bff817 ldw r2,-32(fp) + 8026a24: 10800470 cmpltui r2,r2,17 + 8026a28: 1000021e bne r2,zero,8026a34 + lfromlen = sizeof(struct sockaddr_in); + 8026a2c: 00800404 movi r2,16 + 8026a30: e0bff815 stw r2,-32(fp) +#else + if (lfromlen > sizeof(struct sockaddr_in6)) + lfromlen = sizeof(struct sockaddr_in6); + +#endif + MEMCPY(from, &lfrom, lfromlen); + 8026a34: e0bff817 ldw r2,-32(fp) + 8026a38: 1007883a mov r3,r2 + 8026a3c: e0bff904 addi r2,fp,-28 + 8026a40: 180d883a mov r6,r3 + 8026a44: 100b883a mov r5,r2 + 8026a48: e1000217 ldw r4,8(fp) + 8026a4c: 80086b80 call 80086b8 + *fromlen = lfromlen; + 8026a50: e0fff817 ldw r3,-32(fp) + 8026a54: e0800317 ldw r2,12(fp) + 8026a58: 10c00015 stw r3,0(r2) + } + + return lret; + 8026a5c: e0bffd17 ldw r2,-12(fp) +} + 8026a60: e037883a mov sp,fp + 8026a64: dfc00117 ldw ra,4(sp) + 8026a68: df000017 ldw fp,0(sp) + 8026a6c: dec00204 addi sp,sp,8 + 8026a70: f800283a ret + +08026a74 : +bsd_select(int nfds, + fd_set * readfds, + fd_set * writefds, + fd_set * exceptfds, + BSD_TIMEVAL_T * timeout) +{ + 8026a74: defff804 addi sp,sp,-32 + 8026a78: dfc00715 stw ra,28(sp) + 8026a7c: df000615 stw fp,24(sp) + 8026a80: df000604 addi fp,sp,24 + 8026a84: e13ffd15 stw r4,-12(fp) + 8026a88: e17ffc15 stw r5,-16(fp) + 8026a8c: e1bffb15 stw r6,-20(fp) + 8026a90: e1fffa15 stw r7,-24(fp) + long ltv; /* timeout expressed in ticks */ + long tps; /* local copy of TPS */ + + USE_ARG(nfds); + + if (timeout != NULL) + 8026a94: e0800217 ldw r2,8(fp) + 8026a98: 10004c26 beq r2,zero,8026bcc + * million (i.e. any number of microseconds up to one second). + * So we scale tv_usec from microseconds to something reasonable + * based on TPS, multiply it by TPS, then scale it the rest of + * the way to ticks-per-second. + */ + tps = TPS; + 8026a9c: 00801904 movi r2,100 + 8026aa0: e0bffe15 stw r2,-8(fp) + if (tps >= 1000) + 8026aa4: e0bffe17 ldw r2,-8(fp) + 8026aa8: 1080fa10 cmplti r2,r2,1000 + 8026aac: 10000e1e bne r2,zero,8026ae8 + { + ltv = (((timeout->tv_usec + 50) / 100) * tps) / 10000; + 8026ab0: e0800217 ldw r2,8(fp) + 8026ab4: 10800217 ldw r2,8(r2) + 8026ab8: 10800c84 addi r2,r2,50 + 8026abc: 01401904 movi r5,100 + 8026ac0: 1009883a mov r4,r2 + 8026ac4: 800cf000 call 800cf00 <__divsi3> + 8026ac8: 1007883a mov r3,r2 + 8026acc: e0bffe17 ldw r2,-8(fp) + 8026ad0: 1885383a mul r2,r3,r2 + 8026ad4: 0149c404 movi r5,10000 + 8026ad8: 1009883a mov r4,r2 + 8026adc: 800cf000 call 800cf00 <__divsi3> + 8026ae0: e0bfff15 stw r2,-4(fp) + 8026ae4: 00003106 br 8026bac + } + else if (tps >= 100) + 8026ae8: e0bffe17 ldw r2,-8(fp) + 8026aec: 10801910 cmplti r2,r2,100 + 8026af0: 10000e1e bne r2,zero,8026b2c + { + ltv = (((timeout->tv_usec + 500) / 1000) * tps) / 1000; + 8026af4: e0800217 ldw r2,8(fp) + 8026af8: 10800217 ldw r2,8(r2) + 8026afc: 10807d04 addi r2,r2,500 + 8026b00: 0140fa04 movi r5,1000 + 8026b04: 1009883a mov r4,r2 + 8026b08: 800cf000 call 800cf00 <__divsi3> + 8026b0c: 1007883a mov r3,r2 + 8026b10: e0bffe17 ldw r2,-8(fp) + 8026b14: 1885383a mul r2,r3,r2 + 8026b18: 0140fa04 movi r5,1000 + 8026b1c: 1009883a mov r4,r2 + 8026b20: 800cf000 call 800cf00 <__divsi3> + 8026b24: e0bfff15 stw r2,-4(fp) + 8026b28: 00002006 br 8026bac + } + else if (tps >= 10) + 8026b2c: e0bffe17 ldw r2,-8(fp) + 8026b30: 10800290 cmplti r2,r2,10 + 8026b34: 10000e1e bne r2,zero,8026b70 + { + ltv = (((timeout->tv_usec + 5000) / 10000) * tps) / 100; + 8026b38: e0800217 ldw r2,8(fp) + 8026b3c: 10800217 ldw r2,8(r2) + 8026b40: 1084e204 addi r2,r2,5000 + 8026b44: 0149c404 movi r5,10000 + 8026b48: 1009883a mov r4,r2 + 8026b4c: 800cf000 call 800cf00 <__divsi3> + 8026b50: 1007883a mov r3,r2 + 8026b54: e0bffe17 ldw r2,-8(fp) + 8026b58: 1885383a mul r2,r3,r2 + 8026b5c: 01401904 movi r5,100 + 8026b60: 1009883a mov r4,r2 + 8026b64: 800cf000 call 800cf00 <__divsi3> + 8026b68: e0bfff15 stw r2,-4(fp) + 8026b6c: 00000f06 br 8026bac + } + else + { + ltv = (((timeout->tv_usec + 50000) / 100000) * tps) / 10; + 8026b70: e0800217 ldw r2,8(fp) + 8026b74: 10c00217 ldw r3,8(r2) + 8026b78: 00b0d414 movui r2,50000 + 8026b7c: 1885883a add r2,r3,r2 + 8026b80: 014000b4 movhi r5,2 + 8026b84: 2961a804 addi r5,r5,-31072 + 8026b88: 1009883a mov r4,r2 + 8026b8c: 800cf000 call 800cf00 <__divsi3> + 8026b90: 1007883a mov r3,r2 + 8026b94: e0bffe17 ldw r2,-8(fp) + 8026b98: 1885383a mul r2,r3,r2 + 8026b9c: 01400284 movi r5,10 + 8026ba0: 1009883a mov r4,r2 + 8026ba4: 800cf000 call 800cf00 <__divsi3> + 8026ba8: e0bfff15 stw r2,-4(fp) + } + ltv += (timeout->tv_sec * TPS); + 8026bac: e1000217 ldw r4,8(fp) + 8026bb0: 20800017 ldw r2,0(r4) + 8026bb4: 20c00117 ldw r3,4(r4) + 8026bb8: 10c01924 muli r3,r2,100 + 8026bbc: e0bfff17 ldw r2,-4(fp) + 8026bc0: 1885883a add r2,r3,r2 + 8026bc4: e0bfff15 stw r2,-4(fp) + 8026bc8: 00000206 br 8026bd4 + } + else { + /* + * NULL timeout: wait indefinitely in t_select() + */ + ltv = -1; + 8026bcc: 00bfffc4 movi r2,-1 + 8026bd0: e0bfff15 stw r2,-4(fp) + } + + return (t_select(readfds, writefds, exceptfds, ltv)); + 8026bd4: e1ffff17 ldw r7,-4(fp) + 8026bd8: e1bffa17 ldw r6,-24(fp) + 8026bdc: e17ffb17 ldw r5,-20(fp) + 8026be0: e13ffc17 ldw r4,-16(fp) + 8026be4: 80303f80 call 80303f8 +} + 8026be8: e037883a mov sp,fp + 8026bec: dfc00117 ldw ra,4(sp) + 8026bf0: df000017 ldw fp,0(sp) + 8026bf4: dec00204 addi sp,sp,8 + 8026bf8: f800283a ret + +08026bfc : +int +bsd_setsockopt(BSD_SOCKET s, + int level, + int name, + void * opt, int optlen) +{ + 8026bfc: defff704 addi sp,sp,-36 + 8026c00: dfc00815 stw ra,32(sp) + 8026c04: df000715 stw fp,28(sp) + 8026c08: df000704 addi fp,sp,28 + 8026c0c: e13ffd15 stw r4,-12(fp) + 8026c10: e17ffc15 stw r5,-16(fp) + 8026c14: e1bffb15 stw r6,-20(fp) + 8026c18: e1fffa15 stw r7,-24(fp) + struct socket * so; + + so = LONG2SO(s); + 8026c1c: e0bffd17 ldw r2,-12(fp) + 8026c20: 10bffc04 addi r2,r2,-16 + 8026c24: 100490ba slli r2,r2,2 + 8026c28: e0bffe15 stw r2,-8(fp) + SOC_CHECK(so); + 8026c2c: 008201b4 movhi r2,2054 + 8026c30: 10b87104 addi r2,r2,-7740 + 8026c34: e0bfff15 stw r2,-4(fp) + 8026c38: 00000606 br 8026c54 + 8026c3c: e0ffff17 ldw r3,-4(fp) + 8026c40: e0bffe17 ldw r2,-8(fp) + 8026c44: 18800626 beq r3,r2,8026c60 + 8026c48: e0bfff17 ldw r2,-4(fp) + 8026c4c: 10800017 ldw r2,0(r2) + 8026c50: e0bfff15 stw r2,-4(fp) + 8026c54: e0bfff17 ldw r2,-4(fp) + 8026c58: 103ff81e bne r2,zero,8026c3c + 8026c5c: 00000106 br 8026c64 + 8026c60: 0001883a nop + 8026c64: e0ffff17 ldw r3,-4(fp) + 8026c68: e0bffe17 ldw r2,-8(fp) + 8026c6c: 18800326 beq r3,r2,8026c7c + 8026c70: 8028cd40 call 8028cd4 + 8026c74: 00bfffc4 movi r2,-1 + 8026c78: 00001206 br 8026cc4 + + /* make sure supplied option value is big enough for the + * named option, else fail w/error EFAULT + */ + if (optlen < bsd_i_sockoptlen(level, name)) + 8026c7c: e17ffb17 ldw r5,-20(fp) + 8026c80: e13ffc17 ldw r4,-16(fp) + 8026c84: 80265740 call 8026574 + 8026c88: 1007883a mov r3,r2 + 8026c8c: e0800217 ldw r2,8(fp) + 8026c90: 10c0050e bge r2,r3,8026ca8 + { + so->so_error = EFAULT; + 8026c94: e0bffe17 ldw r2,-8(fp) + 8026c98: 00c00384 movi r3,14 + 8026c9c: 10c00615 stw r3,24(r2) + return -1; + 8026ca0: 00bfffc4 movi r2,-1 + 8026ca4: 00000706 br 8026cc4 + } + + return t_setsockopt(s, level, name, opt, optlen); + 8026ca8: e0800217 ldw r2,8(fp) + 8026cac: d8800015 stw r2,0(sp) + 8026cb0: e1fffa17 ldw r7,-24(fp) + 8026cb4: e1bffb17 ldw r6,-20(fp) + 8026cb8: e17ffc17 ldw r5,-16(fp) + 8026cbc: e13ffd17 ldw r4,-12(fp) + 8026cc0: 802c44c0 call 802c44c +} + 8026cc4: e037883a mov sp,fp + 8026cc8: dfc00117 ldw ra,4(sp) + 8026ccc: df000017 ldw fp,0(sp) + 8026cd0: dec00204 addi sp,sp,8 + 8026cd4: f800283a ret + +08026cd8 : + * be done in 16-bit chunks. + */ + +unsigned short +ccksum (void *ptr, unsigned words) +{ + 8026cd8: defffa04 addi sp,sp,-24 + 8026cdc: df000515 stw fp,20(sp) + 8026ce0: df000504 addi fp,sp,20 + 8026ce4: e13ffc15 stw r4,-16(fp) + 8026ce8: e17ffb15 stw r5,-20(fp) + unsigned short *addr = (unsigned short *)ptr; + 8026cec: e0bffc17 ldw r2,-16(fp) + 8026cf0: e0bfff15 stw r2,-4(fp) + unsigned long sum = 0; + 8026cf4: e03ffe15 stw zero,-8(fp) + int count = (int)words; + 8026cf8: e0bffb17 ldw r2,-20(fp) + 8026cfc: e0bffd15 stw r2,-12(fp) + + while (--count >= 0) + 8026d00: 00000806 br 8026d24 + { + /* This is the inner loop */ + sum += *addr++; + 8026d04: e0bfff17 ldw r2,-4(fp) + 8026d08: 10c00084 addi r3,r2,2 + 8026d0c: e0ffff15 stw r3,-4(fp) + 8026d10: 1080000b ldhu r2,0(r2) + 8026d14: 10bfffcc andi r2,r2,65535 + 8026d18: e0fffe17 ldw r3,-8(fp) + 8026d1c: 1885883a add r2,r3,r2 + 8026d20: e0bffe15 stw r2,-8(fp) + while (--count >= 0) + 8026d24: e0bffd17 ldw r2,-12(fp) + 8026d28: 10bfffc4 addi r2,r2,-1 + 8026d2c: e0bffd15 stw r2,-12(fp) + 8026d30: e0bffd17 ldw r2,-12(fp) + 8026d34: 103ff30e bge r2,zero,8026d04 + } + + /* Fold 32-bit sum to 16 bits */ + sum = (sum & 0xffff) + (sum >> 16); + 8026d38: e0bffe17 ldw r2,-8(fp) + 8026d3c: 10ffffcc andi r3,r2,65535 + 8026d40: e0bffe17 ldw r2,-8(fp) + 8026d44: 1004d43a srli r2,r2,16 + 8026d48: 1885883a add r2,r3,r2 + 8026d4c: e0bffe15 stw r2,-8(fp) + sum = (sum & 0xffff) + (sum >> 16); + 8026d50: e0bffe17 ldw r2,-8(fp) + 8026d54: 10ffffcc andi r3,r2,65535 + 8026d58: e0bffe17 ldw r2,-8(fp) + 8026d5c: 1004d43a srli r2,r2,16 + 8026d60: 1885883a add r2,r3,r2 + 8026d64: e0bffe15 stw r2,-8(fp) + + /* checksum = ~sum; *//* removed for MIT IP stack */ + return ((unsigned short)sum); + 8026d68: e0bffe17 ldw r2,-8(fp) +} + 8026d6c: e037883a mov sp,fp + 8026d70: df000017 ldw fp,0(sp) + 8026d74: dec00104 addi sp,sp,4 + 8026d78: f800283a ret + +08026d7c : + * 3 = user-supplied alternate implementation + */ + +unsigned short +cksum (void *ptr, unsigned count) +{ + 8026d7c: defffc04 addi sp,sp,-16 + 8026d80: dfc00315 stw ra,12(sp) + 8026d84: df000215 stw fp,8(sp) + 8026d88: df000204 addi fp,sp,8 + 8026d8c: e13fff15 stw r4,-4(fp) + 8026d90: e17ffe15 stw r5,-8(fp) + switch (cksum_select) + 8026d94: d0a01317 ldw r2,-32692(gp) + 8026d98: 108000a0 cmpeqi r2,r2,2 + 8026d9c: 1000041e bne r2,zero,8026db0 + { + case 1: + default: + return (ccksum(ptr, count)); + 8026da0: e17ffe17 ldw r5,-8(fp) + 8026da4: e13fff17 ldw r4,-4(fp) + 8026da8: 8026cd80 call 8026cd8 + 8026dac: 00000306 br 8026dbc + #ifndef C_CHECKSUM + case 2: + return (asm_cksum(ptr, count)); + 8026db0: e17ffe17 ldw r5,-8(fp) + 8026db4: e13fff17 ldw r4,-4(fp) + 8026db8: 8028b400 call 8028b40 +#else +#endif + return (alt_cksum(ptr, count)); +#endif + } +} + 8026dbc: e037883a mov sp,fp + 8026dc0: dfc00117 ldw ra,4(sp) + 8026dc4: df000017 ldw fp,0(sp) + 8026dc8: dec00204 addi sp,sp,8 + 8026dcc: f800283a ret + +08026dd0 : + * RETURNS: 0 + */ + +int +do_trap(void) +{ + 8026dd0: defffe04 addi sp,sp,-8 + 8026dd4: dfc00115 stw ra,4(sp) + 8026dd8: df000015 stw fp,0(sp) + 8026ddc: d839883a mov fp,sp + dtrap(); + 8026de0: 8028cd40 call 8028cd4 + return 0; + 8026de4: 0005883a mov r2,zero +} + 8026de8: e037883a mov sp,fp + 8026dec: dfc00117 ldw ra,4(sp) + 8026df0: df000017 ldw fp,0(sp) + 8026df4: dec00204 addi sp,sp,8 + 8026df8: f800283a ret + +08026dfc : + * RETURNS: pointer to next arg in string + */ + +char * +nextarg(char * argp) +{ + 8026dfc: defffe04 addi sp,sp,-8 + 8026e00: df000115 stw fp,4(sp) + 8026e04: df000104 addi fp,sp,4 + 8026e08: e13fff15 stw r4,-4(fp) + while (*argp > ' ')argp++; /* scan past current arg */ + 8026e0c: 00000306 br 8026e1c + 8026e10: e0bfff17 ldw r2,-4(fp) + 8026e14: 10800044 addi r2,r2,1 + 8026e18: e0bfff15 stw r2,-4(fp) + 8026e1c: e0bfff17 ldw r2,-4(fp) + 8026e20: 10800003 ldbu r2,0(r2) + 8026e24: 10803fcc andi r2,r2,255 + 8026e28: 1080201c xori r2,r2,128 + 8026e2c: 10bfe004 addi r2,r2,-128 + 8026e30: 10800848 cmpgei r2,r2,33 + 8026e34: 103ff61e bne r2,zero,8026e10 + while (*argp == ' ')argp++; /* scan past spaces */ + 8026e38: 00000306 br 8026e48 + 8026e3c: e0bfff17 ldw r2,-4(fp) + 8026e40: 10800044 addi r2,r2,1 + 8026e44: e0bfff15 stw r2,-4(fp) + 8026e48: e0bfff17 ldw r2,-4(fp) + 8026e4c: 10800003 ldbu r2,0(r2) + 8026e50: 10803fcc andi r2,r2,255 + 8026e54: 1080201c xori r2,r2,128 + 8026e58: 10bfe004 addi r2,r2,-128 + 8026e5c: 10800820 cmpeqi r2,r2,32 + 8026e60: 103ff61e bne r2,zero,8026e3c + return (argp); + 8026e64: e0bfff17 ldw r2,-4(fp) +} + 8026e68: e037883a mov sp,fp + 8026e6c: df000017 ldw fp,0(sp) + 8026e70: dec00104 addi sp,sp,4 + 8026e74: f800283a ret + +08026e78 : + +#define HEX_BYTES_PER_LINE 16 + +void +hexdump(void * pio, void * buffer, unsigned len) +{ + 8026e78: defff804 addi sp,sp,-32 + 8026e7c: dfc00715 stw ra,28(sp) + 8026e80: df000615 stw fp,24(sp) + 8026e84: df000604 addi fp,sp,24 + 8026e88: e13ffc15 stw r4,-16(fp) + 8026e8c: e17ffb15 stw r5,-20(fp) + 8026e90: e1bffa15 stw r6,-24(fp) + u_char * data = (u_char *)buffer; + 8026e94: e0bffb17 ldw r2,-20(fp) + 8026e98: e0bfff15 stw r2,-4(fp) + unsigned int count; + char c; + + while (len) + 8026e9c: 00003f06 br 8026f9c + { + /* display data in hex */ + for (count = 0; (count < HEX_BYTES_PER_LINE) && (count < len); ++count) + 8026ea0: e03ffe15 stw zero,-8(fp) + 8026ea4: 00000d06 br 8026edc + ns_printf(pio, "%02x ", *(data + count)); + 8026ea8: e0ffff17 ldw r3,-4(fp) + 8026eac: e0bffe17 ldw r2,-8(fp) + 8026eb0: 1885883a add r2,r3,r2 + 8026eb4: 10800003 ldbu r2,0(r2) + 8026eb8: 10803fcc andi r2,r2,255 + 8026ebc: 100d883a mov r6,r2 + 8026ec0: 01420174 movhi r5,2053 + 8026ec4: 29688104 addi r5,r5,-24060 + 8026ec8: e13ffc17 ldw r4,-16(fp) + 8026ecc: 80273900 call 8027390 + for (count = 0; (count < HEX_BYTES_PER_LINE) && (count < len); ++count) + 8026ed0: e0bffe17 ldw r2,-8(fp) + 8026ed4: 10800044 addi r2,r2,1 + 8026ed8: e0bffe15 stw r2,-8(fp) + 8026edc: e0bffe17 ldw r2,-8(fp) + 8026ee0: 10800428 cmpgeui r2,r2,16 + 8026ee4: 1000031e bne r2,zero,8026ef4 + 8026ee8: e0fffe17 ldw r3,-8(fp) + 8026eec: e0bffa17 ldw r2,-24(fp) + 8026ef0: 18bfed36 bltu r3,r2,8026ea8 + /* display data in ascii */ + for (count = 0; (count < HEX_BYTES_PER_LINE) && (count < len); ++count) + 8026ef4: e03ffe15 stw zero,-8(fp) + 8026ef8: 00001606 br 8026f54 + { + c = *(data + count); + 8026efc: e0ffff17 ldw r3,-4(fp) + 8026f00: e0bffe17 ldw r2,-8(fp) + 8026f04: 1885883a add r2,r3,r2 + 8026f08: 10800003 ldbu r2,0(r2) + 8026f0c: e0bffdc5 stb r2,-9(fp) + ns_printf(pio, "%c", ((c >= 0x20) && (c < 0x7f)) ? c : '.'); + 8026f10: e0bffdc7 ldb r2,-9(fp) + 8026f14: 10800810 cmplti r2,r2,32 + 8026f18: 1000051e bne r2,zero,8026f30 + 8026f1c: e0bffdc7 ldb r2,-9(fp) + 8026f20: 10801fe0 cmpeqi r2,r2,127 + 8026f24: 1000021e bne r2,zero,8026f30 + 8026f28: e0bffdc7 ldb r2,-9(fp) + 8026f2c: 00000106 br 8026f34 + 8026f30: 00800b84 movi r2,46 + 8026f34: 100d883a mov r6,r2 + 8026f38: 01420174 movhi r5,2053 + 8026f3c: 29688304 addi r5,r5,-24052 + 8026f40: e13ffc17 ldw r4,-16(fp) + 8026f44: 80273900 call 8027390 + for (count = 0; (count < HEX_BYTES_PER_LINE) && (count < len); ++count) + 8026f48: e0bffe17 ldw r2,-8(fp) + 8026f4c: 10800044 addi r2,r2,1 + 8026f50: e0bffe15 stw r2,-8(fp) + 8026f54: e0bffe17 ldw r2,-8(fp) + 8026f58: 10800428 cmpgeui r2,r2,16 + 8026f5c: 1000031e bne r2,zero,8026f6c + 8026f60: e0fffe17 ldw r3,-8(fp) + 8026f64: e0bffa17 ldw r2,-24(fp) + 8026f68: 18bfe436 bltu r3,r2,8026efc + } + ns_printf(pio,"\n"); + 8026f6c: 01420174 movhi r5,2053 + 8026f70: 29688404 addi r5,r5,-24048 + 8026f74: e13ffc17 ldw r4,-16(fp) + 8026f78: 80273900 call 8027390 + len -= count; + 8026f7c: e0fffa17 ldw r3,-24(fp) + 8026f80: e0bffe17 ldw r2,-8(fp) + 8026f84: 1885c83a sub r2,r3,r2 + 8026f88: e0bffa15 stw r2,-24(fp) + data += count; + 8026f8c: e0ffff17 ldw r3,-4(fp) + 8026f90: e0bffe17 ldw r2,-8(fp) + 8026f94: 1885883a add r2,r3,r2 + 8026f98: e0bfff15 stw r2,-4(fp) + while (len) + 8026f9c: e0bffa17 ldw r2,-24(fp) + 8026fa0: 103fbf1e bne r2,zero,8026ea0 + } +} + 8026fa4: 0001883a nop + 8026fa8: e037883a mov sp,fp + 8026fac: dfc00117 ldw ra,4(sp) + 8026fb0: df000017 ldw fp,0(sp) + 8026fb4: dec00204 addi sp,sp,8 + 8026fb8: f800283a ret + +08026fbc : + +char ipreturn[18]; /* buffer for return */ + +char * +print_ipad(unsigned long ipaddr) +{ + 8026fbc: defffa04 addi sp,sp,-24 + 8026fc0: dfc00515 stw ra,20(sp) + 8026fc4: df000415 stw fp,16(sp) + 8026fc8: df000404 addi fp,sp,16 + 8026fcc: e13ffe15 stw r4,-8(fp) + struct l2b ip; + + ip.ip.iplong = ipaddr; + 8026fd0: e0bffe17 ldw r2,-8(fp) + 8026fd4: e0bfff15 stw r2,-4(fp) + sprintf(ipreturn, "%u.%u.%u.%u", + ip.ip.ipchar[0], + 8026fd8: e0bfff03 ldbu r2,-4(fp) + sprintf(ipreturn, "%u.%u.%u.%u", + 8026fdc: 11003fcc andi r4,r2,255 + ip.ip.ipchar[1], + 8026fe0: e0bfff43 ldbu r2,-3(fp) + sprintf(ipreturn, "%u.%u.%u.%u", + 8026fe4: 11403fcc andi r5,r2,255 + ip.ip.ipchar[2], + 8026fe8: e0bfff83 ldbu r2,-2(fp) + sprintf(ipreturn, "%u.%u.%u.%u", + 8026fec: 10803fcc andi r2,r2,255 + ip.ip.ipchar[3]); + 8026ff0: e0ffffc3 ldbu r3,-1(fp) + sprintf(ipreturn, "%u.%u.%u.%u", + 8026ff4: 18c03fcc andi r3,r3,255 + 8026ff8: d8c00115 stw r3,4(sp) + 8026ffc: d8800015 stw r2,0(sp) + 8027000: 280f883a mov r7,r5 + 8027004: 200d883a mov r6,r4 + 8027008: 01420174 movhi r5,2053 + 802700c: 29688504 addi r5,r5,-24044 + 8027010: 010201b4 movhi r4,2054 + 8027014: 21379184 addi r4,r4,-8634 + 8027018: 8042d980 call 8042d98 + + return ipreturn; + 802701c: 008201b4 movhi r2,2054 + 8027020: 10b79184 addi r2,r2,-8634 +} + 8027024: e037883a mov sp,fp + 8027028: dfc00117 ldw ra,4(sp) + 802702c: df000017 ldw fp,0(sp) + 8027030: dec00204 addi sp,sp,8 + 8027034: f800283a ret + +08027038 : + +static char tistring[24]; /* buffer for return */ + +char * +print_uptime(unsigned long timetick) +{ + 8027038: defff804 addi sp,sp,-32 + 802703c: dfc00715 stw ra,28(sp) + 8027040: df000615 stw fp,24(sp) + 8027044: df000604 addi fp,sp,24 + 8027048: e13ffc15 stw r4,-16(fp) + unsigned seconds, minutes, hours; + + timetick = timetick/100; /* turn timetick into seconds */ + 802704c: e0bffc17 ldw r2,-16(fp) + 8027050: 01401904 movi r5,100 + 8027054: 1009883a mov r4,r2 + 8027058: 800cff80 call 800cff8 <__udivsi3> + 802705c: e0bffc15 stw r2,-16(fp) + seconds = (unsigned)(timetick%60); + 8027060: e0bffc17 ldw r2,-16(fp) + 8027064: 01400f04 movi r5,60 + 8027068: 1009883a mov r4,r2 + 802706c: 800d05c0 call 800d05c <__umodsi3> + 8027070: e0bfff15 stw r2,-4(fp) + timetick = timetick/60; /* turn timetick into minutes */ + 8027074: e0bffc17 ldw r2,-16(fp) + 8027078: 01400f04 movi r5,60 + 802707c: 1009883a mov r4,r2 + 8027080: 800cff80 call 800cff8 <__udivsi3> + 8027084: e0bffc15 stw r2,-16(fp) + minutes = (unsigned)(timetick%60); + 8027088: e0bffc17 ldw r2,-16(fp) + 802708c: 01400f04 movi r5,60 + 8027090: 1009883a mov r4,r2 + 8027094: 800d05c0 call 800d05c <__umodsi3> + 8027098: e0bffe15 stw r2,-8(fp) + timetick = timetick/60; /* turn timetick into hours */ + 802709c: e0bffc17 ldw r2,-16(fp) + 80270a0: 01400f04 movi r5,60 + 80270a4: 1009883a mov r4,r2 + 80270a8: 800cff80 call 800cff8 <__udivsi3> + 80270ac: e0bffc15 stw r2,-16(fp) + hours = (unsigned)(timetick%24); + 80270b0: e0bffc17 ldw r2,-16(fp) + 80270b4: 01400604 movi r5,24 + 80270b8: 1009883a mov r4,r2 + 80270bc: 800d05c0 call 800d05c <__umodsi3> + 80270c0: e0bffd15 stw r2,-12(fp) + timetick = timetick/24; /* turn timetick into days */ + 80270c4: e0bffc17 ldw r2,-16(fp) + 80270c8: 01400604 movi r5,24 + 80270cc: 1009883a mov r4,r2 + 80270d0: 800cff80 call 800cff8 <__udivsi3> + 80270d4: e0bffc15 stw r2,-16(fp) + + if (timetick) /* Is there a whole number of days? */ + 80270d8: e0bffc17 ldw r2,-16(fp) + 80270dc: 10000c26 beq r2,zero,8027110 + sprintf(tistring, "%ld days, %dh:%dm:%ds", + 80270e0: e0bfff17 ldw r2,-4(fp) + 80270e4: d8800115 stw r2,4(sp) + 80270e8: e0bffe17 ldw r2,-8(fp) + 80270ec: d8800015 stw r2,0(sp) + 80270f0: e1fffd17 ldw r7,-12(fp) + 80270f4: e1bffc17 ldw r6,-16(fp) + 80270f8: 01420174 movhi r5,2053 + 80270fc: 29688804 addi r5,r5,-24032 + 8027100: 01020174 movhi r4,2053 + 8027104: 21337d04 addi r4,r4,-12812 + 8027108: 8042d980 call 8042d98 + 802710c: 00001306 br 802715c + timetick, hours, minutes, seconds); + else if (hours) + 8027110: e0bffd17 ldw r2,-12(fp) + 8027114: 10000a26 beq r2,zero,8027140 + sprintf(tistring, "%d hours, %dm:%ds", hours, minutes, seconds); + 8027118: e0bfff17 ldw r2,-4(fp) + 802711c: d8800015 stw r2,0(sp) + 8027120: e1fffe17 ldw r7,-8(fp) + 8027124: e1bffd17 ldw r6,-12(fp) + 8027128: 01420174 movhi r5,2053 + 802712c: 29688e04 addi r5,r5,-24008 + 8027130: 01020174 movhi r4,2053 + 8027134: 21337d04 addi r4,r4,-12812 + 8027138: 8042d980 call 8042d98 + 802713c: 00000706 br 802715c + else + sprintf(tistring, "%d minutes, %d sec.", minutes, seconds); + 8027140: e1ffff17 ldw r7,-4(fp) + 8027144: e1bffe17 ldw r6,-8(fp) + 8027148: 01420174 movhi r5,2053 + 802714c: 29689304 addi r5,r5,-23988 + 8027150: 01020174 movhi r4,2053 + 8027154: 21337d04 addi r4,r4,-12812 + 8027158: 8042d980 call 8042d98 + return tistring; + 802715c: 00820174 movhi r2,2053 + 8027160: 10b37d04 addi r2,r2,-12812 +} + 8027164: e037883a mov sp,fp + 8027168: dfc00117 ldw ra,4(sp) + 802716c: df000017 ldw fp,0(sp) + 8027170: dec00204 addi sp,sp,8 + 8027174: f800283a ret + +08027178 : +/* allow to be ifdeffed out on systems which already have a panic */ +#ifndef PANIC_ALREADY + +void +panic(char * msg) +{ + 8027178: defffd04 addi sp,sp,-12 + 802717c: dfc00215 stw ra,8(sp) + 8027180: df000115 stw fp,4(sp) + 8027184: df000104 addi fp,sp,4 + 8027188: e13fff15 stw r4,-4(fp) + dprintf("panic: %s\n", msg); + 802718c: e17fff17 ldw r5,-4(fp) + 8027190: 01020174 movhi r4,2053 + 8027194: 21289804 addi r4,r4,-23968 + 8027198: 8002c780 call 8002c78 + dtrap(); /* try to hook debugger */ + 802719c: 8028cd40 call 8028cd4 + netexit(1); /* try to clean up */ + 80271a0: 01000044 movi r4,1 + 80271a4: 803c5e80 call 803c5e8 +} + 80271a8: 0001883a nop + 80271ac: e037883a mov sp,fp + 80271b0: dfc00117 ldw ra,4(sp) + 80271b4: df000017 ldw fp,0(sp) + 80271b8: dec00204 addi sp,sp,8 + 80271bc: f800283a ret + +080271c0 : + +char eth_prt_buf[18]; /* buffer for return */ + +char * +print_eth(char * addr, char spacer) +{ + 80271c0: defffb04 addi sp,sp,-20 + 80271c4: df000415 stw fp,16(sp) + 80271c8: df000404 addi fp,sp,16 + 80271cc: e13ffd15 stw r4,-12(fp) + 80271d0: 2805883a mov r2,r5 + 80271d4: e0bffc05 stb r2,-16(fp) + int i; + char * out = eth_prt_buf; + 80271d8: 008201b4 movhi r2,2054 + 80271dc: 10b78d04 addi r2,r2,-8652 + 80271e0: e0bffe15 stw r2,-8(fp) + + /* loop through 6 bytes of ethernet address */ + for (i = 0; i < 6; i++) + 80271e4: e03fff15 stw zero,-4(fp) + 80271e8: 00003f06 br 80272e8 + { + /* high nibble */ + *out = (char)(((*addr >> 4) & 0x0f) + 0x30); + 80271ec: e0bffd17 ldw r2,-12(fp) + 80271f0: 10800003 ldbu r2,0(r2) + 80271f4: 10803fcc andi r2,r2,255 + 80271f8: 1004d13a srli r2,r2,4 + 80271fc: 10800c04 addi r2,r2,48 + 8027200: 1007883a mov r3,r2 + 8027204: e0bffe17 ldw r2,-8(fp) + 8027208: 10c00005 stb r3,0(r2) + if (*out > '9') /* need to make it A-F? */ + 802720c: e0bffe17 ldw r2,-8(fp) + 8027210: 10800003 ldbu r2,0(r2) + 8027214: 10803fcc andi r2,r2,255 + 8027218: 1080201c xori r2,r2,128 + 802721c: 10bfe004 addi r2,r2,-128 + 8027220: 10800e90 cmplti r2,r2,58 + 8027224: 1000061e bne r2,zero,8027240 + (*out) += 7; + 8027228: e0bffe17 ldw r2,-8(fp) + 802722c: 10800003 ldbu r2,0(r2) + 8027230: 108001c4 addi r2,r2,7 + 8027234: 1007883a mov r3,r2 + 8027238: e0bffe17 ldw r2,-8(fp) + 802723c: 10c00005 stb r3,0(r2) + out++; + 8027240: e0bffe17 ldw r2,-8(fp) + 8027244: 10800044 addi r2,r2,1 + 8027248: e0bffe15 stw r2,-8(fp) + + /* low nibble */ + *out = (char)((*addr & 0x0f) + 0x30); /* low nibble to digit */ + 802724c: e0bffd17 ldw r2,-12(fp) + 8027250: 10800003 ldbu r2,0(r2) + 8027254: 108003cc andi r2,r2,15 + 8027258: 10800c04 addi r2,r2,48 + 802725c: 1007883a mov r3,r2 + 8027260: e0bffe17 ldw r2,-8(fp) + 8027264: 10c00005 stb r3,0(r2) + if (*out > '9') /* need to make it A-F? */ + 8027268: e0bffe17 ldw r2,-8(fp) + 802726c: 10800003 ldbu r2,0(r2) + 8027270: 10803fcc andi r2,r2,255 + 8027274: 1080201c xori r2,r2,128 + 8027278: 10bfe004 addi r2,r2,-128 + 802727c: 10800e90 cmplti r2,r2,58 + 8027280: 1000061e bne r2,zero,802729c + (*out) += 7; /* eg 0x3a -> 0x41 ('A') */ + 8027284: e0bffe17 ldw r2,-8(fp) + 8027288: 10800003 ldbu r2,0(r2) + 802728c: 108001c4 addi r2,r2,7 + 8027290: 1007883a mov r3,r2 + 8027294: e0bffe17 ldw r2,-8(fp) + 8027298: 10c00005 stb r3,0(r2) + out++; + 802729c: e0bffe17 ldw r2,-8(fp) + 80272a0: 10800044 addi r2,r2,1 + 80272a4: e0bffe15 stw r2,-8(fp) + + /* optional spacer character */ + if (spacer && i < 5) + 80272a8: e0bffc07 ldb r2,-16(fp) + 80272ac: 10000826 beq r2,zero,80272d0 + 80272b0: e0bfff17 ldw r2,-4(fp) + 80272b4: 10800148 cmpgei r2,r2,5 + 80272b8: 1000051e bne r2,zero,80272d0 + *out++ = spacer; + 80272bc: e0bffe17 ldw r2,-8(fp) + 80272c0: 10c00044 addi r3,r2,1 + 80272c4: e0fffe15 stw r3,-8(fp) + 80272c8: e0fffc03 ldbu r3,-16(fp) + 80272cc: 10c00005 stb r3,0(r2) + addr++; + 80272d0: e0bffd17 ldw r2,-12(fp) + 80272d4: 10800044 addi r2,r2,1 + 80272d8: e0bffd15 stw r2,-12(fp) + for (i = 0; i < 6; i++) + 80272dc: e0bfff17 ldw r2,-4(fp) + 80272e0: 10800044 addi r2,r2,1 + 80272e4: e0bfff15 stw r2,-4(fp) + 80272e8: e0bfff17 ldw r2,-4(fp) + 80272ec: 10800190 cmplti r2,r2,6 + 80272f0: 103fbe1e bne r2,zero,80271ec + } + *out = 0; + 80272f4: e0bffe17 ldw r2,-8(fp) + 80272f8: 10000005 stb zero,0(r2) + return eth_prt_buf; + 80272fc: 008201b4 movhi r2,2054 + 8027300: 10b78d04 addi r2,r2,-8652 +} + 8027304: e037883a mov sp,fp + 8027308: df000017 ldw fp,0(sp) + 802730c: dec00104 addi sp,sp,4 + 8027310: f800283a ret + +08027314 : + * RETURNS: pointer to formatted text + */ + +char * +uslash(char * path) +{ + 8027314: defffd04 addi sp,sp,-12 + 8027318: df000215 stw fp,8(sp) + 802731c: df000204 addi fp,sp,8 + 8027320: e13ffe15 stw r4,-8(fp) + char * cp; + + for (cp = path; *cp; cp++) + 8027324: e0bffe17 ldw r2,-8(fp) + 8027328: e0bfff15 stw r2,-4(fp) + 802732c: 00000d06 br 8027364 + if (*cp == '\\') + 8027330: e0bfff17 ldw r2,-4(fp) + 8027334: 10800003 ldbu r2,0(r2) + 8027338: 10803fcc andi r2,r2,255 + 802733c: 1080201c xori r2,r2,128 + 8027340: 10bfe004 addi r2,r2,-128 + 8027344: 10801718 cmpnei r2,r2,92 + 8027348: 1000031e bne r2,zero,8027358 + *cp = '/'; + 802734c: e0bfff17 ldw r2,-4(fp) + 8027350: 00c00bc4 movi r3,47 + 8027354: 10c00005 stb r3,0(r2) + for (cp = path; *cp; cp++) + 8027358: e0bfff17 ldw r2,-4(fp) + 802735c: 10800044 addi r2,r2,1 + 8027360: e0bfff15 stw r2,-4(fp) + 8027364: e0bfff17 ldw r2,-4(fp) + 8027368: 10800003 ldbu r2,0(r2) + 802736c: 10803fcc andi r2,r2,255 + 8027370: 1080201c xori r2,r2,128 + 8027374: 10bfe004 addi r2,r2,-128 + 8027378: 103fed1e bne r2,zero,8027330 + return path; + 802737c: e0bffe17 ldw r2,-8(fp) +} + 8027380: e037883a mov sp,fp + 8027384: df000017 ldw fp,0(sp) + 8027388: dec00104 addi sp,sp,4 + 802738c: f800283a ret + +08027390 : + */ +#ifndef ns_printf + +int +ns_printf(void * vio, char * format, ...) +{ + 8027390: defff304 addi sp,sp,-52 + 8027394: dfc00a15 stw ra,40(sp) + 8027398: df000915 stw fp,36(sp) + 802739c: dc400815 stw r17,32(sp) + 80273a0: dc000715 stw r16,28(sp) + 80273a4: df000904 addi fp,sp,36 + 80273a8: e13ff815 stw r4,-32(fp) + 80273ac: e17ff715 stw r5,-36(fp) + 80273b0: e1800215 stw r6,8(fp) + 80273b4: e1c00315 stw r7,12(fp) + char * outbuf=NULL; + 80273b8: e03ffc15 stw zero,-16(fp) + int ret_value ; + int buf_size = MAXIOSIZE ; + 80273bc: 00802704 movi r2,156 + 80273c0: e0bffd15 stw r2,-12(fp) + GEN_IO pio = (GEN_IO)vio; /* convert void* to our IO device type */ + 80273c4: e0bff817 ldw r2,-32(fp) + 80273c8: e0bffb15 stw r2,-20(fp) + int * next_arg=(int *) &format; + next_arg += sizeof(char *)/sizeof(int) ; +#endif /* NATIVE_PRINTF || PRINTF_STRING */ + + /* a NULL pio means just dump the output to stdout */ + if (pio == NULL) + 80273cc: e0bffb17 ldw r2,-20(fp) + 80273d0: 1000091e bne r2,zero,80273f8 + { +#ifdef NATIVE_PRINTF + /* use the target system's ANSI routines */ + va_start(argList,format); + 80273d4: e0800204 addi r2,fp,8 + 80273d8: e0bff915 stw r2,-28(fp) + ret_value = vprintf(format,argList); + 80273dc: e0bff917 ldw r2,-28(fp) + 80273e0: 100b883a mov r5,r2 + 80273e4: e13ff717 ldw r4,-36(fp) + 80273e8: 80454580 call 8045458 + 80273ec: e0bffa15 stw r2,-24(fp) + va_end(argList); + return ret_value; + 80273f0: e0bffa17 ldw r2,-24(fp) + 80273f4: 00003b06 br 80274e4 + return strlen(format); +#endif /* NATIVE_PRINTF */ + } + + /* Check if the output function is set */ + if (pio->out == NULL) + 80273f8: e0bffb17 ldw r2,-20(fp) + 80273fc: 10800117 ldw r2,4(r2) + 8027400: 1000021e bne r2,zero,802740c + { + /* Programming mistake. Output function not set. */ + return -1; + 8027404: 00bfffc4 movi r2,-1 + 8027408: 00003606 br 80274e4 + + /* Allocate memory for the output string + * If the format string is greater than MAXIOSIZE, then + * we surely need to allocate a bigger block + */ + ret_value = strlen(format); + 802740c: e13ff717 ldw r4,-36(fp) + 8027410: 8002dac0 call 8002dac + 8027414: e0bffa15 stw r2,-24(fp) + if (ret_value >= MAXIOSIZE) + 8027418: e0bffa17 ldw r2,-24(fp) + 802741c: 10802710 cmplti r2,r2,156 + 8027420: 1000041e bne r2,zero,8027434 + { + buf_size += ret_value ; + 8027424: e0fffd17 ldw r3,-12(fp) + 8027428: e0bffa17 ldw r2,-24(fp) + 802742c: 1885883a add r2,r3,r2 + 8027430: e0bffd15 stw r2,-12(fp) + } + + outbuf=(char *)npalloc(buf_size); + 8027434: e0bffd17 ldw r2,-12(fp) + 8027438: 1009883a mov r4,r2 + 802743c: 802982c0 call 802982c + 8027440: e0bffc15 stw r2,-16(fp) + + if (outbuf == NULL) + 8027444: e0bffc17 ldw r2,-16(fp) + 8027448: 1000021e bne r2,zero,8027454 + { + return -2; + 802744c: 00bfff84 movi r2,-2 + 8027450: 00002406 br 80274e4 + + /* Now populate the output string */ + +#ifdef NATIVE_PRINTF + /* use the target system's ANSI routines */ + va_start(argList,format); + 8027454: e0800204 addi r2,fp,8 + 8027458: e0bff915 stw r2,-28(fp) + ret_value = vsprintf(outbuf,format,argList); + 802745c: e0bff917 ldw r2,-28(fp) + 8027460: 100d883a mov r6,r2 + 8027464: e17ff717 ldw r5,-36(fp) + 8027468: e13ffc17 ldw r4,-16(fp) + 802746c: 80454d00 call 80454d0 + 8027470: e0bffa15 stw r2,-24(fp) +#endif /* PRINTF_STDARG */ +#endif /* NATIVE_PRINTF */ + +#ifdef NATIVE_PRINTF + /* Check if we have overwritten the output buffer */ + if ((int)strlen(outbuf) > buf_size) + 8027474: e13ffc17 ldw r4,-16(fp) + 8027478: 8002dac0 call 8002dac + 802747c: 1007883a mov r3,r2 + 8027480: e0bffd17 ldw r2,-12(fp) + 8027484: 10c0080e bge r2,r3,80274a8 + */ + /* Yes , we have overwritten. Truncate the output string. + * Some memory in the heap has been corrupted, but it is too + * late to rectify. + */ + panic("ns_printf:Buffer overflow"); + 8027488: 01020174 movhi r4,2053 + 802748c: 21289b04 addi r4,r4,-23956 + 8027490: 80271780 call 8027178 + outbuf[buf_size-1]=0; /* Null terminate the string */ + 8027494: e0bffd17 ldw r2,-12(fp) + 8027498: 10bfffc4 addi r2,r2,-1 + 802749c: e0fffc17 ldw r3,-16(fp) + 80274a0: 1885883a add r2,r3,r2 + 80274a4: 10000005 stb zero,0(r2) + } +#endif + + ret_value =(pio->out)(pio->id,outbuf,strlen(outbuf)) ; + 80274a8: e0bffb17 ldw r2,-20(fp) + 80274ac: 14000117 ldw r16,4(r2) + 80274b0: e0bffb17 ldw r2,-20(fp) + 80274b4: 14400217 ldw r17,8(r2) + 80274b8: e13ffc17 ldw r4,-16(fp) + 80274bc: 8002dac0 call 8002dac + 80274c0: 100d883a mov r6,r2 + 80274c4: e17ffc17 ldw r5,-16(fp) + 80274c8: 8809883a mov r4,r17 + 80274cc: 803ee83a callr r16 + 80274d0: e0bffa15 stw r2,-24(fp) + + /* Free memory for the output string */ + npfree(outbuf); + 80274d4: e13ffc17 ldw r4,-16(fp) + 80274d8: 80298600 call 8029860 + + /* since ns_printf() can get called repeatedly down in the bowels + * of a single command interpretting function, spin tk_yield() so + * that some packets get a chance to get received + */ + tk_yield(); + 80274dc: 8027ce40 call 8027ce4 + + return ret_value ; + 80274e0: e0bffa17 ldw r2,-24(fp) +} + 80274e4: e6fffe04 addi sp,fp,-8 + 80274e8: dfc00317 ldw ra,12(sp) + 80274ec: df000217 ldw fp,8(sp) + 80274f0: dc400117 ldw r17,4(sp) + 80274f4: dc000017 ldw r16,0(sp) + 80274f8: dec00604 addi sp,sp,24 + 80274fc: f800283a ret + +08027500 : + * + * RETURNS: Number of bytes send to standard output. + */ + +int std_out(long s, char * buf, int len) +{ + 8027500: defffb04 addi sp,sp,-20 + 8027504: dfc00415 stw ra,16(sp) + 8027508: df000315 stw fp,12(sp) + 802750c: df000304 addi fp,sp,12 + 8027510: e13fff15 stw r4,-4(fp) + 8027514: e17ffe15 stw r5,-8(fp) + 8027518: e1bffd15 stw r6,-12(fp) + /* puts(buf); - This does newline expansion return + * write(0,buf,len); - This doesn't printf(buf); - This has + * problems when printf format strings (eg %s) is part of data. + */ + printf("%s",buf); + 802751c: e17ffe17 ldw r5,-8(fp) + 8027520: 01020174 movhi r4,2053 + 8027524: 2128a204 addi r4,r4,-23928 + 8027528: 8002c780 call 8002c78 + USE_ARG(s); + return len; + 802752c: e0bffd17 ldw r2,-12(fp) +} + 8027530: e037883a mov sp,fp + 8027534: dfc00117 ldw ra,4(sp) + 8027538: df000017 ldw fp,0(sp) + 802753c: dec00204 addi sp,sp,8 + 8027540: f800283a ret + +08027544 : + * RETURNS: 1 if we got a break, 0 to keep printing + */ + +int +con_page(void * vio, int lines) +{ + 8027544: defffa04 addi sp,sp,-24 + 8027548: dfc00515 stw ra,20(sp) + 802754c: df000415 stw fp,16(sp) + 8027550: df000404 addi fp,sp,16 + 8027554: e13ffd15 stw r4,-12(fp) + 8027558: e17ffc15 stw r5,-16(fp) + int ch; + GEN_IO pio = (GEN_IO)vio; /* convert void* to our IO device type */ + 802755c: e0bffd17 ldw r2,-12(fp) + 8027560: e0bfff15 stw r2,-4(fp) + + if (lines % 20 == 0) /* Time to get user input */ + 8027564: e0bffc17 ldw r2,-16(fp) + 8027568: 01400504 movi r5,20 + 802756c: 1009883a mov r4,r2 + 8027570: 800cf800 call 800cf80 <__modsi3> + 8027574: 1000231e bne r2,zero,8027604 + { + if (pio && pio->getch) /*if i/p func is supplied*/ + 8027578: e0bfff17 ldw r2,-4(fp) + 802757c: 10002126 beq r2,zero,8027604 + 8027580: e0bfff17 ldw r2,-4(fp) + 8027584: 10800317 ldw r2,12(r2) + 8027588: 10001e26 beq r2,zero,8027604 + { + ns_printf(pio,"....press any key for more (ESC to break)...."); + 802758c: 01420174 movhi r5,2053 + 8027590: 2968a304 addi r5,r5,-23924 + 8027594: e13fff17 ldw r4,-4(fp) + 8027598: 80273900 call 8027390 + + do + { + ch = (pio->getch)(pio->id); + 802759c: e0bfff17 ldw r2,-4(fp) + 80275a0: 10800317 ldw r2,12(r2) + 80275a4: e0ffff17 ldw r3,-4(fp) + 80275a8: 18c00217 ldw r3,8(r3) + 80275ac: 1809883a mov r4,r3 + 80275b0: 103ee83a callr r2 + 80275b4: e0bffe15 stw r2,-8(fp) + if (ch == 0) + 80275b8: e0bffe17 ldw r2,-8(fp) + 80275bc: 1000011e bne r2,zero,80275c4 + tk_yield(); /* Give timeslice to other processes */ + 80275c0: 8027ce40 call 8027ce4 + } while (ch == 0) ; + 80275c4: e0bffe17 ldw r2,-8(fp) + 80275c8: 103ff426 beq r2,zero,802759c + + /* if there is fatal error, we don't want to do any I/O */ + if (ch == -1) /* fatal error */ + 80275cc: e0bffe17 ldw r2,-8(fp) + 80275d0: 10bfffd8 cmpnei r2,r2,-1 + 80275d4: 1000021e bne r2,zero,80275e0 + return 1 ; + 80275d8: 00800044 movi r2,1 + 80275dc: 00000a06 br 8027608 + + ns_printf(pio,"\n"); + 80275e0: 01420174 movhi r5,2053 + 80275e4: 29688404 addi r5,r5,-24048 + 80275e8: e13fff17 ldw r4,-4(fp) + 80275ec: 80273900 call 8027390 + if (ch == 27) /* ESC key pressed */ + 80275f0: e0bffe17 ldw r2,-8(fp) + 80275f4: 108006d8 cmpnei r2,r2,27 + 80275f8: 1000021e bne r2,zero,8027604 + return 1 ; + 80275fc: 00800044 movi r2,1 + 8027600: 00000106 br 8027608 + } + } + return 0; + 8027604: 0005883a mov r2,zero +} + 8027608: e037883a mov sp,fp + 802760c: dfc00117 ldw ra,4(sp) + 8027610: df000017 ldw fp,0(sp) + 8027614: dec00204 addi sp,sp,8 + 8027618: f800283a ret + +0802761c : + +char **parse_args(char *buf, int argc, int *pargc_index) +{ + 802761c: defff704 addi sp,sp,-36 + 8027620: dfc00815 stw ra,32(sp) + 8027624: df000715 stw fp,28(sp) + 8027628: df000704 addi fp,sp,28 + 802762c: e13ffb15 stw r4,-20(fp) + 8027630: e17ffa15 stw r5,-24(fp) + 8027634: e1bff915 stw r6,-28(fp) + /* This routine assumes buf is a null terminated string */ + int i; + int len; + char *bp = buf; + 8027638: e0bffb17 ldw r2,-20(fp) + 802763c: e0bffe15 stw r2,-8(fp) + char **pargv = NULL; + 8027640: e03ffd15 stw zero,-12(fp) + *pargc_index = 0; + 8027644: e0bff917 ldw r2,-28(fp) + 8027648: 10000015 stw zero,0(r2) + if (buf == NULL) + 802764c: e0bffb17 ldw r2,-20(fp) + 8027650: 1000021e bne r2,zero,802765c + { + return (NULL); + 8027654: 0005883a mov r2,zero + 8027658: 00006906 br 8027800 + } + len = strlen(buf); + 802765c: e13ffb17 ldw r4,-20(fp) + 8027660: 8002dac0 call 8002dac + 8027664: e0bffc15 stw r2,-16(fp) + if (len <= 0) + 8027668: e0bffc17 ldw r2,-16(fp) + 802766c: 00800216 blt zero,r2,8027678 + { + return (NULL); + 8027670: 0005883a mov r2,zero + 8027674: 00006206 br 8027800 + } + pargv = (char **) npalloc(argc * sizeof(char *)); + 8027678: e0bffa17 ldw r2,-24(fp) + 802767c: 100490ba slli r2,r2,2 + 8027680: 1009883a mov r4,r2 + 8027684: 802982c0 call 802982c + 8027688: e0bffd15 stw r2,-12(fp) + if (pargv == NULL) + 802768c: e0bffd17 ldw r2,-12(fp) + 8027690: 1000051e bne r2,zero,80276a8 + { + return (NULL); + 8027694: 0005883a mov r2,zero + 8027698: 00005906 br 8027800 + } + /* skip the initial blanks if any */ + while (*bp == ' ') + { + bp++; + 802769c: e0bffe17 ldw r2,-8(fp) + 80276a0: 10800044 addi r2,r2,1 + 80276a4: e0bffe15 stw r2,-8(fp) + while (*bp == ' ') + 80276a8: e0bffe17 ldw r2,-8(fp) + 80276ac: 10800003 ldbu r2,0(r2) + 80276b0: 10803fcc andi r2,r2,255 + 80276b4: 1080201c xori r2,r2,128 + 80276b8: 10bfe004 addi r2,r2,-128 + 80276bc: 10800820 cmpeqi r2,r2,32 + 80276c0: 103ff61e bne r2,zero,802769c + } + while ((*bp != '\0') && ((*pargc_index) < argc)) + 80276c4: 00002e06 br 8027780 + { + pargv[(*pargc_index)] = bp; + 80276c8: e0bff917 ldw r2,-28(fp) + 80276cc: 10800017 ldw r2,0(r2) + 80276d0: 100490ba slli r2,r2,2 + 80276d4: e0fffd17 ldw r3,-12(fp) + 80276d8: 1885883a add r2,r3,r2 + 80276dc: e0fffe17 ldw r3,-8(fp) + 80276e0: 10c00015 stw r3,0(r2) + (*pargc_index)++; + 80276e4: e0bff917 ldw r2,-28(fp) + 80276e8: 10800017 ldw r2,0(r2) + 80276ec: 10c00044 addi r3,r2,1 + 80276f0: e0bff917 ldw r2,-28(fp) + 80276f4: 10c00015 stw r3,0(r2) + while (*bp != ' ' && *bp != '\0') + 80276f8: 00000306 br 8027708 + { + bp++; + 80276fc: e0bffe17 ldw r2,-8(fp) + 8027700: 10800044 addi r2,r2,1 + 8027704: e0bffe15 stw r2,-8(fp) + while (*bp != ' ' && *bp != '\0') + 8027708: e0bffe17 ldw r2,-8(fp) + 802770c: 10800003 ldbu r2,0(r2) + 8027710: 10803fcc andi r2,r2,255 + 8027714: 1080201c xori r2,r2,128 + 8027718: 10bfe004 addi r2,r2,-128 + 802771c: 10800820 cmpeqi r2,r2,32 + 8027720: 10000a1e bne r2,zero,802774c + 8027724: e0bffe17 ldw r2,-8(fp) + 8027728: 10800003 ldbu r2,0(r2) + 802772c: 10803fcc andi r2,r2,255 + 8027730: 1080201c xori r2,r2,128 + 8027734: 10bfe004 addi r2,r2,-128 + 8027738: 103ff01e bne r2,zero,80276fc + } + while (*bp == ' ' && *bp != '\0') + 802773c: 00000306 br 802774c + { + bp++; + 8027740: e0bffe17 ldw r2,-8(fp) + 8027744: 10800044 addi r2,r2,1 + 8027748: e0bffe15 stw r2,-8(fp) + while (*bp == ' ' && *bp != '\0') + 802774c: e0bffe17 ldw r2,-8(fp) + 8027750: 10800003 ldbu r2,0(r2) + 8027754: 10803fcc andi r2,r2,255 + 8027758: 1080201c xori r2,r2,128 + 802775c: 10bfe004 addi r2,r2,-128 + 8027760: 10800818 cmpnei r2,r2,32 + 8027764: 1000061e bne r2,zero,8027780 + 8027768: e0bffe17 ldw r2,-8(fp) + 802776c: 10800003 ldbu r2,0(r2) + 8027770: 10803fcc andi r2,r2,255 + 8027774: 1080201c xori r2,r2,128 + 8027778: 10bfe004 addi r2,r2,-128 + 802777c: 103ff01e bne r2,zero,8027740 + while ((*bp != '\0') && ((*pargc_index) < argc)) + 8027780: e0bffe17 ldw r2,-8(fp) + 8027784: 10800003 ldbu r2,0(r2) + 8027788: 10803fcc andi r2,r2,255 + 802778c: 1080201c xori r2,r2,128 + 8027790: 10bfe004 addi r2,r2,-128 + 8027794: 10000426 beq r2,zero,80277a8 + 8027798: e0bff917 ldw r2,-28(fp) + 802779c: 10c00017 ldw r3,0(r2) + 80277a0: e0bffa17 ldw r2,-24(fp) + 80277a4: 18bfc816 blt r3,r2,80276c8 + } + } + for (i = 0; i < len; i++) + 80277a8: e03fff15 stw zero,-4(fp) + 80277ac: 00001006 br 80277f0 + { + if (buf[i] == ' ') + 80277b0: e0bfff17 ldw r2,-4(fp) + 80277b4: e0fffb17 ldw r3,-20(fp) + 80277b8: 1885883a add r2,r3,r2 + 80277bc: 10800003 ldbu r2,0(r2) + 80277c0: 10803fcc andi r2,r2,255 + 80277c4: 1080201c xori r2,r2,128 + 80277c8: 10bfe004 addi r2,r2,-128 + 80277cc: 10800818 cmpnei r2,r2,32 + 80277d0: 1000041e bne r2,zero,80277e4 + buf[i] = '\0'; + 80277d4: e0bfff17 ldw r2,-4(fp) + 80277d8: e0fffb17 ldw r3,-20(fp) + 80277dc: 1885883a add r2,r3,r2 + 80277e0: 10000005 stb zero,0(r2) + for (i = 0; i < len; i++) + 80277e4: e0bfff17 ldw r2,-4(fp) + 80277e8: 10800044 addi r2,r2,1 + 80277ec: e0bfff15 stw r2,-4(fp) + 80277f0: e0ffff17 ldw r3,-4(fp) + 80277f4: e0bffc17 ldw r2,-16(fp) + 80277f8: 18bfed16 blt r3,r2,80277b0 + { + printf("pargv[%d] = %s\n", i, pargv[i]); + } +#endif + + return (pargv); + 80277fc: e0bffd17 ldw r2,-12(fp) +} + 8027800: e037883a mov sp,fp + 8027804: dfc00117 ldw ra,4(sp) + 8027808: df000017 ldw fp,0(sp) + 802780c: dec00204 addi sp,sp,8 + 8027810: f800283a ret + +08027814 : + * RETURNS: + */ + +int +netmain(void) +{ + 8027814: defffc04 addi sp,sp,-16 + 8027818: dfc00315 stw ra,12(sp) + 802781c: df000215 stw fp,8(sp) + 8027820: df000204 addi fp,sp,8 + int i; + int e; + + iniche_net_ready = FALSE; + 8027824: d0206f15 stw zero,-32324(gp) + + e = prep_modules(); + 8027828: 8038a5c0 call 8038a5c + 802782c: e0bffe15 stw r2,-8(fp) + + /* Create the threads for net, timer, and apps */ + for (i = 0; i < num_net_tasks; i++) + 8027830: e03fff15 stw zero,-4(fp) + 8027834: 00001a06 br 80278a0 + { + e = TK_NEWTASK(&nettasks[i]); + 8027838: e0bfff17 ldw r2,-4(fp) + 802783c: 10c00624 muli r3,r2,24 + 8027840: 00820174 movhi r2,2053 + 8027844: 10b1ec04 addi r2,r2,-14416 + 8027848: 1885883a add r2,r3,r2 + 802784c: 1009883a mov r4,r2 + 8027850: 80290740 call 8029074 + 8027854: e0bffe15 stw r2,-8(fp) + if (e != 0) + 8027858: e0bffe17 ldw r2,-8(fp) + 802785c: 10000d26 beq r2,zero,8027894 + { + dprintf("task create error\n"); + 8027860: 01020174 movhi r4,2053 + 8027864: 2128b504 addi r4,r4,-23852 + 8027868: 8002d9c0 call 8002d9c + panic((char *)&nettasks[i].name); + 802786c: e0bfff17 ldw r2,-4(fp) + 8027870: 10800624 muli r2,r2,24 + 8027874: 10c00104 addi r3,r2,4 + 8027878: 00820174 movhi r2,2053 + 802787c: 10b1ec04 addi r2,r2,-14416 + 8027880: 1885883a add r2,r3,r2 + 8027884: 1009883a mov r4,r2 + 8027888: 80271780 call 8027178 + return -1; /* compiler warnings */ + 802788c: 00bfffc4 movi r2,-1 + 8027890: 00001306 br 80278e0 + for (i = 0; i < num_net_tasks; i++) + 8027894: e0bfff17 ldw r2,-4(fp) + 8027898: 10800044 addi r2,r2,1 + 802789c: e0bfff15 stw r2,-4(fp) + 80278a0: d0a01417 ldw r2,-32688(gp) + 80278a4: e0ffff17 ldw r3,-4(fp) + 80278a8: 18bfe316 blt r3,r2,8027838 + } + } + + e = create_apptasks(); + 80278ac: 8038e380 call 8038e38 + 80278b0: e0bffe15 stw r2,-8(fp) + if (e != 0) + 80278b4: e0bffe17 ldw r2,-8(fp) + 80278b8: 10000826 beq r2,zero,80278dc + { + dprintf("task create error\n"); + 80278bc: 01020174 movhi r4,2053 + 80278c0: 2128b504 addi r4,r4,-23852 + 80278c4: 8002d9c0 call 8002d9c + panic("netmain"); + 80278c8: 01020174 movhi r4,2053 + 80278cc: 2128ba04 addi r4,r4,-23832 + 80278d0: 80271780 call 8027178 + return -1; /* compiler warnings */ + 80278d4: 00bfffc4 movi r2,-1 + 80278d8: 00000106 br 80278e0 +#ifdef MAIN_TASK_IS_NET + tk_netmain(TK_NETMAINPARM); + panic("net task return"); + return -1; +#else + return 0; + 80278dc: 0005883a mov r2,zero +#endif +#endif /* NO_INET_STACK */ +} + 80278e0: e037883a mov sp,fp + 80278e4: dfc00117 ldw ra,4(sp) + 80278e8: df000017 ldw fp,0(sp) + 80278ec: dec00204 addi sp,sp,8 + 80278f0: f800283a ret + +080278f4 : + * RETURNS: n/a + */ + +#ifndef NO_INET_STACK +TK_ENTRY(tk_netmain) +{ + 80278f4: defffc04 addi sp,sp,-16 + 80278f8: dfc00315 stw ra,12(sp) + 80278fc: df000215 stw fp,8(sp) + 8027900: df000204 addi fp,sp,8 + 8027904: e13ffe15 stw r4,-8(fp) + netmain_init(); /* initialize all modules */ + 8027908: 80386dc0 call 80386dc + + iniche_net_ready = TRUE; /* let the other threads spin */ + 802790c: 00800044 movi r2,1 + 8027910: d0a06f15 stw r2,-32324(gp) + + for (;;) + { + TK_NETRX_BLOCK(); + 8027914: d0a08017 ldw r2,-32256(gp) + 8027918: e0ffffc4 addi r3,fp,-1 + 802791c: 180d883a mov r6,r3 + 8027920: 01401904 movi r5,100 + 8027924: 1009883a mov r4,r2 + 8027928: 8015a600 call 8015a60 + 802792c: e0bfffc3 ldbu r2,-1(fp) + 8027930: 10803fcc andi r2,r2,255 + 8027934: 10000526 beq r2,zero,802794c + 8027938: e0bfffc3 ldbu r2,-1(fp) + 802793c: 10803fcc andi r2,r2,255 + 8027940: 108002a0 cmpeqi r2,r2,10 + 8027944: 1000011e bne r2,zero,802794c + 8027948: 8028cd40 call 8028cd4 + netmain_wakes++; /* count wakeups */ + 802794c: d0a06d17 ldw r2,-32332(gp) + 8027950: 10800044 addi r2,r2,1 + 8027954: d0a06d15 stw r2,-32332(gp) + + /* see if there's newly received network packets */ + if (rcvdq.q_len) + 8027958: 008201b4 movhi r2,2054 + 802795c: 10b6ad17 ldw r2,-9548(r2) + 8027960: 103fec26 beq r2,zero,8027914 + pktdemux(); + 8027964: 80249c40 call 80249c4 + TK_NETRX_BLOCK(); + 8027968: 003fea06 br 8027914 + +0802796c : +extern int dhc_second(void); +#endif + +#ifndef NO_INET_TICK +TK_ENTRY(tk_nettick) +{ + 802796c: defffd04 addi sp,sp,-12 + 8027970: dfc00215 stw ra,8(sp) + 8027974: df000115 stw fp,4(sp) + 8027978: df000104 addi fp,sp,4 + 802797c: e13fff15 stw r4,-4(fp) + /* wait till the stack is initialized */ + while (!iniche_net_ready) + 8027980: 00000206 br 802798c + * run to restart it. + */ +#ifdef DHCP_CLIENT + dhc_second(); +#endif + TK_SLEEP(1); + 8027984: 01000084 movi r4,2 + 8027988: 801730c0 call 801730c + while (!iniche_net_ready) + 802798c: d0a06f17 ldw r2,-32324(gp) + 8027990: 103ffc26 beq r2,zero,8027984 + } + + for (;;) + { + TK_SLEEP(SYS_SHORT_SLEEP); + 8027994: 01000084 movi r4,2 + 8027998: 801730c0 call 801730c + nettick_wakes++; /* count wakeups */ + 802799c: d0a06e17 ldw r2,-32328(gp) + 80279a0: 10800044 addi r2,r2,1 + 80279a4: d0a06e15 stw r2,-32328(gp) + inet_timer(); /* let various timeouts occur */ + 80279a8: 8038ab00 call 8038ab0 + TK_SLEEP(SYS_SHORT_SLEEP); + 80279ac: 003ff906 br 8027994 + +080279b0 : +u_char TK_OSTaskQuery(void); + + + +void TK_OSTimeDly(void) +{ + 80279b0: defffe04 addi sp,sp,-8 + 80279b4: dfc00115 stw ra,4(sp) + 80279b8: df000015 stw fp,0(sp) + 80279bc: d839883a mov fp,sp + OSTimeDly(2); + 80279c0: 01000084 movi r4,2 + 80279c4: 801730c0 call 801730c +} + 80279c8: 0001883a nop + 80279cc: e037883a mov sp,fp + 80279d0: dfc00117 ldw ra,4(sp) + 80279d4: df000017 ldw fp,0(sp) + 80279d8: dec00204 addi sp,sp,8 + 80279dc: f800283a ret + +080279e0 : + + + +void TK_OSTaskResume(u_char * Id) +{ + 80279e0: defffc04 addi sp,sp,-16 + 80279e4: dfc00315 stw ra,12(sp) + 80279e8: df000215 stw fp,8(sp) + 80279ec: df000204 addi fp,sp,8 + 80279f0: e13ffe15 stw r4,-8(fp) +INT8U err; + + err = OSTaskResume(*Id); + 80279f4: e0bffe17 ldw r2,-8(fp) + 80279f8: 10800003 ldbu r2,0(r2) + 80279fc: 10803fcc andi r2,r2,255 + 8027a00: 1009883a mov r4,r2 + 8027a04: 8016ec00 call 8016ec0 + 8027a08: e0bfffc5 stb r2,-1(fp) + +#ifdef NPDEBUG + if ((err != OS_NO_ERR) && (err != OS_TASK_NOT_SUSPENDED)) + 8027a0c: e0bfffc3 ldbu r2,-1(fp) + 8027a10: 10000a26 beq r2,zero,8027a3c + 8027a14: e0bfffc3 ldbu r2,-1(fp) + 8027a18: 10801120 cmpeqi r2,r2,68 + 8027a1c: 1000071e bne r2,zero,8027a3c + { + dprintf("ChronOS API call failure, to Resume Suspended Task!\n"); + 8027a20: 01020174 movhi r4,2053 + 8027a24: 2128bc04 addi r4,r4,-23824 + 8027a28: 8002d9c0 call 8002d9c + dtrap(); + 8027a2c: 8028cd40 call 8028cd4 + panic("TK_OSTaskResume"); + 8027a30: 01020174 movhi r4,2053 + 8027a34: 2128c904 addi r4,r4,-23772 + 8027a38: 80271780 call 8027178 + } +#endif +} + 8027a3c: 0001883a nop + 8027a40: e037883a mov sp,fp + 8027a44: dfc00117 ldw ra,4(sp) + 8027a48: df000017 ldw fp,0(sp) + 8027a4c: dec00204 addi sp,sp,8 + 8027a50: f800283a ret + +08027a54 : + * + * RETURN: none + */ +void +tcp_sleep(void * event) +{ + 8027a54: defffb04 addi sp,sp,-20 + 8027a58: dfc00415 stw ra,16(sp) + 8027a5c: df000315 stw fp,12(sp) + 8027a60: df000304 addi fp,sp,12 + 8027a64: e13ffd15 stw r4,-12(fp) + int i; + INT8U err; + + for (i = 0; i < GLOBWAKE_SZ; i++) + 8027a68: e03fff15 stw zero,-4(fp) + 8027a6c: 00003d06 br 8027b64 + { + if (global_TCPwakeup_set[i].soc_event == NULL) + 8027a70: e0bfff17 ldw r2,-4(fp) + 8027a74: 10c00324 muli r3,r2,12 + 8027a78: 008201b4 movhi r2,2054 + 8027a7c: 1885883a add r2,r3,r2 + 8027a80: 10b82017 ldw r2,-8064(r2) + 8027a84: 1000341e bne r2,zero,8027b58 + { + global_TCPwakeup_set[i].soc_event = event; + 8027a88: e0bfff17 ldw r2,-4(fp) + 8027a8c: 11000324 muli r4,r2,12 + 8027a90: e0fffd17 ldw r3,-12(fp) + 8027a94: 008201b4 movhi r2,2054 + 8027a98: 2085883a add r2,r4,r2 + 8027a9c: 10f82015 stw r3,-8064(r2) + global_TCPwakeup_set[i].ctick = cticks; + 8027aa0: d0e07d17 ldw r3,-32268(gp) + 8027aa4: e0bfff17 ldw r2,-4(fp) + 8027aa8: 11000324 muli r4,r2,12 + 8027aac: 008201b4 movhi r2,2054 + 8027ab0: 2085883a add r2,r4,r2 + 8027ab4: 10f81f15 stw r3,-8068(r2) + if (i > global_TCPwakeup_setIndx) + 8027ab8: d0e07c17 ldw r3,-32272(gp) + 8027abc: e0bfff17 ldw r2,-4(fp) + 8027ac0: 1880020e bge r3,r2,8027acc + global_TCPwakeup_setIndx = i; + 8027ac4: e0bfff17 ldw r2,-4(fp) + 8027ac8: d0a07c15 stw r2,-32272(gp) + + tcp_sleep_count++; + 8027acc: d0a07817 ldw r2,-32288(gp) + 8027ad0: 10800044 addi r2,r2,1 + 8027ad4: d0a07815 stw r2,-32288(gp) + + /* Give up the lock before going to sleep. This can + * potentially cause a context switch to the task + * signaling the event. + */ + UNLOCK_NET_RESOURCE(NET_RESID); + 8027ad8: 0009883a mov r4,zero + 8027adc: 8028ff40 call 8028ff4 + + /* don't wait forever in case we miss the event */ + OSSemPend(global_TCPwakeup_set[i].semaphore, TPS, &err); + 8027ae0: e0bfff17 ldw r2,-4(fp) + 8027ae4: 10c00324 muli r3,r2,12 + 8027ae8: 008201b4 movhi r2,2054 + 8027aec: 1885883a add r2,r3,r2 + 8027af0: 10b82117 ldw r2,-8060(r2) + 8027af4: e0fffec4 addi r3,fp,-5 + 8027af8: 180d883a mov r6,r3 + 8027afc: 01401904 movi r5,100 + 8027b00: 1009883a mov r4,r2 + 8027b04: 8015a600 call 8015a60 + if (err == 10) + 8027b08: e0bffec3 ldbu r2,-5(fp) + 8027b0c: 10803fcc andi r2,r2,255 + 8027b10: 10800298 cmpnei r2,r2,10 + 8027b14: 10000d1e bne r2,zero,8027b4c + { + ++tcp_sleep_timeout; + 8027b18: d0a07117 ldw r2,-32316(gp) + 8027b1c: 10800044 addi r2,r2,1 + 8027b20: d0a07115 stw r2,-32316(gp) + + /* clear the entry */ + global_TCPwakeup_set[i].ctick = 0; + 8027b24: e0bfff17 ldw r2,-4(fp) + 8027b28: 10c00324 muli r3,r2,12 + 8027b2c: 008201b4 movhi r2,2054 + 8027b30: 1885883a add r2,r3,r2 + 8027b34: 10381f15 stw zero,-8068(r2) + global_TCPwakeup_set[i].soc_event = NULL; + 8027b38: e0bfff17 ldw r2,-4(fp) + 8027b3c: 10c00324 muli r3,r2,12 + 8027b40: 008201b4 movhi r2,2054 + 8027b44: 1885883a add r2,r3,r2 + 8027b48: 10382015 stw zero,-8064(r2) + } + + /* Regain the lock */ + LOCK_NET_RESOURCE(NET_RESID); + 8027b4c: 0009883a mov r4,zero + 8027b50: 8028f380 call 8028f38 + 8027b54: 00000d06 br 8027b8c + for (i = 0; i < GLOBWAKE_SZ; i++) + 8027b58: e0bfff17 ldw r2,-4(fp) + 8027b5c: 10800044 addi r2,r2,1 + 8027b60: e0bfff15 stw r2,-4(fp) + 8027b64: e0bfff17 ldw r2,-4(fp) + 8027b68: 10800510 cmplti r2,r2,20 + 8027b6c: 103fc01e bne r2,zero,8027a70 + + /* The table is full. Try calling TK_YIELD() and hope for the best. + * The user should increase the size of the table. + * We'll record the max index for debugging purposes. + */ + global_TCPwakeup_setIndx = i; + 8027b70: e0bfff17 ldw r2,-4(fp) + 8027b74: d0a07c15 stw r2,-32272(gp) + + UNLOCK_NET_RESOURCE(NET_RESID); + 8027b78: 0009883a mov r4,zero + 8027b7c: 8028ff40 call 8028ff4 + TK_YIELD(); + 8027b80: 8027ce40 call 8027ce4 + LOCK_NET_RESOURCE(NET_RESID); + 8027b84: 0009883a mov r4,zero + 8027b88: 8028f380 call 8028f38 +} + 8027b8c: e037883a mov sp,fp + 8027b90: dfc00117 ldw ra,4(sp) + 8027b94: df000017 ldw fp,0(sp) + 8027b98: dec00204 addi sp,sp,8 + 8027b9c: f800283a ret + +08027ba0 : + * + * RETURN: none + */ +void +tcp_wakeup(void *event) +{ + 8027ba0: defffc04 addi sp,sp,-16 + 8027ba4: dfc00315 stw ra,12(sp) + 8027ba8: df000215 stw fp,8(sp) + 8027bac: df000204 addi fp,sp,8 + 8027bb0: e13ffe15 stw r4,-8(fp) + int i; + + OSSchedLock(); + 8027bb4: 80109080 call 8010908 + + for (i = 0; i < GLOBWAKE_SZ; i++) + 8027bb8: e03fff15 stw zero,-4(fp) + 8027bbc: 00002406 br 8027c50 + { + if ((global_TCPwakeup_set[i].ctick != 0) && + 8027bc0: e0bfff17 ldw r2,-4(fp) + 8027bc4: 10c00324 muli r3,r2,12 + 8027bc8: 008201b4 movhi r2,2054 + 8027bcc: 1885883a add r2,r3,r2 + 8027bd0: 10b81f17 ldw r2,-8068(r2) + 8027bd4: 10001b26 beq r2,zero,8027c44 + (global_TCPwakeup_set[i].soc_event == event)) + 8027bd8: e0bfff17 ldw r2,-4(fp) + 8027bdc: 10c00324 muli r3,r2,12 + 8027be0: 008201b4 movhi r2,2054 + 8027be4: 1885883a add r2,r3,r2 + 8027be8: 10b82017 ldw r2,-8064(r2) + if ((global_TCPwakeup_set[i].ctick != 0) && + 8027bec: e0fffe17 ldw r3,-8(fp) + 8027bf0: 1880141e bne r3,r2,8027c44 + { + /* signal the event */ + OSSemPost(global_TCPwakeup_set[i].semaphore); + 8027bf4: e0bfff17 ldw r2,-4(fp) + 8027bf8: 10c00324 muli r3,r2,12 + 8027bfc: 008201b4 movhi r2,2054 + 8027c00: 1885883a add r2,r3,r2 + 8027c04: 10b82117 ldw r2,-8060(r2) + 8027c08: 1009883a mov r4,r2 + 8027c0c: 8015d840 call 8015d84 + + /* clear the entry */ + global_TCPwakeup_set[i].ctick = 0; + 8027c10: e0bfff17 ldw r2,-4(fp) + 8027c14: 10c00324 muli r3,r2,12 + 8027c18: 008201b4 movhi r2,2054 + 8027c1c: 1885883a add r2,r3,r2 + 8027c20: 10381f15 stw zero,-8068(r2) + global_TCPwakeup_set[i].soc_event = NULL; + 8027c24: e0bfff17 ldw r2,-4(fp) + 8027c28: 10c00324 muli r3,r2,12 + 8027c2c: 008201b4 movhi r2,2054 + 8027c30: 1885883a add r2,r3,r2 + 8027c34: 10382015 stw zero,-8064(r2) + + tcp_wakeup_count++; + 8027c38: d0a07917 ldw r2,-32284(gp) + 8027c3c: 10800044 addi r2,r2,1 + 8027c40: d0a07915 stw r2,-32284(gp) + for (i = 0; i < GLOBWAKE_SZ; i++) + 8027c44: e0bfff17 ldw r2,-4(fp) + 8027c48: 10800044 addi r2,r2,1 + 8027c4c: e0bfff15 stw r2,-4(fp) + 8027c50: e0bfff17 ldw r2,-4(fp) + 8027c54: 10800510 cmplti r2,r2,20 + 8027c58: 103fd91e bne r2,zero,8027bc0 + } + } + + OSSchedUnlock(); + 8027c5c: 80109940 call 8010994 +} + 8027c60: 0001883a nop + 8027c64: e037883a mov sp,fp + 8027c68: dfc00117 ldw ra,4(sp) + 8027c6c: df000017 ldw fp,0(sp) + 8027c70: dec00204 addi sp,sp,8 + 8027c74: f800283a ret + +08027c78 : + + + +u_char TK_OSTaskQuery(void) +{ + 8027c78: deffe204 addi sp,sp,-120 + 8027c7c: dfc01d15 stw ra,116(sp) + 8027c80: df001c15 stw fp,112(sp) + 8027c84: df001c04 addi fp,sp,112 + OS_TCB task_data; + INT8U err, task_prio; + + err = OSTaskQuery(OS_PRIO_SELF, &task_data); + 8027c88: e0bfe404 addi r2,fp,-112 + 8027c8c: 100b883a mov r5,r2 + 8027c90: 01003fc4 movi r4,255 + 8027c94: 80172200 call 8017220 + 8027c98: e0bfffc5 stb r2,-1(fp) + + if (err == OS_NO_ERR) + 8027c9c: e0bfffc3 ldbu r2,-1(fp) + 8027ca0: 1000041e bne r2,zero,8027cb4 + { + task_prio = task_data.OSTCBPrio; + 8027ca4: e0bff083 ldbu r2,-62(fp) + 8027ca8: e0bfff85 stb r2,-2(fp) + dprintf("ChronOS API call failure, unable to identify task!"); + panic("TK_OSTaskQuery"); + return 0; + } + + return task_prio; + 8027cac: e0bfff83 ldbu r2,-2(fp) + 8027cb0: 00000706 br 8027cd0 + dprintf("ChronOS API call failure, unable to identify task!"); + 8027cb4: 01020174 movhi r4,2053 + 8027cb8: 2128cd04 addi r4,r4,-23756 + 8027cbc: 8002c780 call 8002c78 + panic("TK_OSTaskQuery"); + 8027cc0: 01020174 movhi r4,2053 + 8027cc4: 2128da04 addi r4,r4,-23704 + 8027cc8: 80271780 call 8027178 + return 0; + 8027ccc: 0005883a mov r2,zero +} + 8027cd0: e037883a mov sp,fp + 8027cd4: dfc00117 ldw ra,4(sp) + 8027cd8: df000017 ldw fp,0(sp) + 8027cdc: dec00204 addi sp,sp,8 + 8027ce0: f800283a ret + +08027ce4 : + + + +void +tk_yield(void) +{ + 8027ce4: defffe04 addi sp,sp,-8 + 8027ce8: dfc00115 stw ra,4(sp) + 8027cec: df000015 stw fp,0(sp) + 8027cf0: d839883a mov fp,sp + /* To ensure cycles to the lower priority tasks we should really + * delay by two ticks, but that really hurts performance on some + * long-tick targets. One tick works better overall.... + */ + OSTimeDly(1); + 8027cf4: 01000044 movi r4,1 + 8027cf8: 801730c0 call 801730c +} + 8027cfc: 0001883a nop + 8027d00: e037883a mov sp,fp + 8027d04: dfc00117 ldw ra,4(sp) + 8027d08: df000017 ldw fp,0(sp) + 8027d0c: dec00204 addi sp,sp,8 + 8027d10: f800283a ret + +08027d14 : +extern struct inet_taskinfo * nettask; +extern int num_net_tasks; + +int +tk_stats(void * pio) +{ + 8027d14: deffef04 addi sp,sp,-68 + 8027d18: dfc01015 stw ra,64(sp) + 8027d1c: df000f15 stw fp,60(sp) + 8027d20: df000f04 addi fp,sp,60 + 8027d24: e13ff215 stw r4,-56(fp) + int stackuse; + char name[OS_TASK_NAME_SIZE+1]; + INT8U err; + + + ns_printf(pio, "ChronOS RTOS stats:\n"); + 8027d28: 01420174 movhi r5,2053 + 8027d2c: 2968de04 addi r5,r5,-23688 + 8027d30: e13ff217 ldw r4,-56(fp) + 8027d34: 80273900 call 8027390 + +#ifdef NO_INICHE_EXTENSIONS + ns_printf(pio, "Context switches; Delay: %lu\n", + 8027d38: d0a04f17 ldw r2,-32452(gp) + 8027d3c: 100d883a mov r6,r2 + 8027d40: 01420174 movhi r5,2053 + 8027d44: 2968e404 addi r5,r5,-23664 + 8027d48: e13ff217 ldw r4,-56(fp) + 8027d4c: 80273900 call 8027390 +#else + ns_printf(pio, "Context switches; Delay: %lu, Interrupt: %lu\n", + OSCtxSwCtr, OSCtxIntCtr); +#endif + + ns_printf(pio, " name prio. state wakeups stack-size stack-use \n"); + 8027d50: 01420174 movhi r5,2053 + 8027d54: 2968ec04 addi r5,r5,-23632 + 8027d58: e13ff217 ldw r4,-56(fp) + 8027d5c: 80273900 call 8027390 + + + for (t = 0; t <= OS_LOWEST_PRIO ; t++) + 8027d60: e03fff15 stw zero,-4(fp) + 8027d64: 00005006 br 8027ea8 + { + /* get pointer to TCB and see if entry is in use and not a mutex */ + tcb = OSTCBPrioTbl[t]; + 8027d68: e0bfff17 ldw r2,-4(fp) + 8027d6c: 100690ba slli r3,r2,2 + 8027d70: 008201b4 movhi r2,2054 + 8027d74: 1885883a add r2,r3,r2 + 8027d78: 10b55d17 ldw r2,-10892(r2) + 8027d7c: e0bffd15 stw r2,-12(fp) + if ((tcb == NULL) || (tcb == (OS_TCB *)1)) + 8027d80: e0bffd17 ldw r2,-12(fp) + 8027d84: 10004426 beq r2,zero,8027e98 + 8027d88: e0bffd17 ldw r2,-12(fp) + 8027d8c: 10800058 cmpnei r2,r2,1 + 8027d90: 10004126 beq r2,zero,8027e98 + continue; + + OSTaskNameGet(tcb->OSTCBPrio, (INT8U *)&name, &err); + 8027d94: e0bffd17 ldw r2,-12(fp) + 8027d98: 10800c83 ldbu r2,50(r2) + 8027d9c: 10803fcc andi r2,r2,255 + 8027da0: e13ff384 addi r4,fp,-50 + 8027da4: e0fff3c4 addi r3,fp,-49 + 8027da8: 200d883a mov r6,r4 + 8027dac: 180b883a mov r5,r3 + 8027db0: 1009883a mov r4,r2 + 8027db4: 8016c2c0 call 8016c2c + +#ifdef NO_INICHE_EXTENSIONS + ns_printf(pio, "%15s %2d 0x%04x, --- ", + name, tcb->OSTCBPrio, tcb->OSTCBStat); + 8027db8: e0bffd17 ldw r2,-12(fp) + 8027dbc: 10800c83 ldbu r2,50(r2) + ns_printf(pio, "%15s %2d 0x%04x, --- ", + 8027dc0: 11003fcc andi r4,r2,255 + name, tcb->OSTCBPrio, tcb->OSTCBStat); + 8027dc4: e0bffd17 ldw r2,-12(fp) + 8027dc8: 10800c03 ldbu r2,48(r2) + ns_printf(pio, "%15s %2d 0x%04x, --- ", + 8027dcc: 10803fcc andi r2,r2,255 + 8027dd0: e0fff3c4 addi r3,fp,-49 + 8027dd4: d8800015 stw r2,0(sp) + 8027dd8: 200f883a mov r7,r4 + 8027ddc: 180d883a mov r6,r3 + 8027de0: 01420174 movhi r5,2053 + 8027de4: 2968fc04 addi r5,r5,-23568 + 8027de8: e13ff217 ldw r4,-56(fp) + 8027dec: 80273900 call 8027390 + /* Find lowest non-zero value in stack so we can estimate the + * unused portion. Subtracting this from size gives us the used + * portion of the stack. + */ +#if OS_TASK_CREATE_EXT_EN > 0 + if(tcb->OSTCBStkBottom && tcb->OSTCBStkSize) + 8027df0: e0bffd17 ldw r2,-12(fp) + 8027df4: 10800217 ldw r2,8(r2) + 8027df8: 10002226 beq r2,zero,8027e84 + 8027dfc: e0bffd17 ldw r2,-12(fp) + 8027e00: 10800317 ldw r2,12(r2) + 8027e04: 10001f26 beq r2,zero,8027e84 + { + sp = tcb->OSTCBStkBottom + 1; + 8027e08: e0bffd17 ldw r2,-12(fp) + 8027e0c: 10800217 ldw r2,8(r2) + 8027e10: 10800104 addi r2,r2,4 + 8027e14: e0bffe15 stw r2,-8(fp) + while(*sp == 0) + 8027e18: 00000306 br 8027e28 + sp++; + 8027e1c: e0bffe17 ldw r2,-8(fp) + 8027e20: 10800104 addi r2,r2,4 + 8027e24: e0bffe15 stw r2,-8(fp) + while(*sp == 0) + 8027e28: e0bffe17 ldw r2,-8(fp) + 8027e2c: 10800017 ldw r2,0(r2) + 8027e30: 103ffa26 beq r2,zero,8027e1c + /* This OS traditionally keeps the size in OS_STK (int) units rather + * than bytes, so convert back to bytes for display. + */ + stackuse = (tcb->OSTCBStkSize - (sp - tcb->OSTCBStkBottom)) * sizeof(OS_STK); + 8027e34: e0bffd17 ldw r2,-12(fp) + 8027e38: 10800317 ldw r2,12(r2) + 8027e3c: e0fffd17 ldw r3,-12(fp) + 8027e40: 18c00217 ldw r3,8(r3) + 8027e44: e13ffe17 ldw r4,-8(fp) + 8027e48: 20c7c83a sub r3,r4,r3 + 8027e4c: 1807d0ba srai r3,r3,2 + 8027e50: 10c5c83a sub r2,r2,r3 + 8027e54: 100490ba slli r2,r2,2 + 8027e58: e0bffc15 stw r2,-16(fp) + ns_printf(pio, "%6d, %6d\n", + tcb->OSTCBStkSize * sizeof(OS_STK), stackuse); + 8027e5c: e0bffd17 ldw r2,-12(fp) + 8027e60: 10800317 ldw r2,12(r2) + ns_printf(pio, "%6d, %6d\n", + 8027e64: 100490ba slli r2,r2,2 + 8027e68: e1fffc17 ldw r7,-16(fp) + 8027e6c: 100d883a mov r6,r2 + 8027e70: 01420174 movhi r5,2053 + 8027e74: 29690404 addi r5,r5,-23536 + 8027e78: e13ff217 ldw r4,-56(fp) + 8027e7c: 80273900 call 8027390 + 8027e80: 00000606 br 8027e9c + } + else +#endif + { + ns_printf(pio, "No stack data\n"); + 8027e84: 01420174 movhi r5,2053 + 8027e88: 29690804 addi r5,r5,-23520 + 8027e8c: e13ff217 ldw r4,-56(fp) + 8027e90: 80273900 call 8027390 + 8027e94: 00000106 br 8027e9c + continue; + 8027e98: 0001883a nop + for (t = 0; t <= OS_LOWEST_PRIO ; t++) + 8027e9c: e0bfff17 ldw r2,-4(fp) + 8027ea0: 10800044 addi r2,r2,1 + 8027ea4: e0bfff15 stw r2,-4(fp) + 8027ea8: e0bfff17 ldw r2,-4(fp) + 8027eac: 10800550 cmplti r2,r2,21 + 8027eb0: 103fad1e bne r2,zero,8027d68 + } + } + + ns_printf(pio, "tcp_sleep_count = %lu, tcp_wakeup_count = %lu\n", + 8027eb4: d0a07817 ldw r2,-32288(gp) + 8027eb8: d0e07917 ldw r3,-32284(gp) + 8027ebc: 180f883a mov r7,r3 + 8027ec0: 100d883a mov r6,r2 + 8027ec4: 01420174 movhi r5,2053 + 8027ec8: 29690c04 addi r5,r5,-23504 + 8027ecc: e13ff217 ldw r4,-56(fp) + 8027ed0: 80273900 call 8027390 + tcp_sleep_count, tcp_wakeup_count); + ns_printf(pio, "global_TCPwakeup_setIndx = %d, tcp_sleep_timeout = %lu\n", + 8027ed4: d0a07c17 ldw r2,-32272(gp) + 8027ed8: d0e07117 ldw r3,-32316(gp) + 8027edc: 180f883a mov r7,r3 + 8027ee0: 100d883a mov r6,r2 + 8027ee4: 01420174 movhi r5,2053 + 8027ee8: 29691804 addi r5,r5,-23456 + 8027eec: e13ff217 ldw r4,-56(fp) + 8027ef0: 80273900 call 8027390 + global_TCPwakeup_setIndx, tcp_sleep_timeout); + + return 0; + 8027ef4: 0005883a mov r2,zero +} + 8027ef8: e037883a mov sp,fp + 8027efc: dfc00117 ldw ra,4(sp) + 8027f00: df000017 ldw fp,0(sp) + 8027f04: dec00204 addi sp,sp,8 + 8027f08: f800283a ret + +08027f0c : +int +icmpEcho(ip_addr host, /* host to ping - 32 bit, network-endian */ + char * data, /* ping data, NULL if don't care */ + unsigned datalen, /* length of data to attach to ping request */ + unshort pingseq) /* ping sequence number */ +{ + 8027f0c: defff504 addi sp,sp,-44 + 8027f10: dfc00a15 stw ra,40(sp) + 8027f14: df000915 stw fp,36(sp) + 8027f18: df000904 addi fp,sp,36 + 8027f1c: e13ffa15 stw r4,-24(fp) + 8027f20: e17ff915 stw r5,-28(fp) + 8027f24: e1bff815 stw r6,-32(fp) + 8027f28: 3805883a mov r2,r7 + 8027f2c: e0bff70d sth r2,-36(fp) + PACKET p; + int ip_err; + struct ping * e; + struct ip * pip; + + LOCK_NET_RESOURCE(FREEQ_RESID); + 8027f30: 01000084 movi r4,2 + 8027f34: 8028f380 call 8028f38 + p = pk_alloc(PINGHDRSLEN + datalen); + 8027f38: e0bff817 ldw r2,-32(fp) + 8027f3c: 10800b04 addi r2,r2,44 + 8027f40: 1009883a mov r4,r2 + 8027f44: 80284340 call 8028434 + 8027f48: e0bffe15 stw r2,-8(fp) + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8027f4c: 01000084 movi r4,2 + 8027f50: 8028ff40 call 8028ff4 + if (!p) + 8027f54: e0bffe17 ldw r2,-8(fp) + 8027f58: 1000081e bne r2,zero,8027f7c + { +#ifdef NPDEBUG + if (NDEBUG & IPTRACE) + 8027f5c: d0a06617 ldw r2,-32360(gp) + 8027f60: 1080800c andi r2,r2,512 + 8027f64: 10000326 beq r2,zero,8027f74 + dprintf("icmp: can't alloc packet\n"); + 8027f68: 01020174 movhi r4,2053 + 8027f6c: 21292d04 addi r4,r4,-23372 + 8027f70: 8002d9c0 call 8002d9c +#endif + return(ENP_NOBUFFER); + 8027f74: 00bffac4 movi r2,-21 + 8027f78: 00008606 br 8028194 + } + + p->nb_prot = p->nb_buff + PINGHDRSLEN; + 8027f7c: e0bffe17 ldw r2,-8(fp) + 8027f80: 10800117 ldw r2,4(r2) + 8027f84: 10c00b04 addi r3,r2,44 + 8027f88: e0bffe17 ldw r2,-8(fp) + 8027f8c: 10c00315 stw r3,12(r2) + p->nb_plen = datalen; + 8027f90: e0bffe17 ldw r2,-8(fp) + 8027f94: e0fff817 ldw r3,-32(fp) + 8027f98: 10c00415 stw r3,16(r2) + p->fhost = host; + 8027f9c: e0bffe17 ldw r2,-8(fp) + 8027fa0: e0fffa17 ldw r3,-24(fp) + 8027fa4: 10c00715 stw r3,28(r2) + + if(host == 0xFFFFFFFF) /* broadcast? */ + 8027fa8: e0bffa17 ldw r2,-24(fp) + 8027fac: 10bfffd8 cmpnei r2,r2,-1 + 8027fb0: 1000041e bne r2,zero,8027fc4 + p->net = nets[0]; /* then use first iface */ + 8027fb4: 008201b4 movhi r2,2054 + 8027fb8: 10f77017 ldw r3,-8768(r2) + 8027fbc: e0bffe17 ldw r2,-8(fp) + 8027fc0: 10c00615 stw r3,24(r2) + + /* copy in data field */ + if (data) + 8027fc4: e0bff917 ldw r2,-28(fp) + 8027fc8: 10000726 beq r2,zero,8027fe8 + { + MEMCPY(p->nb_prot, data, datalen); + 8027fcc: e0bffe17 ldw r2,-8(fp) + 8027fd0: 10800317 ldw r2,12(r2) + 8027fd4: e1bff817 ldw r6,-32(fp) + 8027fd8: e17ff917 ldw r5,-28(fp) + 8027fdc: 1009883a mov r4,r2 + 8027fe0: 80086b80 call 80086b8 + 8027fe4: 00001706 br 8028044 + } + else /* caller didn't specify data */ + { + unsigned donedata; + strcpy(p->nb_prot, pingdata); + 8027fe8: e0bffe17 ldw r2,-8(fp) + 8027fec: 10800317 ldw r2,12(r2) + 8027ff0: d0e01517 ldw r3,-32684(gp) + 8027ff4: 180b883a mov r5,r3 + 8027ff8: 1009883a mov r4,r2 + 8027ffc: 8042f600 call 8042f60 + donedata = (unsigned)strlen(pingdata); + 8028000: d0a01517 ldw r2,-32684(gp) + 8028004: 1009883a mov r4,r2 + 8028008: 8002dac0 call 8002dac + 802800c: e0bfff15 stw r2,-4(fp) + while (donedata < datalen) + 8028010: 00000906 br 8028038 + { + *(p->nb_prot + donedata) = (char)((donedata) & 0x00FF); + 8028014: e0bffe17 ldw r2,-8(fp) + 8028018: 10c00317 ldw r3,12(r2) + 802801c: e0bfff17 ldw r2,-4(fp) + 8028020: 1885883a add r2,r3,r2 + 8028024: e0ffff17 ldw r3,-4(fp) + 8028028: 10c00005 stb r3,0(r2) + donedata++; + 802802c: e0bfff17 ldw r2,-4(fp) + 8028030: 10800044 addi r2,r2,1 + 8028034: e0bfff15 stw r2,-4(fp) + while (donedata < datalen) + 8028038: e0ffff17 ldw r3,-4(fp) + 802803c: e0bff817 ldw r2,-32(fp) + 8028040: 18bff436 bltu r3,r2,8028014 + } + } + + /* adjust packet pointers to icmp ping header */ + p->nb_prot -= sizeof(struct ping); + 8028044: e0bffe17 ldw r2,-8(fp) + 8028048: 10800317 ldw r2,12(r2) + 802804c: 10fffe04 addi r3,r2,-8 + 8028050: e0bffe17 ldw r2,-8(fp) + 8028054: 10c00315 stw r3,12(r2) + p->nb_plen += sizeof(struct ping); + 8028058: e0bffe17 ldw r2,-8(fp) + 802805c: 10800417 ldw r2,16(r2) + 8028060: 10c00204 addi r3,r2,8 + 8028064: e0bffe17 ldw r2,-8(fp) + 8028068: 10c00415 stw r3,16(r2) + + /* fill in icmp ping header */ + e = (struct ping *)p->nb_prot; + 802806c: e0bffe17 ldw r2,-8(fp) + 8028070: 10800317 ldw r2,12(r2) + 8028074: e0bffd15 stw r2,-12(fp) + e->ptype = ECHOREQ; + 8028078: e0bffd17 ldw r2,-12(fp) + 802807c: 00c00204 movi r3,8 + 8028080: 10c00005 stb r3,0(r2) + e->pcode = 0; + 8028084: e0bffd17 ldw r2,-12(fp) + 8028088: 10000045 stb zero,1(r2) + e->pid = 0; + 802808c: e0bffd17 ldw r2,-12(fp) + 8028090: 1000010d sth zero,4(r2) + e->pseq = pingseq; + 8028094: e0bffd17 ldw r2,-12(fp) + 8028098: e0fff70b ldhu r3,-36(fp) + 802809c: 10c0018d sth r3,6(r2) + + /* Calculate the checksum */ + e->pchksum = 0; + 80280a0: e0bffd17 ldw r2,-12(fp) + 80280a4: 1000008d sth zero,2(r2) + if (datalen & 1) /* if data size is odd, pad with a zero */ + 80280a8: e0bff817 ldw r2,-32(fp) + 80280ac: 1080004c andi r2,r2,1 + 80280b0: 10000526 beq r2,zero,80280c8 + *((char*)(e+1) + datalen) = 0; + 80280b4: e0bffd17 ldw r2,-12(fp) + 80280b8: 10c00204 addi r3,r2,8 + 80280bc: e0bff817 ldw r2,-32(fp) + 80280c0: 1885883a add r2,r3,r2 + 80280c4: 10000005 stb zero,0(r2) + + e->pchksum = ~cksum(e, (ICMPSIZE+datalen+1)>>1); + 80280c8: e0bff817 ldw r2,-32(fp) + 80280cc: 10800244 addi r2,r2,9 + 80280d0: 1004d07a srli r2,r2,1 + 80280d4: 100b883a mov r5,r2 + 80280d8: e13ffd17 ldw r4,-12(fp) + 80280dc: 8026d7c0 call 8026d7c + 80280e0: 0084303a nor r2,zero,r2 + 80280e4: 1007883a mov r3,r2 + 80280e8: e0bffd17 ldw r2,-12(fp) + 80280ec: 10c0008d sth r3,2(r2) + + /* need to fill in IP addresses at this layer too */ + pip = (struct ip *)(p->nb_prot - sizeof(struct ip)); + 80280f0: e0bffe17 ldw r2,-8(fp) + 80280f4: 10800317 ldw r2,12(r2) + 80280f8: 10bffb04 addi r2,r2,-20 + 80280fc: e0bffc15 stw r2,-16(fp) + pip->ip_src = ip_mymach(host); + 8028100: e13ffa17 ldw r4,-24(fp) + 8028104: 803b0280 call 803b028 + 8028108: 1007883a mov r3,r2 + 802810c: e0bffc17 ldw r2,-16(fp) + 8028110: 10c00315 stw r3,12(r2) + pip->ip_dest = host; + 8028114: e0bffc17 ldw r2,-16(fp) + 8028118: e0fffa17 ldw r3,-24(fp) + 802811c: 10c00415 stw r3,16(r2) + + LOCK_NET_RESOURCE(NET_RESID); + 8028120: 0009883a mov r4,zero + 8028124: 8028f380 call 8028f38 + ip_err = ip_write(ICMP_PROT, p); /* send down to IP layer */ + 8028128: e17ffe17 ldw r5,-8(fp) + 802812c: 01000044 movi r4,1 + 8028130: 803a9e80 call 803a9e8 + 8028134: e0bffb15 stw r2,-20(fp) + UNLOCK_NET_RESOURCE(NET_RESID); + 8028138: 0009883a mov r4,zero + 802813c: 8028ff40 call 8028ff4 + + /* Errors are negative. A zero means send was OK. a positive number + * usually means we had to ARP. Assume this will work and count a send. + */ + if(ip_err < 0) + 8028140: e0bffb17 ldw r2,-20(fp) + 8028144: 1000080e bge r2,zero,8028168 + { +#ifdef NPDEBUG + if (NDEBUG & NETERR) + 8028148: d0a06617 ldw r2,-32360(gp) + 802814c: 1080020c andi r2,r2,8 + 8028150: 10000326 beq r2,zero,8028160 + dprintf("icmp: can't send echo request\n"); + 8028154: 01020174 movhi r4,2053 + 8028158: 21293404 addi r4,r4,-23344 + 802815c: 8002d9c0 call 8002d9c +#endif + /* rfc 1156 seems to say not to count these. (pg 48) -JB- */ + /* LOCK_NET_RESOURCE(FREEQ_RESID); */ + /* pk_free(p); */ + /* UNLOCK_NET_RESOURCE(FREEQ_RESID); */ + return(ip_err); + 8028160: e0bffb17 ldw r2,-20(fp) + 8028164: 00000b06 br 8028194 + } + /* fall to here if we sent echo request OK */ + icmp_mib.icmpOutMsgs++; + 8028168: 008201b4 movhi r2,2054 + 802816c: 10b94217 ldw r2,-6904(r2) + 8028170: 10c00044 addi r3,r2,1 + 8028174: 008201b4 movhi r2,2054 + 8028178: 10f94215 stw r3,-6904(r2) + icmp_mib.icmpOutEchos++; + 802817c: 008201b4 movhi r2,2054 + 8028180: 10b94917 ldw r2,-6876(r2) + 8028184: 10c00044 addi r3,r2,1 + 8028188: 008201b4 movhi r2,2054 + 802818c: 10f94915 stw r3,-6876(r2) + + return(0); + 8028190: 0005883a mov r2,zero +} + 8028194: e037883a mov sp,fp + 8028198: dfc00117 ldw ra,4(sp) + 802819c: df000017 ldw fp,0(sp) + 80281a0: dec00204 addi sp,sp,8 + 80281a4: f800283a ret + +080281a8 : + * for a PACKET buffer or a data buffer fails, or if there is an inconsistency + * between (bigbufs + lilbufs) and MAXPACKETS) it returns -1. + */ + +int pk_init (void) +{ + 80281a8: defff804 addi sp,sp,-32 + 80281ac: dfc00715 stw ra,28(sp) + 80281b0: df000615 stw fp,24(sp) + 80281b4: df000604 addi fp,sp,24 + PACKET packet; + unsigned i; + unsigned numpkts = bigbufs + lilbufs; + 80281b8: d0e01817 ldw r3,-32672(gp) + 80281bc: d0a01617 ldw r2,-32680(gp) + 80281c0: 1885883a add r2,r3,r2 + 80281c4: e0bffc15 stw r2,-16(fp) + u_char align_req; + +#ifdef ALIGN_BUFS + align_req = ALIGN_BUFS; +#else + align_req = 0; + 80281c8: e03ffbc5 stb zero,-17(fp) +#endif + + for (i = 0; i < numpkts; i++) + 80281cc: e03fff15 stw zero,-4(fp) + 80281d0: 00007806 br 80283b4 + { + packet = (PACKET)NB_ALLOC(sizeof(struct netbuf)); + 80281d4: 01000d04 movi r4,52 + 80281d8: 802982c0 call 802982c + 80281dc: e0bffa15 stw r2,-24(fp) + if (packet == NULL) + 80281e0: e0bffa17 ldw r2,-24(fp) + 80281e4: 10008026 beq r2,zero,80283e8 + goto no_pkt_buf; + +#ifdef NPDEBUG + if (i >= MAXPACKETS) + 80281e8: e0bfff17 ldw r2,-4(fp) + 80281ec: 10800f30 cmpltui r2,r2,60 + 80281f0: 1000051e bne r2,zero,8028208 + { + dprintf("pk_init: bad define\n"); + 80281f4: 01020174 movhi r4,2053 + 80281f8: 21293c04 addi r4,r4,-23312 + 80281fc: 8002d9c0 call 8002d9c + return -1; + 8028200: 00bfffc4 movi r2,-1 + 8028204: 00008606 br 8028420 + } + pktlog[i] = packet; /* save for debugging */ + 8028208: e0bfff17 ldw r2,-4(fp) + 802820c: 100890ba slli r4,r2,2 + 8028210: e0fffa17 ldw r3,-24(fp) + 8028214: 008201b4 movhi r2,2054 + 8028218: 2085883a add r2,r4,r2 + 802821c: 10f79f15 stw r3,-8580(r2) +#endif + + packet->nb_tstamp = 0L; + 8028220: e0bffa17 ldw r2,-24(fp) + 8028224: 10000515 stw zero,20(r2) + + if (i < bigbufs) + 8028228: d0a01817 ldw r2,-32672(gp) + 802822c: e0ffff17 ldw r3,-4(fp) + 8028230: 18802f2e bgeu r3,r2,80282f0 +#ifdef NPDEBUG + { + int j; + + /* for DEBUG compiles, bracket the data area with special chars */ + packet->nb_buff = (char *)BB_ALLOC(bigbufsiz+ALIGN_TYPE+1); + 8028234: d0a01917 ldw r2,-32668(gp) + 8028238: 10800144 addi r2,r2,5 + 802823c: 1009883a mov r4,r2 + 8028240: 80298a00 call 80298a0 + 8028244: 1007883a mov r3,r2 + 8028248: e0bffa17 ldw r2,-24(fp) + 802824c: 10c00115 stw r3,4(r2) + if (!(packet->nb_buff)) + 8028250: e0bffa17 ldw r2,-24(fp) + 8028254: 10800117 ldw r2,4(r2) + 8028258: 10006526 beq r2,zero,80283f0 + goto no_pkt_buf; + + /* Add memory markers for sanity check */ + for(j = 0; j < ALIGN_TYPE; j++) + 802825c: e03ffe15 stw zero,-8(fp) + 8028260: 00000906 br 8028288 + *(packet->nb_buff + j) = 'M'; /* MMs at start of buf */ + 8028264: e0bffa17 ldw r2,-24(fp) + 8028268: 10c00117 ldw r3,4(r2) + 802826c: e0bffe17 ldw r2,-8(fp) + 8028270: 1885883a add r2,r3,r2 + 8028274: 00c01344 movi r3,77 + 8028278: 10c00005 stb r3,0(r2) + for(j = 0; j < ALIGN_TYPE; j++) + 802827c: e0bffe17 ldw r2,-8(fp) + 8028280: 10800044 addi r2,r2,1 + 8028284: e0bffe15 stw r2,-8(fp) + 8028288: e0bffe17 ldw r2,-8(fp) + 802828c: 10800110 cmplti r2,r2,4 + 8028290: 103ff41e bne r2,zero,8028264 + + *(packet->nb_buff + bigbufsiz + ALIGN_TYPE) = 'M'; + 8028294: e0bffa17 ldw r2,-24(fp) + 8028298: 10c00117 ldw r3,4(r2) + 802829c: d0a01917 ldw r2,-32668(gp) + 80282a0: 10800104 addi r2,r2,4 + 80282a4: 1885883a add r2,r3,r2 + 80282a8: 00c01344 movi r3,77 + 80282ac: 10c00005 stb r3,0(r2) + packet->nb_buff += ALIGN_TYPE; /* bump buf past MMs */ + 80282b0: e0bffa17 ldw r2,-24(fp) + 80282b4: 10800117 ldw r2,4(r2) + 80282b8: 10c00104 addi r3,r2,4 + 80282bc: e0bffa17 ldw r2,-24(fp) + 80282c0: 10c00115 stw r3,4(r2) +#ifdef ALIGN_BUFS + /* align start of buffer pointer to desired offset */ + packet->nb_buff += (ALIGN_BUFS - (((u_long) packet->nb_buff) & (ALIGN_BUFS - 1))); +#endif +#endif + if (!(packet->nb_buff)) + 80282c4: e0bffa17 ldw r2,-24(fp) + 80282c8: 10800117 ldw r2,4(r2) + 80282cc: 10004a26 beq r2,zero,80283f8 + goto no_pkt_buf; + packet->nb_blen = bigbufsiz; + 80282d0: d0e01917 ldw r3,-32668(gp) + 80282d4: e0bffa17 ldw r2,-24(fp) + 80282d8: 10c00215 stw r3,8(r2) + q_add(&bigfreeq, packet); /* save it in big pkt free queue */ + 80282dc: e17ffa17 ldw r5,-24(fp) + 80282e0: 010201b4 movhi r4,2054 + 80282e4: 2137db04 addi r4,r4,-8340 + 80282e8: 80289900 call 8028990 + 80282ec: 00002e06 br 80283a8 +#ifdef NPDEBUG + { + int j; + + /* for DEBUG compiles, bracket the data area with special chars */ + packet->nb_buff = (char *)LB_ALLOC(lilbufsiz+ALIGN_TYPE+1); + 80282f0: d0a01717 ldw r2,-32676(gp) + 80282f4: 10800144 addi r2,r2,5 + 80282f8: 1009883a mov r4,r2 + 80282fc: 80298a00 call 80298a0 + 8028300: 1007883a mov r3,r2 + 8028304: e0bffa17 ldw r2,-24(fp) + 8028308: 10c00115 stw r3,4(r2) + if (!(packet->nb_buff)) + 802830c: e0bffa17 ldw r2,-24(fp) + 8028310: 10800117 ldw r2,4(r2) + 8028314: 10003a26 beq r2,zero,8028400 + goto no_pkt_buf; + + /* Add memory markers for sanity check */ + for(j = 0; j < ALIGN_TYPE; j++) + 8028318: e03ffd15 stw zero,-12(fp) + 802831c: 00000906 br 8028344 + *(packet->nb_buff + j) = 'M'; /* MMs at start of buf */ + 8028320: e0bffa17 ldw r2,-24(fp) + 8028324: 10c00117 ldw r3,4(r2) + 8028328: e0bffd17 ldw r2,-12(fp) + 802832c: 1885883a add r2,r3,r2 + 8028330: 00c01344 movi r3,77 + 8028334: 10c00005 stb r3,0(r2) + for(j = 0; j < ALIGN_TYPE; j++) + 8028338: e0bffd17 ldw r2,-12(fp) + 802833c: 10800044 addi r2,r2,1 + 8028340: e0bffd15 stw r2,-12(fp) + 8028344: e0bffd17 ldw r2,-12(fp) + 8028348: 10800110 cmplti r2,r2,4 + 802834c: 103ff41e bne r2,zero,8028320 + + *(packet->nb_buff + lilbufsiz + ALIGN_TYPE) = 'M'; + 8028350: e0bffa17 ldw r2,-24(fp) + 8028354: 10c00117 ldw r3,4(r2) + 8028358: d0a01717 ldw r2,-32676(gp) + 802835c: 10800104 addi r2,r2,4 + 8028360: 1885883a add r2,r3,r2 + 8028364: 00c01344 movi r3,77 + 8028368: 10c00005 stb r3,0(r2) + packet->nb_buff += ALIGN_TYPE; + 802836c: e0bffa17 ldw r2,-24(fp) + 8028370: 10800117 ldw r2,4(r2) + 8028374: 10c00104 addi r3,r2,4 + 8028378: e0bffa17 ldw r2,-24(fp) + 802837c: 10c00115 stw r3,4(r2) +#ifdef ALIGN_BUFS + /* align start of buffer pointer to desired offset */ + packet->nb_buff += (ALIGN_BUFS - (((u_long) packet->nb_buff) & (ALIGN_BUFS - 1))); +#endif +#endif + if (!(packet->nb_buff)) + 8028380: e0bffa17 ldw r2,-24(fp) + 8028384: 10800117 ldw r2,4(r2) + 8028388: 10001f26 beq r2,zero,8028408 + goto no_pkt_buf; + packet->nb_blen = lilbufsiz; + 802838c: d0e01717 ldw r3,-32676(gp) + 8028390: e0bffa17 ldw r2,-24(fp) + 8028394: 10c00215 stw r3,8(r2) + q_add(&lilfreeq, packet); /* save it in little free queue */ + 8028398: e17ffa17 ldw r5,-24(fp) + 802839c: 010201b4 movhi r4,2054 + 80283a0: 21379604 addi r4,r4,-8616 + 80283a4: 80289900 call 8028990 + for (i = 0; i < numpkts; i++) + 80283a8: e0bfff17 ldw r2,-4(fp) + 80283ac: 10800044 addi r2,r2,1 + 80283b0: e0bfff15 stw r2,-4(fp) + 80283b4: e0ffff17 ldw r3,-4(fp) + 80283b8: e0bffc17 ldw r2,-16(fp) + 80283bc: 18bf8536 bltu r3,r2,80281d4 + } + } + bigfreeq.q_min = bigbufs; + 80283c0: d0a01817 ldw r2,-32672(gp) + 80283c4: 1007883a mov r3,r2 + 80283c8: 008201b4 movhi r2,2054 + 80283cc: 10f7df15 stw r3,-8324(r2) + lilfreeq.q_min = lilbufs; + 80283d0: d0a01617 ldw r2,-32680(gp) + 80283d4: 1007883a mov r3,r2 + 80283d8: 008201b4 movhi r2,2054 + 80283dc: 10f79a15 stw r3,-8600(r2) + heap_curr_mem_hi_watermark = 0; + /* set the heap's access type to blocking */ + heap_type = HEAP_ACCESS_BLOCKING; +#endif + + return 0; + 80283e0: 0005883a mov r2,zero + 80283e4: 00000e06 br 8028420 + goto no_pkt_buf; + 80283e8: 0001883a nop + 80283ec: 00000706 br 802840c + goto no_pkt_buf; + 80283f0: 0001883a nop + 80283f4: 00000506 br 802840c + goto no_pkt_buf; + 80283f8: 0001883a nop + 80283fc: 00000306 br 802840c + goto no_pkt_buf; + 8028400: 0001883a nop + 8028404: 00000106 br 802840c + goto no_pkt_buf; + 8028408: 0001883a nop + +no_pkt_buf: +#ifdef NPDEBUG + dprintf("Netinit: calloc failed getting buffer %d\n", i); + 802840c: e17fff17 ldw r5,-4(fp) + 8028410: 01020174 movhi r4,2053 + 8028414: 21294104 addi r4,r4,-23292 + 8028418: 8002c780 call 8002c78 +#endif + return(-1); + 802841c: 00bfffc4 movi r2,-1 +} + 8028420: e037883a mov sp,fp + 8028424: dfc00117 ldw ra,4(sp) + 8028428: df000017 ldw fp,0(sp) + 802842c: dec00204 addi sp,sp,8 + 8028430: f800283a ret + +08028434 : + * OUTPUT: 0 if the request cannot be satisfied, or a pointer to the struct + * netbuf structure that corresponds to the just allocated data buffer. + */ + +PACKET pk_alloc(unsigned len) +{ + 8028434: defffc04 addi sp,sp,-16 + 8028438: dfc00315 stw ra,12(sp) + 802843c: df000215 stw fp,8(sp) + 8028440: df000204 addi fp,sp,8 + 8028444: e13ffe15 stw r4,-8(fp) + PACKET p; + + if (len > bigbufsiz) /* caller wants oversize buffer? */ + 8028448: d0e01917 ldw r3,-32668(gp) + 802844c: e0bffe17 ldw r2,-8(fp) + 8028450: 1880022e bgeu r3,r2,802845c + { +#ifdef HEAPBUFS + if ((p = pk_alloc_heapbuf (len)) == NULL) + return NULL; +#else + return(NULL); + 8028454: 0005883a mov r2,zero + 8028458: 00002106 br 80284e0 +#endif + } + else + { + if ((len > lilbufsiz) || (lilfreeq.q_len == 0)) /* must use a big buffer */ + 802845c: d0e01717 ldw r3,-32676(gp) + 8028460: e0bffe17 ldw r2,-8(fp) + 8028464: 18800336 bltu r3,r2,8028474 + 8028468: 008201b4 movhi r2,2054 + 802846c: 10b79817 ldw r2,-8608(r2) + 8028470: 1000051e bne r2,zero,8028488 + p = (PACKET)getq(&bigfreeq); + 8028474: 010201b4 movhi r4,2054 + 8028478: 2137db04 addi r4,r4,-8340 + 802847c: 80288d80 call 80288d8 + 8028480: e0bfff15 stw r2,-4(fp) + 8028484: 00000406 br 8028498 + else + p = (PACKET)getq(&lilfreeq); + 8028488: 010201b4 movhi r4,2054 + 802848c: 21379604 addi r4,r4,-8616 + 8028490: 80288d80 call 80288d8 + 8028494: e0bfff15 stw r2,-4(fp) + + if (!p) + 8028498: e0bfff17 ldw r2,-4(fp) + 802849c: 1000021e bne r2,zero,80284a8 + return NULL; + 80284a0: 0005883a mov r2,zero + 80284a4: 00000e06 br 80284e0 + } + + p->nb_prot = p->nb_buff + MaxLnh; /* point past biggest mac header */ + 80284a8: e0bfff17 ldw r2,-4(fp) + 80284ac: 10800117 ldw r2,4(r2) + 80284b0: d0e06417 ldw r3,-32368(gp) + 80284b4: 10c7883a add r3,r2,r3 + 80284b8: e0bfff17 ldw r2,-4(fp) + 80284bc: 10c00315 stw r3,12(r2) + p->nb_plen = 0; /* no protocol data there yet */ + 80284c0: e0bfff17 ldw r2,-4(fp) + 80284c4: 10000415 stw zero,16(r2) + p->net = NULL; + 80284c8: e0bfff17 ldw r2,-4(fp) + 80284cc: 10000615 stw zero,24(r2) + p->nexthop = NULL; /* no next hop */ + p->nb_pmtu = 1240; /* Set minimum IPv6 Path MTU */ +#endif /* IP_V6 */ +#endif /* LINKED_PKTS */ + + p->inuse = 1; /* initially buffer in use by 1 user */ + 80284d0: e0bfff17 ldw r2,-4(fp) + 80284d4: 00c00044 movi r3,1 + 80284d8: 10c00915 stw r3,36(r2) + + /* note that 'type' and 'fhost' fields are not set in pk_alloc () */ + return(p); + 80284dc: e0bfff17 ldw r2,-4(fp) +} + 80284e0: e037883a mov sp,fp + 80284e4: dfc00117 ldw ra,4(sp) + 80284e8: df000017 ldw fp,0(sp) + 80284ec: dec00204 addi sp,sp,8 + 80284f0: f800283a ret + +080284f4 : + * OUTPUT: 0 if the buffer being freed was successfully validated, or + * -1 if the validation failed. + */ + +int pk_validate(PACKET pkt) /* check if pk_free() can free the pkt */ +{ + 80284f4: defffb04 addi sp,sp,-20 + 80284f8: dfc00415 stw ra,16(sp) + 80284fc: df000315 stw fp,12(sp) + 8028500: df000304 addi fp,sp,12 + 8028504: e13ffd15 stw r4,-12(fp) + /* If packet link is non-zero, then this packet is + * part of a chain and deleted this packet would break + * the chain and cause memory leak for subsequent pkts. + * Note that heapbufs do not use the 'next' field at all. + */ + if ((pkt->next) && (pkt->inuse >= 1)) + 8028508: e0bffd17 ldw r2,-12(fp) + 802850c: 10800017 ldw r2,0(r2) + 8028510: 10000c26 beq r2,zero,8028544 + 8028514: e0bffd17 ldw r2,-12(fp) + 8028518: 10800917 ldw r2,36(r2) + 802851c: 10000926 beq r2,zero,8028544 + { + INCR_SHARED_VAR (memestats, INCONSISTENT_LOCATION_ERR, 1); + 8028520: 8028e940 call 8028e94 + 8028524: 008201b4 movhi r2,2054 + 8028528: 10b79e17 ldw r2,-8584(r2) + 802852c: 10c00044 addi r3,r2,1 + 8028530: 008201b4 movhi r2,2054 + 8028534: 10f79e15 stw r3,-8584(r2) + 8028538: 8028ef40 call 8028ef4 + return -1; + 802853c: 00bfffc4 movi r2,-1 + 8028540: 00007c06 br 8028734 + } + else +#endif /* HEAPBUFS */ + { + /* check if the packet is already in a freeq */ + if (pkt->nb_blen == bigbufsiz) /* check in bigfreeq */ + 8028544: e0bffd17 ldw r2,-12(fp) + 8028548: 10c00217 ldw r3,8(r2) + 802854c: d0a01917 ldw r2,-32668(gp) + 8028550: 18801d1e bne r3,r2,80285c8 + { + ENTER_CRIT_SECTION(&bigfreeq); + 8028554: 8028e940 call 8028e94 + for (p=(PACKET)bigfreeq.q_head; p; p = p->next) + 8028558: 008201b4 movhi r2,2054 + 802855c: 10b7db17 ldw r2,-8340(r2) + 8028560: e0bfff15 stw r2,-4(fp) + 8028564: 00001406 br 80285b8 + if (p == pkt) + 8028568: e0ffff17 ldw r3,-4(fp) + 802856c: e0bffd17 ldw r2,-12(fp) + 8028570: 18800e1e bne r3,r2,80285ac + { + dprintf("pk_free: buffer %p already in bigfreeq\n", pkt); + 8028574: e17ffd17 ldw r5,-12(fp) + 8028578: 01020174 movhi r4,2053 + 802857c: 21294c04 addi r4,r4,-23248 + 8028580: 8002c780 call 8002c78 + EXIT_CRIT_SECTION(&bigfreeq); + 8028584: 8028ef40 call 8028ef4 + INCR_SHARED_VAR (memestats, MULTIPLE_FREE_ERR, 1); + 8028588: 8028e940 call 8028e94 + 802858c: 008201b4 movhi r2,2054 + 8028590: 10b79d17 ldw r2,-8588(r2) + 8028594: 10c00044 addi r3,r2,1 + 8028598: 008201b4 movhi r2,2054 + 802859c: 10f79d15 stw r3,-8588(r2) + 80285a0: 8028ef40 call 8028ef4 + return -1; + 80285a4: 00bfffc4 movi r2,-1 + 80285a8: 00006206 br 8028734 + for (p=(PACKET)bigfreeq.q_head; p; p = p->next) + 80285ac: e0bfff17 ldw r2,-4(fp) + 80285b0: 10800017 ldw r2,0(r2) + 80285b4: e0bfff15 stw r2,-4(fp) + 80285b8: e0bfff17 ldw r2,-4(fp) + 80285bc: 103fea1e bne r2,zero,8028568 + } + EXIT_CRIT_SECTION(&bigfreeq); + 80285c0: 8028ef40 call 8028ef4 + 80285c4: 00002a06 br 8028670 + } + else if (pkt->nb_blen == lilbufsiz) /* check in lilfreeq */ + 80285c8: e0bffd17 ldw r2,-12(fp) + 80285cc: 10c00217 ldw r3,8(r2) + 80285d0: d0a01717 ldw r2,-32676(gp) + 80285d4: 18801d1e bne r3,r2,802864c + { + ENTER_CRIT_SECTION(&lilfreeq); + 80285d8: 8028e940 call 8028e94 + for (p=(PACKET)lilfreeq.q_head; p; p = p->next) + 80285dc: 008201b4 movhi r2,2054 + 80285e0: 10b79617 ldw r2,-8616(r2) + 80285e4: e0bfff15 stw r2,-4(fp) + 80285e8: 00001406 br 802863c + if (p == pkt) + 80285ec: e0ffff17 ldw r3,-4(fp) + 80285f0: e0bffd17 ldw r2,-12(fp) + 80285f4: 18800e1e bne r3,r2,8028630 + { + dprintf("pk_free: buffer %p already in lilfreeq\n", pkt); + 80285f8: e17ffd17 ldw r5,-12(fp) + 80285fc: 01020174 movhi r4,2053 + 8028600: 21295604 addi r4,r4,-23208 + 8028604: 8002c780 call 8002c78 + EXIT_CRIT_SECTION(&lilfreeq); + 8028608: 8028ef40 call 8028ef4 + INCR_SHARED_VAR (memestats, MULTIPLE_FREE_ERR, 1); + 802860c: 8028e940 call 8028e94 + 8028610: 008201b4 movhi r2,2054 + 8028614: 10b79d17 ldw r2,-8588(r2) + 8028618: 10c00044 addi r3,r2,1 + 802861c: 008201b4 movhi r2,2054 + 8028620: 10f79d15 stw r3,-8588(r2) + 8028624: 8028ef40 call 8028ef4 + return -1; + 8028628: 00bfffc4 movi r2,-1 + 802862c: 00004106 br 8028734 + for (p=(PACKET)lilfreeq.q_head; p; p = p->next) + 8028630: e0bfff17 ldw r2,-4(fp) + 8028634: 10800017 ldw r2,0(r2) + 8028638: e0bfff15 stw r2,-4(fp) + 802863c: e0bfff17 ldw r2,-4(fp) + 8028640: 103fea1e bne r2,zero,80285ec + } + EXIT_CRIT_SECTION(&lilfreeq); + 8028644: 8028ef40 call 8028ef4 + 8028648: 00000906 br 8028670 + } + else + { + /* log an error */ + INCR_SHARED_VAR (memestats, BAD_REGULAR_BUF_LEN_ERR, 1); + 802864c: 8028e940 call 8028e94 + 8028650: 008201b4 movhi r2,2054 + 8028654: 10b79b17 ldw r2,-8596(r2) + 8028658: 10c00044 addi r3,r2,1 + 802865c: 008201b4 movhi r2,2054 + 8028660: 10f79b15 stw r3,-8596(r2) + 8028664: 8028ef40 call 8028ef4 + return -1; + 8028668: 00bfffc4 movi r2,-1 + 802866c: 00003106 br 8028734 + } + +#ifdef NPDEBUG + /* check for corruption of memory markers (the guard bands are only + * present when NPDEBUG is defined) */ + for (j = ALIGN_TYPE; j > 0; j--) + 8028670: 00800104 movi r2,4 + 8028674: e0bffe15 stw r2,-8(fp) + 8028678: 00001706 br 80286d8 + { + if (*(pkt->nb_buff - j) != 'M') + 802867c: e0bffd17 ldw r2,-12(fp) + 8028680: 10c00117 ldw r3,4(r2) + 8028684: e0bffe17 ldw r2,-8(fp) + 8028688: 0085c83a sub r2,zero,r2 + 802868c: 1885883a add r2,r3,r2 + 8028690: 10800003 ldbu r2,0(r2) + 8028694: 10803fcc andi r2,r2,255 + 8028698: 1080201c xori r2,r2,128 + 802869c: 10bfe004 addi r2,r2,-128 + 80286a0: 10801360 cmpeqi r2,r2,77 + 80286a4: 1000091e bne r2,zero,80286cc + { + INCR_SHARED_VAR (memestats, GUARD_BAND_VIOLATED_ERR, 1); + 80286a8: 8028e940 call 8028e94 + 80286ac: 008201b4 movhi r2,2054 + 80286b0: 10b79c17 ldw r2,-8592(r2) + 80286b4: 10c00044 addi r3,r2,1 + 80286b8: 008201b4 movhi r2,2054 + 80286bc: 10f79c15 stw r3,-8592(r2) + 80286c0: 8028ef40 call 8028ef4 + return -1; + 80286c4: 00bfffc4 movi r2,-1 + 80286c8: 00001a06 br 8028734 + for (j = ALIGN_TYPE; j > 0; j--) + 80286cc: e0bffe17 ldw r2,-8(fp) + 80286d0: 10bfffc4 addi r2,r2,-1 + 80286d4: e0bffe15 stw r2,-8(fp) + 80286d8: e0bffe17 ldw r2,-8(fp) + 80286dc: 00bfe716 blt zero,r2,802867c + } + } + if (*(pkt->nb_buff + pkt->nb_blen) != 'M') + 80286e0: e0bffd17 ldw r2,-12(fp) + 80286e4: 10c00117 ldw r3,4(r2) + 80286e8: e0bffd17 ldw r2,-12(fp) + 80286ec: 10800217 ldw r2,8(r2) + 80286f0: 1885883a add r2,r3,r2 + 80286f4: 10800003 ldbu r2,0(r2) + 80286f8: 10803fcc andi r2,r2,255 + 80286fc: 1080201c xori r2,r2,128 + 8028700: 10bfe004 addi r2,r2,-128 + 8028704: 10801360 cmpeqi r2,r2,77 + 8028708: 1000091e bne r2,zero,8028730 + { + INCR_SHARED_VAR (memestats, GUARD_BAND_VIOLATED_ERR, 1); + 802870c: 8028e940 call 8028e94 + 8028710: 008201b4 movhi r2,2054 + 8028714: 10b79c17 ldw r2,-8592(r2) + 8028718: 10c00044 addi r3,r2,1 + 802871c: 008201b4 movhi r2,2054 + 8028720: 10f79c15 stw r3,-8592(r2) + 8028724: 8028ef40 call 8028ef4 + return -1; + 8028728: 00bfffc4 movi r2,-1 + 802872c: 00000106 br 8028734 + } +#endif /* NPDEBUG */ + + return 0; + 8028730: 0005883a mov r2,zero +} + 8028734: e037883a mov sp,fp + 8028738: dfc00117 ldw ra,4(sp) + 802873c: df000017 ldw fp,0(sp) + 8028740: dec00204 addi sp,sp,8 + 8028744: f800283a ret + +08028748 : + * + * OUTPUT: None. + */ + +void pk_free(PACKET pkt) /* PACKET to place in free queue */ +{ + 8028748: defffc04 addi sp,sp,-16 + 802874c: dfc00315 stw ra,12(sp) + 8028750: df000215 stw fp,8(sp) + 8028754: df000204 addi fp,sp,8 + 8028758: e13ffe15 stw r4,-8(fp) + PACKET pknext; + pknext = pkt->pk_next; +#endif /* LINKED_PKTS */ + + /* validate the pkt before freeing */ + e = pk_validate(pkt); + 802875c: e13ffe17 ldw r4,-8(fp) + 8028760: 80284f40 call 80284f4 + 8028764: e0bfff15 stw r2,-4(fp) + if (e) + 8028768: e0bfff17 ldw r2,-4(fp) + 802876c: 1000191e bne r2,zero,80287d4 + continue; /* skip this pkt, examine the next pkt */ + } +#endif + return; + } + if (pkt->inuse-- > 1) /* more than 1 owner? */ + 8028770: e0bffe17 ldw r2,-8(fp) + 8028774: 10800917 ldw r2,36(r2) + 8028778: 113fffc4 addi r4,r2,-1 + 802877c: e0fffe17 ldw r3,-8(fp) + 8028780: 19000915 stw r4,36(r3) + 8028784: 108000b0 cmpltui r2,r2,2 + 8028788: 10001426 beq r2,zero,80287dc + pk_free_heapbuf (pkt); + } + else +#endif /* HEAPBUFS */ + { + if (pkt->nb_blen == bigbufsiz) + 802878c: e0bffe17 ldw r2,-8(fp) + 8028790: 10c00217 ldw r3,8(r2) + 8028794: d0a01917 ldw r2,-32668(gp) + 8028798: 1880051e bne r3,r2,80287b0 + q_add(&bigfreeq, (qp)pkt); + 802879c: e17ffe17 ldw r5,-8(fp) + 80287a0: 010201b4 movhi r4,2054 + 80287a4: 2137db04 addi r4,r4,-8340 + 80287a8: 80289900 call 8028990 + 80287ac: 00000c06 br 80287e0 + else if (pkt->nb_blen == lilbufsiz) + 80287b0: e0bffe17 ldw r2,-8(fp) + 80287b4: 10c00217 ldw r3,8(r2) + 80287b8: d0a01717 ldw r2,-32676(gp) + 80287bc: 1880081e bne r3,r2,80287e0 + q_add(&lilfreeq, (qp)pkt); + 80287c0: e17ffe17 ldw r5,-8(fp) + 80287c4: 010201b4 movhi r4,2054 + 80287c8: 21379604 addi r4,r4,-8616 + 80287cc: 80289900 call 8028990 + 80287d0: 00000306 br 80287e0 + return; + 80287d4: 0001883a nop + 80287d8: 00000106 br 80287e0 + return; /* packet was cloned, don't delete yet */ + 80287dc: 0001883a nop +#ifdef LINKED_PKTS + pkt = pknext; + } +#endif + +} + 80287e0: e037883a mov sp,fp + 80287e4: dfc00117 ldw ra,4(sp) + 80287e8: df000017 ldw fp,0(sp) + 80287ec: dec00204 addi sp,sp,8 + 80287f0: f800283a ret + +080287f4 : + * + * OUTPUT: This function always returns the length of a big buffer (bigbufsiz). + */ + +unsigned pk_get_max_intrsafe_buf_len(void) +{ + 80287f4: deffff04 addi sp,sp,-4 + 80287f8: df000015 stw fp,0(sp) + 80287fc: d839883a mov fp,sp + return bigbufsiz; + 8028800: d0a01917 ldw r2,-32668(gp) +} + 8028804: e037883a mov sp,fp + 8028808: df000017 ldw fp,0(sp) + 802880c: dec00104 addi sp,sp,4 + 8028810: f800283a ret + +08028814 : + * + * OUTPUT: This function always returns 0. + */ + +int dump_buf_estats (void * pio) +{ + 8028814: defff904 addi sp,sp,-28 + 8028818: dfc00615 stw ra,24(sp) + 802881c: df000515 stw fp,20(sp) + 8028820: df000504 addi fp,sp,20 + 8028824: e13ffb15 stw r4,-20(fp) + u_long mlocal [MEMERR_NUM_STATS]; + + LOCK_NET_RESOURCE(FREEQ_RESID); + 8028828: 01000084 movi r4,2 + 802882c: 8028f380 call 8028f38 + ENTER_CRIT_SECTION(&memestats); + 8028830: 8028e940 call 8028e94 + MEMCPY (&mlocal, &memestats, sizeof(memestats)); + 8028834: 008201b4 movhi r2,2054 + 8028838: 10b79b17 ldw r2,-8596(r2) + 802883c: e0bffc15 stw r2,-16(fp) + 8028840: 008201b4 movhi r2,2054 + 8028844: 10b79c17 ldw r2,-8592(r2) + 8028848: e0bffd15 stw r2,-12(fp) + 802884c: 008201b4 movhi r2,2054 + 8028850: 10b79d17 ldw r2,-8588(r2) + 8028854: e0bffe15 stw r2,-8(fp) + 8028858: 008201b4 movhi r2,2054 + 802885c: 10b79e17 ldw r2,-8584(r2) + 8028860: e0bfff15 stw r2,-4(fp) + EXIT_CRIT_SECTION(&memestats); + 8028864: 8028ef40 call 8028ef4 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8028868: 01000084 movi r4,2 + 802886c: 8028ff40 call 8028ff4 + + ns_printf(pio, "Regular buffer error statistics:\n"); + 8028870: 01420174 movhi r5,2053 + 8028874: 29696004 addi r5,r5,-23168 + 8028878: e13ffb17 ldw r4,-20(fp) + 802887c: 80273900 call 8027390 + ns_printf(pio, "Bad buffer length %lu, Guard band violations %lu\n",mlocal[BAD_REGULAR_BUF_LEN_ERR],mlocal[GUARD_BAND_VIOLATED_ERR]); + 8028880: e0bffc17 ldw r2,-16(fp) + 8028884: e0fffd17 ldw r3,-12(fp) + 8028888: 180f883a mov r7,r3 + 802888c: 100d883a mov r6,r2 + 8028890: 01420174 movhi r5,2053 + 8028894: 29696904 addi r5,r5,-23132 + 8028898: e13ffb17 ldw r4,-20(fp) + 802889c: 80273900 call 8027390 + ns_printf(pio, "Multiple frees %lu, Inconsistent location %lu\n",mlocal[MULTIPLE_FREE_ERR],mlocal[INCONSISTENT_LOCATION_ERR]); + 80288a0: e0bffe17 ldw r2,-8(fp) + 80288a4: e0ffff17 ldw r3,-4(fp) + 80288a8: 180f883a mov r7,r3 + 80288ac: 100d883a mov r6,r2 + 80288b0: 01420174 movhi r5,2053 + 80288b4: 29697604 addi r5,r5,-23080 + 80288b8: e13ffb17 ldw r4,-20(fp) + 80288bc: 80273900 call 8027390 + + return 0; + 80288c0: 0005883a mov r2,zero +} + 80288c4: e037883a mov sp,fp + 80288c8: dfc00117 ldw ra,4(sp) + 80288cc: df000017 ldw fp,0(sp) + 80288d0: dec00204 addi sp,sp,8 + 80288d4: f800283a ret + +080288d8 : + * RETURNS: pointer to the first element if any, or 0 if the queue is empty. + */ + +void* +getq(queue * q) +{ + 80288d8: defffc04 addi sp,sp,-16 + 80288dc: dfc00315 stw ra,12(sp) + 80288e0: df000215 stw fp,8(sp) + 80288e4: df000204 addi fp,sp,8 + 80288e8: e13ffe15 stw r4,-8(fp) + q_elt temp; /* temp for result */ + + + ENTER_CRIT_SECTION(q); /* shut off ints, save old state */ + 80288ec: 8028e940 call 8028e94 + + LOCKNET_CHECK(q); /* make sure queue is protected */ + + if ((temp = q->q_head) == 0) /* queue empty? */ + 80288f0: e0bffe17 ldw r2,-8(fp) + 80288f4: 10800017 ldw r2,0(r2) + 80288f8: e0bfff15 stw r2,-4(fp) + 80288fc: e0bfff17 ldw r2,-4(fp) + 8028900: 1000031e bne r2,zero,8028910 + { + EXIT_CRIT_SECTION(q); + 8028904: 8028ef40 call 8028ef4 + return (0); /* yes, show none */ + 8028908: 0005883a mov r2,zero + 802890c: 00001b06 br 802897c + } + + q->q_head = temp->qe_next; /* else unlink */ + 8028910: e0bfff17 ldw r2,-4(fp) + 8028914: 10c00017 ldw r3,0(r2) + 8028918: e0bffe17 ldw r2,-8(fp) + 802891c: 10c00015 stw r3,0(r2) + temp->qe_next = 0; /* avoid dangling pointers */ + 8028920: e0bfff17 ldw r2,-4(fp) + 8028924: 10000015 stw zero,0(r2) + if (q->q_head == 0) /* queue empty? */ + 8028928: e0bffe17 ldw r2,-8(fp) + 802892c: 10800017 ldw r2,0(r2) + 8028930: 1000021e bne r2,zero,802893c + q->q_tail = 0; /* yes, update tail pointer too */ + 8028934: e0bffe17 ldw r2,-8(fp) + 8028938: 10000115 stw zero,4(r2) + q->q_len--; /* update queue length */ + 802893c: e0bffe17 ldw r2,-8(fp) + 8028940: 10800217 ldw r2,8(r2) + 8028944: 10ffffc4 addi r3,r2,-1 + 8028948: e0bffe17 ldw r2,-8(fp) + 802894c: 10c00215 stw r3,8(r2) + if (q->q_len < q->q_min) + 8028950: e0bffe17 ldw r2,-8(fp) + 8028954: 10c00217 ldw r3,8(r2) + 8028958: e0bffe17 ldw r2,-8(fp) + 802895c: 10800417 ldw r2,16(r2) + 8028960: 1880040e bge r3,r2,8028974 + q->q_min = q->q_len; + 8028964: e0bffe17 ldw r2,-8(fp) + 8028968: 10c00217 ldw r3,8(r2) + 802896c: e0bffe17 ldw r2,-8(fp) + 8028970: 10c00415 stw r3,16(r2) + + QUEUE_CHECK(q); /* make sure queue is not corrupted */ + + EXIT_CRIT_SECTION(q); /* restore caller's int state */ + 8028974: 8028ef40 call 8028ef4 + + return ((void*)temp); + 8028978: e0bfff17 ldw r2,-4(fp) +} + 802897c: e037883a mov sp,fp + 8028980: dfc00117 ldw ra,4(sp) + 8028984: df000017 ldw fp,0(sp) + 8028988: dec00204 addi sp,sp,8 + 802898c: f800283a ret + +08028990 : + +void +putq( + queue * q, /* the queue */ + void * elt) /* element to delete */ +{ + 8028990: defffc04 addi sp,sp,-16 + 8028994: dfc00315 stw ra,12(sp) + 8028998: df000215 stw fp,8(sp) + 802899c: df000204 addi fp,sp,8 + 80289a0: e13fff15 stw r4,-4(fp) + 80289a4: e17ffe15 stw r5,-8(fp) + ENTER_CRIT_SECTION(q); + 80289a8: 8028e940 call 8028e94 + LOCKNET_CHECK(q); /* make sure queue is protected */ + q_addt(q, (qp)elt); /* use macro to do work */ + 80289ac: e0bffe17 ldw r2,-8(fp) + 80289b0: 10000015 stw zero,0(r2) + 80289b4: e0bfff17 ldw r2,-4(fp) + 80289b8: 10800017 ldw r2,0(r2) + 80289bc: 1000041e bne r2,zero,80289d0 + 80289c0: e0bfff17 ldw r2,-4(fp) + 80289c4: e0fffe17 ldw r3,-8(fp) + 80289c8: 10c00015 stw r3,0(r2) + 80289cc: 00000406 br 80289e0 + 80289d0: e0bfff17 ldw r2,-4(fp) + 80289d4: 10800117 ldw r2,4(r2) + 80289d8: e0fffe17 ldw r3,-8(fp) + 80289dc: 10c00015 stw r3,0(r2) + 80289e0: e0bfff17 ldw r2,-4(fp) + 80289e4: e0fffe17 ldw r3,-8(fp) + 80289e8: 10c00115 stw r3,4(r2) + 80289ec: e0bfff17 ldw r2,-4(fp) + 80289f0: 10800217 ldw r2,8(r2) + 80289f4: 10c00044 addi r3,r2,1 + 80289f8: e0bfff17 ldw r2,-4(fp) + 80289fc: 10c00215 stw r3,8(r2) + 8028a00: e0bfff17 ldw r2,-4(fp) + 8028a04: 10800217 ldw r2,8(r2) + 8028a08: e0ffff17 ldw r3,-4(fp) + 8028a0c: 18c00317 ldw r3,12(r3) + 8028a10: 1880040e bge r3,r2,8028a24 + 8028a14: e0bfff17 ldw r2,-4(fp) + 8028a18: 10c00217 ldw r3,8(r2) + 8028a1c: e0bfff17 ldw r2,-4(fp) + 8028a20: 10c00315 stw r3,12(r2) + QUEUE_CHECK(q); /* make sure queue is not corrupted */ + EXIT_CRIT_SECTION(q); /* restore int state */ + 8028a24: 8028ef40 call 8028ef4 +} + 8028a28: 0001883a nop + 8028a2c: e037883a mov sp,fp + 8028a30: dfc00117 ldw ra,4(sp) + 8028a34: df000017 ldw fp,0(sp) + 8028a38: dec00204 addi sp,sp,8 + 8028a3c: f800283a ret + +08028a40 : + * RETURNS: Return pointer to queue member if found, else NULL. + */ + +qp +qdel(queue * q, void * elt) +{ + 8028a40: defffa04 addi sp,sp,-24 + 8028a44: dfc00515 stw ra,20(sp) + 8028a48: df000415 stw fp,16(sp) + 8028a4c: df000404 addi fp,sp,16 + 8028a50: e13ffd15 stw r4,-12(fp) + 8028a54: e17ffc15 stw r5,-16(fp) + qp qptr; + qp qlast; + + /* search queue for element passed */ + ENTER_CRIT_SECTION(q); + 8028a58: 8028e940 call 8028e94 + qptr = q->q_head; + 8028a5c: e0bffd17 ldw r2,-12(fp) + 8028a60: 10800017 ldw r2,0(r2) + 8028a64: e0bfff15 stw r2,-4(fp) + qlast = NULL; + 8028a68: e03ffe15 stw zero,-8(fp) + while (qptr) + 8028a6c: 00002b06 br 8028b1c + { + if (qptr == (qp)elt) + 8028a70: e0ffff17 ldw r3,-4(fp) + 8028a74: e0bffc17 ldw r2,-16(fp) + 8028a78: 1880231e bne r3,r2,8028b08 + { + /* found our item; dequeue it */ + if (qlast) + 8028a7c: e0bffe17 ldw r2,-8(fp) + 8028a80: 10000526 beq r2,zero,8028a98 + qlast->qe_next = qptr->qe_next; + 8028a84: e0bfff17 ldw r2,-4(fp) + 8028a88: 10c00017 ldw r3,0(r2) + 8028a8c: e0bffe17 ldw r2,-8(fp) + 8028a90: 10c00015 stw r3,0(r2) + 8028a94: 00000406 br 8028aa8 + else /* item was at head of queqe */ + q->q_head = qptr->qe_next; + 8028a98: e0bfff17 ldw r2,-4(fp) + 8028a9c: 10c00017 ldw r3,0(r2) + 8028aa0: e0bffd17 ldw r2,-12(fp) + 8028aa4: 10c00015 stw r3,0(r2) + + /* fix queue tail pointer if needed */ + if (q->q_tail == (qp)elt) + 8028aa8: e0bffd17 ldw r2,-12(fp) + 8028aac: 10800117 ldw r2,4(r2) + 8028ab0: e0fffc17 ldw r3,-16(fp) + 8028ab4: 1880031e bne r3,r2,8028ac4 + q->q_tail = qlast; + 8028ab8: e0bffd17 ldw r2,-12(fp) + 8028abc: e0fffe17 ldw r3,-8(fp) + 8028ac0: 10c00115 stw r3,4(r2) + + /* fix queue counters */ + q->q_len--; + 8028ac4: e0bffd17 ldw r2,-12(fp) + 8028ac8: 10800217 ldw r2,8(r2) + 8028acc: 10ffffc4 addi r3,r2,-1 + 8028ad0: e0bffd17 ldw r2,-12(fp) + 8028ad4: 10c00215 stw r3,8(r2) + if (q->q_len < q->q_min) + 8028ad8: e0bffd17 ldw r2,-12(fp) + 8028adc: 10c00217 ldw r3,8(r2) + 8028ae0: e0bffd17 ldw r2,-12(fp) + 8028ae4: 10800417 ldw r2,16(r2) + 8028ae8: 1880040e bge r3,r2,8028afc + q->q_min = q->q_len; + 8028aec: e0bffd17 ldw r2,-12(fp) + 8028af0: 10c00217 ldw r3,8(r2) + 8028af4: e0bffd17 ldw r2,-12(fp) + 8028af8: 10c00415 stw r3,16(r2) + EXIT_CRIT_SECTION(q); /* restore int state */ + 8028afc: 8028ef40 call 8028ef4 + return (qp)elt; /* success exit point */ + 8028b00: e0bffc17 ldw r2,-16(fp) + 8028b04: 00000906 br 8028b2c + } + qlast = qptr; + 8028b08: e0bfff17 ldw r2,-4(fp) + 8028b0c: e0bffe15 stw r2,-8(fp) + qptr = qptr->qe_next; + 8028b10: e0bfff17 ldw r2,-4(fp) + 8028b14: 10800017 ldw r2,0(r2) + 8028b18: e0bfff15 stw r2,-4(fp) + while (qptr) + 8028b1c: e0bfff17 ldw r2,-4(fp) + 8028b20: 103fd31e bne r2,zero,8028a70 + } + EXIT_CRIT_SECTION(q); /* restore int state */ + 8028b24: 8028ef40 call 8028ef4 + return NULL; /* item not found in queue */ + 8028b28: 0005883a mov r2,zero +} + 8028b2c: e037883a mov sp,fp + 8028b30: dfc00117 ldw ra,4(sp) + 8028b34: df000017 ldw fp,0(sp) + 8028b38: dec00204 addi sp,sp,8 + 8028b3c: f800283a ret + +08028b40 : + .text + + .global asm_cksum + +asm_cksum: + mov r2, zero /* accumulator = 0 */ + 8028b40: 0005883a mov r2,zero + ble r5, zero, done /* count <= 0 ? */ + 8028b44: 0140620e bge zero,r5,8028cd0 + + mov r6, zero /* carry accumulator */ + 8028b48: 000d883a mov r6,zero + + andi r3, r4, 2 /* ptr 32-bit aligned? */ + 8028b4c: 20c0008c andi r3,r4,2 + beq r3, zero, asm1 + 8028b50: 18000326 beq r3,zero,8028b60 + ldhu r2, (r4) /* no - process first 16-bits */ + 8028b54: 2080000b ldhu r2,0(r4) + addi r4, r4, 2 + 8028b58: 21000084 addi r4,r4,2 + subi r5, r5, 1 + 8028b5c: 297fffc4 addi r5,r5,-1 + +08028b60 : + 8028b60: 02c200f4 movhi r11,2051 +/* + * adjust ptr by ((count/2) mod 16) * 4 bytes + * jump to location: loop0 - (count/2 mod 16) * 4 instructions + */ +asm1: + movia r11, loop0 + 8028b64: 5ae32304 addi r11,r11,-29556 + andi r9, r5, 1 /* r9 = last halfword flag */ + 8028b68: 2a40004c andi r9,r5,1 + srai r5, r5, 1 /* count = number of words */ + 8028b6c: 280bd07a srai r5,r5,1 + andi r10, r5, 0xf /* modulo 16 */ + 8028b70: 2a8003cc andi r10,r5,15 + slli r10, r10, 2 /* * 4 bytes per word */ + 8028b74: 501490ba slli r10,r10,2 + add r4, r10, r4 /* adjust ptr */ + 8028b78: 5109883a add r4,r10,r4 + slli r10, r10, 2 /* * 4 instructions per 4 bytes */ + 8028b7c: 501490ba slli r10,r10,2 + sub r11, r11, r10 + 8028b80: 5a97c83a sub r11,r11,r10 + jmp r11 + 8028b84: 5800683a jmp r11 + +08028b88 : + +loop: + addi r4, r4, 64 /* increment data pointer */ + 8028b88: 21001004 addi r4,r4,64 + + ldw r7, -64(r4) + 8028b8c: 21fff017 ldw r7,-64(r4) + add r2, r7, r2 + 8028b90: 3885883a add r2,r7,r2 + cmpltu r8, r2, r7 + 8028b94: 11d1803a cmpltu r8,r2,r7 + add r6, r8, r6 + 8028b98: 418d883a add r6,r8,r6 + + ldw r7, -60(r4) + 8028b9c: 21fff117 ldw r7,-60(r4) + add r2, r7, r2 + 8028ba0: 3885883a add r2,r7,r2 + cmpltu r8, r2, r7 + 8028ba4: 11d1803a cmpltu r8,r2,r7 + add r6, r8, r6 + 8028ba8: 418d883a add r6,r8,r6 + + ldw r7, -56(r4) + 8028bac: 21fff217 ldw r7,-56(r4) + add r2, r7, r2 + 8028bb0: 3885883a add r2,r7,r2 + cmpltu r8, r2, r7 + 8028bb4: 11d1803a cmpltu r8,r2,r7 + add r6, r8, r6 + 8028bb8: 418d883a add r6,r8,r6 + + ldw r7, -52(r4) + 8028bbc: 21fff317 ldw r7,-52(r4) + add r2, r7, r2 + 8028bc0: 3885883a add r2,r7,r2 + cmpltu r8, r2, r7 + 8028bc4: 11d1803a cmpltu r8,r2,r7 + add r6, r8, r6 + 8028bc8: 418d883a add r6,r8,r6 + + ldw r7, -48(r4) + 8028bcc: 21fff417 ldw r7,-48(r4) + add r2, r7, r2 + 8028bd0: 3885883a add r2,r7,r2 + cmpltu r8, r2, r7 + 8028bd4: 11d1803a cmpltu r8,r2,r7 + add r6, r8, r6 + 8028bd8: 418d883a add r6,r8,r6 + + ldw r7, -44(r4) + 8028bdc: 21fff517 ldw r7,-44(r4) + add r2, r7, r2 + 8028be0: 3885883a add r2,r7,r2 + cmpltu r8, r2, r7 + 8028be4: 11d1803a cmpltu r8,r2,r7 + add r6, r8, r6 + 8028be8: 418d883a add r6,r8,r6 + + ldw r7, -40(r4) + 8028bec: 21fff617 ldw r7,-40(r4) + add r2, r7, r2 + 8028bf0: 3885883a add r2,r7,r2 + cmpltu r8, r2, r7 + 8028bf4: 11d1803a cmpltu r8,r2,r7 + add r6, r8, r6 + 8028bf8: 418d883a add r6,r8,r6 + + ldw r7, -36(r4) + 8028bfc: 21fff717 ldw r7,-36(r4) + add r2, r7, r2 + 8028c00: 3885883a add r2,r7,r2 + cmpltu r8, r2, r7 + 8028c04: 11d1803a cmpltu r8,r2,r7 + add r6, r8, r6 + 8028c08: 418d883a add r6,r8,r6 + + ldw r7, -32(r4) + 8028c0c: 21fff817 ldw r7,-32(r4) + add r2, r7, r2 + 8028c10: 3885883a add r2,r7,r2 + cmpltu r8, r2, r7 + 8028c14: 11d1803a cmpltu r8,r2,r7 + add r6, r8, r6 + 8028c18: 418d883a add r6,r8,r6 + + ldw r7, -28(r4) + 8028c1c: 21fff917 ldw r7,-28(r4) + add r2, r7, r2 + 8028c20: 3885883a add r2,r7,r2 + cmpltu r8, r2, r7 + 8028c24: 11d1803a cmpltu r8,r2,r7 + add r6, r8, r6 + 8028c28: 418d883a add r6,r8,r6 + + ldw r7, -24(r4) + 8028c2c: 21fffa17 ldw r7,-24(r4) + add r2, r7, r2 + 8028c30: 3885883a add r2,r7,r2 + cmpltu r8, r2, r7 + 8028c34: 11d1803a cmpltu r8,r2,r7 + add r6, r8, r6 + 8028c38: 418d883a add r6,r8,r6 + + ldw r7, -20(r4) + 8028c3c: 21fffb17 ldw r7,-20(r4) + add r2, r7, r2 + 8028c40: 3885883a add r2,r7,r2 + cmpltu r8, r2, r7 + 8028c44: 11d1803a cmpltu r8,r2,r7 + add r6, r8, r6 + 8028c48: 418d883a add r6,r8,r6 + + ldw r7, -16(r4) + 8028c4c: 21fffc17 ldw r7,-16(r4) + add r2, r7, r2 + 8028c50: 3885883a add r2,r7,r2 + cmpltu r8, r2, r7 + 8028c54: 11d1803a cmpltu r8,r2,r7 + add r6, r8, r6 + 8028c58: 418d883a add r6,r8,r6 + + ldw r7, -12(r4) + 8028c5c: 21fffd17 ldw r7,-12(r4) + add r2, r7, r2 + 8028c60: 3885883a add r2,r7,r2 + cmpltu r8, r2, r7 + 8028c64: 11d1803a cmpltu r8,r2,r7 + add r6, r8, r6 + 8028c68: 418d883a add r6,r8,r6 + + ldw r7, -8(r4) + 8028c6c: 21fffe17 ldw r7,-8(r4) + add r2, r7, r2 + 8028c70: 3885883a add r2,r7,r2 + cmpltu r8, r2, r7 + 8028c74: 11d1803a cmpltu r8,r2,r7 + add r6, r8, r6 + 8028c78: 418d883a add r6,r8,r6 + + ldw r7, -4(r4) + 8028c7c: 21ffff17 ldw r7,-4(r4) + add r2, r7, r2 + 8028c80: 3885883a add r2,r7,r2 + cmpltu r8, r2, r7 + 8028c84: 11d1803a cmpltu r8,r2,r7 + add r6, r8, r6 + 8028c88: 418d883a add r6,r8,r6 + +08028c8c : +loop0: + subi r5, r5, 16 + 8028c8c: 297ffc04 addi r5,r5,-16 + bge r5, zero, loop + 8028c90: 283fbd0e bge r5,zero,8028b88 +/* + * process last halfword (if any) + */ + beq r9, zero, fold + 8028c94: 48000426 beq r9,zero,8028ca8 + ldhu r7, 0(r4) + 8028c98: 21c0000b ldhu r7,0(r4) + add r2, r7, r2 + 8028c9c: 3885883a add r2,r7,r2 + cmpltu r8, r2, r7 + 8028ca0: 11d1803a cmpltu r8,r2,r7 + add r6, r8, r6 + 8028ca4: 418d883a add r6,r8,r6 + +08028ca8 : + +fold: + srli r7, r2, 16 + 8028ca8: 100ed43a srli r7,r2,16 + andi r2, r2, 0xffff + 8028cac: 10bfffcc andi r2,r2,65535 + add r2, r7, r2 /* add the upper and lower halfwords */ + 8028cb0: 3885883a add r2,r7,r2 + add r2, r6, r2 /* add the carries */ + 8028cb4: 3085883a add r2,r6,r2 +/* the accumulator is 18 bits */ + srli r7, r2, 16 + 8028cb8: 100ed43a srli r7,r2,16 + andi r2, r2, 0xffff + 8028cbc: 10bfffcc andi r2,r2,65535 + add r2, r7, r2 /* add 2 carry bits to lower halfword */ + 8028cc0: 3885883a add r2,r7,r2 +/* the accumulator is 17 bits */ + srli r7, r2, 16 + 8028cc4: 100ed43a srli r7,r2,16 + andi r2, r2, 0xffff + 8028cc8: 10bfffcc andi r2,r2,65535 + add r2, r7, r2 /* add carry to lower halfword */ + 8028ccc: 3885883a add r2,r7,r2 + +08028cd0 : + +done: + ret /* r2 = 16-bit checksum */ + 8028cd0: f800283a ret + +08028cd4 : +void irq_Unmask(void); + +/* dtrap() - function to trap to debugger */ +void +dtrap(void) +{ + 8028cd4: defffe04 addi sp,sp,-8 + 8028cd8: dfc00115 stw ra,4(sp) + 8028cdc: df000015 stw fp,0(sp) + 8028ce0: d839883a mov fp,sp + printf("dtrap - needs breakpoint\n"); + 8028ce4: 01020174 movhi r4,2053 + 8028ce8: 21298204 addi r4,r4,-23032 + 8028cec: 8002d9c0 call 8002d9c +} + 8028cf0: 0001883a nop + 8028cf4: e037883a mov sp,fp + 8028cf8: dfc00117 ldw ra,4(sp) + 8028cfc: df000017 ldw fp,0(sp) + 8028d00: dec00204 addi sp,sp,8 + 8028d04: f800283a ret + +08028d08 : + +int +kbhit() +{ + 8028d08: defffd04 addi sp,sp,-12 + 8028d0c: dfc00215 stw ra,8(sp) + 8028d10: df000115 stw fp,4(sp) + 8028d14: df000104 addi fp,sp,4 + static int kbd_init = 0; + int kb; + + if (!kbd_init) + 8028d18: d0a07517 ldw r2,-32300(gp) + 8028d1c: 10000b1e bne r2,zero,8028d4c + /* we really should read the flags, OR in O_NONBLOCK, and write + * the flags back to STDIN, but the NIOS-II/HAL implementation + * will only let us modify O_NONBLOCK and O_APPEND, so we'll + * just write the new flag value. + */ + if (fcntl(STDIN_FILENO, F_SETFL, O_NONBLOCK) != 0) + 8028d20: 01900004 movi r6,16384 + 8028d24: 01400104 movi r5,4 + 8028d28: 0009883a mov r4,zero + 8028d2c: 8038ed80 call 8038ed8 + 8028d30: 10000426 beq r2,zero,8028d44 + { + printf("F_SETFL failed.\n"); + 8028d34: 01020174 movhi r4,2053 + 8028d38: 21298904 addi r4,r4,-23004 + 8028d3c: 8002d9c0 call 8002d9c + dtrap(); + 8028d40: 8028cd40 call 8028cd4 + } + kbd_init = 1; + 8028d44: 00800044 movi r2,1 + 8028d48: d0a07515 stw r2,-32300(gp) + } + + /* we have to do a read to see if there is a character available. + * we save the character, if there was one, to be read later. */ + if (kb_last == EOF) + 8028d4c: d0a01a17 ldw r2,-32664(gp) + 8028d50: 10bfffd8 cmpnei r2,r2,-1 + 8028d54: 1000081e bne r2,zero,8028d78 + { + kb = getchar(); + 8028d58: 8002c380 call 8002c38 + 8028d5c: e0bfff15 stw r2,-4(fp) + if (kb < 0) /* any error means no character present */ + 8028d60: e0bfff17 ldw r2,-4(fp) + 8028d64: 1000020e bge r2,zero,8028d70 + return (FALSE); + 8028d68: 0005883a mov r2,zero + 8028d6c: 00000306 br 8028d7c + + /* there was a character, and we read it. */ + kb_last = kb; + 8028d70: e0bfff17 ldw r2,-4(fp) + 8028d74: d0a01a15 stw r2,-32664(gp) + } + + return (TRUE); + 8028d78: 00800044 movi r2,1 +} + 8028d7c: e037883a mov sp,fp + 8028d80: dfc00117 ldw ra,4(sp) + 8028d84: df000017 ldw fp,0(sp) + 8028d88: dec00204 addi sp,sp,8 + 8028d8c: f800283a ret + +08028d90 : + +int +getch() +{ + 8028d90: defffd04 addi sp,sp,-12 + 8028d94: dfc00215 stw ra,8(sp) + 8028d98: df000115 stw fp,4(sp) + 8028d9c: df000104 addi fp,sp,4 +int chr; + + if(kb_last != EOF) + 8028da0: d0a01a17 ldw r2,-32664(gp) + 8028da4: 10bfffe0 cmpeqi r2,r2,-1 + 8028da8: 1000051e bne r2,zero,8028dc0 + { + chr = kb_last; + 8028dac: d0a01a17 ldw r2,-32664(gp) + 8028db0: e0bfff15 stw r2,-4(fp) + kb_last = EOF; + 8028db4: 00bfffc4 movi r2,-1 + 8028db8: d0a01a15 stw r2,-32664(gp) + 8028dbc: 00000206 br 8028dc8 + } + else + chr = getchar(); + 8028dc0: 8002c380 call 8002c38 + 8028dc4: e0bfff15 stw r2,-4(fp) + + return chr; + 8028dc8: e0bfff17 ldw r2,-4(fp) +} + 8028dcc: e037883a mov sp,fp + 8028dd0: dfc00117 ldw ra,4(sp) + 8028dd4: df000017 ldw fp,0(sp) + 8028dd8: dec00204 addi sp,sp,8 + 8028ddc: f800283a ret + +08028de0 : +int OS_TPS; +int cticks_factor; +int cticks_initialized = 0; + +void clock_init(void) +{ + 8028de0: deffff04 addi sp,sp,-4 + 8028de4: df000015 stw fp,0(sp) + 8028de8: d839883a mov fp,sp + OS_TPS = OS_TICKS_PER_SEC; + 8028dec: 00801904 movi r2,100 + 8028df0: d0a07715 stw r2,-32292(gp) + cticks_factor = 0; + 8028df4: d0207615 stw zero,-32296(gp) + cticks = 0; + 8028df8: d0207d15 stw zero,-32268(gp) + cticks_initialized = 1; + 8028dfc: 00800044 movi r2,1 + 8028e00: d0a07215 stw r2,-32312(gp) +} + 8028e04: 0001883a nop + 8028e08: e037883a mov sp,fp + 8028e0c: df000017 ldw fp,0(sp) + 8028e10: dec00104 addi sp,sp,4 + 8028e14: f800283a ret + +08028e18 : + +/* undo effects of clock_init (i.e. restore ISR vector) + * NO OP since using RTOS's timer. + */ +void clock_c(void) +{ + 8028e18: deffff04 addi sp,sp,-4 + 8028e1c: df000015 stw fp,0(sp) + 8028e20: d839883a mov fp,sp + /* null */ ; +} + 8028e24: 0001883a nop + 8028e28: e037883a mov sp,fp + 8028e2c: df000017 ldw fp,0(sp) + 8028e30: dec00104 addi sp,sp,4 + 8028e34: f800283a ret + +08028e38 : + * Use the uCOS-II/Altera HAL BSP's timer and scale cticks as per TPS. + */ + +void +cticks_hook(void) +{ + 8028e38: deffff04 addi sp,sp,-4 + 8028e3c: df000015 stw fp,0(sp) + 8028e40: d839883a mov fp,sp + if (cticks_initialized) + 8028e44: d0a07217 ldw r2,-32312(gp) + 8028e48: 10000d26 beq r2,zero,8028e80 + { + cticks_factor += TPS; + 8028e4c: d0a07617 ldw r2,-32296(gp) + 8028e50: 10801904 addi r2,r2,100 + 8028e54: d0a07615 stw r2,-32296(gp) + if (cticks_factor >= OS_TPS) + 8028e58: d0e07617 ldw r3,-32296(gp) + 8028e5c: d0a07717 ldw r2,-32292(gp) + 8028e60: 18800716 blt r3,r2,8028e80 + { + cticks++; + 8028e64: d0a07d17 ldw r2,-32268(gp) + 8028e68: 10800044 addi r2,r2,1 + 8028e6c: d0a07d15 stw r2,-32268(gp) + cticks_factor -= OS_TPS; + 8028e70: d0e07617 ldw r3,-32296(gp) + 8028e74: d0a07717 ldw r2,-32292(gp) + 8028e78: 1885c83a sub r2,r3,r2 + 8028e7c: d0a07615 stw r2,-32296(gp) +#ifdef USE_LCD + update_display(); +#endif + } + } +} + 8028e80: 0001883a nop + 8028e84: e037883a mov sp,fp + 8028e88: df000017 ldw fp,0(sp) + 8028e8c: dec00104 addi sp,sp,4 + 8028e90: f800283a ret + +08028e94 : + * ENTER_CRIT_SECTION() and enable them in EXIT_CRIT_SECTION() + * because calls to ENTER_CRIT_SECTION() can be nested." + */ +void +irq_Mask(void) +{ + 8028e94: defffd04 addi sp,sp,-12 + 8028e98: df000215 stw fp,8(sp) + 8028e9c: df000204 addi fp,sp,8 + NIOS2_READ_STATUS (context); + 8028ea0: 0005303a rdctl r2,status + 8028ea4: e0bffe15 stw r2,-8(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8028ea8: e0fffe17 ldw r3,-8(fp) + 8028eac: 00bfff84 movi r2,-2 + 8028eb0: 1884703a and r2,r3,r2 + 8028eb4: 1001703a wrctl status,r2 + return context; + 8028eb8: e0bffe17 ldw r2,-8(fp) + alt_irq_context local_cpu_statusreg; + + local_cpu_statusreg = alt_irq_disable_all(); + 8028ebc: e0bfff15 stw r2,-4(fp) + + if (++irq_level == 1) + 8028ec0: d0a07317 ldw r2,-32308(gp) + 8028ec4: 10800044 addi r2,r2,1 + 8028ec8: d0a07315 stw r2,-32308(gp) + 8028ecc: d0a07317 ldw r2,-32308(gp) + 8028ed0: 10800058 cmpnei r2,r2,1 + 8028ed4: 1000021e bne r2,zero,8028ee0 + { + cpu_statusreg = local_cpu_statusreg; + 8028ed8: e0bfff17 ldw r2,-4(fp) + 8028edc: d0a07415 stw r2,-32304(gp) + } +} + 8028ee0: 0001883a nop + 8028ee4: e037883a mov sp,fp + 8028ee8: df000017 ldw fp,0(sp) + 8028eec: dec00104 addi sp,sp,4 + 8028ef0: f800283a ret + +08028ef4 : + + +/* Re-Enable Interrupts */ +void +irq_Unmask(void) +{ + 8028ef4: defffe04 addi sp,sp,-8 + 8028ef8: df000115 stw fp,4(sp) + 8028efc: df000104 addi fp,sp,4 + if (--irq_level == 0) + 8028f00: d0a07317 ldw r2,-32308(gp) + 8028f04: 10bfffc4 addi r2,r2,-1 + 8028f08: d0a07315 stw r2,-32308(gp) + 8028f0c: d0a07317 ldw r2,-32308(gp) + 8028f10: 1000041e bne r2,zero,8028f24 + { + alt_irq_enable_all(cpu_statusreg); + 8028f14: d0a07417 ldw r2,-32304(gp) + 8028f18: e0bfff15 stw r2,-4(fp) + NIOS2_WRITE_STATUS (context); + 8028f1c: e0bfff17 ldw r2,-4(fp) + 8028f20: 1001703a wrctl status,r2 + } +} + 8028f24: 0001883a nop + 8028f28: e037883a mov sp,fp + 8028f2c: df000017 ldw fp,0(sp) + 8028f30: dec00104 addi sp,sp,4 + 8028f34: f800283a ret + +08028f38 : +extern void irq_Mask(void); +extern void irq_Unmask(void); + +void +LOCK_NET_RESOURCE(int resid) +{ + 8028f38: defffb04 addi sp,sp,-20 + 8028f3c: dfc00415 stw ra,16(sp) + 8028f40: df000315 stw fp,12(sp) + 8028f44: df000304 addi fp,sp,12 + 8028f48: e13ffd15 stw r4,-12(fp) + INT8U error = 0; + 8028f4c: e03ffec5 stb zero,-5(fp) + int errct = 0; + 8028f50: e03fff15 stw zero,-4(fp) + + if ((0 <= resid) && (resid <= MAX_RESID)) + 8028f54: e0bffd17 ldw r2,-12(fp) + 8028f58: 10002016 blt r2,zero,8028fdc + 8028f5c: e0bffd17 ldw r2,-12(fp) + 8028f60: 10800408 cmpgei r2,r2,16 + 8028f64: 10001d1e bne r2,zero,8028fdc + { + do + { + OSSemPend(resid_semaphore[resid], 0, &error); + 8028f68: e0bffd17 ldw r2,-12(fp) + 8028f6c: 100690ba slli r3,r2,2 + 8028f70: 008201b4 movhi r2,2054 + 8028f74: 1885883a add r2,r3,r2 + 8028f78: 10b85b17 ldw r2,-7828(r2) + 8028f7c: e0fffec4 addi r3,fp,-5 + 8028f80: 180d883a mov r6,r3 + 8028f84: 000b883a mov r5,zero + 8028f88: 1009883a mov r4,r2 + 8028f8c: 8015a600 call 8015a60 + /* + * Sometimes we get a "timeout" error even though we passed a zero + * to indicate we'll wait forever. When this happens, try again: + */ + if ((error == 10) && (++errct > 1000)) + 8028f90: e0bffec3 ldbu r2,-5(fp) + 8028f94: 10803fcc andi r2,r2,255 + 8028f98: 10800298 cmpnei r2,r2,10 + 8028f9c: 10000a1e bne r2,zero,8028fc8 + 8028fa0: e0bfff17 ldw r2,-4(fp) + 8028fa4: 10800044 addi r2,r2,1 + 8028fa8: e0bfff15 stw r2,-4(fp) + 8028fac: e0bfff17 ldw r2,-4(fp) + 8028fb0: 1080fa50 cmplti r2,r2,1001 + 8028fb4: 1000041e bne r2,zero,8028fc8 + { + panic("lock NET"); /* fatal */ + 8028fb8: 01020174 movhi r4,2053 + 8028fbc: 21298d04 addi r4,r4,-22988 + 8028fc0: 80271780 call 8027178 + 8028fc4: 00000606 br 8028fe0 + return; + } + } while (error == 10); + 8028fc8: e0bffec3 ldbu r2,-5(fp) + 8028fcc: 10803fcc andi r2,r2,255 + 8028fd0: 108002a0 cmpeqi r2,r2,10 + 8028fd4: 103fe41e bne r2,zero,8028f68 + if ((0 <= resid) && (resid <= MAX_RESID)) + 8028fd8: 00000106 br 8028fe0 + } + else + dtrap(); + 8028fdc: 8028cd40 call 8028cd4 +} + 8028fe0: e037883a mov sp,fp + 8028fe4: dfc00117 ldw ra,4(sp) + 8028fe8: df000017 ldw fp,0(sp) + 8028fec: dec00204 addi sp,sp,8 + 8028ff0: f800283a ret + +08028ff4 : + +void +UNLOCK_NET_RESOURCE(int resid) +{ + 8028ff4: defffc04 addi sp,sp,-16 + 8028ff8: dfc00315 stw ra,12(sp) + 8028ffc: df000215 stw fp,8(sp) + 8029000: df000204 addi fp,sp,8 + 8029004: e13ffe15 stw r4,-8(fp) + INT8U error = 0; + 8029008: e03fffc5 stb zero,-1(fp) + + if ((0 <= resid) && (resid <= MAX_RESID)) + 802900c: e0bffe17 ldw r2,-8(fp) + 8029010: 10001116 blt r2,zero,8029058 + 8029014: e0bffe17 ldw r2,-8(fp) + 8029018: 10800408 cmpgei r2,r2,16 + 802901c: 10000e1e bne r2,zero,8029058 + { + error = OSSemPost(resid_semaphore[resid]); + 8029020: e0bffe17 ldw r2,-8(fp) + 8029024: 100690ba slli r3,r2,2 + 8029028: 008201b4 movhi r2,2054 + 802902c: 1885883a add r2,r3,r2 + 8029030: 10b85b17 ldw r2,-7828(r2) + 8029034: 1009883a mov r4,r2 + 8029038: 8015d840 call 8015d84 + 802903c: e0bfffc5 stb r2,-1(fp) + if (error != OS_NO_ERR) + 8029040: e0bfffc3 ldbu r2,-1(fp) + 8029044: 10000526 beq r2,zero,802905c + { + panic("unlock NET"); + 8029048: 01020174 movhi r4,2053 + 802904c: 21299004 addi r4,r4,-22976 + 8029050: 80271780 call 8027178 + if (error != OS_NO_ERR) + 8029054: 00000106 br 802905c + } + } + else + dtrap(); + 8029058: 8028cd40 call 8028cd4 +} + 802905c: 0001883a nop + 8029060: e037883a mov sp,fp + 8029064: dfc00117 ldw ra,4(sp) + 8029068: df000017 ldw fp,0(sp) + 802906c: dec00204 addi sp,sp,8 + 8029070: f800283a ret + +08029074 : +extern long nettick_wakes; + + +int +TK_NEWTASK(struct inet_taskinfo * nettask) +{ + 8029074: deffee04 addi sp,sp,-72 + 8029078: dfc01115 stw ra,68(sp) + 802907c: df001015 stw fp,64(sp) + 8029080: df001004 addi fp,sp,64 + 8029084: e13ff515 stw r4,-44(fp) + INT8U error; + OS_STK * stack; + + stack = (OS_STK*)npalloc(nettask->stacksize); + 8029088: e0bff517 ldw r2,-44(fp) + 802908c: 10800417 ldw r2,16(r2) + 8029090: 1009883a mov r4,r2 + 8029094: 802982c0 call 802982c + 8029098: e0bfff15 stw r2,-4(fp) + if(!stack) + 802909c: e0bfff17 ldw r2,-4(fp) + 80290a0: 1000031e bne r2,zero,80290b0 + panic("stack alloc"); + 80290a4: 01020174 movhi r4,2053 + 80290a8: 21299304 addi r4,r4,-22964 + 80290ac: 80271780 call 8027178 + +#if OS_TASK_CREATE_EXT_EN > 0 + error = OSTaskCreateExt( + 80290b0: e0bff517 ldw r2,-44(fp) + 80290b4: 12000217 ldw r8,8(r2) + nettask->entry, + NULL, + stack + (nettask->stacksize/sizeof(OS_STK)) - 1, + 80290b8: e0bff517 ldw r2,-44(fp) + 80290bc: 10800417 ldw r2,16(r2) + 80290c0: 1007883a mov r3,r2 + 80290c4: 00bfff04 movi r2,-4 + 80290c8: 1884703a and r2,r3,r2 + 80290cc: 10bfff04 addi r2,r2,-4 + error = OSTaskCreateExt( + 80290d0: e0ffff17 ldw r3,-4(fp) + 80290d4: 188b883a add r5,r3,r2 + nettask->priority, + 80290d8: e0bff517 ldw r2,-44(fp) + 80290dc: 10800317 ldw r2,12(r2) + error = OSTaskCreateExt( + 80290e0: 11803fcc andi r6,r2,255 + nettask->priority, + 80290e4: e0bff517 ldw r2,-44(fp) + 80290e8: 10800317 ldw r2,12(r2) + error = OSTaskCreateExt( + 80290ec: 10bfffcc andi r2,r2,65535 + stack, + (INT32U)nettask->stacksize / sizeof(OS_STK), + 80290f0: e0fff517 ldw r3,-44(fp) + 80290f4: 18c00417 ldw r3,16(r3) + error = OSTaskCreateExt( + 80290f8: 1806d0ba srli r3,r3,2 + 80290fc: 010000c4 movi r4,3 + 8029100: d9000415 stw r4,16(sp) + 8029104: d8000315 stw zero,12(sp) + 8029108: d8c00215 stw r3,8(sp) + 802910c: e0ffff17 ldw r3,-4(fp) + 8029110: d8c00115 stw r3,4(sp) + 8029114: d8800015 stw r2,0(sp) + 8029118: 300f883a mov r7,r6 + 802911c: 280d883a mov r6,r5 + 8029120: 000b883a mov r5,zero + 8029124: 4009883a mov r4,r8 + 8029128: 801664c0 call 801664c + 802912c: e0bffec5 stb r2,-5(fp) + stack + (nettask->stacksize/sizeof(OS_STK)) - 1, + nettask->priority); +#endif + /* If we go here, then there's another task using our priority */ + /* Tell the user and exit with an error */ + if (error == OS_PRIO_EXIST) + 8029130: e0bffec3 ldbu r2,-5(fp) + 8029134: 10803fcc andi r2,r2,255 + 8029138: 10800a18 cmpnei r2,r2,40 + 802913c: 10001c1e bne r2,zero,80291b0 + { + char curr_task[OS_TASK_NAME_SIZE]; + INT8U err; + OSTaskNameGet(nettask->priority, (INT8U*)curr_task, &err); + 8029140: e0bff517 ldw r2,-44(fp) + 8029144: 10800317 ldw r2,12(r2) + 8029148: 10803fcc andi r2,r2,255 + 802914c: e13ffe84 addi r4,fp,-6 + 8029150: e0fff684 addi r3,fp,-38 + 8029154: 200d883a mov r6,r4 + 8029158: 180b883a mov r5,r3 + 802915c: 1009883a mov r4,r2 + 8029160: 8016c2c0 call 8016c2c + curr_task[OS_TASK_NAME_SIZE-1]=0; + 8029164: e03ffe45 stb zero,-7(fp) + + printf("Priority requested for task \"%s\" (Prio:%d) conflicts with "\ + 8029168: e0bff517 ldw r2,-44(fp) + 802916c: 10c00117 ldw r3,4(r2) + 8029170: e0bff517 ldw r2,-44(fp) + 8029174: 11000317 ldw r4,12(r2) + 8029178: e0bff517 ldw r2,-44(fp) + 802917c: 10800317 ldw r2,12(r2) + 8029180: e17ff684 addi r5,fp,-38 + 8029184: d8800015 stw r2,0(sp) + 8029188: 280f883a mov r7,r5 + 802918c: 200d883a mov r6,r4 + 8029190: 180b883a mov r5,r3 + 8029194: 01020174 movhi r4,2053 + 8029198: 21299604 addi r4,r4,-22952 + 802919c: 8002c780 call 8002c78 + "already running task \"%s\" (Prio: %d)\n", + nettask->name, nettask->priority, curr_task, nettask->priority); + + printf("You may wish to check your task priority settings in "\ + 80291a0: 01020174 movhi r4,2053 + 80291a4: 2129ae04 addi r4,r4,-22856 + 80291a8: 8002d9c0 call 8002d9c + 80291ac: 00002006 br 8029230 + "\"\\iniche\\src\\h\\nios2\\ipport.h\" against "\ + "the priority settings in your application and recompile.\n\n"); + } + else if (error == OS_PRIO_INVALID) + 80291b0: e0bffec3 ldbu r2,-5(fp) + 80291b4: 10803fcc andi r2,r2,255 + 80291b8: 10800a98 cmpnei r2,r2,42 + 80291bc: 10000e1e bne r2,zero,80291f8 + { + printf("Priority requested for task \"%s\" (Prio:%d) exceeds "\ + 80291c0: e0bff517 ldw r2,-44(fp) + 80291c4: 10c00117 ldw r3,4(r2) + 80291c8: e0bff517 ldw r2,-44(fp) + 80291cc: 10800317 ldw r2,12(r2) + 80291d0: 01c00504 movi r7,20 + 80291d4: 100d883a mov r6,r2 + 80291d8: 180b883a mov r5,r3 + 80291dc: 01020174 movhi r4,2053 + 80291e0: 2129d604 addi r4,r4,-22696 + 80291e4: 8002c780 call 8002c78 + "available priority levels in the system (OS_LOWEST_PRIO = %d)\n\n", + nettask->name, nettask->priority, OS_LOWEST_PRIO); + + printf("Please modify the tasks priority level, or modify the "\ + 80291e8: 01020174 movhi r4,2053 + 80291ec: 2129f304 addi r4,r4,-22580 + 80291f0: 8002d9c0 call 8002d9c + 80291f4: 00000e06 br 8029230 + "\"Lowest assignable priority\" setting in the MicroC/OS-II "\ + "component\n"); + } + else if (error != OS_NO_ERR) + 80291f8: e0bffec3 ldbu r2,-5(fp) + 80291fc: 10803fcc andi r2,r2,255 + 8029200: 10000b26 beq r2,zero,8029230 + { /* All other errors are fatal */ + printf("Task create error /(MicroC/OS-II error code:%d/) on %s\n", + 8029204: e0bffec3 ldbu r2,-5(fp) + 8029208: 10c03fcc andi r3,r2,255 + 802920c: e0bff517 ldw r2,-44(fp) + 8029210: 10800117 ldw r2,4(r2) + 8029214: 100d883a mov r6,r2 + 8029218: 180b883a mov r5,r3 + 802921c: 01020174 movhi r4,2053 + 8029220: 212a1204 addi r4,r4,-22456 + 8029224: 8002c780 call 8002c78 + error, nettask->name); + return (-1); + 8029228: 00bfffc4 movi r2,-1 + 802922c: 00001c06 br 80292a0 + } + + /* Include the task name, so that uc/osII (os aware) debuggers can + * display it. + */ + OSTaskNameSet(nettask->priority, (INT8U*)&nettask->name[0], &error); + 8029230: e0bff517 ldw r2,-44(fp) + 8029234: 10800317 ldw r2,12(r2) + 8029238: 10c03fcc andi r3,r2,255 + 802923c: e0bff517 ldw r2,-44(fp) + 8029240: 10800117 ldw r2,4(r2) + 8029244: e13ffec4 addi r4,fp,-5 + 8029248: 200d883a mov r6,r4 + 802924c: 100b883a mov r5,r2 + 8029250: 1809883a mov r4,r3 + 8029254: 8016d640 call 8016d64 + + nettask->stackbase = (char*)stack; + 8029258: e0bff517 ldw r2,-44(fp) + 802925c: e0ffff17 ldw r3,-4(fp) + 8029260: 10c00515 stw r3,20(r2) + *nettask->tk_ptr = (INT8U)nettask->priority; + 8029264: e0bff517 ldw r2,-44(fp) + 8029268: 10c00317 ldw r3,12(r2) + 802926c: e0bff517 ldw r2,-44(fp) + 8029270: 10800017 ldw r2,0(r2) + 8029274: 10c00005 stb r3,0(r2) + + printf("Created \"%s\" task (Prio: %d)\n", + 8029278: e0bff517 ldw r2,-44(fp) + 802927c: 10c00117 ldw r3,4(r2) + 8029280: e0bff517 ldw r2,-44(fp) + 8029284: 10800317 ldw r2,12(r2) + 8029288: 100d883a mov r6,r2 + 802928c: 180b883a mov r5,r3 + 8029290: 01020174 movhi r4,2053 + 8029294: 212a2004 addi r4,r4,-22400 + 8029298: 8002c780 call 8002c78 + (char *)nettask->name, nettask->priority); + + return (0); + 802929c: 0005883a mov r2,zero +} + 80292a0: e037883a mov sp,fp + 80292a4: dfc00117 ldw ra,4(sp) + 80292a8: df000017 ldw fp,0(sp) + 80292ac: dec00204 addi sp,sp,8 + 80292b0: f800283a ret + +080292b4 : + * event (e.g., configuration inputs from user, initiation of a new session, + * or a periodic timeout notification. + */ +void +wait_app_sem(unsigned long semid) +{ + 80292b4: defffb04 addi sp,sp,-20 + 80292b8: dfc00415 stw ra,16(sp) + 80292bc: df000315 stw fp,12(sp) + 80292c0: df000304 addi fp,sp,12 + 80292c4: e13ffd15 stw r4,-12(fp) + INT8U error = 0; + 80292c8: e03ffec5 stb zero,-5(fp) + int errct = 0; + 80292cc: e03fff15 stw zero,-4(fp) + + if ((0 <= semid) && (semid <= MAX_SEMID)) + 80292d0: e0bffd17 ldw r2,-12(fp) + 80292d4: 108001a8 cmpgeui r2,r2,6 + 80292d8: 10001d1e bne r2,zero,8029350 + { + do + { + OSSemPend(app_semaphore[semid], 0, &error); + 80292dc: e0bffd17 ldw r2,-12(fp) + 80292e0: 100690ba slli r3,r2,2 + 80292e4: 008201b4 movhi r2,2054 + 80292e8: 1885883a add r2,r3,r2 + 80292ec: 10b86b17 ldw r2,-7764(r2) + 80292f0: e0fffec4 addi r3,fp,-5 + 80292f4: 180d883a mov r6,r3 + 80292f8: 000b883a mov r5,zero + 80292fc: 1009883a mov r4,r2 + 8029300: 8015a600 call 8015a60 + /* + * Sometimes we get a "timeout" error even though we passed a zero + * to indicate we'll wait forever. When this happens, try again: + */ + if ((error == 10) && (++errct > 1000)) + 8029304: e0bffec3 ldbu r2,-5(fp) + 8029308: 10803fcc andi r2,r2,255 + 802930c: 10800298 cmpnei r2,r2,10 + 8029310: 10000a1e bne r2,zero,802933c + 8029314: e0bfff17 ldw r2,-4(fp) + 8029318: 10800044 addi r2,r2,1 + 802931c: e0bfff15 stw r2,-4(fp) + 8029320: e0bfff17 ldw r2,-4(fp) + 8029324: 1080fa50 cmplti r2,r2,1001 + 8029328: 1000041e bne r2,zero,802933c + { + panic("lock NET"); /* fatal */ + 802932c: 01020174 movhi r4,2053 + 8029330: 21298d04 addi r4,r4,-22988 + 8029334: 80271780 call 8027178 + 8029338: 00000606 br 8029354 + return; + } + } while (error == 10); + 802933c: e0bffec3 ldbu r2,-5(fp) + 8029340: 10803fcc andi r2,r2,255 + 8029344: 108002a0 cmpeqi r2,r2,10 + 8029348: 103fe41e bne r2,zero,80292dc + 802934c: 00000106 br 8029354 + } + else + dtrap(); + 8029350: 8028cd40 call 8028cd4 +} + 8029354: e037883a mov sp,fp + 8029358: dfc00117 ldw ra,4(sp) + 802935c: df000017 ldw fp,0(sp) + 8029360: dec00204 addi sp,sp,8 + 8029364: f800283a ret + +08029368 : + * notification. It signals the corresponding application event. + */ + +void +post_app_sem(unsigned long semid) +{ + 8029368: defffc04 addi sp,sp,-16 + 802936c: dfc00315 stw ra,12(sp) + 8029370: df000215 stw fp,8(sp) + 8029374: df000204 addi fp,sp,8 + 8029378: e13ffe15 stw r4,-8(fp) + INT8U error; + + if ((0 <= semid) && (semid <= MAX_SEMID)) + 802937c: e0bffe17 ldw r2,-8(fp) + 8029380: 108001a8 cmpgeui r2,r2,6 + 8029384: 10000e1e bne r2,zero,80293c0 + { + error = OSSemPost(app_semaphore[semid]); + 8029388: e0bffe17 ldw r2,-8(fp) + 802938c: 100690ba slli r3,r2,2 + 8029390: 008201b4 movhi r2,2054 + 8029394: 1885883a add r2,r3,r2 + 8029398: 10b86b17 ldw r2,-7764(r2) + 802939c: 1009883a mov r4,r2 + 80293a0: 8015d840 call 8015d84 + 80293a4: e0bfffc5 stb r2,-1(fp) + if (error != OS_NO_ERR) + 80293a8: e0bfffc3 ldbu r2,-1(fp) + 80293ac: 10000526 beq r2,zero,80293c4 + { + panic("unlock NET"); + 80293b0: 01020174 movhi r4,2053 + 80293b4: 21299004 addi r4,r4,-22976 + 80293b8: 80271780 call 8027178 + } + } + else + dtrap(); +} + 80293bc: 00000106 br 80293c4 + dtrap(); + 80293c0: 8028cd40 call 8028cd4 +} + 80293c4: 0001883a nop + 80293c8: e037883a mov sp,fp + 80293cc: dfc00117 ldw ra,4(sp) + 80293d0: df000017 ldw fp,0(sp) + 80293d4: dec00204 addi sp,sp,8 + 80293d8: f800283a ret + +080293dc : +#ifndef SUPERLOOP + +extern OS_EVENT *resid_semaphore[MAX_RESID+1]; + +void alt_iniche_init(void) +{ + 80293dc: defffd04 addi sp,sp,-12 + 80293e0: dfc00215 stw ra,8(sp) + 80293e4: df000115 stw fp,4(sp) + 80293e8: df000104 addi fp,sp,4 + int i; + + /* initialize the npalloc() heap semaphore */ + mheap_sem_ptr = OSSemCreate(1); + 80293ec: 01000044 movi r4,1 + 80293f0: 80157740 call 8015774 + 80293f4: d0a07f15 stw r2,-32260(gp) + if (!mheap_sem_ptr) + 80293f8: d0a07f17 ldw r2,-32260(gp) + 80293fc: 1000031e bne r2,zero,802940c + panic("mheap_sem_ptr create err"); + 8029400: 01020174 movhi r4,2053 + 8029404: 212a2804 addi r4,r4,-22368 + 8029408: 80271780 call 8027178 + + rcvdq_sem_ptr = OSSemCreate(0); + 802940c: 0009883a mov r4,zero + 8029410: 80157740 call 8015774 + 8029414: d0a08015 stw r2,-32256(gp) + if (!rcvdq_sem_ptr) + 8029418: d0a08017 ldw r2,-32256(gp) + 802941c: 1000031e bne r2,zero,802942c + panic("rcvdq_sem_ptr create err"); + 8029420: 01020174 movhi r4,2053 + 8029424: 212a2f04 addi r4,r4,-22340 + 8029428: 80271780 call 8027178 + +#ifdef OS_PREEMPTIVE + for (i = 0; i <= MAX_RESID; i++) + 802942c: e03fff15 stw zero,-4(fp) + 8029430: 00001406 br 8029484 + { + resid_semaphore[i] = OSSemCreate(1); + 8029434: 01000044 movi r4,1 + 8029438: 80157740 call 8015774 + 802943c: 1009883a mov r4,r2 + 8029440: e0bfff17 ldw r2,-4(fp) + 8029444: 100690ba slli r3,r2,2 + 8029448: 008201b4 movhi r2,2054 + 802944c: 1885883a add r2,r3,r2 + 8029450: 11385b15 stw r4,-7828(r2) + if (!resid_semaphore[i]) + 8029454: e0bfff17 ldw r2,-4(fp) + 8029458: 100690ba slli r3,r2,2 + 802945c: 008201b4 movhi r2,2054 + 8029460: 1885883a add r2,r3,r2 + 8029464: 10b85b17 ldw r2,-7828(r2) + 8029468: 1000031e bne r2,zero,8029478 + panic("resid_semaphore create err"); + 802946c: 01020174 movhi r4,2053 + 8029470: 212a3604 addi r4,r4,-22312 + 8029474: 80271780 call 8027178 + for (i = 0; i <= MAX_RESID; i++) + 8029478: e0bfff17 ldw r2,-4(fp) + 802947c: 10800044 addi r2,r2,1 + 8029480: e0bfff15 stw r2,-4(fp) + 8029484: e0bfff17 ldw r2,-4(fp) + 8029488: 10800410 cmplti r2,r2,16 + 802948c: 103fe91e bne r2,zero,8029434 + } + for (i = 0; i <= MAX_SEMID; i++) + 8029490: e03fff15 stw zero,-4(fp) + 8029494: 00001406 br 80294e8 + { + app_semaphore[i] = OSSemCreate(1); + 8029498: 01000044 movi r4,1 + 802949c: 80157740 call 8015774 + 80294a0: 1009883a mov r4,r2 + 80294a4: e0bfff17 ldw r2,-4(fp) + 80294a8: 100690ba slli r3,r2,2 + 80294ac: 008201b4 movhi r2,2054 + 80294b0: 1885883a add r2,r3,r2 + 80294b4: 11386b15 stw r4,-7764(r2) + if (!app_semaphore[i]) + 80294b8: e0bfff17 ldw r2,-4(fp) + 80294bc: 100690ba slli r3,r2,2 + 80294c0: 008201b4 movhi r2,2054 + 80294c4: 1885883a add r2,r3,r2 + 80294c8: 10b86b17 ldw r2,-7764(r2) + 80294cc: 1000031e bne r2,zero,80294dc + panic("app_semaphore create err"); + 80294d0: 01020174 movhi r4,2053 + 80294d4: 212a3d04 addi r4,r4,-22284 + 80294d8: 80271780 call 8027178 + for (i = 0; i <= MAX_SEMID; i++) + 80294dc: e0bfff17 ldw r2,-4(fp) + 80294e0: 10800044 addi r2,r2,1 + 80294e4: e0bfff15 stw r2,-4(fp) + 80294e8: e0bfff17 ldw r2,-4(fp) + 80294ec: 10800190 cmplti r2,r2,6 + 80294f0: 103fe91e bne r2,zero,8029498 + +#ifndef TCPWAKE_RTOS + /* + * clear global_TCPwakeup_set + */ + for (i = 0; i < GLOBWAKE_SZ; i++) + 80294f4: e03fff15 stw zero,-4(fp) + 80294f8: 00001e06 br 8029574 + { + global_TCPwakeup_set[i].ctick = 0; + 80294fc: e0bfff17 ldw r2,-4(fp) + 8029500: 10c00324 muli r3,r2,12 + 8029504: 008201b4 movhi r2,2054 + 8029508: 1885883a add r2,r3,r2 + 802950c: 10381f15 stw zero,-8068(r2) + global_TCPwakeup_set[i].soc_event = NULL; + 8029510: e0bfff17 ldw r2,-4(fp) + 8029514: 10c00324 muli r3,r2,12 + 8029518: 008201b4 movhi r2,2054 + 802951c: 1885883a add r2,r3,r2 + 8029520: 10382015 stw zero,-8064(r2) + global_TCPwakeup_set[i].semaphore = OSSemCreate(0); + 8029524: 0009883a mov r4,zero + 8029528: 80157740 call 8015774 + 802952c: 1009883a mov r4,r2 + 8029530: e0bfff17 ldw r2,-4(fp) + 8029534: 10c00324 muli r3,r2,12 + 8029538: 008201b4 movhi r2,2054 + 802953c: 1885883a add r2,r3,r2 + 8029540: 11382115 stw r4,-8060(r2) + if (!global_TCPwakeup_set[i].semaphore) + 8029544: e0bfff17 ldw r2,-4(fp) + 8029548: 10c00324 muli r3,r2,12 + 802954c: 008201b4 movhi r2,2054 + 8029550: 1885883a add r2,r3,r2 + 8029554: 10b82117 ldw r2,-8060(r2) + 8029558: 1000031e bne r2,zero,8029568 + panic("globwake_semaphore create err"); + 802955c: 01020174 movhi r4,2053 + 8029560: 212a4404 addi r4,r4,-22256 + 8029564: 80271780 call 8027178 + for (i = 0; i < GLOBWAKE_SZ; i++) + 8029568: e0bfff17 ldw r2,-4(fp) + 802956c: 10800044 addi r2,r2,1 + 8029570: e0bfff15 stw r2,-4(fp) + 8029574: e0bfff17 ldw r2,-4(fp) + 8029578: 10800510 cmplti r2,r2,20 + 802957c: 103fdf1e bne r2,zero,80294fc + } + global_TCPwakeup_setIndx = 0; + 8029580: d0207c15 stw zero,-32272(gp) +#endif /* TCPWAKE_RTOS */ +} + 8029584: 0001883a nop + 8029588: e037883a mov sp,fp + 802958c: dfc00117 ldw ra,4(sp) + 8029590: df000017 ldw fp,0(sp) + 8029594: dec00204 addi sp,sp,8 + 8029598: f800283a ret + +0802959c : + * Return NULL if OK, else brief error message + */ + +char * +pre_task_setup() +{ + 802959c: deffff04 addi sp,sp,-4 + 80295a0: df000015 stw fp,0(sp) + 80295a4: d839883a mov fp,sp + write_leds(0); + write_7seg_raw(0x0000); +#endif + + /* preset buffer counts; may be overridden from command line */ + bigbufs = MAXBIGPKTS; + 80295a8: 00800784 movi r2,30 + 80295ac: d0a01815 stw r2,-32672(gp) + lilbufs = MAXLILPKTS; + 80295b0: 00800784 movi r2,30 + 80295b4: d0a01615 stw r2,-32680(gp) + bigbufsiz = BIGBUFSIZE; + 80295b8: 00818004 movi r2,1536 + 80295bc: d0a01915 stw r2,-32668(gp) + lilbufsiz = LILBUFSIZE; + 80295c0: 00802004 movi r2,128 + 80295c4: d0a01715 stw r2,-32676(gp) + + /* Install callback to prep_armintcp from prep_ifaces() */ + port_prep = prep_armintcp; + 80295c8: 008200f4 movhi r2,2051 + 80295cc: 10a58204 addi r2,r2,-27128 + 80295d0: d0a09615 stw r2,-32168(gp) +#endif /* NOTDEF */ + +#endif /* USE_PPP */ + + + return NULL; + 80295d4: 0005883a mov r2,zero +} + 80295d8: e037883a mov sp,fp + 80295dc: df000017 ldw fp,0(sp) + 80295e0: dec00104 addi sp,sp,4 + 80295e4: f800283a ret + +080295e8 : + * Return NULL if OK, else brief error message + */ + +char * +post_task_setup() +{ + 80295e8: deffff04 addi sp,sp,-4 + 80295ec: df000015 stw fp,0(sp) + 80295f0: d839883a mov fp,sp + return NULL; + 80295f4: 0005883a mov r2,zero +} + 80295f8: e037883a mov sp,fp + 80295fc: df000017 ldw fp,0(sp) + 8029600: dec00104 addi sp,sp,4 + 8029604: f800283a ret + +08029608 : + +#endif /* INCLUDE_NVPARMS */ + +int +prep_armintcp(int ifaces_found) +{ + 8029608: defffd04 addi sp,sp,-12 + 802960c: dfc00215 stw ra,8(sp) + 8029610: df000115 stw fp,4(sp) + 8029614: df000104 addi fp,sp,4 + 8029618: e13fff15 stw r4,-4(fp) + * Call iniche_devices_init, in alt_iniche_dev.c, + * to step through all devices and all their respective + * low-level initialization routines. + */ +#ifdef ALT_INICHE + ifaces_found = iniche_devices_init(ifaces_found); + 802961c: e13fff17 ldw r4,-4(fp) + 8029620: 8022aa80 call 8022aa8 + 8029624: e0bfff15 stw r2,-4(fp) + +#ifdef USE_SLIP + ifaces_found = prep_slip(ifaces_found); +#endif + + return ifaces_found; + 8029628: e0bfff17 ldw r2,-4(fp) +} + 802962c: e037883a mov sp,fp + 8029630: dfc00117 ldw ra,4(sp) + 8029634: df000017 ldw fp,0(sp) + 8029638: dec00204 addi sp,sp,8 + 802963c: f800283a ret + +08029640 : +#endif + + +char * +npalloc_base(unsigned size, int cacheable) +{ + 8029640: defff804 addi sp,sp,-32 + 8029644: dfc00715 stw ra,28(sp) + 8029648: df000615 stw fp,24(sp) + 802964c: df000604 addi fp,sp,24 + 8029650: e13ffb15 stw r4,-20(fp) + 8029654: e17ffa15 stw r5,-24(fp) +char * ptr; +void *(*alloc_rtn)(size_t size) = cacheable ? malloc : alt_uncached_malloc; + 8029658: e0bffa17 ldw r2,-24(fp) + 802965c: 10000326 beq r2,zero,802966c + 8029660: 00820134 movhi r2,2052 + 8029664: 108b2604 addi r2,r2,11416 + 8029668: 00000206 br 8029674 + 802966c: 00820134 movhi r2,2052 + 8029670: 10a02904 addi r2,r2,-32604 + 8029674: e0bffe15 stw r2,-8(fp) +#ifdef UCOS_II + INT8U err; +#endif + +#ifdef UCOS_II + OSSemPend(mheap_sem_ptr, 0, &err); + 8029678: d0a07f17 ldw r2,-32260(gp) + 802967c: e0fffcc4 addi r3,fp,-13 + 8029680: 180d883a mov r6,r3 + 8029684: 000b883a mov r5,zero + 8029688: 1009883a mov r4,r2 + 802968c: 8015a600 call 8015a60 + if(err) + 8029690: e0bffcc3 ldbu r2,-13(fp) + 8029694: 10803fcc andi r2,r2,255 + 8029698: 10001626 beq r2,zero,80296f4 + { + int errct = 0; + 802969c: e03fff15 stw zero,-4(fp) + + /* sometimes we get a "timeout" error even though we passed a zero + * to indicate we'll wait forever. When this happens, try again: + */ + while(err == 10) + 80296a0: 00001006 br 80296e4 + { + if(errct++ > 1000) + 80296a4: e0bfff17 ldw r2,-4(fp) + 80296a8: 10c00044 addi r3,r2,1 + 80296ac: e0ffff15 stw r3,-4(fp) + 80296b0: 1080fa50 cmplti r2,r2,1001 + 80296b4: 1000051e bne r2,zero,80296cc + { + panic("npalloc"); /* fatal? */ + 80296b8: 01020174 movhi r4,2053 + 80296bc: 212a4c04 addi r4,r4,-22224 + 80296c0: 80271780 call 8027178 + return NULL; + 80296c4: 0005883a mov r2,zero + 80296c8: 00001b06 br 8029738 + } + OSSemPend(mheap_sem_ptr, 0, &err); + 80296cc: d0a07f17 ldw r2,-32260(gp) + 80296d0: e0fffcc4 addi r3,fp,-13 + 80296d4: 180d883a mov r6,r3 + 80296d8: 000b883a mov r5,zero + 80296dc: 1009883a mov r4,r2 + 80296e0: 8015a600 call 8015a60 + while(err == 10) + 80296e4: e0bffcc3 ldbu r2,-13(fp) + 80296e8: 10803fcc andi r2,r2,255 + 80296ec: 108002a0 cmpeqi r2,r2,10 + 80296f0: 103fec1e bne r2,zero,80296a4 +#endif + +#ifdef MEM_WRAPPERS + ptr = wrap_alloc(size, alloc_rtn); +#else + ptr = (*alloc_rtn)(size); + 80296f4: e0bffe17 ldw r2,-8(fp) + 80296f8: e13ffb17 ldw r4,-20(fp) + 80296fc: 103ee83a callr r2 + 8029700: e0bffd15 stw r2,-12(fp) +#endif + +#ifdef UCOS_II + err = OSSemPost(mheap_sem_ptr); + 8029704: d0a07f17 ldw r2,-32260(gp) + 8029708: 1009883a mov r4,r2 + 802970c: 8015d840 call 8015d84 + 8029710: e0bffcc5 stb r2,-13(fp) +#endif + + if(!ptr) + 8029714: e0bffd17 ldw r2,-12(fp) + 8029718: 1000021e bne r2,zero,8029724 + return NULL; + 802971c: 0005883a mov r2,zero + 8029720: 00000506 br 8029738 + + MEMSET(ptr, 0, size); + 8029724: e1bffb17 ldw r6,-20(fp) + 8029728: 000b883a mov r5,zero + 802972c: e13ffd17 ldw r4,-12(fp) + 8029730: 80088e40 call 80088e4 + return ptr; + 8029734: e0bffd17 ldw r2,-12(fp) +} + 8029738: e037883a mov sp,fp + 802973c: dfc00117 ldw ra,4(sp) + 8029740: df000017 ldw fp,0(sp) + 8029744: dec00204 addi sp,sp,8 + 8029748: f800283a ret + +0802974c : + +void +npfree_base(void *ptr, int cacheable) +{ + 802974c: defff904 addi sp,sp,-28 + 8029750: dfc00615 stw ra,24(sp) + 8029754: df000515 stw fp,20(sp) + 8029758: df000504 addi fp,sp,20 + 802975c: e13ffc15 stw r4,-16(fp) + 8029760: e17ffb15 stw r5,-20(fp) + void (*free_rtn)(void *ptr) = cacheable ? free : alt_uncached_free; + 8029764: e0bffb17 ldw r2,-20(fp) + 8029768: 10000326 beq r2,zero,8029778 + 802976c: 00820134 movhi r2,2052 + 8029770: 108b2a04 addi r2,r2,11432 + 8029774: 00000206 br 8029780 + 8029778: 00820134 movhi r2,2052 + 802977c: 10a01804 addi r2,r2,-32672 + 8029780: e0bffe15 stw r2,-8(fp) +#ifdef UCOS_II + INT8U err; + + OSSemPend(mheap_sem_ptr, 0, &err); + 8029784: d0a07f17 ldw r2,-32260(gp) + 8029788: e0fffdc4 addi r3,fp,-9 + 802978c: 180d883a mov r6,r3 + 8029790: 000b883a mov r5,zero + 8029794: 1009883a mov r4,r2 + 8029798: 8015a600 call 8015a60 + if (err) + 802979c: e0bffdc3 ldbu r2,-9(fp) + 80297a0: 10803fcc andi r2,r2,255 + 80297a4: 10001526 beq r2,zero,80297fc + { + int errct = 0; + 80297a8: e03fff15 stw zero,-4(fp) + + /* sometimes we get a "timeout" error even though we passed a zero + * to indicate we'll wait forever. When this happens, try again: + */ + while (err == 10) + 80297ac: 00000f06 br 80297ec + { + if (errct++ > 1000) + 80297b0: e0bfff17 ldw r2,-4(fp) + 80297b4: 10c00044 addi r3,r2,1 + 80297b8: e0ffff15 stw r3,-4(fp) + 80297bc: 1080fa50 cmplti r2,r2,1001 + 80297c0: 1000041e bne r2,zero,80297d4 + { + panic("npfree"); /* fatal? */ + 80297c4: 01020174 movhi r4,2053 + 80297c8: 212a4e04 addi r4,r4,-22216 + 80297cc: 80271780 call 8027178 + 80297d0: 00001106 br 8029818 + return; + } + OSSemPend(mheap_sem_ptr, 0, &err); + 80297d4: d0a07f17 ldw r2,-32260(gp) + 80297d8: e0fffdc4 addi r3,fp,-9 + 80297dc: 180d883a mov r6,r3 + 80297e0: 000b883a mov r5,zero + 80297e4: 1009883a mov r4,r2 + 80297e8: 8015a600 call 8015a60 + while (err == 10) + 80297ec: e0bffdc3 ldbu r2,-9(fp) + 80297f0: 10803fcc andi r2,r2,255 + 80297f4: 108002a0 cmpeqi r2,r2,10 + 80297f8: 103fed1e bne r2,zero,80297b0 + } + +#ifdef MEM_WRAPPERS + wrap_free((char*)ptr, free_rtn); +#else + (*free_rtn)(ptr); + 80297fc: e0bffe17 ldw r2,-8(fp) + 8029800: e13ffc17 ldw r4,-16(fp) + 8029804: 103ee83a callr r2 +#endif + + err = OSSemPost(mheap_sem_ptr); + 8029808: d0a07f17 ldw r2,-32260(gp) + 802980c: 1009883a mov r4,r2 + 8029810: 8015d840 call 8015d84 + 8029814: e0bffdc5 stb r2,-9(fp) +#else + (*free_rtn)(ptr); +#endif +#endif + +} + 8029818: e037883a mov sp,fp + 802981c: dfc00117 ldw ra,4(sp) + 8029820: df000017 ldw fp,0(sp) + 8029824: dec00204 addi sp,sp,8 + 8029828: f800283a ret + +0802982c : + +char * +npalloc(unsigned size) +{ + 802982c: defffd04 addi sp,sp,-12 + 8029830: dfc00215 stw ra,8(sp) + 8029834: df000115 stw fp,4(sp) + 8029838: df000104 addi fp,sp,4 + 802983c: e13fff15 stw r4,-4(fp) + return npalloc_base(size, 1); + 8029840: 01400044 movi r5,1 + 8029844: e13fff17 ldw r4,-4(fp) + 8029848: 80296400 call 8029640 +} + 802984c: e037883a mov sp,fp + 8029850: dfc00117 ldw ra,4(sp) + 8029854: df000017 ldw fp,0(sp) + 8029858: dec00204 addi sp,sp,8 + 802985c: f800283a ret + +08029860 : + +void +npfree(void *ptr) +{ + 8029860: defffd04 addi sp,sp,-12 + 8029864: dfc00215 stw ra,8(sp) + 8029868: df000115 stw fp,4(sp) + 802986c: df000104 addi fp,sp,4 + 8029870: e13fff15 stw r4,-4(fp) + if(ptr) { + 8029874: e0bfff17 ldw r2,-4(fp) + 8029878: 10000326 beq r2,zero,8029888 + npfree_base(ptr, 1); + 802987c: 01400044 movi r5,1 + 8029880: e13fff17 ldw r4,-4(fp) + 8029884: 802974c0 call 802974c + } +} + 8029888: 0001883a nop + 802988c: e037883a mov sp,fp + 8029890: dfc00117 ldw ra,4(sp) + 8029894: df000017 ldw fp,0(sp) + 8029898: dec00204 addi sp,sp,8 + 802989c: f800283a ret + +080298a0 : + * contains macro definitions that assign specific memory + * allocation calls to these routines. + */ +#ifdef ALT_INICHE +char * ncpalloc(unsigned size) +{ + 80298a0: defffd04 addi sp,sp,-12 + 80298a4: dfc00215 stw ra,8(sp) + 80298a8: df000115 stw fp,4(sp) + 80298ac: df000104 addi fp,sp,4 + 80298b0: e13fff15 stw r4,-4(fp) + return npalloc_base(size, 0); + 80298b4: 000b883a mov r5,zero + 80298b8: e13fff17 ldw r4,-4(fp) + 80298bc: 80296400 call 8029640 +} + 80298c0: e037883a mov sp,fp + 80298c4: dfc00117 ldw ra,4(sp) + 80298c8: df000017 ldw fp,0(sp) + 80298cc: dec00204 addi sp,sp,8 + 80298d0: f800283a ret + +080298d4 : + +void ncpfree(void *ptr) +{ + 80298d4: defffd04 addi sp,sp,-12 + 80298d8: dfc00215 stw ra,8(sp) + 80298dc: df000115 stw fp,4(sp) + 80298e0: df000104 addi fp,sp,4 + 80298e4: e13fff15 stw r4,-4(fp) + if(ptr) { + 80298e8: e0bfff17 ldw r2,-4(fp) + 80298ec: 10000326 beq r2,zero,80298fc + npfree_base(ptr, 0); + 80298f0: 000b883a mov r5,zero + 80298f4: e13fff17 ldw r4,-4(fp) + 80298f8: 802974c0 call 802974c + } +} + 80298fc: 0001883a nop + 8029900: e037883a mov sp,fp + 8029904: dfc00117 ldw ra,4(sp) + 8029908: df000017 ldw fp,0(sp) + 802990c: dec00204 addi sp,sp,8 + 8029910: f800283a ret + +08029914 : + * RETURNS: + */ + +struct protosw * +pffindtype(int domain, int type) +{ + 8029914: defffc04 addi sp,sp,-16 + 8029918: dfc00315 stw ra,12(sp) + 802991c: df000215 stw fp,8(sp) + 8029920: df000204 addi fp,sp,8 + 8029924: e13fff15 stw r4,-4(fp) + 8029928: e17ffe15 stw r5,-8(fp) + + /* check that the passed domain is vaid for the build */ + if (domain != AF_INET) + 802992c: e0bfff17 ldw r2,-4(fp) + 8029930: 108000a0 cmpeqi r2,r2,2 + 8029934: 1000031e bne r2,zero,8029944 + { +#ifdef IP_V6 + if(domain != AF_INET6) +#endif + { + dtrap(); /* programming error */ + 8029938: 8028cd40 call 8028cd4 + return NULL; + 802993c: 0005883a mov r2,zero + 8029940: 00001306 br 8029990 + } + } + + if (type == SOCK_STREAM) + 8029944: e0bffe17 ldw r2,-8(fp) + 8029948: 10800058 cmpnei r2,r2,1 + 802994c: 1000031e bne r2,zero,802995c + return &tcp_protosw; + 8029950: 00820174 movhi r2,2053 + 8029954: 10b1f804 addi r2,r2,-14368 + 8029958: 00000d06 br 8029990 +#ifdef UDP_SOCKETS + else if(type == SOCK_DGRAM) + 802995c: e0bffe17 ldw r2,-8(fp) + 8029960: 10800098 cmpnei r2,r2,2 + 8029964: 1000031e bne r2,zero,8029974 + return &udp_protosw; + 8029968: 00820174 movhi r2,2053 + 802996c: 10b1fe04 addi r2,r2,-14344 + 8029970: 00000706 br 8029990 +#endif /* UDP_SOCKETS */ +#ifdef IP_RAW + else if(type == SOCK_RAW) + 8029974: e0bffe17 ldw r2,-8(fp) + 8029978: 108000d8 cmpnei r2,r2,3 + 802997c: 1000031e bne r2,zero,802998c + return &rawip_protosw; + 8029980: 00820174 movhi r2,2053 + 8029984: 10b20404 addi r2,r2,-14320 + 8029988: 00000106 br 8029990 +#endif /* IP_RAW */ + else + return NULL; + 802998c: 0005883a mov r2,zero +} + 8029990: e037883a mov sp,fp + 8029994: dfc00117 ldw ra,4(sp) + 8029998: df000017 ldw fp,0(sp) + 802999c: dec00204 addi sp,sp,8 + 80299a0: f800283a ret + +080299a4 : + * RETURNS: + */ + +struct protosw * +pffindproto(int domain, int protocol, int type) +{ + 80299a4: defffb04 addi sp,sp,-20 + 80299a8: dfc00415 stw ra,16(sp) + 80299ac: df000315 stw fp,12(sp) + 80299b0: df000304 addi fp,sp,12 + 80299b4: e13fff15 stw r4,-4(fp) + 80299b8: e17ffe15 stw r5,-8(fp) + 80299bc: e1bffd15 stw r6,-12(fp) +#ifdef IP_RAW + if (type == SOCK_RAW) + 80299c0: e0bffd17 ldw r2,-12(fp) + 80299c4: 108000d8 cmpnei r2,r2,3 + 80299c8: 1000041e bne r2,zero,80299dc + return(pffindtype(domain, type)); + 80299cc: e17ffd17 ldw r5,-12(fp) + 80299d0: e13fff17 ldw r4,-4(fp) + 80299d4: 80299140 call 8029914 + 80299d8: 00002006 br 8029a5c +#endif + + switch (protocol) + 80299dc: e0bffe17 ldw r2,-8(fp) + 80299e0: 108001a0 cmpeqi r2,r2,6 + 80299e4: 1000061e bne r2,zero,8029a00 + 80299e8: e0bffe17 ldw r2,-8(fp) + 80299ec: 10800460 cmpeqi r2,r2,17 + 80299f0: 1000091e bne r2,zero,8029a18 + 80299f4: e0bffe17 ldw r2,-8(fp) + 80299f8: 10001026 beq r2,zero,8029a3c + 80299fc: 00000c06 br 8029a30 + { +#ifdef BSD_SOCKETS + case IPPROTO_TCP: + if (type == SOCK_STREAM) + 8029a00: e0bffd17 ldw r2,-12(fp) + 8029a04: 10800058 cmpnei r2,r2,1 + 8029a08: 10000e26 beq r2,zero,8029a44 + break; + /* IPPROTO_TCP protocol on non-SOCK_STREAM type socket */ + dtrap(); + 8029a0c: 8028cd40 call 8028cd4 + return NULL; + 8029a10: 0005883a mov r2,zero + 8029a14: 00001106 br 8029a5c + case IPPROTO_UDP: + if (type == SOCK_DGRAM) + 8029a18: e0bffd17 ldw r2,-12(fp) + 8029a1c: 10800098 cmpnei r2,r2,2 + 8029a20: 10000a26 beq r2,zero,8029a4c + break; + /* IPPROTO_UDP protocol on non-SOCK_DGRAM type socket */ + dtrap(); + 8029a24: 8028cd40 call 8028cd4 + return NULL; + 8029a28: 0005883a mov r2,zero + 8029a2c: 00000b06 br 8029a5c + case 0: + /* let protocol default based on socket type */ + break; + default: + /* unknown/unsupported protocol on socket */ + dtrap(); + 8029a30: 8028cd40 call 8028cd4 + return NULL; + 8029a34: 0005883a mov r2,zero + 8029a38: 00000806 br 8029a5c + break; + 8029a3c: 0001883a nop + 8029a40: 00000306 br 8029a50 + break; + 8029a44: 0001883a nop + 8029a48: 00000106 br 8029a50 + break; + 8029a4c: 0001883a nop + } + return(pffindtype(domain, type)); /* map to findtype */ + 8029a50: e17ffd17 ldw r5,-12(fp) + 8029a54: e13fff17 ldw r4,-4(fp) + 8029a58: 80299140 call 8029914 +} + 8029a5c: e037883a mov sp,fp + 8029a60: dfc00117 ldw ra,4(sp) + 8029a64: df000017 ldw fp,0(sp) + 8029a68: dec00204 addi sp,sp,8 + 8029a6c: f800283a ret + +08029a70 : + * RETURNS: + */ + +struct mbuf * +m_getnbuf(int type, int len) +{ + 8029a70: defffa04 addi sp,sp,-24 + 8029a74: dfc00515 stw ra,20(sp) + 8029a78: df000415 stw fp,16(sp) + 8029a7c: df000404 addi fp,sp,16 + 8029a80: e13ffd15 stw r4,-12(fp) + 8029a84: e17ffc15 stw r5,-16(fp) + struct mbuf * m; + PACKET pkt = NULL; + 8029a88: e03fff15 stw zero,-4(fp) + +#ifdef NPDEBUG + if (type < MT_RXDATA || type > MT_IFADDR) + 8029a8c: e0bffd17 ldw r2,-12(fp) + 8029a90: 0080030e bge zero,r2,8029aa0 + 8029a94: e0bffd17 ldw r2,-12(fp) + 8029a98: 10800390 cmplti r2,r2,14 + 8029a9c: 1000011e bne r2,zero,8029aa4 + { + dtrap(); /* is this OK? */ + 8029aa0: 8028cd40 call 8028cd4 + } +#endif + + /* if caller has data (len >= 0), we need to allocate + * a packet buffer; else all we need is the mbuf */ + if (len != 0) + 8029aa4: e0bffc17 ldw r2,-16(fp) + 8029aa8: 10000d26 beq r2,zero,8029ae0 + { + LOCK_NET_RESOURCE(FREEQ_RESID); + 8029aac: 01000084 movi r4,2 + 8029ab0: 8028f380 call 8028f38 + pkt = pk_alloc(len + HDRSLEN); + 8029ab4: e0bffc17 ldw r2,-16(fp) + 8029ab8: 10800e04 addi r2,r2,56 + 8029abc: 1009883a mov r4,r2 + 8029ac0: 80284340 call 8028434 + 8029ac4: e0bfff15 stw r2,-4(fp) + + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8029ac8: 01000084 movi r4,2 + 8029acc: 8028ff40 call 8028ff4 + if (!pkt) + 8029ad0: e0bfff17 ldw r2,-4(fp) + 8029ad4: 1000021e bne r2,zero,8029ae0 + return NULL; + 8029ad8: 0005883a mov r2,zero + 8029adc: 00004106 br 8029be4 + } + + m = (struct mbuf *)getq(&mfreeq); + 8029ae0: 010201b4 movhi r4,2054 + 8029ae4: 21388a04 addi r4,r4,-7640 + 8029ae8: 80288d80 call 80288d8 + 8029aec: e0bffe15 stw r2,-8(fp) + if (!m) + 8029af0: e0bffe17 ldw r2,-8(fp) + 8029af4: 10000a1e bne r2,zero,8029b20 + { + if (pkt) + 8029af8: e0bfff17 ldw r2,-4(fp) + 8029afc: 10000626 beq r2,zero,8029b18 + { + LOCK_NET_RESOURCE(FREEQ_RESID); + 8029b00: 01000084 movi r4,2 + 8029b04: 8028f380 call 8028f38 + pk_free(pkt); + 8029b08: e13fff17 ldw r4,-4(fp) + 8029b0c: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8029b10: 01000084 movi r4,2 + 8029b14: 8028ff40 call 8028ff4 + } + return NULL; + 8029b18: 0005883a mov r2,zero + 8029b1c: 00003106 br 8029be4 + } + m->m_type = type; + 8029b20: e0bffe17 ldw r2,-8(fp) + 8029b24: e0fffd17 ldw r3,-12(fp) + 8029b28: 10c00815 stw r3,32(r2) + if (len == 0) + 8029b2c: e0bffc17 ldw r2,-16(fp) + 8029b30: 1000071e bne r2,zero,8029b50 + { + m->pkt = NULL; + 8029b34: e0bffe17 ldw r2,-8(fp) + 8029b38: 10000115 stw zero,4(r2) + m->m_base = NULL; /* caller better fill these in! */ + 8029b3c: e0bffe17 ldw r2,-8(fp) + 8029b40: 10000415 stw zero,16(r2) + m->m_memsz = 0; + 8029b44: e0bffe17 ldw r2,-8(fp) + 8029b48: 10000515 stw zero,20(r2) + 8029b4c: 00001506 br 8029ba4 + } + else + { + m->pkt = pkt; + 8029b50: e0bffe17 ldw r2,-8(fp) + 8029b54: e0ffff17 ldw r3,-4(fp) + 8029b58: 10c00115 stw r3,4(r2) + /* set m_data to the part where tcp data should go */ + m->m_base = m->m_data = pkt->nb_prot = pkt->nb_buff + HDRSLEN; + 8029b5c: e0bfff17 ldw r2,-4(fp) + 8029b60: 10800117 ldw r2,4(r2) + 8029b64: 10c00e04 addi r3,r2,56 + 8029b68: e0bfff17 ldw r2,-4(fp) + 8029b6c: 10c00315 stw r3,12(r2) + 8029b70: e0bfff17 ldw r2,-4(fp) + 8029b74: 10c00317 ldw r3,12(r2) + 8029b78: e0bffe17 ldw r2,-8(fp) + 8029b7c: 10c00315 stw r3,12(r2) + 8029b80: e0bffe17 ldw r2,-8(fp) + 8029b84: 10c00317 ldw r3,12(r2) + 8029b88: e0bffe17 ldw r2,-8(fp) + 8029b8c: 10c00415 stw r3,16(r2) + m->m_memsz = pkt->nb_blen - HDRSLEN; + 8029b90: e0bfff17 ldw r2,-4(fp) + 8029b94: 10800217 ldw r2,8(r2) + 8029b98: 10fff204 addi r3,r2,-56 + 8029b9c: e0bffe17 ldw r2,-8(fp) + 8029ba0: 10c00515 stw r3,20(r2) + } + m->m_len = 0; + 8029ba4: e0bffe17 ldw r2,-8(fp) + 8029ba8: 10000215 stw zero,8(r2) + m->m_next = m->m_act = NULL; + 8029bac: e0bffe17 ldw r2,-8(fp) + 8029bb0: 10000715 stw zero,28(r2) + 8029bb4: e0bffe17 ldw r2,-8(fp) + 8029bb8: 10c00717 ldw r3,28(r2) + 8029bbc: e0bffe17 ldw r2,-8(fp) + 8029bc0: 10c00615 stw r3,24(r2) + mbstat.allocs++; /* maintain local statistics */ + 8029bc4: d0a08317 ldw r2,-32244(gp) + 8029bc8: 10800044 addi r2,r2,1 + 8029bcc: d0a08315 stw r2,-32244(gp) + putq(&mbufq, (qp)m); + 8029bd0: e17ffe17 ldw r5,-8(fp) + 8029bd4: 010201b4 movhi r4,2054 + 8029bd8: 21388504 addi r4,r4,-7660 + 8029bdc: 80289900 call 8028990 + return m; + 8029be0: e0bffe17 ldw r2,-8(fp) +} + 8029be4: e037883a mov sp,fp + 8029be8: dfc00117 ldw ra,4(sp) + 8029bec: df000017 ldw fp,0(sp) + 8029bf0: dec00204 addi sp,sp,8 + 8029bf4: f800283a ret + +08029bf8 : + */ + + +struct mbuf * +m_free(struct mbuf * m) +{ + 8029bf8: defffc04 addi sp,sp,-16 + 8029bfc: dfc00315 stw ra,12(sp) + 8029c00: df000215 stw fp,8(sp) + 8029c04: df000204 addi fp,sp,8 + 8029c08: e13ffe15 stw r4,-8(fp) + struct mbuf * nextptr; + +#ifdef NPDEBUG + if (mbufq.q_len < 1) + 8029c0c: 008201b4 movhi r2,2054 + 8029c10: 10b88717 ldw r2,-7652(r2) + 8029c14: 00800316 blt zero,r2,8029c24 + panic("mfree: q_len"); + 8029c18: 01020174 movhi r4,2053 + 8029c1c: 212a5004 addi r4,r4,-22208 + 8029c20: 80271780 call 8027178 + + if (m->m_type < MT_RXDATA || m->m_type > MT_IFADDR) + 8029c24: e0bffe17 ldw r2,-8(fp) + 8029c28: 10800817 ldw r2,32(r2) + 8029c2c: 0080040e bge zero,r2,8029c40 + 8029c30: e0bffe17 ldw r2,-8(fp) + 8029c34: 10800817 ldw r2,32(r2) + 8029c38: 10800390 cmplti r2,r2,14 + 8029c3c: 10000a1e bne r2,zero,8029c68 + { + if (m->m_type == MT_FREE) + 8029c40: e0bffe17 ldw r2,-8(fp) + 8029c44: 10800817 ldw r2,32(r2) + 8029c48: 1000041e bne r2,zero,8029c5c + { + dtrap(); /* debug double free of mbuf by tcp_in() */ + 8029c4c: 8028cd40 call 8028cd4 + return m->m_next; /* seems harmless, though.... */ + 8029c50: e0bffe17 ldw r2,-8(fp) + 8029c54: 10800617 ldw r2,24(r2) + 8029c58: 00002306 br 8029ce8 + } + else + panic("m_free: type"); + 8029c5c: 01020174 movhi r4,2053 + 8029c60: 212a5404 addi r4,r4,-22192 + 8029c64: 80271780 call 8027178 + } +#endif /* NPDEBUG */ + + nextptr = m->m_next; /* remember value to return */ + 8029c68: e0bffe17 ldw r2,-8(fp) + 8029c6c: 10800617 ldw r2,24(r2) + 8029c70: e0bfff15 stw r2,-4(fp) + + if (qdel(&mbufq, m) == NULL) + 8029c74: e17ffe17 ldw r5,-8(fp) + 8029c78: 010201b4 movhi r4,2054 + 8029c7c: 21388504 addi r4,r4,-7660 + 8029c80: 8028a400 call 8028a40 + 8029c84: 1000031e bne r2,zero,8029c94 + panic("m_free: missing"); + 8029c88: 01020174 movhi r4,2053 + 8029c8c: 212a5804 addi r4,r4,-22176 + 8029c90: 80271780 call 8027178 + + m->m_type = MT_FREE; /* this may seem silly, but helps error checking */ + 8029c94: e0bffe17 ldw r2,-8(fp) + 8029c98: 10000815 stw zero,32(r2) + + if (m->pkt) + 8029c9c: e0bffe17 ldw r2,-8(fp) + 8029ca0: 10800117 ldw r2,4(r2) + 8029ca4: 10000826 beq r2,zero,8029cc8 + { + LOCK_NET_RESOURCE(FREEQ_RESID); + 8029ca8: 01000084 movi r4,2 + 8029cac: 8028f380 call 8028f38 + pk_free(m->pkt); /* free up the netport buffer */ + 8029cb0: e0bffe17 ldw r2,-8(fp) + 8029cb4: 10800117 ldw r2,4(r2) + 8029cb8: 1009883a mov r4,r2 + 8029cbc: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8029cc0: 01000084 movi r4,2 + 8029cc4: 8028ff40 call 8028ff4 + } + mbstat.frees++; + 8029cc8: d0a08417 ldw r2,-32240(gp) + 8029ccc: 10800044 addi r2,r2,1 + 8029cd0: d0a08415 stw r2,-32240(gp) + putq(&mfreeq, (qp)m); + 8029cd4: e17ffe17 ldw r5,-8(fp) + 8029cd8: 010201b4 movhi r4,2054 + 8029cdc: 21388a04 addi r4,r4,-7640 + 8029ce0: 80289900 call 8028990 + return nextptr; + 8029ce4: e0bfff17 ldw r2,-4(fp) +} + 8029ce8: e037883a mov sp,fp + 8029cec: dfc00117 ldw ra,4(sp) + 8029cf0: df000017 ldw fp,0(sp) + 8029cf4: dec00204 addi sp,sp,8 + 8029cf8: f800283a ret + +08029cfc : + * RETURNS: + */ + +void +m_freem(struct mbuf * m) +{ + 8029cfc: defffd04 addi sp,sp,-12 + 8029d00: dfc00215 stw ra,8(sp) + 8029d04: df000115 stw fp,4(sp) + 8029d08: df000104 addi fp,sp,4 + 8029d0c: e13fff15 stw r4,-4(fp) + while (m != NULL) + 8029d10: 00000306 br 8029d20 + m = m_free(m); + 8029d14: e13fff17 ldw r4,-4(fp) + 8029d18: 8029bf80 call 8029bf8 + 8029d1c: e0bfff15 stw r2,-4(fp) + while (m != NULL) + 8029d20: e0bfff17 ldw r2,-4(fp) + 8029d24: 103ffb1e bne r2,zero,8029d14 +} + 8029d28: 0001883a nop + 8029d2c: e037883a mov sp,fp + 8029d30: dfc00117 ldw ra,4(sp) + 8029d34: df000017 ldw fp,0(sp) + 8029d38: dec00204 addi sp,sp,8 + 8029d3c: f800283a ret + +08029d40 : + * RETURNS: + */ + +struct mbuf * +m_copy(struct mbuf * m, int off, int len) +{ + 8029d40: defff704 addi sp,sp,-36 + 8029d44: dfc00815 stw ra,32(sp) + 8029d48: df000715 stw fp,28(sp) + 8029d4c: df000704 addi fp,sp,28 + 8029d50: e13ffb15 stw r4,-20(fp) + 8029d54: e17ffa15 stw r5,-24(fp) + 8029d58: e1bff915 stw r6,-28(fp) + struct mbuf * nb, * head, * tail; + int tocopy; + + if (len == 0) /* nothing to do */ + 8029d5c: e0bff917 ldw r2,-28(fp) + 8029d60: 1000021e bne r2,zero,8029d6c + return NULL; + 8029d64: 0005883a mov r2,zero + 8029d68: 0000a606 br 802a004 + +#ifdef NPDEBUG + /* sanity test parms */ + if (off < 0 || (len < 0 && len != M_COPYALL)) + 8029d6c: e0bffa17 ldw r2,-24(fp) + 8029d70: 10000516 blt r2,zero,8029d88 + 8029d74: e0bff917 ldw r2,-28(fp) + 8029d78: 1000180e bge r2,zero,8029ddc + 8029d7c: e0bff917 ldw r2,-28(fp) + 8029d80: 10bfffe0 cmpeqi r2,r2,-1 + 8029d84: 1000151e bne r2,zero,8029ddc + { + dtrap(); + 8029d88: 8028cd40 call 8028cd4 + return NULL; + 8029d8c: 0005883a mov r2,zero + 8029d90: 00009c06 br 802a004 +#endif /* NPDEBUG */ + + /* move forward through mbuf q to "off" point */ + while (off > 0) + { + if (!m) + 8029d94: e0bffb17 ldw r2,-20(fp) + 8029d98: 1000031e bne r2,zero,8029da8 + { + dtrap(); + 8029d9c: 8028cd40 call 8028cd4 + return NULL; + 8029da0: 0005883a mov r2,zero + 8029da4: 00009706 br 802a004 + } + if (off < (int)m->m_len) + 8029da8: e0bffb17 ldw r2,-20(fp) + 8029dac: 10800217 ldw r2,8(r2) + 8029db0: 1007883a mov r3,r2 + 8029db4: e0bffa17 ldw r2,-24(fp) + 8029db8: 10c00b16 blt r2,r3,8029de8 + break; + off -= m->m_len; + 8029dbc: e0fffa17 ldw r3,-24(fp) + 8029dc0: e0bffb17 ldw r2,-20(fp) + 8029dc4: 10800217 ldw r2,8(r2) + 8029dc8: 1885c83a sub r2,r3,r2 + 8029dcc: e0bffa15 stw r2,-24(fp) + m = m->m_next; + 8029dd0: e0bffb17 ldw r2,-20(fp) + 8029dd4: 10800617 ldw r2,24(r2) + 8029dd8: e0bffb15 stw r2,-20(fp) + while (off > 0) + 8029ddc: e0bffa17 ldw r2,-24(fp) + 8029de0: 00bfec16 blt zero,r2,8029d94 + 8029de4: 00000106 br 8029dec + break; + 8029de8: 0001883a nop + } + + head = tail = NULL; + 8029dec: e03ffd15 stw zero,-12(fp) + 8029df0: e0bffd17 ldw r2,-12(fp) + 8029df4: e0bffe15 stw r2,-8(fp) + + while (len > 0) + 8029df8: 00007806 br 8029fdc + { + if (m == NULL) /* at end of queue? */ + 8029dfc: e0bffb17 ldw r2,-20(fp) + 8029e00: 1000051e bne r2,zero,8029e18 + { + panic("m_copy: bad len"); + 8029e04: 01020174 movhi r4,2053 + 8029e08: 212a5c04 addi r4,r4,-22160 + 8029e0c: 80271780 call 8027178 + return NULL; + 8029e10: 0005883a mov r2,zero + 8029e14: 00007b06 br 802a004 + } + tocopy = (int)MIN(len, (int)(m->m_len - off)); + 8029e18: e0bffb17 ldw r2,-20(fp) + 8029e1c: 10c00217 ldw r3,8(r2) + 8029e20: e0bffa17 ldw r2,-24(fp) + 8029e24: 1885c83a sub r2,r3,r2 + 8029e28: 1007883a mov r3,r2 + 8029e2c: e0bff917 ldw r2,-28(fp) + 8029e30: 1880010e bge r3,r2,8029e38 + 8029e34: 1805883a mov r2,r3 + 8029e38: e0bffc15 stw r2,-16(fp) + * ALIGN_TYPE, so if the offset isn't aligned, we must + * copy the buffer instead of cloning it. + * Also, don't permit multiple clones; they sometimes + * lead to corrupted data. + */ + if ((off & (ALIGN_TYPE - 1)) || + 8029e3c: e0bffa17 ldw r2,-24(fp) + 8029e40: 108000cc andi r2,r2,3 + 8029e44: 1000051e bne r2,zero,8029e5c + (m->pkt->inuse != 1)) + 8029e48: e0bffb17 ldw r2,-20(fp) + 8029e4c: 10800117 ldw r2,4(r2) + 8029e50: 10800917 ldw r2,36(r2) + if ((off & (ALIGN_TYPE - 1)) || + 8029e54: 10800060 cmpeqi r2,r2,1 + 8029e58: 1000211e bne r2,zero,8029ee0 + { + if ((nb = m_getwithdata (m->m_type, tocopy)) == NULL) + 8029e5c: e0bffb17 ldw r2,-20(fp) + 8029e60: 10800817 ldw r2,32(r2) + 8029e64: e17ffc17 ldw r5,-16(fp) + 8029e68: 1009883a mov r4,r2 + 8029e6c: 8029a700 call 8029a70 + 8029e70: e0bfff15 stw r2,-4(fp) + 8029e74: e0bfff17 ldw r2,-4(fp) + 8029e78: 10005c26 beq r2,zero,8029fec + goto nospace; + MEMCPY(nb->m_data, m->m_data+off, tocopy); + 8029e7c: e0bfff17 ldw r2,-4(fp) + 8029e80: 11000317 ldw r4,12(r2) + 8029e84: e0bffb17 ldw r2,-20(fp) + 8029e88: 10c00317 ldw r3,12(r2) + 8029e8c: e0bffa17 ldw r2,-24(fp) + 8029e90: 1885883a add r2,r3,r2 + 8029e94: e0fffc17 ldw r3,-16(fp) + 8029e98: 180d883a mov r6,r3 + 8029e9c: 100b883a mov r5,r2 + 8029ea0: 80086b80 call 80086b8 + nb->m_len = tocopy; /* set length of data we just moved into new mbuf */ + 8029ea4: e0fffc17 ldw r3,-16(fp) + 8029ea8: e0bfff17 ldw r2,-4(fp) + 8029eac: 10c00215 stw r3,8(r2) + + tcpstat.tcps_mcopies++; + 8029eb0: 008201b4 movhi r2,2054 + 8029eb4: 10b8d217 ldw r2,-7352(r2) + 8029eb8: 10c00044 addi r3,r2,1 + 8029ebc: 008201b4 movhi r2,2054 + 8029ec0: 10f8d215 stw r3,-7352(r2) + tcpstat.tcps_mcopiedbytes += tocopy; + 8029ec4: 008201b4 movhi r2,2054 + 8029ec8: 10f8d417 ldw r3,-7344(r2) + 8029ecc: e0bffc17 ldw r2,-16(fp) + 8029ed0: 1887883a add r3,r3,r2 + 8029ed4: 008201b4 movhi r2,2054 + 8029ed8: 10f8d415 stw r3,-7344(r2) + 8029edc: 00002d06 br 8029f94 + { + /* Rather than memcpy every mbuf's data, "clone" the data by + * making a duplicate of the mbufs involved and bumping the + * inuse count of the actual packet structs + */ + if ((nb = m_getwithdata (m->m_type, 0)) == NULL) + 8029ee0: e0bffb17 ldw r2,-20(fp) + 8029ee4: 10800817 ldw r2,32(r2) + 8029ee8: 000b883a mov r5,zero + 8029eec: 1009883a mov r4,r2 + 8029ef0: 8029a700 call 8029a70 + 8029ef4: e0bfff15 stw r2,-4(fp) + 8029ef8: e0bfff17 ldw r2,-4(fp) + 8029efc: 10003d26 beq r2,zero,8029ff4 + goto nospace; + + m->pkt->inuse++; /* bump pkt use count to clone it */ + 8029f00: e0bffb17 ldw r2,-20(fp) + 8029f04: 10800117 ldw r2,4(r2) + 8029f08: 10c00917 ldw r3,36(r2) + 8029f0c: 18c00044 addi r3,r3,1 + 8029f10: 10c00915 stw r3,36(r2) + + /* set up new mbuf with pointers to cloned packet */ + nb->pkt = m->pkt; + 8029f14: e0bffb17 ldw r2,-20(fp) + 8029f18: 10c00117 ldw r3,4(r2) + 8029f1c: e0bfff17 ldw r2,-4(fp) + 8029f20: 10c00115 stw r3,4(r2) + nb->m_base = m->m_base; + 8029f24: e0bffb17 ldw r2,-20(fp) + 8029f28: 10c00417 ldw r3,16(r2) + 8029f2c: e0bfff17 ldw r2,-4(fp) + 8029f30: 10c00415 stw r3,16(r2) + nb->m_memsz = m->m_memsz; + 8029f34: e0bffb17 ldw r2,-20(fp) + 8029f38: 10c00517 ldw r3,20(r2) + 8029f3c: e0bfff17 ldw r2,-4(fp) + 8029f40: 10c00515 stw r3,20(r2) + nb->m_data = m->m_data + off; + 8029f44: e0bffb17 ldw r2,-20(fp) + 8029f48: 10c00317 ldw r3,12(r2) + 8029f4c: e0bffa17 ldw r2,-24(fp) + 8029f50: 1887883a add r3,r3,r2 + 8029f54: e0bfff17 ldw r2,-4(fp) + 8029f58: 10c00315 stw r3,12(r2) + nb->m_len = tocopy; + 8029f5c: e0fffc17 ldw r3,-16(fp) + 8029f60: e0bfff17 ldw r2,-4(fp) + 8029f64: 10c00215 stw r3,8(r2) + + tcpstat.tcps_mclones++; + 8029f68: 008201b4 movhi r2,2054 + 8029f6c: 10b8d317 ldw r2,-7348(r2) + 8029f70: 10c00044 addi r3,r2,1 + 8029f74: 008201b4 movhi r2,2054 + 8029f78: 10f8d315 stw r3,-7348(r2) + tcpstat.tcps_mclonedbytes += tocopy; + 8029f7c: 008201b4 movhi r2,2054 + 8029f80: 10f8d517 ldw r3,-7340(r2) + 8029f84: e0bffc17 ldw r2,-16(fp) + 8029f88: 1887883a add r3,r3,r2 + 8029f8c: 008201b4 movhi r2,2054 + 8029f90: 10f8d515 stw r3,-7340(r2) + } + + len -= tocopy; + 8029f94: e0fff917 ldw r3,-28(fp) + 8029f98: e0bffc17 ldw r2,-16(fp) + 8029f9c: 1885c83a sub r2,r3,r2 + 8029fa0: e0bff915 stw r2,-28(fp) + off = 0; + 8029fa4: e03ffa15 stw zero,-24(fp) + if (tail) /* head & tail are set by first pass thru loop */ + 8029fa8: e0bffd17 ldw r2,-12(fp) + 8029fac: 10000426 beq r2,zero,8029fc0 + tail->m_next = nb; + 8029fb0: e0bffd17 ldw r2,-12(fp) + 8029fb4: e0ffff17 ldw r3,-4(fp) + 8029fb8: 10c00615 stw r3,24(r2) + 8029fbc: 00000206 br 8029fc8 + else + head = nb; + 8029fc0: e0bfff17 ldw r2,-4(fp) + 8029fc4: e0bffe15 stw r2,-8(fp) + tail = nb; /* always make new mbuf the tail */ + 8029fc8: e0bfff17 ldw r2,-4(fp) + 8029fcc: e0bffd15 stw r2,-12(fp) + m = m->m_next; + 8029fd0: e0bffb17 ldw r2,-20(fp) + 8029fd4: 10800617 ldw r2,24(r2) + 8029fd8: e0bffb15 stw r2,-20(fp) + while (len > 0) + 8029fdc: e0bff917 ldw r2,-28(fp) + 8029fe0: 00bf8616 blt zero,r2,8029dfc + + } + + return head; + 8029fe4: e0bffe17 ldw r2,-8(fp) + 8029fe8: 00000606 br 802a004 + goto nospace; + 8029fec: 0001883a nop + 8029ff0: 00000106 br 8029ff8 + goto nospace; + 8029ff4: 0001883a nop + +nospace: + m_freem (head); + 8029ff8: e13ffe17 ldw r4,-8(fp) + 8029ffc: 8029cfc0 call 8029cfc + return NULL; + 802a000: 0005883a mov r2,zero +} + 802a004: e037883a mov sp,fp + 802a008: dfc00117 ldw ra,4(sp) + 802a00c: df000017 ldw fp,0(sp) + 802a010: dec00204 addi sp,sp,8 + 802a014: f800283a ret + +0802a018 : + * RETURNS: + */ + +void +m_adj(struct mbuf * mp, int len) +{ + 802a018: defffb04 addi sp,sp,-20 + 802a01c: df000415 stw fp,16(sp) + 802a020: df000404 addi fp,sp,16 + 802a024: e13ffd15 stw r4,-12(fp) + 802a028: e17ffc15 stw r5,-16(fp) + struct mbuf * m; + int count; + + if ((m = mp) == NULL) + 802a02c: e0bffd17 ldw r2,-12(fp) + 802a030: e0bfff15 stw r2,-4(fp) + 802a034: e0bfff17 ldw r2,-4(fp) + 802a038: 10006226 beq r2,zero,802a1c4 + return; + + if (len >= 0) + 802a03c: e0bffc17 ldw r2,-16(fp) + 802a040: 10002216 blt r2,zero,802a0cc + { + while (m != NULL && len > 0) + 802a044: 00001c06 br 802a0b8 + { + if (m->m_len <= (unsigned)len) + 802a048: e0bfff17 ldw r2,-4(fp) + 802a04c: 10800217 ldw r2,8(r2) + 802a050: e0fffc17 ldw r3,-16(fp) + 802a054: 18800b36 bltu r3,r2,802a084 + { + len -= m->m_len; + 802a058: e0fffc17 ldw r3,-16(fp) + 802a05c: e0bfff17 ldw r2,-4(fp) + 802a060: 10800217 ldw r2,8(r2) + 802a064: 1885c83a sub r2,r3,r2 + 802a068: e0bffc15 stw r2,-16(fp) + m->m_len = 0; + 802a06c: e0bfff17 ldw r2,-4(fp) + 802a070: 10000215 stw zero,8(r2) + m = m->m_next; + 802a074: e0bfff17 ldw r2,-4(fp) + 802a078: 10800617 ldw r2,24(r2) + 802a07c: e0bfff15 stw r2,-4(fp) + 802a080: 00000d06 br 802a0b8 + } + else + { + m->m_len -= len; + 802a084: e0bfff17 ldw r2,-4(fp) + 802a088: 10c00217 ldw r3,8(r2) + 802a08c: e0bffc17 ldw r2,-16(fp) + 802a090: 1887c83a sub r3,r3,r2 + 802a094: e0bfff17 ldw r2,-4(fp) + 802a098: 10c00215 stw r3,8(r2) + m->m_data += len; + 802a09c: e0bfff17 ldw r2,-4(fp) + 802a0a0: 10c00317 ldw r3,12(r2) + 802a0a4: e0bffc17 ldw r2,-16(fp) + 802a0a8: 1887883a add r3,r3,r2 + 802a0ac: e0bfff17 ldw r2,-4(fp) + 802a0b0: 10c00315 stw r3,12(r2) + break; + 802a0b4: 00004406 br 802a1c8 + while (m != NULL && len > 0) + 802a0b8: e0bfff17 ldw r2,-4(fp) + 802a0bc: 10004226 beq r2,zero,802a1c8 + 802a0c0: e0bffc17 ldw r2,-16(fp) + 802a0c4: 00bfe016 blt zero,r2,802a048 + 802a0c8: 00003f06 br 802a1c8 + * calculating its length and finding the last mbuf. + * If the adjustment only affects this mbuf, then just + * adjust and return. Otherwise, rescan and truncate + * after the remaining size. + */ + len = -len; + 802a0cc: e0bffc17 ldw r2,-16(fp) + 802a0d0: 0085c83a sub r2,zero,r2 + 802a0d4: e0bffc15 stw r2,-16(fp) + count = 0; + 802a0d8: e03ffe15 stw zero,-8(fp) + for (;;) + { + count += m->m_len; + 802a0dc: e0bfff17 ldw r2,-4(fp) + 802a0e0: 10c00217 ldw r3,8(r2) + 802a0e4: e0bffe17 ldw r2,-8(fp) + 802a0e8: 1885883a add r2,r3,r2 + 802a0ec: e0bffe15 stw r2,-8(fp) + if (m->m_next == (struct mbuf *)0) + 802a0f0: e0bfff17 ldw r2,-4(fp) + 802a0f4: 10800617 ldw r2,24(r2) + 802a0f8: 10000426 beq r2,zero,802a10c + break; + m = m->m_next; + 802a0fc: e0bfff17 ldw r2,-4(fp) + 802a100: 10800617 ldw r2,24(r2) + 802a104: e0bfff15 stw r2,-4(fp) + count += m->m_len; + 802a108: 003ff406 br 802a0dc + break; + 802a10c: 0001883a nop + } + if (m->m_len >= (unsigned)len) + 802a110: e0bfff17 ldw r2,-4(fp) + 802a114: 10c00217 ldw r3,8(r2) + 802a118: e0bffc17 ldw r2,-16(fp) + 802a11c: 18800736 bltu r3,r2,802a13c + { + m->m_len -= len; + 802a120: e0bfff17 ldw r2,-4(fp) + 802a124: 10c00217 ldw r3,8(r2) + 802a128: e0bffc17 ldw r2,-16(fp) + 802a12c: 1887c83a sub r3,r3,r2 + 802a130: e0bfff17 ldw r2,-4(fp) + 802a134: 10c00215 stw r3,8(r2) + return; + 802a138: 00002306 br 802a1c8 + } + count -= len; + 802a13c: e0fffe17 ldw r3,-8(fp) + 802a140: e0bffc17 ldw r2,-16(fp) + 802a144: 1885c83a sub r2,r3,r2 + 802a148: e0bffe15 stw r2,-8(fp) + /* + * Correct length for chain is "count". + * Find the mbuf with last data, adjust its length, + * and toss data from remaining mbufs on chain. + */ + for (m = mp; m; m = m->m_next) + 802a14c: e0bffd17 ldw r2,-12(fp) + 802a150: e0bfff15 stw r2,-4(fp) + 802a154: 00001006 br 802a198 + { + if (m->m_len >= (unsigned)count) + 802a158: e0bfff17 ldw r2,-4(fp) + 802a15c: 10c00217 ldw r3,8(r2) + 802a160: e0bffe17 ldw r2,-8(fp) + 802a164: 18800436 bltu r3,r2,802a178 + { + m->m_len = count; + 802a168: e0fffe17 ldw r3,-8(fp) + 802a16c: e0bfff17 ldw r2,-4(fp) + 802a170: 10c00215 stw r3,8(r2) + break; + 802a174: 00000a06 br 802a1a0 + } + count -= m->m_len; + 802a178: e0fffe17 ldw r3,-8(fp) + 802a17c: e0bfff17 ldw r2,-4(fp) + 802a180: 10800217 ldw r2,8(r2) + 802a184: 1885c83a sub r2,r3,r2 + 802a188: e0bffe15 stw r2,-8(fp) + for (m = mp; m; m = m->m_next) + 802a18c: e0bfff17 ldw r2,-4(fp) + 802a190: 10800617 ldw r2,24(r2) + 802a194: e0bfff15 stw r2,-4(fp) + 802a198: e0bfff17 ldw r2,-4(fp) + 802a19c: 103fee1e bne r2,zero,802a158 + } + while ((m = m->m_next) != (struct mbuf *)NULL) + 802a1a0: 00000206 br 802a1ac + m->m_len = 0; + 802a1a4: e0bfff17 ldw r2,-4(fp) + 802a1a8: 10000215 stw zero,8(r2) + while ((m = m->m_next) != (struct mbuf *)NULL) + 802a1ac: e0bfff17 ldw r2,-4(fp) + 802a1b0: 10800617 ldw r2,24(r2) + 802a1b4: e0bfff15 stw r2,-4(fp) + 802a1b8: e0bfff17 ldw r2,-4(fp) + 802a1bc: 103ff91e bne r2,zero,802a1a4 + 802a1c0: 00000106 br 802a1c8 + return; + 802a1c4: 0001883a nop + } +} + 802a1c8: e037883a mov sp,fp + 802a1cc: df000017 ldw fp,0(sp) + 802a1d0: dec00104 addi sp,sp,4 + 802a1d4: f800283a ret + +0802a1d8 : + * RETURNS: + */ + +int +mbuf_len (struct mbuf * m) +{ + 802a1d8: defffd04 addi sp,sp,-12 + 802a1dc: df000215 stw fp,8(sp) + 802a1e0: df000204 addi fp,sp,8 + 802a1e4: e13ffe15 stw r4,-8(fp) + int len = 0; + 802a1e8: e03fff15 stw zero,-4(fp) + + while (m) + 802a1ec: 00000806 br 802a210 + { + len += m->m_len; + 802a1f0: e0bffe17 ldw r2,-8(fp) + 802a1f4: 10c00217 ldw r3,8(r2) + 802a1f8: e0bfff17 ldw r2,-4(fp) + 802a1fc: 1885883a add r2,r3,r2 + 802a200: e0bfff15 stw r2,-4(fp) + m = m->m_next; + 802a204: e0bffe17 ldw r2,-8(fp) + 802a208: 10800617 ldw r2,24(r2) + 802a20c: e0bffe15 stw r2,-8(fp) + while (m) + 802a210: e0bffe17 ldw r2,-8(fp) + 802a214: 103ff61e bne r2,zero,802a1f0 + } + return len; + 802a218: e0bfff17 ldw r2,-4(fp) +} + 802a21c: e037883a mov sp,fp + 802a220: df000017 ldw fp,0(sp) + 802a224: dec00104 addi sp,sp,4 + 802a228: f800283a ret + +0802a22c : + * RETURNS: + */ + +struct mbuf * +dtom(void * data) +{ + 802a22c: defffb04 addi sp,sp,-20 + 802a230: dfc00415 stw ra,16(sp) + 802a234: df000315 stw fp,12(sp) + 802a238: df000304 addi fp,sp,12 + 802a23c: e13ffd15 stw r4,-12(fp) + qp qptr; + struct mbuf * m; + + for (qptr = mbufq.q_head; qptr; qptr = qptr->qe_next) + 802a240: 008201b4 movhi r2,2054 + 802a244: 10b88517 ldw r2,-7660(r2) + 802a248: e0bfff15 stw r2,-4(fp) + 802a24c: 00001206 br 802a298 + { + m = (struct mbuf *)qptr; + 802a250: e0bfff17 ldw r2,-4(fp) + 802a254: e0bffe15 stw r2,-8(fp) + + if (IN_RANGE(m->m_base, m->m_memsz, (char*)data)) + 802a258: e0bffe17 ldw r2,-8(fp) + 802a25c: 10800417 ldw r2,16(r2) + 802a260: e0fffd17 ldw r3,-12(fp) + 802a264: 18800936 bltu r3,r2,802a28c + 802a268: e0bffe17 ldw r2,-8(fp) + 802a26c: 10c00417 ldw r3,16(r2) + 802a270: e0bffe17 ldw r2,-8(fp) + 802a274: 10800517 ldw r2,20(r2) + 802a278: 1885883a add r2,r3,r2 + 802a27c: e0fffd17 ldw r3,-12(fp) + 802a280: 1880022e bgeu r3,r2,802a28c + return (struct mbuf *)qptr; + 802a284: e0bfff17 ldw r2,-4(fp) + 802a288: 00000906 br 802a2b0 + for (qptr = mbufq.q_head; qptr; qptr = qptr->qe_next) + 802a28c: e0bfff17 ldw r2,-4(fp) + 802a290: 10800017 ldw r2,0(r2) + 802a294: e0bfff15 stw r2,-4(fp) + 802a298: e0bfff17 ldw r2,-4(fp) + 802a29c: 103fec1e bne r2,zero,802a250 + else + continue; + + } + + panic("dtom"); /* data not found in any "in use" mbuf */ + 802a2a0: 01020174 movhi r4,2053 + 802a2a4: 212a6004 addi r4,r4,-22144 + 802a2a8: 80271780 call 8027178 + return NULL; + 802a2ac: 0005883a mov r2,zero +} + 802a2b0: e037883a mov sp,fp + 802a2b4: dfc00117 ldw ra,4(sp) + 802a2b8: df000017 ldw fp,0(sp) + 802a2bc: dec00204 addi sp,sp,8 + 802a2c0: f800283a ret + +0802a2c4 : +}; + + +void +remque (void * arg) +{ + 802a2c4: defffd04 addi sp,sp,-12 + 802a2c8: df000215 stw fp,8(sp) + 802a2cc: df000204 addi fp,sp,8 + 802a2d0: e13ffe15 stw r4,-8(fp) + struct bsdq * old; + + old = (struct bsdq *)arg; + 802a2d4: e0bffe17 ldw r2,-8(fp) + 802a2d8: e0bfff15 stw r2,-4(fp) + if (!old->prev) return; + 802a2dc: e0bfff17 ldw r2,-4(fp) + 802a2e0: 10800117 ldw r2,4(r2) + 802a2e4: 10000e26 beq r2,zero,802a320 + old->prev->next = old->next; + 802a2e8: e0bfff17 ldw r2,-4(fp) + 802a2ec: 10800117 ldw r2,4(r2) + 802a2f0: e0ffff17 ldw r3,-4(fp) + 802a2f4: 18c00017 ldw r3,0(r3) + 802a2f8: 10c00015 stw r3,0(r2) + if (old->next) + 802a2fc: e0bfff17 ldw r2,-4(fp) + 802a300: 10800017 ldw r2,0(r2) + 802a304: 10000726 beq r2,zero,802a324 + old->next->prev = old->prev; + 802a308: e0bfff17 ldw r2,-4(fp) + 802a30c: 10800017 ldw r2,0(r2) + 802a310: e0ffff17 ldw r3,-4(fp) + 802a314: 18c00117 ldw r3,4(r3) + 802a318: 10c00115 stw r3,4(r2) + 802a31c: 00000106 br 802a324 + if (!old->prev) return; + 802a320: 0001883a nop +} + 802a324: e037883a mov sp,fp + 802a328: df000017 ldw fp,0(sp) + 802a32c: dec00104 addi sp,sp,4 + 802a330: f800283a ret + +0802a334 : + * RETURNS: + */ + +void +insque(void * n, void * p) +{ + 802a334: defffb04 addi sp,sp,-20 + 802a338: df000415 stw fp,16(sp) + 802a33c: df000404 addi fp,sp,16 + 802a340: e13ffd15 stw r4,-12(fp) + 802a344: e17ffc15 stw r5,-16(fp) + struct bsdq * newe, * prev; + + newe = (struct bsdq *)n; + 802a348: e0bffd17 ldw r2,-12(fp) + 802a34c: e0bfff15 stw r2,-4(fp) + prev = (struct bsdq *)p; + 802a350: e0bffc17 ldw r2,-16(fp) + 802a354: e0bffe15 stw r2,-8(fp) + newe->next = prev->next; + 802a358: e0bffe17 ldw r2,-8(fp) + 802a35c: 10c00017 ldw r3,0(r2) + 802a360: e0bfff17 ldw r2,-4(fp) + 802a364: 10c00015 stw r3,0(r2) + newe->prev = prev; + 802a368: e0bfff17 ldw r2,-4(fp) + 802a36c: e0fffe17 ldw r3,-8(fp) + 802a370: 10c00115 stw r3,4(r2) + prev->next = newe; + 802a374: e0bffe17 ldw r2,-8(fp) + 802a378: e0ffff17 ldw r3,-4(fp) + 802a37c: 10c00015 stw r3,0(r2) + if (newe->next) + 802a380: e0bfff17 ldw r2,-4(fp) + 802a384: 10800017 ldw r2,0(r2) + 802a388: 10000426 beq r2,zero,802a39c + newe->next->prev = newe; + 802a38c: e0bfff17 ldw r2,-4(fp) + 802a390: 10800017 ldw r2,0(r2) + 802a394: e0ffff17 ldw r3,-4(fp) + 802a398: 10c00115 stw r3,4(r2) +} + 802a39c: 0001883a nop + 802a3a0: e037883a mov sp,fp + 802a3a4: df000017 ldw fp,0(sp) + 802a3a8: dec00104 addi sp,sp,4 + 802a3ac: f800283a ret + +0802a3b0 : + * RETURNS: Returns 0 if OK, else non-zero error code. + */ + +int +nptcp_init() +{ + 802a3b0: defffb04 addi sp,sp,-20 + 802a3b4: dfc00415 stw ra,16(sp) + 802a3b8: df000315 stw fp,12(sp) + 802a3bc: df000304 addi fp,sp,12 + * buffers, soreceive() can't complete and the packet buffers stay + * on the queue, so we allocate 3 extra mbufs in the hope that + * this will allow soreceive() to complete and free up the packet + * buffers. yes, its kind of an ugly hack and 3 is a wild guess. + */ + unsigned bufcount = (lilbufs + bigbufs) * 2 + 3; + 802a3c0: d0e01617 ldw r3,-32680(gp) + 802a3c4: d0a01817 ldw r2,-32672(gp) + 802a3c8: 1885883a add r2,r3,r2 + 802a3cc: 1085883a add r2,r2,r2 + 802a3d0: 108000c4 addi r2,r2,3 + 802a3d4: e0bffe15 stw r2,-8(fp) + struct mbuf * m; /* scratch mbuf for mfreeq init */ + + MEMSET(&soq, 0, sizeof(soq)); /* Set socket queue to NULLs */ + 802a3d8: 01800504 movi r6,20 + 802a3dc: 000b883a mov r5,zero + 802a3e0: 010201b4 movhi r4,2054 + 802a3e4: 21387104 addi r4,r4,-7740 + 802a3e8: 80088e40 call 80088e4 + MEMSET(&mbufq, 0, sizeof(mbufq)); + 802a3ec: 01800504 movi r6,20 + 802a3f0: 000b883a mov r5,zero + 802a3f4: 010201b4 movhi r4,2054 + 802a3f8: 21388504 addi r4,r4,-7660 + 802a3fc: 80088e40 call 80088e4 + MEMSET(&mfreeq, 0, sizeof(mfreeq)); + 802a400: 01800504 movi r6,20 + 802a404: 000b883a mov r5,zero + 802a408: 010201b4 movhi r4,2054 + 802a40c: 21388a04 addi r4,r4,-7640 + 802a410: 80088e40 call 80088e4 + for (i = 0; i < (int)bufcount; i++) + 802a414: e03fff15 stw zero,-4(fp) + 802a418: 00001506 br 802a470 + { + m = MBU_ALLOC(sizeof(struct mbuf)); + 802a41c: 01000904 movi r4,36 + 802a420: 802982c0 call 802982c + 802a424: e0bffd15 stw r2,-12(fp) + if (!m) /* malloc error, bail out */ + 802a428: e0bffd17 ldw r2,-12(fp) + 802a42c: 1000031e bne r2,zero,802a43c + panic("tcpinit"); + 802a430: 01020174 movhi r4,2053 + 802a434: 212a6204 addi r4,r4,-22136 + 802a438: 80271780 call 8027178 + m->m_type = MT_FREE; + 802a43c: e0bffd17 ldw r2,-12(fp) + 802a440: 10000815 stw zero,32(r2) + m->m_len = 0; + 802a444: e0bffd17 ldw r2,-12(fp) + 802a448: 10000215 stw zero,8(r2) + m->m_data = NULL; + 802a44c: e0bffd17 ldw r2,-12(fp) + 802a450: 10000315 stw zero,12(r2) + putq(&mfreeq, (qp)m); + 802a454: e17ffd17 ldw r5,-12(fp) + 802a458: 010201b4 movhi r4,2054 + 802a45c: 21388a04 addi r4,r4,-7640 + 802a460: 80289900 call 8028990 + for (i = 0; i < (int)bufcount; i++) + 802a464: e0bfff17 ldw r2,-4(fp) + 802a468: 10800044 addi r2,r2,1 + 802a46c: e0bfff15 stw r2,-4(fp) + 802a470: e0bffe17 ldw r2,-8(fp) + 802a474: e0ffff17 ldw r3,-4(fp) + 802a478: 18bfe816 blt r3,r2,802a41c + } + mfreeq.q_min = (int)bufcount; /* this should match q_max and q_len */ + 802a47c: e0fffe17 ldw r3,-8(fp) + 802a480: 008201b4 movhi r2,2054 + 802a484: 10f88e15 stw r3,-7624(r2) + tcpmib.tcpRtoAlgorithm = 4; /* Van Jacobson's algorithm */ + tcpmib.tcpRtoMin = TCPTV_MIN * 1000; /* PR_SLOWHZ */ + tcpmib.tcpRtoMax = TCPTV_REXMTMAX * 1000; /* PR_SLOWHZ */ +#endif + + tcp_init(); /* call the BSD init in tcp_usr.c */ + 802a488: 80349f80 call 80349f8 + +#ifdef TCP_MENUS + install_menu(&tcpmenu[0]); +#endif /* IN_MENUS */ + + return 0; /* good return */ + 802a48c: 0005883a mov r2,zero +} + 802a490: e037883a mov sp,fp + 802a494: dfc00117 ldw ra,4(sp) + 802a498: df000017 ldw fp,0(sp) + 802a49c: dec00204 addi sp,sp,8 + 802a4a0: f800283a ret + +0802a4a4 : + +#ifdef IP_V4 + +int +tcp_rcv(PACKET pkt) /* NOTE: pkt has nb_prot pointing to IP header */ +{ + 802a4a4: defff904 addi sp,sp,-28 + 802a4a8: dfc00615 stw ra,24(sp) + 802a4ac: df000515 stw fp,20(sp) + 802a4b0: df000504 addi fp,sp,20 + 802a4b4: e13ffb15 stw r4,-20(fp) + + /* For TCP, the netport IP layer is modified to set nb_prot to the + * start of the IP header (not TCP). We need to do some further + * mods which the BSD code expects: + */ + bip = (struct ip *)pkt->nb_prot; /* get ip header */ + 802a4b8: e0bffb17 ldw r2,-20(fp) + 802a4bc: 10800317 ldw r2,12(r2) + 802a4c0: e0bfff15 stw r2,-4(fp) + len = ntohs(bip->ip_len); /* get length in local endian */ + 802a4c4: e0bfff17 ldw r2,-4(fp) + 802a4c8: 1080008b ldhu r2,2(r2) + 802a4cc: 10bfffcc andi r2,r2,65535 + 802a4d0: 1004d23a srli r2,r2,8 + 802a4d4: 1007883a mov r3,r2 + 802a4d8: e0bfff17 ldw r2,-4(fp) + 802a4dc: 1080008b ldhu r2,2(r2) + 802a4e0: 10bfffcc andi r2,r2,65535 + 802a4e4: 1004923a slli r2,r2,8 + 802a4e8: 1884b03a or r2,r3,r2 + 802a4ec: e0bffe8d sth r2,-6(fp) + + /* verify checksum of received packet */ + + tcpp = (struct tcphdr *)ip_data(bip); + 802a4f0: e0bfff17 ldw r2,-4(fp) + 802a4f4: 10800003 ldbu r2,0(r2) + 802a4f8: 10803fcc andi r2,r2,255 + 802a4fc: 100490ba slli r2,r2,2 + 802a500: 10800f0c andi r2,r2,60 + 802a504: e0ffff17 ldw r3,-4(fp) + 802a508: 1885883a add r2,r3,r2 + 802a50c: e0bffd15 stw r2,-12(fp) + if (tcp_cksum(bip) != tcpp->th_sum) + 802a510: e13fff17 ldw r4,-4(fp) + 802a514: 80400c00 call 80400c0 + 802a518: 1007883a mov r3,r2 + 802a51c: e0bffd17 ldw r2,-12(fp) + 802a520: 1080040b ldhu r2,16(r2) + 802a524: 18ffffcc andi r3,r3,65535 + 802a528: 10bfffcc andi r2,r2,65535 + 802a52c: 18801226 beq r3,r2,802a578 + { + TCP_MIB_INC(tcpInErrs); /* keep MIB stats */ + 802a530: 008201b4 movhi r2,2054 + 802a534: 10b88317 ldw r2,-7668(r2) + 802a538: 10c00044 addi r3,r2,1 + 802a53c: 008201b4 movhi r2,2054 + 802a540: 10f88315 stw r3,-7668(r2) + tcpstat.tcps_rcvbadsum++; /* keep BSD stats */ + 802a544: 008201b4 movhi r2,2054 + 802a548: 10b8c017 ldw r2,-7424(r2) + 802a54c: 10c00044 addi r3,r2,1 + 802a550: 008201b4 movhi r2,2054 + 802a554: 10f8c015 stw r3,-7424(r2) + LOCK_NET_RESOURCE(FREEQ_RESID); + 802a558: 01000084 movi r4,2 + 802a55c: 8028f380 call 8028f38 + pk_free(pkt); /* punt packet */ + 802a560: e13ffb17 ldw r4,-20(fp) + 802a564: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 802a568: 01000084 movi r4,2 + 802a56c: 8028ff40 call 8028ff4 + return ENP_BAD_HEADER; + 802a570: 00bff804 movi r2,-32 + 802a574: 00003306 br 802a644 + } + + m_in = m_getnbuf(MT_RXDATA, 0); + 802a578: 000b883a mov r5,zero + 802a57c: 01000044 movi r4,1 + 802a580: 8029a700 call 8029a70 + 802a584: e0bffc15 stw r2,-16(fp) + if (!m_in){ + 802a588: e0bffc17 ldw r2,-16(fp) + 802a58c: 1000081e bne r2,zero,802a5b0 + LOCK_NET_RESOURCE(FREEQ_RESID); + 802a590: 01000084 movi r4,2 + 802a594: 8028f380 call 8028f38 + pk_free(pkt); + 802a598: e13ffb17 ldw r4,-20(fp) + 802a59c: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 802a5a0: 01000084 movi r4,2 + 802a5a4: 8028ff40 call 8028ff4 + return ENP_RESOURCE; + 802a5a8: 00bffa84 movi r2,-22 + 802a5ac: 00002506 br 802a644 + } + + IN_PROFILER(PF_TCP, PF_ENTRY); /* measure time in TCP */ + + /* subtract IP header length from total IP packet length */ + len -= ((unshort)(bip->ip_ver_ihl & 0x0f) << 2); + 802a5b0: e0bfff17 ldw r2,-4(fp) + 802a5b4: 10800003 ldbu r2,0(r2) + 802a5b8: 10803fcc andi r2,r2,255 + 802a5bc: 100490ba slli r2,r2,2 + 802a5c0: 10800f0c andi r2,r2,60 + 802a5c4: 1007883a mov r3,r2 + 802a5c8: e0bffe8b ldhu r2,-6(fp) + 802a5cc: 10c5c83a sub r2,r2,r3 + 802a5d0: e0bffe8d sth r2,-6(fp) + bip->ip_len = len; /* put TCP length in struct for TCP code to use */ + 802a5d4: e0bfff17 ldw r2,-4(fp) + 802a5d8: e0fffe8b ldhu r3,-6(fp) + 802a5dc: 10c0008d sth r3,2(r2) + + /* set mbuf to point to start of IP header (not TCP) */ + m_in->pkt = pkt; + 802a5e0: e0bffc17 ldw r2,-16(fp) + 802a5e4: e0fffb17 ldw r3,-20(fp) + 802a5e8: 10c00115 stw r3,4(r2) + m_in->m_data = pkt->nb_prot; + 802a5ec: e0bffb17 ldw r2,-20(fp) + 802a5f0: 10c00317 ldw r3,12(r2) + 802a5f4: e0bffc17 ldw r2,-16(fp) + 802a5f8: 10c00315 stw r3,12(r2) + m_in->m_len = pkt->nb_plen; + 802a5fc: e0bffb17 ldw r2,-20(fp) + 802a600: 10c00417 ldw r3,16(r2) + 802a604: e0bffc17 ldw r2,-16(fp) + 802a608: 10c00215 stw r3,8(r2) + m_in->m_base = pkt->nb_buff; /* ??? */ + 802a60c: e0bffb17 ldw r2,-20(fp) + 802a610: 10c00117 ldw r3,4(r2) + 802a614: e0bffc17 ldw r2,-16(fp) + 802a618: 10c00415 stw r3,16(r2) + m_in->m_memsz = pkt->nb_blen; /* ??? */ + 802a61c: e0bffb17 ldw r2,-20(fp) + 802a620: 10c00217 ldw r3,8(r2) + 802a624: e0bffc17 ldw r2,-16(fp) + 802a628: 10c00515 stw r3,20(r2) + + tcp_input(m_in, pkt->net); + 802a62c: e0bffb17 ldw r2,-20(fp) + 802a630: 10800617 ldw r2,24(r2) + 802a634: 100b883a mov r5,r2 + 802a638: e13ffc17 ldw r4,-16(fp) + 802a63c: 80310500 call 8031050 + + IN_PROFILER(PF_TCP, PF_EXIT); /* measure time in TCP */ + + return 0; + 802a640: 0005883a mov r2,zero +} + 802a644: e037883a mov sp,fp + 802a648: dfc00117 ldw ra,4(sp) + 802a64c: df000017 ldw fp,0(sp) + 802a650: dec00204 addi sp,sp,8 + 802a654: f800283a ret + +0802a658 : + * RETURNS: + */ + +int +ip_output(struct mbuf * data, struct ip_socopts * so_optsPack) /* mbuf chain with data to send */ +{ + 802a658: defff404 addi sp,sp,-48 + 802a65c: dfc00b15 stw ra,44(sp) + 802a660: df000a15 stw fp,40(sp) + 802a664: df000a04 addi fp,sp,40 + 802a668: e13ff715 stw r4,-36(fp) + 802a66c: e17ff615 stw r5,-40(fp) + * little copying as possible. Typically the mbufs will be either + * 1) a single mbuf with iptcp header info only (e.g.tcp ACK + * packet), or 2) iptcp header with data mbuf chained to it, or 3) + * #2) with a tiny option data mbuf between header and data. + */ + if ((data->m_next)) + 802a670: e0bff717 ldw r2,-36(fp) + 802a674: 10800617 ldw r2,24(r2) + 802a678: 10010226 beq r2,zero,802aa84 + { + m1 = data; + 802a67c: e0bff717 ldw r2,-36(fp) + 802a680: e0bfff15 stw r2,-4(fp) + m2 = data->m_next; + 802a684: e0bff717 ldw r2,-36(fp) + 802a688: 10800617 ldw r2,24(r2) + 802a68c: e0bffe15 stw r2,-8(fp) + + /* If m2 is small (e.g. options), copy it to m1 and free it */ + while (m2 && (m2->m_len < 10)) + 802a690: 00003306 br 802a760 + { + pkt = m1->pkt; + 802a694: e0bfff17 ldw r2,-4(fp) + 802a698: 10800117 ldw r2,4(r2) + 802a69c: e0bffb15 stw r2,-20(fp) + if ((pkt->nb_buff + pkt->nb_blen) > /* make sure m2 will fit in m1 */ + 802a6a0: e0bffb17 ldw r2,-20(fp) + 802a6a4: 10c00117 ldw r3,4(r2) + 802a6a8: e0bffb17 ldw r2,-20(fp) + 802a6ac: 10800217 ldw r2,8(r2) + 802a6b0: 1885883a add r2,r3,r2 + (m1->m_data + m1->m_len + m2->m_len)) + 802a6b4: e0ffff17 ldw r3,-4(fp) + 802a6b8: 19000317 ldw r4,12(r3) + 802a6bc: e0ffff17 ldw r3,-4(fp) + 802a6c0: 19400217 ldw r5,8(r3) + 802a6c4: e0fffe17 ldw r3,-8(fp) + 802a6c8: 18c00217 ldw r3,8(r3) + 802a6cc: 28c7883a add r3,r5,r3 + 802a6d0: 20c7883a add r3,r4,r3 + if ((pkt->nb_buff + pkt->nb_blen) > /* make sure m2 will fit in m1 */ + 802a6d4: 1880292e bgeu r3,r2,802a77c + { + MEMCPY((m1->m_data + m1->m_len), m2->m_data, m2->m_len); + 802a6d8: e0bfff17 ldw r2,-4(fp) + 802a6dc: 10c00317 ldw r3,12(r2) + 802a6e0: e0bfff17 ldw r2,-4(fp) + 802a6e4: 10800217 ldw r2,8(r2) + 802a6e8: 1887883a add r3,r3,r2 + 802a6ec: e0bffe17 ldw r2,-8(fp) + 802a6f0: 11000317 ldw r4,12(r2) + 802a6f4: e0bffe17 ldw r2,-8(fp) + 802a6f8: 10800217 ldw r2,8(r2) + 802a6fc: 100d883a mov r6,r2 + 802a700: 200b883a mov r5,r4 + 802a704: 1809883a mov r4,r3 + 802a708: 80086b80 call 80086b8 + m1->m_len += m2->m_len; + 802a70c: e0bfff17 ldw r2,-4(fp) + 802a710: 10c00217 ldw r3,8(r2) + 802a714: e0bffe17 ldw r2,-8(fp) + 802a718: 10800217 ldw r2,8(r2) + 802a71c: 1887883a add r3,r3,r2 + 802a720: e0bfff17 ldw r2,-4(fp) + 802a724: 10c00215 stw r3,8(r2) + m1->m_next = m2->m_next; + 802a728: e0bffe17 ldw r2,-8(fp) + 802a72c: 10c00617 ldw r3,24(r2) + 802a730: e0bfff17 ldw r2,-4(fp) + 802a734: 10c00615 stw r3,24(r2) + m_free(m2); /* free this m2.... */ + 802a738: e13ffe17 ldw r4,-8(fp) + 802a73c: 8029bf80 call 8029bf8 + m2 = m1->m_next; /* ...and thread the next one */ + 802a740: e0bfff17 ldw r2,-4(fp) + 802a744: 10800617 ldw r2,24(r2) + 802a748: e0bffe15 stw r2,-8(fp) + tcpstat.tcps_oappends++; + 802a74c: 008201b4 movhi r2,2054 + 802a750: 10b8d717 ldw r2,-7332(r2) + 802a754: 10c00044 addi r3,r2,1 + 802a758: 008201b4 movhi r2,2054 + 802a75c: 10f8d715 stw r3,-7332(r2) + while (m2 && (m2->m_len < 10)) + 802a760: e0bffe17 ldw r2,-8(fp) + 802a764: 10005726 beq r2,zero,802a8c4 + 802a768: e0bffe17 ldw r2,-8(fp) + 802a76c: 10800217 ldw r2,8(r2) + 802a770: 108002b0 cmpltui r2,r2,10 + 802a774: 103fc71e bne r2,zero,802a694 + 802a778: 00005206 br 802a8c4 + } + else /* if won't fit, fall to next copy */ + break; + 802a77c: 0001883a nop + } + + while (m2) /* If we still have two or more buffers, more copying: */ + 802a780: 00005006 br 802a8c4 + { + /* try prepending m1 to m2, first see if it fits: */ + e = m2->m_data - m2->pkt->nb_buff; /* e is prepend space */ + 802a784: e0bffe17 ldw r2,-8(fp) + 802a788: 10c00317 ldw r3,12(r2) + 802a78c: e0bffe17 ldw r2,-8(fp) + 802a790: 10800117 ldw r2,4(r2) + 802a794: 10800117 ldw r2,4(r2) + 802a798: 1885c83a sub r2,r3,r2 + 802a79c: e0bffa15 stw r2,-24(fp) + if (e < MaxLnh) + 802a7a0: d0a06417 ldw r2,-32368(gp) + 802a7a4: e0fffa17 ldw r3,-24(fp) + 802a7a8: 1880090e bge r3,r2,802a7d0 + { +#ifdef NPDEBUG + dprintf("nptcp: MaxLnh:%d, e:%d\n", MaxLnh, e); + 802a7ac: d0a06417 ldw r2,-32368(gp) + 802a7b0: e1bffa17 ldw r6,-24(fp) + 802a7b4: 100b883a mov r5,r2 + 802a7b8: 01020174 movhi r4,2053 + 802a7bc: 212a6404 addi r4,r4,-22128 + 802a7c0: 8002c780 call 8002c78 +#endif + panic("tcp_out:mbuf-nbuf"); /* sanity check */ + 802a7c4: 01020174 movhi r4,2053 + 802a7c8: 212a6a04 addi r4,r4,-22104 + 802a7cc: 80271780 call 8027178 + } + + if ((m1->m_len < (unsigned)(e - MaxLnh)) /* leave room for MAC */ + 802a7d0: e0bfff17 ldw r2,-4(fp) + 802a7d4: 10800217 ldw r2,8(r2) + 802a7d8: d0e06417 ldw r3,-32368(gp) + 802a7dc: e13ffa17 ldw r4,-24(fp) + 802a7e0: 20c7c83a sub r3,r4,r3 + 802a7e4: 10c0392e bgeu r2,r3,802a8cc + && ((m1->m_len & (ALIGN_TYPE - 1)) == 0) /* and stay aligned */ + 802a7e8: e0bfff17 ldw r2,-4(fp) + 802a7ec: 10800217 ldw r2,8(r2) + 802a7f0: 108000cc andi r2,r2,3 + 802a7f4: 1000351e bne r2,zero,802a8cc + && ((m2->m_data - m2->pkt->nb_buff) == HDRSLEN)) /* be at start */ + 802a7f8: e0bffe17 ldw r2,-8(fp) + 802a7fc: 10c00317 ldw r3,12(r2) + 802a800: e0bffe17 ldw r2,-8(fp) + 802a804: 10800117 ldw r2,4(r2) + 802a808: 10800117 ldw r2,4(r2) + 802a80c: 1885c83a sub r2,r3,r2 + 802a810: 10800e18 cmpnei r2,r2,56 + 802a814: 10002d1e bne r2,zero,802a8cc + { + MEMCPY((m2->m_data - m1->m_len), m1->m_data, m1->m_len); + 802a818: e0bffe17 ldw r2,-8(fp) + 802a81c: 10c00317 ldw r3,12(r2) + 802a820: e0bfff17 ldw r2,-4(fp) + 802a824: 10800217 ldw r2,8(r2) + 802a828: 0085c83a sub r2,zero,r2 + 802a82c: 1887883a add r3,r3,r2 + 802a830: e0bfff17 ldw r2,-4(fp) + 802a834: 11000317 ldw r4,12(r2) + 802a838: e0bfff17 ldw r2,-4(fp) + 802a83c: 10800217 ldw r2,8(r2) + 802a840: 100d883a mov r6,r2 + 802a844: 200b883a mov r5,r4 + 802a848: 1809883a mov r4,r3 + 802a84c: 80086b80 call 80086b8 + m2->m_data -= m1->m_len; /* fix target to reflect prepend */ + 802a850: e0bffe17 ldw r2,-8(fp) + 802a854: 10c00317 ldw r3,12(r2) + 802a858: e0bfff17 ldw r2,-4(fp) + 802a85c: 10800217 ldw r2,8(r2) + 802a860: 0085c83a sub r2,zero,r2 + 802a864: 1887883a add r3,r3,r2 + 802a868: e0bffe17 ldw r2,-8(fp) + 802a86c: 10c00315 stw r3,12(r2) + m2->m_len += m1->m_len; + 802a870: e0bffe17 ldw r2,-8(fp) + 802a874: 10c00217 ldw r3,8(r2) + 802a878: e0bfff17 ldw r2,-4(fp) + 802a87c: 10800217 ldw r2,8(r2) + 802a880: 1887883a add r3,r3,r2 + 802a884: e0bffe17 ldw r2,-8(fp) + 802a888: 10c00215 stw r3,8(r2) + m_free(m1); /* free head (copied) mbuf */ + 802a88c: e13fff17 ldw r4,-4(fp) + 802a890: 8029bf80 call 8029bf8 + data = m1 = m2; /* move other mbufs up the chain */ + 802a894: e0bffe17 ldw r2,-8(fp) + 802a898: e0bfff15 stw r2,-4(fp) + 802a89c: e0bfff17 ldw r2,-4(fp) + 802a8a0: e0bff715 stw r2,-36(fp) + m2 = m2->m_next; /* loop to while(m2) test */ + 802a8a4: e0bffe17 ldw r2,-8(fp) + 802a8a8: 10800617 ldw r2,24(r2) + 802a8ac: e0bffe15 stw r2,-8(fp) + tcpstat.tcps_oprepends++; + 802a8b0: 008201b4 movhi r2,2054 + 802a8b4: 10b8d617 ldw r2,-7336(r2) + 802a8b8: 10c00044 addi r3,r2,1 + 802a8bc: 008201b4 movhi r2,2054 + 802a8c0: 10f8d615 stw r3,-7336(r2) + while (m2) /* If we still have two or more buffers, more copying: */ + 802a8c4: e0bffe17 ldw r2,-8(fp) + 802a8c8: 103fae1e bne r2,zero,802a784 + } + else /* if won't fit, fall to next copy */ + break; + } + + if (m2) /* If all else fails, brute force copy: */ + 802a8cc: e0bffe17 ldw r2,-8(fp) + 802a8d0: 10006c26 beq r2,zero,802aa84 + { + total = 0; + 802a8d4: e03ffc15 stw zero,-16(fp) + for (mtmp = m1; mtmp; mtmp = mtmp->m_next) + 802a8d8: e0bfff17 ldw r2,-4(fp) + 802a8dc: e0bffd15 stw r2,-12(fp) + 802a8e0: 00000806 br 802a904 + total += mtmp->m_len; + 802a8e4: e0bffd17 ldw r2,-12(fp) + 802a8e8: 10c00217 ldw r3,8(r2) + 802a8ec: e0bffc17 ldw r2,-16(fp) + 802a8f0: 1885883a add r2,r3,r2 + 802a8f4: e0bffc15 stw r2,-16(fp) + for (mtmp = m1; mtmp; mtmp = mtmp->m_next) + 802a8f8: e0bffd17 ldw r2,-12(fp) + 802a8fc: 10800617 ldw r2,24(r2) + 802a900: e0bffd15 stw r2,-12(fp) + 802a904: e0bffd17 ldw r2,-12(fp) + 802a908: 103ff61e bne r2,zero,802a8e4 + LOCK_NET_RESOURCE(FREEQ_RESID); + 802a90c: 01000084 movi r4,2 + 802a910: 8028f380 call 8028f38 + pkt = pk_alloc(total + HDRSLEN); + 802a914: e0bffc17 ldw r2,-16(fp) + 802a918: 10800e04 addi r2,r2,56 + 802a91c: 1009883a mov r4,r2 + 802a920: 80284340 call 8028434 + 802a924: e0bffb15 stw r2,-20(fp) + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 802a928: 01000084 movi r4,2 + 802a92c: 8028ff40 call 8028ff4 + if (!pkt) + 802a930: e0bffb17 ldw r2,-20(fp) + 802a934: 1000021e bne r2,zero,802a940 + return ENOBUFS; + 802a938: 00801a44 movi r2,105 + 802a93c: 0000a306 br 802abcc + pkt->nb_prot = pkt->nb_buff + MaxLnh; + 802a940: e0bffb17 ldw r2,-20(fp) + 802a944: 10800117 ldw r2,4(r2) + 802a948: d0e06417 ldw r3,-32368(gp) + 802a94c: 10c7883a add r3,r2,r3 + 802a950: e0bffb17 ldw r2,-20(fp) + 802a954: 10c00315 stw r3,12(r2) + + mtmp = m1; + 802a958: e0bfff17 ldw r2,-4(fp) + 802a95c: e0bffd15 stw r2,-12(fp) + while (mtmp) + 802a960: 00002706 br 802aa00 + { + MEMCPY(pkt->nb_prot, mtmp->m_data, mtmp->m_len); + 802a964: e0bffb17 ldw r2,-20(fp) + 802a968: 10c00317 ldw r3,12(r2) + 802a96c: e0bffd17 ldw r2,-12(fp) + 802a970: 11000317 ldw r4,12(r2) + 802a974: e0bffd17 ldw r2,-12(fp) + 802a978: 10800217 ldw r2,8(r2) + 802a97c: 100d883a mov r6,r2 + 802a980: 200b883a mov r5,r4 + 802a984: 1809883a mov r4,r3 + 802a988: 80086b80 call 80086b8 + pkt->nb_prot += mtmp->m_len; + 802a98c: e0bffb17 ldw r2,-20(fp) + 802a990: 10c00317 ldw r3,12(r2) + 802a994: e0bffd17 ldw r2,-12(fp) + 802a998: 10800217 ldw r2,8(r2) + 802a99c: 1887883a add r3,r3,r2 + 802a9a0: e0bffb17 ldw r2,-20(fp) + 802a9a4: 10c00315 stw r3,12(r2) + pkt->nb_plen += mtmp->m_len; + 802a9a8: e0bffb17 ldw r2,-20(fp) + 802a9ac: 10c00417 ldw r3,16(r2) + 802a9b0: e0bffd17 ldw r2,-12(fp) + 802a9b4: 10800217 ldw r2,8(r2) + 802a9b8: 1887883a add r3,r3,r2 + 802a9bc: e0bffb17 ldw r2,-20(fp) + 802a9c0: 10c00415 stw r3,16(r2) + m2 = mtmp; + 802a9c4: e0bffd17 ldw r2,-12(fp) + 802a9c8: e0bffe15 stw r2,-8(fp) + mtmp = mtmp->m_next; + 802a9cc: e0bffd17 ldw r2,-12(fp) + 802a9d0: 10800617 ldw r2,24(r2) + 802a9d4: e0bffd15 stw r2,-12(fp) + if (m2 != data) /* save original head */ + 802a9d8: e0fffe17 ldw r3,-8(fp) + 802a9dc: e0bff717 ldw r2,-36(fp) + 802a9e0: 18800226 beq r3,r2,802a9ec + m_free(m2); + 802a9e4: e13ffe17 ldw r4,-8(fp) + 802a9e8: 8029bf80 call 8029bf8 + tcpstat.tcps_ocopies++; + 802a9ec: 008201b4 movhi r2,2054 + 802a9f0: 10b8d817 ldw r2,-7328(r2) + 802a9f4: 10c00044 addi r3,r2,1 + 802a9f8: 008201b4 movhi r2,2054 + 802a9fc: 10f8d815 stw r3,-7328(r2) + while (mtmp) + 802aa00: e0bffd17 ldw r2,-12(fp) + 802aa04: 103fd71e bne r2,zero,802a964 + } + pkt->nb_prot -= total; /* fix data pointer */ + 802aa08: e0bffb17 ldw r2,-20(fp) + 802aa0c: 10c00317 ldw r3,12(r2) + 802aa10: e0bffc17 ldw r2,-16(fp) + 802aa14: 0085c83a sub r2,zero,r2 + 802aa18: 1887883a add r3,r3,r2 + 802aa1c: e0bffb17 ldw r2,-20(fp) + 802aa20: 10c00315 stw r3,12(r2) + + /* release the original mbufs packet install the new one */ + LOCK_NET_RESOURCE(FREEQ_RESID); + 802aa24: 01000084 movi r4,2 + 802aa28: 8028f380 call 8028f38 + pk_free(data->pkt); + 802aa2c: e0bff717 ldw r2,-36(fp) + 802aa30: 10800117 ldw r2,4(r2) + 802aa34: 1009883a mov r4,r2 + 802aa38: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 802aa3c: 01000084 movi r4,2 + 802aa40: 8028ff40 call 8028ff4 + data->pkt = pkt; + 802aa44: e0bff717 ldw r2,-36(fp) + 802aa48: e0fffb17 ldw r3,-20(fp) + 802aa4c: 10c00115 stw r3,4(r2) + data->m_len = pkt->nb_plen; + 802aa50: e0bffb17 ldw r2,-20(fp) + 802aa54: 10c00417 ldw r3,16(r2) + 802aa58: e0bff717 ldw r2,-36(fp) + 802aa5c: 10c00215 stw r3,8(r2) + data->m_next = NULL; + 802aa60: e0bff717 ldw r2,-36(fp) + 802aa64: 10000615 stw zero,24(r2) + data->m_data = pkt->nb_prot; + 802aa68: e0bffb17 ldw r2,-20(fp) + 802aa6c: 10c00317 ldw r3,12(r2) + 802aa70: e0bff717 ldw r2,-36(fp) + 802aa74: 10c00315 stw r3,12(r2) + data->m_len = total; + 802aa78: e0fffc17 ldw r3,-16(fp) + 802aa7c: e0bff717 ldw r2,-36(fp) + 802aa80: 10c00215 stw r3,8(r2) + } + } + + if ((data->m_data < (data->pkt->nb_buff + MaxLnh))) + 802aa84: e0bff717 ldw r2,-36(fp) + 802aa88: 10c00317 ldw r3,12(r2) + 802aa8c: e0bff717 ldw r2,-36(fp) + 802aa90: 10800117 ldw r2,4(r2) + 802aa94: 10800117 ldw r2,4(r2) + 802aa98: d1206417 ldw r4,-32368(gp) + 802aa9c: 1105883a add r2,r2,r4 + 802aaa0: 1880032e bgeu r3,r2,802aab0 + panic("ip_output: overflow"); + 802aaa4: 01020174 movhi r4,2053 + 802aaa8: 212a6f04 addi r4,r4,-22084 + 802aaac: 80271780 call 8027178 + + pkt = data->pkt; + 802aab0: e0bff717 ldw r2,-36(fp) + 802aab4: 10800117 ldw r2,4(r2) + 802aab8: e0bffb15 stw r2,-20(fp) + + /* do we have options? */ + if (so_optsPack) + 802aabc: e0bff617 ldw r2,-40(fp) + 802aac0: 10000326 beq r2,zero,802aad0 + pkt->soxopts = so_optsPack; /* yup */ + 802aac4: e0bffb17 ldw r2,-20(fp) + 802aac8: e0fff617 ldw r3,-40(fp) + 802aacc: 10c00c15 stw r3,48(r2) + panic("ip_output: no so_optsPack for the IPv6 scope"); + } +#endif + + /* fill in dest host for IP layer */ + bip = (struct ip *)data->m_data; + 802aad0: e0bff717 ldw r2,-36(fp) + 802aad4: 10800317 ldw r2,12(r2) + 802aad8: e0bff915 stw r2,-28(fp) + pkt->fhost = bip->ip_dest; + 802aadc: e0bff917 ldw r2,-28(fp) + 802aae0: 10c00417 ldw r3,16(r2) + 802aae4: e0bffb17 ldw r2,-20(fp) + 802aae8: 10c00715 stw r3,28(r2) + + /* make enough IP header for cksum calculation */ + bip->ip_ver_ihl = 0x45; + 802aaec: e0bff917 ldw r2,-28(fp) + 802aaf0: 00c01144 movi r3,69 + 802aaf4: 10c00005 stb r3,0(r2) + bip->ip_len = htons(bip->ip_len); /* make net endian for calculation */ + 802aaf8: e0bff917 ldw r2,-28(fp) + 802aafc: 1080008b ldhu r2,2(r2) + 802ab00: 10bfffcc andi r2,r2,65535 + 802ab04: 1004d23a srli r2,r2,8 + 802ab08: 1007883a mov r3,r2 + 802ab0c: e0bff917 ldw r2,-28(fp) + 802ab10: 1080008b ldhu r2,2(r2) + 802ab14: 10bfffcc andi r2,r2,65535 + 802ab18: 1004923a slli r2,r2,8 + 802ab1c: 1884b03a or r2,r3,r2 + 802ab20: 1007883a mov r3,r2 + 802ab24: e0bff917 ldw r2,-28(fp) + 802ab28: 10c0008d sth r3,2(r2) + tcpp = (struct tcphdr *)ip_data(bip); + 802ab2c: e0bff917 ldw r2,-28(fp) + 802ab30: 10800003 ldbu r2,0(r2) + 802ab34: 10803fcc andi r2,r2,255 + 802ab38: 100490ba slli r2,r2,2 + 802ab3c: 10800f0c andi r2,r2,60 + 802ab40: e0fff917 ldw r3,-28(fp) + 802ab44: 1885883a add r2,r3,r2 + 802ab48: e0bff815 stw r2,-32(fp) +#ifdef CSUM_DEMO + if (!(tcpp->th_flags & TH_SYN)) + tcpp->th_flags |= TH_PUSH; /* force the PSH flag in TCP hdr */ +#endif + tcpp->th_sum = tcp_cksum(bip); + 802ab4c: e13ff917 ldw r4,-28(fp) + 802ab50: 80400c00 call 80400c0 + 802ab54: 1007883a mov r3,r2 + 802ab58: e0bff817 ldw r2,-32(fp) + 802ab5c: 10c0040d sth r3,16(r2) + + pkt->nb_prot = (char*)(bip + 1); /* point past IP header */ + 802ab60: e0bff917 ldw r2,-28(fp) + 802ab64: 10c00504 addi r3,r2,20 + 802ab68: e0bffb17 ldw r2,-20(fp) + 802ab6c: 10c00315 stw r3,12(r2) + pkt->nb_plen = data->m_len - sizeof(struct ip); + 802ab70: e0bff717 ldw r2,-36(fp) + 802ab74: 10800217 ldw r2,8(r2) + 802ab78: 10fffb04 addi r3,r2,-20 + 802ab7c: e0bffb17 ldw r2,-20(fp) + 802ab80: 10c00415 stw r3,16(r2) + + e = ip_write(IPPROTO_TCP, pkt); + 802ab84: e17ffb17 ldw r5,-20(fp) + 802ab88: 01000184 movi r4,6 + 802ab8c: 803a9e80 call 803a9e8 + 802ab90: e0bffa15 stw r2,-24(fp) + + /* ip_write() is now responsable for data->pkt, so... */ + data->pkt = NULL; + 802ab94: e0bff717 ldw r2,-36(fp) + 802ab98: 10000115 stw zero,4(r2) + m_freem(data); + 802ab9c: e13ff717 ldw r4,-36(fp) + 802aba0: 8029cfc0 call 8029cfc + + if (e < 0) + 802aba4: e0bffa17 ldw r2,-24(fp) + 802aba8: 1000070e bge r2,zero,802abc8 + { + /* don't report dropped sends, it causes socket applications to + bail when a TCP retry will fix the problem */ + if (e == SEND_DROPPED) + 802abac: e0bffa17 ldw r2,-24(fp) + 802abb0: 10bffa98 cmpnei r2,r2,-22 + 802abb4: 1000021e bne r2,zero,802abc0 + return 0; + 802abb8: 0005883a mov r2,zero + 802abbc: 00000306 br 802abcc + return e; + 802abc0: e0bffa17 ldw r2,-24(fp) + 802abc4: 00000106 br 802abcc + } + else + return 0; + 802abc8: 0005883a mov r2,zero +} + 802abcc: e037883a mov sp,fp + 802abd0: dfc00117 ldw ra,4(sp) + 802abd4: df000017 ldw fp,0(sp) + 802abd8: dec00204 addi sp,sp,8 + 802abdc: f800283a ret + +0802abe0 : + * RETURNS: TRUE if broadcast, else FALSE + */ + +int +in_broadcast(u_long ipaddr) /* passed in net endian */ +{ + 802abe0: defffe04 addi sp,sp,-8 + 802abe4: df000115 stw fp,4(sp) + 802abe8: df000104 addi fp,sp,4 + 802abec: e13fff15 stw r4,-4(fp) + if (ipaddr == 0xffffffff) + 802abf0: e0bfff17 ldw r2,-4(fp) + 802abf4: 10bfffd8 cmpnei r2,r2,-1 + 802abf8: 1000021e bne r2,zero,802ac04 + return TRUE; + 802abfc: 00800044 movi r2,1 + 802ac00: 00000106 br 802ac08 + + return FALSE; + 802ac04: 0005883a mov r2,zero +} + 802ac08: e037883a mov sp,fp + 802ac0c: df000017 ldw fp,0(sp) + 802ac10: dec00104 addi sp,sp,4 + 802ac14: f800283a ret + +0802ac18 : + * RETURNS: void + */ + +void +np_stripoptions(struct ip * ti, struct mbuf * m) +{ + 802ac18: defffb04 addi sp,sp,-20 + 802ac1c: dfc00415 stw ra,16(sp) + 802ac20: df000315 stw fp,12(sp) + 802ac24: df000304 addi fp,sp,12 + 802ac28: e13ffe15 stw r4,-8(fp) + 802ac2c: e17ffd15 stw r5,-12(fp) + int ihlen; + + /* get the IP header length in octets */ + ihlen = (ti->ip_ver_ihl & 0x0f) << 2; + 802ac30: e0bffe17 ldw r2,-8(fp) + 802ac34: 10800003 ldbu r2,0(r2) + 802ac38: 10803fcc andi r2,r2,255 + 802ac3c: 100490ba slli r2,r2,2 + 802ac40: 10800f0c andi r2,r2,60 + 802ac44: e0bfff15 stw r2,-4(fp) + + /* if it's <= 20 octets, there are no IP header options to strip */ + if (ihlen <= 20) + 802ac48: e0bfff17 ldw r2,-4(fp) + 802ac4c: 10800548 cmpgei r2,r2,21 + 802ac50: 10002726 beq r2,zero,802acf0 + return; + + /* figure out how much to strip: we want to keep the 20-octet IP header */ + ihlen -= 20; + 802ac54: e0bfff17 ldw r2,-4(fp) + 802ac58: 10bffb04 addi r2,r2,-20 + 802ac5c: e0bfff15 stw r2,-4(fp) + + /* remove the stripped options from the IP datagram length */ + ti->ip_len -= ihlen; + 802ac60: e0bffe17 ldw r2,-8(fp) + 802ac64: 1080008b ldhu r2,2(r2) + 802ac68: e0ffff17 ldw r3,-4(fp) + 802ac6c: 10c5c83a sub r2,r2,r3 + 802ac70: 1007883a mov r3,r2 + 802ac74: e0bffe17 ldw r2,-8(fp) + 802ac78: 10c0008d sth r3,2(r2) + + /* and from the IP header length (which will be 5*4 octets long) */ + ti->ip_ver_ihl = (ti->ip_ver_ihl & 0xf0) | 5; + 802ac7c: e0bffe17 ldw r2,-8(fp) + 802ac80: 10800003 ldbu r2,0(r2) + 802ac84: 1007883a mov r3,r2 + 802ac88: 00bffc04 movi r2,-16 + 802ac8c: 1884703a and r2,r3,r2 + 802ac90: 10800154 ori r2,r2,5 + 802ac94: 1007883a mov r3,r2 + 802ac98: e0bffe17 ldw r2,-8(fp) + 802ac9c: 10c00005 stb r3,0(r2) + + /* move the 20-octet IP header up against the IP payload */ + MEMMOVE( ((char*)ti) + ihlen, ti, 20); + 802aca0: e0bfff17 ldw r2,-4(fp) + 802aca4: e0fffe17 ldw r3,-8(fp) + 802aca8: 1885883a add r2,r3,r2 + 802acac: 01800504 movi r6,20 + 802acb0: e17ffe17 ldw r5,-8(fp) + 802acb4: 1009883a mov r4,r2 + 802acb8: 80087b80 call 80087b8 + m->m_len -= ihlen; + 802acbc: e0bffd17 ldw r2,-12(fp) + 802acc0: 10c00217 ldw r3,8(r2) + 802acc4: e0bfff17 ldw r2,-4(fp) + 802acc8: 1887c83a sub r3,r3,r2 + 802accc: e0bffd17 ldw r2,-12(fp) + 802acd0: 10c00215 stw r3,8(r2) + m->m_data += ihlen; + 802acd4: e0bffd17 ldw r2,-12(fp) + 802acd8: 10c00317 ldw r3,12(r2) + 802acdc: e0bfff17 ldw r2,-4(fp) + 802ace0: 1887883a add r3,r3,r2 + 802ace4: e0bffd17 ldw r2,-12(fp) + 802ace8: 10c00315 stw r3,12(r2) + 802acec: 00000106 br 802acf4 + return; + 802acf0: 0001883a nop +} + 802acf4: e037883a mov sp,fp + 802acf8: dfc00117 ldw ra,4(sp) + 802acfc: df000017 ldw fp,0(sp) + 802ad00: dec00204 addi sp,sp,8 + 802ad04: f800283a ret + +0802ad08 : + * RETURNS: + */ + +void +so_icmpdu(PACKET p, struct destun * pdp) +{ + 802ad08: defff304 addi sp,sp,-52 + 802ad0c: dfc00c15 stw ra,48(sp) + 802ad10: df000b15 stw fp,44(sp) + 802ad14: df000b04 addi fp,sp,44 + 802ad18: e13ff815 stw r4,-32(fp) + 802ad1c: e17ff715 stw r5,-36(fp) + struct inpcb * inp; + struct socket * so; + struct tcpcb * tp; + + /* extract information about packet which generated DU */ + fhost = htonl(pdp->dip.ip_dest); + 802ad20: e0bff717 ldw r2,-36(fp) + 802ad24: 10800617 ldw r2,24(r2) + 802ad28: 1006d63a srli r3,r2,24 + 802ad2c: e0bff717 ldw r2,-36(fp) + 802ad30: 10800617 ldw r2,24(r2) + 802ad34: 1004d23a srli r2,r2,8 + 802ad38: 10bfc00c andi r2,r2,65280 + 802ad3c: 1886b03a or r3,r3,r2 + 802ad40: e0bff717 ldw r2,-36(fp) + 802ad44: 10800617 ldw r2,24(r2) + 802ad48: 1004923a slli r2,r2,8 + 802ad4c: 10803fec andhi r2,r2,255 + 802ad50: 1886b03a or r3,r3,r2 + 802ad54: e0bff717 ldw r2,-36(fp) + 802ad58: 10800617 ldw r2,24(r2) + 802ad5c: 1004963a slli r2,r2,24 + 802ad60: 1884b03a or r2,r3,r2 + 802ad64: e0bffe15 stw r2,-8(fp) + lhost = htonl(pdp->dip.ip_src); + 802ad68: e0bff717 ldw r2,-36(fp) + 802ad6c: 10800517 ldw r2,20(r2) + 802ad70: 1006d63a srli r3,r2,24 + 802ad74: e0bff717 ldw r2,-36(fp) + 802ad78: 10800517 ldw r2,20(r2) + 802ad7c: 1004d23a srli r2,r2,8 + 802ad80: 10bfc00c andi r2,r2,65280 + 802ad84: 1886b03a or r3,r3,r2 + 802ad88: e0bff717 ldw r2,-36(fp) + 802ad8c: 10800517 ldw r2,20(r2) + 802ad90: 1004923a slli r2,r2,8 + 802ad94: 10803fec andhi r2,r2,255 + 802ad98: 1886b03a or r3,r3,r2 + 802ad9c: e0bff717 ldw r2,-36(fp) + 802ada0: 10800517 ldw r2,20(r2) + 802ada4: 1004963a slli r2,r2,24 + 802ada8: 1884b03a or r2,r3,r2 + 802adac: e0bffd15 stw r2,-12(fp) + lport = htons(*(unshort*)(&pdp->ddata[0])); + 802adb0: e0bff717 ldw r2,-36(fp) + 802adb4: 10800704 addi r2,r2,28 + 802adb8: 1080000b ldhu r2,0(r2) + 802adbc: 10bfffcc andi r2,r2,65535 + 802adc0: 1004d23a srli r2,r2,8 + 802adc4: 1007883a mov r3,r2 + 802adc8: e0bff717 ldw r2,-36(fp) + 802adcc: 10800704 addi r2,r2,28 + 802add0: 1080000b ldhu r2,0(r2) + 802add4: 10bfffcc andi r2,r2,65535 + 802add8: 1004923a slli r2,r2,8 + 802addc: 1884b03a or r2,r3,r2 + 802ade0: e0bffc8d sth r2,-14(fp) + fport = htons(*(unshort*)(&pdp->ddata[2])); + 802ade4: e0bff717 ldw r2,-36(fp) + 802ade8: 10800784 addi r2,r2,30 + 802adec: 1080000b ldhu r2,0(r2) + 802adf0: 10bfffcc andi r2,r2,65535 + 802adf4: 1004d23a srli r2,r2,8 + 802adf8: 1007883a mov r3,r2 + 802adfc: e0bff717 ldw r2,-36(fp) + 802ae00: 10800784 addi r2,r2,30 + 802ae04: 1080000b ldhu r2,0(r2) + 802ae08: 10bfffcc andi r2,r2,65535 + 802ae0c: 1004923a slli r2,r2,8 + 802ae10: 1884b03a or r2,r3,r2 + 802ae14: e0bffc0d sth r2,-16(fp) +#ifndef IP_PMTU + /* if it's a datagram-too-big message, ignore it -- As the + * build isn't using PMTU Discovery this packet is most + * probably a Denial of Service Attack. + */ + if(pdp->dcode == DSTFRAG) + 802ae18: e0bff717 ldw r2,-36(fp) + 802ae1c: 10800043 ldbu r2,1(r2) + 802ae20: 10803fcc andi r2,r2,255 + 802ae24: 1080201c xori r2,r2,128 + 802ae28: 10bfe004 addi r2,r2,-128 + 802ae2c: 10800118 cmpnei r2,r2,4 + 802ae30: 10006e26 beq r2,zero,802afec + goto done; + } +#endif /* IP_PMTU */ + + /* if it's a TCP connection, clean it up */ + if (pdp->dip.ip_prot == TCPTP) + 802ae34: e0bff717 ldw r2,-36(fp) + 802ae38: 10800443 ldbu r2,17(r2) + 802ae3c: 10803fcc andi r2,r2,255 + 802ae40: 10800198 cmpnei r2,r2,6 + 802ae44: 1000221e bne r2,zero,802aed0 + { + /* find associated data structs and socket */ + inp = in_pcblookup(&tcb, fhost, fport, lhost, lport, INPLOOKUP_WILDCARD); + 802ae48: e13ffc0b ldhu r4,-16(fp) + 802ae4c: e0bffc8b ldhu r2,-14(fp) + 802ae50: 00c00044 movi r3,1 + 802ae54: d8c00115 stw r3,4(sp) + 802ae58: d8800015 stw r2,0(sp) + 802ae5c: e1fffd17 ldw r7,-12(fp) + 802ae60: 200d883a mov r6,r4 + 802ae64: e17ffe17 ldw r5,-8(fp) + 802ae68: 010201b4 movhi r4,2054 + 802ae6c: 21389904 addi r4,r4,-7580 + 802ae70: 8040b600 call 8040b60 + 802ae74: e0bffb15 stw r2,-20(fp) + if (inp == 0) + 802ae78: e0bffb17 ldw r2,-20(fp) + 802ae7c: 10005d26 beq r2,zero,802aff4 + goto done; + so = inp->inp_socket; + 802ae80: e0bffb17 ldw r2,-20(fp) + 802ae84: 10800817 ldw r2,32(r2) + 802ae88: e0bffa15 stw r2,-24(fp) + if (so == 0) + 802ae8c: e0bffa17 ldw r2,-24(fp) + 802ae90: 10005a26 beq r2,zero,802affc + goto done; + tp = intotcpcb(inp); + 802ae94: e0bffb17 ldw r2,-20(fp) + 802ae98: 10800917 ldw r2,36(r2) + 802ae9c: e0bff915 stw r2,-28(fp) + if (tp) + 802aea0: e0bff917 ldw r2,-28(fp) + 802aea4: 10000626 beq r2,zero,802aec0 + { + if (tp->t_state <= TCPS_LISTEN) + 802aea8: e0bff917 ldw r2,-28(fp) + 802aeac: 10800217 ldw r2,8(r2) + 802aeb0: 10800088 cmpgei r2,r2,2 + 802aeb4: 10005326 beq r2,zero,802b004 + goto done; + } + } +#endif + + tcp_close(tp); + 802aeb8: e13ff917 ldw r4,-28(fp) + 802aebc: 80350e80 call 80350e8 + } + so->so_error = ECONNREFUSED; /* set error for socket owner */ + 802aec0: e0bffa17 ldw r2,-24(fp) + 802aec4: 00c01bc4 movi r3,111 + 802aec8: 10c00615 stw r3,24(r2) + 802aecc: 00005406 br 802b020 + } +#ifdef UDP_SOCKETS /* this sockets layer supports UDP too */ + else if(pdp->dip.ip_prot == UDP_PROT) + 802aed0: e0bff717 ldw r2,-36(fp) + 802aed4: 10800443 ldbu r2,17(r2) + 802aed8: 10803fcc andi r2,r2,255 + 802aedc: 10800458 cmpnei r2,r2,17 + 802aee0: 10004a1e bne r2,zero,802b00c + { + UDPCONN tmp; + /* search udp table (which keeps hosts in net endian) */ + for (tmp = firstudp; tmp; tmp = tmp->u_next) + 802aee4: d0a09e17 ldw r2,-32136(gp) + 802aee8: e0bfff15 stw r2,-4(fp) + 802aeec: 00002106 br 802af74 + if ((tmp->u_fport == fport || tmp->u_fport == 0) && + 802aef0: e0bfff17 ldw r2,-4(fp) + 802aef4: 1080020b ldhu r2,8(r2) + 802aef8: e0fffc0b ldhu r3,-16(fp) + 802aefc: 10bfffcc andi r2,r2,65535 + 802af00: 18800426 beq r3,r2,802af14 + 802af04: e0bfff17 ldw r2,-4(fp) + 802af08: 1080020b ldhu r2,8(r2) + 802af0c: 10bfffcc andi r2,r2,65535 + 802af10: 1000151e bne r2,zero,802af68 + (tmp->u_fhost == htonl(fhost)) && + 802af14: e0bfff17 ldw r2,-4(fp) + 802af18: 10c00417 ldw r3,16(r2) + 802af1c: e0bffe17 ldw r2,-8(fp) + 802af20: 1008d63a srli r4,r2,24 + 802af24: e0bffe17 ldw r2,-8(fp) + 802af28: 1004d23a srli r2,r2,8 + 802af2c: 10bfc00c andi r2,r2,65280 + 802af30: 2088b03a or r4,r4,r2 + 802af34: e0bffe17 ldw r2,-8(fp) + 802af38: 1004923a slli r2,r2,8 + 802af3c: 10803fec andhi r2,r2,255 + 802af40: 2088b03a or r4,r4,r2 + 802af44: e0bffe17 ldw r2,-8(fp) + 802af48: 1004963a slli r2,r2,24 + 802af4c: 2084b03a or r2,r4,r2 + if ((tmp->u_fport == fport || tmp->u_fport == 0) && + 802af50: 1880051e bne r3,r2,802af68 + (tmp->u_lport == lport)) + 802af54: e0bfff17 ldw r2,-4(fp) + 802af58: 1080018b ldhu r2,6(r2) + (tmp->u_fhost == htonl(fhost)) && + 802af5c: e0fffc8b ldhu r3,-14(fp) + 802af60: 10bfffcc andi r2,r2,65535 + 802af64: 18800626 beq r3,r2,802af80 + for (tmp = firstudp; tmp; tmp = tmp->u_next) + 802af68: e0bfff17 ldw r2,-4(fp) + 802af6c: 10800017 ldw r2,0(r2) + 802af70: e0bfff15 stw r2,-4(fp) + 802af74: e0bfff17 ldw r2,-4(fp) + 802af78: 103fdd1e bne r2,zero,802aef0 + 802af7c: 00000106 br 802af84 + { + break; /* found our UDP table entry */ + 802af80: 0001883a nop + } + if (!tmp) + 802af84: e0bfff17 ldw r2,-4(fp) + 802af88: 10002226 beq r2,zero,802b014 + goto done; + so = (struct socket *)tmp->u_data; + 802af8c: e0bfff17 ldw r2,-4(fp) + 802af90: 10800617 ldw r2,24(r2) + 802af94: e0bffa15 stw r2,-24(fp) + /* May be non-socket (lightweight) UDP connection. */ + if (so->so_type != SOCK_DGRAM) + 802af98: e0bffa17 ldw r2,-24(fp) + 802af9c: 10800983 ldbu r2,38(r2) + 802afa0: 10803fcc andi r2,r2,255 + 802afa4: 1080201c xori r2,r2,128 + 802afa8: 10bfe004 addi r2,r2,-128 + 802afac: 108000a0 cmpeqi r2,r2,2 + 802afb0: 10001a26 beq r2,zero,802b01c + goto done; + so->so_error = ECONNREFUSED; /* set error for socket owner */ + 802afb4: e0bffa17 ldw r2,-24(fp) + 802afb8: 00c01bc4 movi r3,111 + 802afbc: 10c00615 stw r3,24(r2) + /* do a select() notify on socket here */ + sorwakeup(so); + 802afc0: e0bffa17 ldw r2,-24(fp) + 802afc4: 10800a04 addi r2,r2,40 + 802afc8: 100b883a mov r5,r2 + 802afcc: e13ffa17 ldw r4,-24(fp) + 802afd0: 802f94c0 call 802f94c + sowwakeup(so); + 802afd4: e0bffa17 ldw r2,-24(fp) + 802afd8: 10801204 addi r2,r2,72 + 802afdc: 100b883a mov r5,r2 + 802afe0: e13ffa17 ldw r4,-24(fp) + 802afe4: 802f94c0 call 802f94c + 802afe8: 00000d06 br 802b020 + goto done; + 802afec: 0001883a nop + 802aff0: 00000b06 br 802b020 + goto done; + 802aff4: 0001883a nop + 802aff8: 00000906 br 802b020 + goto done; + 802affc: 0001883a nop + 802b000: 00000706 br 802b020 + goto done; + 802b004: 0001883a nop + 802b008: 00000506 br 802b020 + } +#endif /* UDP_SOCKETS */ + else + goto done; + 802b00c: 0001883a nop + 802b010: 00000306 br 802b020 + goto done; + 802b014: 0001883a nop + 802b018: 00000106 br 802b020 + goto done; + 802b01c: 0001883a nop + if (pdp->dcode == DSTFRAG) + pmtucache_set(pdp->dip.ip_dest, htons(pdp->dno2)); +#endif /* IP_PMTU */ + +done: + LOCK_NET_RESOURCE(FREEQ_RESID); + 802b020: 01000084 movi r4,2 + 802b024: 8028f380 call 8028f38 + pk_free(p); /* done with original packet */ + 802b028: e13ff817 ldw r4,-32(fp) + 802b02c: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 802b030: 01000084 movi r4,2 + 802b034: 8028ff40 call 8028ff4 + return; + 802b038: 0001883a nop +} + 802b03c: e037883a mov sp,fp + 802b040: dfc00117 ldw ra,4(sp) + 802b044: df000017 ldw fp,0(sp) + 802b048: dec00204 addi sp,sp,8 + 802b04c: f800283a ret + +0802b050 : +unsigned long nextslow = 0L; /* next slow tcp timer time */ +static int in_tcptick = 0; /* reentry gaurd */ + +void +tcp_tick() +{ + 802b050: defffe04 addi sp,sp,-8 + 802b054: dfc00115 stw ra,4(sp) + 802b058: df000015 stw fp,0(sp) + 802b05c: d839883a mov fp,sp + /* guard against re-entry */ + if (in_tcptick) + 802b060: d0a08217 ldw r2,-32248(gp) + 802b064: 1000121e bne r2,zero,802b0b0 + return; + in_tcptick++; + 802b068: d0a08217 ldw r2,-32248(gp) + 802b06c: 10800044 addi r2,r2,1 + 802b070: d0a08215 stw r2,-32248(gp) + + LOCK_NET_RESOURCE(NET_RESID); + 802b074: 0009883a mov r4,zero + 802b078: 8028f380 call 8028f38 + + if (cticks >= nextslow) /* time to do it again */ + 802b07c: d0e07d17 ldw r3,-32268(gp) + 802b080: d0a08117 ldw r2,-32252(gp) + 802b084: 18800436 bltu r3,r2,802b098 + { + tcp_slowtimo(); /* call routine in BSD tcp_timr.c */ + 802b088: 80353080 call 8035308 +#ifdef CSUM_DEMO + nextslow = cticks + (TPS/5); /* another 200 ms */ +#else + nextslow = cticks + (TPS/2); /* another 500 ms */ + 802b08c: d0a07d17 ldw r2,-32268(gp) + 802b090: 10800c84 addi r2,r2,50 + 802b094: d0a08115 stw r2,-32252(gp) + +#ifdef DO_DELAY_ACKS + tcp_fasttimo(); +#endif /* DO_DELAY_ACKS */ + + UNLOCK_NET_RESOURCE(NET_RESID); + 802b098: 0009883a mov r4,zero + 802b09c: 8028ff40 call 8028ff4 + + in_tcptick--; + 802b0a0: d0a08217 ldw r2,-32248(gp) + 802b0a4: 10bfffc4 addi r2,r2,-1 + 802b0a8: d0a08215 stw r2,-32248(gp) + 802b0ac: 00000106 br 802b0b4 + return; + 802b0b0: 0001883a nop +} + 802b0b4: e037883a mov sp,fp + 802b0b8: dfc00117 ldw ra,4(sp) + 802b0bc: df000017 ldw fp,0(sp) + 802b0c0: dec00204 addi sp,sp,8 + 802b0c4: f800283a ret + +0802b0c8 : + * or NULL if no matching raw IP endpoint is found. + */ + +struct ipraw_ep * +rawip_lookup(struct socket * so) +{ + 802b0c8: defffd04 addi sp,sp,-12 + 802b0cc: df000215 stw fp,8(sp) + 802b0d0: df000204 addi fp,sp,8 + 802b0d4: e13ffe15 stw r4,-8(fp) + struct ipraw_ep * tmp; + + for (tmp = ipraw_eps; tmp; tmp = tmp->ipr_next) + 802b0d8: d0a09b17 ldw r2,-32148(gp) + 802b0dc: e0bfff15 stw r2,-4(fp) + 802b0e0: 00000906 br 802b108 + if (tmp->ipr_data == (void*)so) + 802b0e4: e0bfff17 ldw r2,-4(fp) + 802b0e8: 10800417 ldw r2,16(r2) + 802b0ec: e0fffe17 ldw r3,-8(fp) + 802b0f0: 1880021e bne r3,r2,802b0fc + return (tmp); + 802b0f4: e0bfff17 ldw r2,-4(fp) + 802b0f8: 00000606 br 802b114 + for (tmp = ipraw_eps; tmp; tmp = tmp->ipr_next) + 802b0fc: e0bfff17 ldw r2,-4(fp) + 802b100: 10800017 ldw r2,0(r2) + 802b104: e0bfff15 stw r2,-4(fp) + 802b108: e0bfff17 ldw r2,-4(fp) + 802b10c: 103ff51e bne r2,zero,802b0e4 + + return NULL; /* didn't find it */ + 802b110: 0005883a mov r2,zero +} + 802b114: e037883a mov sp,fp + 802b118: df000017 ldw fp,0(sp) + 802b11c: dec00104 addi sp,sp,4 + 802b120: f800283a ret + +0802b124 : + * indicates that the packet has not been accepted. + */ + +int +rawip_soinput(PACKET pkt, void * so_ptr) +{ + 802b124: defff504 addi sp,sp,-44 + 802b128: dfc00a15 stw ra,40(sp) + 802b12c: df000915 stw fp,36(sp) + 802b130: df000904 addi fp,sp,36 + 802b134: e13ff815 stw r4,-32(fp) + 802b138: e17ff715 stw r5,-36(fp) + struct mbuf * m_in; /* packet/data mbuf */ + struct socket * so = (struct socket *)so_ptr; + 802b13c: e0bff717 ldw r2,-36(fp) + 802b140: e0bfff15 stw r2,-4(fp) + struct sockaddr_in sin; + + LOCK_NET_RESOURCE(NET_RESID); + 802b144: 0009883a mov r4,zero + 802b148: 8028f380 call 8028f38 + + /* make sure we're not flooding input buffers */ + if ((so->so_rcv.sb_cc + pkt->nb_plen) >= so->so_rcv.sb_hiwat) + 802b14c: e0bfff17 ldw r2,-4(fp) + 802b150: 10c00a17 ldw r3,40(r2) + 802b154: e0bff817 ldw r2,-32(fp) + 802b158: 10800417 ldw r2,16(r2) + 802b15c: 1887883a add r3,r3,r2 + 802b160: e0bfff17 ldw r2,-4(fp) + 802b164: 10800b17 ldw r2,44(r2) + 802b168: 18800436 bltu r3,r2,802b17c + { + UNLOCK_NET_RESOURCE(NET_RESID); + 802b16c: 0009883a mov r4,zero + 802b170: 8028ff40 call 8028ff4 + return ENOBUFS; + 802b174: 00801a44 movi r2,105 + 802b178: 00005606 br 802b2d4 + } + + /* alloc mbuf for received data */ + m_in = m_getnbuf(MT_RXDATA, 0); + 802b17c: 000b883a mov r5,zero + 802b180: 01000044 movi r4,1 + 802b184: 8029a700 call 8029a70 + 802b188: e0bffe15 stw r2,-8(fp) + if (!m_in) + 802b18c: e0bffe17 ldw r2,-8(fp) + 802b190: 1000041e bne r2,zero,802b1a4 + { + UNLOCK_NET_RESOURCE(NET_RESID); + 802b194: 0009883a mov r4,zero + 802b198: 8028ff40 call 8028ff4 + return ENOBUFS; + 802b19c: 00801a44 movi r2,105 + 802b1a0: 00004c06 br 802b2d4 + } + + /* set data mbuf to point to start of IP header */ + m_in->pkt = pkt; + 802b1a4: e0bffe17 ldw r2,-8(fp) + 802b1a8: e0fff817 ldw r3,-32(fp) + 802b1ac: 10c00115 stw r3,4(r2) + m_in->m_base = pkt->nb_buff; + 802b1b0: e0bff817 ldw r2,-32(fp) + 802b1b4: 10c00117 ldw r3,4(r2) + 802b1b8: e0bffe17 ldw r2,-8(fp) + 802b1bc: 10c00415 stw r3,16(r2) + m_in->m_memsz = pkt->nb_blen; + 802b1c0: e0bff817 ldw r2,-32(fp) + 802b1c4: 10c00217 ldw r3,8(r2) + 802b1c8: e0bffe17 ldw r2,-8(fp) + 802b1cc: 10c00515 stw r3,20(r2) + m_in->m_data = pkt->nb_prot; + 802b1d0: e0bff817 ldw r2,-32(fp) + 802b1d4: 10c00317 ldw r3,12(r2) + 802b1d8: e0bffe17 ldw r2,-8(fp) + 802b1dc: 10c00315 stw r3,12(r2) + m_in->m_len = pkt->nb_plen; + 802b1e0: e0bff817 ldw r2,-32(fp) + 802b1e4: 10c00417 ldw r3,16(r2) + 802b1e8: e0bffe17 ldw r2,-8(fp) + 802b1ec: 10c00215 stw r3,8(r2) + + /* if this socket doesn't have IP_HDRINCL set, adjust the + * mbuf to skip past the IP header + */ + if (!(so->so_options & SO_HDRINCL)) + 802b1f0: e0bfff17 ldw r2,-4(fp) + 802b1f4: 10800417 ldw r2,16(r2) + 802b1f8: 1088000c andi r2,r2,8192 + 802b1fc: 1000131e bne r2,zero,802b24c + { + unsigned int ihl = + (((struct ip *)(pkt->nb_prot))->ip_ver_ihl & 0x0f) << 2; + 802b200: e0bff817 ldw r2,-32(fp) + 802b204: 10800317 ldw r2,12(r2) + 802b208: 10800003 ldbu r2,0(r2) + 802b20c: 10803fcc andi r2,r2,255 + 802b210: 100490ba slli r2,r2,2 + unsigned int ihl = + 802b214: 10800f0c andi r2,r2,60 + 802b218: e0bffd15 stw r2,-12(fp) + m_in->m_data += ihl; + 802b21c: e0bffe17 ldw r2,-8(fp) + 802b220: 10c00317 ldw r3,12(r2) + 802b224: e0bffd17 ldw r2,-12(fp) + 802b228: 1887883a add r3,r3,r2 + 802b22c: e0bffe17 ldw r2,-8(fp) + 802b230: 10c00315 stw r3,12(r2) + m_in->m_len -= ihl; + 802b234: e0bffe17 ldw r2,-8(fp) + 802b238: 10c00217 ldw r3,8(r2) + 802b23c: e0bffd17 ldw r2,-12(fp) + 802b240: 1887c83a sub r3,r3,r2 + 802b244: e0bffe17 ldw r2,-8(fp) + 802b248: 10c00215 stw r3,8(r2) + } + + /* fill in net address info for pass to socket append()ers */ + sin.sin_addr.s_addr = pkt->fhost; + 802b24c: e0bff817 ldw r2,-32(fp) + 802b250: 10800717 ldw r2,28(r2) + 802b254: e0bffa15 stw r2,-24(fp) + sin.sin_port = 0; + 802b258: e03ff98d sth zero,-26(fp) + sin.sin_family = AF_INET; + 802b25c: 00800084 movi r2,2 + 802b260: e0bff90d sth r2,-28(fp) + + /* attempt to append address information to mbuf */ + if (!sbappendaddr(&so->so_rcv, (struct sockaddr *)&sin, m_in)) + 802b264: e0bfff17 ldw r2,-4(fp) + 802b268: 10800a04 addi r2,r2,40 + 802b26c: e0fff904 addi r3,fp,-28 + 802b270: e1bffe17 ldw r6,-8(fp) + 802b274: 180b883a mov r5,r3 + 802b278: 1009883a mov r4,r2 + 802b27c: 802fc740 call 802fc74 + 802b280: 1000081e bne r2,zero,802b2a4 + { + /* set the pkt field in the mbuf to NULL so m_free() below wont + * free the packet buffer, because that is left to the + * underlying stack + */ + m_in->pkt = NULL; + 802b284: e0bffe17 ldw r2,-8(fp) + 802b288: 10000115 stw zero,4(r2) + /* free only the mbuf itself */ + m_free(m_in); + 802b28c: e13ffe17 ldw r4,-8(fp) + 802b290: 8029bf80 call 8029bf8 + /* return error condition so caller can free the packet buffer */ + UNLOCK_NET_RESOURCE(NET_RESID); + 802b294: 0009883a mov r4,zero + 802b298: 8028ff40 call 8028ff4 + return ENOBUFS; + 802b29c: 00801a44 movi r2,105 + 802b2a0: 00000c06 br 802b2d4 + } + + tcp_wakeup(&so->so_rcv); /* wake anyone waiting for this */ + 802b2a4: e0bfff17 ldw r2,-4(fp) + 802b2a8: 10800a04 addi r2,r2,40 + 802b2ac: 1009883a mov r4,r2 + 802b2b0: 8027ba00 call 8027ba0 + + sorwakeup(so); /* wake up selects too */ + 802b2b4: e0bfff17 ldw r2,-4(fp) + 802b2b8: 10800a04 addi r2,r2,40 + 802b2bc: 100b883a mov r5,r2 + 802b2c0: e13fff17 ldw r4,-4(fp) + 802b2c4: 802f94c0 call 802f94c + + UNLOCK_NET_RESOURCE(NET_RESID); + 802b2c8: 0009883a mov r4,zero + 802b2cc: 8028ff40 call 8028ff4 + return 0; + 802b2d0: 0005883a mov r2,zero +} + 802b2d4: e037883a mov sp,fp + 802b2d8: dfc00117 ldw ra,4(sp) + 802b2dc: df000017 ldw fp,0(sp) + 802b2e0: dec00204 addi sp,sp,8 + 802b2e4: f800283a ret + +0802b2e8 : + +int +rawip_usrreq(struct socket * so, + struct mbuf * m, + struct mbuf * nam) +{ + 802b2e8: deffef04 addi sp,sp,-68 + 802b2ec: dfc01015 stw ra,64(sp) + 802b2f0: df000f15 stw fp,60(sp) + 802b2f4: dc000e15 stw r16,56(sp) + 802b2f8: df000f04 addi fp,sp,60 + 802b2fc: e13ff415 stw r4,-48(fp) + 802b300: e17ff315 stw r5,-52(fp) + 802b304: e1bff215 stw r6,-56(fp) + u_char prot; + struct ip * pip; + int req; + NET ifp; /* ptr to network interface structure */ + + req = so->so_req; /* get request from socket struct */ + 802b308: e0bff417 ldw r2,-48(fp) + 802b30c: 10800717 ldw r2,28(r2) + 802b310: e0bffa15 stw r2,-24(fp) + + switch (req) + 802b314: e0bffa17 ldw r2,-24(fp) + 802b318: 10800468 cmpgeui r2,r2,17 + 802b31c: 1001b91e bne r2,zero,802ba04 + 802b320: e0bffa17 ldw r2,-24(fp) + 802b324: 100690ba slli r3,r2,2 + 802b328: 008200f4 movhi r2,2051 + 802b32c: 1885883a add r2,r3,r2 + 802b330: 10acce17 ldw r2,-19656(r2) + 802b334: 1000683a jmp r2 + 802b338: 0802b37c xorhi zero,at,2765 + 802b33c: 0802b404 addi zero,at,2768 + 802b340: 0802b440 call 802b44 + 802b344: 0802ba04 addi zero,at,2792 + 802b348: 0802b440 call 802b44 + 802b34c: 0802ba04 addi zero,at,2792 + 802b350: 0802b9f8 rdprs zero,at,2791 + 802b354: 0802ba04 addi zero,at,2792 + 802b358: 0802b9f8 rdprs zero,at,2791 + 802b35c: 0802b5c8 cmpgei zero,at,2775 + 802b360: 0802ba04 addi zero,at,2792 + 802b364: 0802ba04 addi zero,at,2792 + 802b368: 0802ba04 addi zero,at,2792 + 802b36c: 0802ba04 addi zero,at,2792 + 802b370: 0802ba04 addi zero,at,2792 + 802b374: 0802b964 muli zero,at,2789 + 802b378: 0802b964 muli zero,at,2789 + { + case PRU_ATTACH: + /* fake small windows so sockets asks us to move data */ + so->so_rcv.sb_hiwat = so->so_snd.sb_hiwat = + ip_raw_maxalloc(so->so_options & SO_HDRINCL); + 802b37c: e0bff417 ldw r2,-48(fp) + 802b380: 10800417 ldw r2,16(r2) + 802b384: 1088000c andi r2,r2,8192 + 802b388: 1009883a mov r4,r2 + 802b38c: 803cae00 call 803cae0 + 802b390: 1007883a mov r3,r2 + so->so_rcv.sb_hiwat = so->so_snd.sb_hiwat = + 802b394: e0bff417 ldw r2,-48(fp) + 802b398: 10c01315 stw r3,76(r2) + 802b39c: e0bff417 ldw r2,-48(fp) + 802b3a0: 10c01317 ldw r3,76(r2) + 802b3a4: e0bff417 ldw r2,-48(fp) + 802b3a8: 10c00b15 stw r3,44(r2) + /* make a raw IP endpoint */ + prot = (u_char)(MBUF2LONG(nam)); + 802b3ac: e0bff217 ldw r2,-56(fp) + 802b3b0: e0bff9c5 stb r2,-25(fp) + /* unlock the net resource; IP will immediatly re-lock it */ + UNLOCK_NET_RESOURCE(NET_RESID); + 802b3b4: 0009883a mov r4,zero + 802b3b8: 8028ff40 call 8028ff4 + ep = ip_raw_open(prot, 0L, 0L, rawip_soinput, so); + 802b3bc: e0fff9c3 ldbu r3,-25(fp) + 802b3c0: e0bff417 ldw r2,-48(fp) + 802b3c4: d8800015 stw r2,0(sp) + 802b3c8: 01c200f4 movhi r7,2051 + 802b3cc: 39ec4904 addi r7,r7,-20188 + 802b3d0: 000d883a mov r6,zero + 802b3d4: 000b883a mov r5,zero + 802b3d8: 1809883a mov r4,r3 + 802b3dc: 803c63c0 call 803c63c + 802b3e0: e0bff815 stw r2,-32(fp) + LOCK_NET_RESOURCE(NET_RESID); + 802b3e4: 0009883a mov r4,zero + 802b3e8: 8028f380 call 8028f38 + if (!ep) + 802b3ec: e0bff817 ldw r2,-32(fp) + 802b3f0: 1000021e bne r2,zero,802b3fc + return(EINVAL); + 802b3f4: 00800584 movi r2,22 + 802b3f8: 00018306 br 802ba08 + return 0; + 802b3fc: 0005883a mov r2,zero + 802b400: 00018106 br 802ba08 + case PRU_DETACH: + /* delete the raw IP endpoint */ + ep = rawip_lookup(so); + 802b404: e13ff417 ldw r4,-48(fp) + 802b408: 802b0c80 call 802b0c8 + 802b40c: e0bff815 stw r2,-32(fp) + if (!ep) + 802b410: e0bff817 ldw r2,-32(fp) + 802b414: 1000021e bne r2,zero,802b420 + return(EINVAL); + 802b418: 00800584 movi r2,22 + 802b41c: 00017a06 br 802ba08 + /* unlock the net resource; IP will immediatly re-lock it */ + UNLOCK_NET_RESOURCE(NET_RESID); + 802b420: 0009883a mov r4,zero + 802b424: 8028ff40 call 8028ff4 + ip_raw_close(ep); + 802b428: e13ff817 ldw r4,-32(fp) + 802b42c: 803c7140 call 803c714 + LOCK_NET_RESOURCE(NET_RESID); + 802b430: 0009883a mov r4,zero + 802b434: 8028f380 call 8028f38 + return 0; + 802b438: 0005883a mov r2,zero + 802b43c: 00017206 br 802ba08 + * a default address for sending + */ + /* fall through to shared bind logic */ + case PRU_BIND: + /* do bind parameters lookups and tests */ + if (nam == NULL) + 802b440: e0bff217 ldw r2,-56(fp) + 802b444: 1000021e bne r2,zero,802b450 + return(EINVAL); + 802b448: 00800584 movi r2,22 + 802b44c: 00016e06 br 802ba08 + sin = mtod(nam, struct sockaddr_in *); + 802b450: e0bff217 ldw r2,-56(fp) + 802b454: 10800317 ldw r2,12(r2) + 802b458: e0bff715 stw r2,-36(fp) + if (sin == NULL) + 802b45c: e0bff717 ldw r2,-36(fp) + 802b460: 1000021e bne r2,zero,802b46c + return(EINVAL); + 802b464: 00800584 movi r2,22 + 802b468: 00016706 br 802ba08 + if (nam->m_len != sizeof (*sin)) + 802b46c: e0bff217 ldw r2,-56(fp) + 802b470: 10800217 ldw r2,8(r2) + 802b474: 10800420 cmpeqi r2,r2,16 + 802b478: 1000021e bne r2,zero,802b484 + return(EINVAL); + 802b47c: 00800584 movi r2,22 + 802b480: 00016106 br 802ba08 + ep = rawip_lookup(so); + 802b484: e13ff417 ldw r4,-48(fp) + 802b488: 802b0c80 call 802b0c8 + 802b48c: e0bff815 stw r2,-32(fp) + if (!ep) + 802b490: e0bff817 ldw r2,-32(fp) + 802b494: 1000021e bne r2,zero,802b4a0 + return(EINVAL); + 802b498: 00800584 movi r2,22 + 802b49c: 00015a06 br 802ba08 + if (req == PRU_BIND) + 802b4a0: e0bffa17 ldw r2,-24(fp) + 802b4a4: 10800098 cmpnei r2,r2,2 + 802b4a8: 10001f1e bne r2,zero,802b528 + * if the caller-supplied address is INADDR_ANY, + * don't bind to a specific address; else, + * make sure the caller-supplied address is + * an interface IP address and if so, bind to that + */ + if (sin->sin_addr.s_addr == INADDR_ANY) + 802b4ac: e0bff717 ldw r2,-36(fp) + 802b4b0: 10800117 ldw r2,4(r2) + 802b4b4: 1000021e bne r2,zero,802b4c0 + { + lhost = 0L; + 802b4b8: e03ffc15 stw zero,-16(fp) + 802b4bc: 00001606 br 802b518 + } + else + { + lhost = sin->sin_addr.s_addr; + 802b4c0: e0bff717 ldw r2,-36(fp) + 802b4c4: 10800117 ldw r2,4(r2) + 802b4c8: e0bffc15 stw r2,-16(fp) + /* verify that lhost is a local interface address */ + for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next) + 802b4cc: 008201b4 movhi r2,2054 + 802b4d0: 10b6a617 ldw r2,-9576(r2) + 802b4d4: e0bffb15 stw r2,-20(fp) + 802b4d8: 00000706 br 802b4f8 + if (ifp->n_ipaddr == lhost) + 802b4dc: e0bffb17 ldw r2,-20(fp) + 802b4e0: 10800a17 ldw r2,40(r2) + 802b4e4: e0fffc17 ldw r3,-16(fp) + 802b4e8: 18800626 beq r3,r2,802b504 + for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next) + 802b4ec: e0bffb17 ldw r2,-20(fp) + 802b4f0: 10800017 ldw r2,0(r2) + 802b4f4: e0bffb15 stw r2,-20(fp) + 802b4f8: e0bffb17 ldw r2,-20(fp) + 802b4fc: 103ff71e bne r2,zero,802b4dc + 802b500: 00000106 br 802b508 + break; + 802b504: 0001883a nop + if (ifp == NULL) + 802b508: e0bffb17 ldw r2,-20(fp) + 802b50c: 1000021e bne r2,zero,802b518 + return(EADDRNOTAVAIL); + 802b510: 00801f44 movi r2,125 + 802b514: 00013c06 br 802ba08 + } + + /* bind the endpoint */ + ep->ipr_laddr = lhost; + 802b518: e0bff817 ldw r2,-32(fp) + 802b51c: e0fffc17 ldw r3,-16(fp) + 802b520: 10c00115 stw r3,4(r2) + 802b524: 00002606 br 802b5c0 + * + * if the caller-supplied address is INADDR_ANY, + * use the wildcard address; else, use the caller- + * supplied address + */ + if (sin->sin_addr.s_addr == INADDR_ANY) + 802b528: e0bff717 ldw r2,-36(fp) + 802b52c: 10800117 ldw r2,4(r2) + 802b530: 1000021e bne r2,zero,802b53c + fhost = 0L; + 802b534: e03ffd15 stw zero,-12(fp) + 802b538: 00000306 br 802b548 + else + fhost = sin->sin_addr.s_addr; + 802b53c: e0bff717 ldw r2,-36(fp) + 802b540: 10800117 ldw r2,4(r2) + 802b544: e0bffd15 stw r2,-12(fp) + /* connect the IP endpoint */ + ep->ipr_faddr = fhost; + 802b548: e0bff817 ldw r2,-32(fp) + 802b54c: e0fffd17 ldw r3,-12(fp) + 802b550: 10c00215 stw r3,8(r2) + /* mark the socket as connected or disconnected, as appropriate */ + if (fhost != 0L) { + 802b554: e0bffd17 ldw r2,-12(fp) + 802b558: 10000e26 beq r2,zero,802b594 + so->so_state &= ~(SS_ISCONNECTING|SS_ISDISCONNECTING); + 802b55c: e0bff417 ldw r2,-48(fp) + 802b560: 10c0088b ldhu r3,34(r2) + 802b564: 00bffcc4 movi r2,-13 + 802b568: 1884703a and r2,r3,r2 + 802b56c: 1007883a mov r3,r2 + 802b570: e0bff417 ldw r2,-48(fp) + 802b574: 10c0088d sth r3,34(r2) + so->so_state |= SS_ISCONNECTED; + 802b578: e0bff417 ldw r2,-48(fp) + 802b57c: 1080088b ldhu r2,34(r2) + 802b580: 10800094 ori r2,r2,2 + 802b584: 1007883a mov r3,r2 + 802b588: e0bff417 ldw r2,-48(fp) + 802b58c: 10c0088d sth r3,34(r2) + 802b590: 00000706 br 802b5b0 + } + else + { + so->so_state &= ~SS_ISCONNECTED; + 802b594: e0bff417 ldw r2,-48(fp) + 802b598: 10c0088b ldhu r3,34(r2) + 802b59c: 00bfff44 movi r2,-3 + 802b5a0: 1884703a and r2,r3,r2 + 802b5a4: 1007883a mov r3,r2 + 802b5a8: e0bff417 ldw r2,-48(fp) + 802b5ac: 10c0088d sth r3,34(r2) + } + /* since socket was in listen state, packets may be queued */ + sbflush(&so->so_rcv); /* dump these now */ + 802b5b0: e0bff417 ldw r2,-48(fp) + 802b5b4: 10800a04 addi r2,r2,40 + 802b5b8: 1009883a mov r4,r2 + 802b5bc: 803002c0 call 803002c + } + return 0; + 802b5c0: 0005883a mov r2,zero + 802b5c4: 00011006 br 802ba08 + case PRU_SEND: + /* do parameter lookups and tests */ + if (!m) /* no data passed? */ + 802b5c8: e0bff317 ldw r2,-52(fp) + 802b5cc: 1000021e bne r2,zero,802b5d8 + return(EINVAL); + 802b5d0: 00800584 movi r2,22 + 802b5d4: 00010c06 br 802ba08 + + ep = rawip_lookup(so); + 802b5d8: e13ff417 ldw r4,-48(fp) + 802b5dc: 802b0c80 call 802b0c8 + 802b5e0: e0bff815 stw r2,-32(fp) + if (!ep) + 802b5e4: e0bff817 ldw r2,-32(fp) + 802b5e8: 1000041e bne r2,zero,802b5fc + { + m_free(m); + 802b5ec: e13ff317 ldw r4,-52(fp) + 802b5f0: 8029bf80 call 8029bf8 + /* may be bogus socket, but more likely the connection may + have closed due to ICMP dest unreachable from other side. */ + return(ECONNREFUSED); + 802b5f4: 00801bc4 movi r2,111 + 802b5f8: 00010306 br 802ba08 + } + + if (nam == NULL) /* no sendto() info passed, must be send() */ + 802b5fc: e0bff217 ldw r2,-56(fp) + 802b600: 10000b1e bne r2,zero,802b630 + { + if (!(so->so_state & SS_ISCONNECTED)) + 802b604: e0bff417 ldw r2,-48(fp) + 802b608: 1080088b ldhu r2,34(r2) + 802b60c: 10bfffcc andi r2,r2,65535 + 802b610: 1080008c andi r2,r2,2 + 802b614: 1000021e bne r2,zero,802b620 + return (ENOTCONN); + 802b618: 00802004 movi r2,128 + 802b61c: 0000fa06 br 802ba08 + fhost = ep->ipr_faddr; + 802b620: e0bff817 ldw r2,-32(fp) + 802b624: 10800217 ldw r2,8(r2) + 802b628: e0bffd15 stw r2,-12(fp) + 802b62c: 00001406 br 802b680 + } + else + { + if (so->so_state & SS_ISCONNECTED) + 802b630: e0bff417 ldw r2,-48(fp) + 802b634: 1080088b ldhu r2,34(r2) + 802b638: 10bfffcc andi r2,r2,65535 + 802b63c: 1080008c andi r2,r2,2 + 802b640: 10000226 beq r2,zero,802b64c + return (EISCONN); + 802b644: 00801fc4 movi r2,127 + 802b648: 0000ef06 br 802ba08 + if (nam->m_len != sizeof (*sin)) + 802b64c: e0bff217 ldw r2,-56(fp) + 802b650: 10800217 ldw r2,8(r2) + 802b654: 10800420 cmpeqi r2,r2,16 + 802b658: 1000031e bne r2,zero,802b668 + { + dtrap(); + 802b65c: 8028cd40 call 8028cd4 + return (EINVAL); + 802b660: 00800584 movi r2,22 + 802b664: 0000e806 br 802ba08 + } + sin = mtod(nam, struct sockaddr_in *); + 802b668: e0bff217 ldw r2,-56(fp) + 802b66c: 10800317 ldw r2,12(r2) + 802b670: e0bff715 stw r2,-36(fp) + fhost = sin->sin_addr.s_addr; + 802b674: e0bff717 ldw r2,-36(fp) + 802b678: 10800117 ldw r2,4(r2) + 802b67c: e0bffd15 stw r2,-12(fp) + + /* since our pkt->nb_buff size is tied to max packet size, we + * assume our raw IP datagrams are always in one mbuf and that the + * mbuf -- but check anyway + */ + if (m->m_len > (unsigned)ip_raw_maxalloc(so->so_options & SO_HDRINCL)) + 802b680: e0bff317 ldw r2,-52(fp) + 802b684: 14000217 ldw r16,8(r2) + 802b688: e0bff417 ldw r2,-48(fp) + 802b68c: 10800417 ldw r2,16(r2) + 802b690: 1088000c andi r2,r2,8192 + 802b694: 1009883a mov r4,r2 + 802b698: 803cae00 call 803cae0 + 802b69c: 1400032e bgeu r2,r16,802b6ac + { + dtrap(); /* should never happen */ + 802b6a0: 8028cd40 call 8028cd4 + return EMSGSIZE; /* try to recover */ + 802b6a4: 00801e84 movi r2,122 + 802b6a8: 0000d706 br 802ba08 + } + /* get a packet buffer for send */ + pkt = ip_raw_alloc(m->m_len, so->so_options & SO_HDRINCL); + 802b6ac: e0bff317 ldw r2,-52(fp) + 802b6b0: 10800217 ldw r2,8(r2) + 802b6b4: 1007883a mov r3,r2 + 802b6b8: e0bff417 ldw r2,-48(fp) + 802b6bc: 10800417 ldw r2,16(r2) + 802b6c0: 1088000c andi r2,r2,8192 + 802b6c4: 100b883a mov r5,r2 + 802b6c8: 1809883a mov r4,r3 + 802b6cc: 803c9e40 call 803c9e4 + 802b6d0: e0bff615 stw r2,-40(fp) + if (!pkt) + 802b6d4: e0bff617 ldw r2,-40(fp) + 802b6d8: 1000041e bne r2,zero,802b6ec + { + m_free(m); + 802b6dc: e13ff317 ldw r4,-52(fp) + 802b6e0: 8029bf80 call 8029bf8 + return ENOBUFS; /* report buffer shortages */ + 802b6e4: 00801a44 movi r2,105 + 802b6e8: 0000c706 br 802ba08 + } + MEMCPY(pkt->nb_prot, m->m_data, m->m_len); + 802b6ec: e0bff617 ldw r2,-40(fp) + 802b6f0: 10c00317 ldw r3,12(r2) + 802b6f4: e0bff317 ldw r2,-52(fp) + 802b6f8: 11000317 ldw r4,12(r2) + 802b6fc: e0bff317 ldw r2,-52(fp) + 802b700: 10800217 ldw r2,8(r2) + 802b704: 100d883a mov r6,r2 + 802b708: 200b883a mov r5,r4 + 802b70c: 1809883a mov r4,r3 + 802b710: 80086b80 call 80086b8 + pkt->nb_plen = m->m_len; + 802b714: e0bff317 ldw r2,-52(fp) + 802b718: 10c00217 ldw r3,8(r2) + 802b71c: e0bff617 ldw r2,-40(fp) + 802b720: 10c00415 stw r3,16(r2) + /* finished with mbuf, free it now */ + m_free(m); + 802b724: e13ff317 ldw r4,-52(fp) + 802b728: 8029bf80 call 8029bf8 + pkt->fhost = fhost; + 802b72c: e0bff617 ldw r2,-40(fp) + 802b730: e0fffd17 ldw r3,-12(fp) + 802b734: 10c00715 stw r3,28(r2) + * is up; if (after all that) we don't have an interface then we + * fail with error EADDRNOTAVAIL; and finally, if we're built + * for a single-homed configuration where there's only one + * interface, we might as well use it, so we do. + */ + if (fhost == 0xffffffff) + 802b738: e0bffd17 ldw r2,-12(fp) + 802b73c: 10bfffd8 cmpnei r2,r2,-1 + 802b740: 1000471e bne r2,zero,802b860 + { +#ifdef MULTI_HOMED + if (ep->ipr_laddr != 0L) + 802b744: e0bff817 ldw r2,-32(fp) + 802b748: 10800117 ldw r2,4(r2) + 802b74c: 10000f26 beq r2,zero,802b78c + { + for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next) + 802b750: 008201b4 movhi r2,2054 + 802b754: 10b6a617 ldw r2,-9576(r2) + 802b758: e0bffb15 stw r2,-20(fp) + 802b75c: 00000806 br 802b780 + if (ifp->n_ipaddr == ep->ipr_laddr) + 802b760: e0bffb17 ldw r2,-20(fp) + 802b764: 10c00a17 ldw r3,40(r2) + 802b768: e0bff817 ldw r2,-32(fp) + 802b76c: 10800117 ldw r2,4(r2) + 802b770: 18801c26 beq r3,r2,802b7e4 + for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next) + 802b774: e0bffb17 ldw r2,-20(fp) + 802b778: 10800017 ldw r2,0(r2) + 802b77c: e0bffb15 stw r2,-20(fp) + 802b780: e0bffb17 ldw r2,-20(fp) + 802b784: 103ff61e bne r2,zero,802b760 + 802b788: 00001906 br 802b7f0 + break; + } + else { + for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next) + 802b78c: 008201b4 movhi r2,2054 + 802b790: 10b6a617 ldw r2,-9576(r2) + 802b794: e0bffb15 stw r2,-20(fp) + 802b798: 00000f06 br 802b7d8 + if ((ifp->n_flags & NF_BCAST) && + 802b79c: e0bffb17 ldw r2,-20(fp) + 802b7a0: 10802a17 ldw r2,168(r2) + 802b7a4: 1080004c andi r2,r2,1 + 802b7a8: 10000826 beq r2,zero,802b7cc + (ifp->n_mib) && (ifp->n_mib->ifAdminStatus == NI_UP)) + 802b7ac: e0bffb17 ldw r2,-20(fp) + 802b7b0: 10802717 ldw r2,156(r2) + if ((ifp->n_flags & NF_BCAST) && + 802b7b4: 10000526 beq r2,zero,802b7cc + (ifp->n_mib) && (ifp->n_mib->ifAdminStatus == NI_UP)) + 802b7b8: e0bffb17 ldw r2,-20(fp) + 802b7bc: 10802717 ldw r2,156(r2) + 802b7c0: 10800617 ldw r2,24(r2) + 802b7c4: 10800058 cmpnei r2,r2,1 + 802b7c8: 10000826 beq r2,zero,802b7ec + for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next) + 802b7cc: e0bffb17 ldw r2,-20(fp) + 802b7d0: 10800017 ldw r2,0(r2) + 802b7d4: e0bffb15 stw r2,-20(fp) + 802b7d8: e0bffb17 ldw r2,-20(fp) + 802b7dc: 103fef1e bne r2,zero,802b79c + 802b7e0: 00000306 br 802b7f0 + break; + 802b7e4: 0001883a nop + 802b7e8: 00000106 br 802b7f0 + break; + 802b7ec: 0001883a nop + } + if (ifp == NULL) + 802b7f0: e0bffb17 ldw r2,-20(fp) + 802b7f4: 1000171e bne r2,zero,802b854 + { + for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next) + 802b7f8: 008201b4 movhi r2,2054 + 802b7fc: 10b6a617 ldw r2,-9576(r2) + 802b800: e0bffb15 stw r2,-20(fp) + 802b804: 00000b06 br 802b834 + if ((ifp->n_mib) && (ifp->n_mib->ifAdminStatus == NI_UP)) + 802b808: e0bffb17 ldw r2,-20(fp) + 802b80c: 10802717 ldw r2,156(r2) + 802b810: 10000526 beq r2,zero,802b828 + 802b814: e0bffb17 ldw r2,-20(fp) + 802b818: 10802717 ldw r2,156(r2) + 802b81c: 10800617 ldw r2,24(r2) + 802b820: 10800058 cmpnei r2,r2,1 + 802b824: 10000626 beq r2,zero,802b840 + for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next) + 802b828: e0bffb17 ldw r2,-20(fp) + 802b82c: 10800017 ldw r2,0(r2) + 802b830: e0bffb15 stw r2,-20(fp) + 802b834: e0bffb17 ldw r2,-20(fp) + 802b838: 103ff31e bne r2,zero,802b808 + 802b83c: 00000106 br 802b844 + break; + 802b840: 0001883a nop + if (ifp == NULL) + 802b844: e0bffb17 ldw r2,-20(fp) + 802b848: 1000021e bne r2,zero,802b854 + return(EADDRNOTAVAIL); + 802b84c: 00801f44 movi r2,125 + 802b850: 00006d06 br 802ba08 + } + pkt->net = ifp; + 802b854: e0bff617 ldw r2,-40(fp) + 802b858: e0fffb17 ldw r3,-20(fp) + 802b85c: 10c00615 stw r3,24(r2) +#ifdef IP_MULTICAST + + /* If the socket has an IP moptions structure for multicast options, + * place a pointer to this structure in the PACKET structure. + */ + if (so->inp_moptions) + 802b860: e0bff417 ldw r2,-48(fp) + 802b864: 10800317 ldw r2,12(r2) + 802b868: 10000426 beq r2,zero,802b87c + pkt->imo = so->inp_moptions; + 802b86c: e0bff417 ldw r2,-48(fp) + 802b870: 10c00317 ldw r3,12(r2) + 802b874: e0bff617 ldw r2,-40(fp) + 802b878: 10c00b15 stw r3,44(r2) + +#endif /* IP_MULTICAST */ + + if (so->so_options & SO_HDRINCL) + 802b87c: e0bff417 ldw r2,-48(fp) + 802b880: 10800417 ldw r2,16(r2) + 802b884: 1088000c andi r2,r2,8192 + 802b888: 10000826 beq r2,zero,802b8ac + { + UNLOCK_NET_RESOURCE(NET_RESID); + 802b88c: 0009883a mov r4,zero + 802b890: 8028ff40 call 8028ff4 + e = ip_raw_write(pkt); + 802b894: e13ff617 ldw r4,-40(fp) + 802b898: 803af6c0 call 803af6c + 802b89c: e0bffe15 stw r2,-8(fp) + LOCK_NET_RESOURCE(NET_RESID); + 802b8a0: 0009883a mov r4,zero + 802b8a4: 8028f380 call 8028f38 + 802b8a8: 00002806 br 802b94c + } + else + { + pip = (struct ip *)(pkt->nb_prot - IPHSIZ); + 802b8ac: e0bff617 ldw r2,-40(fp) + 802b8b0: 10800317 ldw r2,12(r2) + 802b8b4: 10bffb04 addi r2,r2,-20 + 802b8b8: e0bff515 stw r2,-44(fp) + if (ep->ipr_laddr) + 802b8bc: e0bff817 ldw r2,-32(fp) + 802b8c0: 10800117 ldw r2,4(r2) + 802b8c4: 10000526 beq r2,zero,802b8dc + pip->ip_src = ep->ipr_laddr; + 802b8c8: e0bff817 ldw r2,-32(fp) + 802b8cc: 10c00117 ldw r3,4(r2) + 802b8d0: e0bff517 ldw r2,-44(fp) + 802b8d4: 10c00315 stw r3,12(r2) + 802b8d8: 00000e06 br 802b914 + else + { + if (fhost == 0xffffffff) + 802b8dc: e0bffd17 ldw r2,-12(fp) + 802b8e0: 10bfffd8 cmpnei r2,r2,-1 + 802b8e4: 1000061e bne r2,zero,802b900 + pip->ip_src = pkt->net->n_ipaddr; + 802b8e8: e0bff617 ldw r2,-40(fp) + 802b8ec: 10800617 ldw r2,24(r2) + 802b8f0: 10c00a17 ldw r3,40(r2) + 802b8f4: e0bff517 ldw r2,-44(fp) + 802b8f8: 10c00315 stw r3,12(r2) + 802b8fc: 00000506 br 802b914 + else + pip->ip_src = ip_mymach(fhost); + 802b900: e13ffd17 ldw r4,-12(fp) + 802b904: 803b0280 call 803b028 + 802b908: 1007883a mov r3,r2 + 802b90c: e0bff517 ldw r2,-44(fp) + 802b910: 10c00315 stw r3,12(r2) + } + pip->ip_dest = fhost; + 802b914: e0bff517 ldw r2,-44(fp) + 802b918: e0fffd17 ldw r3,-12(fp) + 802b91c: 10c00415 stw r3,16(r2) + UNLOCK_NET_RESOURCE(NET_RESID); + 802b920: 0009883a mov r4,zero + 802b924: 8028ff40 call 8028ff4 + e = ip_write(ep->ipr_prot, pkt); + 802b928: e0bff817 ldw r2,-32(fp) + 802b92c: 10800503 ldbu r2,20(r2) + 802b930: 10803fcc andi r2,r2,255 + 802b934: e17ff617 ldw r5,-40(fp) + 802b938: 1009883a mov r4,r2 + 802b93c: 803a9e80 call 803a9e8 + 802b940: e0bffe15 stw r2,-8(fp) + LOCK_NET_RESOURCE(NET_RESID); + 802b944: 0009883a mov r4,zero + 802b948: 8028f380 call 8028f38 + } + if (e < 0) + 802b94c: e0bffe17 ldw r2,-8(fp) + 802b950: 1000020e bge r2,zero,802b95c + return(e); + 802b954: e0bffe17 ldw r2,-8(fp) + 802b958: 00002b06 br 802ba08 + return 0; + 802b95c: 0005883a mov r2,zero + 802b960: 00002906 br 802ba08 + case PRU_SOCKADDR: + /* fall through to share PRU_PEERADDR prefix */ + case PRU_PEERADDR: + if (nam == NULL) + 802b964: e0bff217 ldw r2,-56(fp) + 802b968: 1000021e bne r2,zero,802b974 + return(EINVAL); + 802b96c: 00800584 movi r2,22 + 802b970: 00002506 br 802ba08 + sin = mtod(nam, struct sockaddr_in *); + 802b974: e0bff217 ldw r2,-56(fp) + 802b978: 10800317 ldw r2,12(r2) + 802b97c: e0bff715 stw r2,-36(fp) + if (sin == NULL) + 802b980: e0bff717 ldw r2,-36(fp) + 802b984: 1000021e bne r2,zero,802b990 + return(EINVAL); + 802b988: 00800584 movi r2,22 + 802b98c: 00001e06 br 802ba08 + ep = rawip_lookup(so); + 802b990: e13ff417 ldw r4,-48(fp) + 802b994: 802b0c80 call 802b0c8 + 802b998: e0bff815 stw r2,-32(fp) + if (!ep) + 802b99c: e0bff817 ldw r2,-32(fp) + 802b9a0: 1000021e bne r2,zero,802b9ac + return(EINVAL); + 802b9a4: 00800584 movi r2,22 + 802b9a8: 00001706 br 802ba08 + sin->sin_port = 0; + 802b9ac: e0bff717 ldw r2,-36(fp) + 802b9b0: 1000008d sth zero,2(r2) + nam->m_len = sizeof(*sin); + 802b9b4: e0bff217 ldw r2,-56(fp) + 802b9b8: 00c00404 movi r3,16 + 802b9bc: 10c00215 stw r3,8(r2) + if (req == PRU_SOCKADDR) + 802b9c0: e0bffa17 ldw r2,-24(fp) + 802b9c4: 108003d8 cmpnei r2,r2,15 + 802b9c8: 1000051e bne r2,zero,802b9e0 + { + sin->sin_addr.s_addr = ep->ipr_laddr; + 802b9cc: e0bff817 ldw r2,-32(fp) + 802b9d0: 10c00117 ldw r3,4(r2) + 802b9d4: e0bff717 ldw r2,-36(fp) + 802b9d8: 10c00115 stw r3,4(r2) + 802b9dc: 00000406 br 802b9f0 + } + else /* PRU_PEERADDR */ + { + sin->sin_addr.s_addr = ep->ipr_faddr; + 802b9e0: e0bff817 ldw r2,-32(fp) + 802b9e4: 10c00217 ldw r3,8(r2) + 802b9e8: e0bff717 ldw r2,-36(fp) + 802b9ec: 10c00115 stw r3,4(r2) + } + return 0; + 802b9f0: 0005883a mov r2,zero + 802b9f4: 00000406 br 802ba08 + case PRU_DISCONNECT: + case PRU_RCVD: + dtrap(); + 802b9f8: 8028cd40 call 8028cd4 + return 0; + 802b9fc: 0005883a mov r2,zero + 802ba00: 00000106 br 802ba08 + case PRU_LISTEN: /* don't support these for raw IP */ + case PRU_ACCEPT: + default: + return EOPNOTSUPP; + 802ba04: 008017c4 movi r2,95 + } +} + 802ba08: e6ffff04 addi sp,fp,-4 + 802ba0c: dfc00217 ldw ra,8(sp) + 802ba10: df000117 ldw fp,4(sp) + 802ba14: dc000017 ldw r16,0(sp) + 802ba18: dec00304 addi sp,sp,12 + 802ba1c: f800283a ret + +0802ba20 : + */ + +#ifdef NPDEBUG +void +DOMAIN_CHECK(struct socket * so, int size) +{ + 802ba20: defffc04 addi sp,sp,-16 + 802ba24: dfc00315 stw ra,12(sp) + 802ba28: df000215 stw fp,8(sp) + 802ba2c: df000204 addi fp,sp,8 + 802ba30: e13fff15 stw r4,-4(fp) + 802ba34: e17ffe15 stw r5,-8(fp) +#ifdef IP_V4 + if((so->so_domain == AF_INET) && + 802ba38: e0bfff17 ldw r2,-4(fp) + 802ba3c: 10800517 ldw r2,20(r2) + 802ba40: 10800098 cmpnei r2,r2,2 + 802ba44: 1000041e bne r2,zero,802ba58 + (size < sizeof(struct sockaddr_in))) + 802ba48: e0bffe17 ldw r2,-8(fp) + if((so->so_domain == AF_INET) && + 802ba4c: 10800428 cmpgeui r2,r2,16 + 802ba50: 1000011e bne r2,zero,802ba58 + { + dtrap(); /* programmer passed wrong structure */ + 802ba54: 8028cd40 call 8028cd4 + (size != sizeof(struct sockaddr_in6))) + { + dtrap(); /* programmer passed wrong structure */ + } +#endif /* IP_V6 */ +} + 802ba58: 0001883a nop + 802ba5c: e037883a mov sp,fp + 802ba60: dfc00117 ldw ra,4(sp) + 802ba64: df000017 ldw fp,0(sp) + 802ba68: dec00204 addi sp,sp,8 + 802ba6c: f800283a ret + +0802ba70 : + +long +t_socket(int family, + int type, + int proto) +{ + 802ba70: defffa04 addi sp,sp,-24 + 802ba74: dfc00515 stw ra,20(sp) + 802ba78: df000415 stw fp,16(sp) + 802ba7c: df000404 addi fp,sp,16 + 802ba80: e13ffe15 stw r4,-8(fp) + 802ba84: e17ffd15 stw r5,-12(fp) + 802ba88: e1bffc15 stw r6,-16(fp) + struct socket * so; + + INET_TRACE (INETM_SOCKET, ("SOCK:sock:family %d, typ %d, proto %d\n", + family, type, proto)); + LOCK_NET_RESOURCE(NET_RESID); + 802ba8c: 0009883a mov r4,zero + 802ba90: 8028f380 call 8028f38 + if ((so = socreate (family, type, proto)) == NULL) + 802ba94: e1bffc17 ldw r6,-16(fp) + 802ba98: e17ffd17 ldw r5,-12(fp) + 802ba9c: e13ffe17 ldw r4,-8(fp) + 802baa0: 802d0500 call 802d050 + 802baa4: e0bfff15 stw r2,-4(fp) + 802baa8: e0bfff17 ldw r2,-4(fp) + 802baac: 1000041e bne r2,zero,802bac0 + { /* can't really return error info since no socket.... */ + UNLOCK_NET_RESOURCE(NET_RESID); + 802bab0: 0009883a mov r4,zero + 802bab4: 8028ff40 call 8028ff4 + return SOCKET_ERROR; + 802bab8: 00bfffc4 movi r2,-1 + 802babc: 00000706 br 802badc + } + SOC_RANGE(so); + so->so_error = 0; + 802bac0: e0bfff17 ldw r2,-4(fp) + 802bac4: 10000615 stw zero,24(r2) + UNLOCK_NET_RESOURCE(NET_RESID); + 802bac8: 0009883a mov r4,zero + 802bacc: 8028ff40 call 8028ff4 + return SO2LONG(so); + 802bad0: e0bfff17 ldw r2,-4(fp) + 802bad4: 1004d0ba srli r2,r2,2 + 802bad8: 10800404 addi r2,r2,16 +} + 802badc: e037883a mov sp,fp + 802bae0: dfc00117 ldw ra,4(sp) + 802bae4: df000017 ldw fp,0(sp) + 802bae8: dec00204 addi sp,sp,8 + 802baec: f800283a ret + +0802baf0 : + +int +t_bind (long s, + struct sockaddr * addr, + int addrlen) +{ + 802baf0: defff204 addi sp,sp,-56 + 802baf4: dfc00d15 stw ra,52(sp) + 802baf8: df000c15 stw fp,48(sp) + 802bafc: df000c04 addi fp,sp,48 + 802bb00: e13ff615 stw r4,-40(fp) + 802bb04: e17ff515 stw r5,-44(fp) + 802bb08: e1bff415 stw r6,-48(fp) + struct sockaddr sa; + struct sockaddr * sap; + struct socket * so; + int err; + + so = LONG2SO(s); /* convert long to socket */ + 802bb0c: e0bff617 ldw r2,-40(fp) + 802bb10: 10bffc04 addi r2,r2,-16 + 802bb14: 100490ba slli r2,r2,2 + 802bb18: e0bffd15 stw r2,-12(fp) + SOC_CHECK(so); + 802bb1c: 008201b4 movhi r2,2054 + 802bb20: 10b87104 addi r2,r2,-7740 + 802bb24: e0bffe15 stw r2,-8(fp) + 802bb28: 00000606 br 802bb44 + 802bb2c: e0fffe17 ldw r3,-8(fp) + 802bb30: e0bffd17 ldw r2,-12(fp) + 802bb34: 18800626 beq r3,r2,802bb50 + 802bb38: e0bffe17 ldw r2,-8(fp) + 802bb3c: 10800017 ldw r2,0(r2) + 802bb40: e0bffe15 stw r2,-8(fp) + 802bb44: e0bffe17 ldw r2,-8(fp) + 802bb48: 103ff81e bne r2,zero,802bb2c + 802bb4c: 00000106 br 802bb54 + 802bb50: 0001883a nop + 802bb54: e0fffe17 ldw r3,-8(fp) + 802bb58: e0bffd17 ldw r2,-12(fp) + 802bb5c: 18800326 beq r3,r2,802bb6c + 802bb60: 8028cd40 call 8028cd4 + 802bb64: 00bfffc4 movi r2,-1 + 802bb68: 00003406 br 802bc3c + DOMAIN_CHECK(so, addrlen); + 802bb6c: e17ff417 ldw r5,-48(fp) + 802bb70: e13ffd17 ldw r4,-12(fp) + 802bb74: 802ba200 call 802ba20 + + so->so_error = 0; + 802bb78: e0bffd17 ldw r2,-12(fp) + 802bb7c: 10000615 stw zero,24(r2) + if (addr == (struct sockaddr *)NULL) + 802bb80: e0bff517 ldw r2,-44(fp) + 802bb84: 10000d1e bne r2,zero,802bbbc + { + MEMSET ((void *)&sa, 0, sizeof(sa)); + 802bb88: e0bff704 addi r2,fp,-36 + 802bb8c: 01800404 movi r6,16 + 802bb90: 000b883a mov r5,zero + 802bb94: 1009883a mov r4,r2 + 802bb98: 80088e40 call 80088e4 + addrlen = sizeof(sa); + 802bb9c: 00800404 movi r2,16 + 802bba0: e0bff415 stw r2,-48(fp) + sa.sa_family = so->so_domain; + 802bba4: e0bffd17 ldw r2,-12(fp) + 802bba8: 10800517 ldw r2,20(r2) + 802bbac: e0bff70d sth r2,-36(fp) + sap = &sa; + 802bbb0: e0bff704 addi r2,fp,-36 + 802bbb4: e0bfff15 stw r2,-4(fp) + 802bbb8: 00000206 br 802bbc4 + } else + sap = addr; + 802bbbc: e0bff517 ldw r2,-44(fp) + 802bbc0: e0bfff15 stw r2,-4(fp) + + if ((nam = sockargs (sap, addrlen, MT_SONAME)) == NULL) + 802bbc4: 01800244 movi r6,9 + 802bbc8: e17ff417 ldw r5,-48(fp) + 802bbcc: e13fff17 ldw r4,-4(fp) + 802bbd0: 802cf300 call 802cf30 + 802bbd4: e0bffc15 stw r2,-16(fp) + 802bbd8: e0bffc17 ldw r2,-16(fp) + 802bbdc: 1000051e bne r2,zero,802bbf4 + { + so->so_error = ENOMEM; + 802bbe0: e0bffd17 ldw r2,-12(fp) + 802bbe4: 00c00304 movi r3,12 + 802bbe8: 10c00615 stw r3,24(r2) + return SOCKET_ERROR; + 802bbec: 00bfffc4 movi r2,-1 + 802bbf0: 00001206 br 802bc3c + } + LOCK_NET_RESOURCE(NET_RESID); + 802bbf4: 0009883a mov r4,zero + 802bbf8: 8028f380 call 8028f38 + err = sobind (so, nam); + 802bbfc: e17ffc17 ldw r5,-16(fp) + 802bc00: e13ffd17 ldw r4,-12(fp) + 802bc04: 802d1f80 call 802d1f8 + 802bc08: e0bffb15 stw r2,-20(fp) + m_freem(nam); + 802bc0c: e13ffc17 ldw r4,-16(fp) + 802bc10: 8029cfc0 call 8029cfc + UNLOCK_NET_RESOURCE(NET_RESID); + 802bc14: 0009883a mov r4,zero + 802bc18: 8028ff40 call 8028ff4 + if (err) + 802bc1c: e0bffb17 ldw r2,-20(fp) + 802bc20: 10000526 beq r2,zero,802bc38 + { + so->so_error = err; + 802bc24: e0bffd17 ldw r2,-12(fp) + 802bc28: e0fffb17 ldw r3,-20(fp) + 802bc2c: 10c00615 stw r3,24(r2) + return SOCKET_ERROR; + 802bc30: 00bfffc4 movi r2,-1 + 802bc34: 00000106 br 802bc3c + } + return 0; + 802bc38: 0005883a mov r2,zero +} + 802bc3c: e037883a mov sp,fp + 802bc40: dfc00117 ldw ra,4(sp) + 802bc44: df000017 ldw fp,0(sp) + 802bc48: dec00204 addi sp,sp,8 + 802bc4c: f800283a ret + +0802bc50 : + */ + +int +t_listen(long s, + int backlog) +{ + 802bc50: defff904 addi sp,sp,-28 + 802bc54: dfc00615 stw ra,24(sp) + 802bc58: df000515 stw fp,20(sp) + 802bc5c: df000504 addi fp,sp,20 + 802bc60: e13ffc15 stw r4,-16(fp) + 802bc64: e17ffb15 stw r5,-20(fp) + struct socket * so; + int err; + + so = LONG2SO(s); /* convert long to socket */ + 802bc68: e0bffc17 ldw r2,-16(fp) + 802bc6c: 10bffc04 addi r2,r2,-16 + 802bc70: 100490ba slli r2,r2,2 + 802bc74: e0bffe15 stw r2,-8(fp) + SOC_CHECK(so); + 802bc78: 008201b4 movhi r2,2054 + 802bc7c: 10b87104 addi r2,r2,-7740 + 802bc80: e0bfff15 stw r2,-4(fp) + 802bc84: 00000606 br 802bca0 + 802bc88: e0ffff17 ldw r3,-4(fp) + 802bc8c: e0bffe17 ldw r2,-8(fp) + 802bc90: 18800626 beq r3,r2,802bcac + 802bc94: e0bfff17 ldw r2,-4(fp) + 802bc98: 10800017 ldw r2,0(r2) + 802bc9c: e0bfff15 stw r2,-4(fp) + 802bca0: e0bfff17 ldw r2,-4(fp) + 802bca4: 103ff81e bne r2,zero,802bc88 + 802bca8: 00000106 br 802bcb0 + 802bcac: 0001883a nop + 802bcb0: e0ffff17 ldw r3,-4(fp) + 802bcb4: e0bffe17 ldw r2,-8(fp) + 802bcb8: 18800326 beq r3,r2,802bcc8 + 802bcbc: 8028cd40 call 8028cd4 + 802bcc0: 00bfffc4 movi r2,-1 + 802bcc4: 00001206 br 802bd10 + so->so_error = 0; + 802bcc8: e0bffe17 ldw r2,-8(fp) + 802bccc: 10000615 stw zero,24(r2) + INET_TRACE (INETM_SOCKET, ("SOCK:listen:qlen %d\n", backlog)); + + LOCK_NET_RESOURCE(NET_RESID); + 802bcd0: 0009883a mov r4,zero + 802bcd4: 8028f380 call 8028f38 + err = solisten (so, backlog); + 802bcd8: e17ffb17 ldw r5,-20(fp) + 802bcdc: e13ffe17 ldw r4,-8(fp) + 802bce0: 802d2540 call 802d254 + 802bce4: e0bffd15 stw r2,-12(fp) + UNLOCK_NET_RESOURCE(NET_RESID); + 802bce8: 0009883a mov r4,zero + 802bcec: 8028ff40 call 8028ff4 + + if (err != 0) + 802bcf0: e0bffd17 ldw r2,-12(fp) + 802bcf4: 10000526 beq r2,zero,802bd0c + { + so->so_error = err; + 802bcf8: e0bffe17 ldw r2,-8(fp) + 802bcfc: e0fffd17 ldw r3,-12(fp) + 802bd00: 10c00615 stw r3,24(r2) + return SOCKET_ERROR; + 802bd04: 00bfffc4 movi r2,-1 + 802bd08: 00000106 br 802bd10 + } + return 0; + 802bd0c: 0005883a mov r2,zero +} + 802bd10: e037883a mov sp,fp + 802bd14: dfc00117 ldw ra,4(sp) + 802bd18: df000017 ldw fp,0(sp) + 802bd1c: dec00204 addi sp,sp,8 + 802bd20: f800283a ret + +0802bd24 : + +long +t_accept(long s, + struct sockaddr * addr, + int * addrlen) +{ + 802bd24: defff704 addi sp,sp,-36 + 802bd28: dfc00815 stw ra,32(sp) + 802bd2c: df000715 stw fp,28(sp) + 802bd30: df000704 addi fp,sp,28 + 802bd34: e13ffb15 stw r4,-20(fp) + 802bd38: e17ffa15 stw r5,-24(fp) + 802bd3c: e1bff915 stw r6,-28(fp) + char logbuf[10]; +#endif + struct socket * so; + struct mbuf * nam; + + so = LONG2SO(s); + 802bd40: e0bffb17 ldw r2,-20(fp) + 802bd44: 10bffc04 addi r2,r2,-16 + 802bd48: 100490ba slli r2,r2,2 + 802bd4c: e0bffe15 stw r2,-8(fp) + SOC_CHECK(so); + 802bd50: 008201b4 movhi r2,2054 + 802bd54: 10b87104 addi r2,r2,-7740 + 802bd58: e0bfff15 stw r2,-4(fp) + 802bd5c: 00000606 br 802bd78 + 802bd60: e0ffff17 ldw r3,-4(fp) + 802bd64: e0bffe17 ldw r2,-8(fp) + 802bd68: 18800626 beq r3,r2,802bd84 + 802bd6c: e0bfff17 ldw r2,-4(fp) + 802bd70: 10800017 ldw r2,0(r2) + 802bd74: e0bfff15 stw r2,-4(fp) + 802bd78: e0bfff17 ldw r2,-4(fp) + 802bd7c: 103ff81e bne r2,zero,802bd60 + 802bd80: 00000106 br 802bd88 + 802bd84: 0001883a nop + 802bd88: e0ffff17 ldw r3,-4(fp) + 802bd8c: e0bffe17 ldw r2,-8(fp) + 802bd90: 18800326 beq r3,r2,802bda0 + 802bd94: 8028cd40 call 8028cd4 + 802bd98: 00bfffc4 movi r2,-1 + 802bd9c: 00007006 br 802bf60 + DOMAIN_CHECK(so, *addrlen); + 802bda0: e0bff917 ldw r2,-28(fp) + 802bda4: 10800017 ldw r2,0(r2) + 802bda8: 100b883a mov r5,r2 + 802bdac: e13ffe17 ldw r4,-8(fp) + 802bdb0: 802ba200 call 802ba20 + + so->so_error = 0; + 802bdb4: e0bffe17 ldw r2,-8(fp) + 802bdb8: 10000615 stw zero,24(r2) + INET_TRACE (INETM_SOCKET, + ("INET:accept:so %x so_qlen %d so_state %x\n", so, so->so_qlen, so->so_state)); + if ((so->so_options & SO_ACCEPTCONN) == 0) + 802bdbc: e0bffe17 ldw r2,-8(fp) + 802bdc0: 10800417 ldw r2,16(r2) + 802bdc4: 1080008c andi r2,r2,2 + 802bdc8: 1000051e bne r2,zero,802bde0 + { + so->so_error = EINVAL; + 802bdcc: e0bffe17 ldw r2,-8(fp) + 802bdd0: 00c00584 movi r3,22 + 802bdd4: 10c00615 stw r3,24(r2) +#ifdef SOCKDEBUG + sprintf(logbuf, "t_accept[%d]: %d", __LINE__, so->so_error); + glog_with_type(LOG_TYPE_DEBUG, logbuf, 1); +#endif + return SOCKET_ERROR; + 802bdd8: 00bfffc4 movi r2,-1 + 802bddc: 00006006 br 802bf60 + } + if ((so->so_state & SS_NBIO) && so->so_qlen == 0) + 802bde0: e0bffe17 ldw r2,-8(fp) + 802bde4: 1080088b ldhu r2,34(r2) + 802bde8: 10bfffcc andi r2,r2,65535 + 802bdec: 1080400c andi r2,r2,256 + 802bdf0: 10000b26 beq r2,zero,802be20 + 802bdf4: e0bffe17 ldw r2,-8(fp) + 802bdf8: 10801e43 ldbu r2,121(r2) + 802bdfc: 10803fcc andi r2,r2,255 + 802be00: 1080201c xori r2,r2,128 + 802be04: 10bfe004 addi r2,r2,-128 + 802be08: 1000051e bne r2,zero,802be20 + { + so->so_error = EWOULDBLOCK; + 802be0c: e0bffe17 ldw r2,-8(fp) + 802be10: 00c002c4 movi r3,11 + 802be14: 10c00615 stw r3,24(r2) +#ifdef SOCKDEBUG + sprintf(logbuf, "t_accept[%d]: %d", __LINE__, so->so_error); + glog_with_type(LOG_TYPE_DEBUG, logbuf, 1); +#endif + return SOCKET_ERROR; + 802be18: 00bfffc4 movi r2,-1 + 802be1c: 00005006 br 802bf60 + } + LOCK_NET_RESOURCE(NET_RESID); + 802be20: 0009883a mov r4,zero + 802be24: 8028f380 call 8028f38 + while (so->so_qlen == 0 && so->so_error == 0) + 802be28: 00001006 br 802be6c + { + if (so->so_state & SS_CANTRCVMORE) + 802be2c: e0bffe17 ldw r2,-8(fp) + 802be30: 1080088b ldhu r2,34(r2) + 802be34: 10bfffcc andi r2,r2,65535 + 802be38: 1080080c andi r2,r2,32 + 802be3c: 10000726 beq r2,zero,802be5c + { + so->so_error = ECONNABORTED; + 802be40: e0bffe17 ldw r2,-8(fp) + 802be44: 00c01c44 movi r3,113 + 802be48: 10c00615 stw r3,24(r2) + UNLOCK_NET_RESOURCE(NET_RESID); + 802be4c: 0009883a mov r4,zero + 802be50: 8028ff40 call 8028ff4 + return SOCKET_ERROR; + 802be54: 00bfffc4 movi r2,-1 + 802be58: 00004106 br 802bf60 + } + tcp_sleep ((char *)&so->so_timeo); + 802be5c: e0bffe17 ldw r2,-8(fp) + 802be60: 10800904 addi r2,r2,36 + 802be64: 1009883a mov r4,r2 + 802be68: 8027a540 call 8027a54 + while (so->so_qlen == 0 && so->so_error == 0) + 802be6c: e0bffe17 ldw r2,-8(fp) + 802be70: 10801e43 ldbu r2,121(r2) + 802be74: 10803fcc andi r2,r2,255 + 802be78: 1080201c xori r2,r2,128 + 802be7c: 10bfe004 addi r2,r2,-128 + 802be80: 1000031e bne r2,zero,802be90 + 802be84: e0bffe17 ldw r2,-8(fp) + 802be88: 10800617 ldw r2,24(r2) + 802be8c: 103fe726 beq r2,zero,802be2c + } + if (so->so_error) + 802be90: e0bffe17 ldw r2,-8(fp) + 802be94: 10800617 ldw r2,24(r2) + 802be98: 10000426 beq r2,zero,802beac + { +#ifdef SOCKDEBUG + sprintf(logbuf, "t_accept[%d]: %d", __LINE__, so->so_error); + glog_with_type(LOG_TYPE_DEBUG, logbuf, 1); +#endif + UNLOCK_NET_RESOURCE(NET_RESID); + 802be9c: 0009883a mov r4,zero + 802bea0: 8028ff40 call 8028ff4 + return SOCKET_ERROR; + 802bea4: 00bfffc4 movi r2,-1 + 802bea8: 00002d06 br 802bf60 + } + nam = m_getwithdata (MT_SONAME, sizeof (struct sockaddr)); + 802beac: 01400404 movi r5,16 + 802beb0: 01000244 movi r4,9 + 802beb4: 8029a700 call 8029a70 + 802beb8: e0bffd15 stw r2,-12(fp) + if (nam == NULL) + 802bebc: e0bffd17 ldw r2,-12(fp) + 802bec0: 1000071e bne r2,zero,802bee0 + { + UNLOCK_NET_RESOURCE(NET_RESID); + 802bec4: 0009883a mov r4,zero + 802bec8: 8028ff40 call 8028ff4 + so->so_error = ENOMEM; + 802becc: e0bffe17 ldw r2,-8(fp) + 802bed0: 00c00304 movi r3,12 + 802bed4: 10c00615 stw r3,24(r2) +#ifdef SOCKDEBUG + sprintf(logbuf, "t_accept[%d]: %d", __LINE__, so->so_error); + glog_with_type(LOG_TYPE_DEBUG, logbuf, 1); +#endif + return SOCKET_ERROR; + 802bed8: 00bfffc4 movi r2,-1 + 802bedc: 00002006 br 802bf60 + } + { + struct socket *aso = so->so_q; + 802bee0: e0bffe17 ldw r2,-8(fp) + 802bee4: 10801d17 ldw r2,116(r2) + 802bee8: e0bffc15 stw r2,-16(fp) + if (soqremque (aso, 1) == 0) + 802beec: 01400044 movi r5,1 + 802bef0: e13ffc17 ldw r4,-16(fp) + 802bef4: 802f6ec0 call 802f6ec + 802bef8: 1000031e bne r2,zero,802bf08 + panic("accept"); + 802befc: 01020174 movhi r4,2053 + 802bf00: 212a7404 addi r4,r4,-22064 + 802bf04: 80271780 call 8027178 + so = aso; + 802bf08: e0bffc17 ldw r2,-16(fp) + 802bf0c: e0bffe15 stw r2,-8(fp) + } + (void)soaccept (so, nam); + 802bf10: e17ffd17 ldw r5,-12(fp) + 802bf14: e13ffe17 ldw r4,-8(fp) + 802bf18: 802d74c0 call 802d74c + INET_TRACE (INETM_SOCKET, ("INET:accept:done so %lx port %d addr %lx\n", + so, sin->sin_port, sin->sin_addr.s_addr)); + } +#endif /* TRACE_INET */ + /* return the addressing info in the passed structure */ + if (addr != NULL) + 802bf1c: e0bffa17 ldw r2,-24(fp) + 802bf20: 10000826 beq r2,zero,802bf44 + MEMCPY(addr, nam->m_data, *addrlen); + 802bf24: e0bffd17 ldw r2,-12(fp) + 802bf28: 10c00317 ldw r3,12(r2) + 802bf2c: e0bff917 ldw r2,-28(fp) + 802bf30: 10800017 ldw r2,0(r2) + 802bf34: 100d883a mov r6,r2 + 802bf38: 180b883a mov r5,r3 + 802bf3c: e13ffa17 ldw r4,-24(fp) + 802bf40: 80086b80 call 80086b8 + m_freem (nam); + 802bf44: e13ffd17 ldw r4,-12(fp) + 802bf48: 8029cfc0 call 8029cfc + UNLOCK_NET_RESOURCE(NET_RESID); + 802bf4c: 0009883a mov r4,zero + 802bf50: 8028ff40 call 8028ff4 + SOC_RANGE(so); + return SO2LONG(so); + 802bf54: e0bffe17 ldw r2,-8(fp) + 802bf58: 1004d0ba srli r2,r2,2 + 802bf5c: 10800404 addi r2,r2,16 +} + 802bf60: e037883a mov sp,fp + 802bf64: dfc00117 ldw ra,4(sp) + 802bf68: df000017 ldw fp,0(sp) + 802bf6c: dec00204 addi sp,sp,8 + 802bf70: f800283a ret + +0802bf74 : + +int +t_connect(long s, + struct sockaddr * addr, + int addrlen) +{ + 802bf74: defff804 addi sp,sp,-32 + 802bf78: dfc00715 stw ra,28(sp) + 802bf7c: df000615 stw fp,24(sp) + 802bf80: df000604 addi fp,sp,24 + 802bf84: e13ffc15 stw r4,-16(fp) + 802bf88: e17ffb15 stw r5,-20(fp) + 802bf8c: e1bffa15 stw r6,-24(fp) + struct socket * so; + struct mbuf * nam; + + so = LONG2SO(s); + 802bf90: e0bffc17 ldw r2,-16(fp) + 802bf94: 10bffc04 addi r2,r2,-16 + 802bf98: 100490ba slli r2,r2,2 + 802bf9c: e0bffe15 stw r2,-8(fp) + SOC_CHECK(so); + 802bfa0: 008201b4 movhi r2,2054 + 802bfa4: 10b87104 addi r2,r2,-7740 + 802bfa8: e0bfff15 stw r2,-4(fp) + 802bfac: 00000606 br 802bfc8 + 802bfb0: e0ffff17 ldw r3,-4(fp) + 802bfb4: e0bffe17 ldw r2,-8(fp) + 802bfb8: 18800626 beq r3,r2,802bfd4 + 802bfbc: e0bfff17 ldw r2,-4(fp) + 802bfc0: 10800017 ldw r2,0(r2) + 802bfc4: e0bfff15 stw r2,-4(fp) + 802bfc8: e0bfff17 ldw r2,-4(fp) + 802bfcc: 103ff81e bne r2,zero,802bfb0 + 802bfd0: 00000106 br 802bfd8 + 802bfd4: 0001883a nop + 802bfd8: e0ffff17 ldw r3,-4(fp) + 802bfdc: e0bffe17 ldw r2,-8(fp) + 802bfe0: 18800326 beq r3,r2,802bff0 + 802bfe4: 8028cd40 call 8028cd4 + 802bfe8: 00bfffc4 movi r2,-1 + 802bfec: 00007806 br 802c1d0 + DOMAIN_CHECK(so, addrlen); + 802bff0: e17ffa17 ldw r5,-24(fp) + 802bff4: e13ffe17 ldw r4,-8(fp) + 802bff8: 802ba200 call 802ba20 + +#ifdef NB_CONNECT + /* need to test non blocking connect bits in case this is a + poll of a previous request */ + if (so->so_state & SS_NBIO) + 802bffc: e0bffe17 ldw r2,-8(fp) + 802c000: 1080088b ldhu r2,34(r2) + 802c004: 10bfffcc andi r2,r2,65535 + 802c008: 1080400c andi r2,r2,256 + 802c00c: 10002426 beq r2,zero,802c0a0 + { + if (so->so_state & SS_ISCONNECTING) /* still trying */ + 802c010: e0bffe17 ldw r2,-8(fp) + 802c014: 1080088b ldhu r2,34(r2) + 802c018: 10bfffcc andi r2,r2,65535 + 802c01c: 1080010c andi r2,r2,4 + 802c020: 10000526 beq r2,zero,802c038 + { + so->so_error = EINPROGRESS; + 802c024: e0bffe17 ldw r2,-8(fp) + 802c028: 00c01dc4 movi r3,119 + 802c02c: 10c00615 stw r3,24(r2) + return SOCKET_ERROR; + 802c030: 00bfffc4 movi r2,-1 + 802c034: 00006606 br 802c1d0 + } + if (so->so_state & SS_ISCONNECTED) /* connected OK */ + 802c038: e0bffe17 ldw r2,-8(fp) + 802c03c: 1080088b ldhu r2,34(r2) + 802c040: 10bfffcc andi r2,r2,65535 + 802c044: 1080008c andi r2,r2,2 + 802c048: 10000426 beq r2,zero,802c05c + { + so->so_error = 0; + 802c04c: e0bffe17 ldw r2,-8(fp) + 802c050: 10000615 stw zero,24(r2) + return 0; + 802c054: 0005883a mov r2,zero + 802c058: 00005d06 br 802c1d0 + } + if (so->so_state & SS_WASCONNECTING) + 802c05c: e0bffe17 ldw r2,-8(fp) + 802c060: 1080088b ldhu r2,34(r2) + 802c064: 10bfffcc andi r2,r2,65535 + 802c068: 1088000c andi r2,r2,8192 + 802c06c: 10000c26 beq r2,zero,802c0a0 + { + so->so_state &= ~SS_WASCONNECTING; + 802c070: e0bffe17 ldw r2,-8(fp) + 802c074: 10c0088b ldhu r3,34(r2) + 802c078: 00b7ffc4 movi r2,-8193 + 802c07c: 1884703a and r2,r3,r2 + 802c080: 1007883a mov r3,r2 + 802c084: e0bffe17 ldw r2,-8(fp) + 802c088: 10c0088d sth r3,34(r2) + if (so->so_error) /* connect error - maybe timeout */ + 802c08c: e0bffe17 ldw r2,-8(fp) + 802c090: 10800617 ldw r2,24(r2) + 802c094: 10000226 beq r2,zero,802c0a0 + return SOCKET_ERROR; + 802c098: 00bfffc4 movi r2,-1 + 802c09c: 00004c06 br 802c1d0 + } + } +#endif /* NB_CONNECT */ + + so->so_error = 0; + 802c0a0: e0bffe17 ldw r2,-8(fp) + 802c0a4: 10000615 stw zero,24(r2) + + if ((nam = sockargs (addr, addrlen, MT_SONAME)) + 802c0a8: 01800244 movi r6,9 + 802c0ac: e17ffa17 ldw r5,-24(fp) + 802c0b0: e13ffb17 ldw r4,-20(fp) + 802c0b4: 802cf300 call 802cf30 + 802c0b8: e0bffd15 stw r2,-12(fp) + 802c0bc: e0bffd17 ldw r2,-12(fp) + 802c0c0: 1000051e bne r2,zero,802c0d8 + == NULL) + { + so->so_error = ENOMEM; + 802c0c4: e0bffe17 ldw r2,-8(fp) + 802c0c8: 00c00304 movi r3,12 + 802c0cc: 10c00615 stw r3,24(r2) + return SOCKET_ERROR; + 802c0d0: 00bfffc4 movi r2,-1 + 802c0d4: 00003e06 br 802c1d0 + INET_TRACE (INETM_SOCKET, ("INET: connect, port %d addr %lx\n", + sin->sin_port, sin->sin_addr.s_addr)); + } +#endif /* TRACE_DEBUG */ + + LOCK_NET_RESOURCE(NET_RESID); + 802c0d8: 0009883a mov r4,zero + 802c0dc: 8028f380 call 8028f38 + if ((so->so_error = soconnect (so, nam)) != 0) + 802c0e0: e17ffd17 ldw r5,-12(fp) + 802c0e4: e13ffe17 ldw r4,-8(fp) + 802c0e8: 802d7e40 call 802d7e4 + 802c0ec: 1007883a mov r3,r2 + 802c0f0: e0bffe17 ldw r2,-8(fp) + 802c0f4: 10c00615 stw r3,24(r2) + 802c0f8: e0bffe17 ldw r2,-8(fp) + 802c0fc: 10800617 ldw r2,24(r2) + 802c100: 10001b1e bne r2,zero,802c170 + goto bad; + +#ifdef NB_CONNECT + /* need to test non blocking connect bits after soconnect() call */ + if ((so->so_state & SS_NBIO)&& (so->so_state & SS_ISCONNECTING)) + 802c104: e0bffe17 ldw r2,-8(fp) + 802c108: 1080088b ldhu r2,34(r2) + 802c10c: 10bfffcc andi r2,r2,65535 + 802c110: 1080400c andi r2,r2,256 + 802c114: 10000d26 beq r2,zero,802c14c + 802c118: e0bffe17 ldw r2,-8(fp) + 802c11c: 1080088b ldhu r2,34(r2) + 802c120: 10bfffcc andi r2,r2,65535 + 802c124: 1080010c andi r2,r2,4 + 802c128: 10000826 beq r2,zero,802c14c + { + so->so_error = EINPROGRESS; + 802c12c: e0bffe17 ldw r2,-8(fp) + 802c130: 00c01dc4 movi r3,119 + 802c134: 10c00615 stw r3,24(r2) + goto bad; + 802c138: 00001006 br 802c17c + INET_TRACE (INETM_SOCKET, ("INET: connect, so %x so_state %x so_error %d\n", + so, so->so_state, so->so_error)); + + while ((so->so_state & SS_ISCONNECTING) && so->so_error == 0) + { + tcp_sleep ((char *)&so->so_timeo); + 802c13c: e0bffe17 ldw r2,-8(fp) + 802c140: 10800904 addi r2,r2,36 + 802c144: 1009883a mov r4,r2 + 802c148: 8027a540 call 8027a54 + while ((so->so_state & SS_ISCONNECTING) && so->so_error == 0) + 802c14c: e0bffe17 ldw r2,-8(fp) + 802c150: 1080088b ldhu r2,34(r2) + 802c154: 10bfffcc andi r2,r2,65535 + 802c158: 1080010c andi r2,r2,4 + 802c15c: 10000626 beq r2,zero,802c178 + 802c160: e0bffe17 ldw r2,-8(fp) + 802c164: 10800617 ldw r2,24(r2) + 802c168: 103ff426 beq r2,zero,802c13c + } +bad: + 802c16c: 00000206 br 802c178 + goto bad; + 802c170: 0001883a nop + 802c174: 00000106 br 802c17c +bad: + 802c178: 0001883a nop + if (so->so_error != EINPROGRESS) + 802c17c: e0bffe17 ldw r2,-8(fp) + 802c180: 10800617 ldw r2,24(r2) + 802c184: 10801de0 cmpeqi r2,r2,119 + 802c188: 1000071e bne r2,zero,802c1a8 + so->so_state &= ~(SS_ISCONNECTING|SS_WASCONNECTING); + 802c18c: e0bffe17 ldw r2,-8(fp) + 802c190: 10c0088b ldhu r3,34(r2) + 802c194: 00b7fec4 movi r2,-8197 + 802c198: 1884703a and r2,r3,r2 + 802c19c: 1007883a mov r3,r2 + 802c1a0: e0bffe17 ldw r2,-8(fp) + 802c1a4: 10c0088d sth r3,34(r2) + m_freem (nam); + 802c1a8: e13ffd17 ldw r4,-12(fp) + 802c1ac: 8029cfc0 call 8029cfc + + UNLOCK_NET_RESOURCE(NET_RESID); + 802c1b0: 0009883a mov r4,zero + 802c1b4: 8028ff40 call 8028ff4 + if (so->so_error) + 802c1b8: e0bffe17 ldw r2,-8(fp) + 802c1bc: 10800617 ldw r2,24(r2) + 802c1c0: 10000226 beq r2,zero,802c1cc + { +/* printf("t_connect(): so_error = %d\n", so->so_error);*/ + return SOCKET_ERROR; + 802c1c4: 00bfffc4 movi r2,-1 + 802c1c8: 00000106 br 802c1d0 + + } + return 0; + 802c1cc: 0005883a mov r2,zero +} + 802c1d0: e037883a mov sp,fp + 802c1d4: dfc00117 ldw ra,4(sp) + 802c1d8: df000017 ldw fp,0(sp) + 802c1dc: dec00204 addi sp,sp,8 + 802c1e0: f800283a ret + +0802c1e4 : + * RETURNS: + */ + +int +t_getpeername(long s, struct sockaddr * addr, int * addrlen) +{ + 802c1e4: defffb04 addi sp,sp,-20 + 802c1e8: dfc00415 stw ra,16(sp) + 802c1ec: df000315 stw fp,12(sp) + 802c1f0: df000304 addi fp,sp,12 + 802c1f4: e13fff15 stw r4,-4(fp) + 802c1f8: e17ffe15 stw r5,-8(fp) + 802c1fc: e1bffd15 stw r6,-12(fp) + return(t_getname(s, addr, addrlen, PRU_PEERADDR)); + 802c200: 01c00404 movi r7,16 + 802c204: e1bffd17 ldw r6,-12(fp) + 802c208: e17ffe17 ldw r5,-8(fp) + 802c20c: e13fff17 ldw r4,-4(fp) + 802c210: 802c26c0 call 802c26c +} + 802c214: e037883a mov sp,fp + 802c218: dfc00117 ldw ra,4(sp) + 802c21c: df000017 ldw fp,0(sp) + 802c220: dec00204 addi sp,sp,8 + 802c224: f800283a ret + +0802c228 : + * RETURNS: + */ + +int +t_getsockname(long s, struct sockaddr * addr, int * addrlen) +{ + 802c228: defffb04 addi sp,sp,-20 + 802c22c: dfc00415 stw ra,16(sp) + 802c230: df000315 stw fp,12(sp) + 802c234: df000304 addi fp,sp,12 + 802c238: e13fff15 stw r4,-4(fp) + 802c23c: e17ffe15 stw r5,-8(fp) + 802c240: e1bffd15 stw r6,-12(fp) + return(t_getname(s, addr, addrlen, PRU_SOCKADDR)); + 802c244: 01c003c4 movi r7,15 + 802c248: e1bffd17 ldw r6,-12(fp) + 802c24c: e17ffe17 ldw r5,-8(fp) + 802c250: e13fff17 ldw r4,-4(fp) + 802c254: 802c26c0 call 802c26c +} + 802c258: e037883a mov sp,fp + 802c25c: dfc00117 ldw ra,4(sp) + 802c260: df000017 ldw fp,0(sp) + 802c264: dec00204 addi sp,sp,8 + 802c268: f800283a ret + +0802c26c : + * RETURNS: + */ + +static int +t_getname(long s, struct sockaddr * addr, int * addrlen, int opcode) +{ + 802c26c: defff604 addi sp,sp,-40 + 802c270: dfc00915 stw ra,36(sp) + 802c274: df000815 stw fp,32(sp) + 802c278: df000804 addi fp,sp,32 + 802c27c: e13ffb15 stw r4,-20(fp) + 802c280: e17ffa15 stw r5,-24(fp) + 802c284: e1bff915 stw r6,-28(fp) + 802c288: e1fff815 stw r7,-32(fp) + struct socket * so; + struct mbuf * m; + int err; + + so = LONG2SO(s); + 802c28c: e0bffb17 ldw r2,-20(fp) + 802c290: 10bffc04 addi r2,r2,-16 + 802c294: 100490ba slli r2,r2,2 + 802c298: e0bffe15 stw r2,-8(fp) + SOC_CHECK(so); + 802c29c: 008201b4 movhi r2,2054 + 802c2a0: 10b87104 addi r2,r2,-7740 + 802c2a4: e0bfff15 stw r2,-4(fp) + 802c2a8: 00000606 br 802c2c4 + 802c2ac: e0ffff17 ldw r3,-4(fp) + 802c2b0: e0bffe17 ldw r2,-8(fp) + 802c2b4: 18800626 beq r3,r2,802c2d0 + 802c2b8: e0bfff17 ldw r2,-4(fp) + 802c2bc: 10800017 ldw r2,0(r2) + 802c2c0: e0bfff15 stw r2,-4(fp) + 802c2c4: e0bfff17 ldw r2,-4(fp) + 802c2c8: 103ff81e bne r2,zero,802c2ac + 802c2cc: 00000106 br 802c2d4 + 802c2d0: 0001883a nop + 802c2d4: e0ffff17 ldw r3,-4(fp) + 802c2d8: e0bffe17 ldw r2,-8(fp) + 802c2dc: 18800326 beq r3,r2,802c2ec + 802c2e0: 8028cd40 call 8028cd4 + 802c2e4: 00bfffc4 movi r2,-1 + 802c2e8: 00005306 br 802c438 + + so->so_error = 0; + 802c2ec: e0bffe17 ldw r2,-8(fp) + 802c2f0: 10000615 stw zero,24(r2) + INET_TRACE (INETM_SOCKET, ("INET:get[sock|peer]name so %x\n", so)); + if((opcode == PRU_PEERADDR) && (so->so_state & SS_ISCONNECTED) == 0) + 802c2f4: e0bff817 ldw r2,-32(fp) + 802c2f8: 10800418 cmpnei r2,r2,16 + 802c2fc: 10000a1e bne r2,zero,802c328 + 802c300: e0bffe17 ldw r2,-8(fp) + 802c304: 1080088b ldhu r2,34(r2) + 802c308: 10bfffcc andi r2,r2,65535 + 802c30c: 1080008c andi r2,r2,2 + 802c310: 1000051e bne r2,zero,802c328 + { + so->so_error = ENOTCONN; + 802c314: e0bffe17 ldw r2,-8(fp) + 802c318: 00c02004 movi r3,128 + 802c31c: 10c00615 stw r3,24(r2) + return SOCKET_ERROR; + 802c320: 00bfffc4 movi r2,-1 + 802c324: 00004406 br 802c438 + } + LOCK_NET_RESOURCE(NET_RESID); + 802c328: 0009883a mov r4,zero + 802c32c: 8028f380 call 8028f38 + m = m_getwithdata (MT_SONAME, sizeof (struct sockaddr)); + 802c330: 01400404 movi r5,16 + 802c334: 01000244 movi r4,9 + 802c338: 8029a700 call 8029a70 + 802c33c: e0bffd15 stw r2,-12(fp) + if (m == NULL) + 802c340: e0bffd17 ldw r2,-12(fp) + 802c344: 1000071e bne r2,zero,802c364 + { + so->so_error = ENOMEM; + 802c348: e0bffe17 ldw r2,-8(fp) + 802c34c: 00c00304 movi r3,12 + 802c350: 10c00615 stw r3,24(r2) + UNLOCK_NET_RESOURCE(NET_RESID); + 802c354: 0009883a mov r4,zero + 802c358: 8028ff40 call 8028ff4 + return SOCKET_ERROR; + 802c35c: 00bfffc4 movi r2,-1 + 802c360: 00003506 br 802c438 + } + so->so_req = opcode; + 802c364: e0bffe17 ldw r2,-8(fp) + 802c368: e0fff817 ldw r3,-32(fp) + 802c36c: 10c00715 stw r3,28(r2) + if ((err = (*so->so_proto->pr_usrreq)(so, 0, m)) != 0) + 802c370: e0bffe17 ldw r2,-8(fp) + 802c374: 10800217 ldw r2,8(r2) + 802c378: 10800317 ldw r2,12(r2) + 802c37c: e1bffd17 ldw r6,-12(fp) + 802c380: 000b883a mov r5,zero + 802c384: e13ffe17 ldw r4,-8(fp) + 802c388: 103ee83a callr r2 + 802c38c: e0bffc15 stw r2,-16(fp) + 802c390: e0bffc17 ldw r2,-16(fp) + 802c394: 1000191e bne r2,zero,802c3fc + goto bad; + +#ifdef IP_V4 + if(so->so_domain == AF_INET) + 802c398: e0bffe17 ldw r2,-8(fp) + 802c39c: 10800517 ldw r2,20(r2) + 802c3a0: 10800098 cmpnei r2,r2,2 + 802c3a4: 1000171e bne r2,zero,802c404 + { + if(*addrlen < sizeof(struct sockaddr_in)) + 802c3a8: e0bff917 ldw r2,-28(fp) + 802c3ac: 10800017 ldw r2,0(r2) + 802c3b0: 10800428 cmpgeui r2,r2,16 + 802c3b4: 1000071e bne r2,zero,802c3d4 + { + dtrap(); /* programming error */ + 802c3b8: 8028cd40 call 8028cd4 + m_freem(m); + 802c3bc: e13ffd17 ldw r4,-12(fp) + 802c3c0: 8029cfc0 call 8029cfc + UNLOCK_NET_RESOURCE(NET_RESID); + 802c3c4: 0009883a mov r4,zero + 802c3c8: 8028ff40 call 8028ff4 + return EINVAL; + 802c3cc: 00800584 movi r2,22 + 802c3d0: 00001906 br 802c438 + } + MEMCPY(addr, m->m_data, sizeof(struct sockaddr_in)); + 802c3d4: e0bffd17 ldw r2,-12(fp) + 802c3d8: 10800317 ldw r2,12(r2) + 802c3dc: 01800404 movi r6,16 + 802c3e0: 100b883a mov r5,r2 + 802c3e4: e13ffa17 ldw r4,-24(fp) + 802c3e8: 80086b80 call 80086b8 + *addrlen = sizeof(struct sockaddr_in); + 802c3ec: e0bff917 ldw r2,-28(fp) + 802c3f0: 00c00404 movi r3,16 + 802c3f4: 10c00015 stw r3,0(r2) + 802c3f8: 00000306 br 802c408 + goto bad; + 802c3fc: 0001883a nop + 802c400: 00000106 br 802c408 + *addrlen = sizeof(struct sockaddr_in6); + } +#endif /* IP_V6 */ + + +bad: + 802c404: 0001883a nop + m_freem(m); + 802c408: e13ffd17 ldw r4,-12(fp) + 802c40c: 8029cfc0 call 8029cfc + UNLOCK_NET_RESOURCE(NET_RESID); + 802c410: 0009883a mov r4,zero + 802c414: 8028ff40 call 8028ff4 + if (err) + 802c418: e0bffc17 ldw r2,-16(fp) + 802c41c: 10000526 beq r2,zero,802c434 + { + so->so_error = err; + 802c420: e0bffe17 ldw r2,-8(fp) + 802c424: e0fffc17 ldw r3,-16(fp) + 802c428: 10c00615 stw r3,24(r2) + return SOCKET_ERROR; + 802c42c: 00bfffc4 movi r2,-1 + 802c430: 00000106 br 802c438 + } + return 0; + 802c434: 0005883a mov r2,zero +} + 802c438: e037883a mov sp,fp + 802c43c: dfc00117 ldw ra,4(sp) + 802c440: df000017 ldw fp,0(sp) + 802c444: dec00204 addi sp,sp,8 + 802c448: f800283a ret + +0802c44c : +t_setsockopt(long s, + int level, + int name, + void * arg, + int arglen) +{ + 802c44c: defff704 addi sp,sp,-36 + 802c450: dfc00815 stw ra,32(sp) + 802c454: df000715 stw fp,28(sp) + 802c458: df000704 addi fp,sp,28 + 802c45c: e13ffc15 stw r4,-16(fp) + 802c460: e17ffb15 stw r5,-20(fp) + 802c464: e1bffa15 stw r6,-24(fp) + 802c468: e1fff915 stw r7,-28(fp) + struct socket * so; + int err; + + so = LONG2SO(s); + 802c46c: e0bffc17 ldw r2,-16(fp) + 802c470: 10bffc04 addi r2,r2,-16 + 802c474: 100490ba slli r2,r2,2 + 802c478: e0bffe15 stw r2,-8(fp) + SOC_CHECK(so); + 802c47c: 008201b4 movhi r2,2054 + 802c480: 10b87104 addi r2,r2,-7740 + 802c484: e0bfff15 stw r2,-4(fp) + 802c488: 00000606 br 802c4a4 + 802c48c: e0ffff17 ldw r3,-4(fp) + 802c490: e0bffe17 ldw r2,-8(fp) + 802c494: 18800626 beq r3,r2,802c4b0 + 802c498: e0bfff17 ldw r2,-4(fp) + 802c49c: 10800017 ldw r2,0(r2) + 802c4a0: e0bfff15 stw r2,-4(fp) + 802c4a4: e0bfff17 ldw r2,-4(fp) + 802c4a8: 103ff81e bne r2,zero,802c48c + 802c4ac: 00000106 br 802c4b4 + 802c4b0: 0001883a nop + 802c4b4: e0ffff17 ldw r3,-4(fp) + 802c4b8: e0bffe17 ldw r2,-8(fp) + 802c4bc: 18800326 beq r3,r2,802c4cc + 802c4c0: 8028cd40 call 8028cd4 + 802c4c4: 00bfffc4 movi r2,-1 + 802c4c8: 00004b06 br 802c5f8 + USE_ARG(arglen); + + LOCK_NET_RESOURCE (NET_RESID); + 802c4cc: 0009883a mov r4,zero + 802c4d0: 8028f380 call 8028f38 + + so->so_error = 0; + 802c4d4: e0bffe17 ldw r2,-8(fp) + 802c4d8: 10000615 stw zero,24(r2) + INET_TRACE (INETM_SOCKET, + ("INET: setsockopt: name %x val %x valsize %d\n", + name, val)); + + /* is it a level IP_OPTIONS call? */ + if (level != IP_OPTIONS) + 802c4dc: e0bffb17 ldw r2,-20(fp) + 802c4e0: 10800060 cmpeqi r2,r2,1 + 802c4e4: 10000e1e bne r2,zero,802c520 + { + if ((err = sosetopt (so, name, arg)) != 0) + 802c4e8: e1bff917 ldw r6,-28(fp) + 802c4ec: e17ffa17 ldw r5,-24(fp) + 802c4f0: e13ffe17 ldw r4,-8(fp) + 802c4f4: 802e7800 call 802e780 + 802c4f8: e0bffd15 stw r2,-12(fp) + 802c4fc: e0bffd17 ldw r2,-12(fp) + 802c500: 10003a26 beq r2,zero,802c5ec + { + so->so_error = err; + 802c504: e0bffe17 ldw r2,-8(fp) + 802c508: e0fffd17 ldw r3,-12(fp) + 802c50c: 10c00615 stw r3,24(r2) + UNLOCK_NET_RESOURCE (NET_RESID); + 802c510: 0009883a mov r4,zero + 802c514: 8028ff40 call 8028ff4 + return SOCKET_ERROR; + 802c518: 00bfffc4 movi r2,-1 + 802c51c: 00003606 br 802c5f8 + { + /* level 1 options are for the IP packet level. + * the info is carried in the socket CB, then put + * into the PACKET. + */ + if (!so->so_optsPack) + 802c520: e0bffe17 ldw r2,-8(fp) + 802c524: 10801f17 ldw r2,124(r2) + 802c528: 10000f1e bne r2,zero,802c568 + { + so->so_optsPack = (struct ip_socopts *) SOCOPT_ALLOC (sizeof(struct ip_socopts *)); + 802c52c: 01000104 movi r4,4 + 802c530: 802982c0 call 802982c + 802c534: 1007883a mov r3,r2 + 802c538: e0bffe17 ldw r2,-8(fp) + 802c53c: 10c01f15 stw r3,124(r2) + if (!so->so_optsPack) + 802c540: e0bffe17 ldw r2,-8(fp) + 802c544: 10801f17 ldw r2,124(r2) + 802c548: 1000071e bne r2,zero,802c568 + { + so->so_error = ENOMEM; + 802c54c: e0bffe17 ldw r2,-8(fp) + 802c550: 00c00304 movi r3,12 + 802c554: 10c00615 stw r3,24(r2) + UNLOCK_NET_RESOURCE (NET_RESID); + 802c558: 0009883a mov r4,zero + 802c55c: 8028ff40 call 8028ff4 + return SOCKET_ERROR; + 802c560: 00bfffc4 movi r2,-1 + 802c564: 00002406 br 802c5f8 + } + } + + if (name == IP_TTL_OPT) + 802c568: e0bffa17 ldw r2,-24(fp) + 802c56c: 10800118 cmpnei r2,r2,4 + 802c570: 1000061e bne r2,zero,802c58c + so->so_optsPack->ip_ttl = (u_char)(*(int *)arg); + 802c574: e0bff917 ldw r2,-28(fp) + 802c578: 10c00017 ldw r3,0(r2) + 802c57c: e0bffe17 ldw r2,-8(fp) + 802c580: 10801f17 ldw r2,124(r2) + 802c584: 10c00045 stb r3,1(r2) + 802c588: 00001806 br 802c5ec + else + if (name == IP_TOS) + 802c58c: e0bffa17 ldw r2,-24(fp) + 802c590: 108000d8 cmpnei r2,r2,3 + 802c594: 1000061e bne r2,zero,802c5b0 + so->so_optsPack->ip_tos = (u_char)(*(int *)arg); + 802c598: e0bff917 ldw r2,-28(fp) + 802c59c: 10c00017 ldw r3,0(r2) + 802c5a0: e0bffe17 ldw r2,-8(fp) + 802c5a4: 10801f17 ldw r2,124(r2) + 802c5a8: 10c00005 stb r3,0(r2) + 802c5ac: 00000f06 br 802c5ec + else + if (name == IP_SCOPEID) + 802c5b0: e0bffa17 ldw r2,-24(fp) + 802c5b4: 10800398 cmpnei r2,r2,14 + 802c5b8: 1000081e bne r2,zero,802c5dc + so->so_optsPack->ip_scopeid = (u_char)(*(u_int *)arg); + 802c5bc: e0bff917 ldw r2,-28(fp) + 802c5c0: 10800017 ldw r2,0(r2) + 802c5c4: 1007883a mov r3,r2 + 802c5c8: e0bffe17 ldw r2,-8(fp) + 802c5cc: 10801f17 ldw r2,124(r2) + 802c5d0: 18c03fcc andi r3,r3,255 + 802c5d4: 10c00115 stw r3,4(r2) + 802c5d8: 00000406 br 802c5ec + else + { + UNLOCK_NET_RESOURCE (NET_RESID); + 802c5dc: 0009883a mov r4,zero + 802c5e0: 8028ff40 call 8028ff4 + return SOCKET_ERROR; + 802c5e4: 00bfffc4 movi r2,-1 + 802c5e8: 00000306 br 802c5f8 + } + } + + UNLOCK_NET_RESOURCE (NET_RESID); + 802c5ec: 0009883a mov r4,zero + 802c5f0: 8028ff40 call 8028ff4 + return 0; + 802c5f4: 0005883a mov r2,zero +} + 802c5f8: e037883a mov sp,fp + 802c5fc: dfc00117 ldw ra,4(sp) + 802c600: df000017 ldw fp,0(sp) + 802c604: dec00204 addi sp,sp,8 + 802c608: f800283a ret + +0802c60c : + int level, + int name, + void * arg, + int arglen) + +{ + 802c60c: defff704 addi sp,sp,-36 + 802c610: dfc00815 stw ra,32(sp) + 802c614: df000715 stw fp,28(sp) + 802c618: df000704 addi fp,sp,28 + 802c61c: e13ffc15 stw r4,-16(fp) + 802c620: e17ffb15 stw r5,-20(fp) + 802c624: e1bffa15 stw r6,-24(fp) + 802c628: e1fff915 stw r7,-28(fp) + struct socket * so; + int err; + + so = LONG2SO(s); + 802c62c: e0bffc17 ldw r2,-16(fp) + 802c630: 10bffc04 addi r2,r2,-16 + 802c634: 100490ba slli r2,r2,2 + 802c638: e0bffe15 stw r2,-8(fp) + SOC_CHECK(so); + 802c63c: 008201b4 movhi r2,2054 + 802c640: 10b87104 addi r2,r2,-7740 + 802c644: e0bfff15 stw r2,-4(fp) + 802c648: 00000606 br 802c664 + 802c64c: e0ffff17 ldw r3,-4(fp) + 802c650: e0bffe17 ldw r2,-8(fp) + 802c654: 18800626 beq r3,r2,802c670 + 802c658: e0bfff17 ldw r2,-4(fp) + 802c65c: 10800017 ldw r2,0(r2) + 802c660: e0bfff15 stw r2,-4(fp) + 802c664: e0bfff17 ldw r2,-4(fp) + 802c668: 103ff81e bne r2,zero,802c64c + 802c66c: 00000106 br 802c674 + 802c670: 0001883a nop + 802c674: e0ffff17 ldw r3,-4(fp) + 802c678: e0bffe17 ldw r2,-8(fp) + 802c67c: 18800326 beq r3,r2,802c68c + 802c680: 8028cd40 call 8028cd4 + 802c684: 00bfffc4 movi r2,-1 + 802c688: 00003d06 br 802c780 + USE_ARG(level); + USE_ARG(arglen); + + LOCK_NET_RESOURCE (NET_RESID); + 802c68c: 0009883a mov r4,zero + 802c690: 8028f380 call 8028f38 + INET_TRACE (INETM_SOCKET, + ("INET: getsockopt: name %x val %x valsize %d\n", + name, val)); + + /* is it a level IP_OPTIONS call? */ + if (level != IP_OPTIONS) + 802c694: e0bffb17 ldw r2,-20(fp) + 802c698: 10800060 cmpeqi r2,r2,1 + 802c69c: 10000e1e bne r2,zero,802c6d8 + { + if ((err = sogetopt (so, name, arg)) != 0) + 802c6a0: e1bff917 ldw r6,-28(fp) + 802c6a4: e17ffa17 ldw r5,-24(fp) + 802c6a8: e13ffe17 ldw r4,-8(fp) + 802c6ac: 802ec0c0 call 802ec0c + 802c6b0: e0bffd15 stw r2,-12(fp) + 802c6b4: e0bffd17 ldw r2,-12(fp) + 802c6b8: 10002c26 beq r2,zero,802c76c + { + so->so_error = err; + 802c6bc: e0bffe17 ldw r2,-8(fp) + 802c6c0: e0fffd17 ldw r3,-12(fp) + 802c6c4: 10c00615 stw r3,24(r2) + UNLOCK_NET_RESOURCE (NET_RESID); + 802c6c8: 0009883a mov r4,zero + 802c6cc: 8028ff40 call 8028ff4 + return SOCKET_ERROR; + 802c6d0: 00bfffc4 movi r2,-1 + 802c6d4: 00002a06 br 802c780 + { + /* level 1 options are for the IP packet level. + * the info is carried in the socket CB, then put + * into the PACKET. + */ + if (name == IP_TTL_OPT) + 802c6d8: e0bffa17 ldw r2,-24(fp) + 802c6dc: 10800118 cmpnei r2,r2,4 + 802c6e0: 10000e1e bne r2,zero,802c71c + { + if (!so->so_optsPack) *(int *)arg = IP_TTL; + 802c6e4: e0bffe17 ldw r2,-8(fp) + 802c6e8: 10801f17 ldw r2,124(r2) + 802c6ec: 1000041e bne r2,zero,802c700 + 802c6f0: e0bff917 ldw r2,-28(fp) + 802c6f4: 00c01004 movi r3,64 + 802c6f8: 10c00015 stw r3,0(r2) + 802c6fc: 00001b06 br 802c76c + else *(int *)arg = (int)so->so_optsPack->ip_ttl; + 802c700: e0bffe17 ldw r2,-8(fp) + 802c704: 10801f17 ldw r2,124(r2) + 802c708: 10800043 ldbu r2,1(r2) + 802c70c: 10c03fcc andi r3,r2,255 + 802c710: e0bff917 ldw r2,-28(fp) + 802c714: 10c00015 stw r3,0(r2) + 802c718: 00001406 br 802c76c + } + else if (name == IP_TOS) + 802c71c: e0bffa17 ldw r2,-24(fp) + 802c720: 108000d8 cmpnei r2,r2,3 + 802c724: 10000d1e bne r2,zero,802c75c + { + if (!so->so_optsPack) *(int *)arg = IP_TOS_DEFVAL; + 802c728: e0bffe17 ldw r2,-8(fp) + 802c72c: 10801f17 ldw r2,124(r2) + 802c730: 1000031e bne r2,zero,802c740 + 802c734: e0bff917 ldw r2,-28(fp) + 802c738: 10000015 stw zero,0(r2) + 802c73c: 00000b06 br 802c76c + else *(int *)arg = (int)so->so_optsPack->ip_tos; + 802c740: e0bffe17 ldw r2,-8(fp) + 802c744: 10801f17 ldw r2,124(r2) + 802c748: 10800003 ldbu r2,0(r2) + 802c74c: 10c03fcc andi r3,r2,255 + 802c750: e0bff917 ldw r2,-28(fp) + 802c754: 10c00015 stw r3,0(r2) + 802c758: 00000406 br 802c76c + } + else + { + UNLOCK_NET_RESOURCE (NET_RESID); + 802c75c: 0009883a mov r4,zero + 802c760: 8028ff40 call 8028ff4 + return SOCKET_ERROR; + 802c764: 00bfffc4 movi r2,-1 + 802c768: 00000506 br 802c780 + } + } + so->so_error = 0; + 802c76c: e0bffe17 ldw r2,-8(fp) + 802c770: 10000615 stw zero,24(r2) + + UNLOCK_NET_RESOURCE (NET_RESID); + 802c774: 0009883a mov r4,zero + 802c778: 8028ff40 call 8028ff4 + return 0; + 802c77c: 0005883a mov r2,zero +} + 802c780: e037883a mov sp,fp + 802c784: dfc00117 ldw ra,4(sp) + 802c788: df000017 ldw fp,0(sp) + 802c78c: dec00204 addi sp,sp,8 + 802c790: f800283a ret + +0802c794 : +int +t_recv (long s, + char * buf, + int len, + int flag) +{ + 802c794: defff604 addi sp,sp,-40 + 802c798: dfc00915 stw ra,36(sp) + 802c79c: df000815 stw fp,32(sp) + 802c7a0: df000804 addi fp,sp,32 + 802c7a4: e13ffc15 stw r4,-16(fp) + 802c7a8: e17ffb15 stw r5,-20(fp) + 802c7ac: e1bffa15 stw r6,-24(fp) + 802c7b0: e1fff915 stw r7,-28(fp) +#ifdef SOCKDEBUG + char logbuf[10]; +#endif + struct socket * so; + int err; + int sendlen = len; + 802c7b4: e0bffa17 ldw r2,-24(fp) + 802c7b8: e0bfff15 stw r2,-4(fp) + + so = LONG2SO(s); + 802c7bc: e0bffc17 ldw r2,-16(fp) + 802c7c0: 10bffc04 addi r2,r2,-16 + 802c7c4: 100490ba slli r2,r2,2 + 802c7c8: e0bffe15 stw r2,-8(fp) +#ifdef SOC_CHECK_ALWAYS + SOC_CHECK(so); +#endif + if ((so->so_state & SO_IO_OK) != SS_ISCONNECTED) + 802c7cc: e0bffe17 ldw r2,-8(fp) + 802c7d0: 1080088b ldhu r2,34(r2) + 802c7d4: 10bfffcc andi r2,r2,65535 + 802c7d8: 1080038c andi r2,r2,14 + 802c7dc: 108000a0 cmpeqi r2,r2,2 + 802c7e0: 1000051e bne r2,zero,802c7f8 + { + so->so_error = EPIPE; + 802c7e4: e0bffe17 ldw r2,-8(fp) + 802c7e8: 00c00804 movi r3,32 + 802c7ec: 10c00615 stw r3,24(r2) +#ifdef SOCKDEBUG + sprintf(logbuf, "t_recv: %d", so->so_error); + glog_with_type(LOG_TYPE_DEBUG, logbuf, 1); +#endif + return SOCKET_ERROR; + 802c7f0: 00bfffc4 movi r2,-1 + 802c7f4: 00001906 br 802c85c + } + so->so_error = 0; + 802c7f8: e0bffe17 ldw r2,-8(fp) + 802c7fc: 10000615 stw zero,24(r2) + + LOCK_NET_RESOURCE(NET_RESID); + 802c800: 0009883a mov r4,zero + 802c804: 8028f380 call 8028f38 + IN_PROFILER(PF_TCP, PF_ENTRY); /* measure time in TCP */ + INET_TRACE (INETM_IO, ("INET:recv: so %x, len %d\n", so, len)); + err = soreceive(so, NULL, buf, &len, flag); + 802c808: e0fffa04 addi r3,fp,-24 + 802c80c: e0bff917 ldw r2,-28(fp) + 802c810: d8800015 stw r2,0(sp) + 802c814: 180f883a mov r7,r3 + 802c818: e1bffb17 ldw r6,-20(fp) + 802c81c: 000b883a mov r5,zero + 802c820: e13ffe17 ldw r4,-8(fp) + 802c824: 802de940 call 802de94 + 802c828: e0bffd15 stw r2,-12(fp) + IN_PROFILER(PF_TCP, PF_EXIT); /* measure time in TCP */ + UNLOCK_NET_RESOURCE(NET_RESID); + 802c82c: 0009883a mov r4,zero + 802c830: 8028ff40 call 8028ff4 + + if(err) + 802c834: e0bffd17 ldw r2,-12(fp) + 802c838: 10000526 beq r2,zero,802c850 + { + so->so_error = err; + 802c83c: e0bffe17 ldw r2,-8(fp) + 802c840: e0fffd17 ldw r3,-12(fp) + 802c844: 10c00615 stw r3,24(r2) +#ifdef SOCKDEBUG + sprintf(logbuf, "t_recv: %d", so->so_error); + glog_with_type(LOG_TYPE_DEBUG, logbuf, 1); +#endif + return SOCKET_ERROR; + 802c848: 00bfffc4 movi r2,-1 + 802c84c: 00000306 br 802c85c + } + + /* return bytes we sent - the amount we wanted to send minus + * the amount left in the buffer. + */ + return (sendlen - len); + 802c850: e0bffa17 ldw r2,-24(fp) + 802c854: e0ffff17 ldw r3,-4(fp) + 802c858: 1885c83a sub r2,r3,r2 +} + 802c85c: e037883a mov sp,fp + 802c860: dfc00117 ldw ra,4(sp) + 802c864: df000017 ldw fp,0(sp) + 802c868: dec00204 addi sp,sp,8 + 802c86c: f800283a ret + +0802c870 : + char * buf, + int len, + int flags, + struct sockaddr * from, + int * fromlen) +{ + 802c870: defff404 addi sp,sp,-48 + 802c874: dfc00b15 stw ra,44(sp) + 802c878: df000a15 stw fp,40(sp) + 802c87c: df000a04 addi fp,sp,40 + 802c880: e13ffa15 stw r4,-24(fp) + 802c884: e17ff915 stw r5,-28(fp) + 802c888: e1bff815 stw r6,-32(fp) + 802c88c: e1fff715 stw r7,-36(fp) + struct socket * so; + struct mbuf * sender = NULL; + 802c890: e03ffb15 stw zero,-20(fp) + int err; + int sendlen = len; + 802c894: e0bff817 ldw r2,-32(fp) + 802c898: e0bffe15 stw r2,-8(fp) + + so = LONG2SO(s); + 802c89c: e0bffa17 ldw r2,-24(fp) + 802c8a0: 10bffc04 addi r2,r2,-16 + 802c8a4: 100490ba slli r2,r2,2 + 802c8a8: e0bffd15 stw r2,-12(fp) + SOC_CHECK(so); + 802c8ac: 008201b4 movhi r2,2054 + 802c8b0: 10b87104 addi r2,r2,-7740 + 802c8b4: e0bfff15 stw r2,-4(fp) + 802c8b8: 00000606 br 802c8d4 + 802c8bc: e0ffff17 ldw r3,-4(fp) + 802c8c0: e0bffd17 ldw r2,-12(fp) + 802c8c4: 18800626 beq r3,r2,802c8e0 + 802c8c8: e0bfff17 ldw r2,-4(fp) + 802c8cc: 10800017 ldw r2,0(r2) + 802c8d0: e0bfff15 stw r2,-4(fp) + 802c8d4: e0bfff17 ldw r2,-4(fp) + 802c8d8: 103ff81e bne r2,zero,802c8bc + 802c8dc: 00000106 br 802c8e4 + 802c8e0: 0001883a nop + 802c8e4: e0ffff17 ldw r3,-4(fp) + 802c8e8: e0bffd17 ldw r2,-12(fp) + 802c8ec: 18800326 beq r3,r2,802c8fc + 802c8f0: 8028cd40 call 8028cd4 + 802c8f4: 00bfffc4 movi r2,-1 + 802c8f8: 00002706 br 802c998 + so->so_error = 0; + 802c8fc: e0bffd17 ldw r2,-12(fp) + 802c900: 10000615 stw zero,24(r2) + + LOCK_NET_RESOURCE(NET_RESID); + 802c904: 0009883a mov r4,zero + 802c908: 8028f380 call 8028f38 + + err = soreceive(so, &sender, buf, &len, flags); + 802c90c: e13ff804 addi r4,fp,-32 + 802c910: e0fffb04 addi r3,fp,-20 + 802c914: e0bff717 ldw r2,-36(fp) + 802c918: d8800015 stw r2,0(sp) + 802c91c: 200f883a mov r7,r4 + 802c920: e1bff917 ldw r6,-28(fp) + 802c924: 180b883a mov r5,r3 + 802c928: e13ffd17 ldw r4,-12(fp) + 802c92c: 802de940 call 802de94 + 802c930: e0bffc15 stw r2,-16(fp) + + /* copy sender info from mbuf to sockaddr */ + if (sender) + 802c934: e0bffb17 ldw r2,-20(fp) + 802c938: 10000b26 beq r2,zero,802c968 + { + MEMCPY(from, (mtod(sender, struct sockaddr *)), *fromlen ); + 802c93c: e0bffb17 ldw r2,-20(fp) + 802c940: 10c00317 ldw r3,12(r2) + 802c944: e0800317 ldw r2,12(fp) + 802c948: 10800017 ldw r2,0(r2) + 802c94c: 100d883a mov r6,r2 + 802c950: 180b883a mov r5,r3 + 802c954: e1000217 ldw r4,8(fp) + 802c958: 80086b80 call 80086b8 + m_freem (sender); + 802c95c: e0bffb17 ldw r2,-20(fp) + 802c960: 1009883a mov r4,r2 + 802c964: 8029cfc0 call 8029cfc + } + + UNLOCK_NET_RESOURCE(NET_RESID); + 802c968: 0009883a mov r4,zero + 802c96c: 8028ff40 call 8028ff4 + + if(err) + 802c970: e0bffc17 ldw r2,-16(fp) + 802c974: 10000526 beq r2,zero,802c98c + { + so->so_error = err; + 802c978: e0bffd17 ldw r2,-12(fp) + 802c97c: e0fffc17 ldw r3,-16(fp) + 802c980: 10c00615 stw r3,24(r2) + return SOCKET_ERROR; + 802c984: 00bfffc4 movi r2,-1 + 802c988: 00000306 br 802c998 + } + + /* OK return: amount of data actually sent */ + return (sendlen - len); + 802c98c: e0bff817 ldw r2,-32(fp) + 802c990: e0fffe17 ldw r3,-8(fp) + 802c994: 1885c83a sub r2,r3,r2 +} + 802c998: e037883a mov sp,fp + 802c99c: dfc00117 ldw ra,4(sp) + 802c9a0: df000017 ldw fp,0(sp) + 802c9a4: dec00204 addi sp,sp,8 + 802c9a8: f800283a ret + +0802c9ac : + char * buf, + int len, + int flags, + struct sockaddr * to, + int tolen) +{ + 802c9ac: defff404 addi sp,sp,-48 + 802c9b0: dfc00b15 stw ra,44(sp) + 802c9b4: df000a15 stw fp,40(sp) + 802c9b8: df000a04 addi fp,sp,40 + 802c9bc: e13ffa15 stw r4,-24(fp) + 802c9c0: e17ff915 stw r5,-28(fp) + 802c9c4: e1bff815 stw r6,-32(fp) + 802c9c8: e1fff715 stw r7,-36(fp) + struct socket * so; + int sendlen; + int err; + struct mbuf * name; + + so = LONG2SO(s); + 802c9cc: e0bffa17 ldw r2,-24(fp) + 802c9d0: 10bffc04 addi r2,r2,-16 + 802c9d4: 100490ba slli r2,r2,2 + 802c9d8: e0bffd15 stw r2,-12(fp) + SOC_CHECK(so); + 802c9dc: 008201b4 movhi r2,2054 + 802c9e0: 10b87104 addi r2,r2,-7740 + 802c9e4: e0bffe15 stw r2,-8(fp) + 802c9e8: 00000606 br 802ca04 + 802c9ec: e0fffe17 ldw r3,-8(fp) + 802c9f0: e0bffd17 ldw r2,-12(fp) + 802c9f4: 18800626 beq r3,r2,802ca10 + 802c9f8: e0bffe17 ldw r2,-8(fp) + 802c9fc: 10800017 ldw r2,0(r2) + 802ca00: e0bffe15 stw r2,-8(fp) + 802ca04: e0bffe17 ldw r2,-8(fp) + 802ca08: 103ff81e bne r2,zero,802c9ec + 802ca0c: 00000106 br 802ca14 + 802ca10: 0001883a nop + 802ca14: e0fffe17 ldw r3,-8(fp) + 802ca18: e0bffd17 ldw r2,-12(fp) + 802ca1c: 18800326 beq r3,r2,802ca2c + 802ca20: 8028cd40 call 8028cd4 + 802ca24: 00bfffc4 movi r2,-1 + 802ca28: 00005706 br 802cb88 + so->so_error = 0; + 802ca2c: e0bffd17 ldw r2,-12(fp) + 802ca30: 10000615 stw zero,24(r2) + + switch (so->so_type) + 802ca34: e0bffd17 ldw r2,-12(fp) + 802ca38: 10800983 ldbu r2,38(r2) + 802ca3c: 10803fcc andi r2,r2,255 + 802ca40: 1080201c xori r2,r2,128 + 802ca44: 10bfe004 addi r2,r2,-128 + 802ca48: 10c000a0 cmpeqi r3,r2,2 + 802ca4c: 18000a1e bne r3,zero,802ca78 + 802ca50: 10c000e0 cmpeqi r3,r2,3 + 802ca54: 18000b1e bne r3,zero,802ca84 + 802ca58: 10800058 cmpnei r2,r2,1 + 802ca5c: 1000101e bne r2,zero,802caa0 + { + case SOCK_STREAM: + /* this is a stream socket, so pass this request through + * t_send() for its large-send support. + */ + return t_send(s, buf, len, flags); + 802ca60: e1fff717 ldw r7,-36(fp) + 802ca64: e1bff817 ldw r6,-32(fp) + 802ca68: e17ff917 ldw r5,-28(fp) + 802ca6c: e13ffa17 ldw r4,-24(fp) + 802ca70: 802cb9c0 call 802cb9c + 802ca74: 00004406 br 802cb88 + /*NOTREACHED*/ + case SOCK_DGRAM: + /* datagram (UDP) socket -- prepare to check length */ + sendlen = udp_maxalloc(); + 802ca78: 803dd940 call 803dd94 + 802ca7c: e0bffb15 stw r2,-20(fp) + break; + 802ca80: 00000d06 br 802cab8 +#ifdef IP_RAW + case SOCK_RAW: + /* raw socket -- prepare to check length */ + sendlen = ip_raw_maxalloc(so->so_options & SO_HDRINCL); + 802ca84: e0bffd17 ldw r2,-12(fp) + 802ca88: 10800417 ldw r2,16(r2) + 802ca8c: 1088000c andi r2,r2,8192 + 802ca90: 1009883a mov r4,r2 + 802ca94: 803cae00 call 803cae0 + 802ca98: e0bffb15 stw r2,-20(fp) + break; + 802ca9c: 00000606 br 802cab8 +#endif /* IP_RAW */ + default: + /* socket has unknown type */ + dtrap(); + 802caa0: 8028cd40 call 8028cd4 + so->so_error = EFAULT; + 802caa4: e0bffd17 ldw r2,-12(fp) + 802caa8: 00c00384 movi r3,14 + 802caac: 10c00615 stw r3,24(r2) + return SOCKET_ERROR; + 802cab0: 00bfffc4 movi r2,-1 + 802cab4: 00003406 br 802cb88 + /* fall through for non-stream sockets: SOCK_DGRAM (UDP) and + * SOCK_RAW (raw IP) + */ + + /* check length against underlying stack's maximum */ + if (len > sendlen) + 802cab8: e0fffb17 ldw r3,-20(fp) + 802cabc: e0bff817 ldw r2,-32(fp) + 802cac0: 1880050e bge r3,r2,802cad8 + { + so->so_error = EMSGSIZE; + 802cac4: e0bffd17 ldw r2,-12(fp) + 802cac8: 00c01e84 movi r3,122 + 802cacc: 10c00615 stw r3,24(r2) + return SOCKET_ERROR; + 802cad0: 00bfffc4 movi r2,-1 + 802cad4: 00002c06 br 802cb88 + /* if a sockaddr was passed, wrap it in an mbuf and pas it into the + * bowels of the BSD code; else assume this is a bound UDP socket + * and this call came from t_send() below. + */ + + if (to) /* sockaddr was passed */ + 802cad8: e0800217 ldw r2,8(fp) + 802cadc: 10000c26 beq r2,zero,802cb10 + { + name = sockargs(to, tolen, MT_SONAME); + 802cae0: 01800244 movi r6,9 + 802cae4: e1400317 ldw r5,12(fp) + 802cae8: e1000217 ldw r4,8(fp) + 802caec: 802cf300 call 802cf30 + 802caf0: e0bfff15 stw r2,-4(fp) + if(name == NULL) + 802caf4: e0bfff17 ldw r2,-4(fp) + 802caf8: 1000061e bne r2,zero,802cb14 + { + so->so_error = ENOMEM; + 802cafc: e0bffd17 ldw r2,-12(fp) + 802cb00: 00c00304 movi r3,12 + 802cb04: 10c00615 stw r3,24(r2) + return SOCKET_ERROR; + 802cb08: 00bfffc4 movi r2,-1 + 802cb0c: 00001e06 br 802cb88 + } + } + else /* hope user called bind() first... */ + name = NULL; + 802cb10: e03fff15 stw zero,-4(fp) + + sendlen = len; + 802cb14: e0bff817 ldw r2,-32(fp) + 802cb18: e0bffb15 stw r2,-20(fp) + + LOCK_NET_RESOURCE(NET_RESID); + 802cb1c: 0009883a mov r4,zero + 802cb20: 8028f380 call 8028f38 + + err = sosend (so, name, buf, &sendlen, flags); + 802cb24: e0fffb04 addi r3,fp,-20 + 802cb28: e0bff717 ldw r2,-36(fp) + 802cb2c: d8800015 stw r2,0(sp) + 802cb30: 180f883a mov r7,r3 + 802cb34: e1bff917 ldw r6,-28(fp) + 802cb38: e17fff17 ldw r5,-4(fp) + 802cb3c: e13ffd17 ldw r4,-12(fp) + 802cb40: 802d9340 call 802d934 + 802cb44: e0bffc15 stw r2,-16(fp) + + if (name) + 802cb48: e0bfff17 ldw r2,-4(fp) + 802cb4c: 10000226 beq r2,zero,802cb58 + m_freem(name); + 802cb50: e13fff17 ldw r4,-4(fp) + 802cb54: 8029cfc0 call 8029cfc + + UNLOCK_NET_RESOURCE(NET_RESID); + 802cb58: 0009883a mov r4,zero + 802cb5c: 8028ff40 call 8028ff4 + + if (err != 0) + 802cb60: e0bffc17 ldw r2,-16(fp) + 802cb64: 10000526 beq r2,zero,802cb7c + { + so->so_error = err; + 802cb68: e0bffd17 ldw r2,-12(fp) + 802cb6c: e0fffc17 ldw r3,-16(fp) + 802cb70: 10c00615 stw r3,24(r2) + return SOCKET_ERROR; + 802cb74: 00bfffc4 movi r2,-1 + 802cb78: 00000306 br 802cb88 + } + + return (len - sendlen); + 802cb7c: e0bffb17 ldw r2,-20(fp) + 802cb80: e0fff817 ldw r3,-32(fp) + 802cb84: 1885c83a sub r2,r3,r2 +} + 802cb88: e037883a mov sp,fp + 802cb8c: dfc00117 ldw ra,4(sp) + 802cb90: df000017 ldw fp,0(sp) + 802cb94: dec00204 addi sp,sp,8 + 802cb98: f800283a ret + +0802cb9c : +int +t_send(long s, + char * buf, + int len, + int flags) +{ + 802cb9c: defff104 addi sp,sp,-60 + 802cba0: dfc00e15 stw ra,56(sp) + 802cba4: df000d15 stw fp,52(sp) + 802cba8: df000d04 addi fp,sp,52 + 802cbac: e13ff815 stw r4,-32(fp) + 802cbb0: e17ff715 stw r5,-36(fp) + 802cbb4: e1bff615 stw r6,-40(fp) + 802cbb8: e1fff515 stw r7,-44(fp) + struct socket * so; + int e; /* error holder */ + int total_sent = 0; + 802cbbc: e03fff15 stw zero,-4(fp) + int maxpkt; + int sendlen; + int sent; + + so = LONG2SO(s); + 802cbc0: e0bff817 ldw r2,-32(fp) + 802cbc4: 10bffc04 addi r2,r2,-16 + 802cbc8: 100490ba slli r2,r2,2 + 802cbcc: e0bffd15 stw r2,-12(fp) +#ifdef SOC_CHECK_ALWAYS + SOC_CHECK(so); +#endif + if ((so->so_state & SO_IO_OK) != SS_ISCONNECTED) + 802cbd0: e0bffd17 ldw r2,-12(fp) + 802cbd4: 1080088b ldhu r2,34(r2) + 802cbd8: 10bfffcc andi r2,r2,65535 + 802cbdc: 1080038c andi r2,r2,14 + 802cbe0: 108000a0 cmpeqi r2,r2,2 + 802cbe4: 1000051e bne r2,zero,802cbfc + { + so->so_error = EPIPE; + 802cbe8: e0bffd17 ldw r2,-12(fp) + 802cbec: 00c00804 movi r3,32 + 802cbf0: 10c00615 stw r3,24(r2) + return SOCKET_ERROR; + 802cbf4: 00bfffc4 movi r2,-1 + 802cbf8: 00006306 br 802cd88 + } + so->so_error = 0; + 802cbfc: e0bffd17 ldw r2,-12(fp) + 802cc00: 10000615 stw zero,24(r2) + + /* If this is not a stream socket, assume it is bound and pass to + * t_sendto() with a null sockaddr + */ + if (so->so_type != SOCK_STREAM) + 802cc04: e0bffd17 ldw r2,-12(fp) + 802cc08: 10800983 ldbu r2,38(r2) + 802cc0c: 10803fcc andi r2,r2,255 + 802cc10: 1080201c xori r2,r2,128 + 802cc14: 10bfe004 addi r2,r2,-128 + 802cc18: 10800060 cmpeqi r2,r2,1 + 802cc1c: 1000081e bne r2,zero,802cc40 + return(t_sendto(s, buf, len, flags, NULL, 0)); + 802cc20: d8000115 stw zero,4(sp) + 802cc24: d8000015 stw zero,0(sp) + 802cc28: e1fff517 ldw r7,-44(fp) + 802cc2c: e1bff617 ldw r6,-40(fp) + 802cc30: e17ff717 ldw r5,-36(fp) + 802cc34: e13ff817 ldw r4,-32(fp) + 802cc38: 802c9ac0 call 802c9ac + 802cc3c: 00005206 br 802cd88 + + maxpkt = TCP_MSS; + 802cc40: 00816d04 movi r2,1460 + 802cc44: e0bffe15 stw r2,-8(fp) + if(so->so_pcb) + 802cc48: e0bffd17 ldw r2,-12(fp) + 802cc4c: 10800117 ldw r2,4(r2) + 802cc50: 10004826 beq r2,zero,802cd74 + { + struct tcpcb * tp; + tp = intotcpcb(so->so_pcb); /* get tcp structure with mss */ + 802cc54: e0bffd17 ldw r2,-12(fp) + 802cc58: 10800117 ldw r2,4(r2) + 802cc5c: 10800917 ldw r2,36(r2) + 802cc60: e0bffc15 stw r2,-16(fp) + if(tp->t_maxseg) /* Make sure it's set */ + 802cc64: e0bffc17 ldw r2,-16(fp) + 802cc68: 10800a0b ldhu r2,40(r2) + 802cc6c: 10bfffcc andi r2,r2,65535 + 802cc70: 10004026 beq r2,zero,802cd74 + maxpkt = tp->t_maxseg; + 802cc74: e0bffc17 ldw r2,-16(fp) + 802cc78: 10800a0b ldhu r2,40(r2) + 802cc7c: 10bfffcc andi r2,r2,65535 + 802cc80: e0bffe15 stw r2,-8(fp) + } + + IN_PROFILER(PF_TCP, PF_ENTRY); /* measure time in TCP */ + + while (len) + 802cc84: 00003b06 br 802cd74 + { + if (len > maxpkt) + 802cc88: e0bff617 ldw r2,-40(fp) + 802cc8c: e0fffe17 ldw r3,-8(fp) + 802cc90: 1880030e bge r3,r2,802cca0 + sendlen = maxpkt; /* take biggest block we can */ + 802cc94: e0bffe17 ldw r2,-8(fp) + 802cc98: e0bff915 stw r2,-28(fp) + 802cc9c: 00000206 br 802cca8 + else + sendlen = len; + 802cca0: e0bff617 ldw r2,-40(fp) + 802cca4: e0bff915 stw r2,-28(fp) + sent = sendlen; + 802cca8: e0bff917 ldw r2,-28(fp) + 802ccac: e0bffb15 stw r2,-20(fp) + + LOCK_NET_RESOURCE(NET_RESID); + 802ccb0: 0009883a mov r4,zero + 802ccb4: 8028f380 call 8028f38 + e = sosend (so, NULL, buf, &sendlen, flags); + 802ccb8: e0fff904 addi r3,fp,-28 + 802ccbc: e0bff517 ldw r2,-44(fp) + 802ccc0: d8800015 stw r2,0(sp) + 802ccc4: 180f883a mov r7,r3 + 802ccc8: e1bff717 ldw r6,-36(fp) + 802cccc: 000b883a mov r5,zero + 802ccd0: e13ffd17 ldw r4,-12(fp) + 802ccd4: 802d9340 call 802d934 + 802ccd8: e0bffa15 stw r2,-24(fp) + UNLOCK_NET_RESOURCE(NET_RESID); + 802ccdc: 0009883a mov r4,zero + 802cce0: 8028ff40 call 8028ff4 + + if (e != 0) /* sock_sendit failed? */ + 802cce4: e0bffa17 ldw r2,-24(fp) + 802cce8: 10001026 beq r2,zero,802cd2c + { + /* if we simply ran out of bufs, report back to caller. */ + if ((e == ENOBUFS) || (e == EWOULDBLOCK)) + 802ccec: e0bffa17 ldw r2,-24(fp) + 802ccf0: 10801a60 cmpeqi r2,r2,105 + 802ccf4: 1000031e bne r2,zero,802cd04 + 802ccf8: e0bffa17 ldw r2,-24(fp) + 802ccfc: 108002d8 cmpnei r2,r2,11 + 802cd00: 1000051e bne r2,zero,802cd18 + /* if we actually sent something before running out + * of buffers, report what we sent; + * else, report the error and let the application + * retry the call later + */ + if (total_sent != 0) + 802cd04: e0bfff17 ldw r2,-4(fp) + 802cd08: 10000326 beq r2,zero,802cd18 + { + so->so_error = 0; + 802cd0c: e0bffd17 ldw r2,-12(fp) + 802cd10: 10000615 stw zero,24(r2) + break; /* break out of while(len) loop */ + 802cd14: 00001b06 br 802cd84 + } + } + so->so_error = e; + 802cd18: e0bffd17 ldw r2,-12(fp) + 802cd1c: e0fffa17 ldw r3,-24(fp) + 802cd20: 10c00615 stw r3,24(r2) + return SOCKET_ERROR; + 802cd24: 00bfffc4 movi r2,-1 + 802cd28: 00001706 br 802cd88 + } + /* if we can't send anymore, return now */ + if (sendlen != 0) + 802cd2c: e0bff917 ldw r2,-28(fp) + 802cd30: 1000131e bne r2,zero,802cd80 + break; /* break out of while(len) loop */ + + /* adjust numbers & pointers, and go do next send loop */ + sent -= sendlen; /* subtract anything that didn't get sent */ + 802cd34: e0bff917 ldw r2,-28(fp) + 802cd38: e0fffb17 ldw r3,-20(fp) + 802cd3c: 1885c83a sub r2,r3,r2 + 802cd40: e0bffb15 stw r2,-20(fp) + buf += sent; + 802cd44: e0bffb17 ldw r2,-20(fp) + 802cd48: e0fff717 ldw r3,-36(fp) + 802cd4c: 1885883a add r2,r3,r2 + 802cd50: e0bff715 stw r2,-36(fp) + len -= sent; + 802cd54: e0fff617 ldw r3,-40(fp) + 802cd58: e0bffb17 ldw r2,-20(fp) + 802cd5c: 1885c83a sub r2,r3,r2 + 802cd60: e0bff615 stw r2,-40(fp) + total_sent += sent; + 802cd64: e0ffff17 ldw r3,-4(fp) + 802cd68: e0bffb17 ldw r2,-20(fp) + 802cd6c: 1885883a add r2,r3,r2 + 802cd70: e0bfff15 stw r2,-4(fp) + while (len) + 802cd74: e0bff617 ldw r2,-40(fp) + 802cd78: 103fc31e bne r2,zero,802cc88 + 802cd7c: 00000106 br 802cd84 + break; /* break out of while(len) loop */ + 802cd80: 0001883a nop + } + + IN_PROFILER(PF_TCP, PF_EXIT); /* measure time in TCP */ + return total_sent; + 802cd84: e0bfff17 ldw r2,-4(fp) +} + 802cd88: e037883a mov sp,fp + 802cd8c: dfc00117 ldw ra,4(sp) + 802cd90: df000017 ldw fp,0(sp) + 802cd94: dec00204 addi sp,sp,8 + 802cd98: f800283a ret + +0802cd9c : + * RETURNS: + */ + +int +t_shutdown(long s, int how) +{ + 802cd9c: defff904 addi sp,sp,-28 + 802cda0: dfc00615 stw ra,24(sp) + 802cda4: df000515 stw fp,20(sp) + 802cda8: df000504 addi fp,sp,20 + 802cdac: e13ffc15 stw r4,-16(fp) + 802cdb0: e17ffb15 stw r5,-20(fp) + struct socket *so; + int err; + + so = LONG2SO(s); + 802cdb4: e0bffc17 ldw r2,-16(fp) + 802cdb8: 10bffc04 addi r2,r2,-16 + 802cdbc: 100490ba slli r2,r2,2 + 802cdc0: e0bffe15 stw r2,-8(fp) + SOC_CHECK(so); + 802cdc4: 008201b4 movhi r2,2054 + 802cdc8: 10b87104 addi r2,r2,-7740 + 802cdcc: e0bfff15 stw r2,-4(fp) + 802cdd0: 00000606 br 802cdec + 802cdd4: e0ffff17 ldw r3,-4(fp) + 802cdd8: e0bffe17 ldw r2,-8(fp) + 802cddc: 18800626 beq r3,r2,802cdf8 + 802cde0: e0bfff17 ldw r2,-4(fp) + 802cde4: 10800017 ldw r2,0(r2) + 802cde8: e0bfff15 stw r2,-4(fp) + 802cdec: e0bfff17 ldw r2,-4(fp) + 802cdf0: 103ff81e bne r2,zero,802cdd4 + 802cdf4: 00000106 br 802cdfc + 802cdf8: 0001883a nop + 802cdfc: e0ffff17 ldw r3,-4(fp) + 802ce00: e0bffe17 ldw r2,-8(fp) + 802ce04: 18800326 beq r3,r2,802ce14 + 802ce08: 8028cd40 call 8028cd4 + 802ce0c: 00bfffc4 movi r2,-1 + 802ce10: 00001206 br 802ce5c + so->so_error = 0; + 802ce14: e0bffe17 ldw r2,-8(fp) + 802ce18: 10000615 stw zero,24(r2) + INET_TRACE (INETM_SOCKET, ("INET:shutdown so %x how %d\n", so, how)); + + LOCK_NET_RESOURCE(NET_RESID); + 802ce1c: 0009883a mov r4,zero + 802ce20: 8028f380 call 8028f38 + err = soshutdown(so, how); + 802ce24: e17ffb17 ldw r5,-20(fp) + 802ce28: e13ffe17 ldw r4,-8(fp) + 802ce2c: 802e5ec0 call 802e5ec + 802ce30: e0bffd15 stw r2,-12(fp) + UNLOCK_NET_RESOURCE(NET_RESID); + 802ce34: 0009883a mov r4,zero + 802ce38: 8028ff40 call 8028ff4 + + if (err != 0) + 802ce3c: e0bffd17 ldw r2,-12(fp) + 802ce40: 10000526 beq r2,zero,802ce58 + { + so->so_error = err; + 802ce44: e0bffe17 ldw r2,-8(fp) + 802ce48: e0fffd17 ldw r3,-12(fp) + 802ce4c: 10c00615 stw r3,24(r2) + return SOCKET_ERROR; + 802ce50: 00bfffc4 movi r2,-1 + 802ce54: 00000106 br 802ce5c + } + return 0; + 802ce58: 0005883a mov r2,zero +} + 802ce5c: e037883a mov sp,fp + 802ce60: dfc00117 ldw ra,4(sp) + 802ce64: df000017 ldw fp,0(sp) + 802ce68: dec00204 addi sp,sp,8 + 802ce6c: f800283a ret + +0802ce70 : + * RETURNS: + */ + +int +t_socketclose(long s) +{ + 802ce70: defffa04 addi sp,sp,-24 + 802ce74: dfc00515 stw ra,20(sp) + 802ce78: df000415 stw fp,16(sp) + 802ce7c: df000404 addi fp,sp,16 + 802ce80: e13ffc15 stw r4,-16(fp) + struct socket * so; + int err; + + so = LONG2SO(s); + 802ce84: e0bffc17 ldw r2,-16(fp) + 802ce88: 10bffc04 addi r2,r2,-16 + 802ce8c: 100490ba slli r2,r2,2 + 802ce90: e0bffe15 stw r2,-8(fp) + SOC_CHECK(so); + 802ce94: 008201b4 movhi r2,2054 + 802ce98: 10b87104 addi r2,r2,-7740 + 802ce9c: e0bfff15 stw r2,-4(fp) + 802cea0: 00000606 br 802cebc + 802cea4: e0ffff17 ldw r3,-4(fp) + 802cea8: e0bffe17 ldw r2,-8(fp) + 802ceac: 18800626 beq r3,r2,802cec8 + 802ceb0: e0bfff17 ldw r2,-4(fp) + 802ceb4: 10800017 ldw r2,0(r2) + 802ceb8: e0bfff15 stw r2,-4(fp) + 802cebc: e0bfff17 ldw r2,-4(fp) + 802cec0: 103ff81e bne r2,zero,802cea4 + 802cec4: 00000106 br 802cecc + 802cec8: 0001883a nop + 802cecc: e0ffff17 ldw r3,-4(fp) + 802ced0: e0bffe17 ldw r2,-8(fp) + 802ced4: 18800326 beq r3,r2,802cee4 + 802ced8: 8028cd40 call 8028cd4 + 802cedc: 00bfffc4 movi r2,-1 + 802cee0: 00000e06 br 802cf1c + so->so_error = 0; + 802cee4: e0bffe17 ldw r2,-8(fp) + 802cee8: 10000615 stw zero,24(r2) + INET_TRACE ((INETM_CLOSE|INETM_SOCKET), ("INET:close, so %lx\n",so)); + + LOCK_NET_RESOURCE(NET_RESID); + 802ceec: 0009883a mov r4,zero + 802cef0: 8028f380 call 8028f38 + err = soclose(so); + 802cef4: e13ffe17 ldw r4,-8(fp) + 802cef8: 802d4340 call 802d434 + 802cefc: e0bffd15 stw r2,-12(fp) + UNLOCK_NET_RESOURCE(NET_RESID); + 802cf00: 0009883a mov r4,zero + 802cf04: 8028ff40 call 8028ff4 + + if (err != 0) + 802cf08: e0bffd17 ldw r2,-12(fp) + 802cf0c: 10000226 beq r2,zero,802cf18 + { + /* do not do the following assignment since the socket structure + addressed by so has been freed by this point, jharan 12-10-98 */ + /* so->so_error = err; */ + return SOCKET_ERROR; + 802cf10: 00bfffc4 movi r2,-1 + 802cf14: 00000106 br 802cf1c + } + return 0; + 802cf18: 0005883a mov r2,zero +} + 802cf1c: e037883a mov sp,fp + 802cf20: dfc00117 ldw ra,4(sp) + 802cf24: df000017 ldw fp,0(sp) + 802cf28: dec00204 addi sp,sp,8 + 802cf2c: f800283a ret + +0802cf30 : + +static struct mbuf * +sockargs (void * arg, + int arglen, + int type) +{ + 802cf30: defffa04 addi sp,sp,-24 + 802cf34: dfc00515 stw ra,20(sp) + 802cf38: df000415 stw fp,16(sp) + 802cf3c: df000404 addi fp,sp,16 + 802cf40: e13ffe15 stw r4,-8(fp) + 802cf44: e17ffd15 stw r5,-12(fp) + 802cf48: e1bffc15 stw r6,-16(fp) + struct mbuf * m; + + LOCK_NET_RESOURCE(NET_RESID); /* protect mfreeq */ + 802cf4c: 0009883a mov r4,zero + 802cf50: 8028f380 call 8028f38 + m = m_getwithdata (type, arglen); + 802cf54: e17ffd17 ldw r5,-12(fp) + 802cf58: e13ffc17 ldw r4,-16(fp) + 802cf5c: 8029a700 call 8029a70 + 802cf60: e0bfff15 stw r2,-4(fp) + UNLOCK_NET_RESOURCE(NET_RESID); + 802cf64: 0009883a mov r4,zero + 802cf68: 8028ff40 call 8028ff4 + if (m == NULL) + 802cf6c: e0bfff17 ldw r2,-4(fp) + 802cf70: 1000021e bne r2,zero,802cf7c + return NULL; + 802cf74: 0005883a mov r2,zero + 802cf78: 00000b06 br 802cfa8 + m->m_len = arglen; + 802cf7c: e0fffd17 ldw r3,-12(fp) + 802cf80: e0bfff17 ldw r2,-4(fp) + 802cf84: 10c00215 stw r3,8(r2) + MEMCPY(mtod (m, char *), arg, arglen); + 802cf88: e0bfff17 ldw r2,-4(fp) + 802cf8c: 10800317 ldw r2,12(r2) + 802cf90: e0fffd17 ldw r3,-12(fp) + 802cf94: 180d883a mov r6,r3 + 802cf98: e17ffe17 ldw r5,-8(fp) + 802cf9c: 1009883a mov r4,r2 + 802cfa0: 80086b80 call 80086b8 + return m; + 802cfa4: e0bfff17 ldw r2,-4(fp) +} + 802cfa8: e037883a mov sp,fp + 802cfac: dfc00117 ldw ra,4(sp) + 802cfb0: df000017 ldw fp,0(sp) + 802cfb4: dec00204 addi sp,sp,8 + 802cfb8: f800283a ret + +0802cfbc : + * ENOTSOCK if socket not found + */ + +int +t_errno(long s) +{ + 802cfbc: defffa04 addi sp,sp,-24 + 802cfc0: dfc00515 stw ra,20(sp) + 802cfc4: df000415 stw fp,16(sp) + 802cfc8: df000404 addi fp,sp,16 + 802cfcc: e13ffc15 stw r4,-16(fp) + struct socket *so = LONG2SO(s); + 802cfd0: e0bffc17 ldw r2,-16(fp) + 802cfd4: 10bffc04 addi r2,r2,-16 + 802cfd8: 100490ba slli r2,r2,2 + 802cfdc: e0bffd15 stw r2,-12(fp) + struct socket *tmp; + int errcode = ENOTSOCK; + 802cfe0: 00801b04 movi r2,108 + 802cfe4: e0bffe15 stw r2,-8(fp) + + LOCK_NET_RESOURCE(NET_RESID); /* protect soq */ + 802cfe8: 0009883a mov r4,zero + 802cfec: 8028f380 call 8028f38 + + /* search socket queue for passed socket. This routine should + * not use SOC_CHECK since it can be ifdeffed out, and we must + * be ready to return EPIPE if the socket does not exist. + */ + for (tmp = (struct socket *)(&soq); tmp; tmp = tmp->next) + 802cff0: 008201b4 movhi r2,2054 + 802cff4: 10b87104 addi r2,r2,-7740 + 802cff8: e0bfff15 stw r2,-4(fp) + 802cffc: 00000a06 br 802d028 + { + if (tmp == so) /* found socket, return error */ + 802d000: e0ffff17 ldw r3,-4(fp) + 802d004: e0bffd17 ldw r2,-12(fp) + 802d008: 1880041e bne r3,r2,802d01c + { + errcode = so->so_error; + 802d00c: e0bffd17 ldw r2,-12(fp) + 802d010: 10800617 ldw r2,24(r2) + 802d014: e0bffe15 stw r2,-8(fp) + break; + 802d018: 00000506 br 802d030 + for (tmp = (struct socket *)(&soq); tmp; tmp = tmp->next) + 802d01c: e0bfff17 ldw r2,-4(fp) + 802d020: 10800017 ldw r2,0(r2) + 802d024: e0bfff15 stw r2,-4(fp) + 802d028: e0bfff17 ldw r2,-4(fp) + 802d02c: 103ff41e bne r2,zero,802d000 + } + } + + UNLOCK_NET_RESOURCE(NET_RESID); + 802d030: 0009883a mov r4,zero + 802d034: 8028ff40 call 8028ff4 + + return errcode; + 802d038: e0bffe17 ldw r2,-8(fp) +} + 802d03c: e037883a mov sp,fp + 802d040: dfc00117 ldw ra,4(sp) + 802d044: df000017 ldw fp,0(sp) + 802d048: dec00204 addi sp,sp,8 + 802d04c: f800283a ret + +0802d050 : + * RETURNS: + */ + +struct socket * +socreate (int dom, int type, int proto) +{ + 802d050: defff704 addi sp,sp,-36 + 802d054: dfc00815 stw ra,32(sp) + 802d058: df000715 stw fp,28(sp) + 802d05c: df000704 addi fp,sp,28 + 802d060: e13ffb15 stw r4,-20(fp) + 802d064: e17ffa15 stw r5,-24(fp) + 802d068: e1bff915 stw r6,-28(fp) + struct protosw *prp; + struct socket *so; + int error; + int rc; + + if (proto) + 802d06c: e0bff917 ldw r2,-28(fp) + 802d070: 10000626 beq r2,zero,802d08c + prp = pffindproto(dom, proto, type); + 802d074: e1bffa17 ldw r6,-24(fp) + 802d078: e17ff917 ldw r5,-28(fp) + 802d07c: e13ffb17 ldw r4,-20(fp) + 802d080: 80299a40 call 80299a4 + 802d084: e0bfff15 stw r2,-4(fp) + 802d088: 00000406 br 802d09c + else + prp = pffindtype(dom, type); + 802d08c: e17ffa17 ldw r5,-24(fp) + 802d090: e13ffb17 ldw r4,-20(fp) + 802d094: 80299140 call 8029914 + 802d098: e0bfff15 stw r2,-4(fp) + if (prp == 0) + 802d09c: e0bfff17 ldw r2,-4(fp) + 802d0a0: 1000021e bne r2,zero,802d0ac + return NULL; + 802d0a4: 0005883a mov r2,zero + 802d0a8: 00004e06 br 802d1e4 + if (prp->pr_type != type) + 802d0ac: e0bfff17 ldw r2,-4(fp) + 802d0b0: 1080000b ldhu r2,0(r2) + 802d0b4: 10bfffcc andi r2,r2,65535 + 802d0b8: 10a0001c xori r2,r2,32768 + 802d0bc: 10a00004 addi r2,r2,-32768 + 802d0c0: e0fffa17 ldw r3,-24(fp) + 802d0c4: 18800226 beq r3,r2,802d0d0 + return NULL; + 802d0c8: 0005883a mov r2,zero + 802d0cc: 00004506 br 802d1e4 + if ((so = SOC_ALLOC (sizeof (*so))) == NULL) + 802d0d0: 01002104 movi r4,132 + 802d0d4: 802982c0 call 802982c + 802d0d8: e0bffe15 stw r2,-8(fp) + 802d0dc: e0bffe17 ldw r2,-8(fp) + 802d0e0: 1000021e bne r2,zero,802d0ec + return NULL; + 802d0e4: 0005883a mov r2,zero + 802d0e8: 00003e06 br 802d1e4 + so->next = NULL; + 802d0ec: e0bffe17 ldw r2,-8(fp) + 802d0f0: 10000015 stw zero,0(r2) + putq(&soq,(qp)so); + 802d0f4: e17ffe17 ldw r5,-8(fp) + 802d0f8: 010201b4 movhi r4,2054 + 802d0fc: 21387104 addi r4,r4,-7740 + 802d100: 80289900 call 8028990 + + so->so_options = socket_defaults; + 802d104: d0a01c0b ldhu r2,-32656(gp) + 802d108: 10ffffcc andi r3,r2,65535 + 802d10c: e0bffe17 ldw r2,-8(fp) + 802d110: 10c00415 stw r3,16(r2) + so->so_domain = dom; + 802d114: e0bffe17 ldw r2,-8(fp) + 802d118: e0fffb17 ldw r3,-20(fp) + 802d11c: 10c00515 stw r3,20(r2) + so->so_state = 0; + 802d120: e0bffe17 ldw r2,-8(fp) + 802d124: 1000088d sth zero,34(r2) + so->so_type = (char)type; + 802d128: e0bffa17 ldw r2,-24(fp) + 802d12c: 1007883a mov r3,r2 + 802d130: e0bffe17 ldw r2,-8(fp) + 802d134: 10c00985 stb r3,38(r2) + so->so_proto = prp; + 802d138: e0bffe17 ldw r2,-8(fp) + 802d13c: e0ffff17 ldw r3,-4(fp) + 802d140: 10c00215 stw r3,8(r2) + +#ifdef IP_MULTICAST + so->inp_moptions = NULL; + 802d144: e0bffe17 ldw r2,-8(fp) + 802d148: 10000315 stw zero,12(r2) +#endif /* IP_MULTICAST */ + + so->so_req = PRU_ATTACH; + 802d14c: e0bffe17 ldw r2,-8(fp) + 802d150: 10000715 stw zero,28(r2) + error = (*prp->pr_usrreq)(so,(struct mbuf *)0, LONG2MBUF((long)proto)); + 802d154: e0bfff17 ldw r2,-4(fp) + 802d158: 10800317 ldw r2,12(r2) + 802d15c: e0fff917 ldw r3,-28(fp) + 802d160: 180d883a mov r6,r3 + 802d164: 000b883a mov r5,zero + 802d168: e13ffe17 ldw r4,-8(fp) + 802d16c: 103ee83a callr r2 + 802d170: e0bffd15 stw r2,-12(fp) + if (error) goto bad; + 802d174: e0bffd17 ldw r2,-12(fp) + 802d178: 10000a1e bne r2,zero,802d1a4 + + if (so_evtmap) + 802d17c: d0a09a03 ldbu r2,-32152(gp) + 802d180: 10803fcc andi r2,r2,255 + 802d184: 10001626 beq r2,zero,802d1e0 + { + rc = (*so_evtmap_create) (so); + 802d188: d0a09817 ldw r2,-32160(gp) + 802d18c: e13ffe17 ldw r4,-8(fp) + 802d190: 103ee83a callr r2 + 802d194: e0bffc15 stw r2,-16(fp) + if (rc != 0) + 802d198: e0bffc17 ldw r2,-16(fp) + 802d19c: 10000c26 beq r2,zero,802d1d0 + { +bad: + 802d1a0: 00000106 br 802d1a8 + if (error) goto bad; + 802d1a4: 0001883a nop + so->so_state |= SS_NOFDREF; + 802d1a8: e0bffe17 ldw r2,-8(fp) + 802d1ac: 1080088b ldhu r2,34(r2) + 802d1b0: 10800054 ori r2,r2,1 + 802d1b4: 1007883a mov r3,r2 + 802d1b8: e0bffe17 ldw r2,-8(fp) + 802d1bc: 10c0088d sth r3,34(r2) + sofree (so); + 802d1c0: e13ffe17 ldw r4,-8(fp) + 802d1c4: 802d3240 call 802d324 + return NULL; + 802d1c8: 0005883a mov r2,zero + 802d1cc: 00000506 br 802d1e4 + /* + * Altera Niche Stack Nios port modification: + * Remove (void *) cast since -> owner is now TK_OBJECT + * to fix build warning. + */ + so->owner = TK_THIS; + 802d1d0: 8027c780 call 8027c78 + 802d1d4: 1007883a mov r3,r2 + 802d1d8: e0bffe17 ldw r2,-8(fp) + 802d1dc: 10c02005 stb r3,128(r2) + } + + return so; + 802d1e0: e0bffe17 ldw r2,-8(fp) +} + 802d1e4: e037883a mov sp,fp + 802d1e8: dfc00117 ldw ra,4(sp) + 802d1ec: df000017 ldw fp,0(sp) + 802d1f0: dec00204 addi sp,sp,8 + 802d1f4: f800283a ret + +0802d1f8 : + */ + +int +sobind(struct socket * so, + struct mbuf * nam) +{ + 802d1f8: defffb04 addi sp,sp,-20 + 802d1fc: dfc00415 stw ra,16(sp) + 802d200: df000315 stw fp,12(sp) + 802d204: df000304 addi fp,sp,12 + 802d208: e13ffe15 stw r4,-8(fp) + 802d20c: e17ffd15 stw r5,-12(fp) + int error; + + so->so_req = PRU_BIND; + 802d210: e0bffe17 ldw r2,-8(fp) + 802d214: 00c00084 movi r3,2 + 802d218: 10c00715 stw r3,28(r2) + error = (*so->so_proto->pr_usrreq)(so, (struct mbuf *)0, nam); + 802d21c: e0bffe17 ldw r2,-8(fp) + 802d220: 10800217 ldw r2,8(r2) + 802d224: 10800317 ldw r2,12(r2) + 802d228: e1bffd17 ldw r6,-12(fp) + 802d22c: 000b883a mov r5,zero + 802d230: e13ffe17 ldw r4,-8(fp) + 802d234: 103ee83a callr r2 + 802d238: e0bfff15 stw r2,-4(fp) + return (error); + 802d23c: e0bfff17 ldw r2,-4(fp) +} + 802d240: e037883a mov sp,fp + 802d244: dfc00117 ldw ra,4(sp) + 802d248: df000017 ldw fp,0(sp) + 802d24c: dec00204 addi sp,sp,8 + 802d250: f800283a ret + +0802d254 : + */ + +int +solisten(struct socket * so, + int backlog) +{ + 802d254: defffb04 addi sp,sp,-20 + 802d258: dfc00415 stw ra,16(sp) + 802d25c: df000315 stw fp,12(sp) + 802d260: df000304 addi fp,sp,12 + 802d264: e13ffe15 stw r4,-8(fp) + 802d268: e17ffd15 stw r5,-12(fp) + int error; + + so->so_req = PRU_LISTEN; + 802d26c: e0bffe17 ldw r2,-8(fp) + 802d270: 00c000c4 movi r3,3 + 802d274: 10c00715 stw r3,28(r2) + error = (*so->so_proto->pr_usrreq)(so, + 802d278: e0bffe17 ldw r2,-8(fp) + 802d27c: 10800217 ldw r2,8(r2) + 802d280: 10800317 ldw r2,12(r2) + 802d284: 000d883a mov r6,zero + 802d288: 000b883a mov r5,zero + 802d28c: e13ffe17 ldw r4,-8(fp) + 802d290: 103ee83a callr r2 + 802d294: e0bfff15 stw r2,-4(fp) + (struct mbuf *)0, (struct mbuf *)0); + if (error) + 802d298: e0bfff17 ldw r2,-4(fp) + 802d29c: 10000226 beq r2,zero,802d2a8 + { + return (error); + 802d2a0: e0bfff17 ldw r2,-4(fp) + 802d2a4: 00001a06 br 802d310 + } + if (so->so_q == 0) + 802d2a8: e0bffe17 ldw r2,-8(fp) + 802d2ac: 10801d17 ldw r2,116(r2) + 802d2b0: 10000b1e bne r2,zero,802d2e0 + { + so->so_q = so; + 802d2b4: e0bffe17 ldw r2,-8(fp) + 802d2b8: e0fffe17 ldw r3,-8(fp) + 802d2bc: 10c01d15 stw r3,116(r2) + so->so_q0 = so; + 802d2c0: e0bffe17 ldw r2,-8(fp) + 802d2c4: e0fffe17 ldw r3,-8(fp) + 802d2c8: 10c01c15 stw r3,112(r2) + so->so_options |= SO_ACCEPTCONN; + 802d2cc: e0bffe17 ldw r2,-8(fp) + 802d2d0: 10800417 ldw r2,16(r2) + 802d2d4: 10c00094 ori r3,r2,2 + 802d2d8: e0bffe17 ldw r2,-8(fp) + 802d2dc: 10c00415 stw r3,16(r2) + } + if (backlog < 0) + 802d2e0: e0bffd17 ldw r2,-12(fp) + 802d2e4: 1000010e bge r2,zero,802d2ec + backlog = 0; + 802d2e8: e03ffd15 stw zero,-12(fp) + so->so_qlimit = (char)MIN(backlog, SOMAXCONN); + 802d2ec: e0bffd17 ldw r2,-12(fp) + 802d2f0: 10800188 cmpgei r2,r2,6 + 802d2f4: 1000021e bne r2,zero,802d300 + 802d2f8: e0bffd17 ldw r2,-12(fp) + 802d2fc: 00000106 br 802d304 + 802d300: 00800144 movi r2,5 + 802d304: e0fffe17 ldw r3,-8(fp) + 802d308: 18801e85 stb r2,122(r3) + return 0; + 802d30c: 0005883a mov r2,zero +} + 802d310: e037883a mov sp,fp + 802d314: dfc00117 ldw ra,4(sp) + 802d318: df000017 ldw fp,0(sp) + 802d31c: dec00204 addi sp,sp,8 + 802d320: f800283a ret + +0802d324 : + * RETURNS: + */ + +void +sofree(struct socket * so) +{ + 802d324: defffd04 addi sp,sp,-12 + 802d328: dfc00215 stw ra,8(sp) + 802d32c: df000115 stw fp,4(sp) + 802d330: df000104 addi fp,sp,4 + 802d334: e13fff15 stw r4,-4(fp) + INET_TRACE (INETM_SOCKET|INETM_CLOSE, + ("INET: sofree, so %lx so_pcb %lx so_state %x so_head %lx\n", + so, so->so_pcb, so->so_state, so->so_head)); + + if (so->so_pcb || (so->so_state & SS_NOFDREF) == 0) + 802d338: e0bfff17 ldw r2,-4(fp) + 802d33c: 10800117 ldw r2,4(r2) + 802d340: 1000361e bne r2,zero,802d41c + 802d344: e0bfff17 ldw r2,-4(fp) + 802d348: 1080088b ldhu r2,34(r2) + 802d34c: 10bfffcc andi r2,r2,65535 + 802d350: 1080004c andi r2,r2,1 + 802d354: 10003126 beq r2,zero,802d41c + return; + if (so->so_head) + 802d358: e0bfff17 ldw r2,-4(fp) + 802d35c: 10801b17 ldw r2,108(r2) + 802d360: 10000d26 beq r2,zero,802d398 + { + if (!soqremque(so, 0) && !soqremque(so, 1)) + 802d364: 000b883a mov r5,zero + 802d368: e13fff17 ldw r4,-4(fp) + 802d36c: 802f6ec0 call 802f6ec + 802d370: 1000071e bne r2,zero,802d390 + 802d374: 01400044 movi r5,1 + 802d378: e13fff17 ldw r4,-4(fp) + 802d37c: 802f6ec0 call 802f6ec + 802d380: 1000031e bne r2,zero,802d390 + panic("sofree"); + 802d384: 01020174 movhi r4,2053 + 802d388: 212a7604 addi r4,r4,-22056 + 802d38c: 80271780 call 8027178 + so->so_head = 0; + 802d390: e0bfff17 ldw r2,-4(fp) + 802d394: 10001b15 stw zero,108(r2) + } + sbrelease(&so->so_snd); + 802d398: e0bfff17 ldw r2,-4(fp) + 802d39c: 10801204 addi r2,r2,72 + 802d3a0: 1009883a mov r4,r2 + 802d3a4: 802fab00 call 802fab0 + sorflush(so); + 802d3a8: e13fff17 ldw r4,-4(fp) + 802d3ac: 802e6840 call 802e684 + _socket_free_entry (so); +#endif /* SAVE_SOCK_ENDPOINTS */ + +#ifdef IP_MULTICAST + /* multicast opts? */ + if (so->inp_moptions) + 802d3b0: e0bfff17 ldw r2,-4(fp) + 802d3b4: 10800317 ldw r2,12(r2) + 802d3b8: 10000426 beq r2,zero,802d3cc + ip_freemoptions(so->inp_moptions); + 802d3bc: e0bfff17 ldw r2,-4(fp) + 802d3c0: 10800317 ldw r2,12(r2) + 802d3c4: 1009883a mov r4,r2 + 802d3c8: 803ee740 call 803ee74 +#endif /* IP_MULTICAST */ + + /* IP_TOS opts? */ + if (so->so_optsPack) + 802d3cc: e0bfff17 ldw r2,-4(fp) + 802d3d0: 10801f17 ldw r2,124(r2) + 802d3d4: 10000426 beq r2,zero,802d3e8 + SOCOPT_FREE(so->so_optsPack); + 802d3d8: e0bfff17 ldw r2,-4(fp) + 802d3dc: 10801f17 ldw r2,124(r2) + 802d3e0: 1009883a mov r4,r2 + 802d3e4: 80298600 call 8029860 + + qdel(&soq, so); /* Delete the socket entry from the queue */ + 802d3e8: e17fff17 ldw r5,-4(fp) + 802d3ec: 010201b4 movhi r4,2054 + 802d3f0: 21387104 addi r4,r4,-7740 + 802d3f4: 8028a400 call 8028a40 + + if (so_evtmap) + 802d3f8: d0a09a03 ldbu r2,-32152(gp) + 802d3fc: 10803fcc andi r2,r2,255 + 802d400: 10000326 beq r2,zero,802d410 + (*so_evtmap_delete) (so); + 802d404: d0a09917 ldw r2,-32156(gp) + 802d408: e13fff17 ldw r4,-4(fp) + 802d40c: 103ee83a callr r2 + + SOC_FREE(so); + 802d410: e13fff17 ldw r4,-4(fp) + 802d414: 80298600 call 8029860 + 802d418: 00000106 br 802d420 + return; + 802d41c: 0001883a nop +} + 802d420: e037883a mov sp,fp + 802d424: dfc00117 ldw ra,4(sp) + 802d428: df000017 ldw fp,0(sp) + 802d42c: dec00204 addi sp,sp,8 + 802d430: f800283a ret + +0802d434 : + * RETURNS: + */ + +int +soclose(struct socket * so) +{ + 802d434: defff904 addi sp,sp,-28 + 802d438: dfc00615 stw ra,24(sp) + 802d43c: df000515 stw fp,20(sp) + 802d440: df000504 addi fp,sp,20 + 802d444: e13ffb15 stw r4,-20(fp) + int error = 0; + 802d448: e03fff15 stw zero,-4(fp) + unsigned long endtime; + + /* Check whether the closing socket is in the socket queue. If it is + * not, return a EINVAL error code to the caller. + */ + for ((tmpso=(struct socket *)soq.q_head);tmpso != NULL;tmpso=tmpso->next) + 802d44c: 008201b4 movhi r2,2054 + 802d450: 10b87117 ldw r2,-7740(r2) + 802d454: e0bffe15 stw r2,-8(fp) + 802d458: 00000606 br 802d474 + { + if (so == tmpso) + 802d45c: e0fffb17 ldw r3,-20(fp) + 802d460: e0bffe17 ldw r2,-8(fp) + 802d464: 18800626 beq r3,r2,802d480 + for ((tmpso=(struct socket *)soq.q_head);tmpso != NULL;tmpso=tmpso->next) + 802d468: e0bffe17 ldw r2,-8(fp) + 802d46c: 10800017 ldw r2,0(r2) + 802d470: e0bffe15 stw r2,-8(fp) + 802d474: e0bffe17 ldw r2,-8(fp) + 802d478: 103ff81e bne r2,zero,802d45c + 802d47c: 00000106 br 802d484 + break; + 802d480: 0001883a nop + } + if ( tmpso == NULL) + 802d484: e0bffe17 ldw r2,-8(fp) + 802d488: 1000021e bne r2,zero,802d494 + return EINVAL; + 802d48c: 00800584 movi r2,22 + 802d490: 00009506 br 802d6e8 + INET_TRACE (INETM_SOCKET|INETM_CLOSE, + ("INET: soclose, so %lx so_pcb %lx so_state %x so_q %lx\n", + so, so->so_pcb, so->so_state, so->so_q)); + if (so->so_options & SO_ACCEPTCONN) + 802d494: e0bffb17 ldw r2,-20(fp) + 802d498: 10800417 ldw r2,16(r2) + 802d49c: 1080008c andi r2,r2,2 + 802d4a0: 10001226 beq r2,zero,802d4ec + { + while (so->so_q0 != so) + 802d4a4: 00000406 br 802d4b8 + (void) soabort(so->so_q0); + 802d4a8: e0bffb17 ldw r2,-20(fp) + 802d4ac: 10801c17 ldw r2,112(r2) + 802d4b0: 1009883a mov r4,r2 + 802d4b4: 802d6fc0 call 802d6fc + while (so->so_q0 != so) + 802d4b8: e0bffb17 ldw r2,-20(fp) + 802d4bc: 10801c17 ldw r2,112(r2) + 802d4c0: e0fffb17 ldw r3,-20(fp) + 802d4c4: 18bff81e bne r3,r2,802d4a8 + while (so->so_q != so) + 802d4c8: 00000406 br 802d4dc + (void) soabort(so->so_q); + 802d4cc: e0bffb17 ldw r2,-20(fp) + 802d4d0: 10801d17 ldw r2,116(r2) + 802d4d4: 1009883a mov r4,r2 + 802d4d8: 802d6fc0 call 802d6fc + while (so->so_q != so) + 802d4dc: e0bffb17 ldw r2,-20(fp) + 802d4e0: 10801d17 ldw r2,116(r2) + 802d4e4: e0fffb17 ldw r3,-20(fp) + 802d4e8: 18bff81e bne r3,r2,802d4cc + } + /* for datagram-oriented sockets, dispense with further tests */ + if (so->so_type != SOCK_STREAM) + 802d4ec: e0bffb17 ldw r2,-20(fp) + 802d4f0: 10800983 ldbu r2,38(r2) + 802d4f4: 10803fcc andi r2,r2,255 + 802d4f8: 1080201c xori r2,r2,128 + 802d4fc: 10bfe004 addi r2,r2,-128 + 802d500: 10800060 cmpeqi r2,r2,1 + 802d504: 10000c1e bne r2,zero,802d538 + { + so->so_req = PRU_DETACH; + 802d508: e0bffb17 ldw r2,-20(fp) + 802d50c: 00c00044 movi r3,1 + 802d510: 10c00715 stw r3,28(r2) + error = (*so->so_proto->pr_usrreq)(so, + 802d514: e0bffb17 ldw r2,-20(fp) + 802d518: 10800217 ldw r2,8(r2) + 802d51c: 10800317 ldw r2,12(r2) + 802d520: 000d883a mov r6,zero + 802d524: 000b883a mov r5,zero + 802d528: e13ffb17 ldw r4,-20(fp) + 802d52c: 103ee83a callr r2 + 802d530: e0bfff15 stw r2,-4(fp) + (struct mbuf *)0, (struct mbuf *)0); + goto discard; + 802d534: 00005d06 br 802d6ac + } + + if (so->so_pcb == 0) + 802d538: e0bffb17 ldw r2,-20(fp) + 802d53c: 10800117 ldw r2,4(r2) + 802d540: 10005726 beq r2,zero,802d6a0 + goto discard; + if (so->so_state & SS_ISCONNECTED) + 802d544: e0bffb17 ldw r2,-20(fp) + 802d548: 1080088b ldhu r2,34(r2) + 802d54c: 10bfffcc andi r2,r2,65535 + 802d550: 1080008c andi r2,r2,2 + 802d554: 10003a26 beq r2,zero,802d640 + { + if ((so->so_state & SS_ISDISCONNECTING) == 0) + 802d558: e0bffb17 ldw r2,-20(fp) + 802d55c: 1080088b ldhu r2,34(r2) + 802d560: 10bfffcc andi r2,r2,65535 + 802d564: 1080020c andi r2,r2,8 + 802d568: 1000051e bne r2,zero,802d580 + { + error = sodisconnect(so); + 802d56c: e13ffb17 ldw r4,-20(fp) + 802d570: 802d89c0 call 802d89c + 802d574: e0bfff15 stw r2,-4(fp) + if (error) + 802d578: e0bfff17 ldw r2,-4(fp) + 802d57c: 1000321e bne r2,zero,802d648 + goto drop; + } + if (so->so_options & SO_LINGER) + 802d580: e0bffb17 ldw r2,-20(fp) + 802d584: 10800417 ldw r2,16(r2) + 802d588: 1080200c andi r2,r2,128 + 802d58c: 10002126 beq r2,zero,802d614 + { + if ((so->so_state & SS_ISDISCONNECTING) && + 802d590: e0bffb17 ldw r2,-20(fp) + 802d594: 1080088b ldhu r2,34(r2) + 802d598: 10bfffcc andi r2,r2,65535 + 802d59c: 1080020c andi r2,r2,8 + 802d5a0: 10000526 beq r2,zero,802d5b8 + (so->so_state & SS_NBIO)) + 802d5a4: e0bffb17 ldw r2,-20(fp) + 802d5a8: 1080088b ldhu r2,34(r2) + 802d5ac: 10bfffcc andi r2,r2,65535 + 802d5b0: 1080400c andi r2,r2,256 + if ((so->so_state & SS_ISDISCONNECTING) && + 802d5b4: 1000261e bne r2,zero,802d650 + { + goto drop; + } + endtime = cticks + (unsigned long)so->so_linger * TPS; + 802d5b8: e0bffb17 ldw r2,-20(fp) + 802d5bc: 1080080b ldhu r2,32(r2) + 802d5c0: 10bfffcc andi r2,r2,65535 + 802d5c4: 10a0001c xori r2,r2,32768 + 802d5c8: 10a00004 addi r2,r2,-32768 + 802d5cc: 10c01924 muli r3,r2,100 + 802d5d0: d0a07d17 ldw r2,-32268(gp) + 802d5d4: 1885883a add r2,r3,r2 + 802d5d8: e0bffd15 stw r2,-12(fp) + while ((so->so_state & SS_ISCONNECTED) && (cticks < endtime)) + 802d5dc: 00000406 br 802d5f0 + { + tcp_sleep((char *)&so->so_timeo); + 802d5e0: e0bffb17 ldw r2,-20(fp) + 802d5e4: 10800904 addi r2,r2,36 + 802d5e8: 1009883a mov r4,r2 + 802d5ec: 8027a540 call 8027a54 + while ((so->so_state & SS_ISCONNECTED) && (cticks < endtime)) + 802d5f0: e0bffb17 ldw r2,-20(fp) + 802d5f4: 1080088b ldhu r2,34(r2) + 802d5f8: 10bfffcc andi r2,r2,65535 + 802d5fc: 1080008c andi r2,r2,2 + 802d600: 10001426 beq r2,zero,802d654 + 802d604: d0e07d17 ldw r3,-32268(gp) + 802d608: e0bffd17 ldw r2,-12(fp) + 802d60c: 18bff436 bltu r3,r2,802d5e0 + 802d610: 00001006 br 802d654 + { + /* If socket still has send data just return now, leaving the + * socket intact so the data can be sent. Socket should be cleaned + * up later by timers. + */ + if(so->so_snd.sb_cc) + 802d614: e0bffb17 ldw r2,-20(fp) + 802d618: 10801217 ldw r2,72(r2) + 802d61c: 10000826 beq r2,zero,802d640 + { + so->so_state |= SS_NOFDREF; /* mark as OK to close */ + 802d620: e0bffb17 ldw r2,-20(fp) + 802d624: 1080088b ldhu r2,34(r2) + 802d628: 10800054 ori r2,r2,1 + 802d62c: 1007883a mov r3,r2 + 802d630: e0bffb17 ldw r2,-20(fp) + 802d634: 10c0088d sth r3,34(r2) + return 0; + 802d638: 0005883a mov r2,zero + 802d63c: 00002a06 br 802d6e8 + } + } + } +drop: + 802d640: 0001883a nop + 802d644: 00000306 br 802d654 + goto drop; + 802d648: 0001883a nop + 802d64c: 00000106 br 802d654 + goto drop; + 802d650: 0001883a nop + if (so->so_pcb) + 802d654: e0bffb17 ldw r2,-20(fp) + 802d658: 10800117 ldw r2,4(r2) + 802d65c: 10001226 beq r2,zero,802d6a8 + { + int error2; + so->so_req = PRU_DETACH; + 802d660: e0bffb17 ldw r2,-20(fp) + 802d664: 00c00044 movi r3,1 + 802d668: 10c00715 stw r3,28(r2) + error2 = (*so->so_proto->pr_usrreq)(so, + 802d66c: e0bffb17 ldw r2,-20(fp) + 802d670: 10800217 ldw r2,8(r2) + 802d674: 10800317 ldw r2,12(r2) + 802d678: 000d883a mov r6,zero + 802d67c: 000b883a mov r5,zero + 802d680: e13ffb17 ldw r4,-20(fp) + 802d684: 103ee83a callr r2 + 802d688: e0bffc15 stw r2,-16(fp) + (struct mbuf *)0, (struct mbuf *)0); + if (error == 0) + 802d68c: e0bfff17 ldw r2,-4(fp) + 802d690: 1000051e bne r2,zero,802d6a8 + error = error2; + 802d694: e0bffc17 ldw r2,-16(fp) + 802d698: e0bfff15 stw r2,-4(fp) + 802d69c: 00000306 br 802d6ac + goto discard; + 802d6a0: 0001883a nop + 802d6a4: 00000106 br 802d6ac + } +discard: + 802d6a8: 0001883a nop + if (so->so_state & SS_NOFDREF) + 802d6ac: e0bffb17 ldw r2,-20(fp) + 802d6b0: 1080088b ldhu r2,34(r2) + 802d6b4: 10bfffcc andi r2,r2,65535 + 802d6b8: 1080004c andi r2,r2,1 + 802d6bc: 10000126 beq r2,zero,802d6c4 + { + /* panic("soclose"); - non-fatal - degrade to dtrap() for now */ + dtrap(); + 802d6c0: 8028cd40 call 8028cd4 + } + so->so_state |= SS_NOFDREF; + 802d6c4: e0bffb17 ldw r2,-20(fp) + 802d6c8: 1080088b ldhu r2,34(r2) + 802d6cc: 10800054 ori r2,r2,1 + 802d6d0: 1007883a mov r3,r2 + 802d6d4: e0bffb17 ldw r2,-20(fp) + 802d6d8: 10c0088d sth r3,34(r2) + sofree(so); + 802d6dc: e13ffb17 ldw r4,-20(fp) + 802d6e0: 802d3240 call 802d324 + return (error); + 802d6e4: e0bfff17 ldw r2,-4(fp) +} + 802d6e8: e037883a mov sp,fp + 802d6ec: dfc00117 ldw ra,4(sp) + 802d6f0: df000017 ldw fp,0(sp) + 802d6f4: dec00204 addi sp,sp,8 + 802d6f8: f800283a ret + +0802d6fc : + * RETURNS: + */ + +int +soabort(struct socket * so) +{ + 802d6fc: defffd04 addi sp,sp,-12 + 802d700: dfc00215 stw ra,8(sp) + 802d704: df000115 stw fp,4(sp) + 802d708: df000104 addi fp,sp,4 + 802d70c: e13fff15 stw r4,-4(fp) + so->so_req = PRU_ABORT; + 802d710: e0bfff17 ldw r2,-4(fp) + 802d714: 00c00284 movi r3,10 + 802d718: 10c00715 stw r3,28(r2) + return(*so->so_proto->pr_usrreq)(so, (struct mbuf *)0, (struct mbuf *)0); + 802d71c: e0bfff17 ldw r2,-4(fp) + 802d720: 10800217 ldw r2,8(r2) + 802d724: 10800317 ldw r2,12(r2) + 802d728: 000d883a mov r6,zero + 802d72c: 000b883a mov r5,zero + 802d730: e13fff17 ldw r4,-4(fp) + 802d734: 103ee83a callr r2 +} + 802d738: e037883a mov sp,fp + 802d73c: dfc00117 ldw ra,4(sp) + 802d740: df000017 ldw fp,0(sp) + 802d744: dec00204 addi sp,sp,8 + 802d748: f800283a ret + +0802d74c : + */ + +int +soaccept(struct socket * so, + struct mbuf * nam) +{ + 802d74c: defffb04 addi sp,sp,-20 + 802d750: dfc00415 stw ra,16(sp) + 802d754: df000315 stw fp,12(sp) + 802d758: df000304 addi fp,sp,12 + 802d75c: e13ffe15 stw r4,-8(fp) + 802d760: e17ffd15 stw r5,-12(fp) + int error; + + if ((so->so_state & SS_NOFDREF) == 0) + 802d764: e0bffe17 ldw r2,-8(fp) + 802d768: 1080088b ldhu r2,34(r2) + 802d76c: 10bfffcc andi r2,r2,65535 + 802d770: 1080004c andi r2,r2,1 + 802d774: 1000031e bne r2,zero,802d784 + panic("soaccept"); + 802d778: 01020174 movhi r4,2053 + 802d77c: 212a7804 addi r4,r4,-22048 + 802d780: 80271780 call 8027178 + so->so_state &= ~SS_NOFDREF; + 802d784: e0bffe17 ldw r2,-8(fp) + 802d788: 10c0088b ldhu r3,34(r2) + 802d78c: 00bfff84 movi r2,-2 + 802d790: 1884703a and r2,r3,r2 + 802d794: 1007883a mov r3,r2 + 802d798: e0bffe17 ldw r2,-8(fp) + 802d79c: 10c0088d sth r3,34(r2) + so->so_req = PRU_ACCEPT; + 802d7a0: e0bffe17 ldw r2,-8(fp) + 802d7a4: 00c00144 movi r3,5 + 802d7a8: 10c00715 stw r3,28(r2) + error = (*so->so_proto->pr_usrreq)(so, (struct mbuf *)0, nam); + 802d7ac: e0bffe17 ldw r2,-8(fp) + 802d7b0: 10800217 ldw r2,8(r2) + 802d7b4: 10800317 ldw r2,12(r2) + 802d7b8: e1bffd17 ldw r6,-12(fp) + 802d7bc: 000b883a mov r5,zero + 802d7c0: e13ffe17 ldw r4,-8(fp) + 802d7c4: 103ee83a callr r2 + 802d7c8: e0bfff15 stw r2,-4(fp) + + return (error); + 802d7cc: e0bfff17 ldw r2,-4(fp) +} + 802d7d0: e037883a mov sp,fp + 802d7d4: dfc00117 ldw ra,4(sp) + 802d7d8: df000017 ldw fp,0(sp) + 802d7dc: dec00204 addi sp,sp,8 + 802d7e0: f800283a ret + +0802d7e4 : + */ + +int +soconnect(struct socket * so, + struct mbuf * nam) +{ + 802d7e4: defffb04 addi sp,sp,-20 + 802d7e8: dfc00415 stw ra,16(sp) + 802d7ec: df000315 stw fp,12(sp) + 802d7f0: df000304 addi fp,sp,12 + 802d7f4: e13ffe15 stw r4,-8(fp) + 802d7f8: e17ffd15 stw r5,-12(fp) + int error; + + if (so->so_options & SO_ACCEPTCONN) + 802d7fc: e0bffe17 ldw r2,-8(fp) + 802d800: 10800417 ldw r2,16(r2) + 802d804: 1080008c andi r2,r2,2 + 802d808: 10000226 beq r2,zero,802d814 + return (EOPNOTSUPP); + 802d80c: 008017c4 movi r2,95 + 802d810: 00001d06 br 802d888 + * If protocol is connection-based, can only connect once. + * Otherwise, if connected, try to disconnect first. + * This allows user to disconnect by connecting to, e.g., + * a null address. + */ + if (so->so_state & (SS_ISCONNECTED|SS_ISCONNECTING) && + 802d814: e0bffe17 ldw r2,-8(fp) + 802d818: 1080088b ldhu r2,34(r2) + 802d81c: 10bfffcc andi r2,r2,65535 + 802d820: 1080018c andi r2,r2,6 + 802d824: 10000c26 beq r2,zero,802d858 + ((so->so_proto->pr_flags & PR_CONNREQUIRED) || + 802d828: e0bffe17 ldw r2,-8(fp) + 802d82c: 10800217 ldw r2,8(r2) + 802d830: 1080010b ldhu r2,4(r2) + 802d834: 10bfffcc andi r2,r2,65535 + 802d838: 1080010c andi r2,r2,4 + if (so->so_state & (SS_ISCONNECTED|SS_ISCONNECTING) && + 802d83c: 1000031e bne r2,zero,802d84c + (sodisconnect(so) != 0))) + 802d840: e13ffe17 ldw r4,-8(fp) + 802d844: 802d89c0 call 802d89c + ((so->so_proto->pr_flags & PR_CONNREQUIRED) || + 802d848: 10000326 beq r2,zero,802d858 + { + error = EISCONN; + 802d84c: 00801fc4 movi r2,127 + 802d850: e0bfff15 stw r2,-4(fp) + 802d854: 00000b06 br 802d884 + } + else + { + so->so_req = PRU_CONNECT; + 802d858: e0bffe17 ldw r2,-8(fp) + 802d85c: 00c00104 movi r3,4 + 802d860: 10c00715 stw r3,28(r2) + error = (*so->so_proto->pr_usrreq)(so, (struct mbuf *)0, nam); + 802d864: e0bffe17 ldw r2,-8(fp) + 802d868: 10800217 ldw r2,8(r2) + 802d86c: 10800317 ldw r2,12(r2) + 802d870: e1bffd17 ldw r6,-12(fp) + 802d874: 000b883a mov r5,zero + 802d878: e13ffe17 ldw r4,-8(fp) + 802d87c: 103ee83a callr r2 + 802d880: e0bfff15 stw r2,-4(fp) + } + return error; + 802d884: e0bfff17 ldw r2,-4(fp) +} + 802d888: e037883a mov sp,fp + 802d88c: dfc00117 ldw ra,4(sp) + 802d890: df000017 ldw fp,0(sp) + 802d894: dec00204 addi sp,sp,8 + 802d898: f800283a ret + +0802d89c : + * RETURNS: + */ + +int +sodisconnect(struct socket * so) +{ + 802d89c: defffc04 addi sp,sp,-16 + 802d8a0: dfc00315 stw ra,12(sp) + 802d8a4: df000215 stw fp,8(sp) + 802d8a8: df000204 addi fp,sp,8 + 802d8ac: e13ffe15 stw r4,-8(fp) + int error; + + INET_TRACE (INETM_SOCKET|INETM_CLOSE, + ("INET: sodisconnect, so %lx so_state %x\n", so, so->so_state)); + + if ((so->so_state & SS_ISCONNECTED) == 0) + 802d8b0: e0bffe17 ldw r2,-8(fp) + 802d8b4: 1080088b ldhu r2,34(r2) + 802d8b8: 10bfffcc andi r2,r2,65535 + 802d8bc: 1080008c andi r2,r2,2 + 802d8c0: 1000031e bne r2,zero,802d8d0 + { + error = ENOTCONN; + 802d8c4: 00802004 movi r2,128 + 802d8c8: e0bfff15 stw r2,-4(fp) + goto bad; + 802d8cc: 00001306 br 802d91c + } + if (so->so_state & SS_ISDISCONNECTING) + 802d8d0: e0bffe17 ldw r2,-8(fp) + 802d8d4: 1080088b ldhu r2,34(r2) + 802d8d8: 10bfffcc andi r2,r2,65535 + 802d8dc: 1080020c andi r2,r2,8 + 802d8e0: 10000326 beq r2,zero,802d8f0 + { + error = EALREADY; + 802d8e4: 00801e04 movi r2,120 + 802d8e8: e0bfff15 stw r2,-4(fp) + goto bad; + 802d8ec: 00000b06 br 802d91c + } + so->so_req = PRU_DISCONNECT; + 802d8f0: e0bffe17 ldw r2,-8(fp) + 802d8f4: 00c00184 movi r3,6 + 802d8f8: 10c00715 stw r3,28(r2) + error = (*so->so_proto->pr_usrreq)(so, (struct mbuf *)0, (struct mbuf *)0); + 802d8fc: e0bffe17 ldw r2,-8(fp) + 802d900: 10800217 ldw r2,8(r2) + 802d904: 10800317 ldw r2,12(r2) + 802d908: 000d883a mov r6,zero + 802d90c: 000b883a mov r5,zero + 802d910: e13ffe17 ldw r4,-8(fp) + 802d914: 103ee83a callr r2 + 802d918: e0bfff15 stw r2,-4(fp) + +bad: + return (error); + 802d91c: e0bfff17 ldw r2,-4(fp) +} + 802d920: e037883a mov sp,fp + 802d924: dfc00117 ldw ra,4(sp) + 802d928: df000017 ldw fp,0(sp) + 802d92c: dec00204 addi sp,sp,8 + 802d930: f800283a ret + +0802d934 : +sosend(struct socket *so, + struct mbuf *nam, /* sockaddr, if UDP socket, NULL if TCP */ + char *data, /* data to send */ + int *data_length, /* IN/OUT length of (remaining) data */ + int flags) +{ + 802d934: defff204 addi sp,sp,-56 + 802d938: dfc00d15 stw ra,52(sp) + 802d93c: df000c15 stw fp,48(sp) + 802d940: df000c04 addi fp,sp,48 + 802d944: e13ff715 stw r4,-36(fp) + 802d948: e17ff615 stw r5,-40(fp) + 802d94c: e1bff515 stw r6,-44(fp) + 802d950: e1fff415 stw r7,-48(fp) + struct mbuf *head = (struct mbuf *)NULL; + 802d954: e03fff15 stw zero,-4(fp) + struct mbuf *m; + int space; + int resid; + int len; + int error = 0; + 802d958: e03ffb15 stw zero,-20(fp) + int dontroute; + int first = 1; + 802d95c: 00800044 movi r2,1 + 802d960: e0bffa15 stw r2,-24(fp) + + resid = *data_length; + 802d964: e0bff417 ldw r2,-48(fp) + 802d968: 10800017 ldw r2,0(r2) + 802d96c: e0bffc15 stw r2,-16(fp) + * However, space must be signed, as it might be less than 0 + * if we over-committed, and we must use a signed comparison + * of space and resid. On the other hand, a negative resid + * causes us to loop sending 0-length segments to the protocol. + */ + if (resid < 0) + 802d970: e0bffc17 ldw r2,-16(fp) + 802d974: 1000020e bge r2,zero,802d980 + return (EINVAL); + 802d978: 00800584 movi r2,22 + 802d97c: 00014006 br 802de80 + + INET_TRACE (INETM_IO, ("INET:sosend: so %lx resid %d sb_hiwat %d so_state %x\n", + so, resid, so->so_snd.sb_hiwat, so->so_state)); + + if (sosendallatonce(so) && (resid > (int)so->so_snd.sb_hiwat)) + 802d980: e0bff717 ldw r2,-36(fp) + 802d984: 10800217 ldw r2,8(r2) + 802d988: 1080010b ldhu r2,4(r2) + 802d98c: 10bfffcc andi r2,r2,65535 + 802d990: 1080004c andi r2,r2,1 + 802d994: 10000726 beq r2,zero,802d9b4 + 802d998: e0bff717 ldw r2,-36(fp) + 802d99c: 10801317 ldw r2,76(r2) + 802d9a0: 1007883a mov r3,r2 + 802d9a4: e0bffc17 ldw r2,-16(fp) + 802d9a8: 1880020e bge r3,r2,802d9b4 + return (EMSGSIZE); + 802d9ac: 00801e84 movi r2,122 + 802d9b0: 00013306 br 802de80 + + dontroute = (flags & MSG_DONTROUTE) && + 802d9b4: e0800217 ldw r2,8(fp) + 802d9b8: 1080010c andi r2,r2,4 + ((so->so_options & SO_DONTROUTE) == 0) && + 802d9bc: 10000c26 beq r2,zero,802d9f0 + 802d9c0: e0bff717 ldw r2,-36(fp) + 802d9c4: 10800417 ldw r2,16(r2) + 802d9c8: 1080040c andi r2,r2,16 + dontroute = (flags & MSG_DONTROUTE) && + 802d9cc: 1000081e bne r2,zero,802d9f0 + (so->so_proto->pr_flags & PR_ATOMIC); + 802d9d0: e0bff717 ldw r2,-36(fp) + 802d9d4: 10800217 ldw r2,8(r2) + 802d9d8: 1080010b ldhu r2,4(r2) + 802d9dc: 10bfffcc andi r2,r2,65535 + 802d9e0: 1080004c andi r2,r2,1 + ((so->so_options & SO_DONTROUTE) == 0) && + 802d9e4: 10000226 beq r2,zero,802d9f0 + 802d9e8: 00800044 movi r2,1 + 802d9ec: 00000106 br 802d9f4 + 802d9f0: 0005883a mov r2,zero + dontroute = (flags & MSG_DONTROUTE) && + 802d9f4: e0bff915 stw r2,-28(fp) + +#define snderr(errno) { error = errno; goto release; } + +restart: + sblock(&so->so_snd); + 802d9f8: 00000406 br 802da0c + 802d9fc: e0bff717 ldw r2,-36(fp) + 802da00: 10801904 addi r2,r2,100 + 802da04: 1009883a mov r4,r2 + 802da08: 8027a540 call 8027a54 + 802da0c: e0bff717 ldw r2,-36(fp) + 802da10: 1080190b ldhu r2,100(r2) + 802da14: 10bfffcc andi r2,r2,65535 + 802da18: 1080004c andi r2,r2,1 + 802da1c: 103ff71e bne r2,zero,802d9fc + 802da20: e0bff717 ldw r2,-36(fp) + 802da24: 1080190b ldhu r2,100(r2) + 802da28: 10800054 ori r2,r2,1 + 802da2c: 1007883a mov r3,r2 + 802da30: e0bff717 ldw r2,-36(fp) + 802da34: 10c0190d sth r3,100(r2) + do + { + if (so->so_error) + 802da38: e0bff717 ldw r2,-36(fp) + 802da3c: 10800617 ldw r2,24(r2) + 802da40: 10000626 beq r2,zero,802da5c + { + error = so->so_error; + 802da44: e0bff717 ldw r2,-36(fp) + 802da48: 10800617 ldw r2,24(r2) + 802da4c: e0bffb15 stw r2,-20(fp) + so->so_error = 0; /* ??? */ + 802da50: e0bff717 ldw r2,-36(fp) + 802da54: 10000615 stw zero,24(r2) + goto release; + 802da58: 0000f906 br 802de40 + } + if (so->so_state & SS_CANTSENDMORE) + 802da5c: e0bff717 ldw r2,-36(fp) + 802da60: 1080088b ldhu r2,34(r2) + 802da64: 10bfffcc andi r2,r2,65535 + 802da68: 1080040c andi r2,r2,16 + 802da6c: 10000326 beq r2,zero,802da7c + snderr(EPIPE); + 802da70: 00800804 movi r2,32 + 802da74: e0bffb15 stw r2,-20(fp) + 802da78: 0000f106 br 802de40 + if ((so->so_state & SS_ISCONNECTED) == 0) + 802da7c: e0bff717 ldw r2,-36(fp) + 802da80: 1080088b ldhu r2,34(r2) + 802da84: 10bfffcc andi r2,r2,65535 + 802da88: 1080008c andi r2,r2,2 + 802da8c: 10000e1e bne r2,zero,802dac8 + { + if (so->so_proto->pr_flags & PR_CONNREQUIRED) + 802da90: e0bff717 ldw r2,-36(fp) + 802da94: 10800217 ldw r2,8(r2) + 802da98: 1080010b ldhu r2,4(r2) + 802da9c: 10bfffcc andi r2,r2,65535 + 802daa0: 1080010c andi r2,r2,4 + 802daa4: 10000326 beq r2,zero,802dab4 + snderr(ENOTCONN); + 802daa8: 00802004 movi r2,128 + 802daac: e0bffb15 stw r2,-20(fp) + 802dab0: 0000e306 br 802de40 + if (nam == 0) + 802dab4: e0bff617 ldw r2,-40(fp) + 802dab8: 1000031e bne r2,zero,802dac8 + snderr(EDESTADDRREQ); + 802dabc: 00801e44 movi r2,121 + 802dac0: e0bffb15 stw r2,-20(fp) + 802dac4: 0000de06 br 802de40 + } + if (flags & MSG_OOB) + 802dac8: e0800217 ldw r2,8(fp) + 802dacc: 1080004c andi r2,r2,1 + 802dad0: 10000326 beq r2,zero,802dae0 + space = 1024; + 802dad4: 00810004 movi r2,1024 + 802dad8: e0bffd15 stw r2,-12(fp) + 802dadc: 00004706 br 802dbfc + else + { + space = (int)sbspace(&so->so_snd); + 802dae0: e0bff717 ldw r2,-36(fp) + 802dae4: 10801317 ldw r2,76(r2) + 802dae8: 1007883a mov r3,r2 + 802daec: e0bff717 ldw r2,-36(fp) + 802daf0: 10801217 ldw r2,72(r2) + 802daf4: 1885c83a sub r2,r3,r2 + 802daf8: 10000616 blt r2,zero,802db14 + 802dafc: e0bff717 ldw r2,-36(fp) + 802db00: 10c01317 ldw r3,76(r2) + 802db04: e0bff717 ldw r2,-36(fp) + 802db08: 10801217 ldw r2,72(r2) + 802db0c: 1885c83a sub r2,r3,r2 + 802db10: 00000106 br 802db18 + 802db14: 0005883a mov r2,zero + 802db18: e0bffd15 stw r2,-12(fp) + if ((sosendallatonce(so) && (space < resid)) || + 802db1c: e0bff717 ldw r2,-36(fp) + 802db20: 10800217 ldw r2,8(r2) + 802db24: 1080010b ldhu r2,4(r2) + 802db28: 10bfffcc andi r2,r2,65535 + 802db2c: 1080004c andi r2,r2,1 + 802db30: 10000326 beq r2,zero,802db40 + 802db34: e0fffd17 ldw r3,-12(fp) + 802db38: e0bffc17 ldw r2,-16(fp) + 802db3c: 18801216 blt r3,r2,802db88 + 802db40: e0bffc17 ldw r2,-16(fp) + 802db44: 10815e10 cmplti r2,r2,1400 + 802db48: 10002c1e bne r2,zero,802dbfc + ((resid >= CLBYTES) && (space < CLBYTES) && + 802db4c: e0bffd17 ldw r2,-12(fp) + 802db50: 10815e08 cmpgei r2,r2,1400 + 802db54: 1000291e bne r2,zero,802dbfc + (so->so_snd.sb_cc >= CLBYTES) && + 802db58: e0bff717 ldw r2,-36(fp) + 802db5c: 10801217 ldw r2,72(r2) + ((resid >= CLBYTES) && (space < CLBYTES) && + 802db60: 10815e30 cmpltui r2,r2,1400 + 802db64: 1000251e bne r2,zero,802dbfc + ((so->so_state & SS_NBIO) == 0) && + 802db68: e0bff717 ldw r2,-36(fp) + 802db6c: 1080088b ldhu r2,34(r2) + 802db70: 10bfffcc andi r2,r2,65535 + 802db74: 1080400c andi r2,r2,256 + (so->so_snd.sb_cc >= CLBYTES) && + 802db78: 1000201e bne r2,zero,802dbfc + ((flags & MSG_DONTWAIT) == 0))) + 802db7c: e0800217 ldw r2,8(fp) + 802db80: 1080080c andi r2,r2,32 + ((so->so_state & SS_NBIO) == 0) && + 802db84: 10001d1e bne r2,zero,802dbfc + { + if ((so->so_state & SS_NBIO) || (flags & MSG_DONTWAIT)) + 802db88: e0bff717 ldw r2,-36(fp) + 802db8c: 1080088b ldhu r2,34(r2) + 802db90: 10bfffcc andi r2,r2,65535 + 802db94: 1080400c andi r2,r2,256 + 802db98: 1000031e bne r2,zero,802dba8 + 802db9c: e0800217 ldw r2,8(fp) + 802dba0: 1080080c andi r2,r2,32 + 802dba4: 10000526 beq r2,zero,802dbbc + { + if (first) + 802dba8: e0bffa17 ldw r2,-24(fp) + 802dbac: 10009d26 beq r2,zero,802de24 + error = EWOULDBLOCK; + 802dbb0: 008002c4 movi r2,11 + 802dbb4: e0bffb15 stw r2,-20(fp) + goto release; + 802dbb8: 00009a06 br 802de24 + } + sbunlock(&so->so_snd); + 802dbbc: e0bff717 ldw r2,-36(fp) + 802dbc0: 10c0190b ldhu r3,100(r2) + 802dbc4: 00bfff84 movi r2,-2 + 802dbc8: 1884703a and r2,r3,r2 + 802dbcc: 1007883a mov r3,r2 + 802dbd0: e0bff717 ldw r2,-36(fp) + 802dbd4: 10c0190d sth r3,100(r2) + 802dbd8: e0bff717 ldw r2,-36(fp) + 802dbdc: 10801904 addi r2,r2,100 + 802dbe0: 1009883a mov r4,r2 + 802dbe4: 8027ba00 call 8027ba0 + sbwait(&so->so_snd); + 802dbe8: e0bff717 ldw r2,-36(fp) + 802dbec: 10801204 addi r2,r2,72 + 802dbf0: 1009883a mov r4,r2 + 802dbf4: 802f8e00 call 802f8e0 + goto restart; + 802dbf8: 003f7f06 br 802d9f8 + } + } + if ( space <= 0 ) + 802dbfc: e0bffd17 ldw r2,-12(fp) + 802dc00: 00805e16 blt zero,r2,802dd7c + { + /* no space in socket send buffer - see if we can wait */ + if ((so->so_state & SS_NBIO) || (flags & MSG_DONTWAIT)) + 802dc04: e0bff717 ldw r2,-36(fp) + 802dc08: 1080088b ldhu r2,34(r2) + 802dc0c: 10bfffcc andi r2,r2,65535 + 802dc10: 1080400c andi r2,r2,256 + 802dc14: 1000031e bne r2,zero,802dc24 + 802dc18: e0800217 ldw r2,8(fp) + 802dc1c: 1080080c andi r2,r2,32 + 802dc20: 10000526 beq r2,zero,802dc38 + { + if (first) /* report first error */ + 802dc24: e0bffa17 ldw r2,-24(fp) + 802dc28: 10008026 beq r2,zero,802de2c + error = EWOULDBLOCK; + 802dc2c: 008002c4 movi r2,11 + 802dc30: e0bffb15 stw r2,-20(fp) + goto release; + 802dc34: 00007d06 br 802de2c + } + /* If blocking socket, let someone else run */ + sbunlock(&so->so_snd); + 802dc38: e0bff717 ldw r2,-36(fp) + 802dc3c: 10c0190b ldhu r3,100(r2) + 802dc40: 00bfff84 movi r2,-2 + 802dc44: 1884703a and r2,r3,r2 + 802dc48: 1007883a mov r3,r2 + 802dc4c: e0bff717 ldw r2,-36(fp) + 802dc50: 10c0190d sth r3,100(r2) + 802dc54: e0bff717 ldw r2,-36(fp) + 802dc58: 10801904 addi r2,r2,100 + 802dc5c: 1009883a mov r4,r2 + 802dc60: 8027ba00 call 8027ba0 + sbwait(&so->so_snd); + 802dc64: e0bff717 ldw r2,-36(fp) + 802dc68: 10801204 addi r2,r2,72 + 802dc6c: 1009883a mov r4,r2 + 802dc70: 802f8e00 call 802f8e0 + goto restart; + 802dc74: 003f6006 br 802d9f8 + } + + while (space > 0) + { + len = resid; + 802dc78: e0bffc17 ldw r2,-16(fp) + 802dc7c: e0bff815 stw r2,-32(fp) + if ( so->so_type == SOCK_STREAM ) + 802dc80: e0bff717 ldw r2,-36(fp) + 802dc84: 10800983 ldbu r2,38(r2) + 802dc88: 10803fcc andi r2,r2,255 + 802dc8c: 1080201c xori r2,r2,128 + 802dc90: 10bfe004 addi r2,r2,-128 + 802dc94: 10800058 cmpnei r2,r2,1 + 802dc98: 1000171e bne r2,zero,802dcf8 + { + m = m_getwithdata(MT_TXDATA, len); + 802dc9c: e17ff817 ldw r5,-32(fp) + 802dca0: 01000084 movi r4,2 + 802dca4: 8029a700 call 8029a70 + 802dca8: e0bffe15 stw r2,-8(fp) + if (!m) + 802dcac: e0bffe17 ldw r2,-8(fp) + 802dcb0: 1000031e bne r2,zero,802dcc0 + snderr(ENOBUFS); + 802dcb4: 00801a44 movi r2,105 + 802dcb8: e0bffb15 stw r2,-20(fp) + 802dcbc: 00006006 br 802de40 + MEMCPY(m->m_data, data, len); + 802dcc0: e0bffe17 ldw r2,-8(fp) + 802dcc4: 10800317 ldw r2,12(r2) + 802dcc8: e0fff817 ldw r3,-32(fp) + 802dccc: 180d883a mov r6,r3 + 802dcd0: e17ff517 ldw r5,-44(fp) + 802dcd4: 1009883a mov r4,r2 + 802dcd8: 80086b80 call 80086b8 + so->so_snd.sb_flags |= SB_MBCOMP; /* allow compression */ + 802dcdc: e0bff717 ldw r2,-36(fp) + 802dce0: 1080190b ldhu r2,100(r2) + 802dce4: 10802014 ori r2,r2,128 + 802dce8: 1007883a mov r3,r2 + 802dcec: e0bff717 ldw r2,-36(fp) + 802dcf0: 10c0190d sth r3,100(r2) + 802dcf4: 00000706 br 802dd14 + } + else + { + m = m_get (M_WAIT, MT_TXDATA); + 802dcf8: 000b883a mov r5,zero + 802dcfc: 01000084 movi r4,2 + 802dd00: 8029a700 call 8029a70 + 802dd04: e0bffe15 stw r2,-8(fp) + m->m_data = data; + 802dd08: e0bffe17 ldw r2,-8(fp) + 802dd0c: e0fff517 ldw r3,-44(fp) + 802dd10: 10c00315 stw r3,12(r2) + } + INET_TRACE (INETM_IO, + ("sosend:got %d bytes so %lx mlen %d, off %d mtod %x\n", + len, so, m->m_len, m->m_off, mtod (m, caddr_t))); + + *data_length -= len; + 802dd14: e0bff417 ldw r2,-48(fp) + 802dd18: 10c00017 ldw r3,0(r2) + 802dd1c: e0bff817 ldw r2,-32(fp) + 802dd20: 1887c83a sub r3,r3,r2 + 802dd24: e0bff417 ldw r2,-48(fp) + 802dd28: 10c00015 stw r3,0(r2) + resid -= len; + 802dd2c: e0fffc17 ldw r3,-16(fp) + 802dd30: e0bff817 ldw r2,-32(fp) + 802dd34: 1885c83a sub r2,r3,r2 + 802dd38: e0bffc15 stw r2,-16(fp) + data += len; + 802dd3c: e0bff817 ldw r2,-32(fp) + 802dd40: e0fff517 ldw r3,-44(fp) + 802dd44: 1885883a add r2,r3,r2 + 802dd48: e0bff515 stw r2,-44(fp) + m->m_len = len; + 802dd4c: e0fff817 ldw r3,-32(fp) + 802dd50: e0bffe17 ldw r2,-8(fp) + 802dd54: 10c00215 stw r3,8(r2) + if (head == (struct mbuf *)NULL) + 802dd58: e0bfff17 ldw r2,-4(fp) + 802dd5c: 1000021e bne r2,zero,802dd68 + head = m; + 802dd60: e0bffe17 ldw r2,-8(fp) + 802dd64: e0bfff15 stw r2,-4(fp) + if (error) + 802dd68: e0bffb17 ldw r2,-20(fp) + 802dd6c: 1000311e bne r2,zero,802de34 + goto release; + if (*data_length <= 0) + 802dd70: e0bff417 ldw r2,-48(fp) + 802dd74: 10800017 ldw r2,0(r2) + 802dd78: 0080030e bge zero,r2,802dd88 + while (space > 0) + 802dd7c: e0bffd17 ldw r2,-12(fp) + 802dd80: 00bfbd16 blt zero,r2,802dc78 + 802dd84: 00000106 br 802dd8c + break; + 802dd88: 0001883a nop + } + + if (dontroute) + 802dd8c: e0bff917 ldw r2,-28(fp) + 802dd90: 10000526 beq r2,zero,802dda8 + so->so_options |= SO_DONTROUTE; + 802dd94: e0bff717 ldw r2,-36(fp) + 802dd98: 10800417 ldw r2,16(r2) + 802dd9c: 10c00414 ori r3,r2,16 + 802dda0: e0bff717 ldw r2,-36(fp) + 802dda4: 10c00415 stw r3,16(r2) + + so->so_req = (flags & MSG_OOB) ? PRU_SENDOOB : PRU_SEND; + 802dda8: e0800217 ldw r2,8(fp) + 802ddac: 1080004c andi r2,r2,1 + 802ddb0: 10000226 beq r2,zero,802ddbc + 802ddb4: 00800384 movi r2,14 + 802ddb8: 00000106 br 802ddc0 + 802ddbc: 00800244 movi r2,9 + 802ddc0: e0fff717 ldw r3,-36(fp) + 802ddc4: 18800715 stw r2,28(r3) + error = (*so->so_proto->pr_usrreq)(so, head, nam); + 802ddc8: e0bff717 ldw r2,-36(fp) + 802ddcc: 10800217 ldw r2,8(r2) + 802ddd0: 10800317 ldw r2,12(r2) + 802ddd4: e1bff617 ldw r6,-40(fp) + 802ddd8: e17fff17 ldw r5,-4(fp) + 802dddc: e13ff717 ldw r4,-36(fp) + 802dde0: 103ee83a callr r2 + 802dde4: e0bffb15 stw r2,-20(fp) + + if (dontroute) + 802dde8: e0bff917 ldw r2,-28(fp) + 802ddec: 10000626 beq r2,zero,802de08 + so->so_options &= ~SO_DONTROUTE; + 802ddf0: e0bff717 ldw r2,-36(fp) + 802ddf4: 10c00417 ldw r3,16(r2) + 802ddf8: 00bffbc4 movi r2,-17 + 802ddfc: 1886703a and r3,r3,r2 + 802de00: e0bff717 ldw r2,-36(fp) + 802de04: 10c00415 stw r3,16(r2) + + head = (struct mbuf *)NULL; + 802de08: e03fff15 stw zero,-4(fp) + first = 0; + 802de0c: e03ffa15 stw zero,-24(fp) + } while ((resid != 0) && (error == 0)); + 802de10: e0bffc17 ldw r2,-16(fp) + 802de14: 10000926 beq r2,zero,802de3c + 802de18: e0bffb17 ldw r2,-20(fp) + 802de1c: 103f0626 beq r2,zero,802da38 + +release: + 802de20: 00000606 br 802de3c + goto release; + 802de24: 0001883a nop + 802de28: 00000506 br 802de40 + goto release; + 802de2c: 0001883a nop + 802de30: 00000306 br 802de40 + goto release; + 802de34: 0001883a nop + 802de38: 00000106 br 802de40 +release: + 802de3c: 0001883a nop + sbunlock(&so->so_snd); + 802de40: e0bff717 ldw r2,-36(fp) + 802de44: 10c0190b ldhu r3,100(r2) + 802de48: 00bfff84 movi r2,-2 + 802de4c: 1884703a and r2,r3,r2 + 802de50: 1007883a mov r3,r2 + 802de54: e0bff717 ldw r2,-36(fp) + 802de58: 10c0190d sth r3,100(r2) + 802de5c: e0bff717 ldw r2,-36(fp) + 802de60: 10801904 addi r2,r2,100 + 802de64: 1009883a mov r4,r2 + 802de68: 8027ba00 call 8027ba0 + if (head) + 802de6c: e0bfff17 ldw r2,-4(fp) + 802de70: 10000226 beq r2,zero,802de7c + m_freem(head); + 802de74: e13fff17 ldw r4,-4(fp) + 802de78: 8029cfc0 call 8029cfc + return error; + 802de7c: e0bffb17 ldw r2,-20(fp) +} + 802de80: e037883a mov sp,fp + 802de84: dfc00117 ldw ra,4(sp) + 802de88: df000017 ldw fp,0(sp) + 802de8c: dec00204 addi sp,sp,8 + 802de90: f800283a ret + +0802de94 : +soreceive(struct socket * so, + struct mbuf **aname, + char * data, + int * datalen, + int flags) +{ + 802de94: defff204 addi sp,sp,-56 + 802de98: dfc00d15 stw ra,52(sp) + 802de9c: df000c15 stw fp,48(sp) + 802dea0: df000c04 addi fp,sp,48 + 802dea4: e13ff715 stw r4,-36(fp) + 802dea8: e17ff615 stw r5,-40(fp) + 802deac: e1bff515 stw r6,-44(fp) + 802deb0: e1fff415 stw r7,-48(fp) + struct mbuf * m; + int len; + int error = 0; + 802deb4: e03ffd15 stw zero,-12(fp) + int offset; + struct protosw * pr = so->so_proto; + 802deb8: e0bff717 ldw r2,-36(fp) + 802debc: 10800217 ldw r2,8(r2) + 802dec0: e0bff915 stw r2,-28(fp) + struct mbuf * nextrecord; + int moff; + int lflags; + + if (aname) + 802dec4: e0bff617 ldw r2,-40(fp) + 802dec8: 10000226 beq r2,zero,802ded4 + *aname = 0; + 802decc: e0bff617 ldw r2,-40(fp) + 802ded0: 10000015 stw zero,0(r2) + if (flags & MSG_OOB) + 802ded4: e0800217 ldw r2,8(fp) + 802ded8: 1080004c andi r2,r2,1 + 802dedc: 10004126 beq r2,zero,802dfe4 + { + m = m_get (M_WAIT, MT_RXDATA); + 802dee0: 000b883a mov r5,zero + 802dee4: 01000044 movi r4,1 + 802dee8: 8029a700 call 8029a70 + 802deec: e0bfff15 stw r2,-4(fp) + if (m == NULL) + 802def0: e0bfff17 ldw r2,-4(fp) + 802def4: 1000021e bne r2,zero,802df00 + return ENOBUFS; + 802def8: 00801a44 movi r2,105 + 802defc: 0001b606 br 802e5d8 + lflags = flags & MSG_PEEK; + 802df00: e0800217 ldw r2,8(fp) + 802df04: 1080008c andi r2,r2,2 + 802df08: e0bff815 stw r2,-32(fp) + + so->so_req = PRU_RCVOOB; + 802df0c: e0bff717 ldw r2,-36(fp) + 802df10: 00c00344 movi r3,13 + 802df14: 10c00715 stw r3,28(r2) + error = (*pr->pr_usrreq)(so, m, LONG2MBUF((long)lflags)); + 802df18: e0bff917 ldw r2,-28(fp) + 802df1c: 10800317 ldw r2,12(r2) + 802df20: e0fff817 ldw r3,-32(fp) + 802df24: 180d883a mov r6,r3 + 802df28: e17fff17 ldw r5,-4(fp) + 802df2c: e13ff717 ldw r4,-36(fp) + 802df30: 103ee83a callr r2 + 802df34: e0bffd15 stw r2,-12(fp) + if (error == 0) + 802df38: e0bffd17 ldw r2,-12(fp) + 802df3c: 1000231e bne r2,zero,802dfcc + { + do + { + len = *datalen; + 802df40: e0bff417 ldw r2,-48(fp) + 802df44: 10800017 ldw r2,0(r2) + 802df48: e0bffe15 stw r2,-8(fp) + if (len > (int)m->m_len) + 802df4c: e0bfff17 ldw r2,-4(fp) + 802df50: 10800217 ldw r2,8(r2) + 802df54: 1007883a mov r3,r2 + 802df58: e0bffe17 ldw r2,-8(fp) + 802df5c: 1880030e bge r3,r2,802df6c + len = m->m_len; + 802df60: e0bfff17 ldw r2,-4(fp) + 802df64: 10800217 ldw r2,8(r2) + 802df68: e0bffe15 stw r2,-8(fp) + + MEMCPY(data, mtod(m, char*), len); + 802df6c: e0bfff17 ldw r2,-4(fp) + 802df70: 10800317 ldw r2,12(r2) + 802df74: e0fffe17 ldw r3,-8(fp) + 802df78: 180d883a mov r6,r3 + 802df7c: 100b883a mov r5,r2 + 802df80: e13ff517 ldw r4,-44(fp) + 802df84: 80086b80 call 80086b8 + data += len; + 802df88: e0bffe17 ldw r2,-8(fp) + 802df8c: e0fff517 ldw r3,-44(fp) + 802df90: 1885883a add r2,r3,r2 + 802df94: e0bff515 stw r2,-44(fp) + *datalen = len; + 802df98: e0bff417 ldw r2,-48(fp) + 802df9c: e0fffe17 ldw r3,-8(fp) + 802dfa0: 10c00015 stw r3,0(r2) + m = m_free(m); + 802dfa4: e13fff17 ldw r4,-4(fp) + 802dfa8: 8029bf80 call 8029bf8 + 802dfac: e0bfff15 stw r2,-4(fp) + } while (*datalen && (error == 0) && m); + 802dfb0: e0bff417 ldw r2,-48(fp) + 802dfb4: 10800017 ldw r2,0(r2) + 802dfb8: 10000426 beq r2,zero,802dfcc + 802dfbc: e0bffd17 ldw r2,-12(fp) + 802dfc0: 1000021e bne r2,zero,802dfcc + 802dfc4: e0bfff17 ldw r2,-4(fp) + 802dfc8: 103fdd1e bne r2,zero,802df40 + } + + if (m) + 802dfcc: e0bfff17 ldw r2,-4(fp) + 802dfd0: 10000226 beq r2,zero,802dfdc + m_freem(m); + 802dfd4: e13fff17 ldw r4,-4(fp) + 802dfd8: 8029cfc0 call 8029cfc + return (error); + 802dfdc: e0bffd17 ldw r2,-12(fp) + 802dfe0: 00017d06 br 802e5d8 + } + +restart: + 802dfe4: 0001883a nop + sblock (&so->so_rcv); + 802dfe8: 00000406 br 802dffc + 802dfec: e0bff717 ldw r2,-36(fp) + 802dff0: 10801104 addi r2,r2,68 + 802dff4: 1009883a mov r4,r2 + 802dff8: 8027a540 call 8027a54 + 802dffc: e0bff717 ldw r2,-36(fp) + 802e000: 1080110b ldhu r2,68(r2) + 802e004: 10bfffcc andi r2,r2,65535 + 802e008: 1080004c andi r2,r2,1 + 802e00c: 103ff71e bne r2,zero,802dfec + 802e010: e0bff717 ldw r2,-36(fp) + 802e014: 1080110b ldhu r2,68(r2) + 802e018: 10800054 ori r2,r2,1 + 802e01c: 1007883a mov r3,r2 + 802e020: e0bff717 ldw r2,-36(fp) + 802e024: 10c0110d sth r3,68(r2) + INET_TRACE (INETM_IO, + ("INET:soreceive sbcc %d soerror %d so_state %d *datalen %d\n", + so->so_rcv.sb_cc, so->so_error, so->so_state, *datalen)); + + /* If no data is ready, see if we should wait or return */ + if (so->so_rcv.sb_cc == 0) + 802e028: e0bff717 ldw r2,-36(fp) + 802e02c: 10800a17 ldw r2,40(r2) + 802e030: 10003a1e bne r2,zero,802e11c + { + if (so->so_error) + 802e034: e0bff717 ldw r2,-36(fp) + 802e038: 10800617 ldw r2,24(r2) + 802e03c: 10000626 beq r2,zero,802e058 + { + error = so->so_error; + 802e040: e0bff717 ldw r2,-36(fp) + 802e044: 10800617 ldw r2,24(r2) + 802e048: e0bffd15 stw r2,-12(fp) + so->so_error = 0; + 802e04c: e0bff717 ldw r2,-36(fp) + 802e050: 10000615 stw zero,24(r2) + goto release; + 802e054: 00015406 br 802e5a8 + } + if (so->so_state & SS_CANTRCVMORE) + 802e058: e0bff717 ldw r2,-36(fp) + 802e05c: 1080088b ldhu r2,34(r2) + 802e060: 10bfffcc andi r2,r2,65535 + 802e064: 1080080c andi r2,r2,32 + 802e068: 10014a1e bne r2,zero,802e594 + goto release; + if ((so->so_state & SS_ISCONNECTED) == 0 && + 802e06c: e0bff717 ldw r2,-36(fp) + 802e070: 1080088b ldhu r2,34(r2) + 802e074: 10bfffcc andi r2,r2,65535 + 802e078: 1080008c andi r2,r2,2 + 802e07c: 1000091e bne r2,zero,802e0a4 + (so->so_proto->pr_flags & PR_CONNREQUIRED)) + 802e080: e0bff717 ldw r2,-36(fp) + 802e084: 10800217 ldw r2,8(r2) + 802e088: 1080010b ldhu r2,4(r2) + 802e08c: 10bfffcc andi r2,r2,65535 + 802e090: 1080010c andi r2,r2,4 + if ((so->so_state & SS_ISCONNECTED) == 0 && + 802e094: 10000326 beq r2,zero,802e0a4 + { + error = ENOTCONN; + 802e098: 00802004 movi r2,128 + 802e09c: e0bffd15 stw r2,-12(fp) + goto release; + 802e0a0: 00014106 br 802e5a8 + } + if (*datalen == 0) + 802e0a4: e0bff417 ldw r2,-48(fp) + 802e0a8: 10800017 ldw r2,0(r2) + 802e0ac: 10013b26 beq r2,zero,802e59c + goto release; + if ((so->so_state & SS_NBIO) || (flags & MSG_DONTWAIT)) + 802e0b0: e0bff717 ldw r2,-36(fp) + 802e0b4: 1080088b ldhu r2,34(r2) + 802e0b8: 10bfffcc andi r2,r2,65535 + 802e0bc: 1080400c andi r2,r2,256 + 802e0c0: 1000031e bne r2,zero,802e0d0 + 802e0c4: e0800217 ldw r2,8(fp) + 802e0c8: 1080080c andi r2,r2,32 + 802e0cc: 10000326 beq r2,zero,802e0dc + { + error = EWOULDBLOCK; + 802e0d0: 008002c4 movi r2,11 + 802e0d4: e0bffd15 stw r2,-12(fp) + goto release; + 802e0d8: 00013306 br 802e5a8 + } + sbunlock(&so->so_rcv); + 802e0dc: e0bff717 ldw r2,-36(fp) + 802e0e0: 10c0110b ldhu r3,68(r2) + 802e0e4: 00bfff84 movi r2,-2 + 802e0e8: 1884703a and r2,r3,r2 + 802e0ec: 1007883a mov r3,r2 + 802e0f0: e0bff717 ldw r2,-36(fp) + 802e0f4: 10c0110d sth r3,68(r2) + 802e0f8: e0bff717 ldw r2,-36(fp) + 802e0fc: 10801104 addi r2,r2,68 + 802e100: 1009883a mov r4,r2 + 802e104: 8027ba00 call 8027ba0 + sbwait(&so->so_rcv); + 802e108: e0bff717 ldw r2,-36(fp) + 802e10c: 10800a04 addi r2,r2,40 + 802e110: 1009883a mov r4,r2 + 802e114: 802f8e00 call 802f8e0 + goto restart; + 802e118: 003fb306 br 802dfe8 + } + m = so->so_rcv.sb_mb; + 802e11c: e0bff717 ldw r2,-36(fp) + 802e120: 10801017 ldw r2,64(r2) + 802e124: e0bfff15 stw r2,-4(fp) + if (m == 0) + 802e128: e0bfff17 ldw r2,-4(fp) + 802e12c: 1000031e bne r2,zero,802e13c + panic("sorecv 1"); + 802e130: 01020174 movhi r4,2053 + 802e134: 212a7b04 addi r4,r4,-22036 + 802e138: 80271780 call 8027178 + nextrecord = m->m_act; + 802e13c: e0bfff17 ldw r2,-4(fp) + 802e140: 10800717 ldw r2,28(r2) + 802e144: e0bffb15 stw r2,-20(fp) + if (pr->pr_flags & PR_ADDR) + 802e148: e0bff917 ldw r2,-28(fp) + 802e14c: 1080010b ldhu r2,4(r2) + 802e150: 10bfffcc andi r2,r2,65535 + 802e154: 1080008c andi r2,r2,2 + 802e158: 10004226 beq r2,zero,802e264 + { + if (m->m_type != MT_SONAME) + 802e15c: e0bfff17 ldw r2,-4(fp) + 802e160: 10800817 ldw r2,32(r2) + 802e164: 10800260 cmpeqi r2,r2,9 + 802e168: 1000091e bne r2,zero,802e190 + { + dprintf ("sorecv:type %d not nam", m->m_type); + 802e16c: e0bfff17 ldw r2,-4(fp) + 802e170: 10800817 ldw r2,32(r2) + 802e174: 100b883a mov r5,r2 + 802e178: 01020174 movhi r4,2053 + 802e17c: 212a7e04 addi r4,r4,-22024 + 802e180: 8002c780 call 8002c78 + panic("sorecv 2"); + 802e184: 01020174 movhi r4,2053 + 802e188: 212a8404 addi r4,r4,-22000 + 802e18c: 80271780 call 8027178 + } + if (flags & MSG_PEEK) + 802e190: e0800217 ldw r2,8(fp) + 802e194: 1080008c andi r2,r2,2 + 802e198: 10000f26 beq r2,zero,802e1d8 + { + if (aname) + 802e19c: e0bff617 ldw r2,-40(fp) + 802e1a0: 10000926 beq r2,zero,802e1c8 + *aname = m_copy (m, 0, m->m_len); + 802e1a4: e0bfff17 ldw r2,-4(fp) + 802e1a8: 10800217 ldw r2,8(r2) + 802e1ac: 100d883a mov r6,r2 + 802e1b0: 000b883a mov r5,zero + 802e1b4: e13fff17 ldw r4,-4(fp) + 802e1b8: 8029d400 call 8029d40 + 802e1bc: 1007883a mov r3,r2 + 802e1c0: e0bff617 ldw r2,-40(fp) + 802e1c4: 10c00015 stw r3,0(r2) + m = m->m_next; + 802e1c8: e0bfff17 ldw r2,-4(fp) + 802e1cc: 10800617 ldw r2,24(r2) + 802e1d0: e0bfff15 stw r2,-4(fp) + 802e1d4: 00002306 br 802e264 + } else + { + sbfree (&so->so_rcv, m); + 802e1d8: e0bff717 ldw r2,-36(fp) + 802e1dc: 10c00a17 ldw r3,40(r2) + 802e1e0: e0bfff17 ldw r2,-4(fp) + 802e1e4: 10800217 ldw r2,8(r2) + 802e1e8: 1887c83a sub r3,r3,r2 + 802e1ec: e0bff717 ldw r2,-36(fp) + 802e1f0: 10c00a15 stw r3,40(r2) + if (aname) + 802e1f4: e0bff617 ldw r2,-40(fp) + 802e1f8: 10000d26 beq r2,zero,802e230 + { + *aname = m; + 802e1fc: e0bff617 ldw r2,-40(fp) + 802e200: e0ffff17 ldw r3,-4(fp) + 802e204: 10c00015 stw r3,0(r2) + m = m->m_next; + 802e208: e0bfff17 ldw r2,-4(fp) + 802e20c: 10800617 ldw r2,24(r2) + 802e210: e0bfff15 stw r2,-4(fp) + (*aname)->m_next = 0; + 802e214: e0bff617 ldw r2,-40(fp) + 802e218: 10800017 ldw r2,0(r2) + 802e21c: 10000615 stw zero,24(r2) + so->so_rcv.sb_mb = m; + 802e220: e0bff717 ldw r2,-36(fp) + 802e224: e0ffff17 ldw r3,-4(fp) + 802e228: 10c01015 stw r3,64(r2) + 802e22c: 00000806 br 802e250 + } else + { + MFREE(m, so->so_rcv.sb_mb); + 802e230: e13fff17 ldw r4,-4(fp) + 802e234: 8029bf80 call 8029bf8 + 802e238: 1007883a mov r3,r2 + 802e23c: e0bff717 ldw r2,-36(fp) + 802e240: 10c01015 stw r3,64(r2) + m = so->so_rcv.sb_mb; + 802e244: e0bff717 ldw r2,-36(fp) + 802e248: 10801017 ldw r2,64(r2) + 802e24c: e0bfff15 stw r2,-4(fp) + } + if (m) + 802e250: e0bfff17 ldw r2,-4(fp) + 802e254: 10000326 beq r2,zero,802e264 + m->m_act = nextrecord; + 802e258: e0bfff17 ldw r2,-4(fp) + 802e25c: e0fffb17 ldw r3,-20(fp) + 802e260: 10c00715 stw r3,28(r2) + } + } + moff = 0; + 802e264: e03ffa15 stw zero,-24(fp) + offset = 0; + 802e268: e03ffc15 stw zero,-16(fp) + while (m && (*datalen > 0) && (error == 0)) + 802e26c: 00009e06 br 802e4e8 + { + if (m->m_type != MT_RXDATA && m->m_type != MT_HEADER) + 802e270: e0bfff17 ldw r2,-4(fp) + 802e274: 10800817 ldw r2,32(r2) + 802e278: 10800060 cmpeqi r2,r2,1 + 802e27c: 1000071e bne r2,zero,802e29c + 802e280: e0bfff17 ldw r2,-4(fp) + 802e284: 10800817 ldw r2,32(r2) + 802e288: 108000e0 cmpeqi r2,r2,3 + 802e28c: 1000031e bne r2,zero,802e29c + panic("sorecv 3"); + 802e290: 01020174 movhi r4,2053 + 802e294: 212a8704 addi r4,r4,-21988 + 802e298: 80271780 call 8027178 + len = *datalen; + 802e29c: e0bff417 ldw r2,-48(fp) + 802e2a0: 10800017 ldw r2,0(r2) + 802e2a4: e0bffe15 stw r2,-8(fp) + so->so_state &= ~SS_RCVATMARK; + 802e2a8: e0bff717 ldw r2,-36(fp) + 802e2ac: 10c0088b ldhu r3,34(r2) + 802e2b0: 00bfefc4 movi r2,-65 + 802e2b4: 1884703a and r2,r3,r2 + 802e2b8: 1007883a mov r3,r2 + 802e2bc: e0bff717 ldw r2,-36(fp) + 802e2c0: 10c0088d sth r3,34(r2) + if (so->so_oobmark && (len > (int)(so->so_oobmark - offset))) + 802e2c4: e0bff717 ldw r2,-36(fp) + 802e2c8: 10801a17 ldw r2,104(r2) + 802e2cc: 10000c26 beq r2,zero,802e300 + 802e2d0: e0bff717 ldw r2,-36(fp) + 802e2d4: 10c01a17 ldw r3,104(r2) + 802e2d8: e0bffc17 ldw r2,-16(fp) + 802e2dc: 1885c83a sub r2,r3,r2 + 802e2e0: 1007883a mov r3,r2 + 802e2e4: e0bffe17 ldw r2,-8(fp) + 802e2e8: 1880050e bge r3,r2,802e300 + len = (int)(so->so_oobmark - offset); + 802e2ec: e0bff717 ldw r2,-36(fp) + 802e2f0: 10c01a17 ldw r3,104(r2) + 802e2f4: e0bffc17 ldw r2,-16(fp) + 802e2f8: 1885c83a sub r2,r3,r2 + 802e2fc: e0bffe15 stw r2,-8(fp) + if (len > (int)(m->m_len - moff)) + 802e300: e0bfff17 ldw r2,-4(fp) + 802e304: 10c00217 ldw r3,8(r2) + 802e308: e0bffa17 ldw r2,-24(fp) + 802e30c: 1885c83a sub r2,r3,r2 + 802e310: 1007883a mov r3,r2 + 802e314: e0bffe17 ldw r2,-8(fp) + 802e318: 1880050e bge r3,r2,802e330 + len = m->m_len - moff; + 802e31c: e0bfff17 ldw r2,-4(fp) + 802e320: 10c00217 ldw r3,8(r2) + 802e324: e0bffa17 ldw r2,-24(fp) + 802e328: 1885c83a sub r2,r3,r2 + 802e32c: e0bffe15 stw r2,-8(fp) + * it points to next record) when we drop priority; + * we must note any additions to the sockbuf when we + * block interrupts again. + */ + + MEMCPY(data, (mtod(m, char *) + moff), len); + 802e330: e0bfff17 ldw r2,-4(fp) + 802e334: 10c00317 ldw r3,12(r2) + 802e338: e0bffa17 ldw r2,-24(fp) + 802e33c: 1885883a add r2,r3,r2 + 802e340: e0fffe17 ldw r3,-8(fp) + 802e344: 180d883a mov r6,r3 + 802e348: 100b883a mov r5,r2 + 802e34c: e13ff517 ldw r4,-44(fp) + 802e350: 80086b80 call 80086b8 + data += len; + 802e354: e0bffe17 ldw r2,-8(fp) + 802e358: e0fff517 ldw r3,-44(fp) + 802e35c: 1885883a add r2,r3,r2 + 802e360: e0bff515 stw r2,-44(fp) + *datalen -= len; + 802e364: e0bff417 ldw r2,-48(fp) + 802e368: 10c00017 ldw r3,0(r2) + 802e36c: e0bffe17 ldw r2,-8(fp) + 802e370: 1887c83a sub r3,r3,r2 + 802e374: e0bff417 ldw r2,-48(fp) + 802e378: 10c00015 stw r3,0(r2) + + if (len == (int)(m->m_len - moff)) + 802e37c: e0bfff17 ldw r2,-4(fp) + 802e380: 10c00217 ldw r3,8(r2) + 802e384: e0bffa17 ldw r2,-24(fp) + 802e388: 1885c83a sub r2,r3,r2 + 802e38c: 1007883a mov r3,r2 + 802e390: e0bffe17 ldw r2,-8(fp) + 802e394: 10c0201e bne r2,r3,802e418 + { + if (flags & MSG_PEEK) + 802e398: e0800217 ldw r2,8(fp) + 802e39c: 1080008c andi r2,r2,2 + 802e3a0: 10000526 beq r2,zero,802e3b8 + { + m = m->m_next; + 802e3a4: e0bfff17 ldw r2,-4(fp) + 802e3a8: 10800617 ldw r2,24(r2) + 802e3ac: e0bfff15 stw r2,-4(fp) + moff = 0; + 802e3b0: e03ffa15 stw zero,-24(fp) + 802e3b4: 00003206 br 802e480 + } else + { + nextrecord = m->m_act; + 802e3b8: e0bfff17 ldw r2,-4(fp) + 802e3bc: 10800717 ldw r2,28(r2) + 802e3c0: e0bffb15 stw r2,-20(fp) + sbfree(&so->so_rcv, m); + 802e3c4: e0bff717 ldw r2,-36(fp) + 802e3c8: 10c00a17 ldw r3,40(r2) + 802e3cc: e0bfff17 ldw r2,-4(fp) + 802e3d0: 10800217 ldw r2,8(r2) + 802e3d4: 1887c83a sub r3,r3,r2 + 802e3d8: e0bff717 ldw r2,-36(fp) + 802e3dc: 10c00a15 stw r3,40(r2) + { + MFREE(m, so->so_rcv.sb_mb); + 802e3e0: e13fff17 ldw r4,-4(fp) + 802e3e4: 8029bf80 call 8029bf8 + 802e3e8: 1007883a mov r3,r2 + 802e3ec: e0bff717 ldw r2,-36(fp) + 802e3f0: 10c01015 stw r3,64(r2) + m = so->so_rcv.sb_mb; + 802e3f4: e0bff717 ldw r2,-36(fp) + 802e3f8: 10801017 ldw r2,64(r2) + 802e3fc: e0bfff15 stw r2,-4(fp) + } + if (m) + 802e400: e0bfff17 ldw r2,-4(fp) + 802e404: 10001e26 beq r2,zero,802e480 + m->m_act = nextrecord; + 802e408: e0bfff17 ldw r2,-4(fp) + 802e40c: e0fffb17 ldw r3,-20(fp) + 802e410: 10c00715 stw r3,28(r2) + 802e414: 00001a06 br 802e480 + } + } else + { + if (flags & MSG_PEEK) + 802e418: e0800217 ldw r2,8(fp) + 802e41c: 1080008c andi r2,r2,2 + 802e420: 10000526 beq r2,zero,802e438 + moff += len; + 802e424: e0fffa17 ldw r3,-24(fp) + 802e428: e0bffe17 ldw r2,-8(fp) + 802e42c: 1885883a add r2,r3,r2 + 802e430: e0bffa15 stw r2,-24(fp) + 802e434: 00001206 br 802e480 + else + { + m->m_data += len; + 802e438: e0bfff17 ldw r2,-4(fp) + 802e43c: 10c00317 ldw r3,12(r2) + 802e440: e0bffe17 ldw r2,-8(fp) + 802e444: 1887883a add r3,r3,r2 + 802e448: e0bfff17 ldw r2,-4(fp) + 802e44c: 10c00315 stw r3,12(r2) + m->m_len -= len; + 802e450: e0bfff17 ldw r2,-4(fp) + 802e454: 10c00217 ldw r3,8(r2) + 802e458: e0bffe17 ldw r2,-8(fp) + 802e45c: 1887c83a sub r3,r3,r2 + 802e460: e0bfff17 ldw r2,-4(fp) + 802e464: 10c00215 stw r3,8(r2) + so->so_rcv.sb_cc -= len; + 802e468: e0bff717 ldw r2,-36(fp) + 802e46c: 10c00a17 ldw r3,40(r2) + 802e470: e0bffe17 ldw r2,-8(fp) + 802e474: 1887c83a sub r3,r3,r2 + 802e478: e0bff717 ldw r2,-36(fp) + 802e47c: 10c00a15 stw r3,40(r2) + } + } + if (so->so_oobmark) + 802e480: e0bff717 ldw r2,-36(fp) + 802e484: 10801a17 ldw r2,104(r2) + 802e488: 10001726 beq r2,zero,802e4e8 + { + if ((flags & MSG_PEEK) == 0) + 802e48c: e0800217 ldw r2,8(fp) + 802e490: 1080008c andi r2,r2,2 + 802e494: 1000101e bne r2,zero,802e4d8 + { + so->so_oobmark -= len; + 802e498: e0bff717 ldw r2,-36(fp) + 802e49c: 10c01a17 ldw r3,104(r2) + 802e4a0: e0bffe17 ldw r2,-8(fp) + 802e4a4: 1887c83a sub r3,r3,r2 + 802e4a8: e0bff717 ldw r2,-36(fp) + 802e4ac: 10c01a15 stw r3,104(r2) + if (so->so_oobmark == 0) + 802e4b0: e0bff717 ldw r2,-36(fp) + 802e4b4: 10801a17 ldw r2,104(r2) + 802e4b8: 10000b1e bne r2,zero,802e4e8 + { + so->so_state |= SS_RCVATMARK; + 802e4bc: e0bff717 ldw r2,-36(fp) + 802e4c0: 1080088b ldhu r2,34(r2) + 802e4c4: 10801014 ori r2,r2,64 + 802e4c8: 1007883a mov r3,r2 + 802e4cc: e0bff717 ldw r2,-36(fp) + 802e4d0: 10c0088d sth r3,34(r2) + break; + 802e4d4: 00000b06 br 802e504 + } + } else + offset += len; + 802e4d8: e0fffc17 ldw r3,-16(fp) + 802e4dc: e0bffe17 ldw r2,-8(fp) + 802e4e0: 1885883a add r2,r3,r2 + 802e4e4: e0bffc15 stw r2,-16(fp) + while (m && (*datalen > 0) && (error == 0)) + 802e4e8: e0bfff17 ldw r2,-4(fp) + 802e4ec: 10000526 beq r2,zero,802e504 + 802e4f0: e0bff417 ldw r2,-48(fp) + 802e4f4: 10800017 ldw r2,0(r2) + 802e4f8: 0080020e bge zero,r2,802e504 + 802e4fc: e0bffd17 ldw r2,-12(fp) + 802e500: 103f5b26 beq r2,zero,802e270 + } + } + + if ((flags & MSG_PEEK) == 0) + 802e504: e0800217 ldw r2,8(fp) + 802e508: 1080008c andi r2,r2,2 + 802e50c: 1000251e bne r2,zero,802e5a4 + { + if (m == 0) + 802e510: e0bfff17 ldw r2,-4(fp) + 802e514: 1000041e bne r2,zero,802e528 + so->so_rcv.sb_mb = nextrecord; + 802e518: e0bff717 ldw r2,-36(fp) + 802e51c: e0fffb17 ldw r3,-20(fp) + 802e520: 10c01015 stw r3,64(r2) + 802e524: 00000906 br 802e54c + else if (pr->pr_flags & PR_ATOMIC) + 802e528: e0bff917 ldw r2,-28(fp) + 802e52c: 1080010b ldhu r2,4(r2) + 802e530: 10bfffcc andi r2,r2,65535 + 802e534: 1080004c andi r2,r2,1 + 802e538: 10000426 beq r2,zero,802e54c + (void) sbdroprecord(&so->so_rcv); + 802e53c: e0bff717 ldw r2,-36(fp) + 802e540: 10800a04 addi r2,r2,40 + 802e544: 1009883a mov r4,r2 + 802e548: 80303680 call 8030368 + if (pr->pr_flags & PR_WANTRCVD && so->so_pcb) + 802e54c: e0bff917 ldw r2,-28(fp) + 802e550: 1080010b ldhu r2,4(r2) + 802e554: 10bfffcc andi r2,r2,65535 + 802e558: 1080020c andi r2,r2,8 + 802e55c: 10001126 beq r2,zero,802e5a4 + 802e560: e0bff717 ldw r2,-36(fp) + 802e564: 10800117 ldw r2,4(r2) + 802e568: 10000e26 beq r2,zero,802e5a4 + { + so->so_req = PRU_RCVD; + 802e56c: e0bff717 ldw r2,-36(fp) + 802e570: 00c00204 movi r3,8 + 802e574: 10c00715 stw r3,28(r2) + (*pr->pr_usrreq)(so, (struct mbuf *)0, + 802e578: e0bff917 ldw r2,-28(fp) + 802e57c: 10800317 ldw r2,12(r2) + 802e580: 000d883a mov r6,zero + 802e584: 000b883a mov r5,zero + 802e588: e13ff717 ldw r4,-36(fp) + 802e58c: 103ee83a callr r2 + 802e590: 00000506 br 802e5a8 + goto release; + 802e594: 0001883a nop + 802e598: 00000306 br 802e5a8 + goto release; + 802e59c: 0001883a nop + 802e5a0: 00000106 br 802e5a8 + (struct mbuf *)0); + } + } +release: + 802e5a4: 0001883a nop + sbunlock(&so->so_rcv); + 802e5a8: e0bff717 ldw r2,-36(fp) + 802e5ac: 10c0110b ldhu r3,68(r2) + 802e5b0: 00bfff84 movi r2,-2 + 802e5b4: 1884703a and r2,r3,r2 + 802e5b8: 1007883a mov r3,r2 + 802e5bc: e0bff717 ldw r2,-36(fp) + 802e5c0: 10c0110d sth r3,68(r2) + 802e5c4: e0bff717 ldw r2,-36(fp) + 802e5c8: 10801104 addi r2,r2,68 + 802e5cc: 1009883a mov r4,r2 + 802e5d0: 8027ba00 call 8027ba0 + return (error); + 802e5d4: e0bffd17 ldw r2,-12(fp) +} + 802e5d8: e037883a mov sp,fp + 802e5dc: dfc00117 ldw ra,4(sp) + 802e5e0: df000017 ldw fp,0(sp) + 802e5e4: dec00204 addi sp,sp,8 + 802e5e8: f800283a ret + +0802e5ec : + * + * RETURNS: int 0 if successful, else error code + */ +int +soshutdown(struct socket *so, int how) +{ + 802e5ec: defffc04 addi sp,sp,-16 + 802e5f0: dfc00315 stw ra,12(sp) + 802e5f4: df000215 stw fp,8(sp) + 802e5f8: df000204 addi fp,sp,8 + 802e5fc: e13fff15 stw r4,-4(fp) + 802e600: e17ffe15 stw r5,-8(fp) + how++; /* convert 0,1,2 into 1,2,3 */ + 802e604: e0bffe17 ldw r2,-8(fp) + 802e608: 10800044 addi r2,r2,1 + 802e60c: e0bffe15 stw r2,-8(fp) + if (how & 1) /* caller wanted READ or BOTH */ + 802e610: e0bffe17 ldw r2,-8(fp) + 802e614: 1080004c andi r2,r2,1 + 802e618: 10000226 beq r2,zero,802e624 + sorflush(so); + 802e61c: e13fff17 ldw r4,-4(fp) + 802e620: 802e6840 call 802e684 + + if (how & 2) /* caller wanted WRITE or BOTH */ + 802e624: e0bffe17 ldw r2,-8(fp) + 802e628: 1080008c andi r2,r2,2 + 802e62c: 10000f26 beq r2,zero,802e66c + { + sbflush(&so->so_snd); /* flush the socket send queue */ + 802e630: e0bfff17 ldw r2,-4(fp) + 802e634: 10801204 addi r2,r2,72 + 802e638: 1009883a mov r4,r2 + 802e63c: 803002c0 call 803002c + so->so_req = PRU_SHUTDOWN; + 802e640: e0bfff17 ldw r2,-4(fp) + 802e644: 00c001c4 movi r3,7 + 802e648: 10c00715 stw r3,28(r2) + return ((*so->so_proto->pr_usrreq)(so, (struct mbuf *)0, (struct mbuf *)0)); + 802e64c: e0bfff17 ldw r2,-4(fp) + 802e650: 10800217 ldw r2,8(r2) + 802e654: 10800317 ldw r2,12(r2) + 802e658: 000d883a mov r6,zero + 802e65c: 000b883a mov r5,zero + 802e660: e13fff17 ldw r4,-4(fp) + 802e664: 103ee83a callr r2 + 802e668: 00000106 br 802e670 + } + + return 0; + 802e66c: 0005883a mov r2,zero +} + 802e670: e037883a mov sp,fp + 802e674: dfc00117 ldw ra,4(sp) + 802e678: df000017 ldw fp,0(sp) + 802e67c: dec00204 addi sp,sp,8 + 802e680: f800283a ret + +0802e684 : + * socket receive buffer is discarded. Wakeup any processes waiting + * on the socket. + */ +void +sorflush(struct socket * so) +{ + 802e684: defffb04 addi sp,sp,-20 + 802e688: dfc00415 stw ra,16(sp) + 802e68c: df000315 stw fp,12(sp) + 802e690: df000304 addi fp,sp,12 + 802e694: e13ffd15 stw r4,-12(fp) + struct sockbuf *sb = &so->so_rcv; + 802e698: e0bffd17 ldw r2,-12(fp) + 802e69c: 10800a04 addi r2,r2,40 + 802e6a0: e0bfff15 stw r2,-4(fp) + int s; + + sblock(sb); + 802e6a4: 00000406 br 802e6b8 + 802e6a8: e0bfff17 ldw r2,-4(fp) + 802e6ac: 10800704 addi r2,r2,28 + 802e6b0: 1009883a mov r4,r2 + 802e6b4: 8027a540 call 8027a54 + 802e6b8: e0bfff17 ldw r2,-4(fp) + 802e6bc: 1080070b ldhu r2,28(r2) + 802e6c0: 10bfffcc andi r2,r2,65535 + 802e6c4: 1080004c andi r2,r2,1 + 802e6c8: 103ff71e bne r2,zero,802e6a8 + 802e6cc: e0bfff17 ldw r2,-4(fp) + 802e6d0: 1080070b ldhu r2,28(r2) + 802e6d4: 10800054 ori r2,r2,1 + 802e6d8: 1007883a mov r3,r2 + 802e6dc: e0bfff17 ldw r2,-4(fp) + 802e6e0: 10c0070d sth r3,28(r2) + socantrcvmore(so); + 802e6e4: e13ffd17 ldw r4,-12(fp) + 802e6e8: 802f84c0 call 802f84c + sbunlock(sb); + 802e6ec: e0bfff17 ldw r2,-4(fp) + 802e6f0: 10c0070b ldhu r3,28(r2) + 802e6f4: 00bfff84 movi r2,-2 + 802e6f8: 1884703a and r2,r3,r2 + 802e6fc: 1007883a mov r3,r2 + 802e700: e0bfff17 ldw r2,-4(fp) + 802e704: 10c0070d sth r3,28(r2) + 802e708: e0bfff17 ldw r2,-4(fp) + 802e70c: 10800704 addi r2,r2,28 + 802e710: 1009883a mov r4,r2 + 802e714: 8027ba00 call 8027ba0 + sbrelease(sb); + 802e718: e13fff17 ldw r4,-4(fp) + 802e71c: 802fab00 call 802fab0 + MEMSET((char *)sb, 0, sizeof (*sb)); + 802e720: 01800804 movi r6,32 + 802e724: 000b883a mov r5,zero + 802e728: e13fff17 ldw r4,-4(fp) + 802e72c: 80088e40 call 80088e4 + s = so->so_error; + 802e730: e0bffd17 ldw r2,-12(fp) + 802e734: 10800617 ldw r2,24(r2) + 802e738: e0bffe15 stw r2,-8(fp) + so->so_error = ESHUTDOWN; + 802e73c: e0bffd17 ldw r2,-12(fp) + 802e740: 00c01b84 movi r3,110 + 802e744: 10c00615 stw r3,24(r2) + sorwakeup(so); + 802e748: e0bffd17 ldw r2,-12(fp) + 802e74c: 10800a04 addi r2,r2,40 + 802e750: 100b883a mov r5,r2 + 802e754: e13ffd17 ldw r4,-12(fp) + 802e758: 802f94c0 call 802f94c + so->so_error = s; + 802e75c: e0bffd17 ldw r2,-12(fp) + 802e760: e0fffe17 ldw r3,-8(fp) + 802e764: 10c00615 stw r3,24(r2) +} + 802e768: 0001883a nop + 802e76c: e037883a mov sp,fp + 802e770: dfc00117 ldw ra,4(sp) + 802e774: df000017 ldw fp,0(sp) + 802e778: dec00204 addi sp,sp,8 + 802e77c: f800283a ret + +0802e780 : + +int +sosetopt(struct socket * so, + int optname, + void * arg) +{ + 802e780: defff604 addi sp,sp,-40 + 802e784: dfc00915 stw ra,36(sp) + 802e788: df000815 stw fp,32(sp) + 802e78c: df000804 addi fp,sp,32 + 802e790: e13ffa15 stw r4,-24(fp) + 802e794: e17ff915 stw r5,-28(fp) + 802e798: e1bff815 stw r6,-32(fp) + int error = 0; + 802e79c: e03fff15 stw zero,-4(fp) + + switch (optname) + 802e7a0: e0bff917 ldw r2,-28(fp) + 802e7a4: 10808020 cmpeqi r2,r2,512 + 802e7a8: 1000521e bne r2,zero,802e8f4 + 802e7ac: e0bff917 ldw r2,-28(fp) + 802e7b0: 10808048 cmpgei r2,r2,513 + 802e7b4: 1000211e bne r2,zero,802e83c + 802e7b8: e0bff917 ldw r2,-28(fp) + 802e7bc: 10800388 cmpgei r2,r2,14 + 802e7c0: 10000d1e bne r2,zero,802e7f8 + 802e7c4: e0bff917 ldw r2,-28(fp) + 802e7c8: 10800248 cmpgei r2,r2,9 + 802e7cc: 1000971e bne r2,zero,802ea2c + 802e7d0: e0bff917 ldw r2,-28(fp) + 802e7d4: 10800120 cmpeqi r2,r2,4 + 802e7d8: 1000461e bne r2,zero,802e8f4 + 802e7dc: e0bff917 ldw r2,-28(fp) + 802e7e0: 10800220 cmpeqi r2,r2,8 + 802e7e4: 1000431e bne r2,zero,802e8f4 + 802e7e8: e0bff917 ldw r2,-28(fp) + 802e7ec: 108000a0 cmpeqi r2,r2,2 + 802e7f0: 1000941e bne r2,zero,802ea44 + 802e7f4: 0000fb06 br 802ebe4 + 802e7f8: e0bff917 ldw r2,-28(fp) + 802e7fc: 10800820 cmpeqi r2,r2,32 + 802e800: 10003c1e bne r2,zero,802e8f4 + 802e804: e0bff917 ldw r2,-28(fp) + 802e808: 10800848 cmpgei r2,r2,33 + 802e80c: 1000041e bne r2,zero,802e820 + 802e810: e0bff917 ldw r2,-28(fp) + 802e814: 10800420 cmpeqi r2,r2,16 + 802e818: 1000361e bne r2,zero,802e8f4 + 802e81c: 0000f106 br 802ebe4 + 802e820: e0bff917 ldw r2,-28(fp) + 802e824: 10802020 cmpeqi r2,r2,128 + 802e828: 10002d1e bne r2,zero,802e8e0 + 802e82c: e0bff917 ldw r2,-28(fp) + 802e830: 10804020 cmpeqi r2,r2,256 + 802e834: 10002f1e bne r2,zero,802e8f4 + 802e838: 0000ea06 br 802ebe4 + 802e83c: e0bff917 ldw r2,-28(fp) + 802e840: 10840520 cmpeqi r2,r2,4116 + 802e844: 1000531e bne r2,zero,802e994 + 802e848: e0bff917 ldw r2,-28(fp) + 802e84c: 10840548 cmpgei r2,r2,4117 + 802e850: 10000f1e bne r2,zero,802e890 + 802e854: e0bff917 ldw r2,-28(fp) + 802e858: 108401a0 cmpeqi r2,r2,4102 + 802e85c: 1000481e bne r2,zero,802e980 + 802e860: e0bff917 ldw r2,-28(fp) + 802e864: 108401c8 cmpgei r2,r2,4103 + 802e868: 1000051e bne r2,zero,802e880 + 802e86c: e0bff917 ldw r2,-28(fp) + 802e870: 10bbffc4 addi r2,r2,-4097 + 802e874: 108000a8 cmpgeui r2,r2,2 + 802e878: 1000da1e bne r2,zero,802ebe4 + 802e87c: 00002f06 br 802e93c + 802e880: e0bff917 ldw r2,-28(fp) + 802e884: 10840420 cmpeqi r2,r2,4112 + 802e888: 1000af1e bne r2,zero,802eb48 + 802e88c: 0000d506 br 802ebe4 + 802e890: e0bff917 ldw r2,-28(fp) + 802e894: 108800e0 cmpeqi r2,r2,8195 + 802e898: 1000ab1e bne r2,zero,802eb48 + 802e89c: e0bff917 ldw r2,-28(fp) + 802e8a0: 10880108 cmpgei r2,r2,8196 + 802e8a4: 1000071e bne r2,zero,802e8c4 + 802e8a8: e0bff917 ldw r2,-28(fp) + 802e8ac: 10840560 cmpeqi r2,r2,4117 + 802e8b0: 10003f1e bne r2,zero,802e9b0 + 802e8b4: e0bff917 ldw r2,-28(fp) + 802e8b8: 108405a0 cmpeqi r2,r2,4118 + 802e8bc: 1000441e bne r2,zero,802e9d0 + 802e8c0: 0000c806 br 802ebe4 + 802e8c4: e0bff917 ldw r2,-28(fp) + 802e8c8: 10880120 cmpeqi r2,r2,8196 + 802e8cc: 1000721e bne r2,zero,802ea98 + 802e8d0: e0bff917 ldw r2,-28(fp) + 802e8d4: 10900020 cmpeqi r2,r2,16384 + 802e8d8: 1000061e bne r2,zero,802e8f4 + 802e8dc: 0000c106 br 802ebe4 + { + case SO_LINGER: + so->so_linger = (short)((struct linger *)arg)->l_linger; + 802e8e0: e0bff817 ldw r2,-32(fp) + 802e8e4: 10800117 ldw r2,4(r2) + 802e8e8: 1007883a mov r3,r2 + 802e8ec: e0bffa17 ldw r2,-24(fp) + 802e8f0: 10c0080d sth r3,32(r2) + case SO_TCPSACK: + case SO_NOSLOWSTART: +#ifdef SUPPORT_SO_FULLMSS + case SO_FULLMSS: +#endif + if (*(int *)arg) + 802e8f4: e0bff817 ldw r2,-32(fp) + 802e8f8: 10800017 ldw r2,0(r2) + 802e8fc: 10000726 beq r2,zero,802e91c + so->so_options |= optname; + 802e900: e0bffa17 ldw r2,-24(fp) + 802e904: 10c00417 ldw r3,16(r2) + 802e908: e0bff917 ldw r2,-28(fp) + 802e90c: 1886b03a or r3,r3,r2 + 802e910: e0bffa17 ldw r2,-24(fp) + 802e914: 10c00415 stw r3,16(r2) + else + so->so_options &= ~optname; + break; + 802e918: 0000b606 br 802ebf4 + so->so_options &= ~optname; + 802e91c: e0bffa17 ldw r2,-24(fp) + 802e920: 10800417 ldw r2,16(r2) + 802e924: e0fff917 ldw r3,-28(fp) + 802e928: 00c6303a nor r3,zero,r3 + 802e92c: 10c6703a and r3,r2,r3 + 802e930: e0bffa17 ldw r2,-24(fp) + 802e934: 10c00415 stw r3,16(r2) + break; + 802e938: 0000ae06 br 802ebf4 + break; +#endif /* TCP_BIGCWND */ + + case SO_SNDBUF: + case SO_RCVBUF: + if (sbreserve(optname == SO_SNDBUF ? + 802e93c: e0bff917 ldw r2,-28(fp) + 802e940: 10840058 cmpnei r2,r2,4097 + 802e944: 1000031e bne r2,zero,802e954 + 802e948: e0bffa17 ldw r2,-24(fp) + 802e94c: 10801204 addi r2,r2,72 + 802e950: 00000206 br 802e95c + 802e954: e0bffa17 ldw r2,-24(fp) + 802e958: 10800a04 addi r2,r2,40 + &so->so_snd : &so->so_rcv, + (u_long) * (int *)arg) == 0) + 802e95c: e0fff817 ldw r3,-32(fp) + 802e960: 18c00017 ldw r3,0(r3) + if (sbreserve(optname == SO_SNDBUF ? + 802e964: 180b883a mov r5,r3 + 802e968: 1009883a mov r4,r2 + 802e96c: 802fa600 call 802fa60 + 802e970: 10009f1e bne r2,zero,802ebf0 + { + error = ENOBUFS; + 802e974: 00801a44 movi r2,105 + 802e978: e0bfff15 stw r2,-4(fp) + goto bad; + 802e97c: 00009d06 br 802ebf4 + } + break; + + case SO_RCVTIMEO: + so->so_rcv.sb_timeo = *(short *)arg; + 802e980: e0bff817 ldw r2,-32(fp) + 802e984: 10c0000b ldhu r3,0(r2) + 802e988: e0bffa17 ldw r2,-24(fp) + 802e98c: 10c0118d sth r3,70(r2) + break; + 802e990: 00009806 br 802ebf4 + + case SO_NBIO: /* set socket into NON-blocking mode */ + so->so_state |= SS_NBIO; + 802e994: e0bffa17 ldw r2,-24(fp) + 802e998: 1080088b ldhu r2,34(r2) + 802e99c: 10804014 ori r2,r2,256 + 802e9a0: 1007883a mov r3,r2 + 802e9a4: e0bffa17 ldw r2,-24(fp) + 802e9a8: 10c0088d sth r3,34(r2) + break; + 802e9ac: 00009106 br 802ebf4 + + case SO_BIO: /* set socket into blocking mode */ + so->so_state &= ~SS_NBIO; + 802e9b0: e0bffa17 ldw r2,-24(fp) + 802e9b4: 10c0088b ldhu r3,34(r2) + 802e9b8: 00bfbfc4 movi r2,-257 + 802e9bc: 1884703a and r2,r3,r2 + 802e9c0: 1007883a mov r3,r2 + 802e9c4: e0bffa17 ldw r2,-24(fp) + 802e9c8: 10c0088d sth r3,34(r2) + break; + 802e9cc: 00008906 br 802ebf4 + + case SO_NONBLOCK: /* set blocking mode according to arg */ + /* sanity check the arg parameter */ + if (!arg) + 802e9d0: e0bff817 ldw r2,-32(fp) + 802e9d4: 1000031e bne r2,zero,802e9e4 + { + error = ENP_PARAM; + 802e9d8: 00bffd84 movi r2,-10 + 802e9dc: e0bfff15 stw r2,-4(fp) + break; + 802e9e0: 00008406 br 802ebf4 + } + /* if contents of integer addressed by arg are non-zero */ + if (*(int *) arg) + 802e9e4: e0bff817 ldw r2,-32(fp) + 802e9e8: 10800017 ldw r2,0(r2) + 802e9ec: 10000726 beq r2,zero,802ea0c + so->so_state |= SS_NBIO; /* set non-blocking mode */ + 802e9f0: e0bffa17 ldw r2,-24(fp) + 802e9f4: 1080088b ldhu r2,34(r2) + 802e9f8: 10804014 ori r2,r2,256 + 802e9fc: 1007883a mov r3,r2 + 802ea00: e0bffa17 ldw r2,-24(fp) + 802ea04: 10c0088d sth r3,34(r2) + else + so->so_state &= ~SS_NBIO; /* set blocking mode */ + break; + 802ea08: 00007a06 br 802ebf4 + so->so_state &= ~SS_NBIO; /* set blocking mode */ + 802ea0c: e0bffa17 ldw r2,-24(fp) + 802ea10: 10c0088b ldhu r3,34(r2) + 802ea14: 00bfbfc4 movi r2,-257 + 802ea18: 1884703a and r2,r3,r2 + 802ea1c: 1007883a mov r3,r2 + 802ea20: e0bffa17 ldw r2,-24(fp) + 802ea24: 10c0088d sth r3,34(r2) + break; + 802ea28: 00007206 br 802ebf4 + case IP_MULTICAST_IF: + case IP_MULTICAST_TTL: + case IP_MULTICAST_LOOP: + case IP_ADD_MEMBERSHIP: + case IP_DROP_MEMBERSHIP: + error = ip_setmoptions(optname, so, arg); + 802ea2c: e1bff817 ldw r6,-32(fp) + 802ea30: e17ffa17 ldw r5,-24(fp) + 802ea34: e13ff917 ldw r4,-28(fp) + 802ea38: 803e7c40 call 803e7c4 + 802ea3c: e0bfff15 stw r2,-4(fp) + break; + 802ea40: 00006c06 br 802ebf4 + +#ifdef IP_RAW + + case IP_HDRINCL: + /* try to make sure that the argument pointer is valid */ + if (arg == NULL) + 802ea44: e0bff817 ldw r2,-32(fp) + 802ea48: 1000031e bne r2,zero,802ea58 + { + error = ENP_PARAM; + 802ea4c: 00bffd84 movi r2,-10 + 802ea50: e0bfff15 stw r2,-4(fp) + break; + 802ea54: 00006706 br 802ebf4 + } + /* set the socket option flag based on the pointed-to argument */ + if (*(int *)arg) + 802ea58: e0bff817 ldw r2,-32(fp) + 802ea5c: 10800017 ldw r2,0(r2) + 802ea60: 10000626 beq r2,zero,802ea7c + so->so_options |= SO_HDRINCL; + 802ea64: e0bffa17 ldw r2,-24(fp) + 802ea68: 10800417 ldw r2,16(r2) + 802ea6c: 10c80014 ori r3,r2,8192 + 802ea70: e0bffa17 ldw r2,-24(fp) + 802ea74: 10c00415 stw r3,16(r2) + else + so->so_options &= ~SO_HDRINCL; + break; + 802ea78: 00005e06 br 802ebf4 + so->so_options &= ~SO_HDRINCL; + 802ea7c: e0bffa17 ldw r2,-24(fp) + 802ea80: 10c00417 ldw r3,16(r2) + 802ea84: 00b7ffc4 movi r2,-8193 + 802ea88: 1886703a and r3,r3,r2 + 802ea8c: e0bffa17 ldw r2,-24(fp) + 802ea90: 10c00415 stw r3,16(r2) + break; + 802ea94: 00005706 br 802ebf4 + case TCP_NODELAY: + { + struct inpcb * inp; + struct tcpcb * tp; + + if(so->so_type != SOCK_STREAM) + 802ea98: e0bffa17 ldw r2,-24(fp) + 802ea9c: 10800983 ldbu r2,38(r2) + 802eaa0: 10803fcc andi r2,r2,255 + 802eaa4: 1080201c xori r2,r2,128 + 802eaa8: 10bfe004 addi r2,r2,-128 + 802eaac: 10800060 cmpeqi r2,r2,1 + 802eab0: 1000031e bne r2,zero,802eac0 + { + error = EINVAL; + 802eab4: 00800584 movi r2,22 + 802eab8: e0bfff15 stw r2,-4(fp) + break; + 802eabc: 00004d06 br 802ebf4 + } + inp = (struct inpcb *)(so->so_pcb); + 802eac0: e0bffa17 ldw r2,-24(fp) + 802eac4: 10800117 ldw r2,4(r2) + 802eac8: e0bffe15 stw r2,-8(fp) + tp = intotcpcb(inp); + 802eacc: e0bffe17 ldw r2,-8(fp) + 802ead0: 10800917 ldw r2,36(r2) + 802ead4: e0bffd15 stw r2,-12(fp) + if(!tp) + 802ead8: e0bffd17 ldw r2,-12(fp) + 802eadc: 1000031e bne r2,zero,802eaec + { + error = ENOTCONN; + 802eae0: 00802004 movi r2,128 + 802eae4: e0bfff15 stw r2,-4(fp) + break; + 802eae8: 00004206 br 802ebf4 + } + /* try to make sure that the argument pointer is valid */ + if (arg == NULL) + 802eaec: e0bff817 ldw r2,-32(fp) + 802eaf0: 1000031e bne r2,zero,802eb00 + { + error = ENP_PARAM; + 802eaf4: 00bffd84 movi r2,-10 + 802eaf8: e0bfff15 stw r2,-4(fp) + break; + 802eafc: 00003d06 br 802ebf4 + } + /* if contents of integer addressed by arg are non-zero */ + if (*(int *) arg) + 802eb00: e0bff817 ldw r2,-32(fp) + 802eb04: 10800017 ldw r2,0(r2) + 802eb08: 10000726 beq r2,zero,802eb28 + tp->t_flags |= TF_NODELAY; /* Disable Nagle Algorithm */ + 802eb0c: e0bffd17 ldw r2,-12(fp) + 802eb10: 10800b0b ldhu r2,44(r2) + 802eb14: 10800114 ori r2,r2,4 + 802eb18: 1007883a mov r3,r2 + 802eb1c: e0bffd17 ldw r2,-12(fp) + 802eb20: 10c00b0d sth r3,44(r2) + else + tp->t_flags &= ~TF_NODELAY; /* Enable Nagle Algorithm */ + + break; + 802eb24: 00003306 br 802ebf4 + tp->t_flags &= ~TF_NODELAY; /* Enable Nagle Algorithm */ + 802eb28: e0bffd17 ldw r2,-12(fp) + 802eb2c: 10c00b0b ldhu r3,44(r2) + 802eb30: 00bffec4 movi r2,-5 + 802eb34: 1884703a and r2,r3,r2 + 802eb38: 1007883a mov r3,r2 + 802eb3c: e0bffd17 ldw r2,-12(fp) + 802eb40: 10c00b0d sth r3,44(r2) + break; + 802eb44: 00002b06 br 802ebf4 + case TCP_MAXSEG: + { + struct inpcb * inp; + struct tcpcb * tp; + + if(so->so_type != SOCK_STREAM) + 802eb48: e0bffa17 ldw r2,-24(fp) + 802eb4c: 10800983 ldbu r2,38(r2) + 802eb50: 10803fcc andi r2,r2,255 + 802eb54: 1080201c xori r2,r2,128 + 802eb58: 10bfe004 addi r2,r2,-128 + 802eb5c: 10800060 cmpeqi r2,r2,1 + 802eb60: 1000031e bne r2,zero,802eb70 + { + error = EINVAL; + 802eb64: 00800584 movi r2,22 + 802eb68: e0bfff15 stw r2,-4(fp) + break; + 802eb6c: 00002106 br 802ebf4 + } + inp = (struct inpcb *)(so->so_pcb); + 802eb70: e0bffa17 ldw r2,-24(fp) + 802eb74: 10800117 ldw r2,4(r2) + 802eb78: e0bffc15 stw r2,-16(fp) + tp = intotcpcb(inp); + 802eb7c: e0bffc17 ldw r2,-16(fp) + 802eb80: 10800917 ldw r2,36(r2) + 802eb84: e0bffb15 stw r2,-20(fp) + if(!tp) + 802eb88: e0bffb17 ldw r2,-20(fp) + 802eb8c: 1000031e bne r2,zero,802eb9c + { + error = ENOTCONN; + 802eb90: 00802004 movi r2,128 + 802eb94: e0bfff15 stw r2,-4(fp) + break; + 802eb98: 00001606 br 802ebf4 + } + if (tp->t_state != TCPS_CLOSED) + 802eb9c: e0bffb17 ldw r2,-20(fp) + 802eba0: 10800217 ldw r2,8(r2) + 802eba4: 10000326 beq r2,zero,802ebb4 + { + error = EINVAL; + 802eba8: 00800584 movi r2,22 + 802ebac: e0bfff15 stw r2,-4(fp) + break; + 802ebb0: 00001006 br 802ebf4 + } + tp->t_maxseg = *(int*)(arg); /* set TCP MSS */ + 802ebb4: e0bff817 ldw r2,-32(fp) + 802ebb8: 10800017 ldw r2,0(r2) + 802ebbc: 1007883a mov r3,r2 + 802ebc0: e0bffb17 ldw r2,-20(fp) + 802ebc4: 10c00a0d sth r3,40(r2) + tp->t_flags |= TF_MAXSEG; /* mark as user set max seg */ + 802ebc8: e0bffb17 ldw r2,-20(fp) + 802ebcc: 10800b0b ldhu r2,44(r2) + 802ebd0: 10810014 ori r2,r2,1024 + 802ebd4: 1007883a mov r3,r2 + 802ebd8: e0bffb17 ldw r2,-20(fp) + 802ebdc: 10c00b0d sth r3,44(r2) + break; + 802ebe0: 00000406 br 802ebf4 + } + default: + error = ENOPROTOOPT; + 802ebe4: 00801b44 movi r2,109 + 802ebe8: e0bfff15 stw r2,-4(fp) + break; + 802ebec: 00000106 br 802ebf4 + break; + 802ebf0: 0001883a nop + } +bad: + return (error); + 802ebf4: e0bfff17 ldw r2,-4(fp) +} + 802ebf8: e037883a mov sp,fp + 802ebfc: dfc00117 ldw ra,4(sp) + 802ec00: df000017 ldw fp,0(sp) + 802ec04: dec00204 addi sp,sp,8 + 802ec08: f800283a ret + +0802ec0c : + +int +sogetopt(struct socket * so, + int optname, + void * val) +{ + 802ec0c: defff504 addi sp,sp,-44 + 802ec10: dfc00a15 stw ra,40(sp) + 802ec14: df000915 stw fp,36(sp) + 802ec18: df000904 addi fp,sp,36 + 802ec1c: e13ff915 stw r4,-28(fp) + 802ec20: e17ff815 stw r5,-32(fp) + 802ec24: e1bff715 stw r6,-36(fp) + int error = 0; + 802ec28: e03fff15 stw zero,-4(fp) + + /* sanity check the val parameter */ + if (!val) + 802ec2c: e0bff717 ldw r2,-36(fp) + 802ec30: 1000021e bne r2,zero,802ec3c + { + return ENP_PARAM; + 802ec34: 00bffd84 movi r2,-10 + 802ec38: 00013706 br 802f118 + } + + switch (optname) + 802ec3c: e0bff817 ldw r2,-32(fp) + 802ec40: 108400e0 cmpeqi r2,r2,4099 + 802ec44: 10008e1e bne r2,zero,802ee80 + 802ec48: e0bff817 ldw r2,-32(fp) + 802ec4c: 10840108 cmpgei r2,r2,4100 + 802ec50: 10002e1e bne r2,zero,802ed0c + 802ec54: e0bff817 ldw r2,-32(fp) + 802ec58: 10800420 cmpeqi r2,r2,16 + 802ec5c: 1000801e bne r2,zero,802ee60 + 802ec60: e0bff817 ldw r2,-32(fp) + 802ec64: 10800448 cmpgei r2,r2,17 + 802ec68: 1000111e bne r2,zero,802ecb0 + 802ec6c: e0bff817 ldw r2,-32(fp) + 802ec70: 10800220 cmpeqi r2,r2,8 + 802ec74: 10007a1e bne r2,zero,802ee60 + 802ec78: e0bff817 ldw r2,-32(fp) + 802ec7c: 10800248 cmpgei r2,r2,9 + 802ec80: 1000071e bne r2,zero,802eca0 + 802ec84: e0bff817 ldw r2,-32(fp) + 802ec88: 108000a0 cmpeqi r2,r2,2 + 802ec8c: 1000ee1e bne r2,zero,802f048 + 802ec90: e0bff817 ldw r2,-32(fp) + 802ec94: 10800120 cmpeqi r2,r2,4 + 802ec98: 1000711e bne r2,zero,802ee60 + 802ec9c: 00011b06 br 802f10c + 802eca0: e0bff817 ldw r2,-32(fp) + 802eca4: 10800308 cmpgei r2,r2,12 + 802eca8: 1001181e bne r2,zero,802f10c + 802ecac: 0000e006 br 802f030 + 802ecb0: e0bff817 ldw r2,-32(fp) + 802ecb4: 10804020 cmpeqi r2,r2,256 + 802ecb8: 1000691e bne r2,zero,802ee60 + 802ecbc: e0bff817 ldw r2,-32(fp) + 802ecc0: 10804048 cmpgei r2,r2,257 + 802ecc4: 1000071e bne r2,zero,802ece4 + 802ecc8: e0bff817 ldw r2,-32(fp) + 802eccc: 10800820 cmpeqi r2,r2,32 + 802ecd0: 1000631e bne r2,zero,802ee60 + 802ecd4: e0bff817 ldw r2,-32(fp) + 802ecd8: 10802020 cmpeqi r2,r2,128 + 802ecdc: 1000511e bne r2,zero,802ee24 + 802ece0: 00010a06 br 802f10c + 802ece4: e0bff817 ldw r2,-32(fp) + 802ece8: 10840060 cmpeqi r2,r2,4097 + 802ecec: 1000701e bne r2,zero,802eeb0 + 802ecf0: e0bff817 ldw r2,-32(fp) + 802ecf4: 10840088 cmpgei r2,r2,4098 + 802ecf8: 1000731e bne r2,zero,802eec8 + 802ecfc: e0bff817 ldw r2,-32(fp) + 802ed00: 10808020 cmpeqi r2,r2,512 + 802ed04: 1000561e bne r2,zero,802ee60 + 802ed08: 00010006 br 802f10c + 802ed0c: e0bff817 ldw r2,-32(fp) + 802ed10: 10840420 cmpeqi r2,r2,4112 + 802ed14: 10008d1e bne r2,zero,802ef4c + 802ed18: e0bff817 ldw r2,-32(fp) + 802ed1c: 10840448 cmpgei r2,r2,4113 + 802ed20: 1000171e bne r2,zero,802ed80 + 802ed24: e0bff817 ldw r2,-32(fp) + 802ed28: 108401a0 cmpeqi r2,r2,4102 + 802ed2c: 1000a71e bne r2,zero,802efcc + 802ed30: e0bff817 ldw r2,-32(fp) + 802ed34: 108401c8 cmpgei r2,r2,4103 + 802ed38: 1000071e bne r2,zero,802ed58 + 802ed3c: e0bff817 ldw r2,-32(fp) + 802ed40: 10840120 cmpeqi r2,r2,4100 + 802ed44: 1000541e bne r2,zero,802ee98 + 802ed48: e0bff817 ldw r2,-32(fp) + 802ed4c: 10840160 cmpeqi r2,r2,4101 + 802ed50: 1000991e bne r2,zero,802efb8 + 802ed54: 0000ed06 br 802f10c + 802ed58: e0bff817 ldw r2,-32(fp) + 802ed5c: 10840220 cmpeqi r2,r2,4104 + 802ed60: 10006b1e bne r2,zero,802ef10 + 802ed64: e0bff817 ldw r2,-32(fp) + 802ed68: 10840210 cmplti r2,r2,4104 + 802ed6c: 1000701e bne r2,zero,802ef30 + 802ed70: e0bff817 ldw r2,-32(fp) + 802ed74: 10840260 cmpeqi r2,r2,4105 + 802ed78: 1000991e bne r2,zero,802efe0 + 802ed7c: 0000e306 br 802f10c + 802ed80: e0bff817 ldw r2,-32(fp) + 802ed84: 108404e0 cmpeqi r2,r2,4115 + 802ed88: 1000141e bne r2,zero,802eddc + 802ed8c: e0bff817 ldw r2,-32(fp) + 802ed90: 10840508 cmpgei r2,r2,4116 + 802ed94: 1000071e bne r2,zero,802edb4 + 802ed98: e0bff817 ldw r2,-32(fp) + 802ed9c: 10840460 cmpeqi r2,r2,4113 + 802eda0: 10004f1e bne r2,zero,802eee0 + 802eda4: e0bff817 ldw r2,-32(fp) + 802eda8: 108404a0 cmpeqi r2,r2,4114 + 802edac: 1000521e bne r2,zero,802eef8 + 802edb0: 0000d606 br 802f10c + 802edb4: e0bff817 ldw r2,-32(fp) + 802edb8: 108800e0 cmpeqi r2,r2,8195 + 802edbc: 1000631e bne r2,zero,802ef4c + 802edc0: e0bff817 ldw r2,-32(fp) + 802edc4: 10880120 cmpeqi r2,r2,8196 + 802edc8: 1000aa1e bne r2,zero,802f074 + 802edcc: e0bff817 ldw r2,-32(fp) + 802edd0: 108405a0 cmpeqi r2,r2,4118 + 802edd4: 10008a1e bne r2,zero,802f000 + 802edd8: 0000cc06 br 802f10c + { + case SO_MYADDR: + /* Get my IP address. */ + if (so->so_state & SS_ISCONNECTED) + 802eddc: e0bff917 ldw r2,-28(fp) + 802ede0: 1080088b ldhu r2,34(r2) + 802ede4: 10bfffcc andi r2,r2,65535 + 802ede8: 1080008c andi r2,r2,2 + 802edec: 10000726 beq r2,zero,802ee0c + { + *(u_long *)val = so->so_pcb->ifp->n_ipaddr; + 802edf0: e0bff917 ldw r2,-28(fp) + 802edf4: 10800117 ldw r2,4(r2) + 802edf8: 10800a17 ldw r2,40(r2) + 802edfc: 10c00a17 ldw r3,40(r2) + 802ee00: e0bff717 ldw r2,-36(fp) + 802ee04: 10c00015 stw r3,0(r2) + } + else /* not connected, use first iface */ + *(u_long *)val = nets[0]->n_ipaddr; + break; + 802ee08: 0000c206 br 802f114 + *(u_long *)val = nets[0]->n_ipaddr; + 802ee0c: 008201b4 movhi r2,2054 + 802ee10: 10b77017 ldw r2,-8768(r2) + 802ee14: 10c00a17 ldw r3,40(r2) + 802ee18: e0bff717 ldw r2,-36(fp) + 802ee1c: 10c00015 stw r3,0(r2) + break; + 802ee20: 0000bc06 br 802f114 + case SO_LINGER: + { + struct linger * l = (struct linger *)val; + 802ee24: e0bff717 ldw r2,-36(fp) + 802ee28: e0bffe15 stw r2,-8(fp) + l->l_onoff = so->so_options & SO_LINGER; + 802ee2c: e0bff917 ldw r2,-28(fp) + 802ee30: 10800417 ldw r2,16(r2) + 802ee34: 10c0200c andi r3,r2,128 + 802ee38: e0bffe17 ldw r2,-8(fp) + 802ee3c: 10c00015 stw r3,0(r2) + l->l_linger = so->so_linger; + 802ee40: e0bff917 ldw r2,-28(fp) + 802ee44: 1080080b ldhu r2,32(r2) + 802ee48: 10ffffcc andi r3,r2,65535 + 802ee4c: 18e0001c xori r3,r3,32768 + 802ee50: 18e00004 addi r3,r3,-32768 + 802ee54: e0bffe17 ldw r2,-8(fp) + 802ee58: 10c00115 stw r3,4(r2) + } + break; + 802ee5c: 0000ad06 br 802f114 + case SO_OOBINLINE: + case SO_DONTROUTE: + case SO_REUSEADDR: + case SO_BROADCAST: + case SO_TCPSACK: + *(int *)val = so->so_options & optname; + 802ee60: e0bff917 ldw r2,-28(fp) + 802ee64: 10c00417 ldw r3,16(r2) + 802ee68: e0bff817 ldw r2,-32(fp) + 802ee6c: 1884703a and r2,r3,r2 + 802ee70: 1007883a mov r3,r2 + 802ee74: e0bff717 ldw r2,-36(fp) + 802ee78: 10c00015 stw r3,0(r2) + break; + 802ee7c: 0000a506 br 802f114 + + case SO_SNDLOWAT: + *(int *)val = (int)so->so_snd.sb_lowat; + 802ee80: e0bff917 ldw r2,-28(fp) + 802ee84: 10801617 ldw r2,88(r2) + 802ee88: 1007883a mov r3,r2 + 802ee8c: e0bff717 ldw r2,-36(fp) + 802ee90: 10c00015 stw r3,0(r2) + break; + 802ee94: 00009f06 br 802f114 + + case SO_RCVLOWAT: + *(int *)val = (int)so->so_rcv.sb_lowat; + 802ee98: e0bff917 ldw r2,-28(fp) + 802ee9c: 10800e17 ldw r2,56(r2) + 802eea0: 1007883a mov r3,r2 + 802eea4: e0bff717 ldw r2,-36(fp) + 802eea8: 10c00015 stw r3,0(r2) + break; + 802eeac: 00009906 br 802f114 + + case SO_SNDBUF: + *(int *)val = (int)so->so_snd.sb_hiwat; + 802eeb0: e0bff917 ldw r2,-28(fp) + 802eeb4: 10801317 ldw r2,76(r2) + 802eeb8: 1007883a mov r3,r2 + 802eebc: e0bff717 ldw r2,-36(fp) + 802eec0: 10c00015 stw r3,0(r2) + break; + 802eec4: 00009306 br 802f114 + + case SO_RCVBUF: + *(int *)val = (int)so->so_rcv.sb_hiwat; + 802eec8: e0bff917 ldw r2,-28(fp) + 802eecc: 10800b17 ldw r2,44(r2) + 802eed0: 1007883a mov r3,r2 + 802eed4: e0bff717 ldw r2,-36(fp) + 802eed8: 10c00015 stw r3,0(r2) + break; + 802eedc: 00008d06 br 802f114 + + case SO_RXDATA: /* added, JB */ + *(int *)val = (int)so->so_rcv.sb_cc; + 802eee0: e0bff917 ldw r2,-28(fp) + 802eee4: 10800a17 ldw r2,40(r2) + 802eee8: 1007883a mov r3,r2 + 802eeec: e0bff717 ldw r2,-36(fp) + 802eef0: 10c00015 stw r3,0(r2) + break; + 802eef4: 00008706 br 802f114 + + case SO_TXDATA: /* added for rel 1.8 */ + *(int *)val = (int)so->so_snd.sb_cc; + 802eef8: e0bff917 ldw r2,-28(fp) + 802eefc: 10801217 ldw r2,72(r2) + 802ef00: 1007883a mov r3,r2 + 802ef04: e0bff717 ldw r2,-36(fp) + 802ef08: 10c00015 stw r3,0(r2) + break; + 802ef0c: 00008106 br 802f114 + + case SO_TYPE: + *(int *)val = so->so_type; + 802ef10: e0bff917 ldw r2,-28(fp) + 802ef14: 10800983 ldbu r2,38(r2) + 802ef18: 10c03fcc andi r3,r2,255 + 802ef1c: 18c0201c xori r3,r3,128 + 802ef20: 18ffe004 addi r3,r3,-128 + 802ef24: e0bff717 ldw r2,-36(fp) + 802ef28: 10c00015 stw r3,0(r2) + break; + 802ef2c: 00007906 br 802f114 + + case SO_ERROR: + *(int *)val = so->so_error; + 802ef30: e0bff917 ldw r2,-28(fp) + 802ef34: 10c00617 ldw r3,24(r2) + 802ef38: e0bff717 ldw r2,-36(fp) + 802ef3c: 10c00015 stw r3,0(r2) + so->so_error = 0; + 802ef40: e0bff917 ldw r2,-28(fp) + 802ef44: 10000615 stw zero,24(r2) + break; + 802ef48: 00007206 br 802f114 + case TCP_MAXSEG: + { + struct inpcb * inp; + struct tcpcb * tp; + + if(so->so_type != SOCK_STREAM) + 802ef4c: e0bff917 ldw r2,-28(fp) + 802ef50: 10800983 ldbu r2,38(r2) + 802ef54: 10803fcc andi r2,r2,255 + 802ef58: 1080201c xori r2,r2,128 + 802ef5c: 10bfe004 addi r2,r2,-128 + 802ef60: 10800060 cmpeqi r2,r2,1 + 802ef64: 1000031e bne r2,zero,802ef74 + { + error = EINVAL; + 802ef68: 00800584 movi r2,22 + 802ef6c: e0bfff15 stw r2,-4(fp) + break; + 802ef70: 00006806 br 802f114 + } + inp = (struct inpcb *)(so->so_pcb); + 802ef74: e0bff917 ldw r2,-28(fp) + 802ef78: 10800117 ldw r2,4(r2) + 802ef7c: e0bffd15 stw r2,-12(fp) + tp = intotcpcb(inp); + 802ef80: e0bffd17 ldw r2,-12(fp) + 802ef84: 10800917 ldw r2,36(r2) + 802ef88: e0bffc15 stw r2,-16(fp) + if(!tp) + 802ef8c: e0bffc17 ldw r2,-16(fp) + 802ef90: 1000031e bne r2,zero,802efa0 + { + error = ENOTCONN; + 802ef94: 00802004 movi r2,128 + 802ef98: e0bfff15 stw r2,-4(fp) + break; + 802ef9c: 00005d06 br 802f114 + } + *(int *)val = tp->t_maxseg; /* Fill in TCP MSS for current socket */ + 802efa0: e0bffc17 ldw r2,-16(fp) + 802efa4: 10800a0b ldhu r2,40(r2) + 802efa8: 10ffffcc andi r3,r2,65535 + 802efac: e0bff717 ldw r2,-36(fp) + 802efb0: 10c00015 stw r3,0(r2) + break; + 802efb4: 00005706 br 802f114 + } + + case SO_SNDTIMEO: + *(short*)val = so->so_snd.sb_timeo; + 802efb8: e0bff917 ldw r2,-28(fp) + 802efbc: 10c0198b ldhu r3,102(r2) + 802efc0: e0bff717 ldw r2,-36(fp) + 802efc4: 10c0000d sth r3,0(r2) + break; + 802efc8: 00005206 br 802f114 + + case SO_RCVTIMEO: + *(short*)val = so->so_rcv.sb_timeo; + 802efcc: e0bff917 ldw r2,-28(fp) + 802efd0: 10c0118b ldhu r3,70(r2) + 802efd4: e0bff717 ldw r2,-36(fp) + 802efd8: 10c0000d sth r3,0(r2) + break; + 802efdc: 00004d06 br 802f114 + + case SO_HOPCNT: + *(int *)val = so->so_hopcnt; + 802efe0: e0bff917 ldw r2,-28(fp) + 802efe4: 108009c3 ldbu r2,39(r2) + 802efe8: 10c03fcc andi r3,r2,255 + 802efec: 18c0201c xori r3,r3,128 + 802eff0: 18ffe004 addi r3,r3,-128 + 802eff4: e0bff717 ldw r2,-36(fp) + 802eff8: 10c00015 stw r3,0(r2) + break; + 802effc: 00004506 br 802f114 + + case SO_NONBLOCK: /* get blocking mode according to val */ + /* if the non-blocking I/O bit is set in the state */ + if (so->so_state & SS_NBIO) + 802f000: e0bff917 ldw r2,-28(fp) + 802f004: 1080088b ldhu r2,34(r2) + 802f008: 10bfffcc andi r2,r2,65535 + 802f00c: 1080400c andi r2,r2,256 + 802f010: 10000426 beq r2,zero,802f024 + *(int *)val = 1; /* return 1 in val */ + 802f014: e0bff717 ldw r2,-36(fp) + 802f018: 00c00044 movi r3,1 + 802f01c: 10c00015 stw r3,0(r2) + else + *(int *)val = 0; /* return 0 in val */ + break; + 802f020: 00003c06 br 802f114 + *(int *)val = 0; /* return 0 in val */ + 802f024: e0bff717 ldw r2,-36(fp) + 802f028: 10000015 stw zero,0(r2) + break; + 802f02c: 00003906 br 802f114 +#ifdef IP_MULTICAST + + case IP_MULTICAST_IF: + case IP_MULTICAST_TTL: + case IP_MULTICAST_LOOP: + error = ip_getmoptions(optname, so, val); + 802f030: e1bff717 ldw r6,-36(fp) + 802f034: e17ff917 ldw r5,-28(fp) + 802f038: e13ff817 ldw r4,-32(fp) + 802f03c: 803ed640 call 803ed64 + 802f040: e0bfff15 stw r2,-4(fp) + break; + 802f044: 00003306 br 802f114 + +#ifdef IP_RAW + + case IP_HDRINCL: + /* indicate based on header-include flag in socket state */ + if (so->so_options & SO_HDRINCL) + 802f048: e0bff917 ldw r2,-28(fp) + 802f04c: 10800417 ldw r2,16(r2) + 802f050: 1088000c andi r2,r2,8192 + 802f054: 10000426 beq r2,zero,802f068 + *(int *)val = 1; + 802f058: e0bff717 ldw r2,-36(fp) + 802f05c: 00c00044 movi r3,1 + 802f060: 10c00015 stw r3,0(r2) + else + *(int *)val = 0; + break; + 802f064: 00002b06 br 802f114 + *(int *)val = 0; + 802f068: e0bff717 ldw r2,-36(fp) + 802f06c: 10000015 stw zero,0(r2) + break; + 802f070: 00002806 br 802f114 + case TCP_NODELAY: + { + struct inpcb * inp; + struct tcpcb * tp; + + if(so->so_type != SOCK_STREAM) + 802f074: e0bff917 ldw r2,-28(fp) + 802f078: 10800983 ldbu r2,38(r2) + 802f07c: 10803fcc andi r2,r2,255 + 802f080: 1080201c xori r2,r2,128 + 802f084: 10bfe004 addi r2,r2,-128 + 802f088: 10800060 cmpeqi r2,r2,1 + 802f08c: 1000031e bne r2,zero,802f09c + { + error = EINVAL; + 802f090: 00800584 movi r2,22 + 802f094: e0bfff15 stw r2,-4(fp) + break; + 802f098: 00001e06 br 802f114 + } + inp = (struct inpcb *)(so->so_pcb); + 802f09c: e0bff917 ldw r2,-28(fp) + 802f0a0: 10800117 ldw r2,4(r2) + 802f0a4: e0bffb15 stw r2,-20(fp) + tp = intotcpcb(inp); + 802f0a8: e0bffb17 ldw r2,-20(fp) + 802f0ac: 10800917 ldw r2,36(r2) + 802f0b0: e0bffa15 stw r2,-24(fp) + if (!tp) + 802f0b4: e0bffa17 ldw r2,-24(fp) + 802f0b8: 1000031e bne r2,zero,802f0c8 + { + error = ENOTCONN; + 802f0bc: 00802004 movi r2,128 + 802f0c0: e0bfff15 stw r2,-4(fp) + break; + 802f0c4: 00001306 br 802f114 + } + /* try to make sure that the argument pointer is valid */ + if (val == NULL) + 802f0c8: e0bff717 ldw r2,-36(fp) + 802f0cc: 1000031e bne r2,zero,802f0dc + { + error = ENP_PARAM; + 802f0d0: 00bffd84 movi r2,-10 + 802f0d4: e0bfff15 stw r2,-4(fp) + break; + 802f0d8: 00000e06 br 802f114 + } + /* if contents of integer addressed by arg are non-zero */ + if (tp->t_flags & TF_NODELAY) + 802f0dc: e0bffa17 ldw r2,-24(fp) + 802f0e0: 10800b0b ldhu r2,44(r2) + 802f0e4: 10bfffcc andi r2,r2,65535 + 802f0e8: 1080010c andi r2,r2,4 + 802f0ec: 10000426 beq r2,zero,802f100 + *(int *)val = 1; /* Nagle Algorithm is Enabled */ + 802f0f0: e0bff717 ldw r2,-36(fp) + 802f0f4: 00c00044 movi r3,1 + 802f0f8: 10c00015 stw r3,0(r2) + else + *(int *)val = 0; /* Nagle Algorithm is NOT Enabled */ + + break; + 802f0fc: 00000506 br 802f114 + *(int *)val = 0; /* Nagle Algorithm is NOT Enabled */ + 802f100: e0bff717 ldw r2,-36(fp) + 802f104: 10000015 stw zero,0(r2) + break; + 802f108: 00000206 br 802f114 + } + + default: + return ENOPROTOOPT; + 802f10c: 00801b44 movi r2,109 + 802f110: 00000106 br 802f118 + } + return error; /* no error */ + 802f114: e0bfff17 ldw r2,-4(fp) +} + 802f118: e037883a mov sp,fp + 802f11c: dfc00117 ldw ra,4(sp) + 802f120: df000017 ldw fp,0(sp) + 802f124: dec00204 addi sp,sp,8 + 802f128: f800283a ret + +0802f12c : + * RETURNS: + */ + +void +sohasoutofband(struct socket * so) +{ + 802f12c: defffd04 addi sp,sp,-12 + 802f130: dfc00215 stw ra,8(sp) + 802f134: df000115 stw fp,4(sp) + 802f138: df000104 addi fp,sp,4 + 802f13c: e13fff15 stw r4,-4(fp) + so->so_error = EHAVEOOB; /* WILL be picked up by the socket */ + 802f140: e0bfff17 ldw r2,-4(fp) + 802f144: 00c03644 movi r3,217 + 802f148: 10c00615 stw r3,24(r2) + sorwakeup (so); + 802f14c: e0bfff17 ldw r2,-4(fp) + 802f150: 10800a04 addi r2,r2,40 + 802f154: 100b883a mov r5,r2 + 802f158: e13fff17 ldw r4,-4(fp) + 802f15c: 802f94c0 call 802f94c +} + 802f160: 0001883a nop + 802f164: e037883a mov sp,fp + 802f168: dfc00117 ldw ra,4(sp) + 802f16c: df000017 ldw fp,0(sp) + 802f170: dec00204 addi sp,sp,8 + 802f174: f800283a ret + +0802f178 : + * RETURNS: + */ + +void +soisconnecting(struct socket * so) +{ + 802f178: defffd04 addi sp,sp,-12 + 802f17c: dfc00215 stw ra,8(sp) + 802f180: df000115 stw fp,4(sp) + 802f184: df000104 addi fp,sp,4 + 802f188: e13fff15 stw r4,-4(fp) + so->so_state &= ~(SS_ISCONNECTED|SS_ISDISCONNECTING); + 802f18c: e0bfff17 ldw r2,-4(fp) + 802f190: 10c0088b ldhu r3,34(r2) + 802f194: 00bffd44 movi r2,-11 + 802f198: 1884703a and r2,r3,r2 + 802f19c: 1007883a mov r3,r2 + 802f1a0: e0bfff17 ldw r2,-4(fp) + 802f1a4: 10c0088d sth r3,34(r2) + so->so_state |= SS_ISCONNECTING; + 802f1a8: e0bfff17 ldw r2,-4(fp) + 802f1ac: 1080088b ldhu r2,34(r2) + 802f1b0: 10800114 ori r2,r2,4 + 802f1b4: 1007883a mov r3,r2 + 802f1b8: e0bfff17 ldw r2,-4(fp) + 802f1bc: 10c0088d sth r3,34(r2) + tcp_wakeup ((char *)&so->so_timeo); + 802f1c0: e0bfff17 ldw r2,-4(fp) + 802f1c4: 10800904 addi r2,r2,36 + 802f1c8: 1009883a mov r4,r2 + 802f1cc: 8027ba00 call 8027ba0 +} + 802f1d0: 0001883a nop + 802f1d4: e037883a mov sp,fp + 802f1d8: dfc00117 ldw ra,4(sp) + 802f1dc: df000017 ldw fp,0(sp) + 802f1e0: dec00204 addi sp,sp,8 + 802f1e4: f800283a ret + +0802f1e8 : + * RETURNS: + */ + +void +soisconnected(struct socket * so) +{ + 802f1e8: defffc04 addi sp,sp,-16 + 802f1ec: dfc00315 stw ra,12(sp) + 802f1f0: df000215 stw fp,8(sp) + 802f1f4: df000204 addi fp,sp,8 + 802f1f8: e13ffe15 stw r4,-8(fp) + struct socket * head = so->so_head; + 802f1fc: e0bffe17 ldw r2,-8(fp) + 802f200: 10801b17 ldw r2,108(r2) + 802f204: e0bfff15 stw r2,-4(fp) + + if (head) + 802f208: e0bfff17 ldw r2,-4(fp) + 802f20c: 10001426 beq r2,zero,802f260 + { + if (soqremque(so, 0) == 0) + 802f210: 000b883a mov r5,zero + 802f214: e13ffe17 ldw r4,-8(fp) + 802f218: 802f6ec0 call 802f6ec + 802f21c: 1000031e bne r2,zero,802f22c + panic("soisconnected"); + 802f220: 01020174 movhi r4,2053 + 802f224: 212a8a04 addi r4,r4,-21976 + 802f228: 80271780 call 8027178 + soqinsque(head, so, 1); + 802f22c: 01800044 movi r6,1 + 802f230: e17ffe17 ldw r5,-8(fp) + 802f234: e13fff17 ldw r4,-4(fp) + 802f238: 802f6400 call 802f640 + sorwakeup(head); + 802f23c: e0bfff17 ldw r2,-4(fp) + 802f240: 10800a04 addi r2,r2,40 + 802f244: 100b883a mov r5,r2 + 802f248: e13fff17 ldw r4,-4(fp) + 802f24c: 802f94c0 call 802f94c + tcp_wakeup ((char *)&head->so_timeo); + 802f250: e0bfff17 ldw r2,-4(fp) + 802f254: 10800904 addi r2,r2,36 + 802f258: 1009883a mov r4,r2 + 802f25c: 8027ba00 call 8027ba0 + } + + so->so_state &= ~(SS_ISCONNECTING|SS_ISDISCONNECTING); + 802f260: e0bffe17 ldw r2,-8(fp) + 802f264: 10c0088b ldhu r3,34(r2) + 802f268: 00bffcc4 movi r2,-13 + 802f26c: 1884703a and r2,r3,r2 + 802f270: 1007883a mov r3,r2 + 802f274: e0bffe17 ldw r2,-8(fp) + 802f278: 10c0088d sth r3,34(r2) + so->so_state |= SS_ISCONNECTED; + 802f27c: e0bffe17 ldw r2,-8(fp) + 802f280: 1080088b ldhu r2,34(r2) + 802f284: 10800094 ori r2,r2,2 + 802f288: 1007883a mov r3,r2 + 802f28c: e0bffe17 ldw r2,-8(fp) + 802f290: 10c0088d sth r3,34(r2) + so->so_error = 0; + 802f294: e0bffe17 ldw r2,-8(fp) + 802f298: 10000615 stw zero,24(r2) + tcp_wakeup ((char *)&so->so_timeo); + 802f29c: e0bffe17 ldw r2,-8(fp) + 802f2a0: 10800904 addi r2,r2,36 + 802f2a4: 1009883a mov r4,r2 + 802f2a8: 8027ba00 call 8027ba0 + sorwakeup (so); + 802f2ac: e0bffe17 ldw r2,-8(fp) + 802f2b0: 10800a04 addi r2,r2,40 + 802f2b4: 100b883a mov r5,r2 + 802f2b8: e13ffe17 ldw r4,-8(fp) + 802f2bc: 802f94c0 call 802f94c + sowwakeup (so); + 802f2c0: e0bffe17 ldw r2,-8(fp) + 802f2c4: 10801204 addi r2,r2,72 + 802f2c8: 100b883a mov r5,r2 + 802f2cc: e13ffe17 ldw r4,-8(fp) + 802f2d0: 802f94c0 call 802f94c +} + 802f2d4: 0001883a nop + 802f2d8: e037883a mov sp,fp + 802f2dc: dfc00117 ldw ra,4(sp) + 802f2e0: df000017 ldw fp,0(sp) + 802f2e4: dec00204 addi sp,sp,8 + 802f2e8: f800283a ret + +0802f2ec : + * RETURNS: + */ + +void +soisdisconnecting(struct socket * so) +{ + 802f2ec: defffd04 addi sp,sp,-12 + 802f2f0: dfc00215 stw ra,8(sp) + 802f2f4: df000115 stw fp,4(sp) + 802f2f8: df000104 addi fp,sp,4 + 802f2fc: e13fff15 stw r4,-4(fp) + so->so_state &= ~SS_ISCONNECTING; + 802f300: e0bfff17 ldw r2,-4(fp) + 802f304: 10c0088b ldhu r3,34(r2) + 802f308: 00bffec4 movi r2,-5 + 802f30c: 1884703a and r2,r3,r2 + 802f310: 1007883a mov r3,r2 + 802f314: e0bfff17 ldw r2,-4(fp) + 802f318: 10c0088d sth r3,34(r2) + so->so_state |= (SS_ISDISCONNECTING|SS_CANTRCVMORE|SS_CANTSENDMORE); + 802f31c: e0bfff17 ldw r2,-4(fp) + 802f320: 1080088b ldhu r2,34(r2) + 802f324: 10800e14 ori r2,r2,56 + 802f328: 1007883a mov r3,r2 + 802f32c: e0bfff17 ldw r2,-4(fp) + 802f330: 10c0088d sth r3,34(r2) + tcp_wakeup ((char *)&so->so_timeo); + 802f334: e0bfff17 ldw r2,-4(fp) + 802f338: 10800904 addi r2,r2,36 + 802f33c: 1009883a mov r4,r2 + 802f340: 8027ba00 call 8027ba0 + sowwakeup (so); + 802f344: e0bfff17 ldw r2,-4(fp) + 802f348: 10801204 addi r2,r2,72 + 802f34c: 100b883a mov r5,r2 + 802f350: e13fff17 ldw r4,-4(fp) + 802f354: 802f94c0 call 802f94c + sorwakeup (so); + 802f358: e0bfff17 ldw r2,-4(fp) + 802f35c: 10800a04 addi r2,r2,40 + 802f360: 100b883a mov r5,r2 + 802f364: e13fff17 ldw r4,-4(fp) + 802f368: 802f94c0 call 802f94c +} + 802f36c: 0001883a nop + 802f370: e037883a mov sp,fp + 802f374: dfc00117 ldw ra,4(sp) + 802f378: df000017 ldw fp,0(sp) + 802f37c: dec00204 addi sp,sp,8 + 802f380: f800283a ret + +0802f384 : + * RETURNS: + */ + +void +soisdisconnected(struct socket * so) +{ + 802f384: defffd04 addi sp,sp,-12 + 802f388: dfc00215 stw ra,8(sp) + 802f38c: df000115 stw fp,4(sp) + 802f390: df000104 addi fp,sp,4 + 802f394: e13fff15 stw r4,-4(fp) + if (so->so_state & SS_ISCONNECTING) + 802f398: e0bfff17 ldw r2,-4(fp) + 802f39c: 1080088b ldhu r2,34(r2) + 802f3a0: 10bfffcc andi r2,r2,65535 + 802f3a4: 1080010c andi r2,r2,4 + 802f3a8: 10000626 beq r2,zero,802f3c4 + so->so_state |= SS_WASCONNECTING; + 802f3ac: e0bfff17 ldw r2,-4(fp) + 802f3b0: 1080088b ldhu r2,34(r2) + 802f3b4: 10880014 ori r2,r2,8192 + 802f3b8: 1007883a mov r3,r2 + 802f3bc: e0bfff17 ldw r2,-4(fp) + 802f3c0: 10c0088d sth r3,34(r2) + so->so_state &= ~(SS_ISCONNECTING|SS_ISCONNECTED|SS_ISDISCONNECTING); + 802f3c4: e0bfff17 ldw r2,-4(fp) + 802f3c8: 10c0088b ldhu r3,34(r2) + 802f3cc: 00bffc44 movi r2,-15 + 802f3d0: 1884703a and r2,r3,r2 + 802f3d4: 1007883a mov r3,r2 + 802f3d8: e0bfff17 ldw r2,-4(fp) + 802f3dc: 10c0088d sth r3,34(r2) + so->so_state |= (SS_CANTRCVMORE|SS_CANTSENDMORE); + 802f3e0: e0bfff17 ldw r2,-4(fp) + 802f3e4: 1080088b ldhu r2,34(r2) + 802f3e8: 10800c14 ori r2,r2,48 + 802f3ec: 1007883a mov r3,r2 + 802f3f0: e0bfff17 ldw r2,-4(fp) + 802f3f4: 10c0088d sth r3,34(r2) + tcp_wakeup ((char *)&so->so_timeo); + 802f3f8: e0bfff17 ldw r2,-4(fp) + 802f3fc: 10800904 addi r2,r2,36 + 802f400: 1009883a mov r4,r2 + 802f404: 8027ba00 call 8027ba0 + sowwakeup (so); + 802f408: e0bfff17 ldw r2,-4(fp) + 802f40c: 10801204 addi r2,r2,72 + 802f410: 100b883a mov r5,r2 + 802f414: e13fff17 ldw r4,-4(fp) + 802f418: 802f94c0 call 802f94c + sorwakeup (so); + 802f41c: e0bfff17 ldw r2,-4(fp) + 802f420: 10800a04 addi r2,r2,40 + 802f424: 100b883a mov r5,r2 + 802f428: e13fff17 ldw r4,-4(fp) + 802f42c: 802f94c0 call 802f94c +} + 802f430: 0001883a nop + 802f434: e037883a mov sp,fp + 802f438: dfc00117 ldw ra,4(sp) + 802f43c: df000017 ldw fp,0(sp) + 802f440: dec00204 addi sp,sp,8 + 802f444: f800283a ret + +0802f448 : + * RETURNS: + */ + +struct socket * +sonewconn(struct socket * head) +{ + 802f448: defffb04 addi sp,sp,-20 + 802f44c: dfc00415 stw ra,16(sp) + 802f450: df000315 stw fp,12(sp) + 802f454: df000304 addi fp,sp,12 + 802f458: e13ffd15 stw r4,-12(fp) + struct socket * so; + int rc; + + if (head->so_qlen + head->so_q0len > 3 * head->so_qlimit / 2) + 802f45c: e0bffd17 ldw r2,-12(fp) + 802f460: 10801e43 ldbu r2,121(r2) + 802f464: 10c03fcc andi r3,r2,255 + 802f468: 18c0201c xori r3,r3,128 + 802f46c: 18ffe004 addi r3,r3,-128 + 802f470: e0bffd17 ldw r2,-12(fp) + 802f474: 10801e03 ldbu r2,120(r2) + 802f478: 10803fcc andi r2,r2,255 + 802f47c: 1080201c xori r2,r2,128 + 802f480: 10bfe004 addi r2,r2,-128 + 802f484: 1887883a add r3,r3,r2 + 802f488: e0bffd17 ldw r2,-12(fp) + 802f48c: 10801e83 ldbu r2,122(r2) + 802f490: 10803fcc andi r2,r2,255 + 802f494: 1080201c xori r2,r2,128 + 802f498: 10bfe004 addi r2,r2,-128 + 802f49c: 108000e4 muli r2,r2,3 + 802f4a0: 1008d7fa srli r4,r2,31 + 802f4a4: 2085883a add r2,r4,r2 + 802f4a8: 1005d07a srai r2,r2,1 + 802f4ac: 10c05b16 blt r2,r3,802f61c + goto bad; + if ((so = SOC_ALLOC (sizeof (*so))) == NULL) + 802f4b0: 01002104 movi r4,132 + 802f4b4: 802982c0 call 802982c + 802f4b8: e0bfff15 stw r2,-4(fp) + 802f4bc: e0bfff17 ldw r2,-4(fp) + 802f4c0: 10005826 beq r2,zero,802f624 + goto bad; + so->next = NULL; + 802f4c4: e0bfff17 ldw r2,-4(fp) + 802f4c8: 10000015 stw zero,0(r2) + putq(&soq,(qp)so); /* Place newly created socket in a queue */ + 802f4cc: e17fff17 ldw r5,-4(fp) + 802f4d0: 010201b4 movhi r4,2054 + 802f4d4: 21387104 addi r4,r4,-7740 + 802f4d8: 80289900 call 8028990 + so->so_type = head->so_type; + 802f4dc: e0bffd17 ldw r2,-12(fp) + 802f4e0: 10c00983 ldbu r3,38(r2) + 802f4e4: e0bfff17 ldw r2,-4(fp) + 802f4e8: 10c00985 stb r3,38(r2) + so->so_options = head->so_options &~ (unshort)SO_ACCEPTCONN; + 802f4ec: e0bffd17 ldw r2,-12(fp) + 802f4f0: 10c00417 ldw r3,16(r2) + 802f4f4: 00bfff44 movi r2,-3 + 802f4f8: 1886703a and r3,r3,r2 + 802f4fc: e0bfff17 ldw r2,-4(fp) + 802f500: 10c00415 stw r3,16(r2) + so->so_linger = head->so_linger; + 802f504: e0bffd17 ldw r2,-12(fp) + 802f508: 10c0080b ldhu r3,32(r2) + 802f50c: e0bfff17 ldw r2,-4(fp) + 802f510: 10c0080d sth r3,32(r2) + so->so_state = head->so_state | (unshort)SS_NOFDREF; + 802f514: e0bffd17 ldw r2,-12(fp) + 802f518: 1080088b ldhu r2,34(r2) + 802f51c: 10800054 ori r2,r2,1 + 802f520: 1007883a mov r3,r2 + 802f524: e0bfff17 ldw r2,-4(fp) + 802f528: 10c0088d sth r3,34(r2) + so->so_proto = head->so_proto; + 802f52c: e0bffd17 ldw r2,-12(fp) + 802f530: 10c00217 ldw r3,8(r2) + 802f534: e0bfff17 ldw r2,-4(fp) + 802f538: 10c00215 stw r3,8(r2) + so->so_timeo = head->so_timeo; + 802f53c: e0bffd17 ldw r2,-12(fp) + 802f540: 10c0090b ldhu r3,36(r2) + 802f544: e0bfff17 ldw r2,-4(fp) + 802f548: 10c0090d sth r3,36(r2) + so->so_rcv.sb_hiwat = (u_int)tcp_recvspace; + 802f54c: d0e02117 ldw r3,-32636(gp) + 802f550: e0bfff17 ldw r2,-4(fp) + 802f554: 10c00b15 stw r3,44(r2) + so->so_snd.sb_hiwat = (u_int)tcp_sendspace; + 802f558: d0e02017 ldw r3,-32640(gp) + 802f55c: e0bfff17 ldw r2,-4(fp) + 802f560: 10c01315 stw r3,76(r2) + soqinsque (head, so, 0); + 802f564: 000d883a mov r6,zero + 802f568: e17fff17 ldw r5,-4(fp) + 802f56c: e13ffd17 ldw r4,-12(fp) + 802f570: 802f6400 call 802f640 + so->so_req = PRU_ATTACH; + 802f574: e0bfff17 ldw r2,-4(fp) + 802f578: 10000715 stw zero,28(r2) + so->so_domain = head->so_domain; + 802f57c: e0bffd17 ldw r2,-12(fp) + 802f580: 10c00517 ldw r3,20(r2) + 802f584: e0bfff17 ldw r2,-4(fp) + 802f588: 10c00515 stw r3,20(r2) + + if ((*so->so_proto->pr_usrreq)(so, (struct mbuf *)0, (struct mbuf *)0)) + 802f58c: e0bfff17 ldw r2,-4(fp) + 802f590: 10800217 ldw r2,8(r2) + 802f594: 10800317 ldw r2,12(r2) + 802f598: 000d883a mov r6,zero + 802f59c: 000b883a mov r5,zero + 802f5a0: e13fff17 ldw r4,-4(fp) + 802f5a4: 103ee83a callr r2 + 802f5a8: 10000f1e bne r2,zero,802f5e8 + goto bad2; + if (so_evtmap) + 802f5ac: d0a09a03 ldbu r2,-32152(gp) + 802f5b0: 10803fcc andi r2,r2,255 + 802f5b4: 10000a26 beq r2,zero,802f5e0 + { + rc = (*so_evtmap_create) (so); + 802f5b8: d0a09817 ldw r2,-32160(gp) + 802f5bc: e13fff17 ldw r4,-4(fp) + 802f5c0: 103ee83a callr r2 + 802f5c4: e0bffe15 stw r2,-8(fp) + if (rc != 0) goto bad2; + 802f5c8: e0bffe17 ldw r2,-8(fp) + 802f5cc: 1000081e bne r2,zero,802f5f0 + so->owner = head->owner; + 802f5d0: e0bffd17 ldw r2,-12(fp) + 802f5d4: 10c02003 ldbu r3,128(r2) + 802f5d8: e0bfff17 ldw r2,-4(fp) + 802f5dc: 10c02005 stb r3,128(r2) + } + return (so); + 802f5e0: e0bfff17 ldw r2,-4(fp) + 802f5e4: 00001106 br 802f62c + goto bad2; + 802f5e8: 0001883a nop + 802f5ec: 00000106 br 802f5f4 + if (rc != 0) goto bad2; + 802f5f0: 0001883a nop + +bad2: + (void) soqremque (so, 0); + 802f5f4: 000b883a mov r5,zero + 802f5f8: e13fff17 ldw r4,-4(fp) + 802f5fc: 802f6ec0 call 802f6ec + qdel(&soq, so); /* Delete the socket entry from the queue */ + 802f600: e17fff17 ldw r5,-4(fp) + 802f604: 010201b4 movhi r4,2054 + 802f608: 21387104 addi r4,r4,-7740 + 802f60c: 8028a400 call 8028a40 + SOC_FREE(so); /* Free the socket structure */ + 802f610: e13fff17 ldw r4,-4(fp) + 802f614: 80298600 call 8029860 + 802f618: 00000306 br 802f628 + goto bad; + 802f61c: 0001883a nop + 802f620: 00000106 br 802f628 + goto bad; + 802f624: 0001883a nop +bad: + return ((struct socket *)0); + 802f628: 0005883a mov r2,zero +} + 802f62c: e037883a mov sp,fp + 802f630: dfc00117 ldw ra,4(sp) + 802f634: df000017 ldw fp,0(sp) + 802f638: dec00204 addi sp,sp,8 + 802f63c: f800283a ret + +0802f640 : + +void +soqinsque(struct socket * head, + struct socket * so, + int q) +{ + 802f640: defffc04 addi sp,sp,-16 + 802f644: df000315 stw fp,12(sp) + 802f648: df000304 addi fp,sp,12 + 802f64c: e13fff15 stw r4,-4(fp) + 802f650: e17ffe15 stw r5,-8(fp) + 802f654: e1bffd15 stw r6,-12(fp) + so->so_head = head; + 802f658: e0bffe17 ldw r2,-8(fp) + 802f65c: e0ffff17 ldw r3,-4(fp) + 802f660: 10c01b15 stw r3,108(r2) + if (q == 0) + 802f664: e0bffd17 ldw r2,-12(fp) + 802f668: 10000e1e bne r2,zero,802f6a4 + { + head->so_q0len++; + 802f66c: e0bfff17 ldw r2,-4(fp) + 802f670: 10801e03 ldbu r2,120(r2) + 802f674: 10800044 addi r2,r2,1 + 802f678: 1007883a mov r3,r2 + 802f67c: e0bfff17 ldw r2,-4(fp) + 802f680: 10c01e05 stb r3,120(r2) + so->so_q0 = head->so_q0; + 802f684: e0bfff17 ldw r2,-4(fp) + 802f688: 10c01c17 ldw r3,112(r2) + 802f68c: e0bffe17 ldw r2,-8(fp) + 802f690: 10c01c15 stw r3,112(r2) + head->so_q0 = so; + 802f694: e0bfff17 ldw r2,-4(fp) + 802f698: e0fffe17 ldw r3,-8(fp) + 802f69c: 10c01c15 stw r3,112(r2) + { + head->so_qlen++; + so->so_q = head->so_q; + head->so_q = so; + } +} + 802f6a0: 00000d06 br 802f6d8 + head->so_qlen++; + 802f6a4: e0bfff17 ldw r2,-4(fp) + 802f6a8: 10801e43 ldbu r2,121(r2) + 802f6ac: 10800044 addi r2,r2,1 + 802f6b0: 1007883a mov r3,r2 + 802f6b4: e0bfff17 ldw r2,-4(fp) + 802f6b8: 10c01e45 stb r3,121(r2) + so->so_q = head->so_q; + 802f6bc: e0bfff17 ldw r2,-4(fp) + 802f6c0: 10c01d17 ldw r3,116(r2) + 802f6c4: e0bffe17 ldw r2,-8(fp) + 802f6c8: 10c01d15 stw r3,116(r2) + head->so_q = so; + 802f6cc: e0bfff17 ldw r2,-4(fp) + 802f6d0: e0fffe17 ldw r3,-8(fp) + 802f6d4: 10c01d15 stw r3,116(r2) +} + 802f6d8: 0001883a nop + 802f6dc: e037883a mov sp,fp + 802f6e0: df000017 ldw fp,0(sp) + 802f6e4: dec00104 addi sp,sp,4 + 802f6e8: f800283a ret + +0802f6ec : + * RETURNS: + */ + +int +soqremque(struct socket * so, int q) +{ + 802f6ec: defffa04 addi sp,sp,-24 + 802f6f0: df000515 stw fp,20(sp) + 802f6f4: df000504 addi fp,sp,20 + 802f6f8: e13ffc15 stw r4,-16(fp) + 802f6fc: e17ffb15 stw r5,-20(fp) + struct socket * head, * prev, * next; + + head = so->so_head; + 802f700: e0bffc17 ldw r2,-16(fp) + 802f704: 10801b17 ldw r2,108(r2) + 802f708: e0bffe15 stw r2,-8(fp) + prev = head; + 802f70c: e0bffe17 ldw r2,-8(fp) + 802f710: e0bfff15 stw r2,-4(fp) + for (;;) + { + next = q ? prev->so_q : prev->so_q0; + 802f714: e0bffb17 ldw r2,-20(fp) + 802f718: 10000326 beq r2,zero,802f728 + 802f71c: e0bfff17 ldw r2,-4(fp) + 802f720: 10801d17 ldw r2,116(r2) + 802f724: 00000206 br 802f730 + 802f728: e0bfff17 ldw r2,-4(fp) + 802f72c: 10801c17 ldw r2,112(r2) + 802f730: e0bffd15 stw r2,-12(fp) + if (next == so) + 802f734: e0fffd17 ldw r3,-12(fp) + 802f738: e0bffc17 ldw r2,-16(fp) + 802f73c: 18800826 beq r3,r2,802f760 + break; + if (next == head) + 802f740: e0fffd17 ldw r3,-12(fp) + 802f744: e0bffe17 ldw r2,-8(fp) + 802f748: 1880021e bne r3,r2,802f754 + return (0); + 802f74c: 0005883a mov r2,zero + 802f750: 00002406 br 802f7e4 + prev = next; + 802f754: e0bffd17 ldw r2,-12(fp) + 802f758: e0bfff15 stw r2,-4(fp) + next = q ? prev->so_q : prev->so_q0; + 802f75c: 003fed06 br 802f714 + break; + 802f760: 0001883a nop + } + if (q == 0) + 802f764: e0bffb17 ldw r2,-20(fp) + 802f768: 10000b1e bne r2,zero,802f798 + { + prev->so_q0 = next->so_q0; + 802f76c: e0bffd17 ldw r2,-12(fp) + 802f770: 10c01c17 ldw r3,112(r2) + 802f774: e0bfff17 ldw r2,-4(fp) + 802f778: 10c01c15 stw r3,112(r2) + head->so_q0len--; + 802f77c: e0bffe17 ldw r2,-8(fp) + 802f780: 10801e03 ldbu r2,120(r2) + 802f784: 10bfffc4 addi r2,r2,-1 + 802f788: 1007883a mov r3,r2 + 802f78c: e0bffe17 ldw r2,-8(fp) + 802f790: 10c01e05 stb r3,120(r2) + 802f794: 00000a06 br 802f7c0 + } else + { + prev->so_q = next->so_q; + 802f798: e0bffd17 ldw r2,-12(fp) + 802f79c: 10c01d17 ldw r3,116(r2) + 802f7a0: e0bfff17 ldw r2,-4(fp) + 802f7a4: 10c01d15 stw r3,116(r2) + head->so_qlen--; + 802f7a8: e0bffe17 ldw r2,-8(fp) + 802f7ac: 10801e43 ldbu r2,121(r2) + 802f7b0: 10bfffc4 addi r2,r2,-1 + 802f7b4: 1007883a mov r3,r2 + 802f7b8: e0bffe17 ldw r2,-8(fp) + 802f7bc: 10c01e45 stb r3,121(r2) + } + next->so_q0 = next->so_q = 0; + 802f7c0: e0bffd17 ldw r2,-12(fp) + 802f7c4: 10001d15 stw zero,116(r2) + 802f7c8: e0bffd17 ldw r2,-12(fp) + 802f7cc: 10c01d17 ldw r3,116(r2) + 802f7d0: e0bffd17 ldw r2,-12(fp) + 802f7d4: 10c01c15 stw r3,112(r2) + next->so_head = 0; + 802f7d8: e0bffd17 ldw r2,-12(fp) + 802f7dc: 10001b15 stw zero,108(r2) + return 1; + 802f7e0: 00800044 movi r2,1 +} + 802f7e4: e037883a mov sp,fp + 802f7e8: df000017 ldw fp,0(sp) + 802f7ec: dec00104 addi sp,sp,4 + 802f7f0: f800283a ret + +0802f7f4 : + * RETURNS: + */ + +void +socantsendmore(struct socket * so) +{ + 802f7f4: defffd04 addi sp,sp,-12 + 802f7f8: dfc00215 stw ra,8(sp) + 802f7fc: df000115 stw fp,4(sp) + 802f800: df000104 addi fp,sp,4 + 802f804: e13fff15 stw r4,-4(fp) + so->so_state |= SS_CANTSENDMORE; + 802f808: e0bfff17 ldw r2,-4(fp) + 802f80c: 1080088b ldhu r2,34(r2) + 802f810: 10800414 ori r2,r2,16 + 802f814: 1007883a mov r3,r2 + 802f818: e0bfff17 ldw r2,-4(fp) + 802f81c: 10c0088d sth r3,34(r2) + sowwakeup(so); + 802f820: e0bfff17 ldw r2,-4(fp) + 802f824: 10801204 addi r2,r2,72 + 802f828: 100b883a mov r5,r2 + 802f82c: e13fff17 ldw r4,-4(fp) + 802f830: 802f94c0 call 802f94c +} + 802f834: 0001883a nop + 802f838: e037883a mov sp,fp + 802f83c: dfc00117 ldw ra,4(sp) + 802f840: df000017 ldw fp,0(sp) + 802f844: dec00204 addi sp,sp,8 + 802f848: f800283a ret + +0802f84c : + * RETURNS: + */ + +void +socantrcvmore(struct socket * so) +{ + 802f84c: defffd04 addi sp,sp,-12 + 802f850: dfc00215 stw ra,8(sp) + 802f854: df000115 stw fp,4(sp) + 802f858: df000104 addi fp,sp,4 + 802f85c: e13fff15 stw r4,-4(fp) + so->so_state |= SS_CANTRCVMORE; + 802f860: e0bfff17 ldw r2,-4(fp) + 802f864: 1080088b ldhu r2,34(r2) + 802f868: 10800814 ori r2,r2,32 + 802f86c: 1007883a mov r3,r2 + 802f870: e0bfff17 ldw r2,-4(fp) + 802f874: 10c0088d sth r3,34(r2) + sorwakeup(so); + 802f878: e0bfff17 ldw r2,-4(fp) + 802f87c: 10800a04 addi r2,r2,40 + 802f880: 100b883a mov r5,r2 + 802f884: e13fff17 ldw r4,-4(fp) + 802f888: 802f94c0 call 802f94c +} + 802f88c: 0001883a nop + 802f890: e037883a mov sp,fp + 802f894: dfc00117 ldw ra,4(sp) + 802f898: df000017 ldw fp,0(sp) + 802f89c: dec00204 addi sp,sp,8 + 802f8a0: f800283a ret + +0802f8a4 : + * RETURNS: + */ + +void +sbselqueue(struct sockbuf * sb) +{ + 802f8a4: defffe04 addi sp,sp,-8 + 802f8a8: df000115 stw fp,4(sp) + 802f8ac: df000104 addi fp,sp,4 + 802f8b0: e13fff15 stw r4,-4(fp) + sb->sb_flags |= SB_SEL; + 802f8b4: e0bfff17 ldw r2,-4(fp) + 802f8b8: 1080070b ldhu r2,28(r2) + 802f8bc: 10800214 ori r2,r2,8 + 802f8c0: 1007883a mov r3,r2 + 802f8c4: e0bfff17 ldw r2,-4(fp) + 802f8c8: 10c0070d sth r3,28(r2) +} + 802f8cc: 0001883a nop + 802f8d0: e037883a mov sp,fp + 802f8d4: df000017 ldw fp,0(sp) + 802f8d8: dec00104 addi sp,sp,4 + 802f8dc: f800283a ret + +0802f8e0 : + * RETURNS: + */ + +void +sbwait(struct sockbuf * sb) +{ + 802f8e0: defffd04 addi sp,sp,-12 + 802f8e4: dfc00215 stw ra,8(sp) + 802f8e8: df000115 stw fp,4(sp) + 802f8ec: df000104 addi fp,sp,4 + 802f8f0: e13fff15 stw r4,-4(fp) + sb->sb_flags |= SB_WAIT; + 802f8f4: e0bfff17 ldw r2,-4(fp) + 802f8f8: 1080070b ldhu r2,28(r2) + 802f8fc: 10800114 ori r2,r2,4 + 802f900: 1007883a mov r3,r2 + 802f904: e0bfff17 ldw r2,-4(fp) + 802f908: 10c0070d sth r3,28(r2) + tcp_sleep ((char *)&sb->sb_cc); + 802f90c: e0bfff17 ldw r2,-4(fp) + 802f910: 1009883a mov r4,r2 + 802f914: 8027a540 call 8027a54 + sb->sb_flags &= ~SB_WAIT; + 802f918: e0bfff17 ldw r2,-4(fp) + 802f91c: 10c0070b ldhu r3,28(r2) + 802f920: 00bffec4 movi r2,-5 + 802f924: 1884703a and r2,r3,r2 + 802f928: 1007883a mov r3,r2 + 802f92c: e0bfff17 ldw r2,-4(fp) + 802f930: 10c0070d sth r3,28(r2) +} + 802f934: 0001883a nop + 802f938: e037883a mov sp,fp + 802f93c: dfc00117 ldw ra,4(sp) + 802f940: df000017 ldw fp,0(sp) + 802f944: dec00204 addi sp,sp,8 + 802f948: f800283a ret + +0802f94c : + * RETURNS: + */ + +void +sbwakeup(struct socket * so, struct sockbuf * sb) +{ + 802f94c: defffc04 addi sp,sp,-16 + 802f950: dfc00315 stw ra,12(sp) + 802f954: df000215 stw fp,8(sp) + 802f958: df000204 addi fp,sp,8 + 802f95c: e13fff15 stw r4,-4(fp) + 802f960: e17ffe15 stw r5,-8(fp) + if (sb->sb_flags & SB_SEL) + 802f964: e0bffe17 ldw r2,-8(fp) + 802f968: 1080070b ldhu r2,28(r2) + 802f96c: 10bfffcc andi r2,r2,65535 + 802f970: 1080020c andi r2,r2,8 + 802f974: 10000a26 beq r2,zero,802f9a0 + { + select_wait = 0; + 802f978: d020850d sth zero,-32236(gp) +#ifndef SOCK_MAP_EVENTS + tcp_wakeup ((char *)&select_wait); + 802f97c: d1208504 addi r4,gp,-32236 + 802f980: 8027ba00 call 8027ba0 +#else + tcp_wakeup2 (so->owner); +#endif + sb->sb_flags &= ~SB_SEL; + 802f984: e0bffe17 ldw r2,-8(fp) + 802f988: 10c0070b ldhu r3,28(r2) + 802f98c: 00bffdc4 movi r2,-9 + 802f990: 1884703a and r2,r3,r2 + 802f994: 1007883a mov r3,r2 + 802f998: e0bffe17 ldw r2,-8(fp) + 802f99c: 10c0070d sth r3,28(r2) +#ifdef SOCK_WAKEALWAYS /* Always wake the socket? */ + /* Systems Like Green Hills Integrity RTOS, need to process socket + input even if looks like no one is blocked on the socket */ + tcp_wakeup ((char *)&sb->sb_cc); /* signal wake on socket */ +#else /* older BSD style code - only call tcp_wakeup if blocked */ + if (sb->sb_flags & SB_WAIT) /* is sockbuf's WAIT flag set? */ + 802f9a0: e0bffe17 ldw r2,-8(fp) + 802f9a4: 1080070b ldhu r2,28(r2) + 802f9a8: 10bfffcc andi r2,r2,65535 + 802f9ac: 1080010c andi r2,r2,4 + 802f9b0: 10000326 beq r2,zero,802f9c0 + { + tcp_wakeup ((char *)&sb->sb_cc); /* call port wakeup routine */ + 802f9b4: e0bffe17 ldw r2,-8(fp) + 802f9b8: 1009883a mov r4,r2 + 802f9bc: 8027ba00 call 8027ba0 + } +#endif /* SOCK_WAKEALWAYS */ +} + 802f9c0: 0001883a nop + 802f9c4: e037883a mov sp,fp + 802f9c8: dfc00117 ldw ra,4(sp) + 802f9cc: df000017 ldw fp,0(sp) + 802f9d0: dec00204 addi sp,sp,8 + 802f9d4: f800283a ret + +0802f9d8 : + +int +soreserve(struct socket * so, + u_long sndcc, + u_long rcvcc) +{ + 802f9d8: defffb04 addi sp,sp,-20 + 802f9dc: dfc00415 stw ra,16(sp) + 802f9e0: df000315 stw fp,12(sp) + 802f9e4: df000304 addi fp,sp,12 + 802f9e8: e13fff15 stw r4,-4(fp) + 802f9ec: e17ffe15 stw r5,-8(fp) + 802f9f0: e1bffd15 stw r6,-12(fp) + if (sbreserve(&so->so_snd, sndcc) == 0) + 802f9f4: e0bfff17 ldw r2,-4(fp) + 802f9f8: 10801204 addi r2,r2,72 + 802f9fc: e17ffe17 ldw r5,-8(fp) + 802fa00: 1009883a mov r4,r2 + 802fa04: 802fa600 call 802fa60 + 802fa08: 10000e26 beq r2,zero,802fa44 + goto bad; + if (sbreserve(&so->so_rcv, rcvcc) == 0) + 802fa0c: e0bfff17 ldw r2,-4(fp) + 802fa10: 10800a04 addi r2,r2,40 + 802fa14: e17ffd17 ldw r5,-12(fp) + 802fa18: 1009883a mov r4,r2 + 802fa1c: 802fa600 call 802fa60 + 802fa20: 10000226 beq r2,zero,802fa2c + goto bad2; + return (0); + 802fa24: 0005883a mov r2,zero + 802fa28: 00000806 br 802fa4c + goto bad2; + 802fa2c: 0001883a nop +bad2: + sbrelease(&so->so_snd); + 802fa30: e0bfff17 ldw r2,-4(fp) + 802fa34: 10801204 addi r2,r2,72 + 802fa38: 1009883a mov r4,r2 + 802fa3c: 802fab00 call 802fab0 + 802fa40: 00000106 br 802fa48 + goto bad; + 802fa44: 0001883a nop +bad: + return (ENOBUFS); + 802fa48: 00801a44 movi r2,105 +} + 802fa4c: e037883a mov sp,fp + 802fa50: dfc00117 ldw ra,4(sp) + 802fa54: df000017 ldw fp,0(sp) + 802fa58: dec00204 addi sp,sp,8 + 802fa5c: f800283a ret + +0802fa60 : + * RETURNS: + */ + +int +sbreserve(struct sockbuf * sb, u_long cc) +{ + 802fa60: defffd04 addi sp,sp,-12 + 802fa64: df000215 stw fp,8(sp) + 802fa68: df000204 addi fp,sp,8 + 802fa6c: e13fff15 stw r4,-4(fp) + 802fa70: e17ffe15 stw r5,-8(fp) +#ifdef COMPILER_32BIT + if (cc > (u_long)SB_MAX * CLBYTES / (2 * MSIZE + CLBYTES)) + return (0); +#endif + sb->sb_hiwat = cc; + 802fa74: e0bfff17 ldw r2,-4(fp) + 802fa78: e0fffe17 ldw r3,-8(fp) + 802fa7c: 10c00115 stw r3,4(r2) + sb->sb_mbmax = MIN(cc * 2, SB_MAX); + 802fa80: e0bffe17 ldw r2,-8(fp) + 802fa84: 1085883a add r2,r2,r2 + 802fa88: 10d00070 cmpltui r3,r2,16385 + 802fa8c: 1800011e bne r3,zero,802fa94 + 802fa90: 00900004 movi r2,16384 + 802fa94: e0ffff17 ldw r3,-4(fp) + 802fa98: 18800315 stw r2,12(r3) + return (1); + 802fa9c: 00800044 movi r2,1 +} + 802faa0: e037883a mov sp,fp + 802faa4: df000017 ldw fp,0(sp) + 802faa8: dec00104 addi sp,sp,4 + 802faac: f800283a ret + +0802fab0 : + * RETURNS: + */ + +void +sbrelease(struct sockbuf * sb) +{ + 802fab0: defffd04 addi sp,sp,-12 + 802fab4: dfc00215 stw ra,8(sp) + 802fab8: df000115 stw fp,4(sp) + 802fabc: df000104 addi fp,sp,4 + 802fac0: e13fff15 stw r4,-4(fp) + sbflush(sb); + 802fac4: e13fff17 ldw r4,-4(fp) + 802fac8: 803002c0 call 803002c + sb->sb_hiwat = sb->sb_mbmax = 0; + 802facc: e0bfff17 ldw r2,-4(fp) + 802fad0: 10000315 stw zero,12(r2) + 802fad4: e0bfff17 ldw r2,-4(fp) + 802fad8: 10c00317 ldw r3,12(r2) + 802fadc: e0bfff17 ldw r2,-4(fp) + 802fae0: 10c00115 stw r3,4(r2) +} + 802fae4: 0001883a nop + 802fae8: e037883a mov sp,fp + 802faec: dfc00117 ldw ra,4(sp) + 802faf0: df000017 ldw fp,0(sp) + 802faf4: dec00204 addi sp,sp,8 + 802faf8: f800283a ret + +0802fafc : + * RETURNS: + */ + +void +sbappend(struct sockbuf * sb, struct mbuf * m) +{ + 802fafc: defffb04 addi sp,sp,-20 + 802fb00: dfc00415 stw ra,16(sp) + 802fb04: df000315 stw fp,12(sp) + 802fb08: df000304 addi fp,sp,12 + 802fb0c: e13ffe15 stw r4,-8(fp) + 802fb10: e17ffd15 stw r5,-12(fp) + struct mbuf * n; + + if (m == 0) + 802fb14: e0bffd17 ldw r2,-12(fp) + 802fb18: 10001a26 beq r2,zero,802fb84 + return; + ENTER_CRIT_SECTION(sb); + 802fb1c: 8028e940 call 8028e94 + if ((n = sb->sb_mb) != NULL) + 802fb20: e0bffe17 ldw r2,-8(fp) + 802fb24: 10800617 ldw r2,24(r2) + 802fb28: e0bfff15 stw r2,-4(fp) + 802fb2c: e0bfff17 ldw r2,-4(fp) + 802fb30: 10000e26 beq r2,zero,802fb6c + { + while (n->m_act) + 802fb34: 00000306 br 802fb44 + n = n->m_act; + 802fb38: e0bfff17 ldw r2,-4(fp) + 802fb3c: 10800717 ldw r2,28(r2) + 802fb40: e0bfff15 stw r2,-4(fp) + while (n->m_act) + 802fb44: e0bfff17 ldw r2,-4(fp) + 802fb48: 10800717 ldw r2,28(r2) + 802fb4c: 103ffa1e bne r2,zero,802fb38 + while (n->m_next) + 802fb50: 00000306 br 802fb60 + n = n->m_next; + 802fb54: e0bfff17 ldw r2,-4(fp) + 802fb58: 10800617 ldw r2,24(r2) + 802fb5c: e0bfff15 stw r2,-4(fp) + while (n->m_next) + 802fb60: e0bfff17 ldw r2,-4(fp) + 802fb64: 10800617 ldw r2,24(r2) + 802fb68: 103ffa1e bne r2,zero,802fb54 + } + sbcompress(sb, m, n); + 802fb6c: e1bfff17 ldw r6,-4(fp) + 802fb70: e17ffd17 ldw r5,-12(fp) + 802fb74: e13ffe17 ldw r4,-8(fp) + 802fb78: 802fe500 call 802fe50 + EXIT_CRIT_SECTION(sb); + 802fb7c: 8028ef40 call 8028ef4 + 802fb80: 00000106 br 802fb88 + return; + 802fb84: 0001883a nop +} + 802fb88: e037883a mov sp,fp + 802fb8c: dfc00117 ldw ra,4(sp) + 802fb90: df000017 ldw fp,0(sp) + 802fb94: dec00204 addi sp,sp,8 + 802fb98: f800283a ret + +0802fb9c : + */ + +void +sbappendrecord(struct sockbuf * sb, + struct mbuf * m0) +{ + 802fb9c: defffb04 addi sp,sp,-20 + 802fba0: dfc00415 stw ra,16(sp) + 802fba4: df000315 stw fp,12(sp) + 802fba8: df000304 addi fp,sp,12 + 802fbac: e13ffe15 stw r4,-8(fp) + 802fbb0: e17ffd15 stw r5,-12(fp) + struct mbuf * m; + + if (m0 == 0) + 802fbb4: e0bffd17 ldw r2,-12(fp) + 802fbb8: 10002826 beq r2,zero,802fc5c + return; + ENTER_CRIT_SECTION(sb); /* protect so_rcv operations */ + 802fbbc: 8028e940 call 8028e94 + if ((m = sb->sb_mb) != NULL) + 802fbc0: e0bffe17 ldw r2,-8(fp) + 802fbc4: 10800617 ldw r2,24(r2) + 802fbc8: e0bfff15 stw r2,-4(fp) + 802fbcc: e0bfff17 ldw r2,-4(fp) + 802fbd0: 10000726 beq r2,zero,802fbf0 + while (m->m_act) + 802fbd4: 00000306 br 802fbe4 + m = m->m_act; + 802fbd8: e0bfff17 ldw r2,-4(fp) + 802fbdc: 10800717 ldw r2,28(r2) + 802fbe0: e0bfff15 stw r2,-4(fp) + while (m->m_act) + 802fbe4: e0bfff17 ldw r2,-4(fp) + 802fbe8: 10800717 ldw r2,28(r2) + 802fbec: 103ffa1e bne r2,zero,802fbd8 + /* + * Put the first mbuf on the queue. + * Note this permits zero length records. + */ + sballoc(sb, m0); + 802fbf0: e0bffe17 ldw r2,-8(fp) + 802fbf4: 10c00017 ldw r3,0(r2) + 802fbf8: e0bffd17 ldw r2,-12(fp) + 802fbfc: 10800217 ldw r2,8(r2) + 802fc00: 1887883a add r3,r3,r2 + 802fc04: e0bffe17 ldw r2,-8(fp) + 802fc08: 10c00015 stw r3,0(r2) + if (m) + 802fc0c: e0bfff17 ldw r2,-4(fp) + 802fc10: 10000426 beq r2,zero,802fc24 + m->m_act = m0; + 802fc14: e0bfff17 ldw r2,-4(fp) + 802fc18: e0fffd17 ldw r3,-12(fp) + 802fc1c: 10c00715 stw r3,28(r2) + 802fc20: 00000306 br 802fc30 + else + sb->sb_mb = m0; + 802fc24: e0bffe17 ldw r2,-8(fp) + 802fc28: e0fffd17 ldw r3,-12(fp) + 802fc2c: 10c00615 stw r3,24(r2) + m = m0->m_next; + 802fc30: e0bffd17 ldw r2,-12(fp) + 802fc34: 10800617 ldw r2,24(r2) + 802fc38: e0bfff15 stw r2,-4(fp) + m0->m_next = 0; + 802fc3c: e0bffd17 ldw r2,-12(fp) + 802fc40: 10000615 stw zero,24(r2) + sbcompress(sb, m, m0); + 802fc44: e1bffd17 ldw r6,-12(fp) + 802fc48: e17fff17 ldw r5,-4(fp) + 802fc4c: e13ffe17 ldw r4,-8(fp) + 802fc50: 802fe500 call 802fe50 + EXIT_CRIT_SECTION(sb); + 802fc54: 8028ef40 call 8028ef4 + 802fc58: 00000106 br 802fc60 + return; + 802fc5c: 0001883a nop +} + 802fc60: e037883a mov sp,fp + 802fc64: dfc00117 ldw ra,4(sp) + 802fc68: df000017 ldw fp,0(sp) + 802fc6c: dec00204 addi sp,sp,8 + 802fc70: f800283a ret + +0802fc74 : + +int +sbappendaddr(struct sockbuf * sb, + struct sockaddr * asa, + struct mbuf * m0) +{ + 802fc74: defff804 addi sp,sp,-32 + 802fc78: dfc00715 stw ra,28(sp) + 802fc7c: df000615 stw fp,24(sp) + 802fc80: df000604 addi fp,sp,24 + 802fc84: e13ffc15 stw r4,-16(fp) + 802fc88: e17ffb15 stw r5,-20(fp) + 802fc8c: e1bffa15 stw r6,-24(fp) + struct mbuf * m, * n; + int space = sizeof (*asa); + 802fc90: 00800404 movi r2,16 + 802fc94: e0bffd15 stw r2,-12(fp) + + ENTER_CRIT_SECTION(sb); + 802fc98: 8028e940 call 8028e94 + for (m = m0; m; m = m->m_next) + 802fc9c: e0bffa17 ldw r2,-24(fp) + 802fca0: e0bfff15 stw r2,-4(fp) + 802fca4: 00000806 br 802fcc8 + space += m->m_len; + 802fca8: e0bfff17 ldw r2,-4(fp) + 802fcac: 10c00217 ldw r3,8(r2) + 802fcb0: e0bffd17 ldw r2,-12(fp) + 802fcb4: 1885883a add r2,r3,r2 + 802fcb8: e0bffd15 stw r2,-12(fp) + for (m = m0; m; m = m->m_next) + 802fcbc: e0bfff17 ldw r2,-4(fp) + 802fcc0: 10800617 ldw r2,24(r2) + 802fcc4: e0bfff15 stw r2,-4(fp) + 802fcc8: e0bfff17 ldw r2,-4(fp) + 802fccc: 103ff61e bne r2,zero,802fca8 + if (space > (int)sbspace(sb)) + 802fcd0: e0bffc17 ldw r2,-16(fp) + 802fcd4: 10800117 ldw r2,4(r2) + 802fcd8: 1007883a mov r3,r2 + 802fcdc: e0bffc17 ldw r2,-16(fp) + 802fce0: 10800017 ldw r2,0(r2) + 802fce4: 1885c83a sub r2,r3,r2 + 802fce8: 10000716 blt r2,zero,802fd08 + 802fcec: e0bffc17 ldw r2,-16(fp) + 802fcf0: 10c00117 ldw r3,4(r2) + 802fcf4: e0bffc17 ldw r2,-16(fp) + 802fcf8: 10800017 ldw r2,0(r2) + 802fcfc: 1885c83a sub r2,r3,r2 + 802fd00: 1007883a mov r3,r2 + 802fd04: 00000106 br 802fd0c + 802fd08: 0007883a mov r3,zero + 802fd0c: e0bffd17 ldw r2,-12(fp) + 802fd10: 1880030e bge r3,r2,802fd20 + { + EXIT_CRIT_SECTION(sb); + 802fd14: 8028ef40 call 8028ef4 + return (0); + 802fd18: 0005883a mov r2,zero + 802fd1c: 00004706 br 802fe3c + } + if ((m = m_getwithdata (MT_SONAME, sizeof (struct sockaddr))) == NULL) + 802fd20: 01400404 movi r5,16 + 802fd24: 01000244 movi r4,9 + 802fd28: 8029a700 call 8029a70 + 802fd2c: e0bfff15 stw r2,-4(fp) + 802fd30: e0bfff17 ldw r2,-4(fp) + 802fd34: 1000031e bne r2,zero,802fd44 + { + EXIT_CRIT_SECTION(sb); + 802fd38: 8028ef40 call 8028ef4 + return 0; + 802fd3c: 0005883a mov r2,zero + 802fd40: 00003e06 br 802fe3c + } + *mtod(m, struct sockaddr *) = *asa; + 802fd44: e0bfff17 ldw r2,-4(fp) + 802fd48: 10800317 ldw r2,12(r2) + 802fd4c: e0fffb17 ldw r3,-20(fp) + 802fd50: 1900000b ldhu r4,0(r3) + 802fd54: 1100000d sth r4,0(r2) + 802fd58: 1900008b ldhu r4,2(r3) + 802fd5c: 1100008d sth r4,2(r2) + 802fd60: 1900010b ldhu r4,4(r3) + 802fd64: 1100010d sth r4,4(r2) + 802fd68: 1900018b ldhu r4,6(r3) + 802fd6c: 1100018d sth r4,6(r2) + 802fd70: 1900020b ldhu r4,8(r3) + 802fd74: 1100020d sth r4,8(r2) + 802fd78: 1900028b ldhu r4,10(r3) + 802fd7c: 1100028d sth r4,10(r2) + 802fd80: 1900030b ldhu r4,12(r3) + 802fd84: 1100030d sth r4,12(r2) + 802fd88: 18c0038b ldhu r3,14(r3) + 802fd8c: 10c0038d sth r3,14(r2) + m->m_len = sizeof (*asa); + 802fd90: e0bfff17 ldw r2,-4(fp) + 802fd94: 00c00404 movi r3,16 + 802fd98: 10c00215 stw r3,8(r2) + sballoc (sb, m); + 802fd9c: e0bffc17 ldw r2,-16(fp) + 802fda0: 10c00017 ldw r3,0(r2) + 802fda4: e0bfff17 ldw r2,-4(fp) + 802fda8: 10800217 ldw r2,8(r2) + 802fdac: 1887883a add r3,r3,r2 + 802fdb0: e0bffc17 ldw r2,-16(fp) + 802fdb4: 10c00015 stw r3,0(r2) + if ((n = sb->sb_mb) != NULL) + 802fdb8: e0bffc17 ldw r2,-16(fp) + 802fdbc: 10800617 ldw r2,24(r2) + 802fdc0: e0bffe15 stw r2,-8(fp) + 802fdc4: e0bffe17 ldw r2,-8(fp) + 802fdc8: 10000b26 beq r2,zero,802fdf8 + { + while (n->m_act) + 802fdcc: 00000306 br 802fddc + n = n->m_act; + 802fdd0: e0bffe17 ldw r2,-8(fp) + 802fdd4: 10800717 ldw r2,28(r2) + 802fdd8: e0bffe15 stw r2,-8(fp) + while (n->m_act) + 802fddc: e0bffe17 ldw r2,-8(fp) + 802fde0: 10800717 ldw r2,28(r2) + 802fde4: 103ffa1e bne r2,zero,802fdd0 + n->m_act = m; + 802fde8: e0bffe17 ldw r2,-8(fp) + 802fdec: e0ffff17 ldw r3,-4(fp) + 802fdf0: 10c00715 stw r3,28(r2) + 802fdf4: 00000306 br 802fe04 + } else + sb->sb_mb = m; + 802fdf8: e0bffc17 ldw r2,-16(fp) + 802fdfc: e0ffff17 ldw r3,-4(fp) + 802fe00: 10c00615 stw r3,24(r2) + if (m->m_next) + 802fe04: e0bfff17 ldw r2,-4(fp) + 802fe08: 10800617 ldw r2,24(r2) + 802fe0c: 10000326 beq r2,zero,802fe1c + m = m->m_next; + 802fe10: e0bfff17 ldw r2,-4(fp) + 802fe14: 10800617 ldw r2,24(r2) + 802fe18: e0bfff15 stw r2,-4(fp) + if (m0) + 802fe1c: e0bffa17 ldw r2,-24(fp) + 802fe20: 10000426 beq r2,zero,802fe34 + sbcompress(sb, m0, m); + 802fe24: e1bfff17 ldw r6,-4(fp) + 802fe28: e17ffa17 ldw r5,-24(fp) + 802fe2c: e13ffc17 ldw r4,-16(fp) + 802fe30: 802fe500 call 802fe50 + + EXIT_CRIT_SECTION(sb); + 802fe34: 8028ef40 call 8028ef4 + return (1); + 802fe38: 00800044 movi r2,1 +} + 802fe3c: e037883a mov sp,fp + 802fe40: dfc00117 ldw ra,4(sp) + 802fe44: df000017 ldw fp,0(sp) + 802fe48: dec00204 addi sp,sp,8 + 802fe4c: f800283a ret + +0802fe50 : + +void +sbcompress(struct sockbuf * sb, + struct mbuf * m, + struct mbuf * n) +{ + 802fe50: defffb04 addi sp,sp,-20 + 802fe54: dfc00415 stw ra,16(sp) + 802fe58: df000315 stw fp,12(sp) + 802fe5c: df000304 addi fp,sp,12 + 802fe60: e13fff15 stw r4,-4(fp) + 802fe64: e17ffe15 stw r5,-8(fp) + 802fe68: e1bffd15 stw r6,-12(fp) + + while (m) + 802fe6c: 00006706 br 803000c + { + if (m->m_len == 0) + 802fe70: e0bffe17 ldw r2,-8(fp) + 802fe74: 10800217 ldw r2,8(r2) + 802fe78: 1000041e bne r2,zero,802fe8c + { + m = m_free(m); + 802fe7c: e13ffe17 ldw r4,-8(fp) + 802fe80: 8029bf80 call 8029bf8 + 802fe84: e0bffe15 stw r2,-8(fp) + continue; + 802fe88: 00006006 br 803000c + } + if (m->m_type != MT_RXDATA && + 802fe8c: e0bffe17 ldw r2,-8(fp) + 802fe90: 10800817 ldw r2,32(r2) + 802fe94: 10800060 cmpeqi r2,r2,1 + 802fe98: 1000111e bne r2,zero,802fee0 + m->m_type != MT_TXDATA && + 802fe9c: e0bffe17 ldw r2,-8(fp) + 802fea0: 10800817 ldw r2,32(r2) + if (m->m_type != MT_RXDATA && + 802fea4: 108000a0 cmpeqi r2,r2,2 + 802fea8: 10000d1e bne r2,zero,802fee0 + m->m_type != MT_SONAME) + 802feac: e0bffe17 ldw r2,-8(fp) + 802feb0: 10800817 ldw r2,32(r2) + m->m_type != MT_TXDATA && + 802feb4: 10800260 cmpeqi r2,r2,9 + 802feb8: 1000091e bne r2,zero,802fee0 + { + dprintf ("sbcomp:bad type %d\n", m->m_type); + 802febc: e0bffe17 ldw r2,-8(fp) + 802fec0: 10800817 ldw r2,32(r2) + 802fec4: 100b883a mov r5,r2 + 802fec8: 01020174 movhi r4,2053 + 802fecc: 212a8e04 addi r4,r4,-21960 + 802fed0: 8002c780 call 8002c78 + panic ("sbcomp:bad"); + 802fed4: 01020174 movhi r4,2053 + 802fed8: 212a9304 addi r4,r4,-21940 + 802fedc: 80271780 call 8027178 + /* If there is room for all the data in M in N, then + * just copy the data to N. Note that sbdrop will + * increment the n->m_data pointer, so that we must + * correct n->m_memsz. + */ + if ( n && (sb->sb_flags & SB_MBCOMP) && + 802fee0: e0bffd17 ldw r2,-12(fp) + 802fee4: 10003226 beq r2,zero,802ffb0 + 802fee8: e0bfff17 ldw r2,-4(fp) + 802feec: 1080070b ldhu r2,28(r2) + 802fef0: 10bfffcc andi r2,r2,65535 + 802fef4: 1080200c andi r2,r2,128 + 802fef8: 10002d26 beq r2,zero,802ffb0 + ((n->m_len + m->m_len) < + 802fefc: e0bffd17 ldw r2,-12(fp) + 802ff00: 10c00217 ldw r3,8(r2) + 802ff04: e0bffe17 ldw r2,-8(fp) + 802ff08: 10800217 ldw r2,8(r2) + 802ff0c: 1887883a add r3,r3,r2 + n->m_memsz - (n->m_data - n->m_base) ) ) + 802ff10: e0bffd17 ldw r2,-12(fp) + 802ff14: 10800517 ldw r2,20(r2) + 802ff18: e13ffd17 ldw r4,-12(fp) + 802ff1c: 21400317 ldw r5,12(r4) + 802ff20: e13ffd17 ldw r4,-12(fp) + 802ff24: 21000417 ldw r4,16(r4) + 802ff28: 2909c83a sub r4,r5,r4 + 802ff2c: 1105c83a sub r2,r2,r4 + if ( n && (sb->sb_flags & SB_MBCOMP) && + 802ff30: 18801f2e bgeu r3,r2,802ffb0 + { + MEMCPY(n->m_data+n->m_len, m->m_data, m->m_len); + 802ff34: e0bffd17 ldw r2,-12(fp) + 802ff38: 10c00317 ldw r3,12(r2) + 802ff3c: e0bffd17 ldw r2,-12(fp) + 802ff40: 10800217 ldw r2,8(r2) + 802ff44: 1887883a add r3,r3,r2 + 802ff48: e0bffe17 ldw r2,-8(fp) + 802ff4c: 11000317 ldw r4,12(r2) + 802ff50: e0bffe17 ldw r2,-8(fp) + 802ff54: 10800217 ldw r2,8(r2) + 802ff58: 100d883a mov r6,r2 + 802ff5c: 200b883a mov r5,r4 + 802ff60: 1809883a mov r4,r3 + 802ff64: 80086b80 call 80086b8 + sballoc(sb, m); + 802ff68: e0bfff17 ldw r2,-4(fp) + 802ff6c: 10c00017 ldw r3,0(r2) + 802ff70: e0bffe17 ldw r2,-8(fp) + 802ff74: 10800217 ldw r2,8(r2) + 802ff78: 1887883a add r3,r3,r2 + 802ff7c: e0bfff17 ldw r2,-4(fp) + 802ff80: 10c00015 stw r3,0(r2) + n->m_len += m->m_len; + 802ff84: e0bffd17 ldw r2,-12(fp) + 802ff88: 10c00217 ldw r3,8(r2) + 802ff8c: e0bffe17 ldw r2,-8(fp) + 802ff90: 10800217 ldw r2,8(r2) + 802ff94: 1887883a add r3,r3,r2 + 802ff98: e0bffd17 ldw r2,-12(fp) + 802ff9c: 10c00215 stw r3,8(r2) + m = m_free(m); + 802ffa0: e13ffe17 ldw r4,-8(fp) + 802ffa4: 8029bf80 call 8029bf8 + 802ffa8: e0bffe15 stw r2,-8(fp) + continue; + 802ffac: 00001706 br 803000c + } + sballoc(sb, m); + 802ffb0: e0bfff17 ldw r2,-4(fp) + 802ffb4: 10c00017 ldw r3,0(r2) + 802ffb8: e0bffe17 ldw r2,-8(fp) + 802ffbc: 10800217 ldw r2,8(r2) + 802ffc0: 1887883a add r3,r3,r2 + 802ffc4: e0bfff17 ldw r2,-4(fp) + 802ffc8: 10c00015 stw r3,0(r2) + if (n) + 802ffcc: e0bffd17 ldw r2,-12(fp) + 802ffd0: 10000426 beq r2,zero,802ffe4 + n->m_next = m; + 802ffd4: e0bffd17 ldw r2,-12(fp) + 802ffd8: e0fffe17 ldw r3,-8(fp) + 802ffdc: 10c00615 stw r3,24(r2) + 802ffe0: 00000306 br 802fff0 + else + sb->sb_mb = m; + 802ffe4: e0bfff17 ldw r2,-4(fp) + 802ffe8: e0fffe17 ldw r3,-8(fp) + 802ffec: 10c00615 stw r3,24(r2) + n = m; + 802fff0: e0bffe17 ldw r2,-8(fp) + 802fff4: e0bffd15 stw r2,-12(fp) + m = m->m_next; + 802fff8: e0bffe17 ldw r2,-8(fp) + 802fffc: 10800617 ldw r2,24(r2) + 8030000: e0bffe15 stw r2,-8(fp) + n->m_next = 0; + 8030004: e0bffd17 ldw r2,-12(fp) + 8030008: 10000615 stw zero,24(r2) + while (m) + 803000c: e0bffe17 ldw r2,-8(fp) + 8030010: 103f971e bne r2,zero,802fe70 + } +} + 8030014: 0001883a nop + 8030018: e037883a mov sp,fp + 803001c: dfc00117 ldw ra,4(sp) + 8030020: df000017 ldw fp,0(sp) + 8030024: dec00204 addi sp,sp,8 + 8030028: f800283a ret + +0803002c : + * RETURNS: + */ + +void +sbflush(struct sockbuf * sb) +{ + 803002c: defffd04 addi sp,sp,-12 + 8030030: dfc00215 stw ra,8(sp) + 8030034: df000115 stw fp,4(sp) + 8030038: df000104 addi fp,sp,4 + 803003c: e13fff15 stw r4,-4(fp) + ENTER_CRIT_SECTION(sb); + 8030040: 8028e940 call 8028e94 + if (sb->sb_flags & SB_LOCK) + 8030044: e0bfff17 ldw r2,-4(fp) + 8030048: 1080070b ldhu r2,28(r2) + 803004c: 10bfffcc andi r2,r2,65535 + 8030050: 1080004c andi r2,r2,1 + 8030054: 10000926 beq r2,zero,803007c + panic("sbflush"); + 8030058: 01020174 movhi r4,2053 + 803005c: 212a9604 addi r4,r4,-21928 + 8030060: 80271780 call 8027178 + while ((sb->sb_mbcnt) || (sb->sb_cc)) + 8030064: 00000506 br 803007c + sbdrop (sb, (int)sb->sb_cc); + 8030068: e0bfff17 ldw r2,-4(fp) + 803006c: 10800017 ldw r2,0(r2) + 8030070: 100b883a mov r5,r2 + 8030074: e13fff17 ldw r4,-4(fp) + 8030078: 80300b00 call 80300b0 + while ((sb->sb_mbcnt) || (sb->sb_cc)) + 803007c: e0bfff17 ldw r2,-4(fp) + 8030080: 10800217 ldw r2,8(r2) + 8030084: 103ff81e bne r2,zero,8030068 + 8030088: e0bfff17 ldw r2,-4(fp) + 803008c: 10800017 ldw r2,0(r2) + 8030090: 103ff51e bne r2,zero,8030068 + EXIT_CRIT_SECTION(sb); + 8030094: 8028ef40 call 8028ef4 +} + 8030098: 0001883a nop + 803009c: e037883a mov sp,fp + 80300a0: dfc00117 ldw ra,4(sp) + 80300a4: df000017 ldw fp,0(sp) + 80300a8: dec00204 addi sp,sp,8 + 80300ac: f800283a ret + +080300b0 : + * RETURNS: + */ + +void +sbdrop(struct sockbuf * sb, int len) +{ + 80300b0: defff904 addi sp,sp,-28 + 80300b4: dfc00615 stw ra,24(sp) + 80300b8: df000515 stw fp,20(sp) + 80300bc: df000504 addi fp,sp,20 + 80300c0: e13ffc15 stw r4,-16(fp) + 80300c4: e17ffb15 stw r5,-20(fp) + struct mbuf * m, * mn; + struct mbuf * next; + + ENTER_CRIT_SECTION(sb); + 80300c8: 8028e940 call 8028e94 + if ((m = sb->sb_mb) != NULL) + 80300cc: e0bffc17 ldw r2,-16(fp) + 80300d0: 10800617 ldw r2,24(r2) + 80300d4: e0bfff15 stw r2,-4(fp) + 80300d8: e0bfff17 ldw r2,-4(fp) + 80300dc: 10000426 beq r2,zero,80300f0 + next = m->m_act; + 80300e0: e0bfff17 ldw r2,-4(fp) + 80300e4: 10800717 ldw r2,28(r2) + 80300e8: e0bffe15 stw r2,-8(fp) + 80300ec: 00003706 br 80301cc + else + next = NULL; + 80300f0: e03ffe15 stw zero,-8(fp) + while (len > 0) + 80300f4: 00003506 br 80301cc + { + if (m == 0) + 80300f8: e0bfff17 ldw r2,-4(fp) + 80300fc: 10000b1e bne r2,zero,803012c + { + if (next == 0) + 8030100: e0bffe17 ldw r2,-8(fp) + 8030104: 1000031e bne r2,zero,8030114 + panic("sbdrop"); + 8030108: 01020174 movhi r4,2053 + 803010c: 212a9804 addi r4,r4,-21920 + 8030110: 80271780 call 8027178 + m = next; + 8030114: e0bffe17 ldw r2,-8(fp) + 8030118: e0bfff15 stw r2,-4(fp) + next = m->m_act; + 803011c: e0bfff17 ldw r2,-4(fp) + 8030120: 10800717 ldw r2,28(r2) + 8030124: e0bffe15 stw r2,-8(fp) + continue; + 8030128: 00002806 br 80301cc + } + if (m->m_len > (unsigned)len) + 803012c: e0bfff17 ldw r2,-4(fp) + 8030130: 10800217 ldw r2,8(r2) + 8030134: e0fffb17 ldw r3,-20(fp) + 8030138: 1880132e bgeu r3,r2,8030188 + { + m->m_len -= len; + 803013c: e0bfff17 ldw r2,-4(fp) + 8030140: 10c00217 ldw r3,8(r2) + 8030144: e0bffb17 ldw r2,-20(fp) + 8030148: 1887c83a sub r3,r3,r2 + 803014c: e0bfff17 ldw r2,-4(fp) + 8030150: 10c00215 stw r3,8(r2) + m->m_data += len; + 8030154: e0bfff17 ldw r2,-4(fp) + 8030158: 10c00317 ldw r3,12(r2) + 803015c: e0bffb17 ldw r2,-20(fp) + 8030160: 1887883a add r3,r3,r2 + 8030164: e0bfff17 ldw r2,-4(fp) + 8030168: 10c00315 stw r3,12(r2) + sb->sb_cc -= len; + 803016c: e0bffc17 ldw r2,-16(fp) + 8030170: 10c00017 ldw r3,0(r2) + 8030174: e0bffb17 ldw r2,-20(fp) + 8030178: 1887c83a sub r3,r3,r2 + 803017c: e0bffc17 ldw r2,-16(fp) + 8030180: 10c00015 stw r3,0(r2) + break; + 8030184: 00001306 br 80301d4 + } + len -= m->m_len; + 8030188: e0fffb17 ldw r3,-20(fp) + 803018c: e0bfff17 ldw r2,-4(fp) + 8030190: 10800217 ldw r2,8(r2) + 8030194: 1885c83a sub r2,r3,r2 + 8030198: e0bffb15 stw r2,-20(fp) + sbfree (sb, m); + 803019c: e0bffc17 ldw r2,-16(fp) + 80301a0: 10c00017 ldw r3,0(r2) + 80301a4: e0bfff17 ldw r2,-4(fp) + 80301a8: 10800217 ldw r2,8(r2) + 80301ac: 1887c83a sub r3,r3,r2 + 80301b0: e0bffc17 ldw r2,-16(fp) + 80301b4: 10c00015 stw r3,0(r2) + MFREE(m, mn); + 80301b8: e13fff17 ldw r4,-4(fp) + 80301bc: 8029bf80 call 8029bf8 + 80301c0: e0bffd15 stw r2,-12(fp) + m = mn; + 80301c4: e0bffd17 ldw r2,-12(fp) + 80301c8: e0bfff15 stw r2,-4(fp) + while (len > 0) + 80301cc: e0bffb17 ldw r2,-20(fp) + 80301d0: 00bfc916 blt zero,r2,80300f8 + } + while (m && m->m_len == 0) + 80301d4: 00000c06 br 8030208 + { + sbfree(sb, m); + 80301d8: e0bffc17 ldw r2,-16(fp) + 80301dc: 10c00017 ldw r3,0(r2) + 80301e0: e0bfff17 ldw r2,-4(fp) + 80301e4: 10800217 ldw r2,8(r2) + 80301e8: 1887c83a sub r3,r3,r2 + 80301ec: e0bffc17 ldw r2,-16(fp) + 80301f0: 10c00015 stw r3,0(r2) + MFREE(m, mn); + 80301f4: e13fff17 ldw r4,-4(fp) + 80301f8: 8029bf80 call 8029bf8 + 80301fc: e0bffd15 stw r2,-12(fp) + m = mn; + 8030200: e0bffd17 ldw r2,-12(fp) + 8030204: e0bfff15 stw r2,-4(fp) + while (m && m->m_len == 0) + 8030208: e0bfff17 ldw r2,-4(fp) + 803020c: 10000326 beq r2,zero,803021c + 8030210: e0bfff17 ldw r2,-4(fp) + 8030214: 10800217 ldw r2,8(r2) + 8030218: 103fef26 beq r2,zero,80301d8 + } + if (m) + 803021c: e0bfff17 ldw r2,-4(fp) + 8030220: 10000726 beq r2,zero,8030240 + { + sb->sb_mb = m; + 8030224: e0bffc17 ldw r2,-16(fp) + 8030228: e0ffff17 ldw r3,-4(fp) + 803022c: 10c00615 stw r3,24(r2) + m->m_act = next; + 8030230: e0bfff17 ldw r2,-4(fp) + 8030234: e0fffe17 ldw r3,-8(fp) + 8030238: 10c00715 stw r3,28(r2) + 803023c: 00000306 br 803024c + } else + sb->sb_mb = next; + 8030240: e0bffc17 ldw r2,-16(fp) + 8030244: e0fffe17 ldw r3,-8(fp) + 8030248: 10c00615 stw r3,24(r2) + EXIT_CRIT_SECTION(sb); + 803024c: 8028ef40 call 8028ef4 +} + 8030250: 0001883a nop + 8030254: e037883a mov sp,fp + 8030258: dfc00117 ldw ra,4(sp) + 803025c: df000017 ldw fp,0(sp) + 8030260: dec00204 addi sp,sp,8 + 8030264: f800283a ret + +08030268 : + * RETURNS: + */ + +void +sbdropend(struct sockbuf * sb, struct mbuf * m) +{ + 8030268: defff904 addi sp,sp,-28 + 803026c: dfc00615 stw ra,24(sp) + 8030270: df000515 stw fp,20(sp) + 8030274: df000504 addi fp,sp,20 + 8030278: e13ffc15 stw r4,-16(fp) + 803027c: e17ffb15 stw r5,-20(fp) + struct mbuf * nmb, * pmb; + int len; + ENTER_CRIT_SECTION(sb); + 8030280: 8028e940 call 8028e94 + len = mbuf_len(m); + 8030284: e13ffb17 ldw r4,-20(fp) + 8030288: 802a1d80 call 802a1d8 + 803028c: e0bffd15 stw r2,-12(fp) + if (len > 0) + 8030290: e0bffd17 ldw r2,-12(fp) + 8030294: 0080070e bge zero,r2,80302b4 + m_adj(sb->sb_mb, -len); /* Adjust the lengths of the mbuf chain */ + 8030298: e0bffc17 ldw r2,-16(fp) + 803029c: 10c00617 ldw r3,24(r2) + 80302a0: e0bffd17 ldw r2,-12(fp) + 80302a4: 0085c83a sub r2,zero,r2 + 80302a8: 100b883a mov r5,r2 + 80302ac: 1809883a mov r4,r3 + 80302b0: 802a0180 call 802a018 + nmb = sb->sb_mb; + 80302b4: e0bffc17 ldw r2,-16(fp) + 80302b8: 10800617 ldw r2,24(r2) + 80302bc: e0bfff15 stw r2,-4(fp) + pmb = NULL; + 80302c0: e03ffe15 stw zero,-8(fp) + if (sb->sb_mb->m_len == 0) + 80302c4: e0bffc17 ldw r2,-16(fp) + 80302c8: 10800617 ldw r2,24(r2) + 80302cc: 10800217 ldw r2,8(r2) + 80302d0: 1000081e bne r2,zero,80302f4 + sb->sb_mb = NULL; + 80302d4: e0bffc17 ldw r2,-16(fp) + 80302d8: 10000615 stw zero,24(r2) + while (nmb && (nmb->m_len !=0)) /* Release mbufs that have a 0 len */ + 80302dc: 00000506 br 80302f4 + { + pmb = nmb; /* Remember previous */ + 80302e0: e0bfff17 ldw r2,-4(fp) + 80302e4: e0bffe15 stw r2,-8(fp) + nmb = nmb->m_next; + 80302e8: e0bfff17 ldw r2,-4(fp) + 80302ec: 10800617 ldw r2,24(r2) + 80302f0: e0bfff15 stw r2,-4(fp) + while (nmb && (nmb->m_len !=0)) /* Release mbufs that have a 0 len */ + 80302f4: e0bfff17 ldw r2,-4(fp) + 80302f8: 10000326 beq r2,zero,8030308 + 80302fc: e0bfff17 ldw r2,-4(fp) + 8030300: 10800217 ldw r2,8(r2) + 8030304: 103ff61e bne r2,zero,80302e0 + } + if (nmb && (nmb->m_len == 0)) /* Assume once 0 len found, all the rest */ + 8030308: e0bfff17 ldw r2,-4(fp) + 803030c: 10000926 beq r2,zero,8030334 + 8030310: e0bfff17 ldw r2,-4(fp) + 8030314: 10800217 ldw r2,8(r2) + 8030318: 1000061e bne r2,zero,8030334 + { /* are zeroes */ + if (pmb != NULL) + 803031c: e0bffe17 ldw r2,-8(fp) + 8030320: 10000226 beq r2,zero,803032c + pmb->m_next = NULL; + 8030324: e0bffe17 ldw r2,-8(fp) + 8030328: 10000615 stw zero,24(r2) + m_freem(nmb); + 803032c: e13fff17 ldw r4,-4(fp) + 8030330: 8029cfc0 call 8029cfc + } + sb->sb_cc -= len; /* Do a sbfree using the len */ + 8030334: e0bffc17 ldw r2,-16(fp) + 8030338: 10c00017 ldw r3,0(r2) + 803033c: e0bffd17 ldw r2,-12(fp) + 8030340: 1887c83a sub r3,r3,r2 + 8030344: e0bffc17 ldw r2,-16(fp) + 8030348: 10c00015 stw r3,0(r2) + EXIT_CRIT_SECTION(sb); + 803034c: 8028ef40 call 8028ef4 +} + 8030350: 0001883a nop + 8030354: e037883a mov sp,fp + 8030358: dfc00117 ldw ra,4(sp) + 803035c: df000017 ldw fp,0(sp) + 8030360: dec00204 addi sp,sp,8 + 8030364: f800283a ret + +08030368 : + * RETURNS: + */ + +void +sbdroprecord(struct sockbuf * sb) +{ + 8030368: defffb04 addi sp,sp,-20 + 803036c: dfc00415 stw ra,16(sp) + 8030370: df000315 stw fp,12(sp) + 8030374: df000304 addi fp,sp,12 + 8030378: e13ffd15 stw r4,-12(fp) + struct mbuf * m, * mn; + + ENTER_CRIT_SECTION(sb); + 803037c: 8028e940 call 8028e94 + m = sb->sb_mb; + 8030380: e0bffd17 ldw r2,-12(fp) + 8030384: 10800617 ldw r2,24(r2) + 8030388: e0bfff15 stw r2,-4(fp) + if (m) + 803038c: e0bfff17 ldw r2,-4(fp) + 8030390: 10001226 beq r2,zero,80303dc + { sb->sb_mb = m->m_act; + 8030394: e0bfff17 ldw r2,-4(fp) + 8030398: 10c00717 ldw r3,28(r2) + 803039c: e0bffd17 ldw r2,-12(fp) + 80303a0: 10c00615 stw r3,24(r2) + do + { sbfree(sb, m); + 80303a4: e0bffd17 ldw r2,-12(fp) + 80303a8: 10c00017 ldw r3,0(r2) + 80303ac: e0bfff17 ldw r2,-4(fp) + 80303b0: 10800217 ldw r2,8(r2) + 80303b4: 1887c83a sub r3,r3,r2 + 80303b8: e0bffd17 ldw r2,-12(fp) + 80303bc: 10c00015 stw r3,0(r2) + MFREE(m, mn); + 80303c0: e13fff17 ldw r4,-4(fp) + 80303c4: 8029bf80 call 8029bf8 + 80303c8: e0bffe15 stw r2,-8(fp) + } while ((m = mn) != NULL); + 80303cc: e0bffe17 ldw r2,-8(fp) + 80303d0: e0bfff15 stw r2,-4(fp) + 80303d4: e0bfff17 ldw r2,-4(fp) + 80303d8: 103ff21e bne r2,zero,80303a4 + } + EXIT_CRIT_SECTION(sb); + 80303dc: 8028ef40 call 8028ef4 +} + 80303e0: 0001883a nop + 80303e4: e037883a mov sp,fp + 80303e8: dfc00117 ldw ra,4(sp) + 80303ec: df000017 ldw fp,0(sp) + 80303f0: dec00204 addi sp,sp,8 + 80303f4: f800283a ret + +080303f8 : +int +t_select(fd_set * in, /* lists of sockets to watch */ + fd_set * out, + fd_set * ex, + long tv) /* ticks to wait */ +{ + 80303f8: defe7204 addi sp,sp,-1592 + 80303fc: dfc18d15 stw ra,1588(sp) + 8030400: df018c15 stw fp,1584(sp) + 8030404: df018c04 addi fp,sp,1584 + 8030408: e13e7715 stw r4,-1572(fp) + 803040c: e17e7615 stw r5,-1576(fp) + 8030410: e1be7515 stw r6,-1580(fp) + 8030414: e1fe7415 stw r7,-1584(fp) + fd_set obits[3], ibits [3]; + u_long tmo; + int retval = 0; + 8030418: e03fff15 stw zero,-4(fp) + + MEMSET(&obits, 0, sizeof(obits)); + 803041c: e0bf3b04 addi r2,fp,-788 + 8030420: 0180c304 movi r6,780 + 8030424: 000b883a mov r5,zero + 8030428: 1009883a mov r4,r2 + 803042c: 80088e40 call 80088e4 + MEMSET(&ibits, 0, sizeof(ibits)); + 8030430: e0be7804 addi r2,fp,-1568 + 8030434: 0180c304 movi r6,780 + 8030438: 000b883a mov r5,zero + 803043c: 1009883a mov r4,r2 + 8030440: 80088e40 call 80088e4 + + if (in) + 8030444: e0be7717 ldw r2,-1572(fp) + 8030448: 10000526 beq r2,zero,8030460 + MEMCPY(&ibits[0], in, sizeof(fd_set)); + 803044c: e0be7804 addi r2,fp,-1568 + 8030450: 01804104 movi r6,260 + 8030454: e17e7717 ldw r5,-1572(fp) + 8030458: 1009883a mov r4,r2 + 803045c: 80086b80 call 80086b8 + if (out) + 8030460: e0be7617 ldw r2,-1576(fp) + 8030464: 10000626 beq r2,zero,8030480 + MEMCPY(&ibits[1], out, sizeof(fd_set)); + 8030468: e0be7804 addi r2,fp,-1568 + 803046c: 10804104 addi r2,r2,260 + 8030470: 01804104 movi r6,260 + 8030474: e17e7617 ldw r5,-1576(fp) + 8030478: 1009883a mov r4,r2 + 803047c: 80086b80 call 80086b8 + if (ex) + 8030480: e0be7517 ldw r2,-1580(fp) + 8030484: 10000626 beq r2,zero,80304a0 + MEMCPY(&ibits[2], ex, sizeof(fd_set)); + 8030488: e0be7804 addi r2,fp,-1568 + 803048c: 10808204 addi r2,r2,520 + 8030490: 01804104 movi r6,260 + 8030494: e17e7517 ldw r5,-1580(fp) + 8030498: 1009883a mov r4,r2 + 803049c: 80086b80 call 80086b8 + tmo = cticks + tv; + 80304a0: d0e07d17 ldw r3,-32268(gp) + 80304a4: e0be7417 ldw r2,-1584(fp) + 80304a8: 1885883a add r2,r3,r2 + 80304ac: e0bffe15 stw r2,-8(fp) + + /* if all the fd_sets are empty, just block; else do a real select() */ + if ((ibits[0].fd_count == 0) && (ibits[1].fd_count == 0) && + 80304b0: e0be7817 ldw r2,-1568(fp) + 80304b4: 10000c1e bne r2,zero,80304e8 + 80304b8: e0beb917 ldw r2,-1308(fp) + 80304bc: 10000a1e bne r2,zero,80304e8 + (ibits[2].fd_count == 0)) + 80304c0: e0befa17 ldw r2,-1048(fp) + if ((ibits[0].fd_count == 0) && (ibits[1].fd_count == 0) && + 80304c4: 1000081e bne r2,zero,80304e8 + { + if (tv > 0) /* make sure we don't block on nothing forever */ + 80304c8: e0be7417 ldw r2,-1584(fp) + 80304cc: 00801f0e bge zero,r2,803054c + while (tmo > cticks) + { + tk_yield(); + } +#else + TK_SLEEP(tv); + 80304d0: e0be7417 ldw r2,-1584(fp) + 80304d4: 10800044 addi r2,r2,1 + 80304d8: 10bfffcc andi r2,r2,65535 + 80304dc: 1009883a mov r4,r2 + 80304e0: 801730c0 call 801730c + if (tv > 0) /* make sure we don't block on nothing forever */ + 80304e4: 00001906 br 803054c + + /* Lock the net semaphore before going into selscan. Upon + * return we will either call tcp_sleep(), which unlocks the + * semaphore, or fall into the unlock statement. + */ + LOCK_NET_RESOURCE(NET_RESID); + 80304e8: 0009883a mov r4,zero + 80304ec: 8028f380 call 8028f38 + while ((retval = sock_selscan(ibits, obits)) == 0) + 80304f0: 00000a06 br 803051c + { + if (tv != -1L) + 80304f4: e0be7417 ldw r2,-1584(fp) + 80304f8: 10bfffe0 cmpeqi r2,r2,-1 + 80304fc: 1000031e bne r2,zero,803050c + { + if (tmo <= cticks) + 8030500: d0e07d17 ldw r3,-32268(gp) + 8030504: e0bffe17 ldw r2,-8(fp) + 8030508: 18800d2e bgeu r3,r2,8030540 + break; + } + select_wait = 1; + 803050c: 00800044 movi r2,1 + 8030510: d0a0850d sth r2,-32236(gp) + tcp_sleep (&select_wait); + 8030514: d1208504 addi r4,gp,-32236 + 8030518: 8027a540 call 8027a54 + while ((retval = sock_selscan(ibits, obits)) == 0) + 803051c: e0ff3b04 addi r3,fp,-788 + 8030520: e0be7804 addi r2,fp,-1568 + 8030524: 180b883a mov r5,r3 + 8030528: 1009883a mov r4,r2 + 803052c: 80305c80 call 80305c8 + 8030530: e0bfff15 stw r2,-4(fp) + 8030534: e0bfff17 ldw r2,-4(fp) + 8030538: 103fee26 beq r2,zero,80304f4 + 803053c: 00000106 br 8030544 + break; + 8030540: 0001883a nop + } + UNLOCK_NET_RESOURCE(NET_RESID); + 8030544: 0009883a mov r4,zero + 8030548: 8028ff40 call 8028ff4 + + } + + if (retval >= 0) + 803054c: e0bfff17 ldw r2,-4(fp) + 8030550: 10001716 blt r2,zero,80305b0 + { + if (in) + 8030554: e0be7717 ldw r2,-1572(fp) + 8030558: 10000526 beq r2,zero,8030570 + MEMCPY(in, &obits[0], sizeof(fd_set)); + 803055c: e0bf3b04 addi r2,fp,-788 + 8030560: 01804104 movi r6,260 + 8030564: 100b883a mov r5,r2 + 8030568: e13e7717 ldw r4,-1572(fp) + 803056c: 80086b80 call 80086b8 + if (out) + 8030570: e0be7617 ldw r2,-1576(fp) + 8030574: 10000626 beq r2,zero,8030590 + MEMCPY(out, &obits[1], sizeof(fd_set)); + 8030578: e0bf3b04 addi r2,fp,-788 + 803057c: 10804104 addi r2,r2,260 + 8030580: 01804104 movi r6,260 + 8030584: 100b883a mov r5,r2 + 8030588: e13e7617 ldw r4,-1576(fp) + 803058c: 80086b80 call 80086b8 + if (ex) + 8030590: e0be7517 ldw r2,-1580(fp) + 8030594: 10000626 beq r2,zero,80305b0 + MEMCPY(ex, &obits[2], sizeof(fd_set)); + 8030598: e0bf3b04 addi r2,fp,-788 + 803059c: 10808204 addi r2,r2,520 + 80305a0: 01804104 movi r6,260 + 80305a4: 100b883a mov r5,r2 + 80305a8: e13e7517 ldw r4,-1580(fp) + 80305ac: 80086b80 call 80086b8 + } + return retval; + 80305b0: e0bfff17 ldw r2,-4(fp) +} + 80305b4: e037883a mov sp,fp + 80305b8: dfc00117 ldw ra,4(sp) + 80305bc: df000017 ldw fp,0(sp) + 80305c0: dec00204 addi sp,sp,8 + 80305c4: f800283a ret + +080305c8 : + * RETURNS: + */ + +int +sock_selscan(fd_set * ibits, fd_set * obits) +{ + 80305c8: defff604 addi sp,sp,-40 + 80305cc: dfc00915 stw ra,36(sp) + 80305d0: df000815 stw fp,32(sp) + 80305d4: df000804 addi fp,sp,32 + 80305d8: e13ff915 stw r4,-28(fp) + 80305dc: e17ff815 stw r5,-32(fp) + fd_set *in, *out; + int which; + int sock; + int flag = 0; + 80305e0: e03ffd15 stw zero,-12(fp) + int num_sel = 0; + 80305e4: e03ffc15 stw zero,-16(fp) + + for (which = 0; which < 3; which++) + 80305e8: e03fff15 stw zero,-4(fp) + 80305ec: 00003d06 br 80306e4 + { + switch (which) + 80305f0: e0bfff17 ldw r2,-4(fp) + 80305f4: 10800060 cmpeqi r2,r2,1 + 80305f8: 1000081e bne r2,zero,803061c + 80305fc: e0bfff17 ldw r2,-4(fp) + 8030600: 108000a0 cmpeqi r2,r2,2 + 8030604: 1000081e bne r2,zero,8030628 + 8030608: e0bfff17 ldw r2,-4(fp) + 803060c: 1000081e bne r2,zero,8030630 + { + case 0: + flag = SOREAD; break; + 8030610: 00800044 movi r2,1 + 8030614: e0bffd15 stw r2,-12(fp) + 8030618: 00000506 br 8030630 + + case 1: + flag = SOWRITE; break; + 803061c: 00800084 movi r2,2 + 8030620: e0bffd15 stw r2,-12(fp) + 8030624: 00000206 br 8030630 + + case 2: + flag = 0; break; + 8030628: e03ffd15 stw zero,-12(fp) + 803062c: 0001883a nop + } + in = &ibits [which]; + 8030630: e0bfff17 ldw r2,-4(fp) + 8030634: 10804124 muli r2,r2,260 + 8030638: e0fff917 ldw r3,-28(fp) + 803063c: 1885883a add r2,r3,r2 + 8030640: e0bffb15 stw r2,-20(fp) + out = &obits [which]; + 8030644: e0bfff17 ldw r2,-4(fp) + 8030648: 10804124 muli r2,r2,260 + 803064c: e0fff817 ldw r3,-32(fp) + 8030650: 1885883a add r2,r3,r2 + 8030654: e0bffa15 stw r2,-24(fp) + for (sock = 0; sock < (int)in->fd_count; sock++) + 8030658: e03ffe15 stw zero,-8(fp) + 803065c: 00001906 br 80306c4 + { + if (sock_select (in->fd_array[sock], flag)) + 8030660: e0fffb17 ldw r3,-20(fp) + 8030664: e0bffe17 ldw r2,-8(fp) + 8030668: 10800044 addi r2,r2,1 + 803066c: 100490ba slli r2,r2,2 + 8030670: 1885883a add r2,r3,r2 + 8030674: 10800017 ldw r2,0(r2) + 8030678: e17ffd17 ldw r5,-12(fp) + 803067c: 1009883a mov r4,r2 + 8030680: 80307080 call 8030708 + 8030684: 10000c26 beq r2,zero,80306b8 + { + FD_SET(in->fd_array[sock], out); + 8030688: e0fffb17 ldw r3,-20(fp) + 803068c: e0bffe17 ldw r2,-8(fp) + 8030690: 10800044 addi r2,r2,1 + 8030694: 100490ba slli r2,r2,2 + 8030698: 1885883a add r2,r3,r2 + 803069c: 10800017 ldw r2,0(r2) + 80306a0: e17ffa17 ldw r5,-24(fp) + 80306a4: 1009883a mov r4,r2 + 80306a8: 8030b180 call 8030b18 + num_sel++; + 80306ac: e0bffc17 ldw r2,-16(fp) + 80306b0: 10800044 addi r2,r2,1 + 80306b4: e0bffc15 stw r2,-16(fp) + for (sock = 0; sock < (int)in->fd_count; sock++) + 80306b8: e0bffe17 ldw r2,-8(fp) + 80306bc: 10800044 addi r2,r2,1 + 80306c0: e0bffe15 stw r2,-8(fp) + 80306c4: e0bffb17 ldw r2,-20(fp) + 80306c8: 10800017 ldw r2,0(r2) + 80306cc: 1007883a mov r3,r2 + 80306d0: e0bffe17 ldw r2,-8(fp) + 80306d4: 10ffe216 blt r2,r3,8030660 + for (which = 0; which < 3; which++) + 80306d8: e0bfff17 ldw r2,-4(fp) + 80306dc: 10800044 addi r2,r2,1 + 80306e0: e0bfff15 stw r2,-4(fp) + 80306e4: e0bfff17 ldw r2,-4(fp) + 80306e8: 108000d0 cmplti r2,r2,3 + 80306ec: 103fc01e bne r2,zero,80305f0 + } + } + } + return num_sel; + 80306f0: e0bffc17 ldw r2,-16(fp) +} + 80306f4: e037883a mov sp,fp + 80306f8: dfc00117 ldw ra,4(sp) + 80306fc: df000017 ldw fp,0(sp) + 8030700: dec00204 addi sp,sp,8 + 8030704: f800283a ret + +08030708 : + * RETURNS: + */ + +int +sock_select(long sock, int flag) +{ + 8030708: defffa04 addi sp,sp,-24 + 803070c: dfc00515 stw ra,20(sp) + 8030710: df000415 stw fp,16(sp) + 8030714: df000404 addi fp,sp,16 + 8030718: e13ffd15 stw r4,-12(fp) + 803071c: e17ffc15 stw r5,-16(fp) + struct socket * so; + int ready = 0; + 8030720: e03fff15 stw zero,-4(fp) + + so = LONG2SO(sock); + 8030724: e0bffd17 ldw r2,-12(fp) + 8030728: 10bffc04 addi r2,r2,-16 + 803072c: 100490ba slli r2,r2,2 + 8030730: e0bffe15 stw r2,-8(fp) + + switch (flag) + 8030734: e0bffc17 ldw r2,-16(fp) + 8030738: 10800060 cmpeqi r2,r2,1 + 803073c: 1000061e bne r2,zero,8030758 + 8030740: e0bffc17 ldw r2,-16(fp) + 8030744: 108000a0 cmpeqi r2,r2,2 + 8030748: 1000211e bne r2,zero,80307d0 + 803074c: e0bffc17 ldw r2,-16(fp) + 8030750: 10004326 beq r2,zero,8030860 + 8030754: 00006006 br 80308d8 + { + case SOREAD: + /* can we read something from so? */ + if (so->so_rcv.sb_cc) + 8030758: e0bffe17 ldw r2,-8(fp) + 803075c: 10800a17 ldw r2,40(r2) + 8030760: 10000326 beq r2,zero,8030770 + { + ready = 1; + 8030764: 00800044 movi r2,1 + 8030768: e0bfff15 stw r2,-4(fp) + break; + 803076c: 00005a06 br 80308d8 + } + if (so->so_state & SS_CANTRCVMORE) + 8030770: e0bffe17 ldw r2,-8(fp) + 8030774: 1080088b ldhu r2,34(r2) + 8030778: 10bfffcc andi r2,r2,65535 + 803077c: 1080080c andi r2,r2,32 + 8030780: 10000326 beq r2,zero,8030790 + { ready = 1; + 8030784: 00800044 movi r2,1 + 8030788: e0bfff15 stw r2,-4(fp) + break; + 803078c: 00005206 br 80308d8 + } + if (so->so_qlen) /* attach is ready */ + 8030790: e0bffe17 ldw r2,-8(fp) + 8030794: 10801e43 ldbu r2,121(r2) + 8030798: 10803fcc andi r2,r2,255 + 803079c: 1080201c xori r2,r2,128 + 80307a0: 10bfe004 addi r2,r2,-128 + 80307a4: 10000326 beq r2,zero,80307b4 + { + ready = 1; + 80307a8: 00800044 movi r2,1 + 80307ac: e0bfff15 stw r2,-4(fp) + break; + 80307b0: 00004906 br 80308d8 + } + } +#endif /* TCP_ZEROCOPY */ + + /* fall to here if so is not ready to read */ + so->so_rcv.sb_flags |= SB_SEL; /* set flag for select wakeup */ + 80307b4: e0bffe17 ldw r2,-8(fp) + 80307b8: 1080110b ldhu r2,68(r2) + 80307bc: 10800214 ori r2,r2,8 + 80307c0: 1007883a mov r3,r2 + 80307c4: e0bffe17 ldw r2,-8(fp) + 80307c8: 10c0110d sth r3,68(r2) + break; + 80307cc: 00004206 br 80308d8 + + case SOWRITE: + if ((sbspace(&(so)->so_snd) > 0) && + 80307d0: e0bffe17 ldw r2,-8(fp) + 80307d4: 10801317 ldw r2,76(r2) + 80307d8: 1007883a mov r3,r2 + 80307dc: e0bffe17 ldw r2,-8(fp) + 80307e0: 10801217 ldw r2,72(r2) + 80307e4: 1885c83a sub r2,r3,r2 + 80307e8: 10001816 blt r2,zero,803084c + 80307ec: e0bffe17 ldw r2,-8(fp) + 80307f0: 10c01317 ldw r3,76(r2) + 80307f4: e0bffe17 ldw r2,-8(fp) + 80307f8: 10801217 ldw r2,72(r2) + 80307fc: 18801326 beq r3,r2,803084c + ((((so)->so_state&SS_ISCONNECTED) || + 8030800: e0bffe17 ldw r2,-8(fp) + 8030804: 1080088b ldhu r2,34(r2) + 8030808: 10bfffcc andi r2,r2,65535 + 803080c: 1080008c andi r2,r2,2 + if ((sbspace(&(so)->so_snd) > 0) && + 8030810: 10000b1e bne r2,zero,8030840 + ((so)->so_proto->pr_flags&PR_CONNREQUIRED)==0) || + 8030814: e0bffe17 ldw r2,-8(fp) + 8030818: 10800217 ldw r2,8(r2) + 803081c: 1080010b ldhu r2,4(r2) + 8030820: 10bfffcc andi r2,r2,65535 + 8030824: 1080010c andi r2,r2,4 + ((((so)->so_state&SS_ISCONNECTED) || + 8030828: 10000526 beq r2,zero,8030840 + ((so)->so_state & SS_CANTSENDMORE))) + 803082c: e0bffe17 ldw r2,-8(fp) + 8030830: 1080088b ldhu r2,34(r2) + 8030834: 10bfffcc andi r2,r2,65535 + 8030838: 1080040c andi r2,r2,16 + ((so)->so_proto->pr_flags&PR_CONNREQUIRED)==0) || + 803083c: 10000326 beq r2,zero,803084c + { + ready = 1; + 8030840: 00800044 movi r2,1 + 8030844: e0bfff15 stw r2,-4(fp) + break; + 8030848: 00002306 br 80308d8 + } + sbselqueue (&so->so_snd); + 803084c: e0bffe17 ldw r2,-8(fp) + 8030850: 10801204 addi r2,r2,72 + 8030854: 1009883a mov r4,r2 + 8030858: 802f8a40 call 802f8a4 + break; + 803085c: 00001e06 br 80308d8 + + case 0: + if (so->so_oobmark || (so->so_state & SS_RCVATMARK)) + 8030860: e0bffe17 ldw r2,-8(fp) + 8030864: 10801a17 ldw r2,104(r2) + 8030868: 1000051e bne r2,zero,8030880 + 803086c: e0bffe17 ldw r2,-8(fp) + 8030870: 1080088b ldhu r2,34(r2) + 8030874: 10bfffcc andi r2,r2,65535 + 8030878: 1080100c andi r2,r2,64 + 803087c: 10000326 beq r2,zero,803088c + { + ready = 1; + 8030880: 00800044 movi r2,1 + 8030884: e0bfff15 stw r2,-4(fp) + break; + 8030888: 00001306 br 80308d8 + } + if (so->so_error && + 803088c: e0bffe17 ldw r2,-8(fp) + 8030890: 10800617 ldw r2,24(r2) + 8030894: 10000b26 beq r2,zero,80308c4 + (so->so_error != EINPROGRESS) && + 8030898: e0bffe17 ldw r2,-8(fp) + 803089c: 10800617 ldw r2,24(r2) + if (so->so_error && + 80308a0: 10801de0 cmpeqi r2,r2,119 + 80308a4: 1000071e bne r2,zero,80308c4 + (so->so_error != EWOULDBLOCK)) + 80308a8: e0bffe17 ldw r2,-8(fp) + 80308ac: 10800617 ldw r2,24(r2) + (so->so_error != EINPROGRESS) && + 80308b0: 108002e0 cmpeqi r2,r2,11 + 80308b4: 1000031e bne r2,zero,80308c4 + { + ready = 1; + 80308b8: 00800044 movi r2,1 + 80308bc: e0bfff15 stw r2,-4(fp) + break; + 80308c0: 00000506 br 80308d8 + } + sbselqueue(&so->so_rcv); + 80308c4: e0bffe17 ldw r2,-8(fp) + 80308c8: 10800a04 addi r2,r2,40 + 80308cc: 1009883a mov r4,r2 + 80308d0: 802f8a40 call 802f8a4 + break; + 80308d4: 0001883a nop + } + + return ready; + 80308d8: e0bfff17 ldw r2,-4(fp) +} + 80308dc: e037883a mov sp,fp + 80308e0: dfc00117 ldw ra,4(sp) + 80308e4: df000017 ldw fp,0(sp) + 80308e8: dec00204 addi sp,sp,8 + 80308ec: f800283a ret + +080308f0 : +void +in_pcbnotify(struct inpcb * head, + struct in_addr * dst, + int errnum, + void (*notify) __P ((struct inpcb *))) +{ + 80308f0: defff804 addi sp,sp,-32 + 80308f4: dfc00715 stw ra,28(sp) + 80308f8: df000615 stw fp,24(sp) + 80308fc: df000604 addi fp,sp,24 + 8030900: e13ffd15 stw r4,-12(fp) + 8030904: e17ffc15 stw r5,-16(fp) + 8030908: e1bffb15 stw r6,-20(fp) + 803090c: e1fffa15 stw r7,-24(fp) + struct inpcb * inp, * oinp; + + for (inp = head->inp_next; inp != head;) + 8030910: e0bffd17 ldw r2,-12(fp) + 8030914: 10800017 ldw r2,0(r2) + 8030918: e0bfff15 stw r2,-4(fp) + 803091c: 00001c06 br 8030990 + { + if (inp->inp_faddr.s_addr != dst->s_addr || + 8030920: e0bfff17 ldw r2,-4(fp) + 8030924: 10c00317 ldw r3,12(r2) + 8030928: e0bffc17 ldw r2,-16(fp) + 803092c: 10800017 ldw r2,0(r2) + 8030930: 1880031e bne r3,r2,8030940 + inp->inp_socket == 0) + 8030934: e0bfff17 ldw r2,-4(fp) + 8030938: 10800817 ldw r2,32(r2) + if (inp->inp_faddr.s_addr != dst->s_addr || + 803093c: 1000041e bne r2,zero,8030950 + { + inp = inp->inp_next; + 8030940: e0bfff17 ldw r2,-4(fp) + 8030944: 10800017 ldw r2,0(r2) + 8030948: e0bfff15 stw r2,-4(fp) + continue; + 803094c: 00001006 br 8030990 + } + if (errnum) + 8030950: e0bffb17 ldw r2,-20(fp) + 8030954: 10000426 beq r2,zero,8030968 + inp->inp_socket->so_error = errnum; + 8030958: e0bfff17 ldw r2,-4(fp) + 803095c: 10800817 ldw r2,32(r2) + 8030960: e0fffb17 ldw r3,-20(fp) + 8030964: 10c00615 stw r3,24(r2) + oinp = inp; + 8030968: e0bfff17 ldw r2,-4(fp) + 803096c: e0bffe15 stw r2,-8(fp) + inp = inp->inp_next; + 8030970: e0bfff17 ldw r2,-4(fp) + 8030974: 10800017 ldw r2,0(r2) + 8030978: e0bfff15 stw r2,-4(fp) + if (notify) + 803097c: e0bffa17 ldw r2,-24(fp) + 8030980: 10000326 beq r2,zero,8030990 + (*notify)(oinp); + 8030984: e0bffa17 ldw r2,-24(fp) + 8030988: e13ffe17 ldw r4,-8(fp) + 803098c: 103ee83a callr r2 + for (inp = head->inp_next; inp != head;) + 8030990: e0ffff17 ldw r3,-4(fp) + 8030994: e0bffd17 ldw r2,-12(fp) + 8030998: 18bfe11e bne r3,r2,8030920 + } +} + 803099c: 0001883a nop + 80309a0: e037883a mov sp,fp + 80309a4: dfc00117 ldw ra,4(sp) + 80309a8: df000017 ldw fp,0(sp) + 80309ac: dec00204 addi sp,sp,8 + 80309b0: f800283a ret + +080309b4 : + * RETURNS: + */ + +void +tcp_notify(struct inpcb * inp) +{ + 80309b4: defffd04 addi sp,sp,-12 + 80309b8: dfc00215 stw ra,8(sp) + 80309bc: df000115 stw fp,4(sp) + 80309c0: df000104 addi fp,sp,4 + 80309c4: e13fff15 stw r4,-4(fp) + tcp_wakeup(&inp->inp_socket->so_timeo); + 80309c8: e0bfff17 ldw r2,-4(fp) + 80309cc: 10800817 ldw r2,32(r2) + 80309d0: 10800904 addi r2,r2,36 + 80309d4: 1009883a mov r4,r2 + 80309d8: 8027ba00 call 8027ba0 + sorwakeup(inp->inp_socket); + 80309dc: e0bfff17 ldw r2,-4(fp) + 80309e0: 10c00817 ldw r3,32(r2) + 80309e4: e0bfff17 ldw r2,-4(fp) + 80309e8: 10800817 ldw r2,32(r2) + 80309ec: 10800a04 addi r2,r2,40 + 80309f0: 100b883a mov r5,r2 + 80309f4: 1809883a mov r4,r3 + 80309f8: 802f94c0 call 802f94c + sowwakeup(inp->inp_socket); + 80309fc: e0bfff17 ldw r2,-4(fp) + 8030a00: 10c00817 ldw r3,32(r2) + 8030a04: e0bfff17 ldw r2,-4(fp) + 8030a08: 10800817 ldw r2,32(r2) + 8030a0c: 10801204 addi r2,r2,72 + 8030a10: 100b883a mov r5,r2 + 8030a14: 1809883a mov r4,r3 + 8030a18: 802f94c0 call 802f94c +} + 8030a1c: 0001883a nop + 8030a20: e037883a mov sp,fp + 8030a24: dfc00117 ldw ra,4(sp) + 8030a28: df000017 ldw fp,0(sp) + 8030a2c: dec00204 addi sp,sp,8 + 8030a30: f800283a ret + +08030a34 : + * compacts the fd_set. + */ + +void +ifd_clr(long sock, fd_set *set) +{ + 8030a34: defffb04 addi sp,sp,-20 + 8030a38: dfc00415 stw ra,16(sp) + 8030a3c: df000315 stw fp,12(sp) + 8030a40: df000304 addi fp,sp,12 + 8030a44: e13ffe15 stw r4,-8(fp) + 8030a48: e17ffd15 stw r5,-12(fp) + u_int i; + + for (i = 0; i < set->fd_count ; i++) + 8030a4c: e03fff15 stw zero,-4(fp) + 8030a50: 00002706 br 8030af0 + { + if (set->fd_array[i] == sock) + 8030a54: e0fffd17 ldw r3,-12(fp) + 8030a58: e0bfff17 ldw r2,-4(fp) + 8030a5c: 10800044 addi r2,r2,1 + 8030a60: 100490ba slli r2,r2,2 + 8030a64: 1885883a add r2,r3,r2 + 8030a68: 10800017 ldw r2,0(r2) + 8030a6c: e0fffe17 ldw r3,-8(fp) + 8030a70: 18801c1e bne r3,r2,8030ae4 + { + while (i + 1 < set->fd_count) + 8030a74: 00001006 br 8030ab8 + { + set->fd_array[i] = set->fd_array[i + 1]; + 8030a78: e0bfff17 ldw r2,-4(fp) + 8030a7c: 10800044 addi r2,r2,1 + 8030a80: e0fffd17 ldw r3,-12(fp) + 8030a84: 10800044 addi r2,r2,1 + 8030a88: 100490ba slli r2,r2,2 + 8030a8c: 1885883a add r2,r3,r2 + 8030a90: 10c00017 ldw r3,0(r2) + 8030a94: e13ffd17 ldw r4,-12(fp) + 8030a98: e0bfff17 ldw r2,-4(fp) + 8030a9c: 10800044 addi r2,r2,1 + 8030aa0: 100490ba slli r2,r2,2 + 8030aa4: 2085883a add r2,r4,r2 + 8030aa8: 10c00015 stw r3,0(r2) + i++; + 8030aac: e0bfff17 ldw r2,-4(fp) + 8030ab0: 10800044 addi r2,r2,1 + 8030ab4: e0bfff15 stw r2,-4(fp) + while (i + 1 < set->fd_count) + 8030ab8: e0bfff17 ldw r2,-4(fp) + 8030abc: 10c00044 addi r3,r2,1 + 8030ac0: e0bffd17 ldw r2,-12(fp) + 8030ac4: 10800017 ldw r2,0(r2) + 8030ac8: 18bfeb36 bltu r3,r2,8030a78 + } + set->fd_count--; + 8030acc: e0bffd17 ldw r2,-12(fp) + 8030ad0: 10800017 ldw r2,0(r2) + 8030ad4: 10ffffc4 addi r3,r2,-1 + 8030ad8: e0bffd17 ldw r2,-12(fp) + 8030adc: 10c00015 stw r3,0(r2) + return; + 8030ae0: 00000806 br 8030b04 + for (i = 0; i < set->fd_count ; i++) + 8030ae4: e0bfff17 ldw r2,-4(fp) + 8030ae8: 10800044 addi r2,r2,1 + 8030aec: e0bfff15 stw r2,-4(fp) + 8030af0: e0bffd17 ldw r2,-12(fp) + 8030af4: 10800017 ldw r2,0(r2) + 8030af8: e0ffff17 ldw r3,-4(fp) + 8030afc: 18bfd536 bltu r3,r2,8030a54 + } + } + +#ifdef NPDEBUG + dtrap(); /* socket wasn't found in array */ + 8030b00: 8028cd40 call 8028cd4 +#endif +} + 8030b04: e037883a mov sp,fp + 8030b08: dfc00117 ldw ra,4(sp) + 8030b0c: df000017 ldw fp,0(sp) + 8030b10: dec00204 addi sp,sp,8 + 8030b14: f800283a ret + +08030b18 : + * called if the fd_set structure is already full. + */ + +void +ifd_set(long sock, fd_set *set) +{ + 8030b18: defffc04 addi sp,sp,-16 + 8030b1c: dfc00315 stw ra,12(sp) + 8030b20: df000215 stw fp,8(sp) + 8030b24: df000204 addi fp,sp,8 + 8030b28: e13fff15 stw r4,-4(fp) + 8030b2c: e17ffe15 stw r5,-8(fp) + if (set->fd_count < FD_SETSIZE) + 8030b30: e0bffe17 ldw r2,-8(fp) + 8030b34: 10800017 ldw r2,0(r2) + 8030b38: 10801028 cmpgeui r2,r2,64 + 8030b3c: 10000c1e bne r2,zero,8030b70 + set->fd_array[set->fd_count++] = sock; + 8030b40: e0bffe17 ldw r2,-8(fp) + 8030b44: 10800017 ldw r2,0(r2) + 8030b48: 11000044 addi r4,r2,1 + 8030b4c: e0fffe17 ldw r3,-8(fp) + 8030b50: 19000015 stw r4,0(r3) + 8030b54: e0fffe17 ldw r3,-8(fp) + 8030b58: 10800044 addi r2,r2,1 + 8030b5c: 100490ba slli r2,r2,2 + 8030b60: 1885883a add r2,r3,r2 + 8030b64: e0ffff17 ldw r3,-4(fp) + 8030b68: 10c00015 stw r3,0(r2) +#ifdef NPDEBUG + else + dtrap(); +#endif +} + 8030b6c: 00000106 br 8030b74 + dtrap(); + 8030b70: 8028cd40 call 8028cd4 +} + 8030b74: 0001883a nop + 8030b78: e037883a mov sp,fp + 8030b7c: dfc00117 ldw ra,4(sp) + 8030b80: df000017 ldw fp,0(sp) + 8030b84: dec00204 addi sp,sp,8 + 8030b88: f800283a ret + +08030b8c : + * Tests if a socket is a member of a file descriptor set. + */ + +int /* actually, boolean */ +ifd_isset(long sock, fd_set *set) +{ + 8030b8c: defffc04 addi sp,sp,-16 + 8030b90: df000315 stw fp,12(sp) + 8030b94: df000304 addi fp,sp,12 + 8030b98: e13ffe15 stw r4,-8(fp) + 8030b9c: e17ffd15 stw r5,-12(fp) + u_int i; + + for (i = 0; i < set->fd_count ; i++) + 8030ba0: e03fff15 stw zero,-4(fp) + 8030ba4: 00000d06 br 8030bdc + { + if (set->fd_array[i] == sock) + 8030ba8: e0fffd17 ldw r3,-12(fp) + 8030bac: e0bfff17 ldw r2,-4(fp) + 8030bb0: 10800044 addi r2,r2,1 + 8030bb4: 100490ba slli r2,r2,2 + 8030bb8: 1885883a add r2,r3,r2 + 8030bbc: 10800017 ldw r2,0(r2) + 8030bc0: e0fffe17 ldw r3,-8(fp) + 8030bc4: 1880021e bne r3,r2,8030bd0 + return TRUE; + 8030bc8: 00800044 movi r2,1 + 8030bcc: 00000806 br 8030bf0 + for (i = 0; i < set->fd_count ; i++) + 8030bd0: e0bfff17 ldw r2,-4(fp) + 8030bd4: 10800044 addi r2,r2,1 + 8030bd8: e0bfff15 stw r2,-4(fp) + 8030bdc: e0bffd17 ldw r2,-12(fp) + 8030be0: 10800017 ldw r2,0(r2) + 8030be4: e0ffff17 ldw r3,-4(fp) + 8030be8: 18bfef36 bltu r3,r2,8030ba8 + } + return FALSE; + 8030bec: 0005883a mov r2,zero +} + 8030bf0: e037883a mov sp,fp + 8030bf4: df000017 ldw fp,0(sp) + 8030bf8: dec00104 addi sp,sp,4 + 8030bfc: f800283a ret + +08030c00 : + * NOTE: This is not part of the original FD_XXX() functionality. + */ + +long +ifd_get(unsigned i, fd_set *set) +{ + 8030c00: defffc04 addi sp,sp,-16 + 8030c04: dfc00315 stw ra,12(sp) + 8030c08: df000215 stw fp,8(sp) + 8030c0c: df000204 addi fp,sp,8 + 8030c10: e13fff15 stw r4,-4(fp) + 8030c14: e17ffe15 stw r5,-8(fp) + if (i < set->fd_count) + 8030c18: e0bffe17 ldw r2,-8(fp) + 8030c1c: 10800017 ldw r2,0(r2) + 8030c20: e0ffff17 ldw r3,-4(fp) + 8030c24: 1880072e bgeu r3,r2,8030c44 + return set->fd_array[i]; + 8030c28: e0fffe17 ldw r3,-8(fp) + 8030c2c: e0bfff17 ldw r2,-4(fp) + 8030c30: 10800044 addi r2,r2,1 + 8030c34: 100490ba slli r2,r2,2 + 8030c38: 1885883a add r2,r3,r2 + 8030c3c: 10800017 ldw r2,0(r2) + 8030c40: 00000206 br 8030c4c + else + { +#ifdef NPDEBUG + dtrap(); + 8030c44: 8028cd40 call 8028cd4 +#endif + return INVALID_SOCKET; + 8030c48: 00bfffc4 movi r2,-1 + } +} + 8030c4c: e037883a mov sp,fp + 8030c50: dfc00117 ldw ra,4(sp) + 8030c54: df000017 ldw fp,0(sp) + 8030c58: dec00204 addi sp,sp,8 + 8030c5c: f800283a ret + +08030c60 : + +int +tcp_reass(struct tcpcb * tp, + struct tcpiphdr * ti, + struct mbuf * ti_mbuf) +{ + 8030c60: defff504 addi sp,sp,-44 + 8030c64: dfc00a15 stw ra,40(sp) + 8030c68: df000915 stw fp,36(sp) + 8030c6c: df000904 addi fp,sp,36 + 8030c70: e13ff915 stw r4,-28(fp) + 8030c74: e17ff815 stw r5,-32(fp) + 8030c78: e1bff715 stw r6,-36(fp) + struct tcpiphdr * q; + struct socket * so = tp->t_inpcb->inp_socket; + 8030c7c: e0bff917 ldw r2,-28(fp) + 8030c80: 10800d17 ldw r2,52(r2) + 8030c84: 10800817 ldw r2,32(r2) + 8030c88: e0bffe15 stw r2,-8(fp) + + /* + * Call with ti==0 after become established to + * force pre-ESTABLISHED data up to user socket. + */ + if (ti == 0) + 8030c8c: e0bff817 ldw r2,-32(fp) + 8030c90: 10009c26 beq r2,zero,8030f04 + goto present; + + /* + * Find a segment which begins after this one does. + */ + for (q = tp->seg_next; q != (struct tcpiphdr *)tp; + 8030c94: e0bff917 ldw r2,-28(fp) + 8030c98: 10800017 ldw r2,0(r2) + 8030c9c: e0bfff15 stw r2,-4(fp) + 8030ca0: 00000906 br 8030cc8 + q = (struct tcpiphdr *)q->ti_next) + { + if (SEQ_GT(q->ti_seq, ti->ti_seq)) + 8030ca4: e0bfff17 ldw r2,-4(fp) + 8030ca8: 10c00617 ldw r3,24(r2) + 8030cac: e0bff817 ldw r2,-32(fp) + 8030cb0: 10800617 ldw r2,24(r2) + 8030cb4: 1885c83a sub r2,r3,r2 + 8030cb8: 00800716 blt zero,r2,8030cd8 + q = (struct tcpiphdr *)q->ti_next) + 8030cbc: e0bfff17 ldw r2,-4(fp) + 8030cc0: 10800017 ldw r2,0(r2) + 8030cc4: e0bfff15 stw r2,-4(fp) + for (q = tp->seg_next; q != (struct tcpiphdr *)tp; + 8030cc8: e0ffff17 ldw r3,-4(fp) + 8030ccc: e0bff917 ldw r2,-28(fp) + 8030cd0: 18bff41e bne r3,r2,8030ca4 + 8030cd4: 00000106 br 8030cdc + break; + 8030cd8: 0001883a nop + /* + * If there is a preceding segment, it may provide some of + * our data already. If so, drop the data from the incoming + * segment. If it provides all of our data, drop us. + */ + if ((struct tcpiphdr *)q->ti_prev != (struct tcpiphdr *)tp) + 8030cdc: e0bfff17 ldw r2,-4(fp) + 8030ce0: 10800117 ldw r2,4(r2) + 8030ce4: e0fff917 ldw r3,-28(fp) + 8030ce8: 18803b26 beq r3,r2,8030dd8 + { + long i; + q = (struct tcpiphdr *)q->ti_prev; + 8030cec: e0bfff17 ldw r2,-4(fp) + 8030cf0: 10800117 ldw r2,4(r2) + 8030cf4: e0bfff15 stw r2,-4(fp) + /* conversion to int (in i) handles seq wraparound */ + i = q->ti_seq + q->ti_len - ti->ti_seq; + 8030cf8: e0bfff17 ldw r2,-4(fp) + 8030cfc: 10c00617 ldw r3,24(r2) + 8030d00: e0bfff17 ldw r2,-4(fp) + 8030d04: 1080028b ldhu r2,10(r2) + 8030d08: 10bfffcc andi r2,r2,65535 + 8030d0c: 1887883a add r3,r3,r2 + 8030d10: e0bff817 ldw r2,-32(fp) + 8030d14: 10800617 ldw r2,24(r2) + 8030d18: 1885c83a sub r2,r3,r2 + 8030d1c: e0bffd15 stw r2,-12(fp) + if (i > 0) + 8030d20: e0bffd17 ldw r2,-12(fp) + 8030d24: 0080290e bge zero,r2,8030dcc + { + if (i >= (long)ti->ti_len) + 8030d28: e0bff817 ldw r2,-32(fp) + 8030d2c: 1080028b ldhu r2,10(r2) + 8030d30: 10bfffcc andi r2,r2,65535 + 8030d34: e0fffd17 ldw r3,-12(fp) + 8030d38: 18801416 blt r3,r2,8030d8c + { + tcpstat.tcps_rcvduppack++; + 8030d3c: 008201b4 movhi r2,2054 + 8030d40: 10b8c317 ldw r2,-7412(r2) + 8030d44: 10c00044 addi r3,r2,1 + 8030d48: 008201b4 movhi r2,2054 + 8030d4c: 10f8c315 stw r3,-7412(r2) + tcpstat.tcps_rcvdupbyte += ti->ti_len; + 8030d50: 008201b4 movhi r2,2054 + 8030d54: 10f8c417 ldw r3,-7408(r2) + 8030d58: e0bff817 ldw r2,-32(fp) + 8030d5c: 1080028b ldhu r2,10(r2) + 8030d60: 10bfffcc andi r2,r2,65535 + 8030d64: 1887883a add r3,r3,r2 + 8030d68: 008201b4 movhi r2,2054 + 8030d6c: 10f8c415 stw r3,-7408(r2) + GOTO_DROP; + 8030d70: 008025c4 movi r2,151 + 8030d74: d0a08715 stw r2,-32228(gp) + 8030d78: 0001883a nop + } while (ti != (struct tcpiphdr *)tp && ti->ti_seq == tp->rcv_nxt); + sorwakeup(so); + return (flags); +drop: + /**m_freem (dtom(ti));**/ + m_freem (ti_mbuf); + 8030d7c: e13ff717 ldw r4,-36(fp) + 8030d80: 8029cfc0 call 8029cfc + return (0); + 8030d84: 0005883a mov r2,zero + 8030d88: 0000ac06 br 803103c + m_adj (ti_mbuf, (int)i); + 8030d8c: e17ffd17 ldw r5,-12(fp) + 8030d90: e13ff717 ldw r4,-36(fp) + 8030d94: 802a0180 call 802a018 + ti->ti_len -= (short)i; + 8030d98: e0bff817 ldw r2,-32(fp) + 8030d9c: 1080028b ldhu r2,10(r2) + 8030da0: e0fffd17 ldw r3,-12(fp) + 8030da4: 10c5c83a sub r2,r2,r3 + 8030da8: 1007883a mov r3,r2 + 8030dac: e0bff817 ldw r2,-32(fp) + 8030db0: 10c0028d sth r3,10(r2) + ti->ti_seq += (tcp_seq)i; + 8030db4: e0bff817 ldw r2,-32(fp) + 8030db8: 10c00617 ldw r3,24(r2) + 8030dbc: e0bffd17 ldw r2,-12(fp) + 8030dc0: 1887883a add r3,r3,r2 + 8030dc4: e0bff817 ldw r2,-32(fp) + 8030dc8: 10c00615 stw r3,24(r2) + q = (struct tcpiphdr *)(q->ti_next); + 8030dcc: e0bfff17 ldw r2,-4(fp) + 8030dd0: 10800017 ldw r2,0(r2) + 8030dd4: e0bfff15 stw r2,-4(fp) + tcpstat.tcps_rcvoopack++; + 8030dd8: 008201b4 movhi r2,2054 + 8030ddc: 10b8c717 ldw r2,-7396(r2) + 8030de0: 10c00044 addi r3,r2,1 + 8030de4: 008201b4 movhi r2,2054 + 8030de8: 10f8c715 stw r3,-7396(r2) + tcpstat.tcps_rcvoobyte += ti->ti_len; + 8030dec: 008201b4 movhi r2,2054 + 8030df0: 10f8c817 ldw r3,-7392(r2) + 8030df4: e0bff817 ldw r2,-32(fp) + 8030df8: 1080028b ldhu r2,10(r2) + 8030dfc: 10bfffcc andi r2,r2,65535 + 8030e00: 1887883a add r3,r3,r2 + 8030e04: 008201b4 movhi r2,2054 + 8030e08: 10f8c815 stw r3,-7392(r2) + while (q != (struct tcpiphdr *)tp) + 8030e0c: 00003206 br 8030ed8 + int i = (int)((ti->ti_seq + ti->ti_len) - q->ti_seq); + 8030e10: e0bff817 ldw r2,-32(fp) + 8030e14: 10c00617 ldw r3,24(r2) + 8030e18: e0bff817 ldw r2,-32(fp) + 8030e1c: 1080028b ldhu r2,10(r2) + 8030e20: 10bfffcc andi r2,r2,65535 + 8030e24: 1887883a add r3,r3,r2 + 8030e28: e0bfff17 ldw r2,-4(fp) + 8030e2c: 10800617 ldw r2,24(r2) + 8030e30: 1885c83a sub r2,r3,r2 + 8030e34: e0bffc15 stw r2,-16(fp) + if (i <= 0) + 8030e38: e0bffc17 ldw r2,-16(fp) + 8030e3c: 00802a0e bge zero,r2,8030ee8 + if (i < (int)(q->ti_len)) + 8030e40: e0bfff17 ldw r2,-4(fp) + 8030e44: 1080028b ldhu r2,10(r2) + 8030e48: 10bfffcc andi r2,r2,65535 + 8030e4c: e0fffc17 ldw r3,-16(fp) + 8030e50: 1880130e bge r3,r2,8030ea0 + q->ti_seq += i; + 8030e54: e0bfff17 ldw r2,-4(fp) + 8030e58: 10c00617 ldw r3,24(r2) + 8030e5c: e0bffc17 ldw r2,-16(fp) + 8030e60: 1887883a add r3,r3,r2 + 8030e64: e0bfff17 ldw r2,-4(fp) + 8030e68: 10c00615 stw r3,24(r2) + q->ti_len -= (u_short)i; + 8030e6c: e0bfff17 ldw r2,-4(fp) + 8030e70: 1080028b ldhu r2,10(r2) + 8030e74: e0fffc17 ldw r3,-16(fp) + 8030e78: 10c5c83a sub r2,r2,r3 + 8030e7c: 1007883a mov r3,r2 + 8030e80: e0bfff17 ldw r2,-4(fp) + 8030e84: 10c0028d sth r3,10(r2) + m_adj (dtom(q), (int)i); + 8030e88: e13fff17 ldw r4,-4(fp) + 8030e8c: 802a22c0 call 802a22c + 8030e90: e17ffc17 ldw r5,-16(fp) + 8030e94: 1009883a mov r4,r2 + 8030e98: 802a0180 call 802a018 + break; + 8030e9c: 00001306 br 8030eec + q = (struct tcpiphdr *)q->ti_next; + 8030ea0: e0bfff17 ldw r2,-4(fp) + 8030ea4: 10800017 ldw r2,0(r2) + 8030ea8: e0bfff15 stw r2,-4(fp) + m = dtom(q->ti_prev); + 8030eac: e0bfff17 ldw r2,-4(fp) + 8030eb0: 10800117 ldw r2,4(r2) + 8030eb4: 1009883a mov r4,r2 + 8030eb8: 802a22c0 call 802a22c + 8030ebc: e0bffb15 stw r2,-20(fp) + remque (q->ti_prev); + 8030ec0: e0bfff17 ldw r2,-4(fp) + 8030ec4: 10800117 ldw r2,4(r2) + 8030ec8: 1009883a mov r4,r2 + 8030ecc: 802a2c40 call 802a2c4 + m_freem (m); + 8030ed0: e13ffb17 ldw r4,-20(fp) + 8030ed4: 8029cfc0 call 8029cfc + while (q != (struct tcpiphdr *)tp) + 8030ed8: e0ffff17 ldw r3,-4(fp) + 8030edc: e0bff917 ldw r2,-28(fp) + 8030ee0: 18bfcb1e bne r3,r2,8030e10 + 8030ee4: 00000106 br 8030eec + break; + 8030ee8: 0001883a nop + insque(ti, q->ti_prev); + 8030eec: e0bfff17 ldw r2,-4(fp) + 8030ef0: 10800117 ldw r2,4(r2) + 8030ef4: 100b883a mov r5,r2 + 8030ef8: e13ff817 ldw r4,-32(fp) + 8030efc: 802a3340 call 802a334 + 8030f00: 00000106 br 8030f08 + goto present; + 8030f04: 0001883a nop + if (TCPS_HAVERCVDSYN (tp->t_state) == 0) + 8030f08: e0bff917 ldw r2,-28(fp) + 8030f0c: 10800217 ldw r2,8(r2) + 8030f10: 108000c8 cmpgei r2,r2,3 + 8030f14: 1000021e bne r2,zero,8030f20 + return (0); + 8030f18: 0005883a mov r2,zero + 8030f1c: 00004706 br 803103c + ti = tp->seg_next; + 8030f20: e0bff917 ldw r2,-28(fp) + 8030f24: 10800017 ldw r2,0(r2) + 8030f28: e0bff815 stw r2,-32(fp) + if (ti == (struct tcpiphdr *)tp || ti->ti_seq != tp->rcv_nxt) + 8030f2c: e0fff817 ldw r3,-32(fp) + 8030f30: e0bff917 ldw r2,-28(fp) + 8030f34: 18800526 beq r3,r2,8030f4c + 8030f38: e0bff817 ldw r2,-32(fp) + 8030f3c: 10c00617 ldw r3,24(r2) + 8030f40: e0bff917 ldw r2,-28(fp) + 8030f44: 10801617 ldw r2,88(r2) + 8030f48: 18800226 beq r3,r2,8030f54 + return (0); + 8030f4c: 0005883a mov r2,zero + 8030f50: 00003a06 br 803103c + if (tp->t_state == TCPS_SYN_RECEIVED && ti->ti_len) + 8030f54: e0bff917 ldw r2,-28(fp) + 8030f58: 10800217 ldw r2,8(r2) + 8030f5c: 108000d8 cmpnei r2,r2,3 + 8030f60: 1000061e bne r2,zero,8030f7c + 8030f64: e0bff817 ldw r2,-32(fp) + 8030f68: 1080028b ldhu r2,10(r2) + 8030f6c: 10bfffcc andi r2,r2,65535 + 8030f70: 10000226 beq r2,zero,8030f7c + return (0); + 8030f74: 0005883a mov r2,zero + 8030f78: 00003006 br 803103c + tp->rcv_nxt += ti->ti_len; + 8030f7c: e0bff917 ldw r2,-28(fp) + 8030f80: 10c01617 ldw r3,88(r2) + 8030f84: e0bff817 ldw r2,-32(fp) + 8030f88: 1080028b ldhu r2,10(r2) + 8030f8c: 10bfffcc andi r2,r2,65535 + 8030f90: 1887883a add r3,r3,r2 + 8030f94: e0bff917 ldw r2,-28(fp) + 8030f98: 10c01615 stw r3,88(r2) + flags = ti->ti_flags & TH_FIN; + 8030f9c: e0bff817 ldw r2,-32(fp) + 8030fa0: 10800843 ldbu r2,33(r2) + 8030fa4: 10803fcc andi r2,r2,255 + 8030fa8: 1080004c andi r2,r2,1 + 8030fac: e0bffa15 stw r2,-24(fp) + remque(ti); + 8030fb0: e13ff817 ldw r4,-32(fp) + 8030fb4: 802a2c40 call 802a2c4 + m = dtom(ti); + 8030fb8: e13ff817 ldw r4,-32(fp) + 8030fbc: 802a22c0 call 802a22c + 8030fc0: e0bffb15 stw r2,-20(fp) + ti = (struct tcpiphdr *)ti->ti_next; + 8030fc4: e0bff817 ldw r2,-32(fp) + 8030fc8: 10800017 ldw r2,0(r2) + 8030fcc: e0bff815 stw r2,-32(fp) + if (so->so_state & SS_CANTRCVMORE) + 8030fd0: e0bffe17 ldw r2,-8(fp) + 8030fd4: 1080088b ldhu r2,34(r2) + 8030fd8: 10bfffcc andi r2,r2,65535 + 8030fdc: 1080080c andi r2,r2,32 + 8030fe0: 10000326 beq r2,zero,8030ff0 + m_freem (m); + 8030fe4: e13ffb17 ldw r4,-20(fp) + 8030fe8: 8029cfc0 call 8029cfc + 8030fec: 00000506 br 8031004 + sbappend (&so->so_rcv, m); + 8030ff0: e0bffe17 ldw r2,-8(fp) + 8030ff4: 10800a04 addi r2,r2,40 + 8030ff8: e17ffb17 ldw r5,-20(fp) + 8030ffc: 1009883a mov r4,r2 + 8031000: 802fafc0 call 802fafc + } while (ti != (struct tcpiphdr *)tp && ti->ti_seq == tp->rcv_nxt); + 8031004: e0fff817 ldw r3,-32(fp) + 8031008: e0bff917 ldw r2,-28(fp) + 803100c: 18800526 beq r3,r2,8031024 + 8031010: e0bff817 ldw r2,-32(fp) + 8031014: 10c00617 ldw r3,24(r2) + 8031018: e0bff917 ldw r2,-28(fp) + 803101c: 10801617 ldw r2,88(r2) + 8031020: 18bfd626 beq r3,r2,8030f7c + sorwakeup(so); + 8031024: e0bffe17 ldw r2,-8(fp) + 8031028: 10800a04 addi r2,r2,40 + 803102c: 100b883a mov r5,r2 + 8031030: e13ffe17 ldw r4,-8(fp) + 8031034: 802f94c0 call 802f94c + return (flags); + 8031038: e0bffa17 ldw r2,-24(fp) +} + 803103c: e037883a mov sp,fp + 8031040: dfc00117 ldw ra,4(sp) + 8031044: df000017 ldw fp,0(sp) + 8031048: dec00204 addi sp,sp,8 + 803104c: f800283a ret + +08031050 : + * RETURNS: void + */ + +void +tcp_input(struct mbuf * m, NET ifp) +{ + 8031050: deffdf04 addi sp,sp,-132 + 8031054: dfc02015 stw ra,128(sp) + 8031058: df001f15 stw fp,124(sp) + 803105c: df001f04 addi fp,sp,124 + 8031060: e13fe415 stw r4,-112(fp) + 8031064: e17fe315 stw r5,-116(fp) + ip6_addr ip6_src; + ip6_addr ip6_dst; +#endif /* IP_V6 */ + struct tcpiphdr * ti; + struct inpcb * inp; + struct mbuf * om = 0; + 8031068: e03ffd15 stw zero,-12(fp) + int len, tlen, off; + struct tcpcb * tp = 0; + 803106c: e03ffc15 stw zero,-16(fp) + int tiflags; + struct socket * so = NULL; + 8031070: e03ffa15 stw zero,-24(fp) + int todrop, acked, ourfinisacked, needoutput = 0; + 8031074: e03ff715 stw zero,-36(fp) + int dropsocket = 0; + 8031078: e03ff615 stw zero,-40(fp) + long iss = 0; + 803107c: e03ff515 stw zero,-44(fp) +#ifdef DO_TCPTRACE + int ostate; +#endif + + + tcpstat.tcps_rcvtotal++; + 8031080: 008201b4 movhi r2,2054 + 8031084: 10b8bd17 ldw r2,-7436(r2) + 8031088: 10c00044 addi r3,r2,1 + 803108c: 008201b4 movhi r2,2054 + 8031090: 10f8bd15 stw r3,-7436(r2) + TCP_MIB_INC(tcpInSegs); /* keep MIB stats */ + 8031094: 008201b4 movhi r2,2054 + 8031098: 10b87f17 ldw r2,-7684(r2) + 803109c: 10c00044 addi r3,r2,1 + 80310a0: 008201b4 movhi r2,2054 + 80310a4: 10f87f15 stw r3,-7684(r2) + { + /* + * Get IP and TCP header together in first mbuf. + * Note: IP leaves IP header in first mbuf. + */ + pip = mtod(m, struct ip *); + 80310a8: e0bfe417 ldw r2,-112(fp) + 80310ac: 10800317 ldw r2,12(r2) + 80310b0: e0bfff15 stw r2,-4(fp) + if (pip->ip_ver_ihl > 0x45) /* IP v4, 5 dword hdr len */ + 80310b4: e0bfff17 ldw r2,-4(fp) + 80310b8: 10800003 ldbu r2,0(r2) + 80310bc: 10803fcc andi r2,r2,255 + 80310c0: 108011b0 cmpltui r2,r2,70 + 80310c4: 1000061e bne r2,zero,80310e0 + { + np_stripoptions(pip, (struct mbuf *)m); + 80310c8: e17fe417 ldw r5,-112(fp) + 80310cc: e13fff17 ldw r4,-4(fp) + 80310d0: 802ac180 call 802ac18 + pip = mtod(m, struct ip *); + 80310d4: e0bfe417 ldw r2,-112(fp) + 80310d8: 10800317 ldw r2,12(r2) + 80310dc: e0bfff15 stw r2,-4(fp) + } + if (m->m_len < ((sizeof (struct ip) + sizeof (struct tcphdr)))) + 80310e0: e0bfe417 ldw r2,-112(fp) + 80310e4: 10800217 ldw r2,8(r2) + 80310e8: 10800a28 cmpgeui r2,r2,40 + 80310ec: 1000061e bne r2,zero,8031108 + { + tcpstat.tcps_rcvshort++; + 80310f0: 008201b4 movhi r2,2054 + 80310f4: 10b8c217 ldw r2,-7416(r2) + 80310f8: 10c00044 addi r3,r2,1 + 80310fc: 008201b4 movhi r2,2054 + 8031100: 10f8c215 stw r3,-7416(r2) + return; + 8031104: 00085206 br 8033250 + } + tlen = pip->ip_len; /* this was fudged by IP layer */ + 8031108: e0bfff17 ldw r2,-4(fp) + 803110c: 1080008b ldhu r2,2(r2) + 8031110: 10bfffcc andi r2,r2,65535 + 8031114: e0bff115 stw r2,-60(fp) + /* The following is needed in the cases where the size of the + * overlay structure is larger than the size of the ip header. + * This can happen if the ih_next and ih_prev pointers in the + * overlay structure are larger than 32 bit pointers. + */ + ti = (struct tcpiphdr *)(m->m_data + sizeof(struct ip) - + 8031118: e0bfe417 ldw r2,-112(fp) + 803111c: 10800317 ldw r2,12(r2) + 8031120: e0bff015 stw r2,-64(fp) + sizeof(struct ipovly)); + if ((char *)ti < m->pkt->nb_buff) + 8031124: e0bfe417 ldw r2,-112(fp) + 8031128: 10800117 ldw r2,4(r2) + 803112c: 10800117 ldw r2,4(r2) + 8031130: e0fff017 ldw r3,-64(fp) + 8031134: 1880032e bgeu r3,r2,8031144 + { + panic("tcp_input"); + 8031138: 01020174 movhi r4,2053 + 803113c: 212a9a04 addi r4,r4,-21912 + 8031140: 80271780 call 8027178 + /* + * Check that TCP offset makes sense, + * pull out TCP options and adjust length. + */ + + off = GET_TH_OFF(ti->ti_t) << 2; + 8031144: e0bff017 ldw r2,-64(fp) + 8031148: 10800803 ldbu r2,32(r2) + 803114c: 10803fcc andi r2,r2,255 + 8031150: 1004d13a srli r2,r2,4 + 8031154: 10803fcc andi r2,r2,255 + 8031158: 100490ba slli r2,r2,2 + 803115c: e0bfef15 stw r2,-68(fp) + if (off < sizeof (struct tcphdr) || off > tlen) + 8031160: e0bfef17 ldw r2,-68(fp) + 8031164: 10800530 cmpltui r2,r2,20 + 8031168: 1000031e bne r2,zero,8031178 + 803116c: e0bfef17 ldw r2,-68(fp) + 8031170: e0fff117 ldw r3,-60(fp) + 8031174: 18800d0e bge r3,r2,80311ac + { +#ifdef DO_TCPTRACE + tcp_trace("tcp off: src %x off %d\n", ti->ti_src, off); +#endif + tcpstat.tcps_rcvbadoff++; + 8031178: 008201b4 movhi r2,2054 + 803117c: 10b8c117 ldw r2,-7420(r2) + 8031180: 10c00044 addi r3,r2,1 + 8031184: 008201b4 movhi r2,2054 + 8031188: 10f8c115 stw r3,-7420(r2) + TCP_MIB_INC(tcpInErrs); /* keep MIB stats */ + 803118c: 008201b4 movhi r2,2054 + 8031190: 10b88317 ldw r2,-7668(r2) + 8031194: 10c00044 addi r3,r2,1 + 8031198: 008201b4 movhi r2,2054 + 803119c: 10f88315 stw r3,-7668(r2) + GOTO_DROP; + 80311a0: 00805784 movi r2,350 + 80311a4: d0a08715 stw r2,-32228(gp) + 80311a8: 00081406 br 80331fc + } + tlen -= (int)off; + 80311ac: e0fff117 ldw r3,-60(fp) + 80311b0: e0bfef17 ldw r2,-68(fp) + 80311b4: 1885c83a sub r2,r3,r2 + 80311b8: e0bff115 stw r2,-60(fp) + ti->ti_len = (u_short)tlen; + 80311bc: e0bff117 ldw r2,-60(fp) + 80311c0: 1007883a mov r3,r2 + 80311c4: e0bff017 ldw r2,-64(fp) + 80311c8: 10c0028d sth r3,10(r2) + if (off > sizeof (struct tcphdr)) + 80311cc: e0bfef17 ldw r2,-68(fp) + 80311d0: 10800570 cmpltui r2,r2,21 + 80311d4: 1000331e bne r2,zero,80312a4 + { + int olen; /* length of options field */ + u_char * op; /* scratch option pointer */ + + olen = off - sizeof (struct tcphdr); /* get options length */ + 80311d8: e0bfef17 ldw r2,-68(fp) + 80311dc: 10bffb04 addi r2,r2,-20 + 80311e0: e0bfee15 stw r2,-72(fp) + om = m_getwithdata (MT_RXDATA, olen); /* get mbuf for opts */ + 80311e4: e17fee17 ldw r5,-72(fp) + 80311e8: 01000044 movi r4,1 + 80311ec: 8029a700 call 8029a70 + 80311f0: e0bffd15 stw r2,-12(fp) + if (om == 0) + 80311f4: e0bffd17 ldw r2,-12(fp) + 80311f8: 1000031e bne r2,zero,8031208 + GOTO_DROP; + 80311fc: 00805a84 movi r2,362 + 8031200: d0a08715 stw r2,-32228(gp) + 8031204: 0007fd06 br 80331fc + om->m_len = olen; /* set mbuf length */ + 8031208: e0ffee17 ldw r3,-72(fp) + 803120c: e0bffd17 ldw r2,-12(fp) + 8031210: 10c00215 stw r3,8(r2) + /* set pointer to options field at end of TCP header */ + if(m->pkt->type == htons(0x86DD)) /* IPv6 packet */ + 8031214: e0bfe417 ldw r2,-112(fp) + 8031218: 10800117 ldw r2,4(r2) + 803121c: 1080080b ldhu r2,32(r2) + 8031220: 10ffffcc andi r3,r2,65535 + 8031224: 00b76194 movui r2,56710 + 8031228: 1880051e bne r3,r2,8031240 + op = (u_char*)(m->m_data + 20); /* past TCP header */ + 803122c: e0bfe417 ldw r2,-112(fp) + 8031230: 10800317 ldw r2,12(r2) + 8031234: 10800504 addi r2,r2,20 + 8031238: e0bff415 stw r2,-48(fp) + 803123c: 00000406 br 8031250 + else + op = (u_char*)(m->m_data + 40); /* past IP + TCP */ + 8031240: e0bfe417 ldw r2,-112(fp) + 8031244: 10800317 ldw r2,12(r2) + 8031248: 10800a04 addi r2,r2,40 + 803124c: e0bff415 stw r2,-48(fp) + MEMCPY(om->m_data, op, olen); /* copy to new mbuf */ + 8031250: e0bffd17 ldw r2,-12(fp) + 8031254: 10800317 ldw r2,12(r2) + 8031258: e0ffee17 ldw r3,-72(fp) + 803125c: 180d883a mov r6,r3 + 8031260: e17ff417 ldw r5,-48(fp) + 8031264: 1009883a mov r4,r2 + 8031268: 80086b80 call 80086b8 + + /* strip options from data mbuf. This actually just cuts the first + * m_len bytes from the TCP header, but it leaves the mbuf members + * set so the adjustment below does the right thing. + */ + m->m_data += om->m_len; + 803126c: e0bfe417 ldw r2,-112(fp) + 8031270: 10c00317 ldw r3,12(r2) + 8031274: e0bffd17 ldw r2,-12(fp) + 8031278: 10800217 ldw r2,8(r2) + 803127c: 1887883a add r3,r3,r2 + 8031280: e0bfe417 ldw r2,-112(fp) + 8031284: 10c00315 stw r3,12(r2) + m->m_len -= om->m_len; + 8031288: e0bfe417 ldw r2,-112(fp) + 803128c: 10c00217 ldw r3,8(r2) + 8031290: e0bffd17 ldw r2,-12(fp) + 8031294: 10800217 ldw r2,8(r2) + 8031298: 1887c83a sub r3,r3,r2 + 803129c: e0bfe417 ldw r2,-112(fp) + 80312a0: 10c00215 stw r3,8(r2) + } + tiflags = ti->ti_flags; + 80312a4: e0bff017 ldw r2,-64(fp) + 80312a8: 10800843 ldbu r2,33(r2) + 80312ac: 10803fcc andi r2,r2,255 + 80312b0: e0bffb15 stw r2,-20(fp) + +#if (BYTE_ORDER == LITTLE_ENDIAN) + /* Convert TCP protocol specific fields to host format. */ + ti->ti_seq = ntohl(ti->ti_seq); + 80312b4: e0bff017 ldw r2,-64(fp) + 80312b8: 10800617 ldw r2,24(r2) + 80312bc: 1006d63a srli r3,r2,24 + 80312c0: e0bff017 ldw r2,-64(fp) + 80312c4: 10800617 ldw r2,24(r2) + 80312c8: 1004d23a srli r2,r2,8 + 80312cc: 10bfc00c andi r2,r2,65280 + 80312d0: 1886b03a or r3,r3,r2 + 80312d4: e0bff017 ldw r2,-64(fp) + 80312d8: 10800617 ldw r2,24(r2) + 80312dc: 1004923a slli r2,r2,8 + 80312e0: 10803fec andhi r2,r2,255 + 80312e4: 1886b03a or r3,r3,r2 + 80312e8: e0bff017 ldw r2,-64(fp) + 80312ec: 10800617 ldw r2,24(r2) + 80312f0: 1004963a slli r2,r2,24 + 80312f4: 1886b03a or r3,r3,r2 + 80312f8: e0bff017 ldw r2,-64(fp) + 80312fc: 10c00615 stw r3,24(r2) + ti->ti_ack = ntohl(ti->ti_ack); + 8031300: e0bff017 ldw r2,-64(fp) + 8031304: 10800717 ldw r2,28(r2) + 8031308: 1006d63a srli r3,r2,24 + 803130c: e0bff017 ldw r2,-64(fp) + 8031310: 10800717 ldw r2,28(r2) + 8031314: 1004d23a srli r2,r2,8 + 8031318: 10bfc00c andi r2,r2,65280 + 803131c: 1886b03a or r3,r3,r2 + 8031320: e0bff017 ldw r2,-64(fp) + 8031324: 10800717 ldw r2,28(r2) + 8031328: 1004923a slli r2,r2,8 + 803132c: 10803fec andhi r2,r2,255 + 8031330: 1886b03a or r3,r3,r2 + 8031334: e0bff017 ldw r2,-64(fp) + 8031338: 10800717 ldw r2,28(r2) + 803133c: 1004963a slli r2,r2,24 + 8031340: 1886b03a or r3,r3,r2 + 8031344: e0bff017 ldw r2,-64(fp) + 8031348: 10c00715 stw r3,28(r2) + ti->ti_urp = ntohs(ti->ti_urp); + 803134c: e0bff017 ldw r2,-64(fp) + 8031350: 1080098b ldhu r2,38(r2) + 8031354: 10bfffcc andi r2,r2,65535 + 8031358: 1004d23a srli r2,r2,8 + 803135c: 1007883a mov r3,r2 + 8031360: e0bff017 ldw r2,-64(fp) + 8031364: 1080098b ldhu r2,38(r2) + 8031368: 10bfffcc andi r2,r2,65535 + 803136c: 1004923a slli r2,r2,8 + 8031370: 1884b03a or r2,r3,r2 + 8031374: 1007883a mov r3,r2 + 8031378: e0bff017 ldw r2,-64(fp) + 803137c: 10c0098d sth r3,38(r2) + /* + * Locate pcb for segment. + */ +findpcb: + + switch(m->pkt->type) + 8031380: e0bfe417 ldw r2,-112(fp) + 8031384: 10800117 ldw r2,4(r2) + 8031388: 1080080b ldhu r2,32(r2) + 803138c: 10bfffcc andi r2,r2,65535 + 8031390: 10800218 cmpnei r2,r2,8 + 8031394: 1000221e bne r2,zero,8031420 + { +#ifdef IP_V4 + case IPTP: /* IPv4 packet */ + /* Drop TCP and IP headers; TCP options were dropped above. */ + m->m_data += 40; + 8031398: e0bfe417 ldw r2,-112(fp) + 803139c: 10800317 ldw r2,12(r2) + 80313a0: 10c00a04 addi r3,r2,40 + 80313a4: e0bfe417 ldw r2,-112(fp) + 80313a8: 10c00315 stw r3,12(r2) + m->m_len -= 40; + 80313ac: e0bfe417 ldw r2,-112(fp) + 80313b0: 10800217 ldw r2,8(r2) + 80313b4: 10fff604 addi r3,r2,-40 + 80313b8: e0bfe417 ldw r2,-112(fp) + 80313bc: 10c00215 stw r3,8(r2) + + inp = in_pcblookup(&tcb, ti->ti_src.s_addr, ti->ti_sport, + 80313c0: e0bff017 ldw r2,-64(fp) + 80313c4: 11000317 ldw r4,12(r2) + 80313c8: e0bff017 ldw r2,-64(fp) + 80313cc: 1080050b ldhu r2,20(r2) + 80313d0: 117fffcc andi r5,r2,65535 + 80313d4: e0bff017 ldw r2,-64(fp) + 80313d8: 11800417 ldw r6,16(r2) + ti->ti_dst.s_addr, ti->ti_dport, INPLOOKUP_WILDCARD); + 80313dc: e0bff017 ldw r2,-64(fp) + 80313e0: 1080058b ldhu r2,22(r2) + inp = in_pcblookup(&tcb, ti->ti_src.s_addr, ti->ti_sport, + 80313e4: 10bfffcc andi r2,r2,65535 + 80313e8: 00c00044 movi r3,1 + 80313ec: d8c00115 stw r3,4(sp) + 80313f0: d8800015 stw r2,0(sp) + 80313f4: 300f883a mov r7,r6 + 80313f8: 280d883a mov r6,r5 + 80313fc: 200b883a mov r5,r4 + 8031400: 010201b4 movhi r4,2054 + 8031404: 21389904 addi r4,r4,-7580 + 8031408: 8040b600 call 8040b60 + 803140c: e0bffe15 stw r2,-8(fp) + break; + 8031410: 0001883a nop + * If the state is CLOSED (i.e., TCB does not exist) then + * all data in the incoming segment is discarded. + * If the TCB exists but is in CLOSED state, it is embryonic, + * but should either do a listen or a connect soon. + */ + if (inp == 0) + 8031414: e0bffe17 ldw r2,-8(fp) + 8031418: 1000061e bne r2,zero,8031434 + 803141c: 00000206 br 8031428 + dtrap(); + 8031420: 8028cd40 call 8028cd4 + return; + 8031424: 00078a06 br 8033250 + GOTO_DROPWITHRESET; + 8031428: 00806b04 movi r2,428 + 803142c: d0a08715 stw r2,-32228(gp) + 8031430: 00073306 br 8033100 + tp = intotcpcb (inp); + 8031434: e0bffe17 ldw r2,-8(fp) + 8031438: 10800917 ldw r2,36(r2) + 803143c: e0bffc15 stw r2,-16(fp) + if (tp == 0) + 8031440: e0bffc17 ldw r2,-16(fp) + 8031444: 1000031e bne r2,zero,8031454 + GOTO_DROPWITHRESET; + 8031448: 00806bc4 movi r2,431 + 803144c: d0a08715 stw r2,-32228(gp) + 8031450: 00072b06 br 8033100 + if (tp->t_state == TCPS_CLOSED) + 8031454: e0bffc17 ldw r2,-16(fp) + 8031458: 10800217 ldw r2,8(r2) + 803145c: 1000031e bne r2,zero,803146c + GOTO_DROP; + 8031460: 00806c44 movi r2,433 + 8031464: d0a08715 stw r2,-32228(gp) + 8031468: 00076406 br 80331fc + so = inp->inp_socket; + 803146c: e0bffe17 ldw r2,-8(fp) + 8031470: 10800817 ldw r2,32(r2) + 8031474: e0bffa15 stw r2,-24(fp) + tcp_saveti = *ti; + } +#endif + + /* figure out the size of the other guy's receive window */ + rx_win = (tcp_win)(ntohs(ti->ti_win)); /* convert endian */ + 8031478: e0bff017 ldw r2,-64(fp) + 803147c: 1080088b ldhu r2,34(r2) + 8031480: 10bfffcc andi r2,r2,65535 + 8031484: 1004d23a srli r2,r2,8 + 8031488: 10bfffcc andi r2,r2,65535 + 803148c: 10c03fcc andi r3,r2,255 + 8031490: e0bff017 ldw r2,-64(fp) + 8031494: 1080088b ldhu r2,34(r2) + 8031498: 10bfffcc andi r2,r2,65535 + 803149c: 1004923a slli r2,r2,8 + 80314a0: 10bfffcc andi r2,r2,65535 + 80314a4: 1884b03a or r2,r3,r2 + 80314a8: e0bfed15 stw r2,-76(fp) + { + rx_win <<= tp->snd_wind_scale; /* apply scale */ + } +#endif /* TCP_WIN_SCALE */ + + if (so->so_options & SO_ACCEPTCONN) + 80314ac: e0bffa17 ldw r2,-24(fp) + 80314b0: 10800417 ldw r2,16(r2) + 80314b4: 1080008c andi r2,r2,2 + 80314b8: 10002c26 beq r2,zero,803156c + { + so = sonewconn(so); + 80314bc: e13ffa17 ldw r4,-24(fp) + 80314c0: 802f4480 call 802f448 + 80314c4: e0bffa15 stw r2,-24(fp) + if (so == 0) + 80314c8: e0bffa17 ldw r2,-24(fp) + 80314cc: 1000031e bne r2,zero,80314dc + GOTO_DROP; + 80314d0: 00807344 movi r2,461 + 80314d4: d0a08715 stw r2,-32228(gp) + 80314d8: 00074806 br 80331fc + * flag dropsocket to see if the temporary + * socket created here should be discarded. + * We mark the socket as discardable until + * we're committed to it below in TCPS_LISTEN. + */ + dropsocket++; + 80314dc: e0bff617 ldw r2,-40(fp) + 80314e0: 10800044 addi r2,r2,1 + 80314e4: e0bff615 stw r2,-40(fp) + + inp = (struct inpcb *)so->so_pcb; + 80314e8: e0bffa17 ldw r2,-24(fp) + 80314ec: 10800117 ldw r2,4(r2) + 80314f0: e0bffe15 stw r2,-8(fp) + inp->ifp = ifp; /* save iface to peer */ + 80314f4: e0bffe17 ldw r2,-8(fp) + 80314f8: e0ffe317 ldw r3,-116(fp) + 80314fc: 10c00a15 stw r3,40(r2) + + switch(so->so_domain) + 8031500: e0bffa17 ldw r2,-24(fp) + 8031504: 10800517 ldw r2,20(r2) + 8031508: 10800098 cmpnei r2,r2,2 + 803150c: 10000d1e bne r2,zero,8031544 + { +#ifdef IP_V4 + case AF_INET: + inp->inp_laddr = ti->ti_dst; + 8031510: e0bffe17 ldw r2,-8(fp) + 8031514: e0fff017 ldw r3,-64(fp) + 8031518: 18c00417 ldw r3,16(r3) + 803151c: 10c00415 stw r3,16(r2) +#ifdef IP_PMTU + inp->inp_pmtu = pmtucache_get(inp->inp_faddr.s_addr); +#else /* not compiled for pathmtu, guess based on iface */ + inp->inp_pmtu = ifp->n_mtu - (ifp->n_lnh + 40); + 8031520: e0bfe317 ldw r2,-116(fp) + 8031524: 10c00917 ldw r3,36(r2) + 8031528: e0bfe317 ldw r2,-116(fp) + 803152c: 10800817 ldw r2,32(r2) + 8031530: 10800a04 addi r2,r2,40 + 8031534: 1887c83a sub r3,r3,r2 + 8031538: e0bffe17 ldw r2,-8(fp) + 803153c: 10c00615 stw r3,24(r2) +#endif /* IP_PMTU */ + break; + 8031540: 0001883a nop + inp->inp_pmtu = ip6_pmtulookup(&ip6_src, ifp); + break; +#endif /* end v6 */ + } + + inp->inp_lport = ti->ti_dport; + 8031544: e0bff017 ldw r2,-64(fp) + 8031548: 10c0058b ldhu r3,22(r2) + 803154c: e0bffe17 ldw r2,-8(fp) + 8031550: 10c0078d sth r3,30(r2) + tp = intotcpcb(inp); + 8031554: e0bffe17 ldw r2,-8(fp) + 8031558: 10800917 ldw r2,36(r2) + 803155c: e0bffc15 stw r2,-16(fp) + tp->t_state = TCPS_LISTEN; + 8031560: e0bffc17 ldw r2,-16(fp) + 8031564: 00c00044 movi r3,1 + 8031568: 10c00215 stw r3,8(r2) + + /* + * Segment received on connection. + * Reset idle time and keep-alive timer. + */ + tp->t_idle = 0; + 803156c: e0bffc17 ldw r2,-16(fp) + 8031570: 10001d15 stw zero,116(r2) + tp->t_timer[TCPT_KEEP] = tcp_keepidle; + 8031574: d0e01e17 ldw r3,-32648(gp) + 8031578: e0bffc17 ldw r2,-16(fp) + 803157c: 10c00515 stw r3,20(r2) + + /* + * Process options if not in LISTEN state, + * else do it below (after getting remote address). + */ + if (om && tp->t_state != TCPS_LISTEN) + 8031580: e0bffd17 ldw r2,-12(fp) + 8031584: 10000926 beq r2,zero,80315ac + 8031588: e0bffc17 ldw r2,-16(fp) + 803158c: 10800217 ldw r2,8(r2) + 8031590: 10800060 cmpeqi r2,r2,1 + 8031594: 1000051e bne r2,zero,80315ac + { + tcp_dooptions(tp, om, ti); + 8031598: e1bff017 ldw r6,-64(fp) + 803159c: e17ffd17 ldw r5,-12(fp) + 80315a0: e13ffc17 ldw r4,-16(fp) + 80315a4: 80332640 call 8033264 + om = 0; + 80315a8: e03ffd15 stw zero,-12(fp) + } + + acked = (int)(ti->ti_ack - tp->snd_una); + 80315ac: e0bff017 ldw r2,-64(fp) + 80315b0: 10c00717 ldw r3,28(r2) + 80315b4: e0bffc17 ldw r2,-16(fp) + 80315b8: 10800e17 ldw r2,56(r2) + 80315bc: 1885c83a sub r2,r3,r2 + 80315c0: e0bfec15 stw r2,-80(fp) + * Receive window is amount of space in rcv queue, + * but not less than advertised window. + */ + { long win; + + win = (long)sbspace(&so->so_rcv); + 80315c4: e0bffa17 ldw r2,-24(fp) + 80315c8: 10800b17 ldw r2,44(r2) + 80315cc: 1007883a mov r3,r2 + 80315d0: e0bffa17 ldw r2,-24(fp) + 80315d4: 10800a17 ldw r2,40(r2) + 80315d8: 1885c83a sub r2,r3,r2 + 80315dc: 10000616 blt r2,zero,80315f8 + 80315e0: e0bffa17 ldw r2,-24(fp) + 80315e4: 10c00b17 ldw r3,44(r2) + 80315e8: e0bffa17 ldw r2,-24(fp) + 80315ec: 10800a17 ldw r2,40(r2) + 80315f0: 1885c83a sub r2,r3,r2 + 80315f4: 00000106 br 80315fc + 80315f8: 0005883a mov r2,zero + 80315fc: e0bff315 stw r2,-52(fp) + if (win < 0) + 8031600: e0bff317 ldw r2,-52(fp) + 8031604: 1000010e bge r2,zero,803160c + win = 0; + 8031608: e03ff315 stw zero,-52(fp) + tp->rcv_wnd = (tcp_win)MAX((u_long)win, (tp->rcv_adv - tp->rcv_nxt)); + 803160c: e0bffc17 ldw r2,-16(fp) + 8031610: 10c01917 ldw r3,100(r2) + 8031614: e0bffc17 ldw r2,-16(fp) + 8031618: 10801617 ldw r2,88(r2) + 803161c: 1885c83a sub r2,r3,r2 + 8031620: e0fff317 ldw r3,-52(fp) + 8031624: 10c0012e bgeu r2,r3,803162c + 8031628: 1805883a mov r2,r3 + 803162c: e0fffc17 ldw r3,-16(fp) + 8031630: 18801515 stw r2,84(r3) + * is non-zero and the ack didn't move, we're the + * receiver side. If we're getting packets in-order + * (the reassembly queue is empty), add the data to + * the socket buffer and note that we need a delayed ack. + */ + if ((tp->t_state == TCPS_ESTABLISHED) && + 8031634: e0bffc17 ldw r2,-16(fp) + 8031638: 10800217 ldw r2,8(r2) + 803163c: 10800118 cmpnei r2,r2,4 + 8031640: 1000f41e bne r2,zero,8031a14 + ((tiflags & (TH_SYN|TH_FIN|TH_RST|TH_URG|TH_ACK)) == TH_ACK) && + 8031644: e0bffb17 ldw r2,-20(fp) + 8031648: 10800dcc andi r2,r2,55 + if ((tp->t_state == TCPS_ESTABLISHED) && + 803164c: 10800418 cmpnei r2,r2,16 + 8031650: 1000f01e bne r2,zero,8031a14 + (ti->ti_seq == tp->rcv_nxt) && + 8031654: e0bff017 ldw r2,-64(fp) + 8031658: 10c00617 ldw r3,24(r2) + 803165c: e0bffc17 ldw r2,-16(fp) + 8031660: 10801617 ldw r2,88(r2) + ((tiflags & (TH_SYN|TH_FIN|TH_RST|TH_URG|TH_ACK)) == TH_ACK) && + 8031664: 1880eb1e bne r3,r2,8031a14 + (ti->ti_seq == tp->rcv_nxt) && + 8031668: e0bfed17 ldw r2,-76(fp) + 803166c: 1000e926 beq r2,zero,8031a14 + (rx_win && rx_win == tp->snd_wnd) && + 8031670: e0bffc17 ldw r2,-16(fp) + 8031674: 10801417 ldw r2,80(r2) + 8031678: e0ffed17 ldw r3,-76(fp) + 803167c: 1880e51e bne r3,r2,8031a14 + (tp->snd_nxt == tp->snd_max)) + 8031680: e0bffc17 ldw r2,-16(fp) + 8031684: 10c00f17 ldw r3,60(r2) + 8031688: e0bffc17 ldw r2,-16(fp) + 803168c: 10801a17 ldw r2,104(r2) + (rx_win && rx_win == tp->snd_wnd) && + 8031690: 1880e01e bne r3,r2,8031a14 + { + if (ti->ti_len == 0) + 8031694: e0bff017 ldw r2,-64(fp) + 8031698: 1080028b ldhu r2,10(r2) + 803169c: 10bfffcc andi r2,r2,65535 + 80316a0: 10005b1e bne r2,zero,8031810 + { + if (SEQ_GT(ti->ti_ack, tp->snd_una) && + 80316a4: e0bff017 ldw r2,-64(fp) + 80316a8: 10c00717 ldw r3,28(r2) + 80316ac: e0bffc17 ldw r2,-16(fp) + 80316b0: 10800e17 ldw r2,56(r2) + 80316b4: 1885c83a sub r2,r3,r2 + 80316b8: 0080d60e bge zero,r2,8031a14 + SEQ_LEQ(ti->ti_ack, tp->snd_max) && + 80316bc: e0bff017 ldw r2,-64(fp) + 80316c0: 10c00717 ldw r3,28(r2) + 80316c4: e0bffc17 ldw r2,-16(fp) + 80316c8: 10801a17 ldw r2,104(r2) + 80316cc: 1885c83a sub r2,r3,r2 + if (SEQ_GT(ti->ti_ack, tp->snd_una) && + 80316d0: 0080d016 blt zero,r2,8031a14 + tp->snd_cwnd >= tp->snd_wnd) + 80316d4: e0bffc17 ldw r2,-16(fp) + 80316d8: 10c01b17 ldw r3,108(r2) + 80316dc: e0bffc17 ldw r2,-16(fp) + 80316e0: 10801417 ldw r2,80(r2) + SEQ_LEQ(ti->ti_ack, tp->snd_max) && + 80316e4: 1880cb36 bltu r3,r2,8031a14 + { + /* + * this is a pure ack for outstanding data. + */ + ++tcpstat.tcps_predack; + 80316e8: 008201b4 movhi r2,2054 + 80316ec: 10b8d917 ldw r2,-7324(r2) + 80316f0: 10c00044 addi r3,r2,1 + 80316f4: 008201b4 movhi r2,2054 + 80316f8: 10f8d915 stw r3,-7324(r2) + if (tp->t_rttick && + 80316fc: e0bffc17 ldw r2,-16(fp) + 8031700: 10801e17 ldw r2,120(r2) + 8031704: 10000826 beq r2,zero,8031728 +#ifdef TCP_TIMESTAMP + ((tp->t_flags & TF_TIMESTAMP) == 0) && +#endif /* TCP_TIMESTAMP */ + (SEQ_GT(ti->ti_ack, tp->t_rtseq))) + 8031708: e0bff017 ldw r2,-64(fp) + 803170c: 10c00717 ldw r3,28(r2) + 8031710: e0bffc17 ldw r2,-16(fp) + 8031714: 10801f17 ldw r2,124(r2) + 8031718: 1885c83a sub r2,r3,r2 + if (tp->t_rttick && + 803171c: 0080020e bge zero,r2,8031728 + { + tcp_xmit_timer(tp); + 8031720: e13ffc17 ldw r4,-16(fp) + 8031724: 80335180 call 8033518 + } + + tcpstat.tcps_rcvackpack++; + 8031728: 008201b4 movhi r2,2054 + 803172c: 10b8cf17 ldw r2,-7364(r2) + 8031730: 10c00044 addi r3,r2,1 + 8031734: 008201b4 movhi r2,2054 + 8031738: 10f8cf15 stw r3,-7364(r2) + tcpstat.tcps_rcvackbyte += acked; + 803173c: 008201b4 movhi r2,2054 + 8031740: 10f8d017 ldw r3,-7360(r2) + 8031744: e0bfec17 ldw r2,-80(fp) + 8031748: 1887883a add r3,r3,r2 + 803174c: 008201b4 movhi r2,2054 + 8031750: 10f8d015 stw r3,-7360(r2) + sbdrop(&so->so_snd, acked); + 8031754: e0bffa17 ldw r2,-24(fp) + 8031758: 10801204 addi r2,r2,72 + 803175c: e17fec17 ldw r5,-80(fp) + 8031760: 1009883a mov r4,r2 + 8031764: 80300b00 call 80300b0 + tp->snd_una = ti->ti_ack; + 8031768: e0bff017 ldw r2,-64(fp) + 803176c: 10c00717 ldw r3,28(r2) + 8031770: e0bffc17 ldw r2,-16(fp) + 8031774: 10c00e15 stw r3,56(r2) + m_freem(m); + 8031778: e13fe417 ldw r4,-112(fp) + 803177c: 8029cfc0 call 8029cfc + * If process is waiting for space, + * wakeup/selwakeup/signal. If data + * are ready to send, let tcp_output + * decide between more output or persist. + */ + if (tp->snd_una == tp->snd_max) + 8031780: e0bffc17 ldw r2,-16(fp) + 8031784: 10c00e17 ldw r3,56(r2) + 8031788: e0bffc17 ldw r2,-16(fp) + 803178c: 10801a17 ldw r2,104(r2) + 8031790: 1880031e bne r3,r2,80317a0 + tp->t_timer[TCPT_REXMT] = 0; + 8031794: e0bffc17 ldw r2,-16(fp) + 8031798: 10000315 stw zero,12(r2) + 803179c: 00000706 br 80317bc + else if (tp->t_timer[TCPT_PERSIST] == 0) + 80317a0: e0bffc17 ldw r2,-16(fp) + 80317a4: 10800417 ldw r2,16(r2) + 80317a8: 1000041e bne r2,zero,80317bc + tp->t_timer[TCPT_REXMT] = tp->t_rxtcur; + 80317ac: e0bffc17 ldw r2,-16(fp) + 80317b0: 10c00817 ldw r3,32(r2) + 80317b4: e0bffc17 ldw r2,-16(fp) + 80317b8: 10c00315 stw r3,12(r2) + + if (so->so_snd.sb_flags & (SB_WAIT | SB_SEL)) + 80317bc: e0bffa17 ldw r2,-24(fp) + 80317c0: 1080190b ldhu r2,100(r2) + 80317c4: 10bfffcc andi r2,r2,65535 + 80317c8: 1080030c andi r2,r2,12 + 80317cc: 10000526 beq r2,zero,80317e4 + sowwakeup(so); + 80317d0: e0bffa17 ldw r2,-24(fp) + 80317d4: 10801204 addi r2,r2,72 + 80317d8: 100b883a mov r5,r2 + 80317dc: e13ffa17 ldw r4,-24(fp) + 80317e0: 802f94c0 call 802f94c + + /* If there is more data in the send buffer, and some is + * still unsent, then call tcp_output() to try to send it + */ + if (so->so_snd.sb_cc > (tp->snd_nxt - tp->snd_una)) + 80317e4: e0bffa17 ldw r2,-24(fp) + 80317e8: 10801217 ldw r2,72(r2) + 80317ec: e0fffc17 ldw r3,-16(fp) + 80317f0: 19000f17 ldw r4,60(r3) + 80317f4: e0fffc17 ldw r3,-16(fp) + 80317f8: 18c00e17 ldw r3,56(r3) + 80317fc: 20c7c83a sub r3,r4,r3 + 8031800: 18868a2e bgeu r3,r2,803322c + (void) tcp_output(tp); + 8031804: e13ffc17 ldw r4,-16(fp) + 8031808: 80338940 call 8033894 + return; + 803180c: 00068706 br 803322c + } + } + else if (ti->ti_ack == tp->snd_una && + 8031810: e0bff017 ldw r2,-64(fp) + 8031814: 10c00717 ldw r3,28(r2) + 8031818: e0bffc17 ldw r2,-16(fp) + 803181c: 10800e17 ldw r2,56(r2) + 8031820: 18807c1e bne r3,r2,8031a14 + tp->seg_next == (struct tcpiphdr *)tp && + 8031824: e0bffc17 ldw r2,-16(fp) + 8031828: 10800017 ldw r2,0(r2) + else if (ti->ti_ack == tp->snd_una && + 803182c: e0fffc17 ldw r3,-16(fp) + 8031830: 1880781e bne r3,r2,8031a14 + ti->ti_len <= sbspace(&so->so_rcv)) + 8031834: e0bff017 ldw r2,-64(fp) + 8031838: 1080028b ldhu r2,10(r2) + 803183c: 10ffffcc andi r3,r2,65535 + 8031840: e0bffa17 ldw r2,-24(fp) + 8031844: 10800b17 ldw r2,44(r2) + 8031848: 1009883a mov r4,r2 + 803184c: e0bffa17 ldw r2,-24(fp) + 8031850: 10800a17 ldw r2,40(r2) + 8031854: 2085c83a sub r2,r4,r2 + 8031858: 10000616 blt r2,zero,8031874 + 803185c: e0bffa17 ldw r2,-24(fp) + 8031860: 11000b17 ldw r4,44(r2) + 8031864: e0bffa17 ldw r2,-24(fp) + 8031868: 10800a17 ldw r2,40(r2) + 803186c: 2085c83a sub r2,r4,r2 + 8031870: 00000106 br 8031878 + 8031874: 0005883a mov r2,zero + tp->seg_next == (struct tcpiphdr *)tp && + 8031878: 10c06636 bltu r2,r3,8031a14 +#endif /* TCP_ZEROCOPY */ + + /* this may also be a garden-variety probe received because + * the socket sendbuf was full. + */ + if(tp->rcv_wnd == 0) + 803187c: e0bffc17 ldw r2,-16(fp) + 8031880: 10801517 ldw r2,84(r2) + 8031884: 10000a1e bne r2,zero,80318b0 + * info in this seg, but Windows NT 4.0 has a nasty bug where it + * will hammer us mericilessly with these probes (one customer + * reports thousands per second) so we just dump it ASAP to + * save cycles. + */ + tcpstat.tcps_rcvwinprobe++; + 8031888: 008201b4 movhi r2,2054 + 803188c: 10b8cc17 ldw r2,-7376(r2) + 8031890: 10c00044 addi r3,r2,1 + 8031894: 008201b4 movhi r2,2054 + 8031898: 10f8cc15 stw r3,-7376(r2) + m_freem (m); /* free the received mbuf */ + 803189c: e13fe417 ldw r4,-112(fp) + 80318a0: 8029cfc0 call 8029cfc + tcp_output(tp); /* send the ack now... */ + 80318a4: e13ffc17 ldw r4,-16(fp) + 80318a8: 80338940 call 8033894 + return; + 80318ac: 00066806 br 8033250 + /* + * this is a pure, in-sequence data packet + * with nothing on the reassembly queue and + * we have enough buffer space to take it. + */ + ++tcpstat.tcps_preddat; + 80318b0: 008201b4 movhi r2,2054 + 80318b4: 10b8da17 ldw r2,-7320(r2) + 80318b8: 10c00044 addi r3,r2,1 + 80318bc: 008201b4 movhi r2,2054 + 80318c0: 10f8da15 stw r3,-7320(r2) + tp->rcv_nxt += ti->ti_len; + 80318c4: e0bffc17 ldw r2,-16(fp) + 80318c8: 10c01617 ldw r3,88(r2) + 80318cc: e0bff017 ldw r2,-64(fp) + 80318d0: 1080028b ldhu r2,10(r2) + 80318d4: 10bfffcc andi r2,r2,65535 + 80318d8: 1887883a add r3,r3,r2 + 80318dc: e0bffc17 ldw r2,-16(fp) + 80318e0: 10c01615 stw r3,88(r2) + tcpstat.tcps_rcvpack++; + 80318e4: 008201b4 movhi r2,2054 + 80318e8: 10b8be17 ldw r2,-7432(r2) + 80318ec: 10c00044 addi r3,r2,1 + 80318f0: 008201b4 movhi r2,2054 + 80318f4: 10f8be15 stw r3,-7432(r2) + tcpstat.tcps_rcvbyte += ti->ti_len; + 80318f8: 008201b4 movhi r2,2054 + 80318fc: 10f8bf17 ldw r3,-7428(r2) + 8031900: e0bff017 ldw r2,-64(fp) + 8031904: 1080028b ldhu r2,10(r2) + 8031908: 10bfffcc andi r2,r2,65535 + 803190c: 1887883a add r3,r3,r2 + 8031910: 008201b4 movhi r2,2054 + 8031914: 10f8bf15 stw r3,-7428(r2) + /* + * Add data to socket buffer. + */ + sbappend(&so->so_rcv, m); + 8031918: e0bffa17 ldw r2,-24(fp) + 803191c: 10800a04 addi r2,r2,40 + 8031920: e17fe417 ldw r5,-112(fp) + 8031924: 1009883a mov r4,r2 + 8031928: 802fafc0 call 802fafc + sorwakeup(so); + 803192c: e0bffa17 ldw r2,-24(fp) + 8031930: 10800a04 addi r2,r2,40 + 8031934: 100b883a mov r5,r2 + 8031938: e13ffa17 ldw r4,-24(fp) + 803193c: 802f94c0 call 802f94c + /* + * If this is a short packet, then ACK now - with Nagel + * congestion avoidance sender won't send more until + * he gets an ACK. + */ + if (tiflags & TH_PUSH) + 8031940: e0bffb17 ldw r2,-20(fp) + 8031944: 1080020c andi r2,r2,8 + 8031948: 10000726 beq r2,zero,8031968 + tp->t_flags |= TF_ACKNOW; + 803194c: e0bffc17 ldw r2,-16(fp) + 8031950: 10800b0b ldhu r2,44(r2) + 8031954: 10800054 ori r2,r2,1 + 8031958: 1007883a mov r3,r2 + 803195c: e0bffc17 ldw r2,-16(fp) + 8031960: 10c00b0d sth r3,44(r2) + 8031964: 00000606 br 8031980 + else + tp->t_flags |= TF_DELACK; + 8031968: e0bffc17 ldw r2,-16(fp) + 803196c: 10800b0b ldhu r2,44(r2) + 8031970: 10800094 ori r2,r2,2 + 8031974: 1007883a mov r3,r2 + 8031978: e0bffc17 ldw r2,-16(fp) + 803197c: 10c00b0d sth r3,44(r2) + + /* see if we need to send an ack */ + adv = (int)(tp->rcv_wnd - (tcp_win)(tp->rcv_adv - tp->rcv_nxt)); + 8031980: e0bffc17 ldw r2,-16(fp) + 8031984: 10c01517 ldw r3,84(r2) + 8031988: e0bffc17 ldw r2,-16(fp) + 803198c: 11001617 ldw r4,88(r2) + 8031990: e0bffc17 ldw r2,-16(fp) + 8031994: 10801917 ldw r2,100(r2) + 8031998: 2085c83a sub r2,r4,r2 + 803199c: 1885883a add r2,r3,r2 + 80319a0: e0bfeb15 stw r2,-84(fp) + + if ((adv >= (int)(tp->t_maxseg * 2)) || + 80319a4: e0bffc17 ldw r2,-16(fp) + 80319a8: 10800a0b ldhu r2,40(r2) + 80319ac: 10bfffcc andi r2,r2,65535 + 80319b0: 1085883a add r2,r2,r2 + 80319b4: 1007883a mov r3,r2 + 80319b8: e0bfeb17 ldw r2,-84(fp) + 80319bc: 10c0050e bge r2,r3,80319d4 + (tp->t_flags & TF_ACKNOW)) + 80319c0: e0bffc17 ldw r2,-16(fp) + 80319c4: 10800b0b ldhu r2,44(r2) + 80319c8: 10bfffcc andi r2,r2,65535 + 80319cc: 1080004c andi r2,r2,1 + if ((adv >= (int)(tp->t_maxseg * 2)) || + 80319d0: 10061826 beq r2,zero,8033234 + tp->t_flags &= ~TF_ACKNOW; + return; + } +#endif /* DO_DELAY_ACKS */ + + tp->t_flags |= TF_ACKNOW; + 80319d4: e0bffc17 ldw r2,-16(fp) + 80319d8: 10800b0b ldhu r2,44(r2) + 80319dc: 10800054 ori r2,r2,1 + 80319e0: 1007883a mov r3,r2 + 80319e4: e0bffc17 ldw r2,-16(fp) + 80319e8: 10c00b0d sth r3,44(r2) + tp->t_flags &= ~TF_DELACK; + 80319ec: e0bffc17 ldw r2,-16(fp) + 80319f0: 10c00b0b ldhu r3,44(r2) + 80319f4: 00bfff44 movi r2,-3 + 80319f8: 1884703a and r2,r3,r2 + 80319fc: 1007883a mov r3,r2 + 8031a00: e0bffc17 ldw r2,-16(fp) + 8031a04: 10c00b0d sth r3,44(r2) + tcp_output(tp); /* send the ack now... */ + 8031a08: e13ffc17 ldw r4,-16(fp) + 8031a0c: 80338940 call 8033894 + } + + return; + 8031a10: 00060806 br 8033234 + } + } + + switch (tp->t_state) + 8031a14: e0bffc17 ldw r2,-16(fp) + 8031a18: 10800217 ldw r2,8(r2) + 8031a1c: 10c00060 cmpeqi r3,r2,1 + 8031a20: 1800031e bne r3,zero,8031a30 + 8031a24: 108000a0 cmpeqi r2,r2,2 + 8031a28: 1000a81e bne r2,zero,8031ccc + 8031a2c: 00017606 br 8032008 + */ + case TCPS_LISTEN: + { + struct mbuf * am; + + if (tiflags & TH_RST) + 8031a30: e0bffb17 ldw r2,-20(fp) + 8031a34: 1080010c andi r2,r2,4 + 8031a38: 10000326 beq r2,zero,8031a48 + GOTO_DROP; + 8031a3c: 0080bec4 movi r2,763 + 8031a40: d0a08715 stw r2,-32228(gp) + 8031a44: 0005ed06 br 80331fc + if (tiflags & TH_ACK) + 8031a48: e0bffb17 ldw r2,-20(fp) + 8031a4c: 1080040c andi r2,r2,16 + 8031a50: 10000326 beq r2,zero,8031a60 + GOTO_DROPWITHRESET; + 8031a54: 0080bf44 movi r2,765 + 8031a58: d0a08715 stw r2,-32228(gp) + 8031a5c: 0005a806 br 8033100 + if ((tiflags & TH_SYN) == 0) + 8031a60: e0bffb17 ldw r2,-20(fp) + 8031a64: 1080008c andi r2,r2,2 + 8031a68: 1000031e bne r2,zero,8031a78 + GOTO_DROP; + 8031a6c: 0080bfc4 movi r2,767 + 8031a70: d0a08715 stw r2,-32228(gp) + 8031a74: 0005e106 br 80331fc + if(in_broadcast(ti->ti_dst.s_addr)) + 8031a78: e0bff017 ldw r2,-64(fp) + 8031a7c: 10800417 ldw r2,16(r2) + 8031a80: 1009883a mov r4,r2 + 8031a84: 802abe00 call 802abe0 + 8031a88: 10000326 beq r2,zero,8031a98 + GOTO_DROP; + 8031a8c: 0080c044 movi r2,769 + 8031a90: d0a08715 stw r2,-32228(gp) + 8031a94: 0005d906 br 80331fc + am = m_getwithdata (MT_SONAME, sizeof (struct sockaddr)); + 8031a98: 01400404 movi r5,16 + 8031a9c: 01000244 movi r4,9 + 8031aa0: 8029a700 call 8029a70 + 8031aa4: e0bfea15 stw r2,-88(fp) + if (am == NULL) + 8031aa8: e0bfea17 ldw r2,-88(fp) + 8031aac: 1000031e bne r2,zero,8031abc + GOTO_DROP; + 8031ab0: 0080c104 movi r2,772 + 8031ab4: d0a08715 stw r2,-32228(gp) + 8031ab8: 0005d006 br 80331fc + +#ifdef IP_V4 + if(inp->inp_socket->so_domain == AF_INET) + 8031abc: e0bffe17 ldw r2,-8(fp) + 8031ac0: 10800817 ldw r2,32(r2) + 8031ac4: 10800517 ldw r2,20(r2) + 8031ac8: 10800098 cmpnei r2,r2,2 + 8031acc: 10002c1e bne r2,zero,8031b80 + { + struct sockaddr_in * sin; + am->m_len = sizeof (struct sockaddr_in); + 8031ad0: e0bfea17 ldw r2,-88(fp) + 8031ad4: 00c00404 movi r3,16 + 8031ad8: 10c00215 stw r3,8(r2) + sin = mtod(am, struct sockaddr_in *); + 8031adc: e0bfea17 ldw r2,-88(fp) + 8031ae0: 10800317 ldw r2,12(r2) + 8031ae4: e0bfe915 stw r2,-92(fp) + sin->sin_family = AF_INET; + 8031ae8: e0bfe917 ldw r2,-92(fp) + 8031aec: 00c00084 movi r3,2 + 8031af0: 10c0000d sth r3,0(r2) + sin->sin_addr = ti->ti_src; + 8031af4: e0bfe917 ldw r2,-92(fp) + 8031af8: e0fff017 ldw r3,-64(fp) + 8031afc: 18c00317 ldw r3,12(r3) + 8031b00: 10c00115 stw r3,4(r2) + sin->sin_port = ti->ti_sport; + 8031b04: e0bff017 ldw r2,-64(fp) + 8031b08: 10c0050b ldhu r3,20(r2) + 8031b0c: e0bfe917 ldw r2,-92(fp) + 8031b10: 10c0008d sth r3,2(r2) + /* Assuming pcbconnect will work, we put the sender's address in + * the inp_laddr (after saving a local laddr copy). If the connect + * fails we restore the inpcb before going to drop: + */ + laddr = inp->inp_laddr; /* save tmp laddr */ + 8031b14: e0bffe17 ldw r2,-8(fp) + 8031b18: 10800417 ldw r2,16(r2) + 8031b1c: e0bfe515 stw r2,-108(fp) + if (inp->inp_laddr.s_addr == INADDR_ANY) + 8031b20: e0bffe17 ldw r2,-8(fp) + 8031b24: 10800417 ldw r2,16(r2) + 8031b28: 1000041e bne r2,zero,8031b3c + inp->inp_laddr = ti->ti_dst; + 8031b2c: e0bffe17 ldw r2,-8(fp) + 8031b30: e0fff017 ldw r3,-64(fp) + 8031b34: 18c00417 ldw r3,16(r3) + 8031b38: 10c00415 stw r3,16(r2) + if (in_pcbconnect (inp, am)) + 8031b3c: e17fea17 ldw r5,-88(fp) + 8031b40: e13ffe17 ldw r4,-8(fp) + 8031b44: 804081c0 call 804081c + 8031b48: 10000826 beq r2,zero,8031b6c + { + inp->inp_laddr = laddr; + 8031b4c: e0bffe17 ldw r2,-8(fp) + 8031b50: e0ffe517 ldw r3,-108(fp) + 8031b54: 10c00415 stw r3,16(r2) + (void) m_free(am); + 8031b58: e13fea17 ldw r4,-88(fp) + 8031b5c: 8029bf80 call 8029bf8 + GOTO_DROP; + 8031b60: 0080c684 movi r2,794 + 8031b64: d0a08715 stw r2,-32228(gp) + 8031b68: 0005a406 br 80331fc + } + + inp->ifp = ifp; /* set interface for conn.*/ + 8031b6c: e0bffe17 ldw r2,-8(fp) + 8031b70: e0ffe317 ldw r3,-116(fp) + 8031b74: 10c00a15 stw r3,40(r2) + + (void) m_free (am); + 8031b78: e13fea17 ldw r4,-88(fp) + 8031b7c: 8029bf80 call 8029bf8 + } + (void) m_free(am); + } +#endif /* end v6 */ + + tp->t_template = tcp_template(tp); + 8031b80: e13ffc17 ldw r4,-16(fp) + 8031b84: 8034a400 call 8034a40 + 8031b88: 1007883a mov r3,r2 + 8031b8c: e0bffc17 ldw r2,-16(fp) + 8031b90: 10c00c15 stw r3,48(r2) + if (tp->t_template == 0) + 8031b94: e0bffc17 ldw r2,-16(fp) + 8031b98: 10800c17 ldw r2,48(r2) + 8031b9c: 1000071e bne r2,zero,8031bbc + { + SETTP(tp, tcp_drop(tp, ENOBUFS)); + 8031ba0: 01401a44 movi r5,105 + 8031ba4: e13ffc17 ldw r4,-16(fp) + 8031ba8: 803504c0 call 803504c + dropsocket = 0; /* socket is already gone */ + 8031bac: e03ff615 stw zero,-40(fp) + GOTO_DROP; + 8031bb0: 0080d1c4 movi r2,839 + 8031bb4: d0a08715 stw r2,-32228(gp) + 8031bb8: 00059006 br 80331fc + } + if (om) + 8031bbc: e0bffd17 ldw r2,-12(fp) + 8031bc0: 10000526 beq r2,zero,8031bd8 + { + tcp_dooptions(tp, om, ti); + 8031bc4: e1bff017 ldw r6,-64(fp) + 8031bc8: e17ffd17 ldw r5,-12(fp) + 8031bcc: e13ffc17 ldw r4,-16(fp) + 8031bd0: 80332640 call 8033264 + om = 0; + 8031bd4: e03ffd15 stw zero,-12(fp) + } + if (iss) + 8031bd8: e0bff517 ldw r2,-44(fp) + 8031bdc: 10000426 beq r2,zero,8031bf0 + tp->iss = iss; + 8031be0: e0fff517 ldw r3,-44(fp) + 8031be4: e0bffc17 ldw r2,-16(fp) + 8031be8: 10c01315 stw r3,76(r2) + 8031bec: 00000306 br 8031bfc + else + tp->iss = tcp_iss; + 8031bf0: d0e08a17 ldw r3,-32216(gp) + 8031bf4: e0bffc17 ldw r2,-16(fp) + 8031bf8: 10c01315 stw r3,76(r2) + tcp_iss += (unsigned)(TCP_ISSINCR/2); + 8031bfc: d0e08a17 ldw r3,-32216(gp) + 8031c00: 00be9fd4 movui r2,64127 + 8031c04: 1885883a add r2,r3,r2 + 8031c08: d0a08a15 stw r2,-32216(gp) + tp->irs = ti->ti_seq; + 8031c0c: e0bff017 ldw r2,-64(fp) + 8031c10: 10c00617 ldw r3,24(r2) + 8031c14: e0bffc17 ldw r2,-16(fp) + 8031c18: 10c01815 stw r3,96(r2) + tcp_sendseqinit(tp); + 8031c1c: e0bffc17 ldw r2,-16(fp) + 8031c20: 10c01317 ldw r3,76(r2) + 8031c24: e0bffc17 ldw r2,-16(fp) + 8031c28: 10c01015 stw r3,64(r2) + 8031c2c: e0bffc17 ldw r2,-16(fp) + 8031c30: 10c01017 ldw r3,64(r2) + 8031c34: e0bffc17 ldw r2,-16(fp) + 8031c38: 10c01a15 stw r3,104(r2) + 8031c3c: e0bffc17 ldw r2,-16(fp) + 8031c40: 10c01a17 ldw r3,104(r2) + 8031c44: e0bffc17 ldw r2,-16(fp) + 8031c48: 10c00f15 stw r3,60(r2) + 8031c4c: e0bffc17 ldw r2,-16(fp) + 8031c50: 10c00f17 ldw r3,60(r2) + 8031c54: e0bffc17 ldw r2,-16(fp) + 8031c58: 10c00e15 stw r3,56(r2) + tcp_rcvseqinit(tp); + 8031c5c: e0bffc17 ldw r2,-16(fp) + 8031c60: 10801817 ldw r2,96(r2) + 8031c64: 10c00044 addi r3,r2,1 + 8031c68: e0bffc17 ldw r2,-16(fp) + 8031c6c: 10c01615 stw r3,88(r2) + 8031c70: e0bffc17 ldw r2,-16(fp) + 8031c74: 10c01617 ldw r3,88(r2) + 8031c78: e0bffc17 ldw r2,-16(fp) + 8031c7c: 10c01915 stw r3,100(r2) + tp->t_flags |= TF_ACKNOW; + 8031c80: e0bffc17 ldw r2,-16(fp) + 8031c84: 10800b0b ldhu r2,44(r2) + 8031c88: 10800054 ori r2,r2,1 + 8031c8c: 1007883a mov r3,r2 + 8031c90: e0bffc17 ldw r2,-16(fp) + 8031c94: 10c00b0d sth r3,44(r2) + tp->t_state = TCPS_SYN_RECEIVED; + 8031c98: e0bffc17 ldw r2,-16(fp) + 8031c9c: 00c000c4 movi r3,3 + 8031ca0: 10c00215 stw r3,8(r2) + tp->t_timer[TCPT_KEEP] = TCPTV_KEEP_INIT; + 8031ca4: e0bffc17 ldw r2,-16(fp) + 8031ca8: 00c02584 movi r3,150 + 8031cac: 10c00515 stw r3,20(r2) + dropsocket = 0; /* committed to socket */ + 8031cb0: e03ff615 stw zero,-40(fp) + tcpstat.tcps_accepts++; + 8031cb4: 008201b4 movhi r2,2054 + 8031cb8: 10b8a517 ldw r2,-7532(r2) + 8031cbc: 10c00044 addi r3,r2,1 + 8031cc0: 008201b4 movhi r2,2054 + 8031cc4: 10f8a515 stw r3,-7532(r2) + goto trimthenstep6; + 8031cc8: 00008e06 br 8031f04 + * if SYN has been acked change to ESTABLISHED else SYN_RCVD state + * arrange for segment to be acked (eventually) + * continue processing rest of data/controls, beginning with URG + */ + case TCPS_SYN_SENT: + inp->ifp = ifp; + 8031ccc: e0bffe17 ldw r2,-8(fp) + 8031cd0: e0ffe317 ldw r3,-116(fp) + 8031cd4: 10c00a15 stw r3,40(r2) + if ((tiflags & TH_ACK) && + 8031cd8: e0bffb17 ldw r2,-20(fp) + 8031cdc: 1080040c andi r2,r2,16 + 8031ce0: 10000f26 beq r2,zero,8031d20 + (SEQ_LEQ(ti->ti_ack, tp->iss) || + 8031ce4: e0bff017 ldw r2,-64(fp) + 8031ce8: 10c00717 ldw r3,28(r2) + 8031cec: e0bffc17 ldw r2,-16(fp) + 8031cf0: 10801317 ldw r2,76(r2) + 8031cf4: 1885c83a sub r2,r3,r2 + if ((tiflags & TH_ACK) && + 8031cf8: 0080060e bge zero,r2,8031d14 + SEQ_GT(ti->ti_ack, tp->snd_max))) + 8031cfc: e0bff017 ldw r2,-64(fp) + 8031d00: 10c00717 ldw r3,28(r2) + 8031d04: e0bffc17 ldw r2,-16(fp) + 8031d08: 10801a17 ldw r2,104(r2) + 8031d0c: 1885c83a sub r2,r3,r2 + (SEQ_LEQ(ti->ti_ack, tp->iss) || + 8031d10: 0080030e bge zero,r2,8031d20 + { + GOTO_DROPWITHRESET; + 8031d14: 0080dc04 movi r2,880 + 8031d18: d0a08715 stw r2,-32228(gp) + 8031d1c: 0004f806 br 8033100 + } + if (tiflags & TH_RST) + 8031d20: e0bffb17 ldw r2,-20(fp) + 8031d24: 1080010c andi r2,r2,4 + 8031d28: 10000926 beq r2,zero,8031d50 + { + if (tiflags & TH_ACK) + 8031d2c: e0bffb17 ldw r2,-20(fp) + 8031d30: 1080040c andi r2,r2,16 + 8031d34: 10000326 beq r2,zero,8031d44 + SETTP(tp, tcp_drop(tp, ECONNREFUSED)); + 8031d38: 01401bc4 movi r5,111 + 8031d3c: e13ffc17 ldw r4,-16(fp) + 8031d40: 803504c0 call 803504c + GOTO_DROP; + 8031d44: 0080dd84 movi r2,886 + 8031d48: d0a08715 stw r2,-32228(gp) + 8031d4c: 00052b06 br 80331fc + } + if ((tiflags & TH_SYN) == 0) + 8031d50: e0bffb17 ldw r2,-20(fp) + 8031d54: 1080008c andi r2,r2,2 + 8031d58: 1000031e bne r2,zero,8031d68 + GOTO_DROP; + 8031d5c: 0080de44 movi r2,889 + 8031d60: d0a08715 stw r2,-32228(gp) + 8031d64: 00052506 br 80331fc + if (tiflags & TH_ACK) + 8031d68: e0bffb17 ldw r2,-20(fp) + 8031d6c: 1080040c andi r2,r2,16 + 8031d70: 10000e26 beq r2,zero,8031dac + { + tp->snd_una = ti->ti_ack; + 8031d74: e0bff017 ldw r2,-64(fp) + 8031d78: 10c00717 ldw r3,28(r2) + 8031d7c: e0bffc17 ldw r2,-16(fp) + 8031d80: 10c00e15 stw r3,56(r2) + if (SEQ_LT(tp->snd_nxt, tp->snd_una)) + 8031d84: e0bffc17 ldw r2,-16(fp) + 8031d88: 10c00f17 ldw r3,60(r2) + 8031d8c: e0bffc17 ldw r2,-16(fp) + 8031d90: 10800e17 ldw r2,56(r2) + 8031d94: 1885c83a sub r2,r3,r2 + 8031d98: 1000040e bge r2,zero,8031dac + tp->snd_nxt = tp->snd_una; + 8031d9c: e0bffc17 ldw r2,-16(fp) + 8031da0: 10c00e17 ldw r3,56(r2) + 8031da4: e0bffc17 ldw r2,-16(fp) + 8031da8: 10c00f15 stw r3,60(r2) + } + tp->t_timer[TCPT_REXMT] = 0; + 8031dac: e0bffc17 ldw r2,-16(fp) + 8031db0: 10000315 stw zero,12(r2) + tp->irs = ti->ti_seq; + 8031db4: e0bff017 ldw r2,-64(fp) + 8031db8: 10c00617 ldw r3,24(r2) + 8031dbc: e0bffc17 ldw r2,-16(fp) + 8031dc0: 10c01815 stw r3,96(r2) + tcp_rcvseqinit(tp); + 8031dc4: e0bffc17 ldw r2,-16(fp) + 8031dc8: 10801817 ldw r2,96(r2) + 8031dcc: 10c00044 addi r3,r2,1 + 8031dd0: e0bffc17 ldw r2,-16(fp) + 8031dd4: 10c01615 stw r3,88(r2) + 8031dd8: e0bffc17 ldw r2,-16(fp) + 8031ddc: 10c01617 ldw r3,88(r2) + 8031de0: e0bffc17 ldw r2,-16(fp) + 8031de4: 10c01915 stw r3,100(r2) + if (inp->inp_laddr.s_addr != ti->ti_dst.s_addr) + 8031de8: e0bffe17 ldw r2,-8(fp) + 8031dec: 10c00417 ldw r3,16(r2) + 8031df0: e0bff017 ldw r2,-64(fp) + 8031df4: 10800417 ldw r2,16(r2) + 8031df8: 18801726 beq r3,r2,8031e58 + * the IP interface may have changed address since we sent our SYN + * (e.g. PPP brings link up as a result of said SYN and gets new + * address via IPCP); if so we need to update the inpcb and the + * TCP header template with the new address. + */ + if ((m->pkt->net != NULL) + 8031dfc: e0bfe417 ldw r2,-112(fp) + 8031e00: 10800117 ldw r2,4(r2) + 8031e04: 10800617 ldw r2,24(r2) + 8031e08: 10001326 beq r2,zero,8031e58 + && (m->pkt->net->n_ipaddr == ti->ti_dst.s_addr)) + 8031e0c: e0bfe417 ldw r2,-112(fp) + 8031e10: 10800117 ldw r2,4(r2) + 8031e14: 10800617 ldw r2,24(r2) + 8031e18: 10c00a17 ldw r3,40(r2) + 8031e1c: e0bff017 ldw r2,-64(fp) + 8031e20: 10800417 ldw r2,16(r2) + 8031e24: 18800c1e bne r3,r2,8031e58 + /* send an ack */ + { + inp->inp_laddr = ti->ti_dst; + 8031e28: e0bffe17 ldw r2,-8(fp) + 8031e2c: e0fff017 ldw r3,-64(fp) + 8031e30: 18c00417 ldw r3,16(r3) + 8031e34: 10c00415 stw r3,16(r2) + if (tp->t_template != NULL) + 8031e38: e0bffc17 ldw r2,-16(fp) + 8031e3c: 10800c17 ldw r2,48(r2) + 8031e40: 10000526 beq r2,zero,8031e58 + tp->t_template->ti_src = ti->ti_dst; + 8031e44: e0bffc17 ldw r2,-16(fp) + 8031e48: 10800c17 ldw r2,48(r2) + 8031e4c: e0fff017 ldw r3,-64(fp) + 8031e50: 18c00417 ldw r3,16(r3) + 8031e54: 10c00315 stw r3,12(r2) + } + } + tp->t_flags |= TF_ACKNOW; + 8031e58: e0bffc17 ldw r2,-16(fp) + 8031e5c: 10800b0b ldhu r2,44(r2) + 8031e60: 10800054 ori r2,r2,1 + 8031e64: 1007883a mov r3,r2 + 8031e68: e0bffc17 ldw r2,-16(fp) + 8031e6c: 10c00b0d sth r3,44(r2) + if (tiflags & TH_ACK && SEQ_GT(tp->snd_una, tp->iss)) + 8031e70: e0bffb17 ldw r2,-20(fp) + 8031e74: 1080040c andi r2,r2,16 + 8031e78: 10001f26 beq r2,zero,8031ef8 + 8031e7c: e0bffc17 ldw r2,-16(fp) + 8031e80: 10c00e17 ldw r3,56(r2) + 8031e84: e0bffc17 ldw r2,-16(fp) + 8031e88: 10801317 ldw r2,76(r2) + 8031e8c: 1885c83a sub r2,r3,r2 + 8031e90: 0080190e bge zero,r2,8031ef8 + { + tcpstat.tcps_connects++; + 8031e94: 008201b4 movhi r2,2054 + 8031e98: 10b8a617 ldw r2,-7528(r2) + 8031e9c: 10c00044 addi r3,r2,1 + 8031ea0: 008201b4 movhi r2,2054 + 8031ea4: 10f8a615 stw r3,-7528(r2) + tp->t_state = TCPS_ESTABLISHED; + 8031ea8: e0bffc17 ldw r2,-16(fp) + 8031eac: 00c00104 movi r3,4 + 8031eb0: 10c00215 stw r3,8(r2) + soisconnected (so); + 8031eb4: e13ffa17 ldw r4,-24(fp) + 8031eb8: 802f1e80 call 802f1e8 + tp->t_maxseg = tcp_mss(so); + 8031ebc: e13ffa17 ldw r4,-24(fp) + 8031ec0: 803379c0 call 803379c + 8031ec4: 1007883a mov r3,r2 + 8031ec8: e0bffc17 ldw r2,-16(fp) + 8031ecc: 10c00a0d sth r3,40(r2) + (void) tcp_reass (tp, (struct tcpiphdr *)0, m); + 8031ed0: e1bfe417 ldw r6,-112(fp) + 8031ed4: 000b883a mov r5,zero + 8031ed8: e13ffc17 ldw r4,-16(fp) + 8031edc: 8030c600 call 8030c60 + /* + * if we didn't have to retransmit the SYN, + * use its rtt as our initial srtt & rtt var. + */ + if (tp->t_rttick) + 8031ee0: e0bffc17 ldw r2,-16(fp) + 8031ee4: 10801e17 ldw r2,120(r2) + 8031ee8: 10000626 beq r2,zero,8031f04 + { + tcp_xmit_timer(tp); + 8031eec: e13ffc17 ldw r4,-16(fp) + 8031ef0: 80335180 call 8033518 + if (tp->t_rttick) + 8031ef4: 00000306 br 8031f04 + } + } else + tp->t_state = TCPS_SYN_RECEIVED; + 8031ef8: e0bffc17 ldw r2,-16(fp) + 8031efc: 00c000c4 movi r3,3 + 8031f00: 10c00215 stw r3,8(r2) + /* + * Advance ti->ti_seq to correspond to first data byte. + * If data, trim to stay within window, + * dropping FIN if necessary. + */ + ti->ti_seq++; + 8031f04: e0bff017 ldw r2,-64(fp) + 8031f08: 10800617 ldw r2,24(r2) + 8031f0c: 10c00044 addi r3,r2,1 + 8031f10: e0bff017 ldw r2,-64(fp) + 8031f14: 10c00615 stw r3,24(r2) + if ((tcp_win)ti->ti_len > tp->rcv_wnd) + 8031f18: e0bff017 ldw r2,-64(fp) + 8031f1c: 1080028b ldhu r2,10(r2) + 8031f20: 10bfffcc andi r2,r2,65535 + 8031f24: e0fffc17 ldw r3,-16(fp) + 8031f28: 18c01517 ldw r3,84(r3) + 8031f2c: 18802c2e bgeu r3,r2,8031fe0 + { + todrop = ti->ti_len - (u_short)tp->rcv_wnd; + 8031f30: e0bff017 ldw r2,-64(fp) + 8031f34: 1080028b ldhu r2,10(r2) + 8031f38: 10ffffcc andi r3,r2,65535 + 8031f3c: e0bffc17 ldw r2,-16(fp) + 8031f40: 10801517 ldw r2,84(r2) + 8031f44: 10bfffcc andi r2,r2,65535 + 8031f48: 1885c83a sub r2,r3,r2 + 8031f4c: e0bff915 stw r2,-28(fp) + /* XXX work around 4.2 m_adj bug */ + if (m->m_len) + 8031f50: e0bfe417 ldw r2,-112(fp) + 8031f54: 10800217 ldw r2,8(r2) + 8031f58: 10000626 beq r2,zero,8031f74 + { + m_adj(m, -todrop); + 8031f5c: e0bff917 ldw r2,-28(fp) + 8031f60: 0085c83a sub r2,zero,r2 + 8031f64: 100b883a mov r5,r2 + 8031f68: e13fe417 ldw r4,-112(fp) + 8031f6c: 802a0180 call 802a018 + 8031f70: 00000706 br 8031f90 + } + else + { + /* skip tcp/ip header in first mbuf */ + m_adj(m->m_next, -todrop); + 8031f74: e0bfe417 ldw r2,-112(fp) + 8031f78: 10c00617 ldw r3,24(r2) + 8031f7c: e0bff917 ldw r2,-28(fp) + 8031f80: 0085c83a sub r2,zero,r2 + 8031f84: 100b883a mov r5,r2 + 8031f88: 1809883a mov r4,r3 + 8031f8c: 802a0180 call 802a018 + } + ti->ti_len = (u_short)tp->rcv_wnd; + 8031f90: e0bffc17 ldw r2,-16(fp) + 8031f94: 10801517 ldw r2,84(r2) + 8031f98: 1007883a mov r3,r2 + 8031f9c: e0bff017 ldw r2,-64(fp) + 8031fa0: 10c0028d sth r3,10(r2) + tiflags &= ~TH_FIN; + 8031fa4: e0fffb17 ldw r3,-20(fp) + 8031fa8: 00bfff84 movi r2,-2 + 8031fac: 1884703a and r2,r3,r2 + 8031fb0: e0bffb15 stw r2,-20(fp) + tcpstat.tcps_rcvpackafterwin++; + 8031fb4: 008201b4 movhi r2,2054 + 8031fb8: 10b8c917 ldw r2,-7388(r2) + 8031fbc: 10c00044 addi r3,r2,1 + 8031fc0: 008201b4 movhi r2,2054 + 8031fc4: 10f8c915 stw r3,-7388(r2) + tcpstat.tcps_rcvbyteafterwin += todrop; + 8031fc8: 008201b4 movhi r2,2054 + 8031fcc: 10f8ca17 ldw r3,-7384(r2) + 8031fd0: e0bff917 ldw r2,-28(fp) + 8031fd4: 1887883a add r3,r3,r2 + 8031fd8: 008201b4 movhi r2,2054 + 8031fdc: 10f8ca15 stw r3,-7384(r2) + } + tp->snd_wl1 = ti->ti_seq - 1; + 8031fe0: e0bff017 ldw r2,-64(fp) + 8031fe4: 10800617 ldw r2,24(r2) + 8031fe8: 10ffffc4 addi r3,r2,-1 + 8031fec: e0bffc17 ldw r2,-16(fp) + 8031ff0: 10c01115 stw r3,68(r2) + tp->rcv_up = ti->ti_seq; + 8031ff4: e0bff017 ldw r2,-64(fp) + 8031ff8: 10c00617 ldw r3,24(r2) + 8031ffc: e0bffc17 ldw r2,-16(fp) + 8032000: 10c01715 stw r3,92(r2) + goto step6; + 8032004: 0002cb06 br 8032b34 + * States other than LISTEN or SYN_SENT. + * First check that at least some bytes of segment are within + * receive window. If segment begins before rcv_nxt, + * drop leading data (and SYN); if nothing left, just ack. + */ + todrop = (int)(tp->rcv_nxt - ti->ti_seq); + 8032008: e0bffc17 ldw r2,-16(fp) + 803200c: 10c01617 ldw r3,88(r2) + 8032010: e0bff017 ldw r2,-64(fp) + 8032014: 10800617 ldw r2,24(r2) + 8032018: 1885c83a sub r2,r3,r2 + 803201c: e0bff915 stw r2,-28(fp) + if (todrop > 0) + 8032020: e0bff917 ldw r2,-28(fp) + 8032024: 0080890e bge zero,r2,803224c + { + if (tiflags & TH_SYN) + 8032028: e0bffb17 ldw r2,-20(fp) + 803202c: 1080008c andi r2,r2,2 + 8032030: 10001c26 beq r2,zero,80320a4 + { + tiflags &= ~TH_SYN; + 8032034: e0fffb17 ldw r3,-20(fp) + 8032038: 00bfff44 movi r2,-3 + 803203c: 1884703a and r2,r3,r2 + 8032040: e0bffb15 stw r2,-20(fp) + ti->ti_seq++; + 8032044: e0bff017 ldw r2,-64(fp) + 8032048: 10800617 ldw r2,24(r2) + 803204c: 10c00044 addi r3,r2,1 + 8032050: e0bff017 ldw r2,-64(fp) + 8032054: 10c00615 stw r3,24(r2) + if (ti->ti_urp > 1) + 8032058: e0bff017 ldw r2,-64(fp) + 803205c: 1080098b ldhu r2,38(r2) + 8032060: 10bfffcc andi r2,r2,65535 + 8032064: 108000b0 cmpltui r2,r2,2 + 8032068: 1000071e bne r2,zero,8032088 + ti->ti_urp--; + 803206c: e0bff017 ldw r2,-64(fp) + 8032070: 1080098b ldhu r2,38(r2) + 8032074: 10bfffc4 addi r2,r2,-1 + 8032078: 1007883a mov r3,r2 + 803207c: e0bff017 ldw r2,-64(fp) + 8032080: 10c0098d sth r3,38(r2) + 8032084: 00000406 br 8032098 + else + tiflags &= ~TH_URG; + 8032088: e0fffb17 ldw r3,-20(fp) + 803208c: 00bff7c4 movi r2,-33 + 8032090: 1884703a and r2,r3,r2 + 8032094: e0bffb15 stw r2,-20(fp) + todrop--; + 8032098: e0bff917 ldw r2,-28(fp) + 803209c: 10bfffc4 addi r2,r2,-1 + 80320a0: e0bff915 stw r2,-28(fp) + /* + * Altera Niche Stack Nios port modification: + * Add parenthesis to remove implicit order of operaton + * & possible build warning. + */ + if ((todrop > (int)ti->ti_len) || + 80320a4: e0bff017 ldw r2,-64(fp) + 80320a8: 1080028b ldhu r2,10(r2) + 80320ac: 10ffffcc andi r3,r2,65535 + 80320b0: e0bff917 ldw r2,-28(fp) + 80320b4: 18800816 blt r3,r2,80320d8 + ((todrop == (int)ti->ti_len) && + 80320b8: e0bff017 ldw r2,-64(fp) + 80320bc: 1080028b ldhu r2,10(r2) + 80320c0: 10bfffcc andi r2,r2,65535 + if ((todrop > (int)ti->ti_len) || + 80320c4: e0fff917 ldw r3,-28(fp) + 80320c8: 1880311e bne r3,r2,8032190 + (tiflags&TH_FIN) == 0)) + 80320cc: e0bffb17 ldw r2,-20(fp) + 80320d0: 1080004c andi r2,r2,1 + ((todrop == (int)ti->ti_len) && + 80320d4: 10002e1e bne r2,zero,8032190 + { + tcpstat.tcps_rcvduppack++; + 80320d8: 008201b4 movhi r2,2054 + 80320dc: 10b8c317 ldw r2,-7412(r2) + 80320e0: 10c00044 addi r3,r2,1 + 80320e4: 008201b4 movhi r2,2054 + 80320e8: 10f8c315 stw r3,-7412(r2) + tcpstat.tcps_rcvdupbyte += ti->ti_len; + 80320ec: 008201b4 movhi r2,2054 + 80320f0: 10f8c417 ldw r3,-7408(r2) + 80320f4: e0bff017 ldw r2,-64(fp) + 80320f8: 1080028b ldhu r2,10(r2) + 80320fc: 10bfffcc andi r2,r2,65535 + 8032100: 1887883a add r3,r3,r2 + 8032104: 008201b4 movhi r2,2054 + 8032108: 10f8c415 stw r3,-7408(r2) + * it, but check the ACK or we will get into FIN + * wars if our FINs crossed (both CLOSING). + * In either case, send ACK to resynchronize, + * but keep on processing for RST or ACK. + */ + if ((tiflags & TH_FIN && todrop == (int)ti->ti_len + 1) || + 803210c: e0bffb17 ldw r2,-20(fp) + 8032110: 1080004c andi r2,r2,1 + 8032114: 10000626 beq r2,zero,8032130 + 8032118: e0bff017 ldw r2,-64(fp) + 803211c: 1080028b ldhu r2,10(r2) + 8032120: 10bfffcc andi r2,r2,65535 + 8032124: 10800044 addi r2,r2,1 + 8032128: e0fff917 ldw r3,-28(fp) + 803212c: 18800926 beq r3,r2,8032154 + (tiflags & TH_RST && ti->ti_seq == tp->rcv_nxt - 1)) + 8032130: e0bffb17 ldw r2,-20(fp) + 8032134: 1080010c andi r2,r2,4 + if ((tiflags & TH_FIN && todrop == (int)ti->ti_len + 1) || + 8032138: 1003dd26 beq r2,zero,80330b0 + (tiflags & TH_RST && ti->ti_seq == tp->rcv_nxt - 1)) + 803213c: e0bff017 ldw r2,-64(fp) + 8032140: 10c00617 ldw r3,24(r2) + 8032144: e0bffc17 ldw r2,-16(fp) + 8032148: 10801617 ldw r2,88(r2) + 803214c: 10bfffc4 addi r2,r2,-1 + 8032150: 1883d71e bne r3,r2,80330b0 + { + todrop = ti->ti_len; + 8032154: e0bff017 ldw r2,-64(fp) + 8032158: 1080028b ldhu r2,10(r2) + 803215c: 10bfffcc andi r2,r2,65535 + 8032160: e0bff915 stw r2,-28(fp) + tiflags &= ~TH_FIN; + 8032164: e0fffb17 ldw r3,-20(fp) + 8032168: 00bfff84 movi r2,-2 + 803216c: 1884703a and r2,r3,r2 + 8032170: e0bffb15 stw r2,-20(fp) + tp->t_flags |= TF_ACKNOW; + 8032174: e0bffc17 ldw r2,-16(fp) + 8032178: 10800b0b ldhu r2,44(r2) + 803217c: 10800054 ori r2,r2,1 + 8032180: 1007883a mov r3,r2 + 8032184: e0bffc17 ldw r2,-16(fp) + 8032188: 10c00b0d sth r3,44(r2) + if ((tiflags & TH_FIN && todrop == (int)ti->ti_len + 1) || + 803218c: 00000b06 br 80321bc + else + goto dropafterack; + } + else + { + tcpstat.tcps_rcvpartduppack++; + 8032190: 008201b4 movhi r2,2054 + 8032194: 10b8c517 ldw r2,-7404(r2) + 8032198: 10c00044 addi r3,r2,1 + 803219c: 008201b4 movhi r2,2054 + 80321a0: 10f8c515 stw r3,-7404(r2) + tcpstat.tcps_rcvpartdupbyte += todrop; + 80321a4: 008201b4 movhi r2,2054 + 80321a8: 10f8c617 ldw r3,-7400(r2) + 80321ac: e0bff917 ldw r2,-28(fp) + 80321b0: 1887883a add r3,r3,r2 + 80321b4: 008201b4 movhi r2,2054 + 80321b8: 10f8c615 stw r3,-7400(r2) + } + m_adj(m, todrop); + 80321bc: e17ff917 ldw r5,-28(fp) + 80321c0: e13fe417 ldw r4,-112(fp) + 80321c4: 802a0180 call 802a018 + ti->ti_seq += todrop; + 80321c8: e0bff017 ldw r2,-64(fp) + 80321cc: 10c00617 ldw r3,24(r2) + 80321d0: e0bff917 ldw r2,-28(fp) + 80321d4: 1887883a add r3,r3,r2 + 80321d8: e0bff017 ldw r2,-64(fp) + 80321dc: 10c00615 stw r3,24(r2) + ti->ti_len -= (u_short)todrop; + 80321e0: e0bff017 ldw r2,-64(fp) + 80321e4: 1080028b ldhu r2,10(r2) + 80321e8: e0fff917 ldw r3,-28(fp) + 80321ec: 10c5c83a sub r2,r2,r3 + 80321f0: 1007883a mov r3,r2 + 80321f4: e0bff017 ldw r2,-64(fp) + 80321f8: 10c0028d sth r3,10(r2) + if (ti->ti_urp > (u_short)todrop) + 80321fc: e0bff017 ldw r2,-64(fp) + 8032200: 1080098b ldhu r2,38(r2) + 8032204: e0fff917 ldw r3,-28(fp) + 8032208: 10bfffcc andi r2,r2,65535 + 803220c: 18ffffcc andi r3,r3,65535 + 8032210: 1880082e bgeu r3,r2,8032234 + ti->ti_urp -= (u_short)todrop; + 8032214: e0bff017 ldw r2,-64(fp) + 8032218: 1080098b ldhu r2,38(r2) + 803221c: e0fff917 ldw r3,-28(fp) + 8032220: 10c5c83a sub r2,r2,r3 + 8032224: 1007883a mov r3,r2 + 8032228: e0bff017 ldw r2,-64(fp) + 803222c: 10c0098d sth r3,38(r2) + 8032230: 00000606 br 803224c + else + { + tiflags &= ~TH_URG; + 8032234: e0fffb17 ldw r3,-20(fp) + 8032238: 00bff7c4 movi r2,-33 + 803223c: 1884703a and r2,r3,r2 + 8032240: e0bffb15 stw r2,-20(fp) + ti->ti_urp = 0; + 8032244: e0bff017 ldw r2,-64(fp) + 8032248: 1000098d sth zero,38(r2) + + /* + * If new data are received on a connection after the + * user processes are gone, then RST the other end. + */ + if ((so->so_state & SS_NOFDREF) && + 803224c: e0bffa17 ldw r2,-24(fp) + 8032250: 1080088b ldhu r2,34(r2) + 8032254: 10bfffcc andi r2,r2,65535 + 8032258: 1080004c andi r2,r2,1 + 803225c: 10001326 beq r2,zero,80322ac + tp->t_state > TCPS_CLOSE_WAIT && ti->ti_len) + 8032260: e0bffc17 ldw r2,-16(fp) + 8032264: 10800217 ldw r2,8(r2) + if ((so->so_state & SS_NOFDREF) && + 8032268: 10800190 cmplti r2,r2,6 + 803226c: 10000f1e bne r2,zero,80322ac + tp->t_state > TCPS_CLOSE_WAIT && ti->ti_len) + 8032270: e0bff017 ldw r2,-64(fp) + 8032274: 1080028b ldhu r2,10(r2) + 8032278: 10bfffcc andi r2,r2,65535 + 803227c: 10000b26 beq r2,zero,80322ac + { + tp = tcp_close(tp); + 8032280: e13ffc17 ldw r4,-16(fp) + 8032284: 80350e80 call 80350e8 + 8032288: e0bffc15 stw r2,-16(fp) + tcpstat.tcps_rcvafterclose++; + 803228c: 008201b4 movhi r2,2054 + 8032290: 10b8cb17 ldw r2,-7380(r2) + 8032294: 10c00044 addi r3,r2,1 + 8032298: 008201b4 movhi r2,2054 + 803229c: 10f8cb15 stw r3,-7380(r2) + GOTO_DROPWITHRESET; + 80322a0: 00810444 movi r2,1041 + 80322a4: d0a08715 stw r2,-32228(gp) + 80322a8: 00039506 br 8033100 + + /* + * If segment ends after window, drop trailing data + * (and PUSH and FIN); if nothing left, just ACK. + */ + todrop = (int)((ti->ti_seq + (short)ti->ti_len) - (tp->rcv_nxt+tp->rcv_wnd)); + 80322ac: e0bff017 ldw r2,-64(fp) + 80322b0: 10c00617 ldw r3,24(r2) + 80322b4: e0bff017 ldw r2,-64(fp) + 80322b8: 1080028b ldhu r2,10(r2) + 80322bc: 10bfffcc andi r2,r2,65535 + 80322c0: 10a0001c xori r2,r2,32768 + 80322c4: 10a00004 addi r2,r2,-32768 + 80322c8: 1887883a add r3,r3,r2 + 80322cc: e0bffc17 ldw r2,-16(fp) + 80322d0: 11001617 ldw r4,88(r2) + 80322d4: e0bffc17 ldw r2,-16(fp) + 80322d8: 10801517 ldw r2,84(r2) + 80322dc: 2085883a add r2,r4,r2 + 80322e0: 1885c83a sub r2,r3,r2 + 80322e4: e0bff915 stw r2,-28(fp) + if (todrop > 0) + 80322e8: e0bff917 ldw r2,-28(fp) + 80322ec: 0080610e bge zero,r2,8032474 + { + tcpstat.tcps_rcvpackafterwin++; + 80322f0: 008201b4 movhi r2,2054 + 80322f4: 10b8c917 ldw r2,-7388(r2) + 80322f8: 10c00044 addi r3,r2,1 + 80322fc: 008201b4 movhi r2,2054 + 8032300: 10f8c915 stw r3,-7388(r2) + if (todrop >= (int)ti->ti_len) + 8032304: e0bff017 ldw r2,-64(fp) + 8032308: 1080028b ldhu r2,10(r2) + 803230c: 10bfffcc andi r2,r2,65535 + 8032310: e0fff917 ldw r3,-28(fp) + 8032314: 18803616 blt r3,r2,80323f0 + { + tcpstat.tcps_rcvbyteafterwin += ti->ti_len; + 8032318: 008201b4 movhi r2,2054 + 803231c: 10f8ca17 ldw r3,-7384(r2) + 8032320: e0bff017 ldw r2,-64(fp) + 8032324: 1080028b ldhu r2,10(r2) + 8032328: 10bfffcc andi r2,r2,65535 + 803232c: 1887883a add r3,r3,r2 + 8032330: 008201b4 movhi r2,2054 + 8032334: 10f8ca15 stw r3,-7384(r2) + * If a new connection request is received + * while in TIME_WAIT, drop the old connection + * and start over if the sequence numbers + * are above the previous ones. + */ + if (tiflags & TH_SYN && + 8032338: e0bffb17 ldw r2,-20(fp) + 803233c: 1080008c andi r2,r2,2 + 8032340: 10001726 beq r2,zero,80323a0 + tp->t_state == TCPS_TIME_WAIT && + 8032344: e0bffc17 ldw r2,-16(fp) + 8032348: 10800217 ldw r2,8(r2) + if (tiflags & TH_SYN && + 803234c: 10800298 cmpnei r2,r2,10 + 8032350: 1000131e bne r2,zero,80323a0 + SEQ_GT(ti->ti_seq, tp->rcv_nxt)) + 8032354: e0bff017 ldw r2,-64(fp) + 8032358: 10c00617 ldw r3,24(r2) + 803235c: e0bffc17 ldw r2,-16(fp) + 8032360: 10801617 ldw r2,88(r2) + 8032364: 1885c83a sub r2,r3,r2 + tp->t_state == TCPS_TIME_WAIT && + 8032368: 00800d0e bge zero,r2,80323a0 + { + iss = (tcp_seq)(tp->rcv_nxt + (TCP_ISSINCR)); + 803236c: e0bffc17 ldw r2,-16(fp) + 8032370: 10c01617 ldw r3,88(r2) + 8032374: 008000b4 movhi r2,2 + 8032378: 10bd3fc4 addi r2,r2,-2817 + 803237c: 1885883a add r2,r3,r2 + 8032380: e0bff515 stw r2,-44(fp) + if (iss & 0xff000000) + 8032384: e0bff517 ldw r2,-44(fp) + 8032388: 10bfc02c andhi r2,r2,65280 + 803238c: 10000126 beq r2,zero,8032394 + { + iss = 0L; + 8032390: e03ff515 stw zero,-44(fp) + } + (void) tcp_close(tp); + 8032394: e13ffc17 ldw r4,-16(fp) + 8032398: 80350e80 call 80350e8 + goto findpcb; + 803239c: 003bf806 br 8031380 + * window edge, and have to drop data and PUSH from + * incoming segments. Continue processing, but + * remember to ack. Otherwise, drop segment + * and ack. + */ + if ((tp->rcv_wnd == 0) && (ti->ti_seq == tp->rcv_nxt)) + 80323a0: e0bffc17 ldw r2,-16(fp) + 80323a4: 10801517 ldw r2,84(r2) + 80323a8: 1003431e bne r2,zero,80330b8 + 80323ac: e0bff017 ldw r2,-64(fp) + 80323b0: 10c00617 ldw r3,24(r2) + 80323b4: e0bffc17 ldw r2,-16(fp) + 80323b8: 10801617 ldw r2,88(r2) + 80323bc: 18833e1e bne r3,r2,80330b8 + { + tp->t_flags |= TF_ACKNOW; + 80323c0: e0bffc17 ldw r2,-16(fp) + 80323c4: 10800b0b ldhu r2,44(r2) + 80323c8: 10800054 ori r2,r2,1 + 80323cc: 1007883a mov r3,r2 + 80323d0: e0bffc17 ldw r2,-16(fp) + 80323d4: 10c00b0d sth r3,44(r2) + tcpstat.tcps_rcvwinprobe++; + 80323d8: 008201b4 movhi r2,2054 + 80323dc: 10b8cc17 ldw r2,-7376(r2) + 80323e0: 10c00044 addi r3,r2,1 + 80323e4: 008201b4 movhi r2,2054 + 80323e8: 10f8cc15 stw r3,-7376(r2) + 80323ec: 00000606 br 8032408 + } else + goto dropafterack; + } else + tcpstat.tcps_rcvbyteafterwin += todrop; + 80323f0: 008201b4 movhi r2,2054 + 80323f4: 10f8ca17 ldw r3,-7384(r2) + 80323f8: e0bff917 ldw r2,-28(fp) + 80323fc: 1887883a add r3,r3,r2 + 8032400: 008201b4 movhi r2,2054 + 8032404: 10f8ca15 stw r3,-7384(r2) + /* XXX work around m_adj bug */ + if (m->m_len) + 8032408: e0bfe417 ldw r2,-112(fp) + 803240c: 10800217 ldw r2,8(r2) + 8032410: 10000626 beq r2,zero,803242c + { + m_adj(m, -todrop); + 8032414: e0bff917 ldw r2,-28(fp) + 8032418: 0085c83a sub r2,zero,r2 + 803241c: 100b883a mov r5,r2 + 8032420: e13fe417 ldw r4,-112(fp) + 8032424: 802a0180 call 802a018 + 8032428: 00000706 br 8032448 + } + else + { + /* skip tcp/ip header in first mbuf */ + m_adj(m->m_next, -todrop); + 803242c: e0bfe417 ldw r2,-112(fp) + 8032430: 10c00617 ldw r3,24(r2) + 8032434: e0bff917 ldw r2,-28(fp) + 8032438: 0085c83a sub r2,zero,r2 + 803243c: 100b883a mov r5,r2 + 8032440: 1809883a mov r4,r3 + 8032444: 802a0180 call 802a018 + } + ti->ti_len -= (u_short)todrop; + 8032448: e0bff017 ldw r2,-64(fp) + 803244c: 1080028b ldhu r2,10(r2) + 8032450: e0fff917 ldw r3,-28(fp) + 8032454: 10c5c83a sub r2,r2,r3 + 8032458: 1007883a mov r3,r2 + 803245c: e0bff017 ldw r2,-64(fp) + 8032460: 10c0028d sth r3,10(r2) + tiflags &= ~(TH_PUSH|TH_FIN); + 8032464: e0fffb17 ldw r3,-20(fp) + 8032468: 00bffd84 movi r2,-10 + 803246c: 1884703a and r2,r3,r2 + 8032470: e0bffb15 stw r2,-20(fp) + tiflags &= ~TH_RST; /* clear reset flag */ + goto dropafterack; /* send an ack and drop current packet */ + } +#endif /* DOS_RST */ + + if (tiflags&TH_RST) + 8032474: e0bffb17 ldw r2,-20(fp) + 8032478: 1080010c andi r2,r2,4 + 803247c: 10002f26 beq r2,zero,803253c + { + switch (tp->t_state) + 8032480: e0bffc17 ldw r2,-16(fp) + 8032484: 10800217 ldw r2,8(r2) + 8032488: 10bfff44 addi r2,r2,-3 + 803248c: 10c00228 cmpgeui r3,r2,8 + 8032490: 18002a1e bne r3,zero,803253c + 8032494: 100690ba slli r3,r2,2 + 8032498: 008200f4 movhi r2,2051 + 803249c: 1885883a add r2,r3,r2 + 80324a0: 10892a17 ldw r2,9384(r2) + 80324a4: 1000683a jmp r2 + 80324a8: 080324c8 cmpgei zero,at,3219 + 80324ac: 080324d8 cmpnei zero,at,3219 + 80324b0: 080324ec andhi zero,at,3219 + 80324b4: 080324ec andhi zero,at,3219 + 80324b8: 08032528 cmpgeui zero,at,3220 + 80324bc: 08032528 cmpgeui zero,at,3220 + 80324c0: 080324ec andhi zero,at,3219 + 80324c4: 08032528 cmpgeui zero,at,3220 + { + + case TCPS_SYN_RECEIVED: + so->so_error = ECONNREFUSED; + 80324c8: e0bffa17 ldw r2,-24(fp) + 80324cc: 00c01bc4 movi r3,111 + 80324d0: 10c00615 stw r3,24(r2) + goto close; + 80324d4: 00000806 br 80324f8 + + case TCPS_ESTABLISHED: + TCP_MIB_INC(tcpEstabResets); /* keep MIB stats */ + 80324d8: 008201b4 movhi r2,2054 + 80324dc: 10b87d17 ldw r2,-7692(r2) + 80324e0: 10c00044 addi r3,r2,1 + 80324e4: 008201b4 movhi r2,2054 + 80324e8: 10f87d15 stw r3,-7692(r2) + case TCPS_FIN_WAIT_1: + case TCPS_FIN_WAIT_2: + case TCPS_CLOSE_WAIT: + so->so_error = ECONNRESET; + 80324ec: e0bffa17 ldw r2,-24(fp) + 80324f0: 00c01a04 movi r3,104 + 80324f4: 10c00615 stw r3,24(r2) + close: + tp->t_state = TCPS_CLOSED; + 80324f8: e0bffc17 ldw r2,-16(fp) + 80324fc: 10000215 stw zero,8(r2) + tcpstat.tcps_drops++; + 8032500: 008201b4 movhi r2,2054 + 8032504: 10b8a717 ldw r2,-7524(r2) + 8032508: 10c00044 addi r3,r2,1 + 803250c: 008201b4 movhi r2,2054 + 8032510: 10f8a715 stw r3,-7524(r2) + SETTP(tp, tcp_close(tp)); + 8032514: e13ffc17 ldw r4,-16(fp) + 8032518: 80350e80 call 80350e8 +#ifdef TCP_ZEROCOPY + if (so->rx_upcall) + so->rx_upcall(so, NULL, ECONNRESET); +#endif /* TCP_ZEROCOPY */ + GOTO_DROP; + 803251c: 00812204 movi r2,1160 + 8032520: d0a08715 stw r2,-32228(gp) + 8032524: 00033506 br 80331fc + + case TCPS_CLOSING: + case TCPS_LAST_ACK: + case TCPS_TIME_WAIT: + SETTP(tp, tcp_close(tp)); + 8032528: e13ffc17 ldw r4,-16(fp) + 803252c: 80350e80 call 80350e8 + GOTO_DROP; + 8032530: 00812384 movi r2,1166 + 8032534: d0a08715 stw r2,-32228(gp) + 8032538: 00033006 br 80331fc + tcp_trace("rcvd SYN in established state - ignoring SYN.\n"); +#endif + GOTO_DROP; + } +#else + if (tiflags & TH_SYN) + 803253c: e0bffb17 ldw r2,-20(fp) + 8032540: 1080008c andi r2,r2,2 + 8032544: 10000726 beq r2,zero,8032564 + { + tp = tcp_drop(tp, ECONNRESET); + 8032548: 01401a04 movi r5,104 + 803254c: e13ffc17 ldw r4,-16(fp) + 8032550: 803504c0 call 803504c + 8032554: e0bffc15 stw r2,-16(fp) + GOTO_DROPWITHRESET; + 8032558: 00812b04 movi r2,1196 + 803255c: d0a08715 stw r2,-32228(gp) + 8032560: 0002e706 br 8033100 +#endif /* end of else of DOS_SYN */ + + /* + * If the ACK bit is off we drop the segment and return. + */ + if ((tiflags & TH_ACK) == 0) + 8032564: e0bffb17 ldw r2,-20(fp) + 8032568: 1080040c andi r2,r2,16 + 803256c: 1000031e bne r2,zero,803257c + GOTO_DROP; + 8032570: 00812d04 movi r2,1204 + 8032574: d0a08715 stw r2,-32228(gp) + 8032578: 00032006 br 80331fc + + /* + * Ack processing. + */ + switch (tp->t_state) + 803257c: e0bffc17 ldw r2,-16(fp) + 8032580: 10800217 ldw r2,8(r2) + 8032584: 10c000e0 cmpeqi r3,r2,3 + 8032588: 1800051e bne r3,zero,80325a0 + 803258c: 10c000d0 cmplti r3,r2,3 + 8032590: 1801681e bne r3,zero,8032b34 + 8032594: 108002c8 cmpgei r2,r2,11 + 8032598: 1001661e bne r2,zero,8032b34 + 803259c: 00002c06 br 8032650 + * In SYN_RECEIVED state if the ack ACKs our SYN then enter + * ESTABLISHED state and continue processing, otherwise + * send an RST. + */ + case TCPS_SYN_RECEIVED: + if (SEQ_GT(tp->snd_una, ti->ti_ack) || + 80325a0: e0bffc17 ldw r2,-16(fp) + 80325a4: 10c00e17 ldw r3,56(r2) + 80325a8: e0bff017 ldw r2,-64(fp) + 80325ac: 10800717 ldw r2,28(r2) + 80325b0: 1885c83a sub r2,r3,r2 + 80325b4: 00800616 blt zero,r2,80325d0 + SEQ_GT(ti->ti_ack, tp->snd_max)) + 80325b8: e0bff017 ldw r2,-64(fp) + 80325bc: 10c00717 ldw r3,28(r2) + 80325c0: e0bffc17 ldw r2,-16(fp) + 80325c4: 10801a17 ldw r2,104(r2) + 80325c8: 1885c83a sub r2,r3,r2 + if (SEQ_GT(tp->snd_una, ti->ti_ack) || + 80325cc: 0080080e bge zero,r2,80325f0 + { + TCP_MIB_INC(tcpEstabResets); /* keep MIB stats */ + 80325d0: 008201b4 movhi r2,2054 + 80325d4: 10b87d17 ldw r2,-7692(r2) + 80325d8: 10c00044 addi r3,r2,1 + 80325dc: 008201b4 movhi r2,2054 + 80325e0: 10f87d15 stw r3,-7692(r2) + GOTO_DROPWITHRESET; + 80325e4: 00813184 movi r2,1222 + 80325e8: d0a08715 stw r2,-32228(gp) + 80325ec: 0002c406 br 8033100 + } + tcpstat.tcps_connects++; + 80325f0: 008201b4 movhi r2,2054 + 80325f4: 10b8a617 ldw r2,-7528(r2) + 80325f8: 10c00044 addi r3,r2,1 + 80325fc: 008201b4 movhi r2,2054 + 8032600: 10f8a615 stw r3,-7528(r2) + tp->t_state = TCPS_ESTABLISHED; + 8032604: e0bffc17 ldw r2,-16(fp) + 8032608: 00c00104 movi r3,4 + 803260c: 10c00215 stw r3,8(r2) + soisconnected(so); + 8032610: e13ffa17 ldw r4,-24(fp) + 8032614: 802f1e80 call 802f1e8 + tp->t_maxseg = tcp_mss(so); + 8032618: e13ffa17 ldw r4,-24(fp) + 803261c: 803379c0 call 803379c + 8032620: 1007883a mov r3,r2 + 8032624: e0bffc17 ldw r2,-16(fp) + 8032628: 10c00a0d sth r3,40(r2) + (void) tcp_reass(tp, (struct tcpiphdr *)0, m); + 803262c: e1bfe417 ldw r6,-112(fp) + 8032630: 000b883a mov r5,zero + 8032634: e13ffc17 ldw r4,-16(fp) + 8032638: 8030c600 call 8030c60 + tp->snd_wl1 = ti->ti_seq - 1; + 803263c: e0bff017 ldw r2,-64(fp) + 8032640: 10800617 ldw r2,24(r2) + 8032644: 10ffffc4 addi r3,r2,-1 + 8032648: e0bffc17 ldw r2,-16(fp) + 803264c: 10c01115 stw r3,68(r2) + case TCPS_CLOSE_WAIT: + case TCPS_CLOSING: + case TCPS_LAST_ACK: + case TCPS_TIME_WAIT: + + if (SEQ_LEQ(ti->ti_ack, tp->snd_una)) + 8032650: e0bff017 ldw r2,-64(fp) + 8032654: 10c00717 ldw r3,28(r2) + 8032658: e0bffc17 ldw r2,-16(fp) + 803265c: 10800e17 ldw r2,56(r2) + 8032660: 1885c83a sub r2,r3,r2 + 8032664: 00806116 blt zero,r2,80327ec + { + if (ti->ti_len == 0 && rx_win == tp->snd_wnd) + 8032668: e0bff017 ldw r2,-64(fp) + 803266c: 1080028b ldhu r2,10(r2) + 8032670: 10bfffcc andi r2,r2,65535 + 8032674: 1000581e bne r2,zero,80327d8 + 8032678: e0bffc17 ldw r2,-16(fp) + 803267c: 10801417 ldw r2,80(r2) + 8032680: e0ffed17 ldw r3,-76(fp) + 8032684: 1880541e bne r3,r2,80327d8 + { + tcpstat.tcps_rcvdupack++; + 8032688: 008201b4 movhi r2,2054 + 803268c: 10b8cd17 ldw r2,-7372(r2) + 8032690: 10c00044 addi r3,r2,1 + 8032694: 008201b4 movhi r2,2054 + 8032698: 10f8cd15 stw r3,-7372(r2) + * ack and the exp-to-linear thresh + * set for half the current window + * size (since we know we're losing at + * the current window size). + */ + if (tp->t_timer[TCPT_REXMT] == 0 || + 803269c: e0bffc17 ldw r2,-16(fp) + 80326a0: 10800317 ldw r2,12(r2) + 80326a4: 10000526 beq r2,zero,80326bc + ti->ti_ack != tp->snd_una) + 80326a8: e0bff017 ldw r2,-64(fp) + 80326ac: 10c00717 ldw r3,28(r2) + 80326b0: e0bffc17 ldw r2,-16(fp) + 80326b4: 10800e17 ldw r2,56(r2) + if (tp->t_timer[TCPT_REXMT] == 0 || + 80326b8: 18800326 beq r3,r2,80326c8 + { + tp->t_dupacks = 0; + 80326bc: e0bffc17 ldw r2,-16(fp) + 80326c0: 10000915 stw zero,36(r2) + if (tp->t_timer[TCPT_REXMT] == 0 || + 80326c4: 00004706 br 80327e4 + } + else if (++tp->t_dupacks == tcprexmtthresh) + 80326c8: e0bffc17 ldw r2,-16(fp) + 80326cc: 10800917 ldw r2,36(r2) + 80326d0: 10c00044 addi r3,r2,1 + 80326d4: e0bffc17 ldw r2,-16(fp) + 80326d8: 10c00915 stw r3,36(r2) + 80326dc: e0bffc17 ldw r2,-16(fp) + 80326e0: 10c00917 ldw r3,36(r2) + 80326e4: d0a01c83 ldbu r2,-32654(gp) + 80326e8: 10803fcc andi r2,r2,255 + 80326ec: 1080201c xori r2,r2,128 + 80326f0: 10bfe004 addi r2,r2,-128 + 80326f4: 18803b1e bne r3,r2,80327e4 + { + tcp_seq onxt = tp->snd_nxt; + 80326f8: e0bffc17 ldw r2,-16(fp) + 80326fc: 10800f17 ldw r2,60(r2) + 8032700: e0bfe815 stw r2,-96(fp) + u_short win = + MIN(tp->snd_wnd, tp->snd_cwnd) / 2 / + 8032704: e0bffc17 ldw r2,-16(fp) + 8032708: 11001417 ldw r4,80(r2) + 803270c: e0bffc17 ldw r2,-16(fp) + 8032710: 10c01b17 ldw r3,108(r2) + 8032714: 2005883a mov r2,r4 + 8032718: 1880012e bgeu r3,r2,8032720 + 803271c: 1805883a mov r2,r3 + 8032720: 1006d07a srli r3,r2,1 + tp->t_maxseg; + 8032724: e0bffc17 ldw r2,-16(fp) + 8032728: 10800a0b ldhu r2,40(r2) + 803272c: 10bfffcc andi r2,r2,65535 + MIN(tp->snd_wnd, tp->snd_cwnd) / 2 / + 8032730: 100b883a mov r5,r2 + 8032734: 1809883a mov r4,r3 + 8032738: 800cff80 call 800cff8 <__udivsi3> + u_short win = + 803273c: e0bff28d sth r2,-54(fp) + + if (win < 2) + 8032740: e0bff28b ldhu r2,-54(fp) + 8032744: 108000a8 cmpgeui r2,r2,2 + 8032748: 1000021e bne r2,zero,8032754 + win = 2; + 803274c: 00800084 movi r2,2 + 8032750: e0bff28d sth r2,-54(fp) + tp->snd_ssthresh = (u_short)(win * tp->t_maxseg); + 8032754: e0bffc17 ldw r2,-16(fp) + 8032758: 10800a0b ldhu r2,40(r2) + 803275c: e0fff28b ldhu r3,-54(fp) + 8032760: 1885383a mul r2,r3,r2 + 8032764: 10ffffcc andi r3,r2,65535 + 8032768: e0bffc17 ldw r2,-16(fp) + 803276c: 10c01c15 stw r3,112(r2) + + tp->t_timer[TCPT_REXMT] = 0; + 8032770: e0bffc17 ldw r2,-16(fp) + 8032774: 10000315 stw zero,12(r2) + tp->t_rttick = 0; + 8032778: e0bffc17 ldw r2,-16(fp) + 803277c: 10001e15 stw zero,120(r2) + tp->snd_nxt = ti->ti_ack; + 8032780: e0bff017 ldw r2,-64(fp) + 8032784: 10c00717 ldw r3,28(r2) + 8032788: e0bffc17 ldw r2,-16(fp) + 803278c: 10c00f15 stw r3,60(r2) + tp->snd_cwnd = tp->t_maxseg; + 8032790: e0bffc17 ldw r2,-16(fp) + 8032794: 10800a0b ldhu r2,40(r2) + 8032798: 10ffffcc andi r3,r2,65535 + 803279c: e0bffc17 ldw r2,-16(fp) + 80327a0: 10c01b15 stw r3,108(r2) + (void) tcp_output(tp); + 80327a4: e13ffc17 ldw r4,-16(fp) + 80327a8: 80338940 call 8033894 + + if (SEQ_GT(onxt, tp->snd_nxt)) + 80327ac: e0bffc17 ldw r2,-16(fp) + 80327b0: 10800f17 ldw r2,60(r2) + 80327b4: e0ffe817 ldw r3,-96(fp) + 80327b8: 1885c83a sub r2,r3,r2 + 80327bc: 0080030e bge zero,r2,80327cc + tp->snd_nxt = onxt; + 80327c0: e0bffc17 ldw r2,-16(fp) + 80327c4: e0ffe817 ldw r3,-96(fp) + 80327c8: 10c00f15 stw r3,60(r2) + GOTO_DROP; + 80327cc: 00814544 movi r2,1301 + 80327d0: d0a08715 stw r2,-32228(gp) + 80327d4: 00028906 br 80331fc + } + } else + tp->t_dupacks = 0; + 80327d8: e0bffc17 ldw r2,-16(fp) + 80327dc: 10000915 stw zero,36(r2) + break; + 80327e0: 0000d406 br 8032b34 + if (tp->t_timer[TCPT_REXMT] == 0 || + 80327e4: 0001883a nop + break; + 80327e8: 0000d206 br 8032b34 + } + tp->t_dupacks = 0; + 80327ec: e0bffc17 ldw r2,-16(fp) + 80327f0: 10000915 stw zero,36(r2) + if (SEQ_GT(ti->ti_ack, tp->snd_max)) + 80327f4: e0bff017 ldw r2,-64(fp) + 80327f8: 10c00717 ldw r3,28(r2) + 80327fc: e0bffc17 ldw r2,-16(fp) + 8032800: 10801a17 ldw r2,104(r2) + 8032804: 1885c83a sub r2,r3,r2 + 8032808: 0080060e bge zero,r2,8032824 + { + tcpstat.tcps_rcvacktoomuch++; + 803280c: 008201b4 movhi r2,2054 + 8032810: 10b8ce17 ldw r2,-7368(r2) + 8032814: 10c00044 addi r3,r2,1 + 8032818: 008201b4 movhi r2,2054 + 803281c: 10f8ce15 stw r3,-7368(r2) + goto dropafterack; + 8032820: 00022606 br 80330bc + } + acked = (int)(ti->ti_ack - tp->snd_una); + 8032824: e0bff017 ldw r2,-64(fp) + 8032828: 10c00717 ldw r3,28(r2) + 803282c: e0bffc17 ldw r2,-16(fp) + 8032830: 10800e17 ldw r2,56(r2) + 8032834: 1885c83a sub r2,r3,r2 + 8032838: e0bfec15 stw r2,-80(fp) + tcpstat.tcps_rcvackpack++; + 803283c: 008201b4 movhi r2,2054 + 8032840: 10b8cf17 ldw r2,-7364(r2) + 8032844: 10c00044 addi r3,r2,1 + 8032848: 008201b4 movhi r2,2054 + 803284c: 10f8cf15 stw r3,-7364(r2) + tcpstat.tcps_rcvackbyte += acked; + 8032850: 008201b4 movhi r2,2054 + 8032854: 10f8d017 ldw r3,-7360(r2) + 8032858: e0bfec17 ldw r2,-80(fp) + 803285c: 1887883a add r3,r3,r2 + 8032860: 008201b4 movhi r2,2054 + 8032864: 10f8d015 stw r3,-7360(r2) + * number was acked, update smoothed round trip time. + * Since we now have an rtt measurement, cancel the + * timer backoff (cf., Phil Karn's retransmit alg.). + * Recompute the initial retransmit timer. + */ + if((tp->t_rttick) && + 8032868: e0bffc17 ldw r2,-16(fp) + 803286c: 10801e17 ldw r2,120(r2) + 8032870: 10000826 beq r2,zero,8032894 +#ifdef TCP_TIMESTAMP + ((tp->t_flags & TF_TIMESTAMP) == 0) && +#endif /* TCP_TIMESTAMP */ + (SEQ_GT(ti->ti_ack, tp->t_rtseq))) + 8032874: e0bff017 ldw r2,-64(fp) + 8032878: 10c00717 ldw r3,28(r2) + 803287c: e0bffc17 ldw r2,-16(fp) + 8032880: 10801f17 ldw r2,124(r2) + 8032884: 1885c83a sub r2,r3,r2 + if((tp->t_rttick) && + 8032888: 0080020e bge zero,r2,8032894 + tcp_xmit_timer(tp); + 803288c: e13ffc17 ldw r4,-16(fp) + 8032890: 80335180 call 8033518 + * If all outstanding data is acked, stop retransmit + * timer and remember to restart (more output or persist). + * If there is more data to be acked, restart retransmit + * timer, using current (possibly backed-off) value. + */ + if (ti->ti_ack == tp->snd_max) + 8032894: e0bff017 ldw r2,-64(fp) + 8032898: 10c00717 ldw r3,28(r2) + 803289c: e0bffc17 ldw r2,-16(fp) + 80328a0: 10801a17 ldw r2,104(r2) + 80328a4: 1880051e bne r3,r2,80328bc + { + tp->t_timer[TCPT_REXMT] = 0; + 80328a8: e0bffc17 ldw r2,-16(fp) + 80328ac: 10000315 stw zero,12(r2) + needoutput = 1; + 80328b0: 00800044 movi r2,1 + 80328b4: e0bff715 stw r2,-36(fp) + 80328b8: 00000706 br 80328d8 + } else if (tp->t_timer[TCPT_PERSIST] == 0) + 80328bc: e0bffc17 ldw r2,-16(fp) + 80328c0: 10800417 ldw r2,16(r2) + 80328c4: 1000041e bne r2,zero,80328d8 + tp->t_timer[TCPT_REXMT] = tp->t_rxtcur; + 80328c8: e0bffc17 ldw r2,-16(fp) + 80328cc: 10c00817 ldw r3,32(r2) + 80328d0: e0bffc17 ldw r2,-16(fp) + 80328d4: 10c00315 stw r3,12(r2) + * in flight, open exponentially (maxseg per packet). + * Otherwise open linearly (maxseg per window, + * or maxseg^2 / cwnd per packet). + */ + { + tcp_win cw = tp->snd_cwnd; + 80328d8: e0bffc17 ldw r2,-16(fp) + 80328dc: 10801b17 ldw r2,108(r2) + 80328e0: e0bfe715 stw r2,-100(fp) + u_short incr = tp->t_maxseg; + 80328e4: e0bffc17 ldw r2,-16(fp) + 80328e8: 10800a0b ldhu r2,40(r2) + 80328ec: e0bff20d sth r2,-56(fp) + + if (cw > tp->snd_ssthresh) + 80328f0: e0bffc17 ldw r2,-16(fp) + 80328f4: 10c01c17 ldw r3,112(r2) + 80328f8: e0bfe717 ldw r2,-100(fp) + 80328fc: 18800a2e bgeu r3,r2,8032928 + incr = MAX( (incr * incr / cw), (ALIGN_TYPE << 2) ); + 8032900: e0fff20b ldhu r3,-56(fp) + 8032904: e0bff20b ldhu r2,-56(fp) + 8032908: 1885383a mul r2,r3,r2 + 803290c: e17fe717 ldw r5,-100(fp) + 8032910: 1009883a mov r4,r2 + 8032914: 800cff80 call 800cff8 <__udivsi3> + 8032918: 10c00428 cmpgeui r3,r2,16 + 803291c: 1800011e bne r3,zero,8032924 + 8032920: 00800404 movi r2,16 + 8032924: e0bff20d sth r2,-56(fp) + + tp->snd_cwnd = MIN(cw + (u_short)incr, (IP_MAXPACKET)); + 8032928: e0fff20b ldhu r3,-56(fp) + 803292c: e0bfe717 ldw r2,-100(fp) + 8032930: 1885883a add r2,r3,r2 + 8032934: 10d80070 cmpltui r3,r2,24577 + 8032938: 1800011e bne r3,zero,8032940 + 803293c: 00980004 movi r2,24576 + 8032940: e0fffc17 ldw r3,-16(fp) + 8032944: 18801b15 stw r2,108(r3) + } + if (acked > (int)so->so_snd.sb_cc) + 8032948: e0bffa17 ldw r2,-24(fp) + 803294c: 10801217 ldw r2,72(r2) + 8032950: 1007883a mov r3,r2 + 8032954: e0bfec17 ldw r2,-80(fp) + 8032958: 1880120e bge r3,r2,80329a4 + { + tp->snd_wnd -= (u_short)so->so_snd.sb_cc; + 803295c: e0bffc17 ldw r2,-16(fp) + 8032960: 10c01417 ldw r3,80(r2) + 8032964: e0bffa17 ldw r2,-24(fp) + 8032968: 10801217 ldw r2,72(r2) + 803296c: 10bfffcc andi r2,r2,65535 + 8032970: 1887c83a sub r3,r3,r2 + 8032974: e0bffc17 ldw r2,-16(fp) + 8032978: 10c01415 stw r3,80(r2) + sbdrop(&so->so_snd, (int)so->so_snd.sb_cc); + 803297c: e0bffa17 ldw r2,-24(fp) + 8032980: 10c01204 addi r3,r2,72 + 8032984: e0bffa17 ldw r2,-24(fp) + 8032988: 10801217 ldw r2,72(r2) + 803298c: 100b883a mov r5,r2 + 8032990: 1809883a mov r4,r3 + 8032994: 80300b00 call 80300b0 + ourfinisacked = 1; + 8032998: 00800044 movi r2,1 + 803299c: e0bff815 stw r2,-32(fp) + 80329a0: 00000d06 br 80329d8 + } + else + { + sbdrop(&so->so_snd, acked); + 80329a4: e0bffa17 ldw r2,-24(fp) + 80329a8: 10801204 addi r2,r2,72 + 80329ac: e17fec17 ldw r5,-80(fp) + 80329b0: 1009883a mov r4,r2 + 80329b4: 80300b00 call 80300b0 + tp->snd_wnd -= (u_short)acked; + 80329b8: e0bffc17 ldw r2,-16(fp) + 80329bc: 10c01417 ldw r3,80(r2) + 80329c0: e0bfec17 ldw r2,-80(fp) + 80329c4: 10bfffcc andi r2,r2,65535 + 80329c8: 1887c83a sub r3,r3,r2 + 80329cc: e0bffc17 ldw r2,-16(fp) + 80329d0: 10c01415 stw r3,80(r2) + ourfinisacked = 0; + 80329d4: e03ff815 stw zero,-32(fp) + } + + if (so->so_snd.sb_flags & (SB_WAIT | SB_SEL)) + 80329d8: e0bffa17 ldw r2,-24(fp) + 80329dc: 1080190b ldhu r2,100(r2) + 80329e0: 10bfffcc andi r2,r2,65535 + 80329e4: 1080030c andi r2,r2,12 + 80329e8: 10000526 beq r2,zero,8032a00 + sowwakeup(so); + 80329ec: e0bffa17 ldw r2,-24(fp) + 80329f0: 10801204 addi r2,r2,72 + 80329f4: 100b883a mov r5,r2 + 80329f8: e13ffa17 ldw r4,-24(fp) + 80329fc: 802f94c0 call 802f94c + + tp->snd_una = ti->ti_ack; + 8032a00: e0bff017 ldw r2,-64(fp) + 8032a04: 10c00717 ldw r3,28(r2) + 8032a08: e0bffc17 ldw r2,-16(fp) + 8032a0c: 10c00e15 stw r3,56(r2) + if (SEQ_LT(tp->snd_nxt, tp->snd_una)) + 8032a10: e0bffc17 ldw r2,-16(fp) + 8032a14: 10c00f17 ldw r3,60(r2) + 8032a18: e0bffc17 ldw r2,-16(fp) + 8032a1c: 10800e17 ldw r2,56(r2) + 8032a20: 1885c83a sub r2,r3,r2 + 8032a24: 1000040e bge r2,zero,8032a38 + tp->snd_nxt = tp->snd_una; + 8032a28: e0bffc17 ldw r2,-16(fp) + 8032a2c: 10c00e17 ldw r3,56(r2) + 8032a30: e0bffc17 ldw r2,-16(fp) + 8032a34: 10c00f15 stw r3,60(r2) + + + switch (tp->t_state) + 8032a38: e0bffc17 ldw r2,-16(fp) + 8032a3c: 10800217 ldw r2,8(r2) + 8032a40: 10c001e0 cmpeqi r3,r2,7 + 8032a44: 18001a1e bne r3,zero,8032ab0 + 8032a48: 10c00208 cmpgei r3,r2,8 + 8032a4c: 1800031e bne r3,zero,8032a5c + 8032a50: 108001a0 cmpeqi r2,r2,6 + 8032a54: 1000061e bne r2,zero,8032a70 + 8032a58: 00003606 br 8032b34 + 8032a5c: 10c00220 cmpeqi r3,r2,8 + 8032a60: 1800221e bne r3,zero,8032aec + 8032a64: 108002a0 cmpeqi r2,r2,10 + 8032a68: 1000271e bne r2,zero,8032b08 + 8032a6c: 00003106 br 8032b34 + * In FIN_WAIT_1 STATE in addition to the processing + * for the ESTABLISHED state if our FIN is now acknowledged + * then enter FIN_WAIT_2. + */ + case TCPS_FIN_WAIT_1: + if (ourfinisacked) + 8032a70: e0bff817 ldw r2,-32(fp) + 8032a74: 10002a26 beq r2,zero,8032b20 + * data, then closing user can proceed. + * Starting the timer is contrary to the + * specification, but if we don't get a FIN + * we'll hang forever. + */ + if (so->so_state & SS_CANTRCVMORE) + 8032a78: e0bffa17 ldw r2,-24(fp) + 8032a7c: 1080088b ldhu r2,34(r2) + 8032a80: 10bfffcc andi r2,r2,65535 + 8032a84: 1080080c andi r2,r2,32 + 8032a88: 10000526 beq r2,zero,8032aa0 + { + soisdisconnected(so); + 8032a8c: e13ffa17 ldw r4,-24(fp) + 8032a90: 802f3840 call 802f384 + tp->t_timer[TCPT_2MSL] = tcp_maxidle; + 8032a94: d0e08917 ldw r3,-32220(gp) + 8032a98: e0bffc17 ldw r2,-16(fp) + 8032a9c: 10c00615 stw r3,24(r2) + } + tp->t_state = TCPS_FIN_WAIT_2; + 8032aa0: e0bffc17 ldw r2,-16(fp) + 8032aa4: 00c00244 movi r3,9 + 8032aa8: 10c00215 stw r3,8(r2) + } + break; + 8032aac: 00001c06 br 8032b20 + * the ESTABLISHED state if the ACK acknowledges our FIN + * then enter the TIME-WAIT state, otherwise ignore + * the segment. + */ + case TCPS_CLOSING: + if (ourfinisacked) + 8032ab0: e0bff817 ldw r2,-32(fp) + 8032ab4: 10001c26 beq r2,zero,8032b28 + { + tp->t_state = TCPS_TIME_WAIT; + 8032ab8: e0bffc17 ldw r2,-16(fp) + 8032abc: 00c00284 movi r3,10 + 8032ac0: 10c00215 stw r3,8(r2) + tcp_canceltimers(tp); + 8032ac4: e13ffc17 ldw r4,-16(fp) + 8032ac8: 80355640 call 8035564 + tp->t_timer[TCPT_2MSL] = 2 * TCPTV_MSL; + 8032acc: d0a01b17 ldw r2,-32660(gp) + 8032ad0: 1085883a add r2,r2,r2 + 8032ad4: 1007883a mov r3,r2 + 8032ad8: e0bffc17 ldw r2,-16(fp) + 8032adc: 10c00615 stw r3,24(r2) + soisdisconnected(so); + 8032ae0: e13ffa17 ldw r4,-24(fp) + 8032ae4: 802f3840 call 802f384 + } + break; + 8032ae8: 00000f06 br 8032b28 + * and/or to be acked, as well as for the ack of our FIN. + * If our FIN is now acknowledged, delete the TCB, + * enter the closed state and return. + */ + case TCPS_LAST_ACK: + if (ourfinisacked) + 8032aec: e0bff817 ldw r2,-32(fp) + 8032af0: 10000f26 beq r2,zero,8032b30 + { + SETTP(tp, tcp_close(tp)); + 8032af4: e13ffc17 ldw r4,-16(fp) + 8032af8: 80350e80 call 80350e8 + GOTO_DROP; + 8032afc: 00816644 movi r2,1433 + 8032b00: d0a08715 stw r2,-32228(gp) + 8032b04: 0001bd06 br 80331fc + * In TIME_WAIT state the only thing that should arrive + * is a retransmission of the remote FIN. Acknowledge + * it and restart the finack timer. + */ + case TCPS_TIME_WAIT: + tp->t_timer[TCPT_2MSL] = 2 * TCPTV_MSL; + 8032b08: d0a01b17 ldw r2,-32660(gp) + 8032b0c: 1085883a add r2,r2,r2 + 8032b10: 1007883a mov r3,r2 + 8032b14: e0bffc17 ldw r2,-16(fp) + 8032b18: 10c00615 stw r3,24(r2) + goto dropafterack; + 8032b1c: 00016706 br 80330bc + break; + 8032b20: 0001883a nop + 8032b24: 00000306 br 8032b34 + break; + 8032b28: 0001883a nop + 8032b2c: 00000106 br 8032b34 + break; + 8032b30: 0001883a nop +step6: + /* + * Update window information. + * Don't look at window if no ACK: TAC's send garbage on first SYN. + */ + if ((tiflags & TH_ACK) && + 8032b34: e0bffb17 ldw r2,-20(fp) + 8032b38: 1080040c andi r2,r2,16 + 8032b3c: 10004226 beq r2,zero,8032c48 + /* + * Altera Niche Stack Nios port modification: + * Add parenthesis to remove implicit order of operation + * & possible build warnings. + */ + (SEQ_LT(tp->snd_wl1, ti->ti_seq) || (tp->snd_wl1 == ti->ti_seq && + 8032b40: e0bffc17 ldw r2,-16(fp) + 8032b44: 10c01117 ldw r3,68(r2) + 8032b48: e0bff017 ldw r2,-64(fp) + 8032b4c: 10800617 ldw r2,24(r2) + 8032b50: 1885c83a sub r2,r3,r2 + if ((tiflags & TH_ACK) && + 8032b54: 10001416 blt r2,zero,8032ba8 + (SEQ_LT(tp->snd_wl1, ti->ti_seq) || (tp->snd_wl1 == ti->ti_seq && + 8032b58: e0bffc17 ldw r2,-16(fp) + 8032b5c: 10c01117 ldw r3,68(r2) + 8032b60: e0bff017 ldw r2,-64(fp) + 8032b64: 10800617 ldw r2,24(r2) + 8032b68: 1880371e bne r3,r2,8032c48 + (SEQ_LT(tp->snd_wl2, ti->ti_ack) || + 8032b6c: e0bffc17 ldw r2,-16(fp) + 8032b70: 10c01217 ldw r3,72(r2) + 8032b74: e0bff017 ldw r2,-64(fp) + 8032b78: 10800717 ldw r2,28(r2) + 8032b7c: 1885c83a sub r2,r3,r2 + (SEQ_LT(tp->snd_wl1, ti->ti_seq) || (tp->snd_wl1 == ti->ti_seq && + 8032b80: 10000916 blt r2,zero,8032ba8 + ((tp->snd_wl2 == ti->ti_ack) && (rx_win > tp->snd_wnd)))))) + 8032b84: e0bffc17 ldw r2,-16(fp) + 8032b88: 10c01217 ldw r3,72(r2) + 8032b8c: e0bff017 ldw r2,-64(fp) + 8032b90: 10800717 ldw r2,28(r2) + (SEQ_LT(tp->snd_wl2, ti->ti_ack) || + 8032b94: 18802c1e bne r3,r2,8032c48 + ((tp->snd_wl2 == ti->ti_ack) && (rx_win > tp->snd_wnd)))))) + 8032b98: e0bffc17 ldw r2,-16(fp) + 8032b9c: 10c01417 ldw r3,80(r2) + 8032ba0: e0bfed17 ldw r2,-76(fp) + 8032ba4: 1880282e bgeu r3,r2,8032c48 + { + /* keep track of pure window updates */ + if ((ti->ti_len == 0) && + 8032ba8: e0bff017 ldw r2,-64(fp) + 8032bac: 1080028b ldhu r2,10(r2) + 8032bb0: 10bfffcc andi r2,r2,65535 + 8032bb4: 10000e1e bne r2,zero,8032bf0 + (tp->snd_wl2 == ti->ti_ack) && + 8032bb8: e0bffc17 ldw r2,-16(fp) + 8032bbc: 10c01217 ldw r3,72(r2) + 8032bc0: e0bff017 ldw r2,-64(fp) + 8032bc4: 10800717 ldw r2,28(r2) + if ((ti->ti_len == 0) && + 8032bc8: 1880091e bne r3,r2,8032bf0 + (rx_win > tp->snd_wnd)) + 8032bcc: e0bffc17 ldw r2,-16(fp) + 8032bd0: 10c01417 ldw r3,80(r2) + (tp->snd_wl2 == ti->ti_ack) && + 8032bd4: e0bfed17 ldw r2,-76(fp) + 8032bd8: 1880052e bgeu r3,r2,8032bf0 + { + tcpstat.tcps_rcvwinupd++; + 8032bdc: 008201b4 movhi r2,2054 + 8032be0: 10b8d117 ldw r2,-7356(r2) + 8032be4: 10c00044 addi r3,r2,1 + 8032be8: 008201b4 movhi r2,2054 + 8032bec: 10f8d115 stw r3,-7356(r2) + } + tp->snd_wnd = rx_win; + 8032bf0: e0bffc17 ldw r2,-16(fp) + 8032bf4: e0ffed17 ldw r3,-76(fp) + 8032bf8: 10c01415 stw r3,80(r2) + tp->snd_wl1 = ti->ti_seq; + 8032bfc: e0bff017 ldw r2,-64(fp) + 8032c00: 10c00617 ldw r3,24(r2) + 8032c04: e0bffc17 ldw r2,-16(fp) + 8032c08: 10c01115 stw r3,68(r2) + tp->snd_wl2 = ti->ti_ack; + 8032c0c: e0bff017 ldw r2,-64(fp) + 8032c10: 10c00717 ldw r3,28(r2) + 8032c14: e0bffc17 ldw r2,-16(fp) + 8032c18: 10c01215 stw r3,72(r2) + if (tp->snd_wnd > tp->max_sndwnd) + 8032c1c: e0bffc17 ldw r2,-16(fp) + 8032c20: 10801417 ldw r2,80(r2) + 8032c24: e0fffc17 ldw r3,-16(fp) + 8032c28: 18c02317 ldw r3,140(r3) + 8032c2c: 1880042e bgeu r3,r2,8032c40 + tp->max_sndwnd = tp->snd_wnd; + 8032c30: e0bffc17 ldw r2,-16(fp) + 8032c34: 10c01417 ldw r3,80(r2) + 8032c38: e0bffc17 ldw r2,-16(fp) + 8032c3c: 10c02315 stw r3,140(r2) + needoutput = 1; + 8032c40: 00800044 movi r2,1 + 8032c44: e0bff715 stw r2,-36(fp) + } + + /* + * Process segments with URG. + */ + if ((tiflags & TH_URG) && ti->ti_urp && + 8032c48: e0bffb17 ldw r2,-20(fp) + 8032c4c: 1080080c andi r2,r2,32 + 8032c50: 10005626 beq r2,zero,8032dac + 8032c54: e0bff017 ldw r2,-64(fp) + 8032c58: 1080098b ldhu r2,38(r2) + 8032c5c: 10bfffcc andi r2,r2,65535 + 8032c60: 10005226 beq r2,zero,8032dac + TCPS_HAVERCVDFIN(tp->t_state) == 0) + 8032c64: e0bffc17 ldw r2,-16(fp) + 8032c68: 10800217 ldw r2,8(r2) + if ((tiflags & TH_URG) && ti->ti_urp && + 8032c6c: 10800288 cmpgei r2,r2,10 + 8032c70: 10004e1e bne r2,zero,8032dac + * This is a kludge, but if we receive and accept + * random urgent pointers, we'll crash in + * soreceive. It's hard to imagine someone + * actually wanting to send this much urgent data. + */ + if (ti->ti_urp + so->so_rcv.sb_cc > SB_MAX) + 8032c74: e0bff017 ldw r2,-64(fp) + 8032c78: 1080098b ldhu r2,38(r2) + 8032c7c: 10ffffcc andi r3,r2,65535 + 8032c80: e0bffa17 ldw r2,-24(fp) + 8032c84: 10800a17 ldw r2,40(r2) + 8032c88: 1885883a add r2,r3,r2 + 8032c8c: 10900070 cmpltui r2,r2,16385 + 8032c90: 1000071e bne r2,zero,8032cb0 + { + ti->ti_urp = 0; /* XXX */ + 8032c94: e0bff017 ldw r2,-64(fp) + 8032c98: 1000098d sth zero,38(r2) + tiflags &= ~TH_URG; /* XXX */ + 8032c9c: e0fffb17 ldw r3,-20(fp) + 8032ca0: 00bff7c4 movi r2,-33 + 8032ca4: 1884703a and r2,r3,r2 + 8032ca8: e0bffb15 stw r2,-20(fp) + goto dodata; /* XXX */ + 8032cac: 00004d06 br 8032de4 + * of urgent data. We continue, however, + * to consider it to indicate the first octet + * of data past the urgent section + * as the original spec states. + */ + if (SEQ_GT(ti->ti_seq+ti->ti_urp, tp->rcv_up)) + 8032cb0: e0bff017 ldw r2,-64(fp) + 8032cb4: 10c00617 ldw r3,24(r2) + 8032cb8: e0bff017 ldw r2,-64(fp) + 8032cbc: 1080098b ldhu r2,38(r2) + 8032cc0: 10bfffcc andi r2,r2,65535 + 8032cc4: 1887883a add r3,r3,r2 + 8032cc8: e0bffc17 ldw r2,-16(fp) + 8032ccc: 10801717 ldw r2,92(r2) + 8032cd0: 1885c83a sub r2,r3,r2 + 8032cd4: 0080250e bge zero,r2,8032d6c + { + tp->rcv_up = ti->ti_seq + ti->ti_urp; + 8032cd8: e0bff017 ldw r2,-64(fp) + 8032cdc: 10c00617 ldw r3,24(r2) + 8032ce0: e0bff017 ldw r2,-64(fp) + 8032ce4: 1080098b ldhu r2,38(r2) + 8032ce8: 10bfffcc andi r2,r2,65535 + 8032cec: 1887883a add r3,r3,r2 + 8032cf0: e0bffc17 ldw r2,-16(fp) + 8032cf4: 10c01715 stw r3,92(r2) + so->so_oobmark = so->so_rcv.sb_cc + + 8032cf8: e0bffa17 ldw r2,-24(fp) + 8032cfc: 10c00a17 ldw r3,40(r2) + (tp->rcv_up - tp->rcv_nxt) - 1; + 8032d00: e0bffc17 ldw r2,-16(fp) + 8032d04: 11001717 ldw r4,92(r2) + 8032d08: e0bffc17 ldw r2,-16(fp) + 8032d0c: 10801617 ldw r2,88(r2) + 8032d10: 2085c83a sub r2,r4,r2 + so->so_oobmark = so->so_rcv.sb_cc + + 8032d14: 1885883a add r2,r3,r2 + (tp->rcv_up - tp->rcv_nxt) - 1; + 8032d18: 10ffffc4 addi r3,r2,-1 + so->so_oobmark = so->so_rcv.sb_cc + + 8032d1c: e0bffa17 ldw r2,-24(fp) + 8032d20: 10c01a15 stw r3,104(r2) + if (so->so_oobmark == 0) + 8032d24: e0bffa17 ldw r2,-24(fp) + 8032d28: 10801a17 ldw r2,104(r2) + 8032d2c: 1000061e bne r2,zero,8032d48 + so->so_state |= SS_RCVATMARK; + 8032d30: e0bffa17 ldw r2,-24(fp) + 8032d34: 1080088b ldhu r2,34(r2) + 8032d38: 10801014 ori r2,r2,64 + 8032d3c: 1007883a mov r3,r2 + 8032d40: e0bffa17 ldw r2,-24(fp) + 8032d44: 10c0088d sth r3,34(r2) + sohasoutofband(so); + 8032d48: e13ffa17 ldw r4,-24(fp) + 8032d4c: 802f12c0 call 802f12c + tp->t_oobflags &= ~(TCPOOB_HAVEDATA | TCPOOB_HADDATA); + 8032d50: e0bffc17 ldw r2,-16(fp) + 8032d54: 10c02403 ldbu r3,144(r2) + 8032d58: 00bfff04 movi r2,-4 + 8032d5c: 1884703a and r2,r3,r2 + 8032d60: 1007883a mov r3,r2 + 8032d64: e0bffc17 ldw r2,-16(fp) + 8032d68: 10c02405 stb r3,144(r2) + * Remove out of band data so doesn't get presented to user. + * This can happen independent of advancing the URG pointer, + * but if two URG's are pending at once, some out-of-band + * data may creep in... ick. + */ + if ( (ti->ti_urp <= ti->ti_len) + 8032d6c: e0bff017 ldw r2,-64(fp) + 8032d70: 1100098b ldhu r4,38(r2) + 8032d74: e0bff017 ldw r2,-64(fp) + 8032d78: 10c0028b ldhu r3,10(r2) + 8032d7c: 20bfffcc andi r2,r4,65535 + 8032d80: 18ffffcc andi r3,r3,65535 + 8032d84: 18801436 bltu r3,r2,8032dd8 +#ifdef SO_OOBINLINE + && (so->so_options & SO_OOBINLINE) == 0 + 8032d88: e0bffa17 ldw r2,-24(fp) + 8032d8c: 10800417 ldw r2,16(r2) + 8032d90: 1080400c andi r2,r2,256 + 8032d94: 1000101e bne r2,zero,8032dd8 +#endif + ) + { + tcp_pulloutofband(so, ti, m); + 8032d98: e1bfe417 ldw r6,-112(fp) + 8032d9c: e17ff017 ldw r5,-64(fp) + 8032da0: e13ffa17 ldw r4,-24(fp) + 8032da4: 80333ec0 call 80333ec + if ( (ti->ti_urp <= ti->ti_len) + 8032da8: 00000b06 br 8032dd8 + /* + * If no out of band data is expected, + * pull receive urgent pointer along + * with the receive window. + */ + if (SEQ_GT(tp->rcv_nxt, tp->rcv_up)) + 8032dac: e0bffc17 ldw r2,-16(fp) + 8032db0: 10c01617 ldw r3,88(r2) + 8032db4: e0bffc17 ldw r2,-16(fp) + 8032db8: 10801717 ldw r2,92(r2) + 8032dbc: 1885c83a sub r2,r3,r2 + 8032dc0: 0080070e bge zero,r2,8032de0 + tp->rcv_up = tp->rcv_nxt; + 8032dc4: e0bffc17 ldw r2,-16(fp) + 8032dc8: 10c01617 ldw r3,88(r2) + 8032dcc: e0bffc17 ldw r2,-16(fp) + 8032dd0: 10c01715 stw r3,92(r2) + 8032dd4: 00000306 br 8032de4 + if ( (ti->ti_urp <= ti->ti_len) + 8032dd8: 0001883a nop + 8032ddc: 00000106 br 8032de4 +dodata: /* XXX */ + 8032de0: 0001883a nop + * This process logically involves adjusting tp->rcv_wnd as data + * is presented to the user (this happens in tcp_usrreq.c, + * case PRU_RCVD). If a FIN has already been received on this + * connection then we just ignore the text. + */ + if ((ti->ti_len || (tiflags&TH_FIN)) && + 8032de4: e0bff017 ldw r2,-64(fp) + 8032de8: 1080028b ldhu r2,10(r2) + 8032dec: 10bfffcc andi r2,r2,65535 + 8032df0: 1000031e bne r2,zero,8032e00 + 8032df4: e0bffb17 ldw r2,-20(fp) + 8032df8: 1080004c andi r2,r2,1 + 8032dfc: 10005a26 beq r2,zero,8032f68 + TCPS_HAVERCVDFIN(tp->t_state) == 0) + 8032e00: e0bffc17 ldw r2,-16(fp) + 8032e04: 10800217 ldw r2,8(r2) + if ((ti->ti_len || (tiflags&TH_FIN)) && + 8032e08: 10800288 cmpgei r2,r2,10 + 8032e0c: 1000561e bne r2,zero,8032f68 + { + + /* Do the common segment reassembly case inline */ + if((ti->ti_seq == tp->rcv_nxt) && + 8032e10: e0bff017 ldw r2,-64(fp) + 8032e14: 10c00617 ldw r3,24(r2) + 8032e18: e0bffc17 ldw r2,-16(fp) + 8032e1c: 10801617 ldw r2,88(r2) + 8032e20: 1880331e bne r3,r2,8032ef0 + (tp->seg_next == (struct tcpiphdr *)(tp) ) && + 8032e24: e0bffc17 ldw r2,-16(fp) + 8032e28: 10800017 ldw r2,0(r2) + if((ti->ti_seq == tp->rcv_nxt) && + 8032e2c: e0fffc17 ldw r3,-16(fp) + 8032e30: 18802f1e bne r3,r2,8032ef0 + (tp->t_state == TCPS_ESTABLISHED)) + 8032e34: e0bffc17 ldw r2,-16(fp) + 8032e38: 10800217 ldw r2,8(r2) + (tp->seg_next == (struct tcpiphdr *)(tp) ) && + 8032e3c: 10800118 cmpnei r2,r2,4 + 8032e40: 10002b1e bne r2,zero,8032ef0 + else + { + tp->t_flags |= TF_ACKNOW; + } +#else /* not DO_DELAY_ACKS */ + tp->t_flags |= TF_ACKNOW; + 8032e44: e0bffc17 ldw r2,-16(fp) + 8032e48: 10800b0b ldhu r2,44(r2) + 8032e4c: 10800054 ori r2,r2,1 + 8032e50: 1007883a mov r3,r2 + 8032e54: e0bffc17 ldw r2,-16(fp) + 8032e58: 10c00b0d sth r3,44(r2) +#endif /* DO_DELAY_ACKS */ + + tp->rcv_nxt += ti->ti_len; + 8032e5c: e0bffc17 ldw r2,-16(fp) + 8032e60: 10c01617 ldw r3,88(r2) + 8032e64: e0bff017 ldw r2,-64(fp) + 8032e68: 1080028b ldhu r2,10(r2) + 8032e6c: 10bfffcc andi r2,r2,65535 + 8032e70: 1887883a add r3,r3,r2 + 8032e74: e0bffc17 ldw r2,-16(fp) + 8032e78: 10c01615 stw r3,88(r2) + tiflags = ti->ti_flags & TH_FIN; + 8032e7c: e0bff017 ldw r2,-64(fp) + 8032e80: 10800843 ldbu r2,33(r2) + 8032e84: 10803fcc andi r2,r2,255 + 8032e88: 1080004c andi r2,r2,1 + 8032e8c: e0bffb15 stw r2,-20(fp) + tcpstat.tcps_rcvpack++; + 8032e90: 008201b4 movhi r2,2054 + 8032e94: 10b8be17 ldw r2,-7432(r2) + 8032e98: 10c00044 addi r3,r2,1 + 8032e9c: 008201b4 movhi r2,2054 + 8032ea0: 10f8be15 stw r3,-7432(r2) + tcpstat.tcps_rcvbyte += ti->ti_len; + 8032ea4: 008201b4 movhi r2,2054 + 8032ea8: 10f8bf17 ldw r3,-7428(r2) + 8032eac: e0bff017 ldw r2,-64(fp) + 8032eb0: 1080028b ldhu r2,10(r2) + 8032eb4: 10bfffcc andi r2,r2,65535 + 8032eb8: 1887883a add r3,r3,r2 + 8032ebc: 008201b4 movhi r2,2054 + 8032ec0: 10f8bf15 stw r3,-7428(r2) + sbappend(&so->so_rcv, (m)); + 8032ec4: e0bffa17 ldw r2,-24(fp) + 8032ec8: 10800a04 addi r2,r2,40 + 8032ecc: e17fe417 ldw r5,-112(fp) + 8032ed0: 1009883a mov r4,r2 + 8032ed4: 802fafc0 call 802fafc + sorwakeup(so); + 8032ed8: e0bffa17 ldw r2,-24(fp) + 8032edc: 10800a04 addi r2,r2,40 + 8032ee0: 100b883a mov r5,r2 + 8032ee4: e13ffa17 ldw r4,-24(fp) + 8032ee8: 802f94c0 call 802f94c + 8032eec: 00000b06 br 8032f1c +#endif /* TCP_SACK */ + } + else /* received out of sequence segment */ + { + /* Drop it in the reassmbly queue */ + tiflags = tcp_reass(tp, ti, m); + 8032ef0: e1bfe417 ldw r6,-112(fp) + 8032ef4: e17ff017 ldw r5,-64(fp) + 8032ef8: e13ffc17 ldw r4,-16(fp) + 8032efc: 8030c600 call 8030c60 + 8032f00: e0bffb15 stw r2,-20(fp) + tp->t_flags |= TF_ACKNOW; + 8032f04: e0bffc17 ldw r2,-16(fp) + 8032f08: 10800b0b ldhu r2,44(r2) + 8032f0c: 10800054 ori r2,r2,1 + 8032f10: 1007883a mov r3,r2 + 8032f14: e0bffc17 ldw r2,-16(fp) + 8032f18: 10c00b0d sth r3,44(r2) + /* + * Note the amount of data that peer has sent into + * our window, in order to estimate the sender's + * buffer size. + */ + len = (int)(so->so_rcv.sb_hiwat - (tp->rcv_adv - tp->rcv_nxt)); + 8032f1c: e0bffa17 ldw r2,-24(fp) + 8032f20: 10c00b17 ldw r3,44(r2) + 8032f24: e0bffc17 ldw r2,-16(fp) + 8032f28: 11001617 ldw r4,88(r2) + 8032f2c: e0bffc17 ldw r2,-16(fp) + 8032f30: 10801917 ldw r2,100(r2) + 8032f34: 2085c83a sub r2,r4,r2 + 8032f38: 1885883a add r2,r3,r2 + 8032f3c: e0bfe615 stw r2,-104(fp) + if (len > (int)tp->max_rcvd) + 8032f40: e0bffc17 ldw r2,-16(fp) + 8032f44: 10802217 ldw r2,136(r2) + 8032f48: 1007883a mov r3,r2 + 8032f4c: e0bfe617 ldw r2,-104(fp) + 8032f50: 18800b0e bge r3,r2,8032f80 + tp->max_rcvd = (u_short)len; + 8032f54: e0bfe617 ldw r2,-104(fp) + 8032f58: 10ffffcc andi r3,r2,65535 + 8032f5c: e0bffc17 ldw r2,-16(fp) + 8032f60: 10c02215 stw r3,136(r2) + if (len > (int)tp->max_rcvd) + 8032f64: 00000606 br 8032f80 + } +#endif /* TCP_ZEROCOPY */ + } + else + { + m_freem(m); + 8032f68: e13fe417 ldw r4,-112(fp) + 8032f6c: 8029cfc0 call 8029cfc + tiflags &= ~TH_FIN; + 8032f70: e0fffb17 ldw r3,-20(fp) + 8032f74: 00bfff84 movi r2,-2 + 8032f78: 1884703a and r2,r3,r2 + 8032f7c: e0bffb15 stw r2,-20(fp) + + /* + * If FIN is received ACK the FIN and let the user know + * that the connection is closing. + */ + if (tiflags & TH_FIN) + 8032f80: e0bffb17 ldw r2,-20(fp) + 8032f84: 1080004c andi r2,r2,1 + 8032f88: 10003e26 beq r2,zero,8033084 + { + if (TCPS_HAVERCVDFIN(tp->t_state) == 0) + 8032f8c: e0bffc17 ldw r2,-16(fp) + 8032f90: 10800217 ldw r2,8(r2) + 8032f94: 10800288 cmpgei r2,r2,10 + 8032f98: 10000d1e bne r2,zero,8032fd0 + { + socantrcvmore(so); + 8032f9c: e13ffa17 ldw r4,-24(fp) + 8032fa0: 802f84c0 call 802f84c + tp->t_flags |= TF_ACKNOW; + 8032fa4: e0bffc17 ldw r2,-16(fp) + 8032fa8: 10800b0b ldhu r2,44(r2) + 8032fac: 10800054 ori r2,r2,1 + 8032fb0: 1007883a mov r3,r2 + 8032fb4: e0bffc17 ldw r2,-16(fp) + 8032fb8: 10c00b0d sth r3,44(r2) + tp->rcv_nxt++; + 8032fbc: e0bffc17 ldw r2,-16(fp) + 8032fc0: 10801617 ldw r2,88(r2) + 8032fc4: 10c00044 addi r3,r2,1 + 8032fc8: e0bffc17 ldw r2,-16(fp) + 8032fcc: 10c01615 stw r3,88(r2) + } + switch (tp->t_state) + 8032fd0: e0bffc17 ldw r2,-16(fp) + 8032fd4: 10800217 ldw r2,8(r2) + 8032fd8: 10bfff44 addi r2,r2,-3 + 8032fdc: 10c00228 cmpgeui r3,r2,8 + 8032fe0: 1800291e bne r3,zero,8033088 + 8032fe4: 100690ba slli r3,r2,2 + 8032fe8: 008200f4 movhi r2,2051 + 8032fec: 1885883a add r2,r3,r2 + 8032ff0: 108bfe17 ldw r2,12280(r2) + 8032ff4: 1000683a jmp r2 + 8032ff8: 08033018 cmpnei zero,at,3264 + 8032ffc: 08033018 cmpnei zero,at,3264 + 8033000: 08033088 cmpgei zero,at,3266 + 8033004: 08033028 cmpgeui zero,at,3264 + 8033008: 08033088 cmpgei zero,at,3266 + 803300c: 08033088 cmpgei zero,at,3266 + 8033010: 08033038 rdprs zero,at,3264 + 8033014: 0803306c andhi zero,at,3265 + * In SYN_RECEIVED and ESTABLISHED STATES + * enter the CLOSE_WAIT state. + */ + case TCPS_SYN_RECEIVED: + case TCPS_ESTABLISHED: + tp->t_state = TCPS_CLOSE_WAIT; + 8033018: e0bffc17 ldw r2,-16(fp) + 803301c: 00c00144 movi r3,5 + 8033020: 10c00215 stw r3,8(r2) + break; + 8033024: 00001806 br 8033088 + /* + * If still in FIN_WAIT_1 STATE FIN has not been acked so + * enter the CLOSING state. + */ + case TCPS_FIN_WAIT_1: + tp->t_state = TCPS_CLOSING; + 8033028: e0bffc17 ldw r2,-16(fp) + 803302c: 00c001c4 movi r3,7 + 8033030: 10c00215 stw r3,8(r2) + break; + 8033034: 00001406 br 8033088 + * In FIN_WAIT_2 state enter the TIME_WAIT state, + * starting the time-wait timer, turning off the other + * standard timers. + */ + case TCPS_FIN_WAIT_2: + tp->t_state = TCPS_TIME_WAIT; + 8033038: e0bffc17 ldw r2,-16(fp) + 803303c: 00c00284 movi r3,10 + 8033040: 10c00215 stw r3,8(r2) + tcp_canceltimers(tp); + 8033044: e13ffc17 ldw r4,-16(fp) + 8033048: 80355640 call 8035564 + tp->t_timer[TCPT_2MSL] = 2 * TCPTV_MSL; + 803304c: d0a01b17 ldw r2,-32660(gp) + 8033050: 1085883a add r2,r2,r2 + 8033054: 1007883a mov r3,r2 + 8033058: e0bffc17 ldw r2,-16(fp) + 803305c: 10c00615 stw r3,24(r2) + soisdisconnected(so); + 8033060: e13ffa17 ldw r4,-24(fp) + 8033064: 802f3840 call 802f384 + break; + 8033068: 00000706 br 8033088 + + /* + * In TIME_WAIT state restart the 2 MSL time_wait timer. + */ + case TCPS_TIME_WAIT: + tp->t_timer[TCPT_2MSL] = 2 * TCPTV_MSL; + 803306c: d0a01b17 ldw r2,-32660(gp) + 8033070: 1085883a add r2,r2,r2 + 8033074: 1007883a mov r3,r2 + 8033078: e0bffc17 ldw r2,-16(fp) + 803307c: 10c00615 stw r3,24(r2) + break; + 8033080: 00000106 br 8033088 + } + } + 8033084: 0001883a nop + ostate, tp, &tcp_saveti); +#endif + /* + * Return any desired output. + */ + if (needoutput || (tp->t_flags & TF_ACKNOW)) + 8033088: e0bff717 ldw r2,-36(fp) + 803308c: 1000051e bne r2,zero,80330a4 + 8033090: e0bffc17 ldw r2,-16(fp) + 8033094: 10800b0b ldhu r2,44(r2) + 8033098: 10bfffcc andi r2,r2,65535 + 803309c: 1080004c andi r2,r2,1 + 80330a0: 10006626 beq r2,zero,803323c + (void) tcp_output(tp); + 80330a4: e13ffc17 ldw r4,-16(fp) + 80330a8: 80338940 call 8033894 + return; + 80330ac: 00006306 br 803323c + goto dropafterack; + 80330b0: 0001883a nop + 80330b4: 00000106 br 80330bc + goto dropafterack; + 80330b8: 0001883a nop +dropafterack: + /* + * Generate an ACK dropping incoming segment if it occupies + * sequence space, where the ACK reflects our state. + */ + if (tiflags & TH_RST) + 80330bc: e0bffb17 ldw r2,-20(fp) + 80330c0: 1080010c andi r2,r2,4 + 80330c4: 10000326 beq r2,zero,80330d4 + GOTO_DROP; + 80330c8: 0081a904 movi r2,1700 + 80330cc: d0a08715 stw r2,-32228(gp) + 80330d0: 00004a06 br 80331fc + m_freem (m); + 80330d4: e13fe417 ldw r4,-112(fp) + 80330d8: 8029cfc0 call 8029cfc + tp->t_flags |= TF_ACKNOW; + 80330dc: e0bffc17 ldw r2,-16(fp) + 80330e0: 10800b0b ldhu r2,44(r2) + 80330e4: 10800054 ori r2,r2,1 + 80330e8: 1007883a mov r3,r2 + 80330ec: e0bffc17 ldw r2,-16(fp) + 80330f0: 10c00b0d sth r3,44(r2) + (void) tcp_output (tp); + 80330f4: e13ffc17 ldw r4,-16(fp) + 80330f8: 80338940 call 8033894 + return; + 80330fc: 00005406 br 8033250 + +dropwithreset: + TCP_MIB_INC(tcpInErrs); /* keep MIB stats */ + 8033100: 008201b4 movhi r2,2054 + 8033104: 10b88317 ldw r2,-7668(r2) + 8033108: 10c00044 addi r3,r2,1 + 803310c: 008201b4 movhi r2,2054 + 8033110: 10f88315 stw r3,-7668(r2) + if (om) + 8033114: e0bffd17 ldw r2,-12(fp) + 8033118: 10000326 beq r2,zero,8033128 + { + (void) m_free(om); + 803311c: e13ffd17 ldw r4,-12(fp) + 8033120: 8029bf80 call 8029bf8 + om = 0; + 8033124: e03ffd15 stw zero,-12(fp) + } + + /* Don't reset resets */ + if (tiflags & TH_RST) + 8033128: e0bffb17 ldw r2,-20(fp) + 803312c: 1080010c andi r2,r2,4 + 8033130: 10000326 beq r2,zero,8033140 + GOTO_DROP; + 8033134: 0081ad04 movi r2,1716 + 8033138: d0a08715 stw r2,-32228(gp) + 803313c: 00002f06 br 80331fc + * Generate a RST, dropping incoming segment. + * Make ACK acceptable to originator of segment. + * Don't bother to respond if destination was broadcast. + */ +#ifdef IP_V4 + if (in_broadcast(ti->ti_dst.s_addr)) + 8033140: e0bff017 ldw r2,-64(fp) + 8033144: 10800417 ldw r2,16(r2) + 8033148: 1009883a mov r4,r2 + 803314c: 802abe00 call 802abe0 + 8033150: 10000326 beq r2,zero,8033160 + GOTO_DROP; + 8033154: 0081af44 movi r2,1725 + 8033158: d0a08715 stw r2,-32228(gp) + 803315c: 00002706 br 80331fc + IP6CPY(&(m->pkt->ip6_hdr->ip_src), &ip6_src); + IP6CPY(&(m->pkt->ip6_hdr->ip_dest), &ip6_dst); + } +#endif /* IP_V6 */ + + if (tiflags & TH_ACK) + 8033160: e0bffb17 ldw r2,-20(fp) + 8033164: 1080040c andi r2,r2,16 + 8033168: 10000c26 beq r2,zero,803319c + tcp_respond (tp, ti, (tcp_seq)0, ti->ti_ack, TH_RST, m); + 803316c: e0bff017 ldw r2,-64(fp) + 8033170: 10c00717 ldw r3,28(r2) + 8033174: e0bfe417 ldw r2,-112(fp) + 8033178: d8800115 stw r2,4(sp) + 803317c: 00800104 movi r2,4 + 8033180: d8800015 stw r2,0(sp) + 8033184: 180f883a mov r7,r3 + 8033188: 000d883a mov r6,zero + 803318c: e17ff017 ldw r5,-64(fp) + 8033190: e13ffc17 ldw r4,-16(fp) + 8033194: 8034b480 call 8034b48 + 8033198: 00001306 br 80331e8 + else + { + if (tiflags & TH_SYN) + 803319c: e0bffb17 ldw r2,-20(fp) + 80331a0: 1080008c andi r2,r2,2 + 80331a4: 10000526 beq r2,zero,80331bc + ti->ti_seq++; + 80331a8: e0bff017 ldw r2,-64(fp) + 80331ac: 10800617 ldw r2,24(r2) + 80331b0: 10c00044 addi r3,r2,1 + 80331b4: e0bff017 ldw r2,-64(fp) + 80331b8: 10c00615 stw r3,24(r2) + tcp_respond(tp, ti, ti->ti_seq, (tcp_seq)0, TH_RST|TH_ACK, m); + 80331bc: e0bff017 ldw r2,-64(fp) + 80331c0: 10c00617 ldw r3,24(r2) + 80331c4: e0bfe417 ldw r2,-112(fp) + 80331c8: d8800115 stw r2,4(sp) + 80331cc: 00800504 movi r2,20 + 80331d0: d8800015 stw r2,0(sp) + 80331d4: 000f883a mov r7,zero + 80331d8: 180d883a mov r6,r3 + 80331dc: e17ff017 ldw r5,-64(fp) + 80331e0: e13ffc17 ldw r4,-16(fp) + 80331e4: 8034b480 call 8034b48 + } + /* destroy temporarily created socket */ + if (dropsocket) + 80331e8: e0bff617 ldw r2,-40(fp) + 80331ec: 10001526 beq r2,zero,8033244 + (void) soabort(so); + 80331f0: e13ffa17 ldw r4,-24(fp) + 80331f4: 802d6fc0 call 802d6fc + return; + 80331f8: 00001206 br 8033244 + +drop: + if (om) + 80331fc: e0bffd17 ldw r2,-12(fp) + 8033200: 10000226 beq r2,zero,803320c + (void) m_free(om); + 8033204: e13ffd17 ldw r4,-12(fp) + 8033208: 8029bf80 call 8029bf8 +#ifdef DO_TCPTRACE + if (tp && (tp->t_inpcb->inp_socket->so_options & SO_DEBUG)) + tcp_trace("drop: state %d, tcpcb: %x, saveti: %x", + ostate, tp, &tcp_saveti); +#endif + m_freem(m); + 803320c: e13fe417 ldw r4,-112(fp) + 8033210: 8029cfc0 call 8029cfc + /* destroy temporarily created socket */ + if (dropsocket) + 8033214: e0bff617 ldw r2,-40(fp) + 8033218: 10000c26 beq r2,zero,803324c + (void) soabort(so); + 803321c: e13ffa17 ldw r4,-24(fp) + 8033220: 802d6fc0 call 802d6fc + return; + 8033224: 0001883a nop + 8033228: 00000806 br 803324c + return; + 803322c: 0001883a nop + 8033230: 00000706 br 8033250 + return; + 8033234: 0001883a nop + 8033238: 00000506 br 8033250 + return; + 803323c: 0001883a nop + 8033240: 00000306 br 8033250 + return; + 8033244: 0001883a nop + 8033248: 00000106 br 8033250 + return; + 803324c: 0001883a nop +} + 8033250: e037883a mov sp,fp + 8033254: dfc00117 ldw ra,4(sp) + 8033258: df000017 ldw fp,0(sp) + 803325c: dec00204 addi sp,sp,8 + 8033260: f800283a ret + +08033264 : + +void +tcp_dooptions(struct tcpcb * tp, + struct mbuf * om, + struct tcpiphdr * ti) +{ + 8033264: defff504 addi sp,sp,-44 + 8033268: dfc00a15 stw ra,40(sp) + 803326c: df000915 stw fp,36(sp) + 8033270: df000904 addi fp,sp,36 + 8033274: e13ff915 stw r4,-28(fp) + 8033278: e17ff815 stw r5,-32(fp) + 803327c: e1bff715 stw r6,-36(fp) + u_char * cp; /* pointer into option buffer */ + int opt; /* current option code */ + int optlen; /* length of current option */ + int cnt; /* byte count left in header */ + struct socket * so = tp->t_inpcb->inp_socket; + 8033280: e0bff917 ldw r2,-28(fp) + 8033284: 10800d17 ldw r2,52(r2) + 8033288: 10800817 ldw r2,32(r2) + 803328c: e0bffc15 stw r2,-16(fp) +#ifdef TCP_TIMESTAMP + int gotstamp = FALSE; /* TRUE if we got a timestamp */ +#endif /* TCP_TIMESTAMP */ + + + cp = mtod(om, u_char *); + 8033290: e0bff817 ldw r2,-32(fp) + 8033294: 10800317 ldw r2,12(r2) + 8033298: e0bfff15 stw r2,-4(fp) + cnt = om->m_len; + 803329c: e0bff817 ldw r2,-32(fp) + 80332a0: 10800217 ldw r2,8(r2) + 80332a4: e0bffd15 stw r2,-12(fp) + for (; cnt > 0; cnt -= optlen, cp += optlen) + 80332a8: 00004206 br 80333b4 + { + opt = cp[0]; + 80332ac: e0bfff17 ldw r2,-4(fp) + 80332b0: 10800003 ldbu r2,0(r2) + 80332b4: 10803fcc andi r2,r2,255 + 80332b8: e0bffb15 stw r2,-20(fp) + if (opt == TCPOPT_EOL) + 80332bc: e0bffb17 ldw r2,-20(fp) + 80332c0: 10003f26 beq r2,zero,80333c0 + break; + if (opt == TCPOPT_NOP) + 80332c4: e0bffb17 ldw r2,-20(fp) + 80332c8: 10800058 cmpnei r2,r2,1 + 80332cc: 1000031e bne r2,zero,80332dc + optlen = 1; + 80332d0: 00800044 movi r2,1 + 80332d4: e0bffe15 stw r2,-8(fp) + 80332d8: 00000706 br 80332f8 + else + { + optlen = cp[1]; + 80332dc: e0bfff17 ldw r2,-4(fp) + 80332e0: 10800044 addi r2,r2,1 + 80332e4: 10800003 ldbu r2,0(r2) + 80332e8: 10803fcc andi r2,r2,255 + 80332ec: e0bffe15 stw r2,-8(fp) + if (optlen <= 0) + 80332f0: e0bffe17 ldw r2,-8(fp) + 80332f4: 0080340e bge zero,r2,80333c8 + break; + } + + switch (opt) + 80332f8: e0bffb17 ldw r2,-20(fp) + 80332fc: 10800098 cmpnei r2,r2,2 + 8033300: 10001f1e bne r2,zero,8033380 + { + case TCPOPT_MAXSEG: + { + u_short mssval; + if (optlen != 4) + 8033304: e0bffe17 ldw r2,-8(fp) + 8033308: 10800120 cmpeqi r2,r2,4 + 803330c: 10001e26 beq r2,zero,8033388 + continue; + if (!(ti->ti_flags & TH_SYN)) /* MSS only on SYN */ + 8033310: e0bff717 ldw r2,-36(fp) + 8033314: 10800843 ldbu r2,33(r2) + 8033318: 10803fcc andi r2,r2,255 + 803331c: 1080008c andi r2,r2,2 + 8033320: 10001b26 beq r2,zero,8033390 + continue; + mssval = *(u_short *)(cp + 2); + 8033324: e0bfff17 ldw r2,-4(fp) + 8033328: 1080008b ldhu r2,2(r2) + 803332c: e0bffa8d sth r2,-22(fp) + mssval = ntohs(mssval); + 8033330: e0bffa8b ldhu r2,-22(fp) + 8033334: 1004d23a srli r2,r2,8 + 8033338: 1007883a mov r3,r2 + 803333c: e0bffa8b ldhu r2,-22(fp) + 8033340: 1004923a slli r2,r2,8 + 8033344: 1884b03a or r2,r3,r2 + 8033348: e0bffa8d sth r2,-22(fp) + tp->t_maxseg = (u_short)MIN(mssval, (u_short)tcp_mss(so)); + 803334c: e13ffc17 ldw r4,-16(fp) + 8033350: 803379c0 call 803379c + 8033354: 1007883a mov r3,r2 + 8033358: e0bffa8b ldhu r2,-22(fp) + 803335c: 18ffffcc andi r3,r3,65535 + 8033360: 1880032e bgeu r3,r2,8033370 + 8033364: e13ffc17 ldw r4,-16(fp) + 8033368: 803379c0 call 803379c + 803336c: 00000106 br 8033374 + 8033370: e0bffa8b ldhu r2,-22(fp) + 8033374: e0fff917 ldw r3,-28(fp) + 8033378: 18800a0d sth r2,40(r3) + break; + 803337c: 00000506 br 8033394 + } + break; +#endif /* TCP_TIMESTAMP */ + + default: + break; + 8033380: 0001883a nop + 8033384: 00000306 br 8033394 + continue; + 8033388: 0001883a nop + 803338c: 00000106 br 8033394 + continue; + 8033390: 0001883a nop + for (; cnt > 0; cnt -= optlen, cp += optlen) + 8033394: e0fffd17 ldw r3,-12(fp) + 8033398: e0bffe17 ldw r2,-8(fp) + 803339c: 1885c83a sub r2,r3,r2 + 80333a0: e0bffd15 stw r2,-12(fp) + 80333a4: e0bffe17 ldw r2,-8(fp) + 80333a8: e0ffff17 ldw r3,-4(fp) + 80333ac: 1885883a add r2,r3,r2 + 80333b0: e0bfff15 stw r2,-4(fp) + 80333b4: e0bffd17 ldw r2,-12(fp) + 80333b8: 00bfbc16 blt zero,r2,80332ac + 80333bc: 00000306 br 80333cc + break; + 80333c0: 0001883a nop + 80333c4: 00000106 br 80333cc + break; + 80333c8: 0001883a nop + } + } + (void) m_free(om); + 80333cc: e13ff817 ldw r4,-32(fp) + 80333d0: 8029bf80 call 8029bf8 + if(!gotstamp) + tp->t_flags &= ~TF_TIMESTAMP; + } +#endif /* TCP_TIMESTAMP */ + + return; + 80333d4: 0001883a nop +} + 80333d8: e037883a mov sp,fp + 80333dc: dfc00117 ldw ra,4(sp) + 80333e0: df000017 ldw fp,0(sp) + 80333e4: dec00204 addi sp,sp,8 + 80333e8: f800283a ret + +080333ec : + +void +tcp_pulloutofband(struct socket * so, + struct tcpiphdr * ti, + struct mbuf * m) +{ + 80333ec: defff804 addi sp,sp,-32 + 80333f0: dfc00715 stw ra,28(sp) + 80333f4: df000615 stw fp,24(sp) + 80333f8: df000604 addi fp,sp,24 + 80333fc: e13ffc15 stw r4,-16(fp) + 8033400: e17ffb15 stw r5,-20(fp) + 8033404: e1bffa15 stw r6,-24(fp) + int cnt = ti->ti_urp - 1; + 8033408: e0bffb17 ldw r2,-20(fp) + 803340c: 1080098b ldhu r2,38(r2) + 8033410: 10bfffcc andi r2,r2,65535 + 8033414: 10bfffc4 addi r2,r2,-1 + 8033418: e0bfff15 stw r2,-4(fp) + + /**m = dtom(ti);**/ + while (cnt >= 0) + 803341c: 00003206 br 80334e8 + { + if (m->m_len > (unsigned)cnt) + 8033420: e0bffa17 ldw r2,-24(fp) + 8033424: 10800217 ldw r2,8(r2) + 8033428: e0ffff17 ldw r3,-4(fp) + 803342c: 1880242e bgeu r3,r2,80334c0 + { + char * cp = mtod(m, char *) + cnt; + 8033430: e0bffa17 ldw r2,-24(fp) + 8033434: 10c00317 ldw r3,12(r2) + 8033438: e0bfff17 ldw r2,-4(fp) + 803343c: 1885883a add r2,r3,r2 + 8033440: e0bffe15 stw r2,-8(fp) + struct tcpcb * tp = sototcpcb(so); + 8033444: e0bffc17 ldw r2,-16(fp) + 8033448: 10800117 ldw r2,4(r2) + 803344c: 10800917 ldw r2,36(r2) + 8033450: e0bffd15 stw r2,-12(fp) + + tp->t_iobc = *cp; + 8033454: e0bffe17 ldw r2,-8(fp) + 8033458: 10c00003 ldbu r3,0(r2) + 803345c: e0bffd17 ldw r2,-12(fp) + 8033460: 10c02445 stb r3,145(r2) + tp->t_oobflags |= TCPOOB_HAVEDATA; + 8033464: e0bffd17 ldw r2,-12(fp) + 8033468: 10802403 ldbu r2,144(r2) + 803346c: 10800054 ori r2,r2,1 + 8033470: 1007883a mov r3,r2 + 8033474: e0bffd17 ldw r2,-12(fp) + 8033478: 10c02405 stb r3,144(r2) + MEMCPY(cp, cp+1, (unsigned)(m->m_len - cnt - 1)); + 803347c: e0bffe17 ldw r2,-8(fp) + 8033480: 11000044 addi r4,r2,1 + 8033484: e0bffa17 ldw r2,-24(fp) + 8033488: 10c00217 ldw r3,8(r2) + 803348c: e0bfff17 ldw r2,-4(fp) + 8033490: 1885c83a sub r2,r3,r2 + 8033494: 10bfffc4 addi r2,r2,-1 + 8033498: 100d883a mov r6,r2 + 803349c: 200b883a mov r5,r4 + 80334a0: e13ffe17 ldw r4,-8(fp) + 80334a4: 80086b80 call 80086b8 + m->m_len--; + 80334a8: e0bffa17 ldw r2,-24(fp) + 80334ac: 10800217 ldw r2,8(r2) + 80334b0: 10ffffc4 addi r3,r2,-1 + 80334b4: e0bffa17 ldw r2,-24(fp) + 80334b8: 10c00215 stw r3,8(r2) + return; + 80334bc: 00001106 br 8033504 + } + cnt -= m->m_len; + 80334c0: e0ffff17 ldw r3,-4(fp) + 80334c4: e0bffa17 ldw r2,-24(fp) + 80334c8: 10800217 ldw r2,8(r2) + 80334cc: 1885c83a sub r2,r3,r2 + 80334d0: e0bfff15 stw r2,-4(fp) + m = m->m_next; + 80334d4: e0bffa17 ldw r2,-24(fp) + 80334d8: 10800617 ldw r2,24(r2) + 80334dc: e0bffa15 stw r2,-24(fp) + if (m == 0) + 80334e0: e0bffa17 ldw r2,-24(fp) + 80334e4: 10000326 beq r2,zero,80334f4 + while (cnt >= 0) + 80334e8: e0bfff17 ldw r2,-4(fp) + 80334ec: 103fcc0e bge r2,zero,8033420 + 80334f0: 00000106 br 80334f8 + break; + 80334f4: 0001883a nop + } + panic("tcp_pulloutofband"); + 80334f8: 01020174 movhi r4,2053 + 80334fc: 212a9d04 addi r4,r4,-21900 + 8033500: 80271780 call 8027178 +} + 8033504: e037883a mov sp,fp + 8033508: dfc00117 ldw ra,4(sp) + 803350c: df000017 ldw fp,0(sp) + 8033510: dec00204 addi sp,sp,8 + 8033514: f800283a ret + +08033518 : + * RETURNS: + */ + +void +tcp_xmit_timer(struct tcpcb * tp) +{ + 8033518: defffb04 addi sp,sp,-20 + 803351c: dfc00415 stw ra,16(sp) + 8033520: df000315 stw fp,12(sp) + 8033524: df000304 addi fp,sp,12 + 8033528: e13ffd15 stw r4,-12(fp) + int delta; + int rtt; + +#ifdef NPDEBUG + if(tp->t_rttick == 0){ dtrap(); return; } + 803352c: e0bffd17 ldw r2,-12(fp) + 8033530: 10801e17 ldw r2,120(r2) + 8033534: 1000021e bne r2,zero,8033540 + 8033538: 8028cd40 call 8028cd4 + 803353c: 00008006 br 8033740 +#endif + + tcpstat.tcps_rttupdated++; + 8033540: 008201b4 movhi r2,2054 + 8033544: 10b8ab17 ldw r2,-7508(r2) + 8033548: 10c00044 addi r3,r2,1 + 803354c: 008201b4 movhi r2,2054 + 8033550: 10f8ab15 stw r3,-7508(r2) + + /* get this rtt. Convert from cticks to TCP slow ticks */ + rtt = (int)((cticks - tp->t_rttick) / (TPS/2)); + 8033554: d0e07d17 ldw r3,-32268(gp) + 8033558: e0bffd17 ldw r2,-12(fp) + 803355c: 10801e17 ldw r2,120(r2) + 8033560: 1885c83a sub r2,r3,r2 + 8033564: 01400c84 movi r5,50 + 8033568: 1009883a mov r4,r2 + 803356c: 800cff80 call 800cff8 <__udivsi3> + 8033570: e0bffe15 stw r2,-8(fp) + if(tp->t_srtt != 0) + 8033574: e0bffd17 ldw r2,-12(fp) + 8033578: 10802017 ldw r2,128(r2) + 803357c: 10004426 beq r2,zero,8033690 + { + if(rtt == 0) /* fast path for small round trip */ + 8033580: e0bffe17 ldw r2,-8(fp) + 8033584: 1000131e bne r2,zero,80335d4 + { + /* if either the rtt or varience is over 1, reduce it. */ + if(tp->t_srtt > 1) + 8033588: e0bffd17 ldw r2,-12(fp) + 803358c: 10802017 ldw r2,128(r2) + 8033590: 10800090 cmplti r2,r2,2 + 8033594: 1000051e bne r2,zero,80335ac + tp->t_srtt--; + 8033598: e0bffd17 ldw r2,-12(fp) + 803359c: 10802017 ldw r2,128(r2) + 80335a0: 10ffffc4 addi r3,r2,-1 + 80335a4: e0bffd17 ldw r2,-12(fp) + 80335a8: 10c02015 stw r3,128(r2) + if(tp->t_rttvar > 1) + 80335ac: e0bffd17 ldw r2,-12(fp) + 80335b0: 10802117 ldw r2,132(r2) + 80335b4: 10800090 cmplti r2,r2,2 + 80335b8: 1000421e bne r2,zero,80336c4 + tp->t_rttvar--; + 80335bc: e0bffd17 ldw r2,-12(fp) + 80335c0: 10802117 ldw r2,132(r2) + 80335c4: 10ffffc4 addi r3,r2,-1 + 80335c8: e0bffd17 ldw r2,-12(fp) + 80335cc: 10c02115 stw r3,132(r2) + 80335d0: 00003c06 br 80336c4 + * The following magic is equivalent + * to the smoothing algorithm in rfc793 + * with an alpha of .875 + * (srtt = rtt/8 + srtt*7/8 in fixed point). + */ + delta = ((rtt - 1) << 2) - (int)(tp->t_srtt >> 3); + 80335d4: e0bffe17 ldw r2,-8(fp) + 80335d8: 10bfffc4 addi r2,r2,-1 + 80335dc: 100690ba slli r3,r2,2 + 80335e0: e0bffd17 ldw r2,-12(fp) + 80335e4: 10802017 ldw r2,128(r2) + 80335e8: 1005d0fa srai r2,r2,3 + 80335ec: 1885c83a sub r2,r3,r2 + 80335f0: e0bfff15 stw r2,-4(fp) + if ((tp->t_srtt += delta) <= 0) + 80335f4: e0bffd17 ldw r2,-12(fp) + 80335f8: 10c02017 ldw r3,128(r2) + 80335fc: e0bfff17 ldw r2,-4(fp) + 8033600: 1887883a add r3,r3,r2 + 8033604: e0bffd17 ldw r2,-12(fp) + 8033608: 10c02015 stw r3,128(r2) + 803360c: e0bffd17 ldw r2,-12(fp) + 8033610: 10802017 ldw r2,128(r2) + 8033614: 00800316 blt zero,r2,8033624 + tp->t_srtt = 1; + 8033618: e0bffd17 ldw r2,-12(fp) + 803361c: 00c00044 movi r3,1 + 8033620: 10c02015 stw r3,128(r2) + * (scaled by 4). The following is equivalent + * to rfc793 smoothing with an alpha of .75 + * (rttvar = rttvar*3/4 + |delta| / 4). + * This replaces rfc793's wired-in beta. + */ + if (delta < 0) + 8033624: e0bfff17 ldw r2,-4(fp) + 8033628: 1000030e bge r2,zero,8033638 + delta = -delta; + 803362c: e0bfff17 ldw r2,-4(fp) + 8033630: 0085c83a sub r2,zero,r2 + 8033634: e0bfff15 stw r2,-4(fp) + delta -= (short)(tp->t_rttvar >> 1); + 8033638: e0bffd17 ldw r2,-12(fp) + 803363c: 10802117 ldw r2,132(r2) + 8033640: 1005d07a srai r2,r2,1 + 8033644: 10bfffcc andi r2,r2,65535 + 8033648: 10a0001c xori r2,r2,32768 + 803364c: 10a00004 addi r2,r2,-32768 + 8033650: e0ffff17 ldw r3,-4(fp) + 8033654: 1885c83a sub r2,r3,r2 + 8033658: e0bfff15 stw r2,-4(fp) + if ((tp->t_rttvar += delta) <= 0) + 803365c: e0bffd17 ldw r2,-12(fp) + 8033660: 10c02117 ldw r3,132(r2) + 8033664: e0bfff17 ldw r2,-4(fp) + 8033668: 1887883a add r3,r3,r2 + 803366c: e0bffd17 ldw r2,-12(fp) + 8033670: 10c02115 stw r3,132(r2) + 8033674: e0bffd17 ldw r2,-12(fp) + 8033678: 10802117 ldw r2,132(r2) + 803367c: 00801116 blt zero,r2,80336c4 + tp->t_rttvar = 1; + 8033680: e0bffd17 ldw r2,-12(fp) + 8033684: 00c00044 movi r3,1 + 8033688: 10c02115 stw r3,132(r2) + 803368c: 00000d06 br 80336c4 + * No rtt measurement yet - use the + * unsmoothed rtt. Set the variance + * to half the rtt (so our first + * retransmit happens at 2*rtt) + */ + if(rtt < 1) + 8033690: e0bffe17 ldw r2,-8(fp) + 8033694: 00800216 blt zero,r2,80336a0 + rtt = 1; + 8033698: 00800044 movi r2,1 + 803369c: e0bffe15 stw r2,-8(fp) + tp->t_srtt = rtt << 3; + 80336a0: e0bffe17 ldw r2,-8(fp) + 80336a4: 100690fa slli r3,r2,3 + 80336a8: e0bffd17 ldw r2,-12(fp) + 80336ac: 10c02015 stw r3,128(r2) + tp->t_rttvar = rtt << 1; + 80336b0: e0bffe17 ldw r2,-8(fp) + 80336b4: 1085883a add r2,r2,r2 + 80336b8: 1007883a mov r3,r2 + 80336bc: e0bffd17 ldw r2,-12(fp) + 80336c0: 10c02115 stw r3,132(r2) + } + tp->t_rttick = 0; /* clear RT timer */ + 80336c4: e0bffd17 ldw r2,-12(fp) + 80336c8: 10001e15 stw zero,120(r2) + tp->t_rxtshift = 0; + 80336cc: e0bffd17 ldw r2,-12(fp) + 80336d0: 10000715 stw zero,28(r2) + TCPT_RANGESET(tp->t_rxtcur, + 80336d4: e0bffd17 ldw r2,-12(fp) + 80336d8: 10802017 ldw r2,128(r2) + 80336dc: 1007d0ba srai r3,r2,2 + 80336e0: e0bffd17 ldw r2,-12(fp) + 80336e4: 10802117 ldw r2,132(r2) + 80336e8: 1885883a add r2,r3,r2 + 80336ec: 1005d07a srai r2,r2,1 + 80336f0: 10ffffcc andi r3,r2,65535 + 80336f4: 18e0001c xori r3,r3,32768 + 80336f8: 18e00004 addi r3,r3,-32768 + 80336fc: e0bffd17 ldw r2,-12(fp) + 8033700: 10c00815 stw r3,32(r2) + 8033704: e0bffd17 ldw r2,-12(fp) + 8033708: 10800817 ldw r2,32(r2) + 803370c: 10800088 cmpgei r2,r2,2 + 8033710: 1000041e bne r2,zero,8033724 + 8033714: e0bffd17 ldw r2,-12(fp) + 8033718: 00c00084 movi r3,2 + 803371c: 10c00815 stw r3,32(r2) + 8033720: 00000706 br 8033740 + 8033724: e0bffd17 ldw r2,-12(fp) + 8033728: 10800817 ldw r2,32(r2) + 803372c: 10802050 cmplti r2,r2,129 + 8033730: 1000031e bne r2,zero,8033740 + 8033734: e0bffd17 ldw r2,-12(fp) + 8033738: 00c02004 movi r3,128 + 803373c: 10c00815 stw r3,32(r2) + ((tp->t_srtt >> 2) + tp->t_rttvar) >> 1, + TCPTV_MIN, TCPTV_REXMTMAX); +} + 8033740: e037883a mov sp,fp + 8033744: dfc00117 ldw ra,4(sp) + 8033748: df000017 ldw fp,0(sp) + 803374c: dec00204 addi sp,sp,8 + 8033750: f800283a ret + +08033754 : + + +#ifdef IP_V4 +int +ip4_tcpmss(struct socket * so) +{ + 8033754: defffd04 addi sp,sp,-12 + 8033758: df000215 stw fp,8(sp) + 803375c: df000204 addi fp,sp,8 + 8033760: e13ffe15 stw r4,-8(fp) + NET ifp; + + ifp = so->so_pcb->ifp; + 8033764: e0bffe17 ldw r2,-8(fp) + 8033768: 10800117 ldw r2,4(r2) + 803376c: 10800a17 ldw r2,40(r2) + 8033770: e0bfff15 stw r2,-4(fp) + return(ifp->n_mtu - (40 + ifp->n_lnh)); + 8033774: e0bfff17 ldw r2,-4(fp) + 8033778: 10c00917 ldw r3,36(r2) + 803377c: e0bfff17 ldw r2,-4(fp) + 8033780: 10800817 ldw r2,32(r2) + 8033784: 10800a04 addi r2,r2,40 + 8033788: 1885c83a sub r2,r3,r2 +} + 803378c: e037883a mov sp,fp + 8033790: df000017 ldw fp,0(sp) + 8033794: dec00104 addi sp,sp,4 + 8033798: f800283a ret + +0803379c : + */ + + +int +tcp_mss(struct socket * so) +{ + 803379c: defffa04 addi sp,sp,-24 + 80337a0: dfc00515 stw ra,20(sp) + 80337a4: df000415 stw fp,16(sp) + 80337a8: df000404 addi fp,sp,16 + 80337ac: e13ffc15 stw r4,-16(fp) + struct tcpcb * tp; +#ifdef IP_V6 + NET ifp = 0; +#endif + + if ((so == NULL) || + 80337b0: e0bffc17 ldw r2,-16(fp) + 80337b4: 10000726 beq r2,zero,80337d4 + (so->so_pcb == NULL) || + 80337b8: e0bffc17 ldw r2,-16(fp) + 80337bc: 10800117 ldw r2,4(r2) + if ((so == NULL) || + 80337c0: 10000426 beq r2,zero,80337d4 + (so->so_pcb->ifp == NULL)) + 80337c4: e0bffc17 ldw r2,-16(fp) + 80337c8: 10800117 ldw r2,4(r2) + 80337cc: 10800a17 ldw r2,40(r2) + (so->so_pcb == NULL) || + 80337d0: 1000061e bne r2,zero,80337ec + { + if (so->so_domain == AF_INET) /* IPv4 */ + 80337d4: e0bffc17 ldw r2,-16(fp) + 80337d8: 10800517 ldw r2,20(r2) + 80337dc: 10800098 cmpnei r2,r2,2 + 80337e0: 1000021e bne r2,zero,80337ec + return TCP_MSS; /* user defined */ + 80337e4: 00816d04 movi r2,1460 + 80337e8: 00002506 br 8033880 +#endif /* IP_V6 */ + + +#ifdef IP_V4 /* Begin messy domain defines */ +#ifndef IP_V6 /* V4 only version */ + mss = ip4_tcpmss(so); + 80337ec: e13ffc17 ldw r4,-16(fp) + 80337f0: 80337540 call 8033754 + 80337f4: e0bfff15 stw r2,-4(fp) +#endif /* end of dual mode */ +#else /* no IP_v4, assume V6 only */ + mss = ip6_tcpmss(so, ifp); +#endif /* end messy domain defines */ + + if (mss > TCP_MSS) /* check upper limit from compile */ + 80337f8: e0bfff17 ldw r2,-4(fp) + 80337fc: 10816d50 cmplti r2,r2,1461 + 8033800: 1000021e bne r2,zero,803380c + mss = TCP_MSS; + 8033804: 00816d04 movi r2,1460 + 8033808: e0bfff15 stw r2,-4(fp) + + /* check upper limit which may be set by setsockopt() */ + inp = (struct inpcb *)so->so_pcb; /* Map socket to IP cb */ + 803380c: e0bffc17 ldw r2,-16(fp) + 8033810: 10800117 ldw r2,4(r2) + 8033814: e0bffe15 stw r2,-8(fp) + tp = (struct tcpcb *)inp->inp_ppcb; /* Map IP to TCP cb */ + 8033818: e0bffe17 ldw r2,-8(fp) + 803381c: 10800917 ldw r2,36(r2) + 8033820: e0bffd15 stw r2,-12(fp) + + /* has user set max seg? */ + if (tp->t_flags & TF_MAXSEG) + 8033824: e0bffd17 ldw r2,-12(fp) + 8033828: 10800b0b ldhu r2,44(r2) + 803382c: 10bfffcc andi r2,r2,65535 + 8033830: 1081000c andi r2,r2,1024 + 8033834: 10000426 beq r2,zero,8033848 + return tp->t_maxseg; /* yup */ + 8033838: e0bffd17 ldw r2,-12(fp) + 803383c: 10800a0b ldhu r2,40(r2) + 8033840: 10bfffcc andi r2,r2,65535 + 8033844: 00000e06 br 8033880 + + if (tp->t_maxseg && (mss > tp->t_maxseg)) /* check tcp's mss */ + 8033848: e0bffd17 ldw r2,-12(fp) + 803384c: 10800a0b ldhu r2,40(r2) + 8033850: 10bfffcc andi r2,r2,65535 + 8033854: 10000926 beq r2,zero,803387c + 8033858: e0bffd17 ldw r2,-12(fp) + 803385c: 10800a0b ldhu r2,40(r2) + 8033860: 10ffffcc andi r3,r2,65535 + 8033864: e0bfff17 ldw r2,-4(fp) + 8033868: 1880040e bge r3,r2,803387c + { + mss = tp->t_maxseg; /* limit new MSS to set MSS */ + 803386c: e0bffd17 ldw r2,-12(fp) + 8033870: 10800a0b ldhu r2,40(r2) + 8033874: 10bfffcc andi r2,r2,65535 + 8033878: e0bfff15 stw r2,-4(fp) + } + + return mss; + 803387c: e0bfff17 ldw r2,-4(fp) +} + 8033880: e037883a mov sp,fp + 8033884: dfc00117 ldw ra,4(sp) + 8033888: df000017 ldw fp,0(sp) + 803388c: dec00204 addi sp,sp,8 + 8033890: f800283a ret + +08033894 : + * RETURNS: 0 if OK, else a sockets error code. + */ + +int +tcp_output(struct tcpcb * tp) +{ + 8033894: deffe804 addi sp,sp,-96 + 8033898: dfc01715 stw ra,92(sp) + 803389c: df001615 stw fp,88(sp) + 80338a0: df001604 addi fp,sp,88 + 80338a4: e13fea15 stw r4,-88(fp) + struct socket * so = tp->t_inpcb->inp_socket; + 80338a8: e0bfea17 ldw r2,-88(fp) + 80338ac: 10800d17 ldw r2,52(r2) + 80338b0: 10800817 ldw r2,32(r2) + 80338b4: e0bff715 stw r2,-36(fp) + int len; + long win; + int off, flags, error; + struct mbuf * m; + struct tcpiphdr * ti; + unsigned optlen = 0; + 80338b8: e03ffb15 stw zero,-20(fp) + * Determine length of data that should be transmitted, + * and flags that will be used. + * If there is some data or critical controls (SYN, RST) + * to send, then transmit; otherwise, investigate further. + */ + idle = (tp->snd_max == tp->snd_una); + 80338bc: e0bfea17 ldw r2,-88(fp) + 80338c0: 10c01a17 ldw r3,104(r2) + 80338c4: e0bfea17 ldw r2,-88(fp) + 80338c8: 10800e17 ldw r2,56(r2) + 80338cc: 1885003a cmpeq r2,r3,r2 + 80338d0: 10803fcc andi r2,r2,255 + 80338d4: e0bff615 stw r2,-40(fp) + +again: + sendalot = 0; + 80338d8: e03ffa15 stw zero,-24(fp) + off = (int)(tp->snd_nxt - tp->snd_una); + 80338dc: e0bfea17 ldw r2,-88(fp) + 80338e0: 10c00f17 ldw r3,60(r2) + 80338e4: e0bfea17 ldw r2,-88(fp) + 80338e8: 10800e17 ldw r2,56(r2) + 80338ec: 1885c83a sub r2,r3,r2 + 80338f0: e0bff515 stw r2,-44(fp) + win = (long)tp->snd_wnd; /* set basic send window */ + 80338f4: e0bfea17 ldw r2,-88(fp) + 80338f8: 10801417 ldw r2,80(r2) + 80338fc: e0bffe15 stw r2,-8(fp) + if (win > (long)tp->snd_cwnd) /* see if we need congestion control */ + 8033900: e0bfea17 ldw r2,-88(fp) + 8033904: 10801b17 ldw r2,108(r2) + 8033908: 1007883a mov r3,r2 + 803390c: e0bffe17 ldw r2,-8(fp) + 8033910: 1880060e bge r3,r2,803392c + { + win = (int)(tp->snd_cwnd & ~(ALIGN_TYPE-1)); /* keep data aligned */ + 8033914: e0bfea17 ldw r2,-88(fp) + 8033918: 10801b17 ldw r2,108(r2) + 803391c: 1007883a mov r3,r2 + 8033920: 00bfff04 movi r2,-4 + 8033924: 1884703a and r2,r3,r2 + 8033928: e0bffe15 stw r2,-8(fp) + * If in persist timeout with window of 0, send 1 byte. + * Otherwise, if window is small but nonzero + * and timer expired, we will send what we can + * and go to transmit state. + */ + if (tp->t_force) + 803392c: e0bfea17 ldw r2,-88(fp) + 8033930: 10800a83 ldbu r2,42(r2) + 8033934: 10803fcc andi r2,r2,255 + 8033938: 1080201c xori r2,r2,128 + 803393c: 10bfe004 addi r2,r2,-128 + 8033940: 10000926 beq r2,zero,8033968 + { + if (win == 0) + 8033944: e0bffe17 ldw r2,-8(fp) + 8033948: 1000031e bne r2,zero,8033958 + win = 1; + 803394c: 00800044 movi r2,1 + 8033950: e0bffe15 stw r2,-8(fp) + 8033954: 00000406 br 8033968 + else + { + tp->t_timer[TCPT_PERSIST] = 0; + 8033958: e0bfea17 ldw r2,-88(fp) + 803395c: 10000415 stw zero,16(r2) + tp->t_rxtshift = 0; + 8033960: e0bfea17 ldw r2,-88(fp) + 8033964: 10000715 stw zero,28(r2) + } + else +#endif /* TCP_SACK */ + { + /* set length of packets which are not sack resends */ + len = (int)MIN(so->so_snd.sb_cc, (unsigned)win) - off; + 8033968: e0bff717 ldw r2,-36(fp) + 803396c: 10801217 ldw r2,72(r2) + 8033970: e0fffe17 ldw r3,-8(fp) + 8033974: 1880012e bgeu r3,r2,803397c + 8033978: 1805883a mov r2,r3 + 803397c: 1007883a mov r3,r2 + 8033980: e0bff517 ldw r2,-44(fp) + 8033984: 1885c83a sub r2,r3,r2 + 8033988: e0bfff15 stw r2,-4(fp) + } + + flags = tcp_outflags[tp->t_state]; + 803398c: e0bfea17 ldw r2,-88(fp) + 8033990: 10c00217 ldw r3,8(r2) + 8033994: 00820174 movhi r2,2053 + 8033998: 1885883a add r2,r3,r2 + 803399c: 10b20a03 ldbu r2,-14296(r2) + 80339a0: 10803fcc andi r2,r2,255 + 80339a4: e0bffd15 stw r2,-12(fp) + } +#else + /* If other options not defined this build then don't bother to call bld_options() except + * on SYN packets + */ + if(flags & TH_SYN) + 80339a8: e0bffd17 ldw r2,-12(fp) + 80339ac: 1080008c andi r2,r2,2 + 80339b0: 10000926 beq r2,zero,80339d8 + { + optlen = bld_options(tp, &tcp_optionbuf[optlen], flags, so); + 80339b4: e0fffb17 ldw r3,-20(fp) + 80339b8: d0a08804 addi r2,gp,-32224 + 80339bc: 1885883a add r2,r3,r2 + 80339c0: e1fff717 ldw r7,-36(fp) + 80339c4: e1bffd17 ldw r6,-12(fp) + 80339c8: 100b883a mov r5,r2 + 80339cc: e13fea17 ldw r4,-88(fp) + 80339d0: 803492c0 call 803492c + 80339d4: e0bffb15 stw r2,-20(fp) + } +#endif + + if (len < 0) + 80339d8: e0bfff17 ldw r2,-4(fp) + 80339dc: 1000090e bge r2,zero,8033a04 + * cancel pending retransmit and pull snd_nxt + * back to (closed) window. We will enter persist + * state below. If the window didn't close completely, + * just wait for an ACK. + */ + len = 0; + 80339e0: e03fff15 stw zero,-4(fp) + if (win == 0) + 80339e4: e0bffe17 ldw r2,-8(fp) + 80339e8: 1000061e bne r2,zero,8033a04 + { + tp->t_timer[TCPT_REXMT] = 0; + 80339ec: e0bfea17 ldw r2,-88(fp) + 80339f0: 10000315 stw zero,12(r2) + tp->snd_nxt = tp->snd_una; + 80339f4: e0bfea17 ldw r2,-88(fp) + 80339f8: 10c00e17 ldw r3,56(r2) + 80339fc: e0bfea17 ldw r2,-88(fp) + 8033a00: 10c00f15 stw r3,60(r2) + } + } + + if (len > (int)tp->t_maxseg) + 8033a04: e0bfea17 ldw r2,-88(fp) + 8033a08: 10800a0b ldhu r2,40(r2) + 8033a0c: 10ffffcc andi r3,r2,65535 + 8033a10: e0bfff17 ldw r2,-4(fp) + 8033a14: 1880060e bge r3,r2,8033a30 + { + len = tp->t_maxseg; + 8033a18: e0bfea17 ldw r2,-88(fp) + 8033a1c: 10800a0b ldhu r2,40(r2) + 8033a20: 10bfffcc andi r2,r2,65535 + 8033a24: e0bfff15 stw r2,-4(fp) + sendalot = 1; + 8033a28: 00800044 movi r2,1 + 8033a2c: e0bffa15 stw r2,-24(fp) + /* We don't need a pmtu test for IPv6. V6 code limits t_maxseg to + * the Path MTU, so the test above the v4 ifdef above covers us. + */ +#endif /* IP_V4 */ + + if (SEQ_LT(tp->snd_nxt + len, tp->snd_una + so->so_snd.sb_cc)) + 8033a30: e0bfea17 ldw r2,-88(fp) + 8033a34: 10c00f17 ldw r3,60(r2) + 8033a38: e0bfff17 ldw r2,-4(fp) + 8033a3c: 1887883a add r3,r3,r2 + 8033a40: e0bfea17 ldw r2,-88(fp) + 8033a44: 11000e17 ldw r4,56(r2) + 8033a48: e0bff717 ldw r2,-36(fp) + 8033a4c: 10801217 ldw r2,72(r2) + 8033a50: 2085883a add r2,r4,r2 + 8033a54: 1885c83a sub r2,r3,r2 + 8033a58: 1000040e bge r2,zero,8033a6c + flags &= ~TH_FIN; + 8033a5c: e0fffd17 ldw r3,-12(fp) + 8033a60: 00bfff84 movi r2,-2 + 8033a64: 1884703a and r2,r3,r2 + 8033a68: e0bffd15 stw r2,-12(fp) + win = (long)(sbspace(&so->so_rcv)); + 8033a6c: e0bff717 ldw r2,-36(fp) + 8033a70: 10800b17 ldw r2,44(r2) + 8033a74: 1007883a mov r3,r2 + 8033a78: e0bff717 ldw r2,-36(fp) + 8033a7c: 10800a17 ldw r2,40(r2) + 8033a80: 1885c83a sub r2,r3,r2 + 8033a84: 10000616 blt r2,zero,8033aa0 + 8033a88: e0bff717 ldw r2,-36(fp) + 8033a8c: 10c00b17 ldw r3,44(r2) + 8033a90: e0bff717 ldw r2,-36(fp) + 8033a94: 10800a17 ldw r2,40(r2) + 8033a98: 1885c83a sub r2,r3,r2 + 8033a9c: 00000106 br 8033aa4 + 8033aa0: 0005883a mov r2,zero + 8033aa4: e0bffe15 stw r2,-8(fp) + /* + * If our state indicates that FIN should be sent + * and we have not yet done so, or we're retransmitting the FIN, + * then we need to send. + */ + if ((flags & TH_FIN) && + 8033aa8: e0bffd17 ldw r2,-12(fp) + 8033aac: 1080004c andi r2,r2,1 + 8033ab0: 10000d26 beq r2,zero,8033ae8 + (so->so_snd.sb_cc == 0) && + 8033ab4: e0bff717 ldw r2,-36(fp) + 8033ab8: 10801217 ldw r2,72(r2) + if ((flags & TH_FIN) && + 8033abc: 10000a1e bne r2,zero,8033ae8 + ((tp->t_flags & TF_SENTFIN) == 0 || tp->snd_nxt == tp->snd_una)) + 8033ac0: e0bfea17 ldw r2,-88(fp) + 8033ac4: 10800b0b ldhu r2,44(r2) + 8033ac8: 10bfffcc andi r2,r2,65535 + 8033acc: 1080040c andi r2,r2,16 + (so->so_snd.sb_cc == 0) && + 8033ad0: 10006626 beq r2,zero,8033c6c + ((tp->t_flags & TF_SENTFIN) == 0 || tp->snd_nxt == tp->snd_una)) + 8033ad4: e0bfea17 ldw r2,-88(fp) + 8033ad8: 10c00f17 ldw r3,60(r2) + 8033adc: e0bfea17 ldw r2,-88(fp) + 8033ae0: 10800e17 ldw r2,56(r2) + 8033ae4: 18806126 beq r3,r2,8033c6c + goto send; + } + /* + * Send if we owe peer an ACK. + */ + if (tp->t_flags & TF_ACKNOW) + 8033ae8: e0bfea17 ldw r2,-88(fp) + 8033aec: 10800b0b ldhu r2,44(r2) + 8033af0: 10bfffcc andi r2,r2,65535 + 8033af4: 1080004c andi r2,r2,1 + 8033af8: 10005e1e bne r2,zero,8033c74 + goto send; + if (flags & (TH_SYN|TH_RST)) + 8033afc: e0bffd17 ldw r2,-12(fp) + 8033b00: 1080018c andi r2,r2,6 + 8033b04: 10005d1e bne r2,zero,8033c7c + goto send; + if (SEQ_GT(tp->snd_up, tp->snd_una)) + 8033b08: e0bfea17 ldw r2,-88(fp) + 8033b0c: 10c01017 ldw r3,64(r2) + 8033b10: e0bfea17 ldw r2,-88(fp) + 8033b14: 10800e17 ldw r2,56(r2) + 8033b18: 1885c83a sub r2,r3,r2 + 8033b1c: 00805916 blt zero,r2,8033c84 + * If peer's buffer is tiny, then send + * when window is at least half open. + * If retransmitting (possibly after persist timer forced us + * to send into a small window), then must resend. + */ + if (len) + 8033b20: e0bfff17 ldw r2,-4(fp) + 8033b24: 10002426 beq r2,zero,8033bb8 + { + if (len == (int)tp->t_maxseg) + 8033b28: e0bfea17 ldw r2,-88(fp) + 8033b2c: 10800a0b ldhu r2,40(r2) + 8033b30: 10bfffcc andi r2,r2,65535 + 8033b34: e0ffff17 ldw r3,-4(fp) + 8033b38: 18805426 beq r3,r2,8033c8c + goto send; + if ((idle || tp->t_flags & TF_NODELAY) && + 8033b3c: e0bff617 ldw r2,-40(fp) + 8033b40: 1000051e bne r2,zero,8033b58 + 8033b44: e0bfea17 ldw r2,-88(fp) + 8033b48: 10800b0b ldhu r2,44(r2) + 8033b4c: 10bfffcc andi r2,r2,65535 + 8033b50: 1080010c andi r2,r2,4 + 8033b54: 10000626 beq r2,zero,8033b70 + len + off >= (int)so->so_snd.sb_cc) + 8033b58: e0ffff17 ldw r3,-4(fp) + 8033b5c: e0bff517 ldw r2,-44(fp) + 8033b60: 1885883a add r2,r3,r2 + 8033b64: e0fff717 ldw r3,-36(fp) + 8033b68: 18c01217 ldw r3,72(r3) + if ((idle || tp->t_flags & TF_NODELAY) && + 8033b6c: 10c0490e bge r2,r3,8033c94 + { + goto send; + } + if (tp->t_force) + 8033b70: e0bfea17 ldw r2,-88(fp) + 8033b74: 10800a83 ldbu r2,42(r2) + 8033b78: 10803fcc andi r2,r2,255 + 8033b7c: 1080201c xori r2,r2,128 + 8033b80: 10bfe004 addi r2,r2,-128 + 8033b84: 1000451e bne r2,zero,8033c9c + goto send; + if (len >= (int)(tp->max_sndwnd / 2)) + 8033b88: e0bfea17 ldw r2,-88(fp) + 8033b8c: 10802317 ldw r2,140(r2) + 8033b90: 1004d07a srli r2,r2,1 + 8033b94: 1007883a mov r3,r2 + 8033b98: e0bfff17 ldw r2,-4(fp) + 8033b9c: 10c0410e bge r2,r3,8033ca4 + goto send; + if (SEQ_LT(tp->snd_nxt, tp->snd_max)) + 8033ba0: e0bfea17 ldw r2,-88(fp) + 8033ba4: 10c00f17 ldw r3,60(r2) + 8033ba8: e0bfea17 ldw r2,-88(fp) + 8033bac: 10801a17 ldw r2,104(r2) + 8033bb0: 1885c83a sub r2,r3,r2 + 8033bb4: 10003d16 blt r2,zero,8033cac + * known to peer (as advertised window less + * next expected input). If the difference is at least two + * max size segments or at least 35% of the maximum possible + * window, then want to send a window update to peer. + */ + if (win > 0) + 8033bb8: e0bffe17 ldw r2,-8(fp) + 8033bbc: 00801c0e bge zero,r2,8033c30 + { + int adv = (int)win - (int)(tp->rcv_adv - tp->rcv_nxt); + 8033bc0: e0bfea17 ldw r2,-88(fp) + 8033bc4: 10c01917 ldw r3,100(r2) + 8033bc8: e0bfea17 ldw r2,-88(fp) + 8033bcc: 10801617 ldw r2,88(r2) + 8033bd0: 1885c83a sub r2,r3,r2 + 8033bd4: 1007883a mov r3,r2 + 8033bd8: e0bffe17 ldw r2,-8(fp) + 8033bdc: 10c5c83a sub r2,r2,r3 + 8033be0: e0bff415 stw r2,-48(fp) + + if (so->so_rcv.sb_cc == 0 && adv >= (int)(tp->t_maxseg * 2)) + 8033be4: e0bff717 ldw r2,-36(fp) + 8033be8: 10800a17 ldw r2,40(r2) + 8033bec: 1000071e bne r2,zero,8033c0c + 8033bf0: e0bfea17 ldw r2,-88(fp) + 8033bf4: 10800a0b ldhu r2,40(r2) + 8033bf8: 10bfffcc andi r2,r2,65535 + 8033bfc: 1085883a add r2,r2,r2 + 8033c00: 1007883a mov r3,r2 + 8033c04: e0bff417 ldw r2,-48(fp) + 8033c08: 10c02a0e bge r2,r3,8033cb4 + goto send; + if (100 * (u_int)adv / so->so_rcv.sb_hiwat >= 35) + 8033c0c: e0bff417 ldw r2,-48(fp) + 8033c10: 10c01924 muli r3,r2,100 + 8033c14: e0bff717 ldw r2,-36(fp) + 8033c18: 10800b17 ldw r2,44(r2) + 8033c1c: 100b883a mov r5,r2 + 8033c20: 1809883a mov r4,r3 + 8033c24: 800cff80 call 800cff8 <__udivsi3> + 8033c28: 108008f0 cmpltui r2,r2,35 + 8033c2c: 10002326 beq r2,zero,8033cbc + * retransmit or persist is pending, then go to persist state. + * If nothing happens soon, send when timer expires: + * if window is nonzero, transmit what we can, + * otherwise force out a byte. + */ + if (so->so_snd.sb_cc && tp->t_timer[TCPT_REXMT] == 0 && + 8033c30: e0bff717 ldw r2,-36(fp) + 8033c34: 10801217 ldw r2,72(r2) + 8033c38: 10000a26 beq r2,zero,8033c64 + 8033c3c: e0bfea17 ldw r2,-88(fp) + 8033c40: 10800317 ldw r2,12(r2) + 8033c44: 1000071e bne r2,zero,8033c64 + tp->t_timer[TCPT_PERSIST] == 0) + 8033c48: e0bfea17 ldw r2,-88(fp) + 8033c4c: 10800417 ldw r2,16(r2) + if (so->so_snd.sb_cc && tp->t_timer[TCPT_REXMT] == 0 && + 8033c50: 1000041e bne r2,zero,8033c64 + { + tp->t_rxtshift = 0; + 8033c54: e0bfea17 ldw r2,-88(fp) + 8033c58: 10000715 stw zero,28(r2) + tcp_setpersist(tp); + 8033c5c: e13fea17 ldw r4,-88(fp) + 8033c60: 80348300 call 8034830 + } + + /* + * No reason to send a segment, just return. + */ + return (0); + 8033c64: 0005883a mov r2,zero + 8033c68: 0002ec06 br 803481c + goto send; + 8033c6c: 0001883a nop + 8033c70: 00001306 br 8033cc0 + goto send; + 8033c74: 0001883a nop + 8033c78: 00001106 br 8033cc0 + goto send; + 8033c7c: 0001883a nop + 8033c80: 00000f06 br 8033cc0 + goto send; + 8033c84: 0001883a nop + 8033c88: 00000d06 br 8033cc0 + goto send; + 8033c8c: 0001883a nop + 8033c90: 00000b06 br 8033cc0 + goto send; + 8033c94: 0001883a nop + 8033c98: 00000906 br 8033cc0 + goto send; + 8033c9c: 0001883a nop + 8033ca0: 00000706 br 8033cc0 + goto send; + 8033ca4: 0001883a nop + 8033ca8: 00000506 br 8033cc0 + goto send; + 8033cac: 0001883a nop + 8033cb0: 00000306 br 8033cc0 + goto send; + 8033cb4: 0001883a nop + 8033cb8: 00000106 br 8033cc0 + goto send; + 8033cbc: 0001883a nop + +send: + ENTER_CRIT_SECTION(tp); + 8033cc0: 8028e940 call 8028e94 + + /* Limit send length to the current buffer so as to + * avoid doing the "mbuf shuffle" in m_copy(). + */ + bufoff = off; + 8033cc4: e0bff517 ldw r2,-44(fp) + 8033cc8: e0bff815 stw r2,-32(fp) + sendm = so->so_snd.sb_mb; + 8033ccc: e0bff717 ldw r2,-36(fp) + 8033cd0: 10801817 ldw r2,96(r2) + 8033cd4: e0bff915 stw r2,-28(fp) + if (len) + 8033cd8: e0bfff17 ldw r2,-4(fp) + 8033cdc: 10005526 beq r2,zero,8033e34 + { + /* find mbuf containing data to send (at "off") */ + while (sendm) /* loop through socket send list */ + 8033ce0: 00000a06 br 8033d0c + { + bufoff -= sendm->m_len; + 8033ce4: e0fff817 ldw r3,-32(fp) + 8033ce8: e0bff917 ldw r2,-28(fp) + 8033cec: 10800217 ldw r2,8(r2) + 8033cf0: 1885c83a sub r2,r3,r2 + 8033cf4: e0bff815 stw r2,-32(fp) + if (bufoff < 0) /* if off is in this buffer, break */ + 8033cf8: e0bff817 ldw r2,-32(fp) + 8033cfc: 10000616 blt r2,zero,8033d18 + break; + sendm = sendm->m_next; + 8033d00: e0bff917 ldw r2,-28(fp) + 8033d04: 10800617 ldw r2,24(r2) + 8033d08: e0bff915 stw r2,-28(fp) + while (sendm) /* loop through socket send list */ + 8033d0c: e0bff917 ldw r2,-28(fp) + 8033d10: 103ff41e bne r2,zero,8033ce4 + 8033d14: 00000106 br 8033d1c + break; + 8033d18: 0001883a nop + } + if (!sendm) { dtrap(); /* shouldn't happen */ } + 8033d1c: e0bff917 ldw r2,-28(fp) + 8033d20: 1000011e bne r2,zero,8033d28 + 8033d24: 8028cd40 call 8028cd4 + bufoff += sendm->m_len; /* index to next data to send in msend */ + 8033d28: e0bff917 ldw r2,-28(fp) + 8033d2c: 10c00217 ldw r3,8(r2) + 8033d30: e0bff817 ldw r2,-32(fp) + 8033d34: 1885883a add r2,r3,r2 + 8033d38: e0bff815 stw r2,-32(fp) + + /* if socket has multiple unsent mbufs, set flag for send to loop */ + if ((sendm->m_next) && (len > (int)sendm->m_len)) + 8033d3c: e0bff917 ldw r2,-28(fp) + 8033d40: 10800617 ldw r2,24(r2) + 8033d44: 10000b26 beq r2,zero,8033d74 + 8033d48: e0bff917 ldw r2,-28(fp) + 8033d4c: 10800217 ldw r2,8(r2) + 8033d50: 1007883a mov r3,r2 + 8033d54: e0bfff17 ldw r2,-4(fp) + 8033d58: 1880060e bge r3,r2,8033d74 + { + flags &= ~TH_FIN; /* don't FIN on segment prior to last */ + 8033d5c: e0fffd17 ldw r3,-12(fp) + 8033d60: 00bfff84 movi r2,-2 + 8033d64: 1884703a and r2,r3,r2 + 8033d68: e0bffd15 stw r2,-12(fp) + sendalot = 1; /* set to send more segments */ + 8033d6c: 00800044 movi r2,1 + 8033d70: e0bffa15 stw r2,-24(fp) + } + if((flags & TH_FIN) && (so->so_snd.sb_cc > (unsigned)len)) + 8033d74: e0bffd17 ldw r2,-12(fp) + 8033d78: 1080004c andi r2,r2,1 + 8033d7c: 10000826 beq r2,zero,8033da0 + 8033d80: e0bff717 ldw r2,-36(fp) + 8033d84: 10801217 ldw r2,72(r2) + 8033d88: e0ffff17 ldw r3,-4(fp) + 8033d8c: 1880042e bgeu r3,r2,8033da0 + { + /* This can happen on slow links (PPP) which retry the last + * segment - the one with the FIN bit attached to data. + */ + flags &= ~TH_FIN; /* don't FIN on segment prior to last */ + 8033d90: e0fffd17 ldw r3,-12(fp) + 8033d94: 00bfff84 movi r2,-2 + 8033d98: 1884703a and r2,r3,r2 + 8033d9c: e0bffd15 stw r2,-12(fp) + } + + /* only send the rest of msend */ + len = min(len, (int)sendm->m_len); + 8033da0: e0bff917 ldw r2,-28(fp) + 8033da4: 10800217 ldw r2,8(r2) + 8033da8: 1007883a mov r3,r2 + 8033dac: e0bfff17 ldw r2,-4(fp) + 8033db0: 1880010e bge r3,r2,8033db8 + 8033db4: 1805883a mov r2,r3 + 8033db8: e0bfff15 stw r2,-4(fp) + * Similarly, if sendm->m_data is not aligned with respect to + * sendm->m_base and ALIGN_TYPE, we will copy the data to + * ensure that it (and the then-prepended IP/TCP headers) will + * be aligned according to ALIGN_TYPE. + */ + if ((bufoff != 0) || /* data not front aligned in send mbuf? */ + 8033dbc: e0bff817 ldw r2,-32(fp) + 8033dc0: 1000071e bne r2,zero,8033de0 + (((sendm->m_data - sendm->m_base) & (ALIGN_TYPE - 1)) != 0)) + 8033dc4: e0bff917 ldw r2,-28(fp) + 8033dc8: 10c00317 ldw r3,12(r2) + 8033dcc: e0bff917 ldw r2,-28(fp) + 8033dd0: 10800417 ldw r2,16(r2) + 8033dd4: 1885c83a sub r2,r3,r2 + 8033dd8: 108000cc andi r2,r2,3 + if ((bufoff != 0) || /* data not front aligned in send mbuf? */ + 8033ddc: 10001526 beq r2,zero,8033e34 + { + len = min(len, (int)(sendm->m_len - bufoff)); /* limit len again */ + 8033de0: e0bff917 ldw r2,-28(fp) + 8033de4: 10c00217 ldw r3,8(r2) + 8033de8: e0bff817 ldw r2,-32(fp) + 8033dec: 1885c83a sub r2,r3,r2 + 8033df0: 1007883a mov r3,r2 + 8033df4: e0bfff17 ldw r2,-4(fp) + 8033df8: 1880010e bge r3,r2,8033e00 + 8033dfc: 1805883a mov r2,r3 + 8033e00: e0bfff15 stw r2,-4(fp) + * of the m_data buffer then we can't use it in place, else we + * might write the IP/TCP header over data that has not yet + * been acked. In this case we must make sure our send + * fits into a little buffer and send what we can. + */ + if ((len > (int)(lilbufsiz - HDRSLEN)) && /* length is bigger the small buffer? */ + 8033e04: d0a01717 ldw r2,-32676(gp) + 8033e08: 10bff204 addi r2,r2,-56 + 8033e0c: 1007883a mov r3,r2 + 8033e10: e0bfff17 ldw r2,-4(fp) + 8033e14: 1880070e bge r3,r2,8033e34 + (bigfreeq.q_len < 2)) /* and we are low on big buffers */ + 8033e18: 008201b4 movhi r2,2054 + 8033e1c: 10b7dd17 ldw r2,-8332(r2) + if ((len > (int)(lilbufsiz - HDRSLEN)) && /* length is bigger the small buffer? */ + 8033e20: 10800088 cmpgei r2,r2,2 + 8033e24: 1000031e bne r2,zero,8033e34 + { + len = lilbufsiz - HDRSLEN; + 8033e28: d0a01717 ldw r2,-32676(gp) + 8033e2c: 10bff204 addi r2,r2,-56 + 8033e30: e0bfff15 stw r2,-4(fp) + } + + /* if send data is sufficiently aligned in packet, prepend TCP/IP header + * in the space provided. + */ + if (len && (bufoff == 0) && + 8033e34: e0bfff17 ldw r2,-4(fp) + 8033e38: 10003526 beq r2,zero,8033f10 + 8033e3c: e0bff817 ldw r2,-32(fp) + 8033e40: 1000331e bne r2,zero,8033f10 + (sendm->pkt->inuse == 1) && + 8033e44: e0bff917 ldw r2,-28(fp) + 8033e48: 10800117 ldw r2,4(r2) + 8033e4c: 10800917 ldw r2,36(r2) + if (len && (bufoff == 0) && + 8033e50: 10800058 cmpnei r2,r2,1 + 8033e54: 10002e1e bne r2,zero,8033f10 + (((sendm->m_data - sendm->m_base) & (ALIGN_TYPE - 1)) == 0) && + 8033e58: e0bff917 ldw r2,-28(fp) + 8033e5c: 10c00317 ldw r3,12(r2) + 8033e60: e0bff917 ldw r2,-28(fp) + 8033e64: 10800417 ldw r2,16(r2) + 8033e68: 1885c83a sub r2,r3,r2 + 8033e6c: 108000cc andi r2,r2,3 + (sendm->pkt->inuse == 1) && + 8033e70: 1000271e bne r2,zero,8033f10 + (((sendm->m_data - sendm->m_base) & (ALIGN_TYPE - 1)) == 0) && + 8033e74: e0bffb17 ldw r2,-20(fp) + 8033e78: 1000251e bne r2,zero,8033f10 + (optlen == 0)) + { + /* get an empty mbuf to "clone" the data */ + m = m_getnbuf(MT_TXDATA, 0); + 8033e7c: 000b883a mov r5,zero + 8033e80: 01000084 movi r4,2 + 8033e84: 8029a700 call 8029a70 + 8033e88: e0bffc15 stw r2,-16(fp) + if (!m) + 8033e8c: e0bffc17 ldw r2,-16(fp) + 8033e90: 1000031e bne r2,zero,8033ea0 + { + EXIT_CRIT_SECTION(tp); + 8033e94: 8028ef40 call 8028ef4 + return (ENOBUFS); + 8033e98: 00801a44 movi r2,105 + 8033e9c: 00025f06 br 803481c + } + m->pkt = sendm->pkt; /* copy packet location in new mbuf */ + 8033ea0: e0bff917 ldw r2,-28(fp) + 8033ea4: 10c00117 ldw r3,4(r2) + 8033ea8: e0bffc17 ldw r2,-16(fp) + 8033eac: 10c00115 stw r3,4(r2) + m->pkt->inuse++; /* bump packet's use count */ + 8033eb0: e0bffc17 ldw r2,-16(fp) + 8033eb4: 10800117 ldw r2,4(r2) + 8033eb8: 10c00917 ldw r3,36(r2) + 8033ebc: 18c00044 addi r3,r3,1 + 8033ec0: 10c00915 stw r3,36(r2) + m->m_base = sendm->m_base; /* clone mbuf members */ + 8033ec4: e0bff917 ldw r2,-28(fp) + 8033ec8: 10c00417 ldw r3,16(r2) + 8033ecc: e0bffc17 ldw r2,-16(fp) + 8033ed0: 10c00415 stw r3,16(r2) + m->m_memsz = sendm->m_memsz; + 8033ed4: e0bff917 ldw r2,-28(fp) + 8033ed8: 10c00517 ldw r3,20(r2) + 8033edc: e0bffc17 ldw r2,-16(fp) + 8033ee0: 10c00515 stw r3,20(r2) + m->m_len = len + TCPIPHDRSZ; /* adjust clone for header */ + 8033ee4: e0bfff17 ldw r2,-4(fp) + 8033ee8: 10800a04 addi r2,r2,40 + 8033eec: 1007883a mov r3,r2 + 8033ef0: e0bffc17 ldw r2,-16(fp) + 8033ef4: 10c00215 stw r3,8(r2) + m->m_data = sendm->m_data - TCPIPHDRSZ; + 8033ef8: e0bff917 ldw r2,-28(fp) + 8033efc: 10800317 ldw r2,12(r2) + 8033f00: 10fff604 addi r3,r2,-40 + 8033f04: e0bffc17 ldw r2,-16(fp) + 8033f08: 10c00315 stw r3,12(r2) + 8033f0c: 00002706 br 8033fac + { + /* Grab a header mbuf, attaching a copy of data to be + * transmitted, and initialize the header from + * the template for sends on this connection. + */ + m = m_getwithdata (MT_HEADER, IFNETHDR_SIZE + TCPIPHDRSZ); + 8033f10: d0a06417 ldw r2,-32368(gp) + 8033f14: 10800a04 addi r2,r2,40 + 8033f18: 100b883a mov r5,r2 + 8033f1c: 010000c4 movi r4,3 + 8033f20: 8029a700 call 8029a70 + 8033f24: e0bffc15 stw r2,-16(fp) + if (m ==(struct mbuf *)NULL) + 8033f28: e0bffc17 ldw r2,-16(fp) + 8033f2c: 1000031e bne r2,zero,8033f3c + { + EXIT_CRIT_SECTION(tp); + 8033f30: 8028ef40 call 8028ef4 + return ENOBUFS; + 8033f34: 00801a44 movi r2,105 + 8033f38: 00023806 br 803481c + } + + m->m_len = TCPIPHDRSZ; + 8033f3c: e0bffc17 ldw r2,-16(fp) + 8033f40: 00c00a04 movi r3,40 + 8033f44: 10c00215 stw r3,8(r2) + m->m_data += IFNETHDR_SIZE;/* Move this to sizeof tcpip hdr leave*/ + 8033f48: e0bffc17 ldw r2,-16(fp) + 8033f4c: 10800317 ldw r2,12(r2) + 8033f50: d0e06417 ldw r3,-32368(gp) + 8033f54: 10c7883a add r3,r2,r3 + 8033f58: e0bffc17 ldw r2,-16(fp) + 8033f5c: 10c00315 stw r3,12(r2) + /* 14 bytes for ethernet header */ + + if (len) /* attach any data to send */ + 8033f60: e0bfff17 ldw r2,-4(fp) + 8033f64: 10001126 beq r2,zero,8033fac + { + m->m_next = m_copy(so->so_snd.sb_mb, off, (int) len); + 8033f68: e0bff717 ldw r2,-36(fp) + 8033f6c: 10801817 ldw r2,96(r2) + 8033f70: e1bfff17 ldw r6,-4(fp) + 8033f74: e17ff517 ldw r5,-44(fp) + 8033f78: 1009883a mov r4,r2 + 8033f7c: 8029d400 call 8029d40 + 8033f80: 1007883a mov r3,r2 + 8033f84: e0bffc17 ldw r2,-16(fp) + 8033f88: 10c00615 stw r3,24(r2) + if (m->m_next == 0) + 8033f8c: e0bffc17 ldw r2,-16(fp) + 8033f90: 10800617 ldw r2,24(r2) + 8033f94: 1000051e bne r2,zero,8033fac + { + m_freem(m); + 8033f98: e13ffc17 ldw r4,-16(fp) + 8033f9c: 8029cfc0 call 8029cfc + EXIT_CRIT_SECTION(tp); + 8033fa0: 8028ef40 call 8028ef4 + return ENOBUFS; + 8033fa4: 00801a44 movi r2,105 + 8033fa8: 00021c06 br 803481c + } + } + } + EXIT_CRIT_SECTION(tp); + 8033fac: 8028ef40 call 8028ef4 + + if (len) + 8033fb0: e0bfff17 ldw r2,-4(fp) + 8033fb4: 10002d26 beq r2,zero,803406c + { + if (tp->t_force && len == 1) + 8033fb8: e0bfea17 ldw r2,-88(fp) + 8033fbc: 10800a83 ldbu r2,42(r2) + 8033fc0: 10803fcc andi r2,r2,255 + 8033fc4: 1080201c xori r2,r2,128 + 8033fc8: 10bfe004 addi r2,r2,-128 + 8033fcc: 10000926 beq r2,zero,8033ff4 + 8033fd0: e0bfff17 ldw r2,-4(fp) + 8033fd4: 10800058 cmpnei r2,r2,1 + 8033fd8: 1000061e bne r2,zero,8033ff4 + tcpstat.tcps_sndprobe++; + 8033fdc: 008201b4 movhi r2,2054 + 8033fe0: 10b8b917 ldw r2,-7452(r2) + 8033fe4: 10c00044 addi r3,r2,1 + 8033fe8: 008201b4 movhi r2,2054 + 8033fec: 10f8b915 stw r3,-7452(r2) + 8033ff0: 00004306 br 8034100 + else if (SEQ_LT(tp->snd_nxt, tp->snd_max)) + 8033ff4: e0bfea17 ldw r2,-88(fp) + 8033ff8: 10c00f17 ldw r3,60(r2) + 8033ffc: e0bfea17 ldw r2,-88(fp) + 8034000: 10801a17 ldw r2,104(r2) + 8034004: 1885c83a sub r2,r3,r2 + 8034008: 10000c0e bge r2,zero,803403c + { + tcpstat.tcps_sndrexmitpack++; + 803400c: 008201b4 movhi r2,2054 + 8034010: 10b8b617 ldw r2,-7464(r2) + 8034014: 10c00044 addi r3,r2,1 + 8034018: 008201b4 movhi r2,2054 + 803401c: 10f8b615 stw r3,-7464(r2) + tcpstat.tcps_sndrexmitbyte += len; + 8034020: 008201b4 movhi r2,2054 + 8034024: 10f8b717 ldw r3,-7460(r2) + 8034028: e0bfff17 ldw r2,-4(fp) + 803402c: 1887883a add r3,r3,r2 + 8034030: 008201b4 movhi r2,2054 + 8034034: 10f8b715 stw r3,-7460(r2) + 8034038: 00003106 br 8034100 + tcpstat.tcps_sackresend++; +#endif + } + else + { + tcpstat.tcps_sndpack++; + 803403c: 008201b4 movhi r2,2054 + 8034040: 10b8b417 ldw r2,-7472(r2) + 8034044: 10c00044 addi r3,r2,1 + 8034048: 008201b4 movhi r2,2054 + 803404c: 10f8b415 stw r3,-7472(r2) + tcpstat.tcps_sndbyte += len; + 8034050: 008201b4 movhi r2,2054 + 8034054: 10f8b517 ldw r3,-7468(r2) + 8034058: e0bfff17 ldw r2,-4(fp) + 803405c: 1887883a add r3,r3,r2 + 8034060: 008201b4 movhi r2,2054 + 8034064: 10f8b515 stw r3,-7468(r2) + 8034068: 00002506 br 8034100 + } + } + else if (tp->t_flags & TF_ACKNOW) + 803406c: e0bfea17 ldw r2,-88(fp) + 8034070: 10800b0b ldhu r2,44(r2) + 8034074: 10bfffcc andi r2,r2,65535 + 8034078: 1080004c andi r2,r2,1 + 803407c: 10000626 beq r2,zero,8034098 + { + tcpstat.tcps_sndacks++; + 8034080: 008201b4 movhi r2,2054 + 8034084: 10b8b817 ldw r2,-7456(r2) + 8034088: 10c00044 addi r3,r2,1 + 803408c: 008201b4 movhi r2,2054 + 8034090: 10f8b815 stw r3,-7456(r2) + 8034094: 00001a06 br 8034100 + } + else if (flags & (TH_SYN|TH_FIN|TH_RST)) + 8034098: e0bffd17 ldw r2,-12(fp) + 803409c: 108001cc andi r2,r2,7 + 80340a0: 10000626 beq r2,zero,80340bc + tcpstat.tcps_sndctrl++; + 80340a4: 008201b4 movhi r2,2054 + 80340a8: 10b8bc17 ldw r2,-7440(r2) + 80340ac: 10c00044 addi r3,r2,1 + 80340b0: 008201b4 movhi r2,2054 + 80340b4: 10f8bc15 stw r3,-7440(r2) + 80340b8: 00001106 br 8034100 + else if (SEQ_GT(tp->snd_up, tp->snd_una)) + 80340bc: e0bfea17 ldw r2,-88(fp) + 80340c0: 10c01017 ldw r3,64(r2) + 80340c4: e0bfea17 ldw r2,-88(fp) + 80340c8: 10800e17 ldw r2,56(r2) + 80340cc: 1885c83a sub r2,r3,r2 + 80340d0: 0080060e bge zero,r2,80340ec + tcpstat.tcps_sndurg++; + 80340d4: 008201b4 movhi r2,2054 + 80340d8: 10b8ba17 ldw r2,-7448(r2) + 80340dc: 10c00044 addi r3,r2,1 + 80340e0: 008201b4 movhi r2,2054 + 80340e4: 10f8ba15 stw r3,-7448(r2) + 80340e8: 00000506 br 8034100 + else + tcpstat.tcps_sndwinup++; + 80340ec: 008201b4 movhi r2,2054 + 80340f0: 10b8bb17 ldw r2,-7444(r2) + 80340f4: 10c00044 addi r3,r2,1 + 80340f8: 008201b4 movhi r2,2054 + 80340fc: 10f8bb15 stw r3,-7444(r2) + + ti = (struct tcpiphdr *)(m->m_data+sizeof(struct ip)-sizeof(struct ipovly)); + 8034100: e0bffc17 ldw r2,-16(fp) + 8034104: 10800317 ldw r2,12(r2) + 8034108: e0bff315 stw r2,-52(fp) + if ((char *)ti < m->pkt->nb_buff) + 803410c: e0bffc17 ldw r2,-16(fp) + 8034110: 10800117 ldw r2,4(r2) + 8034114: 10800117 ldw r2,4(r2) + 8034118: e0fff317 ldw r3,-52(fp) + 803411c: 1880032e bgeu r3,r2,803412c + { + panic("tcp_out- packet ptr underflow\n"); + 8034120: 01020174 movhi r4,2053 + 8034124: 212aa204 addi r4,r4,-21880 + 8034128: 80271780 call 8027178 + } + tcp_mbuf = m; /* flag TCP header mbuf */ + 803412c: e0bffc17 ldw r2,-16(fp) + 8034130: e0bff215 stw r2,-56(fp) + tcp_mbuf->m_data += sizeof(struct ipovly); + tcp_mbuf->m_len -= sizeof(struct ipovly); + } +#endif /* end IP_V6 */ + + if (tp->t_template == 0) + 8034134: e0bfea17 ldw r2,-88(fp) + 8034138: 10800c17 ldw r2,48(r2) + 803413c: 1000031e bne r2,zero,803414c + panic("tcp_output"); + 8034140: 01020174 movhi r4,2053 + 8034144: 212aaa04 addi r4,r4,-21848 + 8034148: 80271780 call 8027178 + + MEMCPY((char*)ti, (char*)tp->t_template, sizeof(struct tcpiphdr)); + 803414c: e0bfea17 ldw r2,-88(fp) + 8034150: 10800c17 ldw r2,48(r2) + 8034154: 01800a04 movi r6,40 + 8034158: 100b883a mov r5,r2 + 803415c: e13ff317 ldw r4,-52(fp) + 8034160: 80086b80 call 80086b8 + /* + * Fill in fields, remembering maximum advertised + * window for use in delaying messages about window sizes. + * If resending a FIN, be sure not to use a new sequence number. + */ + if (flags & TH_FIN && tp->t_flags & TF_SENTFIN && + 8034164: e0bffd17 ldw r2,-12(fp) + 8034168: 1080004c andi r2,r2,1 + 803416c: 10000f26 beq r2,zero,80341ac + 8034170: e0bfea17 ldw r2,-88(fp) + 8034174: 10800b0b ldhu r2,44(r2) + 8034178: 10bfffcc andi r2,r2,65535 + 803417c: 1080040c andi r2,r2,16 + 8034180: 10000a26 beq r2,zero,80341ac + tp->snd_nxt == tp->snd_max) + 8034184: e0bfea17 ldw r2,-88(fp) + 8034188: 10c00f17 ldw r3,60(r2) + 803418c: e0bfea17 ldw r2,-88(fp) + 8034190: 10801a17 ldw r2,104(r2) + if (flags & TH_FIN && tp->t_flags & TF_SENTFIN && + 8034194: 1880051e bne r3,r2,80341ac + { + tp->snd_nxt--; + 8034198: e0bfea17 ldw r2,-88(fp) + 803419c: 10800f17 ldw r2,60(r2) + 80341a0: 10ffffc4 addi r3,r2,-1 + 80341a4: e0bfea17 ldw r2,-88(fp) + 80341a8: 10c00f15 stw r3,60(r2) + } + + ti->ti_seq = htonl(tp->snd_nxt); + 80341ac: e0bfea17 ldw r2,-88(fp) + 80341b0: 10800f17 ldw r2,60(r2) + 80341b4: 1006d63a srli r3,r2,24 + 80341b8: e0bfea17 ldw r2,-88(fp) + 80341bc: 10800f17 ldw r2,60(r2) + 80341c0: 1004d23a srli r2,r2,8 + 80341c4: 10bfc00c andi r2,r2,65280 + 80341c8: 1886b03a or r3,r3,r2 + 80341cc: e0bfea17 ldw r2,-88(fp) + 80341d0: 10800f17 ldw r2,60(r2) + 80341d4: 1004923a slli r2,r2,8 + 80341d8: 10803fec andhi r2,r2,255 + 80341dc: 1886b03a or r3,r3,r2 + 80341e0: e0bfea17 ldw r2,-88(fp) + 80341e4: 10800f17 ldw r2,60(r2) + 80341e8: 1004963a slli r2,r2,24 + 80341ec: 1886b03a or r3,r3,r2 + 80341f0: e0bff317 ldw r2,-52(fp) + 80341f4: 10c00615 stw r3,24(r2) + ti->ti_ack = htonl(tp->rcv_nxt); + 80341f8: e0bfea17 ldw r2,-88(fp) + 80341fc: 10801617 ldw r2,88(r2) + 8034200: 1006d63a srli r3,r2,24 + 8034204: e0bfea17 ldw r2,-88(fp) + 8034208: 10801617 ldw r2,88(r2) + 803420c: 1004d23a srli r2,r2,8 + 8034210: 10bfc00c andi r2,r2,65280 + 8034214: 1886b03a or r3,r3,r2 + 8034218: e0bfea17 ldw r2,-88(fp) + 803421c: 10801617 ldw r2,88(r2) + 8034220: 1004923a slli r2,r2,8 + 8034224: 10803fec andhi r2,r2,255 + 8034228: 1886b03a or r3,r3,r2 + 803422c: e0bfea17 ldw r2,-88(fp) + 8034230: 10801617 ldw r2,88(r2) + 8034234: 1004963a slli r2,r2,24 + 8034238: 1886b03a or r3,r3,r2 + 803423c: e0bff317 ldw r2,-52(fp) + 8034240: 10c00715 stw r3,28(r2) + * a retransmission, and the original SYN caused PPP to start + * bringing the interface up, and PPP has got a new IP address + * via IPCP), update the template and the inpcb with the new + * address. + */ + if (flags & TH_SYN) + 8034244: e0bffd17 ldw r2,-12(fp) + 8034248: 1080008c andi r2,r2,2 + 803424c: 10002326 beq r2,zero,80342dc + { + struct inpcb * inp; + inp = (struct inpcb *)so->so_pcb; + 8034250: e0bff717 ldw r2,-36(fp) + 8034254: 10800117 ldw r2,4(r2) + 8034258: e0bff115 stw r2,-60(fp) + + switch(so->so_domain) + 803425c: e0bff717 ldw r2,-36(fp) + 8034260: 10800517 ldw r2,20(r2) + 8034264: 10800098 cmpnei r2,r2,2 + 8034268: 10001a1e bne r2,zero,80342d4 + } + } +#endif /* INCLUDE_PPP */ + + /* If this is a SYN (not a SYN/ACK) then set the pmtu */ + if((flags & TH_ACK) == 0) + 803426c: e0bffd17 ldw r2,-12(fp) + 8034270: 1080040c andi r2,r2,16 + 8034274: 10001b1e bne r2,zero,80342e4 + inp->inp_pmtu = pmtucache_get(inp->inp_faddr.s_addr); +#else /* not compiled for pathmtu, guess based on iface */ + { + NET ifp; + /* find iface for route. Pass "src" as nexthop return */ + ifp = iproute(ti->ti_dst.s_addr, &src); + 8034278: e0bff317 ldw r2,-52(fp) + 803427c: 10800417 ldw r2,16(r2) + 8034280: e0ffeb04 addi r3,fp,-84 + 8034284: 180b883a mov r5,r3 + 8034288: 1009883a mov r4,r2 + 803428c: 803b3700 call 803b370 + 8034290: e0bff015 stw r2,-64(fp) + if(ifp) + 8034294: e0bff017 ldw r2,-64(fp) + 8034298: 10000926 beq r2,zero,80342c0 + inp->inp_pmtu = ifp->n_mtu - (ifp->n_lnh + 40); + 803429c: e0bff017 ldw r2,-64(fp) + 80342a0: 10c00917 ldw r3,36(r2) + 80342a4: e0bff017 ldw r2,-64(fp) + 80342a8: 10800817 ldw r2,32(r2) + 80342ac: 10800a04 addi r2,r2,40 + 80342b0: 1887c83a sub r3,r3,r2 + 80342b4: e0bff117 ldw r2,-60(fp) + 80342b8: 10c00615 stw r3,24(r2) + else + inp->inp_pmtu = 580; /* Ugh. */ + } +#endif /* IP_PMTU */ + } + break; + 80342bc: 00000906 br 80342e4 + inp->inp_pmtu = 580; /* Ugh. */ + 80342c0: e0bff117 ldw r2,-60(fp) + 80342c4: 00c09104 movi r3,580 + 80342c8: 10c00615 stw r3,24(r2) + break; + 80342cc: 0001883a nop + 80342d0: 00000406 br 80342e4 + } + break; + } +#endif /* IP_V6 */ + default: + dtrap(); /* bad domain setting */ + 80342d4: 8028cd40 call 8028cd4 + 80342d8: 00000306 br 80342e8 + } + } + 80342dc: 0001883a nop + 80342e0: 00000106 br 80342e8 + break; + 80342e4: 0001883a nop + + /* fill in options if any are set */ + if (optlen) + 80342e8: e0bffb17 ldw r2,-20(fp) + 80342ec: 10002b26 beq r2,zero,803439c + { + struct mbuf * mopt; + + mopt = m_getwithdata(MT_TXDATA, MAXOPTLEN); + 80342f0: 01404004 movi r5,256 + 80342f4: 01000084 movi r4,2 + 80342f8: 8029a700 call 8029a70 + 80342fc: e0bfef15 stw r2,-68(fp) + if (mopt == NULL) + 8034300: e0bfef17 ldw r2,-68(fp) + 8034304: 1000041e bne r2,zero,8034318 + { + m_freem(m); + 8034308: e13ffc17 ldw r4,-16(fp) + 803430c: 8029cfc0 call 8029cfc + return (ENOBUFS); + 8034310: 00801a44 movi r2,105 + 8034314: 00014106 br 803481c + } + + /* insert options mbuf after after tmp_mbuf */ + mopt->m_next = tcp_mbuf->m_next; + 8034318: e0bff217 ldw r2,-56(fp) + 803431c: 10c00617 ldw r3,24(r2) + 8034320: e0bfef17 ldw r2,-68(fp) + 8034324: 10c00615 stw r3,24(r2) + tcp_mbuf->m_next = mopt; + 8034328: e0bff217 ldw r2,-56(fp) + 803432c: e0ffef17 ldw r3,-68(fp) + 8034330: 10c00615 stw r3,24(r2) + + /* extend options to aligned address */ + while(optlen & 0x03) + 8034334: 00000606 br 8034350 + tcp_optionbuf[optlen++] = TCPOPT_EOL; + 8034338: e0bffb17 ldw r2,-20(fp) + 803433c: 10c00044 addi r3,r2,1 + 8034340: e0fffb15 stw r3,-20(fp) + 8034344: d0e08804 addi r3,gp,-32224 + 8034348: 10c5883a add r2,r2,r3 + 803434c: 10000005 stb zero,0(r2) + while(optlen & 0x03) + 8034350: e0bffb17 ldw r2,-20(fp) + 8034354: 108000cc andi r2,r2,3 + 8034358: 103ff71e bne r2,zero,8034338 + + MEMCPY(mtod(mopt, char *), tcp_optionbuf, optlen); + 803435c: e0bfef17 ldw r2,-68(fp) + 8034360: 10800317 ldw r2,12(r2) + 8034364: e1bffb17 ldw r6,-20(fp) + 8034368: d1608804 addi r5,gp,-32224 + 803436c: 1009883a mov r4,r2 + 8034370: 80086b80 call 80086b8 + mopt->m_len = optlen; + 8034374: e0bfef17 ldw r2,-68(fp) + 8034378: e0fffb17 ldw r3,-20(fp) + 803437c: 10c00215 stw r3,8(r2) + /* use portable macro to set tcp data offset bits */ + SET_TH_OFF(ti->ti_t, ((sizeof (struct tcphdr) + optlen) >> 2)); + 8034380: e0bffb17 ldw r2,-20(fp) + 8034384: 10800504 addi r2,r2,20 + 8034388: 1004d0ba srli r2,r2,2 + 803438c: 1004913a slli r2,r2,4 + 8034390: 1007883a mov r3,r2 + 8034394: e0bff317 ldw r2,-52(fp) + 8034398: 10c00805 stb r3,32(r2) + } + + ti->ti_flags = (u_char)flags; + 803439c: e0bffd17 ldw r2,-12(fp) + 80343a0: 1007883a mov r3,r2 + 80343a4: e0bff317 ldw r2,-52(fp) + 80343a8: 10c00845 stb r3,33(r2) + /* + * Calculate receive window. Don't shrink window, + * but avoid silly window syndrome. + */ + if (win < (long)(so->so_rcv.sb_hiwat / 4) && win < (long)tp->t_maxseg) + 80343ac: e0bff717 ldw r2,-36(fp) + 80343b0: 10800b17 ldw r2,44(r2) + 80343b4: 1004d0ba srli r2,r2,2 + 80343b8: 1007883a mov r3,r2 + 80343bc: e0bffe17 ldw r2,-8(fp) + 80343c0: 10c0060e bge r2,r3,80343dc + 80343c4: e0bfea17 ldw r2,-88(fp) + 80343c8: 10800a0b ldhu r2,40(r2) + 80343cc: 10bfffcc andi r2,r2,65535 + 80343d0: e0fffe17 ldw r3,-8(fp) + 80343d4: 1880010e bge r3,r2,80343dc + win = 0; + 80343d8: e03ffe15 stw zero,-8(fp) + if (win < (long)(tp->rcv_adv - tp->rcv_nxt)) + 80343dc: e0bfea17 ldw r2,-88(fp) + 80343e0: 10c01917 ldw r3,100(r2) + 80343e4: e0bfea17 ldw r2,-88(fp) + 80343e8: 10801617 ldw r2,88(r2) + 80343ec: 1885c83a sub r2,r3,r2 + 80343f0: 1007883a mov r3,r2 + 80343f4: e0bffe17 ldw r2,-8(fp) + 80343f8: 10c0060e bge r2,r3,8034414 + win = (long)(tp->rcv_adv - tp->rcv_nxt); + 80343fc: e0bfea17 ldw r2,-88(fp) + 8034400: 10c01917 ldw r3,100(r2) + 8034404: e0bfea17 ldw r2,-88(fp) + 8034408: 10801617 ldw r2,88(r2) + 803440c: 1885c83a sub r2,r3,r2 + 8034410: e0bffe15 stw r2,-8(fp) + + /* do check for Iniche buffer limits -JB- */ + if (bigfreeq.q_len == 0) /* If queue length is 0, set window to 0 */ + 8034414: 008201b4 movhi r2,2054 + 8034418: 10b7dd17 ldw r2,-8332(r2) + 803441c: 1000021e bne r2,zero,8034428 + { + win = 0; + 8034420: e03ffe15 stw zero,-8(fp) + 8034424: 00000e06 br 8034460 + } + else if(win > (((long)bigfreeq.q_len - 1) * (long)bigbufsiz)) + 8034428: 008201b4 movhi r2,2054 + 803442c: 10b7dd17 ldw r2,-8332(r2) + 8034430: 10bfffc4 addi r2,r2,-1 + 8034434: d0e01917 ldw r3,-32668(gp) + 8034438: 10c7383a mul r3,r2,r3 + 803443c: e0bffe17 ldw r2,-8(fp) + 8034440: 1880070e bge r3,r2,8034460 + { + win = ((long)bigfreeq.q_len - 1) * bigbufsiz; + 8034444: 008201b4 movhi r2,2054 + 8034448: 10b7dd17 ldw r2,-8332(r2) + 803444c: 10bfffc4 addi r2,r2,-1 + 8034450: 1007883a mov r3,r2 + 8034454: d0a01917 ldw r2,-32668(gp) + 8034458: 1885383a mul r2,r3,r2 + 803445c: e0bffe15 stw r2,-8(fp) + ti->ti_win = htons((u_short)(win >> tp->rcv_wind_scale)); /* apply scale */ + } + else +#endif /* TCP_WIN_SCALE */ + { + ti->ti_win = htons((u_short)win); + 8034460: e0bffe17 ldw r2,-8(fp) + 8034464: 10bfffcc andi r2,r2,65535 + 8034468: 1004d23a srli r2,r2,8 + 803446c: 1007883a mov r3,r2 + 8034470: e0bffe17 ldw r2,-8(fp) + 8034474: 10bfffcc andi r2,r2,65535 + 8034478: 1004923a slli r2,r2,8 + 803447c: 1884b03a or r2,r3,r2 + 8034480: 1007883a mov r3,r2 + 8034484: e0bff317 ldw r2,-52(fp) + 8034488: 10c0088d sth r3,34(r2) + } + + if (SEQ_GT(tp->snd_up, tp->snd_nxt)) + 803448c: e0bfea17 ldw r2,-88(fp) + 8034490: 10c01017 ldw r3,64(r2) + 8034494: e0bfea17 ldw r2,-88(fp) + 8034498: 10800f17 ldw r2,60(r2) + 803449c: 1885c83a sub r2,r3,r2 + 80344a0: 00801c0e bge zero,r2,8034514 + { + ti->ti_urp = htons((u_short)(tp->snd_up - tp->snd_nxt)); + 80344a4: e0bfea17 ldw r2,-88(fp) + 80344a8: 10801017 ldw r2,64(r2) + 80344ac: 1007883a mov r3,r2 + 80344b0: e0bfea17 ldw r2,-88(fp) + 80344b4: 10800f17 ldw r2,60(r2) + 80344b8: 1885c83a sub r2,r3,r2 + 80344bc: 10bfffcc andi r2,r2,65535 + 80344c0: 1004d23a srli r2,r2,8 + 80344c4: 1007883a mov r3,r2 + 80344c8: e0bfea17 ldw r2,-88(fp) + 80344cc: 10801017 ldw r2,64(r2) + 80344d0: 1009883a mov r4,r2 + 80344d4: e0bfea17 ldw r2,-88(fp) + 80344d8: 10800f17 ldw r2,60(r2) + 80344dc: 2085c83a sub r2,r4,r2 + 80344e0: 10bfffcc andi r2,r2,65535 + 80344e4: 1004923a slli r2,r2,8 + 80344e8: 1884b03a or r2,r3,r2 + 80344ec: 1007883a mov r3,r2 + 80344f0: e0bff317 ldw r2,-52(fp) + 80344f4: 10c0098d sth r3,38(r2) + ti->ti_flags |= TH_URG; + 80344f8: e0bff317 ldw r2,-52(fp) + 80344fc: 10800843 ldbu r2,33(r2) + 8034500: 10800814 ori r2,r2,32 + 8034504: 1007883a mov r3,r2 + 8034508: e0bff317 ldw r2,-52(fp) + 803450c: 10c00845 stb r3,33(r2) + 8034510: 00000406 br 8034524 + * If no urgent pointer to send, then we pull + * the urgent pointer to the left edge of the send window + * so that it doesn't drift into the send window on sequence + * number wraparound. + */ + tp->snd_up = tp->snd_una; /* drag it along */ + 8034514: e0bfea17 ldw r2,-88(fp) + 8034518: 10c00e17 ldw r3,56(r2) + 803451c: e0bfea17 ldw r2,-88(fp) + 8034520: 10c01015 stw r3,64(r2) + /* + * If anything to send and we can send it all, set PUSH. + * (This will keep happy those implementations which only + * give data to the user when a buffer fills or a PUSH comes in.) + */ + if (len && off+len == (int)so->so_snd.sb_cc) + 8034524: e0bfff17 ldw r2,-4(fp) + 8034528: 10000c26 beq r2,zero,803455c + 803452c: e0fff517 ldw r3,-44(fp) + 8034530: e0bfff17 ldw r2,-4(fp) + 8034534: 1885883a add r2,r3,r2 + 8034538: e0fff717 ldw r3,-36(fp) + 803453c: 18c01217 ldw r3,72(r3) + 8034540: 10c0061e bne r2,r3,803455c + ti->ti_flags |= TH_PUSH; + 8034544: e0bff317 ldw r2,-52(fp) + 8034548: 10800843 ldbu r2,33(r2) + 803454c: 10800214 ori r2,r2,8 + 8034550: 1007883a mov r3,r2 + 8034554: e0bff317 ldw r2,-52(fp) + 8034558: 10c00845 stb r3,33(r2) + + /* + * In transmit state, time the transmission and arrange for + * the retransmit. In persist state, just set snd_max. + */ + if (tp->t_force == 0 || tp->t_timer[TCPT_PERSIST] == 0) + 803455c: e0bfea17 ldw r2,-88(fp) + 8034560: 10800a83 ldbu r2,42(r2) + 8034564: 10803fcc andi r2,r2,255 + 8034568: 1080201c xori r2,r2,128 + 803456c: 10bfe004 addi r2,r2,-128 + 8034570: 10000326 beq r2,zero,8034580 + 8034574: e0bfea17 ldw r2,-88(fp) + 8034578: 10800417 ldw r2,16(r2) + 803457c: 10004b1e bne r2,zero,80346ac + { + tcp_seq startseq = tp->snd_nxt; + 8034580: e0bfea17 ldw r2,-88(fp) + 8034584: 10800f17 ldw r2,60(r2) + 8034588: e0bfee15 stw r2,-72(fp) + + /* + * Advance snd_nxt over sequence space of this segment. + */ + if (flags & TH_SYN) + 803458c: e0bffd17 ldw r2,-12(fp) + 8034590: 1080008c andi r2,r2,2 + 8034594: 10000526 beq r2,zero,80345ac + tp->snd_nxt++; + 8034598: e0bfea17 ldw r2,-88(fp) + 803459c: 10800f17 ldw r2,60(r2) + 80345a0: 10c00044 addi r3,r2,1 + 80345a4: e0bfea17 ldw r2,-88(fp) + 80345a8: 10c00f15 stw r3,60(r2) + + if (flags & TH_FIN) + 80345ac: e0bffd17 ldw r2,-12(fp) + 80345b0: 1080004c andi r2,r2,1 + 80345b4: 10000b26 beq r2,zero,80345e4 + { + tp->snd_nxt++; + 80345b8: e0bfea17 ldw r2,-88(fp) + 80345bc: 10800f17 ldw r2,60(r2) + 80345c0: 10c00044 addi r3,r2,1 + 80345c4: e0bfea17 ldw r2,-88(fp) + 80345c8: 10c00f15 stw r3,60(r2) + tp->t_flags |= TF_SENTFIN; + 80345cc: e0bfea17 ldw r2,-88(fp) + 80345d0: 10800b0b ldhu r2,44(r2) + 80345d4: 10800414 ori r2,r2,16 + 80345d8: 1007883a mov r3,r2 + 80345dc: e0bfea17 ldw r2,-88(fp) + 80345e0: 10c00b0d sth r3,44(r2) + } + tp->snd_nxt += len; + 80345e4: e0bfea17 ldw r2,-88(fp) + 80345e8: 10c00f17 ldw r3,60(r2) + 80345ec: e0bfff17 ldw r2,-4(fp) + 80345f0: 1887883a add r3,r3,r2 + 80345f4: e0bfea17 ldw r2,-88(fp) + 80345f8: 10c00f15 stw r3,60(r2) + if (SEQ_GT(tp->snd_nxt, tp->snd_max)) + 80345fc: e0bfea17 ldw r2,-88(fp) + 8034600: 10c00f17 ldw r3,60(r2) + 8034604: e0bfea17 ldw r2,-88(fp) + 8034608: 10801a17 ldw r2,104(r2) + 803460c: 1885c83a sub r2,r3,r2 + 8034610: 0080120e bge zero,r2,803465c + { + tp->snd_max = tp->snd_nxt; + 8034614: e0bfea17 ldw r2,-88(fp) + 8034618: 10c00f17 ldw r3,60(r2) + 803461c: e0bfea17 ldw r2,-88(fp) + 8034620: 10c01a15 stw r3,104(r2) + /* + * Time this transmission if not a retransmission and + * not currently timing anything. + */ + if (tp->t_rttick == 0) + 8034624: e0bfea17 ldw r2,-88(fp) + 8034628: 10801e17 ldw r2,120(r2) + 803462c: 10000b1e bne r2,zero,803465c + { + tp->t_rttick = cticks; + 8034630: d0e07d17 ldw r3,-32268(gp) + 8034634: e0bfea17 ldw r2,-88(fp) + 8034638: 10c01e15 stw r3,120(r2) + tp->t_rtseq = startseq; + 803463c: e0bfea17 ldw r2,-88(fp) + 8034640: e0ffee17 ldw r3,-72(fp) + 8034644: 10c01f15 stw r3,124(r2) + tcpstat.tcps_segstimed++; + 8034648: 008201b4 movhi r2,2054 + 803464c: 10b8aa17 ldw r2,-7512(r2) + 8034650: 10c00044 addi r3,r2,1 + 8034654: 008201b4 movhi r2,2054 + 8034658: 10f8aa15 stw r3,-7512(r2) + * Initial value for retransmit timer is smoothed + * round-trip time + 2 * round-trip time variance. + * Initialize shift counter which is used for backoff + * of retransmit time. + */ + if (tp->t_timer[TCPT_REXMT] == 0 && + 803465c: e0bfea17 ldw r2,-88(fp) + 8034660: 10800317 ldw r2,12(r2) + 8034664: 1000201e bne r2,zero,80346e8 + tp->snd_nxt != tp->snd_una) + 8034668: e0bfea17 ldw r2,-88(fp) + 803466c: 10c00f17 ldw r3,60(r2) + 8034670: e0bfea17 ldw r2,-88(fp) + 8034674: 10800e17 ldw r2,56(r2) + if (tp->t_timer[TCPT_REXMT] == 0 && + 8034678: 18801b26 beq r3,r2,80346e8 + { + tp->t_timer[TCPT_REXMT] = tp->t_rxtcur; + 803467c: e0bfea17 ldw r2,-88(fp) + 8034680: 10c00817 ldw r3,32(r2) + 8034684: e0bfea17 ldw r2,-88(fp) + 8034688: 10c00315 stw r3,12(r2) + if (tp->t_timer[TCPT_PERSIST]) + 803468c: e0bfea17 ldw r2,-88(fp) + 8034690: 10800417 ldw r2,16(r2) + 8034694: 10001426 beq r2,zero,80346e8 + { + tp->t_timer[TCPT_PERSIST] = 0; + 8034698: e0bfea17 ldw r2,-88(fp) + 803469c: 10000415 stw zero,16(r2) + tp->t_rxtshift = 0; + 80346a0: e0bfea17 ldw r2,-88(fp) + 80346a4: 10000715 stw zero,28(r2) + { + 80346a8: 00000f06 br 80346e8 + } + } + } + else + { + if (SEQ_GT(tp->snd_nxt + len, tp->snd_max)) + 80346ac: e0bfea17 ldw r2,-88(fp) + 80346b0: 10c00f17 ldw r3,60(r2) + 80346b4: e0bfff17 ldw r2,-4(fp) + 80346b8: 1887883a add r3,r3,r2 + 80346bc: e0bfea17 ldw r2,-88(fp) + 80346c0: 10801a17 ldw r2,104(r2) + 80346c4: 1885c83a sub r2,r3,r2 + 80346c8: 0080080e bge zero,r2,80346ec + tp->snd_max = tp->snd_nxt + len; + 80346cc: e0bfea17 ldw r2,-88(fp) + 80346d0: 10c00f17 ldw r3,60(r2) + 80346d4: e0bfff17 ldw r2,-4(fp) + 80346d8: 1887883a add r3,r3,r2 + 80346dc: e0bfea17 ldw r2,-88(fp) + 80346e0: 10c01a15 stw r3,104(r2) + 80346e4: 00000106 br 80346ec + { + 80346e8: 0001883a nop + tcp_trace("tcp_output: sending, state %d, tcpcb: %x", + tp->t_state, tp ); +#endif + +#ifdef MUTE_WARNS + error = 0; + 80346ec: e03fed15 stw zero,-76(fp) + if(so->so_domain != AF_INET6) +#endif /* IP_V6 */ + { + struct ip * pip; + + pip = mtod(m, struct ip *); + 80346f0: e0bffc17 ldw r2,-16(fp) + 80346f4: 10800317 ldw r2,12(r2) + 80346f8: e0bfec15 stw r2,-80(fp) + /* Fill in IP length and send to IP level. */ + pip->ip_len = (u_short)(TCPIPHDRSZ + optlen + len); + 80346fc: e0bffb17 ldw r2,-20(fp) + 8034700: 1007883a mov r3,r2 + 8034704: e0bfff17 ldw r2,-4(fp) + 8034708: 1885883a add r2,r3,r2 + 803470c: 10800a04 addi r2,r2,40 + 8034710: 1007883a mov r3,r2 + 8034714: e0bfec17 ldw r2,-80(fp) + 8034718: 10c0008d sth r3,2(r2) + error = ip_output(m, so->so_optsPack); + 803471c: e0bff717 ldw r2,-36(fp) + 8034720: 10801f17 ldw r2,124(r2) + 8034724: 100b883a mov r5,r2 + 8034728: e13ffc17 ldw r4,-16(fp) + 803472c: 802a6580 call 802a658 + 8034730: e0bfed15 stw r2,-76(fp) + (sizeof(struct ipv6) + sizeof(struct tcphdr) + optlen + len), + (struct ip_socopts *)0); + } +#endif /* IP_V6 */ + + if (error) + 8034734: e0bfed17 ldw r2,-76(fp) + 8034738: 10001326 beq r2,zero,8034788 + { + if (error == ENOBUFS) /* ip_output needed a copy buffer it couldn't get */ + 803473c: e0bfed17 ldw r2,-76(fp) + 8034740: 10801a58 cmpnei r2,r2,105 + 8034744: 10000e1e bne r2,zero,8034780 + { + if (m->m_type == MT_FREE) /* ip_output() probably freed first mbuf */ + 8034748: e0bffc17 ldw r2,-16(fp) + 803474c: 10800817 ldw r2,32(r2) + 8034750: 1000031e bne r2,zero,8034760 + m = m->m_next; + 8034754: e0bffc17 ldw r2,-16(fp) + 8034758: 10800617 ldw r2,24(r2) + 803475c: e0bffc15 stw r2,-16(fp) + m_freem(m); /* free the mbuf chain */ + 8034760: e13ffc17 ldw r4,-16(fp) + 8034764: 8029cfc0 call 8029cfc + tcp_quench(tp->t_inpcb); + 8034768: e0bfea17 ldw r2,-88(fp) + 803476c: 10800d17 ldw r2,52(r2) + 8034770: 1009883a mov r4,r2 + 8034774: 80351d00 call 80351d0 + return (error); + 8034778: e0bfed17 ldw r2,-76(fp) + 803477c: 00002706 br 803481c + } + return (error); + 8034780: e0bfed17 ldw r2,-76(fp) + 8034784: 00002506 br 803481c + + /* + * Data sent (as far as we can tell). + */ + + TCP_MIB_INC(tcpOutSegs); /* keep MIB stats */ + 8034788: 008201b4 movhi r2,2054 + 803478c: 10b88017 ldw r2,-7680(r2) + 8034790: 10c00044 addi r3,r2,1 + 8034794: 008201b4 movhi r2,2054 + 8034798: 10f88015 stw r3,-7680(r2) + tcpstat.tcps_sndtotal++; + 803479c: 008201b4 movhi r2,2054 + 80347a0: 10b8b317 ldw r2,-7476(r2) + 80347a4: 10c00044 addi r3,r2,1 + 80347a8: 008201b4 movhi r2,2054 + 80347ac: 10f8b315 stw r3,-7476(r2) + /* + * If this advertises a larger window than any other segment, + * then remember the size of the advertised window. + * Any pending ACK has now been sent. + */ + if (win > 0 && SEQ_GT(tp->rcv_nxt+win, tp->rcv_adv)) + 80347b0: e0bffe17 ldw r2,-8(fp) + 80347b4: 00800e0e bge zero,r2,80347f0 + 80347b8: e0bfea17 ldw r2,-88(fp) + 80347bc: 10c01617 ldw r3,88(r2) + 80347c0: e0bffe17 ldw r2,-8(fp) + 80347c4: 1887883a add r3,r3,r2 + 80347c8: e0bfea17 ldw r2,-88(fp) + 80347cc: 10801917 ldw r2,100(r2) + 80347d0: 1885c83a sub r2,r3,r2 + 80347d4: 0080060e bge zero,r2,80347f0 + tp->rcv_adv = tp->rcv_nxt + (unsigned)win; + 80347d8: e0bfea17 ldw r2,-88(fp) + 80347dc: 10c01617 ldw r3,88(r2) + 80347e0: e0bffe17 ldw r2,-8(fp) + 80347e4: 1887883a add r3,r3,r2 + 80347e8: e0bfea17 ldw r2,-88(fp) + 80347ec: 10c01915 stw r3,100(r2) + tp->t_flags &= ~(TF_ACKNOW|TF_SACKNOW|TF_DELACK); + 80347f0: e0bfea17 ldw r2,-88(fp) + 80347f4: 10c00b0b ldhu r3,44(r2) + 80347f8: 00bfef04 movi r2,-68 + 80347fc: 1884703a and r2,r3,r2 + 8034800: 1007883a mov r3,r2 + 8034804: e0bfea17 ldw r2,-88(fp) + 8034808: 10c00b0d sth r3,44(r2) + if (sendalot) + 803480c: e0bffa17 ldw r2,-24(fp) + 8034810: 10000126 beq r2,zero,8034818 + goto again; + 8034814: 003c3006 br 80338d8 + return (0); + 8034818: 0005883a mov r2,zero +} + 803481c: e037883a mov sp,fp + 8034820: dfc00117 ldw ra,4(sp) + 8034824: df000017 ldw fp,0(sp) + 8034828: dec00204 addi sp,sp,8 + 803482c: f800283a ret + +08034830 : + * RETURNS: NA + */ + +void +tcp_setpersist(struct tcpcb * tp) +{ + 8034830: defffc04 addi sp,sp,-16 + 8034834: dfc00315 stw ra,12(sp) + 8034838: df000215 stw fp,8(sp) + 803483c: df000204 addi fp,sp,8 + 8034840: e13ffe15 stw r4,-8(fp) + int t; + + t = ((tp->t_srtt >> 2) + tp->t_rttvar) >> 1; + 8034844: e0bffe17 ldw r2,-8(fp) + 8034848: 10802017 ldw r2,128(r2) + 803484c: 1007d0ba srai r3,r2,2 + 8034850: e0bffe17 ldw r2,-8(fp) + 8034854: 10802117 ldw r2,132(r2) + 8034858: 1885883a add r2,r3,r2 + 803485c: 1005d07a srai r2,r2,1 + 8034860: e0bfff15 stw r2,-4(fp) + + if (tp->t_timer[TCPT_REXMT]) + 8034864: e0bffe17 ldw r2,-8(fp) + 8034868: 10800317 ldw r2,12(r2) + 803486c: 10000326 beq r2,zero,803487c + panic("tcp_output REXMT"); + 8034870: 01020174 movhi r4,2053 + 8034874: 212aad04 addi r4,r4,-21836 + 8034878: 80271780 call 8027178 + /* + * Start/restart persistance timer. + */ + TCPT_RANGESET(tp->t_timer[TCPT_PERSIST], + 803487c: e0bfff17 ldw r2,-4(fp) + 8034880: 1009883a mov r4,r2 + 8034884: e0bffe17 ldw r2,-8(fp) + 8034888: 10c00717 ldw r3,28(r2) + 803488c: 00820174 movhi r2,2053 + 8034890: 1885883a add r2,r3,r2 + 8034894: 10b20cc3 ldbu r2,-14285(r2) + 8034898: 10803fcc andi r2,r2,255 + 803489c: 2085383a mul r2,r4,r2 + 80348a0: 10ffffcc andi r3,r2,65535 + 80348a4: 18e0001c xori r3,r3,32768 + 80348a8: 18e00004 addi r3,r3,-32768 + 80348ac: e0bffe17 ldw r2,-8(fp) + 80348b0: 10c00415 stw r3,16(r2) + 80348b4: e0bffe17 ldw r2,-8(fp) + 80348b8: 10800417 ldw r2,16(r2) + 80348bc: 10800288 cmpgei r2,r2,10 + 80348c0: 1000041e bne r2,zero,80348d4 + 80348c4: e0bffe17 ldw r2,-8(fp) + 80348c8: 00c00284 movi r3,10 + 80348cc: 10c00415 stw r3,16(r2) + 80348d0: 00000706 br 80348f0 + 80348d4: e0bffe17 ldw r2,-8(fp) + 80348d8: 10800417 ldw r2,16(r2) + 80348dc: 10801e50 cmplti r2,r2,121 + 80348e0: 1000031e bne r2,zero,80348f0 + 80348e4: e0bffe17 ldw r2,-8(fp) + 80348e8: 00c01e04 movi r3,120 + 80348ec: 10c00415 stw r3,16(r2) + t * tcp_backoff[tp->t_rxtshift], + TCPTV_PERSMIN, TCPTV_PERSMAX); + if (tp->t_rxtshift < TCP_MAXRXTSHIFT) + 80348f0: e0bffe17 ldw r2,-8(fp) + 80348f4: 10800717 ldw r2,28(r2) + 80348f8: 10800308 cmpgei r2,r2,12 + 80348fc: 1000051e bne r2,zero,8034914 + tp->t_rxtshift++; + 8034900: e0bffe17 ldw r2,-8(fp) + 8034904: 10800717 ldw r2,28(r2) + 8034908: 10c00044 addi r3,r2,1 + 803490c: e0bffe17 ldw r2,-8(fp) + 8034910: 10c00715 stw r3,28(r2) + +} + 8034914: 0001883a nop + 8034918: e037883a mov sp,fp + 803491c: dfc00117 ldw ra,4(sp) + 8034920: df000017 ldw fp,0(sp) + 8034924: dec00204 addi sp,sp,8 + 8034928: f800283a ret + +0803492c : + * RETURNS: length of option data added to buffer + */ + +static int +bld_options(struct tcpcb * tp, u_char * cp, int flags, struct socket * so) +{ + 803492c: defff804 addi sp,sp,-32 + 8034930: dfc00715 stw ra,28(sp) + 8034934: df000615 stw fp,24(sp) + 8034938: df000604 addi fp,sp,24 + 803493c: e13ffd15 stw r4,-12(fp) + 8034940: e17ffc15 stw r5,-16(fp) + 8034944: e1bffb15 stw r6,-20(fp) + 8034948: e1fffa15 stw r7,-24(fp) + int len; + u_short mss; + + if(tp->t_flags & TF_NOOPT) /* no options allowed? */ + 803494c: e0bffd17 ldw r2,-12(fp) + 8034950: 10800b0b ldhu r2,44(r2) + 8034954: 10bfffcc andi r2,r2,65535 + 8034958: 1080020c andi r2,r2,8 + 803495c: 10000226 beq r2,zero,8034968 + return 0; + 8034960: 0005883a mov r2,zero + 8034964: 00001f06 br 80349e4 + + /* Alway put MSS option on SYN packets */ + if (flags & TH_SYN) + 8034968: e0bffb17 ldw r2,-20(fp) + 803496c: 1080008c andi r2,r2,2 + 8034970: 10001a26 beq r2,zero,80349dc + { + mss = (u_short)tcp_mss(so); + 8034974: e13ffa17 ldw r4,-24(fp) + 8034978: 803379c0 call 803379c + 803497c: e0bffe8d sth r2,-6(fp) + + /* always send MSS option on SYN, fill in MSS parm */ + *(cp + 0) = TCPOPT_MAXSEG; + 8034980: e0bffc17 ldw r2,-16(fp) + 8034984: 00c00084 movi r3,2 + 8034988: 10c00005 stb r3,0(r2) + *(cp + 1) = MSSOPT_LEN; /* length byte */ + 803498c: e0bffc17 ldw r2,-16(fp) + 8034990: 10800044 addi r2,r2,1 + 8034994: 00c00104 movi r3,4 + 8034998: 10c00005 stb r3,0(r2) + *(cp + 2) = (u_char) ((mss & 0xff00) >> 8); + 803499c: e0bffe8b ldhu r2,-6(fp) + 80349a0: 1004d23a srli r2,r2,8 + 80349a4: 1007883a mov r3,r2 + 80349a8: e0bffc17 ldw r2,-16(fp) + 80349ac: 10800084 addi r2,r2,2 + 80349b0: 10c00005 stb r3,0(r2) + *(cp + 3) = (u_char) (mss & 0xff); + 80349b4: e0bffc17 ldw r2,-16(fp) + 80349b8: 108000c4 addi r2,r2,3 + 80349bc: e0fffe8b ldhu r3,-6(fp) + 80349c0: 10c00005 stb r3,0(r2) + len = 4; + 80349c4: 00800104 movi r2,4 + 80349c8: e0bfff15 stw r2,-4(fp) + cp += 4; + 80349cc: e0bffc17 ldw r2,-16(fp) + 80349d0: 10800104 addi r2,r2,4 + 80349d4: e0bffc15 stw r2,-16(fp) + 80349d8: 00000106 br 80349e0 + } + else + len = 0; + 80349dc: e03fff15 stw zero,-4(fp) + len += 10; + } +#endif /* TCP_TIMESTAMP */ + + USE_ARG(so); + return len; + 80349e0: e0bfff17 ldw r2,-4(fp) +} + 80349e4: e037883a mov sp,fp + 80349e8: dfc00117 ldw ra,4(sp) + 80349ec: df000017 ldw fp,0(sp) + 80349f0: dec00204 addi sp,sp,8 + 80349f4: f800283a ret + +080349f8 : + * RETURNS: + */ + +void +tcp_init() +{ + 80349f8: deffff04 addi sp,sp,-4 + 80349fc: df000015 stw fp,0(sp) + 8034a00: d839883a mov fp,sp + tcp_iss = 1; /* wrong */ + 8034a04: 00800044 movi r2,1 + 8034a08: d0a08a15 stw r2,-32216(gp) + tcb.inp_next = tcb.inp_prev = &tcb; + 8034a0c: 008201b4 movhi r2,2054 + 8034a10: 10b89904 addi r2,r2,-7580 + 8034a14: 00c201b4 movhi r3,2054 + 8034a18: 18b89a15 stw r2,-7576(r3) + 8034a1c: 008201b4 movhi r2,2054 + 8034a20: 10f89a17 ldw r3,-7576(r2) + 8034a24: 008201b4 movhi r2,2054 + 8034a28: 10f89915 stw r3,-7580(r2) +} + 8034a2c: 0001883a nop + 8034a30: e037883a mov sp,fp + 8034a34: df000017 ldw fp,0(sp) + 8034a38: dec00104 addi sp,sp,4 + 8034a3c: f800283a ret + +08034a40 : + * RETURNS: + */ + +struct tcpiphdr * +tcp_template(struct tcpcb * tp) +{ + 8034a40: defffb04 addi sp,sp,-20 + 8034a44: dfc00415 stw ra,16(sp) + 8034a48: df000315 stw fp,12(sp) + 8034a4c: df000304 addi fp,sp,12 + 8034a50: e13ffd15 stw r4,-12(fp) + struct inpcb * inp = tp->t_inpcb; + 8034a54: e0bffd17 ldw r2,-12(fp) + 8034a58: 10800d17 ldw r2,52(r2) + 8034a5c: e0bffe15 stw r2,-8(fp) + struct tcpiphdr * n; + + if ((n = tp->t_template) == 0) + 8034a60: e0bffd17 ldw r2,-12(fp) + 8034a64: 10800c17 ldw r2,48(r2) + 8034a68: e0bfff15 stw r2,-4(fp) + 8034a6c: e0bfff17 ldw r2,-4(fp) + 8034a70: 1000071e bne r2,zero,8034a90 + { + n = (struct tcpiphdr *)TPH_ALLOC (sizeof (*n)); + 8034a74: 01000a04 movi r4,40 + 8034a78: 802982c0 call 802982c + 8034a7c: e0bfff15 stw r2,-4(fp) + if (n == NULL) + 8034a80: e0bfff17 ldw r2,-4(fp) + 8034a84: 1000021e bne r2,zero,8034a90 + return (0); + 8034a88: 0005883a mov r2,zero + 8034a8c: 00002906 br 8034b34 + } + n->ti_next = n->ti_prev = 0; + 8034a90: e0bfff17 ldw r2,-4(fp) + 8034a94: 10000115 stw zero,4(r2) + 8034a98: e0bfff17 ldw r2,-4(fp) + 8034a9c: 10c00117 ldw r3,4(r2) + 8034aa0: e0bfff17 ldw r2,-4(fp) + 8034aa4: 10c00015 stw r3,0(r2) + n->ti_len = htons(sizeof (struct tcpiphdr) - sizeof (struct ip)); + 8034aa8: e0bfff17 ldw r2,-4(fp) + 8034aac: 00c50004 movi r3,5120 + 8034ab0: 10c0028d sth r3,10(r2) + n->ti_src = inp->inp_laddr; + 8034ab4: e0bfff17 ldw r2,-4(fp) + 8034ab8: e0fffe17 ldw r3,-8(fp) + 8034abc: 18c00417 ldw r3,16(r3) + 8034ac0: 10c00315 stw r3,12(r2) + n->ti_dst = inp->inp_faddr; + 8034ac4: e0bfff17 ldw r2,-4(fp) + 8034ac8: e0fffe17 ldw r3,-8(fp) + 8034acc: 18c00317 ldw r3,12(r3) + 8034ad0: 10c00415 stw r3,16(r2) + n->ti_sport = inp->inp_lport; + 8034ad4: e0bffe17 ldw r2,-8(fp) + 8034ad8: 10c0078b ldhu r3,30(r2) + 8034adc: e0bfff17 ldw r2,-4(fp) + 8034ae0: 10c0050d sth r3,20(r2) + n->ti_dport = inp->inp_fport; + 8034ae4: e0bffe17 ldw r2,-8(fp) + 8034ae8: 10c0070b ldhu r3,28(r2) + 8034aec: e0bfff17 ldw r2,-4(fp) + 8034af0: 10c0058d sth r3,22(r2) + n->ti_seq = 0; + 8034af4: e0bfff17 ldw r2,-4(fp) + 8034af8: 10000615 stw zero,24(r2) + n->ti_ack = 0; + 8034afc: e0bfff17 ldw r2,-4(fp) + 8034b00: 10000715 stw zero,28(r2) + n->ti_t.th_doff = (5 << 4); /* NetPort */ + 8034b04: e0bfff17 ldw r2,-4(fp) + 8034b08: 00c01404 movi r3,80 + 8034b0c: 10c00805 stb r3,32(r2) + n->ti_flags = 0; + 8034b10: e0bfff17 ldw r2,-4(fp) + 8034b14: 10000845 stb zero,33(r2) + n->ti_win = 0; + 8034b18: e0bfff17 ldw r2,-4(fp) + 8034b1c: 1000088d sth zero,34(r2) + n->ti_sum = 0; + 8034b20: e0bfff17 ldw r2,-4(fp) + 8034b24: 1000090d sth zero,36(r2) + n->ti_urp = 0; + 8034b28: e0bfff17 ldw r2,-4(fp) + 8034b2c: 1000098d sth zero,38(r2) + return (n); + 8034b30: e0bfff17 ldw r2,-4(fp) +} + 8034b34: e037883a mov sp,fp + 8034b38: dfc00117 ldw ra,4(sp) + 8034b3c: df000017 ldw fp,0(sp) + 8034b40: dec00204 addi sp,sp,8 + 8034b44: f800283a ret + +08034b48 : + struct tcpiphdr * ti, + tcp_seq ack, + tcp_seq seq, + int flags, + struct mbuf * ti_mbuf) +{ + 8034b48: defff204 addi sp,sp,-56 + 8034b4c: dfc00d15 stw ra,52(sp) + 8034b50: df000c15 stw fp,48(sp) + 8034b54: df000c04 addi fp,sp,48 + 8034b58: e13ff715 stw r4,-36(fp) + 8034b5c: e17ff615 stw r5,-40(fp) + 8034b60: e1bff515 stw r6,-44(fp) + 8034b64: e1fff415 stw r7,-48(fp) + int tlen; /* tcp data len - 0 or 1 */ + int domain; /* AF_INET or AF_INET6 */ + int win = 0; /* window to use in sent packet */ + 8034b68: e03ffd15 stw zero,-12(fp) + struct mbuf * m; /* mbuf to send */ + struct tcpiphdr * tmp_thdr; /* scratch */ + + if (tp) + 8034b6c: e0bff717 ldw r2,-36(fp) + 8034b70: 10001726 beq r2,zero,8034bd0 + win = (int)sbspace(&tp->t_inpcb->inp_socket->so_rcv); + 8034b74: e0bff717 ldw r2,-36(fp) + 8034b78: 10800d17 ldw r2,52(r2) + 8034b7c: 10800817 ldw r2,32(r2) + 8034b80: 10800b17 ldw r2,44(r2) + 8034b84: 1007883a mov r3,r2 + 8034b88: e0bff717 ldw r2,-36(fp) + 8034b8c: 10800d17 ldw r2,52(r2) + 8034b90: 10800817 ldw r2,32(r2) + 8034b94: 10800a17 ldw r2,40(r2) + 8034b98: 1885c83a sub r2,r3,r2 + 8034b9c: 10000a16 blt r2,zero,8034bc8 + 8034ba0: e0bff717 ldw r2,-36(fp) + 8034ba4: 10800d17 ldw r2,52(r2) + 8034ba8: 10800817 ldw r2,32(r2) + 8034bac: 10c00b17 ldw r3,44(r2) + 8034bb0: e0bff717 ldw r2,-36(fp) + 8034bb4: 10800d17 ldw r2,52(r2) + 8034bb8: 10800817 ldw r2,32(r2) + 8034bbc: 10800a17 ldw r2,40(r2) + 8034bc0: 1885c83a sub r2,r3,r2 + 8034bc4: 00000106 br 8034bcc + 8034bc8: 0005883a mov r2,zero + 8034bcc: e0bffd15 stw r2,-12(fp) + + /* Figure out of we can recycle the passed buffer or if we need a + * new one. Construct the easy parts of the the TCP and IP headers. + */ + if (flags == 0) /* sending keepalive from timer */ + 8034bd0: e0800217 ldw r2,8(fp) + 8034bd4: 1000261e bne r2,zero,8034c70 + { + /* no flags == need a new buffer */ + m = m_getwithdata (MT_HEADER, 64); + 8034bd8: 01401004 movi r5,64 + 8034bdc: 010000c4 movi r4,3 + 8034be0: 8029a700 call 8029a70 + 8034be4: e0bffc15 stw r2,-16(fp) + if (m == NULL) + 8034be8: e0bffc17 ldw r2,-16(fp) + 8034bec: 1000ce26 beq r2,zero,8034f28 + return; + tlen = 1; /* Keepalives have one byte of data */ + 8034bf0: 00800044 movi r2,1 + 8034bf4: e0bfff15 stw r2,-4(fp) + m->m_len = TCPIPHDRSZ + tlen; + 8034bf8: e0bfff17 ldw r2,-4(fp) + 8034bfc: 10800a04 addi r2,r2,40 + 8034c00: 1007883a mov r3,r2 + 8034c04: e0bffc17 ldw r2,-16(fp) + 8034c08: 10c00215 stw r3,8(r2) + /* + * Copy template contents into the mbuf and set ti to point + * to the header structure in the mbuf. + */ + tmp_thdr = (struct tcpiphdr *)((char *)m->m_data+sizeof(struct ip) + 8034c0c: e0bffc17 ldw r2,-16(fp) + 8034c10: 10800317 ldw r2,12(r2) + 8034c14: e0bffb15 stw r2,-20(fp) + - sizeof(struct ipovly)); + if ((char *)tmp_thdr < m->pkt->nb_buff) + 8034c18: e0bffc17 ldw r2,-16(fp) + 8034c1c: 10800117 ldw r2,4(r2) + 8034c20: 10800117 ldw r2,4(r2) + 8034c24: e0fffb17 ldw r3,-20(fp) + 8034c28: 1880032e bgeu r3,r2,8034c38 + { + panic("tcp_respond- packet ptr underflow\n"); + 8034c2c: 01020174 movhi r4,2053 + 8034c30: 212ab204 addi r4,r4,-21816 + 8034c34: 80271780 call 8027178 + } + MEMCPY(tmp_thdr, ti, sizeof(struct tcpiphdr)); + 8034c38: 01800a04 movi r6,40 + 8034c3c: e17ff617 ldw r5,-40(fp) + 8034c40: e13ffb17 ldw r4,-20(fp) + 8034c44: 80086b80 call 80086b8 + ti = tmp_thdr; + 8034c48: e0bffb17 ldw r2,-20(fp) + 8034c4c: e0bff615 stw r2,-40(fp) + flags = TH_ACK; + 8034c50: 00800404 movi r2,16 + 8034c54: e0800215 stw r2,8(fp) + domain = tp->t_inpcb->inp_socket->so_domain; + 8034c58: e0bff717 ldw r2,-36(fp) + 8034c5c: 10800d17 ldw r2,52(r2) + 8034c60: 10800817 ldw r2,32(r2) + 8034c64: 10800517 ldw r2,20(r2) + 8034c68: e0bffe15 stw r2,-8(fp) + 8034c6c: 00003906 br 8034d54 + } + else /* Flag was passed (e.g. reset); recycle passed mbuf */ + { + m = ti_mbuf; /*dtom(ti);*/ + 8034c70: e0800317 ldw r2,12(fp) + 8034c74: e0bffc15 stw r2,-16(fp) + if(m->pkt->type == IPTP) /* IPv4 packet */ + 8034c78: e0bffc17 ldw r2,-16(fp) + 8034c7c: 10800117 ldw r2,4(r2) + 8034c80: 1080080b ldhu r2,32(r2) + 8034c84: 10bfffcc andi r2,r2,65535 + 8034c88: 10800218 cmpnei r2,r2,8 + 8034c8c: 1000031e bne r2,zero,8034c9c + domain = AF_INET; + 8034c90: 00800084 movi r2,2 + 8034c94: e0bffe15 stw r2,-8(fp) + 8034c98: 00000206 br 8034ca4 + else + domain = AF_INET6; + 8034c9c: 008000c4 movi r2,3 + 8034ca0: e0bffe15 stw r2,-8(fp) + + m_freem(m->m_next); + 8034ca4: e0bffc17 ldw r2,-16(fp) + 8034ca8: 10800617 ldw r2,24(r2) + 8034cac: 1009883a mov r4,r2 + 8034cb0: 8029cfc0 call 8029cfc + m->m_next = 0; + 8034cb4: e0bffc17 ldw r2,-16(fp) + 8034cb8: 10000615 stw zero,24(r2) + tlen = 0; /* NO data */ + 8034cbc: e03fff15 stw zero,-4(fp) + m->m_len = TCPIPHDRSZ; + 8034cc0: e0bffc17 ldw r2,-16(fp) + 8034cc4: 00c00a04 movi r3,40 + 8034cc8: 10c00215 stw r3,8(r2) + xchg(ti->ti_dport, ti->ti_sport, u_short); + 8034ccc: e0bff617 ldw r2,-40(fp) + 8034cd0: 1080058b ldhu r2,22(r2) + 8034cd4: e0bffa8d sth r2,-22(fp) + 8034cd8: e0bff617 ldw r2,-40(fp) + 8034cdc: 10c0050b ldhu r3,20(r2) + 8034ce0: e0bff617 ldw r2,-40(fp) + 8034ce4: 10c0058d sth r3,22(r2) + 8034ce8: e0bff617 ldw r2,-40(fp) + 8034cec: e0fffa8b ldhu r3,-22(fp) + 8034cf0: 10c0050d sth r3,20(r2) + if(m->pkt->type == IPTP) + 8034cf4: e0bffc17 ldw r2,-16(fp) + 8034cf8: 10800117 ldw r2,4(r2) + 8034cfc: 1080080b ldhu r2,32(r2) + 8034d00: 10bfffcc andi r2,r2,65535 + 8034d04: 10800218 cmpnei r2,r2,8 + 8034d08: 10000a1e bne r2,zero,8034d34 + xchg(ti->ti_dst.s_addr, ti->ti_src.s_addr, u_long); + 8034d0c: e0bff617 ldw r2,-40(fp) + 8034d10: 10800417 ldw r2,16(r2) + 8034d14: e0bff915 stw r2,-28(fp) + 8034d18: e0bff617 ldw r2,-40(fp) + 8034d1c: 10c00317 ldw r3,12(r2) + 8034d20: e0bff617 ldw r2,-40(fp) + 8034d24: 10c00415 stw r3,16(r2) + 8034d28: e0bff617 ldw r2,-40(fp) + 8034d2c: e0fff917 ldw r3,-28(fp) + 8034d30: 10c00315 stw r3,12(r2) + if (flags & TH_RST) /* count resets in MIB */ + 8034d34: e0800217 ldw r2,8(fp) + 8034d38: 1080010c andi r2,r2,4 + 8034d3c: 10000526 beq r2,zero,8034d54 + TCP_MIB_INC(tcpOutRsts); /* keep MIB stats */ + 8034d40: 008201b4 movhi r2,2054 + 8034d44: 10b88417 ldw r2,-7664(r2) + 8034d48: 10c00044 addi r3,r2,1 + 8034d4c: 008201b4 movhi r2,2054 + 8034d50: 10f88415 stw r3,-7664(r2) + } + + /* finish constructing the TCP header */ + ti->ti_seq = htonl(seq); + 8034d54: e0bff417 ldw r2,-48(fp) + 8034d58: 1006d63a srli r3,r2,24 + 8034d5c: e0bff417 ldw r2,-48(fp) + 8034d60: 1004d23a srli r2,r2,8 + 8034d64: 10bfc00c andi r2,r2,65280 + 8034d68: 1886b03a or r3,r3,r2 + 8034d6c: e0bff417 ldw r2,-48(fp) + 8034d70: 1004923a slli r2,r2,8 + 8034d74: 10803fec andhi r2,r2,255 + 8034d78: 1886b03a or r3,r3,r2 + 8034d7c: e0bff417 ldw r2,-48(fp) + 8034d80: 1004963a slli r2,r2,24 + 8034d84: 1886b03a or r3,r3,r2 + 8034d88: e0bff617 ldw r2,-40(fp) + 8034d8c: 10c00615 stw r3,24(r2) + ti->ti_ack = htonl(ack); + 8034d90: e0bff517 ldw r2,-44(fp) + 8034d94: 1006d63a srli r3,r2,24 + 8034d98: e0bff517 ldw r2,-44(fp) + 8034d9c: 1004d23a srli r2,r2,8 + 8034da0: 10bfc00c andi r2,r2,65280 + 8034da4: 1886b03a or r3,r3,r2 + 8034da8: e0bff517 ldw r2,-44(fp) + 8034dac: 1004923a slli r2,r2,8 + 8034db0: 10803fec andhi r2,r2,255 + 8034db4: 1886b03a or r3,r3,r2 + 8034db8: e0bff517 ldw r2,-44(fp) + 8034dbc: 1004963a slli r2,r2,24 + 8034dc0: 1886b03a or r3,r3,r2 + 8034dc4: e0bff617 ldw r2,-40(fp) + 8034dc8: 10c00715 stw r3,28(r2) + ti->ti_t.th_doff = 0x50; /* NetPort: init data offset bits */ + 8034dcc: e0bff617 ldw r2,-40(fp) + 8034dd0: 00c01404 movi r3,80 + 8034dd4: 10c00805 stb r3,32(r2) + ti->ti_flags = (u_char)flags; + 8034dd8: e0800217 ldw r2,8(fp) + 8034ddc: 1007883a mov r3,r2 + 8034de0: e0bff617 ldw r2,-40(fp) + 8034de4: 10c00845 stb r3,33(r2) + ti->ti_win = htons((u_short)win); + 8034de8: e0bffd17 ldw r2,-12(fp) + 8034dec: 10bfffcc andi r2,r2,65535 + 8034df0: 1004d23a srli r2,r2,8 + 8034df4: 1007883a mov r3,r2 + 8034df8: e0bffd17 ldw r2,-12(fp) + 8034dfc: 10bfffcc andi r2,r2,65535 + 8034e00: 1004923a slli r2,r2,8 + 8034e04: 1884b03a or r2,r3,r2 + 8034e08: 1007883a mov r3,r2 + 8034e0c: e0bff617 ldw r2,-40(fp) + 8034e10: 10c0088d sth r3,34(r2) + ti->ti_urp = 0; + 8034e14: e0bff617 ldw r2,-40(fp) + 8034e18: 1000098d sth zero,38(r2) + + /* Finish constructing IP header and send, based on IP type in use */ + switch(domain) + 8034e1c: e0bffe17 ldw r2,-8(fp) + 8034e20: 10800098 cmpnei r2,r2,2 + 8034e24: 10003c1e bne r2,zero,8034f18 +#ifdef IP_V4 + case AF_INET: + { + struct ip * pip; + + pip = (struct ip *)((char*)ti+sizeof(struct ipovly)-sizeof(struct ip)); + 8034e28: e0bff617 ldw r2,-40(fp) + 8034e2c: e0bff815 stw r2,-32(fp) + + pip->ip_len = (unshort)(TCPIPHDRSZ + tlen); + 8034e30: e0bfff17 ldw r2,-4(fp) + 8034e34: 10800a04 addi r2,r2,40 + 8034e38: 1007883a mov r3,r2 + 8034e3c: e0bff817 ldw r2,-32(fp) + 8034e40: 10c0008d sth r3,2(r2) + /* If our system's max. MAC header size is geater than the size + * of the MAC header in the received packet then we need to + * adjust the IP header offset to allow for this. Since the packets + * are only headers they should always fit. + */ + if(pip >= (struct ip *)(m->pkt->nb_buff + MaxLnh)) + 8034e44: e0bffc17 ldw r2,-16(fp) + 8034e48: 10800117 ldw r2,4(r2) + 8034e4c: 10800117 ldw r2,4(r2) + 8034e50: d0e06417 ldw r3,-32368(gp) + 8034e54: 10c5883a add r2,r2,r3 + 8034e58: e0fff817 ldw r3,-32(fp) + 8034e5c: 18800436 bltu r3,r2,8034e70 + { + m->m_data = (char*)pip; /* headers will fit, just set pointer */ + 8034e60: e0bffc17 ldw r2,-16(fp) + 8034e64: e0fff817 ldw r3,-32(fp) + 8034e68: 10c00315 stw r3,12(r2) + 8034e6c: 00001206 br 8034eb8 + } + else /* MAC may not fit, adjust pointer and move headers back */ + { + m->m_data = m->pkt->nb_prot = m->pkt->nb_buff + MaxLnh; /* new ptr */ + 8034e70: e0bffc17 ldw r2,-16(fp) + 8034e74: 10800117 ldw r2,4(r2) + 8034e78: 10c00117 ldw r3,4(r2) + 8034e7c: d0a06417 ldw r2,-32368(gp) + 8034e80: 1009883a mov r4,r2 + 8034e84: e0bffc17 ldw r2,-16(fp) + 8034e88: 10800117 ldw r2,4(r2) + 8034e8c: 1907883a add r3,r3,r4 + 8034e90: 10c00315 stw r3,12(r2) + 8034e94: 10c00317 ldw r3,12(r2) + 8034e98: e0bffc17 ldw r2,-16(fp) + 8034e9c: 10c00315 stw r3,12(r2) + MEMMOVE(m->m_data, pip, TCPIPHDRSZ); /* move back tcp/ip headers */ + 8034ea0: e0bffc17 ldw r2,-16(fp) + 8034ea4: 10800317 ldw r2,12(r2) + 8034ea8: 01800a04 movi r6,40 + 8034eac: e17ff817 ldw r5,-32(fp) + 8034eb0: 1009883a mov r4,r2 + 8034eb4: 80087b80 call 80087b8 + + /* + * In the case of a SYN DOS attack, many RST|ACK replies + * have no tp structure and need to be freed. + */ + if (!tp) + 8034eb8: e0bff717 ldw r2,-36(fp) + 8034ebc: 1000031e bne r2,zero,8034ecc + m_freem(m); + 8034ec0: e13ffc17 ldw r4,-16(fp) + 8034ec4: 8029cfc0 call 8029cfc + ip_output(m, tp->t_inpcb->inp_socket->so_optsPack); + else + ip_output(m, (struct ip_socopts *)NULL); + } + + break; + 8034ec8: 00001506 br 8034f20 + if ((tp->t_inpcb) && (tp->t_inpcb->inp_socket)) + 8034ecc: e0bff717 ldw r2,-36(fp) + 8034ed0: 10800d17 ldw r2,52(r2) + 8034ed4: 10000c26 beq r2,zero,8034f08 + 8034ed8: e0bff717 ldw r2,-36(fp) + 8034edc: 10800d17 ldw r2,52(r2) + 8034ee0: 10800817 ldw r2,32(r2) + 8034ee4: 10000826 beq r2,zero,8034f08 + ip_output(m, tp->t_inpcb->inp_socket->so_optsPack); + 8034ee8: e0bff717 ldw r2,-36(fp) + 8034eec: 10800d17 ldw r2,52(r2) + 8034ef0: 10800817 ldw r2,32(r2) + 8034ef4: 10801f17 ldw r2,124(r2) + 8034ef8: 100b883a mov r5,r2 + 8034efc: e13ffc17 ldw r4,-16(fp) + 8034f00: 802a6580 call 802a658 + break; + 8034f04: 00000606 br 8034f20 + ip_output(m, (struct ip_socopts *)NULL); + 8034f08: 000b883a mov r5,zero + 8034f0c: e13ffc17 ldw r4,-16(fp) + 8034f10: 802a6580 call 802a658 + break; + 8034f14: 00000206 br 8034f20 + + break; + } +#endif /* IP_V6 */ + default: + dtrap(); + 8034f18: 8028cd40 call 8028cd4 + break; + 8034f1c: 0001883a nop + } + return; + 8034f20: 0001883a nop + 8034f24: 00000106 br 8034f2c + return; + 8034f28: 0001883a nop +} + 8034f2c: e037883a mov sp,fp + 8034f30: dfc00117 ldw ra,4(sp) + 8034f34: df000017 ldw fp,0(sp) + 8034f38: dec00204 addi sp,sp,8 + 8034f3c: f800283a ret + +08034f40 : + * RETURNS: + */ + +struct tcpcb * +tcp_newtcpcb(struct inpcb * inp) +{ + 8034f40: defffb04 addi sp,sp,-20 + 8034f44: dfc00415 stw ra,16(sp) + 8034f48: df000315 stw fp,12(sp) + 8034f4c: df000304 addi fp,sp,12 + 8034f50: e13ffd15 stw r4,-12(fp) + struct tcpcb * tp; + short t_time; + + tp = TCB_ALLOC(sizeof (*tp)); + 8034f54: 01002504 movi r4,148 + 8034f58: 802982c0 call 802982c + 8034f5c: e0bfff15 stw r2,-4(fp) + if (tp == NULL) + 8034f60: e0bfff17 ldw r2,-4(fp) + 8034f64: 1000021e bne r2,zero,8034f70 + return (struct tcpcb *)NULL; + 8034f68: 0005883a mov r2,zero + 8034f6c: 00003206 br 8035038 + tp->seg_next = tp->seg_prev = (struct tcpiphdr *)tp; + 8034f70: e0bfff17 ldw r2,-4(fp) + 8034f74: e0ffff17 ldw r3,-4(fp) + 8034f78: 10c00115 stw r3,4(r2) + 8034f7c: e0bfff17 ldw r2,-4(fp) + 8034f80: 10c00117 ldw r3,4(r2) + 8034f84: e0bfff17 ldw r2,-4(fp) + 8034f88: 10c00015 stw r3,0(r2) + tp->t_maxseg = TCP_MSS; + 8034f8c: e0bfff17 ldw r2,-4(fp) + 8034f90: 00c16d04 movi r3,1460 + 8034f94: 10c00a0d sth r3,40(r2) + tp->t_flags = 0; /* sends options! */ + 8034f98: e0bfff17 ldw r2,-4(fp) + 8034f9c: 10000b0d sth zero,44(r2) + tp->t_inpcb = inp; + 8034fa0: e0bfff17 ldw r2,-4(fp) + 8034fa4: e0fffd17 ldw r3,-12(fp) + 8034fa8: 10c00d15 stw r3,52(r2) + /* + * Init srtt to TCPTV_SRTTBASE (0), so we can tell that we have no + * rtt estimate. Set rttvar so that srtt + 2 * rttvar gives + * reasonable initial retransmit time. + */ + tp->t_srtt = TCPTV_SRTTBASE; + 8034fac: e0bfff17 ldw r2,-4(fp) + 8034fb0: 10002015 stw zero,128(r2) + tp->t_rttvar = TCPTV_SRTTDFLT << 2; + 8034fb4: e0bfff17 ldw r2,-4(fp) + 8034fb8: 00c00604 movi r3,24 + 8034fbc: 10c02115 stw r3,132(r2) + + t_time = ((TCPTV_SRTTBASE >> 2) + (TCPTV_SRTTDFLT << 2)) >> 1; + 8034fc0: 00800304 movi r2,12 + 8034fc4: e0bffe8d sth r2,-6(fp) + TCPT_RANGESET(tp->t_rxtcur, t_time, TCPTV_MIN, TCPTV_REXMTMAX); + 8034fc8: e0fffe8f ldh r3,-6(fp) + 8034fcc: e0bfff17 ldw r2,-4(fp) + 8034fd0: 10c00815 stw r3,32(r2) + 8034fd4: e0bfff17 ldw r2,-4(fp) + 8034fd8: 10800817 ldw r2,32(r2) + 8034fdc: 10800088 cmpgei r2,r2,2 + 8034fe0: 1000041e bne r2,zero,8034ff4 + 8034fe4: e0bfff17 ldw r2,-4(fp) + 8034fe8: 00c00084 movi r3,2 + 8034fec: 10c00815 stw r3,32(r2) + 8034ff0: 00000706 br 8035010 + 8034ff4: e0bfff17 ldw r2,-4(fp) + 8034ff8: 10800817 ldw r2,32(r2) + 8034ffc: 10802050 cmplti r2,r2,129 + 8035000: 1000031e bne r2,zero,8035010 + 8035004: e0bfff17 ldw r2,-4(fp) + 8035008: 00c02004 movi r3,128 + 803500c: 10c00815 stw r3,32(r2) + + /* Set initial congestion window - RFC-2581, pg 4. */ + tp->snd_cwnd = 2 * TCP_MSS; + 8035010: e0bfff17 ldw r2,-4(fp) + 8035014: 00c2da04 movi r3,2920 + 8035018: 10c01b15 stw r3,108(r2) + +#ifdef DO_DELAY_ACKS + tp->t_delacktime = 1; +#endif /* DO_DELAY_ACKS */ + + tp->snd_ssthresh = 65535; /* Start with high slow-start threshold */ + 803501c: e0bfff17 ldw r2,-4(fp) + 8035020: 00ffffd4 movui r3,65535 + 8035024: 10c01c15 stw r3,112(r2) + + inp->inp_ppcb = (char *)tp; + 8035028: e0bffd17 ldw r2,-12(fp) + 803502c: e0ffff17 ldw r3,-4(fp) + 8035030: 10c00915 stw r3,36(r2) + return (tp); + 8035034: e0bfff17 ldw r2,-4(fp) +} + 8035038: e037883a mov sp,fp + 803503c: dfc00117 ldw ra,4(sp) + 8035040: df000017 ldw fp,0(sp) + 8035044: dec00204 addi sp,sp,8 + 8035048: f800283a ret + +0803504c : + * RETURNS: + */ + +struct tcpcb * +tcp_drop(struct tcpcb * tp, int err) +{ + 803504c: defffb04 addi sp,sp,-20 + 8035050: dfc00415 stw ra,16(sp) + 8035054: df000315 stw fp,12(sp) + 8035058: df000304 addi fp,sp,12 + 803505c: e13ffe15 stw r4,-8(fp) + 8035060: e17ffd15 stw r5,-12(fp) + struct socket * so = tp->t_inpcb->inp_socket; + 8035064: e0bffe17 ldw r2,-8(fp) + 8035068: 10800d17 ldw r2,52(r2) + 803506c: 10800817 ldw r2,32(r2) + 8035070: e0bfff15 stw r2,-4(fp) + + if (TCPS_HAVERCVDSYN(tp->t_state)) + 8035074: e0bffe17 ldw r2,-8(fp) + 8035078: 10800217 ldw r2,8(r2) + 803507c: 108000d0 cmplti r2,r2,3 + 8035080: 10000a1e bne r2,zero,80350ac + { + tp->t_state = TCPS_CLOSED; + 8035084: e0bffe17 ldw r2,-8(fp) + 8035088: 10000215 stw zero,8(r2) + (void) tcp_output(tp); + 803508c: e13ffe17 ldw r4,-8(fp) + 8035090: 80338940 call 8033894 + tcpstat.tcps_drops++; + 8035094: 008201b4 movhi r2,2054 + 8035098: 10b8a717 ldw r2,-7524(r2) + 803509c: 10c00044 addi r3,r2,1 + 80350a0: 008201b4 movhi r2,2054 + 80350a4: 10f8a715 stw r3,-7524(r2) + 80350a8: 00000506 br 80350c0 + } + else + tcpstat.tcps_conndrops++; + 80350ac: 008201b4 movhi r2,2054 + 80350b0: 10b8a817 ldw r2,-7520(r2) + 80350b4: 10c00044 addi r3,r2,1 + 80350b8: 008201b4 movhi r2,2054 + 80350bc: 10f8a815 stw r3,-7520(r2) + so->so_error = err; + 80350c0: e0bfff17 ldw r2,-4(fp) + 80350c4: e0fffd17 ldw r3,-12(fp) + 80350c8: 10c00615 stw r3,24(r2) +#ifdef TCP_ZEROCOPY + if (so->rx_upcall) + so->rx_upcall(so, NULL, err); +#endif /* TCP_ZEROCOPY */ + return (tcp_close(tp)); + 80350cc: e13ffe17 ldw r4,-8(fp) + 80350d0: 80350e80 call 80350e8 +} + 80350d4: e037883a mov sp,fp + 80350d8: dfc00117 ldw ra,4(sp) + 80350dc: df000017 ldw fp,0(sp) + 80350e0: dec00204 addi sp,sp,8 + 80350e4: f800283a ret + +080350e8 : + * RETURNS: + */ + +struct tcpcb * +tcp_close(struct tcpcb * tp) +{ + 80350e8: defff904 addi sp,sp,-28 + 80350ec: dfc00615 stw ra,24(sp) + 80350f0: df000515 stw fp,20(sp) + 80350f4: df000504 addi fp,sp,20 + 80350f8: e13ffb15 stw r4,-20(fp) + struct tcpiphdr * t; + struct inpcb * inp = tp->t_inpcb; + 80350fc: e0bffb17 ldw r2,-20(fp) + 8035100: 10800d17 ldw r2,52(r2) + 8035104: e0bffe15 stw r2,-8(fp) + struct socket * so = inp->inp_socket; + 8035108: e0bffe17 ldw r2,-8(fp) + 803510c: 10800817 ldw r2,32(r2) + 8035110: e0bffd15 stw r2,-12(fp) + struct mbuf * m; + + t = tp->seg_next; + 8035114: e0bffb17 ldw r2,-20(fp) + 8035118: 10800017 ldw r2,0(r2) + 803511c: e0bfff15 stw r2,-4(fp) + while (t != (struct tcpiphdr *)tp) + 8035120: 00000e06 br 803515c + { + t = (struct tcpiphdr *)t->ti_next; + 8035124: e0bfff17 ldw r2,-4(fp) + 8035128: 10800017 ldw r2,0(r2) + 803512c: e0bfff15 stw r2,-4(fp) + m = dtom(t->ti_prev); + 8035130: e0bfff17 ldw r2,-4(fp) + 8035134: 10800117 ldw r2,4(r2) + 8035138: 1009883a mov r4,r2 + 803513c: 802a22c0 call 802a22c + 8035140: e0bffc15 stw r2,-16(fp) + remque(t->ti_prev); + 8035144: e0bfff17 ldw r2,-4(fp) + 8035148: 10800117 ldw r2,4(r2) + 803514c: 1009883a mov r4,r2 + 8035150: 802a2c40 call 802a2c4 + m_freem (m); + 8035154: e13ffc17 ldw r4,-16(fp) + 8035158: 8029cfc0 call 8029cfc + while (t != (struct tcpiphdr *)tp) + 803515c: e0ffff17 ldw r3,-4(fp) + 8035160: e0bffb17 ldw r2,-20(fp) + 8035164: 18bfef1e bne r3,r2,8035124 + } + if (tp->t_template) + 8035168: e0bffb17 ldw r2,-20(fp) + 803516c: 10800c17 ldw r2,48(r2) + 8035170: 10000426 beq r2,zero,8035184 + TPH_FREE (tp->t_template); + 8035174: e0bffb17 ldw r2,-20(fp) + 8035178: 10800c17 ldw r2,48(r2) + 803517c: 1009883a mov r4,r2 + 8035180: 80298600 call 8029860 + TCB_FREE (tp); + 8035184: e13ffb17 ldw r4,-20(fp) + 8035188: 80298600 call 8029860 + inp->inp_ppcb = 0; + 803518c: e0bffe17 ldw r2,-8(fp) + 8035190: 10000915 stw zero,36(r2) + soisdisconnected(so); + 8035194: e13ffd17 ldw r4,-12(fp) + 8035198: 802f3840 call 802f384 + in_pcbdetach(inp); + 803519c: e13ffe17 ldw r4,-8(fp) + 80351a0: 80405b40 call 80405b4 + tcpstat.tcps_closed++; + 80351a4: 008201b4 movhi r2,2054 + 80351a8: 10b8a917 ldw r2,-7516(r2) + 80351ac: 10c00044 addi r3,r2,1 + 80351b0: 008201b4 movhi r2,2054 + 80351b4: 10f8a915 stw r3,-7516(r2) + return ((struct tcpcb *)0); + 80351b8: 0005883a mov r2,zero +} + 80351bc: e037883a mov sp,fp + 80351c0: dfc00117 ldw ra,4(sp) + 80351c4: df000017 ldw fp,0(sp) + 80351c8: dec00204 addi sp,sp,8 + 80351cc: f800283a ret + +080351d0 : + * RETURNS: + */ + +void +tcp_quench(struct inpcb * inp) +{ + 80351d0: defffd04 addi sp,sp,-12 + 80351d4: df000215 stw fp,8(sp) + 80351d8: df000204 addi fp,sp,8 + 80351dc: e13ffe15 stw r4,-8(fp) + struct tcpcb * tp = intotcpcb(inp); + 80351e0: e0bffe17 ldw r2,-8(fp) + 80351e4: 10800917 ldw r2,36(r2) + 80351e8: e0bfff15 stw r2,-4(fp) + + if (tp) + 80351ec: e0bfff17 ldw r2,-4(fp) + 80351f0: 10000526 beq r2,zero,8035208 + tp->snd_cwnd = tp->t_maxseg; + 80351f4: e0bfff17 ldw r2,-4(fp) + 80351f8: 10800a0b ldhu r2,40(r2) + 80351fc: 10ffffcc andi r3,r2,65535 + 8035200: e0bfff17 ldw r2,-4(fp) + 8035204: 10c01b15 stw r3,108(r2) +} + 8035208: 0001883a nop + 803520c: e037883a mov sp,fp + 8035210: df000017 ldw fp,0(sp) + 8035214: dec00104 addi sp,sp,4 + 8035218: f800283a ret + +0803521c : + +/* tcp_putseq() */ + +u_char * +tcp_putseq(u_char * cp, tcp_seq seq) +{ + 803521c: defffc04 addi sp,sp,-16 + 8035220: df000315 stw fp,12(sp) + 8035224: df000304 addi fp,sp,12 + 8035228: e13ffe15 stw r4,-8(fp) + 803522c: e17ffd15 stw r5,-12(fp) + int i; + + cp += 3; /* do low byte first */ + 8035230: e0bffe17 ldw r2,-8(fp) + 8035234: 108000c4 addi r2,r2,3 + 8035238: e0bffe15 stw r2,-8(fp) + for(i = 0; i< 4; i++) /* put 4 bytes into buffer */ + 803523c: e03fff15 stw zero,-4(fp) + 8035240: 00000b06 br 8035270 + { + *cp-- = (u_char)(seq & 0xFF); /* back through buffer */ + 8035244: e0bffe17 ldw r2,-8(fp) + 8035248: 10ffffc4 addi r3,r2,-1 + 803524c: e0fffe15 stw r3,-8(fp) + 8035250: e0fffd17 ldw r3,-12(fp) + 8035254: 10c00005 stb r3,0(r2) + seq >>= 8; + 8035258: e0bffd17 ldw r2,-12(fp) + 803525c: 1004d23a srli r2,r2,8 + 8035260: e0bffd15 stw r2,-12(fp) + for(i = 0; i< 4; i++) /* put 4 bytes into buffer */ + 8035264: e0bfff17 ldw r2,-4(fp) + 8035268: 10800044 addi r2,r2,1 + 803526c: e0bfff15 stw r2,-4(fp) + 8035270: e0bfff17 ldw r2,-4(fp) + 8035274: 10800110 cmplti r2,r2,4 + 8035278: 103ff21e bne r2,zero,8035244 + } + return (cp + 5); + 803527c: e0bffe17 ldw r2,-8(fp) + 8035280: 10800144 addi r2,r2,5 +} + 8035284: e037883a mov sp,fp + 8035288: df000017 ldw fp,0(sp) + 803528c: dec00104 addi sp,sp,4 + 8035290: f800283a ret + +08035294 : + * RETURNS: a long in local endian + */ + +u_long +tcp_getseq(u_char * cp) +{ + 8035294: defffc04 addi sp,sp,-16 + 8035298: df000315 stw fp,12(sp) + 803529c: df000304 addi fp,sp,12 + 80352a0: e13ffd15 stw r4,-12(fp) + int i; + ulong seq = 0; + 80352a4: e03ffe15 stw zero,-8(fp) + + for(i = 0; i < 4; i++) + 80352a8: e03fff15 stw zero,-4(fp) + 80352ac: 00000e06 br 80352e8 + { + seq <<= 8; + 80352b0: e0bffe17 ldw r2,-8(fp) + 80352b4: 1004923a slli r2,r2,8 + 80352b8: e0bffe15 stw r2,-8(fp) + seq += (u_long)*(cp++); + 80352bc: e0bffd17 ldw r2,-12(fp) + 80352c0: 10c00044 addi r3,r2,1 + 80352c4: e0fffd15 stw r3,-12(fp) + 80352c8: 10800003 ldbu r2,0(r2) + 80352cc: 10803fcc andi r2,r2,255 + 80352d0: e0fffe17 ldw r3,-8(fp) + 80352d4: 1885883a add r2,r3,r2 + 80352d8: e0bffe15 stw r2,-8(fp) + for(i = 0; i < 4; i++) + 80352dc: e0bfff17 ldw r2,-4(fp) + 80352e0: 10800044 addi r2,r2,1 + 80352e4: e0bfff15 stw r2,-4(fp) + 80352e8: e0bfff17 ldw r2,-4(fp) + 80352ec: 10800110 cmplti r2,r2,4 + 80352f0: 103fef1e bne r2,zero,80352b0 + } + return seq; + 80352f4: e0bffe17 ldw r2,-8(fp) +} + 80352f8: e037883a mov sp,fp + 80352fc: df000017 ldw fp,0(sp) + 8035300: dec00104 addi sp,sp,4 + 8035304: f800283a ret + +08035308 : + * RETURNS: + */ + +void +tcp_slowtimo(void) +{ + 8035308: defff704 addi sp,sp,-36 + 803530c: dfc00815 stw ra,32(sp) + 8035310: df000715 stw fp,28(sp) + 8035314: df000704 addi fp,sp,28 + struct tcpcb * tp; + int i; + struct socket * so, * sonext; + struct sockbuf * sb; + + tcp_maxidle = TCPTV_KEEPCNT * tcp_keepintvl; + 8035318: d0a01f17 ldw r2,-32644(gp) + 803531c: 100490fa slli r2,r2,3 + 8035320: d0a08915 stw r2,-32220(gp) + + /* search through open sockets */ + for (so = (struct socket *)soq.q_head; so != NULL; so = sonext) + 8035324: 008201b4 movhi r2,2054 + 8035328: 10b87117 ldw r2,-7740(r2) + 803532c: e0bffe15 stw r2,-8(fp) + 8035330: 00007c06 br 8035524 + { + sonext = so->next; + 8035334: e0bffe17 ldw r2,-8(fp) + 8035338: 10800017 ldw r2,0(r2) + 803533c: e0bffd15 stw r2,-12(fp) + + /* for SOCK_STREAM (TCP) sockets, we must do slow-timeout + * processing and (optionally) processing of pending + * zero-copy socket upcalls. + */ + if (so->so_type == SOCK_STREAM) + 8035340: e0bffe17 ldw r2,-8(fp) + 8035344: 10800983 ldbu r2,38(r2) + 8035348: 10803fcc andi r2,r2,255 + 803534c: 1080201c xori r2,r2,128 + 8035350: 10bfe004 addi r2,r2,-128 + 8035354: 10800058 cmpnei r2,r2,1 + 8035358: 1000421e bne r2,zero,8035464 + { + ip = so->so_pcb; + 803535c: e0bffe17 ldw r2,-8(fp) + 8035360: 10800117 ldw r2,4(r2) + 8035364: e0bffc15 stw r2,-16(fp) + if (!ip) + 8035368: e0bffc17 ldw r2,-16(fp) + 803536c: 10006626 beq r2,zero,8035508 + continue; + ipnxt = ip->inp_next; + 8035370: e0bffc17 ldw r2,-16(fp) + 8035374: 10800017 ldw r2,0(r2) + 8035378: e0bffb15 stw r2,-20(fp) + + tp = intotcpcb(so->so_pcb); + 803537c: e0bffe17 ldw r2,-8(fp) + 8035380: 10800117 ldw r2,4(r2) + 8035384: 10800917 ldw r2,36(r2) + 8035388: e0bffa15 stw r2,-24(fp) + if (!tp) + 803538c: e0bffa17 ldw r2,-24(fp) + 8035390: 10005f26 beq r2,zero,8035510 + continue; + + for (i = 0; i < TCPT_NTIMERS; i++) + 8035394: e03fff15 stw zero,-4(fp) + 8035398: 00002a06 br 8035444 + { + if (tp->t_timer[i] && --tp->t_timer[i] == 0) + 803539c: e0fffa17 ldw r3,-24(fp) + 80353a0: e0bfff17 ldw r2,-4(fp) + 80353a4: 108000c4 addi r2,r2,3 + 80353a8: 100490ba slli r2,r2,2 + 80353ac: 1885883a add r2,r3,r2 + 80353b0: 10800017 ldw r2,0(r2) + 80353b4: 10002026 beq r2,zero,8035438 + 80353b8: e0fffa17 ldw r3,-24(fp) + 80353bc: e0bfff17 ldw r2,-4(fp) + 80353c0: 108000c4 addi r2,r2,3 + 80353c4: 100490ba slli r2,r2,2 + 80353c8: 1885883a add r2,r3,r2 + 80353cc: 10800017 ldw r2,0(r2) + 80353d0: 10ffffc4 addi r3,r2,-1 + 80353d4: e13ffa17 ldw r4,-24(fp) + 80353d8: e0bfff17 ldw r2,-4(fp) + 80353dc: 108000c4 addi r2,r2,3 + 80353e0: 100490ba slli r2,r2,2 + 80353e4: 2085883a add r2,r4,r2 + 80353e8: 10c00015 stw r3,0(r2) + 80353ec: e0fffa17 ldw r3,-24(fp) + 80353f0: e0bfff17 ldw r2,-4(fp) + 80353f4: 108000c4 addi r2,r2,3 + 80353f8: 100490ba slli r2,r2,2 + 80353fc: 1885883a add r2,r3,r2 + 8035400: 10800017 ldw r2,0(r2) + 8035404: 10000c1e bne r2,zero,8035438 + { + /* call usrreq to do actual work */ + so->so_req = PRU_SLOWTIMO; + 8035408: e0bffe17 ldw r2,-8(fp) + 803540c: 00c004c4 movi r3,19 + 8035410: 10c00715 stw r3,28(r2) + (void) tcp_usrreq(so, (struct mbuf *)0, + 8035414: e0bfff17 ldw r2,-4(fp) + 8035418: 100d883a mov r6,r2 + 803541c: 000b883a mov r5,zero + 8035420: e13ffe17 ldw r4,-8(fp) + 8035424: 8035a140 call 8035a14 + LONG2MBUF((long)i)); + + /* If ip disappeared on us, handle it */ + if (ipnxt->inp_prev != ip) + 8035428: e0bffb17 ldw r2,-20(fp) + 803542c: 10800117 ldw r2,4(r2) + 8035430: e0fffc17 ldw r3,-16(fp) + 8035434: 1880381e bne r3,r2,8035518 + for (i = 0; i < TCPT_NTIMERS; i++) + 8035438: e0bfff17 ldw r2,-4(fp) + 803543c: 10800044 addi r2,r2,1 + 8035440: e0bfff15 stw r2,-4(fp) + 8035444: e0bfff17 ldw r2,-4(fp) + 8035448: 10800110 cmplti r2,r2,4 + 803544c: 103fd31e bne r2,zero,803539c + } + } + } +#endif /* TCP_ZEROCOPY */ + + tp->t_idle++; + 8035450: e0bffa17 ldw r2,-24(fp) + 8035454: 10801d17 ldw r2,116(r2) + 8035458: 10c00044 addi r3,r2,1 + 803545c: e0bffa17 ldw r2,-24(fp) + 8035460: 10c01d15 stw r3,116(r2) + } + + /* wake up anyone sleeping in a select() involving this socket */ + sb = &so->so_rcv; + 8035464: e0bffe17 ldw r2,-8(fp) + 8035468: 10800a04 addi r2,r2,40 + 803546c: e0bff915 stw r2,-28(fp) + if (sb->sb_flags & SB_SEL) + 8035470: e0bff917 ldw r2,-28(fp) + 8035474: 1080070b ldhu r2,28(r2) + 8035478: 10bfffcc andi r2,r2,65535 + 803547c: 1080020c andi r2,r2,8 + 8035480: 10000a26 beq r2,zero,80354ac + { + select_wait = 0; + 8035484: d020850d sth zero,-32236(gp) +#ifndef SOCK_MAP_EVENTS + tcp_wakeup ((char *)&select_wait); + 8035488: d1208504 addi r4,gp,-32236 + 803548c: 8027ba00 call 8027ba0 +#else + tcp_wakeup2 (so->owner); +#endif + sb->sb_flags &= ~SB_SEL; + 8035490: e0bff917 ldw r2,-28(fp) + 8035494: 10c0070b ldhu r3,28(r2) + 8035498: 00bffdc4 movi r2,-9 + 803549c: 1884703a and r2,r3,r2 + 80354a0: 1007883a mov r3,r2 + 80354a4: e0bff917 ldw r2,-28(fp) + 80354a8: 10c0070d sth r3,28(r2) + } + sb = &so->so_snd; + 80354ac: e0bffe17 ldw r2,-8(fp) + 80354b0: 10801204 addi r2,r2,72 + 80354b4: e0bff915 stw r2,-28(fp) + if (sb->sb_flags & SB_SEL) + 80354b8: e0bff917 ldw r2,-28(fp) + 80354bc: 1080070b ldhu r2,28(r2) + 80354c0: 10bfffcc andi r2,r2,65535 + 80354c4: 1080020c andi r2,r2,8 + 80354c8: 10000a26 beq r2,zero,80354f4 + { + select_wait = 0; + 80354cc: d020850d sth zero,-32236(gp) +#ifndef SOCK_MAP_EVENTS + tcp_wakeup ((char *)&select_wait); + 80354d0: d1208504 addi r4,gp,-32236 + 80354d4: 8027ba00 call 8027ba0 +#else + tcp_wakeup2 (so->owner); +#endif + sb->sb_flags &= ~SB_SEL; + 80354d8: e0bff917 ldw r2,-28(fp) + 80354dc: 10c0070b ldhu r3,28(r2) + 80354e0: 00bffdc4 movi r2,-9 + 80354e4: 1884703a and r2,r3,r2 + 80354e8: 1007883a mov r3,r2 + 80354ec: e0bff917 ldw r2,-28(fp) + 80354f0: 10c0070d sth r3,28(r2) + } + + /* wake any thread with a timer going for a connection state change */ + tcp_wakeup((char*)&so->so_timeo); + 80354f4: e0bffe17 ldw r2,-8(fp) + 80354f8: 10800904 addi r2,r2,36 + 80354fc: 1009883a mov r4,r2 + 8035500: 8027ba00 call 8027ba0 + 8035504: 00000506 br 803551c + continue; + 8035508: 0001883a nop + 803550c: 00000306 br 803551c + continue; + 8035510: 0001883a nop + 8035514: 00000106 br 803551c + goto tpgone; + 8035518: 0001883a nop + for (so = (struct socket *)soq.q_head; so != NULL; so = sonext) + 803551c: e0bffd17 ldw r2,-12(fp) + 8035520: e0bffe15 stw r2,-8(fp) + 8035524: e0bffe17 ldw r2,-8(fp) + 8035528: 103f821e bne r2,zero,8035334 + +tpgone: + ; + } + + tcp_iss += (unsigned)(TCP_ISSINCR/PR_SLOWHZ); /* increment iss */ + 803552c: d0e08a17 ldw r3,-32216(gp) + 8035530: 00be9fd4 movui r2,64127 + 8035534: 1885883a add r2,r3,r2 + 8035538: d0a08a15 stw r2,-32216(gp) + + if (tcp_iss & 0xff000000) + 803553c: d0a08a17 ldw r2,-32216(gp) + 8035540: 10bfc02c andhi r2,r2,65280 + 8035544: 10000126 beq r2,zero,803554c + tcp_iss = 0L; + 8035548: d0208a15 stw zero,-32216(gp) +} + 803554c: 0001883a nop + 8035550: e037883a mov sp,fp + 8035554: dfc00117 ldw ra,4(sp) + 8035558: df000017 ldw fp,0(sp) + 803555c: dec00204 addi sp,sp,8 + 8035560: f800283a ret + +08035564 : + * RETURNS: + */ + +void +tcp_canceltimers(struct tcpcb * tp) +{ + 8035564: defffd04 addi sp,sp,-12 + 8035568: df000215 stw fp,8(sp) + 803556c: df000204 addi fp,sp,8 + 8035570: e13ffe15 stw r4,-8(fp) + int i; + + for (i = 0; i < TCPT_NTIMERS; i++) + 8035574: e03fff15 stw zero,-4(fp) + 8035578: 00000906 br 80355a0 + tp->t_timer[i] = 0; + 803557c: e0fffe17 ldw r3,-8(fp) + 8035580: e0bfff17 ldw r2,-4(fp) + 8035584: 108000c4 addi r2,r2,3 + 8035588: 100490ba slli r2,r2,2 + 803558c: 1885883a add r2,r3,r2 + 8035590: 10000015 stw zero,0(r2) + for (i = 0; i < TCPT_NTIMERS; i++) + 8035594: e0bfff17 ldw r2,-4(fp) + 8035598: 10800044 addi r2,r2,1 + 803559c: e0bfff15 stw r2,-4(fp) + 80355a0: e0bfff17 ldw r2,-4(fp) + 80355a4: 10800110 cmplti r2,r2,4 + 80355a8: 103ff41e bne r2,zero,803557c +} + 80355ac: 0001883a nop + 80355b0: e037883a mov sp,fp + 80355b4: df000017 ldw fp,0(sp) + 80355b8: dec00104 addi sp,sp,4 + 80355bc: f800283a ret + +080355c0 : + * RETURNS: + */ + +struct tcpcb * +tcp_timers(struct tcpcb * tp, int timer) +{ + 80355c0: defff804 addi sp,sp,-32 + 80355c4: dfc00715 stw ra,28(sp) + 80355c8: df000615 stw fp,24(sp) + 80355cc: df000604 addi fp,sp,24 + 80355d0: e13ffd15 stw r4,-12(fp) + 80355d4: e17ffc15 stw r5,-16(fp) + int rexmt; + + switch (timer) + 80355d8: e0bffc17 ldw r2,-16(fp) + 80355dc: 10800060 cmpeqi r2,r2,1 + 80355e0: 1000af1e bne r2,zero,80358a0 + 80355e4: e0bffc17 ldw r2,-16(fp) + 80355e8: 10800088 cmpgei r2,r2,2 + 80355ec: 1000031e bne r2,zero,80355fc + 80355f0: e0bffc17 ldw r2,-16(fp) + 80355f4: 10001a26 beq r2,zero,8035660 + 80355f8: 00010006 br 80359fc + 80355fc: e0bffc17 ldw r2,-16(fp) + 8035600: 108000a0 cmpeqi r2,r2,2 + 8035604: 1000b51e bne r2,zero,80358dc + 8035608: e0bffc17 ldw r2,-16(fp) + 803560c: 108000d8 cmpnei r2,r2,3 + 8035610: 1000fa1e bne r2,zero,80359fc + * still waiting for peer to close and connection has been idle + * too long, or if 2MSL time is up from TIME_WAIT, delete connection + * control block. Otherwise, check again in a bit. + */ + case TCPT_2MSL: + if (tp->t_state != TCPS_TIME_WAIT && + 8035614: e0bffd17 ldw r2,-12(fp) + 8035618: 10800217 ldw r2,8(r2) + 803561c: 108002a0 cmpeqi r2,r2,10 + 8035620: 10000b1e bne r2,zero,8035650 + tp->t_idle <= tcp_maxidle) + 8035624: e0bffd17 ldw r2,-12(fp) + 8035628: 10801d17 ldw r2,116(r2) + 803562c: d0e08917 ldw r3,-32220(gp) + if (tp->t_state != TCPS_TIME_WAIT && + 8035630: 18800716 blt r3,r2,8035650 + { + tp->t_timer[TCPT_2MSL] = (short)tcp_keepintvl; + 8035634: d0a01f17 ldw r2,-32644(gp) + 8035638: 10ffffcc andi r3,r2,65535 + 803563c: 18e0001c xori r3,r3,32768 + 8035640: 18e00004 addi r3,r3,-32768 + 8035644: e0bffd17 ldw r2,-12(fp) + 8035648: 10c00615 stw r3,24(r2) + } + else + tp = tcp_close(tp); + break; + 803564c: 0000eb06 br 80359fc + tp = tcp_close(tp); + 8035650: e13ffd17 ldw r4,-12(fp) + 8035654: 80350e80 call 80350e8 + 8035658: e0bffd15 stw r2,-12(fp) + break; + 803565c: 0000e706 br 80359fc + * Retransmission timer went off. Message has not + * been acked within retransmit interval. Back off + * to a longer retransmit interval and retransmit one segment. + */ + case TCPT_REXMT: + TCP_MIB_INC(tcpRetransSegs); /* keep MIB stats */ + 8035660: 008201b4 movhi r2,2054 + 8035664: 10b88117 ldw r2,-7676(r2) + 8035668: 10c00044 addi r3,r2,1 + 803566c: 008201b4 movhi r2,2054 + 8035670: 10f88115 stw r3,-7676(r2) + if (++tp->t_rxtshift > TCP_MAXRXTSHIFT) + 8035674: e0bffd17 ldw r2,-12(fp) + 8035678: 10800717 ldw r2,28(r2) + 803567c: 10c00044 addi r3,r2,1 + 8035680: e0bffd17 ldw r2,-12(fp) + 8035684: 10c00715 stw r3,28(r2) + 8035688: e0bffd17 ldw r2,-12(fp) + 803568c: 10800717 ldw r2,28(r2) + 8035690: 10800350 cmplti r2,r2,13 + 8035694: 10000d1e bne r2,zero,80356cc + { + tp->t_rxtshift = TCP_MAXRXTSHIFT; + 8035698: e0bffd17 ldw r2,-12(fp) + 803569c: 00c00304 movi r3,12 + 80356a0: 10c00715 stw r3,28(r2) + tcpstat.tcps_timeoutdrop++; + 80356a4: 008201b4 movhi r2,2054 + 80356a8: 10b8ad17 ldw r2,-7500(r2) + 80356ac: 10c00044 addi r3,r2,1 + 80356b0: 008201b4 movhi r2,2054 + 80356b4: 10f8ad15 stw r3,-7500(r2) + tp = tcp_drop(tp, ETIMEDOUT); + 80356b8: 01401d04 movi r5,116 + 80356bc: e13ffd17 ldw r4,-12(fp) + 80356c0: 803504c0 call 803504c + 80356c4: e0bffd15 stw r2,-12(fp) + break; + 80356c8: 0000cc06 br 80359fc + } + tcpstat.tcps_rexmttimeo++; + 80356cc: 008201b4 movhi r2,2054 + 80356d0: 10b8ae17 ldw r2,-7496(r2) + 80356d4: 10c00044 addi r3,r2,1 + 80356d8: 008201b4 movhi r2,2054 + 80356dc: 10f8ae15 stw r3,-7496(r2) + rexmt = ((tp->t_srtt >> 2) + tp->t_rttvar) >> 1; + 80356e0: e0bffd17 ldw r2,-12(fp) + 80356e4: 10802017 ldw r2,128(r2) + 80356e8: 1007d0ba srai r3,r2,2 + 80356ec: e0bffd17 ldw r2,-12(fp) + 80356f0: 10802117 ldw r2,132(r2) + 80356f4: 1885883a add r2,r3,r2 + 80356f8: 1005d07a srai r2,r2,1 + 80356fc: e0bffe15 stw r2,-8(fp) + rexmt *= tcp_backoff[tp->t_rxtshift]; + 8035700: e0bffd17 ldw r2,-12(fp) + 8035704: 10c00717 ldw r3,28(r2) + 8035708: 00820174 movhi r2,2053 + 803570c: 1885883a add r2,r3,r2 + 8035710: 10b20cc3 ldbu r2,-14285(r2) + 8035714: 10803fcc andi r2,r2,255 + 8035718: e0fffe17 ldw r3,-8(fp) + 803571c: 1885383a mul r2,r3,r2 + 8035720: e0bffe15 stw r2,-8(fp) + TCPT_RANGESET(tp->t_rxtcur, rexmt, TCPTV_MIN, TCPTV_REXMTMAX); + 8035724: e0bffe17 ldw r2,-8(fp) + 8035728: 10ffffcc andi r3,r2,65535 + 803572c: 18e0001c xori r3,r3,32768 + 8035730: 18e00004 addi r3,r3,-32768 + 8035734: e0bffd17 ldw r2,-12(fp) + 8035738: 10c00815 stw r3,32(r2) + 803573c: e0bffd17 ldw r2,-12(fp) + 8035740: 10800817 ldw r2,32(r2) + 8035744: 10800088 cmpgei r2,r2,2 + 8035748: 1000041e bne r2,zero,803575c + 803574c: e0bffd17 ldw r2,-12(fp) + 8035750: 00c00084 movi r3,2 + 8035754: 10c00815 stw r3,32(r2) + 8035758: 00000706 br 8035778 + 803575c: e0bffd17 ldw r2,-12(fp) + 8035760: 10800817 ldw r2,32(r2) + 8035764: 10802050 cmplti r2,r2,129 + 8035768: 1000031e bne r2,zero,8035778 + 803576c: e0bffd17 ldw r2,-12(fp) + 8035770: 00c02004 movi r3,128 + 8035774: 10c00815 stw r3,32(r2) + tp->t_timer[TCPT_REXMT] = tp->t_rxtcur; + 8035778: e0bffd17 ldw r2,-12(fp) + 803577c: 10c00817 ldw r3,32(r2) + 8035780: e0bffd17 ldw r2,-12(fp) + 8035784: 10c00315 stw r3,12(r2) + * so we'll take the next rtt measurement as our srtt; + * move the current srtt into rttvar to keep the current + * retransmit times until then. Don't clobber with rtt + * if we got it from a timestamp option. + */ + if((tp->t_rxtshift > TCP_MAXRXTSHIFT / 4) && + 8035788: e0bffd17 ldw r2,-12(fp) + 803578c: 10800717 ldw r2,28(r2) + 8035790: 10800110 cmplti r2,r2,4 + 8035794: 10000f1e bne r2,zero,80357d4 + ((tp->t_flags & TF_TIMESTAMP) == 0)) + 8035798: e0bffd17 ldw r2,-12(fp) + 803579c: 10800b0b ldhu r2,44(r2) + 80357a0: 10bfffcc andi r2,r2,65535 + 80357a4: 1080400c andi r2,r2,256 + if((tp->t_rxtshift > TCP_MAXRXTSHIFT / 4) && + 80357a8: 10000a1e bne r2,zero,80357d4 + { + tp->t_rttvar += (tp->t_srtt >> 2); + 80357ac: e0bffd17 ldw r2,-12(fp) + 80357b0: 10c02117 ldw r3,132(r2) + 80357b4: e0bffd17 ldw r2,-12(fp) + 80357b8: 10802017 ldw r2,128(r2) + 80357bc: 1005d0ba srai r2,r2,2 + 80357c0: 1887883a add r3,r3,r2 + 80357c4: e0bffd17 ldw r2,-12(fp) + 80357c8: 10c02115 stw r3,132(r2) + tp->t_srtt = 0; + 80357cc: e0bffd17 ldw r2,-12(fp) + 80357d0: 10002015 stw zero,128(r2) + } + tp->snd_nxt = tp->snd_una; + 80357d4: e0bffd17 ldw r2,-12(fp) + 80357d8: 10c00e17 ldw r3,56(r2) + 80357dc: e0bffd17 ldw r2,-12(fp) + 80357e0: 10c00f15 stw r3,60(r2) + /* + * If timing a segment in this window, stop the timer. + */ + tp->t_rttick = 0; + 80357e4: e0bffd17 ldw r2,-12(fp) + 80357e8: 10001e15 stw zero,120(r2) + * to go below this.) + * + * Vers 1.9 - Skip slow start if the SO_NOSLOWSTART socket option + * is set. + */ + if((tp->t_inpcb->inp_socket->so_options & SO_NOSLOWSTART) == 0) + 80357ec: e0bffd17 ldw r2,-12(fp) + 80357f0: 10800d17 ldw r2,52(r2) + 80357f4: 10800817 ldw r2,32(r2) + 80357f8: 10800417 ldw r2,16(r2) + 80357fc: 1090000c andi r2,r2,16384 + 8035800: 1000241e bne r2,zero,8035894 + { + u_int win = MIN(tp->snd_wnd, tp->snd_cwnd); + 8035804: e0bffd17 ldw r2,-12(fp) + 8035808: 11001417 ldw r4,80(r2) + 803580c: e0bffd17 ldw r2,-12(fp) + 8035810: 10c01b17 ldw r3,108(r2) + 8035814: 2005883a mov r2,r4 + 8035818: 1880012e bgeu r3,r2,8035820 + 803581c: 1805883a mov r2,r3 + 8035820: e0bfff15 stw r2,-4(fp) + win = win / 2 / tp->t_maxseg; + 8035824: e0bfff17 ldw r2,-4(fp) + 8035828: 1006d07a srli r3,r2,1 + 803582c: e0bffd17 ldw r2,-12(fp) + 8035830: 10800a0b ldhu r2,40(r2) + 8035834: 10bfffcc andi r2,r2,65535 + 8035838: 100b883a mov r5,r2 + 803583c: 1809883a mov r4,r3 + 8035840: 800cff80 call 800cff8 <__udivsi3> + 8035844: e0bfff15 stw r2,-4(fp) + if (win < 2) + 8035848: e0bfff17 ldw r2,-4(fp) + 803584c: 108000a8 cmpgeui r2,r2,2 + 8035850: 1000021e bne r2,zero,803585c + win = 2; + 8035854: 00800084 movi r2,2 + 8035858: e0bfff15 stw r2,-4(fp) + tp->snd_cwnd = tp->t_maxseg; + 803585c: e0bffd17 ldw r2,-12(fp) + 8035860: 10800a0b ldhu r2,40(r2) + 8035864: 10ffffcc andi r3,r2,65535 + 8035868: e0bffd17 ldw r2,-12(fp) + 803586c: 10c01b15 stw r3,108(r2) + tp->snd_ssthresh = (u_short)win * tp->t_maxseg; + 8035870: e0bfff17 ldw r2,-4(fp) + 8035874: 10ffffcc andi r3,r2,65535 + 8035878: e0bffd17 ldw r2,-12(fp) + 803587c: 10800a0b ldhu r2,40(r2) + 8035880: 10bfffcc andi r2,r2,65535 + 8035884: 1885383a mul r2,r3,r2 + 8035888: 1007883a mov r3,r2 + 803588c: e0bffd17 ldw r2,-12(fp) + 8035890: 10c01c15 stw r3,112(r2) + } + (void) tcp_output(tp); + 8035894: e13ffd17 ldw r4,-12(fp) + 8035898: 80338940 call 8033894 + break; + 803589c: 00005706 br 80359fc + /* + * Persistance timer into zero window. + * Force a byte to be output, if possible. + */ + case TCPT_PERSIST: + tcpstat.tcps_persisttimeo++; + 80358a0: 008201b4 movhi r2,2054 + 80358a4: 10b8af17 ldw r2,-7492(r2) + 80358a8: 10c00044 addi r3,r2,1 + 80358ac: 008201b4 movhi r2,2054 + 80358b0: 10f8af15 stw r3,-7492(r2) + tcp_setpersist(tp); + 80358b4: e13ffd17 ldw r4,-12(fp) + 80358b8: 80348300 call 8034830 + tp->t_force = 1; + 80358bc: e0bffd17 ldw r2,-12(fp) + 80358c0: 00c00044 movi r3,1 + 80358c4: 10c00a85 stb r3,42(r2) + (void) tcp_output(tp); + 80358c8: e13ffd17 ldw r4,-12(fp) + 80358cc: 80338940 call 8033894 + tp->t_force = 0; + 80358d0: e0bffd17 ldw r2,-12(fp) + 80358d4: 10000a85 stb zero,42(r2) + break; + 80358d8: 00004806 br 80359fc + /* + * Keep-alive timer went off; send something + * or drop connection if idle for too long. + */ + case TCPT_KEEP: + tcpstat.tcps_keeptimeo++; + 80358dc: 008201b4 movhi r2,2054 + 80358e0: 10b8b017 ldw r2,-7488(r2) + 80358e4: 10c00044 addi r3,r2,1 + 80358e8: 008201b4 movhi r2,2054 + 80358ec: 10f8b015 stw r3,-7488(r2) + if (tp->t_state < TCPS_ESTABLISHED) + 80358f0: e0bffd17 ldw r2,-12(fp) + 80358f4: 10800217 ldw r2,8(r2) + 80358f8: 10800108 cmpgei r2,r2,4 + 80358fc: 10003226 beq r2,zero,80359c8 + goto dropit; + if (tp->t_inpcb->inp_socket->so_options & SO_KEEPALIVE && + 8035900: e0bffd17 ldw r2,-12(fp) + 8035904: 10800d17 ldw r2,52(r2) + 8035908: 10800817 ldw r2,32(r2) + 803590c: 10800417 ldw r2,16(r2) + 8035910: 1080020c andi r2,r2,8 + 8035914: 10002526 beq r2,zero,80359ac + tp->t_state <= TCPS_CLOSE_WAIT) + 8035918: e0bffd17 ldw r2,-12(fp) + 803591c: 10800217 ldw r2,8(r2) + if (tp->t_inpcb->inp_socket->so_options & SO_KEEPALIVE && + 8035920: 10800188 cmpgei r2,r2,6 + 8035924: 1000211e bne r2,zero,80359ac + { + if (tp->t_idle >= tcp_keepidle + tcp_maxidle) + 8035928: e0bffd17 ldw r2,-12(fp) + 803592c: 10c01d17 ldw r3,116(r2) + 8035930: d1201e17 ldw r4,-32648(gp) + 8035934: d0a08917 ldw r2,-32220(gp) + 8035938: 2085883a add r2,r4,r2 + 803593c: 1880240e bge r3,r2,80359d0 + * causes the transmitted zero-length segment + * to lie outside the receive window; + * by the protocol spec, this requires the + * correspondent TCP to respond. + */ + tcpstat.tcps_keepprobe++; + 8035940: 008201b4 movhi r2,2054 + 8035944: 10b8b117 ldw r2,-7484(r2) + 8035948: 10c00044 addi r3,r2,1 + 803594c: 008201b4 movhi r2,2054 + 8035950: 10f8b115 stw r3,-7484(r2) + + /* + * The keepalive packet must have nonzero length + * to get a 4.2 host to respond. + */ + tcp_respond(tp, tp->t_template, tp->rcv_nxt - 1, + 8035954: e0bffd17 ldw r2,-12(fp) + 8035958: 10c00c17 ldw r3,48(r2) + 803595c: e0bffd17 ldw r2,-12(fp) + 8035960: 10801617 ldw r2,88(r2) + 8035964: 113fffc4 addi r4,r2,-1 + tp->snd_una - 1, 0, (struct mbuf *)NULL); + 8035968: e0bffd17 ldw r2,-12(fp) + 803596c: 10800e17 ldw r2,56(r2) + tcp_respond(tp, tp->t_template, tp->rcv_nxt - 1, + 8035970: 10bfffc4 addi r2,r2,-1 + 8035974: d8000115 stw zero,4(sp) + 8035978: d8000015 stw zero,0(sp) + 803597c: 100f883a mov r7,r2 + 8035980: 200d883a mov r6,r4 + 8035984: 180b883a mov r5,r3 + 8035988: e13ffd17 ldw r4,-12(fp) + 803598c: 8034b480 call 8034b48 + + tp->t_timer[TCPT_KEEP] = (short)tcp_keepintvl; + 8035990: d0a01f17 ldw r2,-32644(gp) + 8035994: 10ffffcc andi r3,r2,65535 + 8035998: 18e0001c xori r3,r3,32768 + 803599c: 18e00004 addi r3,r3,-32768 + 80359a0: e0bffd17 ldw r2,-12(fp) + 80359a4: 10c00515 stw r3,20(r2) + } + else + tp->t_timer[TCPT_KEEP] = (short)tcp_keepidle; + break; + 80359a8: 00001406 br 80359fc + tp->t_timer[TCPT_KEEP] = (short)tcp_keepidle; + 80359ac: d0a01e17 ldw r2,-32648(gp) + 80359b0: 10ffffcc andi r3,r2,65535 + 80359b4: 18e0001c xori r3,r3,32768 + 80359b8: 18e00004 addi r3,r3,-32768 + 80359bc: e0bffd17 ldw r2,-12(fp) + 80359c0: 10c00515 stw r3,20(r2) + break; + 80359c4: 00000d06 br 80359fc + goto dropit; + 80359c8: 0001883a nop + 80359cc: 00000106 br 80359d4 + goto dropit; + 80359d0: 0001883a nop + dropit: + tcpstat.tcps_keepdrops++; + 80359d4: 008201b4 movhi r2,2054 + 80359d8: 10b8b217 ldw r2,-7480(r2) + 80359dc: 10c00044 addi r3,r2,1 + 80359e0: 008201b4 movhi r2,2054 + 80359e4: 10f8b215 stw r3,-7480(r2) + tp = tcp_drop (tp, ETIMEDOUT); + 80359e8: 01401d04 movi r5,116 + 80359ec: e13ffd17 ldw r4,-12(fp) + 80359f0: 803504c0 call 803504c + 80359f4: e0bffd15 stw r2,-12(fp) + break; + 80359f8: 0001883a nop + } + return tp; + 80359fc: e0bffd17 ldw r2,-12(fp) +} + 8035a00: e037883a mov sp,fp + 8035a04: dfc00117 ldw ra,4(sp) + 8035a08: df000017 ldw fp,0(sp) + 8035a0c: dec00204 addi sp,sp,8 + 8035a10: f800283a ret + +08035a14 : + +int +tcp_usrreq(struct socket * so, + struct mbuf * m, + struct mbuf * nam) +{ + 8035a14: defff604 addi sp,sp,-40 + 8035a18: dfc00915 stw ra,36(sp) + 8035a1c: df000815 stw fp,32(sp) + 8035a20: df000804 addi fp,sp,32 + 8035a24: e13ffa15 stw r4,-24(fp) + 8035a28: e17ff915 stw r5,-28(fp) + 8035a2c: e1bff815 stw r6,-32(fp) + struct inpcb * inp; + struct tcpcb * tp; + int error = 0; + 8035a30: e03ffe15 stw zero,-8(fp) + +#ifdef DO_TCPTRACE + int ostate; +#endif + + req = so->so_req; /* get request from socket struct */ + 8035a34: e0bffa17 ldw r2,-24(fp) + 8035a38: 10800717 ldw r2,28(r2) + 8035a3c: e0bffd15 stw r2,-12(fp) + inp = sotoinpcb(so); + 8035a40: e0bffa17 ldw r2,-24(fp) + 8035a44: 10800117 ldw r2,4(r2) + 8035a48: e0bffc15 stw r2,-16(fp) + /* + * When a TCP is attached to a socket, then there will be + * a (struct inpcb) pointed at by the socket, and this + * structure will point at a subsidary (struct tcpcb). + */ + if (inp == 0 && req != PRU_ATTACH) + 8035a4c: e0bffc17 ldw r2,-16(fp) + 8035a50: 1000041e bne r2,zero,8035a64 + 8035a54: e0bffd17 ldw r2,-12(fp) + 8035a58: 10000226 beq r2,zero,8035a64 + { + return (EINVAL); + 8035a5c: 00800584 movi r2,22 + 8035a60: 00019506 br 80360b8 + } + + if (inp) + 8035a64: e0bffc17 ldw r2,-16(fp) + 8035a68: 10000426 beq r2,zero,8035a7c + tp = intotcpcb(inp); + 8035a6c: e0bffc17 ldw r2,-16(fp) + 8035a70: 10800917 ldw r2,36(r2) + 8035a74: e0bfff15 stw r2,-4(fp) + 8035a78: 00000706 br 8035a98 + else /* inp and tp not set, make sure this is OK: */ + { + if (req == PRU_ATTACH) + 8035a7c: e0bffd17 ldw r2,-12(fp) + 8035a80: 1000021e bne r2,zero,8035a8c + tp = NULL; /* stifle compiler warnings about using unassigned tp*/ + 8035a84: e03fff15 stw zero,-4(fp) + 8035a88: 00000306 br 8035a98 + else + { + dtrap(); /* programming error? */ + 8035a8c: 8028cd40 call 8028cd4 + return EINVAL; + 8035a90: 00800584 movi r2,22 + 8035a94: 00018806 br 80360b8 + } + } + + switch (req) + 8035a98: e0bffd17 ldw r2,-12(fp) + 8035a9c: 10800528 cmpgeui r2,r2,20 + 8035aa0: 10016f1e bne r2,zero,8036060 + 8035aa4: e0bffd17 ldw r2,-12(fp) + 8035aa8: 100690ba slli r3,r2,2 + 8035aac: 008200f4 movhi r2,2051 + 8035ab0: 1885883a add r2,r3,r2 + 8035ab4: 1096af17 ldw r2,23228(r2) + 8035ab8: 1000683a jmp r2 + 8035abc: 08035b0c andi zero,at,3436 + 8035ac0: 08035b6c andhi zero,at,3437 + 8035ac4: 08035b94 ori zero,at,3438 + 8035ac8: 08035bcc andi zero,at,3439 + 8035acc: 08035c04 addi zero,at,3440 + 8035ad0: 08035d4c andi zero,at,3445 + 8035ad4: 08035d40 call 8035d4 + 8035ad8: 08035df4 orhi zero,at,3447 + 8035adc: 08035e20 cmpeqi zero,at,3448 + 8035ae0: 08035e2c andhi zero,at,3448 + 8035ae4: 08035e88 cmpgei zero,at,3450 + 8035ae8: 08036060 cmpeqi zero,at,3457 + 8035aec: 08035e98 cmpnei zero,at,3450 + 8035af0: 08035ea4 muli zero,at,3450 + 8035af4: 08035f5c xori zero,at,3453 + 8035af8: 0803602c andhi zero,at,3456 + 8035afc: 0803603c xorhi zero,at,3456 + 8035b00: 08035d34 orhi zero,at,3444 + 8035b04: 08036060 cmpeqi zero,at,3457 + 8035b08: 0803604c andi zero,at,3457 + /* + * TCP attaches to socket via PRU_ATTACH, reserving space, + * and an internet control block. + */ + case PRU_ATTACH: + if (inp) + 8035b0c: e0bffc17 ldw r2,-16(fp) + 8035b10: 10000326 beq r2,zero,8035b20 + { + error = EISCONN; + 8035b14: 00801fc4 movi r2,127 + 8035b18: e0bffe15 stw r2,-8(fp) + break; + 8035b1c: 00016506 br 80360b4 + } + error = tcp_attach(so); + 8035b20: e13ffa17 ldw r4,-24(fp) + 8035b24: 80360cc0 call 80360cc + 8035b28: e0bffe15 stw r2,-8(fp) + if (error) + 8035b2c: e0bffe17 ldw r2,-8(fp) + 8035b30: 10014f1e bne r2,zero,8036070 + break; + if ((so->so_options & SO_LINGER) && so->so_linger == 0) + 8035b34: e0bffa17 ldw r2,-24(fp) + 8035b38: 10800417 ldw r2,16(r2) + 8035b3c: 1080200c andi r2,r2,128 + 8035b40: 10014d26 beq r2,zero,8036078 + 8035b44: e0bffa17 ldw r2,-24(fp) + 8035b48: 1080080b ldhu r2,32(r2) + 8035b4c: 10bfffcc andi r2,r2,65535 + 8035b50: 10a0001c xori r2,r2,32768 + 8035b54: 10a00004 addi r2,r2,-32768 + 8035b58: 1001471e bne r2,zero,8036078 + so->so_linger = TCP_LINGERTIME; + 8035b5c: e0bffa17 ldw r2,-24(fp) + 8035b60: 00c01e04 movi r3,120 + 8035b64: 10c0080d sth r3,32(r2) +#ifdef DO_TCPTRACE + SETTP(tp, sototcpcb(so)); +#endif + break; + 8035b68: 00014306 br 8036078 + * do this directly: have to initiate a PRU_DISCONNECT, + * which may finish later; embryonic TCB's can just + * be discarded here. + */ + case PRU_DETACH: + if (tp->t_state > TCPS_LISTEN) + 8035b6c: e0bfff17 ldw r2,-4(fp) + 8035b70: 10800217 ldw r2,8(r2) + 8035b74: 10800090 cmplti r2,r2,2 + 8035b78: 1000031e bne r2,zero,8035b88 + SETTP(tp, tcp_disconnect(tp)); + 8035b7c: e13fff17 ldw r4,-4(fp) + 8035b80: 80361e40 call 80361e4 + else + SETTP(tp, tcp_close(tp)); + break; + 8035b84: 00014b06 br 80360b4 + SETTP(tp, tcp_close(tp)); + 8035b88: e13fff17 ldw r4,-4(fp) + 8035b8c: 80350e80 call 80350e8 + break; + 8035b90: 00014806 br 80360b4 + /* bind is quite different for IPv4 and v6, so we use two + * seperate pcbbind routines. so_domain was checked for + * validity way up in t_bind() + */ +#ifdef IP_V4 + if(inp->inp_socket->so_domain == AF_INET) + 8035b94: e0bffc17 ldw r2,-16(fp) + 8035b98: 10800817 ldw r2,32(r2) + 8035b9c: 10800517 ldw r2,20(r2) + 8035ba0: 10800098 cmpnei r2,r2,2 + 8035ba4: 1000051e bne r2,zero,8035bbc + { + error = in_pcbbind(inp, nam); + 8035ba8: e17ff817 ldw r5,-32(fp) + 8035bac: e13ffc17 ldw r4,-16(fp) + 8035bb0: 804060c0 call 804060c + 8035bb4: e0bffe15 stw r2,-8(fp) + break; + 8035bb8: 00013e06 br 80360b4 + { + error = ip6_pcbbind(inp, nam); + break; + } +#endif /* IP_V6 */ + dtrap(); /* not v4 or v6? */ + 8035bbc: 8028cd40 call 8028cd4 + error = EINVAL; + 8035bc0: 00800584 movi r2,22 + 8035bc4: e0bffe15 stw r2,-8(fp) + break; + 8035bc8: 00013a06 br 80360b4 + /* + * Prepare to accept connections. + */ + case PRU_LISTEN: + if (inp->inp_lport == 0) + 8035bcc: e0bffc17 ldw r2,-16(fp) + 8035bd0: 1080078b ldhu r2,30(r2) + 8035bd4: 10bfffcc andi r2,r2,65535 + 8035bd8: 1000041e bne r2,zero,8035bec + error = in_pcbbind(inp, (struct mbuf *)0); + 8035bdc: 000b883a mov r5,zero + 8035be0: e13ffc17 ldw r4,-16(fp) + 8035be4: 804060c0 call 804060c + 8035be8: e0bffe15 stw r2,-8(fp) + if (error == 0) + 8035bec: e0bffe17 ldw r2,-8(fp) + 8035bf0: 1001231e bne r2,zero,8036080 + tp->t_state = TCPS_LISTEN; + 8035bf4: e0bfff17 ldw r2,-4(fp) + 8035bf8: 00c00044 movi r3,1 + 8035bfc: 10c00215 stw r3,8(r2) + break; + 8035c00: 00011f06 br 8036080 + * Enter SYN_SENT state, and mark socket as connecting. + * Start keep-alive timer, and seed output sequence space. + * Send initial segment on connection. + */ + case PRU_CONNECT: + if (inp->inp_lport == 0) + 8035c04: e0bffc17 ldw r2,-16(fp) + 8035c08: 1080078b ldhu r2,30(r2) + 8035c0c: 10bfffcc andi r2,r2,65535 + 8035c10: 1000061e bne r2,zero,8035c2c + { + +#ifdef IP_V4 +#ifndef IP_V6 /* v4 only */ + error = in_pcbbind(inp, (struct mbuf *)0); + 8035c14: 000b883a mov r5,zero + 8035c18: e13ffc17 ldw r4,-16(fp) + 8035c1c: 804060c0 call 804060c + 8035c20: e0bffe15 stw r2,-8(fp) +#endif /* end dual mode code */ +#else /* no v4, v6 only */ + error = ip6_pcbbind(inp, (struct mbuf *)0); +#endif /* end v6 only */ + + if (error) + 8035c24: e0bffe17 ldw r2,-8(fp) + 8035c28: 1001171e bne r2,zero,8036088 + break; + } + +#ifdef IP_V4 +#ifndef IP_V6 /* v4 only */ + error = in_pcbconnect(inp, nam); + 8035c2c: e17ff817 ldw r5,-32(fp) + 8035c30: e13ffc17 ldw r4,-16(fp) + 8035c34: 804081c0 call 804081c + 8035c38: e0bffe15 stw r2,-8(fp) +#endif /* end dual mode code */ +#else /* no v4, v6 only */ + error = ip6_pcbconnect(inp, nam); +#endif /* end v6 only */ + + if (error) + 8035c3c: e0bffe17 ldw r2,-8(fp) + 8035c40: 1001131e bne r2,zero,8036090 + break; + tp->t_template = tcp_template(tp); + 8035c44: e13fff17 ldw r4,-4(fp) + 8035c48: 8034a400 call 8034a40 + 8035c4c: 1007883a mov r3,r2 + 8035c50: e0bfff17 ldw r2,-4(fp) + 8035c54: 10c00c15 stw r3,48(r2) + if (tp->t_template == 0) + 8035c58: e0bfff17 ldw r2,-4(fp) + 8035c5c: 10800c17 ldw r2,48(r2) + 8035c60: 1000051e bne r2,zero,8035c78 + { + +#ifdef IP_V4 +#ifndef IP_V6 /* v4 only */ + in_pcbdisconnect(inp); + 8035c64: e13ffc17 ldw r4,-16(fp) + 8035c68: 80409fc0 call 80409fc +#endif /* end dual mode code */ +#else /* no v4, v6 only */ + ip6_pcbdisconnect(inp); +#endif /* end v6 only */ + + error = ENOBUFS; + 8035c6c: 00801a44 movi r2,105 + 8035c70: e0bffe15 stw r2,-8(fp) + break; + 8035c74: 00010f06 br 80360b4 + } + + soisconnecting(so); + 8035c78: e13ffa17 ldw r4,-24(fp) + 8035c7c: 802f1780 call 802f178 + tcpstat.tcps_connattempt++; + 8035c80: 008201b4 movhi r2,2054 + 8035c84: 10b8a417 ldw r2,-7536(r2) + 8035c88: 10c00044 addi r3,r2,1 + 8035c8c: 008201b4 movhi r2,2054 + 8035c90: 10f8a415 stw r3,-7536(r2) + tp->t_state = TCPS_SYN_SENT; + 8035c94: e0bfff17 ldw r2,-4(fp) + 8035c98: 00c00084 movi r3,2 + 8035c9c: 10c00215 stw r3,8(r2) + tp->t_timer[TCPT_KEEP] = TCPTV_KEEP_INIT; + 8035ca0: e0bfff17 ldw r2,-4(fp) + 8035ca4: 00c02584 movi r3,150 + 8035ca8: 10c00515 stw r3,20(r2) + tp->iss = tcp_iss; + 8035cac: d0e08a17 ldw r3,-32216(gp) + 8035cb0: e0bfff17 ldw r2,-4(fp) + 8035cb4: 10c01315 stw r3,76(r2) + tcp_iss += (tcp_seq)(TCP_ISSINCR/2); + 8035cb8: d0e08a17 ldw r3,-32216(gp) + 8035cbc: 00be9fd4 movui r2,64127 + 8035cc0: 1885883a add r2,r3,r2 + 8035cc4: d0a08a15 stw r2,-32216(gp) + tcp_sendseqinit(tp); + 8035cc8: e0bfff17 ldw r2,-4(fp) + 8035ccc: 10c01317 ldw r3,76(r2) + 8035cd0: e0bfff17 ldw r2,-4(fp) + 8035cd4: 10c01015 stw r3,64(r2) + 8035cd8: e0bfff17 ldw r2,-4(fp) + 8035cdc: 10c01017 ldw r3,64(r2) + 8035ce0: e0bfff17 ldw r2,-4(fp) + 8035ce4: 10c01a15 stw r3,104(r2) + 8035ce8: e0bfff17 ldw r2,-4(fp) + 8035cec: 10c01a17 ldw r3,104(r2) + 8035cf0: e0bfff17 ldw r2,-4(fp) + 8035cf4: 10c00f15 stw r3,60(r2) + 8035cf8: e0bfff17 ldw r2,-4(fp) + 8035cfc: 10c00f17 ldw r3,60(r2) + 8035d00: e0bfff17 ldw r2,-4(fp) + 8035d04: 10c00e15 stw r3,56(r2) + error = tcp_output(tp); + 8035d08: e13fff17 ldw r4,-4(fp) + 8035d0c: 80338940 call 8033894 + 8035d10: e0bffe15 stw r2,-8(fp) + if (!error) + 8035d14: e0bffe17 ldw r2,-8(fp) + 8035d18: 1000df1e bne r2,zero,8036098 + TCP_MIB_INC(tcpActiveOpens); /* keep MIB stats */ + 8035d1c: 008201b4 movhi r2,2054 + 8035d20: 10b87a17 ldw r2,-7704(r2) + 8035d24: 10c00044 addi r3,r2,1 + 8035d28: 008201b4 movhi r2,2054 + 8035d2c: 10f87a15 stw r3,-7704(r2) + break; + 8035d30: 0000d906 br 8036098 + + /* + * Create a TCP connection between two sockets. + */ + case PRU_CONNECT2: + error = EOPNOTSUPP; + 8035d34: 008017c4 movi r2,95 + 8035d38: e0bffe15 stw r2,-8(fp) + break; + 8035d3c: 0000dd06 br 80360b4 + * when peer sends FIN and acks ours. + * + * SHOULD IMPLEMENT LATER PRU_CONNECT VIA REALLOC TCPCB. + */ + case PRU_DISCONNECT: + SETTP(tp, tcp_disconnect(tp)); + 8035d40: e13fff17 ldw r4,-4(fp) + 8035d44: 80361e40 call 80361e4 + break; + 8035d48: 0000da06 br 80360b4 + * done at higher levels; just return the address + * of the peer, storing through addr. + */ + case PRU_ACCEPT: + { + struct sockaddr_in * sin = mtod(nam, struct sockaddr_in *); + 8035d4c: e0bff817 ldw r2,-32(fp) + 8035d50: 10800317 ldw r2,12(r2) + 8035d54: e0bffb15 stw r2,-20(fp) + IP6CPY(&sin6->sin6_addr, &inp->ip6_faddr); + } +#endif + +#ifdef IP_V4 + if (so->so_domain == AF_INET) + 8035d58: e0bffa17 ldw r2,-24(fp) + 8035d5c: 10800517 ldw r2,20(r2) + 8035d60: 10800098 cmpnei r2,r2,2 + 8035d64: 10000e1e bne r2,zero,8035da0 + { + nam->m_len = sizeof (struct sockaddr_in); + 8035d68: e0bff817 ldw r2,-32(fp) + 8035d6c: 00c00404 movi r3,16 + 8035d70: 10c00215 stw r3,8(r2) + sin->sin_family = AF_INET; + 8035d74: e0bffb17 ldw r2,-20(fp) + 8035d78: 00c00084 movi r3,2 + 8035d7c: 10c0000d sth r3,0(r2) + sin->sin_port = inp->inp_fport; + 8035d80: e0bffc17 ldw r2,-16(fp) + 8035d84: 10c0070b ldhu r3,28(r2) + 8035d88: e0bffb17 ldw r2,-20(fp) + 8035d8c: 10c0008d sth r3,2(r2) + sin->sin_addr = inp->inp_faddr; + 8035d90: e0bffb17 ldw r2,-20(fp) + 8035d94: e0fffc17 ldw r3,-16(fp) + 8035d98: 18c00317 ldw r3,12(r3) + 8035d9c: 10c00115 stw r3,4(r2) + } +#endif + if ( !(so->so_domain == AF_INET) && + 8035da0: e0bffa17 ldw r2,-24(fp) + 8035da4: 10800517 ldw r2,20(r2) + 8035da8: 108000a0 cmpeqi r2,r2,2 + 8035dac: 10000b1e bne r2,zero,8035ddc + !(so->so_domain == AF_INET6) + 8035db0: e0bffa17 ldw r2,-24(fp) + 8035db4: 10800517 ldw r2,20(r2) + if ( !(so->so_domain == AF_INET) && + 8035db8: 108000e0 cmpeqi r2,r2,3 + 8035dbc: 1000071e bne r2,zero,8035ddc + ) + { + dprintf("*** PRU_ACCEPT bad domain = %d\n", so->so_domain); + 8035dc0: e0bffa17 ldw r2,-24(fp) + 8035dc4: 10800517 ldw r2,20(r2) + 8035dc8: 100b883a mov r5,r2 + 8035dcc: 01020174 movhi r4,2053 + 8035dd0: 212abb04 addi r4,r4,-21780 + 8035dd4: 8002c780 call 8002c78 + dtrap(); + 8035dd8: 8028cd40 call 8028cd4 + } + TCP_MIB_INC(tcpPassiveOpens); /* keep MIB stats */ + 8035ddc: 008201b4 movhi r2,2054 + 8035de0: 10b87b17 ldw r2,-7700(r2) + 8035de4: 10c00044 addi r3,r2,1 + 8035de8: 008201b4 movhi r2,2054 + 8035dec: 10f87b15 stw r3,-7700(r2) + break; + 8035df0: 0000b006 br 80360b4 + + /* + * Mark the connection as being incapable of further output. + */ + case PRU_SHUTDOWN: + socantsendmore(so); + 8035df4: e13ffa17 ldw r4,-24(fp) + 8035df8: 802f7f40 call 802f7f4 + tp = tcp_usrclosed(tp); + 8035dfc: e13fff17 ldw r4,-4(fp) + 8035e00: 80362b00 call 80362b0 + 8035e04: e0bfff15 stw r2,-4(fp) + if (tp) + 8035e08: e0bfff17 ldw r2,-4(fp) + 8035e0c: 1000a426 beq r2,zero,80360a0 + error = tcp_output(tp); + 8035e10: e13fff17 ldw r4,-4(fp) + 8035e14: 80338940 call 8033894 + 8035e18: e0bffe15 stw r2,-8(fp) + break; + 8035e1c: 0000a006 br 80360a0 + + /* + * After a receive, possibly send window update to peer. + */ + case PRU_RCVD: + (void) tcp_output(tp); + 8035e20: e13fff17 ldw r4,-4(fp) + 8035e24: 80338940 call 8033894 + break; + 8035e28: 0000a206 br 80360b4 + /* + * Do a send by putting data in output queue and updating urgent + * marker if URG set. Possibly send more data. + */ + case PRU_SEND: + if (so->so_pcb == NULL) + 8035e2c: e0bffa17 ldw r2,-24(fp) + 8035e30: 10800117 ldw r2,4(r2) + 8035e34: 1000031e bne r2,zero,8035e44 + { /* Return EPIPE error if socket is not connected */ + error = EPIPE; + 8035e38: 00800804 movi r2,32 + 8035e3c: e0bffe15 stw r2,-8(fp) + break; + 8035e40: 00009c06 br 80360b4 + } + sbappend(&so->so_snd, m); + 8035e44: e0bffa17 ldw r2,-24(fp) + 8035e48: 10801204 addi r2,r2,72 + 8035e4c: e17ff917 ldw r5,-28(fp) + 8035e50: 1009883a mov r4,r2 + 8035e54: 802fafc0 call 802fafc + error = tcp_output(tp); + 8035e58: e13fff17 ldw r4,-4(fp) + 8035e5c: 80338940 call 8033894 + 8035e60: e0bffe15 stw r2,-8(fp) + if (error == ENOBUFS) + 8035e64: e0bffe17 ldw r2,-8(fp) + 8035e68: 10801a58 cmpnei r2,r2,105 + 8035e6c: 10008e1e bne r2,zero,80360a8 + sbdropend(&so->so_snd,m); /* Remove data from socket buffer */ + 8035e70: e0bffa17 ldw r2,-24(fp) + 8035e74: 10801204 addi r2,r2,72 + 8035e78: e17ff917 ldw r5,-28(fp) + 8035e7c: 1009883a mov r4,r2 + 8035e80: 80302680 call 8030268 + break; + 8035e84: 00008806 br 80360a8 + + /* + * Abort the TCP. + */ + case PRU_ABORT: + SETTP(tp, tcp_drop(tp, ECONNABORTED)); + 8035e88: 01401c44 movi r5,113 + 8035e8c: e13fff17 ldw r4,-4(fp) + 8035e90: 803504c0 call 803504c + break; + 8035e94: 00008706 br 80360b4 + + case PRU_SENSE: + /* ((struct stat *) m)->st_blksize = so->so_snd.sb_hiwat; */ + dtrap(); /* does this ever happen? */ + 8035e98: 8028cd40 call 8028cd4 + return (0); + 8035e9c: 0005883a mov r2,zero + 8035ea0: 00008506 br 80360b8 + + case PRU_RCVOOB: + if ((so->so_oobmark == 0 && + 8035ea4: e0bffa17 ldw r2,-24(fp) + 8035ea8: 10801a17 ldw r2,104(r2) + 8035eac: 1000051e bne r2,zero,8035ec4 + (so->so_state & SS_RCVATMARK) == 0) || + 8035eb0: e0bffa17 ldw r2,-24(fp) + 8035eb4: 1080088b ldhu r2,34(r2) + 8035eb8: 10bfffcc andi r2,r2,65535 + 8035ebc: 1080100c andi r2,r2,64 + if ((so->so_oobmark == 0 && + 8035ec0: 10000926 beq r2,zero,8035ee8 +#ifdef SO_OOBINLINE + so->so_options & SO_OOBINLINE || + 8035ec4: e0bffa17 ldw r2,-24(fp) + 8035ec8: 10800417 ldw r2,16(r2) + 8035ecc: 1080400c andi r2,r2,256 + (so->so_state & SS_RCVATMARK) == 0) || + 8035ed0: 1000051e bne r2,zero,8035ee8 +#endif + tp->t_oobflags & TCPOOB_HADDATA) + 8035ed4: e0bfff17 ldw r2,-4(fp) + 8035ed8: 10802403 ldbu r2,144(r2) + 8035edc: 10803fcc andi r2,r2,255 + 8035ee0: 1080008c andi r2,r2,2 + so->so_options & SO_OOBINLINE || + 8035ee4: 10000326 beq r2,zero,8035ef4 + { + error = EINVAL; + 8035ee8: 00800584 movi r2,22 + 8035eec: e0bffe15 stw r2,-8(fp) + break; + 8035ef0: 00007006 br 80360b4 + } + if ((tp->t_oobflags & TCPOOB_HAVEDATA) == 0) + 8035ef4: e0bfff17 ldw r2,-4(fp) + 8035ef8: 10802403 ldbu r2,144(r2) + 8035efc: 10803fcc andi r2,r2,255 + 8035f00: 1080004c andi r2,r2,1 + 8035f04: 1000031e bne r2,zero,8035f14 + { + error = EWOULDBLOCK; + 8035f08: 008002c4 movi r2,11 + 8035f0c: e0bffe15 stw r2,-8(fp) + break; + 8035f10: 00006806 br 80360b4 + } + m->m_len = 1; + 8035f14: e0bff917 ldw r2,-28(fp) + 8035f18: 00c00044 movi r3,1 + 8035f1c: 10c00215 stw r3,8(r2) + *mtod(m, char *) = tp->t_iobc; + 8035f20: e0bff917 ldw r2,-28(fp) + 8035f24: 10800317 ldw r2,12(r2) + 8035f28: e0ffff17 ldw r3,-4(fp) + 8035f2c: 18c02443 ldbu r3,145(r3) + 8035f30: 10c00005 stb r3,0(r2) + if ((MBUF2LONG(nam) & MSG_PEEK) == 0) + 8035f34: e0bff817 ldw r2,-32(fp) + 8035f38: 1080008c andi r2,r2,2 + 8035f3c: 10005c1e bne r2,zero,80360b0 + tp->t_oobflags ^= (TCPOOB_HAVEDATA | TCPOOB_HADDATA); + 8035f40: e0bfff17 ldw r2,-4(fp) + 8035f44: 10802403 ldbu r2,144(r2) + 8035f48: 108000dc xori r2,r2,3 + 8035f4c: 1007883a mov r3,r2 + 8035f50: e0bfff17 ldw r2,-4(fp) + 8035f54: 10c02405 stb r3,144(r2) + break; + 8035f58: 00005506 br 80360b0 + + case PRU_SENDOOB: + if (so->so_pcb == NULL) + 8035f5c: e0bffa17 ldw r2,-24(fp) + 8035f60: 10800117 ldw r2,4(r2) + 8035f64: 1000031e bne r2,zero,8035f74 + { /* Return EPIPE error if socket is not connected */ + error = EPIPE; + 8035f68: 00800804 movi r2,32 + 8035f6c: e0bffe15 stw r2,-8(fp) + break; + 8035f70: 00005006 br 80360b4 + } + if (sbspace(&so->so_snd) == 0) + 8035f74: e0bffa17 ldw r2,-24(fp) + 8035f78: 10801317 ldw r2,76(r2) + 8035f7c: 1007883a mov r3,r2 + 8035f80: e0bffa17 ldw r2,-24(fp) + 8035f84: 10801217 ldw r2,72(r2) + 8035f88: 1885c83a sub r2,r3,r2 + 8035f8c: 10000516 blt r2,zero,8035fa4 + 8035f90: e0bffa17 ldw r2,-24(fp) + 8035f94: 10c01317 ldw r3,76(r2) + 8035f98: e0bffa17 ldw r2,-24(fp) + 8035f9c: 10801217 ldw r2,72(r2) + 8035fa0: 1880051e bne r3,r2,8035fb8 + { + m_freem(m); + 8035fa4: e13ff917 ldw r4,-28(fp) + 8035fa8: 8029cfc0 call 8029cfc + error = ENOBUFS; + 8035fac: 00801a44 movi r2,105 + 8035fb0: e0bffe15 stw r2,-8(fp) + break; + 8035fb4: 00003f06 br 80360b4 + * of urgent data. We continue, however, + * to consider it to indicate the first octet + * of data past the urgent section. + * Otherwise, snd_up should be one lower. + */ + sbappend(&so->so_snd, m); + 8035fb8: e0bffa17 ldw r2,-24(fp) + 8035fbc: 10801204 addi r2,r2,72 + 8035fc0: e17ff917 ldw r5,-28(fp) + 8035fc4: 1009883a mov r4,r2 + 8035fc8: 802fafc0 call 802fafc + tp->snd_up = tp->snd_una + so->so_snd.sb_cc; + 8035fcc: e0bfff17 ldw r2,-4(fp) + 8035fd0: 10c00e17 ldw r3,56(r2) + 8035fd4: e0bffa17 ldw r2,-24(fp) + 8035fd8: 10801217 ldw r2,72(r2) + 8035fdc: 1887883a add r3,r3,r2 + 8035fe0: e0bfff17 ldw r2,-4(fp) + 8035fe4: 10c01015 stw r3,64(r2) + tp->t_force = 1; + 8035fe8: e0bfff17 ldw r2,-4(fp) + 8035fec: 00c00044 movi r3,1 + 8035ff0: 10c00a85 stb r3,42(r2) + error = tcp_output(tp); + 8035ff4: e13fff17 ldw r4,-4(fp) + 8035ff8: 80338940 call 8033894 + 8035ffc: e0bffe15 stw r2,-8(fp) + if (error == ENOBUFS) + 8036000: e0bffe17 ldw r2,-8(fp) + 8036004: 10801a58 cmpnei r2,r2,105 + 8036008: 1000051e bne r2,zero,8036020 + sbdropend(&so->so_snd,m); /* Remove data from socket buffer */ + 803600c: e0bffa17 ldw r2,-24(fp) + 8036010: 10801204 addi r2,r2,72 + 8036014: e17ff917 ldw r5,-28(fp) + 8036018: 1009883a mov r4,r2 + 803601c: 80302680 call 8030268 + tp->t_force = 0; + 8036020: e0bfff17 ldw r2,-4(fp) + 8036024: 10000a85 stb zero,42(r2) + break; + 8036028: 00002206 br 80360b4 + case PRU_SOCKADDR: + + /* sockaddr and peeraddr have to switch based on IP type */ +#ifdef IP_V4 +#ifndef IP_V6 /* v4 only */ + in_setsockaddr(inp, nam); + 803602c: e17ff817 ldw r5,-32(fp) + 8036030: e13ffc17 ldw r4,-16(fp) + 8036034: 8040a580 call 8040a58 + in_setsockaddr(inp, nam); +#endif /* dual mode */ +#else /* IP_V6 */ + ip6_setsockaddr(inp, nam); +#endif + break; + 8036038: 00001e06 br 80360b4 + + case PRU_PEERADDR: +#ifdef IP_V4 +#ifndef IP_V6 /* v4 only */ + in_setpeeraddr(inp, nam); + 803603c: e17ff817 ldw r5,-32(fp) + 8036040: e13ffc17 ldw r4,-16(fp) + 8036044: 8040adc0 call 8040adc + in_setpeeraddr(inp, nam); +#endif /* dual mode */ +#else /* IP_V6 */ + ip6_setpeeraddr(inp, nam); +#endif + break; + 8036048: 00001a06 br 80360b4 + + case PRU_SLOWTIMO: + SETTP(tp, tcp_timers(tp, (int)MBUF2LONG(nam))); + 803604c: e0bff817 ldw r2,-32(fp) + 8036050: 100b883a mov r5,r2 + 8036054: e13fff17 ldw r4,-4(fp) + 8036058: 80355c00 call 80355c0 +#ifdef DO_TCPTRACE + req |= (long)nam << 8; /* for debug's sake */ +#endif + break; + 803605c: 00001506 br 80360b4 + + default: + panic("tcp_usrreq"); + 8036060: 01020174 movhi r4,2053 + 8036064: 212ac304 addi r4,r4,-21748 + 8036068: 80271780 call 8027178 + 803606c: 00001106 br 80360b4 + break; + 8036070: 0001883a nop + 8036074: 00000f06 br 80360b4 + break; + 8036078: 0001883a nop + 803607c: 00000d06 br 80360b4 + break; + 8036080: 0001883a nop + 8036084: 00000b06 br 80360b4 + break; + 8036088: 0001883a nop + 803608c: 00000906 br 80360b4 + break; + 8036090: 0001883a nop + 8036094: 00000706 br 80360b4 + break; + 8036098: 0001883a nop + 803609c: 00000506 br 80360b4 + break; + 80360a0: 0001883a nop + 80360a4: 00000306 br 80360b4 + break; + 80360a8: 0001883a nop + 80360ac: 00000106 br 80360b4 + break; + 80360b0: 0001883a nop +#ifdef DO_TCPTRACE + if (tp && (so->so_options & SO_DEBUG)) + tcp_trace("usrreq: state: %d, tcpcb: %x, req: %d", + ostate, tp, req); +#endif + return (error); + 80360b4: e0bffe17 ldw r2,-8(fp) +} + 80360b8: e037883a mov sp,fp + 80360bc: dfc00117 ldw ra,4(sp) + 80360c0: df000017 ldw fp,0(sp) + 80360c4: dec00204 addi sp,sp,8 + 80360c8: f800283a ret + +080360cc : + * RETURNS: 0 if OK, or nonzero error code. + */ + +int +tcp_attach(struct socket * so) +{ + 80360cc: defff904 addi sp,sp,-28 + 80360d0: dfc00615 stw ra,24(sp) + 80360d4: df000515 stw fp,20(sp) + 80360d8: df000504 addi fp,sp,20 + 80360dc: e13ffb15 stw r4,-20(fp) + struct tcpcb * tp; + struct inpcb * inp; + int error; + + if (so->so_snd.sb_hiwat == 0 || so->so_rcv.sb_hiwat == 0) + 80360e0: e0bffb17 ldw r2,-20(fp) + 80360e4: 10801317 ldw r2,76(r2) + 80360e8: 10000326 beq r2,zero,80360f8 + 80360ec: e0bffb17 ldw r2,-20(fp) + 80360f0: 10800b17 ldw r2,44(r2) + 80360f4: 10000b1e bne r2,zero,8036124 + { + error = soreserve(so, tcp_sendspace, tcp_recvspace); + 80360f8: d0a02017 ldw r2,-32640(gp) + 80360fc: d0e02117 ldw r3,-32636(gp) + 8036100: 180d883a mov r6,r3 + 8036104: 100b883a mov r5,r2 + 8036108: e13ffb17 ldw r4,-20(fp) + 803610c: 802f9d80 call 802f9d8 + 8036110: e0bfff15 stw r2,-4(fp) + if (error) + 8036114: e0bfff17 ldw r2,-4(fp) + 8036118: 10000226 beq r2,zero,8036124 + return (error); + 803611c: e0bfff17 ldw r2,-4(fp) + 8036120: 00002b06 br 80361d0 + } + error = in_pcballoc(so, &tcb); + 8036124: 014201b4 movhi r5,2054 + 8036128: 29789904 addi r5,r5,-7580 + 803612c: e13ffb17 ldw r4,-20(fp) + 8036130: 804052c0 call 804052c + 8036134: e0bfff15 stw r2,-4(fp) + if (error) + 8036138: e0bfff17 ldw r2,-4(fp) + 803613c: 10000226 beq r2,zero,8036148 + return (error); + 8036140: e0bfff17 ldw r2,-4(fp) + 8036144: 00002206 br 80361d0 + inp = sotoinpcb(so); + 8036148: e0bffb17 ldw r2,-20(fp) + 803614c: 10800117 ldw r2,4(r2) + 8036150: e0bffe15 stw r2,-8(fp) + tp = tcp_newtcpcb(inp); + 8036154: e13ffe17 ldw r4,-8(fp) + 8036158: 8034f400 call 8034f40 + 803615c: e0bffd15 stw r2,-12(fp) + if (tp == 0) + 8036160: e0bffd17 ldw r2,-12(fp) + 8036164: 1000171e bne r2,zero,80361c4 + { + int nofd = so->so_state & SS_NOFDREF; /* XXX */ + 8036168: e0bffb17 ldw r2,-20(fp) + 803616c: 1080088b ldhu r2,34(r2) + 8036170: 10bfffcc andi r2,r2,65535 + 8036174: 1080004c andi r2,r2,1 + 8036178: e0bffc15 stw r2,-16(fp) + + so->so_state &= ~SS_NOFDREF; /* don't free the socket yet */ + 803617c: e0bffb17 ldw r2,-20(fp) + 8036180: 10c0088b ldhu r3,34(r2) + 8036184: 00bfff84 movi r2,-2 + 8036188: 1884703a and r2,r3,r2 + 803618c: 1007883a mov r3,r2 + 8036190: e0bffb17 ldw r2,-20(fp) + 8036194: 10c0088d sth r3,34(r2) + in_pcbdetach(inp); + 8036198: e13ffe17 ldw r4,-8(fp) + 803619c: 80405b40 call 80405b4 + so->so_state |= nofd; + 80361a0: e0bffb17 ldw r2,-20(fp) + 80361a4: 1080088b ldhu r2,34(r2) + 80361a8: e0fffc17 ldw r3,-16(fp) + 80361ac: 10c4b03a or r2,r2,r3 + 80361b0: 1007883a mov r3,r2 + 80361b4: e0bffb17 ldw r2,-20(fp) + 80361b8: 10c0088d sth r3,34(r2) + return (ENOBUFS); + 80361bc: 00801a44 movi r2,105 + 80361c0: 00000306 br 80361d0 + } + tp->t_state = TCPS_CLOSED; + 80361c4: e0bffd17 ldw r2,-12(fp) + 80361c8: 10000215 stw zero,8(r2) + return (0); + 80361cc: 0005883a mov r2,zero +} + 80361d0: e037883a mov sp,fp + 80361d4: dfc00117 ldw ra,4(sp) + 80361d8: df000017 ldw fp,0(sp) + 80361dc: dec00204 addi sp,sp,8 + 80361e0: f800283a ret + +080361e4 : + * RETURNS: + */ + +struct tcpcb * +tcp_disconnect(struct tcpcb * tp) +{ + 80361e4: defffc04 addi sp,sp,-16 + 80361e8: dfc00315 stw ra,12(sp) + 80361ec: df000215 stw fp,8(sp) + 80361f0: df000204 addi fp,sp,8 + 80361f4: e13ffe15 stw r4,-8(fp) + struct socket * so = tp->t_inpcb->inp_socket; + 80361f8: e0bffe17 ldw r2,-8(fp) + 80361fc: 10800d17 ldw r2,52(r2) + 8036200: 10800817 ldw r2,32(r2) + 8036204: e0bfff15 stw r2,-4(fp) + + if (tp->t_state < TCPS_ESTABLISHED) + 8036208: e0bffe17 ldw r2,-8(fp) + 803620c: 10800217 ldw r2,8(r2) + 8036210: 10800108 cmpgei r2,r2,4 + 8036214: 1000041e bne r2,zero,8036228 + tp = tcp_close(tp); + 8036218: e13ffe17 ldw r4,-8(fp) + 803621c: 80350e80 call 80350e8 + 8036220: e0bffe15 stw r2,-8(fp) + 8036224: 00001c06 br 8036298 + else if ((so->so_options & SO_LINGER) && so->so_linger == 0) + 8036228: e0bfff17 ldw r2,-4(fp) + 803622c: 10800417 ldw r2,16(r2) + 8036230: 1080200c andi r2,r2,128 + 8036234: 10000b26 beq r2,zero,8036264 + 8036238: e0bfff17 ldw r2,-4(fp) + 803623c: 1080080b ldhu r2,32(r2) + 8036240: 10bfffcc andi r2,r2,65535 + 8036244: 10a0001c xori r2,r2,32768 + 8036248: 10a00004 addi r2,r2,-32768 + 803624c: 1000051e bne r2,zero,8036264 + tp = tcp_drop(tp, 0); + 8036250: 000b883a mov r5,zero + 8036254: e13ffe17 ldw r4,-8(fp) + 8036258: 803504c0 call 803504c + 803625c: e0bffe15 stw r2,-8(fp) + 8036260: 00000d06 br 8036298 + else + { + soisdisconnecting(so); + 8036264: e13fff17 ldw r4,-4(fp) + 8036268: 802f2ec0 call 802f2ec + sbflush(&so->so_rcv); + 803626c: e0bfff17 ldw r2,-4(fp) + 8036270: 10800a04 addi r2,r2,40 + 8036274: 1009883a mov r4,r2 + 8036278: 803002c0 call 803002c + tp = tcp_usrclosed(tp); + 803627c: e13ffe17 ldw r4,-8(fp) + 8036280: 80362b00 call 80362b0 + 8036284: e0bffe15 stw r2,-8(fp) + if (tp) + 8036288: e0bffe17 ldw r2,-8(fp) + 803628c: 10000226 beq r2,zero,8036298 + (void) tcp_output(tp); + 8036290: e13ffe17 ldw r4,-8(fp) + 8036294: 80338940 call 8033894 + } + return (tp); + 8036298: e0bffe17 ldw r2,-8(fp) +} + 803629c: e037883a mov sp,fp + 80362a0: dfc00117 ldw ra,4(sp) + 80362a4: df000017 ldw fp,0(sp) + 80362a8: dec00204 addi sp,sp,8 + 80362ac: f800283a ret + +080362b0 : + * RETURNS: + */ + +struct tcpcb * +tcp_usrclosed(struct tcpcb * tp) +{ + 80362b0: defffd04 addi sp,sp,-12 + 80362b4: dfc00215 stw ra,8(sp) + 80362b8: df000115 stw fp,4(sp) + 80362bc: df000104 addi fp,sp,4 + 80362c0: e13fff15 stw r4,-4(fp) + + switch (tp->t_state) + 80362c4: e0bfff17 ldw r2,-4(fp) + 80362c8: 10800217 ldw r2,8(r2) + 80362cc: 10c001a8 cmpgeui r3,r2,6 + 80362d0: 1800191e bne r3,zero,8036338 + 80362d4: 100690ba slli r3,r2,2 + 80362d8: 008200f4 movhi r2,2051 + 80362dc: 1885883a add r2,r3,r2 + 80362e0: 1098ba17 ldw r2,25320(r2) + 80362e4: 1000683a jmp r2 + 80362e8: 08036300 call 803630 + 80362ec: 08036300 call 803630 + 80362f0: 08036300 call 803630 + 80362f4: 08036318 cmpnei zero,at,3468 + 80362f8: 08036318 cmpnei zero,at,3468 + 80362fc: 08036328 cmpgeui zero,at,3468 + { + case TCPS_CLOSED: + case TCPS_LISTEN: + case TCPS_SYN_SENT: + tp->t_state = TCPS_CLOSED; + 8036300: e0bfff17 ldw r2,-4(fp) + 8036304: 10000215 stw zero,8(r2) + tp = tcp_close(tp); + 8036308: e13fff17 ldw r4,-4(fp) + 803630c: 80350e80 call 80350e8 + 8036310: e0bfff15 stw r2,-4(fp) + break; + 8036314: 00000806 br 8036338 + + case TCPS_SYN_RECEIVED: + case TCPS_ESTABLISHED: + tp->t_state = TCPS_FIN_WAIT_1; + 8036318: e0bfff17 ldw r2,-4(fp) + 803631c: 00c00184 movi r3,6 + 8036320: 10c00215 stw r3,8(r2) + break; + 8036324: 00000406 br 8036338 + + case TCPS_CLOSE_WAIT: + tp->t_state = TCPS_LAST_ACK; + 8036328: e0bfff17 ldw r2,-4(fp) + 803632c: 00c00204 movi r3,8 + 8036330: 10c00215 stw r3,8(r2) + break; + 8036334: 0001883a nop + } + if (tp && tp->t_state >= TCPS_FIN_WAIT_2) + 8036338: e0bfff17 ldw r2,-4(fp) + 803633c: 10000926 beq r2,zero,8036364 + 8036340: e0bfff17 ldw r2,-4(fp) + 8036344: 10800217 ldw r2,8(r2) + 8036348: 10800250 cmplti r2,r2,9 + 803634c: 1000051e bne r2,zero,8036364 + soisdisconnected(tp->t_inpcb->inp_socket); + 8036350: e0bfff17 ldw r2,-4(fp) + 8036354: 10800d17 ldw r2,52(r2) + 8036358: 10800817 ldw r2,32(r2) + 803635c: 1009883a mov r4,r2 + 8036360: 802f3840 call 802f384 + return (tp); + 8036364: e0bfff17 ldw r2,-4(fp) +} + 8036368: e037883a mov sp,fp + 803636c: dfc00117 ldw ra,4(sp) + 8036370: df000017 ldw fp,0(sp) + 8036374: dec00204 addi sp,sp,8 + 8036378: f800283a ret + +0803637c : + * RETURNS: 0 if OK, else one of the ENP_ error codes + */ + +int +tcpinit(void) +{ + 803637c: defffd04 addi sp,sp,-12 + 8036380: dfc00215 stw ra,8(sp) + 8036384: df000115 stw fp,4(sp) + 8036388: df000104 addi fp,sp,4 + tcp_sendspace = (TCP_MSS) * 2; + tcp_recvspace = (TCP_MSS) * 2; + TCPTV_MSL = (4 * PR_SLOWHZ); /* max seg lifetime default */ +#endif + + e = nptcp_init(); /* call the NetPort init in nptcp.c */ + 803638c: 802a3b00 call 802a3b0 + 8036390: e0bfff15 stw r2,-4(fp) + if (e) + 8036394: e0bfff17 ldw r2,-4(fp) + 8036398: 10000226 beq r2,zero,80363a4 + return e; + 803639c: e0bfff17 ldw r2,-4(fp) + 80363a0: 00000106 br 80363a8 + + return 0; /* good return */ + 80363a4: 0005883a mov r2,zero +} + 80363a8: e037883a mov sp,fp + 80363ac: dfc00117 ldw ra,4(sp) + 80363b0: df000017 ldw fp,0(sp) + 80363b4: dec00204 addi sp,sp,8 + 80363b8: f800283a ret + +080363bc : + * RETURNS: + */ + +UDPCONN +udp_lookup(struct socket * so) +{ + 80363bc: defffd04 addi sp,sp,-12 + 80363c0: df000215 stw fp,8(sp) + 80363c4: df000204 addi fp,sp,8 + 80363c8: e13ffe15 stw r4,-8(fp) + UDPCONN tmp; + + for (tmp = firstudp; tmp; tmp = tmp->u_next) + 80363cc: d0a09e17 ldw r2,-32136(gp) + 80363d0: e0bfff15 stw r2,-4(fp) + 80363d4: 00000906 br 80363fc + if (tmp->u_data == (void*)so) + 80363d8: e0bfff17 ldw r2,-4(fp) + 80363dc: 10800617 ldw r2,24(r2) + 80363e0: e0fffe17 ldw r3,-8(fp) + 80363e4: 1880021e bne r3,r2,80363f0 + return (tmp); + 80363e8: e0bfff17 ldw r2,-4(fp) + 80363ec: 00000606 br 8036408 + for (tmp = firstudp; tmp; tmp = tmp->u_next) + 80363f0: e0bfff17 ldw r2,-4(fp) + 80363f4: 10800017 ldw r2,0(r2) + 80363f8: e0bfff15 stw r2,-4(fp) + 80363fc: e0bfff17 ldw r2,-4(fp) + 8036400: 103ff51e bne r2,zero,80363d8 + + return NULL; /* didn't find it */ + 8036404: 0005883a mov r2,zero +} + 8036408: e037883a mov sp,fp + 803640c: df000017 ldw fp,0(sp) + 8036410: dec00104 addi sp,sp,4 + 8036414: f800283a ret + +08036418 : + * RETURNS: + */ + +int +udp_soinput(PACKET pkt, void * so_ptr) +{ + 8036418: defff504 addi sp,sp,-44 + 803641c: dfc00a15 stw ra,40(sp) + 8036420: df000915 stw fp,36(sp) + 8036424: df000904 addi fp,sp,36 + 8036428: e13ff815 stw r4,-32(fp) + 803642c: e17ff715 stw r5,-36(fp) + struct mbuf * m_in; /* packet/data mbuf */ + struct socket * so = (struct socket *)so_ptr; + 8036430: e0bff717 ldw r2,-36(fp) + 8036434: e0bfff15 stw r2,-4(fp) + struct sockaddr_in sin; + struct udp * udpp; + + LOCK_NET_RESOURCE(NET_RESID); + 8036438: 0009883a mov r4,zero + 803643c: 8028f380 call 8028f38 + + /* make sure we're not flooding input buffers */ + if ((so->so_rcv.sb_cc + pkt->nb_plen) >= so->so_rcv.sb_hiwat) + 8036440: e0bfff17 ldw r2,-4(fp) + 8036444: 10c00a17 ldw r3,40(r2) + 8036448: e0bff817 ldw r2,-32(fp) + 803644c: 10800417 ldw r2,16(r2) + 8036450: 1887883a add r3,r3,r2 + 8036454: e0bfff17 ldw r2,-4(fp) + 8036458: 10800b17 ldw r2,44(r2) + 803645c: 18800436 bltu r3,r2,8036470 + { + UNLOCK_NET_RESOURCE(NET_RESID); + 8036460: 0009883a mov r4,zero + 8036464: 8028ff40 call 8028ff4 + return ENOBUFS; + 8036468: 00801a44 movi r2,105 + 803646c: 00004d06 br 80365a4 + } + + /* alloc mbuf for received data */ + m_in = m_getnbuf(MT_RXDATA, 0); + 8036470: 000b883a mov r5,zero + 8036474: 01000044 movi r4,1 + 8036478: 8029a700 call 8029a70 + 803647c: e0bffe15 stw r2,-8(fp) + if (!m_in) + 8036480: e0bffe17 ldw r2,-8(fp) + 8036484: 1000041e bne r2,zero,8036498 + { + UNLOCK_NET_RESOURCE(NET_RESID); + 8036488: 0009883a mov r4,zero + 803648c: 8028ff40 call 8028ff4 + return ENOBUFS; + 8036490: 00801a44 movi r2,105 + 8036494: 00004306 br 80365a4 + } + + /* set data mbuf to point to start of UDP data */ + m_in->pkt = pkt; + 8036498: e0bffe17 ldw r2,-8(fp) + 803649c: e0fff817 ldw r3,-32(fp) + 80364a0: 10c00115 stw r3,4(r2) + m_in->m_data = pkt->nb_prot; + 80364a4: e0bff817 ldw r2,-32(fp) + 80364a8: 10c00317 ldw r3,12(r2) + 80364ac: e0bffe17 ldw r2,-8(fp) + 80364b0: 10c00315 stw r3,12(r2) + m_in->m_len = pkt->nb_plen; + 80364b4: e0bff817 ldw r2,-32(fp) + 80364b8: 10c00417 ldw r3,16(r2) + 80364bc: e0bffe17 ldw r2,-8(fp) + 80364c0: 10c00215 stw r3,8(r2) + m_in->m_base = pkt->nb_buff; + 80364c4: e0bff817 ldw r2,-32(fp) + 80364c8: 10c00117 ldw r3,4(r2) + 80364cc: e0bffe17 ldw r2,-8(fp) + 80364d0: 10c00415 stw r3,16(r2) + m_in->m_memsz = pkt->nb_blen; + 80364d4: e0bff817 ldw r2,-32(fp) + 80364d8: 10c00217 ldw r3,8(r2) + 80364dc: e0bffe17 ldw r2,-8(fp) + 80364e0: 10c00515 stw r3,20(r2) + + /* fill in net address info for pass to socket append()ers */ + sin.sin_addr.s_addr = pkt->fhost; + 80364e4: e0bff817 ldw r2,-32(fp) + 80364e8: 10800717 ldw r2,28(r2) + 80364ec: e0bffa15 stw r2,-24(fp) + udpp = (struct udp *)(pkt->nb_prot - sizeof(struct udp)); + 80364f0: e0bff817 ldw r2,-32(fp) + 80364f4: 10800317 ldw r2,12(r2) + 80364f8: 10bffe04 addi r2,r2,-8 + 80364fc: e0bffd15 stw r2,-12(fp) + sin.sin_port = htons(udpp->ud_srcp); + 8036500: e0bffd17 ldw r2,-12(fp) + 8036504: 1080000b ldhu r2,0(r2) + 8036508: 10bfffcc andi r2,r2,65535 + 803650c: 1004d23a srli r2,r2,8 + 8036510: 1007883a mov r3,r2 + 8036514: e0bffd17 ldw r2,-12(fp) + 8036518: 1080000b ldhu r2,0(r2) + 803651c: 10bfffcc andi r2,r2,65535 + 8036520: 1004923a slli r2,r2,8 + 8036524: 1884b03a or r2,r3,r2 + 8036528: e0bff98d sth r2,-26(fp) + sin.sin_family = AF_INET; + 803652c: 00800084 movi r2,2 + 8036530: e0bff90d sth r2,-28(fp) + + /* attempt to append address information to mbuf */ + if (!sbappendaddr(&so->so_rcv, (struct sockaddr *)&sin, m_in)) + 8036534: e0bfff17 ldw r2,-4(fp) + 8036538: 10800a04 addi r2,r2,40 + 803653c: e0fff904 addi r3,fp,-28 + 8036540: e1bffe17 ldw r6,-8(fp) + 8036544: 180b883a mov r5,r3 + 8036548: 1009883a mov r4,r2 + 803654c: 802fc740 call 802fc74 + 8036550: 1000081e bne r2,zero,8036574 + { + /* set the pkt field in the mbuf to NULL so m_free() below wont + * free the packet buffer, because that is left to the + */ + m_in->pkt = NULL; + 8036554: e0bffe17 ldw r2,-8(fp) + 8036558: 10000115 stw zero,4(r2) + /* free only the mbuf itself */ + m_free(m_in); + 803655c: e13ffe17 ldw r4,-8(fp) + 8036560: 8029bf80 call 8029bf8 + /* return error condition so caller can free the packet buffer */ + UNLOCK_NET_RESOURCE(NET_RESID); + 8036564: 0009883a mov r4,zero + 8036568: 8028ff40 call 8028ff4 + return ENOBUFS; + 803656c: 00801a44 movi r2,105 + 8036570: 00000c06 br 80365a4 + } + + tcp_wakeup(&so->so_rcv); /* wake anyone waiting for this */ + 8036574: e0bfff17 ldw r2,-4(fp) + 8036578: 10800a04 addi r2,r2,40 + 803657c: 1009883a mov r4,r2 + 8036580: 8027ba00 call 8027ba0 + + sorwakeup(so); /* wake up selects too */ + 8036584: e0bfff17 ldw r2,-4(fp) + 8036588: 10800a04 addi r2,r2,40 + 803658c: 100b883a mov r5,r2 + 8036590: e13fff17 ldw r4,-4(fp) + 8036594: 802f94c0 call 802f94c + + UNLOCK_NET_RESOURCE(NET_RESID); + 8036598: 0009883a mov r4,zero + 803659c: 8028ff40 call 8028ff4 + return 0; + 80365a0: 0005883a mov r2,zero +} + 80365a4: e037883a mov sp,fp + 80365a8: dfc00117 ldw ra,4(sp) + 80365ac: df000017 ldw fp,0(sp) + 80365b0: dec00204 addi sp,sp,8 + 80365b4: f800283a ret + +080365b8 : + +int +udp_usrreq(struct socket * so, + struct mbuf * m, + struct mbuf * nam) +{ + 80365b8: defff804 addi sp,sp,-32 + 80365bc: dfc00715 stw ra,28(sp) + 80365c0: df000615 stw fp,24(sp) + 80365c4: df000604 addi fp,sp,24 + 80365c8: e13ffd15 stw r4,-12(fp) + 80365cc: e17ffc15 stw r5,-16(fp) + 80365d0: e1bffb15 stw r6,-20(fp) + UDPCONN udpconn = (UDPCONN)NULL; + 80365d4: e03fff15 stw zero,-4(fp) + int req; + + req = so->so_req; /* get request from socket struct */ + 80365d8: e0bffd17 ldw r2,-12(fp) + 80365dc: 10800717 ldw r2,28(r2) + 80365e0: e0bffe15 stw r2,-8(fp) + + switch (req) + 80365e4: e0bffe17 ldw r2,-8(fp) + 80365e8: 10800468 cmpgeui r2,r2,17 + 80365ec: 10007a1e bne r2,zero,80367d8 + 80365f0: e0bffe17 ldw r2,-8(fp) + 80365f4: 100690ba slli r3,r2,2 + 80365f8: 008200f4 movhi r2,2051 + 80365fc: 1885883a add r2,r3,r2 + 8036600: 10998217 ldw r2,26120(r2) + 8036604: 1000683a jmp r2 + 8036608: 0803664c andi zero,at,3481 + 803660c: 080366d0 cmplti zero,at,3483 + 8036610: 0803670c andi zero,at,3484 + 8036614: 080367d8 cmpnei zero,at,3487 + 8036618: 0803670c andi zero,at,3484 + 803661c: 080367d8 cmpnei zero,at,3487 + 8036620: 080367cc andi zero,at,3487 + 8036624: 080367d8 cmpnei zero,at,3487 + 8036628: 080367cc andi zero,at,3487 + 803662c: 0803674c andi zero,at,3485 + 8036630: 080367d8 cmpnei zero,at,3487 + 8036634: 080367d8 cmpnei zero,at,3487 + 8036638: 080367d8 cmpnei zero,at,3487 + 803663c: 080367d8 cmpnei zero,at,3487 + 8036640: 080367d8 cmpnei zero,at,3487 + 8036644: 0803678c andi zero,at,3486 + 8036648: 0803678c andi zero,at,3486 + { + case PRU_ATTACH: + /* fake small windows so sockets asks us to move data */ + so->so_rcv.sb_hiwat = so->so_snd.sb_hiwat = udp_maxalloc(); + 803664c: 803dd940 call 803dd94 + 8036650: 1007883a mov r3,r2 + 8036654: e0bffd17 ldw r2,-12(fp) + 8036658: 10c01315 stw r3,76(r2) + 803665c: e0bffd17 ldw r2,-12(fp) + 8036660: 10c01317 ldw r3,76(r2) + 8036664: e0bffd17 ldw r2,-12(fp) + 8036668: 10c00b15 stw r3,44(r2) + +#ifdef IP_V4 + /* make a NetPort UDP connection */ + /* unlock the net resource; UDP will immediatly re-lock it */ + if (so->so_domain == AF_INET){ + 803666c: e0bffd17 ldw r2,-12(fp) + 8036670: 10800517 ldw r2,20(r2) + 8036674: 10800098 cmpnei r2,r2,2 + 8036678: 10000f1e bne r2,zero,80366b8 + UNLOCK_NET_RESOURCE(NET_RESID); + 803667c: 0009883a mov r4,zero + 8036680: 8028ff40 call 8028ff4 + udpconn = udp_open(0L, 0, udp_socket(), udp_soinput, so); + 8036684: 803dc280 call 803dc28 + 8036688: 10ffffcc andi r3,r2,65535 + 803668c: e0bffd17 ldw r2,-12(fp) + 8036690: d8800015 stw r2,0(sp) + 8036694: 01c200f4 movhi r7,2051 + 8036698: 39d90604 addi r7,r7,25624 + 803669c: 180d883a mov r6,r3 + 80366a0: 000b883a mov r5,zero + 80366a4: 0009883a mov r4,zero + 80366a8: 80402540 call 8040254 + 80366ac: e0bfff15 stw r2,-4(fp) + LOCK_NET_RESOURCE(NET_RESID); + 80366b0: 0009883a mov r4,zero + 80366b4: 8028f380 call 8028f38 + UNLOCK_NET_RESOURCE(NET_RESID); + udpconn = udp6_open(0L, 0, udp_socket(), udp6_soinput, so); + LOCK_NET_RESOURCE(NET_RESID); + } +#endif + if (!udpconn) + 80366b8: e0bfff17 ldw r2,-4(fp) + 80366bc: 1000021e bne r2,zero,80366c8 + return(EINVAL); + 80366c0: 00800584 movi r2,22 + 80366c4: 00004506 br 80367dc + return 0; + 80366c8: 0005883a mov r2,zero + 80366cc: 00004306 br 80367dc + case PRU_DETACH: + /* delete the NetPort UDP connection */ + udpconn = udp_lookup(so); + 80366d0: e13ffd17 ldw r4,-12(fp) + 80366d4: 80363bc0 call 80363bc + 80366d8: e0bfff15 stw r2,-4(fp) + if (!udpconn) + 80366dc: e0bfff17 ldw r2,-4(fp) + 80366e0: 1000021e bne r2,zero,80366ec + return(EINVAL); + 80366e4: 00800584 movi r2,22 + 80366e8: 00003c06 br 80367dc + /* unlock the net resource; UDP will immediatly re-lock it */ + UNLOCK_NET_RESOURCE(NET_RESID); + 80366ec: 0009883a mov r4,zero + 80366f0: 8028ff40 call 8028ff4 + udp_close(udpconn); + 80366f4: e13fff17 ldw r4,-4(fp) + 80366f8: 80404540 call 8040454 + LOCK_NET_RESOURCE(NET_RESID); + 80366fc: 0009883a mov r4,zero + 8036700: 8028f380 call 8028f38 + return 0; + 8036704: 0005883a mov r2,zero + 8036708: 00003406 br 80367dc + case PRU_CONNECT: + /* Install foreign port for UDP, making a virtual connection */ + /* fall to shared bind logic */ + case PRU_BIND: + /* do bind parameters lookups and tests */ + if (nam == NULL) + 803670c: e0bffb17 ldw r2,-20(fp) + 8036710: 1000021e bne r2,zero,803671c + return(EINVAL); + 8036714: 00800584 movi r2,22 + 8036718: 00003006 br 80367dc +#ifdef IP_V4 + if (so->so_domain == AF_INET){ + 803671c: e0bffd17 ldw r2,-12(fp) + 8036720: 10800517 ldw r2,20(r2) + 8036724: 10800098 cmpnei r2,r2,2 + 8036728: 1000051e bne r2,zero,8036740 + return udp4_sockbind(so, nam, req ); + 803672c: e1bffe17 ldw r6,-8(fp) + 8036730: e17ffb17 ldw r5,-20(fp) + 8036734: e13ffd17 ldw r4,-12(fp) + 8036738: 80367f00 call 80367f0 + 803673c: 00002706 br 80367dc +#ifdef IP_V6 + if (so->so_domain == AF_INET6){ + return udp6_sockbind(so, nam, req); + } +#endif + dtrap(); /* invalid address */ + 8036740: 8028cd40 call 8028cd4 + return EINVAL; + 8036744: 00800584 movi r2,22 + 8036748: 00002406 br 80367dc + case PRU_SEND: + /* do parameter lookups and tests */ + if (!m) /* no data passed? */ + 803674c: e0bffc17 ldw r2,-16(fp) + 8036750: 1000021e bne r2,zero,803675c + return(EINVAL); + 8036754: 00800584 movi r2,22 + 8036758: 00002006 br 80367dc +#ifdef IP_V4 + if (so->so_domain == AF_INET){ + 803675c: e0bffd17 ldw r2,-12(fp) + 8036760: 10800517 ldw r2,20(r2) + 8036764: 10800098 cmpnei r2,r2,2 + 8036768: 1000051e bne r2,zero,8036780 + return udp4_socksend(so, m, nam ); + 803676c: e1bffb17 ldw r6,-20(fp) + 8036770: e17ffc17 ldw r5,-16(fp) + 8036774: e13ffd17 ldw r4,-12(fp) + 8036778: 8036ac00 call 8036ac0 + 803677c: 00001706 br 80367dc +#ifdef IP_V6 + if (so->so_domain == AF_INET6){ + return udp6_socksend(so, m, nam); + } +#endif + dtrap(); /* invalid address */ + 8036780: 8028cd40 call 8028cd4 + return EINVAL; + 8036784: 00800584 movi r2,22 + 8036788: 00001406 br 80367dc + + case PRU_SOCKADDR: + /* fall through to share PRU_PEERADDR prefix */ + case PRU_PEERADDR: + if (nam == NULL) + 803678c: e0bffb17 ldw r2,-20(fp) + 8036790: 1000021e bne r2,zero,803679c + return(EINVAL); + 8036794: 00800584 movi r2,22 + 8036798: 00001006 br 80367dc +#ifdef IP_V4 + if (so->so_domain == AF_INET){ + 803679c: e0bffd17 ldw r2,-12(fp) + 80367a0: 10800517 ldw r2,20(r2) + 80367a4: 10800098 cmpnei r2,r2,2 + 80367a8: 1000051e bne r2,zero,80367c0 + return udp4_sockaddr(so, nam, req ); + 80367ac: e1bffe17 ldw r6,-8(fp) + 80367b0: e17ffb17 ldw r5,-20(fp) + 80367b4: e13ffd17 ldw r4,-12(fp) + 80367b8: 8036e340 call 8036e34 + 80367bc: 00000706 br 80367dc +#ifdef IP_V6 + if (so->so_domain == AF_INET6){ + return udp6_sockaddr(so, nam, req); + } +#endif + dtrap(); /* invalid address */ + 80367c0: 8028cd40 call 8028cd4 + return EINVAL; + 80367c4: 00800584 movi r2,22 + 80367c8: 00000406 br 80367dc + + case PRU_DISCONNECT: + case PRU_RCVD: + dtrap(); + 80367cc: 8028cd40 call 8028cd4 + return 0; + 80367d0: 0005883a mov r2,zero + 80367d4: 00000106 br 80367dc + case PRU_LISTEN: /* don't support these for UDP */ + case PRU_ACCEPT: + default: + return EOPNOTSUPP; + 80367d8: 008017c4 movi r2,95 + } +} + 80367dc: e037883a mov sp,fp + 80367e0: dfc00117 ldw ra,4(sp) + 80367e4: df000017 ldw fp,0(sp) + 80367e8: dec00204 addi sp,sp,8 + 80367ec: f800283a ret + +080367f0 : + +#ifdef IP_V4 +int udp4_sockbind(struct socket *so, struct mbuf *nam, int req ) +{ + 80367f0: defff304 addi sp,sp,-52 + 80367f4: dfc00c15 stw ra,48(sp) + 80367f8: df000b15 stw fp,44(sp) + 80367fc: df000b04 addi fp,sp,44 + 8036800: e13ff715 stw r4,-36(fp) + 8036804: e17ff615 stw r5,-40(fp) + 8036808: e1bff515 stw r6,-44(fp) + u_short lport; /* local port (local byte order) */ + ip_addr fhost; /* host to send to/recv from (network byte order) */ + ip_addr lhost; /* local IP address to bind to (network byte order) */ + NET ifp; + + sin = mtod(nam, struct sockaddr_in *); + 803680c: e0bff617 ldw r2,-40(fp) + 8036810: 10800317 ldw r2,12(r2) + 8036814: e0bffa15 stw r2,-24(fp) + if (sin == NULL) + 8036818: e0bffa17 ldw r2,-24(fp) + 803681c: 1000021e bne r2,zero,8036828 + return(EINVAL); + 8036820: 00800584 movi r2,22 + 8036824: 0000a106 br 8036aac + if (nam->m_len != sizeof (*sin)) + 8036828: e0bff617 ldw r2,-40(fp) + 803682c: 10800217 ldw r2,8(r2) + 8036830: 10800420 cmpeqi r2,r2,16 + 8036834: 1000021e bne r2,zero,8036840 + return(EINVAL); + 8036838: 00800584 movi r2,22 + 803683c: 00009b06 br 8036aac + udpconn = udp_lookup(so); + 8036840: e13ff717 ldw r4,-36(fp) + 8036844: 80363bc0 call 80363bc + 8036848: e0bff915 stw r2,-28(fp) + if (!udpconn) + 803684c: e0bff917 ldw r2,-28(fp) + 8036850: 1000021e bne r2,zero,803685c + return(EINVAL); + 8036854: 00800584 movi r2,22 + 8036858: 00009406 br 8036aac + if (req == PRU_BIND) + 803685c: e0bff517 ldw r2,-44(fp) + 8036860: 10800098 cmpnei r2,r2,2 + 8036864: 1000521e bne r2,zero,80369b0 + * if the caller-supplied port is 0, try to get + * the port from the UDP endpoint, or pick a new + * unique port; else, use the caller-supplied + * port + */ + if (sin->sin_port == 0) + 8036868: e0bffa17 ldw r2,-24(fp) + 803686c: 1080008b ldhu r2,2(r2) + 8036870: 10bfffcc andi r2,r2,65535 + 8036874: 10000b1e bne r2,zero,80368a4 + { + if (udpconn->u_lport != 0) + 8036878: e0bff917 ldw r2,-28(fp) + 803687c: 1080018b ldhu r2,6(r2) + 8036880: 10bfffcc andi r2,r2,65535 + 8036884: 10000426 beq r2,zero,8036898 + lport = udpconn->u_lport; + 8036888: e0bff917 ldw r2,-28(fp) + 803688c: 1080018b ldhu r2,6(r2) + 8036890: e0bffe8d sth r2,-6(fp) + 8036894: 00000e06 br 80368d0 + else + lport = udp_socket(); + 8036898: 803dc280 call 803dc28 + 803689c: e0bffe8d sth r2,-6(fp) + 80368a0: 00000b06 br 80368d0 + } + else + { + lport = ntohs(sin->sin_port); + 80368a4: e0bffa17 ldw r2,-24(fp) + 80368a8: 1080008b ldhu r2,2(r2) + 80368ac: 10bfffcc andi r2,r2,65535 + 80368b0: 1004d23a srli r2,r2,8 + 80368b4: 1007883a mov r3,r2 + 80368b8: e0bffa17 ldw r2,-24(fp) + 80368bc: 1080008b ldhu r2,2(r2) + 80368c0: 10bfffcc andi r2,r2,65535 + 80368c4: 1004923a slli r2,r2,8 + 80368c8: 1884b03a or r2,r3,r2 + 80368cc: e0bffe8d sth r2,-6(fp) + /* if the caller-supplied address is INADDR_ANY, + * don't bind to a specific address; else, + * make sure the caller-supplied address is + * an interface IP address and if so, bind to that + */ + if (sin->sin_addr.s_addr == INADDR_ANY) + 80368d0: e0bffa17 ldw r2,-24(fp) + 80368d4: 10800117 ldw r2,4(r2) + 80368d8: 1000021e bne r2,zero,80368e4 + { + lhost = 0L; + 80368dc: e03ffc15 stw zero,-16(fp) + 80368e0: 00001606 br 803693c + } + else + { + lhost = sin->sin_addr.s_addr; + 80368e4: e0bffa17 ldw r2,-24(fp) + 80368e8: 10800117 ldw r2,4(r2) + 80368ec: e0bffc15 stw r2,-16(fp) +#ifndef UDP_SKIP_LCL_ADDR_CHECK + /* verify that lhost is a local interface address */ + for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next) + 80368f0: 008201b4 movhi r2,2054 + 80368f4: 10b6a617 ldw r2,-9576(r2) + 80368f8: e0bffb15 stw r2,-20(fp) + 80368fc: 00000706 br 803691c + if (ifp->n_ipaddr == lhost) + 8036900: e0bffb17 ldw r2,-20(fp) + 8036904: 10800a17 ldw r2,40(r2) + 8036908: e0fffc17 ldw r3,-16(fp) + 803690c: 18800626 beq r3,r2,8036928 + for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next) + 8036910: e0bffb17 ldw r2,-20(fp) + 8036914: 10800017 ldw r2,0(r2) + 8036918: e0bffb15 stw r2,-20(fp) + 803691c: e0bffb17 ldw r2,-20(fp) + 8036920: 103ff71e bne r2,zero,8036900 + 8036924: 00000106 br 803692c + break; + 8036928: 0001883a nop + if (ifp == NULL) + 803692c: e0bffb17 ldw r2,-20(fp) + 8036930: 1000021e bne r2,zero,803693c + return(EADDRNOTAVAIL); + 8036934: 00801f44 movi r2,125 + 8036938: 00005c06 br 8036aac + } + + /* make sure we're not about to collide with an + * existing binding + */ + if (!(so->so_options & SO_REUSEADDR)) + 803693c: e0bff717 ldw r2,-36(fp) + 8036940: 10800417 ldw r2,16(r2) + 8036944: 1080010c andi r2,r2,4 + 8036948: 1000121e bne r2,zero,8036994 + for (udptmp = firstudp; udptmp; udptmp = udptmp->u_next) + 803694c: d0a09e17 ldw r2,-32136(gp) + 8036950: e0bfff15 stw r2,-4(fp) + 8036954: 00000d06 br 803698c + if ((udptmp->u_lport == lport) && (udptmp != udpconn)) + 8036958: e0bfff17 ldw r2,-4(fp) + 803695c: 1080018b ldhu r2,6(r2) + 8036960: e0fffe8b ldhu r3,-6(fp) + 8036964: 10bfffcc andi r2,r2,65535 + 8036968: 1880051e bne r3,r2,8036980 + 803696c: e0ffff17 ldw r3,-4(fp) + 8036970: e0bff917 ldw r2,-28(fp) + 8036974: 18800226 beq r3,r2,8036980 + return(EADDRINUSE); + 8036978: 00801c04 movi r2,112 + 803697c: 00004b06 br 8036aac + for (udptmp = firstudp; udptmp; udptmp = udptmp->u_next) + 8036980: e0bfff17 ldw r2,-4(fp) + 8036984: 10800017 ldw r2,0(r2) + 8036988: e0bfff15 stw r2,-4(fp) + 803698c: e0bfff17 ldw r2,-4(fp) + 8036990: 103ff11e bne r2,zero,8036958 + /* bind the UDP endpoint */ + udpconn->u_lport = lport; + 8036994: e0bff917 ldw r2,-28(fp) + 8036998: e0fffe8b ldhu r3,-6(fp) + 803699c: 10c0018d sth r3,6(r2) + udpconn->u_lhost = lhost; + 80369a0: e0bff917 ldw r2,-28(fp) + 80369a4: e0fffc17 ldw r3,-16(fp) + 80369a8: 10c00315 stw r3,12(r2) + 80369ac: 00003e06 br 8036aa8 + else /* PRU_CONNECT */ + { + /* connect the socket to a remote IP address and + * UDP port. + */ + fport = ntohs(sin->sin_port); + 80369b0: e0bffa17 ldw r2,-24(fp) + 80369b4: 1080008b ldhu r2,2(r2) + 80369b8: 10bfffcc andi r2,r2,65535 + 80369bc: 1004d23a srli r2,r2,8 + 80369c0: 1007883a mov r3,r2 + 80369c4: e0bffa17 ldw r2,-24(fp) + 80369c8: 1080008b ldhu r2,2(r2) + 80369cc: 10bfffcc andi r2,r2,65535 + 80369d0: 1004923a slli r2,r2,8 + 80369d4: 1884b03a or r2,r3,r2 + 80369d8: e0bff88d sth r2,-30(fp) + /* if the caller-supplied address is INADDR_ANY, + * use the wildcard address; else, use the caller- + * supplied address + */ + if (sin->sin_addr.s_addr == INADDR_ANY) + 80369dc: e0bffa17 ldw r2,-24(fp) + 80369e0: 10800117 ldw r2,4(r2) + 80369e4: 1000021e bne r2,zero,80369f0 + fhost = 0L; + 80369e8: e03ffd15 stw zero,-12(fp) + 80369ec: 00000306 br 80369fc + else + fhost = sin->sin_addr.s_addr; + 80369f0: e0bffa17 ldw r2,-24(fp) + 80369f4: 10800117 ldw r2,4(r2) + 80369f8: e0bffd15 stw r2,-12(fp) + /* prepare to bind the socket to the appropriate + * local interface address for the to-be-connected + * peer + */ + lhost = ip_mymach(fhost); + 80369fc: e13ffd17 ldw r4,-12(fp) + 8036a00: 803b0280 call 803b028 + 8036a04: e0bffc15 stw r2,-16(fp) + if (lhost == 0) + 8036a08: e0bffc17 ldw r2,-16(fp) + 8036a0c: 1000021e bne r2,zero,8036a18 + return(ENETUNREACH); + 8036a10: 00801c84 movi r2,114 + 8036a14: 00002506 br 8036aac + /* if the socket hasn't been bound to a local + * port yet, do so now + */ + lport = udpconn->u_lport; + 8036a18: e0bff917 ldw r2,-28(fp) + 8036a1c: 1080018b ldhu r2,6(r2) + 8036a20: e0bffe8d sth r2,-6(fp) + if (lport == 0) + 8036a24: e0bffe8b ldhu r2,-6(fp) + 8036a28: 1000021e bne r2,zero,8036a34 + lport = udp_socket(); + 8036a2c: 803dc280 call 803dc28 + 8036a30: e0bffe8d sth r2,-6(fp) + /* bind and connect the UDP endpoint */ + udpconn->u_lhost = lhost; + 8036a34: e0bff917 ldw r2,-28(fp) + 8036a38: e0fffc17 ldw r3,-16(fp) + 8036a3c: 10c00315 stw r3,12(r2) + udpconn->u_lport = lport; + 8036a40: e0bff917 ldw r2,-28(fp) + 8036a44: e0fffe8b ldhu r3,-6(fp) + 8036a48: 10c0018d sth r3,6(r2) + udpconn->u_fhost = fhost; + 8036a4c: e0bff917 ldw r2,-28(fp) + 8036a50: e0fffd17 ldw r3,-12(fp) + 8036a54: 10c00415 stw r3,16(r2) + udpconn->u_fport = fport; + 8036a58: e0bff917 ldw r2,-28(fp) + 8036a5c: e0fff88b ldhu r3,-30(fp) + 8036a60: 10c0020d sth r3,8(r2) + /* mark the socket as connected */ + so->so_state &= ~(SS_ISCONNECTING|SS_ISDISCONNECTING); + 8036a64: e0bff717 ldw r2,-36(fp) + 8036a68: 10c0088b ldhu r3,34(r2) + 8036a6c: 00bffcc4 movi r2,-13 + 8036a70: 1884703a and r2,r3,r2 + 8036a74: 1007883a mov r3,r2 + 8036a78: e0bff717 ldw r2,-36(fp) + 8036a7c: 10c0088d sth r3,34(r2) + so->so_state |= SS_ISCONNECTED; + 8036a80: e0bff717 ldw r2,-36(fp) + 8036a84: 1080088b ldhu r2,34(r2) + 8036a88: 10800094 ori r2,r2,2 + 8036a8c: 1007883a mov r3,r2 + 8036a90: e0bff717 ldw r2,-36(fp) + 8036a94: 10c0088d sth r3,34(r2) + /* since socket was in listen state, packets may be queued */ + sbflush(&so->so_rcv); /* dump these now */ + 8036a98: e0bff717 ldw r2,-36(fp) + 8036a9c: 10800a04 addi r2,r2,40 + 8036aa0: 1009883a mov r4,r2 + 8036aa4: 803002c0 call 803002c + } + return 0; + 8036aa8: 0005883a mov r2,zero +} + 8036aac: e037883a mov sp,fp + 8036ab0: dfc00117 ldw ra,4(sp) + 8036ab4: df000017 ldw fp,0(sp) + 8036ab8: dec00204 addi sp,sp,8 + 8036abc: f800283a ret + +08036ac0 : + +int udp4_socksend(struct socket *so, struct mbuf *m, + struct mbuf *nam ) +{ + 8036ac0: defff304 addi sp,sp,-52 + 8036ac4: dfc00c15 stw ra,48(sp) + 8036ac8: df000b15 stw fp,44(sp) + 8036acc: dc000a15 stw r16,40(sp) + 8036ad0: df000b04 addi fp,sp,44 + 8036ad4: e13ff715 stw r4,-36(fp) + 8036ad8: e17ff615 stw r5,-40(fp) + 8036adc: e1bff515 stw r6,-44(fp) + PACKET pkt; +#ifdef MULTI_HOMED + NET ifp; +#endif + + udpconn = udp_lookup(so); + 8036ae0: e13ff717 ldw r4,-36(fp) + 8036ae4: 80363bc0 call 80363bc + 8036ae8: e0bffb15 stw r2,-20(fp) + if (!udpconn) + 8036aec: e0bffb17 ldw r2,-20(fp) + 8036af0: 1000041e bne r2,zero,8036b04 + { + m_free(m); + 8036af4: e13ff617 ldw r4,-40(fp) + 8036af8: 8029bf80 call 8029bf8 + /* may be bogus socket, but more likely the connection may + have closed due to ICMP dest unreachable from other side. */ + return(ECONNREFUSED); + 8036afc: 00801bc4 movi r2,111 + 8036b00: 0000c606 br 8036e1c + } + + if (nam == NULL) /* no sendto() info passed, must be send() */ + 8036b04: e0bff517 ldw r2,-44(fp) + 8036b08: 10000e1e bne r2,zero,8036b44 + { + if (so->so_state & SS_ISCONNECTED) + 8036b0c: e0bff717 ldw r2,-36(fp) + 8036b10: 1080088b ldhu r2,34(r2) + 8036b14: 10bfffcc andi r2,r2,65535 + 8036b18: 1080008c andi r2,r2,2 + 8036b1c: 10000726 beq r2,zero,8036b3c + { + fport = udpconn->u_fport; + 8036b20: e0bffb17 ldw r2,-20(fp) + 8036b24: 1080020b ldhu r2,8(r2) + 8036b28: e0bffe8d sth r2,-6(fp) + fhost = udpconn->u_fhost; + 8036b2c: e0bffb17 ldw r2,-20(fp) + 8036b30: 10800417 ldw r2,16(r2) + 8036b34: e0bffd15 stw r2,-12(fp) + 8036b38: 00002806 br 8036bdc + } + else + return (EINVAL); + 8036b3c: 00800584 movi r2,22 + 8036b40: 0000b606 br 8036e1c + } + else if(nam->m_len != sizeof (*sin)) + 8036b44: e0bff517 ldw r2,-44(fp) + 8036b48: 10800217 ldw r2,8(r2) + 8036b4c: 10800420 cmpeqi r2,r2,16 + 8036b50: 1000031e bne r2,zero,8036b60 + { + dtrap(); + 8036b54: 8028cd40 call 8028cd4 + return (EINVAL); + 8036b58: 00800584 movi r2,22 + 8036b5c: 0000af06 br 8036e1c + } + else + { + sin = mtod(nam, struct sockaddr_in *); + 8036b60: e0bff517 ldw r2,-44(fp) + 8036b64: 10800317 ldw r2,12(r2) + 8036b68: e0bffa15 stw r2,-24(fp) + fhost = sin->sin_addr.s_addr; + 8036b6c: e0bffa17 ldw r2,-24(fp) + 8036b70: 10800117 ldw r2,4(r2) + 8036b74: e0bffd15 stw r2,-12(fp) + /* use caller's fport if specified, ours may be a wildcard */ + if (sin->sin_port) /* caller gets to change fport on the fly */ + 8036b78: e0bffa17 ldw r2,-24(fp) + 8036b7c: 1080008b ldhu r2,2(r2) + 8036b80: 10bfffcc andi r2,r2,65535 + 8036b84: 10000c26 beq r2,zero,8036bb8 + fport = ntohs(sin->sin_port); + 8036b88: e0bffa17 ldw r2,-24(fp) + 8036b8c: 1080008b ldhu r2,2(r2) + 8036b90: 10bfffcc andi r2,r2,65535 + 8036b94: 1004d23a srli r2,r2,8 + 8036b98: 1007883a mov r3,r2 + 8036b9c: e0bffa17 ldw r2,-24(fp) + 8036ba0: 1080008b ldhu r2,2(r2) + 8036ba4: 10bfffcc andi r2,r2,65535 + 8036ba8: 1004923a slli r2,r2,8 + 8036bac: 1884b03a or r2,r3,r2 + 8036bb0: e0bffe8d sth r2,-6(fp) + 8036bb4: 00000906 br 8036bdc + else /* use port already set in UDP connection */ + { + if (udpconn->u_fport == 0) /* don't send to port 0 */ + 8036bb8: e0bffb17 ldw r2,-20(fp) + 8036bbc: 1080020b ldhu r2,8(r2) + 8036bc0: 10bfffcc andi r2,r2,65535 + 8036bc4: 1000021e bne r2,zero,8036bd0 + return (EINVAL); + 8036bc8: 00800584 movi r2,22 + 8036bcc: 00009306 br 8036e1c + fport = udpconn->u_fport; + 8036bd0: e0bffb17 ldw r2,-20(fp) + 8036bd4: 1080020b ldhu r2,8(r2) + 8036bd8: e0bffe8d sth r2,-6(fp) + + /* since our pkt->nb_buff size is tied to max packet size, we + * assume our UDP datagrams are always in one mbuf and that the + * mbuf + */ + if (m->m_len > (unsigned)udp_maxalloc()) /* but check anyway:*/ + 8036bdc: e0bff617 ldw r2,-40(fp) + 8036be0: 14000217 ldw r16,8(r2) + 8036be4: 803dd940 call 803dd94 + 8036be8: 1400032e bgeu r2,r16,8036bf8 + { + dtrap(); /* should never happen */ + 8036bec: 8028cd40 call 8028cd4 + return EMSGSIZE; /* try to recover */ + 8036bf0: 00801e84 movi r2,122 + 8036bf4: 00008906 br 8036e1c + } + pkt = udp_alloc(m->m_len, 0); /* get a NetPort buffer for send */ + 8036bf8: e0bff617 ldw r2,-40(fp) + 8036bfc: 10800217 ldw r2,8(r2) + 8036c00: 000b883a mov r5,zero + 8036c04: 1009883a mov r4,r2 + 8036c08: 803dcd80 call 803dcd8 + 8036c0c: e0bff915 stw r2,-28(fp) + if (!pkt) + 8036c10: e0bff917 ldw r2,-28(fp) + 8036c14: 1000041e bne r2,zero,8036c28 + { + m_free(m); + 8036c18: e13ff617 ldw r4,-40(fp) + 8036c1c: 8029bf80 call 8029bf8 + return ENOBUFS; /* report buffer shortages */ + 8036c20: 00801a44 movi r2,105 + 8036c24: 00007d06 br 8036e1c + } + MEMCPY(pkt->nb_prot, m->m_data, m->m_len); + 8036c28: e0bff917 ldw r2,-28(fp) + 8036c2c: 10c00317 ldw r3,12(r2) + 8036c30: e0bff617 ldw r2,-40(fp) + 8036c34: 11000317 ldw r4,12(r2) + 8036c38: e0bff617 ldw r2,-40(fp) + 8036c3c: 10800217 ldw r2,8(r2) + 8036c40: 100d883a mov r6,r2 + 8036c44: 200b883a mov r5,r4 + 8036c48: 1809883a mov r4,r3 + 8036c4c: 80086b80 call 80086b8 + pkt->nb_plen = m->m_len; + 8036c50: e0bff617 ldw r2,-40(fp) + 8036c54: 10c00217 ldw r3,8(r2) + 8036c58: e0bff917 ldw r2,-28(fp) + 8036c5c: 10c00415 stw r3,16(r2) + /* finished with mbuf, free it now */ + m_free(m); + 8036c60: e13ff617 ldw r4,-40(fp) + 8036c64: 8029bf80 call 8029bf8 + pkt->fhost = fhost; + 8036c68: e0bff917 ldw r2,-28(fp) + 8036c6c: e0fffd17 ldw r3,-12(fp) + 8036c70: 10c00715 stw r3,28(r2) + * is up; if (after all that) we don't have an interface then we + * fail with error EADDRNOTAVAIL; and finally, if we're built + * for a single-homed configuration where there's only one + * interface, we might as well use it, so we do. + */ + if (fhost == 0xffffffff) + 8036c74: e0bffd17 ldw r2,-12(fp) + 8036c78: 10bfffd8 cmpnei r2,r2,-1 + 8036c7c: 1000471e bne r2,zero,8036d9c + { +#ifdef MULTI_HOMED + if (udpconn->u_lhost != 0L) + 8036c80: e0bffb17 ldw r2,-20(fp) + 8036c84: 10800317 ldw r2,12(r2) + 8036c88: 10000f26 beq r2,zero,8036cc8 + { + for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next) + 8036c8c: 008201b4 movhi r2,2054 + 8036c90: 10b6a617 ldw r2,-9576(r2) + 8036c94: e0bffc15 stw r2,-16(fp) + 8036c98: 00000806 br 8036cbc + if (ifp->n_ipaddr == udpconn->u_lhost) + 8036c9c: e0bffc17 ldw r2,-16(fp) + 8036ca0: 10c00a17 ldw r3,40(r2) + 8036ca4: e0bffb17 ldw r2,-20(fp) + 8036ca8: 10800317 ldw r2,12(r2) + 8036cac: 18801c26 beq r3,r2,8036d20 + for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next) + 8036cb0: e0bffc17 ldw r2,-16(fp) + 8036cb4: 10800017 ldw r2,0(r2) + 8036cb8: e0bffc15 stw r2,-16(fp) + 8036cbc: e0bffc17 ldw r2,-16(fp) + 8036cc0: 103ff61e bne r2,zero,8036c9c + 8036cc4: 00001906 br 8036d2c + break; + } + else { + for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next) + 8036cc8: 008201b4 movhi r2,2054 + 8036ccc: 10b6a617 ldw r2,-9576(r2) + 8036cd0: e0bffc15 stw r2,-16(fp) + 8036cd4: 00000f06 br 8036d14 + if ((ifp->n_flags & NF_BCAST) && + 8036cd8: e0bffc17 ldw r2,-16(fp) + 8036cdc: 10802a17 ldw r2,168(r2) + 8036ce0: 1080004c andi r2,r2,1 + 8036ce4: 10000826 beq r2,zero,8036d08 + (ifp->n_mib) && (ifp->n_mib->ifAdminStatus == NI_UP)) + 8036ce8: e0bffc17 ldw r2,-16(fp) + 8036cec: 10802717 ldw r2,156(r2) + if ((ifp->n_flags & NF_BCAST) && + 8036cf0: 10000526 beq r2,zero,8036d08 + (ifp->n_mib) && (ifp->n_mib->ifAdminStatus == NI_UP)) + 8036cf4: e0bffc17 ldw r2,-16(fp) + 8036cf8: 10802717 ldw r2,156(r2) + 8036cfc: 10800617 ldw r2,24(r2) + 8036d00: 10800058 cmpnei r2,r2,1 + 8036d04: 10000826 beq r2,zero,8036d28 + for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next) + 8036d08: e0bffc17 ldw r2,-16(fp) + 8036d0c: 10800017 ldw r2,0(r2) + 8036d10: e0bffc15 stw r2,-16(fp) + 8036d14: e0bffc17 ldw r2,-16(fp) + 8036d18: 103fef1e bne r2,zero,8036cd8 + 8036d1c: 00000306 br 8036d2c + break; + 8036d20: 0001883a nop + 8036d24: 00000106 br 8036d2c + break; + 8036d28: 0001883a nop + } + if (ifp == NULL) + 8036d2c: e0bffc17 ldw r2,-16(fp) + 8036d30: 1000171e bne r2,zero,8036d90 + { + for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next) + 8036d34: 008201b4 movhi r2,2054 + 8036d38: 10b6a617 ldw r2,-9576(r2) + 8036d3c: e0bffc15 stw r2,-16(fp) + 8036d40: 00000b06 br 8036d70 + if ((ifp->n_mib) && (ifp->n_mib->ifAdminStatus == NI_UP)) + 8036d44: e0bffc17 ldw r2,-16(fp) + 8036d48: 10802717 ldw r2,156(r2) + 8036d4c: 10000526 beq r2,zero,8036d64 + 8036d50: e0bffc17 ldw r2,-16(fp) + 8036d54: 10802717 ldw r2,156(r2) + 8036d58: 10800617 ldw r2,24(r2) + 8036d5c: 10800058 cmpnei r2,r2,1 + 8036d60: 10000626 beq r2,zero,8036d7c + for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next) + 8036d64: e0bffc17 ldw r2,-16(fp) + 8036d68: 10800017 ldw r2,0(r2) + 8036d6c: e0bffc15 stw r2,-16(fp) + 8036d70: e0bffc17 ldw r2,-16(fp) + 8036d74: 103ff31e bne r2,zero,8036d44 + 8036d78: 00000106 br 8036d80 + break; + 8036d7c: 0001883a nop + if (ifp == NULL) + 8036d80: e0bffc17 ldw r2,-16(fp) + 8036d84: 1000021e bne r2,zero,8036d90 + return(EADDRNOTAVAIL); + 8036d88: 00801f44 movi r2,125 + 8036d8c: 00002306 br 8036e1c + } + pkt->net = ifp; + 8036d90: e0bff917 ldw r2,-28(fp) + 8036d94: e0fffc17 ldw r3,-16(fp) + 8036d98: 10c00615 stw r3,24(r2) +#ifdef IP_MULTICAST + + /* If the socket has an IP moptions structure for multicast options, + * place a pointer to this structure in the PACKET structure. + */ + if (so->inp_moptions) + 8036d9c: e0bff717 ldw r2,-36(fp) + 8036da0: 10800317 ldw r2,12(r2) + 8036da4: 10000426 beq r2,zero,8036db8 + pkt->imo = so->inp_moptions; + 8036da8: e0bff717 ldw r2,-36(fp) + 8036dac: 10c00317 ldw r3,12(r2) + 8036db0: e0bff917 ldw r2,-28(fp) + 8036db4: 10c00b15 stw r3,44(r2) + +#endif /* IP_MULTICAST */ + + /* have we set options? */ + if (so->so_optsPack) + 8036db8: e0bff717 ldw r2,-36(fp) + 8036dbc: 10801f17 ldw r2,124(r2) + 8036dc0: 10000426 beq r2,zero,8036dd4 + pkt->soxopts = so->so_optsPack; /* yup - copy to pkt */ + 8036dc4: e0bff717 ldw r2,-36(fp) + 8036dc8: 10c01f17 ldw r3,124(r2) + 8036dcc: e0bff917 ldw r2,-28(fp) + 8036dd0: 10c00c15 stw r3,48(r2) + + /* unlock the net resource; UDP will immediately re-lock it */ + UNLOCK_NET_RESOURCE(NET_RESID); + 8036dd4: 0009883a mov r4,zero + 8036dd8: 8028ff40 call 8028ff4 + e = udp_send(fport, udpconn->u_lport, pkt); + 8036ddc: e0fffe8b ldhu r3,-6(fp) + 8036de0: e0bffb17 ldw r2,-20(fp) + 8036de4: 1080018b ldhu r2,6(r2) + 8036de8: 10bfffcc andi r2,r2,65535 + 8036dec: e1bff917 ldw r6,-28(fp) + 8036df0: 100b883a mov r5,r2 + 8036df4: 1809883a mov r4,r3 + 8036df8: 803d8a00 call 803d8a0 + 8036dfc: e0bff815 stw r2,-32(fp) + LOCK_NET_RESOURCE(NET_RESID); + 8036e00: 0009883a mov r4,zero + 8036e04: 8028f380 call 8028f38 + if (e < 0) + 8036e08: e0bff817 ldw r2,-32(fp) + 8036e0c: 1000020e bge r2,zero,8036e18 + return(e); + 8036e10: e0bff817 ldw r2,-32(fp) + 8036e14: 00000106 br 8036e1c + return 0; + 8036e18: 0005883a mov r2,zero +} + 8036e1c: e6ffff04 addi sp,fp,-4 + 8036e20: dfc00217 ldw ra,8(sp) + 8036e24: df000117 ldw fp,4(sp) + 8036e28: dc000017 ldw r16,0(sp) + 8036e2c: dec00304 addi sp,sp,12 + 8036e30: f800283a ret + +08036e34 : + +int udp4_sockaddr(struct socket *so, struct mbuf *nam , int req) +{ + 8036e34: defff904 addi sp,sp,-28 + 8036e38: dfc00615 stw ra,24(sp) + 8036e3c: df000515 stw fp,20(sp) + 8036e40: df000504 addi fp,sp,20 + 8036e44: e13ffd15 stw r4,-12(fp) + 8036e48: e17ffc15 stw r5,-16(fp) + 8036e4c: e1bffb15 stw r6,-20(fp) + struct sockaddr_in * sin; + UDPCONN udpconn; + + sin = mtod(nam, struct sockaddr_in *); + 8036e50: e0bffc17 ldw r2,-16(fp) + 8036e54: 10800317 ldw r2,12(r2) + 8036e58: e0bfff15 stw r2,-4(fp) + if (sin == NULL) + 8036e5c: e0bfff17 ldw r2,-4(fp) + 8036e60: 1000021e bne r2,zero,8036e6c + return(EINVAL); + 8036e64: 00800584 movi r2,22 + 8036e68: 00003706 br 8036f48 + udpconn = udp_lookup(so); + 8036e6c: e13ffd17 ldw r4,-12(fp) + 8036e70: 80363bc0 call 80363bc + 8036e74: e0bffe15 stw r2,-8(fp) + if (!udpconn) + 8036e78: e0bffe17 ldw r2,-8(fp) + 8036e7c: 1000021e bne r2,zero,8036e88 + return(EINVAL); + 8036e80: 00800584 movi r2,22 + 8036e84: 00003006 br 8036f48 + nam->m_len = sizeof(*sin); + 8036e88: e0bffc17 ldw r2,-16(fp) + 8036e8c: 00c00404 movi r3,16 + 8036e90: 10c00215 stw r3,8(r2) + if (req == PRU_SOCKADDR) + 8036e94: e0bffb17 ldw r2,-20(fp) + 8036e98: 108003d8 cmpnei r2,r2,15 + 8036e9c: 1000151e bne r2,zero,8036ef4 + { + sin->sin_family = AF_INET; + 8036ea0: e0bfff17 ldw r2,-4(fp) + 8036ea4: 00c00084 movi r3,2 + 8036ea8: 10c0000d sth r3,0(r2) + sin->sin_port = htons(udpconn->u_lport); + 8036eac: e0bffe17 ldw r2,-8(fp) + 8036eb0: 1080018b ldhu r2,6(r2) + 8036eb4: 10bfffcc andi r2,r2,65535 + 8036eb8: 1004d23a srli r2,r2,8 + 8036ebc: 1007883a mov r3,r2 + 8036ec0: e0bffe17 ldw r2,-8(fp) + 8036ec4: 1080018b ldhu r2,6(r2) + 8036ec8: 10bfffcc andi r2,r2,65535 + 8036ecc: 1004923a slli r2,r2,8 + 8036ed0: 1884b03a or r2,r3,r2 + 8036ed4: 1007883a mov r3,r2 + 8036ed8: e0bfff17 ldw r2,-4(fp) + 8036edc: 10c0008d sth r3,2(r2) + sin->sin_addr.s_addr = udpconn->u_lhost; + 8036ee0: e0bffe17 ldw r2,-8(fp) + 8036ee4: 10c00317 ldw r3,12(r2) + 8036ee8: e0bfff17 ldw r2,-4(fp) + 8036eec: 10c00115 stw r3,4(r2) + 8036ef0: 00001406 br 8036f44 + } + else /* PRU_PEERADDR */ + { + sin->sin_family = AF_INET; + 8036ef4: e0bfff17 ldw r2,-4(fp) + 8036ef8: 00c00084 movi r3,2 + 8036efc: 10c0000d sth r3,0(r2) + sin->sin_port = htons(udpconn->u_fport); + 8036f00: e0bffe17 ldw r2,-8(fp) + 8036f04: 1080020b ldhu r2,8(r2) + 8036f08: 10bfffcc andi r2,r2,65535 + 8036f0c: 1004d23a srli r2,r2,8 + 8036f10: 1007883a mov r3,r2 + 8036f14: e0bffe17 ldw r2,-8(fp) + 8036f18: 1080020b ldhu r2,8(r2) + 8036f1c: 10bfffcc andi r2,r2,65535 + 8036f20: 1004923a slli r2,r2,8 + 8036f24: 1884b03a or r2,r3,r2 + 8036f28: 1007883a mov r3,r2 + 8036f2c: e0bfff17 ldw r2,-4(fp) + 8036f30: 10c0008d sth r3,2(r2) + sin->sin_addr.s_addr = udpconn->u_fhost; + 8036f34: e0bffe17 ldw r2,-8(fp) + 8036f38: 10c00417 ldw r3,16(r2) + 8036f3c: e0bfff17 ldw r2,-4(fp) + 8036f40: 10c00115 stw r3,4(r2) + } + return 0; + 8036f44: 0005883a mov r2,zero +} + 8036f48: e037883a mov sp,fp + 8036f4c: dfc00117 ldw ra,4(sp) + 8036f50: df000017 ldw fp,0(sp) + 8036f54: dec00204 addi sp,sp,8 + 8036f58: f800283a ret + +08036f5c : +#include "alt_types.h" + +#include "priv/alt_busy_sleep.h" + +unsigned int alt_busy_sleep (unsigned int us) +{ + 8036f5c: defffa04 addi sp,sp,-24 + 8036f60: dfc00515 stw ra,20(sp) + 8036f64: df000415 stw fp,16(sp) + 8036f68: df000404 addi fp,sp,16 + 8036f6c: e13ffc15 stw r4,-16(fp) + { + cycles_per_loop = 9; + } + else + { + cycles_per_loop = 3; + 8036f70: 008000c4 movi r2,3 + 8036f74: e0bffe15 stw r2,-8(fp) + } + + + big_loops = us / (INT_MAX/ + (ALT_CPU_FREQ/(cycles_per_loop * 1000000))); + 8036f78: e0fffe17 ldw r3,-8(fp) + 8036f7c: 008003f4 movhi r2,15 + 8036f80: 10909004 addi r2,r2,16960 + 8036f84: 1885383a mul r2,r3,r2 + 8036f88: 100b883a mov r5,r2 + 8036f8c: 0100bef4 movhi r4,763 + 8036f90: 213c2004 addi r4,r4,-3968 + 8036f94: 800cff80 call 800cff8 <__udivsi3> + big_loops = us / (INT_MAX/ + 8036f98: 100b883a mov r5,r2 + 8036f9c: 01200034 movhi r4,32768 + 8036fa0: 213fffc4 addi r4,r4,-1 + 8036fa4: 800cff80 call 800cff8 <__udivsi3> + 8036fa8: 100b883a mov r5,r2 + 8036fac: e13ffc17 ldw r4,-16(fp) + 8036fb0: 800cff80 call 800cff8 <__udivsi3> + 8036fb4: e0bffd15 stw r2,-12(fp) + + if (big_loops) + 8036fb8: e0bffd17 ldw r2,-12(fp) + 8036fbc: 10002a26 beq r2,zero,8037068 + { + for(i=0;i + /* + * Do NOT Try to single step the asm statement below + * (single step will never return) + * Step out of this function or set a breakpoint after the asm statements + */ + __asm__ volatile ( + 8036fc8: 00a00034 movhi r2,32768 + 8036fcc: 10bfffc4 addi r2,r2,-1 + 8036fd0: 10bfffc4 addi r2,r2,-1 + 8036fd4: 103ffe1e bne r2,zero,8036fd0 + "\n\t.pushsection .debug_alt_sim_info" + "\n\t.int 4, 0, 0b, 1b" + "\n\t.popsection" + :: "r" (INT_MAX)); + us -= (INT_MAX/(ALT_CPU_FREQ/ + (cycles_per_loop * 1000000))); + 8036fd8: e0fffe17 ldw r3,-8(fp) + 8036fdc: 008003f4 movhi r2,15 + 8036fe0: 10909004 addi r2,r2,16960 + 8036fe4: 1885383a mul r2,r3,r2 + us -= (INT_MAX/(ALT_CPU_FREQ/ + 8036fe8: 100b883a mov r5,r2 + 8036fec: 0100bef4 movhi r4,763 + 8036ff0: 213c2004 addi r4,r4,-3968 + 8036ff4: 800cff80 call 800cff8 <__udivsi3> + 8036ff8: 100b883a mov r5,r2 + 8036ffc: 01200034 movhi r4,32768 + 8037000: 213fffc4 addi r4,r4,-1 + 8037004: 800cff80 call 800cff8 <__udivsi3> + 8037008: 1007883a mov r3,r2 + 803700c: e0bffc17 ldw r2,-16(fp) + 8037010: 10c5c83a sub r2,r2,r3 + 8037014: e0bffc15 stw r2,-16(fp) + for(i=0;i + "\n\tbne %0,zero,0b" + "\n1:" + "\n\t.pushsection .debug_alt_sim_info" + "\n\t.int 4, 0, 0b, 1b" + "\n\t.popsection" + :: "r" (us*(ALT_CPU_FREQ/(cycles_per_loop * 1000000)))); + 8037030: e0fffe17 ldw r3,-8(fp) + 8037034: 008003f4 movhi r2,15 + 8037038: 10909004 addi r2,r2,16960 + 803703c: 1885383a mul r2,r3,r2 + 8037040: 100b883a mov r5,r2 + 8037044: 0100bef4 movhi r4,763 + 8037048: 213c2004 addi r4,r4,-3968 + 803704c: 800cff80 call 800cff8 <__udivsi3> + 8037050: 1007883a mov r3,r2 + 8037054: e0bffc17 ldw r2,-16(fp) + 8037058: 1885383a mul r2,r3,r2 + __asm__ volatile ( + 803705c: 10bfffc4 addi r2,r2,-1 + 8037060: 103ffe1e bne r2,zero,803705c + 8037064: 00000d06 br 803709c + "\n\tbgt %0,zero,0b" + "\n1:" + "\n\t.pushsection .debug_alt_sim_info" + "\n\t.int 4, 0, 0b, 1b" + "\n\t.popsection" + :: "r" (us*(ALT_CPU_FREQ/(cycles_per_loop * 1000000)))); + 8037068: e0fffe17 ldw r3,-8(fp) + 803706c: 008003f4 movhi r2,15 + 8037070: 10909004 addi r2,r2,16960 + 8037074: 1885383a mul r2,r3,r2 + 8037078: 100b883a mov r5,r2 + 803707c: 0100bef4 movhi r4,763 + 8037080: 213c2004 addi r4,r4,-3968 + 8037084: 800cff80 call 800cff8 <__udivsi3> + 8037088: 1007883a mov r3,r2 + 803708c: e0bffc17 ldw r2,-16(fp) + 8037090: 1885383a mul r2,r3,r2 + __asm__ volatile ( + 8037094: 10bfffc4 addi r2,r2,-1 + 8037098: 00bffe16 blt zero,r2,8037094 + } +#endif /* #ifndef ALT_SIM_OPTIMIZE */ + return 0; + 803709c: 0005883a mov r2,zero +} + 80370a0: e037883a mov sp,fp + 80370a4: dfc00117 ldw ra,4(sp) + 80370a8: df000017 ldw fp,0(sp) + 80370ac: dec00204 addi sp,sp,8 + 80370b0: f800283a ret + +080370b4 : +{ + 80370b4: defffe04 addi sp,sp,-8 + 80370b8: dfc00115 stw ra,4(sp) + 80370bc: df000015 stw fp,0(sp) + 80370c0: d839883a mov fp,sp + return ((alt_errno) ? alt_errno() : &errno); + 80370c4: d0a02717 ldw r2,-32612(gp) + 80370c8: 10000326 beq r2,zero,80370d8 + 80370cc: d0a02717 ldw r2,-32612(gp) + 80370d0: 103ee83a callr r2 + 80370d4: 00000106 br 80370dc + 80370d8: d0a04204 addi r2,gp,-32504 +} + 80370dc: e037883a mov sp,fp + 80370e0: dfc00117 ldw ra,4(sp) + 80370e4: df000017 ldw fp,0(sp) + 80370e8: dec00204 addi sp,sp,8 + 80370ec: f800283a ret + +080370f0 : + * + * ALT_CLOSE is mapped onto the close() system call in alt_syscall.h + */ + +int ALT_CLOSE (int fildes) +{ + 80370f0: defffb04 addi sp,sp,-20 + 80370f4: dfc00415 stw ra,16(sp) + 80370f8: df000315 stw fp,12(sp) + 80370fc: df000304 addi fp,sp,12 + 8037100: e13ffd15 stw r4,-12(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (fildes < 0) ? NULL : &alt_fd_list[fildes]; + 8037104: e0bffd17 ldw r2,-12(fp) + 8037108: 10000616 blt r2,zero,8037124 + 803710c: e0bffd17 ldw r2,-12(fp) + 8037110: 10c00324 muli r3,r2,12 + 8037114: 00820174 movhi r2,2053 + 8037118: 10b21a04 addi r2,r2,-14232 + 803711c: 1885883a add r2,r3,r2 + 8037120: 00000106 br 8037128 + 8037124: 0005883a mov r2,zero + 8037128: e0bfff15 stw r2,-4(fp) + + if (fd) + 803712c: e0bfff17 ldw r2,-4(fp) + 8037130: 10001926 beq r2,zero,8037198 + /* + * If the associated file system/device has a close function, call it so + * that any necessary cleanup code can run. + */ + + rval = (fd->dev->close) ? fd->dev->close(fd) : 0; + 8037134: e0bfff17 ldw r2,-4(fp) + 8037138: 10800017 ldw r2,0(r2) + 803713c: 10800417 ldw r2,16(r2) + 8037140: 10000626 beq r2,zero,803715c + 8037144: e0bfff17 ldw r2,-4(fp) + 8037148: 10800017 ldw r2,0(r2) + 803714c: 10800417 ldw r2,16(r2) + 8037150: e13fff17 ldw r4,-4(fp) + 8037154: 103ee83a callr r2 + 8037158: 00000106 br 8037160 + 803715c: 0005883a mov r2,zero + 8037160: e0bffe15 stw r2,-8(fp) + + /* Free the file descriptor structure and return. */ + + alt_release_fd (fildes); + 8037164: e13ffd17 ldw r4,-12(fp) + 8037168: 8037e300 call 8037e30 + if (rval < 0) + 803716c: e0bffe17 ldw r2,-8(fp) + 8037170: 1000070e bge r2,zero,8037190 + { + ALT_ERRNO = -rval; + 8037174: 80370b40 call 80370b4 + 8037178: 1007883a mov r3,r2 + 803717c: e0bffe17 ldw r2,-8(fp) + 8037180: 0085c83a sub r2,zero,r2 + 8037184: 18800015 stw r2,0(r3) + return -1; + 8037188: 00bfffc4 movi r2,-1 + 803718c: 00000706 br 80371ac + } + return 0; + 8037190: 0005883a mov r2,zero + 8037194: 00000506 br 80371ac + } + else + { + ALT_ERRNO = EBADFD; + 8037198: 80370b40 call 80370b4 + 803719c: 1007883a mov r3,r2 + 80371a0: 00801444 movi r2,81 + 80371a4: 18800015 stw r2,0(r3) + return -1; + 80371a8: 00bfffc4 movi r2,-1 + } +} + 80371ac: e037883a mov sp,fp + 80371b0: dfc00117 ldw ra,4(sp) + 80371b4: df000017 ldw fp,0(sp) + 80371b8: dec00204 addi sp,sp,8 + 80371bc: f800283a ret + +080371c0 : + * + * Any dirty lines in the data cache are written back to memory. + */ + +void alt_dcache_flush (void* start, alt_u32 len) +{ + 80371c0: defffb04 addi sp,sp,-20 + 80371c4: df000415 stw fp,16(sp) + 80371c8: df000404 addi fp,sp,16 + 80371cc: e13ffd15 stw r4,-12(fp) + 80371d0: e17ffc15 stw r5,-16(fp) +#if NIOS2_DCACHE_SIZE > 0 + + char* i; + char* end = ((char*) start) + len; + 80371d4: e0fffd17 ldw r3,-12(fp) + 80371d8: e0bffc17 ldw r2,-16(fp) + 80371dc: 1885883a add r2,r3,r2 + 80371e0: e0bffe15 stw r2,-8(fp) + + for (i = start; i < end; i+= NIOS2_DCACHE_LINE_SIZE) + 80371e4: e0bffd17 ldw r2,-12(fp) + 80371e8: e0bfff15 stw r2,-4(fp) + 80371ec: 00000506 br 8037204 + { + ALT_FLUSH_DATA(i); + 80371f0: e0bfff17 ldw r2,-4(fp) + 80371f4: 1000001b flushda 0(r2) + for (i = start; i < end; i+= NIOS2_DCACHE_LINE_SIZE) + 80371f8: e0bfff17 ldw r2,-4(fp) + 80371fc: 10800804 addi r2,r2,32 + 8037200: e0bfff15 stw r2,-4(fp) + 8037204: e0ffff17 ldw r3,-4(fp) + 8037208: e0bffe17 ldw r2,-8(fp) + 803720c: 18bff836 bltu r3,r2,80371f0 + * For an unaligned flush request, we've got one more line left. + * Note that this is dependent on NIOS2_DCACHE_LINE_SIZE to be a + * multiple of 2 (which it always is). + */ + + if (((alt_u32) start) & (NIOS2_DCACHE_LINE_SIZE - 1)) + 8037210: e0bffd17 ldw r2,-12(fp) + 8037214: 108007cc andi r2,r2,31 + 8037218: 10000226 beq r2,zero,8037224 + { + ALT_FLUSH_DATA(i); + 803721c: e0bfff17 ldw r2,-4(fp) + 8037220: 1000001b flushda 0(r2) + } + +#endif /* NIOS2_DCACHE_SIZE > 0 */ +} + 8037224: 0001883a nop + 8037228: e037883a mov sp,fp + 803722c: df000017 ldw fp,0(sp) + 8037230: dec00104 addi sp,sp,4 + 8037234: f800283a ret + +08037238 : + * by the alt_dev_null device. It simple discards all data passed to it, and + * indicates that the data has been successfully transmitted. + */ + +static int alt_dev_null_write (alt_fd* fd, const char* ptr, int len) +{ + 8037238: defffc04 addi sp,sp,-16 + 803723c: df000315 stw fp,12(sp) + 8037240: df000304 addi fp,sp,12 + 8037244: e13fff15 stw r4,-4(fp) + 8037248: e17ffe15 stw r5,-8(fp) + 803724c: e1bffd15 stw r6,-12(fp) + return len; + 8037250: e0bffd17 ldw r2,-12(fp) +} + 8037254: e037883a mov sp,fp + 8037258: df000017 ldw fp,0(sp) + 803725c: dec00104 addi sp,sp,4 + 8037260: f800283a ret + +08037264 : +{ + 8037264: defffe04 addi sp,sp,-8 + 8037268: dfc00115 stw ra,4(sp) + 803726c: df000015 stw fp,0(sp) + 8037270: d839883a mov fp,sp + return ((alt_errno) ? alt_errno() : &errno); + 8037274: d0a02717 ldw r2,-32612(gp) + 8037278: 10000326 beq r2,zero,8037288 + 803727c: d0a02717 ldw r2,-32612(gp) + 8037280: 103ee83a callr r2 + 8037284: 00000106 br 803728c + 8037288: d0a04204 addi r2,gp,-32504 +} + 803728c: e037883a mov sp,fp + 8037290: dfc00117 ldw ra,4(sp) + 8037294: df000017 ldw fp,0(sp) + 8037298: dec00204 addi sp,sp,8 + 803729c: f800283a ret + +080372a0 : +/* + * + */ + +int alt_dev_llist_insert (alt_dev_llist* dev, alt_llist* list) +{ + 80372a0: defffa04 addi sp,sp,-24 + 80372a4: dfc00515 stw ra,20(sp) + 80372a8: df000415 stw fp,16(sp) + 80372ac: df000404 addi fp,sp,16 + 80372b0: e13ffd15 stw r4,-12(fp) + 80372b4: e17ffc15 stw r5,-16(fp) + /* + * check that the device exists, and that it has a valid name. + */ + + if (!dev || !dev->name) + 80372b8: e0bffd17 ldw r2,-12(fp) + 80372bc: 10000326 beq r2,zero,80372cc + 80372c0: e0bffd17 ldw r2,-12(fp) + 80372c4: 10800217 ldw r2,8(r2) + 80372c8: 1000061e bne r2,zero,80372e4 + { + ALT_ERRNO = EINVAL; + 80372cc: 80372640 call 8037264 + 80372d0: 1007883a mov r3,r2 + 80372d4: 00800584 movi r2,22 + 80372d8: 18800015 stw r2,0(r3) + return -EINVAL; + 80372dc: 00bffa84 movi r2,-22 + 80372e0: 00001306 br 8037330 + + /* + * register the device. + */ + + alt_llist_insert(list, &dev->llist); + 80372e4: e0bffd17 ldw r2,-12(fp) + 80372e8: e0fffc17 ldw r3,-16(fp) + 80372ec: e0ffff15 stw r3,-4(fp) + 80372f0: e0bffe15 stw r2,-8(fp) + entry->previous = list; + 80372f4: e0bffe17 ldw r2,-8(fp) + 80372f8: e0ffff17 ldw r3,-4(fp) + 80372fc: 10c00115 stw r3,4(r2) + entry->next = list->next; + 8037300: e0bfff17 ldw r2,-4(fp) + 8037304: 10c00017 ldw r3,0(r2) + 8037308: e0bffe17 ldw r2,-8(fp) + 803730c: 10c00015 stw r3,0(r2) + list->next->previous = entry; + 8037310: e0bfff17 ldw r2,-4(fp) + 8037314: 10800017 ldw r2,0(r2) + 8037318: e0fffe17 ldw r3,-8(fp) + 803731c: 10c00115 stw r3,4(r2) + list->next = entry; + 8037320: e0bfff17 ldw r2,-4(fp) + 8037324: e0fffe17 ldw r3,-8(fp) + 8037328: 10c00015 stw r3,0(r2) + + return 0; + 803732c: 0005883a mov r2,zero +} + 8037330: e037883a mov sp,fp + 8037334: dfc00117 ldw ra,4(sp) + 8037338: df000017 ldw fp,0(sp) + 803733c: dec00204 addi sp,sp,8 + 8037340: f800283a ret + +08037344 <_do_ctors>: +/* + * Run the C++ static constructors. + */ + +void _do_ctors(void) +{ + 8037344: defffd04 addi sp,sp,-12 + 8037348: dfc00215 stw ra,8(sp) + 803734c: df000115 stw fp,4(sp) + 8037350: df000104 addi fp,sp,4 + constructor* ctor; + + for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--) + 8037354: 00820134 movhi r2,2052 + 8037358: 109a6904 addi r2,r2,27044 + 803735c: e0bfff15 stw r2,-4(fp) + 8037360: 00000606 br 803737c <_do_ctors+0x38> + (*ctor) (); + 8037364: e0bfff17 ldw r2,-4(fp) + 8037368: 10800017 ldw r2,0(r2) + 803736c: 103ee83a callr r2 + for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--) + 8037370: e0bfff17 ldw r2,-4(fp) + 8037374: 10bfff04 addi r2,r2,-4 + 8037378: e0bfff15 stw r2,-4(fp) + 803737c: e0ffff17 ldw r3,-4(fp) + 8037380: 00820134 movhi r2,2052 + 8037384: 109a6a04 addi r2,r2,27048 + 8037388: 18bff62e bgeu r3,r2,8037364 <_do_ctors+0x20> +} + 803738c: 0001883a nop + 8037390: e037883a mov sp,fp + 8037394: dfc00117 ldw ra,4(sp) + 8037398: df000017 ldw fp,0(sp) + 803739c: dec00204 addi sp,sp,8 + 80373a0: f800283a ret + +080373a4 <_do_dtors>: +/* + * Run the C++ static destructors. + */ + +void _do_dtors(void) +{ + 80373a4: defffd04 addi sp,sp,-12 + 80373a8: dfc00215 stw ra,8(sp) + 80373ac: df000115 stw fp,4(sp) + 80373b0: df000104 addi fp,sp,4 + destructor* dtor; + + for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--) + 80373b4: 00820134 movhi r2,2052 + 80373b8: 109a6904 addi r2,r2,27044 + 80373bc: e0bfff15 stw r2,-4(fp) + 80373c0: 00000606 br 80373dc <_do_dtors+0x38> + (*dtor) (); + 80373c4: e0bfff17 ldw r2,-4(fp) + 80373c8: 10800017 ldw r2,0(r2) + 80373cc: 103ee83a callr r2 + for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--) + 80373d0: e0bfff17 ldw r2,-4(fp) + 80373d4: 10bfff04 addi r2,r2,-4 + 80373d8: e0bfff15 stw r2,-4(fp) + 80373dc: e0ffff17 ldw r3,-4(fp) + 80373e0: 00820134 movhi r2,2052 + 80373e4: 109a6a04 addi r2,r2,27048 + 80373e8: 18bff62e bgeu r3,r2,80373c4 <_do_dtors+0x20> +} + 80373ec: 0001883a nop + 80373f0: e037883a mov sp,fp + 80373f4: dfc00117 ldw ra,4(sp) + 80373f8: df000017 ldw fp,0(sp) + 80373fc: dec00204 addi sp,sp,8 + 8037400: f800283a ret + +08037404 : + * "name" must be an exact match for the devices registered name for a match to + * be found. + */ + +alt_dev* alt_find_dev(const char* name, alt_llist* llist) +{ + 8037404: defffa04 addi sp,sp,-24 + 8037408: dfc00515 stw ra,20(sp) + 803740c: df000415 stw fp,16(sp) + 8037410: df000404 addi fp,sp,16 + 8037414: e13ffd15 stw r4,-12(fp) + 8037418: e17ffc15 stw r5,-16(fp) + alt_dev* next = (alt_dev*) llist->next; + 803741c: e0bffc17 ldw r2,-16(fp) + 8037420: 10800017 ldw r2,0(r2) + 8037424: e0bfff15 stw r2,-4(fp) + alt_32 len; + + len = strlen(name) + 1; + 8037428: e13ffd17 ldw r4,-12(fp) + 803742c: 8002dac0 call 8002dac + 8037430: 10800044 addi r2,r2,1 + 8037434: e0bffe15 stw r2,-8(fp) + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) llist) + 8037438: 00000d06 br 8037470 + /* + * memcmp() is used here rather than strcmp() in order to reduce the size + * of the executable. + */ + + if (!memcmp (next->name, name, len)) + 803743c: e0bfff17 ldw r2,-4(fp) + 8037440: 10800217 ldw r2,8(r2) + 8037444: e0fffe17 ldw r3,-8(fp) + 8037448: 180d883a mov r6,r3 + 803744c: e17ffd17 ldw r5,-12(fp) + 8037450: 1009883a mov r4,r2 + 8037454: 8042cb80 call 8042cb8 + 8037458: 1000021e bne r2,zero,8037464 + { + /* match found */ + + return next; + 803745c: e0bfff17 ldw r2,-4(fp) + 8037460: 00000706 br 8037480 + } + next = (alt_dev*) next->llist.next; + 8037464: e0bfff17 ldw r2,-4(fp) + 8037468: 10800017 ldw r2,0(r2) + 803746c: e0bfff15 stw r2,-4(fp) + while (next != (alt_dev*) llist) + 8037470: e0ffff17 ldw r3,-4(fp) + 8037474: e0bffc17 ldw r2,-16(fp) + 8037478: 18bff01e bne r3,r2,803743c + } + + /* No match found */ + + return NULL; + 803747c: 0005883a mov r2,zero +} + 8037480: e037883a mov sp,fp + 8037484: dfc00117 ldw ra,4(sp) + 8037488: df000017 ldw fp,0(sp) + 803748c: dec00204 addi sp,sp,8 + 8037490: f800283a ret + +08037494 : + * @param irq IRQ number + * @return 0 if successful, else error (-1) + */ +int alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, + void *isr_context, void *flags) +{ + 8037494: defff904 addi sp,sp,-28 + 8037498: dfc00615 stw ra,24(sp) + 803749c: df000515 stw fp,20(sp) + 80374a0: df000504 addi fp,sp,20 + 80374a4: e13fff15 stw r4,-4(fp) + 80374a8: e17ffe15 stw r5,-8(fp) + 80374ac: e1bffd15 stw r6,-12(fp) + 80374b0: e1fffc15 stw r7,-16(fp) + return alt_iic_isr_register(ic_id, irq, isr, isr_context, flags); + 80374b4: e0800217 ldw r2,8(fp) + 80374b8: d8800015 stw r2,0(sp) + 80374bc: e1fffc17 ldw r7,-16(fp) + 80374c0: e1bffd17 ldw r6,-12(fp) + 80374c4: e17ffe17 ldw r5,-8(fp) + 80374c8: e13fff17 ldw r4,-4(fp) + 80374cc: 80376440 call 8037644 +} + 80374d0: e037883a mov sp,fp + 80374d4: dfc00117 ldw ra,4(sp) + 80374d8: df000017 ldw fp,0(sp) + 80374dc: dec00204 addi sp,sp,8 + 80374e0: f800283a ret + +080374e4 : + * @param ic_id Ignored. + * @param irq IRQ number + * @return 0 if successful, else error (-1) + */ +int alt_ic_irq_enable (alt_u32 ic_id, alt_u32 irq) +{ + 80374e4: defff904 addi sp,sp,-28 + 80374e8: df000615 stw fp,24(sp) + 80374ec: df000604 addi fp,sp,24 + 80374f0: e13ffb15 stw r4,-20(fp) + 80374f4: e17ffa15 stw r5,-24(fp) + 80374f8: e0bffa17 ldw r2,-24(fp) + 80374fc: e0bfff15 stw r2,-4(fp) + NIOS2_READ_STATUS (context); + 8037500: 0005303a rdctl r2,status + 8037504: e0bffe15 stw r2,-8(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8037508: e0fffe17 ldw r3,-8(fp) + 803750c: 00bfff84 movi r2,-2 + 8037510: 1884703a and r2,r3,r2 + 8037514: 1001703a wrctl status,r2 + return context; + 8037518: e0bffe17 ldw r2,-8(fp) +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_enable (alt_u32 id) +{ + alt_irq_context status; + extern volatile alt_u32 alt_irq_active; + + status = alt_irq_disable_all (); + 803751c: e0bffd15 stw r2,-12(fp) + + alt_irq_active |= (1 << id); + 8037520: 00c00044 movi r3,1 + 8037524: e0bfff17 ldw r2,-4(fp) + 8037528: 1884983a sll r2,r3,r2 + 803752c: 1007883a mov r3,r2 + 8037530: d0a08c17 ldw r2,-32208(gp) + 8037534: 1884b03a or r2,r3,r2 + 8037538: d0a08c15 stw r2,-32208(gp) + NIOS2_WRITE_IENABLE (alt_irq_active); + 803753c: d0a08c17 ldw r2,-32208(gp) + 8037540: 100170fa wrctl ienable,r2 + 8037544: e0bffd17 ldw r2,-12(fp) + 8037548: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 803754c: e0bffc17 ldw r2,-16(fp) + 8037550: 1001703a wrctl status,r2 + + alt_irq_enable_all(status); + + return 0; + 8037554: 0005883a mov r2,zero + return alt_irq_enable(irq); + 8037558: 0001883a nop +} + 803755c: e037883a mov sp,fp + 8037560: df000017 ldw fp,0(sp) + 8037564: dec00104 addi sp,sp,4 + 8037568: f800283a ret + +0803756c : + * @param ic_id Ignored. + * @param irq IRQ number + * @return 0 if successful, else error (-1) + */ +int alt_ic_irq_disable(alt_u32 ic_id, alt_u32 irq) +{ + 803756c: defff904 addi sp,sp,-28 + 8037570: df000615 stw fp,24(sp) + 8037574: df000604 addi fp,sp,24 + 8037578: e13ffb15 stw r4,-20(fp) + 803757c: e17ffa15 stw r5,-24(fp) + 8037580: e0bffa17 ldw r2,-24(fp) + 8037584: e0bfff15 stw r2,-4(fp) + NIOS2_READ_STATUS (context); + 8037588: 0005303a rdctl r2,status + 803758c: e0bffe15 stw r2,-8(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8037590: e0fffe17 ldw r3,-8(fp) + 8037594: 00bfff84 movi r2,-2 + 8037598: 1884703a and r2,r3,r2 + 803759c: 1001703a wrctl status,r2 + return context; + 80375a0: e0bffe17 ldw r2,-8(fp) + status = alt_irq_disable_all (); + 80375a4: e0bffd15 stw r2,-12(fp) + alt_irq_active &= ~(1 << id); + 80375a8: 00c00044 movi r3,1 + 80375ac: e0bfff17 ldw r2,-4(fp) + 80375b0: 1884983a sll r2,r3,r2 + 80375b4: 0084303a nor r2,zero,r2 + 80375b8: 1007883a mov r3,r2 + 80375bc: d0a08c17 ldw r2,-32208(gp) + 80375c0: 1884703a and r2,r3,r2 + 80375c4: d0a08c15 stw r2,-32208(gp) + NIOS2_WRITE_IENABLE (alt_irq_active); + 80375c8: d0a08c17 ldw r2,-32208(gp) + 80375cc: 100170fa wrctl ienable,r2 + 80375d0: e0bffd17 ldw r2,-12(fp) + 80375d4: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context); + 80375d8: e0bffc17 ldw r2,-16(fp) + 80375dc: 1001703a wrctl status,r2 + return 0; + 80375e0: 0005883a mov r2,zero + return alt_irq_disable(irq); + 80375e4: 0001883a nop +} + 80375e8: e037883a mov sp,fp + 80375ec: df000017 ldw fp,0(sp) + 80375f0: dec00104 addi sp,sp,4 + 80375f4: f800283a ret + +080375f8 : + * @param irq IRQ number + * @return Zero if corresponding interrupt is disabled and + * non-zero otherwise. + */ +alt_u32 alt_ic_irq_enabled(alt_u32 ic_id, alt_u32 irq) +{ + 80375f8: defffc04 addi sp,sp,-16 + 80375fc: df000315 stw fp,12(sp) + 8037600: df000304 addi fp,sp,12 + 8037604: e13ffe15 stw r4,-8(fp) + 8037608: e17ffd15 stw r5,-12(fp) + alt_u32 irq_enabled; + + NIOS2_READ_IENABLE(irq_enabled); + 803760c: 000530fa rdctl r2,ienable + 8037610: e0bfff15 stw r2,-4(fp) + + return (irq_enabled & (1 << irq)) ? 1: 0; + 8037614: 00c00044 movi r3,1 + 8037618: e0bffd17 ldw r2,-12(fp) + 803761c: 1884983a sll r2,r3,r2 + 8037620: 1007883a mov r3,r2 + 8037624: e0bfff17 ldw r2,-4(fp) + 8037628: 1884703a and r2,r3,r2 + 803762c: 1004c03a cmpne r2,r2,zero + 8037630: 10803fcc andi r2,r2,255 +} + 8037634: e037883a mov sp,fp + 8037638: df000017 ldw fp,0(sp) + 803763c: dec00104 addi sp,sp,4 + 8037640: f800283a ret + +08037644 : + * @param flags + * @return 0 if successful, else error (-1) + */ +int alt_iic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, + void *isr_context, void *flags) +{ + 8037644: defff504 addi sp,sp,-44 + 8037648: dfc00a15 stw ra,40(sp) + 803764c: df000915 stw fp,36(sp) + 8037650: df000904 addi fp,sp,36 + 8037654: e13ffa15 stw r4,-24(fp) + 8037658: e17ff915 stw r5,-28(fp) + 803765c: e1bff815 stw r6,-32(fp) + 8037660: e1fff715 stw r7,-36(fp) + int rc = -EINVAL; + 8037664: 00bffa84 movi r2,-22 + 8037668: e0bfff15 stw r2,-4(fp) + int id = irq; /* IRQ interpreted as the interrupt ID. */ + 803766c: e0bff917 ldw r2,-28(fp) + 8037670: e0bffe15 stw r2,-8(fp) + alt_irq_context status; + + if (id < ALT_NIRQ) + 8037674: e0bffe17 ldw r2,-8(fp) + 8037678: 10800808 cmpgei r2,r2,32 + 803767c: 1000241e bne r2,zero,8037710 + NIOS2_READ_STATUS (context); + 8037680: 0005303a rdctl r2,status + 8037684: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8037688: e0fffc17 ldw r3,-16(fp) + 803768c: 00bfff84 movi r2,-2 + 8037690: 1884703a and r2,r3,r2 + 8037694: 1001703a wrctl status,r2 + return context; + 8037698: e0bffc17 ldw r2,-16(fp) + * interrupts are disabled while the handler tables are updated to ensure + * that an interrupt doesn't occur while the tables are in an inconsistant + * state. + */ + + status = alt_irq_disable_all(); + 803769c: e0bffd15 stw r2,-12(fp) + + alt_irq[id].handler = isr; + 80376a0: e0bffe17 ldw r2,-8(fp) + 80376a4: 100890fa slli r4,r2,3 + 80376a8: e0fff817 ldw r3,-32(fp) + 80376ac: 008201b4 movhi r2,2054 + 80376b0: 2085883a add r2,r4,r2 + 80376b4: 10f8dc15 stw r3,-7312(r2) + alt_irq[id].context = isr_context; + 80376b8: e0bffe17 ldw r2,-8(fp) + 80376bc: 100890fa slli r4,r2,3 + 80376c0: e0fff717 ldw r3,-36(fp) + 80376c4: 008201b4 movhi r2,2054 + 80376c8: 2085883a add r2,r4,r2 + 80376cc: 10f8dd15 stw r3,-7308(r2) + + rc = (isr) ? alt_ic_irq_enable(ic_id, id) : alt_ic_irq_disable(ic_id, id); + 80376d0: e0bff817 ldw r2,-32(fp) + 80376d4: 10000526 beq r2,zero,80376ec + 80376d8: e0bffe17 ldw r2,-8(fp) + 80376dc: 100b883a mov r5,r2 + 80376e0: e13ffa17 ldw r4,-24(fp) + 80376e4: 80374e40 call 80374e4 + 80376e8: 00000406 br 80376fc + 80376ec: e0bffe17 ldw r2,-8(fp) + 80376f0: 100b883a mov r5,r2 + 80376f4: e13ffa17 ldw r4,-24(fp) + 80376f8: 803756c0 call 803756c + 80376fc: e0bfff15 stw r2,-4(fp) + 8037700: e0bffd17 ldw r2,-12(fp) + 8037704: e0bffb15 stw r2,-20(fp) + NIOS2_WRITE_STATUS (context); + 8037708: e0bffb17 ldw r2,-20(fp) + 803770c: 1001703a wrctl status,r2 + + alt_irq_enable_all(status); + } + + return rc; + 8037710: e0bfff17 ldw r2,-4(fp) +} + 8037714: e037883a mov sp,fp + 8037718: dfc00117 ldw ra,4(sp) + 803771c: df000017 ldw fp,0(sp) + 8037720: dec00204 addi sp,sp,8 + 8037724: f800283a ret + +08037728 : + * If the device can not be succesfully opened, then the input file descriptor + * remains unchanged. + */ + +static void alt_open_fd(alt_fd* fd, const char* name, int flags, int mode) +{ + 8037728: defff904 addi sp,sp,-28 + 803772c: dfc00615 stw ra,24(sp) + 8037730: df000515 stw fp,20(sp) + 8037734: df000504 addi fp,sp,20 + 8037738: e13ffe15 stw r4,-8(fp) + 803773c: e17ffd15 stw r5,-12(fp) + 8037740: e1bffc15 stw r6,-16(fp) + 8037744: e1fffb15 stw r7,-20(fp) + int old; + + old = open (name, flags, mode); + 8037748: e1bffb17 ldw r6,-20(fp) + 803774c: e17ffc17 ldw r5,-16(fp) + 8037750: e13ffd17 ldw r4,-12(fp) + 8037754: 80379480 call 8037948 + 8037758: e0bfff15 stw r2,-4(fp) + + if (old >= 0) + 803775c: e0bfff17 ldw r2,-4(fp) + 8037760: 10001716 blt r2,zero,80377c0 + { + fd->dev = alt_fd_list[old].dev; + 8037764: e0bfff17 ldw r2,-4(fp) + 8037768: 10c00324 muli r3,r2,12 + 803776c: 00820174 movhi r2,2053 + 8037770: 1885883a add r2,r3,r2 + 8037774: 10f21a17 ldw r3,-14232(r2) + 8037778: e0bffe17 ldw r2,-8(fp) + 803777c: 10c00015 stw r3,0(r2) + fd->priv = alt_fd_list[old].priv; + 8037780: e0bfff17 ldw r2,-4(fp) + 8037784: 10c00324 muli r3,r2,12 + 8037788: 00820174 movhi r2,2053 + 803778c: 1885883a add r2,r3,r2 + 8037790: 10f21b17 ldw r3,-14228(r2) + 8037794: e0bffe17 ldw r2,-8(fp) + 8037798: 10c00115 stw r3,4(r2) + fd->fd_flags = alt_fd_list[old].fd_flags; + 803779c: e0bfff17 ldw r2,-4(fp) + 80377a0: 10c00324 muli r3,r2,12 + 80377a4: 00820174 movhi r2,2053 + 80377a8: 1885883a add r2,r3,r2 + 80377ac: 10f21c17 ldw r3,-14224(r2) + 80377b0: e0bffe17 ldw r2,-8(fp) + 80377b4: 10c00215 stw r3,8(r2) + + alt_release_fd (old); + 80377b8: e13fff17 ldw r4,-4(fp) + 80377bc: 8037e300 call 8037e30 + } +} + 80377c0: 0001883a nop + 80377c4: e037883a mov sp,fp + 80377c8: dfc00117 ldw ra,4(sp) + 80377cc: df000017 ldw fp,0(sp) + 80377d0: dec00204 addi sp,sp,8 + 80377d4: f800283a ret + +080377d8 : + */ + +void alt_io_redirect(const char* stdout_dev, + const char* stdin_dev, + const char* stderr_dev) +{ + 80377d8: defffb04 addi sp,sp,-20 + 80377dc: dfc00415 stw ra,16(sp) + 80377e0: df000315 stw fp,12(sp) + 80377e4: df000304 addi fp,sp,12 + 80377e8: e13fff15 stw r4,-4(fp) + 80377ec: e17ffe15 stw r5,-8(fp) + 80377f0: e1bffd15 stw r6,-12(fp) + /* Redirect the channels */ + + alt_open_fd (&alt_fd_list[STDOUT_FILENO], stdout_dev, O_WRONLY, 0777); + 80377f4: 01c07fc4 movi r7,511 + 80377f8: 01800044 movi r6,1 + 80377fc: e17fff17 ldw r5,-4(fp) + 8037800: 01020174 movhi r4,2053 + 8037804: 21321d04 addi r4,r4,-14220 + 8037808: 80377280 call 8037728 + alt_open_fd (&alt_fd_list[STDIN_FILENO], stdin_dev, O_RDONLY, 0777); + 803780c: 01c07fc4 movi r7,511 + 8037810: 000d883a mov r6,zero + 8037814: e17ffe17 ldw r5,-8(fp) + 8037818: 01020174 movhi r4,2053 + 803781c: 21321a04 addi r4,r4,-14232 + 8037820: 80377280 call 8037728 + alt_open_fd (&alt_fd_list[STDERR_FILENO], stderr_dev, O_WRONLY, 0777); + 8037824: 01c07fc4 movi r7,511 + 8037828: 01800044 movi r6,1 + 803782c: e17ffd17 ldw r5,-12(fp) + 8037830: 01020174 movhi r4,2053 + 8037834: 21322004 addi r4,r4,-14208 + 8037838: 80377280 call 8037728 +} + 803783c: 0001883a nop + 8037840: e037883a mov sp,fp + 8037844: dfc00117 ldw ra,4(sp) + 8037848: df000017 ldw fp,0(sp) + 803784c: dec00204 addi sp,sp,8 + 8037850: f800283a ret + +08037854 : +{ + 8037854: defffe04 addi sp,sp,-8 + 8037858: dfc00115 stw ra,4(sp) + 803785c: df000015 stw fp,0(sp) + 8037860: d839883a mov fp,sp + return ((alt_errno) ? alt_errno() : &errno); + 8037864: d0a02717 ldw r2,-32612(gp) + 8037868: 10000326 beq r2,zero,8037878 + 803786c: d0a02717 ldw r2,-32612(gp) + 8037870: 103ee83a callr r2 + 8037874: 00000106 br 803787c + 8037878: d0a04204 addi r2,gp,-32504 +} + 803787c: e037883a mov sp,fp + 8037880: dfc00117 ldw ra,4(sp) + 8037884: df000017 ldw fp,0(sp) + 8037888: dec00204 addi sp,sp,8 + 803788c: f800283a ret + +08037890 : + * performed for devices. Filesystems are required to handle the ioctl() call + * themselves, and report the error from the filesystems open() function. + */ + +static int alt_file_locked (alt_fd* fd) +{ + 8037890: defffd04 addi sp,sp,-12 + 8037894: df000215 stw fp,8(sp) + 8037898: df000204 addi fp,sp,8 + 803789c: e13ffe15 stw r4,-8(fp) + + /* + * Mark the file descriptor as belonging to a device. + */ + + fd->fd_flags |= ALT_FD_DEV; + 80378a0: e0bffe17 ldw r2,-8(fp) + 80378a4: 10800217 ldw r2,8(r2) + 80378a8: 10d00034 orhi r3,r2,16384 + 80378ac: e0bffe17 ldw r2,-8(fp) + 80378b0: 10c00215 stw r3,8(r2) + /* + * Loop through all current file descriptors searching for one that's locked + * for exclusive access. If a match is found, generate an error. + */ + + for (i = 0; i <= alt_max_fd; i++) + 80378b4: e03fff15 stw zero,-4(fp) + 80378b8: 00001a06 br 8037924 + { + if ((alt_fd_list[i].dev == fd->dev) && + 80378bc: e0bfff17 ldw r2,-4(fp) + 80378c0: 10c00324 muli r3,r2,12 + 80378c4: 00820174 movhi r2,2053 + 80378c8: 1885883a add r2,r3,r2 + 80378cc: 10f21a17 ldw r3,-14232(r2) + 80378d0: e0bffe17 ldw r2,-8(fp) + 80378d4: 10800017 ldw r2,0(r2) + 80378d8: 18800f1e bne r3,r2,8037918 + (alt_fd_list[i].fd_flags & ALT_FD_EXCL) && + 80378dc: e0bfff17 ldw r2,-4(fp) + 80378e0: 10c00324 muli r3,r2,12 + 80378e4: 00820174 movhi r2,2053 + 80378e8: 1885883a add r2,r3,r2 + 80378ec: 10b21c17 ldw r2,-14224(r2) + if ((alt_fd_list[i].dev == fd->dev) && + 80378f0: 1000090e bge r2,zero,8037918 + (&alt_fd_list[i] != fd)) + 80378f4: e0bfff17 ldw r2,-4(fp) + 80378f8: 10c00324 muli r3,r2,12 + 80378fc: 00820174 movhi r2,2053 + 8037900: 10b21a04 addi r2,r2,-14232 + 8037904: 1885883a add r2,r3,r2 + (alt_fd_list[i].fd_flags & ALT_FD_EXCL) && + 8037908: e0fffe17 ldw r3,-8(fp) + 803790c: 18800226 beq r3,r2,8037918 + { + return -EACCES; + 8037910: 00bffcc4 movi r2,-13 + 8037914: 00000806 br 8037938 + for (i = 0; i <= alt_max_fd; i++) + 8037918: e0bfff17 ldw r2,-4(fp) + 803791c: 10800044 addi r2,r2,1 + 8037920: e0bfff15 stw r2,-4(fp) + 8037924: d0a02617 ldw r2,-32616(gp) + 8037928: 1007883a mov r3,r2 + 803792c: e0bfff17 ldw r2,-4(fp) + 8037930: 18bfe22e bgeu r3,r2,80378bc + } + } + + /* The device is not locked */ + + return 0; + 8037934: 0005883a mov r2,zero +} + 8037938: e037883a mov sp,fp + 803793c: df000017 ldw fp,0(sp) + 8037940: dec00104 addi sp,sp,4 + 8037944: f800283a ret + +08037948 : + * + * ALT_OPEN is mapped onto the open() system call in alt_syscall.h + */ + +int ALT_OPEN (const char* file, int flags, int mode) +{ + 8037948: defff604 addi sp,sp,-40 + 803794c: dfc00915 stw ra,36(sp) + 8037950: df000815 stw fp,32(sp) + 8037954: df000804 addi fp,sp,32 + 8037958: e13ffa15 stw r4,-24(fp) + 803795c: e17ff915 stw r5,-28(fp) + 8037960: e1bff815 stw r6,-32(fp) + alt_dev* dev; + alt_fd* fd; + int index = -1; + 8037964: 00bfffc4 movi r2,-1 + 8037968: e0bffe15 stw r2,-8(fp) + int status = -ENODEV; + 803796c: 00bffb44 movi r2,-19 + 8037970: e0bffd15 stw r2,-12(fp) + int isafs = 0; + 8037974: e03ffc15 stw zero,-16(fp) + /* + * Check the device list, to see if a device with a matching name is + * registered. + */ + + if (!(dev = alt_find_dev (file, &alt_dev_list))) + 8037978: d1602404 addi r5,gp,-32624 + 803797c: e13ffa17 ldw r4,-24(fp) + 8037980: 80374040 call 8037404 + 8037984: e0bfff15 stw r2,-4(fp) + 8037988: e0bfff17 ldw r2,-4(fp) + 803798c: 1000051e bne r2,zero,80379a4 + { + /* No matching device, so try the filesystem list */ + + dev = alt_find_file (file); + 8037990: e13ffa17 ldw r4,-24(fp) + 8037994: 80428180 call 8042818 + 8037998: e0bfff15 stw r2,-4(fp) + isafs = 1; + 803799c: 00800044 movi r2,1 + 80379a0: e0bffc15 stw r2,-16(fp) + + /* + * If a matching device or filesystem is found, allocate a file descriptor. + */ + + if (dev) + 80379a4: e0bfff17 ldw r2,-4(fp) + 80379a8: 10002926 beq r2,zero,8037a50 + { + if ((index = alt_get_fd (dev)) < 0) + 80379ac: e13fff17 ldw r4,-4(fp) + 80379b0: 80429200 call 8042920 + 80379b4: e0bffe15 stw r2,-8(fp) + 80379b8: e0bffe17 ldw r2,-8(fp) + 80379bc: 1000030e bge r2,zero,80379cc + { + status = index; + 80379c0: e0bffe17 ldw r2,-8(fp) + 80379c4: e0bffd15 stw r2,-12(fp) + 80379c8: 00002306 br 8037a58 + } + else + { + fd = &alt_fd_list[index]; + 80379cc: e0bffe17 ldw r2,-8(fp) + 80379d0: 10c00324 muli r3,r2,12 + 80379d4: 00820174 movhi r2,2053 + 80379d8: 10b21a04 addi r2,r2,-14232 + 80379dc: 1885883a add r2,r3,r2 + 80379e0: e0bffb15 stw r2,-20(fp) + fd->fd_flags = (flags & ~ALT_FD_FLAGS_MASK); + 80379e4: e0fff917 ldw r3,-28(fp) + 80379e8: 00900034 movhi r2,16384 + 80379ec: 10bfffc4 addi r2,r2,-1 + 80379f0: 1886703a and r3,r3,r2 + 80379f4: e0bffb17 ldw r2,-20(fp) + 80379f8: 10c00215 stw r3,8(r2) + + /* If this is a device, ensure it isn't already locked */ + + if (isafs || ((status = alt_file_locked (fd)) >= 0)) + 80379fc: e0bffc17 ldw r2,-16(fp) + 8037a00: 1000051e bne r2,zero,8037a18 + 8037a04: e13ffb17 ldw r4,-20(fp) + 8037a08: 80378900 call 8037890 + 8037a0c: e0bffd15 stw r2,-12(fp) + 8037a10: e0bffd17 ldw r2,-12(fp) + 8037a14: 10001016 blt r2,zero,8037a58 + /* + * If the device or filesystem provides an open() callback function, + * call it now to perform any device/filesystem specific operations. + */ + + status = (dev->open) ? dev->open(fd, file, flags, mode): 0; + 8037a18: e0bfff17 ldw r2,-4(fp) + 8037a1c: 10800317 ldw r2,12(r2) + 8037a20: 10000826 beq r2,zero,8037a44 + 8037a24: e0bfff17 ldw r2,-4(fp) + 8037a28: 10800317 ldw r2,12(r2) + 8037a2c: e1fff817 ldw r7,-32(fp) + 8037a30: e1bff917 ldw r6,-28(fp) + 8037a34: e17ffa17 ldw r5,-24(fp) + 8037a38: e13ffb17 ldw r4,-20(fp) + 8037a3c: 103ee83a callr r2 + 8037a40: 00000106 br 8037a48 + 8037a44: 0005883a mov r2,zero + 8037a48: e0bffd15 stw r2,-12(fp) + 8037a4c: 00000206 br 8037a58 + } + } + } + else + { + status = -ENODEV; + 8037a50: 00bffb44 movi r2,-19 + 8037a54: e0bffd15 stw r2,-12(fp) + } + + /* Allocation failed, so clean up and return an error */ + + if (status < 0) + 8037a58: e0bffd17 ldw r2,-12(fp) + 8037a5c: 1000090e bge r2,zero,8037a84 + { + alt_release_fd (index); + 8037a60: e13ffe17 ldw r4,-8(fp) + 8037a64: 8037e300 call 8037e30 + ALT_ERRNO = -status; + 8037a68: 80378540 call 8037854 + 8037a6c: 1007883a mov r3,r2 + 8037a70: e0bffd17 ldw r2,-12(fp) + 8037a74: 0085c83a sub r2,zero,r2 + 8037a78: 18800015 stw r2,0(r3) + return -1; + 8037a7c: 00bfffc4 movi r2,-1 + 8037a80: 00000106 br 8037a88 + } + + /* return the reference upon success */ + + return index; + 8037a84: e0bffe17 ldw r2,-8(fp) +} + 8037a88: e037883a mov sp,fp + 8037a8c: dfc00117 ldw ra,4(sp) + 8037a90: df000017 ldw fp,0(sp) + 8037a94: dec00204 addi sp,sp,8 + 8037a98: f800283a ret + +08037a9c : +/* + * ALT printf function + */ +void +alt_printf(const char* fmt, ... ) +{ + 8037a9c: defff204 addi sp,sp,-56 + 8037aa0: dfc00a15 stw ra,40(sp) + 8037aa4: df000915 stw fp,36(sp) + 8037aa8: df000904 addi fp,sp,36 + 8037aac: e13ff715 stw r4,-36(fp) + 8037ab0: e1400215 stw r5,8(fp) + 8037ab4: e1800315 stw r6,12(fp) + 8037ab8: e1c00415 stw r7,16(fp) + va_list args; + va_start(args, fmt); + 8037abc: e0800204 addi r2,fp,8 + 8037ac0: e0bff815 stw r2,-32(fp) + const char *w; + char c; + + /* Process format string. */ + w = fmt; + 8037ac4: e0bff717 ldw r2,-36(fp) + 8037ac8: e0bfff15 stw r2,-4(fp) + while ((c = *w++) != 0) + 8037acc: 00006f06 br 8037c8c + { + /* If not a format escape character, just print */ + /* character. Otherwise, process format string. */ + if (c != '%') + 8037ad0: e0bffec7 ldb r2,-5(fp) + 8037ad4: 10800960 cmpeqi r2,r2,37 + 8037ad8: 1000041e bne r2,zero,8037aec + { + alt_putchar(c); + 8037adc: e0bffec7 ldb r2,-5(fp) + 8037ae0: 1009883a mov r4,r2 + 8037ae4: 8037cc80 call 8037cc8 + 8037ae8: 00006806 br 8037c8c + } + else + { + /* Get format character. If none */ + /* available, processing is complete. */ + if ((c = *w++) != 0) + 8037aec: e0bfff17 ldw r2,-4(fp) + 8037af0: 10c00044 addi r3,r2,1 + 8037af4: e0ffff15 stw r3,-4(fp) + 8037af8: 10800003 ldbu r2,0(r2) + 8037afc: e0bffec5 stb r2,-5(fp) + 8037b00: e0bffec7 ldb r2,-5(fp) + 8037b04: 10006926 beq r2,zero,8037cac + { + if (c == '%') + 8037b08: e0bffec7 ldb r2,-5(fp) + 8037b0c: 10800958 cmpnei r2,r2,37 + 8037b10: 1000041e bne r2,zero,8037b24 + { + /* Process "%" escape sequence. */ + alt_putchar(c); + 8037b14: e0bffec7 ldb r2,-5(fp) + 8037b18: 1009883a mov r4,r2 + 8037b1c: 8037cc80 call 8037cc8 + 8037b20: 00005a06 br 8037c8c + } + else if (c == 'c') + 8037b24: e0bffec7 ldb r2,-5(fp) + 8037b28: 108018d8 cmpnei r2,r2,99 + 8037b2c: 1000081e bne r2,zero,8037b50 + { + int v = va_arg(args, int); + 8037b30: e0bff817 ldw r2,-32(fp) + 8037b34: 10c00104 addi r3,r2,4 + 8037b38: e0fff815 stw r3,-32(fp) + 8037b3c: 10800017 ldw r2,0(r2) + 8037b40: e0bffb15 stw r2,-20(fp) + alt_putchar(v); + 8037b44: e13ffb17 ldw r4,-20(fp) + 8037b48: 8037cc80 call 8037cc8 + 8037b4c: 00004f06 br 8037c8c + } + else if (c == 'x') + 8037b50: e0bffec7 ldb r2,-5(fp) + 8037b54: 10801e18 cmpnei r2,r2,120 + 8037b58: 1000341e bne r2,zero,8037c2c + { + /* Process hexadecimal number format. */ + unsigned long v = va_arg(args, unsigned long); + 8037b5c: e0bff817 ldw r2,-32(fp) + 8037b60: 10c00104 addi r3,r2,4 + 8037b64: e0fff815 stw r3,-32(fp) + 8037b68: 10800017 ldw r2,0(r2) + 8037b6c: e0bffa15 stw r2,-24(fp) + unsigned long digit; + int digit_shift; + + /* If the number value is zero, just print and continue. */ + if (v == 0) + 8037b70: e0bffa17 ldw r2,-24(fp) + 8037b74: 1000031e bne r2,zero,8037b84 + { + alt_putchar('0'); + 8037b78: 01000c04 movi r4,48 + 8037b7c: 8037cc80 call 8037cc8 + continue; + 8037b80: 00004206 br 8037c8c + } + + /* Find first non-zero digit. */ + digit_shift = 28; + 8037b84: 00800704 movi r2,28 + 8037b88: e0bffd15 stw r2,-12(fp) + while (!(v & (0xF << digit_shift))) + 8037b8c: 00000306 br 8037b9c + digit_shift -= 4; + 8037b90: e0bffd17 ldw r2,-12(fp) + 8037b94: 10bfff04 addi r2,r2,-4 + 8037b98: e0bffd15 stw r2,-12(fp) + while (!(v & (0xF << digit_shift))) + 8037b9c: 00c003c4 movi r3,15 + 8037ba0: e0bffd17 ldw r2,-12(fp) + 8037ba4: 1884983a sll r2,r3,r2 + 8037ba8: 1007883a mov r3,r2 + 8037bac: e0bffa17 ldw r2,-24(fp) + 8037bb0: 1884703a and r2,r3,r2 + 8037bb4: 103ff626 beq r2,zero,8037b90 + + /* Print digits. */ + for (; digit_shift >= 0; digit_shift -= 4) + 8037bb8: 00001906 br 8037c20 + { + digit = (v & (0xF << digit_shift)) >> digit_shift; + 8037bbc: 00c003c4 movi r3,15 + 8037bc0: e0bffd17 ldw r2,-12(fp) + 8037bc4: 1884983a sll r2,r3,r2 + 8037bc8: 1007883a mov r3,r2 + 8037bcc: e0bffa17 ldw r2,-24(fp) + 8037bd0: 1886703a and r3,r3,r2 + 8037bd4: e0bffd17 ldw r2,-12(fp) + 8037bd8: 1884d83a srl r2,r3,r2 + 8037bdc: e0bff915 stw r2,-28(fp) + if (digit <= 9) + 8037be0: e0bff917 ldw r2,-28(fp) + 8037be4: 108002a8 cmpgeui r2,r2,10 + 8037be8: 1000041e bne r2,zero,8037bfc + c = '0' + digit; + 8037bec: e0bff917 ldw r2,-28(fp) + 8037bf0: 10800c04 addi r2,r2,48 + 8037bf4: e0bffec5 stb r2,-5(fp) + 8037bf8: 00000306 br 8037c08 + else + c = 'a' + digit - 10; + 8037bfc: e0bff917 ldw r2,-28(fp) + 8037c00: 108015c4 addi r2,r2,87 + 8037c04: e0bffec5 stb r2,-5(fp) + alt_putchar(c); + 8037c08: e0bffec7 ldb r2,-5(fp) + 8037c0c: 1009883a mov r4,r2 + 8037c10: 8037cc80 call 8037cc8 + for (; digit_shift >= 0; digit_shift -= 4) + 8037c14: e0bffd17 ldw r2,-12(fp) + 8037c18: 10bfff04 addi r2,r2,-4 + 8037c1c: e0bffd15 stw r2,-12(fp) + 8037c20: e0bffd17 ldw r2,-12(fp) + 8037c24: 103fe50e bge r2,zero,8037bbc + 8037c28: 00001806 br 8037c8c + } + } + else if (c == 's') + 8037c2c: e0bffec7 ldb r2,-5(fp) + 8037c30: 10801cd8 cmpnei r2,r2,115 + 8037c34: 1000151e bne r2,zero,8037c8c + { + /* Process string format. */ + char *s = va_arg(args, char *); + 8037c38: e0bff817 ldw r2,-32(fp) + 8037c3c: 10c00104 addi r3,r2,4 + 8037c40: e0fff815 stw r3,-32(fp) + 8037c44: 10800017 ldw r2,0(r2) + 8037c48: e0bffc15 stw r2,-16(fp) + + while(*s) + 8037c4c: 00000906 br 8037c74 + alt_putchar(*s++); + 8037c50: e0bffc17 ldw r2,-16(fp) + 8037c54: 10c00044 addi r3,r2,1 + 8037c58: e0fffc15 stw r3,-16(fp) + 8037c5c: 10800003 ldbu r2,0(r2) + 8037c60: 10803fcc andi r2,r2,255 + 8037c64: 1080201c xori r2,r2,128 + 8037c68: 10bfe004 addi r2,r2,-128 + 8037c6c: 1009883a mov r4,r2 + 8037c70: 8037cc80 call 8037cc8 + while(*s) + 8037c74: e0bffc17 ldw r2,-16(fp) + 8037c78: 10800003 ldbu r2,0(r2) + 8037c7c: 10803fcc andi r2,r2,255 + 8037c80: 1080201c xori r2,r2,128 + 8037c84: 10bfe004 addi r2,r2,-128 + 8037c88: 103ff11e bne r2,zero,8037c50 + while ((c = *w++) != 0) + 8037c8c: e0bfff17 ldw r2,-4(fp) + 8037c90: 10c00044 addi r3,r2,1 + 8037c94: e0ffff15 stw r3,-4(fp) + 8037c98: 10800003 ldbu r2,0(r2) + 8037c9c: e0bffec5 stb r2,-5(fp) + 8037ca0: e0bffec7 ldb r2,-5(fp) + 8037ca4: 103f8a1e bne r2,zero,8037ad0 + } + } +#ifdef ALT_SEMIHOSTING + alt_putbufflush(); +#endif +} + 8037ca8: 00000106 br 8037cb0 + break; + 8037cac: 0001883a nop +} + 8037cb0: 0001883a nop + 8037cb4: e037883a mov sp,fp + 8037cb8: dfc00117 ldw ra,4(sp) + 8037cbc: df000017 ldw fp,0(sp) + 8037cc0: dec00504 addi sp,sp,20 + 8037cc4: f800283a ret + +08037cc8 : + * Uses the ALT_DRIVER_WRITE() macro to call directly to driver if available. + * Otherwise, uses newlib provided putchar() routine. + */ +int +alt_putchar(int c) +{ + 8037cc8: defffd04 addi sp,sp,-12 + 8037ccc: dfc00215 stw ra,8(sp) + 8037cd0: df000115 stw fp,4(sp) + 8037cd4: df000104 addi fp,sp,4 + 8037cd8: e13fff15 stw r4,-4(fp) + if (ALT_DRIVER_WRITE(ALT_STDOUT_DEV, &c1, 1, 0) == -1) { + return -1; + } + return c; +#else + return putchar(c); + 8037cdc: e13fff17 ldw r4,-4(fp) + 8037ce0: 8002cb80 call 8002cb8 +#endif +#endif +} + 8037ce4: e037883a mov sp,fp + 8037ce8: dfc00117 ldw ra,4(sp) + 8037cec: df000017 ldw fp,0(sp) + 8037cf0: dec00204 addi sp,sp,8 + 8037cf4: f800283a ret + +08037cf8 : +{ + 8037cf8: defffe04 addi sp,sp,-8 + 8037cfc: dfc00115 stw ra,4(sp) + 8037d00: df000015 stw fp,0(sp) + 8037d04: d839883a mov fp,sp + return ((alt_errno) ? alt_errno() : &errno); + 8037d08: d0a02717 ldw r2,-32612(gp) + 8037d0c: 10000326 beq r2,zero,8037d1c + 8037d10: d0a02717 ldw r2,-32612(gp) + 8037d14: 103ee83a callr r2 + 8037d18: 00000106 br 8037d20 + 8037d1c: d0a04204 addi r2,gp,-32504 +} + 8037d20: e037883a mov sp,fp + 8037d24: dfc00117 ldw ra,4(sp) + 8037d28: df000017 ldw fp,0(sp) + 8037d2c: dec00204 addi sp,sp,8 + 8037d30: f800283a ret + +08037d34 : +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_READ (int file, void *ptr, size_t len) +{ + 8037d34: defff904 addi sp,sp,-28 + 8037d38: dfc00615 stw ra,24(sp) + 8037d3c: df000515 stw fp,20(sp) + 8037d40: df000504 addi fp,sp,20 + 8037d44: e13ffd15 stw r4,-12(fp) + 8037d48: e17ffc15 stw r5,-16(fp) + 8037d4c: e1bffb15 stw r6,-20(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 8037d50: e0bffd17 ldw r2,-12(fp) + 8037d54: 10000616 blt r2,zero,8037d70 + 8037d58: e0bffd17 ldw r2,-12(fp) + 8037d5c: 10c00324 muli r3,r2,12 + 8037d60: 00820174 movhi r2,2053 + 8037d64: 10b21a04 addi r2,r2,-14232 + 8037d68: 1885883a add r2,r3,r2 + 8037d6c: 00000106 br 8037d74 + 8037d70: 0005883a mov r2,zero + 8037d74: e0bfff15 stw r2,-4(fp) + + if (fd) + 8037d78: e0bfff17 ldw r2,-4(fp) + 8037d7c: 10002226 beq r2,zero,8037e08 + * If the file has not been opened with read access, or if the driver does + * not provide an implementation of read(), generate an error. Otherwise + * call the drivers read() function to process the request. + */ + + if (((fd->fd_flags & O_ACCMODE) != O_WRONLY) && + 8037d80: e0bfff17 ldw r2,-4(fp) + 8037d84: 10800217 ldw r2,8(r2) + 8037d88: 108000cc andi r2,r2,3 + 8037d8c: 10800060 cmpeqi r2,r2,1 + 8037d90: 1000181e bne r2,zero,8037df4 + (fd->dev->read)) + 8037d94: e0bfff17 ldw r2,-4(fp) + 8037d98: 10800017 ldw r2,0(r2) + 8037d9c: 10800517 ldw r2,20(r2) + if (((fd->fd_flags & O_ACCMODE) != O_WRONLY) && + 8037da0: 10001426 beq r2,zero,8037df4 + { + if ((rval = fd->dev->read(fd, ptr, len)) < 0) + 8037da4: e0bfff17 ldw r2,-4(fp) + 8037da8: 10800017 ldw r2,0(r2) + 8037dac: 10800517 ldw r2,20(r2) + 8037db0: e0fffb17 ldw r3,-20(fp) + 8037db4: 180d883a mov r6,r3 + 8037db8: e17ffc17 ldw r5,-16(fp) + 8037dbc: e13fff17 ldw r4,-4(fp) + 8037dc0: 103ee83a callr r2 + 8037dc4: e0bffe15 stw r2,-8(fp) + 8037dc8: e0bffe17 ldw r2,-8(fp) + 8037dcc: 1000070e bge r2,zero,8037dec + { + ALT_ERRNO = -rval; + 8037dd0: 8037cf80 call 8037cf8 + 8037dd4: 1007883a mov r3,r2 + 8037dd8: e0bffe17 ldw r2,-8(fp) + 8037ddc: 0085c83a sub r2,zero,r2 + 8037de0: 18800015 stw r2,0(r3) + return -1; + 8037de4: 00bfffc4 movi r2,-1 + 8037de8: 00000c06 br 8037e1c + } + return rval; + 8037dec: e0bffe17 ldw r2,-8(fp) + 8037df0: 00000a06 br 8037e1c + } + else + { + ALT_ERRNO = EACCES; + 8037df4: 8037cf80 call 8037cf8 + 8037df8: 1007883a mov r3,r2 + 8037dfc: 00800344 movi r2,13 + 8037e00: 18800015 stw r2,0(r3) + 8037e04: 00000406 br 8037e18 + } + } + else + { + ALT_ERRNO = EBADFD; + 8037e08: 8037cf80 call 8037cf8 + 8037e0c: 1007883a mov r3,r2 + 8037e10: 00801444 movi r2,81 + 8037e14: 18800015 stw r2,0(r3) + } + return -1; + 8037e18: 00bfffc4 movi r2,-1 +} + 8037e1c: e037883a mov sp,fp + 8037e20: dfc00117 ldw ra,4(sp) + 8037e24: df000017 ldw fp,0(sp) + 8037e28: dec00204 addi sp,sp,8 + 8037e2c: f800283a ret + +08037e30 : + * File descriptors correcponding to standard in, standard out and standard + * error cannont be released backed to the pool. They are always reserved. + */ + +void alt_release_fd (int fd) +{ + 8037e30: defffe04 addi sp,sp,-8 + 8037e34: df000115 stw fp,4(sp) + 8037e38: df000104 addi fp,sp,4 + 8037e3c: e13fff15 stw r4,-4(fp) + if (fd > 2) + 8037e40: e0bfff17 ldw r2,-4(fp) + 8037e44: 108000d0 cmplti r2,r2,3 + 8037e48: 10000a1e bne r2,zero,8037e74 + { + alt_fd_list[fd].fd_flags = 0; + 8037e4c: e0bfff17 ldw r2,-4(fp) + 8037e50: 10c00324 muli r3,r2,12 + 8037e54: 00820174 movhi r2,2053 + 8037e58: 1885883a add r2,r3,r2 + 8037e5c: 10321c15 stw zero,-14224(r2) + alt_fd_list[fd].dev = 0; + 8037e60: e0bfff17 ldw r2,-4(fp) + 8037e64: 10c00324 muli r3,r2,12 + 8037e68: 00820174 movhi r2,2053 + 8037e6c: 1885883a add r2,r3,r2 + 8037e70: 10321a15 stw zero,-14232(r2) + } +} + 8037e74: 0001883a nop + 8037e78: e037883a mov sp,fp + 8037e7c: df000017 ldw fp,0(sp) + 8037e80: dec00104 addi sp,sp,4 + 8037e84: f800283a ret + +08037e88 : + * Return a pointer that should be used to access the cached memory. + */ + +void* +alt_remap_cached(volatile void* ptr, alt_u32 len) +{ + 8037e88: defffd04 addi sp,sp,-12 + 8037e8c: df000215 stw fp,8(sp) + 8037e90: df000204 addi fp,sp,8 + 8037e94: e13fff15 stw r4,-4(fp) + 8037e98: e17ffe15 stw r5,-8(fp) +#if ALT_CPU_DCACHE_SIZE > 0 +#ifdef ALT_CPU_DCACHE_BYPASS_MASK + return (void*) (((alt_u32)ptr) & ~ALT_CPU_DCACHE_BYPASS_MASK); + 8037e9c: e0ffff17 ldw r3,-4(fp) + 8037ea0: 00a00034 movhi r2,32768 + 8037ea4: 10bfffc4 addi r2,r2,-1 + 8037ea8: 1884703a and r2,r3,r2 +#endif /* No address mask option enabled. */ +#else /* No data cache */ + /* Nothing needs to be done to the pointer. */ + return (void*) ptr; +#endif /* No data cache */ +} + 8037eac: e037883a mov sp,fp + 8037eb0: df000017 ldw fp,0(sp) + 8037eb4: dec00104 addi sp,sp,4 + 8037eb8: f800283a ret + +08037ebc : + * alarms. Alternatively an alarm can unregister itself by returning zero when + * the alarm executes. + */ + +void alt_alarm_stop (alt_alarm* alarm) +{ + 8037ebc: defffa04 addi sp,sp,-24 + 8037ec0: df000515 stw fp,20(sp) + 8037ec4: df000504 addi fp,sp,20 + 8037ec8: e13ffb15 stw r4,-20(fp) + NIOS2_READ_STATUS (context); + 8037ecc: 0005303a rdctl r2,status + 8037ed0: e0bffc15 stw r2,-16(fp) + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 8037ed4: e0fffc17 ldw r3,-16(fp) + 8037ed8: 00bfff84 movi r2,-2 + 8037edc: 1884703a and r2,r3,r2 + 8037ee0: 1001703a wrctl status,r2 + return context; + 8037ee4: e0bffc17 ldw r2,-16(fp) + alt_irq_context irq_context; + + irq_context = alt_irq_disable_all(); + 8037ee8: e0bfff15 stw r2,-4(fp) + alt_llist_remove (&alarm->llist); + 8037eec: e0bffb17 ldw r2,-20(fp) + 8037ef0: e0bffd15 stw r2,-12(fp) + * input argument is the element to remove. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_remove(alt_llist* entry) +{ + entry->next->previous = entry->previous; + 8037ef4: e0bffd17 ldw r2,-12(fp) + 8037ef8: 10800017 ldw r2,0(r2) + 8037efc: e0fffd17 ldw r3,-12(fp) + 8037f00: 18c00117 ldw r3,4(r3) + 8037f04: 10c00115 stw r3,4(r2) + entry->previous->next = entry->next; + 8037f08: e0bffd17 ldw r2,-12(fp) + 8037f0c: 10800117 ldw r2,4(r2) + 8037f10: e0fffd17 ldw r3,-12(fp) + 8037f14: 18c00017 ldw r3,0(r3) + 8037f18: 10c00015 stw r3,0(r2) + /* + * Set the entry to point to itself, so that any further calls to + * alt_llist_remove() are harmless. + */ + + entry->previous = entry; + 8037f1c: e0bffd17 ldw r2,-12(fp) + 8037f20: e0fffd17 ldw r3,-12(fp) + 8037f24: 10c00115 stw r3,4(r2) + entry->next = entry; + 8037f28: e0bffd17 ldw r2,-12(fp) + 8037f2c: e0fffd17 ldw r3,-12(fp) + 8037f30: 10c00015 stw r3,0(r2) + 8037f34: e0bfff17 ldw r2,-4(fp) + 8037f38: e0bffe15 stw r2,-8(fp) + NIOS2_WRITE_STATUS (context); + 8037f3c: e0bffe17 ldw r2,-8(fp) + 8037f40: 1001703a wrctl status,r2 + alt_irq_enable_all (irq_context); +} + 8037f44: 0001883a nop + 8037f48: e037883a mov sp,fp + 8037f4c: df000017 ldw fp,0(sp) + 8037f50: dec00104 addi sp,sp,4 + 8037f54: f800283a ret + +08037f58 : + * + * alt_tick() is expected to run at interrupt level. + */ + +void alt_tick (void) +{ + 8037f58: defffb04 addi sp,sp,-20 + 8037f5c: dfc00415 stw ra,16(sp) + 8037f60: df000315 stw fp,12(sp) + 8037f64: df000304 addi fp,sp,12 + alt_alarm* next; + alt_alarm* alarm = (alt_alarm*) alt_alarm_list.next; + 8037f68: d0a02917 ldw r2,-32604(gp) + 8037f6c: e0bfff15 stw r2,-4(fp) + + alt_u32 next_callback; + + /* update the tick counter */ + + _alt_nticks++; + 8037f70: d0a08e17 ldw r2,-32200(gp) + 8037f74: 10800044 addi r2,r2,1 + 8037f78: d0a08e15 stw r2,-32200(gp) + + /* process the registered callbacks */ + + while (alarm != (alt_alarm*) &alt_alarm_list) + 8037f7c: 00002e06 br 8038038 + { + next = (alt_alarm*) alarm->llist.next; + 8037f80: e0bfff17 ldw r2,-4(fp) + 8037f84: 10800017 ldw r2,0(r2) + 8037f88: e0bffe15 stw r2,-8(fp) + /* + * Upon the tick-counter rolling over it is safe to clear the + * roll-over flag; once the flag is cleared this (or subsequnt) + * tick events are enabled to generate an alarm event. + */ + if ((alarm->rollover) && (_alt_nticks == 0)) + 8037f8c: e0bfff17 ldw r2,-4(fp) + 8037f90: 10800403 ldbu r2,16(r2) + 8037f94: 10803fcc andi r2,r2,255 + 8037f98: 10000426 beq r2,zero,8037fac + 8037f9c: d0a08e17 ldw r2,-32200(gp) + 8037fa0: 1000021e bne r2,zero,8037fac + { + alarm->rollover = 0; + 8037fa4: e0bfff17 ldw r2,-4(fp) + 8037fa8: 10000405 stb zero,16(r2) + } + + /* if the alarm period has expired, make the callback */ + if ((alarm->time <= _alt_nticks) && (alarm->rollover == 0)) + 8037fac: e0bfff17 ldw r2,-4(fp) + 8037fb0: 10800217 ldw r2,8(r2) + 8037fb4: d0e08e17 ldw r3,-32200(gp) + 8037fb8: 18801d36 bltu r3,r2,8038030 + 8037fbc: e0bfff17 ldw r2,-4(fp) + 8037fc0: 10800403 ldbu r2,16(r2) + 8037fc4: 10803fcc andi r2,r2,255 + 8037fc8: 1000191e bne r2,zero,8038030 + { + next_callback = alarm->callback (alarm->context); + 8037fcc: e0bfff17 ldw r2,-4(fp) + 8037fd0: 10800317 ldw r2,12(r2) + 8037fd4: e0ffff17 ldw r3,-4(fp) + 8037fd8: 18c00517 ldw r3,20(r3) + 8037fdc: 1809883a mov r4,r3 + 8037fe0: 103ee83a callr r2 + 8037fe4: e0bffd15 stw r2,-12(fp) + + /* deactivate the alarm if the return value is zero */ + + if (next_callback == 0) + 8037fe8: e0bffd17 ldw r2,-12(fp) + 8037fec: 1000031e bne r2,zero,8037ffc + { + alt_alarm_stop (alarm); + 8037ff0: e13fff17 ldw r4,-4(fp) + 8037ff4: 8037ebc0 call 8037ebc + 8037ff8: 00000d06 br 8038030 + } + else + { + alarm->time += next_callback; + 8037ffc: e0bfff17 ldw r2,-4(fp) + 8038000: 10c00217 ldw r3,8(r2) + 8038004: e0bffd17 ldw r2,-12(fp) + 8038008: 1887883a add r3,r3,r2 + 803800c: e0bfff17 ldw r2,-4(fp) + 8038010: 10c00215 stw r3,8(r2) + /* + * If the desired alarm time causes a roll-over, set the rollover + * flag. This will prevent the subsequent tick event from causing + * an alarm too early. + */ + if(alarm->time < _alt_nticks) + 8038014: e0bfff17 ldw r2,-4(fp) + 8038018: 10c00217 ldw r3,8(r2) + 803801c: d0a08e17 ldw r2,-32200(gp) + 8038020: 1880032e bgeu r3,r2,8038030 + { + alarm->rollover = 1; + 8038024: e0bfff17 ldw r2,-4(fp) + 8038028: 00c00044 movi r3,1 + 803802c: 10c00405 stb r3,16(r2) + } + } + } + alarm = next; + 8038030: e0bffe17 ldw r2,-8(fp) + 8038034: e0bfff15 stw r2,-4(fp) + while (alarm != (alt_alarm*) &alt_alarm_list) + 8038038: e0ffff17 ldw r3,-4(fp) + 803803c: d0a02904 addi r2,gp,-32604 + 8038040: 18bfcf1e bne r3,r2,8037f80 + + /* + * Update the operating system specific timer facilities. + */ + + ALT_OS_TIME_TICK(); + 8038044: 8010ad80 call 8010ad8 +} + 8038048: 0001883a nop + 803804c: e037883a mov sp,fp + 8038050: dfc00117 ldw ra,4(sp) + 8038054: df000017 ldw fp,0(sp) + 8038058: dec00204 addi sp,sp,8 + 803805c: f800283a ret + +08038060 : + * Free a block of uncached memory. + */ + +void +alt_uncached_free(volatile void* ptr) +{ + 8038060: defffd04 addi sp,sp,-12 + 8038064: dfc00215 stw ra,8(sp) + 8038068: df000115 stw fp,4(sp) + 803806c: df000104 addi fp,sp,4 + 8038070: e13fff15 stw r4,-4(fp) +#if ALT_CPU_DCACHE_SIZE > 0 +#ifdef ALT_CPU_DCACHE_BYPASS_MASK + free((void*) (((alt_u32)ptr) & ~ALT_CPU_DCACHE_BYPASS_MASK)); + 8038074: e0ffff17 ldw r3,-4(fp) + 8038078: 00a00034 movhi r2,32768 + 803807c: 10bfffc4 addi r2,r2,-1 + 8038080: 1884703a and r2,r3,r2 + 8038084: 1009883a mov r4,r2 + 8038088: 8042ca80 call 8042ca8 +#endif /* No address mask option enabled. */ +#else /* No data cache */ + /* Nothing needs to be done to the pointer. */ + free((void*)ptr); +#endif /* No data cache */ +} + 803808c: 0001883a nop + 8038090: e037883a mov sp,fp + 8038094: dfc00117 ldw ra,4(sp) + 8038098: df000017 ldw fp,0(sp) + 803809c: dec00204 addi sp,sp,8 + 80380a0: f800283a ret + +080380a4 : + * Return pointer to the block of memory or NULL if can't allocate it. + */ + +volatile void* +alt_uncached_malloc(size_t size) +{ + 80380a4: defffa04 addi sp,sp,-24 + 80380a8: dfc00515 stw ra,20(sp) + 80380ac: df000415 stw fp,16(sp) + 80380b0: df000404 addi fp,sp,16 + 80380b4: e13ffc15 stw r4,-16(fp) + + void* ptr; + + /* Round up size to an integer number of data cache lines. Required to guarantee that + * cacheable and non-cacheable data won't be mixed on the same cache line. */ + const size_t num_lines = (size + ALT_CPU_DCACHE_LINE_SIZE - 1) / ALT_CPU_DCACHE_LINE_SIZE; + 80380b8: e0bffc17 ldw r2,-16(fp) + 80380bc: 108007c4 addi r2,r2,31 + 80380c0: 1004d17a srli r2,r2,5 + 80380c4: e0bfff15 stw r2,-4(fp) + const size_t aligned_size = num_lines * ALT_CPU_DCACHE_LINE_SIZE; + 80380c8: e0bfff17 ldw r2,-4(fp) + 80380cc: 1004917a slli r2,r2,5 + 80380d0: e0bffe15 stw r2,-8(fp) + + /* Use memalign() Newlib routine to allocate starting on a data cache aligned address. + * Required to guarantee that cacheable and non-cacheable data won't be mixed on the + * same cache line. */ + ptr = memalign(ALT_CPU_DCACHE_LINE_SIZE, aligned_size); + 80380d4: e17ffe17 ldw r5,-8(fp) + 80380d8: 01000804 movi r4,32 + 80380dc: 8042af00 call 8042af0 + 80380e0: e0bffd15 stw r2,-12(fp) + + if (ptr == NULL) { + 80380e4: e0bffd17 ldw r2,-12(fp) + 80380e8: 1000021e bne r2,zero,80380f4 + return NULL; /* Out of memory */ + 80380ec: 0005883a mov r2,zero + 80380f0: 00000506 br 8038108 + } + + /* Ensure that the memory region isn't in the data cache. */ + alt_dcache_flush(ptr, aligned_size); + 80380f4: e17ffe17 ldw r5,-8(fp) + 80380f8: e13ffd17 ldw r4,-12(fp) + 80380fc: 80371c00 call 80371c0 + + return (volatile void*) (((alt_u32)ptr) | ALT_CPU_DCACHE_BYPASS_MASK); + 8038100: e0bffd17 ldw r2,-12(fp) + 8038104: 10a00034 orhi r2,r2,32768 +#endif /* No address mask option enabled. */ +#else /* No data cache */ + /* Just use regular malloc. */ + return malloc(size); +#endif /* No data cache */ +} + 8038108: e037883a mov sp,fp + 803810c: dfc00117 ldw ra,4(sp) + 8038110: df000017 ldw fp,0(sp) + 8038114: dec00204 addi sp,sp,8 + 8038118: f800283a ret + +0803811c : +#if defined (__GNUC__) && __GNUC__ >= 4 +int ALT_USLEEP (useconds_t us) +#else +unsigned int ALT_USLEEP (unsigned int us) +#endif +{ + 803811c: defffa04 addi sp,sp,-24 + 8038120: dfc00515 stw ra,20(sp) + 8038124: df000415 stw fp,16(sp) + 8038128: dc000315 stw r16,12(sp) + 803812c: df000404 addi fp,sp,16 + 8038130: e13ffc15 stw r4,-16(fp) + * If the O/S hasn't started yet, then we delay using a busy loop, rather than + * OSTimeDly (since this would fail). The use of a busy loop is acceptable, + * since the system is still running in a single-threaded mode. + */ + + if (OSRunning == OS_FALSE) + 8038134: d0a04b43 ldbu r2,-32467(gp) + 8038138: 10803fcc andi r2,r2,255 + 803813c: 1000031e bne r2,zero,803814c + { + return alt_busy_sleep (us); + 8038140: e13ffc17 ldw r4,-16(fp) + 8038144: 8036f5c0 call 8036f5c + 8038148: 00003306 br 8038218 + return _alt_tick_rate; + 803814c: d0a08d17 ldw r2,-32204(gp) + + /* + * Calculate the number of whole system clock ticks to delay. + */ + + tick_rate = alt_ticks_per_second (); + 8038150: e0bffd15 stw r2,-12(fp) + ticks = (us/ALT_US)* tick_rate + ((us%ALT_US)*tick_rate)/ALT_US; + 8038154: e0bffc17 ldw r2,-16(fp) + 8038158: 014003f4 movhi r5,15 + 803815c: 29509004 addi r5,r5,16960 + 8038160: 1009883a mov r4,r2 + 8038164: 800cff80 call 800cff8 <__udivsi3> + 8038168: 1007883a mov r3,r2 + 803816c: e0bffd17 ldw r2,-12(fp) + 8038170: 18a1383a mul r16,r3,r2 + 8038174: e0bffc17 ldw r2,-16(fp) + 8038178: 014003f4 movhi r5,15 + 803817c: 29509004 addi r5,r5,16960 + 8038180: 1009883a mov r4,r2 + 8038184: 800d05c0 call 800d05c <__umodsi3> + 8038188: 1007883a mov r3,r2 + 803818c: e0bffd17 ldw r2,-12(fp) + 8038190: 1885383a mul r2,r3,r2 + 8038194: 014003f4 movhi r5,15 + 8038198: 29509004 addi r5,r5,16960 + 803819c: 1009883a mov r4,r2 + 80381a0: 800cff80 call 800cff8 <__udivsi3> + 80381a4: 8085883a add r2,r16,r2 + 80381a8: e0bffe15 stw r2,-8(fp) + * OSTimeDly can only delay for a maximum of 0xffff ticks, so if the requested + * delay is greater than that, we need to break it down into a number of + * seperate delays. + */ + + while (ticks > 0xffff) + 80381ac: 00000706 br 80381cc + { + OSTimeDly(0xffff); + 80381b0: 013fffd4 movui r4,65535 + 80381b4: 801730c0 call 801730c + ticks -= 0xffff; + 80381b8: e0fffe17 ldw r3,-8(fp) + 80381bc: 00bffff4 movhi r2,65535 + 80381c0: 10800044 addi r2,r2,1 + 80381c4: 1885883a add r2,r3,r2 + 80381c8: e0bffe15 stw r2,-8(fp) + while (ticks > 0xffff) + 80381cc: e0bffe17 ldw r2,-8(fp) + 80381d0: 00ffffd4 movui r3,65535 + 80381d4: 18bff636 bltu r3,r2,80381b0 + } + + OSTimeDly ((INT16U) (ticks)); + 80381d8: e0bffe17 ldw r2,-8(fp) + 80381dc: 10bfffcc andi r2,r2,65535 + 80381e0: 1009883a mov r4,r2 + 80381e4: 801730c0 call 801730c + /* + * Now delay by the remainder using a busy loop. This is here in order to + * provide very short delays of less than one clock tick. + */ + + alt_busy_sleep (us%(ALT_US/tick_rate)); + 80381e8: e17ffd17 ldw r5,-12(fp) + 80381ec: 010003f4 movhi r4,15 + 80381f0: 21109004 addi r4,r4,16960 + 80381f4: 800cff80 call 800cff8 <__udivsi3> + 80381f8: 1007883a mov r3,r2 + 80381fc: e0bffc17 ldw r2,-16(fp) + 8038200: 180b883a mov r5,r3 + 8038204: 1009883a mov r4,r2 + 8038208: 800d05c0 call 800d05c <__umodsi3> + 803820c: 1009883a mov r4,r2 + 8038210: 8036f5c0 call 8036f5c + + return 0; + 8038214: 0005883a mov r2,zero +} + 8038218: e6ffff04 addi sp,fp,-4 + 803821c: dfc00217 ldw ra,8(sp) + 8038220: df000117 ldw fp,4(sp) + 8038224: dc000017 ldw r16,0(sp) + 8038228: dec00304 addi sp,sp,12 + 803822c: f800283a ret + +08038230 : +{ + 8038230: defffe04 addi sp,sp,-8 + 8038234: dfc00115 stw ra,4(sp) + 8038238: df000015 stw fp,0(sp) + 803823c: d839883a mov fp,sp + return ((alt_errno) ? alt_errno() : &errno); + 8038240: d0a02717 ldw r2,-32612(gp) + 8038244: 10000326 beq r2,zero,8038254 + 8038248: d0a02717 ldw r2,-32612(gp) + 803824c: 103ee83a callr r2 + 8038250: 00000106 br 8038258 + 8038254: d0a04204 addi r2,gp,-32504 +} + 8038258: e037883a mov sp,fp + 803825c: dfc00117 ldw ra,4(sp) + 8038260: df000017 ldw fp,0(sp) + 8038264: dec00204 addi sp,sp,8 + 8038268: f800283a ret + +0803826c : +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_WRITE (int file, const void *ptr, size_t len) +{ + 803826c: defff904 addi sp,sp,-28 + 8038270: dfc00615 stw ra,24(sp) + 8038274: df000515 stw fp,20(sp) + 8038278: df000504 addi fp,sp,20 + 803827c: e13ffd15 stw r4,-12(fp) + 8038280: e17ffc15 stw r5,-16(fp) + 8038284: e1bffb15 stw r6,-20(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 8038288: e0bffd17 ldw r2,-12(fp) + 803828c: 10000616 blt r2,zero,80382a8 + 8038290: e0bffd17 ldw r2,-12(fp) + 8038294: 10c00324 muli r3,r2,12 + 8038298: 00820174 movhi r2,2053 + 803829c: 10b21a04 addi r2,r2,-14232 + 80382a0: 1885883a add r2,r3,r2 + 80382a4: 00000106 br 80382ac + 80382a8: 0005883a mov r2,zero + 80382ac: e0bfff15 stw r2,-4(fp) + + if (fd) + 80382b0: e0bfff17 ldw r2,-4(fp) + 80382b4: 10002126 beq r2,zero,803833c + * If the file has not been opened with write access, or if the driver does + * not provide an implementation of write(), generate an error. Otherwise + * call the drivers write() function to process the request. + */ + + if (((fd->fd_flags & O_ACCMODE) != O_RDONLY) && fd->dev->write) + 80382b8: e0bfff17 ldw r2,-4(fp) + 80382bc: 10800217 ldw r2,8(r2) + 80382c0: 108000cc andi r2,r2,3 + 80382c4: 10001826 beq r2,zero,8038328 + 80382c8: e0bfff17 ldw r2,-4(fp) + 80382cc: 10800017 ldw r2,0(r2) + 80382d0: 10800617 ldw r2,24(r2) + 80382d4: 10001426 beq r2,zero,8038328 + { + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_WRITE_FUNCTION(ptr,len); + + if ((rval = fd->dev->write(fd, ptr, len)) < 0) + 80382d8: e0bfff17 ldw r2,-4(fp) + 80382dc: 10800017 ldw r2,0(r2) + 80382e0: 10800617 ldw r2,24(r2) + 80382e4: e0fffb17 ldw r3,-20(fp) + 80382e8: 180d883a mov r6,r3 + 80382ec: e17ffc17 ldw r5,-16(fp) + 80382f0: e13fff17 ldw r4,-4(fp) + 80382f4: 103ee83a callr r2 + 80382f8: e0bffe15 stw r2,-8(fp) + 80382fc: e0bffe17 ldw r2,-8(fp) + 8038300: 1000070e bge r2,zero,8038320 + { + ALT_ERRNO = -rval; + 8038304: 80382300 call 8038230 + 8038308: 1007883a mov r3,r2 + 803830c: e0bffe17 ldw r2,-8(fp) + 8038310: 0085c83a sub r2,zero,r2 + 8038314: 18800015 stw r2,0(r3) + return -1; + 8038318: 00bfffc4 movi r2,-1 + 803831c: 00000c06 br 8038350 + } + return rval; + 8038320: e0bffe17 ldw r2,-8(fp) + 8038324: 00000a06 br 8038350 + } + else + { + ALT_ERRNO = EACCES; + 8038328: 80382300 call 8038230 + 803832c: 1007883a mov r3,r2 + 8038330: 00800344 movi r2,13 + 8038334: 18800015 stw r2,0(r3) + 8038338: 00000406 br 803834c + } + } + else + { + ALT_ERRNO = EBADFD; + 803833c: 80382300 call 8038230 + 8038340: 1007883a mov r3,r2 + 8038344: 00801444 movi r2,81 + 8038348: 18800015 stw r2,0(r3) + } + return -1; + 803834c: 00bfffc4 movi r2,-1 +} + 8038350: e037883a mov sp,fp + 8038354: dfc00117 ldw ra,4(sp) + 8038358: df000017 ldw fp,0(sp) + 803835c: dec00204 addi sp,sp,8 + 8038360: f800283a ret + +08038364 : +/* + * To initialize the internal interrupt controller, just clear the IENABLE + * register so that all possible IRQs are disabled. + */ +void altera_nios2_gen2_irq_init(void) +{ + 8038364: deffff04 addi sp,sp,-4 + 8038368: df000015 stw fp,0(sp) + 803836c: d839883a mov fp,sp + NIOS2_WRITE_IENABLE(0); + 8038370: 000170fa wrctl ienable,zero +} + 8038374: 0001883a nop + 8038378: e037883a mov sp,fp + 803837c: df000017 ldw fp,0(sp) + 8038380: dec00104 addi sp,sp,4 + 8038384: f800283a ret + +08038388 : + + /* + * Save the remaining registers to the stack. + */ + + addi sp, sp, -44 + 8038388: defff504 addi sp,sp,-44 + bltu sp, et, .Lstack_overflow + +#endif + +#if OS_THREAD_SAFE_NEWLIB + ldw r3, %gprel(_impure_ptr)(gp) /* load the pointer */ + 803838c: d0e00117 ldw r3,-32764(gp) +#endif /* OS_THREAD_SAFE_NEWLIB */ + + ldw r4, %gprel(OSTCBCur)(gp) + 8038390: d1205817 ldw r4,-32416(gp) + + stw ra, 0(sp) + 8038394: dfc00015 stw ra,0(sp) + stw fp, 4(sp) + 8038398: df000115 stw fp,4(sp) + stw r23, 8(sp) + 803839c: ddc00215 stw r23,8(sp) + stw r22, 12(sp) + 80383a0: dd800315 stw r22,12(sp) + stw r21, 16(sp) + 80383a4: dd400415 stw r21,16(sp) + stw r20, 20(sp) + 80383a8: dd000515 stw r20,20(sp) + stw r19, 24(sp) + 80383ac: dcc00615 stw r19,24(sp) + stw r18, 28(sp) + 80383b0: dc800715 stw r18,28(sp) + stw r17, 32(sp) + 80383b4: dc400815 stw r17,32(sp) + stw r16, 36(sp) + 80383b8: dc000915 stw r16,36(sp) + * store the current value of _impure_ptr so it can be restored + * later; _impure_ptr is asigned on a per task basis. It is used + * by Newlib to achieve reentrancy. + */ + + stw r3, 40(sp) /* save the impure pointer */ + 80383bc: d8c00a15 stw r3,40(sp) + /* + * Save the current tasks stack pointer into the current tasks OS_TCB. + * i.e. OSTCBCur->OSTCBStkPtr = sp; + */ + + stw sp, (r4) /* save the stack pointer (OSTCBStkPtr */ + 80383c0: 26c00015 stw sp,0(r4) + + /* + * Call the user definable OSTaskSWHook() + */ + + call OSTaskSwHook + 80383c4: 80385ec0 call 80385ec + /* + * OSTCBCur = OSTCBHighRdy; + * OSPrioCur = OSPrioHighRdy; + */ + + ldw r4, %gprel(OSTCBHighRdy)(gp) + 80383c8: d1205317 ldw r4,-32436(gp) + ldb r5, %gprel(OSPrioHighRdy)(gp) + 80383cc: d1604d07 ldb r5,-32460(gp) + + stw r4, %gprel(OSTCBCur)(gp) /* set the current task to be the new task */ + 80383d0: d1205815 stw r4,-32416(gp) + stb r5, %gprel(OSPrioCur)(gp) /* store the new task's priority as the current */ + 80383d4: d1604d45 stb r5,-32459(gp) + + /* + * Set the stack pointer to point to the new task's stack + */ + + ldw sp, (r4) /* the stack pointer is the first entry in the OS_TCB structure */ + 80383d8: 26c00017 ldw sp,0(r4) + /* + * restore the value of _impure_ptr ; _impure_ptr is asigned on a + * per task basis. It is used by Newlib to achieve reentrancy. + */ + + ldw r3, 40(sp) /* load the new impure pointer */ + 80383dc: d8c00a17 ldw r3,40(sp) + + /* + * Restore the saved registers for the new task. + */ + + ldw ra, 0(sp) + 80383e0: dfc00017 ldw ra,0(sp) + ldw fp, 4(sp) + 80383e4: df000117 ldw fp,4(sp) + ldw r23, 8(sp) + 80383e8: ddc00217 ldw r23,8(sp) + ldw r22, 12(sp) + 80383ec: dd800317 ldw r22,12(sp) + ldw r21, 16(sp) + 80383f0: dd400417 ldw r21,16(sp) + ldw r20, 20(sp) + 80383f4: dd000517 ldw r20,20(sp) + ldw r19, 24(sp) + 80383f8: dcc00617 ldw r19,24(sp) + ldw r18, 28(sp) + 80383fc: dc800717 ldw r18,28(sp) + ldw r17, 32(sp) + 8038400: dc400817 ldw r17,32(sp) + ldw r16, 36(sp) + 8038404: dc000917 ldw r16,36(sp) + +#if OS_THREAD_SAFE_NEWLIB + + stw r3, %gprel(_impure_ptr)(gp) /* update _impure_ptr */ + 8038408: d0e00115 stw r3,-32764(gp) + + stw et, %gprel(alt_stack_limit_value)(gp) + +#endif + + addi sp, sp, 44 + 803840c: dec00b04 addi sp,sp,44 + + /* + * resume execution of the new task. + */ + + ret + 8038410: f800283a ret + +08038414 : + + /* + * disable interrupts so that the scheduler doesn't run while + * we're initialising this task. + */ + rdctl r18, status + 8038414: 0025303a rdctl r18,status + subi r17, zero, 2 /* r17 = 0xfffffffe */ + 8038418: 047fff84 movi r17,-2 + and r18, r18, r17 + 803841c: 9464703a and r18,r18,r17 + wrctl status, r18 + 8038420: 9001703a wrctl status,r18 + + /* + * Call the user definable OSTaskSWHook() + */ + + call OSTaskSwHook + 8038424: 80385ec0 call 80385ec + + /* + * set OSRunning = TRUE. + */ + + movi r18, 1 /* set r18 to the value 'TRUE' */ + 8038428: 04800044 movi r18,1 + stb r18, %gprel(OSRunning)(gp) /* save this to OSRunning */ + 803842c: d4a04b45 stb r18,-32467(gp) + + /* + * start execution of the new task. + */ + + br 9b + 8038430: 003fe506 br 80383c8 + +08038434 : + +OSStartTsk: + /* This instruction is never executed. Its here to make the + * backtrace work right + */ + movi sp, 0 + 8038434: 06c00004 movi sp,0 + + /* Enable interrupts */ + rdctl r2, status + 8038438: 0005303a rdctl r2,status + ori r2, r2, 0x1 + 803843c: 10800054 ori r2,r2,1 + wrctl status, r2 + 8038440: 1001703a wrctl status,r2 + + ldw r2, 4(sp) + 8038444: d8800117 ldw r2,4(sp) + ldw r4, 0(sp) + 8038448: d9000017 ldw r4,0(sp) + + addi sp, sp, 8 + 803844c: dec00204 addi sp,sp,8 + + callr r2 + 8038450: 103ee83a callr r2 + + nop + 8038454: 0001883a nop + +08038458 : + * been placed on the stack in the proper order. + * + ***********************************************************************************************/ + +OS_STK *OSTaskStkInit(void (*task)(void *pd), void *pdata, OS_STK *pstk, INT16U opt) +{ + 8038458: defff704 addi sp,sp,-36 + 803845c: dfc00815 stw ra,32(sp) + 8038460: df000715 stw fp,28(sp) + 8038464: df000704 addi fp,sp,28 + 8038468: e13ffc15 stw r4,-16(fp) + 803846c: e17ffb15 stw r5,-20(fp) + 8038470: e1bffa15 stw r6,-24(fp) + 8038474: 3805883a mov r2,r7 + 8038478: e0bff90d sth r2,-28(fp) + * create and initialise the impure pointer used for Newlib thread local storage. + * This is only done if the C library is being used in a thread safe mode. Otherwise + * a single reent structure is used for all threads, which saves memory. + */ + + local_impure_ptr = (struct _reent*)((((INT32U)(pstk)) & ~0x3) - sizeof(struct _reent)); + 803847c: e0fffa17 ldw r3,-24(fp) + 8038480: 00bfff04 movi r2,-4 + 8038484: 1884703a and r2,r3,r2 + 8038488: 10bef704 addi r2,r2,-1060 + 803848c: e0bfff15 stw r2,-4(fp) + + _REENT_INIT_PTR (local_impure_ptr); + 8038490: 01810904 movi r6,1060 + 8038494: 000b883a mov r5,zero + 8038498: e13fff17 ldw r4,-4(fp) + 803849c: 80088e40 call 80088e4 + 80384a0: e0bfff17 ldw r2,-4(fp) + 80384a4: 10c0bb04 addi r3,r2,748 + 80384a8: e0bfff17 ldw r2,-4(fp) + 80384ac: 10c00115 stw r3,4(r2) + 80384b0: e0bfff17 ldw r2,-4(fp) + 80384b4: 10c0d504 addi r3,r2,852 + 80384b8: e0bfff17 ldw r2,-4(fp) + 80384bc: 10c00215 stw r3,8(r2) + 80384c0: e0bfff17 ldw r2,-4(fp) + 80384c4: 10c0ef04 addi r3,r2,956 + 80384c8: e0bfff17 ldw r2,-4(fp) + 80384cc: 10c00315 stw r3,12(r2) + 80384d0: e0bfff17 ldw r2,-4(fp) + 80384d4: 00c00044 movi r3,1 + 80384d8: 10c02915 stw r3,164(r2) + 80384dc: 10002a15 stw zero,168(r2) + 80384e0: e0bfff17 ldw r2,-4(fp) + 80384e4: 00ccc384 movi r3,13070 + 80384e8: 10c02b0d sth r3,172(r2) + 80384ec: e0bfff17 ldw r2,-4(fp) + 80384f0: 00eaf344 movi r3,-21555 + 80384f4: 10c02b8d sth r3,174(r2) + 80384f8: e0bfff17 ldw r2,-4(fp) + 80384fc: 00c48d04 movi r3,4660 + 8038500: 10c02c0d sth r3,176(r2) + 8038504: e0bfff17 ldw r2,-4(fp) + 8038508: 00f99b44 movi r3,-6547 + 803850c: 10c02c8d sth r3,178(r2) + 8038510: e0bfff17 ldw r2,-4(fp) + 8038514: 00f7bb04 movi r3,-8468 + 8038518: 10c02d0d sth r3,180(r2) + 803851c: e0bfff17 ldw r2,-4(fp) + 8038520: 00c00144 movi r3,5 + 8038524: 10c02d8d sth r3,182(r2) + 8038528: e0bfff17 ldw r2,-4(fp) + 803852c: 00c002c4 movi r3,11 + 8038530: 10c02e0d sth r3,184(r2) + /* + * create a stack frame at the top of the stack (leaving space for the + * reentrant data structure). + */ + + frame_pointer = (INT32U*) local_impure_ptr; + 8038534: e0bfff17 ldw r2,-4(fp) + 8038538: e0bffe15 stw r2,-8(fp) +#else + frame_pointer = (INT32U*) (((INT32U)(pstk)) & ~0x3); +#endif /* OS_THREAD_SAFE_NEWLIB */ + stk = frame_pointer - 13; + 803853c: e0bffe17 ldw r2,-8(fp) + 8038540: 10bff304 addi r2,r2,-52 + 8038544: e0bffd15 stw r2,-12(fp) + + /* Now fill the stack frame. */ + + stk[12] = (INT32U)task; /* task address (ra) */ + 8038548: e0bffd17 ldw r2,-12(fp) + 803854c: 10800c04 addi r2,r2,48 + 8038550: e0fffc17 ldw r3,-16(fp) + 8038554: 10c00015 stw r3,0(r2) + stk[11] = (INT32U) pdata; /* first register argument (r4) */ + 8038558: e0bffd17 ldw r2,-12(fp) + 803855c: 10800b04 addi r2,r2,44 + 8038560: e0fffb17 ldw r3,-20(fp) + 8038564: 10c00015 stw r3,0(r2) + +#if OS_THREAD_SAFE_NEWLIB + stk[10] = (INT32U) local_impure_ptr; /* value of _impure_ptr for this thread */ + 8038568: e0bffd17 ldw r2,-12(fp) + 803856c: 10800a04 addi r2,r2,40 + 8038570: e0ffff17 ldw r3,-4(fp) + 8038574: 10c00015 stw r3,0(r2) +#endif /* OS_THREAD_SAFE_NEWLIB */ + stk[0] = ((INT32U)&OSStartTsk) + 4;/* exception return address (ea) */ + 8038578: 00820134 movhi r2,2052 + 803857c: 10a10d04 addi r2,r2,-31692 + 8038580: 10c00104 addi r3,r2,4 + 8038584: e0bffd17 ldw r2,-12(fp) + 8038588: 10c00015 stw r3,0(r2) + */ + __asm__ (".set OSTCBNext_OFFSET,%0" :: "i" (offsetof(OS_TCB, OSTCBNext))); + __asm__ (".set OSTCBPrio_OFFSET,%0" :: "i" (offsetof(OS_TCB, OSTCBPrio))); + __asm__ (".set OSTCBStkPtr_OFFSET,%0" :: "i" (offsetof(OS_TCB, OSTCBStkPtr))); + + return((OS_STK *)stk); + 803858c: e0bffd17 ldw r2,-12(fp) +} + 8038590: e037883a mov sp,fp + 8038594: dfc00117 ldw ra,4(sp) + 8038598: df000017 ldw fp,0(sp) + 803859c: dec00204 addi sp,sp,8 + 80385a0: f800283a ret + +080385a4 : +* +* Note(s) : 1) Interrupts are disabled during this call. +********************************************************************************************************* +*/ +void OSTaskCreateHook (OS_TCB *ptcb) +{ + 80385a4: defffe04 addi sp,sp,-8 + 80385a8: df000115 stw fp,4(sp) + 80385ac: df000104 addi fp,sp,4 + 80385b0: e13fff15 stw r4,-4(fp) + ptcb = ptcb; /* Prevent compiler warning */ +} + 80385b4: 0001883a nop + 80385b8: e037883a mov sp,fp + 80385bc: df000017 ldw fp,0(sp) + 80385c0: dec00104 addi sp,sp,4 + 80385c4: f800283a ret + +080385c8 : +* +* Note(s) : 1) Interrupts are disabled during this call. +********************************************************************************************************* +*/ +void OSTaskDelHook (OS_TCB *ptcb) +{ + 80385c8: defffe04 addi sp,sp,-8 + 80385cc: df000115 stw fp,4(sp) + 80385d0: df000104 addi fp,sp,4 + 80385d4: e13fff15 stw r4,-4(fp) + ptcb = ptcb; /* Prevent compiler warning */ +} + 80385d8: 0001883a nop + 80385dc: e037883a mov sp,fp + 80385e0: df000017 ldw fp,0(sp) + 80385e4: dec00104 addi sp,sp,4 + 80385e8: f800283a ret + +080385ec : +* will be 'switched in' (i.e. the highest priority task) and, 'OSTCBCur' points to the +* task being switched out (i.e. the preempted task). +********************************************************************************************************* +*/ +void OSTaskSwHook (void) +{ + 80385ec: deffff04 addi sp,sp,-4 + 80385f0: df000015 stw fp,0(sp) + 80385f4: d839883a mov fp,sp +} + 80385f8: 0001883a nop + 80385fc: e037883a mov sp,fp + 8038600: df000017 ldw fp,0(sp) + 8038604: dec00104 addi sp,sp,4 + 8038608: f800283a ret + +0803860c : +* +* Arguments : none +********************************************************************************************************* +*/ +void OSTaskStatHook (void) +{ + 803860c: deffff04 addi sp,sp,-4 + 8038610: df000015 stw fp,0(sp) + 8038614: d839883a mov fp,sp +} + 8038618: 0001883a nop + 803861c: e037883a mov sp,fp + 8038620: df000017 ldw fp,0(sp) + 8038624: dec00104 addi sp,sp,4 + 8038628: f800283a ret + +0803862c : +#ifdef ALT_INICHE +void cticks_hook(void); +#endif + +void OSTimeTickHook (void) +{ + 803862c: defffe04 addi sp,sp,-8 + 8038630: dfc00115 stw ra,4(sp) + 8038634: df000015 stw fp,0(sp) + 8038638: d839883a mov fp,sp + } +#endif + +#ifdef ALT_INICHE + /* Service the Interniche timer */ + cticks_hook(); + 803863c: 8028e380 call 8028e38 +#endif +} + 8038640: 0001883a nop + 8038644: e037883a mov sp,fp + 8038648: dfc00117 ldw ra,4(sp) + 803864c: df000017 ldw fp,0(sp) + 8038650: dec00204 addi sp,sp,8 + 8038654: f800283a ret + +08038658 : + +void OSInitHookBegin(void) +{ + 8038658: deffff04 addi sp,sp,-4 + 803865c: df000015 stw fp,0(sp) + 8038660: d839883a mov fp,sp +#if OS_TMR_EN > 0 + OSTmrCtr = 0; +#endif +} + 8038664: 0001883a nop + 8038668: e037883a mov sp,fp + 803866c: df000017 ldw fp,0(sp) + 8038670: dec00104 addi sp,sp,4 + 8038674: f800283a ret + +08038678 : + +void OSInitHookEnd(void) +{ + 8038678: deffff04 addi sp,sp,-4 + 803867c: df000015 stw fp,0(sp) + 8038680: d839883a mov fp,sp +} + 8038684: 0001883a nop + 8038688: e037883a mov sp,fp + 803868c: df000017 ldw fp,0(sp) + 8038690: dec00104 addi sp,sp,4 + 8038694: f800283a ret + +08038698 : + +void OSTaskIdleHook(void) +{ + 8038698: deffff04 addi sp,sp,-4 + 803869c: df000015 stw fp,0(sp) + 80386a0: d839883a mov fp,sp +} + 80386a4: 0001883a nop + 80386a8: e037883a mov sp,fp + 80386ac: df000017 ldw fp,0(sp) + 80386b0: dec00104 addi sp,sp,4 + 80386b4: f800283a ret + +080386b8 : + +void OSTCBInitHook(OS_TCB *ptcb) +{ + 80386b8: defffe04 addi sp,sp,-8 + 80386bc: df000115 stw fp,4(sp) + 80386c0: df000104 addi fp,sp,4 + 80386c4: e13fff15 stw r4,-4(fp) +} + 80386c8: 0001883a nop + 80386cc: e037883a mov sp,fp + 80386d0: df000017 ldw fp,0(sp) + 80386d4: dec00104 addi sp,sp,4 + 80386d8: f800283a ret + +080386dc : + * RETURNS: + */ + +void +netmain_init(void) +{ + 80386dc: defffb04 addi sp,sp,-20 + 80386e0: dfc00415 stw ra,16(sp) + 80386e4: df000315 stw fp,12(sp) + 80386e8: dc000215 stw r16,8(sp) + 80386ec: df000304 addi fp,sp,12 + int e = 0; + 80386f0: e03ffe15 stw zero,-8(fp) + char * msg; +#ifdef IP_V6 + ip6_addr host; +#endif + + printf("%s\n", name); + 80386f4: d0a02b17 ldw r2,-32596(gp) + 80386f8: 1009883a mov r4,r2 + 80386fc: 8002d9c0 call 8002d9c + printf("Copyright 1996-2008 by InterNiche Technologies. All rights reserved. \n"); + 8038700: 01020174 movhi r4,2053 + 8038704: 212ad404 addi r4,r4,-21680 + 8038708: 8002d9c0 call 8002d9c +#ifdef IN_MENUS + install_version("allports3.1"); +#endif +#ifndef SUPERLOOP + /* call this to do pre-task setup including intialization of port_prep */ + msg = pre_task_setup(); + 803870c: 802959c0 call 802959c + 8038710: e0bffd15 stw r2,-12(fp) + if (msg) + 8038714: e0bffd17 ldw r2,-12(fp) + 8038718: 10000226 beq r2,zero,8038724 + panic(msg); + 803871c: e13ffd17 ldw r4,-12(fp) + 8038720: 80271780 call 8027178 + printf("global_log_create() failed\n"); + } + glog_with_type(LOG_TYPE_INFO, "INICHE LOG initialized", 1); +#endif + + msg = ip_startup(); + 8038724: 8024f800 call 8024f80 + 8038728: e0bffd15 stw r2,-12(fp) + if (msg) + 803872c: e0bffd17 ldw r2,-12(fp) + 8038730: 10000726 beq r2,zero,8038750 + { + printf("inet startup error: %s\n", msg); + 8038734: e17ffd17 ldw r5,-12(fp) + 8038738: 01020174 movhi r4,2053 + 803873c: 212ae604 addi r4,r4,-21608 + 8038740: 8002c780 call 8002c78 + panic("IP"); + 8038744: 01020174 movhi r4,2053 + 8038748: 212aec04 addi r4,r4,-21584 + 803874c: 80271780 call 8027178 + } + +#if defined(MEMDEV_SIZE) && defined(VFS_FILES) + init_memdev(); /* init the mem and null test devices */ + 8038750: 803f5980 call 803f598 +#endif + +#ifdef IP_MULTICAST +#ifdef INCLUDE_TCP + /* call the IP multicast test program */ + u_mctest_init(); + 8038754: 803eef80 call 803eef8 + + /* clear debugging flags. Port can optionally turn them + * back on in post_task_setup(); + * NDEBUG = UPCTRACE | IPTRACE | TPTRACE ; + */ + NDEBUG = 0; + 8038758: d0206615 stw zero,-32360(gp) + + /* print IP address of the first interface - for user's benefit */ + printf("IP address of %s : %s\n" , ((NET)(netlist.q_head))->name, + 803875c: 008201b4 movhi r2,2054 + 8038760: 10b6a617 ldw r2,-9576(r2) + 8038764: 14000104 addi r16,r2,4 + print_ipad(((NET)(netlist.q_head))->n_ipaddr)); + 8038768: 008201b4 movhi r2,2054 + 803876c: 10b6a617 ldw r2,-9576(r2) + printf("IP address of %s : %s\n" , ((NET)(netlist.q_head))->name, + 8038770: 10800a17 ldw r2,40(r2) + 8038774: 1009883a mov r4,r2 + 8038778: 8026fbc0 call 8026fbc + 803877c: 100d883a mov r6,r2 + 8038780: 800b883a mov r5,r16 + 8038784: 01020174 movhi r4,2053 + 8038788: 212aed04 addi r4,r4,-21580 + 803878c: 8002c780 call 8002c78 + +#ifndef SUPERLOOP + /* call this per-target routine after basic tasks & net are up */ + msg = post_task_setup(); + 8038790: 80295e80 call 80295e8 + 8038794: e0bffd15 stw r2,-12(fp) + if (msg) + 8038798: e0bffd17 ldw r2,-12(fp) + 803879c: 10000226 beq r2,zero,80387a8 + panic(msg); + 80387a0: e13ffd17 ldw r4,-12(fp) + 80387a4: 80271780 call 8027178 + panic("prep_modules"); + } +#endif + USE_ARG(e); /* Avoid compiler warnings */ + +} /* end of netmain_init() */ + 80387a8: 0001883a nop + 80387ac: e6ffff04 addi sp,fp,-4 + 80387b0: dfc00217 ldw ra,8(sp) + 80387b4: df000117 ldw fp,4(sp) + 80387b8: dc000017 ldw r16,0(sp) + 80387bc: dec00304 addi sp,sp,12 + 80387c0: f800283a ret + +080387c4 : + * RETURNS: + */ + +void +icmp_port_du(PACKET p, struct destun * pdp) +{ + 80387c4: defffb04 addi sp,sp,-20 + 80387c8: dfc00415 stw ra,16(sp) + 80387cc: df000315 stw fp,12(sp) + 80387d0: dc000215 stw r16,8(sp) + 80387d4: df000304 addi fp,sp,12 + 80387d8: e13ffe15 stw r4,-8(fp) + 80387dc: e17ffd15 stw r5,-12(fp) + dprintf("got ICMP %s UNREACHABLE from %s\n", + icmpdu_types[(int)(pdp->dtype)], print_ipad(p->fhost) ); + 80387e0: e0bffd17 ldw r2,-12(fp) + 80387e4: 10800003 ldbu r2,0(r2) + 80387e8: 10803fcc andi r2,r2,255 + 80387ec: 1080201c xori r2,r2,128 + 80387f0: 10bfe004 addi r2,r2,-128 + dprintf("got ICMP %s UNREACHABLE from %s\n", + 80387f4: 100690ba slli r3,r2,2 + 80387f8: 00820174 movhi r2,2053 + 80387fc: 1885883a add r2,r3,r2 + 8038800: 14324a17 ldw r16,-14040(r2) + 8038804: e0bffe17 ldw r2,-8(fp) + 8038808: 10800717 ldw r2,28(r2) + 803880c: 1009883a mov r4,r2 + 8038810: 8026fbc0 call 8026fbc + 8038814: 100d883a mov r6,r2 + 8038818: 800b883a mov r5,r16 + 803881c: 01020174 movhi r4,2053 + 8038820: 212afd04 addi r4,r4,-21516 + 8038824: 8002c780 call 8002c78 + dprintf(prompt); + 8038828: d0a02c17 ldw r2,-32592(gp) + 803882c: 1009883a mov r4,r2 + 8038830: 8002c780 call 8002c78 +} + 8038834: 0001883a nop + 8038838: e6ffff04 addi sp,fp,-4 + 803883c: dfc00217 ldw ra,8(sp) + 8038840: df000117 ldw fp,4(sp) + 8038844: dc000017 ldw r16,0(sp) + 8038848: dec00304 addi sp,sp,12 + 803884c: f800283a ret + +08038850 : + * RETURNS: + */ + +int +station_state(void * pio) +{ + 8038850: defff904 addi sp,sp,-28 + 8038854: dfc00615 stw ra,24(sp) + 8038858: df000515 stw fp,20(sp) + 803885c: dc000415 stw r16,16(sp) + 8038860: df000504 addi fp,sp,20 + 8038864: e13ffc15 stw r4,-16(fp) + int i; + +#ifndef NO_INET_STACK + NET ifp; + + for (i = 0, ifp = (NET)netlist.q_head; ifp; ifp = ifp->n_next, i++) + 8038868: e03ffe15 stw zero,-8(fp) + 803886c: 008201b4 movhi r2,2054 + 8038870: 10b6a617 ldw r2,-9576(r2) + 8038874: e0bffd15 stw r2,-12(fp) + 8038878: 00002506 br 8038910 + { + ns_printf(pio, "iface %d-%s IP addr:%s ", + i, ifp->name, print_ipad(ifp->n_ipaddr) ); + 803887c: e0bffd17 ldw r2,-12(fp) + 8038880: 14000104 addi r16,r2,4 + ns_printf(pio, "iface %d-%s IP addr:%s ", + 8038884: e0bffd17 ldw r2,-12(fp) + 8038888: 10800a17 ldw r2,40(r2) + 803888c: 1009883a mov r4,r2 + 8038890: 8026fbc0 call 8026fbc + 8038894: d8800015 stw r2,0(sp) + 8038898: 800f883a mov r7,r16 + 803889c: e1bffe17 ldw r6,-8(fp) + 80388a0: 01420174 movhi r5,2053 + 80388a4: 296b0604 addi r5,r5,-21480 + 80388a8: e13ffc17 ldw r4,-16(fp) + 80388ac: 80273900 call 8027390 + ns_printf(pio, "subnet:%s ", print_ipad(ifp->snmask) ); + 80388b0: e0bffd17 ldw r2,-12(fp) + 80388b4: 10800c17 ldw r2,48(r2) + 80388b8: 1009883a mov r4,r2 + 80388bc: 8026fbc0 call 8026fbc + 80388c0: 100d883a mov r6,r2 + 80388c4: 01420174 movhi r5,2053 + 80388c8: 296b0d04 addi r5,r5,-21452 + 80388cc: e13ffc17 ldw r4,-16(fp) + 80388d0: 80273900 call 8027390 + ns_printf(pio, "gateway:%s\n", print_ipad(ifp->n_defgw) ); + 80388d4: e0bffd17 ldw r2,-12(fp) + 80388d8: 10800d17 ldw r2,52(r2) + 80388dc: 1009883a mov r4,r2 + 80388e0: 8026fbc0 call 8026fbc + 80388e4: 100d883a mov r6,r2 + 80388e8: 01420174 movhi r5,2053 + 80388ec: 296b1004 addi r5,r5,-21440 + 80388f0: e13ffc17 ldw r4,-16(fp) + 80388f4: 80273900 call 8027390 + for (i = 0, ifp = (NET)netlist.q_head; ifp; ifp = ifp->n_next, i++) + 80388f8: e0bffd17 ldw r2,-12(fp) + 80388fc: 10800017 ldw r2,0(r2) + 8038900: e0bffd15 stw r2,-12(fp) + 8038904: e0bffe17 ldw r2,-8(fp) + 8038908: 10800044 addi r2,r2,1 + 803890c: e0bffe15 stw r2,-8(fp) + 8038910: e0bffd17 ldw r2,-12(fp) + 8038914: 103fd91e bne r2,zero,803887c + } +#endif /* NO_INET_STACK */ + + ns_printf(pio, "current tick count %lu\n", cticks); + 8038918: d0a07d17 ldw r2,-32268(gp) + 803891c: 100d883a mov r6,r2 + 8038920: 01420174 movhi r5,2053 + 8038924: 296b1304 addi r5,r5,-21428 + 8038928: e13ffc17 ldw r4,-16(fp) + 803892c: 80273900 call 8027390 + + ns_printf(pio, "common delay parameter: %lu ticks (%lu ms).\n", pingdelay, (pingdelay * TIMEFOR1TICK)); + 8038930: d0e02d17 ldw r3,-32588(gp) + 8038934: d0a02d17 ldw r2,-32588(gp) + 8038938: 108002a4 muli r2,r2,10 + 803893c: 100f883a mov r7,r2 + 8038940: 180d883a mov r6,r3 + 8038944: 01420174 movhi r5,2053 + 8038948: 296b1904 addi r5,r5,-21404 + 803894c: e13ffc17 ldw r4,-16(fp) + 8038950: 80273900 call 8027390 + ns_printf(pio, "common host parameter: %s\n", print_ipad(activehost)); + 8038954: d0a08f17 ldw r2,-32196(gp) + 8038958: 1009883a mov r4,r2 + 803895c: 8026fbc0 call 8026fbc + 8038960: 100d883a mov r6,r2 + 8038964: 01420174 movhi r5,2053 + 8038968: 296b2504 addi r5,r5,-21356 + 803896c: e13ffc17 ldw r4,-16(fp) + 8038970: 80273900 call 8027390 + ns_printf(pio, "common length parameter: %d\n", deflength); + 8038974: d0a02e17 ldw r2,-32584(gp) + 8038978: 100d883a mov r6,r2 + 803897c: 01420174 movhi r5,2053 + 8038980: 296b2c04 addi r5,r5,-21328 + 8038984: e13ffc17 ldw r4,-16(fp) + 8038988: 80273900 call 8027390 +#ifdef USE_PPP + ns_printf(pio, "current dial-in user name is %s\n", pppcfg.username); + ns_printf(pio, "current dial-in password is %s\n", pppcfg.password); +#endif /* USE_PPP */ + + task_stats(pio); + 803898c: e13ffc17 ldw r4,-16(fp) + 8038990: 8038e5c0 call 8038e5c + + return 0; + 8038994: 0005883a mov r2,zero +} + 8038998: e6ffff04 addi sp,fp,-4 + 803899c: dfc00217 ldw ra,8(sp) + 80389a0: df000117 ldw fp,4(sp) + 80389a4: dc000017 ldw r16,0(sp) + 80389a8: dec00304 addi sp,sp,12 + 80389ac: f800283a ret + +080389b0 : + * RETURNS: + */ + +unsigned long +sysuptime() +{ + 80389b0: defffe04 addi sp,sp,-8 + 80389b4: dfc00115 stw ra,4(sp) + 80389b8: df000015 stw fp,0(sp) + 80389bc: d839883a mov fp,sp + return ((cticks/TPS)*100); /* 100ths of a sec since boot time */ + 80389c0: d0a07d17 ldw r2,-32268(gp) + 80389c4: 01401904 movi r5,100 + 80389c8: 1009883a mov r4,r2 + 80389cc: 800cff80 call 800cff8 <__udivsi3> + 80389d0: 10801924 muli r2,r2,100 +} + 80389d4: e037883a mov sp,fp + 80389d8: dfc00117 ldw ra,4(sp) + 80389dc: df000017 ldw fp,0(sp) + 80389e0: dec00204 addi sp,sp,8 + 80389e4: f800283a ret + +080389e8 : + +static int inside_pktdemux = 0; + +void +packet_check(void) +{ + 80389e8: defffe04 addi sp,sp,-8 + 80389ec: dfc00115 stw ra,4(sp) + 80389f0: df000015 stw fp,0(sp) + 80389f4: d839883a mov fp,sp + if(inside_pktdemux != 0) /* check re-entrancy flag */ + 80389f8: d0a09017 ldw r2,-32192(gp) + 80389fc: 1000081e bne r2,zero,8038a20 + return; /* do not re-enter pktdemux(), packet will wait... */ + inside_pktdemux++; /* set re-entrany flag */ + 8038a00: d0a09017 ldw r2,-32192(gp) + 8038a04: 10800044 addi r2,r2,1 + 8038a08: d0a09015 stw r2,-32192(gp) + pktdemux(); /* process low level packet input */ + 8038a0c: 80249c40 call 80249c4 + inside_pktdemux--; /* clear re-entrany flag */ + 8038a10: d0a09017 ldw r2,-32192(gp) + 8038a14: 10bfffc4 addi r2,r2,-1 + 8038a18: d0a09015 stw r2,-32192(gp) + 8038a1c: 00000106 br 8038a24 + return; /* do not re-enter pktdemux(), packet will wait... */ + 8038a20: 0001883a nop +} + 8038a24: e037883a mov sp,fp + 8038a28: dfc00117 ldw ra,4(sp) + 8038a2c: df000017 ldw fp,0(sp) + 8038a30: dec00204 addi sp,sp,8 + 8038a34: f800283a ret + +08038a38 : + * RETURNS: + */ + +int +mcastlist(struct in_multi * multi_ptr) +{ + 8038a38: defffe04 addi sp,sp,-8 + 8038a3c: df000115 stw fp,4(sp) + 8038a40: df000104 addi fp,sp,4 + 8038a44: e13fff15 stw r4,-4(fp) + USE_ARG(multi_ptr); + + return 0; + 8038a48: 0005883a mov r2,zero +} + 8038a4c: e037883a mov sp,fp + 8038a50: df000017 ldw fp,0(sp) + 8038a54: dec00104 addi sp,sp,4 + 8038a58: f800283a ret + +08038a5c : +#ifdef USE_MODEM +extern int prep_modem(void); +#endif /* USE_MODEM */ + +int prep_modules(void) +{ + 8038a5c: defffd04 addi sp,sp,-12 + 8038a60: dfc00215 stw ra,8(sp) + 8038a64: df000115 stw fp,4(sp) + 8038a68: df000104 addi fp,sp,4 +#ifdef IP_V6 + ip6_addr host; + int i; +#endif + +int e = 0; + 8038a6c: e03fff15 stw zero,-4(fp) + panic("prep_modules"); + } +#endif /* SMTP_ALERTS */ + +#ifdef VFS_FILES + e = prep_vfs(); + 8038a70: 80426940 call 8042694 + 8038a74: e0bfff15 stw r2,-4(fp) + if (e != 0) + 8038a78: e0bfff17 ldw r2,-4(fp) + 8038a7c: 10000626 beq r2,zero,8038a98 + { + dprintf("VFS Module prep failed\n"); + 8038a80: 01020174 movhi r4,2053 + 8038a84: 212b3404 addi r4,r4,-21296 + 8038a88: 8002d9c0 call 8002d9c + panic("prep_modules"); + 8038a8c: 01020174 movhi r4,2053 + 8038a90: 212b3a04 addi r4,r4,-21272 + 8038a94: 80271780 call 8027178 + { + dprintf("sslapp_init() failed\n"); + panic("prep_modules"); + } +#endif + return 0; + 8038a98: 0005883a mov r2,zero +} + 8038a9c: e037883a mov sp,fp + 8038aa0: dfc00117 ldw ra,4(sp) + 8038aa4: df000017 ldw fp,0(sp) + 8038aa8: dec00204 addi sp,sp,8 + 8038aac: f800283a ret + +08038ab0 : + * RETURNS: + */ + +void +inet_timer(void) +{ + 8038ab0: defffe04 addi sp,sp,-8 + 8038ab4: dfc00115 stw ra,4(sp) + 8038ab8: df000015 stw fp,0(sp) + 8038abc: d839883a mov fp,sp + if (ire_cticks < cticks) + ip_reasm_process_timer_tick (); +#endif + +#ifdef INCLUDE_TCP + tcp_tick(); /* run TCP timers */ + 8038ac0: 802b0500 call 802b050 +#endif + +#ifdef INICHE_TIMERS /* interval timers? */ + check_interval_timers(); + 8038ac4: 8038b280 call 8038b28 +#endif + +#if defined (IP_MULTICAST) && (defined (IGMP_V1) || defined (IGMP_V2)) + /* Call igmp timeout routine */ + if (igmp_cticks < cticks) /* Call igmp timeout routine 5 times per sec */ + 8038ac8: d0e06a17 ldw r3,-32344(gp) + 8038acc: d0a07d17 ldw r2,-32268(gp) + 8038ad0: 1880012e bgeu r3,r2,8038ad8 + igmp_fasttimo(); + 8038ad4: 80254ec0 call 80254ec +#endif + + + + /* Some timer routines only need calling once a second: */ + if ((nextppp < cticks) || /* next call to PPP is due */ + 8038ad8: d0e09117 ldw r3,-32188(gp) + 8038adc: d0a07d17 ldw r2,-32268(gp) + 8038ae0: 18800436 bltu r3,r2,8038af4 + (nextppp > (cticks+(10*TPS))) ) /* for when cticks wraps */ + 8038ae4: d0a07d17 ldw r2,-32268(gp) + 8038ae8: 10c0fa04 addi r3,r2,1000 + 8038aec: d0a09117 ldw r2,-32188(gp) + if ((nextppp < cticks) || /* next call to PPP is due */ + 8038af0: 1880072e bgeu r3,r2,8038b10 + { + nextppp = cticks + TPS; + 8038af4: d0a07d17 ldw r2,-32268(gp) + 8038af8: 10801904 addi r2,r2,100 + 8038afc: d0a09115 stw r2,-32188(gp) + + if (port_1s_callout != NULL) + 8038b00: d0a09217 ldw r2,-32184(gp) + 8038b04: 10000226 beq r2,zero,8038b10 + (*port_1s_callout)(); + 8038b08: d0a09217 ldw r2,-32184(gp) + 8038b0c: 103ee83a callr r2 +#endif +#ifdef IPSEC + IPSecTimer(); +#endif + } +} + 8038b10: 0001883a nop + 8038b14: e037883a mov sp,fp + 8038b18: dfc00117 ldw ra,4(sp) + 8038b1c: df000017 ldw fp,0(sp) + 8038b20: dec00204 addi sp,sp,8 + 8038b24: f800283a ret + +08038b28 : + +static int numtimers = 0; /* number of active timers */ + +static void +check_interval_timers(void) +{ + 8038b28: defffc04 addi sp,sp,-16 + 8038b2c: dfc00315 stw ra,12(sp) + 8038b30: df000215 stw fp,8(sp) + 8038b34: df000204 addi fp,sp,8 + int i; + int found = 0; /* number of valid timers found */ + 8038b38: e03ffe15 stw zero,-8(fp) + + /* if no timers, just return */ + if (numtimers > 0) + 8038b3c: d0a09317 ldw r2,-32180(gp) + 8038b40: 0080460e bge zero,r2,8038c5c + { + /* loop throught the timer list looking for active timers ready to fire */ + for (i = 0; i < NUM_INTIMERS; i++) + 8038b44: e03fff15 stw zero,-4(fp) + 8038b48: 00003f06 br 8038c48 + { + if (intimers[i].callback) /* is this timer active? */ + 8038b4c: e0bfff17 ldw r2,-4(fp) + 8038b50: 10c00524 muli r3,r2,20 + 8038b54: 008201b4 movhi r2,2054 + 8038b58: 1885883a add r2,r3,r2 + 8038b5c: 10b91c17 ldw r2,-7056(r2) + 8038b60: 10003626 beq r2,zero,8038c3c + { + if ((intimers[i].tmo < cticks) && (!intimers[i].inuse)) /* timer ready fire? */ + 8038b64: e0bfff17 ldw r2,-4(fp) + 8038b68: 10c00524 muli r3,r2,20 + 8038b6c: 008201b4 movhi r2,2054 + 8038b70: 1885883a add r2,r3,r2 + 8038b74: 10f91f17 ldw r3,-7044(r2) + 8038b78: d0a07d17 ldw r2,-32268(gp) + 8038b7c: 1880292e bgeu r3,r2,8038c24 + 8038b80: e0bfff17 ldw r2,-4(fp) + 8038b84: 10c00524 muli r3,r2,20 + 8038b88: 008201b4 movhi r2,2054 + 8038b8c: 1885883a add r2,r3,r2 + 8038b90: 10b92017 ldw r2,-7040(r2) + 8038b94: 1000231e bne r2,zero,8038c24 + { + intimers[i].tmo = intimers[i].interval + cticks; /* set next tmo */ + 8038b98: e0bfff17 ldw r2,-4(fp) + 8038b9c: 10c00524 muli r3,r2,20 + 8038ba0: 008201b4 movhi r2,2054 + 8038ba4: 1885883a add r2,r3,r2 + 8038ba8: 10f91e17 ldw r3,-7048(r2) + 8038bac: d0a07d17 ldw r2,-32268(gp) + 8038bb0: 1887883a add r3,r3,r2 + 8038bb4: e0bfff17 ldw r2,-4(fp) + 8038bb8: 11000524 muli r4,r2,20 + 8038bbc: 008201b4 movhi r2,2054 + 8038bc0: 2085883a add r2,r4,r2 + 8038bc4: 10f91f15 stw r3,-7044(r2) + intimers[i].inuse = TRUE; + 8038bc8: e0bfff17 ldw r2,-4(fp) + 8038bcc: 11000524 muli r4,r2,20 + 8038bd0: 00c00044 movi r3,1 + 8038bd4: 008201b4 movhi r2,2054 + 8038bd8: 2085883a add r2,r4,r2 + 8038bdc: 10f92015 stw r3,-7040(r2) + intimers[i].callback(intimers[i].parm); /* call user routine */ + 8038be0: e0bfff17 ldw r2,-4(fp) + 8038be4: 10c00524 muli r3,r2,20 + 8038be8: 008201b4 movhi r2,2054 + 8038bec: 1885883a add r2,r3,r2 + 8038bf0: 10f91c17 ldw r3,-7056(r2) + 8038bf4: e0bfff17 ldw r2,-4(fp) + 8038bf8: 11000524 muli r4,r2,20 + 8038bfc: 008201b4 movhi r2,2054 + 8038c00: 2085883a add r2,r4,r2 + 8038c04: 10b91d17 ldw r2,-7052(r2) + 8038c08: 1009883a mov r4,r2 + 8038c0c: 183ee83a callr r3 + intimers[i].inuse = FALSE; + 8038c10: e0bfff17 ldw r2,-4(fp) + 8038c14: 10c00524 muli r3,r2,20 + 8038c18: 008201b4 movhi r2,2054 + 8038c1c: 1885883a add r2,r3,r2 + 8038c20: 10392015 stw zero,-7040(r2) + } + /* If we've examined all the active timers, we're done */ + if (++found >= numtimers) + 8038c24: e0bffe17 ldw r2,-8(fp) + 8038c28: 10800044 addi r2,r2,1 + 8038c2c: e0bffe15 stw r2,-8(fp) + 8038c30: d0a09317 ldw r2,-32180(gp) + 8038c34: e0fffe17 ldw r3,-8(fp) + 8038c38: 1880070e bge r3,r2,8038c58 + for (i = 0; i < NUM_INTIMERS; i++) + 8038c3c: e0bfff17 ldw r2,-4(fp) + 8038c40: 10800044 addi r2,r2,1 + 8038c44: e0bfff15 stw r2,-4(fp) + 8038c48: e0bfff17 ldw r2,-4(fp) + 8038c4c: 10800150 cmplti r2,r2,5 + 8038c50: 103fbe1e bne r2,zero,8038b4c + break; + } + } + } +} + 8038c54: 00000106 br 8038c5c + break; + 8038c58: 0001883a nop +} + 8038c5c: 0001883a nop + 8038c60: e037883a mov sp,fp + 8038c64: dfc00117 ldw ra,4(sp) + 8038c68: df000017 ldw fp,0(sp) + 8038c6c: dec00204 addi sp,sp,8 + 8038c70: f800283a ret + +08038c74 : + * RETURNS: timer ID if OK, else if table is full. + */ + +long +in_timerset(void (*callback)(long), long msecs, long parm) +{ + 8038c74: defffa04 addi sp,sp,-24 + 8038c78: dfc00515 stw ra,20(sp) + 8038c7c: df000415 stw fp,16(sp) + 8038c80: df000404 addi fp,sp,16 + 8038c84: e13ffe15 stw r4,-8(fp) + 8038c88: e17ffd15 stw r5,-12(fp) + 8038c8c: e1bffc15 stw r6,-16(fp) + int i; + + for(i = 0; i < NUM_INTIMERS; i++) + 8038c90: e03fff15 stw zero,-4(fp) + 8038c94: 00003906 br 8038d7c + { + if(intimers[i].callback == NULL) + 8038c98: e0bfff17 ldw r2,-4(fp) + 8038c9c: 10c00524 muli r3,r2,20 + 8038ca0: 008201b4 movhi r2,2054 + 8038ca4: 1885883a add r2,r3,r2 + 8038ca8: 10b91c17 ldw r2,-7056(r2) + 8038cac: 1000301e bne r2,zero,8038d70 + { + /* found empty table entry, set up new timer */ + intimers[i].callback = callback; + 8038cb0: e0bfff17 ldw r2,-4(fp) + 8038cb4: 11000524 muli r4,r2,20 + 8038cb8: e0fffe17 ldw r3,-8(fp) + 8038cbc: 008201b4 movhi r2,2054 + 8038cc0: 2085883a add r2,r4,r2 + 8038cc4: 10f91c15 stw r3,-7056(r2) + intimers[i].parm = parm; + 8038cc8: e0bfff17 ldw r2,-4(fp) + 8038ccc: 11000524 muli r4,r2,20 + 8038cd0: e0fffc17 ldw r3,-16(fp) + 8038cd4: 008201b4 movhi r2,2054 + 8038cd8: 2085883a add r2,r4,r2 + 8038cdc: 10f91d15 stw r3,-7052(r2) + /* set interval, in TPS (cticks) units */ + intimers[i].interval = (msecs * TPS)/1000; + 8038ce0: e0bffd17 ldw r2,-12(fp) + 8038ce4: 01400284 movi r5,10 + 8038ce8: 1009883a mov r4,r2 + 8038cec: 800cf000 call 800cf00 <__divsi3> + 8038cf0: 1009883a mov r4,r2 + 8038cf4: e0bfff17 ldw r2,-4(fp) + 8038cf8: 10c00524 muli r3,r2,20 + 8038cfc: 008201b4 movhi r2,2054 + 8038d00: 1885883a add r2,r3,r2 + 8038d04: 11391e15 stw r4,-7048(r2) + intimers[i].tmo = intimers[i].interval + cticks; /* first tmo */ + 8038d08: e0bfff17 ldw r2,-4(fp) + 8038d0c: 10c00524 muli r3,r2,20 + 8038d10: 008201b4 movhi r2,2054 + 8038d14: 1885883a add r2,r3,r2 + 8038d18: 10f91e17 ldw r3,-7048(r2) + 8038d1c: d0a07d17 ldw r2,-32268(gp) + 8038d20: 1887883a add r3,r3,r2 + 8038d24: e0bfff17 ldw r2,-4(fp) + 8038d28: 11000524 muli r4,r2,20 + 8038d2c: 008201b4 movhi r2,2054 + 8038d30: 2085883a add r2,r4,r2 + 8038d34: 10f91f15 stw r3,-7044(r2) + intimers[i].inuse = FALSE; + 8038d38: e0bfff17 ldw r2,-4(fp) + 8038d3c: 10c00524 muli r3,r2,20 + 8038d40: 008201b4 movhi r2,2054 + 8038d44: 1885883a add r2,r3,r2 + 8038d48: 10392015 stw zero,-7040(r2) + numtimers++; + 8038d4c: d0a09317 ldw r2,-32180(gp) + 8038d50: 10800044 addi r2,r2,1 + 8038d54: d0a09315 stw r2,-32180(gp) + return (long)&intimers[i]; + 8038d58: e0bfff17 ldw r2,-4(fp) + 8038d5c: 10c00524 muli r3,r2,20 + 8038d60: 008201b4 movhi r2,2054 + 8038d64: 10b91c04 addi r2,r2,-7056 + 8038d68: 1885883a add r2,r3,r2 + 8038d6c: 00000706 br 8038d8c + for(i = 0; i < NUM_INTIMERS; i++) + 8038d70: e0bfff17 ldw r2,-4(fp) + 8038d74: 10800044 addi r2,r2,1 + 8038d78: e0bfff15 stw r2,-4(fp) + 8038d7c: e0bfff17 ldw r2,-4(fp) + 8038d80: 10800150 cmplti r2,r2,5 + 8038d84: 103fc41e bne r2,zero,8038c98 + } + } + return 0; + 8038d88: 0005883a mov r2,zero +} + 8038d8c: e037883a mov sp,fp + 8038d90: dfc00117 ldw ra,4(sp) + 8038d94: df000017 ldw fp,0(sp) + 8038d98: dec00204 addi sp,sp,8 + 8038d9c: f800283a ret + +08038da0 : + */ + + +int +in_timerkill(long timer) +{ + 8038da0: defffc04 addi sp,sp,-16 + 8038da4: dfc00315 stw ra,12(sp) + 8038da8: df000215 stw fp,8(sp) + 8038dac: df000204 addi fp,sp,8 + 8038db0: e13ffe15 stw r4,-8(fp) + int i; + + for(i = 0; i < NUM_INTIMERS; i++) + 8038db4: e03fff15 stw zero,-4(fp) + 8038db8: 00001506 br 8038e10 + { + if(timer == (long)&intimers[i]) + 8038dbc: e0bfff17 ldw r2,-4(fp) + 8038dc0: 10c00524 muli r3,r2,20 + 8038dc4: 008201b4 movhi r2,2054 + 8038dc8: 10b91c04 addi r2,r2,-7056 + 8038dcc: 1885883a add r2,r3,r2 + 8038dd0: 1007883a mov r3,r2 + 8038dd4: e0bffe17 ldw r2,-8(fp) + 8038dd8: 10c00a1e bne r2,r3,8038e04 + { + intimers[i].callback = NULL; + 8038ddc: e0bfff17 ldw r2,-4(fp) + 8038de0: 10c00524 muli r3,r2,20 + 8038de4: 008201b4 movhi r2,2054 + 8038de8: 1885883a add r2,r3,r2 + 8038dec: 10391c15 stw zero,-7056(r2) + numtimers--; + 8038df0: d0a09317 ldw r2,-32180(gp) + 8038df4: 10bfffc4 addi r2,r2,-1 + 8038df8: d0a09315 stw r2,-32180(gp) + return 0; /* OK return */ + 8038dfc: 0005883a mov r2,zero + 8038e00: 00000806 br 8038e24 + for(i = 0; i < NUM_INTIMERS; i++) + 8038e04: e0bfff17 ldw r2,-4(fp) + 8038e08: 10800044 addi r2,r2,1 + 8038e0c: e0bfff15 stw r2,-4(fp) + 8038e10: e0bfff17 ldw r2,-4(fp) + 8038e14: 10800150 cmplti r2,r2,5 + 8038e18: 103fe81e bne r2,zero,8038dbc + } + } + dtrap(); /* timer to kill not found */ + 8038e1c: 8028cd40 call 8028cd4 + return ENP_PARAM; + 8038e20: 00bffd84 movi r2,-10 +} + 8038e24: e037883a mov sp,fp + 8038e28: dfc00117 ldw ra,4(sp) + 8038e2c: df000017 ldw fp,0(sp) + 8038e30: dec00204 addi sp,sp,8 + 8038e34: f800283a ret + +08038e38 : +#endif +/* per-application thread definitions */ + +int +create_apptasks(void) +{ + 8038e38: defffe04 addi sp,sp,-8 + 8038e3c: df000115 stw fp,4(sp) + 8038e40: df000104 addi fp,sp,4 +int e = 0; + 8038e44: e03fff15 stw zero,-4(fp) +#endif +/* + * Altera Niche Stack Nios port modification: + * return error code, if any + */ + return e; + 8038e48: e0bfff17 ldw r2,-4(fp) +} + 8038e4c: e037883a mov sp,fp + 8038e50: df000017 ldw fp,0(sp) + 8038e54: dec00104 addi sp,sp,4 + 8038e58: f800283a ret + +08038e5c : + */ + + +void +task_stats(void * pio) +{ + 8038e5c: defffd04 addi sp,sp,-12 + 8038e60: dfc00215 stw ra,8(sp) + 8038e64: df000115 stw fp,4(sp) + 8038e68: df000104 addi fp,sp,4 + 8038e6c: e13fff15 stw r4,-4(fp) + ns_printf(pio, "Task wakeups:"); + 8038e70: 01420174 movhi r5,2053 + 8038e74: 296b3e04 addi r5,r5,-21256 + 8038e78: e13fff17 ldw r4,-4(fp) + 8038e7c: 80273900 call 8027390 + +#ifndef NO_INET_STACK + ns_printf(pio, "netmain: %lu\n", netmain_wakes); + 8038e80: d0a06d17 ldw r2,-32332(gp) + 8038e84: 100d883a mov r6,r2 + 8038e88: 01420174 movhi r5,2053 + 8038e8c: 296b4204 addi r5,r5,-21240 + 8038e90: e13fff17 ldw r4,-4(fp) + 8038e94: 80273900 call 8027390 +#endif +#ifndef NO_INET_TICK + ns_printf(pio, "nettick: %lu\n", nettick_wakes); + 8038e98: d0a06e17 ldw r2,-32328(gp) + 8038e9c: 100d883a mov r6,r2 + 8038ea0: 01420174 movhi r5,2053 + 8038ea4: 296b4604 addi r5,r5,-21224 + 8038ea8: e13fff17 ldw r4,-4(fp) + 8038eac: 80273900 call 8027390 + ns_printf(pio, "browtask: %lu ", browtask_wakes); +#endif +#ifdef INCLUDE_SSLAPP + ns_printf(pio, "INCLUDE_SSLAPP: %lu ", sslapp_wakes); +#endif + ns_printf(pio, "\n"); + 8038eb0: 01420174 movhi r5,2053 + 8038eb4: 296b4a04 addi r5,r5,-21208 + 8038eb8: e13fff17 ldw r4,-4(fp) + 8038ebc: 80273900 call 8027390 +} + 8038ec0: 0001883a nop + 8038ec4: e037883a mov sp,fp + 8038ec8: dfc00117 ldw ra,4(sp) + 8038ecc: df000017 ldw fp,0(sp) + 8038ed0: dec00204 addi sp,sp,8 + 8038ed4: f800283a ret + +08038ed8 : + * (for files and device drivers) or calls the InterNiche bsd_ioctl for + * sockets. + */ + +int fcntl (int file, int cmd, ...) +{ + 8038ed8: defff804 addi sp,sp,-32 + 8038edc: dfc00515 stw ra,20(sp) + 8038ee0: df000415 stw fp,16(sp) + 8038ee4: df000404 addi fp,sp,16 + 8038ee8: e13ffd15 stw r4,-12(fp) + 8038eec: e17ffc15 stw r5,-16(fp) + 8038ef0: e1800215 stw r6,8(fp) + 8038ef4: e1c00315 stw r7,12(fp) + long flags; + va_list argp; + + if (file < ALT_MAX_FD) + 8038ef8: e0bffd17 ldw r2,-12(fp) + 8038efc: 10800408 cmpgei r2,r2,16 + 8038f00: 10000c1e bne r2,zero,8038f34 + { + va_start(argp, cmd); + 8038f04: e0800204 addi r2,fp,8 + 8038f08: e0bffe15 stw r2,-8(fp) + flags = va_arg(argp, long); + 8038f0c: e0bffe17 ldw r2,-8(fp) + 8038f10: 10c00104 addi r3,r2,4 + 8038f14: e0fffe15 stw r3,-8(fp) + 8038f18: 10800017 ldw r2,0(r2) + 8038f1c: e0bfff15 stw r2,-4(fp) + va_end(argp); + return alt_fcntl(file, cmd, flags); + 8038f20: e1bfff17 ldw r6,-4(fp) + 8038f24: e17ffc17 ldw r5,-16(fp) + 8038f28: e13ffd17 ldw r4,-12(fp) + 8038f2c: 80426f40 call 80426f4 + 8038f30: 00000c06 br 8038f64 + } + else + { + va_start(argp, cmd); + 8038f34: e0800204 addi r2,fp,8 + 8038f38: e0bffe15 stw r2,-8(fp) + flags = va_arg(argp, long); + 8038f3c: e0bffe17 ldw r2,-8(fp) + 8038f40: 10c00104 addi r3,r2,4 + 8038f44: e0fffe15 stw r3,-8(fp) + 8038f48: 10800017 ldw r2,0(r2) + 8038f4c: e0bfff15 stw r2,-4(fp) + va_end(argp); + return bsd_ioctl(file, cmd, flags); + 8038f50: e0bffc17 ldw r2,-16(fp) + 8038f54: e1bfff17 ldw r6,-4(fp) + 8038f58: 100b883a mov r5,r2 + 8038f5c: e13ffd17 ldw r4,-12(fp) + 8038f60: 802680c0 call 802680c + } +} + 8038f64: e037883a mov sp,fp + 8038f68: dfc00117 ldw ra,4(sp) + 8038f6c: df000017 ldw fp,0(sp) + 8038f70: dec00404 addi sp,sp,16 + 8038f74: f800283a ret + +08038f78 : +}; +#endif /* USER_PING_TSTAMP */ + +int +icmprcv(PACKET p) /* the incoming packet */ +{ + 8038f78: deffef04 addi sp,sp,-68 + 8038f7c: dfc01015 stw ra,64(sp) + 8038f80: df000f15 stw fp,60(sp) + 8038f84: dc400e15 stw r17,56(sp) + 8038f88: dc000d15 stw r16,52(sp) + 8038f8c: df000f04 addi fp,sp,60 + 8038f90: e13ff315 stw r4,-52(fp) + unsigned short xsum; +#ifdef FULL_ICMP + struct redirect * rd; + struct destun * pdp; +#endif /* FULL_ICMP */ + char sav_ch = 0; + 8038f94: e03ffdc5 stb zero,-9(fp) + int i; + + icmp_mib.icmpInMsgs++; /* received one more icmp */ + 8038f98: 008201b4 movhi r2,2054 + 8038f9c: 10b93517 ldw r2,-6956(r2) + 8038fa0: 10c00044 addi r3,r2,1 + 8038fa4: 008201b4 movhi r2,2054 + 8038fa8: 10f93515 stw r3,-6956(r2) + + pip = ip_head(p); /* find IP header */ + 8038fac: e0bff317 ldw r2,-52(fp) + 8038fb0: 10800317 ldw r2,12(r2) + 8038fb4: e0bffc15 stw r2,-16(fp) + len = p->nb_plen - (ip_hlen(pip)); /* strip IP header length */ + 8038fb8: e0bff317 ldw r2,-52(fp) + 8038fbc: 10c00417 ldw r3,16(r2) + 8038fc0: e0bffc17 ldw r2,-16(fp) + 8038fc4: 10800003 ldbu r2,0(r2) + 8038fc8: 10803fcc andi r2,r2,255 + 8038fcc: 100490ba slli r2,r2,2 + 8038fd0: 10800f0c andi r2,r2,60 + 8038fd4: 1885c83a sub r2,r3,r2 + 8038fd8: e0bffb15 stw r2,-20(fp) + host = p->fhost; /* filled in by IP layer */ + 8038fdc: e0bff317 ldw r2,-52(fp) + 8038fe0: 10800717 ldw r2,28(r2) + 8038fe4: e0bffa15 stw r2,-24(fp) + +#ifdef NPDEBUG + if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE)) + 8038fe8: d0a06617 ldw r2,-32360(gp) + 8038fec: 1081000c andi r2,r2,1024 + 8038ff0: 10001526 beq r2,zero,8039048 + 8038ff4: d0a06617 ldw r2,-32360(gp) + 8038ff8: 1080800c andi r2,r2,512 + 8038ffc: 10001226 beq r2,zero,8039048 + dprintf("ICMP: p[%u] from %u.%u.%u.%u\n", len, PUSH_IPADDR(host)); + 8039000: e0bffa17 ldw r2,-24(fp) + 8039004: 11003fcc andi r4,r2,255 + 8039008: e0bffa17 ldw r2,-24(fp) + 803900c: 1004d23a srli r2,r2,8 + 8039010: 11403fcc andi r5,r2,255 + 8039014: e0bffa17 ldw r2,-24(fp) + 8039018: 1004d43a srli r2,r2,16 + 803901c: 10803fcc andi r2,r2,255 + 8039020: e0fffa17 ldw r3,-24(fp) + 8039024: 1806d63a srli r3,r3,24 + 8039028: d8c00115 stw r3,4(sp) + 803902c: d8800015 stw r2,0(sp) + 8039030: 280f883a mov r7,r5 + 8039034: 200d883a mov r6,r4 + 8039038: e17ffb17 ldw r5,-20(fp) + 803903c: 01020174 movhi r4,2053 + 8039040: 212b4b04 addi r4,r4,-21204 + 8039044: 8002c780 call 8002c78 +#endif + + e = (struct ping *)ip_data(pip); /* finally, extract ICMP header */ + 8039048: e0bffc17 ldw r2,-16(fp) + 803904c: 10800003 ldbu r2,0(r2) + 8039050: 10803fcc andi r2,r2,255 + 8039054: 100490ba slli r2,r2,2 + 8039058: 10800f0c andi r2,r2,60 + 803905c: e0fffc17 ldw r3,-16(fp) + 8039060: 1885883a add r2,r3,r2 + 8039064: e0bff915 stw r2,-28(fp) + + osum = e->pchksum; + 8039068: e0bff917 ldw r2,-28(fp) + 803906c: 1080008b ldhu r2,2(r2) + 8039070: e0bff88d sth r2,-30(fp) + e->pchksum = 0; + 8039074: e0bff917 ldw r2,-28(fp) + 8039078: 1000008d sth zero,2(r2) + + if (len&1) + 803907c: e0bffb17 ldw r2,-20(fp) + 8039080: 1080004c andi r2,r2,1 + 8039084: 10000926 beq r2,zero,80390ac + { + sav_ch = *(((char *) e) + len); + 8039088: e0fff917 ldw r3,-28(fp) + 803908c: e0bffb17 ldw r2,-20(fp) + 8039090: 1885883a add r2,r3,r2 + 8039094: 10800003 ldbu r2,0(r2) + 8039098: e0bffdc5 stb r2,-9(fp) + ((char *)e)[len] = 0; + 803909c: e0fff917 ldw r3,-28(fp) + 80390a0: e0bffb17 ldw r2,-20(fp) + 80390a4: 1885883a add r2,r3,r2 + 80390a8: 10000005 stb zero,0(r2) + } + + xsum = ~cksum(e, (len+1)>>1); + 80390ac: e0bffb17 ldw r2,-20(fp) + 80390b0: 10800044 addi r2,r2,1 + 80390b4: 1004d07a srli r2,r2,1 + 80390b8: 100b883a mov r5,r2 + 80390bc: e13ff917 ldw r4,-28(fp) + 80390c0: 8026d7c0 call 8026d7c + 80390c4: 0084303a nor r2,zero,r2 + 80390c8: e0bff80d sth r2,-32(fp) + if (len&1) *(((char *) e) + len) = sav_ch; + 80390cc: e0bffb17 ldw r2,-20(fp) + 80390d0: 1080004c andi r2,r2,1 + 80390d4: 10000526 beq r2,zero,80390ec + 80390d8: e0fff917 ldw r3,-28(fp) + 80390dc: e0bffb17 ldw r2,-20(fp) + 80390e0: 1885883a add r2,r3,r2 + 80390e4: e0fffdc3 ldbu r3,-9(fp) + 80390e8: 10c00005 stb r3,0(r2) + if (xsum != osum) + 80390ec: e0fff80b ldhu r3,-32(fp) + 80390f0: e0bff88b ldhu r2,-30(fp) + 80390f4: 18802226 beq r3,r2,8039180 + { + e->pchksum = osum; + 80390f8: e0bff917 ldw r2,-28(fp) + 80390fc: e0fff88b ldhu r3,-30(fp) + 8039100: 10c0008d sth r3,2(r2) +#ifdef NPDEBUG + if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE)) + 8039104: d0a06617 ldw r2,-32360(gp) + 8039108: 1081000c andi r2,r2,1024 + 803910c: 10000f26 beq r2,zero,803914c + 8039110: d0a06617 ldw r2,-32360(gp) + 8039114: 1080800c andi r2,r2,512 + 8039118: 10000c26 beq r2,zero,803914c + { + dprintf("ICMP: Bad xsum %04x should have been %04x\n", + 803911c: e0bff88b ldhu r2,-30(fp) + 8039120: e0fff80b ldhu r3,-32(fp) + 8039124: 180d883a mov r6,r3 + 8039128: 100b883a mov r5,r2 + 803912c: 01020174 movhi r4,2053 + 8039130: 212b5304 addi r4,r4,-21172 + 8039134: 8002c780 call 8002c78 + osum, xsum); + if (NDEBUG & DUMP) ip_dump(p); + 8039138: d0a06617 ldw r2,-32360(gp) + 803913c: 1080008c andi r2,r2,2 + 8039140: 10000226 beq r2,zero,803914c + 8039144: e13ff317 ldw r4,-52(fp) + 8039148: 803b0cc0 call 803b0cc + } +#endif + icmp_mib.icmpInErrors++; + 803914c: 008201b4 movhi r2,2054 + 8039150: 10b93617 ldw r2,-6952(r2) + 8039154: 10c00044 addi r3,r2,1 + 8039158: 008201b4 movhi r2,2054 + 803915c: 10f93615 stw r3,-6952(r2) + LOCK_NET_RESOURCE(FREEQ_RESID); + 8039160: 01000084 movi r4,2 + 8039164: 8028f380 call 8028f38 + pk_free(p); + 8039168: e13ff317 ldw r4,-52(fp) + 803916c: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8039170: 01000084 movi r4,2 + 8039174: 8028ff40 call 8028ff4 + return ENP_BAD_HEADER; + 8039178: 00bff804 movi r2,-32 + 803917c: 00022e06 br 8039a38 + } + + e->pchksum = osum; + 8039180: e0bff917 ldw r2,-28(fp) + 8039184: e0fff88b ldhu r3,-30(fp) + 8039188: 10c0008d sth r3,2(r2) + + switch (e->ptype) + 803918c: e0bff917 ldw r2,-28(fp) + 8039190: 10800003 ldbu r2,0(r2) + 8039194: 10803fcc andi r2,r2,255 + 8039198: 1080201c xori r2,r2,128 + 803919c: 10bfe004 addi r2,r2,-128 + 80391a0: 10c00428 cmpgeui r3,r2,16 + 80391a4: 18020a1e bne r3,zero,80399d0 + 80391a8: 100690ba slli r3,r2,2 + 80391ac: 00820134 movhi r2,2052 + 80391b0: 1885883a add r2,r3,r2 + 80391b4: 10a46f17 ldw r2,-28228(r2) + 80391b8: 1000683a jmp r2 + 80391bc: 08039454 ori zero,at,3665 + 80391c0: 080399d0 cmplti zero,at,3687 + 80391c4: 080399d0 cmplti zero,at,3687 + 80391c8: 08039474 orhi zero,at,3665 + 80391cc: 08039568 cmpgeui zero,at,3669 + 80391d0: 080395fc xorhi zero,at,3671 + 80391d4: 080399d0 cmplti zero,at,3687 + 80391d8: 080399d0 cmplti zero,at,3687 + 80391dc: 080391fc xorhi zero,at,3655 + 80391e0: 080399d0 cmplti zero,at,3687 + 80391e4: 080399d0 cmplti zero,at,3687 + 80391e8: 08039728 cmpgeui zero,at,3676 + 80391ec: 08039828 cmpgeui zero,at,3680 + 80391f0: 08039884 addi zero,at,3682 + 80391f4: 080399d0 cmplti zero,at,3687 + 80391f8: 0803999c xori zero,at,3686 + { + case ECHOREQ: /* got ping request, send reply */ + icmp_mib.icmpInEchos++; + 80391fc: 008201b4 movhi r2,2054 + 8039200: 10b93c17 ldw r2,-6928(r2) + 8039204: 10c00044 addi r3,r2,1 + 8039208: 008201b4 movhi r2,2054 + 803920c: 10f93c15 stw r3,-6928(r2) +#ifdef NPDEBUG + if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE)) + 8039210: d0a06617 ldw r2,-32360(gp) + 8039214: 1081000c andi r2,r2,1024 + 8039218: 10001426 beq r2,zero,803926c + 803921c: d0a06617 ldw r2,-32360(gp) + 8039220: 1080800c andi r2,r2,512 + 8039224: 10001126 beq r2,zero,803926c + dprintf("ICMP: echo reply to %u.%u.%u.%u\n", PUSH_IPADDR(host)); + 8039228: e0bffa17 ldw r2,-24(fp) + 803922c: 10c03fcc andi r3,r2,255 + 8039230: e0bffa17 ldw r2,-24(fp) + 8039234: 1004d23a srli r2,r2,8 + 8039238: 11003fcc andi r4,r2,255 + 803923c: e0bffa17 ldw r2,-24(fp) + 8039240: 1004d43a srli r2,r2,16 + 8039244: 11403fcc andi r5,r2,255 + 8039248: e0bffa17 ldw r2,-24(fp) + 803924c: 1004d63a srli r2,r2,24 + 8039250: d8800015 stw r2,0(sp) + 8039254: 280f883a mov r7,r5 + 8039258: 200d883a mov r6,r4 + 803925c: 180b883a mov r5,r3 + 8039260: 01020174 movhi r4,2053 + 8039264: 212b5e04 addi r4,r4,-21128 + 8039268: 8002c780 call 8002c78 +#endif + e->ptype = ECHOREP; + 803926c: e0bff917 ldw r2,-28(fp) + 8039270: 10000005 stb zero,0(r2) + e->pchksum = 0; + 8039274: e0bff917 ldw r2,-28(fp) + 8039278: 1000008d sth zero,2(r2) + if (len&1) /* pad odd length packets for checksum routine */ + 803927c: e0bffb17 ldw r2,-20(fp) + 8039280: 1080004c andi r2,r2,1 + 8039284: 10000926 beq r2,zero,80392ac + { + sav_ch = *(((char *) e) + len); + 8039288: e0fff917 ldw r3,-28(fp) + 803928c: e0bffb17 ldw r2,-20(fp) + 8039290: 1885883a add r2,r3,r2 + 8039294: 10800003 ldbu r2,0(r2) + 8039298: e0bffdc5 stb r2,-9(fp) + ((char *)e)[len] = 0; + 803929c: e0fff917 ldw r3,-28(fp) + 80392a0: e0bffb17 ldw r2,-20(fp) + 80392a4: 1885883a add r2,r3,r2 + 80392a8: 10000005 stb zero,0(r2) + } + + e->pchksum = ~cksum(e, (len+1)>>1); + 80392ac: e0bffb17 ldw r2,-20(fp) + 80392b0: 10800044 addi r2,r2,1 + 80392b4: 1004d07a srli r2,r2,1 + 80392b8: 100b883a mov r5,r2 + 80392bc: e13ff917 ldw r4,-28(fp) + 80392c0: 8026d7c0 call 8026d7c + 80392c4: 0084303a nor r2,zero,r2 + 80392c8: 1007883a mov r3,r2 + 80392cc: e0bff917 ldw r2,-28(fp) + 80392d0: 10c0008d sth r3,2(r2) + if (len&1) *(((char *) e) + len) = sav_ch; + 80392d4: e0bffb17 ldw r2,-20(fp) + 80392d8: 1080004c andi r2,r2,1 + 80392dc: 10000526 beq r2,zero,80392f4 + 80392e0: e0fff917 ldw r3,-28(fp) + 80392e4: e0bffb17 ldw r2,-20(fp) + 80392e8: 1885883a add r2,r3,r2 + 80392ec: e0fffdc3 ldbu r3,-9(fp) + 80392f0: 10c00005 stb r3,0(r2) + /* check to see if the destination is the IPv4 broadcast address, + * or if the destination is a multicast group address, or if the + * destination address is the subnet-directed broadcast + */ + if ((pip->ip_dest == 0xffffffff) || + 80392f4: e0bffc17 ldw r2,-16(fp) + 80392f8: 10800417 ldw r2,16(r2) + 80392fc: 10bfffe0 cmpeqi r2,r2,-1 + 8039300: 10001f1e bne r2,zero,8039380 +#ifdef IP_MULTICAST + (IN_MULTICAST(ntohl(pip->ip_dest))) || + 8039304: e0bffc17 ldw r2,-16(fp) + 8039308: 10800417 ldw r2,16(r2) + 803930c: 1006d63a srli r3,r2,24 + 8039310: e0bffc17 ldw r2,-16(fp) + 8039314: 10800417 ldw r2,16(r2) + 8039318: 1004d23a srli r2,r2,8 + 803931c: 10bfc00c andi r2,r2,65280 + 8039320: 1886b03a or r3,r3,r2 + 8039324: e0bffc17 ldw r2,-16(fp) + 8039328: 10800417 ldw r2,16(r2) + 803932c: 1004923a slli r2,r2,8 + 8039330: 10803fec andhi r2,r2,255 + 8039334: 1886b03a or r3,r3,r2 + 8039338: e0bffc17 ldw r2,-16(fp) + 803933c: 10800417 ldw r2,16(r2) + 8039340: 1004963a slli r2,r2,24 + 8039344: 1884b03a or r2,r3,r2 + 8039348: 10fc002c andhi r3,r2,61440 + if ((pip->ip_dest == 0xffffffff) || + 803934c: 00b80034 movhi r2,57344 + 8039350: 18800b26 beq r3,r2,8039380 +#endif + (pip->ip_dest == (p->net->n_ipaddr | (~(p->net->snmask))))) + 8039354: e0bffc17 ldw r2,-16(fp) + 8039358: 10c00417 ldw r3,16(r2) + 803935c: e0bff317 ldw r2,-52(fp) + 8039360: 10800617 ldw r2,24(r2) + 8039364: 11000a17 ldw r4,40(r2) + 8039368: e0bff317 ldw r2,-52(fp) + 803936c: 10800617 ldw r2,24(r2) + 8039370: 10800c17 ldw r2,48(r2) + 8039374: 0084303a nor r2,zero,r2 + 8039378: 2084b03a or r2,r4,r2 + (IN_MULTICAST(ntohl(pip->ip_dest))) || + 803937c: 1880061e bne r3,r2,8039398 + { + pip->ip_src = p->net->n_ipaddr; + 8039380: e0bff317 ldw r2,-52(fp) + 8039384: 10800617 ldw r2,24(r2) + 8039388: 10c00a17 ldw r3,40(r2) + 803938c: e0bffc17 ldw r2,-16(fp) + 8039390: 10c00315 stw r3,12(r2) + 8039394: 00000406 br 80393a8 + } + else pip->ip_src = pip->ip_dest; + 8039398: e0bffc17 ldw r2,-16(fp) + 803939c: 10c00417 ldw r3,16(r2) + 80393a0: e0bffc17 ldw r2,-16(fp) + 80393a4: 10c00315 stw r3,12(r2) + + pip->ip_dest = host; + 80393a8: e0bffc17 ldw r2,-16(fp) + 80393ac: e0fffa17 ldw r3,-24(fp) + 80393b0: 10c00415 stw r3,16(r2) + icmp_mib.icmpOutEchoReps++; + 80393b4: 008201b4 movhi r2,2054 + 80393b8: 10b94a17 ldw r2,-6872(r2) + 80393bc: 10c00044 addi r3,r2,1 + 80393c0: 008201b4 movhi r2,2054 + 80393c4: 10f94a15 stw r3,-6872(r2) + icmp_mib.icmpOutMsgs++; + 80393c8: 008201b4 movhi r2,2054 + 80393cc: 10b94217 ldw r2,-6904(r2) + 80393d0: 10c00044 addi r3,r2,1 + 80393d4: 008201b4 movhi r2,2054 + 80393d8: 10f94215 stw r3,-6904(r2) + p->fhost = host; + 80393dc: e0bff317 ldw r2,-52(fp) + 80393e0: e0fffa17 ldw r3,-24(fp) + 80393e4: 10c00715 stw r3,28(r2) + p->nb_prot += ip_hlen(pip); /* move pointer past IP to ICMP */ + 80393e8: e0bff317 ldw r2,-52(fp) + 80393ec: 10c00317 ldw r3,12(r2) + 80393f0: e0bffc17 ldw r2,-16(fp) + 80393f4: 10800003 ldbu r2,0(r2) + 80393f8: 10803fcc andi r2,r2,255 + 80393fc: 100490ba slli r2,r2,2 + 8039400: 10800f0c andi r2,r2,60 + 8039404: 1887883a add r3,r3,r2 + 8039408: e0bff317 ldw r2,-52(fp) + 803940c: 10c00315 stw r3,12(r2) + p->nb_plen = len; + 8039410: e0bff317 ldw r2,-52(fp) + 8039414: e0fffb17 ldw r3,-20(fp) + 8039418: 10c00415 stw r3,16(r2) + + i = ip_write(ICMP_PROT, p); + 803941c: e17ff317 ldw r5,-52(fp) + 8039420: 01000044 movi r4,1 + 8039424: 803a9e80 call 803a9e8 + 8039428: e0bff715 stw r2,-36(fp) + if (i < 0) + 803942c: e0bff717 ldw r2,-36(fp) + 8039430: 1000060e bge r2,zero,803944c + { +#ifdef NPDEBUG + if (NDEBUG & (UPCTRACE)) + 8039434: d0a06617 ldw r2,-32360(gp) + 8039438: 1081000c andi r2,r2,1024 + 803943c: 10000326 beq r2,zero,803944c + dprintf("icmp: reply failed\n"); + 8039440: 01020174 movhi r4,2053 + 8039444: 212b6704 addi r4,r4,-21092 + 8039448: 8002d9c0 call 8002d9c +#endif + } + /* reused p will be freed by net->xxx_send() */ + return 0; + 803944c: 0005883a mov r2,zero + 8039450: 00017906 br 8039a38 + case ECHOREP: + icmp_mib.icmpInEchoReps++; + 8039454: 008201b4 movhi r2,2054 + 8039458: 10b93d17 ldw r2,-6924(r2) + 803945c: 10c00044 addi r3,r2,1 + 8039460: 008201b4 movhi r2,2054 + 8039464: 10f93d15 stw r3,-6924(r2) + +/* + * Altera Niche Stack Nios port modification + */ +#if defined(ALT_INICHE) && !defined(PING_APP) && defined(IP_RAW) + return(ip_raw_input(p)); + 8039468: e13ff317 ldw r4,-52(fp) + 803946c: 803c7d00 call 803c7d0 + 8039470: 00017106 br 8039a38 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + return(0); +#endif /* PING_APP */ +#ifdef FULL_ICMP + case DESTIN: + icmp_mib.icmpInDestUnreachs++; + 8039474: 008201b4 movhi r2,2054 + 8039478: 10b93717 ldw r2,-6948(r2) + 803947c: 10c00044 addi r3,r2,1 + 8039480: 008201b4 movhi r2,2054 + 8039484: 10f93715 stw r3,-6948(r2) + pdp = (struct destun *)e; + 8039488: e0bff917 ldw r2,-28(fp) + 803948c: e0bff615 stw r2,-40(fp) +#ifdef NPDEBUG + if (NDEBUG & UPCTRACE) + 8039490: d0a06617 ldw r2,-32360(gp) + 8039494: 1081000c andi r2,r2,1024 + 8039498: 10002f26 beq r2,zero,8039558 + { + dprintf("ICMP: got dest unreachable type "); + 803949c: 01020174 movhi r4,2053 + 80394a0: 212b6c04 addi r4,r4,-21072 + 80394a4: 8002c780 call 8002c78 + dprintf("%u on %u.%u.%u.%u ", pdp->dcode, + 80394a8: e0bff617 ldw r2,-40(fp) + 80394ac: 10800043 ldbu r2,1(r2) + 80394b0: 11003fcc andi r4,r2,255 + 80394b4: 2100201c xori r4,r4,128 + 80394b8: 213fe004 addi r4,r4,-128 + PUSH_IPADDR(pdp->dip.ip_dest)); + 80394bc: e0bff617 ldw r2,-40(fp) + 80394c0: 10800617 ldw r2,24(r2) + dprintf("%u on %u.%u.%u.%u ", pdp->dcode, + 80394c4: 11403fcc andi r5,r2,255 + PUSH_IPADDR(pdp->dip.ip_dest)); + 80394c8: e0bff617 ldw r2,-40(fp) + 80394cc: 10800617 ldw r2,24(r2) + 80394d0: 1004d23a srli r2,r2,8 + dprintf("%u on %u.%u.%u.%u ", pdp->dcode, + 80394d4: 11803fcc andi r6,r2,255 + PUSH_IPADDR(pdp->dip.ip_dest)); + 80394d8: e0bff617 ldw r2,-40(fp) + 80394dc: 10800617 ldw r2,24(r2) + 80394e0: 1004d43a srli r2,r2,16 + dprintf("%u on %u.%u.%u.%u ", pdp->dcode, + 80394e4: 10803fcc andi r2,r2,255 + PUSH_IPADDR(pdp->dip.ip_dest)); + 80394e8: e0fff617 ldw r3,-40(fp) + 80394ec: 18c00617 ldw r3,24(r3) + 80394f0: 1806d63a srli r3,r3,24 + dprintf("%u on %u.%u.%u.%u ", pdp->dcode, + 80394f4: d8c00115 stw r3,4(sp) + 80394f8: d8800015 stw r2,0(sp) + 80394fc: 300f883a mov r7,r6 + 8039500: 280d883a mov r6,r5 + 8039504: 200b883a mov r5,r4 + 8039508: 01020174 movhi r4,2053 + 803950c: 212b7504 addi r4,r4,-21036 + 8039510: 8002c780 call 8002c78 + dprintf("from %u.%u.%u.%u\n", PUSH_IPADDR(host)); + 8039514: e0bffa17 ldw r2,-24(fp) + 8039518: 10c03fcc andi r3,r2,255 + 803951c: e0bffa17 ldw r2,-24(fp) + 8039520: 1004d23a srli r2,r2,8 + 8039524: 11003fcc andi r4,r2,255 + 8039528: e0bffa17 ldw r2,-24(fp) + 803952c: 1004d43a srli r2,r2,16 + 8039530: 11403fcc andi r5,r2,255 + 8039534: e0bffa17 ldw r2,-24(fp) + 8039538: 1004d63a srli r2,r2,24 + 803953c: d8800015 stw r2,0(sp) + 8039540: 280f883a mov r7,r5 + 8039544: 200d883a mov r6,r4 + 8039548: 180b883a mov r5,r3 + 803954c: 01020174 movhi r4,2053 + 8039550: 212b7a04 addi r4,r4,-21016 + 8039554: 8002c780 call 8002c78 + } +#endif /* NPDEBUG */ + icmp_du(p, pdp); + 8039558: e17ff617 ldw r5,-40(fp) + 803955c: e13ff317 ldw r4,-52(fp) + 8039560: 803a01c0 call 803a01c + break; + 8039564: 00013306 br 8039a34 + case SOURCEQ: + icmp_mib.icmpInSrcQuenchs++; + 8039568: 008201b4 movhi r2,2054 + 803956c: 10b93a17 ldw r2,-6936(r2) + 8039570: 10c00044 addi r3,r2,1 + 8039574: 008201b4 movhi r2,2054 + 8039578: 10f93a15 stw r3,-6936(r2) +#ifdef NPDEBUG + if (NDEBUG & UPCTRACE) + 803957c: d0a06617 ldw r2,-32360(gp) + 8039580: 1081000c andi r2,r2,1024 + 8039584: 10001626 beq r2,zero,80395e0 + { + dprintf("ICMP: source quench from %u.%u.%u.%u\n", PUSH_IPADDR(host)); + 8039588: e0bffa17 ldw r2,-24(fp) + 803958c: 10c03fcc andi r3,r2,255 + 8039590: e0bffa17 ldw r2,-24(fp) + 8039594: 1004d23a srli r2,r2,8 + 8039598: 11003fcc andi r4,r2,255 + 803959c: e0bffa17 ldw r2,-24(fp) + 80395a0: 1004d43a srli r2,r2,16 + 80395a4: 11403fcc andi r5,r2,255 + 80395a8: e0bffa17 ldw r2,-24(fp) + 80395ac: 1004d63a srli r2,r2,24 + 80395b0: d8800015 stw r2,0(sp) + 80395b4: 280f883a mov r7,r5 + 80395b8: 200d883a mov r6,r4 + 80395bc: 180b883a mov r5,r3 + 80395c0: 01020174 movhi r4,2053 + 80395c4: 212b7f04 addi r4,r4,-20996 + 80395c8: 8002c780 call 8002c78 + if (NDEBUG & DUMP) ip_dump(p); + 80395cc: d0a06617 ldw r2,-32360(gp) + 80395d0: 1080008c andi r2,r2,2 + 80395d4: 10000226 beq r2,zero,80395e0 + 80395d8: e13ff317 ldw r4,-52(fp) + 80395dc: 803b0cc0 call 803b0cc + } +#endif /* NPDEBUG */ + LOCK_NET_RESOURCE(FREEQ_RESID); + 80395e0: 01000084 movi r4,2 + 80395e4: 8028f380 call 8028f38 + pk_free(p); + 80395e8: e13ff317 ldw r4,-52(fp) + 80395ec: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 80395f0: 01000084 movi r4,2 + 80395f4: 8028ff40 call 8028ff4 + break; + 80395f8: 00010e06 br 8039a34 + case REDIR: /* got an icmp redirect */ + icmp_mib.icmpInRedirects++; + 80395fc: 008201b4 movhi r2,2054 + 8039600: 10b93b17 ldw r2,-6932(r2) + 8039604: 10c00044 addi r3,r2,1 + 8039608: 008201b4 movhi r2,2054 + 803960c: 10f93b15 stw r3,-6932(r2) + rd = (struct redirect *)e; + 8039610: e0bff917 ldw r2,-28(fp) + 8039614: e0bff515 stw r2,-44(fp) +#ifdef NPDEBUG + if (NDEBUG & UPCTRACE) + 8039618: d0a06617 ldw r2,-32360(gp) + 803961c: 1081000c andi r2,r2,1024 + 8039620: 10002a26 beq r2,zero,80396cc + { + dprintf("ICMP: rcvd redirect for %u.%u.%u.%u ", + PUSH_IPADDR(rd->rdip.ip_dest)); + 8039624: e0bff517 ldw r2,-44(fp) + 8039628: 10800617 ldw r2,24(r2) + dprintf("ICMP: rcvd redirect for %u.%u.%u.%u ", + 803962c: 10c03fcc andi r3,r2,255 + PUSH_IPADDR(rd->rdip.ip_dest)); + 8039630: e0bff517 ldw r2,-44(fp) + 8039634: 10800617 ldw r2,24(r2) + 8039638: 1004d23a srli r2,r2,8 + dprintf("ICMP: rcvd redirect for %u.%u.%u.%u ", + 803963c: 11003fcc andi r4,r2,255 + PUSH_IPADDR(rd->rdip.ip_dest)); + 8039640: e0bff517 ldw r2,-44(fp) + 8039644: 10800617 ldw r2,24(r2) + 8039648: 1004d43a srli r2,r2,16 + dprintf("ICMP: rcvd redirect for %u.%u.%u.%u ", + 803964c: 11403fcc andi r5,r2,255 + PUSH_IPADDR(rd->rdip.ip_dest)); + 8039650: e0bff517 ldw r2,-44(fp) + 8039654: 10800617 ldw r2,24(r2) + 8039658: 1004d63a srli r2,r2,24 + dprintf("ICMP: rcvd redirect for %u.%u.%u.%u ", + 803965c: d8800015 stw r2,0(sp) + 8039660: 280f883a mov r7,r5 + 8039664: 200d883a mov r6,r4 + 8039668: 180b883a mov r5,r3 + 803966c: 01020174 movhi r4,2053 + 8039670: 212b8904 addi r4,r4,-20956 + 8039674: 8002c780 call 8002c78 + dprintf("to %u.%u.%u.%u\n", PUSH_IPADDR(rd->rdgw)); + 8039678: e0bff517 ldw r2,-44(fp) + 803967c: 10800117 ldw r2,4(r2) + 8039680: 10c03fcc andi r3,r2,255 + 8039684: e0bff517 ldw r2,-44(fp) + 8039688: 10800117 ldw r2,4(r2) + 803968c: 1004d23a srli r2,r2,8 + 8039690: 11003fcc andi r4,r2,255 + 8039694: e0bff517 ldw r2,-44(fp) + 8039698: 10800117 ldw r2,4(r2) + 803969c: 1004d43a srli r2,r2,16 + 80396a0: 11403fcc andi r5,r2,255 + 80396a4: e0bff517 ldw r2,-44(fp) + 80396a8: 10800117 ldw r2,4(r2) + 80396ac: 1004d63a srli r2,r2,24 + 80396b0: d8800015 stw r2,0(sp) + 80396b4: 280f883a mov r7,r5 + 80396b8: 200d883a mov r6,r4 + 80396bc: 180b883a mov r5,r3 + 80396c0: 01020174 movhi r4,2053 + 80396c4: 212b9304 addi r4,r4,-20916 + 80396c8: 8002c780 call 8002c78 + } +#endif /* NPDEBUG */ +#ifdef IP_ROUTING + /* try to add/update route table */ + add_route(rd->rdip.ip_dest, 0xFFFFFFFF, rd->rdgw, + 80396cc: e0bff517 ldw r2,-44(fp) + 80396d0: 14000617 ldw r16,24(r2) + 80396d4: e0bff517 ldw r2,-44(fp) + 80396d8: 14400117 ldw r17,4(r2) + 80396dc: e0bff317 ldw r2,-52(fp) + 80396e0: 10800617 ldw r2,24(r2) + 80396e4: 1009883a mov r4,r2 + 80396e8: 80252fc0 call 80252fc + 80396ec: 1007883a mov r3,r2 + 80396f0: 00800104 movi r2,4 + 80396f4: d8800015 stw r2,0(sp) + 80396f8: 180f883a mov r7,r3 + 80396fc: 880d883a mov r6,r17 + 8039700: 017fffc4 movi r5,-1 + 8039704: 8009883a mov r4,r16 + 8039708: 803cc7c0 call 803cc7c + net_num(p->net), IPRP_ICMP); +#endif /* IP_ROUTING */ + LOCK_NET_RESOURCE(FREEQ_RESID); + 803970c: 01000084 movi r4,2 + 8039710: 8028f380 call 8028f38 + pk_free(p); + 8039714: e13ff317 ldw r4,-52(fp) + 8039718: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803971c: 01000084 movi r4,2 + 8039720: 8028ff40 call 8028ff4 + break; + 8039724: 0000c306 br 8039a34 + case TIMEX: + icmp_mib.icmpInTimeExcds++; + 8039728: 008201b4 movhi r2,2054 + 803972c: 10b93817 ldw r2,-6944(r2) + 8039730: 10c00044 addi r3,r2,1 + 8039734: 008201b4 movhi r2,2054 + 8039738: 10f93815 stw r3,-6944(r2) +#ifdef NPDEBUG + if (NDEBUG & UPCTRACE) + 803973c: d0a06617 ldw r2,-32360(gp) + 8039740: 1081000c andi r2,r2,1024 + 8039744: 10003126 beq r2,zero,803980c + { + struct timex * pt = (struct timex *)e; + 8039748: e0bff917 ldw r2,-28(fp) + 803974c: e0bff415 stw r2,-48(fp) + + dprintf("ICMP: timex msg from %u.%u.%u.%u\n", + PUSH_IPADDR(p->fhost)); + 8039750: e0bff317 ldw r2,-52(fp) + 8039754: 10800717 ldw r2,28(r2) + dprintf("ICMP: timex msg from %u.%u.%u.%u\n", + 8039758: 10c03fcc andi r3,r2,255 + PUSH_IPADDR(p->fhost)); + 803975c: e0bff317 ldw r2,-52(fp) + 8039760: 10800717 ldw r2,28(r2) + 8039764: 1004d23a srli r2,r2,8 + dprintf("ICMP: timex msg from %u.%u.%u.%u\n", + 8039768: 11003fcc andi r4,r2,255 + PUSH_IPADDR(p->fhost)); + 803976c: e0bff317 ldw r2,-52(fp) + 8039770: 10800717 ldw r2,28(r2) + 8039774: 1004d43a srli r2,r2,16 + dprintf("ICMP: timex msg from %u.%u.%u.%u\n", + 8039778: 11403fcc andi r5,r2,255 + PUSH_IPADDR(p->fhost)); + 803977c: e0bff317 ldw r2,-52(fp) + 8039780: 10800717 ldw r2,28(r2) + 8039784: 1004d63a srli r2,r2,24 + dprintf("ICMP: timex msg from %u.%u.%u.%u\n", + 8039788: d8800015 stw r2,0(sp) + 803978c: 280f883a mov r7,r5 + 8039790: 200d883a mov r6,r4 + 8039794: 180b883a mov r5,r3 + 8039798: 01020174 movhi r4,2053 + 803979c: 212b9704 addi r4,r4,-20900 + 80397a0: 8002c780 call 8002c78 + dprintf(" about %u.%u.%u.%u\n", PUSH_IPADDR(pt->tip.ip_dest)); + 80397a4: e0bff417 ldw r2,-48(fp) + 80397a8: 10800617 ldw r2,24(r2) + 80397ac: 10c03fcc andi r3,r2,255 + 80397b0: e0bff417 ldw r2,-48(fp) + 80397b4: 10800617 ldw r2,24(r2) + 80397b8: 1004d23a srli r2,r2,8 + 80397bc: 11003fcc andi r4,r2,255 + 80397c0: e0bff417 ldw r2,-48(fp) + 80397c4: 10800617 ldw r2,24(r2) + 80397c8: 1004d43a srli r2,r2,16 + 80397cc: 11403fcc andi r5,r2,255 + 80397d0: e0bff417 ldw r2,-48(fp) + 80397d4: 10800617 ldw r2,24(r2) + 80397d8: 1004d63a srli r2,r2,24 + 80397dc: d8800015 stw r2,0(sp) + 80397e0: 280f883a mov r7,r5 + 80397e4: 200d883a mov r6,r4 + 80397e8: 180b883a mov r5,r3 + 80397ec: 01020174 movhi r4,2053 + 80397f0: 212ba004 addi r4,r4,-20864 + 80397f4: 8002c780 call 8002c78 + if (NDEBUG & DUMP) ip_dump(p); + 80397f8: d0a06617 ldw r2,-32360(gp) + 80397fc: 1080008c andi r2,r2,2 + 8039800: 10000226 beq r2,zero,803980c + 8039804: e13ff317 ldw r4,-52(fp) + 8039808: 803b0cc0 call 803b0cc + } +#endif /* NPDEBUG */ + LOCK_NET_RESOURCE(FREEQ_RESID); + 803980c: 01000084 movi r4,2 + 8039810: 8028f380 call 8028f38 + pk_free(p); + 8039814: e13ff317 ldw r4,-52(fp) + 8039818: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803981c: 01000084 movi r4,2 + 8039820: 8028ff40 call 8028ff4 + break; + 8039824: 00008306 br 8039a34 + case PARAM: + icmp_mib.icmpInParmProbs++; + 8039828: 008201b4 movhi r2,2054 + 803982c: 10b93917 ldw r2,-6940(r2) + 8039830: 10c00044 addi r3,r2,1 + 8039834: 008201b4 movhi r2,2054 + 8039838: 10f93915 stw r3,-6940(r2) +#ifdef NPDEBUG + if (NDEBUG & UPCTRACE) + 803983c: d0a06617 ldw r2,-32360(gp) + 8039840: 1081000c andi r2,r2,1024 + 8039844: 10000326 beq r2,zero,8039854 + dprintf("ICMP: got param problem message\n"); + 8039848: 01020174 movhi r4,2053 + 803984c: 212ba504 addi r4,r4,-20844 + 8039850: 8002d9c0 call 8002d9c + if (NDEBUG & DUMP) + 8039854: d0a06617 ldw r2,-32360(gp) + 8039858: 1080008c andi r2,r2,2 + 803985c: 10000226 beq r2,zero,8039868 + { + ip_dump(p); + 8039860: e13ff317 ldw r4,-52(fp) + 8039864: 803b0cc0 call 803b0cc + } +#endif /* NPDEBUG */ + LOCK_NET_RESOURCE(FREEQ_RESID); + 8039868: 01000084 movi r4,2 + 803986c: 8028f380 call 8028f38 + pk_free(p); + 8039870: e13ff317 ldw r4,-52(fp) + 8039874: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8039878: 01000084 movi r4,2 + 803987c: 8028ff40 call 8028ff4 + break; + 8039880: 00006c06 br 8039a34 + case TIMEREQ: + icmp_mib.icmpInTimestamps++; + 8039884: 008201b4 movhi r2,2054 + 8039888: 10b93e17 ldw r2,-6920(r2) + 803988c: 10c00044 addi r3,r2,1 + 8039890: 008201b4 movhi r2,2054 + 8039894: 10f93e15 stw r3,-6920(r2) +#ifdef NPDEBUG + if (NDEBUG & UPCTRACE) + 8039898: d0a06617 ldw r2,-32360(gp) + 803989c: 1081000c andi r2,r2,1024 + 80398a0: 10000326 beq r2,zero,80398b0 + dprintf("ICMP: got timestamp request\n"); + 80398a4: 01020174 movhi r4,2053 + 80398a8: 212bad04 addi r4,r4,-20812 + 80398ac: 8002d9c0 call 8002d9c +#endif /* NPDEBUG */ + e->ptype = TIMEREP; + 80398b0: e0bff917 ldw r2,-28(fp) + 80398b4: 00c00384 movi r3,14 + 80398b8: 10c00005 stb r3,0(r2) + e->pchksum = 0; + 80398bc: e0bff917 ldw r2,-28(fp) + 80398c0: 1000008d sth zero,2(r2) + */ + sstmp->dtstamp[1] = sstmp->dtstamp[2] = user_UTCtime(); + } +#endif /* USER_PING_TSTAMP */ + + e->pchksum = ~cksum(e, sizeof(struct tstamp)>>1); + 80398c4: 01400284 movi r5,10 + 80398c8: e13ff917 ldw r4,-28(fp) + 80398cc: 8026d7c0 call 8026d7c + 80398d0: 0084303a nor r2,zero,r2 + 80398d4: 1007883a mov r3,r2 + 80398d8: e0bff917 ldw r2,-28(fp) + 80398dc: 10c0008d sth r3,2(r2) + pip->ip_src = pip->ip_dest; + 80398e0: e0bffc17 ldw r2,-16(fp) + 80398e4: 10c00417 ldw r3,16(r2) + 80398e8: e0bffc17 ldw r2,-16(fp) + 80398ec: 10c00315 stw r3,12(r2) + pip->ip_dest = host; + 80398f0: e0bffc17 ldw r2,-16(fp) + 80398f4: e0fffa17 ldw r3,-24(fp) + 80398f8: 10c00415 stw r3,16(r2) + icmp_mib.icmpOutMsgs++; + 80398fc: 008201b4 movhi r2,2054 + 8039900: 10b94217 ldw r2,-6904(r2) + 8039904: 10c00044 addi r3,r2,1 + 8039908: 008201b4 movhi r2,2054 + 803990c: 10f94215 stw r3,-6904(r2) + icmp_mib.icmpOutTimestampReps++; + 8039910: 008201b4 movhi r2,2054 + 8039914: 10b94c17 ldw r2,-6864(r2) + 8039918: 10c00044 addi r3,r2,1 + 803991c: 008201b4 movhi r2,2054 + 8039920: 10f94c15 stw r3,-6864(r2) + p->nb_prot += ip_hlen(pip); /* move pointer past IP to ICMP */ + 8039924: e0bff317 ldw r2,-52(fp) + 8039928: 10c00317 ldw r3,12(r2) + 803992c: e0bffc17 ldw r2,-16(fp) + 8039930: 10800003 ldbu r2,0(r2) + 8039934: 10803fcc andi r2,r2,255 + 8039938: 100490ba slli r2,r2,2 + 803993c: 10800f0c andi r2,r2,60 + 8039940: 1887883a add r3,r3,r2 + 8039944: e0bff317 ldw r2,-52(fp) + 8039948: 10c00315 stw r3,12(r2) + p->nb_plen = sizeof(struct tstamp); + 803994c: e0bff317 ldw r2,-52(fp) + 8039950: 00c00504 movi r3,20 + 8039954: 10c00415 stw r3,16(r2) + p->fhost = host; + 8039958: e0bff317 ldw r2,-52(fp) + 803995c: e0fffa17 ldw r3,-24(fp) + 8039960: 10c00715 stw r3,28(r2) + i = ip_write(ICMP_PROT, p); + 8039964: e17ff317 ldw r5,-52(fp) + 8039968: 01000044 movi r4,1 + 803996c: 803a9e80 call 803a9e8 + 8039970: e0bff715 stw r2,-36(fp) + if (i < 0) + 8039974: e0bff717 ldw r2,-36(fp) + 8039978: 1000060e bge r2,zero,8039994 + { +#ifdef NPDEBUG + if (NDEBUG & UPCTRACE) + 803997c: d0a06617 ldw r2,-32360(gp) + 8039980: 1081000c andi r2,r2,1024 + 8039984: 10000326 beq r2,zero,8039994 + dprintf("icmp: can't send timestamp reply\n"); + 8039988: 01020174 movhi r4,2053 + 803998c: 212bb404 addi r4,r4,-20784 + 8039990: 8002d9c0 call 8002d9c +#endif /* NPDEBUG */ + } + /* re-used packet was pk_free()d by net->send() */ + return (0); + 8039994: 0005883a mov r2,zero + 8039998: 00002706 br 8039a38 + case INFO: +#ifdef NPDEBUG + if (NDEBUG & UPCTRACE) + 803999c: d0a06617 ldw r2,-32360(gp) + 80399a0: 1081000c andi r2,r2,1024 + 80399a4: 10000326 beq r2,zero,80399b4 + dprintf("icmp: got info request\n"); + 80399a8: 01020174 movhi r4,2053 + 80399ac: 212bbd04 addi r4,r4,-20748 + 80399b0: 8002d9c0 call 8002d9c +#endif /* NPDEBUG */ + LOCK_NET_RESOURCE(FREEQ_RESID); + 80399b4: 01000084 movi r4,2 + 80399b8: 8028f380 call 8028f38 + pk_free(p); + 80399bc: e13ff317 ldw r4,-52(fp) + 80399c0: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 80399c4: 01000084 movi r4,2 + 80399c8: 8028ff40 call 8028ff4 + break; + 80399cc: 00001906 br 8039a34 +#endif /* FULL_ICMP */ + default: +#ifdef NPDEBUG + if (NDEBUG & UPCTRACE) + 80399d0: d0a06617 ldw r2,-32360(gp) + 80399d4: 1081000c andi r2,r2,1024 + 80399d8: 10000e26 beq r2,zero,8039a14 + { + dprintf("icmp: unhandled type %u\n", e->ptype); + 80399dc: e0bff917 ldw r2,-28(fp) + 80399e0: 10800003 ldbu r2,0(r2) + 80399e4: 10803fcc andi r2,r2,255 + 80399e8: 1080201c xori r2,r2,128 + 80399ec: 10bfe004 addi r2,r2,-128 + 80399f0: 100b883a mov r5,r2 + 80399f4: 01020174 movhi r4,2053 + 80399f8: 212bc304 addi r4,r4,-20724 + 80399fc: 8002c780 call 8002c78 + if (NDEBUG & DUMP) ip_dump(p); + 8039a00: d0a06617 ldw r2,-32360(gp) + 8039a04: 1080008c andi r2,r2,2 + 8039a08: 10000226 beq r2,zero,8039a14 + 8039a0c: e13ff317 ldw r4,-52(fp) + 8039a10: 803b0cc0 call 803b0cc + } +#endif /* NPDEBUG */ + LOCK_NET_RESOURCE(FREEQ_RESID); + 8039a14: 01000084 movi r4,2 + 8039a18: 8028f380 call 8028f38 + pk_free(p); + 8039a1c: e13ff317 ldw r4,-52(fp) + 8039a20: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8039a24: 01000084 movi r4,2 + 8039a28: 8028ff40 call 8028ff4 + return ENP_NOT_MINE; + 8039a2c: 00800084 movi r2,2 + 8039a30: 00000106 br 8039a38 + } +#ifdef FULL_ICMP + return ENP_NOT_MINE; + 8039a34: 00800084 movi r2,2 +#endif /* FULL_ICMP */ +} + 8039a38: e6fffe04 addi sp,fp,-8 + 8039a3c: dfc00317 ldw ra,12(sp) + 8039a40: df000217 ldw fp,8(sp) + 8039a44: dc400117 ldw r17,4(sp) + 8039a48: dc000017 ldw r16,0(sp) + 8039a4c: dec00404 addi sp,sp,16 + 8039a50: f800283a ret + +08039a54 : +icmp_destun(ip_addr host, /* host to complain to */ + ip_addr src_addr, /* source address for outgoing ICMP/IP packet header */ + struct ip * ip, /* IP header of offending packet */ + unsigned typecode, /* type & code of DU to send (PROT, PORT, HOST) */ + NET net) /* interface that this packet came in on */ +{ + 8039a54: defff404 addi sp,sp,-48 + 8039a58: dfc00b15 stw ra,44(sp) + 8039a5c: df000a15 stw fp,40(sp) + 8039a60: df000a04 addi fp,sp,40 + 8039a64: e13ffb15 stw r4,-20(fp) + 8039a68: e17ffa15 stw r5,-24(fp) + 8039a6c: e1bff915 stw r6,-28(fp) + 8039a70: e1fff815 stw r7,-32(fp) + struct destun * d; + struct ip * pip; + int i; + +#ifdef NPDEBUG + if (NDEBUG & PROTERR) + 8039a74: d0a06617 ldw r2,-32360(gp) + 8039a78: 1080040c andi r2,r2,16 + 8039a7c: 10001826 beq r2,zero,8039ae0 + dprintf("icmp: sending %s dest unreachable to %u.%u.%u.%u\n", + dsts[typecode & 0xFF], PUSH_IPADDR(host)); + 8039a80: e0bff817 ldw r2,-32(fp) + 8039a84: 10803fcc andi r2,r2,255 + dprintf("icmp: sending %s dest unreachable to %u.%u.%u.%u\n", + 8039a88: 100690ba slli r3,r2,2 + 8039a8c: 00820174 movhi r2,2053 + 8039a90: 1885883a add r2,r3,r2 + 8039a94: 11325017 ldw r4,-14016(r2) + 8039a98: e0bffb17 ldw r2,-20(fp) + 8039a9c: 11403fcc andi r5,r2,255 + dsts[typecode & 0xFF], PUSH_IPADDR(host)); + 8039aa0: e0bffb17 ldw r2,-20(fp) + 8039aa4: 1004d23a srli r2,r2,8 + dprintf("icmp: sending %s dest unreachable to %u.%u.%u.%u\n", + 8039aa8: 11803fcc andi r6,r2,255 + dsts[typecode & 0xFF], PUSH_IPADDR(host)); + 8039aac: e0bffb17 ldw r2,-20(fp) + 8039ab0: 1004d43a srli r2,r2,16 + dprintf("icmp: sending %s dest unreachable to %u.%u.%u.%u\n", + 8039ab4: 10803fcc andi r2,r2,255 + dsts[typecode & 0xFF], PUSH_IPADDR(host)); + 8039ab8: e0fffb17 ldw r3,-20(fp) + 8039abc: 1806d63a srli r3,r3,24 + dprintf("icmp: sending %s dest unreachable to %u.%u.%u.%u\n", + 8039ac0: d8c00115 stw r3,4(sp) + 8039ac4: d8800015 stw r2,0(sp) + 8039ac8: 300f883a mov r7,r6 + 8039acc: 280d883a mov r6,r5 + 8039ad0: 200b883a mov r5,r4 + 8039ad4: 01020174 movhi r4,2053 + 8039ad8: 212bdd04 addi r4,r4,-20620 + 8039adc: 8002c780 call 8002c78 +#endif /* NPDEBUG */ + + LOCK_NET_RESOURCE(FREEQ_RESID); + 8039ae0: 01000084 movi r4,2 + 8039ae4: 8028f380 call 8028f38 + p = pk_alloc(512 + IPHSIZ); /* get packet to send icmp dest unreachable */ + 8039ae8: 01008504 movi r4,532 + 8039aec: 80284340 call 8028434 + 8039af0: e0bfff15 stw r2,-4(fp) + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8039af4: 01000084 movi r4,2 + 8039af8: 8028ff40 call 8028ff4 + + if (p == NULL) + 8039afc: e0bfff17 ldw r2,-4(fp) + 8039b00: 10000c1e bne r2,zero,8039b34 + { +#ifdef NPDEBUG + if (NDEBUG & IPTRACE) + 8039b04: d0a06617 ldw r2,-32360(gp) + 8039b08: 1080800c andi r2,r2,512 + 8039b0c: 10000326 beq r2,zero,8039b1c + dprintf("icmp: can't alloc pkt\n"); + 8039b10: 01020174 movhi r4,2053 + 8039b14: 212bea04 addi r4,r4,-20568 + 8039b18: 8002d9c0 call 8002d9c +#endif /* NPDEBUG */ + icmp_mib.icmpOutErrors++; + 8039b1c: 008201b4 movhi r2,2054 + 8039b20: 10b94317 ldw r2,-6900(r2) + 8039b24: 10c00044 addi r3,r2,1 + 8039b28: 008201b4 movhi r2,2054 + 8039b2c: 10f94315 stw r3,-6900(r2) + return; + 8039b30: 00007906 br 8039d18 + } + + /* build the addresses in the IP header */ + pip = (struct ip *)p->nb_prot; + 8039b34: e0bfff17 ldw r2,-4(fp) + 8039b38: 10800317 ldw r2,12(r2) + 8039b3c: e0bffe15 stw r2,-8(fp) + pip->ip_src = src_addr; + 8039b40: e0bffe17 ldw r2,-8(fp) + 8039b44: e0fffa17 ldw r3,-24(fp) + 8039b48: 10c00315 stw r3,12(r2) + pip->ip_dest = host; + 8039b4c: e0bffe17 ldw r2,-8(fp) + 8039b50: e0fffb17 ldw r3,-20(fp) + 8039b54: 10c00415 stw r3,16(r2) + + /* allow space for icmp header */ + p->nb_prot += sizeof(struct ip); + 8039b58: e0bfff17 ldw r2,-4(fp) + 8039b5c: 10800317 ldw r2,12(r2) + 8039b60: 10c00504 addi r3,r2,20 + 8039b64: e0bfff17 ldw r2,-4(fp) + 8039b68: 10c00315 stw r3,12(r2) + p->nb_plen -= sizeof(struct ip); + 8039b6c: e0bfff17 ldw r2,-4(fp) + 8039b70: 10800417 ldw r2,16(r2) + 8039b74: 10fffb04 addi r3,r2,-20 + 8039b78: e0bfff17 ldw r2,-4(fp) + 8039b7c: 10c00415 stw r3,16(r2) + p->net = net; /* Put in the interface that this packet came in on */ + 8039b80: e0bfff17 ldw r2,-4(fp) + 8039b84: e0c00217 ldw r3,8(fp) + 8039b88: 10c00615 stw r3,24(r2) + + d = (struct destun *)p->nb_prot; + 8039b8c: e0bfff17 ldw r2,-4(fp) + 8039b90: 10800317 ldw r2,12(r2) + 8039b94: e0bffd15 stw r2,-12(fp) + + if (typecode & 0xFF00) /* if the type was sent */ + 8039b98: e0bff817 ldw r2,-32(fp) + 8039b9c: 10bfc00c andi r2,r2,65280 + 8039ba0: 10000626 beq r2,zero,8039bbc + d->dtype = (char)(typecode >>8); /* then use it */ + 8039ba4: e0bff817 ldw r2,-32(fp) + 8039ba8: 1004d23a srli r2,r2,8 + 8039bac: 1007883a mov r3,r2 + 8039bb0: e0bffd17 ldw r2,-12(fp) + 8039bb4: 10c00005 stb r3,0(r2) + 8039bb8: 00000306 br 8039bc8 + else /* else use default */ + d->dtype = DESTIN; + 8039bbc: e0bffd17 ldw r2,-12(fp) + 8039bc0: 00c000c4 movi r3,3 + 8039bc4: 10c00005 stb r3,0(r2) + d->dcode = (char)(typecode & 0xFF); + 8039bc8: e0bff817 ldw r2,-32(fp) + 8039bcc: 1007883a mov r3,r2 + 8039bd0: e0bffd17 ldw r2,-12(fp) + 8039bd4: 10c00045 stb r3,1(r2) + d->dno1 = d->dno2 = 0; + 8039bd8: e0bffd17 ldw r2,-12(fp) + 8039bdc: 1000018d sth zero,6(r2) + 8039be0: e0bffd17 ldw r2,-12(fp) + 8039be4: 10c0018b ldhu r3,6(r2) + 8039be8: e0bffd17 ldw r2,-12(fp) + 8039bec: 10c0010d sth r3,4(r2) +#ifndef ICMP_SUPPRESS_PMTU + if ((typecode & 0xFF) == DSTFRAG) + 8039bf0: e0bff817 ldw r2,-32(fp) + 8039bf4: 10803fcc andi r2,r2,255 + 8039bf8: 10800118 cmpnei r2,r2,4 + 8039bfc: 1000121e bne r2,zero,8039c48 + d->dno2 = htons(net->n_mtu - net->n_lnh); + 8039c00: e0800217 ldw r2,8(fp) + 8039c04: 10c00917 ldw r3,36(r2) + 8039c08: e0800217 ldw r2,8(fp) + 8039c0c: 10800817 ldw r2,32(r2) + 8039c10: 1885c83a sub r2,r3,r2 + 8039c14: 1005d23a srai r2,r2,8 + 8039c18: 10803fcc andi r2,r2,255 + 8039c1c: 1009883a mov r4,r2 + 8039c20: e0800217 ldw r2,8(fp) + 8039c24: 10c00917 ldw r3,36(r2) + 8039c28: e0800217 ldw r2,8(fp) + 8039c2c: 10800817 ldw r2,32(r2) + 8039c30: 1885c83a sub r2,r3,r2 + 8039c34: 1004923a slli r2,r2,8 + 8039c38: 2084b03a or r2,r4,r2 + 8039c3c: 1007883a mov r3,r2 + 8039c40: e0bffd17 ldw r2,-12(fp) + 8039c44: 10c0018d sth r3,6(r2) +#endif /* ICMP_SUPPRESS_PMTU */ + MEMCPY(&d->dip, ip, (sizeof(struct ip) + ICMPDUDATA)); + 8039c48: e0bffd17 ldw r2,-12(fp) + 8039c4c: 10800204 addi r2,r2,8 + 8039c50: 01800704 movi r6,28 + 8039c54: e17ff917 ldw r5,-28(fp) + 8039c58: 1009883a mov r4,r2 + 8039c5c: 80086b80 call 80086b8 + + d->dchksum = 0; + 8039c60: e0bffd17 ldw r2,-12(fp) + 8039c64: 1000008d sth zero,2(r2) + d->dchksum = ~cksum(d, sizeof(struct destun)>>1); + 8039c68: 01400484 movi r5,18 + 8039c6c: e13ffd17 ldw r4,-12(fp) + 8039c70: 8026d7c0 call 8026d7c + 8039c74: 0084303a nor r2,zero,r2 + 8039c78: 1007883a mov r3,r2 + 8039c7c: e0bffd17 ldw r2,-12(fp) + 8039c80: 10c0008d sth r3,2(r2) + + p->nb_plen = sizeof(struct destun); + 8039c84: e0bfff17 ldw r2,-4(fp) + 8039c88: 00c00904 movi r3,36 + 8039c8c: 10c00415 stw r3,16(r2) + p->fhost = host; + 8039c90: e0bfff17 ldw r2,-4(fp) + 8039c94: e0fffb17 ldw r3,-20(fp) + 8039c98: 10c00715 stw r3,28(r2) + i = ip_write(ICMP_PROT, p); + 8039c9c: e17fff17 ldw r5,-4(fp) + 8039ca0: 01000044 movi r4,1 + 8039ca4: 803a9e80 call 803a9e8 + 8039ca8: e0bffc15 stw r2,-16(fp) + if (i < 0) + 8039cac: e0bffc17 ldw r2,-16(fp) + 8039cb0: 10000c0e bge r2,zero,8039ce4 + { + icmp_mib.icmpOutErrors++; + 8039cb4: 008201b4 movhi r2,2054 + 8039cb8: 10b94317 ldw r2,-6900(r2) + 8039cbc: 10c00044 addi r3,r2,1 + 8039cc0: 008201b4 movhi r2,2054 + 8039cc4: 10f94315 stw r3,-6900(r2) +#ifdef NPDEBUG + if (NDEBUG & (IPTRACE|NETERR|PROTERR)) + 8039cc8: d0a06617 ldw r2,-32360(gp) + 8039ccc: 1080860c andi r2,r2,536 + 8039cd0: 10001026 beq r2,zero,8039d14 + dprintf("ICMP: Can't send dest unreachable\n"); + 8039cd4: 01020174 movhi r4,2053 + 8039cd8: 212bf004 addi r4,r4,-20544 + 8039cdc: 8002d9c0 call 8002d9c +#endif /* NPDEBUG */ + return; + 8039ce0: 00000c06 br 8039d14 + } + icmp_mib.icmpOutMsgs++; + 8039ce4: 008201b4 movhi r2,2054 + 8039ce8: 10b94217 ldw r2,-6904(r2) + 8039cec: 10c00044 addi r3,r2,1 + 8039cf0: 008201b4 movhi r2,2054 + 8039cf4: 10f94215 stw r3,-6904(r2) + icmp_mib.icmpOutDestUnreachs++; + 8039cf8: 008201b4 movhi r2,2054 + 8039cfc: 10b94417 ldw r2,-6896(r2) + 8039d00: 10c00044 addi r3,r2,1 + 8039d04: 008201b4 movhi r2,2054 + 8039d08: 10f94415 stw r3,-6896(r2) + return; + 8039d0c: 0001883a nop + 8039d10: 00000106 br 8039d18 + return; + 8039d14: 0001883a nop +} + 8039d18: e037883a mov sp,fp + 8039d1c: dfc00117 ldw ra,4(sp) + 8039d20: df000017 ldw fp,0(sp) + 8039d24: dec00204 addi sp,sp,8 + 8039d28: f800283a ret + +08039d2c : + * + * RETURNS: void + */ + +void icmp_timex (struct ip * ip, char code) +{ + 8039d2c: defff504 addi sp,sp,-44 + 8039d30: dfc00a15 stw ra,40(sp) + 8039d34: df000915 stw fp,36(sp) + 8039d38: df000904 addi fp,sp,36 + 8039d3c: e13ffa15 stw r4,-24(fp) + 8039d40: 2805883a mov r2,r5 + 8039d44: e0bff905 stb r2,-28(fp) + struct ip * pip; + int i; + u_char icmp_pkt_len; + +#ifdef NPDEBUG + if (NDEBUG & PROTERR) + 8039d48: d0a06617 ldw r2,-32360(gp) + 8039d4c: 1080040c andi r2,r2,16 + 8039d50: 10003026 beq r2,zero,8039e14 + dprintf("icmp: sending ICMP Time Exceeded with code %u to %u.%u.%u.%u\n", + 8039d54: e17ff907 ldb r5,-28(fp) + code, PUSH_IPADDR((ntohs(ip->ip_src)))); + 8039d58: e0bffa17 ldw r2,-24(fp) + 8039d5c: 10800317 ldw r2,12(r2) + 8039d60: 1004d23a srli r2,r2,8 + 8039d64: 10c03fcc andi r3,r2,255 + 8039d68: e0bffa17 ldw r2,-24(fp) + 8039d6c: 10800317 ldw r2,12(r2) + 8039d70: 1004923a slli r2,r2,8 + 8039d74: 10bfffcc andi r2,r2,65535 + 8039d78: 1884b03a or r2,r3,r2 + dprintf("icmp: sending ICMP Time Exceeded with code %u to %u.%u.%u.%u\n", + 8039d7c: 11803fcc andi r6,r2,255 + code, PUSH_IPADDR((ntohs(ip->ip_src)))); + 8039d80: e0bffa17 ldw r2,-24(fp) + 8039d84: 10800317 ldw r2,12(r2) + 8039d88: 1004d23a srli r2,r2,8 + 8039d8c: 10c03fcc andi r3,r2,255 + 8039d90: e0bffa17 ldw r2,-24(fp) + 8039d94: 10800317 ldw r2,12(r2) + 8039d98: 1004923a slli r2,r2,8 + 8039d9c: 10bfffcc andi r2,r2,65535 + 8039da0: 1884b03a or r2,r3,r2 + 8039da4: 1004d23a srli r2,r2,8 + dprintf("icmp: sending ICMP Time Exceeded with code %u to %u.%u.%u.%u\n", + 8039da8: 11c03fcc andi r7,r2,255 + code, PUSH_IPADDR((ntohs(ip->ip_src)))); + 8039dac: e0bffa17 ldw r2,-24(fp) + 8039db0: 10800317 ldw r2,12(r2) + 8039db4: 1004d23a srli r2,r2,8 + 8039db8: 10c03fcc andi r3,r2,255 + 8039dbc: e0bffa17 ldw r2,-24(fp) + 8039dc0: 10800317 ldw r2,12(r2) + 8039dc4: 1004923a slli r2,r2,8 + 8039dc8: 10bfffcc andi r2,r2,65535 + 8039dcc: 1884b03a or r2,r3,r2 + 8039dd0: 1004d43a srli r2,r2,16 + dprintf("icmp: sending ICMP Time Exceeded with code %u to %u.%u.%u.%u\n", + 8039dd4: 10803fcc andi r2,r2,255 + code, PUSH_IPADDR((ntohs(ip->ip_src)))); + 8039dd8: e0fffa17 ldw r3,-24(fp) + 8039ddc: 18c00317 ldw r3,12(r3) + 8039de0: 1806d23a srli r3,r3,8 + 8039de4: 19003fcc andi r4,r3,255 + 8039de8: e0fffa17 ldw r3,-24(fp) + 8039dec: 18c00317 ldw r3,12(r3) + 8039df0: 1806923a slli r3,r3,8 + 8039df4: 18ffffcc andi r3,r3,65535 + 8039df8: 20c6b03a or r3,r4,r3 + 8039dfc: 1806d63a srli r3,r3,24 + dprintf("icmp: sending ICMP Time Exceeded with code %u to %u.%u.%u.%u\n", + 8039e00: d8c00115 stw r3,4(sp) + 8039e04: d8800015 stw r2,0(sp) + 8039e08: 01020174 movhi r4,2053 + 8039e0c: 212bf904 addi r4,r4,-20508 + 8039e10: 8002c780 call 8002c78 +#endif /* NPDEBUG */ + + icmp_pkt_len = ICMPTIMEX_HDR_LEN + ip_hlen(ip) + ICMPTIMEX_PAYLOAD_DATA_LEN; + 8039e14: e0bffa17 ldw r2,-24(fp) + 8039e18: 10800003 ldbu r2,0(r2) + 8039e1c: 10803fcc andi r2,r2,255 + 8039e20: 100490ba slli r2,r2,2 + 8039e24: 10800f0c andi r2,r2,60 + 8039e28: 10800404 addi r2,r2,16 + 8039e2c: e0bfffc5 stb r2,-1(fp) + LOCK_NET_RESOURCE(FREEQ_RESID); + 8039e30: 01000084 movi r4,2 + 8039e34: 8028f380 call 8028f38 + * length of the "outer" IP header, length of the ICMP header (ICMPTIMEX_HDR_LEN, + * 8 bytes), length of the "inner" IP header, and length of "user" data + * (ICMPTIMEX_PAYLOAD_DATA_LEN, 8 bytes) (just past the "inner" IP header). The + * latter two items are from the packet that the ICMP Time Exceeded message is + * being sent in response to. */ + p = pk_alloc(MaxLnh + IPHSIZ + icmp_pkt_len); + 8039e38: e0bfffc3 ldbu r2,-1(fp) + 8039e3c: d0e06417 ldw r3,-32368(gp) + 8039e40: 10c5883a add r2,r2,r3 + 8039e44: 10800504 addi r2,r2,20 + 8039e48: 1009883a mov r4,r2 + 8039e4c: 80284340 call 8028434 + 8039e50: e0bffe15 stw r2,-8(fp) + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 8039e54: 01000084 movi r4,2 + 8039e58: 8028ff40 call 8028ff4 + + if (p == NULL) + 8039e5c: e0bffe17 ldw r2,-8(fp) + 8039e60: 10000c1e bne r2,zero,8039e94 + { +#ifdef NPDEBUG + if (NDEBUG & IPTRACE) + 8039e64: d0a06617 ldw r2,-32360(gp) + 8039e68: 1080800c andi r2,r2,512 + 8039e6c: 10000326 beq r2,zero,8039e7c + dprintf("icmp: can't alloc pkt\n"); + 8039e70: 01020174 movhi r4,2053 + 8039e74: 212bea04 addi r4,r4,-20568 + 8039e78: 8002d9c0 call 8002d9c +#endif /* NPDEBUG */ + icmp_mib.icmpOutErrors++; + 8039e7c: 008201b4 movhi r2,2054 + 8039e80: 10b94317 ldw r2,-6900(r2) + 8039e84: 10c00044 addi r3,r2,1 + 8039e88: 008201b4 movhi r2,2054 + 8039e8c: 10f94315 stw r3,-6900(r2) + return; + 8039e90: 00005d06 br 803a008 + } + + /* build the addresses in the IP header */ + pip = (struct ip *)p->nb_prot; + 8039e94: e0bffe17 ldw r2,-8(fp) + 8039e98: 10800317 ldw r2,12(r2) + 8039e9c: e0bffd15 stw r2,-12(fp) + /* source IP address of packet is our address (i.e., destination IP address + * in the datagram whose reassembly timed out) */ + pip->ip_src = ip->ip_dest; + 8039ea0: e0bffa17 ldw r2,-24(fp) + 8039ea4: 10c00417 ldw r3,16(r2) + 8039ea8: e0bffd17 ldw r2,-12(fp) + 8039eac: 10c00315 stw r3,12(r2) + /* the destination address is the same as the source IP address of the + * datagram whose reassembly timed out */ + pip->ip_dest = ip->ip_src; + 8039eb0: e0bffa17 ldw r2,-24(fp) + 8039eb4: 10c00317 ldw r3,12(r2) + 8039eb8: e0bffd17 ldw r2,-12(fp) + 8039ebc: 10c00415 stw r3,16(r2) + + /* move past space for IP header to get to start of ICMP header */ + p->nb_prot += sizeof(struct ip); + 8039ec0: e0bffe17 ldw r2,-8(fp) + 8039ec4: 10800317 ldw r2,12(r2) + 8039ec8: 10c00504 addi r3,r2,20 + 8039ecc: e0bffe17 ldw r2,-8(fp) + 8039ed0: 10c00315 stw r3,12(r2) + + tx = (struct timex *) p->nb_prot; + 8039ed4: e0bffe17 ldw r2,-8(fp) + 8039ed8: 10800317 ldw r2,12(r2) + 8039edc: e0bffc15 stw r2,-16(fp) + + tx->ttype = TIMEX; + 8039ee0: e0bffc17 ldw r2,-16(fp) + 8039ee4: 00c002c4 movi r3,11 + 8039ee8: 10c00005 stb r3,0(r2) + tx->tcode = code; + 8039eec: e0bffc17 ldw r2,-16(fp) + 8039ef0: e0fff903 ldbu r3,-28(fp) + 8039ef4: 10c00045 stb r3,1(r2) + tx->tno1 = tx->tno2 = 0; + 8039ef8: e0bffc17 ldw r2,-16(fp) + 8039efc: 1000018d sth zero,6(r2) + 8039f00: e0bffc17 ldw r2,-16(fp) + 8039f04: 10c0018b ldhu r3,6(r2) + 8039f08: e0bffc17 ldw r2,-16(fp) + 8039f0c: 10c0010d sth r3,4(r2) + MEMCPY(&tx->tip, ip, (ip_hlen(ip) + ICMPTIMEX_PAYLOAD_DATA_LEN)); + 8039f10: e0bffc17 ldw r2,-16(fp) + 8039f14: 10c00204 addi r3,r2,8 + 8039f18: e0bffa17 ldw r2,-24(fp) + 8039f1c: 10800003 ldbu r2,0(r2) + 8039f20: 10803fcc andi r2,r2,255 + 8039f24: 100490ba slli r2,r2,2 + 8039f28: 10800f0c andi r2,r2,60 + 8039f2c: 10800204 addi r2,r2,8 + 8039f30: 100d883a mov r6,r2 + 8039f34: e17ffa17 ldw r5,-24(fp) + 8039f38: 1809883a mov r4,r3 + 8039f3c: 80086b80 call 80086b8 + + tx->tchksum = 0; + 8039f40: e0bffc17 ldw r2,-16(fp) + 8039f44: 1000008d sth zero,2(r2) + tx->tchksum = ~cksum(tx, (icmp_pkt_len>>1)); + 8039f48: e0bfffc3 ldbu r2,-1(fp) + 8039f4c: 1004d07a srli r2,r2,1 + 8039f50: 10803fcc andi r2,r2,255 + 8039f54: 100b883a mov r5,r2 + 8039f58: e13ffc17 ldw r4,-16(fp) + 8039f5c: 8026d7c0 call 8026d7c + 8039f60: 0084303a nor r2,zero,r2 + 8039f64: 1007883a mov r3,r2 + 8039f68: e0bffc17 ldw r2,-16(fp) + 8039f6c: 10c0008d sth r3,2(r2) + + p->nb_plen = icmp_pkt_len; + 8039f70: e0ffffc3 ldbu r3,-1(fp) + 8039f74: e0bffe17 ldw r2,-8(fp) + 8039f78: 10c00415 stw r3,16(r2) + /* p->fhost is expected to be in network byte order */ + p->fhost = pip->ip_dest; + 8039f7c: e0bffd17 ldw r2,-12(fp) + 8039f80: 10c00417 ldw r3,16(r2) + 8039f84: e0bffe17 ldw r2,-8(fp) + 8039f88: 10c00715 stw r3,28(r2) + i = ip_write(ICMP_PROT, p); + 8039f8c: e17ffe17 ldw r5,-8(fp) + 8039f90: 01000044 movi r4,1 + 8039f94: 803a9e80 call 803a9e8 + 8039f98: e0bffb15 stw r2,-20(fp) + if (i < 0) + 8039f9c: e0bffb17 ldw r2,-20(fp) + 8039fa0: 10000c0e bge r2,zero,8039fd4 + { + icmp_mib.icmpOutErrors++; + 8039fa4: 008201b4 movhi r2,2054 + 8039fa8: 10b94317 ldw r2,-6900(r2) + 8039fac: 10c00044 addi r3,r2,1 + 8039fb0: 008201b4 movhi r2,2054 + 8039fb4: 10f94315 stw r3,-6900(r2) +#ifdef NPDEBUG + if (NDEBUG & (IPTRACE|NETERR|PROTERR)) + 8039fb8: d0a06617 ldw r2,-32360(gp) + 8039fbc: 1080860c andi r2,r2,536 + 8039fc0: 10001026 beq r2,zero,803a004 + dprintf("ICMP: Can't send Time Exceeded\n"); + 8039fc4: 01020174 movhi r4,2053 + 8039fc8: 212c0904 addi r4,r4,-20444 + 8039fcc: 8002d9c0 call 8002d9c +#endif /* NPDEBUG */ + return; + 8039fd0: 00000c06 br 803a004 + } + icmp_mib.icmpOutMsgs++; + 8039fd4: 008201b4 movhi r2,2054 + 8039fd8: 10b94217 ldw r2,-6904(r2) + 8039fdc: 10c00044 addi r3,r2,1 + 8039fe0: 008201b4 movhi r2,2054 + 8039fe4: 10f94215 stw r3,-6904(r2) + icmp_mib.icmpOutTimeExcds++; + 8039fe8: 008201b4 movhi r2,2054 + 8039fec: 10b94517 ldw r2,-6892(r2) + 8039ff0: 10c00044 addi r3,r2,1 + 8039ff4: 008201b4 movhi r2,2054 + 8039ff8: 10f94515 stw r3,-6892(r2) + return; + 8039ffc: 0001883a nop + 803a000: 00000106 br 803a008 + return; + 803a004: 0001883a nop +} + 803a008: e037883a mov sp,fp + 803a00c: dfc00117 ldw ra,4(sp) + 803a010: df000017 ldw fp,0(sp) + 803a014: dec00204 addi sp,sp,8 + 803a018: f800283a ret + +0803a01c : + * RETURNS: void + */ + +void +icmp_du(PACKET p, struct destun * pdp) +{ + 803a01c: defffc04 addi sp,sp,-16 + 803a020: dfc00315 stw ra,12(sp) + 803a024: df000215 stw fp,8(sp) + 803a028: df000204 addi fp,sp,8 + 803a02c: e13fff15 stw r4,-4(fp) + 803a030: e17ffe15 stw r5,-8(fp) + /* see if user app wants notification first */ + if (icmpdu_hook) + 803a034: d0a09417 ldw r2,-32176(gp) + 803a038: 10000426 beq r2,zero,803a04c + icmpdu_hook(p, pdp); + 803a03c: d0a09417 ldw r2,-32176(gp) + 803a040: e17ffe17 ldw r5,-8(fp) + 803a044: e13fff17 ldw r4,-4(fp) + 803a048: 103ee83a callr r2 + +#ifdef INCLUDE_TCP + /* Tell the sockets layer so it can correct the problem. */ + so_icmpdu(p, pdp); /* this call should free packet p */ + 803a04c: e17ffe17 ldw r5,-8(fp) + 803a050: e13fff17 ldw r4,-4(fp) + 803a054: 802ad080 call 802ad08 +done: + LOCK_NET_RESOURCE(FREEQ_RESID); + pk_free(p); /* else just free packet */ + UNLOCK_NET_RESOURCE(FREEQ_RESID); +#endif /* INCLUDE_TCP */ +} + 803a058: 0001883a nop + 803a05c: e037883a mov sp,fp + 803a060: dfc00117 ldw ra,4(sp) + 803a064: df000017 ldw fp,0(sp) + 803a068: dec00204 addi sp,sp,8 + 803a06c: f800283a ret + +0803a070 : + * OK, else returns a non-zero error code. + */ + +int +ip_init(void) +{ + 803a070: defffe04 addi sp,sp,-8 + 803a074: dfc00115 stw ra,4(sp) + 803a078: df000015 stw fp,0(sp) + 803a07c: d839883a mov fp,sp + + /* register IP type with link layer drivers */ + if (reg_type(IP_TYPE) != 0) + 803a080: 01000204 movi r4,8 + 803a084: 80241c80 call 80241c8 + 803a088: 10000526 beq r2,zero,803a0a0 + { +#ifdef NPDEBUG + dprintf("IP_INIT: unable to register type with MAC driver\n"); + 803a08c: 01020174 movhi r4,2053 + 803a090: 212c1104 addi r4,r4,-20412 + 803a094: 8002d9c0 call 8002d9c +#endif + return(1); + 803a098: 00800044 movi r2,1 + 803a09c: 00002506 br 803a134 + } + + /* initialize the IP mib */ + MEMSET(&ip_mib, 0, sizeof(ip_mib)); + 803a0a0: 01801404 movi r6,80 + 803a0a4: 000b883a mov r5,zero + 803a0a8: 010201b4 movhi r4,2054 + 803a0ac: 21394f04 addi r4,r4,-6852 + 803a0b0: 80088e40 call 80088e4 + ip_mib.ipForwarding = 2; /* default to host, not gateway (router) */ + 803a0b4: 00c00084 movi r3,2 + 803a0b8: 008201b4 movhi r2,2054 + 803a0bc: 10f94f15 stw r3,-6852(r2) + ip_mib.ipDefaultTTL = IP_TTL; + 803a0c0: 00c01004 movi r3,64 + 803a0c4: 008201b4 movhi r2,2054 + 803a0c8: 10f95015 stw r3,-6848(r2) + +#ifdef IP_ROUTING + /* alloc space for the route table */ + rt_mib = (struct RtMib*)RT_ALLOC(ipRoutes * sizeof(struct RtMib)); + 803a0cc: d0a03017 ldw r2,-32576(gp) + 803a0d0: 10800f24 muli r2,r2,60 + 803a0d4: 1009883a mov r4,r2 + 803a0d8: 802982c0 call 802982c + 803a0dc: d0a09515 stw r2,-32172(gp) + if (!rt_mib) + 803a0e0: d0a09517 ldw r2,-32172(gp) + 803a0e4: 1000051e bne r2,zero,803a0fc + { +#ifdef NPDEBUG + dprintf("IP_INIT ERROR: can't alloc route table\n"); + 803a0e8: 01020174 movhi r4,2053 + 803a0ec: 212c1e04 addi r4,r4,-20360 + 803a0f0: 8002d9c0 call 8002d9c +#endif /* NPDEBUG */ + return(ENP_NOMEM); + 803a0f4: 00bffb04 movi r2,-20 + 803a0f8: 00000e06 br 803a134 + } + + MEMSET(rt_mib,0, ipRoutes * sizeof(struct RtMib)) ; + 803a0fc: d0e09517 ldw r3,-32172(gp) + 803a100: d0a03017 ldw r2,-32576(gp) + 803a104: 10800f24 muli r2,r2,60 + 803a108: 100d883a mov r6,r2 + 803a10c: 000b883a mov r5,zero + 803a110: 1809883a mov r4,r3 + 803a114: 80088e40 call 80088e4 + ip_mib.ipForwarding = 1; /* override default, be gateway (router) */ + 803a118: 00c00044 movi r3,1 + 803a11c: 008201b4 movhi r2,2054 + 803a120: 10f94f15 stw r3,-6852(r2) +#endif /* IP_ROUTING */ + + /* set IP reassembly timeout */ + ip_mib.ipReasmTimeout = IRE_TMO; + 803a124: 00c01e04 movi r3,120 + 803a128: 008201b4 movhi r2,2054 + 803a12c: 10f95b15 stw r3,-6804(r2) + return(1); + } +#endif /* IPSEC */ + + /* everything opened OK return 0 */ + return(SUCCESS); + 803a130: 0005883a mov r2,zero +} + 803a134: e037883a mov sp,fp + 803a138: dfc00117 ldw ra,4(sp) + 803a13c: df000017 ldw fp,0(sp) + 803a140: dec00204 addi sp,sp,8 + 803a144: f800283a ret + +0803a148 : + * RETURNS: void + */ + +void +ip_bldhead(PACKET p, unsigned pid, u_char prot, unshort fragword) +{ + 803a148: defff804 addi sp,sp,-32 + 803a14c: dfc00715 stw ra,28(sp) + 803a150: df000615 stw fp,24(sp) + 803a154: df000604 addi fp,sp,24 + 803a158: e13ffd15 stw r4,-12(fp) + 803a15c: e17ffc15 stw r5,-16(fp) + 803a160: 3005883a mov r2,r6 + 803a164: 3807883a mov r3,r7 + 803a168: e0bffb05 stb r2,-20(fp) + 803a16c: 1805883a mov r2,r3 + 803a170: e0bffa0d sth r2,-24(fp) + struct ip * pip; + struct ip_socopts *sopts; + + /* prepend IP header to packet data */ + p->nb_prot -= sizeof(struct ip); /* this assumes no send options! */ + 803a174: e0bffd17 ldw r2,-12(fp) + 803a178: 10800317 ldw r2,12(r2) + 803a17c: 10fffb04 addi r3,r2,-20 + 803a180: e0bffd17 ldw r2,-12(fp) + 803a184: 10c00315 stw r3,12(r2) + p->nb_plen += sizeof(struct ip); + 803a188: e0bffd17 ldw r2,-12(fp) + 803a18c: 10800417 ldw r2,16(r2) + 803a190: 10c00504 addi r3,r2,20 + 803a194: e0bffd17 ldw r2,-12(fp) + 803a198: 10c00415 stw r3,16(r2) + + pip = (struct ip*)p->nb_prot; + 803a19c: e0bffd17 ldw r2,-12(fp) + 803a1a0: 10800317 ldw r2,12(r2) + 803a1a4: e0bfff15 stw r2,-4(fp) + + pip->ip_ver_ihl = 0x45; /* 2 nibbles; VER:4, IHL:5. */ + 803a1a8: e0bfff17 ldw r2,-4(fp) + 803a1ac: 00c01144 movi r3,69 + 803a1b0: 10c00005 stb r3,0(r2) + pip->ip_flgs_foff = fragword; /* fragment flags and offset */ + 803a1b4: e0bfff17 ldw r2,-4(fp) + 803a1b8: e0fffa0b ldhu r3,-24(fp) + 803a1bc: 10c0018d sth r3,6(r2) + pip->ip_id = htons((unshort)pid); /* IP datagram ID */ + 803a1c0: e0bffc17 ldw r2,-16(fp) + 803a1c4: 10bfffcc andi r2,r2,65535 + 803a1c8: 1004d23a srli r2,r2,8 + 803a1cc: 1007883a mov r3,r2 + 803a1d0: e0bffc17 ldw r2,-16(fp) + 803a1d4: 10bfffcc andi r2,r2,65535 + 803a1d8: 1004923a slli r2,r2,8 + 803a1dc: 1884b03a or r2,r3,r2 + 803a1e0: 1007883a mov r3,r2 + 803a1e4: e0bfff17 ldw r2,-4(fp) + 803a1e8: 10c0010d sth r3,4(r2) + pip->ip_len = htons((unshort)p->nb_plen); + 803a1ec: e0bffd17 ldw r2,-12(fp) + 803a1f0: 10800417 ldw r2,16(r2) + 803a1f4: 10bfffcc andi r2,r2,65535 + 803a1f8: 1004d23a srli r2,r2,8 + 803a1fc: 1007883a mov r3,r2 + 803a200: e0bffd17 ldw r2,-12(fp) + 803a204: 10800417 ldw r2,16(r2) + 803a208: 10bfffcc andi r2,r2,65535 + 803a20c: 1004923a slli r2,r2,8 + 803a210: 1884b03a or r2,r3,r2 + 803a214: 1007883a mov r3,r2 + 803a218: e0bfff17 ldw r2,-4(fp) + 803a21c: 10c0008d sth r3,2(r2) + pip->ip_prot = prot; /* install protocol ID (TCP, UDP, etc) */ + 803a220: e0bfff17 ldw r2,-4(fp) + 803a224: e0fffb03 ldbu r3,-20(fp) + 803a228: 10c00245 stb r3,9(r2) + + /* have IP_TOS or IP_TTL been set? */ + if ((sopts = p->soxopts)) + 803a22c: e0bffd17 ldw r2,-12(fp) + 803a230: 10800c17 ldw r2,48(r2) + 803a234: e0bffe15 stw r2,-8(fp) + 803a238: e0bffe17 ldw r2,-8(fp) + 803a23c: 10001126 beq r2,zero,803a284 + { + /* yup */ + if (sopts->ip_ttl) + 803a240: e0bffe17 ldw r2,-8(fp) + 803a244: 10800043 ldbu r2,1(r2) + 803a248: 10803fcc andi r2,r2,255 + 803a24c: 10000526 beq r2,zero,803a264 + pip->ip_time = sopts->ip_ttl; + 803a250: e0bffe17 ldw r2,-8(fp) + 803a254: 10c00043 ldbu r3,1(r2) + 803a258: e0bfff17 ldw r2,-4(fp) + 803a25c: 10c00205 stb r3,8(r2) + 803a260: 00000306 br 803a270 + else + pip->ip_time = (u_char)IP_TTL; /* default number of hops, really */ + 803a264: e0bfff17 ldw r2,-4(fp) + 803a268: 00c01004 movi r3,64 + 803a26c: 10c00205 stb r3,8(r2) + pip->ip_tos = sopts->ip_tos; + 803a270: e0bffe17 ldw r2,-8(fp) + 803a274: 10c00003 ldbu r3,0(r2) + 803a278: e0bfff17 ldw r2,-4(fp) + 803a27c: 10c00045 stb r3,1(r2) + 803a280: 00000506 br 803a298 + } + else + { + /* nope */ + pip->ip_time = (u_char)IP_TTL; /* default number of hops, really */ + 803a284: e0bfff17 ldw r2,-4(fp) + 803a288: 00c01004 movi r3,64 + 803a28c: 10c00205 stb r3,8(r2) + pip->ip_tos = IP_TOS_DEFVAL; + 803a290: e0bfff17 ldw r2,-4(fp) + 803a294: 10000045 stb zero,1(r2) + } + + pip->ip_chksum = IPXSUM; /* clear checksum field for summing */ + 803a298: e0bfff17 ldw r2,-4(fp) + 803a29c: 1000028d sth zero,10(r2) + pip->ip_chksum = ~cksum(pip, 10); + 803a2a0: 01400284 movi r5,10 + 803a2a4: e13fff17 ldw r4,-4(fp) + 803a2a8: 8026d7c0 call 8026d7c + 803a2ac: 0084303a nor r2,zero,r2 + 803a2b0: 1007883a mov r3,r2 + 803a2b4: e0bfff17 ldw r2,-4(fp) + 803a2b8: 10c0028d sth r3,10(r2) +} + 803a2bc: 0001883a nop + 803a2c0: e037883a mov sp,fp + 803a2c4: dfc00117 ldw ra,4(sp) + 803a2c8: df000017 ldw fp,0(sp) + 803a2cc: dec00204 addi sp,sp,8 + 803a2d0: f800283a ret + +0803a2d4 : + * RETURNS: Returns 0 if sent OK, ENP_SEND_PENDING (1) if + * waiting for ARP, else negative error code if error detected. + */ +int +ip_write_internal(PACKET p) +{ + 803a2d4: defff104 addi sp,sp,-60 + 803a2d8: dfc00e15 stw ra,56(sp) + 803a2dc: df000d15 stw fp,52(sp) + 803a2e0: df000d04 addi fp,sp,52 + 803a2e4: e13ff615 stw r4,-40(fp) + PACKET newpkt; + unsigned maxbuflen; + +#ifdef IP_MULTICAST + /* If destination address is multicast, process multicast options */ + if (IN_MULTICAST(ntohl(p->fhost))) + 803a2e8: e0bff617 ldw r2,-40(fp) + 803a2ec: 10800717 ldw r2,28(r2) + 803a2f0: 1006d63a srli r3,r2,24 + 803a2f4: e0bff617 ldw r2,-40(fp) + 803a2f8: 10800717 ldw r2,28(r2) + 803a2fc: 1004d23a srli r2,r2,8 + 803a300: 10bfc00c andi r2,r2,65280 + 803a304: 1886b03a or r3,r3,r2 + 803a308: e0bff617 ldw r2,-40(fp) + 803a30c: 10800717 ldw r2,28(r2) + 803a310: 1004923a slli r2,r2,8 + 803a314: 10803fec andhi r2,r2,255 + 803a318: 1886b03a or r3,r3,r2 + 803a31c: e0bff617 ldw r2,-40(fp) + 803a320: 10800717 ldw r2,28(r2) + 803a324: 1004963a slli r2,r2,24 + 803a328: 1884b03a or r2,r3,r2 + 803a32c: 10fc002c andhi r3,r2,61440 + 803a330: 00b80034 movhi r2,57344 + 803a334: 1880a21e bne r3,r2,803a5c0 + { + if (p->imo != NULL) + 803a338: e0bff617 ldw r2,-40(fp) + 803a33c: 10800b17 ldw r2,44(r2) + 803a340: 10001426 beq r2,zero,803a394 + if (p->imo->imo_multicast_netp) + 803a344: e0bff617 ldw r2,-40(fp) + 803a348: 10800b17 ldw r2,44(r2) + 803a34c: 10800017 ldw r2,0(r2) + 803a350: 10000626 beq r2,zero,803a36c + p->net = p->imo->imo_multicast_netp; + 803a354: e0bff617 ldw r2,-40(fp) + 803a358: 10800b17 ldw r2,44(r2) + 803a35c: 10c00017 ldw r3,0(r2) + 803a360: e0bff617 ldw r2,-40(fp) + 803a364: 10c00615 stw r3,24(r2) + 803a368: 00002106 br 803a3f0 + else + p->net = iproute(p->fhost, &firsthop); + 803a36c: e0bff617 ldw r2,-40(fp) + 803a370: 10800717 ldw r2,28(r2) + 803a374: e0fff704 addi r3,fp,-36 + 803a378: 180b883a mov r5,r3 + 803a37c: 1009883a mov r4,r2 + 803a380: 803b3700 call 803b370 + 803a384: 1007883a mov r3,r2 + 803a388: e0bff617 ldw r2,-40(fp) + 803a38c: 10c00615 stw r3,24(r2) + 803a390: 00001706 br 803a3f0 + else + { + for (i = 0; i < ifNumber; i++) + 803a394: e03fff15 stw zero,-4(fp) + 803a398: 00001206 br 803a3e4 + if (nets[i]->n_mcastlist) + 803a39c: e0bfff17 ldw r2,-4(fp) + 803a3a0: 100690ba slli r3,r2,2 + 803a3a4: 008201b4 movhi r2,2054 + 803a3a8: 1885883a add r2,r3,r2 + 803a3ac: 10b77017 ldw r2,-8768(r2) + 803a3b0: 10802b17 ldw r2,172(r2) + 803a3b4: 10000826 beq r2,zero,803a3d8 + { + p->net = nets[i]; + 803a3b8: e0bfff17 ldw r2,-4(fp) + 803a3bc: 100690ba slli r3,r2,2 + 803a3c0: 008201b4 movhi r2,2054 + 803a3c4: 1885883a add r2,r3,r2 + 803a3c8: 10f77017 ldw r3,-8768(r2) + 803a3cc: e0bff617 ldw r2,-40(fp) + 803a3d0: 10c00615 stw r3,24(r2) + break; + 803a3d4: 00000606 br 803a3f0 + for (i = 0; i < ifNumber; i++) + 803a3d8: e0bfff17 ldw r2,-4(fp) + 803a3dc: 10800044 addi r2,r2,1 + 803a3e0: e0bfff15 stw r2,-4(fp) + 803a3e4: d0a06717 ldw r2,-32356(gp) + 803a3e8: e0ffff17 ldw r3,-4(fp) + 803a3ec: 18bfeb36 bltu r3,r2,803a39c + } + } + + /* Confirm that the outgoing interface supports multicast. */ + if ((p->net == NULL) || (p->net->n_mcastlist) == NULL) + 803a3f0: e0bff617 ldw r2,-40(fp) + 803a3f4: 10800617 ldw r2,24(r2) + 803a3f8: 10000426 beq r2,zero,803a40c + 803a3fc: e0bff617 ldw r2,-40(fp) + 803a400: 10800617 ldw r2,24(r2) + 803a404: 10802b17 ldw r2,172(r2) + 803a408: 10002a1e bne r2,zero,803a4b4 + { +#ifdef NPDEBUG + if (NDEBUG & (IPTRACE|PROTERR)) + 803a40c: d0a06617 ldw r2,-32360(gp) + 803a410: 1080840c andi r2,r2,528 + 803a414: 10001a26 beq r2,zero,803a480 + { + dprintf("ip_write_internal: pkt:%p len%u to %u.%u.%u.%u, can't route\n", + 803a418: e0bff617 ldw r2,-40(fp) + 803a41c: 11400417 ldw r5,16(r2) + p, p->nb_plen, PUSH_IPADDR(p->fhost)); + 803a420: e0bff617 ldw r2,-40(fp) + 803a424: 10800717 ldw r2,28(r2) + dprintf("ip_write_internal: pkt:%p len%u to %u.%u.%u.%u, can't route\n", + 803a428: 11803fcc andi r6,r2,255 + p, p->nb_plen, PUSH_IPADDR(p->fhost)); + 803a42c: e0bff617 ldw r2,-40(fp) + 803a430: 10800717 ldw r2,28(r2) + 803a434: 1004d23a srli r2,r2,8 + dprintf("ip_write_internal: pkt:%p len%u to %u.%u.%u.%u, can't route\n", + 803a438: 10803fcc andi r2,r2,255 + p, p->nb_plen, PUSH_IPADDR(p->fhost)); + 803a43c: e0fff617 ldw r3,-40(fp) + 803a440: 18c00717 ldw r3,28(r3) + 803a444: 1806d43a srli r3,r3,16 + dprintf("ip_write_internal: pkt:%p len%u to %u.%u.%u.%u, can't route\n", + 803a448: 18c03fcc andi r3,r3,255 + p, p->nb_plen, PUSH_IPADDR(p->fhost)); + 803a44c: e13ff617 ldw r4,-40(fp) + 803a450: 21000717 ldw r4,28(r4) + 803a454: 2008d63a srli r4,r4,24 + dprintf("ip_write_internal: pkt:%p len%u to %u.%u.%u.%u, can't route\n", + 803a458: d9000215 stw r4,8(sp) + 803a45c: d8c00115 stw r3,4(sp) + 803a460: d8800015 stw r2,0(sp) + 803a464: 300f883a mov r7,r6 + 803a468: 280d883a mov r6,r5 + 803a46c: e17ff617 ldw r5,-40(fp) + 803a470: 01020174 movhi r4,2053 + 803a474: 212c2804 addi r4,r4,-20320 + 803a478: 8002c780 call 8002c78 + dtrap(); + 803a47c: 8028cd40 call 8028cd4 + } +#endif + ip_mib.ipOutNoRoutes++; + 803a480: 008201b4 movhi r2,2054 + 803a484: 10b95a17 ldw r2,-6808(r2) + 803a488: 10c00044 addi r3,r2,1 + 803a48c: 008201b4 movhi r2,2054 + 803a490: 10f95a15 stw r3,-6808(r2) + LOCK_NET_RESOURCE(FREEQ_RESID); + 803a494: 01000084 movi r4,2 + 803a498: 8028f380 call 8028f38 + pk_free(p); + 803a49c: e13ff617 ldw r4,-40(fp) + 803a4a0: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803a4a4: 01000084 movi r4,2 + 803a4a8: 8028ff40 call 8028ff4 + IN_PROFILER(PF_IP, PF_EXIT); + return (ENP_NO_ROUTE); + 803a4ac: 00bff7c4 movi r2,-33 + 803a4b0: 00014806 br 803a9d4 + * If we belong to the destination multicast group + * on the outgoing interface, and the caller did not + * forbid loopback, put a copy of the packet on the + * received queue. + */ + inm = lookup_mcast(p->fhost, p->net); + 803a4b4: e0bff617 ldw r2,-40(fp) + 803a4b8: 10c00717 ldw r3,28(r2) + 803a4bc: e0bff617 ldw r2,-40(fp) + 803a4c0: 10800617 ldw r2,24(r2) + 803a4c4: 100b883a mov r5,r2 + 803a4c8: 1809883a mov r4,r3 + 803a4cc: 803c5040 call 803c504 + 803a4d0: e0bffd15 stw r2,-12(fp) + if ((inm != NULL) && + 803a4d4: e0bffd17 ldw r2,-12(fp) + 803a4d8: 10001b26 beq r2,zero,803a548 + ((p->imo == NULL) || p->imo->imo_multicast_loop)) + 803a4dc: e0bff617 ldw r2,-40(fp) + 803a4e0: 10800b17 ldw r2,44(r2) + if ((inm != NULL) && + 803a4e4: 10000526 beq r2,zero,803a4fc + ((p->imo == NULL) || p->imo->imo_multicast_loop)) + 803a4e8: e0bff617 ldw r2,-40(fp) + 803a4ec: 10800b17 ldw r2,44(r2) + 803a4f0: 10800143 ldbu r2,5(r2) + 803a4f4: 10803fcc andi r2,r2,255 + 803a4f8: 10001326 beq r2,zero,803a548 + { + p->type = IPTP; + 803a4fc: e0bff617 ldw r2,-40(fp) + 803a500: 00c00204 movi r3,8 + 803a504: 10c0080d sth r3,32(r2) + pkt2 = ip_copypkt(p); + 803a508: e13ff617 ldw r4,-40(fp) + 803a50c: 803b53c0 call 803b53c + 803a510: e0bffc15 stw r2,-16(fp) + if (pkt2) + 803a514: e0bffc17 ldw r2,-16(fp) + 803a518: 10000b26 beq r2,zero,803a548 + { + LOCK_NET_RESOURCE(RXQ_RESID); + 803a51c: 01000044 movi r4,1 + 803a520: 8028f380 call 8028f38 + putq(&rcvdq, (q_elt)pkt2); + 803a524: e17ffc17 ldw r5,-16(fp) + 803a528: 010201b4 movhi r4,2054 + 803a52c: 2136ab04 addi r4,r4,-9556 + 803a530: 80289900 call 8028990 + UNLOCK_NET_RESOURCE(RXQ_RESID); + 803a534: 01000044 movi r4,1 + 803a538: 8028ff40 call 8028ff4 + SignalPktDemux(); + 803a53c: d0a08017 ldw r2,-32256(gp) + 803a540: 1009883a mov r4,r2 + 803a544: 8015d840 call 8015d84 + * Also, multicasts addressed to the loopback interface + * are not sent -- a copy will already have been looped + * back above if this host actually belongs to the + * destination group on the loopback interface. + */ + pip = (struct ip *)(p->nb_prot); + 803a548: e0bff617 ldw r2,-40(fp) + 803a54c: 10800317 ldw r2,12(r2) + 803a550: e0bffb15 stw r2,-20(fp) + if ((pip->ip_time == 0) || + 803a554: e0bffb17 ldw r2,-20(fp) + 803a558: 10800203 ldbu r2,8(r2) + 803a55c: 10803fcc andi r2,r2,255 + 803a560: 10000b26 beq r2,zero,803a590 + ((p->fhost & htonl(0xFF000000)) == IPLBA) || + 803a564: e0bff617 ldw r2,-40(fp) + 803a568: 10800717 ldw r2,28(r2) + 803a56c: 10803fcc andi r2,r2,255 + if ((pip->ip_time == 0) || + 803a570: 10801fe0 cmpeqi r2,r2,127 + 803a574: 1000061e bne r2,zero,803a590 + (p->fhost == p->net->n_ipaddr)) + 803a578: e0bff617 ldw r2,-40(fp) + 803a57c: 10c00717 ldw r3,28(r2) + 803a580: e0bff617 ldw r2,-40(fp) + 803a584: 10800617 ldw r2,24(r2) + 803a588: 10800a17 ldw r2,40(r2) + ((p->fhost & htonl(0xFF000000)) == IPLBA) || + 803a58c: 1880081e bne r3,r2,803a5b0 + { + LOCK_NET_RESOURCE(FREEQ_RESID); + 803a590: 01000084 movi r4,2 + 803a594: 8028f380 call 8028f38 + pk_free(p); + 803a598: e13ff617 ldw r4,-40(fp) + 803a59c: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803a5a0: 01000084 movi r4,2 + 803a5a4: 8028ff40 call 8028ff4 + IN_PROFILER(PF_IP, PF_EXIT); + return(SUCCESS); + 803a5a8: 0005883a mov r2,zero + 803a5ac: 00010906 br 803a9d4 + } + + firsthop = p->fhost; + 803a5b0: e0bff617 ldw r2,-40(fp) + 803a5b4: 10800717 ldw r2,28(r2) + 803a5b8: e0bff715 stw r2,-36(fp) + + goto sendit; + 803a5bc: 00003f06 br 803a6bc + } + +#endif /* IP_MULTICAST */ + + /* if this is a broadcast packet, use the caller-selected network */ + if (p->fhost == 0xFFFFFFFF) + 803a5c0: e0bff617 ldw r2,-40(fp) + 803a5c4: 10800717 ldw r2,28(r2) + 803a5c8: 10bfffd8 cmpnei r2,r2,-1 + 803a5cc: 1000041e bne r2,zero,803a5e0 + { + firsthop = p->fhost; + 803a5d0: e0bff617 ldw r2,-40(fp) + 803a5d4: 10800717 ldw r2,28(r2) + 803a5d8: e0bff715 stw r2,-36(fp) + 803a5dc: 00003706 br 803a6bc + } + else + { + p->net = iproute(p->fhost, &firsthop); + 803a5e0: e0bff617 ldw r2,-40(fp) + 803a5e4: 10800717 ldw r2,28(r2) + 803a5e8: e0fff704 addi r3,fp,-36 + 803a5ec: 180b883a mov r5,r3 + 803a5f0: 1009883a mov r4,r2 + 803a5f4: 803b3700 call 803b370 + 803a5f8: 1007883a mov r3,r2 + 803a5fc: e0bff617 ldw r2,-40(fp) + 803a600: 10c00615 stw r3,24(r2) + if (p->net == NULL) + 803a604: e0bff617 ldw r2,-40(fp) + 803a608: 10800617 ldw r2,24(r2) + 803a60c: 10002a1e bne r2,zero,803a6b8 + { +#ifdef NPDEBUG + if (NDEBUG & (IPTRACE|PROTERR)) + 803a610: d0a06617 ldw r2,-32360(gp) + 803a614: 1080840c andi r2,r2,528 + 803a618: 10001a26 beq r2,zero,803a684 + { + dprintf("ip_write_internal: pkt:%p len%u to %u.%u.%u.%u, can't route\n", + 803a61c: e0bff617 ldw r2,-40(fp) + 803a620: 11400417 ldw r5,16(r2) + p, p->nb_plen, PUSH_IPADDR(p->fhost)); + 803a624: e0bff617 ldw r2,-40(fp) + 803a628: 10800717 ldw r2,28(r2) + dprintf("ip_write_internal: pkt:%p len%u to %u.%u.%u.%u, can't route\n", + 803a62c: 11803fcc andi r6,r2,255 + p, p->nb_plen, PUSH_IPADDR(p->fhost)); + 803a630: e0bff617 ldw r2,-40(fp) + 803a634: 10800717 ldw r2,28(r2) + 803a638: 1004d23a srli r2,r2,8 + dprintf("ip_write_internal: pkt:%p len%u to %u.%u.%u.%u, can't route\n", + 803a63c: 10803fcc andi r2,r2,255 + p, p->nb_plen, PUSH_IPADDR(p->fhost)); + 803a640: e0fff617 ldw r3,-40(fp) + 803a644: 18c00717 ldw r3,28(r3) + 803a648: 1806d43a srli r3,r3,16 + dprintf("ip_write_internal: pkt:%p len%u to %u.%u.%u.%u, can't route\n", + 803a64c: 18c03fcc andi r3,r3,255 + p, p->nb_plen, PUSH_IPADDR(p->fhost)); + 803a650: e13ff617 ldw r4,-40(fp) + 803a654: 21000717 ldw r4,28(r4) + 803a658: 2008d63a srli r4,r4,24 + dprintf("ip_write_internal: pkt:%p len%u to %u.%u.%u.%u, can't route\n", + 803a65c: d9000215 stw r4,8(sp) + 803a660: d8c00115 stw r3,4(sp) + 803a664: d8800015 stw r2,0(sp) + 803a668: 300f883a mov r7,r6 + 803a66c: 280d883a mov r6,r5 + 803a670: e17ff617 ldw r5,-40(fp) + 803a674: 01020174 movhi r4,2053 + 803a678: 212c2804 addi r4,r4,-20320 + 803a67c: 8002c780 call 8002c78 + dtrap(); + 803a680: 8028cd40 call 8028cd4 + } +#endif /* NPDEBUG */ + ip_mib.ipOutNoRoutes++; + 803a684: 008201b4 movhi r2,2054 + 803a688: 10b95a17 ldw r2,-6808(r2) + 803a68c: 10c00044 addi r3,r2,1 + 803a690: 008201b4 movhi r2,2054 + 803a694: 10f95a15 stw r3,-6808(r2) + LOCK_NET_RESOURCE(FREEQ_RESID); + 803a698: 01000084 movi r4,2 + 803a69c: 8028f380 call 8028f38 + pk_free(p); + 803a6a0: e13ff617 ldw r4,-40(fp) + 803a6a4: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803a6a8: 01000084 movi r4,2 + 803a6ac: 8028ff40 call 8028ff4 + IN_PROFILER(PF_IP, PF_EXIT); + return (ENP_NO_ROUTE); + 803a6b0: 00bff7c4 movi r2,-33 + 803a6b4: 0000c706 br 803a9d4 + } + } + +#ifdef IP_MULTICAST +sendit: /* label used for multicast packets to skip routing logic */ + 803a6b8: 0001883a nop +#endif /* IP_MULTICAST */ + +#ifdef NPDEBUG + if (NDEBUG & IPTRACE) + 803a6bc: d0a06617 ldw r2,-32360(gp) + 803a6c0: 1080800c andi r2,r2,512 + 803a6c4: 10002926 beq r2,zero,803a76c + { + dprintf("ip_write: pkt[%u] to %u.%u.%u.%u,", + 803a6c8: e0bff617 ldw r2,-40(fp) + 803a6cc: 11000417 ldw r4,16(r2) + p->nb_plen, PUSH_IPADDR(p->fhost)); + 803a6d0: e0bff617 ldw r2,-40(fp) + 803a6d4: 10800717 ldw r2,28(r2) + dprintf("ip_write: pkt[%u] to %u.%u.%u.%u,", + 803a6d8: 11403fcc andi r5,r2,255 + p->nb_plen, PUSH_IPADDR(p->fhost)); + 803a6dc: e0bff617 ldw r2,-40(fp) + 803a6e0: 10800717 ldw r2,28(r2) + 803a6e4: 1004d23a srli r2,r2,8 + dprintf("ip_write: pkt[%u] to %u.%u.%u.%u,", + 803a6e8: 11803fcc andi r6,r2,255 + p->nb_plen, PUSH_IPADDR(p->fhost)); + 803a6ec: e0bff617 ldw r2,-40(fp) + 803a6f0: 10800717 ldw r2,28(r2) + 803a6f4: 1004d43a srli r2,r2,16 + dprintf("ip_write: pkt[%u] to %u.%u.%u.%u,", + 803a6f8: 10803fcc andi r2,r2,255 + p->nb_plen, PUSH_IPADDR(p->fhost)); + 803a6fc: e0fff617 ldw r3,-40(fp) + 803a700: 18c00717 ldw r3,28(r3) + 803a704: 1806d63a srli r3,r3,24 + dprintf("ip_write: pkt[%u] to %u.%u.%u.%u,", + 803a708: d8c00115 stw r3,4(sp) + 803a70c: d8800015 stw r2,0(sp) + 803a710: 300f883a mov r7,r6 + 803a714: 280d883a mov r6,r5 + 803a718: 200b883a mov r5,r4 + 803a71c: 01020174 movhi r4,2053 + 803a720: 212c3804 addi r4,r4,-20256 + 803a724: 8002c780 call 8002c78 + dprintf(" route %u.%u.%u.%u\n", PUSH_IPADDR(firsthop)); + 803a728: e0bff717 ldw r2,-36(fp) + 803a72c: 10c03fcc andi r3,r2,255 + 803a730: e0bff717 ldw r2,-36(fp) + 803a734: 1004d23a srli r2,r2,8 + 803a738: 11003fcc andi r4,r2,255 + 803a73c: e0bff717 ldw r2,-36(fp) + 803a740: 1004d43a srli r2,r2,16 + 803a744: 11403fcc andi r5,r2,255 + 803a748: e0bff717 ldw r2,-36(fp) + 803a74c: 1004d63a srli r2,r2,24 + 803a750: d8800015 stw r2,0(sp) + 803a754: 280f883a mov r7,r5 + 803a758: 200d883a mov r6,r4 + 803a75c: 180b883a mov r5,r3 + 803a760: 01020174 movhi r4,2053 + 803a764: 212c4104 addi r4,r4,-20220 + 803a768: 8002c780 call 8002c78 +#endif /* IPSEC */ + + /* If the packet is being sent to the same interface it will be sent + * from, short-cut things and just put it on the received queue. + */ + if ((p->net->n_ipaddr == p->fhost) && + 803a76c: e0bff617 ldw r2,-40(fp) + 803a770: 10800617 ldw r2,24(r2) + 803a774: 10c00a17 ldw r3,40(r2) + 803a778: e0bff617 ldw r2,-40(fp) + 803a77c: 10800717 ldw r2,28(r2) + 803a780: 1880271e bne r3,r2,803a820 + ((p->fhost & htonl(0xff000000)) != htonl(0x7f000000))) + 803a784: e0bff617 ldw r2,-40(fp) + 803a788: 10800717 ldw r2,28(r2) + 803a78c: 10803fcc andi r2,r2,255 + if ((p->net->n_ipaddr == p->fhost) && + 803a790: 10801fe0 cmpeqi r2,r2,127 + 803a794: 1000221e bne r2,zero,803a820 + { + if (!(p->net->n_flags & NF_NBPROT)) + 803a798: e0bff617 ldw r2,-40(fp) + 803a79c: 10800617 ldw r2,24(r2) + 803a7a0: 10802a17 ldw r2,168(r2) + 803a7a4: 1080020c andi r2,r2,8 + 803a7a8: 1000091e bne r2,zero,803a7d0 + * IP or ARP protocol header) and nb_type to the protocol + * type, and set the NF_NBPROT flag in its interfaces' + * n_flags fields. + */ +#ifdef NPDEBUG + dtrap(); + 803a7ac: 8028cd40 call 8028cd4 +#endif + LOCK_NET_RESOURCE(FREEQ_RESID); + 803a7b0: 01000084 movi r4,2 + 803a7b4: 8028f380 call 8028f38 + pk_free(p); + 803a7b8: e13ff617 ldw r4,-40(fp) + 803a7bc: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803a7c0: 01000084 movi r4,2 + 803a7c4: 8028ff40 call 8028ff4 + IN_PROFILER(PF_IP, PF_EXIT); + return ENP_LOGIC; + 803a7c8: 00bffd44 movi r2,-11 + 803a7cc: 00008106 br 803a9d4 + } + p->type = IPTP; + 803a7d0: e0bff617 ldw r2,-40(fp) + 803a7d4: 00c00204 movi r3,8 + 803a7d8: 10c0080d sth r3,32(r2) + UNLOCK_NET_RESOURCE(NET_RESID); + 803a7dc: 0009883a mov r4,zero + 803a7e0: 8028ff40 call 8028ff4 + LOCK_NET_RESOURCE(RXQ_RESID); + 803a7e4: 01000044 movi r4,1 + 803a7e8: 8028f380 call 8028f38 + putq(&rcvdq, (q_elt)p); + 803a7ec: e17ff617 ldw r5,-40(fp) + 803a7f0: 010201b4 movhi r4,2054 + 803a7f4: 2136ab04 addi r4,r4,-9556 + 803a7f8: 80289900 call 8028990 + UNLOCK_NET_RESOURCE(RXQ_RESID); + 803a7fc: 01000044 movi r4,1 + 803a800: 8028ff40 call 8028ff4 + LOCK_NET_RESOURCE(NET_RESID); + 803a804: 0009883a mov r4,zero + 803a808: 8028f380 call 8028f38 + IN_PROFILER(PF_IP, PF_EXIT); + + SignalPktDemux(); + 803a80c: d0a08017 ldw r2,-32256(gp) + 803a810: 1009883a mov r4,r2 + 803a814: 8015d840 call 8015d84 + + return SUCCESS; + 803a818: 0005883a mov r2,zero + 803a81c: 00006d06 br 803a9d4 + } + + /* determine if the buffer that needs to be transmitted is interrupt-safe */ + intrsafe_buf = ((p->flags & PKF_INTRUNSAFE) ? 0 : 1); + 803a820: e0bff617 ldw r2,-40(fp) + 803a824: 10800a17 ldw r2,40(r2) + 803a828: 1080040c andi r2,r2,16 + 803a82c: 1005003a cmpeq r2,r2,zero + 803a830: e0bffac5 stb r2,-21(fp) + /* obtain the length of the largest interrupt-safe buffer that can be + * allocated via pk_alloc () */ + maxbuflen = pk_get_max_intrsafe_buf_len (); + 803a834: 80287f40 call 80287f4 + 803a838: e0bff915 stw r2,-28(fp) + * the original buffer is interrupt-safe, we just need to consider the + * MTU of the egress interface. If the original buffer is interrupt- + * unsafe, we compute the MIN of the largest interrupt-safe buffer that + * we can use and the MTU of the egress interface (since we must satisfy + * both constraints) */ + if (!intrsafe_buf) + 803a83c: e0bffac3 ldbu r2,-21(fp) + 803a840: 1000091e bne r2,zero,803a868 + limit = MIN(maxbuflen,p->net->n_mtu); + 803a844: e0bff617 ldw r2,-40(fp) + 803a848: 10800617 ldw r2,24(r2) + 803a84c: 10800917 ldw r2,36(r2) + 803a850: 1007883a mov r3,r2 + 803a854: e0bff917 ldw r2,-28(fp) + 803a858: 1880012e bgeu r3,r2,803a860 + 803a85c: 1805883a mov r2,r3 + 803a860: e0bffe15 stw r2,-8(fp) + 803a864: 00000406 br 803a878 + else + limit = p->net->n_mtu; + 803a868: e0bff617 ldw r2,-40(fp) + 803a86c: 10800617 ldw r2,24(r2) + 803a870: 10800917 ldw r2,36(r2) + 803a874: e0bffe15 stw r2,-8(fp) + + if ((p->nb_plen + p->net->n_lnh) > limit) + 803a878: e0bff617 ldw r2,-40(fp) + 803a87c: 10800417 ldw r2,16(r2) + 803a880: e0fff617 ldw r3,-40(fp) + 803a884: 18c00617 ldw r3,24(r3) + 803a888: 18c00817 ldw r3,32(r3) + 803a88c: 10c5883a add r2,r2,r3 + 803a890: e0fffe17 ldw r3,-8(fp) + 803a894: 1880092e bgeu r3,r2,803a8bc + int err; + err = ip_fragment(p, firsthop); + IN_PROFILER(PF_IP, PF_EXIT); + return(err); +#else + dtrap(); /* this should be caught by programmers during development */ + 803a898: 8028cd40 call 8028cd4 + LOCK_NET_RESOURCE(FREEQ_RESID); + 803a89c: 01000084 movi r4,2 + 803a8a0: 8028f380 call 8028f38 + pk_free(p); + 803a8a4: e13ff617 ldw r4,-40(fp) + 803a8a8: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803a8ac: 01000084 movi r4,2 + 803a8b0: 8028ff40 call 8028ff4 + IN_PROFILER(PF_IP, PF_EXIT); + return ENP_LOGIC; + 803a8b4: 00bffd44 movi r2,-11 + 803a8b8: 00004606 br 803a9d4 + } + else + { + /* fragmentation is not required; check to see if we need to copy out of + * an interrupt-unsafe buffer */ + if (!intrsafe_buf) + 803a8bc: e0bffac3 ldbu r2,-21(fp) + 803a8c0: 1000401e bne r2,zero,803a9c4 + { + LOCK_NET_RESOURCE(FREEQ_RESID); + 803a8c4: 01000084 movi r4,2 + 803a8c8: 8028f380 call 8028f38 + newpkt = pk_alloc(p->nb_plen + p->net->n_lnh); + 803a8cc: e0bff617 ldw r2,-40(fp) + 803a8d0: 10800417 ldw r2,16(r2) + 803a8d4: e0fff617 ldw r3,-40(fp) + 803a8d8: 18c00617 ldw r3,24(r3) + 803a8dc: 18c00817 ldw r3,32(r3) + 803a8e0: 10c5883a add r2,r2,r3 + 803a8e4: 1009883a mov r4,r2 + 803a8e8: 80284340 call 8028434 + 803a8ec: e0bff815 stw r2,-32(fp) + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803a8f0: 01000084 movi r4,2 + 803a8f4: 8028ff40 call 8028ff4 + if (newpkt == 0) + 803a8f8: e0bff817 ldw r2,-32(fp) + 803a8fc: 1000081e bne r2,zero,803a920 + { + /* can't allocate interrupt-safe buffer, so free the packet that + * we are working with */ + LOCK_NET_RESOURCE(FREEQ_RESID); + 803a900: 01000084 movi r4,2 + 803a904: 8028f380 call 8028f38 + pk_free(p); + 803a908: e13ff617 ldw r4,-40(fp) + 803a90c: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803a910: 01000084 movi r4,2 + 803a914: 8028ff40 call 8028ff4 + IN_PROFILER(PF_IP, PF_EXIT); + return ENP_NOBUFFER; + 803a918: 00bffac4 movi r2,-21 + 803a91c: 00002d06 br 803a9d4 + } + else + { + /* copy from interrupt-unsafe buffer into interrupt-safe buffer */ + newpkt->nb_prot = newpkt->nb_buff + p->net->n_lnh; + 803a920: e0bff817 ldw r2,-32(fp) + 803a924: 10800117 ldw r2,4(r2) + 803a928: e0fff617 ldw r3,-40(fp) + 803a92c: 18c00617 ldw r3,24(r3) + 803a930: 18c00817 ldw r3,32(r3) + 803a934: 10c7883a add r3,r2,r3 + 803a938: e0bff817 ldw r2,-32(fp) + 803a93c: 10c00315 stw r3,12(r2) + MEMCPY(newpkt->nb_prot, p->nb_prot, p->nb_plen); + 803a940: e0bff817 ldw r2,-32(fp) + 803a944: 10c00317 ldw r3,12(r2) + 803a948: e0bff617 ldw r2,-40(fp) + 803a94c: 11000317 ldw r4,12(r2) + 803a950: e0bff617 ldw r2,-40(fp) + 803a954: 10800417 ldw r2,16(r2) + 803a958: 100d883a mov r6,r2 + 803a95c: 200b883a mov r5,r4 + 803a960: 1809883a mov r4,r3 + 803a964: 80086b80 call 80086b8 + /* setup various fields in the newly allocated PACKET structure */ + newpkt->nb_plen = p->nb_plen; + 803a968: e0bff617 ldw r2,-40(fp) + 803a96c: 10c00417 ldw r3,16(r2) + 803a970: e0bff817 ldw r2,-32(fp) + 803a974: 10c00415 stw r3,16(r2) + newpkt->net = p->net; + 803a978: e0bff617 ldw r2,-40(fp) + 803a97c: 10c00617 ldw r3,24(r2) + 803a980: e0bff817 ldw r2,-32(fp) + 803a984: 10c00615 stw r3,24(r2) + newpkt->fhost = p->fhost; + 803a988: e0bff617 ldw r2,-40(fp) + 803a98c: 10c00717 ldw r3,28(r2) + 803a990: e0bff817 ldw r2,-32(fp) + 803a994: 10c00715 stw r3,28(r2) + /* free the original packet since it is no longer needed */ + LOCK_NET_RESOURCE(FREEQ_RESID); + 803a998: 01000084 movi r4,2 + 803a99c: 8028f380 call 8028f38 + pk_free(p); + 803a9a0: e13ff617 ldw r4,-40(fp) + 803a9a4: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803a9a8: 01000084 movi r4,2 + 803a9ac: 8028ff40 call 8028ff4 + IN_PROFILER(PF_IP, PF_EXIT); + /* send packet to MAC layer. This will try to resolve MAC layer addressing + * and send packet. ip2mac() can return SUCCESS, PENDING, or error codes. + */ + return(ip2mac(newpkt, firsthop)); + 803a9b0: e0bff717 ldw r2,-36(fp) + 803a9b4: 100b883a mov r5,r2 + 803a9b8: e13ff817 ldw r4,-32(fp) + 803a9bc: 8024df40 call 8024df4 + 803a9c0: 00000406 br 803a9d4 + else + { + /* since the packet is in an interrupt-safe buffer, it can be passed to + * ip2mac () without any additional work. */ + IN_PROFILER(PF_IP, PF_EXIT); + return(ip2mac(p, firsthop)); + 803a9c4: e0bff717 ldw r2,-36(fp) + 803a9c8: 100b883a mov r5,r2 + 803a9cc: e13ff617 ldw r4,-40(fp) + 803a9d0: 8024df40 call 8024df4 + } + } +} + 803a9d4: e037883a mov sp,fp + 803a9d8: dfc00117 ldw ra,4(sp) + 803a9dc: df000017 ldw fp,0(sp) + 803a9e0: dec00204 addi sp,sp,8 + 803a9e4: f800283a ret + +0803a9e8 : + +int +ip_write( + u_char prot, + PACKET p) +{ + 803a9e8: defff904 addi sp,sp,-28 + 803a9ec: dfc00615 stw ra,24(sp) + 803a9f0: df000515 stw fp,20(sp) + 803a9f4: df000504 addi fp,sp,20 + 803a9f8: 2005883a mov r2,r4 + 803a9fc: e17ffb15 stw r5,-20(fp) + 803aa00: e0bffc05 stb r2,-16(fp) + u_char ttl; + struct ip_socopts *sopts; + + IN_PROFILER(PF_IP, PF_ENTRY); /* measure time in IP */ + + ip_mib.ipOutRequests++; + 803aa04: 008201b4 movhi r2,2054 + 803aa08: 10b95817 ldw r2,-6816(r2) + 803aa0c: 10c00044 addi r3,r2,1 + 803aa10: 008201b4 movhi r2,2054 + 803aa14: 10f95815 stw r3,-6816(r2) + + /* make room for IP header, and form a pointer to it (pip) */ + p->nb_prot -= sizeof(struct ip); + 803aa18: e0bffb17 ldw r2,-20(fp) + 803aa1c: 10800317 ldw r2,12(r2) + 803aa20: 10fffb04 addi r3,r2,-20 + 803aa24: e0bffb17 ldw r2,-20(fp) + 803aa28: 10c00315 stw r3,12(r2) + p->nb_plen += sizeof(struct ip); + 803aa2c: e0bffb17 ldw r2,-20(fp) + 803aa30: 10800417 ldw r2,16(r2) + 803aa34: 10c00504 addi r3,r2,20 + 803aa38: e0bffb17 ldw r2,-20(fp) + 803aa3c: 10c00415 stw r3,16(r2) + pip = (struct ip*)(p->nb_prot); + 803aa40: e0bffb17 ldw r2,-20(fp) + 803aa44: 10800317 ldw r2,12(r2) + 803aa48: e0bffe15 stw r2,-8(fp) + + /* build the initial IP header: + * IP source address (ip_src) and IP destination address (ip_dest) + * should already have been filled in by upper-layer protocol + */ + pip->ip_ver_ihl = 0x45; /* 2 nibbles; VER:4, IHL:5. */ + 803aa4c: e0bffe17 ldw r2,-8(fp) + 803aa50: 00c01144 movi r3,69 + 803aa54: 10c00005 stb r3,0(r2) + pip->ip_flgs_foff = 0; /* clear fragmentation info field */ + 803aa58: e0bffe17 ldw r2,-8(fp) + 803aa5c: 1000018d sth zero,6(r2) + pip->ip_id = htons((unshort)uid); + 803aa60: d0a02f17 ldw r2,-32580(gp) + 803aa64: 10bfffcc andi r2,r2,65535 + 803aa68: 1004d23a srli r2,r2,8 + 803aa6c: 1007883a mov r3,r2 + 803aa70: d0a02f17 ldw r2,-32580(gp) + 803aa74: 10bfffcc andi r2,r2,65535 + 803aa78: 1004923a slli r2,r2,8 + 803aa7c: 1884b03a or r2,r3,r2 + 803aa80: 1007883a mov r3,r2 + 803aa84: e0bffe17 ldw r2,-8(fp) + 803aa88: 10c0010d sth r3,4(r2) + uid++; + 803aa8c: d0a02f17 ldw r2,-32580(gp) + 803aa90: 10800044 addi r2,r2,1 + 803aa94: d0a02f15 stw r2,-32580(gp) + pip->ip_len = htons((unshort)(p->nb_plen)); + 803aa98: e0bffb17 ldw r2,-20(fp) + 803aa9c: 10800417 ldw r2,16(r2) + 803aaa0: 10bfffcc andi r2,r2,65535 + 803aaa4: 1004d23a srli r2,r2,8 + 803aaa8: 1007883a mov r3,r2 + 803aaac: e0bffb17 ldw r2,-20(fp) + 803aab0: 10800417 ldw r2,16(r2) + 803aab4: 10bfffcc andi r2,r2,65535 + 803aab8: 1004923a slli r2,r2,8 + 803aabc: 1884b03a or r2,r3,r2 + 803aac0: 1007883a mov r3,r2 + 803aac4: e0bffe17 ldw r2,-8(fp) + 803aac8: 10c0008d sth r3,2(r2) + pip->ip_prot = prot; + 803aacc: e0bffe17 ldw r2,-8(fp) + 803aad0: e0fffc03 ldbu r3,-16(fp) + 803aad4: 10c00245 stb r3,9(r2) + pip->ip_chksum = IPXSUM; /* clear checksum field */ + 803aad8: e0bffe17 ldw r2,-8(fp) + 803aadc: 1000028d sth zero,10(r2) + ttl = IP_TTL; + 803aae0: 00801004 movi r2,64 + 803aae4: e0bfffc5 stb r2,-1(fp) +#ifdef IP_MULTICAST + if ((IN_MULTICAST(ntohl(p->fhost))) && (p->imo != NULL)) + 803aae8: e0bffb17 ldw r2,-20(fp) + 803aaec: 10800717 ldw r2,28(r2) + 803aaf0: 1006d63a srli r3,r2,24 + 803aaf4: e0bffb17 ldw r2,-20(fp) + 803aaf8: 10800717 ldw r2,28(r2) + 803aafc: 1004d23a srli r2,r2,8 + 803ab00: 10bfc00c andi r2,r2,65280 + 803ab04: 1886b03a or r3,r3,r2 + 803ab08: e0bffb17 ldw r2,-20(fp) + 803ab0c: 10800717 ldw r2,28(r2) + 803ab10: 1004923a slli r2,r2,8 + 803ab14: 10803fec andhi r2,r2,255 + 803ab18: 1886b03a or r3,r3,r2 + 803ab1c: e0bffb17 ldw r2,-20(fp) + 803ab20: 10800717 ldw r2,28(r2) + 803ab24: 1004963a slli r2,r2,24 + 803ab28: 1884b03a or r2,r3,r2 + 803ab2c: 10fc002c andhi r3,r2,61440 + 803ab30: 00b80034 movhi r2,57344 + 803ab34: 1880071e bne r3,r2,803ab54 + 803ab38: e0bffb17 ldw r2,-20(fp) + 803ab3c: 10800b17 ldw r2,44(r2) + 803ab40: 10000426 beq r2,zero,803ab54 + ttl = p->imo->imo_multicast_ttl; + 803ab44: e0bffb17 ldw r2,-20(fp) + 803ab48: 10800b17 ldw r2,44(r2) + 803ab4c: 10800103 ldbu r2,4(r2) + 803ab50: e0bfffc5 stb r2,-1(fp) +#endif /* IP_MULTICAST */ + + /* have IP_TOS or IP_TTL been set? */ + if ((sopts = p->soxopts)) + 803ab54: e0bffb17 ldw r2,-20(fp) + 803ab58: 10800c17 ldw r2,48(r2) + 803ab5c: e0bffd15 stw r2,-12(fp) + 803ab60: e0bffd17 ldw r2,-12(fp) + 803ab64: 10001126 beq r2,zero,803abac + { + /* yup */ + if (sopts->ip_ttl) + 803ab68: e0bffd17 ldw r2,-12(fp) + 803ab6c: 10800043 ldbu r2,1(r2) + 803ab70: 10803fcc andi r2,r2,255 + 803ab74: 10000526 beq r2,zero,803ab8c + pip->ip_time = sopts->ip_ttl; + 803ab78: e0bffd17 ldw r2,-12(fp) + 803ab7c: 10c00043 ldbu r3,1(r2) + 803ab80: e0bffe17 ldw r2,-8(fp) + 803ab84: 10c00205 stb r3,8(r2) + 803ab88: 00000306 br 803ab98 + else + pip->ip_time = ttl; + 803ab8c: e0bffe17 ldw r2,-8(fp) + 803ab90: e0ffffc3 ldbu r3,-1(fp) + 803ab94: 10c00205 stb r3,8(r2) + pip->ip_tos = sopts->ip_tos; + 803ab98: e0bffd17 ldw r2,-12(fp) + 803ab9c: 10c00003 ldbu r3,0(r2) + 803aba0: e0bffe17 ldw r2,-8(fp) + 803aba4: 10c00045 stb r3,1(r2) + 803aba8: 00000506 br 803abc0 + } + else + { + /* nope */ + pip->ip_time = ttl; + 803abac: e0bffe17 ldw r2,-8(fp) + 803abb0: e0ffffc3 ldbu r3,-1(fp) + 803abb4: 10c00205 stb r3,8(r2) + pip->ip_tos = IP_TOS_DEFVAL; + 803abb8: e0bffe17 ldw r2,-8(fp) + 803abbc: 10000045 stb zero,1(r2) + } + + /* checksum the IP header */ + pip->ip_chksum = ~cksum(pip, 10); + 803abc0: 01400284 movi r5,10 + 803abc4: e13ffe17 ldw r4,-8(fp) + 803abc8: 8026d7c0 call 8026d7c + 803abcc: 0084303a nor r2,zero,r2 + 803abd0: 1007883a mov r3,r2 + 803abd4: e0bffe17 ldw r2,-8(fp) + 803abd8: 10c0028d sth r3,10(r2) + + /* do the actual write */ + return (ip_write_internal(p)); + 803abdc: e13ffb17 ldw r4,-20(fp) + 803abe0: 803a2d40 call 803a2d4 +} + 803abe4: e037883a mov sp,fp + 803abe8: dfc00117 ldw ra,4(sp) + 803abec: df000017 ldw fp,0(sp) + 803abf0: dec00204 addi sp,sp,8 + 803abf4: f800283a ret + +0803abf8 : + * OUTPUT: This function returns the return code from + * ip_write_internal (). + */ + +int ip_write2 (u_char prot, PACKET p, u_char * optp) +{ + 803abf8: defff604 addi sp,sp,-40 + 803abfc: dfc00915 stw ra,36(sp) + 803ac00: df000815 stw fp,32(sp) + 803ac04: df000804 addi fp,sp,32 + 803ac08: 2005883a mov r2,r4 + 803ac0c: e17ff915 stw r5,-28(fp) + 803ac10: e1bff815 stw r6,-32(fp) + 803ac14: e0bffa05 stb r2,-24(fp) + struct ip * pip; + u_char ttl; + struct ip_socopts * sopts; + u_char iphlen = sizeof (struct ip); + 803ac18: 00800504 movi r2,20 + 803ac1c: e0bfff85 stb r2,-2(fp) + u_char iphlen_pad; + u_char i; + + IN_PROFILER(PF_IP, PF_ENTRY); /* measure time in IP */ + + ip_mib.ipOutRequests++; + 803ac20: 008201b4 movhi r2,2054 + 803ac24: 10b95817 ldw r2,-6816(r2) + 803ac28: 10c00044 addi r3,r2,1 + 803ac2c: 008201b4 movhi r2,2054 + 803ac30: 10f95815 stw r3,-6816(r2) + + /* compute the total length of the options requested */ + for (tmpp = optp; (*tmpp) != EOL_OPT; ++tmpp) + 803ac34: e0bff817 ldw r2,-32(fp) + 803ac38: e0bffe15 stw r2,-8(fp) + 803ac3c: 00000d06 br 803ac74 + { + /* account for options, if any (caller has already created + * adequate space for the requested option) */ + switch (*tmpp) + 803ac40: e0bffe17 ldw r2,-8(fp) + 803ac44: 10800003 ldbu r2,0(r2) + 803ac48: 10803fcc andi r2,r2,255 + 803ac4c: 10800518 cmpnei r2,r2,20 + 803ac50: 1000041e bne r2,zero,803ac64 + { + case IP_RTR_ALERT_OPT: + iphlen += IP_RTR_ALERT_OPT_SIZE; + 803ac54: e0bfff83 ldbu r2,-2(fp) + 803ac58: 10800104 addi r2,r2,4 + 803ac5c: e0bfff85 stb r2,-2(fp) + break; + 803ac60: 00000106 br 803ac68 + default: + break; + 803ac64: 0001883a nop + for (tmpp = optp; (*tmpp) != EOL_OPT; ++tmpp) + 803ac68: e0bffe17 ldw r2,-8(fp) + 803ac6c: 10800044 addi r2,r2,1 + 803ac70: e0bffe15 stw r2,-8(fp) + 803ac74: e0bffe17 ldw r2,-8(fp) + 803ac78: 10800003 ldbu r2,0(r2) + 803ac7c: 10803fcc andi r2,r2,255 + 803ac80: 103fef1e bne r2,zero,803ac40 + } + + /* compute the amount of padding required, if any (to ensure + * that the IP header (including options) ends on a dword + * (four byte) boundary */ + if (iphlen & 0x3) + 803ac84: e0bfff83 ldbu r2,-2(fp) + 803ac88: 108000cc andi r2,r2,3 + 803ac8c: 10000726 beq r2,zero,803acac + iphlen_pad = 4 - (iphlen & 0x3); + 803ac90: e0bfff83 ldbu r2,-2(fp) + 803ac94: 108000cc andi r2,r2,3 + 803ac98: 1007883a mov r3,r2 + 803ac9c: 00800104 movi r2,4 + 803aca0: 10c5c83a sub r2,r2,r3 + 803aca4: e0bffdc5 stb r2,-9(fp) + 803aca8: 00000106 br 803acb0 + else iphlen_pad = 0; /* no header padding required */ + 803acac: e03ffdc5 stb zero,-9(fp) + /* the packet passed to ip_write2 () has its nb_prot set to + * point to start of the protocol's (e.g., IGMP) data, and + * nb_plen set to the length of that data. locate start of + * the IP header (account for IP options), and form a pointer + * to it (pip) */ + p->nb_prot -= (iphlen + iphlen_pad); + 803acb0: e0bff917 ldw r2,-28(fp) + 803acb4: 10c00317 ldw r3,12(r2) + 803acb8: e13fff83 ldbu r4,-2(fp) + 803acbc: e0bffdc3 ldbu r2,-9(fp) + 803acc0: 2085883a add r2,r4,r2 + 803acc4: 0085c83a sub r2,zero,r2 + 803acc8: 1887883a add r3,r3,r2 + 803accc: e0bff917 ldw r2,-28(fp) + 803acd0: 10c00315 stw r3,12(r2) + /* add padding length to the total length of the IP datagram */ + p->nb_plen += (iphlen + iphlen_pad); + 803acd4: e0bff917 ldw r2,-28(fp) + 803acd8: 10800417 ldw r2,16(r2) + 803acdc: e13fff83 ldbu r4,-2(fp) + 803ace0: e0fffdc3 ldbu r3,-9(fp) + 803ace4: 20c7883a add r3,r4,r3 + 803ace8: 10c7883a add r3,r2,r3 + 803acec: e0bff917 ldw r2,-28(fp) + 803acf0: 10c00415 stw r3,16(r2) + pip = (struct ip *) (p->nb_prot); + 803acf4: e0bff917 ldw r2,-28(fp) + 803acf8: 10800317 ldw r2,12(r2) + 803acfc: e0bffc15 stw r2,-16(fp) + + /* build the initial IP header: + * IP source address (ip_src) and IP destination address (ip_dest) + * should already have been filled in by upper-layer protocol + */ + pip->ip_ver_ihl = ((IP_VER << 4) | ((iphlen + iphlen_pad) >> 2)); + 803ad00: e0ffff83 ldbu r3,-2(fp) + 803ad04: e0bffdc3 ldbu r2,-9(fp) + 803ad08: 1885883a add r2,r3,r2 + 803ad0c: 1005d0ba srai r2,r2,2 + 803ad10: 10801014 ori r2,r2,64 + 803ad14: 1007883a mov r3,r2 + 803ad18: e0bffc17 ldw r2,-16(fp) + 803ad1c: 10c00005 stb r3,0(r2) + pip->ip_flgs_foff = 0; /* clear fragmentation info field */ + 803ad20: e0bffc17 ldw r2,-16(fp) + 803ad24: 1000018d sth zero,6(r2) + pip->ip_id = htons((unshort)uid); + 803ad28: d0a02f17 ldw r2,-32580(gp) + 803ad2c: 10bfffcc andi r2,r2,65535 + 803ad30: 1004d23a srli r2,r2,8 + 803ad34: 1007883a mov r3,r2 + 803ad38: d0a02f17 ldw r2,-32580(gp) + 803ad3c: 10bfffcc andi r2,r2,65535 + 803ad40: 1004923a slli r2,r2,8 + 803ad44: 1884b03a or r2,r3,r2 + 803ad48: 1007883a mov r3,r2 + 803ad4c: e0bffc17 ldw r2,-16(fp) + 803ad50: 10c0010d sth r3,4(r2) + uid++; + 803ad54: d0a02f17 ldw r2,-32580(gp) + 803ad58: 10800044 addi r2,r2,1 + 803ad5c: d0a02f15 stw r2,-32580(gp) + pip->ip_len = htons((unshort)(p->nb_plen)); + 803ad60: e0bff917 ldw r2,-28(fp) + 803ad64: 10800417 ldw r2,16(r2) + 803ad68: 10bfffcc andi r2,r2,65535 + 803ad6c: 1004d23a srli r2,r2,8 + 803ad70: 1007883a mov r3,r2 + 803ad74: e0bff917 ldw r2,-28(fp) + 803ad78: 10800417 ldw r2,16(r2) + 803ad7c: 10bfffcc andi r2,r2,65535 + 803ad80: 1004923a slli r2,r2,8 + 803ad84: 1884b03a or r2,r3,r2 + 803ad88: 1007883a mov r3,r2 + 803ad8c: e0bffc17 ldw r2,-16(fp) + 803ad90: 10c0008d sth r3,2(r2) + pip->ip_prot = prot; + 803ad94: e0bffc17 ldw r2,-16(fp) + 803ad98: e0fffa03 ldbu r3,-24(fp) + 803ad9c: 10c00245 stb r3,9(r2) + pip->ip_chksum = IPXSUM; /* clear checksum field */ + 803ada0: e0bffc17 ldw r2,-16(fp) + 803ada4: 1000028d sth zero,10(r2) + ttl = IP_TTL; + 803ada8: 00801004 movi r2,64 + 803adac: e0bfffc5 stb r2,-1(fp) +#ifdef IP_MULTICAST + if ((IN_MULTICAST(ntohl(p->fhost))) && (p->imo != NULL)) + 803adb0: e0bff917 ldw r2,-28(fp) + 803adb4: 10800717 ldw r2,28(r2) + 803adb8: 1006d63a srli r3,r2,24 + 803adbc: e0bff917 ldw r2,-28(fp) + 803adc0: 10800717 ldw r2,28(r2) + 803adc4: 1004d23a srli r2,r2,8 + 803adc8: 10bfc00c andi r2,r2,65280 + 803adcc: 1886b03a or r3,r3,r2 + 803add0: e0bff917 ldw r2,-28(fp) + 803add4: 10800717 ldw r2,28(r2) + 803add8: 1004923a slli r2,r2,8 + 803addc: 10803fec andhi r2,r2,255 + 803ade0: 1886b03a or r3,r3,r2 + 803ade4: e0bff917 ldw r2,-28(fp) + 803ade8: 10800717 ldw r2,28(r2) + 803adec: 1004963a slli r2,r2,24 + 803adf0: 1884b03a or r2,r3,r2 + 803adf4: 10fc002c andhi r3,r2,61440 + 803adf8: 00b80034 movhi r2,57344 + 803adfc: 1880071e bne r3,r2,803ae1c + 803ae00: e0bff917 ldw r2,-28(fp) + 803ae04: 10800b17 ldw r2,44(r2) + 803ae08: 10000426 beq r2,zero,803ae1c + ttl = p->imo->imo_multicast_ttl; + 803ae0c: e0bff917 ldw r2,-28(fp) + 803ae10: 10800b17 ldw r2,44(r2) + 803ae14: 10800103 ldbu r2,4(r2) + 803ae18: e0bfffc5 stb r2,-1(fp) +#endif /* IP_MULTICAST */ + + /* have TOS or TTL been set (via socket options)? */ + if ((sopts = p->soxopts)) + 803ae1c: e0bff917 ldw r2,-28(fp) + 803ae20: 10800c17 ldw r2,48(r2) + 803ae24: e0bffb15 stw r2,-20(fp) + 803ae28: e0bffb17 ldw r2,-20(fp) + 803ae2c: 10001126 beq r2,zero,803ae74 + { + if (sopts->ip_ttl) + 803ae30: e0bffb17 ldw r2,-20(fp) + 803ae34: 10800043 ldbu r2,1(r2) + 803ae38: 10803fcc andi r2,r2,255 + 803ae3c: 10000526 beq r2,zero,803ae54 + pip->ip_time = sopts->ip_ttl; + 803ae40: e0bffb17 ldw r2,-20(fp) + 803ae44: 10c00043 ldbu r3,1(r2) + 803ae48: e0bffc17 ldw r2,-16(fp) + 803ae4c: 10c00205 stb r3,8(r2) + 803ae50: 00000306 br 803ae60 + else + pip->ip_time = ttl; + 803ae54: e0bffc17 ldw r2,-16(fp) + 803ae58: e0ffffc3 ldbu r3,-1(fp) + 803ae5c: 10c00205 stb r3,8(r2) + pip->ip_tos = sopts->ip_tos; + 803ae60: e0bffb17 ldw r2,-20(fp) + 803ae64: 10c00003 ldbu r3,0(r2) + 803ae68: e0bffc17 ldw r2,-16(fp) + 803ae6c: 10c00045 stb r3,1(r2) + 803ae70: 00000506 br 803ae88 + } + else + { + pip->ip_time = ttl; + 803ae74: e0bffc17 ldw r2,-16(fp) + 803ae78: e0ffffc3 ldbu r3,-1(fp) + 803ae7c: 10c00205 stb r3,8(r2) + pip->ip_tos = IP_TOS_DEFVAL; + 803ae80: e0bffc17 ldw r2,-16(fp) + 803ae84: 10000045 stb zero,1(r2) + } + + /* point to the start of the IP options, and insert the options */ + for (tmpp = (u_char *)(p->nb_prot + sizeof(struct ip)); *optp != EOL_OPT; ++optp) + 803ae88: e0bff917 ldw r2,-28(fp) + 803ae8c: 10800317 ldw r2,12(r2) + 803ae90: 10800504 addi r2,r2,20 + 803ae94: e0bffe15 stw r2,-8(fp) + 803ae98: 00001006 br 803aedc + { + /* caller has already provided adequate space for the requested options */ + switch (*optp) + 803ae9c: e0bff817 ldw r2,-32(fp) + 803aea0: 10800003 ldbu r2,0(r2) + 803aea4: 10803fcc andi r2,r2,255 + 803aea8: 10800518 cmpnei r2,r2,20 + 803aeac: 1000071e bne r2,zero,803aecc + { + case IP_RTR_ALERT_OPT: + *((u_long *) tmpp) = htonl (IP_RTR_ALERT_OPT_DATA); + 803aeb0: e0bffe17 ldw r2,-8(fp) + 803aeb4: 00c12504 movi r3,1172 + 803aeb8: 10c00015 stw r3,0(r2) + /* this option is 4 bytes long */ + tmpp += IP_RTR_ALERT_OPT_SIZE; + 803aebc: e0bffe17 ldw r2,-8(fp) + 803aec0: 10800104 addi r2,r2,4 + 803aec4: e0bffe15 stw r2,-8(fp) + break; + 803aec8: 00000106 br 803aed0 + default: + break; + 803aecc: 0001883a nop + for (tmpp = (u_char *)(p->nb_prot + sizeof(struct ip)); *optp != EOL_OPT; ++optp) + 803aed0: e0bff817 ldw r2,-32(fp) + 803aed4: 10800044 addi r2,r2,1 + 803aed8: e0bff815 stw r2,-32(fp) + 803aedc: e0bff817 ldw r2,-32(fp) + 803aee0: 10800003 ldbu r2,0(r2) + 803aee4: 10803fcc andi r2,r2,255 + 803aee8: 103fec1e bne r2,zero,803ae9c + } + } + + /* add one (or more) one-byte long End of Option options (if required) */ + for (i = 0; i < iphlen_pad; ++i) *(tmpp + i) = 0; + 803aeec: e03ffd85 stb zero,-10(fp) + 803aef0: 00000706 br 803af10 + 803aef4: e0bffd83 ldbu r2,-10(fp) + 803aef8: e0fffe17 ldw r3,-8(fp) + 803aefc: 1885883a add r2,r3,r2 + 803af00: 10000005 stb zero,0(r2) + 803af04: e0bffd83 ldbu r2,-10(fp) + 803af08: 10800044 addi r2,r2,1 + 803af0c: e0bffd85 stb r2,-10(fp) + 803af10: e0fffd83 ldbu r3,-10(fp) + 803af14: e0bffdc3 ldbu r2,-9(fp) + 803af18: 18bff636 bltu r3,r2,803aef4 + + /* checksum the IP header */ + pip->ip_chksum = ~cksum (pip, ((iphlen + iphlen_pad)/2)); + 803af1c: e0ffff83 ldbu r3,-2(fp) + 803af20: e0bffdc3 ldbu r2,-9(fp) + 803af24: 1885883a add r2,r3,r2 + 803af28: 1006d7fa srli r3,r2,31 + 803af2c: 1885883a add r2,r3,r2 + 803af30: 1005d07a srai r2,r2,1 + 803af34: 100b883a mov r5,r2 + 803af38: e13ffc17 ldw r4,-16(fp) + 803af3c: 8026d7c0 call 8026d7c + 803af40: 0084303a nor r2,zero,r2 + 803af44: 1007883a mov r3,r2 + 803af48: e0bffc17 ldw r2,-16(fp) + 803af4c: 10c0028d sth r3,10(r2) + + /* do the actual write */ + return (ip_write_internal (p)); + 803af50: e13ff917 ldw r4,-28(fp) + 803af54: 803a2d40 call 803a2d4 +} + 803af58: e037883a mov sp,fp + 803af5c: dfc00117 ldw ra,4(sp) + 803af60: df000017 ldw fp,0(sp) + 803af64: dec00204 addi sp,sp,8 + 803af68: f800283a ret + +0803af6c : + * RETURNS: Returns 0 if sent OK, ENP_SEND_PENDING (1) if + * waiting for ARP, else negative error code if error detected. + */ +int +ip_raw_write(PACKET p) +{ + 803af6c: defffc04 addi sp,sp,-16 + 803af70: dfc00315 stw ra,12(sp) + 803af74: df000215 stw fp,8(sp) + 803af78: df000204 addi fp,sp,8 + 803af7c: e13ffe15 stw r4,-8(fp) + struct ip * pip; + + IN_PROFILER(PF_IP, PF_ENTRY); /* measure time in IP */ + + ip_mib.ipOutRequests++; + 803af80: 008201b4 movhi r2,2054 + 803af84: 10b95817 ldw r2,-6816(r2) + 803af88: 10c00044 addi r3,r2,1 + 803af8c: 008201b4 movhi r2,2054 + 803af90: 10f95815 stw r3,-6816(r2) + + /* form a pointer to IP header (pip) */ + pip = (struct ip*)(p->nb_prot); + 803af94: e0bffe17 ldw r2,-8(fp) + 803af98: 10800317 ldw r2,12(r2) + 803af9c: e0bfff15 stw r2,-4(fp) + + /* if there's no IP id, give it one */ + if (pip->ip_id == 0) + 803afa0: e0bfff17 ldw r2,-4(fp) + 803afa4: 1080010b ldhu r2,4(r2) + 803afa8: 10bfffcc andi r2,r2,65535 + 803afac: 10000e1e bne r2,zero,803afe8 + { + pip->ip_id = htons((unshort)uid); + 803afb0: d0a02f17 ldw r2,-32580(gp) + 803afb4: 10bfffcc andi r2,r2,65535 + 803afb8: 1004d23a srli r2,r2,8 + 803afbc: 1007883a mov r3,r2 + 803afc0: d0a02f17 ldw r2,-32580(gp) + 803afc4: 10bfffcc andi r2,r2,65535 + 803afc8: 1004923a slli r2,r2,8 + 803afcc: 1884b03a or r2,r3,r2 + 803afd0: 1007883a mov r3,r2 + 803afd4: e0bfff17 ldw r2,-4(fp) + 803afd8: 10c0010d sth r3,4(r2) + uid++; + 803afdc: d0a02f17 ldw r2,-32580(gp) + 803afe0: 10800044 addi r2,r2,1 + 803afe4: d0a02f15 stw r2,-32580(gp) + } + + /* checksum the IP header */ + pip->ip_chksum = IPXSUM; /* clear checksum field */ + 803afe8: e0bfff17 ldw r2,-4(fp) + 803afec: 1000028d sth zero,10(r2) + pip->ip_chksum = ~cksum(pip, 10); + 803aff0: 01400284 movi r5,10 + 803aff4: e13fff17 ldw r4,-4(fp) + 803aff8: 8026d7c0 call 8026d7c + 803affc: 0084303a nor r2,zero,r2 + 803b000: 1007883a mov r3,r2 + 803b004: e0bfff17 ldw r2,-4(fp) + 803b008: 10c0028d sth r3,10(r2) + + /* do the actual write */ + return (ip_write_internal(p)); + 803b00c: e13ffe17 ldw r4,-8(fp) + 803b010: 803a2d40 call 803a2d4 +} + 803b014: e037883a mov sp,fp + 803b018: dfc00117 ldw ra,4(sp) + 803b01c: df000017 ldw fp,0(sp) + 803b020: dec00204 addi sp,sp,8 + 803b024: f800283a ret + +0803b028 : + * certain foreign host. + */ + +ip_addr +ip_mymach(ip_addr host) +{ + 803b028: defffa04 addi sp,sp,-24 + 803b02c: dfc00515 stw ra,20(sp) + 803b030: df000415 stw fp,16(sp) + 803b034: df000404 addi fp,sp,16 + 803b038: e13ffd15 stw r4,-12(fp) + +#ifndef MULTI_HOMED /* single static interface */ + USE_ARG(host); + return(nets[0]->n_ipaddr); /* always use address from only net */ +#else /* MULTI_HOMED */ + tnet = iproute(host, &temp); + 803b03c: e0bffe04 addi r2,fp,-8 + 803b040: 100b883a mov r5,r2 + 803b044: e13ffd17 ldw r4,-12(fp) + 803b048: 803b3700 call 803b370 + 803b04c: e0bfff15 stw r2,-4(fp) + if (tnet == 0) + 803b050: e0bfff17 ldw r2,-4(fp) + 803b054: 1000161e bne r2,zero,803b0b0 + { +#ifdef NPDEBUG + if (NDEBUG & (PROTERR|INFOMSG)) + 803b058: d0a06617 ldw r2,-32360(gp) + 803b05c: 1080050c andi r2,r2,20 + 803b060: 10001126 beq r2,zero,803b0a8 + dprintf("IP: Couldn't route to %u.%u.%u.%u\n", PUSH_IPADDR(host)); + 803b064: e0bffd17 ldw r2,-12(fp) + 803b068: 10c03fcc andi r3,r2,255 + 803b06c: e0bffd17 ldw r2,-12(fp) + 803b070: 1004d23a srli r2,r2,8 + 803b074: 11003fcc andi r4,r2,255 + 803b078: e0bffd17 ldw r2,-12(fp) + 803b07c: 1004d43a srli r2,r2,16 + 803b080: 11403fcc andi r5,r2,255 + 803b084: e0bffd17 ldw r2,-12(fp) + 803b088: 1004d63a srli r2,r2,24 + 803b08c: d8800015 stw r2,0(sp) + 803b090: 280f883a mov r7,r5 + 803b094: 200d883a mov r6,r4 + 803b098: 180b883a mov r5,r3 + 803b09c: 01020174 movhi r4,2053 + 803b0a0: 212c4604 addi r4,r4,-20200 + 803b0a4: 8002c780 call 8002c78 +#endif /* NPDEBUG */ + return 0L; + 803b0a8: 0005883a mov r2,zero + 803b0ac: 00000206 br 803b0b8 + } + return tnet->n_ipaddr; + 803b0b0: e0bfff17 ldw r2,-4(fp) + 803b0b4: 10800a17 ldw r2,40(r2) +#endif /* MULTI_HOMED */ +} + 803b0b8: e037883a mov sp,fp + 803b0bc: dfc00117 ldw ra,4(sp) + 803b0c0: df000017 ldw fp,0(sp) + 803b0c4: dec00204 addi sp,sp,8 + 803b0c8: f800283a ret + +0803b0cc : + * RETURNS: void + */ + +void +ip_dump(PACKET p) +{ + 803b0cc: defff704 addi sp,sp,-36 + 803b0d0: dfc00815 stw ra,32(sp) + 803b0d4: df000715 stw fp,28(sp) + 803b0d8: df000704 addi fp,sp,28 + 803b0dc: e13ffc15 stw r4,-16(fp) + struct ip * pip; + unsigned char * cp; + unsigned short xsum, osum; + + pip = ip_head(p); + 803b0e0: e0bffc17 ldw r2,-16(fp) + 803b0e4: 10800317 ldw r2,12(r2) + 803b0e8: e0bfff15 stw r2,-4(fp) + osum = pip->ip_chksum; + 803b0ec: e0bfff17 ldw r2,-4(fp) + 803b0f0: 1080028b ldhu r2,10(r2) + 803b0f4: e0bffe8d sth r2,-6(fp) + pip->ip_chksum = 0; + 803b0f8: e0bfff17 ldw r2,-4(fp) + 803b0fc: 1000028d sth zero,10(r2) + xsum = ~cksum(pip, ip_hlen(pip) >> 1); + 803b100: e0bfff17 ldw r2,-4(fp) + 803b104: 10800003 ldbu r2,0(r2) + 803b108: 10803fcc andi r2,r2,255 + 803b10c: 100490ba slli r2,r2,2 + 803b110: 1005d07a srai r2,r2,1 + 803b114: 1080078c andi r2,r2,30 + 803b118: 100b883a mov r5,r2 + 803b11c: e13fff17 ldw r4,-4(fp) + 803b120: 8026d7c0 call 8026d7c + 803b124: 0084303a nor r2,zero,r2 + 803b128: e0bffe0d sth r2,-8(fp) + + if (osum != xsum) /* trap here if checksum is wrong */ + 803b12c: e0fffe8b ldhu r3,-6(fp) + 803b130: e0bffe0b ldhu r2,-8(fp) + 803b134: 18800126 beq r3,r2,803b13c + { + dtrap(); + 803b138: 8028cd40 call 8028cd4 + /* dtrap() is fatal in the default Windows implementation, so + * we comment it out */ + dtrap(); /* use debugger to view variables & packet */ +#endif + + ns_printf(NULL ,"IP packet header:\n"); + 803b13c: 01420174 movhi r5,2053 + 803b140: 296c4f04 addi r5,r5,-20164 + 803b144: 0009883a mov r4,zero + 803b148: 80273900 call 8027390 + cp = (unsigned char *)pip; /* make char pointer for bitmasks */ + 803b14c: e0bfff17 ldw r2,-4(fp) + 803b150: e0bffd15 stw r2,-12(fp) + ns_printf(NULL ,"ver/hlen: %02x, TOS: %02x, len: %04x, id: %04x\n", + *cp, *(cp+1), htons(pip->ip_len), htons(pip->ip_id)); + 803b154: e0bffd17 ldw r2,-12(fp) + 803b158: 10800003 ldbu r2,0(r2) + ns_printf(NULL ,"ver/hlen: %02x, TOS: %02x, len: %04x, id: %04x\n", + 803b15c: 11403fcc andi r5,r2,255 + *cp, *(cp+1), htons(pip->ip_len), htons(pip->ip_id)); + 803b160: e0bffd17 ldw r2,-12(fp) + 803b164: 10800044 addi r2,r2,1 + 803b168: 10800003 ldbu r2,0(r2) + ns_printf(NULL ,"ver/hlen: %02x, TOS: %02x, len: %04x, id: %04x\n", + 803b16c: 11803fcc andi r6,r2,255 + *cp, *(cp+1), htons(pip->ip_len), htons(pip->ip_id)); + 803b170: e0bfff17 ldw r2,-4(fp) + 803b174: 1080008b ldhu r2,2(r2) + 803b178: 10bfffcc andi r2,r2,65535 + 803b17c: 1004d23a srli r2,r2,8 + 803b180: 10bfffcc andi r2,r2,65535 + 803b184: 10c03fcc andi r3,r2,255 + 803b188: e0bfff17 ldw r2,-4(fp) + 803b18c: 1080008b ldhu r2,2(r2) + 803b190: 10bfffcc andi r2,r2,65535 + 803b194: 1004923a slli r2,r2,8 + 803b198: 10bfffcc andi r2,r2,65535 + ns_printf(NULL ,"ver/hlen: %02x, TOS: %02x, len: %04x, id: %04x\n", + 803b19c: 1884b03a or r2,r3,r2 + *cp, *(cp+1), htons(pip->ip_len), htons(pip->ip_id)); + 803b1a0: e0ffff17 ldw r3,-4(fp) + 803b1a4: 18c0010b ldhu r3,4(r3) + 803b1a8: 18ffffcc andi r3,r3,65535 + 803b1ac: 1806d23a srli r3,r3,8 + 803b1b0: 18ffffcc andi r3,r3,65535 + 803b1b4: 19003fcc andi r4,r3,255 + 803b1b8: e0ffff17 ldw r3,-4(fp) + 803b1bc: 18c0010b ldhu r3,4(r3) + 803b1c0: 18ffffcc andi r3,r3,65535 + 803b1c4: 1806923a slli r3,r3,8 + 803b1c8: 18ffffcc andi r3,r3,65535 + ns_printf(NULL ,"ver/hlen: %02x, TOS: %02x, len: %04x, id: %04x\n", + 803b1cc: 20c6b03a or r3,r4,r3 + 803b1d0: d8c00115 stw r3,4(sp) + 803b1d4: d8800015 stw r2,0(sp) + 803b1d8: 300f883a mov r7,r6 + 803b1dc: 280d883a mov r6,r5 + 803b1e0: 01420174 movhi r5,2053 + 803b1e4: 296c5404 addi r5,r5,-20144 + 803b1e8: 0009883a mov r4,zero + 803b1ec: 80273900 call 8027390 + ns_printf(NULL ,"flags/offs: %04x, TTL %02x, protocol: %02x, cksum: %04x (%s)\n", + htons(*(unshort*)(cp+6)), pip->ip_time, pip->ip_prot, + 803b1f0: e0bffd17 ldw r2,-12(fp) + 803b1f4: 10800184 addi r2,r2,6 + 803b1f8: 1080000b ldhu r2,0(r2) + 803b1fc: 10bfffcc andi r2,r2,65535 + 803b200: 1004d23a srli r2,r2,8 + 803b204: 10bfffcc andi r2,r2,65535 + 803b208: 10c03fcc andi r3,r2,255 + 803b20c: e0bffd17 ldw r2,-12(fp) + 803b210: 10800184 addi r2,r2,6 + 803b214: 1080000b ldhu r2,0(r2) + 803b218: 10bfffcc andi r2,r2,65535 + 803b21c: 1004923a slli r2,r2,8 + 803b220: 10bfffcc andi r2,r2,65535 + ns_printf(NULL ,"flags/offs: %04x, TTL %02x, protocol: %02x, cksum: %04x (%s)\n", + 803b224: 188cb03a or r6,r3,r2 + htons(*(unshort*)(cp+6)), pip->ip_time, pip->ip_prot, + 803b228: e0bfff17 ldw r2,-4(fp) + 803b22c: 10800203 ldbu r2,8(r2) + ns_printf(NULL ,"flags/offs: %04x, TTL %02x, protocol: %02x, cksum: %04x (%s)\n", + 803b230: 11c03fcc andi r7,r2,255 + htons(*(unshort*)(cp+6)), pip->ip_time, pip->ip_prot, + 803b234: e0bfff17 ldw r2,-4(fp) + 803b238: 10800243 ldbu r2,9(r2) + ns_printf(NULL ,"flags/offs: %04x, TTL %02x, protocol: %02x, cksum: %04x (%s)\n", + 803b23c: 10c03fcc andi r3,r2,255 + htons(osum), (osum==xsum)?"ok":"bad"); + 803b240: e0bffe8b ldhu r2,-6(fp) + 803b244: 1004d23a srli r2,r2,8 + 803b248: 10bfffcc andi r2,r2,65535 + 803b24c: 11003fcc andi r4,r2,255 + 803b250: e0bffe8b ldhu r2,-6(fp) + 803b254: 1004923a slli r2,r2,8 + 803b258: 10bfffcc andi r2,r2,65535 + ns_printf(NULL ,"flags/offs: %04x, TTL %02x, protocol: %02x, cksum: %04x (%s)\n", + 803b25c: 2088b03a or r4,r4,r2 + 803b260: e17ffe8b ldhu r5,-6(fp) + 803b264: e0bffe0b ldhu r2,-8(fp) + 803b268: 2880031e bne r5,r2,803b278 + 803b26c: 00820174 movhi r2,2053 + 803b270: 10ac6004 addi r2,r2,-20096 + 803b274: 00000206 br 803b280 + 803b278: 00820174 movhi r2,2053 + 803b27c: 10ac6104 addi r2,r2,-20092 + 803b280: d8800215 stw r2,8(sp) + 803b284: d9000115 stw r4,4(sp) + 803b288: d8c00015 stw r3,0(sp) + 803b28c: 01420174 movhi r5,2053 + 803b290: 296c6204 addi r5,r5,-20088 + 803b294: 0009883a mov r4,zero + 803b298: 80273900 call 8027390 + ns_printf(NULL ,"src: %u.%u.%u.%u ", PUSH_IPADDR(pip->ip_src)); + 803b29c: e0bfff17 ldw r2,-4(fp) + 803b2a0: 10800317 ldw r2,12(r2) + 803b2a4: 11003fcc andi r4,r2,255 + 803b2a8: e0bfff17 ldw r2,-4(fp) + 803b2ac: 10800317 ldw r2,12(r2) + 803b2b0: 1004d23a srli r2,r2,8 + 803b2b4: 11403fcc andi r5,r2,255 + 803b2b8: e0bfff17 ldw r2,-4(fp) + 803b2bc: 10800317 ldw r2,12(r2) + 803b2c0: 1004d43a srli r2,r2,16 + 803b2c4: 10803fcc andi r2,r2,255 + 803b2c8: e0ffff17 ldw r3,-4(fp) + 803b2cc: 18c00317 ldw r3,12(r3) + 803b2d0: 1806d63a srli r3,r3,24 + 803b2d4: d8c00115 stw r3,4(sp) + 803b2d8: d8800015 stw r2,0(sp) + 803b2dc: 280f883a mov r7,r5 + 803b2e0: 200d883a mov r6,r4 + 803b2e4: 01420174 movhi r5,2053 + 803b2e8: 296c7204 addi r5,r5,-20024 + 803b2ec: 0009883a mov r4,zero + 803b2f0: 80273900 call 8027390 + ns_printf(NULL ,"dest: %u.%u.%u.%u\n", PUSH_IPADDR(pip->ip_dest)); + 803b2f4: e0bfff17 ldw r2,-4(fp) + 803b2f8: 10800417 ldw r2,16(r2) + 803b2fc: 11003fcc andi r4,r2,255 + 803b300: e0bfff17 ldw r2,-4(fp) + 803b304: 10800417 ldw r2,16(r2) + 803b308: 1004d23a srli r2,r2,8 + 803b30c: 11403fcc andi r5,r2,255 + 803b310: e0bfff17 ldw r2,-4(fp) + 803b314: 10800417 ldw r2,16(r2) + 803b318: 1004d43a srli r2,r2,16 + 803b31c: 10803fcc andi r2,r2,255 + 803b320: e0ffff17 ldw r3,-4(fp) + 803b324: 18c00417 ldw r3,16(r3) + 803b328: 1806d63a srli r3,r3,24 + 803b32c: d8c00115 stw r3,4(sp) + 803b330: d8800015 stw r2,0(sp) + 803b334: 280f883a mov r7,r5 + 803b338: 200d883a mov r6,r4 + 803b33c: 01420174 movhi r5,2053 + 803b340: 296c7704 addi r5,r5,-20004 + 803b344: 0009883a mov r4,zero + 803b348: 80273900 call 8027390 + + pip->ip_chksum = osum; /* fix what we clobbered */ + 803b34c: e0bfff17 ldw r2,-4(fp) + 803b350: e0fffe8b ldhu r3,-6(fp) + 803b354: 10c0028d sth r3,10(r2) +} + 803b358: 0001883a nop + 803b35c: e037883a mov sp,fp + 803b360: dfc00117 ldw ra,4(sp) + 803b364: df000017 ldw fp,0(sp) + 803b368: dec00204 addi sp,sp,8 + 803b36c: f800283a ret + +0803b370 : + * RETURNS: Returns NULL when unable to route, else returns a NET pointer. + */ + +NET +iproute(ip_addr host, ip_addr * hop1) +{ + 803b370: defff804 addi sp,sp,-32 + 803b374: dfc00715 stw ra,28(sp) + 803b378: df000615 stw fp,24(sp) + 803b37c: df000604 addi fp,sp,24 + 803b380: e13ffc15 stw r4,-16(fp) + 803b384: e17ffb15 stw r5,-20(fp) + NET ifp; +#ifdef IP_ROUTING + RTMIB rtp; +#endif /* IP_ROUTING */ + + if (host == 0L) /* Sanity check parameter. */ + 803b388: e0bffc17 ldw r2,-16(fp) + 803b38c: 1000021e bne r2,zero,803b398 + return NULL; + 803b390: 0005883a mov r2,zero + 803b394: 00006406 br 803b528 + * stack has been initialized (tk_yield() gets called out of the + * dialer code as part of PPP initialization), one symptom of + * which is the routing table not being present yet. if this + * happens, quit. + */ + if (rt_mib == NULL) + 803b398: d0a09517 ldw r2,-32172(gp) + 803b39c: 1000021e bne r2,zero,803b3a8 + return NULL; + 803b3a0: 0005883a mov r2,zero + 803b3a4: 00006006 br 803b528 +#endif /* BTREE_ROUTING */ + + /* see if the host matches the cached route */ + if (cachedRoute) /* don't test this if route is null */ + 803b3a8: d0a09c17 ldw r2,-32144(gp) + 803b3ac: 10000e26 beq r2,zero,803b3e8 + { + if (cachedRoute->ipRouteDest == host) /* exact match */ + 803b3b0: d0a09c17 ldw r2,-32144(gp) + 803b3b4: 10800017 ldw r2,0(r2) + 803b3b8: e0fffc17 ldw r3,-16(fp) + 803b3bc: 18800a1e bne r3,r2,803b3e8 + { + *hop1 = cachedRoute->ipRouteNextHop; /* fill in nexthop IP addr */ + 803b3c0: d0a09c17 ldw r2,-32144(gp) + 803b3c4: 10c00617 ldw r3,24(r2) + 803b3c8: e0bffb17 ldw r2,-20(fp) + 803b3cc: 10c00015 stw r3,0(r2) + cachedRoute->ipRouteAge = cticks; /* timestamp route entry */ + 803b3d0: d0a09c17 ldw r2,-32144(gp) + 803b3d4: d0e07d17 ldw r3,-32268(gp) + 803b3d8: 10c00915 stw r3,36(r2) + return(cachedRoute->ifp); /* net to send on */ + 803b3dc: d0a09c17 ldw r2,-32144(gp) + 803b3e0: 10800e17 ldw r2,56(r2) + 803b3e4: 00005006 br 803b528 + } + } + + rtp = rt_lookup(host); + 803b3e8: e13ffc17 ldw r4,-16(fp) + 803b3ec: 803cb280 call 803cb28 + 803b3f0: e0bffd15 stw r2,-12(fp) + if(rtp) + 803b3f4: e0bffd17 ldw r2,-12(fp) + 803b3f8: 10000926 beq r2,zero,803b420 + { + cachedRoute = rtp; + 803b3fc: e0bffd17 ldw r2,-12(fp) + 803b400: d0a09c15 stw r2,-32144(gp) + *hop1 = rtp->ipRouteNextHop; /* fill in IP dest (next hop) */ + 803b404: e0bffd17 ldw r2,-12(fp) + 803b408: 10c00617 ldw r3,24(r2) + 803b40c: e0bffb17 ldw r2,-20(fp) + 803b410: 10c00015 stw r3,0(r2) + return(rtp->ifp); /* return pointer to net */ + 803b414: e0bffd17 ldw r2,-12(fp) + 803b418: 10800e17 ldw r2,56(r2) + 803b41c: 00004206 br 803b528 + * the initial state for the for loop that iterates through the + * list), but only build the iterator for multi-homed systems + * because single-homed systems are often memory-limited systems as + * well. + */ + ifp = (NET)(netlist.q_head); + 803b420: 008201b4 movhi r2,2054 + 803b424: 10b6a617 ldw r2,-9576(r2) + 803b428: e0bffe15 stw r2,-8(fp) + i = 0; + 803b42c: e03fff15 stw zero,-4(fp) +#ifdef MULTI_HOMED + for(; ifp; ifp = ifp->n_next, i++) + 803b430: 00002406 br 803b4c4 +#endif /* MULTI_HOMED */ + { + if((ifp->snmask != 0) && /* skip ifaces with no IP or subnet mask set */ + 803b434: e0bffe17 ldw r2,-8(fp) + 803b438: 10800c17 ldw r2,48(r2) + 803b43c: 10001b26 beq r2,zero,803b4ac + (ifp->n_ipaddr != 0) && + 803b440: e0bffe17 ldw r2,-8(fp) + 803b444: 10800a17 ldw r2,40(r2) + if((ifp->snmask != 0) && /* skip ifaces with no IP or subnet mask set */ + 803b448: 10001826 beq r2,zero,803b4ac + ((ifp->n_ipaddr & ifp->snmask) == (host & ifp->snmask))) + 803b44c: e0bffe17 ldw r2,-8(fp) + 803b450: 10c00a17 ldw r3,40(r2) + 803b454: e0bffc17 ldw r2,-16(fp) + 803b458: 1886f03a xor r3,r3,r2 + 803b45c: e0bffe17 ldw r2,-8(fp) + 803b460: 10800c17 ldw r2,48(r2) + 803b464: 1884703a and r2,r3,r2 + (ifp->n_ipaddr != 0) && + 803b468: 1000101e bne r2,zero,803b4ac + { +#ifdef IP_ROUTING + /* make a cached Route entry for next time */ + cachedRoute = add_route(host, 0xFFFFFFFF, host, i, IPRP_OTHER); + 803b46c: 00800044 movi r2,1 + 803b470: d8800015 stw r2,0(sp) + 803b474: e1ffff17 ldw r7,-4(fp) + 803b478: e1bffc17 ldw r6,-16(fp) + 803b47c: 017fffc4 movi r5,-1 + 803b480: e13ffc17 ldw r4,-16(fp) + 803b484: 803cc7c0 call 803cc7c + 803b488: d0a09c15 stw r2,-32144(gp) +#ifdef NPDEBUG + if (cachedRoute == NULL) + 803b48c: d0a09c17 ldw r2,-32144(gp) + 803b490: 1000011e bne r2,zero,803b498 + dtrap(); + 803b494: 8028cd40 call 8028cd4 +#endif /* NPDEBUG */ +#endif /* IP_ROUTING */ + *hop1 = host; + 803b498: e0bffb17 ldw r2,-20(fp) + 803b49c: e0fffc17 ldw r3,-16(fp) + 803b4a0: 10c00015 stw r3,0(r2) + return ifp; + 803b4a4: e0bffe17 ldw r2,-8(fp) + 803b4a8: 00001f06 br 803b528 + for(; ifp; ifp = ifp->n_next, i++) + 803b4ac: e0bffe17 ldw r2,-8(fp) + 803b4b0: 10800017 ldw r2,0(r2) + 803b4b4: e0bffe15 stw r2,-8(fp) + 803b4b8: e0bfff17 ldw r2,-4(fp) + 803b4bc: 10800044 addi r2,r2,1 + 803b4c0: e0bfff15 stw r2,-4(fp) + 803b4c4: e0bffe17 ldw r2,-8(fp) + 803b4c8: 103fda1e bne r2,zero,803b434 +#endif /* IP_LOOPBACK */ + + /* The host isn't on a net I'm on, so send it to the default + * gateway on the first net which has one. + */ + ifp = (NET)(netlist.q_head); + 803b4cc: 008201b4 movhi r2,2054 + 803b4d0: 10b6a617 ldw r2,-9576(r2) + 803b4d4: e0bffe15 stw r2,-8(fp) +#ifdef MULTI_HOMED + for(; ifp; ifp = ifp->n_next) + 803b4d8: 00000c06 br 803b50c +#endif /* MULTI_HOMED */ + { + /* Check if this net has a gateway */ + if(ifp->n_defgw) + 803b4dc: e0bffe17 ldw r2,-8(fp) + 803b4e0: 10800d17 ldw r2,52(r2) + 803b4e4: 10000626 beq r2,zero,803b500 + { + *hop1 = ifp->n_defgw; + 803b4e8: e0bffe17 ldw r2,-8(fp) + 803b4ec: 10c00d17 ldw r3,52(r2) + 803b4f0: e0bffb17 ldw r2,-20(fp) + 803b4f4: 10c00015 stw r3,0(r2) + return ifp; + 803b4f8: e0bffe17 ldw r2,-8(fp) + 803b4fc: 00000a06 br 803b528 + for(; ifp; ifp = ifp->n_next) + 803b500: e0bffe17 ldw r2,-8(fp) + 803b504: 10800017 ldw r2,0(r2) + 803b508: e0bffe15 stw r2,-8(fp) + 803b50c: e0bffe17 ldw r2,-8(fp) + 803b510: 103ff21e bne r2,zero,803b4dc + /* if no gateway is set, then change the first hop address to the + * host we're trying to route to. this is just a kluge to make + * this work with arp routing. otherwise, we would try to return + * some sort of error indication. + */ + *hop1 = host; + 803b514: e0bffb17 ldw r2,-20(fp) + 803b518: e0fffc17 ldw r3,-16(fp) + 803b51c: 10c00015 stw r3,0(r2) + return((NET)(netlist.q_head)); + 803b520: 008201b4 movhi r2,2054 + 803b524: 10b6a617 ldw r2,-9576(r2) +#endif /* STRICT_SUBNETTING */ +} + 803b528: e037883a mov sp,fp + 803b52c: dfc00117 ldw ra,4(sp) + 803b530: df000017 ldw fp,0(sp) + 803b534: dec00204 addi sp,sp,8 + 803b538: f800283a ret + +0803b53c : + * RETURNS: a pointer to the new copy of the packet, + * or NULL if no packet buffer could be allocated + */ +PACKET +ip_copypkt(PACKET p) +{ + 803b53c: defffb04 addi sp,sp,-20 + 803b540: dfc00415 stw ra,16(sp) + 803b544: df000315 stw fp,12(sp) + 803b548: df000304 addi fp,sp,12 + 803b54c: e13ffd15 stw r4,-12(fp) + int len; + + /* figure out how much we need to copy from the packet, + * and allocate a new buffer to hold it + */ + len = p->nb_plen + (p->nb_prot - p->nb_buff); + 803b550: e0bffd17 ldw r2,-12(fp) + 803b554: 10800417 ldw r2,16(r2) + 803b558: e0fffd17 ldw r3,-12(fp) + 803b55c: 19000317 ldw r4,12(r3) + 803b560: e0fffd17 ldw r3,-12(fp) + 803b564: 18c00117 ldw r3,4(r3) + 803b568: 20c7c83a sub r3,r4,r3 + 803b56c: 10c5883a add r2,r2,r3 + 803b570: e0bfff15 stw r2,-4(fp) + LOCK_NET_RESOURCE(FREEQ_RESID); + 803b574: 01000084 movi r4,2 + 803b578: 8028f380 call 8028f38 + np = pk_alloc(len); + 803b57c: e0bfff17 ldw r2,-4(fp) + 803b580: 1009883a mov r4,r2 + 803b584: 80284340 call 8028434 + 803b588: e0bffe15 stw r2,-8(fp) + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803b58c: 01000084 movi r4,2 + 803b590: 8028ff40 call 8028ff4 + if (np == NULL) + 803b594: e0bffe17 ldw r2,-8(fp) + 803b598: 1000061e bne r2,zero,803b5b4 + { +#ifdef NPDEBUG + dprintf("ip_copypkt(): unable to obtain packet (len %d)\n", len); + 803b59c: e17fff17 ldw r5,-4(fp) + 803b5a0: 01020174 movhi r4,2053 + 803b5a4: 212c7c04 addi r4,r4,-19984 + 803b5a8: 8002c780 call 8002c78 +#endif + return NULL; + 803b5ac: 0005883a mov r2,zero + 803b5b0: 00002806 br 803b654 + } + + /* copy packet data into new buffer */ + MEMCPY(np->nb_buff, p->nb_buff, len); + 803b5b4: e0bffe17 ldw r2,-8(fp) + 803b5b8: 10c00117 ldw r3,4(r2) + 803b5bc: e0bffd17 ldw r2,-12(fp) + 803b5c0: 10800117 ldw r2,4(r2) + 803b5c4: e13fff17 ldw r4,-4(fp) + 803b5c8: 200d883a mov r6,r4 + 803b5cc: 100b883a mov r5,r2 + 803b5d0: 1809883a mov r4,r3 + 803b5d4: 80086b80 call 80086b8 + + /* copy relevant packet fields */ + np->nb_prot = np->nb_buff + (p->nb_prot - p->nb_buff); + 803b5d8: e0bffe17 ldw r2,-8(fp) + 803b5dc: 10800117 ldw r2,4(r2) + 803b5e0: e0fffd17 ldw r3,-12(fp) + 803b5e4: 19000317 ldw r4,12(r3) + 803b5e8: e0fffd17 ldw r3,-12(fp) + 803b5ec: 18c00117 ldw r3,4(r3) + 803b5f0: 20c7c83a sub r3,r4,r3 + 803b5f4: 10c7883a add r3,r2,r3 + 803b5f8: e0bffe17 ldw r2,-8(fp) + 803b5fc: 10c00315 stw r3,12(r2) + np->nb_plen = p->nb_plen; + 803b600: e0bffd17 ldw r2,-12(fp) + 803b604: 10c00417 ldw r3,16(r2) + 803b608: e0bffe17 ldw r2,-8(fp) + 803b60c: 10c00415 stw r3,16(r2) + np->net = p->net; + 803b610: e0bffd17 ldw r2,-12(fp) + 803b614: 10c00617 ldw r3,24(r2) + 803b618: e0bffe17 ldw r2,-8(fp) + 803b61c: 10c00615 stw r3,24(r2) + np->fhost = p->fhost; + 803b620: e0bffd17 ldw r2,-12(fp) + 803b624: 10c00717 ldw r3,28(r2) + 803b628: e0bffe17 ldw r2,-8(fp) + 803b62c: 10c00715 stw r3,28(r2) + np->type = p->type; + 803b630: e0bffd17 ldw r2,-12(fp) + 803b634: 10c0080b ldhu r3,32(r2) + 803b638: e0bffe17 ldw r2,-8(fp) + 803b63c: 10c0080d sth r3,32(r2) + np->nb_tstamp = p->nb_tstamp; + 803b640: e0bffd17 ldw r2,-12(fp) + 803b644: 10c00517 ldw r3,20(r2) + 803b648: e0bffe17 ldw r2,-8(fp) + 803b64c: 10c00515 stw r3,20(r2) + + /* return pointer to the copy */ + return np; + 803b650: e0bffe17 ldw r2,-8(fp) +} + 803b654: e037883a mov sp,fp + 803b658: dfc00117 ldw ra,4(sp) + 803b65c: df000017 ldw fp,0(sp) + 803b660: dec00204 addi sp,sp,8 + 803b664: f800283a ret + +0803b668 : + * RETURNS: + */ + +int +ip_rcv(PACKET p) +{ + 803b668: defff404 addi sp,sp,-48 + 803b66c: dfc00b15 stw ra,44(sp) + 803b670: df000a15 stw fp,40(sp) + 803b674: dc000915 stw r16,36(sp) + 803b678: df000a04 addi fp,sp,40 + 803b67c: e13ff615 stw r4,-40(fp) + unsigned hdrlen; /* length of IP header including options */ + unsigned len; /* total length including IP header */ + unsigned short int num_pkts; + PACKET * pktp; + unsigned char i; + int rcvrc = -1; + 803b680: 00bfffc4 movi r2,-1 + 803b684: e0bffd15 stw r2,-12(fp) + unsigned char rc_ret; +#endif + + +#ifdef NPDEBUG + if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE)) + 803b688: d0a06617 ldw r2,-32360(gp) + 803b68c: 1081000c andi r2,r2,1024 + 803b690: 10000e26 beq r2,zero,803b6cc + 803b694: d0a06617 ldw r2,-32360(gp) + 803b698: 1080800c andi r2,r2,512 + 803b69c: 10000b26 beq r2,zero,803b6cc + dprintf("ip_rcv: got packet, len:%d, if:%d\n", + p->nb_plen, net_num(p->net)); + 803b6a0: e0bff617 ldw r2,-40(fp) + dprintf("ip_rcv: got packet, len:%d, if:%d\n", + 803b6a4: 14000417 ldw r16,16(r2) + p->nb_plen, net_num(p->net)); + 803b6a8: e0bff617 ldw r2,-40(fp) + dprintf("ip_rcv: got packet, len:%d, if:%d\n", + 803b6ac: 10800617 ldw r2,24(r2) + 803b6b0: 1009883a mov r4,r2 + 803b6b4: 80252fc0 call 80252fc + 803b6b8: 100d883a mov r6,r2 + 803b6bc: 800b883a mov r5,r16 + 803b6c0: 01020174 movhi r4,2053 + 803b6c4: 212c8804 addi r4,r4,-19936 + 803b6c8: 8002c780 call 8002c78 +#endif + + IN_PROFILER(PF_IP, PF_ENTRY); + + ip_mib.ipInReceives++; + 803b6cc: 008201b4 movhi r2,2054 + 803b6d0: 10b95117 ldw r2,-6844(r2) + 803b6d4: 10c00044 addi r3,r2,1 + 803b6d8: 008201b4 movhi r2,2054 + 803b6dc: 10f95115 stw r3,-6844(r2) + pip = ip_head(p); + 803b6e0: e0bff617 ldw r2,-40(fp) + 803b6e4: 10800317 ldw r2,12(r2) + 803b6e8: e0bffc15 stw r2,-16(fp) + + /* test received MAC len against IP header len */ + if (p->nb_plen < (unsigned)htons(pip->ip_len)) + 803b6ec: e0bff617 ldw r2,-40(fp) + 803b6f0: 10800417 ldw r2,16(r2) + 803b6f4: e0fffc17 ldw r3,-16(fp) + 803b6f8: 18c0008b ldhu r3,2(r3) + 803b6fc: 18ffffcc andi r3,r3,65535 + 803b700: 1806d23a srli r3,r3,8 + 803b704: 18ffffcc andi r3,r3,65535 + 803b708: 19003fcc andi r4,r3,255 + 803b70c: e0fffc17 ldw r3,-16(fp) + 803b710: 18c0008b ldhu r3,2(r3) + 803b714: 18ffffcc andi r3,r3,65535 + 803b718: 1806923a slli r3,r3,8 + 803b71c: 18ffffcc andi r3,r3,65535 + 803b720: 20c6b03a or r3,r4,r3 + 803b724: 10c01d2e bgeu r2,r3,803b79c + { +#ifdef NPDEBUG + if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE)) + 803b728: d0a06617 ldw r2,-32360(gp) + 803b72c: 1081000c andi r2,r2,1024 + 803b730: 10000c26 beq r2,zero,803b764 + 803b734: d0a06617 ldw r2,-32360(gp) + 803b738: 1080800c andi r2,r2,512 + 803b73c: 10000926 beq r2,zero,803b764 + { + dprintf("ip_rcv: bad pkt len\n"); + 803b740: 01020174 movhi r4,2053 + 803b744: 212c9104 addi r4,r4,-19900 + 803b748: 8002d9c0 call 8002d9c + if (NDEBUG & DUMP) ip_dump(p); + 803b74c: d0a06617 ldw r2,-32360(gp) + 803b750: 1080008c andi r2,r2,2 + 803b754: 10000326 beq r2,zero,803b764 + 803b758: e0bff617 ldw r2,-40(fp) + 803b75c: 1009883a mov r4,r2 + 803b760: 803b0cc0 call 803b0cc + } +#endif + ip_mib.ipInHdrErrors++; + 803b764: 008201b4 movhi r2,2054 + 803b768: 10b95217 ldw r2,-6840(r2) + 803b76c: 10c00044 addi r3,r2,1 + 803b770: 008201b4 movhi r2,2054 + 803b774: 10f95215 stw r3,-6840(r2) + LOCK_NET_RESOURCE(FREEQ_RESID); + 803b778: 01000084 movi r4,2 + 803b77c: 8028f380 call 8028f38 + pk_free(p); + 803b780: e0bff617 ldw r2,-40(fp) + 803b784: 1009883a mov r4,r2 + 803b788: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803b78c: 01000084 movi r4,2 + 803b790: 8028ff40 call 8028ff4 + IN_PROFILER(PF_IP, PF_EXIT); + return(ENP_BAD_HEADER); + 803b794: 00bff804 movi r2,-32 + 803b798: 00008206 br 803b9a4 + } + + /* use length from IP header; MAC value may be padded */ + len = htons(pip->ip_len); + 803b79c: e0bffc17 ldw r2,-16(fp) + 803b7a0: 1080008b ldhu r2,2(r2) + 803b7a4: 10bfffcc andi r2,r2,65535 + 803b7a8: 1004d23a srli r2,r2,8 + 803b7ac: 10bfffcc andi r2,r2,65535 + 803b7b0: 10c03fcc andi r3,r2,255 + 803b7b4: e0bffc17 ldw r2,-16(fp) + 803b7b8: 1080008b ldhu r2,2(r2) + 803b7bc: 10bfffcc andi r2,r2,65535 + 803b7c0: 1004923a slli r2,r2,8 + 803b7c4: 10bfffcc andi r2,r2,65535 + 803b7c8: 1884b03a or r2,r3,r2 + 803b7cc: e0bffb15 stw r2,-20(fp) + p->nb_plen = len; /* fix pkt len */ + 803b7d0: e0bff617 ldw r2,-40(fp) + 803b7d4: e0fffb17 ldw r3,-20(fp) + 803b7d8: 10c00415 stw r3,16(r2) + + if ( ((pip->ip_ver_ihl & 0xf0) >> 4) != IP_VER) + 803b7dc: e0bffc17 ldw r2,-16(fp) + 803b7e0: 10800003 ldbu r2,0(r2) + 803b7e4: 10803fcc andi r2,r2,255 + 803b7e8: 1004d13a srli r2,r2,4 + 803b7ec: 10803fcc andi r2,r2,255 + 803b7f0: 10800120 cmpeqi r2,r2,4 + 803b7f4: 10001d1e bne r2,zero,803b86c + { +#ifdef NPDEBUG + if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE)) + 803b7f8: d0a06617 ldw r2,-32360(gp) + 803b7fc: 1081000c andi r2,r2,1024 + 803b800: 10000c26 beq r2,zero,803b834 + 803b804: d0a06617 ldw r2,-32360(gp) + 803b808: 1080800c andi r2,r2,512 + 803b80c: 10000926 beq r2,zero,803b834 + { + dprintf("ip_rcv: bad version number\n"); + 803b810: 01020174 movhi r4,2053 + 803b814: 212c9604 addi r4,r4,-19880 + 803b818: 8002d9c0 call 8002d9c + if (NDEBUG & DUMP) ip_dump(p); + 803b81c: d0a06617 ldw r2,-32360(gp) + 803b820: 1080008c andi r2,r2,2 + 803b824: 10000326 beq r2,zero,803b834 + 803b828: e0bff617 ldw r2,-40(fp) + 803b82c: 1009883a mov r4,r2 + 803b830: 803b0cc0 call 803b0cc + } +#endif + ip_mib.ipInHdrErrors++; + 803b834: 008201b4 movhi r2,2054 + 803b838: 10b95217 ldw r2,-6840(r2) + 803b83c: 10c00044 addi r3,r2,1 + 803b840: 008201b4 movhi r2,2054 + 803b844: 10f95215 stw r3,-6840(r2) + LOCK_NET_RESOURCE(FREEQ_RESID); + 803b848: 01000084 movi r4,2 + 803b84c: 8028f380 call 8028f38 + pk_free(p); + 803b850: e0bff617 ldw r2,-40(fp) + 803b854: 1009883a mov r4,r2 + 803b858: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803b85c: 01000084 movi r4,2 + 803b860: 8028ff40 call 8028ff4 + IN_PROFILER(PF_IP, PF_EXIT); + return(ENP_BAD_HEADER); + 803b864: 00bff804 movi r2,-32 + 803b868: 00004e06 br 803b9a4 + } + + csum = pip->ip_chksum; + 803b86c: e0bffc17 ldw r2,-16(fp) + 803b870: 1080028b ldhu r2,10(r2) + 803b874: e0bffa8d sth r2,-22(fp) + pip->ip_chksum = 0; + 803b878: e0bffc17 ldw r2,-16(fp) + 803b87c: 1000028d sth zero,10(r2) + hdrlen = ip_hlen(pip); + 803b880: e0bffc17 ldw r2,-16(fp) + 803b884: 10800003 ldbu r2,0(r2) + 803b888: 10803fcc andi r2,r2,255 + 803b88c: 100490ba slli r2,r2,2 + 803b890: 10800f0c andi r2,r2,60 + 803b894: e0bff915 stw r2,-28(fp) + tempsum = ~cksum(pip, hdrlen >> 1); + 803b898: e0bff917 ldw r2,-28(fp) + 803b89c: 1004d07a srli r2,r2,1 + 803b8a0: 100b883a mov r5,r2 + 803b8a4: e13ffc17 ldw r4,-16(fp) + 803b8a8: 8026d7c0 call 8026d7c + 803b8ac: 0084303a nor r2,zero,r2 + 803b8b0: e0bff88d sth r2,-30(fp) + + if (csum != tempsum) + 803b8b4: e0fffa8b ldhu r3,-22(fp) + 803b8b8: e0bff88b ldhu r2,-30(fp) + 803b8bc: 18802026 beq r3,r2,803b940 + { + pip->ip_chksum = csum; + 803b8c0: e0bffc17 ldw r2,-16(fp) + 803b8c4: e0fffa8b ldhu r3,-22(fp) + 803b8c8: 10c0028d sth r3,10(r2) +#ifdef NPDEBUG + if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE)) + 803b8cc: d0a06617 ldw r2,-32360(gp) + 803b8d0: 1081000c andi r2,r2,1024 + 803b8d4: 10000c26 beq r2,zero,803b908 + 803b8d8: d0a06617 ldw r2,-32360(gp) + 803b8dc: 1080800c andi r2,r2,512 + 803b8e0: 10000926 beq r2,zero,803b908 + { + dprintf("ip_rcv: bad xsum\n"); + 803b8e4: 01020174 movhi r4,2053 + 803b8e8: 212c9d04 addi r4,r4,-19852 + 803b8ec: 8002d9c0 call 8002d9c + if (NDEBUG & DUMP) ip_dump(p); + 803b8f0: d0a06617 ldw r2,-32360(gp) + 803b8f4: 1080008c andi r2,r2,2 + 803b8f8: 10000326 beq r2,zero,803b908 + 803b8fc: e0bff617 ldw r2,-40(fp) + 803b900: 1009883a mov r4,r2 + 803b904: 803b0cc0 call 803b0cc + } +#endif + ip_mib.ipInHdrErrors++; + 803b908: 008201b4 movhi r2,2054 + 803b90c: 10b95217 ldw r2,-6840(r2) + 803b910: 10c00044 addi r3,r2,1 + 803b914: 008201b4 movhi r2,2054 + 803b918: 10f95215 stw r3,-6840(r2) + LOCK_NET_RESOURCE(FREEQ_RESID); + 803b91c: 01000084 movi r4,2 + 803b920: 8028f380 call 8028f38 + pk_free(p); + 803b924: e0bff617 ldw r2,-40(fp) + 803b928: 1009883a mov r4,r2 + 803b92c: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803b930: 01000084 movi r4,2 + 803b934: 8028ff40 call 8028ff4 + IN_PROFILER(PF_IP, PF_EXIT); + return(ENP_BAD_HEADER); + 803b938: 00bff804 movi r2,-32 + 803b93c: 00001906 br 803b9a4 + } + + pip->ip_chksum = csum; + 803b940: e0bffc17 ldw r2,-16(fp) + 803b944: e0fffa8b ldhu r3,-22(fp) + 803b948: 10c0028d sth r3,10(r2) +#endif + + /* start off by assuming that we will only process the "current" packet; + * these values may get overwritten by the NAT module if it returns + * more than one packet back to this function (ip_rcv ()) */ + num_pkts = 1; + 803b94c: 00800044 movi r2,1 + 803b950: e0bff80d sth r2,-32(fp) + pktp = &p; + 803b954: e0bff604 addi r2,fp,-40 + 803b958: e0bff715 stw r2,-36(fp) + * by other modules */ +#endif /* NATRT */ + + /* we need to process 'num_pkts' packets. Pointers to these packets are stored + * in storage @ 'pktp' */ + for (i = 0; i < num_pkts; ++i) + 803b95c: e03ffec5 stb zero,-5(fp) + 803b960: 00000b06 br 803b990 + { + rcvrc = ip_rcv_phase2 (*(pktp + i)); + 803b964: e0bffec3 ldbu r2,-5(fp) + 803b968: 100490ba slli r2,r2,2 + 803b96c: e0fff717 ldw r3,-36(fp) + 803b970: 1885883a add r2,r3,r2 + 803b974: 10800017 ldw r2,0(r2) + 803b978: 1009883a mov r4,r2 + 803b97c: 803b9bc0 call 803b9bc + 803b980: e0bffd15 stw r2,-12(fp) + for (i = 0; i < num_pkts; ++i) + 803b984: e0bffec3 ldbu r2,-5(fp) + 803b988: 10800044 addi r2,r2,1 + 803b98c: e0bffec5 stb r2,-5(fp) + 803b990: e0fffec3 ldbu r3,-5(fp) + 803b994: e0bff80b ldhu r2,-32(fp) + 803b998: 18ffffcc andi r3,r3,65535 + 803b99c: 18bff136 bltu r3,r2,803b964 + if (pktp != &p) nat_free (pktp); +#endif /* NATRT */ + + /* when multiple packets are processed in the loop above, the return code + * contains the return code for the last packet */ + return rcvrc; + 803b9a0: e0bffd17 ldw r2,-12(fp) +} + 803b9a4: e6ffff04 addi sp,fp,-4 + 803b9a8: dfc00217 ldw ra,8(sp) + 803b9ac: df000117 ldw fp,4(sp) + 803b9b0: dc000017 ldw r16,0(sp) + 803b9b4: dec00304 addi sp,sp,12 + 803b9b8: f800283a ret + +0803b9bc : + + +int ip_rcv_phase2 (PACKET p) +{ + 803b9bc: defff604 addi sp,sp,-40 + 803b9c0: dfc00915 stw ra,36(sp) + 803b9c4: df000815 stw fp,32(sp) + 803b9c8: df000804 addi fp,sp,32 + 803b9cc: e13ff915 stw r4,-28(fp) + + struct ip * pip; /* the internet header */ + NET nt; + unsigned short tempsum; + + pip = ip_head(p); + 803b9d0: e0bff917 ldw r2,-28(fp) + 803b9d4: 10800317 ldw r2,12(r2) + 803b9d8: e0bfff15 stw r2,-4(fp) + nt = p->net; /* which interface it came in on */ + 803b9dc: e0bff917 ldw r2,-28(fp) + 803b9e0: 10800617 ldw r2,24(r2) + 803b9e4: e0bffe15 stw r2,-8(fp) + +#ifdef IP_MULTICAST + + if (IN_MULTICAST(ntohl(pip->ip_dest))) + 803b9e8: e0bfff17 ldw r2,-4(fp) + 803b9ec: 10800417 ldw r2,16(r2) + 803b9f0: 1006d63a srli r3,r2,24 + 803b9f4: e0bfff17 ldw r2,-4(fp) + 803b9f8: 10800417 ldw r2,16(r2) + 803b9fc: 1004d23a srli r2,r2,8 + 803ba00: 10bfc00c andi r2,r2,65280 + 803ba04: 1886b03a or r3,r3,r2 + 803ba08: e0bfff17 ldw r2,-4(fp) + 803ba0c: 10800417 ldw r2,16(r2) + 803ba10: 1004923a slli r2,r2,8 + 803ba14: 10803fec andhi r2,r2,255 + 803ba18: 1886b03a or r3,r3,r2 + 803ba1c: e0bfff17 ldw r2,-4(fp) + 803ba20: 10800417 ldw r2,16(r2) + 803ba24: 1004963a slli r2,r2,24 + 803ba28: 1884b03a or r2,r3,r2 + 803ba2c: 10fc002c andhi r3,r2,61440 + 803ba30: 00b80034 movhi r2,57344 + 803ba34: 1880151e bne r3,r2,803ba8c + struct in_multi * inm; + /* + * See if we belong to the destination multicast group on the + * arrival interface. + */ + inm = lookup_mcast(pip->ip_dest, nt); + 803ba38: e0bfff17 ldw r2,-4(fp) + 803ba3c: 10800417 ldw r2,16(r2) + 803ba40: e17ffe17 ldw r5,-8(fp) + 803ba44: 1009883a mov r4,r2 + 803ba48: 803c5040 call 803c504 + 803ba4c: e0bffd15 stw r2,-12(fp) + if (inm == NULL) + 803ba50: e0bffd17 ldw r2,-12(fp) + 803ba54: 1000dc1e bne r2,zero,803bdc8 + { + ip_mib.ipOutNoRoutes++; + 803ba58: 008201b4 movhi r2,2054 + 803ba5c: 10b95a17 ldw r2,-6808(r2) + 803ba60: 10c00044 addi r3,r2,1 + 803ba64: 008201b4 movhi r2,2054 + 803ba68: 10f95a15 stw r3,-6808(r2) + LOCK_NET_RESOURCE(FREEQ_RESID); + 803ba6c: 01000084 movi r4,2 + 803ba70: 8028f380 call 8028f38 + pk_free(p); + 803ba74: e13ff917 ldw r4,-28(fp) + 803ba78: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803ba7c: 01000084 movi r4,2 + 803ba80: 8028ff40 call 8028ff4 + IN_PROFILER(PF_IP, PF_EXIT); + return (ENP_NOT_MINE); + 803ba84: 00800084 movi r2,2 + 803ba88: 00011a06 br 803bef4 + else + goto ours; + } +#endif /* IP_MULTICAST */ + + if ((pip->ip_dest != nt->n_ipaddr) && /* Quick check on our own addr */ + 803ba8c: e0bfff17 ldw r2,-4(fp) + 803ba90: 10c00417 ldw r3,16(r2) + 803ba94: e0bffe17 ldw r2,-8(fp) + 803ba98: 10800a17 ldw r2,40(r2) + 803ba9c: 1880cc26 beq r3,r2,803bdd0 + (pip->ip_dest != 0xffffffffL) && /* Physical cable broadcast addr*/ + 803baa0: e0bfff17 ldw r2,-4(fp) + 803baa4: 10800417 ldw r2,16(r2) + if ((pip->ip_dest != nt->n_ipaddr) && /* Quick check on our own addr */ + 803baa8: 10bfffe0 cmpeqi r2,r2,-1 + 803baac: 1000c81e bne r2,zero,803bdd0 + (pip->ip_dest != nt->n_netbr) && /* All subnet broadcast */ + 803bab0: e0bfff17 ldw r2,-4(fp) + 803bab4: 10c00417 ldw r3,16(r2) + 803bab8: e0bffe17 ldw r2,-8(fp) + 803babc: 10800e17 ldw r2,56(r2) + (pip->ip_dest != 0xffffffffL) && /* Physical cable broadcast addr*/ + 803bac0: 1880c326 beq r3,r2,803bdd0 + (pip->ip_dest != nt->n_netbr42) && /* All subnet bcast (4.2bsd) */ + 803bac4: e0bfff17 ldw r2,-4(fp) + 803bac8: 10c00417 ldw r3,16(r2) + 803bacc: e0bffe17 ldw r2,-8(fp) + 803bad0: 10800f17 ldw r2,60(r2) + (pip->ip_dest != nt->n_netbr) && /* All subnet broadcast */ + 803bad4: 1880be26 beq r3,r2,803bdd0 + (pip->ip_dest != nt->n_subnetbr) &&/* Our subnet broadcast */ + 803bad8: e0bfff17 ldw r2,-4(fp) + 803badc: 10c00417 ldw r3,16(r2) + 803bae0: e0bffe17 ldw r2,-8(fp) + 803bae4: 10801017 ldw r2,64(r2) + (pip->ip_dest != nt->n_netbr42) && /* All subnet bcast (4.2bsd) */ + 803bae8: 1880b926 beq r3,r2,803bdd0 + (nt->n_ipaddr & ~nt->snmask)) /* Know our own host address? */ + 803baec: e0bffe17 ldw r2,-8(fp) + 803baf0: 10c00a17 ldw r3,40(r2) + 803baf4: e0bffe17 ldw r2,-8(fp) + 803baf8: 10800c17 ldw r2,48(r2) + 803bafc: 0084303a nor r2,zero,r2 + 803bb00: 1884703a and r2,r3,r2 + (pip->ip_dest != nt->n_subnetbr) &&/* Our subnet broadcast */ + 803bb04: 1000b226 beq r2,zero,803bdd0 + { +#ifdef NPDEBUG + if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE)) + 803bb08: d0a06617 ldw r2,-32360(gp) + 803bb0c: 1081000c andi r2,r2,1024 + 803bb10: 10001826 beq r2,zero,803bb74 + 803bb14: d0a06617 ldw r2,-32360(gp) + 803bb18: 1080800c andi r2,r2,512 + 803bb1c: 10001526 beq r2,zero,803bb74 + dprintf("ip_rcv: got pkt not for me; for %u.%u.%u.%u\n", + PUSH_IPADDR(pip->ip_dest)); + 803bb20: e0bfff17 ldw r2,-4(fp) + 803bb24: 10800417 ldw r2,16(r2) + dprintf("ip_rcv: got pkt not for me; for %u.%u.%u.%u\n", + 803bb28: 10c03fcc andi r3,r2,255 + PUSH_IPADDR(pip->ip_dest)); + 803bb2c: e0bfff17 ldw r2,-4(fp) + 803bb30: 10800417 ldw r2,16(r2) + 803bb34: 1004d23a srli r2,r2,8 + dprintf("ip_rcv: got pkt not for me; for %u.%u.%u.%u\n", + 803bb38: 11003fcc andi r4,r2,255 + PUSH_IPADDR(pip->ip_dest)); + 803bb3c: e0bfff17 ldw r2,-4(fp) + 803bb40: 10800417 ldw r2,16(r2) + 803bb44: 1004d43a srli r2,r2,16 + dprintf("ip_rcv: got pkt not for me; for %u.%u.%u.%u\n", + 803bb48: 11403fcc andi r5,r2,255 + PUSH_IPADDR(pip->ip_dest)); + 803bb4c: e0bfff17 ldw r2,-4(fp) + 803bb50: 10800417 ldw r2,16(r2) + 803bb54: 1004d63a srli r2,r2,24 + dprintf("ip_rcv: got pkt not for me; for %u.%u.%u.%u\n", + 803bb58: d8800015 stw r2,0(sp) + 803bb5c: 280f883a mov r7,r5 + 803bb60: 200d883a mov r6,r4 + 803bb64: 180b883a mov r5,r3 + 803bb68: 01020174 movhi r4,2053 + 803bb6c: 212ca204 addi r4,r4,-19832 + 803bb70: 8002c780 call 8002c78 + +#ifdef IP_ROUTING /* if multi-homed router, try to route */ + /* Do routing only if ipForwarding is enabled in the IP MIB. This + * is the switch for routing whether SNMP is used or not. + */ + if (ip_mib.ipForwarding == 2) + 803bb74: 008201b4 movhi r2,2054 + 803bb78: 10b94f17 ldw r2,-6852(r2) + 803bb7c: 10800098 cmpnei r2,r2,2 + 803bb80: 10000d1e bne r2,zero,803bbb8 + { + ip_mib.ipOutDiscards++; /* Is this the right counter for these? */ + 803bb84: 008201b4 movhi r2,2054 + 803bb88: 10b95917 ldw r2,-6812(r2) + 803bb8c: 10c00044 addi r3,r2,1 + 803bb90: 008201b4 movhi r2,2054 + 803bb94: 10f95915 stw r3,-6812(r2) + LOCK_NET_RESOURCE(FREEQ_RESID); + 803bb98: 01000084 movi r4,2 + 803bb9c: 8028f380 call 8028f38 + pk_free(p); + 803bba0: e13ff917 ldw r4,-28(fp) + 803bba4: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803bba8: 01000084 movi r4,2 + 803bbac: 8028ff40 call 8028ff4 + IN_PROFILER(PF_IP, PF_EXIT); + return ENP_NO_ROUTE; + 803bbb0: 00bff7c4 movi r2,-33 + 803bbb4: 0000cf06 br 803bef4 + NET outnet; +#ifdef IP_FRAGMENTS + int err; +#endif + + ip_mib.ipForwDatagrams++; /* Count MIB-2 route attempts here */ + 803bbb8: 008201b4 movhi r2,2054 + 803bbbc: 10b95417 ldw r2,-6832(r2) + 803bbc0: 10c00044 addi r3,r2,1 + 803bbc4: 008201b4 movhi r2,2054 + 803bbc8: 10f95415 stw r3,-6832(r2) + if (pip->ip_time <= 1) /* Time to Live (hopcount) expired? */ + 803bbcc: e0bfff17 ldw r2,-4(fp) + 803bbd0: 10800203 ldbu r2,8(r2) + 803bbd4: 10803fcc andi r2,r2,255 + 803bbd8: 108000a8 cmpgeui r2,r2,2 + 803bbdc: 10001a1e bne r2,zero,803bc48 + { + ip_mib.ipOutDiscards++; /* Is this the right counter for these? */ + 803bbe0: 008201b4 movhi r2,2054 + 803bbe4: 10b95917 ldw r2,-6812(r2) + 803bbe8: 10c00044 addi r3,r2,1 + 803bbec: 008201b4 movhi r2,2054 + 803bbf0: 10f95915 stw r3,-6812(r2) +#ifdef FULL_ICMP + icmp_destun(pip->ip_src, p->net->n_ipaddr, pip, (TIMEX <<8), p->net); + 803bbf4: e0bfff17 ldw r2,-4(fp) + 803bbf8: 10c00317 ldw r3,12(r2) + 803bbfc: e0bff917 ldw r2,-28(fp) + 803bc00: 10800617 ldw r2,24(r2) + 803bc04: 11000a17 ldw r4,40(r2) + 803bc08: e0bff917 ldw r2,-28(fp) + 803bc0c: 10800617 ldw r2,24(r2) + 803bc10: d8800015 stw r2,0(sp) + 803bc14: 01c2c004 movi r7,2816 + 803bc18: e1bfff17 ldw r6,-4(fp) + 803bc1c: 200b883a mov r5,r4 + 803bc20: 1809883a mov r4,r3 + 803bc24: 8039a540 call 8039a54 +#endif /* FULL_ICMP */ + LOCK_NET_RESOURCE(FREEQ_RESID); + 803bc28: 01000084 movi r4,2 + 803bc2c: 8028f380 call 8028f38 + pk_free(p); + 803bc30: e13ff917 ldw r4,-28(fp) + 803bc34: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803bc38: 01000084 movi r4,2 + 803bc3c: 8028ff40 call 8028ff4 + IN_PROFILER(PF_IP, PF_EXIT); + return ENP_NO_ROUTE; + 803bc40: 00bff7c4 movi r2,-33 + 803bc44: 0000ab06 br 803bef4 + } + + p->fhost = pip->ip_dest; /* set packet's target IP in net endian */ + 803bc48: e0bfff17 ldw r2,-4(fp) + 803bc4c: 10c00417 ldw r3,16(r2) + 803bc50: e0bff917 ldw r2,-28(fp) + 803bc54: 10c00715 stw r3,28(r2) + if ((outnet = iproute(p->fhost, &firsthop)) == NULL) /* find route */ + 803bc58: e0bff917 ldw r2,-28(fp) + 803bc5c: 10800717 ldw r2,28(r2) + 803bc60: e0fffa04 addi r3,fp,-24 + 803bc64: 180b883a mov r5,r3 + 803bc68: 1009883a mov r4,r2 + 803bc6c: 803b3700 call 803b370 + 803bc70: e0bffc15 stw r2,-16(fp) + 803bc74: e0bffc17 ldw r2,-16(fp) + 803bc78: 10000d1e bne r2,zero,803bcb0 + { + ip_mib.ipOutNoRoutes++; /* count unroutable pkts */ + 803bc7c: 008201b4 movhi r2,2054 + 803bc80: 10b95a17 ldw r2,-6808(r2) + 803bc84: 10c00044 addi r3,r2,1 + 803bc88: 008201b4 movhi r2,2054 + 803bc8c: 10f95a15 stw r3,-6808(r2) + LOCK_NET_RESOURCE(FREEQ_RESID); + 803bc90: 01000084 movi r4,2 + 803bc94: 8028f380 call 8028f38 + pk_free(p); + 803bc98: e13ff917 ldw r4,-28(fp) + 803bc9c: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803bca0: 01000084 movi r4,2 + 803bca4: 8028ff40 call 8028ff4 + IN_PROFILER(PF_IP, PF_EXIT); + return ENP_NO_ROUTE; + 803bca8: 00bff7c4 movi r2,-33 + 803bcac: 00009106 br 803bef4 + /* Check to see if the packet was is addressed to one of our IP + * addresses other than the interface it was received on. If so, + * routing should have returned that interface and we can trap this + * situation by checking the interfaces IP address. + */ + if(pip->ip_dest == outnet->n_ipaddr) + 803bcb0: e0bfff17 ldw r2,-4(fp) + 803bcb4: 10c00417 ldw r3,16(r2) + 803bcb8: e0bffc17 ldw r2,-16(fp) + 803bcbc: 10800a17 ldw r2,40(r2) + 803bcc0: 18804526 beq r3,r2,803bdd8 + goto ours; + + /* Make sure the packet is not a subnet broadcast for either the + * source or destination network. + */ + if((pip->ip_dest == outnet->n_netbr) || + 803bcc4: e0bfff17 ldw r2,-4(fp) + 803bcc8: 10c00417 ldw r3,16(r2) + 803bccc: e0bffc17 ldw r2,-16(fp) + 803bcd0: 10800e17 ldw r2,56(r2) + 803bcd4: 18804226 beq r3,r2,803bde0 + (pip->ip_dest == p->net->n_netbr)) + 803bcd8: e0bfff17 ldw r2,-4(fp) + 803bcdc: 10c00417 ldw r3,16(r2) + 803bce0: e0bff917 ldw r2,-28(fp) + 803bce4: 10800617 ldw r2,24(r2) + 803bce8: 10800e17 ldw r2,56(r2) + if((pip->ip_dest == outnet->n_netbr) || + 803bcec: 18803c26 beq r3,r2,803bde0 + { + goto ours; + } + + /* Routed OK, prepare to send */ + p->net = outnet; /* set iface to send on */ + 803bcf0: e0bff917 ldw r2,-28(fp) + 803bcf4: e0fffc17 ldw r3,-16(fp) + 803bcf8: 10c00615 stw r3,24(r2) + } + } +#endif /* IPSEC */ + + /* see if packet is too big for media of dest net */ + if ((p->nb_plen + p->net->n_lnh) > (unsigned)outnet->n_mtu) + 803bcfc: e0bff917 ldw r2,-28(fp) + 803bd00: 10800417 ldw r2,16(r2) + 803bd04: e0fff917 ldw r3,-28(fp) + 803bd08: 18c00617 ldw r3,24(r3) + 803bd0c: 18c00817 ldw r3,32(r3) + 803bd10: 10c5883a add r2,r2,r3 + 803bd14: e0fffc17 ldw r3,-16(fp) + 803bd18: 18c00917 ldw r3,36(r3) + 803bd1c: 1880162e bgeu r3,r2,803bd78 + pip->ip_time--; /* datagram's hop count */ + err = ip_fragment(p, firsthop); + IN_PROFILER(PF_IP, PF_EXIT); + return(err); +#else /* IP fragments not supported? Bad news....*/ + dtrap(); /* this should be caught by programmers during development */ + 803bd20: 8028cd40 call 8028cd4 +#ifdef FULL_ICMP + icmp_destun(pip->ip_src, p->net->n_ipaddr, pip, DSTFRAG, p->net); + 803bd24: e0bfff17 ldw r2,-4(fp) + 803bd28: 10c00317 ldw r3,12(r2) + 803bd2c: e0bff917 ldw r2,-28(fp) + 803bd30: 10800617 ldw r2,24(r2) + 803bd34: 11000a17 ldw r4,40(r2) + 803bd38: e0bff917 ldw r2,-28(fp) + 803bd3c: 10800617 ldw r2,24(r2) + 803bd40: d8800015 stw r2,0(sp) + 803bd44: 01c00104 movi r7,4 + 803bd48: e1bfff17 ldw r6,-4(fp) + 803bd4c: 200b883a mov r5,r4 + 803bd50: 1809883a mov r4,r3 + 803bd54: 8039a540 call 8039a54 +#endif /* FULL_ICMP */ + LOCK_NET_RESOURCE(FREEQ_RESID); + 803bd58: 01000084 movi r4,2 + 803bd5c: 8028f380 call 8028f38 + pk_free(p); + 803bd60: e13ff917 ldw r4,-28(fp) + 803bd64: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803bd68: 01000084 movi r4,2 + 803bd6c: 8028ff40 call 8028ff4 + return ENP_LOGIC; + 803bd70: 00bffd44 movi r2,-11 + 803bd74: 00005f06 br 803bef4 +#endif /* IP_FRAGMENTS */ + } + pip->ip_time--; /* datagram's hop count */ + 803bd78: e0bfff17 ldw r2,-4(fp) + 803bd7c: 10800203 ldbu r2,8(r2) + 803bd80: 10bfffc4 addi r2,r2,-1 + 803bd84: 1007883a mov r3,r2 + 803bd88: e0bfff17 ldw r2,-4(fp) + 803bd8c: 10c00205 stb r3,8(r2) + pip->ip_chksum = IPXSUM; /* clear checksum field for summing */ + 803bd90: e0bfff17 ldw r2,-4(fp) + 803bd94: 1000028d sth zero,10(r2) + pip->ip_chksum = ~cksum(pip, 10); /* new xsum */ + 803bd98: 01400284 movi r5,10 + 803bd9c: e13fff17 ldw r4,-4(fp) + 803bda0: 8026d7c0 call 8026d7c + 803bda4: 0084303a nor r2,zero,r2 + 803bda8: 1007883a mov r3,r2 + 803bdac: e0bfff17 ldw r2,-4(fp) + 803bdb0: 10c0028d sth r3,10(r2) + IN_PROFILER(PF_IP, PF_EXIT); +#ifdef RF_SIMULATION + if(rfsim_routing) + return(rfsim_send(p, firsthop)); +#endif /* RF_SIMULATION */ + return(ip2mac(p, firsthop)); + 803bdb4: e0bffa17 ldw r2,-24(fp) + 803bdb8: 100b883a mov r5,r2 + 803bdbc: e13ff917 ldw r4,-28(fp) + 803bdc0: 8024df40 call 8024df4 + 803bdc4: 00004b06 br 803bef4 + goto ours; + 803bdc8: 0001883a nop + 803bdcc: 00000506 br 803bde4 + return(ENP_NOT_MINE); +#endif + } + +#if defined (IP_MULTICAST) || defined (IP_ROUTING) +ours: + 803bdd0: 0001883a nop + 803bdd4: 00000306 br 803bde4 + goto ours; + 803bdd8: 0001883a nop + 803bddc: 00000106 br 803bde4 + goto ours; + 803bde0: 0001883a nop +#endif + + /* Test for fragment: */ + tempsum = htons(pip->ip_flgs_foff); /* borrow cksum variable */ + 803bde4: e0bfff17 ldw r2,-4(fp) + 803bde8: 1080018b ldhu r2,6(r2) + 803bdec: 10bfffcc andi r2,r2,65535 + 803bdf0: 1004d23a srli r2,r2,8 + 803bdf4: 1007883a mov r3,r2 + 803bdf8: e0bfff17 ldw r2,-4(fp) + 803bdfc: 1080018b ldhu r2,6(r2) + 803be00: 10bfffcc andi r2,r2,65535 + 803be04: 1004923a slli r2,r2,8 + 803be08: 1884b03a or r2,r3,r2 + 803be0c: e0bffb8d sth r2,-18(fp) + if ((tempsum & IP_FLG_MF) || /* IP flag for "More Fragments" set? */ + 803be10: e0bffb8b ldhu r2,-18(fp) + 803be14: 1088000c andi r2,r2,8192 + 803be18: 1000051e bne r2,zero,803be30 + (tempsum & ~IP_FLG_MASK)) /* or offset to last frag? */ + 803be1c: e0fffb8b ldhu r3,-18(fp) + 803be20: 00bffff4 movhi r2,65535 + 803be24: 1087ffc4 addi r2,r2,8191 + 803be28: 1884703a and r2,r3,r2 + if ((tempsum & IP_FLG_MF) || /* IP flag for "More Fragments" set? */ + 803be2c: 10002f26 beq r2,zero,803beec + { +#ifdef NPDEBUG + if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE)) + 803be30: d0a06617 ldw r2,-32360(gp) + 803be34: 1081000c andi r2,r2,1024 + 803be38: 10001a26 beq r2,zero,803bea4 + 803be3c: d0a06617 ldw r2,-32360(gp) + 803be40: 1080800c andi r2,r2,512 + 803be44: 10001726 beq r2,zero,803bea4 + { + dprintf("ip_rcv: fragment from %u.%u.%u.%u\n", + PUSH_IPADDR(pip->ip_src)); + 803be48: e0bfff17 ldw r2,-4(fp) + 803be4c: 10800317 ldw r2,12(r2) + dprintf("ip_rcv: fragment from %u.%u.%u.%u\n", + 803be50: 10c03fcc andi r3,r2,255 + PUSH_IPADDR(pip->ip_src)); + 803be54: e0bfff17 ldw r2,-4(fp) + 803be58: 10800317 ldw r2,12(r2) + 803be5c: 1004d23a srli r2,r2,8 + dprintf("ip_rcv: fragment from %u.%u.%u.%u\n", + 803be60: 11003fcc andi r4,r2,255 + PUSH_IPADDR(pip->ip_src)); + 803be64: e0bfff17 ldw r2,-4(fp) + 803be68: 10800317 ldw r2,12(r2) + 803be6c: 1004d43a srli r2,r2,16 + dprintf("ip_rcv: fragment from %u.%u.%u.%u\n", + 803be70: 11403fcc andi r5,r2,255 + PUSH_IPADDR(pip->ip_src)); + 803be74: e0bfff17 ldw r2,-4(fp) + 803be78: 10800317 ldw r2,12(r2) + 803be7c: 1004d63a srli r2,r2,24 + dprintf("ip_rcv: fragment from %u.%u.%u.%u\n", + 803be80: d8800015 stw r2,0(sp) + 803be84: 280f883a mov r7,r5 + 803be88: 200d883a mov r6,r4 + 803be8c: 180b883a mov r5,r3 + 803be90: 01020174 movhi r4,2053 + 803be94: 212cae04 addi r4,r4,-19784 + 803be98: 8002c780 call 8002c78 + ip_dump(p); + 803be9c: e13ff917 ldw r4,-28(fp) + 803bea0: 803b0cc0 call 803b0cc + } +#endif + ip_mib.ipReasmReqds++; /* got a reassemble request; ie a frag */ + 803bea4: 008201b4 movhi r2,2054 + 803bea8: 10b95c17 ldw r2,-6800(r2) + 803beac: 10c00044 addi r3,r2,1 + 803beb0: 008201b4 movhi r2,2054 + 803beb4: 10f95c15 stw r3,-6800(r2) +#ifdef IP_FRAGMENTS + return(ip_reassm(p)); +#else + ip_mib.ipReasmFails++; /* we don't do these */ + 803beb8: 008201b4 movhi r2,2054 + 803bebc: 10b95e17 ldw r2,-6792(r2) + 803bec0: 10c00044 addi r3,r2,1 + 803bec4: 008201b4 movhi r2,2054 + 803bec8: 10f95e15 stw r3,-6792(r2) + LOCK_NET_RESOURCE(FREEQ_RESID); + 803becc: 01000084 movi r4,2 + 803bed0: 8028f380 call 8028f38 + pk_free(p); + 803bed4: e13ff917 ldw r4,-28(fp) + 803bed8: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803bedc: 01000084 movi r4,2 + 803bee0: 8028ff40 call 8028ff4 + IN_PROFILER(PF_IP, PF_EXIT); + return ENP_NOT_MINE; /* perhaps should be ENP_BAD_HEADER? */ + 803bee4: 00800084 movi r2,2 + 803bee8: 00000206 br 803bef4 + { + return ENP_LOGIC; + } +#endif /* IPSEC */ + + return(ip_demux(p)); /* demux to correct to upper layer */ + 803beec: e13ff917 ldw r4,-28(fp) + 803bef0: 803bf080 call 803bf08 +} + 803bef4: e037883a mov sp,fp + 803bef8: dfc00117 ldw ra,4(sp) + 803befc: df000017 ldw fp,0(sp) + 803bf00: dec00204 addi sp,sp,8 + 803bf04: f800283a ret + +0803bf08 : + * RETURNS: Same return values as ip_rcv(). + */ + +int +ip_demux(PACKET p) +{ + 803bf08: defff904 addi sp,sp,-28 + 803bf0c: dfc00615 stw ra,24(sp) + 803bf10: df000515 stw fp,20(sp) + 803bf14: df000504 addi fp,sp,20 + 803bf18: e13ffd15 stw r4,-12(fp) + int err; + + /* The packet is verified; the header is correct. Now we have + * to demultiplex it among our internet connections. + */ + pip = (struct ip *)(p->nb_prot); + 803bf1c: e0bffd17 ldw r2,-12(fp) + 803bf20: 10800317 ldw r2,12(r2) + 803bf24: e0bffe15 stw r2,-8(fp) + +#ifdef NPDEBUG + /* make sure the caller set p->nb_prot */ + if(pip->ip_ver_ihl != 0x45) + 803bf28: e0bffe17 ldw r2,-8(fp) + 803bf2c: 10800003 ldbu r2,0(r2) + 803bf30: 10803fcc andi r2,r2,255 + 803bf34: 10801160 cmpeqi r2,r2,69 + 803bf38: 1000131e bne r2,zero,803bf88 + { + if((pip->ip_ver_ihl < 0x45) || + 803bf3c: e0bffe17 ldw r2,-8(fp) + 803bf40: 10800003 ldbu r2,0(r2) + 803bf44: 10803fcc andi r2,r2,255 + 803bf48: 10801170 cmpltui r2,r2,69 + 803bf4c: 1000051e bne r2,zero,803bf64 + (pip->ip_ver_ihl > 0x47)) + 803bf50: e0bffe17 ldw r2,-8(fp) + 803bf54: 10800003 ldbu r2,0(r2) + if((pip->ip_ver_ihl < 0x45) || + 803bf58: 10803fcc andi r2,r2,255 + 803bf5c: 10801230 cmpltui r2,r2,72 + 803bf60: 1000091e bne r2,zero,803bf88 + { + dprintf("ip_demux: bad IP type 0x%x\n", pip->ip_ver_ihl); + 803bf64: e0bffe17 ldw r2,-8(fp) + 803bf68: 10800003 ldbu r2,0(r2) + 803bf6c: 10803fcc andi r2,r2,255 + 803bf70: 100b883a mov r5,r2 + 803bf74: 01020174 movhi r4,2053 + 803bf78: 212cb704 addi r4,r4,-19748 + 803bf7c: 8002c780 call 8002c78 + return ENP_LOGIC; + 803bf80: 00bffd44 movi r2,-11 + 803bf84: 0000c406 br 803c298 + + /* for profiling purposes count the upper layers (UDP, ICMP) in the IP + * profile bucket. TCP will insert it's own nested profile calls + */ + IN_PROFILER(PF_IP, PF_ENTRY); + p->fhost = pip->ip_src; + 803bf88: e0bffe17 ldw r2,-8(fp) + 803bf8c: 10c00317 ldw r3,12(r2) + 803bf90: e0bffd17 ldw r2,-12(fp) + 803bf94: 10c00715 stw r3,28(r2) + +#ifdef NPDEBUG + if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE)) + 803bf98: d0a06617 ldw r2,-32360(gp) + 803bf9c: 1081000c andi r2,r2,1024 + 803bfa0: 10002126 beq r2,zero,803c028 + 803bfa4: d0a06617 ldw r2,-32360(gp) + 803bfa8: 1080800c andi r2,r2,512 + 803bfac: 10001e26 beq r2,zero,803c028 + { + dprintf("ip_demux: pkt prot %u from %u.%u.%u.%u\n", + pip->ip_prot, PUSH_IPADDR(pip->ip_src)); + 803bfb0: e0bffe17 ldw r2,-8(fp) + 803bfb4: 10800243 ldbu r2,9(r2) + dprintf("ip_demux: pkt prot %u from %u.%u.%u.%u\n", + 803bfb8: 11003fcc andi r4,r2,255 + pip->ip_prot, PUSH_IPADDR(pip->ip_src)); + 803bfbc: e0bffe17 ldw r2,-8(fp) + 803bfc0: 10800317 ldw r2,12(r2) + dprintf("ip_demux: pkt prot %u from %u.%u.%u.%u\n", + 803bfc4: 11403fcc andi r5,r2,255 + pip->ip_prot, PUSH_IPADDR(pip->ip_src)); + 803bfc8: e0bffe17 ldw r2,-8(fp) + 803bfcc: 10800317 ldw r2,12(r2) + 803bfd0: 1004d23a srli r2,r2,8 + dprintf("ip_demux: pkt prot %u from %u.%u.%u.%u\n", + 803bfd4: 11803fcc andi r6,r2,255 + pip->ip_prot, PUSH_IPADDR(pip->ip_src)); + 803bfd8: e0bffe17 ldw r2,-8(fp) + 803bfdc: 10800317 ldw r2,12(r2) + 803bfe0: 1004d43a srli r2,r2,16 + dprintf("ip_demux: pkt prot %u from %u.%u.%u.%u\n", + 803bfe4: 10803fcc andi r2,r2,255 + pip->ip_prot, PUSH_IPADDR(pip->ip_src)); + 803bfe8: e0fffe17 ldw r3,-8(fp) + 803bfec: 18c00317 ldw r3,12(r3) + 803bff0: 1806d63a srli r3,r3,24 + dprintf("ip_demux: pkt prot %u from %u.%u.%u.%u\n", + 803bff4: d8c00115 stw r3,4(sp) + 803bff8: d8800015 stw r2,0(sp) + 803bffc: 300f883a mov r7,r6 + 803c000: 280d883a mov r6,r5 + 803c004: 200b883a mov r5,r4 + 803c008: 01020174 movhi r4,2053 + 803c00c: 212cbe04 addi r4,r4,-19720 + 803c010: 8002c780 call 8002c78 + if (NDEBUG & DUMP) ip_dump(p); + 803c014: d0a06617 ldw r2,-32360(gp) + 803c018: 1080008c andi r2,r2,2 + 803c01c: 10000226 beq r2,zero,803c028 + 803c020: e13ffd17 ldw r4,-12(fp) + 803c024: 803b0cc0 call 803b0cc + } +#endif + + switch (pip->ip_prot) + 803c028: e0bffe17 ldw r2,-8(fp) + 803c02c: 10800243 ldbu r2,9(r2) + 803c030: 10803fcc andi r2,r2,255 + 803c034: 10c000a0 cmpeqi r3,r2,2 + 803c038: 18001b1e bne r3,zero,803c0a8 + 803c03c: 10c000c8 cmpgei r3,r2,3 + 803c040: 1800031e bne r3,zero,803c050 + 803c044: 10800060 cmpeqi r2,r2,1 + 803c048: 10000e1e bne r2,zero,803c084 + 803c04c: 00002806 br 803c0f0 + 803c050: 10c001a0 cmpeqi r3,r2,6 + 803c054: 18001d1e bne r3,zero,803c0cc + 803c058: 10800458 cmpnei r2,r2,17 + 803c05c: 1000241e bne r2,zero,803c0f0 + { + case UDP_PROT: + ip_mib.ipInDelivers++; + 803c060: 008201b4 movhi r2,2054 + 803c064: 10b95717 ldw r2,-6820(r2) + 803c068: 10c00044 addi r3,r2,1 + 803c06c: 008201b4 movhi r2,2054 + 803c070: 10f95715 stw r3,-6820(r2) + err = udpdemux(p); + 803c074: e13ffd17 ldw r4,-12(fp) + 803c078: 803d1340 call 803d134 + 803c07c: e0bfff15 stw r2,-4(fp) + break; + 803c080: 00002406 br 803c114 + case ICMP_PROT: + ip_mib.ipInDelivers++; + 803c084: 008201b4 movhi r2,2054 + 803c088: 10b95717 ldw r2,-6820(r2) + 803c08c: 10c00044 addi r3,r2,1 + 803c090: 008201b4 movhi r2,2054 + 803c094: 10f95715 stw r3,-6820(r2) + err = icmprcv(p); + 803c098: e13ffd17 ldw r4,-12(fp) + 803c09c: 8038f780 call 8038f78 + 803c0a0: e0bfff15 stw r2,-4(fp) + break; + 803c0a4: 00001b06 br 803c114 +#if defined (IP_MULTICAST) && (defined (IGMP_V1) || defined (IGMP_V2)) + case IGMP_PROT: + ip_mib.ipInDelivers++; + 803c0a8: 008201b4 movhi r2,2054 + 803c0ac: 10b95717 ldw r2,-6820(r2) + 803c0b0: 10c00044 addi r3,r2,1 + 803c0b4: 008201b4 movhi r2,2054 + 803c0b8: 10f95715 stw r3,-6820(r2) + err = igmp_input(p); + 803c0bc: e13ffd17 ldw r4,-12(fp) + 803c0c0: 802541c0 call 802541c + 803c0c4: e0bfff15 stw r2,-4(fp) + break; + 803c0c8: 00001206 br 803c114 +#endif /* IP_MULTICAST and (IGMPv1 or IGMPv2) */ +#ifdef INCLUDE_TCP + case TCP_PROT: + ip_mib.ipInDelivers++; + 803c0cc: 008201b4 movhi r2,2054 + 803c0d0: 10b95717 ldw r2,-6820(r2) + 803c0d4: 10c00044 addi r3,r2,1 + 803c0d8: 008201b4 movhi r2,2054 + 803c0dc: 10f95715 stw r3,-6820(r2) + err = tcp_rcv(p); + 803c0e0: e13ffd17 ldw r4,-12(fp) + 803c0e4: 802a4a40 call 802a4a4 + 803c0e8: e0bfff15 stw r2,-4(fp) + break; + 803c0ec: 00000906 br 803c114 + err = v6t_rcv(p); + break; +#endif /* IPV6_TUNNEL */ + default: /* unknown upper protocol */ +#ifdef IP_RAW + ip_mib.ipInDelivers++; + 803c0f0: 008201b4 movhi r2,2054 + 803c0f4: 10b95717 ldw r2,-6820(r2) + 803c0f8: 10c00044 addi r3,r2,1 + 803c0fc: 008201b4 movhi r2,2054 + 803c100: 10f95715 stw r3,-6820(r2) + err = ip_raw_input(p); + 803c104: e13ffd17 ldw r4,-12(fp) + 803c108: 803c7d00 call 803c7d0 + 803c10c: e0bfff15 stw r2,-4(fp) + break; + 803c110: 0001883a nop +#endif /* IP_RAW */ + } + + IN_PROFILER(PF_IP, PF_EXIT); + + if(err != ENP_PARAM) + 803c114: e0bfff17 ldw r2,-4(fp) + 803c118: 10bffda0 cmpeqi r2,r2,-10 + 803c11c: 1000021e bne r2,zero,803c128 + { + return err; + 803c120: e0bfff17 ldw r2,-4(fp) + 803c124: 00005c06 br 803c298 + +#ifdef FULL_ICMP + /* nobody's listening for this packet. Unless it was broadcast or + * multicast, send a destination unreachable. + */ + if ((pip->ip_dest != 0xffffffffL) && /* Physical cable broadcast addr*/ + 803c128: e0bffe17 ldw r2,-8(fp) + 803c12c: 10800417 ldw r2,16(r2) + 803c130: 10bfffe0 cmpeqi r2,r2,-1 + 803c134: 10004c1e bne r2,zero,803c268 +#ifdef IP_MULTICAST + (!(IN_MULTICAST(ntohl(pip->ip_dest)))) && /* multicast address */ + 803c138: e0bffe17 ldw r2,-8(fp) + 803c13c: 10800417 ldw r2,16(r2) + 803c140: 1006d63a srli r3,r2,24 + 803c144: e0bffe17 ldw r2,-8(fp) + 803c148: 10800417 ldw r2,16(r2) + 803c14c: 1004d23a srli r2,r2,8 + 803c150: 10bfc00c andi r2,r2,65280 + 803c154: 1886b03a or r3,r3,r2 + 803c158: e0bffe17 ldw r2,-8(fp) + 803c15c: 10800417 ldw r2,16(r2) + 803c160: 1004923a slli r2,r2,8 + 803c164: 10803fec andhi r2,r2,255 + 803c168: 1886b03a or r3,r3,r2 + 803c16c: e0bffe17 ldw r2,-8(fp) + 803c170: 10800417 ldw r2,16(r2) + 803c174: 1004963a slli r2,r2,24 + 803c178: 1884b03a or r2,r3,r2 + 803c17c: 10fc002c andhi r3,r2,61440 + if ((pip->ip_dest != 0xffffffffL) && /* Physical cable broadcast addr*/ + 803c180: 00b80034 movhi r2,57344 + 803c184: 18803826 beq r3,r2,803c268 +#endif /* IP_MULTICAST */ + (pip->ip_dest != p->net->n_netbr) && /* All subnet broadcast */ + 803c188: e0bffe17 ldw r2,-8(fp) + 803c18c: 10c00417 ldw r3,16(r2) + 803c190: e0bffd17 ldw r2,-12(fp) + 803c194: 10800617 ldw r2,24(r2) + 803c198: 10800e17 ldw r2,56(r2) + (!(IN_MULTICAST(ntohl(pip->ip_dest)))) && /* multicast address */ + 803c19c: 18803226 beq r3,r2,803c268 + (pip->ip_dest != p->net->n_netbr42) && /* All subnet bcast (4.2bsd) */ + 803c1a0: e0bffe17 ldw r2,-8(fp) + 803c1a4: 10c00417 ldw r3,16(r2) + 803c1a8: e0bffd17 ldw r2,-12(fp) + 803c1ac: 10800617 ldw r2,24(r2) + 803c1b0: 10800f17 ldw r2,60(r2) + (pip->ip_dest != p->net->n_netbr) && /* All subnet broadcast */ + 803c1b4: 18802c26 beq r3,r2,803c268 + (pip->ip_dest != p->net->n_subnetbr) && /* Our subnet broadcast */ + 803c1b8: e0bffe17 ldw r2,-8(fp) + 803c1bc: 10c00417 ldw r3,16(r2) + 803c1c0: e0bffd17 ldw r2,-12(fp) + 803c1c4: 10800617 ldw r2,24(r2) + 803c1c8: 10801017 ldw r2,64(r2) + (pip->ip_dest != p->net->n_netbr42) && /* All subnet bcast (4.2bsd) */ + 803c1cc: 18802626 beq r3,r2,803c268 + (p->net->n_ipaddr ^ p->net->n_subnetbr)) /* Know our own host address? */ + 803c1d0: e0bffd17 ldw r2,-12(fp) + 803c1d4: 10800617 ldw r2,24(r2) + 803c1d8: 10c00a17 ldw r3,40(r2) + 803c1dc: e0bffd17 ldw r2,-12(fp) + 803c1e0: 10800617 ldw r2,24(r2) + 803c1e4: 10801017 ldw r2,64(r2) + (pip->ip_dest != p->net->n_subnetbr) && /* Our subnet broadcast */ + 803c1e8: 18801f26 beq r3,r2,803c268 + { + +#ifdef NPDEBUG + if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE)) + 803c1ec: d0a06617 ldw r2,-32360(gp) + 803c1f0: 1081000c andi r2,r2,1024 + 803c1f4: 10000f26 beq r2,zero,803c234 + 803c1f8: d0a06617 ldw r2,-32360(gp) + 803c1fc: 1080800c andi r2,r2,512 + 803c200: 10000c26 beq r2,zero,803c234 + { + dprintf("ip_demux: unhandled prot %u\n", pip->ip_prot); + 803c204: e0bffe17 ldw r2,-8(fp) + 803c208: 10800243 ldbu r2,9(r2) + 803c20c: 10803fcc andi r2,r2,255 + 803c210: 100b883a mov r5,r2 + 803c214: 01020174 movhi r4,2053 + 803c218: 212cc804 addi r4,r4,-19680 + 803c21c: 8002c780 call 8002c78 + if (NDEBUG & DUMP) ip_dump(p); + 803c220: d0a06617 ldw r2,-32360(gp) + 803c224: 1080008c andi r2,r2,2 + 803c228: 10000226 beq r2,zero,803c234 + 803c22c: e13ffd17 ldw r4,-12(fp) + 803c230: 803b0cc0 call 803b0cc + } +#endif /* NPDEBUG */ + icmp_destun(pip->ip_src, p->net->n_ipaddr, pip, DSTPROT, p->net); + 803c234: e0bffe17 ldw r2,-8(fp) + 803c238: 10c00317 ldw r3,12(r2) + 803c23c: e0bffd17 ldw r2,-12(fp) + 803c240: 10800617 ldw r2,24(r2) + 803c244: 11000a17 ldw r4,40(r2) + 803c248: e0bffd17 ldw r2,-12(fp) + 803c24c: 10800617 ldw r2,24(r2) + 803c250: d8800015 stw r2,0(sp) + 803c254: 01c00084 movi r7,2 + 803c258: e1bffe17 ldw r6,-8(fp) + 803c25c: 200b883a mov r5,r4 + 803c260: 1809883a mov r4,r3 + 803c264: 8039a540 call 8039a54 + } +#endif /* FULL_ICMP */ + + ip_mib.ipUnknownProtos++; + 803c268: 008201b4 movhi r2,2054 + 803c26c: 10b95517 ldw r2,-6828(r2) + 803c270: 10c00044 addi r3,r2,1 + 803c274: 008201b4 movhi r2,2054 + 803c278: 10f95515 stw r3,-6828(r2) + LOCK_NET_RESOURCE(FREEQ_RESID); + 803c27c: 01000084 movi r4,2 + 803c280: 8028f380 call 8028f38 + pk_free(p); + 803c284: e13ffd17 ldw r4,-12(fp) + 803c288: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803c28c: 01000084 movi r4,2 + 803c290: 8028ff40 call 8028ff4 + return ENP_NOT_MINE; + 803c294: 00800084 movi r2,2 +} + 803c298: e037883a mov sp,fp + 803c29c: dfc00117 ldw ra,4(sp) + 803c2a0: df000017 ldw fp,0(sp) + 803c2a4: dec00204 addi sp,sp,8 + 803c2a8: f800283a ret + +0803c2ac : + * RETURNS: + */ + +struct in_multi * +in_addmulti(ip_addr *ap, struct net *netp, int addrtype) +{ + 803c2ac: defff904 addi sp,sp,-28 + 803c2b0: dfc00615 stw ra,24(sp) + 803c2b4: df000515 stw fp,20(sp) + 803c2b8: df000504 addi fp,sp,20 + 803c2bc: e13ffd15 stw r4,-12(fp) + 803c2c0: e17ffc15 stw r5,-16(fp) + 803c2c4: e1bffb15 stw r6,-20(fp) + struct in_multi *inm = (struct in_multi *)NULL; + 803c2c8: e03fff15 stw zero,-4(fp) + int error; + + /* check for good addr. */ + if ((ap == (ip_addr *)NULL) || (*ap == 0)) + 803c2cc: e0bffd17 ldw r2,-12(fp) + 803c2d0: 10000326 beq r2,zero,803c2e0 + 803c2d4: e0bffd17 ldw r2,-12(fp) + 803c2d8: 10800017 ldw r2,0(r2) + 803c2dc: 1000021e bne r2,zero,803c2e8 + return ((struct in_multi *)NULL); + 803c2e0: 0005883a mov r2,zero + 803c2e4: 00003f06 br 803c3e4 + + ENTER_CRIT_SECTION(netp); + 803c2e8: 8028e940 call 8028e94 +#ifdef IP_V6 + if(addrtype == 6) + inm = v6_lookup_mcast((ip6_addr*)ap, netp); +#endif +#ifdef IP_V4 + if(addrtype != 6) + 803c2ec: e0bffb17 ldw r2,-20(fp) + 803c2f0: 108001a0 cmpeqi r2,r2,6 + 803c2f4: 1000061e bne r2,zero,803c310 + inm = lookup_mcast(*ap, netp); + 803c2f8: e0bffd17 ldw r2,-12(fp) + 803c2fc: 10800017 ldw r2,0(r2) + 803c300: e17ffc17 ldw r5,-16(fp) + 803c304: 1009883a mov r4,r2 + 803c308: 803c5040 call 803c504 + 803c30c: e0bfff15 stw r2,-4(fp) +#endif + + if (inm != (struct in_multi *)NULL) + 803c310: e0bfff17 ldw r2,-4(fp) + 803c314: 10000626 beq r2,zero,803c330 + { + /* Found it; just increment the reference count. */ + ++inm->inm_refcount; + 803c318: e0bfff17 ldw r2,-4(fp) + 803c31c: 10800217 ldw r2,8(r2) + 803c320: 10c00044 addi r3,r2,1 + 803c324: e0bfff17 ldw r2,-4(fp) + 803c328: 10c00215 stw r3,8(r2) + 803c32c: 00002b06 br 803c3dc + { + /* + * New address; allocate a new multicast record + * and link it into the interface's multicast list. + */ + inm = (struct in_multi *)INM_ALLOC(sizeof(*inm)); + 803c330: 01000604 movi r4,24 + 803c334: 802982c0 call 802982c + 803c338: e0bfff15 stw r2,-4(fp) + + if (inm == (struct in_multi *)NULL) + 803c33c: e0bfff17 ldw r2,-4(fp) + 803c340: 1000031e bne r2,zero,803c350 + { + EXIT_CRIT_SECTION(netp); + 803c344: 8028ef40 call 8028ef4 + return ((struct in_multi *)NULL); + 803c348: 0005883a mov r2,zero + 803c34c: 00002506 br 803c3e4 +#ifdef IP_V6 + if(addrtype == 6) + IP6CPY(&inm->ip6addr, (struct in6_addr *)ap); +#endif +#ifdef IP_V4 + if(addrtype != 6) + 803c350: e0bffb17 ldw r2,-20(fp) + 803c354: 108001a0 cmpeqi r2,r2,6 + 803c358: 1000041e bne r2,zero,803c36c + inm->inm_addr = *ap; + 803c35c: e0bffd17 ldw r2,-12(fp) + 803c360: 10c00017 ldw r3,0(r2) + 803c364: e0bfff17 ldw r2,-4(fp) + 803c368: 10c00015 stw r3,0(r2) +#endif + inm->inm_netp = netp; + 803c36c: e0bfff17 ldw r2,-4(fp) + 803c370: e0fffc17 ldw r3,-16(fp) + 803c374: 10c00115 stw r3,4(r2) + inm->inm_refcount = 1; + 803c378: e0bfff17 ldw r2,-4(fp) + 803c37c: 00c00044 movi r3,1 + 803c380: 10c00215 stw r3,8(r2) + inm->inm_next = netp->mc_list; + 803c384: e0bffc17 ldw r2,-16(fp) + 803c388: 10c02c17 ldw r3,176(r2) + 803c38c: e0bfff17 ldw r2,-4(fp) + 803c390: 10c00515 stw r3,20(r2) + netp->mc_list = inm; + 803c394: e0bffc17 ldw r2,-16(fp) + 803c398: e0ffff17 ldw r3,-4(fp) + 803c39c: 10c02c15 stw r3,176(r2) + /* + * If net has a multicast address registration routine then ask + * the network driver to update its multicast reception + * filter appropriately for the new address. + */ + if(netp->n_mcastlist) + 803c3a0: e0bffc17 ldw r2,-16(fp) + 803c3a4: 10802b17 ldw r2,172(r2) + 803c3a8: 10000626 beq r2,zero,803c3c4 + error = netp->n_mcastlist(inm); + 803c3ac: e0bffc17 ldw r2,-16(fp) + 803c3b0: 10802b17 ldw r2,172(r2) + 803c3b4: e13fff17 ldw r4,-4(fp) + 803c3b8: 103ee83a callr r2 + 803c3bc: e0bffe15 stw r2,-8(fp) + 803c3c0: 00000106 br 803c3c8 + else + error = 0; + 803c3c4: e03ffe15 stw zero,-8(fp) +#if defined (IGMP_V1) || defined (IGMP_V2) + /* + * Let IGMP know that we have joined a new IP multicast group. + */ + if (inm->inm_addr) igmp_joingroup(inm); + 803c3c8: e0bfff17 ldw r2,-4(fp) + 803c3cc: 10800017 ldw r2,0(r2) + 803c3d0: 10000226 beq r2,zero,803c3dc + 803c3d4: e13fff17 ldw r4,-4(fp) + 803c3d8: 80258d80 call 80258d8 +#endif + } + + EXIT_CRIT_SECTION(netp); + 803c3dc: 8028ef40 call 8028ef4 + USE_ARG(error); + + return (inm); + 803c3e0: e0bfff17 ldw r2,-4(fp) +} + 803c3e4: e037883a mov sp,fp + 803c3e8: dfc00117 ldw ra,4(sp) + 803c3ec: df000017 ldw fp,0(sp) + 803c3f0: dec00204 addi sp,sp,8 + 803c3f4: f800283a ret + +0803c3f8 : + * RETURNS: + */ + +void +in_delmulti(struct in_multi * inm) +{ + 803c3f8: defffa04 addi sp,sp,-24 + 803c3fc: dfc00515 stw ra,20(sp) + 803c400: df000415 stw fp,16(sp) + 803c404: df000404 addi fp,sp,16 + 803c408: e13ffc15 stw r4,-16(fp) + struct in_multi * p; + NET netp = inm->inm_netp; + 803c40c: e0bffc17 ldw r2,-16(fp) + 803c410: 10800117 ldw r2,4(r2) + 803c414: e0bffd15 stw r2,-12(fp) + int error; + + ENTER_CRIT_SECTION(inm); + 803c418: 8028e940 call 8028e94 + if (--inm->inm_refcount == 0) + 803c41c: e0bffc17 ldw r2,-16(fp) + 803c420: 10800217 ldw r2,8(r2) + 803c424: 10ffffc4 addi r3,r2,-1 + 803c428: e0bffc17 ldw r2,-16(fp) + 803c42c: 10c00215 stw r3,8(r2) + 803c430: e0bffc17 ldw r2,-16(fp) + 803c434: 10800217 ldw r2,8(r2) + 803c438: 10002b1e bne r2,zero,803c4e8 + { + /* Unlink from list. */ + for (p = netp->mc_list; p; p = p->inm_next) + 803c43c: e0bffd17 ldw r2,-12(fp) + 803c440: 10802c17 ldw r2,176(r2) + 803c444: e0bfff15 stw r2,-4(fp) + 803c448: 00001406 br 803c49c + { + if(p == inm) /* inm is first in mc_list */ + 803c44c: e0ffff17 ldw r3,-4(fp) + 803c450: e0bffc17 ldw r2,-16(fp) + 803c454: 1880051e bne r3,r2,803c46c + { + netp->mc_list = p->inm_next; /* unlink */ + 803c458: e0bfff17 ldw r2,-4(fp) + 803c45c: 10c00517 ldw r3,20(r2) + 803c460: e0bffd17 ldw r2,-12(fp) + 803c464: 10c02c15 stw r3,176(r2) + break; + 803c468: 00000e06 br 803c4a4 + } + else if(p->inm_next == inm) /* inm is next */ + 803c46c: e0bfff17 ldw r2,-4(fp) + 803c470: 10800517 ldw r2,20(r2) + 803c474: e0fffc17 ldw r3,-16(fp) + 803c478: 1880051e bne r3,r2,803c490 + { + p->inm_next = inm->inm_next; /* unlink */ + 803c47c: e0bffc17 ldw r2,-16(fp) + 803c480: 10c00517 ldw r3,20(r2) + 803c484: e0bfff17 ldw r2,-4(fp) + 803c488: 10c00515 stw r3,20(r2) + break; + 803c48c: 00000506 br 803c4a4 + for (p = netp->mc_list; p; p = p->inm_next) + 803c490: e0bfff17 ldw r2,-4(fp) + 803c494: 10800517 ldw r2,20(r2) + 803c498: e0bfff15 stw r2,-4(fp) + 803c49c: e0bfff17 ldw r2,-4(fp) + 803c4a0: 103fea1e bne r2,zero,803c44c + /* + * If net has a multicast address registration routine then ask + * the network driver to update its multicast reception + * filter appropriately for the deleted address. + */ + if(netp->n_mcastlist) + 803c4a4: e0bffd17 ldw r2,-12(fp) + 803c4a8: 10802b17 ldw r2,172(r2) + 803c4ac: 10000626 beq r2,zero,803c4c8 + error = netp->n_mcastlist(inm); + 803c4b0: e0bffd17 ldw r2,-12(fp) + 803c4b4: 10802b17 ldw r2,172(r2) + 803c4b8: e13ffc17 ldw r4,-16(fp) + 803c4bc: 103ee83a callr r2 + 803c4c0: e0bffe15 stw r2,-8(fp) + 803c4c4: 00000106 br 803c4cc + else + error = 0; + 803c4c8: e03ffe15 stw zero,-8(fp) +#if defined (IGMP_V2) + /* + * No remaining claims to this record; let IGMP know that + * we are leaving the multicast group. + */ + if (inm->inm_addr) igmp_leavegroup(inm); + 803c4cc: e0bffc17 ldw r2,-16(fp) + 803c4d0: 10800017 ldw r2,0(r2) + 803c4d4: 10000226 beq r2,zero,803c4e0 + 803c4d8: e13ffc17 ldw r4,-16(fp) + 803c4dc: 8025b040 call 8025b04 +#endif + + IM_FREE(inm); + 803c4e0: e13ffc17 ldw r4,-16(fp) + 803c4e4: 80298600 call 8029860 + } + + EXIT_CRIT_SECTION(inm); + 803c4e8: 8028ef40 call 8028ef4 + USE_ARG(error); +} + 803c4ec: 0001883a nop + 803c4f0: e037883a mov sp,fp + 803c4f4: dfc00117 ldw ra,4(sp) + 803c4f8: df000017 ldw fp,0(sp) + 803c4fc: dec00204 addi sp,sp,8 + 803c500: f800283a ret + +0803c504 : + * RETURNS: pointer to mcast addr structure, or NULL if not found. + */ + +struct in_multi * +lookup_mcast(ip_addr addr, NET netp) +{ + 803c504: defffc04 addi sp,sp,-16 + 803c508: df000315 stw fp,12(sp) + 803c50c: df000304 addi fp,sp,12 + 803c510: e13ffe15 stw r4,-8(fp) + 803c514: e17ffd15 stw r5,-12(fp) + struct in_multi * imp; + + for (imp = netp->mc_list; imp; imp = imp->inm_next) + 803c518: e0bffd17 ldw r2,-12(fp) + 803c51c: 10802c17 ldw r2,176(r2) + 803c520: e0bfff15 stw r2,-4(fp) + 803c524: 00000906 br 803c54c + { + if(imp->inm_addr == addr) + 803c528: e0bfff17 ldw r2,-4(fp) + 803c52c: 10800017 ldw r2,0(r2) + 803c530: e0fffe17 ldw r3,-8(fp) + 803c534: 1880021e bne r3,r2,803c540 + return imp; + 803c538: e0bfff17 ldw r2,-4(fp) + 803c53c: 00000606 br 803c558 + for (imp = netp->mc_list; imp; imp = imp->inm_next) + 803c540: e0bfff17 ldw r2,-4(fp) + 803c544: 10800517 ldw r2,20(r2) + 803c548: e0bfff15 stw r2,-4(fp) + 803c54c: e0bfff17 ldw r2,-4(fp) + 803c550: 103ff51e bne r2,zero,803c528 + } + return NULL; /* addr not found in mcast list */ + 803c554: 0005883a mov r2,zero +} + 803c558: e037883a mov sp,fp + 803c55c: df000017 ldw fp,0(sp) + 803c560: dec00104 addi sp,sp,4 + 803c564: f800283a ret + +0803c568 : + * passed value. + */ + +int +prep_ifaces(int ifaces_found) +{ + 803c568: defffd04 addi sp,sp,-12 + 803c56c: dfc00215 stw ra,8(sp) + 803c570: df000115 stw fp,4(sp) + 803c574: df000104 addi fp,sp,4 + 803c578: e13fff15 stw r4,-4(fp) + if (port_prep) + 803c57c: d0a09617 ldw r2,-32168(gp) + 803c580: 10000426 beq r2,zero,803c594 + ifaces_found = port_prep(ifaces_found); + 803c584: d0a09617 ldw r2,-32168(gp) + 803c588: e13fff17 ldw r4,-4(fp) + 803c58c: 103ee83a callr r2 + 803c590: e0bfff15 stw r2,-4(fp) + +#ifdef MAC_LOOPBACK + ifaces_found = prep_lb(ifaces_found); +#endif /* MAC_LOOPBACK */ + + ifNumber = ifaces_found; /* set global interface counter */ + 803c594: e0bfff17 ldw r2,-4(fp) + 803c598: d0a06715 stw r2,-32356(gp) + + initmsg("prepped %u interface%s, initializing...\n", + 803c59c: e0bfff17 ldw r2,-4(fp) + 803c5a0: 10800058 cmpnei r2,r2,1 + 803c5a4: 1000031e bne r2,zero,803c5b4 + 803c5a8: 00820174 movhi r2,2053 + 803c5ac: 10acd004 addi r2,r2,-19648 + 803c5b0: 00000206 br 803c5bc + 803c5b4: 00820174 movhi r2,2053 + 803c5b8: 10acd104 addi r2,r2,-19644 + 803c5bc: 100d883a mov r6,r2 + 803c5c0: e17fff17 ldw r5,-4(fp) + 803c5c4: 01020174 movhi r4,2053 + 803c5c8: 212cd204 addi r4,r4,-19640 + 803c5cc: 8002c780 call 8002c78 + ifaces_found, ifaces_found==1?"":"s"); + + return ifaces_found; + 803c5d0: e0bfff17 ldw r2,-4(fp) +} + 803c5d4: e037883a mov sp,fp + 803c5d8: dfc00117 ldw ra,4(sp) + 803c5dc: df000017 ldw fp,0(sp) + 803c5e0: dec00204 addi sp,sp,8 + 803c5e4: f800283a ret + +0803c5e8 : + * RETURNS: SHould not return + */ + +void +netexit(int err) /* exit error level */ +{ + 803c5e8: defffd04 addi sp,sp,-12 + 803c5ec: dfc00215 stw ra,8(sp) + 803c5f0: df000115 stw fp,4(sp) + 803c5f4: df000104 addi fp,sp,4 + 803c5f8: e13fff15 stw r4,-4(fp) + net_system_exit = TRUE; /* set flag for shutting down */ + 803c5fc: 00800044 movi r2,1 + 803c600: d0a09715 stw r2,-32164(gp) + ip_exit(); /* do the exit_hook()ed stuff */ + 803c604: 802524c0 call 802524c + + PORT_EXIT_FUNC(err); /* should not return! */ + 803c608: e13fff17 ldw r4,-4(fp) + 803c60c: 8042abc0 call 8042abc + +0803c610 : + * INPUT: None. + * OUTPUT: None + */ + +void evtmap_setup (void) +{ + 803c610: deffff04 addi sp,sp,-4 + 803c614: df000015 stw fp,0(sp) + 803c618: d839883a mov fp,sp +#ifdef SOCK_MAP_EVENTS + so_evtmap = TRUE; + so_evtmap_create = evtmap_create; + so_evtmap_delete = evtmap_delete; +#else + so_evtmap = FALSE; + 803c61c: d0209a05 stb zero,-32152(gp) + so_evtmap_create = 0; + 803c620: d0209815 stw zero,-32160(gp) + so_evtmap_delete = 0; + 803c624: d0209915 stw zero,-32156(gp) +#endif /* SOCK_MAP_EVENTS */ + +} + 803c628: 0001883a nop + 803c62c: e037883a mov sp,fp + 803c630: df000017 ldw fp,0(sp) + 803c634: dec00104 addi sp,sp,4 + 803c638: f800283a ret + +0803c63c : +ip_raw_open(u_char prot, + ip_addr laddr, + ip_addr faddr, + int (*handler)(PACKET, void *), + void * data) +{ + 803c63c: defff904 addi sp,sp,-28 + 803c640: dfc00615 stw ra,24(sp) + 803c644: df000515 stw fp,20(sp) + 803c648: df000504 addi fp,sp,20 + 803c64c: 2005883a mov r2,r4 + 803c650: e17ffd15 stw r5,-12(fp) + 803c654: e1bffc15 stw r6,-16(fp) + 803c658: e1fffb15 stw r7,-20(fp) + 803c65c: e0bffe05 stb r2,-8(fp) + struct ipraw_ep * ep; + + LOCK_NET_RESOURCE(NET_RESID); + 803c660: 0009883a mov r4,zero + 803c664: 8028f380 call 8028f38 + + /* allocate a structure for the endpoint */ + ep = (struct ipraw_ep *)IEP_ALLOC(sizeof(struct ipraw_ep)); + 803c668: 01000604 movi r4,24 + 803c66c: 802982c0 call 802982c + 803c670: e0bfff15 stw r2,-4(fp) + if (ep == NULL) + 803c674: e0bfff17 ldw r2,-4(fp) + 803c678: 10000a1e bne r2,zero,803c6a4 + { +#ifdef NPDEBUG + if (NDEBUG & INFOMSG) + 803c67c: d0a06617 ldw r2,-32360(gp) + 803c680: 1080010c andi r2,r2,4 + 803c684: 10000326 beq r2,zero,803c694 + dprintf("IP: Couldn't allocate ep storage.\n"); + 803c688: 01020174 movhi r4,2053 + 803c68c: 212cdd04 addi r4,r4,-19596 + 803c690: 8002d9c0 call 8002d9c +#endif + UNLOCK_NET_RESOURCE(NET_RESID); + 803c694: 0009883a mov r4,zero + 803c698: 8028ff40 call 8028ff4 + return ep; + 803c69c: e0bfff17 ldw r2,-4(fp) + 803c6a0: 00001706 br 803c700 + } + + /* fill it in with the caller's requested binding */ + ep->ipr_laddr = laddr; + 803c6a4: e0bfff17 ldw r2,-4(fp) + 803c6a8: e0fffd17 ldw r3,-12(fp) + 803c6ac: 10c00115 stw r3,4(r2) + ep->ipr_faddr = faddr; + 803c6b0: e0bfff17 ldw r2,-4(fp) + 803c6b4: e0fffc17 ldw r3,-16(fp) + 803c6b8: 10c00215 stw r3,8(r2) + ep->ipr_prot = prot; + 803c6bc: e0bfff17 ldw r2,-4(fp) + 803c6c0: e0fffe03 ldbu r3,-8(fp) + 803c6c4: 10c00505 stb r3,20(r2) + ep->ipr_rcv = handler; + 803c6c8: e0bfff17 ldw r2,-4(fp) + 803c6cc: e0fffb17 ldw r3,-20(fp) + 803c6d0: 10c00315 stw r3,12(r2) + ep->ipr_data = data; + 803c6d4: e0bfff17 ldw r2,-4(fp) + 803c6d8: e0c00217 ldw r3,8(fp) + 803c6dc: 10c00415 stw r3,16(r2) + + /* link it into the list + * (at the head, because that's simple and fast) + */ + ep->ipr_next = ipraw_eps; + 803c6e0: d0e09b17 ldw r3,-32148(gp) + 803c6e4: e0bfff17 ldw r2,-4(fp) + 803c6e8: 10c00015 stw r3,0(r2) + ipraw_eps = ep; + 803c6ec: e0bfff17 ldw r2,-4(fp) + 803c6f0: d0a09b15 stw r2,-32148(gp) + + /* and return the pointer to the endpoint */ + UNLOCK_NET_RESOURCE(NET_RESID); + 803c6f4: 0009883a mov r4,zero + 803c6f8: 8028ff40 call 8028ff4 + return ep; + 803c6fc: e0bfff17 ldw r2,-4(fp) +} + 803c700: e037883a mov sp,fp + 803c704: dfc00117 ldw ra,4(sp) + 803c708: df000017 ldw fp,0(sp) + 803c70c: dec00204 addi sp,sp,8 + 803c710: f800283a ret + +0803c714 : + * that is to be closed + * RETURNS: void + */ +void +ip_raw_close(struct ipraw_ep * ep) +{ + 803c714: defffb04 addi sp,sp,-20 + 803c718: dfc00415 stw ra,16(sp) + 803c71c: df000315 stw fp,12(sp) + 803c720: df000304 addi fp,sp,12 + 803c724: e13ffd15 stw r4,-12(fp) + struct ipraw_ep * prev_ep; + struct ipraw_ep * curr_ep; + + LOCK_NET_RESOURCE(NET_RESID); + 803c728: 0009883a mov r4,zero + 803c72c: 8028f380 call 8028f38 + + /* search the list of endpoints for the one we're supposed to close */ + for (prev_ep = NULL, curr_ep = ipraw_eps; + 803c730: e03fff15 stw zero,-4(fp) + 803c734: d0a09b17 ldw r2,-32148(gp) + 803c738: e0bffe15 stw r2,-8(fp) + 803c73c: 00000806 br 803c760 + curr_ep != NULL; + curr_ep = curr_ep->ipr_next) + { + if (curr_ep == ep) + 803c740: e0fffe17 ldw r3,-8(fp) + 803c744: e0bffd17 ldw r2,-12(fp) + 803c748: 18800826 beq r3,r2,803c76c + break; + prev_ep = curr_ep; + 803c74c: e0bffe17 ldw r2,-8(fp) + 803c750: e0bfff15 stw r2,-4(fp) + curr_ep = curr_ep->ipr_next) + 803c754: e0bffe17 ldw r2,-8(fp) + 803c758: 10800017 ldw r2,0(r2) + 803c75c: e0bffe15 stw r2,-8(fp) + for (prev_ep = NULL, curr_ep = ipraw_eps; + 803c760: e0bffe17 ldw r2,-8(fp) + 803c764: 103ff61e bne r2,zero,803c740 + 803c768: 00000106 br 803c770 + break; + 803c76c: 0001883a nop + } + + /* if we didn't find it, we can't close it, so just return */ + if (curr_ep == NULL) + 803c770: e0bffe17 ldw r2,-8(fp) + 803c774: 1000041e bne r2,zero,803c788 + { +#ifdef NPDEBUG + /* caller passed pointer to endpoint not in list + * -- not fatal, but may be programming error + */ + dtrap(); + 803c778: 8028cd40 call 8028cd4 +#endif /* NPDEBUG */ + UNLOCK_NET_RESOURCE(NET_RESID); + 803c77c: 0009883a mov r4,zero + 803c780: 8028ff40 call 8028ff4 + return; + 803c784: 00000d06 br 803c7bc + } + + /* unlink it from the list */ + if (prev_ep) + 803c788: e0bfff17 ldw r2,-4(fp) + 803c78c: 10000426 beq r2,zero,803c7a0 + prev_ep = curr_ep->ipr_next; + 803c790: e0bffe17 ldw r2,-8(fp) + 803c794: 10800017 ldw r2,0(r2) + 803c798: e0bfff15 stw r2,-4(fp) + 803c79c: 00000306 br 803c7ac + else + ipraw_eps = curr_ep->ipr_next; + 803c7a0: e0bffe17 ldw r2,-8(fp) + 803c7a4: 10800017 ldw r2,0(r2) + 803c7a8: d0a09b15 stw r2,-32148(gp) + + /* free its storage */ + IEP_FREE(curr_ep); + 803c7ac: e13ffe17 ldw r4,-8(fp) + 803c7b0: 80298600 call 8029860 + + /* and return */ + UNLOCK_NET_RESOURCE(NET_RESID); + 803c7b4: 0009883a mov r4,zero + 803c7b8: 8028ff40 call 8028ff4 +} + 803c7bc: e037883a mov sp,fp + 803c7c0: dfc00117 ldw ra,4(sp) + 803c7c4: df000017 ldw fp,0(sp) + 803c7c8: dec00204 addi sp,sp,8 + 803c7cc: f800283a ret + +0803c7d0 : + * freed); else an error code indicating that the + * received packet was not accepted/processed + */ +int +ip_raw_input(PACKET p) +{ + 803c7d0: defff604 addi sp,sp,-40 + 803c7d4: dfc00915 stw ra,36(sp) + 803c7d8: df000815 stw fp,32(sp) + 803c7dc: df000804 addi fp,sp,32 + 803c7e0: e13ff815 stw r4,-32(fp) + struct ip * pip; /* the internet header */ + struct ipraw_ep * ep; + struct ipraw_ep * next_ep; + struct ipraw_ep * matched_ep = NULL; + 803c7e4: e03ffe15 stw zero,-8(fp) + int err; + int delivered; + + /* start out expecting to not deliver the packet */ + delivered = 0; + 803c7e8: e03ffc15 stw zero,-16(fp) + + /* get a pointer to the received packet's IP header */ + pip = (struct ip *)(p->nb_prot); + 803c7ec: e0bff817 ldw r2,-32(fp) + 803c7f0: 10800317 ldw r2,12(r2) + 803c7f4: e0bffb15 stw r2,-20(fp) + + /* search the list of raw-IP endpoints for matches */ + for (ep = ipraw_eps; ep != NULL; ep = next_ep) + 803c7f8: d0a09b17 ldw r2,-32148(gp) + 803c7fc: e0bfff15 stw r2,-4(fp) + 803c800: 00004c06 br 803c934 + { + /* keep track of next endpoint -- defense against upcall + * function closing its own endpoint + */ + next_ep = ep->ipr_next; + 803c804: e0bfff17 ldw r2,-4(fp) + 803c808: 10800017 ldw r2,0(r2) + 803c80c: e0bffa15 stw r2,-24(fp) + + /* if this packet doesn't match the endpoint's filters (IP + * protocol ID, locally-bound address, connected-peer address) + * then skip ahead to next endpoint + */ + if (ep->ipr_prot && ep->ipr_prot != pip->ip_prot) + 803c810: e0bfff17 ldw r2,-4(fp) + 803c814: 10800503 ldbu r2,20(r2) + 803c818: 10803fcc andi r2,r2,255 + 803c81c: 10000726 beq r2,zero,803c83c + 803c820: e0bfff17 ldw r2,-4(fp) + 803c824: 10c00503 ldbu r3,20(r2) + 803c828: e0bffb17 ldw r2,-20(fp) + 803c82c: 10800243 ldbu r2,9(r2) + 803c830: 18c03fcc andi r3,r3,255 + 803c834: 10803fcc andi r2,r2,255 + 803c838: 1880371e bne r3,r2,803c918 + continue; + if (ep->ipr_laddr && ep->ipr_laddr != pip->ip_dest) + 803c83c: e0bfff17 ldw r2,-4(fp) + 803c840: 10800117 ldw r2,4(r2) + 803c844: 10000526 beq r2,zero,803c85c + 803c848: e0bfff17 ldw r2,-4(fp) + 803c84c: 10c00117 ldw r3,4(r2) + 803c850: e0bffb17 ldw r2,-20(fp) + 803c854: 10800417 ldw r2,16(r2) + 803c858: 1880311e bne r3,r2,803c920 + continue; + if (ep->ipr_faddr && ep->ipr_faddr != pip->ip_src) + 803c85c: e0bfff17 ldw r2,-4(fp) + 803c860: 10800217 ldw r2,8(r2) + 803c864: 10000526 beq r2,zero,803c87c + 803c868: e0bfff17 ldw r2,-4(fp) + 803c86c: 10c00217 ldw r3,8(r2) + 803c870: e0bffb17 ldw r2,-20(fp) + 803c874: 10800317 ldw r2,12(r2) + 803c878: 18802b1e bne r3,r2,803c928 + continue; + + /* if the endpoint has a receive upcall function, + * keep track of the endpoint + */ + if (ep->ipr_rcv != NULL) + 803c87c: e0bfff17 ldw r2,-4(fp) + 803c880: 10800317 ldw r2,12(r2) + 803c884: 10002926 beq r2,zero,803c92c + * copy the packet into a new buffer, + * and pass the new copy to the previously matched + * endpoint's upcall function + * before we forget the previous endpoint + */ + if ((matched_ep != NULL) && (matched_ep->ipr_rcv != NULL)) + 803c888: e0bffe17 ldw r2,-8(fp) + 803c88c: 10001f26 beq r2,zero,803c90c + 803c890: e0bffe17 ldw r2,-8(fp) + 803c894: 10800317 ldw r2,12(r2) + 803c898: 10001c26 beq r2,zero,803c90c + { + PACKET p2; + + p2 = ip_copypkt(p); + 803c89c: e13ff817 ldw r4,-32(fp) + 803c8a0: 803b53c0 call 803b53c + 803c8a4: e0bff915 stw r2,-28(fp) + if (p2) + 803c8a8: e0bff917 ldw r2,-28(fp) + 803c8ac: 10001726 beq r2,zero,803c90c + { + UNLOCK_NET_RESOURCE(NET_RESID); + 803c8b0: 0009883a mov r4,zero + 803c8b4: 8028ff40 call 8028ff4 + err = ((*matched_ep->ipr_rcv)(p2, matched_ep->ipr_data)); + 803c8b8: e0bffe17 ldw r2,-8(fp) + 803c8bc: 10800317 ldw r2,12(r2) + 803c8c0: e0fffe17 ldw r3,-8(fp) + 803c8c4: 18c00417 ldw r3,16(r3) + 803c8c8: 180b883a mov r5,r3 + 803c8cc: e13ff917 ldw r4,-28(fp) + 803c8d0: 103ee83a callr r2 + 803c8d4: e0bffd15 stw r2,-12(fp) + LOCK_NET_RESOURCE(NET_RESID); + 803c8d8: 0009883a mov r4,zero + 803c8dc: 8028f380 call 8028f38 + if (err) + 803c8e0: e0bffd17 ldw r2,-12(fp) + 803c8e4: 10000726 beq r2,zero,803c904 + { + LOCK_NET_RESOURCE(FREEQ_RESID); + 803c8e8: 01000084 movi r4,2 + 803c8ec: 8028f380 call 8028f38 + pk_free(p2); + 803c8f0: e13ff917 ldw r4,-28(fp) + 803c8f4: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803c8f8: 01000084 movi r4,2 + 803c8fc: 8028ff40 call 8028ff4 + 803c900: 00000206 br 803c90c + } + else + delivered = 1; + 803c904: 00800044 movi r2,1 + 803c908: e0bffc15 stw r2,-16(fp) + } + } + matched_ep = ep; + 803c90c: e0bfff17 ldw r2,-4(fp) + 803c910: e0bffe15 stw r2,-8(fp) + 803c914: 00000506 br 803c92c + continue; + 803c918: 0001883a nop + 803c91c: 00000306 br 803c92c + continue; + 803c920: 0001883a nop + 803c924: 00000106 br 803c92c + continue; + 803c928: 0001883a nop + for (ep = ipraw_eps; ep != NULL; ep = next_ep) + 803c92c: e0bffa17 ldw r2,-24(fp) + 803c930: e0bfff15 stw r2,-4(fp) + 803c934: e0bfff17 ldw r2,-4(fp) + 803c938: 103fb21e bne r2,zero,803c804 + /* if we matched an endpoint, + * pass the packet to its upcall function + * otherwise, return ENP_PARAM to indicate that the + * packet was not processed and freed + */ + if ((matched_ep != NULL) && (matched_ep->ipr_rcv != NULL)) + 803c93c: e0bffe17 ldw r2,-8(fp) + 803c940: 10001426 beq r2,zero,803c994 + 803c944: e0bffe17 ldw r2,-8(fp) + 803c948: 10800317 ldw r2,12(r2) + 803c94c: 10001126 beq r2,zero,803c994 + { + UNLOCK_NET_RESOURCE(NET_RESID); + 803c950: 0009883a mov r4,zero + 803c954: 8028ff40 call 8028ff4 + err = ((*matched_ep->ipr_rcv)(p, matched_ep->ipr_data)); + 803c958: e0bffe17 ldw r2,-8(fp) + 803c95c: 10800317 ldw r2,12(r2) + 803c960: e0fffe17 ldw r3,-8(fp) + 803c964: 18c00417 ldw r3,16(r3) + 803c968: 180b883a mov r5,r3 + 803c96c: e13ff817 ldw r4,-32(fp) + 803c970: 103ee83a callr r2 + 803c974: e0bffd15 stw r2,-12(fp) + LOCK_NET_RESOURCE(NET_RESID); + 803c978: 0009883a mov r4,zero + 803c97c: 8028f380 call 8028f38 + if (err == 0) + 803c980: e0bffd17 ldw r2,-12(fp) + 803c984: 10000a1e bne r2,zero,803c9b0 + delivered = 1; + 803c988: 00800044 movi r2,1 + 803c98c: e0bffc15 stw r2,-16(fp) + if (err == 0) + 803c990: 00000706 br 803c9b0 + } + else + { + err = ENP_PARAM; + 803c994: 00bffd84 movi r2,-10 + 803c998: e0bffd15 stw r2,-12(fp) + ip_mib.ipUnknownProtos++; + 803c99c: 008201b4 movhi r2,2054 + 803c9a0: 10b95517 ldw r2,-6828(r2) + 803c9a4: 10c00044 addi r3,r2,1 + 803c9a8: 008201b4 movhi r2,2054 + 803c9ac: 10f95515 stw r3,-6828(r2) + } + + if (!delivered) + 803c9b0: e0bffc17 ldw r2,-16(fp) + 803c9b4: 1000051e bne r2,zero,803c9cc + ip_mib.ipInDelivers--; + 803c9b8: 008201b4 movhi r2,2054 + 803c9bc: 10b95717 ldw r2,-6820(r2) + 803c9c0: 10ffffc4 addi r3,r2,-1 + 803c9c4: 008201b4 movhi r2,2054 + 803c9c8: 10f95715 stw r3,-6820(r2) + + return err; + 803c9cc: e0bffd17 ldw r2,-12(fp) +} + 803c9d0: e037883a mov sp,fp + 803c9d4: dfc00117 ldw ra,4(sp) + 803c9d8: df000017 ldw fp,0(sp) + 803c9dc: dec00204 addi sp,sp,8 + 803c9e0: f800283a ret + +0803c9e4 : + * inclhdr is zero. + */ + +PACKET +ip_raw_alloc(int reqlen, int hdrincl) +{ + 803c9e4: defffa04 addi sp,sp,-24 + 803c9e8: dfc00515 stw ra,20(sp) + 803c9ec: df000415 stw fp,16(sp) + 803c9f0: df000404 addi fp,sp,16 + 803c9f4: e13ffd15 stw r4,-12(fp) + 803c9f8: e17ffc15 stw r5,-16(fp) + int len; + PACKET p; + + len = (reqlen + 1) & ~1; + 803c9fc: e0bffd17 ldw r2,-12(fp) + 803ca00: 10c00044 addi r3,r2,1 + 803ca04: 00bfff84 movi r2,-2 + 803ca08: 1884703a and r2,r3,r2 + 803ca0c: e0bfff15 stw r2,-4(fp) + if (!hdrincl) + 803ca10: e0bffc17 ldw r2,-16(fp) + 803ca14: 1000031e bne r2,zero,803ca24 + len += IPHSIZ; + 803ca18: e0bfff17 ldw r2,-4(fp) + 803ca1c: 10800504 addi r2,r2,20 + 803ca20: e0bfff15 stw r2,-4(fp) + LOCK_NET_RESOURCE(FREEQ_RESID); + 803ca24: 01000084 movi r4,2 + 803ca28: 8028f380 call 8028f38 + p = pk_alloc(len + MaxLnh); + 803ca2c: d0e06417 ldw r3,-32368(gp) + 803ca30: e0bfff17 ldw r2,-4(fp) + 803ca34: 1885883a add r2,r3,r2 + 803ca38: 1009883a mov r4,r2 + 803ca3c: 80284340 call 8028434 + 803ca40: e0bffe15 stw r2,-8(fp) + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803ca44: 01000084 movi r4,2 + 803ca48: 8028ff40 call 8028ff4 + if (p) + 803ca4c: e0bffe17 ldw r2,-8(fp) + 803ca50: 10000c26 beq r2,zero,803ca84 + { + if (!hdrincl) + 803ca54: e0bffc17 ldw r2,-16(fp) + 803ca58: 10000a1e bne r2,zero,803ca84 + { + p->nb_prot += IPHSIZ; + 803ca5c: e0bffe17 ldw r2,-8(fp) + 803ca60: 10800317 ldw r2,12(r2) + 803ca64: 10c00504 addi r3,r2,20 + 803ca68: e0bffe17 ldw r2,-8(fp) + 803ca6c: 10c00315 stw r3,12(r2) + p->nb_plen -= IPHSIZ; + 803ca70: e0bffe17 ldw r2,-8(fp) + 803ca74: 10800417 ldw r2,16(r2) + 803ca78: 10fffb04 addi r3,r2,-20 + 803ca7c: e0bffe17 ldw r2,-8(fp) + 803ca80: 10c00415 stw r3,16(r2) + } + } + return p; + 803ca84: e0bffe17 ldw r2,-8(fp) +} + 803ca88: e037883a mov sp,fp + 803ca8c: dfc00117 ldw ra,4(sp) + 803ca90: df000017 ldw fp,0(sp) + 803ca94: dec00204 addi sp,sp,8 + 803ca98: f800283a ret + +0803ca9c : + * RETURNS: void + */ + +void +ip_raw_free(PACKET p) +{ + 803ca9c: defffd04 addi sp,sp,-12 + 803caa0: dfc00215 stw ra,8(sp) + 803caa4: df000115 stw fp,4(sp) + 803caa8: df000104 addi fp,sp,4 + 803caac: e13fff15 stw r4,-4(fp) + LOCK_NET_RESOURCE(FREEQ_RESID); + 803cab0: 01000084 movi r4,2 + 803cab4: 8028f380 call 8028f38 + pk_free(p); + 803cab8: e13fff17 ldw r4,-4(fp) + 803cabc: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803cac0: 01000084 movi r4,2 + 803cac4: 8028ff40 call 8028ff4 +} + 803cac8: 0001883a nop + 803cacc: e037883a mov sp,fp + 803cad0: dfc00117 ldw ra,4(sp) + 803cad4: df000017 ldw fp,0(sp) + 803cad8: dec00204 addi sp,sp,8 + 803cadc: f800283a ret + +0803cae0 : + * for + */ + +int +ip_raw_maxalloc(int hdrincl) +{ + 803cae0: defffd04 addi sp,sp,-12 + 803cae4: df000215 stw fp,8(sp) + 803cae8: df000204 addi fp,sp,8 + 803caec: e13ffe15 stw r4,-8(fp) + int len; + + len = bigbufsiz - MaxLnh; + 803caf0: d0a01917 ldw r2,-32668(gp) + 803caf4: d0e06417 ldw r3,-32368(gp) + 803caf8: 10c5c83a sub r2,r2,r3 + 803cafc: e0bfff15 stw r2,-4(fp) + if (!hdrincl) + 803cb00: e0bffe17 ldw r2,-8(fp) + 803cb04: 1000031e bne r2,zero,803cb14 + len -= IPHSIZ; + 803cb08: e0bfff17 ldw r2,-4(fp) + 803cb0c: 10bffb04 addi r2,r2,-20 + 803cb10: e0bfff15 stw r2,-4(fp) + return len; + 803cb14: e0bfff17 ldw r2,-4(fp) +} + 803cb18: e037883a mov sp,fp + 803cb1c: df000017 ldw fp,0(sp) + 803cb20: dec00104 addi sp,sp,4 + 803cb24: f800283a ret + +0803cb28 : + * entry was found. + */ + +RTMIB +rt_lookup(ip_addr host) +{ + 803cb28: defff804 addi sp,sp,-32 + 803cb2c: df000715 stw fp,28(sp) + 803cb30: df000704 addi fp,sp,28 + 803cb34: e13ff915 stw r4,-28(fp) + RTMIB rtp; + RTMIB netmatch; + unsigned char max_bits_matched = 0; + 803cb38: e03ffdc5 stb zero,-9(fp) + unsigned char curr_bits_matched; + ip_addr entry_mask; + unsigned long int bitcount_mask; + unsigned long int extracted_bit; + + netmatch = NULL; + 803cb3c: e03ffe15 stw zero,-8(fp) + + /* see if it's in the route table. */ + for (rtp = rt_mib; rtp < rt_mib + ipRoutes; rtp++) + 803cb40: d0a09517 ldw r2,-32172(gp) + 803cb44: e0bfff15 stw r2,-4(fp) + 803cb48: 00003a06 br 803cc34 + { + if (rtp->ipRouteNextHop == 0L) /* skip over empty entries */ + 803cb4c: e0bfff17 ldw r2,-4(fp) + 803cb50: 10800617 ldw r2,24(r2) + 803cb54: 10003326 beq r2,zero,803cc24 +#ifdef RIP_SUPPORT + /* skip RIP private entries */ + if (rtp->ipRouteFlags & RIP_PRIVATE) + continue; +#endif + entry_mask = rtp->ipRouteMask; + 803cb58: e0bfff17 ldw r2,-4(fp) + 803cb5c: 10800a17 ldw r2,40(r2) + 803cb60: e0bffb15 stw r2,-20(fp) + /* check to see if we have a match in the route table */ + if ((rtp->ipRouteDest & entry_mask) == (host & entry_mask)) + 803cb64: e0bfff17 ldw r2,-4(fp) + 803cb68: 10c00017 ldw r3,0(r2) + 803cb6c: e0bff917 ldw r2,-28(fp) + 803cb70: 1886f03a xor r3,r3,r2 + 803cb74: e0bffb17 ldw r2,-20(fp) + 803cb78: 1884703a and r2,r3,r2 + 803cb7c: 10002a1e bne r2,zero,803cc28 + { + /* check to see if current match is better than the previous best + * by computing the number of bits that matched */ + for (curr_bits_matched = 0, bitcount_mask = 0x80000000; bitcount_mask > 0; bitcount_mask >>= 1) + 803cb80: e03ffd85 stb zero,-10(fp) + 803cb84: 00a00034 movhi r2,32768 + 803cb88: e0bffc15 stw r2,-16(fp) + 803cb8c: 00001806 br 803cbf0 + { + extracted_bit = (ntohl(entry_mask)) & bitcount_mask; + 803cb90: e0bffb17 ldw r2,-20(fp) + 803cb94: 1006d63a srli r3,r2,24 + 803cb98: e0bffb17 ldw r2,-20(fp) + 803cb9c: 1004d23a srli r2,r2,8 + 803cba0: 10bfc00c andi r2,r2,65280 + 803cba4: 1886b03a or r3,r3,r2 + 803cba8: e0bffb17 ldw r2,-20(fp) + 803cbac: 1004923a slli r2,r2,8 + 803cbb0: 10803fec andhi r2,r2,255 + 803cbb4: 1886b03a or r3,r3,r2 + 803cbb8: e0bffb17 ldw r2,-20(fp) + 803cbbc: 1004963a slli r2,r2,24 + 803cbc0: 1884b03a or r2,r3,r2 + 803cbc4: e0fffc17 ldw r3,-16(fp) + 803cbc8: 1884703a and r2,r3,r2 + 803cbcc: e0bffa15 stw r2,-24(fp) + if (extracted_bit) ++curr_bits_matched; + 803cbd0: e0bffa17 ldw r2,-24(fp) + 803cbd4: 10000326 beq r2,zero,803cbe4 + 803cbd8: e0bffd83 ldbu r2,-10(fp) + 803cbdc: 10800044 addi r2,r2,1 + 803cbe0: e0bffd85 stb r2,-10(fp) + for (curr_bits_matched = 0, bitcount_mask = 0x80000000; bitcount_mask > 0; bitcount_mask >>= 1) + 803cbe4: e0bffc17 ldw r2,-16(fp) + 803cbe8: 1004d07a srli r2,r2,1 + 803cbec: e0bffc15 stw r2,-16(fp) + 803cbf0: e0bffc17 ldw r2,-16(fp) + 803cbf4: 103fe61e bne r2,zero,803cb90 + } + if (curr_bits_matched > max_bits_matched) + 803cbf8: e0bffd83 ldbu r2,-10(fp) + 803cbfc: e0fffdc3 ldbu r3,-9(fp) + 803cc00: 1880092e bgeu r3,r2,803cc28 + { + /* save a pointer to the best match */ + max_bits_matched = curr_bits_matched; + 803cc04: e0bffd83 ldbu r2,-10(fp) + 803cc08: e0bffdc5 stb r2,-9(fp) + netmatch = rtp; + 803cc0c: e0bfff17 ldw r2,-4(fp) + 803cc10: e0bffe15 stw r2,-8(fp) + /* if all 32 bits match, stop searching the route table */ + if (max_bits_matched == 32) + 803cc14: e0bffdc3 ldbu r2,-9(fp) + 803cc18: 10800818 cmpnei r2,r2,32 + 803cc1c: 10000c26 beq r2,zero,803cc50 + 803cc20: 00000106 br 803cc28 + continue; + 803cc24: 0001883a nop + for (rtp = rt_mib; rtp < rt_mib + ipRoutes; rtp++) + 803cc28: e0bfff17 ldw r2,-4(fp) + 803cc2c: 10800f04 addi r2,r2,60 + 803cc30: e0bfff15 stw r2,-4(fp) + 803cc34: d0e09517 ldw r3,-32172(gp) + 803cc38: d0a03017 ldw r2,-32576(gp) + 803cc3c: 10800f24 muli r2,r2,60 + 803cc40: 1885883a add r2,r3,r2 + 803cc44: e0ffff17 ldw r3,-4(fp) + 803cc48: 18bfc036 bltu r3,r2,803cb4c + 803cc4c: 00000106 br 803cc54 + break; + 803cc50: 0001883a nop + } + } + } + + if (netmatch) + 803cc54: e0bffe17 ldw r2,-8(fp) + 803cc58: 10000326 beq r2,zero,803cc68 + netmatch->ipRouteAge = cticks; /* timestamp entry we used */ + 803cc5c: d0e07d17 ldw r3,-32268(gp) + 803cc60: e0bffe17 ldw r2,-8(fp) + 803cc64: 10c00915 stw r3,36(r2) + + return netmatch; + 803cc68: e0bffe17 ldw r2,-8(fp) +} + 803cc6c: e037883a mov sp,fp + 803cc70: df000017 ldw fp,0(sp) + 803cc74: dec00104 addi sp,sp,4 + 803cc78: f800283a ret + +0803cc7c : + ip_addr dest, /* ultimate destination */ + ip_addr mask, /* net mask, 0xFFFFFFFF if dest is host address */ + ip_addr nexthop, /* where to forward to */ + int iface, /* interface (net) for nexthop */ + int prot) /* how we know it: icmp, table, etc */ +{ + 803cc7c: defff704 addi sp,sp,-36 + 803cc80: dfc00815 stw ra,32(sp) + 803cc84: df000715 stw fp,28(sp) + 803cc88: df000704 addi fp,sp,28 + 803cc8c: e13ffc15 stw r4,-16(fp) + 803cc90: e17ffb15 stw r5,-20(fp) + 803cc94: e1bffa15 stw r6,-24(fp) + 803cc98: e1fff915 stw r7,-28(fp) + RTMIB rtp; /* scratch route table entrry pointer */ + RTMIB newrt; /* best entry for new route */ + struct net * ifp; /* interface (net) for nexthop */ + + newrt = NULL; /* may be replaced with empty or more expendable entry */ + 803cc9c: e03ffe15 stw zero,-8(fp) + + /* set the route interface pointer according to the index passed. This allows + * the passed index to be used to access dynamic interfaces, which do not appear + * in the nets[] array. + */ + ifp = if_getbynum(iface); + 803cca0: e13ff917 ldw r4,-28(fp) + 803cca4: 80240880 call 8024088 + 803cca8: e0bffd15 stw r2,-12(fp) + if(!ifp) + 803ccac: e0bffd17 ldw r2,-12(fp) + 803ccb0: 1000021e bne r2,zero,803ccbc + return NULL; + 803ccb4: 0005883a mov r2,zero + 803ccb8: 0000d406 br 803d00c + + if (rt_mib == NULL) + 803ccbc: d0a09517 ldw r2,-32172(gp) + 803ccc0: 1000021e bne r2,zero,803cccc + return NULL; + 803ccc4: 0005883a mov r2,zero + 803ccc8: 0000d006 br 803d00c + + /* Don't add null masks or IP addresses - they give false positives on + * net matches and don't belong here anyway. + */ + if((dest == 0) || (mask == 0)) + 803cccc: e0bffc17 ldw r2,-16(fp) + 803ccd0: 10000226 beq r2,zero,803ccdc + 803ccd4: e0bffb17 ldw r2,-20(fp) + 803ccd8: 1000221e bne r2,zero,803cd64 + { + dtrap(); /* bad configuration? */ + 803ccdc: 8028cd40 call 8028cd4 + dprintf("add_route: rejected null parm; dest: %lx, mask: %lx\n", + htonl(dest), htonl(mask) ); + 803cce0: e0bffc17 ldw r2,-16(fp) + 803cce4: 1006d63a srli r3,r2,24 + 803cce8: e0bffc17 ldw r2,-16(fp) + 803ccec: 1004d23a srli r2,r2,8 + 803ccf0: 10bfc00c andi r2,r2,65280 + 803ccf4: 1886b03a or r3,r3,r2 + 803ccf8: e0bffc17 ldw r2,-16(fp) + 803ccfc: 1004923a slli r2,r2,8 + 803cd00: 10803fec andhi r2,r2,255 + 803cd04: 1886b03a or r3,r3,r2 + 803cd08: e0bffc17 ldw r2,-16(fp) + 803cd0c: 1004963a slli r2,r2,24 + dprintf("add_route: rejected null parm; dest: %lx, mask: %lx\n", + 803cd10: 1888b03a or r4,r3,r2 + htonl(dest), htonl(mask) ); + 803cd14: e0bffb17 ldw r2,-20(fp) + 803cd18: 1006d63a srli r3,r2,24 + 803cd1c: e0bffb17 ldw r2,-20(fp) + 803cd20: 1004d23a srli r2,r2,8 + 803cd24: 10bfc00c andi r2,r2,65280 + 803cd28: 1886b03a or r3,r3,r2 + 803cd2c: e0bffb17 ldw r2,-20(fp) + 803cd30: 1004923a slli r2,r2,8 + 803cd34: 10803fec andhi r2,r2,255 + 803cd38: 1886b03a or r3,r3,r2 + 803cd3c: e0bffb17 ldw r2,-20(fp) + 803cd40: 1004963a slli r2,r2,24 + dprintf("add_route: rejected null parm; dest: %lx, mask: %lx\n", + 803cd44: 1884b03a or r2,r3,r2 + 803cd48: 100d883a mov r6,r2 + 803cd4c: 200b883a mov r5,r4 + 803cd50: 01020174 movhi r4,2053 + 803cd54: 212ce604 addi r4,r4,-19560 + 803cd58: 8002c780 call 8002c78 + return NULL; + 803cd5c: 0005883a mov r2,zero + 803cd60: 0000aa06 br 803d00c + } + + + + /* if it's already in the route table, just update it. */ + for (rtp = rt_mib; rtp < rt_mib + ipRoutes; rtp++) + 803cd64: d0a09517 ldw r2,-32172(gp) + 803cd68: e0bfff15 stw r2,-4(fp) + 803cd6c: 00006406 br 803cf00 + { + if (rtp->ipRouteDest == dest) /* found existing entry for target */ + 803cd70: e0bfff17 ldw r2,-4(fp) + 803cd74: 10800017 ldw r2,0(r2) + 803cd78: e0fffc17 ldw r3,-16(fp) + 803cd7c: 1880151e bne r3,r2,803cdd4 + { + rtp->ipRouteNextHop = nexthop; /* fix entry */ + 803cd80: e0bfff17 ldw r2,-4(fp) + 803cd84: e0fffa17 ldw r3,-24(fp) + 803cd88: 10c00615 stw r3,24(r2) + rtp->ipRouteAge = cticks; /* timestamp it */ + 803cd8c: d0e07d17 ldw r3,-32268(gp) + 803cd90: e0bfff17 ldw r2,-4(fp) + 803cd94: 10c00915 stw r3,36(r2) + /* set the rfc1213 1-based SNMP-ish interface index */ + rtp->ipRouteIfIndex = (long)(iface) + 1; + 803cd98: e0bff917 ldw r2,-28(fp) + 803cd9c: 10c00044 addi r3,r2,1 + 803cda0: e0bfff17 ldw r2,-4(fp) + 803cda4: 10c00115 stw r3,4(r2) + rtp->ipRouteProto = prot; /* icmp, or whatever */ + 803cda8: e0bfff17 ldw r2,-4(fp) + 803cdac: e0c00217 ldw r3,8(fp) + 803cdb0: 10c00815 stw r3,32(r2) + rtp->ipRouteMask = mask; + 803cdb4: e0bfff17 ldw r2,-4(fp) + 803cdb8: e0fffb17 ldw r3,-20(fp) + 803cdbc: 10c00a15 stw r3,40(r2) + rtp->ifp = ifp; + 803cdc0: e0bfff17 ldw r2,-4(fp) + 803cdc4: e0fffd17 ldw r3,-12(fp) + 803cdc8: 10c00e15 stw r3,56(r2) + return(rtp); /* just update and exit */ + 803cdcc: e0bfff17 ldw r2,-4(fp) + 803cdd0: 00008e06 br 803d00c + } + /* if we didn't find empty slot yet, look for good slot to recycle */ + if (!newrt || (newrt->ipRouteProto != 0)) + 803cdd4: e0bffe17 ldw r2,-8(fp) + 803cdd8: 10000326 beq r2,zero,803cde8 + 803cddc: e0bffe17 ldw r2,-8(fp) + 803cde0: 10800817 ldw r2,32(r2) + 803cde4: 10004326 beq r2,zero,803cef4 + { + if (!rtp->ipRouteNextHop) /* found empty slot for use */ + 803cde8: e0bfff17 ldw r2,-4(fp) + 803cdec: 10800617 ldw r2,24(r2) + 803cdf0: 1000051e bne r2,zero,803ce08 + { + newrt = rtp; /* record empty route for use */ + 803cdf4: e0bfff17 ldw r2,-4(fp) + 803cdf8: e0bffe15 stw r2,-8(fp) + newrt->ipRouteProto = 0; + 803cdfc: e0bffe17 ldw r2,-8(fp) + 803ce00: 10000815 stw zero,32(r2) + continue; + 803ce04: 00003b06 br 803cef4 + } + /* else see if the new route has higher priority than this slot: */ + if (rtp_priority[prot] >= rtp_priority[rtp->ipRouteProto]) + 803ce08: e0c00217 ldw r3,8(fp) + 803ce0c: 00820174 movhi r2,2053 + 803ce10: 1885883a add r2,r3,r2 + 803ce14: 11325603 ldbu r4,-13992(r2) + 803ce18: e0bfff17 ldw r2,-4(fp) + 803ce1c: 10c00817 ldw r3,32(r2) + 803ce20: 00820174 movhi r2,2053 + 803ce24: 1885883a add r2,r3,r2 + 803ce28: 10b25603 ldbu r2,-13992(r2) + 803ce2c: 20c03fcc andi r3,r4,255 + 803ce30: 10803fcc andi r2,r2,255 + 803ce34: 18802f36 bltu r3,r2,803cef4 + { + if (!newrt) + 803ce38: e0bffe17 ldw r2,-8(fp) + 803ce3c: 1000031e bne r2,zero,803ce4c + { + newrt = rtp; + 803ce40: e0bfff17 ldw r2,-4(fp) + 803ce44: e0bffe15 stw r2,-8(fp) + continue; + 803ce48: 00002a06 br 803cef4 + } + + /* see if rtp is less important then newrtp */ + if (rtp_priority[rtp->ipRouteProto] < + 803ce4c: e0bfff17 ldw r2,-4(fp) + 803ce50: 10c00817 ldw r3,32(r2) + 803ce54: 00820174 movhi r2,2053 + 803ce58: 1885883a add r2,r3,r2 + 803ce5c: 11325603 ldbu r4,-13992(r2) + rtp_priority[newrt->ipRouteProto]) + 803ce60: e0bffe17 ldw r2,-8(fp) + 803ce64: 10c00817 ldw r3,32(r2) + 803ce68: 00820174 movhi r2,2053 + 803ce6c: 1885883a add r2,r3,r2 + 803ce70: 10b25603 ldbu r2,-13992(r2) + if (rtp_priority[rtp->ipRouteProto] < + 803ce74: 20c03fcc andi r3,r4,255 + 803ce78: 10803fcc andi r2,r2,255 + 803ce7c: 1880032e bgeu r3,r2,803ce8c + { + newrt = rtp; /* save lower priority entry for recycle */ + 803ce80: e0bfff17 ldw r2,-4(fp) + 803ce84: e0bffe15 stw r2,-8(fp) + 803ce88: 00001a06 br 803cef4 + } + else if(rtp_priority[rtp->ipRouteProto] == + 803ce8c: e0bfff17 ldw r2,-4(fp) + 803ce90: 10c00817 ldw r3,32(r2) + 803ce94: 00820174 movhi r2,2053 + 803ce98: 1885883a add r2,r3,r2 + 803ce9c: 11325603 ldbu r4,-13992(r2) + rtp_priority[newrt->ipRouteProto]) + 803cea0: e0bffe17 ldw r2,-8(fp) + 803cea4: 10c00817 ldw r3,32(r2) + 803cea8: 00820174 movhi r2,2053 + 803ceac: 1885883a add r2,r3,r2 + 803ceb0: 10b25603 ldbu r2,-13992(r2) + else if(rtp_priority[rtp->ipRouteProto] == + 803ceb4: 20c03fcc andi r3,r4,255 + 803ceb8: 10803fcc andi r2,r2,255 + 803cebc: 18800d1e bne r3,r2,803cef4 + { + /* if equal priority, keep the older entry for deletion */ + if (c_older(rtp->ipRouteAge, newrt->ipRouteAge) == rtp->ipRouteAge) + 803cec0: e0bfff17 ldw r2,-4(fp) + 803cec4: 10c00917 ldw r3,36(r2) + 803cec8: e0bffe17 ldw r2,-8(fp) + 803cecc: 10800917 ldw r2,36(r2) + 803ced0: 100b883a mov r5,r2 + 803ced4: 1809883a mov r4,r3 + 803ced8: 8024d640 call 8024d64 + 803cedc: 1007883a mov r3,r2 + 803cee0: e0bfff17 ldw r2,-4(fp) + 803cee4: 10800917 ldw r2,36(r2) + 803cee8: 1880021e bne r3,r2,803cef4 + newrt = rtp; /* got an older one */ + 803ceec: e0bfff17 ldw r2,-4(fp) + 803cef0: e0bffe15 stw r2,-8(fp) + for (rtp = rt_mib; rtp < rt_mib + ipRoutes; rtp++) + 803cef4: e0bfff17 ldw r2,-4(fp) + 803cef8: 10800f04 addi r2,r2,60 + 803cefc: e0bfff15 stw r2,-4(fp) + 803cf00: d0e09517 ldw r3,-32172(gp) + 803cf04: d0a03017 ldw r2,-32576(gp) + 803cf08: 10800f24 muli r2,r2,60 + 803cf0c: 1885883a add r2,r3,r2 + 803cf10: e0ffff17 ldw r3,-4(fp) + 803cf14: 18bf9636 bltu r3,r2,803cd70 + } + } + } + + /* fall to here if not in table: create a new route */ + if (newrt) /* did we find an empty or lower priority route entry? */ + 803cf18: e0bffe17 ldw r2,-8(fp) + 803cf1c: 10002826 beq r2,zero,803cfc0 + rtp = newrt; /* create new entry in lowest priority slot */ + 803cf20: e0bffe17 ldw r2,-8(fp) + 803cf24: e0bfff15 stw r2,-4(fp) + else /* all slots have higher priority, new entry looses */ + return NULL; + + /* set default value in new route entry, caller can modiy further. */ + rtp->ifp = ifp; + 803cf28: e0bfff17 ldw r2,-4(fp) + 803cf2c: e0fffd17 ldw r3,-12(fp) + 803cf30: 10c00e15 stw r3,56(r2) + rtp->ipRouteDest = dest; + 803cf34: e0bfff17 ldw r2,-4(fp) + 803cf38: e0fffc17 ldw r3,-16(fp) + 803cf3c: 10c00015 stw r3,0(r2) + rtp->ipRouteIfIndex = (long)(if_netnumber(ifp)) + 1; /* set interface number */ + 803cf40: e13ffd17 ldw r4,-12(fp) + 803cf44: 80252fc0 call 80252fc + 803cf48: 10c00044 addi r3,r2,1 + 803cf4c: e0bfff17 ldw r2,-4(fp) + 803cf50: 10c00115 stw r3,4(r2) + rtp->ipRouteMetric1 = ip_mib.ipDefaultTTL; + 803cf54: 008201b4 movhi r2,2054 + 803cf58: 10b95017 ldw r2,-6848(r2) + 803cf5c: 1007883a mov r3,r2 + 803cf60: e0bfff17 ldw r2,-4(fp) + 803cf64: 10c00215 stw r3,8(r2) + rtp->ipRouteMetric2 = -1; + 803cf68: e0bfff17 ldw r2,-4(fp) + 803cf6c: 00ffffc4 movi r3,-1 + 803cf70: 10c00315 stw r3,12(r2) + rtp->ipRouteMetric3 = -1; + 803cf74: e0bfff17 ldw r2,-4(fp) + 803cf78: 00ffffc4 movi r3,-1 + 803cf7c: 10c00415 stw r3,16(r2) + rtp->ipRouteMetric4 = -1; + 803cf80: e0bfff17 ldw r2,-4(fp) + 803cf84: 00ffffc4 movi r3,-1 + 803cf88: 10c00515 stw r3,20(r2) + rtp->ipRouteNextHop = nexthop; + 803cf8c: e0bfff17 ldw r2,-4(fp) + 803cf90: e0fffa17 ldw r3,-24(fp) + 803cf94: 10c00615 stw r3,24(r2) + rtp->ipRouteProto = prot; /* icmp, or whatever */ + 803cf98: e0bfff17 ldw r2,-4(fp) + 803cf9c: e0c00217 ldw r3,8(fp) + 803cfa0: 10c00815 stw r3,32(r2) + + if ((dest & mask) == (nexthop & mask)) + 803cfa4: e0fffc17 ldw r3,-16(fp) + 803cfa8: e0bffa17 ldw r2,-24(fp) + 803cfac: 1886f03a xor r3,r3,r2 + 803cfb0: e0bffb17 ldw r2,-20(fp) + 803cfb4: 1884703a and r2,r3,r2 + 803cfb8: 1000071e bne r2,zero,803cfd8 + 803cfbc: 00000206 br 803cfc8 + return NULL; + 803cfc0: 0005883a mov r2,zero + 803cfc4: 00001106 br 803d00c + rtp->ipRouteType = IPRT_DIRECT; + 803cfc8: e0bfff17 ldw r2,-4(fp) + 803cfcc: 00c000c4 movi r3,3 + 803cfd0: 10c00715 stw r3,28(r2) + 803cfd4: 00000306 br 803cfe4 + else + rtp->ipRouteType = IPRT_INDIRECT; + 803cfd8: e0bfff17 ldw r2,-4(fp) + 803cfdc: 00c00104 movi r3,4 + 803cfe0: 10c00715 stw r3,28(r2) + + rtp->ipRouteAge = cticks; /* timestamp it */ + 803cfe4: d0e07d17 ldw r3,-32268(gp) + 803cfe8: e0bfff17 ldw r2,-4(fp) + 803cfec: 10c00915 stw r3,36(r2) + rtp->ipRouteMask = mask; + 803cff0: e0bfff17 ldw r2,-4(fp) + 803cff4: e0fffb17 ldw r3,-20(fp) + 803cff8: 10c00a15 stw r3,40(r2) + rtp->ipRouteMetric5 = -1; + 803cffc: e0bfff17 ldw r2,-4(fp) + 803d000: 00ffffc4 movi r3,-1 + 803d004: 10c00b15 stw r3,44(r2) + return(rtp); + 803d008: e0bfff17 ldw r2,-4(fp) +} + 803d00c: e037883a mov sp,fp + 803d010: dfc00117 ldw ra,4(sp) + 803d014: df000017 ldw fp,0(sp) + 803d018: dec00204 addi sp,sp,8 + 803d01c: f800283a ret + +0803d020 : + * RETURNS: Returns number of route table entries deleted. + */ + +int +del_route(ip_addr dest, ip_addr mask, int iface) +{ + 803d020: defff804 addi sp,sp,-32 + 803d024: dfc00715 stw ra,28(sp) + 803d028: df000615 stw fp,24(sp) + 803d02c: df000604 addi fp,sp,24 + 803d030: e13ffc15 stw r4,-16(fp) + 803d034: e17ffb15 stw r5,-20(fp) + 803d038: e1bffa15 stw r6,-24(fp) + RTMIB rtp; + int retval = 0; + 803d03c: e03ffe15 stw zero,-8(fp) + + /* set the route interface pointer according to the index passed. This allows + * the passed index to be used to access dynamic interfaces, which do not appear + * in the nets[] array. + */ + if(iface == -1) + 803d040: e0bffa17 ldw r2,-24(fp) + 803d044: 10bfffd8 cmpnei r2,r2,-1 + 803d048: 1000021e bne r2,zero,803d054 + ifp = NULL; /* wildcard */ + 803d04c: e03ffd15 stw zero,-12(fp) + 803d050: 00000306 br 803d060 + else + ifp = if_getbynum(iface); + 803d054: e13ffa17 ldw r4,-24(fp) + 803d058: 80240880 call 8024088 + 803d05c: e0bffd15 stw r2,-12(fp) + + if (rt_mib == NULL) /* Make sure we're up */ + 803d060: d0a09517 ldw r2,-32172(gp) + 803d064: 1000021e bne r2,zero,803d070 + return 0; + 803d068: 0005883a mov r2,zero + 803d06c: 00002c06 br 803d120 + + for (rtp = rt_mib; rtp < rt_mib + ipRoutes; rtp++) + 803d070: d0a09517 ldw r2,-32172(gp) + 803d074: e0bfff15 stw r2,-4(fp) + 803d078: 00002206 br 803d104 + { + if (!rtp->ipRouteNextHop) /* empty slot */ + 803d07c: e0bfff17 ldw r2,-4(fp) + 803d080: 10800617 ldw r2,24(r2) + 803d084: 10001926 beq r2,zero,803d0ec + continue; + if(ifp != NULL && ifp != rtp->ifp) + 803d088: e0bffd17 ldw r2,-12(fp) + 803d08c: 10000426 beq r2,zero,803d0a0 + 803d090: e0bfff17 ldw r2,-4(fp) + 803d094: 10800e17 ldw r2,56(r2) + 803d098: e0fffd17 ldw r3,-12(fp) + 803d09c: 1880151e bne r3,r2,803d0f4 + continue; /* interface didn't match */ + if ((rtp->ipRouteDest & mask) == (dest & mask)) + 803d0a0: e0bfff17 ldw r2,-4(fp) + 803d0a4: 10c00017 ldw r3,0(r2) + 803d0a8: e0bffc17 ldw r2,-16(fp) + 803d0ac: 1886f03a xor r3,r3,r2 + 803d0b0: e0bffb17 ldw r2,-20(fp) + 803d0b4: 1884703a and r2,r3,r2 + 803d0b8: 1000071e bne r2,zero,803d0d8 + { + MEMSET(rtp, 0, sizeof(*rtp)); /* clear entry */ + 803d0bc: 01800f04 movi r6,60 + 803d0c0: 000b883a mov r5,zero + 803d0c4: e13fff17 ldw r4,-4(fp) + 803d0c8: 80088e40 call 80088e4 + retval++; + 803d0cc: e0bffe17 ldw r2,-8(fp) + 803d0d0: 10800044 addi r2,r2,1 + 803d0d4: e0bffe15 stw r2,-8(fp) + } + if (cachedRoute == rtp) /* clear cache if it's being deleted */ + 803d0d8: d0a09c17 ldw r2,-32144(gp) + 803d0dc: e0ffff17 ldw r3,-4(fp) + 803d0e0: 1880051e bne r3,r2,803d0f8 + cachedRoute = NULL; + 803d0e4: d0209c15 stw zero,-32144(gp) + 803d0e8: 00000306 br 803d0f8 + continue; + 803d0ec: 0001883a nop + 803d0f0: 00000106 br 803d0f8 + continue; /* interface didn't match */ + 803d0f4: 0001883a nop + for (rtp = rt_mib; rtp < rt_mib + ipRoutes; rtp++) + 803d0f8: e0bfff17 ldw r2,-4(fp) + 803d0fc: 10800f04 addi r2,r2,60 + 803d100: e0bfff15 stw r2,-4(fp) + 803d104: d0e09517 ldw r3,-32172(gp) + 803d108: d0a03017 ldw r2,-32576(gp) + 803d10c: 10800f24 muli r2,r2,60 + 803d110: 1885883a add r2,r3,r2 + 803d114: e0ffff17 ldw r3,-4(fp) + 803d118: 18bfd836 bltu r3,r2,803d07c + } + return retval; + 803d11c: e0bffe17 ldw r2,-8(fp) +} + 803d120: e037883a mov sp,fp + 803d124: dfc00117 ldw ra,4(sp) + 803d128: df000017 ldw fp,0(sp) + 803d12c: dec00204 addi sp,sp,8 + 803d130: f800283a ret + +0803d134 : + * RETURNS: 0 if OK or ENP error code + */ + +int +udpdemux(PACKET p) +{ + 803d134: deffec04 addi sp,sp,-80 + 803d138: dfc01315 stw ra,76(sp) + 803d13c: df001215 stw fp,72(sp) + 803d140: df001204 addi fp,sp,72 + 803d144: e13ff215 stw r4,-56(fp) + unsigned short osum, xsum; /* scratch checksum holders */ + unsigned plen; /* packet length */ + int e; /* general error holder */ + + /* First let's verify that it's a valid UDP packet. */ + pip = ip_head(p); /* we'll need IP header info */ + 803d148: e0bff217 ldw r2,-56(fp) + 803d14c: 10800317 ldw r2,12(r2) + 803d150: e0bffb15 stw r2,-20(fp) + pup = (struct udp*)ip_data(pip); /* also need UDP header */ + 803d154: e0bffb17 ldw r2,-20(fp) + 803d158: 10800003 ldbu r2,0(r2) + 803d15c: 10803fcc andi r2,r2,255 + 803d160: 100490ba slli r2,r2,2 + 803d164: 10800f0c andi r2,r2,60 + 803d168: e0fffb17 ldw r3,-20(fp) + 803d16c: 1885883a add r2,r3,r2 + 803d170: e0bffa15 stw r2,-24(fp) + plen = htons(pup->ud_len); + 803d174: e0bffa17 ldw r2,-24(fp) + 803d178: 1080010b ldhu r2,4(r2) + 803d17c: 10bfffcc andi r2,r2,65535 + 803d180: 1004d23a srli r2,r2,8 + 803d184: 10bfffcc andi r2,r2,65535 + 803d188: 10c03fcc andi r3,r2,255 + 803d18c: e0bffa17 ldw r2,-24(fp) + 803d190: 1080010b ldhu r2,4(r2) + 803d194: 10bfffcc andi r2,r2,65535 + 803d198: 1004923a slli r2,r2,8 + 803d19c: 10bfffcc andi r2,r2,65535 + 803d1a0: 1884b03a or r2,r3,r2 + 803d1a4: e0bff915 stw r2,-28(fp) + + if (plen > p->nb_plen) + 803d1a8: e0bff217 ldw r2,-56(fp) + 803d1ac: 10c00417 ldw r3,16(r2) + 803d1b0: e0bff917 ldw r2,-28(fp) + 803d1b4: 1880232e bgeu r3,r2,803d244 +#ifdef NPDEBUG +/* + * Altera Niche Stack Nios port modification: + * cast arg to unsigned long to remove build warning + */ + if ((NDEBUG & UPCTRACE) && (NDEBUG & TPTRACE)) + 803d1b8: d0a06617 ldw r2,-32360(gp) + 803d1bc: 1081000c andi r2,r2,1024 + 803d1c0: 10001726 beq r2,zero,803d220 + 803d1c4: d0a06617 ldw r2,-32360(gp) + 803d1c8: 1080400c andi r2,r2,256 + 803d1cc: 10001426 beq r2,zero,803d220 + dprintf("UDP: bad len pkt: rcvd: %u, hdr: %u.\n", + 803d1d0: e0bff217 ldw r2,-56(fp) + 803d1d4: 11000417 ldw r4,16(r2) + p->nb_plen, (unsigned int)(htons(pup->ud_len) + UDPLEN)); + 803d1d8: e0bffa17 ldw r2,-24(fp) + 803d1dc: 1080010b ldhu r2,4(r2) + 803d1e0: 10bfffcc andi r2,r2,65535 + 803d1e4: 1004d23a srli r2,r2,8 + 803d1e8: 10bfffcc andi r2,r2,65535 + 803d1ec: 10c03fcc andi r3,r2,255 + 803d1f0: e0bffa17 ldw r2,-24(fp) + 803d1f4: 1080010b ldhu r2,4(r2) + 803d1f8: 10bfffcc andi r2,r2,65535 + 803d1fc: 1004923a slli r2,r2,8 + 803d200: 10bfffcc andi r2,r2,65535 + 803d204: 1884b03a or r2,r3,r2 + dprintf("UDP: bad len pkt: rcvd: %u, hdr: %u.\n", + 803d208: 10800204 addi r2,r2,8 + 803d20c: 100d883a mov r6,r2 + 803d210: 200b883a mov r5,r4 + 803d214: 01020174 movhi r4,2053 + 803d218: 212cf404 addi r4,r4,-19504 + 803d21c: 8002c780 call 8002c78 +#endif + udp_mib.udpInErrors++; + 803d220: 008201b4 movhi r2,2054 + 803d224: 10b96517 ldw r2,-6764(r2) + 803d228: 10c00044 addi r3,r2,1 + 803d22c: 008201b4 movhi r2,2054 + 803d230: 10f96515 stw r3,-6764(r2) + udp_free(p); + 803d234: e13ff217 ldw r4,-56(fp) + 803d238: 803ddb80 call 803ddb8 + return ENP_BAD_HEADER; + 803d23c: 00bff804 movi r2,-32 + 803d240: 00019206 br 803d88c + } + + osum = pup->ud_cksum; + 803d244: e0bffa17 ldw r2,-24(fp) + 803d248: 1080018b ldhu r2,6(r2) + 803d24c: e0bff88d sth r2,-30(fp) + /* did other guy use checksumming? */ + if (osum) + 803d250: e0bff88b ldhu r2,-30(fp) + 803d254: 10005626 beq r2,zero,803d3b0 + { + if (plen & 1) ((char *)pup)[plen] = 0; + 803d258: e0bff917 ldw r2,-28(fp) + 803d25c: 1080004c andi r2,r2,1 + 803d260: 10000426 beq r2,zero,803d274 + 803d264: e0fffa17 ldw r3,-24(fp) + 803d268: e0bff917 ldw r2,-28(fp) + 803d26c: 1885883a add r2,r3,r2 + 803d270: 10000005 stb zero,0(r2) + php.ph_src = p->fhost; + 803d274: e0bff217 ldw r2,-56(fp) + 803d278: 10800717 ldw r2,28(r2) + 803d27c: e0bff315 stw r2,-52(fp) + php.ph_dest = pip->ip_dest; + 803d280: e0bffb17 ldw r2,-20(fp) + 803d284: 10800417 ldw r2,16(r2) + 803d288: e0bff415 stw r2,-48(fp) + php.ph_zero = 0; + 803d28c: e03ff505 stb zero,-44(fp) + php.ph_prot = UDP_PROT; + 803d290: 00800444 movi r2,17 + 803d294: e0bff545 stb r2,-43(fp) + php.ph_len = pup->ud_len; + 803d298: e0bffa17 ldw r2,-24(fp) + 803d29c: 1080010b ldhu r2,4(r2) + 803d2a0: e0bff58d sth r2,-42(fp) + + pup->ud_cksum = cksum(&php, sizeof(struct ph)>>1); + 803d2a4: e0bff304 addi r2,fp,-52 + 803d2a8: 01400184 movi r5,6 + 803d2ac: 1009883a mov r4,r2 + 803d2b0: 8026d7c0 call 8026d7c + 803d2b4: 1007883a mov r3,r2 + 803d2b8: e0bffa17 ldw r2,-24(fp) + 803d2bc: 10c0018d sth r3,6(r2) + xsum = ~cksum(pup, (plen+1)>>1); + 803d2c0: e0bff917 ldw r2,-28(fp) + 803d2c4: 10800044 addi r2,r2,1 + 803d2c8: 1004d07a srli r2,r2,1 + 803d2cc: 100b883a mov r5,r2 + 803d2d0: e13ffa17 ldw r4,-24(fp) + 803d2d4: 8026d7c0 call 8026d7c + 803d2d8: 0084303a nor r2,zero,r2 + 803d2dc: e0bffe8d sth r2,-6(fp) + if (!xsum) + 803d2e0: e0bffe8b ldhu r2,-6(fp) + 803d2e4: 1000021e bne r2,zero,803d2f0 + xsum = 0xffff; + 803d2e8: 00bfffc4 movi r2,-1 + 803d2ec: e0bffe8d sth r2,-6(fp) + pup->ud_cksum = osum; + 803d2f0: e0bffa17 ldw r2,-24(fp) + 803d2f4: e0fff88b ldhu r3,-30(fp) + 803d2f8: 10c0018d sth r3,6(r2) + if (xsum != osum) + 803d2fc: e0fffe8b ldhu r3,-6(fp) + 803d300: e0bff88b ldhu r2,-30(fp) + 803d304: 18802a26 beq r3,r2,803d3b0 + { +#ifdef NPDEBUG + if ((NDEBUG & UPCTRACE) && (NDEBUG & TPTRACE)) + 803d308: d0a06617 ldw r2,-32360(gp) + 803d30c: 1081000c andi r2,r2,1024 + 803d310: 10001e26 beq r2,zero,803d38c + 803d314: d0a06617 ldw r2,-32360(gp) + 803d318: 1080400c andi r2,r2,256 + 803d31c: 10001b26 beq r2,zero,803d38c + { + dprintf("UDPDEMUX: bad xsum %04x right %04x from %u.%u.%u.%u\n", + 803d320: e17ff88b ldhu r5,-30(fp) + 803d324: e1bffe8b ldhu r6,-6(fp) + osum, xsum, PUSH_IPADDR(p->fhost)); + 803d328: e0bff217 ldw r2,-56(fp) + 803d32c: 10800717 ldw r2,28(r2) + dprintf("UDPDEMUX: bad xsum %04x right %04x from %u.%u.%u.%u\n", + 803d330: 11c03fcc andi r7,r2,255 + osum, xsum, PUSH_IPADDR(p->fhost)); + 803d334: e0bff217 ldw r2,-56(fp) + 803d338: 10800717 ldw r2,28(r2) + 803d33c: 1004d23a srli r2,r2,8 + dprintf("UDPDEMUX: bad xsum %04x right %04x from %u.%u.%u.%u\n", + 803d340: 10803fcc andi r2,r2,255 + osum, xsum, PUSH_IPADDR(p->fhost)); + 803d344: e0fff217 ldw r3,-56(fp) + 803d348: 18c00717 ldw r3,28(r3) + 803d34c: 1806d43a srli r3,r3,16 + dprintf("UDPDEMUX: bad xsum %04x right %04x from %u.%u.%u.%u\n", + 803d350: 18c03fcc andi r3,r3,255 + osum, xsum, PUSH_IPADDR(p->fhost)); + 803d354: e13ff217 ldw r4,-56(fp) + 803d358: 21000717 ldw r4,28(r4) + 803d35c: 2008d63a srli r4,r4,24 + dprintf("UDPDEMUX: bad xsum %04x right %04x from %u.%u.%u.%u\n", + 803d360: d9000215 stw r4,8(sp) + 803d364: d8c00115 stw r3,4(sp) + 803d368: d8800015 stw r2,0(sp) + 803d36c: 01020174 movhi r4,2053 + 803d370: 212cfe04 addi r4,r4,-19464 + 803d374: 8002c780 call 8002c78 + if (NDEBUG & DUMP) + 803d378: d0a06617 ldw r2,-32360(gp) + 803d37c: 1080008c andi r2,r2,2 + 803d380: 10000226 beq r2,zero,803d38c + ip_dump(p); + 803d384: e13ff217 ldw r4,-56(fp) + 803d388: 803b0cc0 call 803b0cc + } +#endif + udp_mib.udpInErrors++; + 803d38c: 008201b4 movhi r2,2054 + 803d390: 10b96517 ldw r2,-6764(r2) + 803d394: 10c00044 addi r3,r2,1 + 803d398: 008201b4 movhi r2,2054 + 803d39c: 10f96515 stw r3,-6764(r2) + udp_free(p); + 803d3a0: e13ff217 ldw r4,-56(fp) + 803d3a4: 803ddb80 call 803ddb8 + return ENP_BAD_HEADER; + 803d3a8: 00bff804 movi r2,-32 + 803d3ac: 00013706 br 803d88c + } + } + +#if (BYTE_ORDER == LITTLE_ENDIAN) + udpswap(pup); + 803d3b0: e13ffa17 ldw r4,-24(fp) + 803d3b4: 803db340 call 803db34 +#endif + + /* Prior to upcall, adjust nb_prot for size of IP and UDP headers */ + e = (sizeof(struct udp) + ip_hlen(pip)); + 803d3b8: e0bffb17 ldw r2,-20(fp) + 803d3bc: 10800003 ldbu r2,0(r2) + 803d3c0: 10803fcc andi r2,r2,255 + 803d3c4: 100490ba slli r2,r2,2 + 803d3c8: 10800f0c andi r2,r2,60 + 803d3cc: 10800204 addi r2,r2,8 + 803d3d0: e0bffd15 stw r2,-12(fp) + p->nb_plen -= e; + 803d3d4: e0bff217 ldw r2,-56(fp) + 803d3d8: 10c00417 ldw r3,16(r2) + 803d3dc: e0bffd17 ldw r2,-12(fp) + 803d3e0: 1887c83a sub r3,r3,r2 + 803d3e4: e0bff217 ldw r2,-56(fp) + 803d3e8: 10c00415 stw r3,16(r2) + p->nb_prot += e; + 803d3ec: e0bff217 ldw r2,-56(fp) + 803d3f0: 10c00317 ldw r3,12(r2) + 803d3f4: e0bffd17 ldw r2,-12(fp) + 803d3f8: 1887883a add r3,r3,r2 + 803d3fc: e0bff217 ldw r2,-56(fp) + 803d400: 10c00315 stw r3,12(r2) + +#ifdef NPDEBUG + if ((NDEBUG & UPCTRACE) && (NDEBUG & TPTRACE)) + 803d404: d0a06617 ldw r2,-32360(gp) + 803d408: 1081000c andi r2,r2,1024 + 803d40c: 10001f26 beq r2,zero,803d48c + 803d410: d0a06617 ldw r2,-32360(gp) + 803d414: 1080400c andi r2,r2,256 + 803d418: 10001c26 beq r2,zero,803d48c + { + dprintf("UDP: pkt[%u] from %u.%u.%u.%u:%d to %d\n", + plen, PUSH_IPADDR(p->fhost), pup->ud_srcp, pup->ud_dstp); + 803d41c: e0bff217 ldw r2,-56(fp) + 803d420: 10800717 ldw r2,28(r2) + dprintf("UDP: pkt[%u] from %u.%u.%u.%u:%d to %d\n", + 803d424: 11803fcc andi r6,r2,255 + plen, PUSH_IPADDR(p->fhost), pup->ud_srcp, pup->ud_dstp); + 803d428: e0bff217 ldw r2,-56(fp) + 803d42c: 10800717 ldw r2,28(r2) + 803d430: 1004d23a srli r2,r2,8 + dprintf("UDP: pkt[%u] from %u.%u.%u.%u:%d to %d\n", + 803d434: 11c03fcc andi r7,r2,255 + plen, PUSH_IPADDR(p->fhost), pup->ud_srcp, pup->ud_dstp); + 803d438: e0bff217 ldw r2,-56(fp) + 803d43c: 10800717 ldw r2,28(r2) + 803d440: 1004d43a srli r2,r2,16 + dprintf("UDP: pkt[%u] from %u.%u.%u.%u:%d to %d\n", + 803d444: 10803fcc andi r2,r2,255 + plen, PUSH_IPADDR(p->fhost), pup->ud_srcp, pup->ud_dstp); + 803d448: e0fff217 ldw r3,-56(fp) + 803d44c: 18c00717 ldw r3,28(r3) + 803d450: 1806d63a srli r3,r3,24 + 803d454: e13ffa17 ldw r4,-24(fp) + 803d458: 2100000b ldhu r4,0(r4) + dprintf("UDP: pkt[%u] from %u.%u.%u.%u:%d to %d\n", + 803d45c: 213fffcc andi r4,r4,65535 + plen, PUSH_IPADDR(p->fhost), pup->ud_srcp, pup->ud_dstp); + 803d460: e17ffa17 ldw r5,-24(fp) + 803d464: 2940008b ldhu r5,2(r5) + dprintf("UDP: pkt[%u] from %u.%u.%u.%u:%d to %d\n", + 803d468: 297fffcc andi r5,r5,65535 + 803d46c: d9400315 stw r5,12(sp) + 803d470: d9000215 stw r4,8(sp) + 803d474: d8c00115 stw r3,4(sp) + 803d478: d8800015 stw r2,0(sp) + 803d47c: e17ff917 ldw r5,-28(fp) + 803d480: 01020174 movhi r4,2053 + 803d484: 212d0c04 addi r4,r4,-19408 + 803d488: 8002c780 call 8002c78 +#endif /* INCLUDE_SNMPV3 */ +#endif /* PREBIND_AGENT */ + + /* run through the demux table and try to upcall it */ + + for (con = firstudp; con; con = con->u_next) + 803d48c: d0a09e17 ldw r2,-32136(gp) + 803d490: e0bfff15 stw r2,-4(fp) + 803d494: 0000aa06 br 803d740 + continue; +#endif + + /* enforce all three aspects of tuple matching. Old code + assumed lport was unique, which is not always so. */ + if (con->u_lport && (con->u_lport != pup->ud_dstp)) + 803d498: e0bfff17 ldw r2,-4(fp) + 803d49c: 1080018b ldhu r2,6(r2) + 803d4a0: 10bfffcc andi r2,r2,65535 + 803d4a4: 10000726 beq r2,zero,803d4c4 + 803d4a8: e0bfff17 ldw r2,-4(fp) + 803d4ac: 10c0018b ldhu r3,6(r2) + 803d4b0: e0bffa17 ldw r2,-24(fp) + 803d4b4: 1080008b ldhu r2,2(r2) + 803d4b8: 18ffffcc andi r3,r3,65535 + 803d4bc: 10bfffcc andi r2,r2,65535 + 803d4c0: 1880951e bne r3,r2,803d718 + continue; + if (con->u_fport && (con->u_fport != pup->ud_srcp)) + 803d4c4: e0bfff17 ldw r2,-4(fp) + 803d4c8: 1080020b ldhu r2,8(r2) + 803d4cc: 10bfffcc andi r2,r2,65535 + 803d4d0: 10000726 beq r2,zero,803d4f0 + 803d4d4: e0bfff17 ldw r2,-4(fp) + 803d4d8: 10c0020b ldhu r3,8(r2) + 803d4dc: e0bffa17 ldw r2,-24(fp) + 803d4e0: 1080000b ldhu r2,0(r2) + 803d4e4: 18ffffcc andi r3,r3,65535 + 803d4e8: 10bfffcc andi r2,r2,65535 + 803d4ec: 18808c1e bne r3,r2,803d720 + continue; + if (con->u_fhost && (con->u_fhost != p->fhost)) + 803d4f0: e0bfff17 ldw r2,-4(fp) + 803d4f4: 10800417 ldw r2,16(r2) + 803d4f8: 10000526 beq r2,zero,803d510 + 803d4fc: e0bfff17 ldw r2,-4(fp) + 803d500: 10c00417 ldw r3,16(r2) + 803d504: e0bff217 ldw r2,-56(fp) + 803d508: 10800717 ldw r2,28(r2) + 803d50c: 1880861e bne r3,r2,803d728 +#ifdef IP_MULTICAST + /* In the case of multicast, check if there is multicast membership + * attached to this socket and if so, is the incoming packet + * addressed to the multicast address + */ + if (IN_MULTICAST(ntohl(pip->ip_dest))) + 803d510: e0bffb17 ldw r2,-20(fp) + 803d514: 10800417 ldw r2,16(r2) + 803d518: 1006d63a srli r3,r2,24 + 803d51c: e0bffb17 ldw r2,-20(fp) + 803d520: 10800417 ldw r2,16(r2) + 803d524: 1004d23a srli r2,r2,8 + 803d528: 10bfc00c andi r2,r2,65280 + 803d52c: 1886b03a or r3,r3,r2 + 803d530: e0bffb17 ldw r2,-20(fp) + 803d534: 10800417 ldw r2,16(r2) + 803d538: 1004923a slli r2,r2,8 + 803d53c: 10803fec andhi r2,r2,255 + 803d540: 1886b03a or r3,r3,r2 + 803d544: e0bffb17 ldw r2,-20(fp) + 803d548: 10800417 ldw r2,16(r2) + 803d54c: 1004963a slli r2,r2,24 + 803d550: 1884b03a or r2,r3,r2 + 803d554: 10fc002c andhi r3,r2,61440 + 803d558: 00b80034 movhi r2,57344 + 803d55c: 18802d1e bne r3,r2,803d614 + { + struct socket *soptr = (struct socket *)con->u_data; + 803d560: e0bfff17 ldw r2,-4(fp) + 803d564: 10800617 ldw r2,24(r2) + 803d568: e0bff715 stw r2,-36(fp) + + if ((con->u_rcv == udp_soinput) && (soptr->inp_moptions != NULL)) + 803d56c: e0bfff17 ldw r2,-4(fp) + 803d570: 10c00517 ldw r3,20(r2) + 803d574: 008200f4 movhi r2,2051 + 803d578: 10990604 addi r2,r2,25624 + 803d57c: 1880251e bne r3,r2,803d614 + 803d580: e0bff717 ldw r2,-36(fp) + 803d584: 10800317 ldw r2,12(r2) + 803d588: 10002226 beq r2,zero,803d614 + { + u_short i; + struct ip_moptions *imo = soptr->inp_moptions; + 803d58c: e0bff717 ldw r2,-36(fp) + 803d590: 10800317 ldw r2,12(r2) + 803d594: e0bff615 stw r2,-40(fp) + + for (i = 0; i < imo->imo_num_memberships; ++i) + 803d598: e03ffc8d sth zero,-14(fp) + 803d59c: 00001706 br 803d5fc + { + if ((imo->imo_membership[i]->inm_netp == p->net) && + 803d5a0: e0bffc8b ldhu r2,-14(fp) + 803d5a4: e0fff617 ldw r3,-40(fp) + 803d5a8: 10800084 addi r2,r2,2 + 803d5ac: 100490ba slli r2,r2,2 + 803d5b0: 1885883a add r2,r3,r2 + 803d5b4: 10800017 ldw r2,0(r2) + 803d5b8: 10c00117 ldw r3,4(r2) + 803d5bc: e0bff217 ldw r2,-56(fp) + 803d5c0: 10800617 ldw r2,24(r2) + 803d5c4: 18800a1e bne r3,r2,803d5f0 + (imo->imo_membership[i]->inm_addr == pip->ip_dest)) + 803d5c8: e0bffc8b ldhu r2,-14(fp) + 803d5cc: e0fff617 ldw r3,-40(fp) + 803d5d0: 10800084 addi r2,r2,2 + 803d5d4: 100490ba slli r2,r2,2 + 803d5d8: 1885883a add r2,r3,r2 + 803d5dc: 10800017 ldw r2,0(r2) + 803d5e0: 10c00017 ldw r3,0(r2) + 803d5e4: e0bffb17 ldw r2,-20(fp) + 803d5e8: 10800417 ldw r2,16(r2) + if ((imo->imo_membership[i]->inm_netp == p->net) && + 803d5ec: 18800b26 beq r3,r2,803d61c + for (i = 0; i < imo->imo_num_memberships; ++i) + 803d5f0: e0bffc8b ldhu r2,-14(fp) + 803d5f4: 10800044 addi r2,r2,1 + 803d5f8: e0bffc8d sth r2,-14(fp) + 803d5fc: e0bff617 ldw r2,-40(fp) + 803d600: 1080018b ldhu r2,6(r2) + 803d604: e0fffc8b ldhu r3,-14(fp) + 803d608: 10bfffcc andi r2,r2,65535 + 803d60c: 18bfe436 bltu r3,r2,803d5a0 + { + goto found; + } + } + continue; + 803d610: 00004806 br 803d734 + } + } + found: + 803d614: 0001883a nop + 803d618: 00000106 br 803d620 + goto found; + 803d61c: 0001883a nop +#endif /* INCLUDE_TCP */ + + /* if this endpoint has been bound to a local interface address, + * make sure the packet was received on that interface address + */ + if (!IN_MULTICAST(ntohl(pip->ip_dest))) + 803d620: e0bffb17 ldw r2,-20(fp) + 803d624: 10800417 ldw r2,16(r2) + 803d628: 1006d63a srli r3,r2,24 + 803d62c: e0bffb17 ldw r2,-20(fp) + 803d630: 10800417 ldw r2,16(r2) + 803d634: 1004d23a srli r2,r2,8 + 803d638: 10bfc00c andi r2,r2,65280 + 803d63c: 1886b03a or r3,r3,r2 + 803d640: e0bffb17 ldw r2,-20(fp) + 803d644: 10800417 ldw r2,16(r2) + 803d648: 1004923a slli r2,r2,8 + 803d64c: 10803fec andhi r2,r2,255 + 803d650: 1886b03a or r3,r3,r2 + 803d654: e0bffb17 ldw r2,-20(fp) + 803d658: 10800417 ldw r2,16(r2) + 803d65c: 1004963a slli r2,r2,24 + 803d660: 1884b03a or r2,r3,r2 + 803d664: 10fc002c andhi r3,r2,61440 + 803d668: 00b80034 movhi r2,57344 + 803d66c: 18800826 beq r3,r2,803d690 + { + if ((con->u_lhost != 0) && (con->u_lhost != pip->ip_dest)) + 803d670: e0bfff17 ldw r2,-4(fp) + 803d674: 10800317 ldw r2,12(r2) + 803d678: 10000526 beq r2,zero,803d690 + 803d67c: e0bfff17 ldw r2,-4(fp) + 803d680: 10c00317 ldw r3,12(r2) + 803d684: e0bffb17 ldw r2,-20(fp) + 803d688: 10800417 ldw r2,16(r2) + 803d68c: 1880281e bne r3,r2,803d730 + continue; + } + + /* fall to here if we found it */ + udp_mib.udpInDatagrams++; + 803d690: 008201b4 movhi r2,2054 + 803d694: 10b96317 ldw r2,-6772(r2) + 803d698: 10c00044 addi r3,r2,1 + 803d69c: 008201b4 movhi r2,2054 + 803d6a0: 10f96315 stw r3,-6772(r2) + if (con->u_rcv) /* if upcall address is set... */ + 803d6a4: e0bfff17 ldw r2,-4(fp) + 803d6a8: 10800517 ldw r2,20(r2) + 803d6ac: 10000d26 beq r2,zero,803d6e4 + { + UNLOCK_NET_RESOURCE(NET_RESID); + 803d6b0: 0009883a mov r4,zero + 803d6b4: 8028ff40 call 8028ff4 + e = ((*con->u_rcv)(p, con->u_data)); /* upcall it */ + 803d6b8: e0bfff17 ldw r2,-4(fp) + 803d6bc: 10800517 ldw r2,20(r2) + 803d6c0: e0ffff17 ldw r3,-4(fp) + 803d6c4: 18c00617 ldw r3,24(r3) + 803d6c8: 180b883a mov r5,r3 + 803d6cc: e13ff217 ldw r4,-56(fp) + 803d6d0: 103ee83a callr r2 + 803d6d4: e0bffd15 stw r2,-12(fp) + LOCK_NET_RESOURCE(NET_RESID); + 803d6d8: 0009883a mov r4,zero + 803d6dc: 8028f380 call 8028f38 + 803d6e0: 00000206 br 803d6ec + } + else + e = ENP_LOGIC; + 803d6e4: 00bffd44 movi r2,-11 + 803d6e8: e0bffd15 stw r2,-12(fp) + + /* if error occurred in upcall or there was no upcall hander + its up to this routine to free the packet buffer */ + if (e) + 803d6ec: e0bffd17 ldw r2,-12(fp) + 803d6f0: 10000726 beq r2,zero,803d710 + { + udp_mib.udpInErrors++; + 803d6f4: 008201b4 movhi r2,2054 + 803d6f8: 10b96517 ldw r2,-6764(r2) + 803d6fc: 10c00044 addi r3,r2,1 + 803d700: 008201b4 movhi r2,2054 + 803d704: 10f96515 stw r3,-6764(r2) + udp_free(p); + 803d708: e13ff217 ldw r4,-56(fp) + 803d70c: 803ddb80 call 803ddb8 + } + + return(e); + 803d710: e0bffd17 ldw r2,-12(fp) + 803d714: 00005d06 br 803d88c + continue; + 803d718: 0001883a nop + 803d71c: 00000506 br 803d734 + continue; + 803d720: 0001883a nop + 803d724: 00000306 br 803d734 + continue; + 803d728: 0001883a nop + 803d72c: 00000106 br 803d734 + continue; + 803d730: 0001883a nop + for (con = firstudp; con; con = con->u_next) + 803d734: e0bfff17 ldw r2,-4(fp) + 803d738: 10800017 ldw r2,0(r2) + 803d73c: e0bfff15 stw r2,-4(fp) + 803d740: e0bfff17 ldw r2,-4(fp) + 803d744: 103f541e bne r2,zero,803d498 + + /* Fall to here if packet is not for us. Check if the packet was + * sent to an ip broadcast address. If it was, don't send a + * destination unreachable. + */ + if ((pip->ip_dest == 0xffffffffL) || /* Physical cable broadcast addr*/ + 803d748: e0bffb17 ldw r2,-20(fp) + 803d74c: 10800417 ldw r2,16(r2) + 803d750: 10bfffe0 cmpeqi r2,r2,-1 + 803d754: 1000121e bne r2,zero,803d7a0 + (pip->ip_dest == p->net->n_netbr) || /* All subnet broadcast */ + 803d758: e0bffb17 ldw r2,-20(fp) + 803d75c: 10c00417 ldw r3,16(r2) + 803d760: e0bff217 ldw r2,-56(fp) + 803d764: 10800617 ldw r2,24(r2) + 803d768: 10800e17 ldw r2,56(r2) + if ((pip->ip_dest == 0xffffffffL) || /* Physical cable broadcast addr*/ + 803d76c: 18800c26 beq r3,r2,803d7a0 + (pip->ip_dest == p->net->n_netbr42) || /* All subnet bcast (4.2bsd) */ + 803d770: e0bffb17 ldw r2,-20(fp) + 803d774: 10c00417 ldw r3,16(r2) + 803d778: e0bff217 ldw r2,-56(fp) + 803d77c: 10800617 ldw r2,24(r2) + 803d780: 10800f17 ldw r2,60(r2) + (pip->ip_dest == p->net->n_netbr) || /* All subnet broadcast */ + 803d784: 18800626 beq r3,r2,803d7a0 + (pip->ip_dest == p->net->n_subnetbr)) /* Our subnet broadcast */ + 803d788: e0bffb17 ldw r2,-20(fp) + 803d78c: 10c00417 ldw r3,16(r2) + 803d790: e0bff217 ldw r2,-56(fp) + 803d794: 10800617 ldw r2,24(r2) + 803d798: 10801017 ldw r2,64(r2) + (pip->ip_dest == p->net->n_netbr42) || /* All subnet bcast (4.2bsd) */ + 803d79c: 1880121e bne r3,r2,803d7e8 + { +#ifdef NPDEBUG + if ((NDEBUG & UPCTRACE) && (NDEBUG & TPTRACE)) + 803d7a0: d0a06617 ldw r2,-32360(gp) + 803d7a4: 1081000c andi r2,r2,1024 + 803d7a8: 10000626 beq r2,zero,803d7c4 + 803d7ac: d0a06617 ldw r2,-32360(gp) + 803d7b0: 1080400c andi r2,r2,256 + 803d7b4: 10000326 beq r2,zero,803d7c4 + dprintf("UDP: ignoring ip broadcast\n"); + 803d7b8: 01020174 movhi r4,2053 + 803d7bc: 212d1604 addi r4,r4,-19368 + 803d7c0: 8002d9c0 call 8002d9c +#endif + udp_mib.udpInErrors++; + 803d7c4: 008201b4 movhi r2,2054 + 803d7c8: 10b96517 ldw r2,-6764(r2) + 803d7cc: 10c00044 addi r3,r2,1 + 803d7d0: 008201b4 movhi r2,2054 + 803d7d4: 10f96515 stw r3,-6764(r2) + udp_free(p); + 803d7d8: e13ff217 ldw r4,-56(fp) + 803d7dc: 803ddb80 call 803ddb8 + return ENP_NOT_MINE; + 803d7e0: 00800084 movi r2,2 + 803d7e4: 00002906 br 803d88c + } + +#ifdef NPDEBUG + if ((NDEBUG & UPCTRACE) && (NDEBUG & TPTRACE)) + 803d7e8: d0a06617 ldw r2,-32360(gp) + 803d7ec: 1081000c andi r2,r2,1024 + 803d7f0: 10000f26 beq r2,zero,803d830 + 803d7f4: d0a06617 ldw r2,-32360(gp) + 803d7f8: 1080400c andi r2,r2,256 + 803d7fc: 10000c26 beq r2,zero,803d830 + { + dprintf("UDP: unexpected port %04x\n", pup->ud_dstp); + 803d800: e0bffa17 ldw r2,-24(fp) + 803d804: 1080008b ldhu r2,2(r2) + 803d808: 10bfffcc andi r2,r2,65535 + 803d80c: 100b883a mov r5,r2 + 803d810: 01020174 movhi r4,2053 + 803d814: 212d1d04 addi r4,r4,-19340 + 803d818: 8002c780 call 8002c78 + if (NDEBUG & DUMP) + 803d81c: d0a06617 ldw r2,-32360(gp) + 803d820: 1080008c andi r2,r2,2 + 803d824: 10000226 beq r2,zero,803d830 + ip_dump(p); + 803d828: e13ff217 ldw r4,-56(fp) + 803d82c: 803b0cc0 call 803b0cc +#ifdef FULL_ICMP + /* send destination unreachable. Swap back all the swapped information */ + /* so that the destun packet format is correct */ + +#if (BYTE_ORDER == LITTLE_ENDIAN) + udpswap(pup); + 803d830: e13ffa17 ldw r4,-24(fp) + 803d834: 803db340 call 803db34 +#endif /* BYTE_ORDER */ + + icmp_destun(p->fhost, p->net->n_ipaddr, pip, DSTPORT, p->net); + 803d838: e0bff217 ldw r2,-56(fp) + 803d83c: 10c00717 ldw r3,28(r2) + 803d840: e0bff217 ldw r2,-56(fp) + 803d844: 10800617 ldw r2,24(r2) + 803d848: 11000a17 ldw r4,40(r2) + 803d84c: e0bff217 ldw r2,-56(fp) + 803d850: 10800617 ldw r2,24(r2) + 803d854: d8800015 stw r2,0(sp) + 803d858: 01c000c4 movi r7,3 + 803d85c: e1bffb17 ldw r6,-20(fp) + 803d860: 200b883a mov r5,r4 + 803d864: 1809883a mov r4,r3 + 803d868: 8039a540 call 8039a54 +#endif /* FULL_ICMP */ + + udp_mib.udpNoPorts++; + 803d86c: 008201b4 movhi r2,2054 + 803d870: 10b96417 ldw r2,-6768(r2) + 803d874: 10c00044 addi r3,r2,1 + 803d878: 008201b4 movhi r2,2054 + 803d87c: 10f96415 stw r3,-6768(r2) + udp_free(p); + 803d880: e13ff217 ldw r4,-56(fp) + 803d884: 803ddb80 call 803ddb8 + return ENP_NOT_MINE; + 803d888: 00800084 movi r2,2 +} + 803d88c: e037883a mov sp,fp + 803d890: dfc00117 ldw ra,4(sp) + 803d894: df000017 ldw fp,0(sp) + 803d898: dec00204 addi sp,sp,8 + 803d89c: f800283a ret + +0803d8a0 : + * detected. + */ + +int +udp_send(unshort fport, unshort lport, PACKET p) +{ + 803d8a0: deffef04 addi sp,sp,-68 + 803d8a4: dfc01015 stw ra,64(sp) + 803d8a8: df000f15 stw fp,60(sp) + 803d8ac: df000f04 addi fp,sp,60 + 803d8b0: 2005883a mov r2,r4 + 803d8b4: 2807883a mov r3,r5 + 803d8b8: e1bff515 stw r6,-44(fp) + 803d8bc: e0bff70d sth r2,-36(fp) + 803d8c0: 1805883a mov r2,r3 + 803d8c4: e0bff60d sth r2,-40(fp) + int udplen; + int e; + ip_addr src_ip; /* source IP, for checksumming purposes */ + +#ifdef NPDEBUG + if (NDEBUG & (INFOMSG|TPTRACE)) + 803d8c8: d0a06617 ldw r2,-32360(gp) + 803d8cc: 1080410c andi r2,r2,260 + 803d8d0: 10001a26 beq r2,zero,803d93c + dprintf("UDP: pkt [%u] %04x -> %u.%u.%u.%u:%04x\n", p->nb_plen, lport, + 803d8d4: e0bff517 ldw r2,-44(fp) + 803d8d8: 12000417 ldw r8,16(r2) + 803d8dc: e1bff60b ldhu r6,-40(fp) + PUSH_IPADDR(p->fhost), fport); + 803d8e0: e0bff517 ldw r2,-44(fp) + 803d8e4: 10800717 ldw r2,28(r2) + dprintf("UDP: pkt [%u] %04x -> %u.%u.%u.%u:%04x\n", p->nb_plen, lport, + 803d8e8: 11c03fcc andi r7,r2,255 + PUSH_IPADDR(p->fhost), fport); + 803d8ec: e0bff517 ldw r2,-44(fp) + 803d8f0: 10800717 ldw r2,28(r2) + 803d8f4: 1004d23a srli r2,r2,8 + dprintf("UDP: pkt [%u] %04x -> %u.%u.%u.%u:%04x\n", p->nb_plen, lport, + 803d8f8: 10803fcc andi r2,r2,255 + PUSH_IPADDR(p->fhost), fport); + 803d8fc: e0fff517 ldw r3,-44(fp) + 803d900: 18c00717 ldw r3,28(r3) + 803d904: 1806d43a srli r3,r3,16 + dprintf("UDP: pkt [%u] %04x -> %u.%u.%u.%u:%04x\n", p->nb_plen, lport, + 803d908: 18c03fcc andi r3,r3,255 + PUSH_IPADDR(p->fhost), fport); + 803d90c: e13ff517 ldw r4,-44(fp) + 803d910: 21000717 ldw r4,28(r4) + 803d914: 2008d63a srli r4,r4,24 + dprintf("UDP: pkt [%u] %04x -> %u.%u.%u.%u:%04x\n", p->nb_plen, lport, + 803d918: e17ff70b ldhu r5,-36(fp) + 803d91c: d9400315 stw r5,12(sp) + 803d920: d9000215 stw r4,8(sp) + 803d924: d8c00115 stw r3,4(sp) + 803d928: d8800015 stw r2,0(sp) + 803d92c: 400b883a mov r5,r8 + 803d930: 01020174 movhi r4,2053 + 803d934: 212d2404 addi r4,r4,-19312 + 803d938: 8002c780 call 8002c78 +#endif + + LOCK_NET_RESOURCE(NET_RESID); + 803d93c: 0009883a mov r4,zero + 803d940: 8028f380 call 8028f38 + /* prepend UDP header to upper layer's data */ + p->nb_prot -= sizeof(struct udp); + 803d944: e0bff517 ldw r2,-44(fp) + 803d948: 10800317 ldw r2,12(r2) + 803d94c: 10fffe04 addi r3,r2,-8 + 803d950: e0bff517 ldw r2,-44(fp) + 803d954: 10c00315 stw r3,12(r2) + pup = (struct udp*)p->nb_prot; + 803d958: e0bff517 ldw r2,-44(fp) + 803d95c: 10800317 ldw r2,12(r2) + 803d960: e0bffe15 stw r2,-8(fp) + udplen = p->nb_plen + sizeof(struct udp); + 803d964: e0bff517 ldw r2,-44(fp) + 803d968: 10800417 ldw r2,16(r2) + 803d96c: 10800204 addi r2,r2,8 + 803d970: e0bffd15 stw r2,-12(fp) + p->nb_plen = udplen; + 803d974: e0fffd17 ldw r3,-12(fp) + 803d978: e0bff517 ldw r2,-44(fp) + 803d97c: 10c00415 stw r3,16(r2) + if (udplen & 1) ((char *)pup)[udplen] = 0; + 803d980: e0bffd17 ldw r2,-12(fp) + 803d984: 1080004c andi r2,r2,1 + 803d988: 10000426 beq r2,zero,803d99c + 803d98c: e0bffd17 ldw r2,-12(fp) + 803d990: e0fffe17 ldw r3,-8(fp) + 803d994: 1885883a add r2,r3,r2 + 803d998: 10000005 stb zero,0(r2) + + pup->ud_len = (unshort)udplen; /* fill in the UDP header */ + 803d99c: e0bffd17 ldw r2,-12(fp) + 803d9a0: 1007883a mov r3,r2 + 803d9a4: e0bffe17 ldw r2,-8(fp) + 803d9a8: 10c0010d sth r3,4(r2) + pup->ud_srcp = lport; + 803d9ac: e0bffe17 ldw r2,-8(fp) + 803d9b0: e0fff60b ldhu r3,-40(fp) + 803d9b4: 10c0000d sth r3,0(r2) + pup->ud_dstp = fport; + 803d9b8: e0bffe17 ldw r2,-8(fp) + 803d9bc: e0fff70b ldhu r3,-36(fp) + 803d9c0: 10c0008d sth r3,2(r2) + +#if (BYTE_ORDER == LITTLE_ENDIAN) + udpswap(pup); + 803d9c4: e13ffe17 ldw r4,-8(fp) + 803d9c8: 803db340 call 803db34 +#endif /* BYTE_ORDER */ + +#ifdef MULTI_HOMED + /* getting the source IP address for a broadcast is a bit tricky: */ + if (p->fhost == 0xffffffff) + 803d9cc: e0bff517 ldw r2,-44(fp) + 803d9d0: 10800717 ldw r2,28(r2) + 803d9d4: 10bfffd8 cmpnei r2,r2,-1 + 803d9d8: 10000f1e bne r2,zero,803da18 + { + if (!p->net) + 803d9dc: e0bff517 ldw r2,-44(fp) + 803d9e0: 10800617 ldw r2,24(r2) + 803d9e4: 1000071e bne r2,zero,803da04 + { + dtrap(); /* programmer forgot to select iface */ + 803d9e8: 8028cd40 call 8028cd4 + /* it would appear that the callers of udp_send() expect it + to do cleanup on failure, so free the packet buffer here */ + udp_free(p); + 803d9ec: e13ff517 ldw r4,-44(fp) + 803d9f0: 803ddb80 call 803ddb8 + UNLOCK_NET_RESOURCE(NET_RESID); + 803d9f4: 0009883a mov r4,zero + 803d9f8: 8028ff40 call 8028ff4 + return ENP_NO_IFACE; + 803d9fc: 00bff784 movi r2,-34 + 803da00: 00004706 br 803db20 + } + src_ip = p->net->n_ipaddr; + 803da04: e0bff517 ldw r2,-44(fp) + 803da08: 10800617 ldw r2,24(r2) + 803da0c: 10800a17 ldw r2,40(r2) + 803da10: e0bfff15 stw r2,-4(fp) + 803da14: 00000506 br 803da2c + /* set the IP addresses in the IP header. The pseudo header used for + * checksumming overlays the addresses on the IP header area in the + * buffer, so setting them there (which we need to do for cksum + * anyway) sets up for IP too. + */ + src_ip = ip_mymach(p->fhost); + 803da18: e0bff517 ldw r2,-44(fp) + 803da1c: 10800717 ldw r2,28(r2) + 803da20: 1009883a mov r4,r2 + 803da24: 803b0280 call 803b028 + 803da28: e0bfff15 stw r2,-4(fp) + php.ph_src = src_ip; + 803da2c: e0bfff17 ldw r2,-4(fp) + 803da30: e0bff815 stw r2,-32(fp) + php.ph_dest = p->fhost; + 803da34: e0bff517 ldw r2,-44(fp) + 803da38: 10800717 ldw r2,28(r2) + 803da3c: e0bff915 stw r2,-28(fp) +#ifdef NO_UDP_CKSUM + /* If no UDP checksum support, just zero the checksum field */ + pup->ud_cksum = 0; +#else + /* finish filling in the pseudo header required for checksumming */ + php.ph_zero = 0; + 803da40: e03ffa05 stb zero,-24(fp) + php.ph_prot = UDP_PROT; + 803da44: 00800444 movi r2,17 + 803da48: e0bffa45 stb r2,-23(fp) + php.ph_len = pup->ud_len; + 803da4c: e0bffe17 ldw r2,-8(fp) + 803da50: 1080010b ldhu r2,4(r2) + 803da54: e0bffa8d sth r2,-22(fp) + pup->ud_cksum = cksum(&php, sizeof(struct ph)>>1); + 803da58: e0bff804 addi r2,fp,-32 + 803da5c: 01400184 movi r5,6 + 803da60: 1009883a mov r4,r2 + 803da64: 8026d7c0 call 8026d7c + 803da68: 1007883a mov r3,r2 + 803da6c: e0bffe17 ldw r2,-8(fp) + 803da70: 10c0018d sth r3,6(r2) + pup->ud_cksum = ~cksum(pup, (udplen+1)>>1); + 803da74: e0bffd17 ldw r2,-12(fp) + 803da78: 10800044 addi r2,r2,1 + 803da7c: 1005d07a srai r2,r2,1 + 803da80: 100b883a mov r5,r2 + 803da84: e13ffe17 ldw r4,-8(fp) + 803da88: 8026d7c0 call 8026d7c + 803da8c: 0084303a nor r2,zero,r2 + 803da90: 1007883a mov r3,r2 + 803da94: e0bffe17 ldw r2,-8(fp) + 803da98: 10c0018d sth r3,6(r2) + if (pup->ud_cksum == 0) + 803da9c: e0bffe17 ldw r2,-8(fp) + 803daa0: 1080018b ldhu r2,6(r2) + 803daa4: 10bfffcc andi r2,r2,65535 + 803daa8: 1000031e bne r2,zero,803dab8 + pup->ud_cksum = 0xffff; + 803daac: e0bffe17 ldw r2,-8(fp) + 803dab0: 00ffffc4 movi r3,-1 + 803dab4: 10c0018d sth r3,6(r2) +#endif + + /* need to fill in IP addresses at this layer too */ + pip = (struct ip *)(p->nb_prot - sizeof(struct ip)); + 803dab8: e0bff517 ldw r2,-44(fp) + 803dabc: 10800317 ldw r2,12(r2) + 803dac0: 10bffb04 addi r2,r2,-20 + 803dac4: e0bffc15 stw r2,-16(fp) + pip->ip_src = src_ip; + 803dac8: e0bffc17 ldw r2,-16(fp) + 803dacc: e0ffff17 ldw r3,-4(fp) + 803dad0: 10c00315 stw r3,12(r2) + pip->ip_dest = p->fhost; + 803dad4: e0bff517 ldw r2,-44(fp) + 803dad8: 10c00717 ldw r3,28(r2) + 803dadc: e0bffc17 ldw r2,-16(fp) + 803dae0: 10c00415 stw r3,16(r2) + + udp_mib.udpOutDatagrams++; + 803dae4: 008201b4 movhi r2,2054 + 803dae8: 10b96617 ldw r2,-6760(r2) + 803daec: 10c00044 addi r3,r2,1 + 803daf0: 008201b4 movhi r2,2054 + 803daf4: 10f96615 stw r3,-6760(r2) + + p->nb_plen = udplen; /* nb_prot was adjusted above */ + 803daf8: e0fffd17 ldw r3,-12(fp) + 803dafc: e0bff517 ldw r2,-44(fp) + 803db00: 10c00415 stw r3,16(r2) + e = ip_write(UDP_PROT, p); + 803db04: e17ff517 ldw r5,-44(fp) + 803db08: 01000444 movi r4,17 + 803db0c: 803a9e80 call 803a9e8 + 803db10: e0bffb15 stw r2,-20(fp) + UNLOCK_NET_RESOURCE(NET_RESID); + 803db14: 0009883a mov r4,zero + 803db18: 8028ff40 call 8028ff4 + return e; + 803db1c: e0bffb17 ldw r2,-20(fp) +} + 803db20: e037883a mov sp,fp + 803db24: dfc00117 ldw ra,4(sp) + 803db28: df000017 ldw fp,0(sp) + 803db2c: dec00204 addi sp,sp,8 + 803db30: f800283a ret + +0803db34 : + */ + +#if (BYTE_ORDER == LITTLE_ENDIAN) +void +udpswap(struct udp *pup) +{ + 803db34: defffe04 addi sp,sp,-8 + 803db38: df000115 stw fp,4(sp) + 803db3c: df000104 addi fp,sp,4 + 803db40: e13fff15 stw r4,-4(fp) + + pup->ud_srcp = htons(pup->ud_srcp); + 803db44: e0bfff17 ldw r2,-4(fp) + 803db48: 1080000b ldhu r2,0(r2) + 803db4c: 10bfffcc andi r2,r2,65535 + 803db50: 1004d23a srli r2,r2,8 + 803db54: 1007883a mov r3,r2 + 803db58: e0bfff17 ldw r2,-4(fp) + 803db5c: 1080000b ldhu r2,0(r2) + 803db60: 10bfffcc andi r2,r2,65535 + 803db64: 1004923a slli r2,r2,8 + 803db68: 1884b03a or r2,r3,r2 + 803db6c: 1007883a mov r3,r2 + 803db70: e0bfff17 ldw r2,-4(fp) + 803db74: 10c0000d sth r3,0(r2) + pup->ud_dstp = htons(pup->ud_dstp); + 803db78: e0bfff17 ldw r2,-4(fp) + 803db7c: 1080008b ldhu r2,2(r2) + 803db80: 10bfffcc andi r2,r2,65535 + 803db84: 1004d23a srli r2,r2,8 + 803db88: 1007883a mov r3,r2 + 803db8c: e0bfff17 ldw r2,-4(fp) + 803db90: 1080008b ldhu r2,2(r2) + 803db94: 10bfffcc andi r2,r2,65535 + 803db98: 1004923a slli r2,r2,8 + 803db9c: 1884b03a or r2,r3,r2 + 803dba0: 1007883a mov r3,r2 + 803dba4: e0bfff17 ldw r2,-4(fp) + 803dba8: 10c0008d sth r3,2(r2) + pup->ud_len = htons(pup->ud_len); + 803dbac: e0bfff17 ldw r2,-4(fp) + 803dbb0: 1080010b ldhu r2,4(r2) + 803dbb4: 10bfffcc andi r2,r2,65535 + 803dbb8: 1004d23a srli r2,r2,8 + 803dbbc: 1007883a mov r3,r2 + 803dbc0: e0bfff17 ldw r2,-4(fp) + 803dbc4: 1080010b ldhu r2,4(r2) + 803dbc8: 10bfffcc andi r2,r2,65535 + 803dbcc: 1004923a slli r2,r2,8 + 803dbd0: 1884b03a or r2,r3,r2 + 803dbd4: 1007883a mov r3,r2 + 803dbd8: e0bfff17 ldw r2,-4(fp) + 803dbdc: 10c0010d sth r3,4(r2) + pup->ud_cksum = htons(pup->ud_cksum); + 803dbe0: e0bfff17 ldw r2,-4(fp) + 803dbe4: 1080018b ldhu r2,6(r2) + 803dbe8: 10bfffcc andi r2,r2,65535 + 803dbec: 1004d23a srli r2,r2,8 + 803dbf0: 1007883a mov r3,r2 + 803dbf4: e0bfff17 ldw r2,-4(fp) + 803dbf8: 1080018b ldhu r2,6(r2) + 803dbfc: 10bfffcc andi r2,r2,65535 + 803dc00: 1004923a slli r2,r2,8 + 803dc04: 1884b03a or r2,r3,r2 + 803dc08: 1007883a mov r3,r2 + 803dc0c: e0bfff17 ldw r2,-4(fp) + 803dc10: 10c0018d sth r3,6(r2) +} + 803dc14: 0001883a nop + 803dc18: e037883a mov sp,fp + 803dc1c: df000017 ldw fp,0(sp) + 803dc20: dec00104 addi sp,sp,4 + 803dc24: f800283a ret + +0803dc28 : +#define MINSOCKET 1200 +static unshort usocket = 0; /* next socket to grab */ + +unshort +udp_socket(void) +{ + 803dc28: defffe04 addi sp,sp,-8 + 803dc2c: df000115 stw fp,4(sp) + 803dc30: df000104 addi fp,sp,4 + UDPCONN tmp; + + if (usocket < MINSOCKET) + 803dc34: d0a09d0b ldhu r2,-32140(gp) + 803dc38: 10bfffcc andi r2,r2,65535 + 803dc3c: 10812c28 cmpgeui r2,r2,1200 + 803dc40: 10000a1e bne r2,zero,803dc6c + { + /* logic for for init and after wraps */ + usocket = (unshort)(cticks & 0x7fff); + 803dc44: d0a07d17 ldw r2,-32268(gp) + 803dc48: 109fffcc andi r2,r2,32767 + 803dc4c: d0a09d0d sth r2,-32140(gp) + if (usocket < MINSOCKET) + 803dc50: d0a09d0b ldhu r2,-32140(gp) + 803dc54: 10bfffcc andi r2,r2,65535 + 803dc58: 10812c28 cmpgeui r2,r2,1200 + 803dc5c: 1000031e bne r2,zero,803dc6c + usocket += MINSOCKET; + 803dc60: d0a09d0b ldhu r2,-32140(gp) + 803dc64: 10812c04 addi r2,r2,1200 + 803dc68: d0a09d0d sth r2,-32140(gp) + } + /* scan existing connections, making sure socket isn't in use */ + for (tmp = firstudp; tmp; tmp = tmp->u_next) + 803dc6c: d0a09e17 ldw r2,-32136(gp) + 803dc70: e0bfff15 stw r2,-4(fp) + 803dc74: 00000f06 br 803dcb4 + { + if (tmp->u_lport == usocket) + 803dc78: e0bfff17 ldw r2,-4(fp) + 803dc7c: 10c0018b ldhu r3,6(r2) + 803dc80: d0a09d0b ldhu r2,-32140(gp) + 803dc84: 18ffffcc andi r3,r3,65535 + 803dc88: 10bfffcc andi r2,r2,65535 + 803dc8c: 1880061e bne r3,r2,803dca8 + { + usocket++; /* bump socket number */ + 803dc90: d0a09d0b ldhu r2,-32140(gp) + 803dc94: 10800044 addi r2,r2,1 + 803dc98: d0a09d0d sth r2,-32140(gp) + tmp = firstudp; /* restart scan */ + 803dc9c: d0a09e17 ldw r2,-32136(gp) + 803dca0: e0bfff15 stw r2,-4(fp) + continue; + 803dca4: 0001883a nop + for (tmp = firstudp; tmp; tmp = tmp->u_next) + 803dca8: e0bfff17 ldw r2,-4(fp) + 803dcac: 10800017 ldw r2,0(r2) + 803dcb0: e0bfff15 stw r2,-4(fp) + 803dcb4: e0bfff17 ldw r2,-4(fp) + 803dcb8: 103fef1e bne r2,zero,803dc78 + } + } + return usocket++; + 803dcbc: d0a09d0b ldhu r2,-32140(gp) + 803dcc0: 10c00044 addi r3,r2,1 + 803dcc4: d0e09d0d sth r3,-32140(gp) +} + 803dcc8: e037883a mov sp,fp + 803dccc: df000017 ldw fp,0(sp) + 803dcd0: dec00104 addi sp,sp,4 + 803dcd4: f800283a ret + +0803dcd8 : + * RETURNS: Returns buffer, or NULL in no buffer was available. + */ + +PACKET +udp_alloc(int datalen, int optlen) +{ + 803dcd8: defffa04 addi sp,sp,-24 + 803dcdc: dfc00515 stw ra,20(sp) + 803dce0: df000415 stw fp,16(sp) + 803dce4: df000404 addi fp,sp,16 + 803dce8: e13ffd15 stw r4,-12(fp) + 803dcec: e17ffc15 stw r5,-16(fp) + int len; + PACKET p; + + len = (datalen + sizeof(struct udp) + 1) & ~1; + 803dcf0: e0bffd17 ldw r2,-12(fp) + 803dcf4: 10800244 addi r2,r2,9 + 803dcf8: 1007883a mov r3,r2 + 803dcfc: 00bfff84 movi r2,-2 + 803dd00: 1884703a and r2,r3,r2 + 803dd04: e0bfff15 stw r2,-4(fp) + LOCK_NET_RESOURCE(FREEQ_RESID); + 803dd08: 01000084 movi r4,2 + 803dd0c: 8028f380 call 8028f38 + p = pk_alloc(len + UDPHDRSLEN + optlen); + 803dd10: e0bfff17 ldw r2,-4(fp) + 803dd14: 10c00904 addi r3,r2,36 + 803dd18: e0bffc17 ldw r2,-16(fp) + 803dd1c: 1885883a add r2,r3,r2 + 803dd20: 1009883a mov r4,r2 + 803dd24: 80284340 call 8028434 + 803dd28: e0bffe15 stw r2,-8(fp) + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803dd2c: 01000084 movi r4,2 + 803dd30: 8028ff40 call 8028ff4 + + if (p != (PACKET)NULL) + 803dd34: e0bffe17 ldw r2,-8(fp) + 803dd38: 10001026 beq r2,zero,803dd7c + { + /* set prot pointers past end of UDP header */ + len = sizeof(struct ip) + (optlen >> 2) + sizeof(struct udp); + 803dd3c: e0bffc17 ldw r2,-16(fp) + 803dd40: 1005d0ba srai r2,r2,2 + 803dd44: 10800704 addi r2,r2,28 + 803dd48: e0bfff15 stw r2,-4(fp) + p->nb_prot += len; + 803dd4c: e0bffe17 ldw r2,-8(fp) + 803dd50: 10c00317 ldw r3,12(r2) + 803dd54: e0bfff17 ldw r2,-4(fp) + 803dd58: 1887883a add r3,r3,r2 + 803dd5c: e0bffe17 ldw r2,-8(fp) + 803dd60: 10c00315 stw r3,12(r2) + p->nb_plen -= len; + 803dd64: e0bffe17 ldw r2,-8(fp) + 803dd68: 10c00417 ldw r3,16(r2) + 803dd6c: e0bfff17 ldw r2,-4(fp) + 803dd70: 1887c83a sub r3,r3,r2 + 803dd74: e0bffe17 ldw r2,-8(fp) + 803dd78: 10c00415 stw r3,16(r2) + } + + return (p); + 803dd7c: e0bffe17 ldw r2,-8(fp) +} + 803dd80: e037883a mov sp,fp + 803dd84: dfc00117 ldw ra,4(sp) + 803dd88: df000017 ldw fp,0(sp) + 803dd8c: dec00204 addi sp,sp,8 + 803dd90: f800283a ret + +0803dd94 : + * returned value, the allocation will fail + */ + +int +udp_maxalloc(void) +{ + 803dd94: deffff04 addi sp,sp,-4 + 803dd98: df000015 stw fp,0(sp) + 803dd9c: d839883a mov fp,sp + * created is ((2^16 - 1) - (size of IP and UDP headers)) */ + return (0xFFFF - (sizeof (struct ip) + sizeof (struct udp))); +#else + /* if heap buffers are not available, the largest size of a UDP datagram + * is constrained by what will fit inside a big buffer */ + return (bigbufsiz - UDPHDRSLEN); + 803dda0: d0a01917 ldw r2,-32668(gp) + 803dda4: 10bff704 addi r2,r2,-36 +#endif +} + 803dda8: e037883a mov sp,fp + 803ddac: df000017 ldw fp,0(sp) + 803ddb0: dec00104 addi sp,sp,4 + 803ddb4: f800283a ret + +0803ddb8 : + * RETURNS: void + */ + +void +udp_free(PACKET p) +{ + 803ddb8: defffd04 addi sp,sp,-12 + 803ddbc: dfc00215 stw ra,8(sp) + 803ddc0: df000115 stw fp,4(sp) + 803ddc4: df000104 addi fp,sp,4 + 803ddc8: e13fff15 stw r4,-4(fp) + LOCK_NET_RESOURCE(FREEQ_RESID); + 803ddcc: 01000084 movi r4,2 + 803ddd0: 8028f380 call 8028f38 + pk_free(p); + 803ddd4: e13fff17 ldw r4,-4(fp) + 803ddd8: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803dddc: 01000084 movi r4,2 + 803dde0: 8028ff40 call 8028ff4 +} + 803dde4: 0001883a nop + 803dde8: e037883a mov sp,fp + 803ddec: dfc00117 ldw ra,4(sp) + 803ddf0: df000017 ldw fp,0(sp) + 803ddf4: dec00204 addi sp,sp,8 + 803ddf8: f800283a ret + +0803ddfc : + * OUTPUT: This function returns IGMP_ERR if it is passed an "unknown" + * packet type. Otherwise, it returns IGMP_OK. + */ + +int igmpv1_input(PACKET p) +{ + 803ddfc: defff804 addi sp,sp,-32 + 803de00: dfc00715 stw ra,28(sp) + 803de04: df000615 stw fp,24(sp) + 803de08: df000604 addi fp,sp,24 + 803de0c: e13ffa15 stw r4,-24(fp) + struct igmp * igmp; + struct ip * pip; + struct in_multi * inm; + NET netp = p->net; + 803de10: e0bffa17 ldw r2,-24(fp) + 803de14: 10800617 ldw r2,24(r2) + 803de18: e0bffd15 stw r2,-12(fp) + int rc; + + pip = ip_head (p); + 803de1c: e0bffa17 ldw r2,-24(fp) + 803de20: 10800317 ldw r2,12(r2) + 803de24: e0bffc15 stw r2,-16(fp) + igmp = (struct igmp *) (ip_data (pip)); + 803de28: e0bffc17 ldw r2,-16(fp) + 803de2c: 10800003 ldbu r2,0(r2) + 803de30: 10803fcc andi r2,r2,255 + 803de34: 100490ba slli r2,r2,2 + 803de38: 10800f0c andi r2,r2,60 + 803de3c: e0fffc17 ldw r3,-16(fp) + 803de40: 1885883a add r2,r3,r2 + 803de44: e0bffb15 stw r2,-20(fp) + + switch (igmp->igmp_type) + 803de48: e0bffb17 ldw r2,-20(fp) + 803de4c: 10800003 ldbu r2,0(r2) + 803de50: 10803fcc andi r2,r2,255 + 803de54: 10c00460 cmpeqi r3,r2,17 + 803de58: 1800031e bne r3,zero,803de68 + 803de5c: 108004a0 cmpeqi r2,r2,18 + 803de60: 1000501e bne r2,zero,803dfa4 + 803de64: 00006b06 br 803e014 + { + case IGMP_HOST_MEMBERSHIP_QUERY: + ++igmpstats.igmpv1mode_v1_queries_rcvd; + 803de68: 008201b4 movhi r2,2054 + 803de6c: 10b77517 ldw r2,-8748(r2) + 803de70: 10c00044 addi r3,r2,1 + 803de74: 008201b4 movhi r2,2054 + 803de78: 10f77515 stw r3,-8748(r2) + * Start the timers in all of our membership records for + * the interface on which the query arrived, except those + * that are already running and those that belong to the + * "all-hosts" group. + */ + for (inm = netp->mc_list; inm; inm = inm->inm_next) + 803de7c: e0bffd17 ldw r2,-12(fp) + 803de80: 10802c17 ldw r2,176(r2) + 803de84: e0bfff15 stw r2,-4(fp) + 803de88: 00004206 br 803df94 + { + /* skip all IPv6 entries - they are indicated by + * an IPv4 address field of 0 */ + if (inm->inm_addr == 0) + 803de8c: e0bfff17 ldw r2,-4(fp) + 803de90: 10800017 ldw r2,0(r2) + 803de94: 10003b26 beq r2,zero,803df84 + continue; + /* skip IPv4 multicast address of 224.0.0.1 (note that + * the IPv4 address stored in inm_addr is in network + * byte order */ + if (inm->inm_addr != igmp_all_hosts_group) + 803de98: e0bfff17 ldw r2,-4(fp) + 803de9c: 10c00017 ldw r3,0(r2) + 803dea0: d0a06b17 ldw r2,-32340(gp) + 803dea4: 18803826 beq r3,r2,803df88 + { + if (inm->inm_timer == 0) + 803dea8: e0bfff17 ldw r2,-4(fp) + 803deac: 10800317 ldw r2,12(r2) + 803deb0: 1000351e bne r2,zero,803df88 + { + inm->inm_timer = (unsigned) IGMP_RANDOM_DELAY(inm->inm_addr); + 803deb4: 008201b4 movhi r2,2054 + 803deb8: 10f95117 ldw r3,-6844(r2) + 803debc: 008201b4 movhi r2,2054 + 803dec0: 10b77017 ldw r2,-8768(r2) + 803dec4: 10800a17 ldw r2,40(r2) + 803dec8: 1008d63a srli r4,r2,24 + 803decc: 008201b4 movhi r2,2054 + 803ded0: 10b77017 ldw r2,-8768(r2) + 803ded4: 10800a17 ldw r2,40(r2) + 803ded8: 1004d23a srli r2,r2,8 + 803dedc: 10bfc00c andi r2,r2,65280 + 803dee0: 2088b03a or r4,r4,r2 + 803dee4: 008201b4 movhi r2,2054 + 803dee8: 10b77017 ldw r2,-8768(r2) + 803deec: 10800a17 ldw r2,40(r2) + 803def0: 1004923a slli r2,r2,8 + 803def4: 10803fec andhi r2,r2,255 + 803def8: 2088b03a or r4,r4,r2 + 803defc: 008201b4 movhi r2,2054 + 803df00: 10b77017 ldw r2,-8768(r2) + 803df04: 10800a17 ldw r2,40(r2) + 803df08: 1004963a slli r2,r2,24 + 803df0c: 2084b03a or r2,r4,r2 + 803df10: 1887883a add r3,r3,r2 + 803df14: e0bfff17 ldw r2,-4(fp) + 803df18: 10800017 ldw r2,0(r2) + 803df1c: 1008d63a srli r4,r2,24 + 803df20: e0bfff17 ldw r2,-4(fp) + 803df24: 10800017 ldw r2,0(r2) + 803df28: 1004d23a srli r2,r2,8 + 803df2c: 10bfc00c andi r2,r2,65280 + 803df30: 2088b03a or r4,r4,r2 + 803df34: e0bfff17 ldw r2,-4(fp) + 803df38: 10800017 ldw r2,0(r2) + 803df3c: 1004923a slli r2,r2,8 + 803df40: 10803fec andhi r2,r2,255 + 803df44: 2088b03a or r4,r4,r2 + 803df48: e0bfff17 ldw r2,-4(fp) + 803df4c: 10800017 ldw r2,0(r2) + 803df50: 1004963a slli r2,r2,24 + 803df54: 2084b03a or r2,r4,r2 + 803df58: 1885883a add r2,r3,r2 + 803df5c: 01400c84 movi r5,50 + 803df60: 1009883a mov r4,r2 + 803df64: 800d05c0 call 800d05c <__umodsi3> + 803df68: 10c00044 addi r3,r2,1 + 803df6c: e0bfff17 ldw r2,-4(fp) + 803df70: 10c00315 stw r3,12(r2) + /* increment the count of running timers */ + ++igmp_timers_are_running; + 803df74: d0a06917 ldw r2,-32348(gp) + 803df78: 10800044 addi r2,r2,1 + 803df7c: d0a06915 stw r2,-32348(gp) + 803df80: 00000106 br 803df88 + continue; + 803df84: 0001883a nop + for (inm = netp->mc_list; inm; inm = inm->inm_next) + 803df88: e0bfff17 ldw r2,-4(fp) + 803df8c: 10800517 ldw r2,20(r2) + 803df90: e0bfff15 stw r2,-4(fp) + 803df94: e0bfff17 ldw r2,-4(fp) + 803df98: 103fbc1e bne r2,zero,803de8c + } + } + } + rc = IGMP_OK; + 803df9c: e03ffe15 stw zero,-8(fp) + break; + 803dfa0: 00002406 br 803e034 + + case IGMP_HOST_MEMBERSHIP_REPORT: + ++igmpstats.igmpv1mode_v1_reports_rcvd; + 803dfa4: 008201b4 movhi r2,2054 + 803dfa8: 10b77617 ldw r2,-8744(r2) + 803dfac: 10c00044 addi r3,r2,1 + 803dfb0: 008201b4 movhi r2,2054 + 803dfb4: 10f77615 stw r3,-8744(r2) + /* + * If we belong to the group being reported and have a + * running timer for that group, stop our timer for that + * group. + */ + inm = lookup_mcast(igmp->igmp_group, netp); + 803dfb8: e0bffb17 ldw r2,-20(fp) + 803dfbc: 10800117 ldw r2,4(r2) + 803dfc0: e17ffd17 ldw r5,-12(fp) + 803dfc4: 1009883a mov r4,r2 + 803dfc8: 803c5040 call 803c504 + 803dfcc: e0bfff15 stw r2,-4(fp) + if (inm != NULL) + 803dfd0: e0bfff17 ldw r2,-4(fp) + 803dfd4: 10000d26 beq r2,zero,803e00c + { + if (inm->inm_timer > 0) + 803dfd8: e0bfff17 ldw r2,-4(fp) + 803dfdc: 10800317 ldw r2,12(r2) + 803dfe0: 10000a26 beq r2,zero,803e00c + { + inm->inm_timer = 0; + 803dfe4: e0bfff17 ldw r2,-4(fp) + 803dfe8: 10000315 stw zero,12(r2) + /* decrement the count of running timers */ + --igmp_timers_are_running; + 803dfec: d0a06917 ldw r2,-32348(gp) + 803dff0: 10bfffc4 addi r2,r2,-1 + 803dff4: d0a06915 stw r2,-32348(gp) + ++igmpstats.igmpv1mode_v1_reports_rcvd_canceled_timer; + 803dff8: 008201b4 movhi r2,2054 + 803dffc: 10b77717 ldw r2,-8740(r2) + 803e000: 10c00044 addi r3,r2,1 + 803e004: 008201b4 movhi r2,2054 + 803e008: 10f77715 stw r3,-8740(r2) + } + } + rc = IGMP_OK; + 803e00c: e03ffe15 stw zero,-8(fp) + break; + 803e010: 00000806 br 803e034 + + default: + ++igmpstats.igmpv1mode_unknown_pkttype; + 803e014: 008201b4 movhi r2,2054 + 803e018: 10b78417 ldw r2,-8688(r2) + 803e01c: 10c00044 addi r3,r2,1 + 803e020: 008201b4 movhi r2,2054 + 803e024: 10f78415 stw r3,-8688(r2) + rc = IGMP_ERR; + 803e028: 00bfffc4 movi r2,-1 + 803e02c: e0bffe15 stw r2,-8(fp) + break; + 803e030: 0001883a nop + } + + /* we're done with the received packet; return packet buffer back + * to free pool */ + LOCK_NET_RESOURCE(FREEQ_RESID); + 803e034: 01000084 movi r4,2 + 803e038: 8028f380 call 8028f38 + pk_free(p); + 803e03c: e13ffa17 ldw r4,-24(fp) + 803e040: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803e044: 01000084 movi r4,2 + 803e048: 8028ff40 call 8028ff4 + + return rc; + 803e04c: e0bffe17 ldw r2,-8(fp) +} + 803e050: e037883a mov sp,fp + 803e054: dfc00117 ldw ra,4(sp) + 803e058: df000017 ldw fp,0(sp) + 803e05c: dec00204 addi sp,sp,8 + 803e060: f800283a ret + +0803e064 : + * from igmpv2_process_report (), IGMP_OK (for a received Leave Group + * message only), or IGMP_ERR (for a message of an "unknown" type). + */ + +int igmpv2_input (PACKET p) +{ + 803e064: defff904 addi sp,sp,-28 + 803e068: dfc00615 stw ra,24(sp) + 803e06c: df000515 stw fp,20(sp) + 803e070: df000504 addi fp,sp,20 + 803e074: e13ffb15 stw r4,-20(fp) + struct igmp * igmp; + struct ip * pip; + u_char type; + int rc; + + pip = ip_head (p); + 803e078: e0bffb17 ldw r2,-20(fp) + 803e07c: 10800317 ldw r2,12(r2) + 803e080: e0bffe15 stw r2,-8(fp) + igmp = (struct igmp *) (ip_data (pip)); + 803e084: e0bffe17 ldw r2,-8(fp) + 803e088: 10800003 ldbu r2,0(r2) + 803e08c: 10803fcc andi r2,r2,255 + 803e090: 100490ba slli r2,r2,2 + 803e094: 10800f0c andi r2,r2,60 + 803e098: e0fffe17 ldw r3,-8(fp) + 803e09c: 1885883a add r2,r3,r2 + 803e0a0: e0bffd15 stw r2,-12(fp) + /* extract the IGMP packet type from received packet */ + type = igmp->igmp_type; + 803e0a4: e0bffd17 ldw r2,-12(fp) + 803e0a8: 10800003 ldbu r2,0(r2) + 803e0ac: e0bffcc5 stb r2,-13(fp) + + switch (type) + 803e0b0: e0bffcc3 ldbu r2,-13(fp) + 803e0b4: 10c004a0 cmpeqi r3,r2,18 + 803e0b8: 18000e1e bne r3,zero,803e0f4 + 803e0bc: 10c004c8 cmpgei r3,r2,19 + 803e0c0: 1800031e bne r3,zero,803e0d0 + 803e0c4: 10800460 cmpeqi r2,r2,17 + 803e0c8: 1000061e bne r2,zero,803e0e4 + 803e0cc: 00001406 br 803e120 + 803e0d0: 10c005a0 cmpeqi r3,r2,22 + 803e0d4: 1800071e bne r3,zero,803e0f4 + 803e0d8: 108005e0 cmpeqi r2,r2,23 + 803e0dc: 1000091e bne r2,zero,803e104 + 803e0e0: 00000f06 br 803e120 + { + case IGMP_HOST_MEMBERSHIP_QUERY: + rc = igmpv2_process_query (p); + 803e0e4: e13ffb17 ldw r4,-20(fp) + 803e0e8: 803e2840 call 803e284 + 803e0ec: e0bfff15 stw r2,-4(fp) + break; + 803e0f0: 00001306 br 803e140 + + case IGMP_HOST_MEMBERSHIP_REPORT: + case IGMPv2_MEMBERSHIP_REPORT: + rc = igmpv2_process_report (p); + 803e0f4: e13ffb17 ldw r4,-20(fp) + 803e0f8: 803e1700 call 803e170 + 803e0fc: e0bfff15 stw r2,-4(fp) + break; + 803e100: 00000f06 br 803e140 + * expect to receive such messages. However, according to + * RFC 2236, some implementations of an older version of the + * IGMPv2 specification send leave messages to the group + * being left. If we do receive such a message, we will + * drop it. */ + ++igmpstats.igmpv2mode_v2_leave_msgs_rcvd; + 803e104: 008201b4 movhi r2,2054 + 803e108: 10b77d17 ldw r2,-8716(r2) + 803e10c: 10c00044 addi r3,r2,1 + 803e110: 008201b4 movhi r2,2054 + 803e114: 10f77d15 stw r3,-8716(r2) + rc = IGMP_OK; + 803e118: e03fff15 stw zero,-4(fp) + break; + 803e11c: 00000806 br 803e140 + + default: + ++igmpstats.igmpv2mode_unknown_pkttype; + 803e120: 008201b4 movhi r2,2054 + 803e124: 10b78917 ldw r2,-8668(r2) + 803e128: 10c00044 addi r3,r2,1 + 803e12c: 008201b4 movhi r2,2054 + 803e130: 10f78915 stw r3,-8668(r2) + rc = IGMP_ERR; + 803e134: 00bfffc4 movi r2,-1 + 803e138: e0bfff15 stw r2,-4(fp) + break; + 803e13c: 0001883a nop + } /* end SWITCH */ + + /* we're done processing the received packet; return packet buffer + * back to free pool */ + LOCK_NET_RESOURCE(FREEQ_RESID); + 803e140: 01000084 movi r4,2 + 803e144: 8028f380 call 8028f38 + pk_free(p); + 803e148: e13ffb17 ldw r4,-20(fp) + 803e14c: 80287480 call 8028748 + UNLOCK_NET_RESOURCE(FREEQ_RESID); + 803e150: 01000084 movi r4,2 + 803e154: 8028ff40 call 8028ff4 + + return rc; + 803e158: e0bfff17 ldw r2,-4(fp) +} + 803e15c: e037883a mov sp,fp + 803e160: dfc00117 ldw ra,4(sp) + 803e164: df000017 ldw fp,0(sp) + 803e168: dec00204 addi sp,sp,8 + 803e16c: f800283a ret + +0803e170 : + * + * OUTPUT: This function always returns IGMP_OK. + */ + +int igmpv2_process_report (PACKET p) +{ + 803e170: defff904 addi sp,sp,-28 + 803e174: dfc00615 stw ra,24(sp) + 803e178: df000515 stw fp,20(sp) + 803e17c: df000504 addi fp,sp,20 + 803e180: e13ffb15 stw r4,-20(fp) + struct igmp * igmp; + struct ip * pip; + NET netp; + struct in_multi * inm; + + netp = p->net; + 803e184: e0bffb17 ldw r2,-20(fp) + 803e188: 10800617 ldw r2,24(r2) + 803e18c: e0bfff15 stw r2,-4(fp) + pip = ip_head (p); + 803e190: e0bffb17 ldw r2,-20(fp) + 803e194: 10800317 ldw r2,12(r2) + 803e198: e0bffe15 stw r2,-8(fp) + igmp = (struct igmp *) (ip_data (pip)); + 803e19c: e0bffe17 ldw r2,-8(fp) + 803e1a0: 10800003 ldbu r2,0(r2) + 803e1a4: 10803fcc andi r2,r2,255 + 803e1a8: 100490ba slli r2,r2,2 + 803e1ac: 10800f0c andi r2,r2,60 + 803e1b0: e0fffe17 ldw r3,-8(fp) + 803e1b4: 1885883a add r2,r3,r2 + 803e1b8: e0bffd15 stw r2,-12(fp) + * processing IGMPv2 packets (it has "downgraded" itself because + * there are IGMPv1 routers on that network); however, we do not + * know that, and hence we don't cancel our timer (for the + * subsequent transmission of a IGMPv1 report). + */ + inm = lookup_mcast(igmp->igmp_group, netp); + 803e1bc: e0bffd17 ldw r2,-12(fp) + 803e1c0: 10800117 ldw r2,4(r2) + 803e1c4: e17fff17 ldw r5,-4(fp) + 803e1c8: 1009883a mov r4,r2 + 803e1cc: 803c5040 call 803c504 + 803e1d0: e0bffc15 stw r2,-16(fp) + if (inm != NULL) + 803e1d4: e0bffc17 ldw r2,-16(fp) + 803e1d8: 10001f26 beq r2,zero,803e258 + { + if (inm->inm_timer != 0) + 803e1dc: e0bffc17 ldw r2,-16(fp) + 803e1e0: 10800317 ldw r2,12(r2) + 803e1e4: 10001626 beq r2,zero,803e240 + { + /* we have a timer running */ + if (!(netp->igmpv1_rtr_present && + 803e1e8: e0bfff17 ldw r2,-4(fp) + 803e1ec: 10802d03 ldbu r2,180(r2) + 803e1f0: 10803fcc andi r2,r2,255 + 803e1f4: 10000526 beq r2,zero,803e20c + igmp->igmp_type == IGMPv2_MEMBERSHIP_REPORT)) + 803e1f8: e0bffd17 ldw r2,-12(fp) + 803e1fc: 10800003 ldbu r2,0(r2) + if (!(netp->igmpv1_rtr_present && + 803e200: 10803fcc andi r2,r2,255 + 803e204: 108005a0 cmpeqi r2,r2,22 + 803e208: 1000181e bne r2,zero,803e26c + { + /* cancel timer */ + inm->inm_timer = 0; + 803e20c: e0bffc17 ldw r2,-16(fp) + 803e210: 10000315 stw zero,12(r2) + /* decrement the count of running timers */ + --igmp_timers_are_running; + 803e214: d0a06917 ldw r2,-32348(gp) + 803e218: 10bfffc4 addi r2,r2,-1 + 803e21c: d0a06915 stw r2,-32348(gp) + /* indicate that we are not the last host to send a + * report for this group */ + inm->last2send_report = IGMP_FALSE; + 803e220: e0bffc17 ldw r2,-16(fp) + 803e224: 10000405 stb zero,16(r2) + ++igmpstats.igmpv2mode_v12_reports_rcvd_canceled_timer; + 803e228: 008201b4 movhi r2,2054 + 803e22c: 10b77b17 ldw r2,-8724(r2) + 803e230: 10c00044 addi r3,r2,1 + 803e234: 008201b4 movhi r2,2054 + 803e238: 10f77b15 stw r3,-8724(r2) + 803e23c: 00000b06 br 803e26c + else + { + /* we don't have a timer running; perhaps the source + * host has just joined the group, and has sent an + * unsolicited report */ + ++igmpstats.igmpv2mode_v12_reports_rcvd_no_timer; + 803e240: 008201b4 movhi r2,2054 + 803e244: 10b77c17 ldw r2,-8720(r2) + 803e248: 10c00044 addi r3,r2,1 + 803e24c: 008201b4 movhi r2,2054 + 803e250: 10f77c15 stw r3,-8720(r2) + 803e254: 00000506 br 803e26c + * on that interface. Even if imperfect filtering at the + * device level causes reports for unregistered groups to + * be passed up to the IP module, ip_rcv_phase2 () is + * responsible for dropping them, and so we should never + * receive such packets. */ + ++igmpstats.igmpv2mode_v12_unknown_grp_reports_rcvd; + 803e258: 008201b4 movhi r2,2054 + 803e25c: 10b78717 ldw r2,-8676(r2) + 803e260: 10c00044 addi r3,r2,1 + 803e264: 008201b4 movhi r2,2054 + 803e268: 10f78715 stw r3,-8676(r2) + } + + return IGMP_OK; + 803e26c: 0005883a mov r2,zero +} + 803e270: e037883a mov sp,fp + 803e274: dfc00117 ldw ra,4(sp) + 803e278: df000017 ldw fp,0(sp) + 803e27c: dec00204 addi sp,sp,8 + 803e280: f800283a ret + +0803e284 : + * + * OUTPUT: This function always returns IGMP_OK. + */ + +int igmpv2_process_query (PACKET p) +{ + 803e284: defff804 addi sp,sp,-32 + 803e288: dfc00715 stw ra,28(sp) + 803e28c: df000615 stw fp,24(sp) + 803e290: df000604 addi fp,sp,24 + 803e294: e13ffa15 stw r4,-24(fp) + NET netp; + u_short max_resp_time; + u_char process_all; + struct in_multi * inm; + + netp = p->net; + 803e298: e0bffa17 ldw r2,-24(fp) + 803e29c: 10800617 ldw r2,24(r2) + 803e2a0: e0bffd15 stw r2,-12(fp) + pip = ip_head (p); + 803e2a4: e0bffa17 ldw r2,-24(fp) + 803e2a8: 10800317 ldw r2,12(r2) + 803e2ac: e0bffc15 stw r2,-16(fp) + igmp = (struct igmp *) (ip_data (pip)); + 803e2b0: e0bffc17 ldw r2,-16(fp) + 803e2b4: 10800003 ldbu r2,0(r2) + 803e2b8: 10803fcc andi r2,r2,255 + 803e2bc: 100490ba slli r2,r2,2 + 803e2c0: 10800f0c andi r2,r2,60 + 803e2c4: e0fffc17 ldw r3,-16(fp) + 803e2c8: 1885883a add r2,r3,r2 + 803e2cc: e0bffb15 stw r2,-20(fp) + + if (igmp->igmp_code == 0) + 803e2d0: e0bffb17 ldw r2,-20(fp) + 803e2d4: 10800043 ldbu r2,1(r2) + 803e2d8: 10803fcc andi r2,r2,255 + 803e2dc: 1000101e bne r2,zero,803e320 + { + /* this is a IGMPv1 Host Membership Query */ + netp->igmpv1_rtr_present = IGMP_TRUE; + 803e2e0: e0bffd17 ldw r2,-12(fp) + 803e2e4: 00c00044 movi r3,1 + 803e2e8: 10c02d05 stb r3,180(r2) + netp->igmpv1_query_rcvd_time = cticks; + 803e2ec: d0e07d17 ldw r3,-32268(gp) + 803e2f0: e0bffd17 ldw r2,-12(fp) + 803e2f4: 10c02e15 stw r3,184(r2) + ++igmpstats.igmpv2mode_v1_queries_rcvd; + 803e2f8: 008201b4 movhi r2,2054 + 803e2fc: 10b77817 ldw r2,-8736(r2) + 803e300: 10c00044 addi r3,r2,1 + 803e304: 008201b4 movhi r2,2054 + 803e308: 10f77815 stw r3,-8736(r2) + /* set maximum time to respond to the equivalent of 10 + * seconds worth of "ticks" (the timeout routine is + * intended to be invoked PR_FASTHZ (5) times a second, + * so each tick is equal to 200 ms) */ + max_resp_time = IGMP_MAX_HOST_REPORT_DELAY * PR_FASTHZ; + 803e30c: 00800c84 movi r2,50 + 803e310: e0bfff8d sth r2,-2(fp) + process_all = IGMP_TRUE; + 803e314: 00800044 movi r2,1 + 803e318: e0bfff45 stb r2,-3(fp) + 803e31c: 00001806 br 803e380 + } + else + { + /* this is either a IGMPv2 General Query or + * a IGMPv2 Group-Specific Query */ + if (igmp->igmp_group == 0) + 803e320: e0bffb17 ldw r2,-20(fp) + 803e324: 10800117 ldw r2,4(r2) + 803e328: 1000081e bne r2,zero,803e34c + { + /* this is a IGMPv2 General Query */ + ++igmpstats.igmpv2mode_v2_general_queries_rcvd; + 803e32c: 008201b4 movhi r2,2054 + 803e330: 10b77917 ldw r2,-8732(r2) + 803e334: 10c00044 addi r3,r2,1 + 803e338: 008201b4 movhi r2,2054 + 803e33c: 10f77915 stw r3,-8732(r2) + process_all = IGMP_TRUE; + 803e340: 00800044 movi r2,1 + 803e344: e0bfff45 stb r2,-3(fp) + 803e348: 00000606 br 803e364 + } + else + { + /* this is a IGMPv2 Group-Specific Query */ + ++igmpstats.igmpv2mode_v2_grp_specific_queries_rcvd; + 803e34c: 008201b4 movhi r2,2054 + 803e350: 10b77a17 ldw r2,-8728(r2) + 803e354: 10c00044 addi r3,r2,1 + 803e358: 008201b4 movhi r2,2054 + 803e35c: 10f77a15 stw r3,-8728(r2) + process_all = IGMP_FALSE; + 803e360: e03fff45 stb zero,-3(fp) + * IGMPv2 General Query or a IGMPv2 Group-Specific Query, + * set maximum time to respond to value extracted + * from received message. The value in the message + * is in tenths of a second. max_resp_time is in + * units of ticks (where one tick is 200 ms) */ + max_resp_time = (igmp->igmp_code * PR_FASTHZ) / 10; + 803e364: e0bffb17 ldw r2,-20(fp) + 803e368: 10800043 ldbu r2,1(r2) + 803e36c: 10803fcc andi r2,r2,255 + 803e370: 1006d7fa srli r3,r2,31 + 803e374: 1885883a add r2,r3,r2 + 803e378: 1005d07a srai r2,r2,1 + 803e37c: e0bfff8d sth r2,-2(fp) + + /* process all entries in a link's multicast address linked + * list (pointed to by mc_list) as part of the response to + * the received IGMPv1 Host Membership Query or IGMPv2 General + * Query message */ + if (process_all) + 803e380: e0bfff43 ldbu r2,-3(fp) + 803e384: 10001726 beq r2,zero,803e3e4 + { + for (inm = netp->mc_list; inm; inm = inm->inm_next) + 803e388: e0bffd17 ldw r2,-12(fp) + 803e38c: 10802c17 ldw r2,176(r2) + 803e390: e0bffe15 stw r2,-8(fp) + 803e394: 00001006 br 803e3d8 + { + /* skip all IPv6 entries - they are indicated by + * an IPv4 address field of 0 */ + if (!(inm->inm_addr)) continue; + 803e398: e0bffe17 ldw r2,-8(fp) + 803e39c: 10800017 ldw r2,0(r2) + 803e3a0: 10000926 beq r2,zero,803e3c8 + /* skip IPv4 multicast address of 224.0.0.1 (note that + * the IPv4 address stored in inm_addr is in network + * byte order */ + if (inm->inm_addr != igmp_all_hosts_group) + 803e3a4: e0bffe17 ldw r2,-8(fp) + 803e3a8: 10c00017 ldw r3,0(r2) + 803e3ac: d0a06b17 ldw r2,-32340(gp) + 803e3b0: 18800626 beq r3,r2,803e3cc + igmpv2_chk_set_timer (inm, max_resp_time); + 803e3b4: e0bfff8b ldhu r2,-2(fp) + 803e3b8: 100b883a mov r5,r2 + 803e3bc: e13ffe17 ldw r4,-8(fp) + 803e3c0: 803e4440 call 803e444 + 803e3c4: 00000106 br 803e3cc + if (!(inm->inm_addr)) continue; + 803e3c8: 0001883a nop + for (inm = netp->mc_list; inm; inm = inm->inm_next) + 803e3cc: e0bffe17 ldw r2,-8(fp) + 803e3d0: 10800517 ldw r2,20(r2) + 803e3d4: e0bffe15 stw r2,-8(fp) + 803e3d8: e0bffe17 ldw r2,-8(fp) + 803e3dc: 103fee1e bne r2,zero,803e398 + 803e3e0: 00001206 br 803e42c + { + /* process one (for IGMPv2 Group-Specific Query) entry (the + * one that corresponds to the address listed in the received + * query) - it should be present in the link's multicast + * address list */ + inm = lookup_mcast(igmp->igmp_group, netp); + 803e3e4: e0bffb17 ldw r2,-20(fp) + 803e3e8: 10800117 ldw r2,4(r2) + 803e3ec: e17ffd17 ldw r5,-12(fp) + 803e3f0: 1009883a mov r4,r2 + 803e3f4: 803c5040 call 803c504 + 803e3f8: e0bffe15 stw r2,-8(fp) + if (inm != NULL) + 803e3fc: e0bffe17 ldw r2,-8(fp) + 803e400: 10000526 beq r2,zero,803e418 + igmpv2_chk_set_timer (inm, max_resp_time); + 803e404: e0bfff8b ldhu r2,-2(fp) + 803e408: 100b883a mov r5,r2 + 803e40c: e13ffe17 ldw r4,-8(fp) + 803e410: 803e4440 call 803e444 + 803e414: 00000506 br 803e42c + else ++igmpstats.igmpv2mode_v2_unknown_grp_specific_queries_rcvd; + 803e418: 008201b4 movhi r2,2054 + 803e41c: 10b78617 ldw r2,-8680(r2) + 803e420: 10c00044 addi r3,r2,1 + 803e424: 008201b4 movhi r2,2054 + 803e428: 10f78615 stw r3,-8680(r2) + } /* end ELSE (process ALL) */ + + /* return success; caller will the received packet back to the + * free pool */ + return IGMP_OK; + 803e42c: 0005883a mov r2,zero +} + 803e430: e037883a mov sp,fp + 803e434: dfc00117 ldw ra,4(sp) + 803e438: df000017 ldw fp,0(sp) + 803e43c: dec00204 addi sp,sp,8 + 803e440: f800283a ret + +0803e444 : + * + * OUTPUT: None. + */ + +void igmpv2_chk_set_timer (struct in_multi * inm, u_short max_resp_time) +{ + 803e444: defffc04 addi sp,sp,-16 + 803e448: dfc00315 stw ra,12(sp) + 803e44c: df000215 stw fp,8(sp) + 803e450: df000204 addi fp,sp,8 + 803e454: e13fff15 stw r4,-4(fp) + 803e458: 2805883a mov r2,r5 + 803e45c: e0bffe0d sth r2,-8(fp) + + * Otherwise, the current timer for this group is scheduled + * to expire within the duration indicated in the Query + * message, so we let it continue. + */ + if ((inm->inm_timer > max_resp_time) || + 803e460: e0bfff17 ldw r2,-4(fp) + 803e464: 10800317 ldw r2,12(r2) + 803e468: e0fffe0b ldhu r3,-8(fp) + 803e46c: 18800336 bltu r3,r2,803e47c + (inm->inm_timer == 0)) + 803e470: e0bfff17 ldw r2,-4(fp) + 803e474: 10800317 ldw r2,12(r2) + if ((inm->inm_timer > max_resp_time) || + 803e478: 1000381e bne r2,zero,803e55c + { + if (inm->inm_timer == 0) ++igmp_timers_are_running; + 803e47c: e0bfff17 ldw r2,-4(fp) + 803e480: 10800317 ldw r2,12(r2) + 803e484: 1000031e bne r2,zero,803e494 + 803e488: d0a06917 ldw r2,-32348(gp) + 803e48c: 10800044 addi r2,r2,1 + 803e490: d0a06915 stw r2,-32348(gp) + inm->inm_timer = (unsigned) IGMPv2_RANDOM_DELAY (max_resp_time, inm->inm_addr); + 803e494: 008201b4 movhi r2,2054 + 803e498: 10f95117 ldw r3,-6844(r2) + 803e49c: 008201b4 movhi r2,2054 + 803e4a0: 10b77017 ldw r2,-8768(r2) + 803e4a4: 10800a17 ldw r2,40(r2) + 803e4a8: 1008d63a srli r4,r2,24 + 803e4ac: 008201b4 movhi r2,2054 + 803e4b0: 10b77017 ldw r2,-8768(r2) + 803e4b4: 10800a17 ldw r2,40(r2) + 803e4b8: 1004d23a srli r2,r2,8 + 803e4bc: 10bfc00c andi r2,r2,65280 + 803e4c0: 2088b03a or r4,r4,r2 + 803e4c4: 008201b4 movhi r2,2054 + 803e4c8: 10b77017 ldw r2,-8768(r2) + 803e4cc: 10800a17 ldw r2,40(r2) + 803e4d0: 1004923a slli r2,r2,8 + 803e4d4: 10803fec andhi r2,r2,255 + 803e4d8: 2088b03a or r4,r4,r2 + 803e4dc: 008201b4 movhi r2,2054 + 803e4e0: 10b77017 ldw r2,-8768(r2) + 803e4e4: 10800a17 ldw r2,40(r2) + 803e4e8: 1004963a slli r2,r2,24 + 803e4ec: 2084b03a or r2,r4,r2 + 803e4f0: 1887883a add r3,r3,r2 + 803e4f4: e0bfff17 ldw r2,-4(fp) + 803e4f8: 10800017 ldw r2,0(r2) + 803e4fc: 1008d63a srli r4,r2,24 + 803e500: e0bfff17 ldw r2,-4(fp) + 803e504: 10800017 ldw r2,0(r2) + 803e508: 1004d23a srli r2,r2,8 + 803e50c: 10bfc00c andi r2,r2,65280 + 803e510: 2088b03a or r4,r4,r2 + 803e514: e0bfff17 ldw r2,-4(fp) + 803e518: 10800017 ldw r2,0(r2) + 803e51c: 1004923a slli r2,r2,8 + 803e520: 10803fec andhi r2,r2,255 + 803e524: 2088b03a or r4,r4,r2 + 803e528: e0bfff17 ldw r2,-4(fp) + 803e52c: 10800017 ldw r2,0(r2) + 803e530: 1004963a slli r2,r2,24 + 803e534: 2084b03a or r2,r4,r2 + 803e538: 1885883a add r2,r3,r2 + 803e53c: e0fffe0b ldhu r3,-8(fp) + 803e540: 180b883a mov r5,r3 + 803e544: 1009883a mov r4,r2 + 803e548: 800d05c0 call 800d05c <__umodsi3> + 803e54c: 10c00044 addi r3,r2,1 + 803e550: e0bfff17 ldw r2,-4(fp) + 803e554: 10c00315 stw r3,12(r2) + } + + return; + 803e558: 0001883a nop + 803e55c: 0001883a nop +} + 803e560: e037883a mov sp,fp + 803e564: dfc00117 ldw ra,4(sp) + 803e568: df000017 ldw fp,0(sp) + 803e56c: dec00204 addi sp,sp,8 + 803e570: f800283a ret + +0803e574 : + * the IP Router Alert option in the received + * packet, and IGMP_FALSE otherwise. + */ + +u_char igmpv2_chk4_rtr_alert_opt (struct ip * pip) +{ + 803e574: defffb04 addi sp,sp,-20 + 803e578: df000415 stw fp,16(sp) + 803e57c: df000404 addi fp,sp,16 + 803e580: e13ffc15 stw r4,-16(fp) + u_long * rtr_alert_optp; + u_char total_optlen; + u_char optlen; + u_char optval; + + total_optlen = ip_hlen (pip) - sizeof (struct ip); + 803e584: e0bffc17 ldw r2,-16(fp) + 803e588: 10800003 ldbu r2,0(r2) + 803e58c: 100490ba slli r2,r2,2 + 803e590: 10800f0c andi r2,r2,60 + 803e594: 10bffb04 addi r2,r2,-20 + 803e598: e0bffec5 stb r2,-5(fp) + + if (total_optlen > 0) + 803e59c: e0bffec3 ldbu r2,-5(fp) + 803e5a0: 10003e26 beq r2,zero,803e69c + { + /* point to just past the end of the IP header */ + optp = (u_char *) (pip + 1); + 803e5a4: e0bffc17 ldw r2,-16(fp) + 803e5a8: 10800504 addi r2,r2,20 + 803e5ac: e0bfff15 stw r2,-4(fp) + + while (total_optlen > 0) + 803e5b0: 00003806 br 803e694 + { + /* only the lowermost 5 bits are significant */ + optval = (*optp) & IPOPT_TYPE_MASK; + 803e5b4: e0bfff17 ldw r2,-4(fp) + 803e5b8: 10800003 ldbu r2,0(r2) + 803e5bc: 108007cc andi r2,r2,31 + 803e5c0: e0bffe45 stb r2,-7(fp) + switch (optval) + 803e5c4: e0bffe43 ldbu r2,-7(fp) + 803e5c8: 10c00060 cmpeqi r3,r2,1 + 803e5cc: 1800071e bne r3,zero,803e5ec + 803e5d0: 10c00520 cmpeqi r3,r2,20 + 803e5d4: 1800081e bne r3,zero,803e5f8 + 803e5d8: 1000201e bne r2,zero,803e65c + { + case EOL_OPT: + /* we've encountered the End of Option List option, + * and so setting optlen isn't necessary */ + optlen = 1; + 803e5dc: 00800044 movi r2,1 + 803e5e0: e0bffe85 stb r2,-6(fp) + /* we're done - we couldn't locate the IP Router Alert + * option in this IP header */ + return IGMP_FALSE; + 803e5e4: 0005883a mov r2,zero + 803e5e8: 00002d06 br 803e6a0 + + case NOOP_OPT: + /* skip past the one byte of the No Operation option */ + optlen = 1; + 803e5ec: 00800044 movi r2,1 + 803e5f0: e0bffe85 stb r2,-6(fp) + break; + 803e5f4: 00001f06 br 803e674 + + case IP_RTR_ALERT_OPT: + rtr_alert_optp = (u_long *) optp; + 803e5f8: e0bfff17 ldw r2,-4(fp) + 803e5fc: e0bffd15 stw r2,-12(fp) + if ((ntohl (*rtr_alert_optp)) == IP_RTR_ALERT_OPT_DATA) + 803e600: e0bffd17 ldw r2,-12(fp) + 803e604: 10800017 ldw r2,0(r2) + 803e608: 1006d63a srli r3,r2,24 + 803e60c: e0bffd17 ldw r2,-12(fp) + 803e610: 10800017 ldw r2,0(r2) + 803e614: 1004d23a srli r2,r2,8 + 803e618: 10bfc00c andi r2,r2,65280 + 803e61c: 1886b03a or r3,r3,r2 + 803e620: e0bffd17 ldw r2,-12(fp) + 803e624: 10800017 ldw r2,0(r2) + 803e628: 1004923a slli r2,r2,8 + 803e62c: 10803fec andhi r2,r2,255 + 803e630: 1886b03a or r3,r3,r2 + 803e634: e0bffd17 ldw r2,-12(fp) + 803e638: 10800017 ldw r2,0(r2) + 803e63c: 1004963a slli r2,r2,24 + 803e640: 1886b03a or r3,r3,r2 + 803e644: 00a50134 movhi r2,37892 + 803e648: 1880021e bne r3,r2,803e654 + /* found the option, return success */ + return IGMP_TRUE; + 803e64c: 00800044 movi r2,1 + 803e650: 00001306 br 803e6a0 + else return IGMP_FALSE; + 803e654: 0005883a mov r2,zero + 803e658: 00001106 br 803e6a0 + + default: + /* extract the length of the current option, and compute + * the total length of this option */ + optlen = (*(optp + 1)) + 2; + 803e65c: e0bfff17 ldw r2,-4(fp) + 803e660: 10800044 addi r2,r2,1 + 803e664: 10800003 ldbu r2,0(r2) + 803e668: 10800084 addi r2,r2,2 + 803e66c: e0bffe85 stb r2,-6(fp) + break; + 803e670: 0001883a nop + } + + /* skip past the bytes associated with the current option to + * point to the next option. */ + optp += optlen; + 803e674: e0bffe83 ldbu r2,-6(fp) + 803e678: e0ffff17 ldw r3,-4(fp) + 803e67c: 1885883a add r2,r3,r2 + 803e680: e0bfff15 stw r2,-4(fp) + total_optlen -= optlen; + 803e684: e0fffec3 ldbu r3,-5(fp) + 803e688: e0bffe83 ldbu r2,-6(fp) + 803e68c: 1885c83a sub r2,r3,r2 + 803e690: e0bffec5 stb r2,-5(fp) + while (total_optlen > 0) + 803e694: e0bffec3 ldbu r2,-5(fp) + 803e698: 103fc61e bne r2,zero,803e5b4 + } /* end WHILE */ + } + + /* didn't find IP Alert option in IP header of rcvd packet */ + return IGMP_FALSE; + 803e69c: 0005883a mov r2,zero +} + 803e6a0: e037883a mov sp,fp + 803e6a4: df000017 ldw fp,0(sp) + 803e6a8: dec00104 addi sp,sp,4 + 803e6ac: f800283a ret + +0803e6b0 : + * RETURNS: + */ + +void +IPADDR_TO_NETP(ip_addr addr, NET* netp) +{ + 803e6b0: defffc04 addi sp,sp,-16 + 803e6b4: df000315 stw fp,12(sp) + 803e6b8: df000304 addi fp,sp,12 + 803e6bc: e13ffe15 stw r4,-8(fp) + 803e6c0: e17ffd15 stw r5,-12(fp) + u_short idx = 0; + 803e6c4: e03fff8d sth zero,-2(fp) + *netp = nets[idx]; + 803e6c8: e0bfff8b ldhu r2,-2(fp) + 803e6cc: 100690ba slli r3,r2,2 + 803e6d0: 008201b4 movhi r2,2054 + 803e6d4: 1885883a add r2,r3,r2 + 803e6d8: 10f77017 ldw r3,-8768(r2) + 803e6dc: e0bffd17 ldw r2,-12(fp) + 803e6e0: 10c00015 stw r3,0(r2) +/* + * If ip address is not specified, return the first intfc that supports + * multicast + */ + if (addr == AADDR) + 803e6e4: e0bffe17 ldw r2,-8(fp) + 803e6e8: 1000281e bne r2,zero,803e78c + { + for (idx = 0; idx < ifNumber; idx++) + 803e6ec: e03fff8d sth zero,-2(fp) + 803e6f0: 00001206 br 803e73c + { + if (nets[idx]->n_mcastlist) + 803e6f4: e0bfff8b ldhu r2,-2(fp) + 803e6f8: 100690ba slli r3,r2,2 + 803e6fc: 008201b4 movhi r2,2054 + 803e700: 1885883a add r2,r3,r2 + 803e704: 10b77017 ldw r2,-8768(r2) + 803e708: 10802b17 ldw r2,172(r2) + 803e70c: 10000826 beq r2,zero,803e730 + { + *netp = nets[idx]; + 803e710: e0bfff8b ldhu r2,-2(fp) + 803e714: 100690ba slli r3,r2,2 + 803e718: 008201b4 movhi r2,2054 + 803e71c: 1885883a add r2,r3,r2 + 803e720: 10f77017 ldw r3,-8768(r2) + 803e724: e0bffd17 ldw r2,-12(fp) + 803e728: 10c00015 stw r3,0(r2) + break; + 803e72c: 00002006 br 803e7b0 + for (idx = 0; idx < ifNumber; idx++) + 803e730: e0bfff8b ldhu r2,-2(fp) + 803e734: 10800044 addi r2,r2,1 + 803e738: e0bfff8d sth r2,-2(fp) + 803e73c: e0ffff8b ldhu r3,-2(fp) + 803e740: d0a06717 ldw r2,-32356(gp) + 803e744: 18bfeb36 bltu r3,r2,803e6f4 + } + else + *netp = nets[idx]; + } + } +} + 803e748: 00001906 br 803e7b0 + idx++; + 803e74c: e0bfff8b ldhu r2,-2(fp) + 803e750: 10800044 addi r2,r2,1 + 803e754: e0bfff8d sth r2,-2(fp) + if (idx >= ifNumber) + 803e758: e0ffff8b ldhu r3,-2(fp) + 803e75c: d0a06717 ldw r2,-32356(gp) + 803e760: 18800336 bltu r3,r2,803e770 + *netp = NULL; + 803e764: e0bffd17 ldw r2,-12(fp) + 803e768: 10000015 stw zero,0(r2) + break; + 803e76c: 00001006 br 803e7b0 + *netp = nets[idx]; + 803e770: e0bfff8b ldhu r2,-2(fp) + 803e774: 100690ba slli r3,r2,2 + 803e778: 008201b4 movhi r2,2054 + 803e77c: 1885883a add r2,r3,r2 + 803e780: 10f77017 ldw r3,-8768(r2) + 803e784: e0bffd17 ldw r2,-12(fp) + 803e788: 10c00015 stw r3,0(r2) + while ((*netp != NULL) && ((*netp)->n_ipaddr != addr)) + 803e78c: e0bffd17 ldw r2,-12(fp) + 803e790: 10800017 ldw r2,0(r2) + 803e794: 10000626 beq r2,zero,803e7b0 + 803e798: e0bffd17 ldw r2,-12(fp) + 803e79c: 10800017 ldw r2,0(r2) + 803e7a0: 10800a17 ldw r2,40(r2) + 803e7a4: e0fffe17 ldw r3,-8(fp) + 803e7a8: 18bfe81e bne r3,r2,803e74c +} + 803e7ac: 00000006 br 803e7b0 + 803e7b0: 0001883a nop + 803e7b4: e037883a mov sp,fp + 803e7b8: df000017 ldw fp,0(sp) + 803e7bc: dec00104 addi sp,sp,4 + 803e7c0: f800283a ret + +0803e7c4 : + * RETURNS: + */ + +int +ip_setmoptions(int optname, struct socket * so, void * val) +{ + 803e7c4: defff304 addi sp,sp,-52 + 803e7c8: dfc00c15 stw ra,48(sp) + 803e7cc: df000b15 stw fp,44(sp) + 803e7d0: dc000a15 stw r16,40(sp) + 803e7d4: df000b04 addi fp,sp,44 + 803e7d8: e13ff715 stw r4,-36(fp) + 803e7dc: e17ff615 stw r5,-40(fp) + 803e7e0: e1bff515 stw r6,-44(fp) + int error = 0; + 803e7e4: e03ffe15 stw zero,-8(fp) + u_short i; + struct ip_mreq * mreq; + struct net * netp = NULL; + 803e7e8: e03ff815 stw zero,-32(fp) + struct ip_moptions * imo = so->inp_moptions; + 803e7ec: e0bff617 ldw r2,-40(fp) + 803e7f0: 10800317 ldw r2,12(r2) + 803e7f4: e0bffc15 stw r2,-16(fp) + struct ip_moptions **imop = &so->inp_moptions; + 803e7f8: e0bff617 ldw r2,-40(fp) + 803e7fc: 10800304 addi r2,r2,12 + 803e800: e0bffb15 stw r2,-20(fp) + ip_addr addr; + + + if (imo == NULL) + 803e804: e0bffc17 ldw r2,-16(fp) + 803e808: 1000141e bne r2,zero,803e85c + { + /* + * No multicast option buffer attached to the pcb; + * allocate one and initialize to default values. + */ + imo = (struct ip_moptions*)IM_ALLOC(sizeof(*imo)); + 803e80c: 01001604 movi r4,88 + 803e810: 802982c0 call 802982c + 803e814: e0bffc15 stw r2,-16(fp) + + if (imo == NULL) + 803e818: e0bffc17 ldw r2,-16(fp) + 803e81c: 1000021e bne r2,zero,803e828 + return (ENOBUFS); + 803e820: 00801a44 movi r2,105 + 803e824: 00014906 br 803ed4c + *imop = imo; + 803e828: e0bffb17 ldw r2,-20(fp) + 803e82c: e0fffc17 ldw r3,-16(fp) + 803e830: 10c00015 stw r3,0(r2) + imo->imo_multicast_netp = NULL; + 803e834: e0bffc17 ldw r2,-16(fp) + 803e838: 10000015 stw zero,0(r2) + imo->imo_multicast_ttl = IP_DEFAULT_MULTICAST_TTL; + 803e83c: e0bffc17 ldw r2,-16(fp) + 803e840: 00c00044 movi r3,1 + 803e844: 10c00105 stb r3,4(r2) + imo->imo_multicast_loop = IP_DEFAULT_MULTICAST_LOOP; + 803e848: e0bffc17 ldw r2,-16(fp) + 803e84c: 00c00044 movi r3,1 + 803e850: 10c00145 stb r3,5(r2) + imo->imo_num_memberships = 0; + 803e854: e0bffc17 ldw r2,-16(fp) + 803e858: 1000018d sth zero,6(r2) + } + + switch (optname) + 803e85c: e0bff717 ldw r2,-36(fp) + 803e860: 10bffdc4 addi r2,r2,-9 + 803e864: 10c00168 cmpgeui r3,r2,5 + 803e868: 18011c1e bne r3,zero,803ecdc + 803e86c: 100690ba slli r3,r2,2 + 803e870: 00820134 movhi r2,2052 + 803e874: 1885883a add r2,r3,r2 + 803e878: 10ba2017 ldw r2,-6016(r2) + 803e87c: 1000683a jmp r2 + 803e880: 0803e894 ori zero,at,4002 + 803e884: 0803e8fc xorhi zero,at,4003 + 803e888: 0803e910 cmplti zero,at,4004 + 803e88c: 0803e944 addi zero,at,4005 + 803e890: 0803eb08 cmpgei zero,at,4012 + + case IP_MULTICAST_IF: + /* + * Select the interface for outgoing multicast packets. + */ + addr = *(ip_addr *)val; + 803e894: e0bff517 ldw r2,-44(fp) + 803e898: 10800017 ldw r2,0(r2) + 803e89c: e0bffa15 stw r2,-24(fp) + /* + * AADDR is used to remove a previous selection. + * When no interface is selected, a default one is + * chosen every time a multicast packet is sent. + */ + if (addr == AADDR) + 803e8a0: e0bffa17 ldw r2,-24(fp) + 803e8a4: 1000031e bne r2,zero,803e8b4 + { + imo->imo_multicast_netp = NULL; + 803e8a8: e0bffc17 ldw r2,-16(fp) + 803e8ac: 10000015 stw zero,0(r2) + break; + 803e8b0: 00010e06 br 803ecec + /* + * The selected interface is identified by its local + * IP address. Find the interface and confirm that + * it supports multicasting. + */ + IPADDR_TO_NETP(addr, &netp); + 803e8b4: e0bff804 addi r2,fp,-32 + 803e8b8: 100b883a mov r5,r2 + 803e8bc: e13ffa17 ldw r4,-24(fp) + 803e8c0: 803e6b00 call 803e6b0 + if ((netp == NULL) || (netp->n_mcastlist) == NULL) + 803e8c4: e0bff817 ldw r2,-32(fp) + 803e8c8: 10000326 beq r2,zero,803e8d8 + 803e8cc: e0bff817 ldw r2,-32(fp) + 803e8d0: 10802b17 ldw r2,172(r2) + 803e8d4: 1000031e bne r2,zero,803e8e4 + { + error = EADDRNOTAVAIL; + 803e8d8: 00801f44 movi r2,125 + 803e8dc: e0bffe15 stw r2,-8(fp) + break; + 803e8e0: 00010206 br 803ecec + } + if (addr != AADDR) + 803e8e4: e0bffa17 ldw r2,-24(fp) + 803e8e8: 1000ff26 beq r2,zero,803ece8 + imo->imo_multicast_netp = netp; + 803e8ec: e0fff817 ldw r3,-32(fp) + 803e8f0: e0bffc17 ldw r2,-16(fp) + 803e8f4: 10c00015 stw r3,0(r2) + break; + 803e8f8: 0000fb06 br 803ece8 + + case IP_MULTICAST_TTL: + /* + * Set the IP time-to-live for outgoing multicast packets. + */ + imo->imo_multicast_ttl = *(u_char *)val; + 803e8fc: e0bff517 ldw r2,-44(fp) + 803e900: 10c00003 ldbu r3,0(r2) + 803e904: e0bffc17 ldw r2,-16(fp) + 803e908: 10c00105 stb r3,4(r2) + break; + 803e90c: 0000f706 br 803ecec + case IP_MULTICAST_LOOP: + /* + * Set the loopback flag for outgoing multicast packets. + * Must be zero or one. + */ + if (*(u_char *)val > 1) + 803e910: e0bff517 ldw r2,-44(fp) + 803e914: 10800003 ldbu r2,0(r2) + 803e918: 10803fcc andi r2,r2,255 + 803e91c: 108000b0 cmpltui r2,r2,2 + 803e920: 1000031e bne r2,zero,803e930 + { + error = EINVAL; + 803e924: 00800584 movi r2,22 + 803e928: e0bffe15 stw r2,-8(fp) + break; + 803e92c: 0000ef06 br 803ecec + } + imo->imo_multicast_loop = *(u_char *)(val); + 803e930: e0bff517 ldw r2,-44(fp) + 803e934: 10c00003 ldbu r3,0(r2) + 803e938: e0bffc17 ldw r2,-16(fp) + 803e93c: 10c00145 stb r3,5(r2) + break; + 803e940: 0000ea06 br 803ecec + case IP_ADD_MEMBERSHIP: + /* + * Add a multicast group membership. + * Group must be a valid IP multicast address. + */ + mreq = (struct ip_mreq *)val; + 803e944: e0bff517 ldw r2,-44(fp) + 803e948: e0bff915 stw r2,-28(fp) + if (!IN_MULTICAST(ntohl(mreq->imr_multiaddr))) + 803e94c: e0bff917 ldw r2,-28(fp) + 803e950: 10800017 ldw r2,0(r2) + 803e954: 1006d63a srli r3,r2,24 + 803e958: e0bff917 ldw r2,-28(fp) + 803e95c: 10800017 ldw r2,0(r2) + 803e960: 1004d23a srli r2,r2,8 + 803e964: 10bfc00c andi r2,r2,65280 + 803e968: 1886b03a or r3,r3,r2 + 803e96c: e0bff917 ldw r2,-28(fp) + 803e970: 10800017 ldw r2,0(r2) + 803e974: 1004923a slli r2,r2,8 + 803e978: 10803fec andhi r2,r2,255 + 803e97c: 1886b03a or r3,r3,r2 + 803e980: e0bff917 ldw r2,-28(fp) + 803e984: 10800017 ldw r2,0(r2) + 803e988: 1004963a slli r2,r2,24 + 803e98c: 1884b03a or r2,r3,r2 + 803e990: 10fc002c andhi r3,r2,61440 + 803e994: 00b80034 movhi r2,57344 + 803e998: 18800326 beq r3,r2,803e9a8 + { + error = EINVAL; + 803e99c: 00800584 movi r2,22 + 803e9a0: e0bffe15 stw r2,-8(fp) + break; + 803e9a4: 0000d106 br 803ecec + * If no interface address was provided, use the interface of + * the route to the given multicast address. + * For the Iniche stack implementation, look for a default + * interface that supports multicast. + */ + IPADDR_TO_NETP(mreq->imr_interface, &netp); + 803e9a8: e0bff917 ldw r2,-28(fp) + 803e9ac: 10800117 ldw r2,4(r2) + 803e9b0: e0fff804 addi r3,fp,-32 + 803e9b4: 180b883a mov r5,r3 + 803e9b8: 1009883a mov r4,r2 + 803e9bc: 803e6b00 call 803e6b0 + /* + * See if we found an interface, and confirm that it + * supports multicast. + */ + if (netp == NULL || (netp->n_mcastlist) == NULL) + 803e9c0: e0bff817 ldw r2,-32(fp) + 803e9c4: 10000326 beq r2,zero,803e9d4 + 803e9c8: e0bff817 ldw r2,-32(fp) + 803e9cc: 10802b17 ldw r2,172(r2) + 803e9d0: 1000031e bne r2,zero,803e9e0 + { + error = EADDRNOTAVAIL; + 803e9d4: 00801f44 movi r2,125 + 803e9d8: e0bffe15 stw r2,-8(fp) + break; + 803e9dc: 0000c306 br 803ecec + } + /* + * See if the membership already exists or if all the + * membership slots are full. + */ + for (i = 0; i < imo->imo_num_memberships; ++i) + 803e9e0: e03ffd8d sth zero,-10(fp) + 803e9e4: 00001606 br 803ea40 + { + if (imo->imo_membership[i]->inm_netp == netp && + 803e9e8: e0bffd8b ldhu r2,-10(fp) + 803e9ec: e0fffc17 ldw r3,-16(fp) + 803e9f0: 10800084 addi r2,r2,2 + 803e9f4: 100490ba slli r2,r2,2 + 803e9f8: 1885883a add r2,r3,r2 + 803e9fc: 10800017 ldw r2,0(r2) + 803ea00: 10c00117 ldw r3,4(r2) + 803ea04: e0bff817 ldw r2,-32(fp) + 803ea08: 18800a1e bne r3,r2,803ea34 + imo->imo_membership[i]->inm_addr + 803ea0c: e0bffd8b ldhu r2,-10(fp) + 803ea10: e0fffc17 ldw r3,-16(fp) + 803ea14: 10800084 addi r2,r2,2 + 803ea18: 100490ba slli r2,r2,2 + 803ea1c: 1885883a add r2,r3,r2 + 803ea20: 10800017 ldw r2,0(r2) + 803ea24: 10c00017 ldw r3,0(r2) + == mreq->imr_multiaddr) + 803ea28: e0bff917 ldw r2,-28(fp) + 803ea2c: 10800017 ldw r2,0(r2) + if (imo->imo_membership[i]->inm_netp == netp && + 803ea30: 18800926 beq r3,r2,803ea58 + for (i = 0; i < imo->imo_num_memberships; ++i) + 803ea34: e0bffd8b ldhu r2,-10(fp) + 803ea38: 10800044 addi r2,r2,1 + 803ea3c: e0bffd8d sth r2,-10(fp) + 803ea40: e0bffc17 ldw r2,-16(fp) + 803ea44: 1080018b ldhu r2,6(r2) + 803ea48: e0fffd8b ldhu r3,-10(fp) + 803ea4c: 10bfffcc andi r2,r2,65535 + 803ea50: 18bfe536 bltu r3,r2,803e9e8 + 803ea54: 00000106 br 803ea5c + { + break; + 803ea58: 0001883a nop + } + } + if (i < imo->imo_num_memberships) + 803ea5c: e0bffc17 ldw r2,-16(fp) + 803ea60: 1080018b ldhu r2,6(r2) + 803ea64: e0fffd8b ldhu r3,-10(fp) + 803ea68: 10bfffcc andi r2,r2,65535 + 803ea6c: 1880032e bgeu r3,r2,803ea7c + { + error = EADDRINUSE; + 803ea70: 00801c04 movi r2,112 + 803ea74: e0bffe15 stw r2,-8(fp) + break; + 803ea78: 00009c06 br 803ecec + } + if (i == IP_MAX_MEMBERSHIPS) + 803ea7c: e0bffd8b ldhu r2,-10(fp) + 803ea80: 10800518 cmpnei r2,r2,20 + 803ea84: 1000031e bne r2,zero,803ea94 + { + error = ETOOMANYREFS; + 803ea88: 00802044 movi r2,129 + 803ea8c: e0bffe15 stw r2,-8(fp) + break; + 803ea90: 00009606 br 803ecec + /* + * Everything looks good; add a new record to the multicast + * address list for the given interface. + */ + if ((imo->imo_membership[i] = + in_addmulti(&mreq->imr_multiaddr, netp, 4)) == NULL) + 803ea94: e0bff917 ldw r2,-28(fp) + 803ea98: e0fff817 ldw r3,-32(fp) + if ((imo->imo_membership[i] = + 803ea9c: e43ffd8b ldhu r16,-10(fp) + in_addmulti(&mreq->imr_multiaddr, netp, 4)) == NULL) + 803eaa0: 01800104 movi r6,4 + 803eaa4: 180b883a mov r5,r3 + 803eaa8: 1009883a mov r4,r2 + 803eaac: 803c2ac0 call 803c2ac + 803eab0: 1009883a mov r4,r2 + if ((imo->imo_membership[i] = + 803eab4: e0fffc17 ldw r3,-16(fp) + 803eab8: 80800084 addi r2,r16,2 + 803eabc: 100490ba slli r2,r2,2 + 803eac0: 1885883a add r2,r3,r2 + 803eac4: 11000015 stw r4,0(r2) + 803eac8: e0fffc17 ldw r3,-16(fp) + 803eacc: 80800084 addi r2,r16,2 + 803ead0: 100490ba slli r2,r2,2 + 803ead4: 1885883a add r2,r3,r2 + 803ead8: 10800017 ldw r2,0(r2) + 803eadc: 1000031e bne r2,zero,803eaec + { + error = ENOBUFS; + 803eae0: 00801a44 movi r2,105 + 803eae4: e0bffe15 stw r2,-8(fp) + break; + 803eae8: 00008006 br 803ecec + } + ++imo->imo_num_memberships; + 803eaec: e0bffc17 ldw r2,-16(fp) + 803eaf0: 1080018b ldhu r2,6(r2) + 803eaf4: 10800044 addi r2,r2,1 + 803eaf8: 1007883a mov r3,r2 + 803eafc: e0bffc17 ldw r2,-16(fp) + 803eb00: 10c0018d sth r3,6(r2) + break; + 803eb04: 00007906 br 803ecec + case IP_DROP_MEMBERSHIP: + /* + * Drop a multicast group membership. + * Group must be a valid IP multicast address. + */ + mreq = (struct ip_mreq *)val; + 803eb08: e0bff517 ldw r2,-44(fp) + 803eb0c: e0bff915 stw r2,-28(fp) + if (!IN_MULTICAST(ntohl(mreq->imr_multiaddr))) + 803eb10: e0bff917 ldw r2,-28(fp) + 803eb14: 10800017 ldw r2,0(r2) + 803eb18: 1006d63a srli r3,r2,24 + 803eb1c: e0bff917 ldw r2,-28(fp) + 803eb20: 10800017 ldw r2,0(r2) + 803eb24: 1004d23a srli r2,r2,8 + 803eb28: 10bfc00c andi r2,r2,65280 + 803eb2c: 1886b03a or r3,r3,r2 + 803eb30: e0bff917 ldw r2,-28(fp) + 803eb34: 10800017 ldw r2,0(r2) + 803eb38: 1004923a slli r2,r2,8 + 803eb3c: 10803fec andhi r2,r2,255 + 803eb40: 1886b03a or r3,r3,r2 + 803eb44: e0bff917 ldw r2,-28(fp) + 803eb48: 10800017 ldw r2,0(r2) + 803eb4c: 1004963a slli r2,r2,24 + 803eb50: 1884b03a or r2,r3,r2 + 803eb54: 10fc002c andhi r3,r2,61440 + 803eb58: 00b80034 movhi r2,57344 + 803eb5c: 18800326 beq r3,r2,803eb6c + { + error = EINVAL; + 803eb60: 00800584 movi r2,22 + 803eb64: e0bffe15 stw r2,-8(fp) + break; + 803eb68: 00006006 br 803ecec + * If an interface address was specified, get a pointer + * to its ifnet structure. If an interface address was not + * specified, get a pointer to the first interface that + * supports multicast. + */ + IPADDR_TO_NETP(mreq->imr_interface, &netp); + 803eb6c: e0bff917 ldw r2,-28(fp) + 803eb70: 10800117 ldw r2,4(r2) + 803eb74: e0fff804 addi r3,fp,-32 + 803eb78: 180b883a mov r5,r3 + 803eb7c: 1009883a mov r4,r2 + 803eb80: 803e6b00 call 803e6b0 + if (netp == NULL) + 803eb84: e0bff817 ldw r2,-32(fp) + 803eb88: 1000031e bne r2,zero,803eb98 + { + error = EADDRNOTAVAIL; + 803eb8c: 00801f44 movi r2,125 + 803eb90: e0bffe15 stw r2,-8(fp) + break; + 803eb94: 00005506 br 803ecec + } + + /* + * Find the membership in the membership array. + */ + for (i = 0; i < imo->imo_num_memberships; ++i) + 803eb98: e03ffd8d sth zero,-10(fp) + 803eb9c: 00001806 br 803ec00 + { + if ((netp == NULL || + 803eba0: e0bff817 ldw r2,-32(fp) + 803eba4: 10000926 beq r2,zero,803ebcc + imo->imo_membership[i]->inm_netp == netp) && + 803eba8: e0bffd8b ldhu r2,-10(fp) + 803ebac: e0fffc17 ldw r3,-16(fp) + 803ebb0: 10800084 addi r2,r2,2 + 803ebb4: 100490ba slli r2,r2,2 + 803ebb8: 1885883a add r2,r3,r2 + 803ebbc: 10800017 ldw r2,0(r2) + 803ebc0: 10c00117 ldw r3,4(r2) + 803ebc4: e0bff817 ldw r2,-32(fp) + if ((netp == NULL || + 803ebc8: 18800a1e bne r3,r2,803ebf4 + imo->imo_membership[i]->inm_addr == + 803ebcc: e0bffd8b ldhu r2,-10(fp) + 803ebd0: e0fffc17 ldw r3,-16(fp) + 803ebd4: 10800084 addi r2,r2,2 + 803ebd8: 100490ba slli r2,r2,2 + 803ebdc: 1885883a add r2,r3,r2 + 803ebe0: 10800017 ldw r2,0(r2) + 803ebe4: 10c00017 ldw r3,0(r2) + mreq->imr_multiaddr) + 803ebe8: e0bff917 ldw r2,-28(fp) + 803ebec: 10800017 ldw r2,0(r2) + imo->imo_membership[i]->inm_netp == netp) && + 803ebf0: 18800926 beq r3,r2,803ec18 + for (i = 0; i < imo->imo_num_memberships; ++i) + 803ebf4: e0bffd8b ldhu r2,-10(fp) + 803ebf8: 10800044 addi r2,r2,1 + 803ebfc: e0bffd8d sth r2,-10(fp) + 803ec00: e0bffc17 ldw r2,-16(fp) + 803ec04: 1080018b ldhu r2,6(r2) + 803ec08: e0fffd8b ldhu r3,-10(fp) + 803ec0c: 10bfffcc andi r2,r2,65535 + 803ec10: 18bfe336 bltu r3,r2,803eba0 + 803ec14: 00000106 br 803ec1c + { + break; + 803ec18: 0001883a nop + } + } + if (i == imo->imo_num_memberships) + 803ec1c: e0bffc17 ldw r2,-16(fp) + 803ec20: 1080018b ldhu r2,6(r2) + 803ec24: e0fffd8b ldhu r3,-10(fp) + 803ec28: 10bfffcc andi r2,r2,65535 + 803ec2c: 1880031e bne r3,r2,803ec3c + { + error = EADDRNOTAVAIL; + 803ec30: 00801f44 movi r2,125 + 803ec34: e0bffe15 stw r2,-8(fp) + break; + 803ec38: 00002c06 br 803ecec + } + /* + * Give up the multicast address record to which the + * membership points. + */ + in_delmulti(imo->imo_membership[i]); + 803ec3c: e0bffd8b ldhu r2,-10(fp) + 803ec40: e0fffc17 ldw r3,-16(fp) + 803ec44: 10800084 addi r2,r2,2 + 803ec48: 100490ba slli r2,r2,2 + 803ec4c: 1885883a add r2,r3,r2 + 803ec50: 10800017 ldw r2,0(r2) + 803ec54: 1009883a mov r4,r2 + 803ec58: 803c3f80 call 803c3f8 + /* + * Remove the gap in the membership array. + */ + for (++i; i < imo->imo_num_memberships; ++i) + 803ec5c: e0bffd8b ldhu r2,-10(fp) + 803ec60: 10800044 addi r2,r2,1 + 803ec64: e0bffd8d sth r2,-10(fp) + 803ec68: 00001006 br 803ecac + imo->imo_membership[i-1] = imo->imo_membership[i]; + 803ec6c: e0fffd8b ldhu r3,-10(fp) + 803ec70: e0bffd8b ldhu r2,-10(fp) + 803ec74: 10bfffc4 addi r2,r2,-1 + 803ec78: e13ffc17 ldw r4,-16(fp) + 803ec7c: 18c00084 addi r3,r3,2 + 803ec80: 180690ba slli r3,r3,2 + 803ec84: 20c7883a add r3,r4,r3 + 803ec88: 18c00017 ldw r3,0(r3) + 803ec8c: e13ffc17 ldw r4,-16(fp) + 803ec90: 10800084 addi r2,r2,2 + 803ec94: 100490ba slli r2,r2,2 + 803ec98: 2085883a add r2,r4,r2 + 803ec9c: 10c00015 stw r3,0(r2) + for (++i; i < imo->imo_num_memberships; ++i) + 803eca0: e0bffd8b ldhu r2,-10(fp) + 803eca4: 10800044 addi r2,r2,1 + 803eca8: e0bffd8d sth r2,-10(fp) + 803ecac: e0bffc17 ldw r2,-16(fp) + 803ecb0: 1080018b ldhu r2,6(r2) + 803ecb4: e0fffd8b ldhu r3,-10(fp) + 803ecb8: 10bfffcc andi r2,r2,65535 + 803ecbc: 18bfeb36 bltu r3,r2,803ec6c + --imo->imo_num_memberships; + 803ecc0: e0bffc17 ldw r2,-16(fp) + 803ecc4: 1080018b ldhu r2,6(r2) + 803ecc8: 10bfffc4 addi r2,r2,-1 + 803eccc: 1007883a mov r3,r2 + 803ecd0: e0bffc17 ldw r2,-16(fp) + 803ecd4: 10c0018d sth r3,6(r2) + break; + 803ecd8: 00000406 br 803ecec + + default: + error = EOPNOTSUPP; + 803ecdc: 008017c4 movi r2,95 + 803ece0: e0bffe15 stw r2,-8(fp) + break; + 803ece4: 00000106 br 803ecec + break; + 803ece8: 0001883a nop + } + + /* + * If all options have default values, no need to keep the mbuf. + */ + if (imo->imo_multicast_netp == NULL && + 803ecec: e0bffc17 ldw r2,-16(fp) + 803ecf0: 10800017 ldw r2,0(r2) + 803ecf4: 1000141e bne r2,zero,803ed48 + imo->imo_multicast_ttl == IP_DEFAULT_MULTICAST_TTL && + 803ecf8: e0bffc17 ldw r2,-16(fp) + 803ecfc: 10800103 ldbu r2,4(r2) + if (imo->imo_multicast_netp == NULL && + 803ed00: 10803fcc andi r2,r2,255 + 803ed04: 10800058 cmpnei r2,r2,1 + 803ed08: 10000f1e bne r2,zero,803ed48 + imo->imo_multicast_loop == IP_DEFAULT_MULTICAST_LOOP && + 803ed0c: e0bffc17 ldw r2,-16(fp) + 803ed10: 10800143 ldbu r2,5(r2) + imo->imo_multicast_ttl == IP_DEFAULT_MULTICAST_TTL && + 803ed14: 10803fcc andi r2,r2,255 + 803ed18: 10800058 cmpnei r2,r2,1 + 803ed1c: 10000a1e bne r2,zero,803ed48 + imo->imo_num_memberships == 0) + 803ed20: e0bffc17 ldw r2,-16(fp) + 803ed24: 1080018b ldhu r2,6(r2) + imo->imo_multicast_loop == IP_DEFAULT_MULTICAST_LOOP && + 803ed28: 10bfffcc andi r2,r2,65535 + 803ed2c: 1000061e bne r2,zero,803ed48 + { + IM_FREE(*imop); + 803ed30: e0bffb17 ldw r2,-20(fp) + 803ed34: 10800017 ldw r2,0(r2) + 803ed38: 1009883a mov r4,r2 + 803ed3c: 80298600 call 8029860 + *imop = NULL; + 803ed40: e0bffb17 ldw r2,-20(fp) + 803ed44: 10000015 stw zero,0(r2) + } + return (error); + 803ed48: e0bffe17 ldw r2,-8(fp) +} + 803ed4c: e6ffff04 addi sp,fp,-4 + 803ed50: dfc00217 ldw ra,8(sp) + 803ed54: df000117 ldw fp,4(sp) + 803ed58: dc000017 ldw r16,0(sp) + 803ed5c: dec00304 addi sp,sp,12 + 803ed60: f800283a ret + +0803ed64 : + * RETURNS: + */ + +int +ip_getmoptions(int optname, struct socket * so, void * val) +{ + 803ed64: defff804 addi sp,sp,-32 + 803ed68: df000715 stw fp,28(sp) + 803ed6c: df000704 addi fp,sp,28 + 803ed70: e13ffb15 stw r4,-20(fp) + 803ed74: e17ffa15 stw r5,-24(fp) + 803ed78: e1bff915 stw r6,-28(fp) + u_char * ttl; + u_char * loop; + ip_addr *addr; + struct ip_moptions* imo = so->inp_moptions; + 803ed7c: e0bffa17 ldw r2,-24(fp) + 803ed80: 10800317 ldw r2,12(r2) + 803ed84: e0bfff15 stw r2,-4(fp) + /* The following code will be commented out for Iniche stack. + * Don't allocate a buffer here. + * + * *mp = m_get(M_WAIT, MT_SOOPTS); + */ + switch (optname) + 803ed88: e0bffb17 ldw r2,-20(fp) + 803ed8c: 108002a0 cmpeqi r2,r2,10 + 803ed90: 1000171e bne r2,zero,803edf0 + 803ed94: e0bffb17 ldw r2,-20(fp) + 803ed98: 108002e0 cmpeqi r2,r2,11 + 803ed9c: 1000221e bne r2,zero,803ee28 + 803eda0: e0bffb17 ldw r2,-20(fp) + 803eda4: 10800258 cmpnei r2,r2,9 + 803eda8: 10002d1e bne r2,zero,803ee60 + { + + case IP_MULTICAST_IF: + addr = (ip_addr *)(val); + 803edac: e0bff917 ldw r2,-28(fp) + 803edb0: e0bffe15 stw r2,-8(fp) + if (imo == NULL || imo->imo_multicast_netp == NULL) + 803edb4: e0bfff17 ldw r2,-4(fp) + 803edb8: 10000326 beq r2,zero,803edc8 + 803edbc: e0bfff17 ldw r2,-4(fp) + 803edc0: 10800017 ldw r2,0(r2) + 803edc4: 1000031e bne r2,zero,803edd4 + *addr = AADDR; + 803edc8: e0bffe17 ldw r2,-8(fp) + 803edcc: 10000015 stw zero,0(r2) + 803edd0: 00000506 br 803ede8 + else + *addr = imo->imo_multicast_netp->n_ipaddr; + 803edd4: e0bfff17 ldw r2,-4(fp) + 803edd8: 10800017 ldw r2,0(r2) + 803eddc: 10c00a17 ldw r3,40(r2) + 803ede0: e0bffe17 ldw r2,-8(fp) + 803ede4: 10c00015 stw r3,0(r2) + return (0); + 803ede8: 0005883a mov r2,zero + 803edec: 00001d06 br 803ee64 + + case IP_MULTICAST_TTL: + ttl = (u_char *)val; + 803edf0: e0bff917 ldw r2,-28(fp) + 803edf4: e0bffd15 stw r2,-12(fp) + if (imo == NULL) + 803edf8: e0bfff17 ldw r2,-4(fp) + 803edfc: 1000041e bne r2,zero,803ee10 + *ttl = IP_DEFAULT_MULTICAST_TTL; + 803ee00: e0bffd17 ldw r2,-12(fp) + 803ee04: 00c00044 movi r3,1 + 803ee08: 10c00005 stb r3,0(r2) + 803ee0c: 00000406 br 803ee20 + else + *ttl = imo->imo_multicast_ttl; + 803ee10: e0bfff17 ldw r2,-4(fp) + 803ee14: 10c00103 ldbu r3,4(r2) + 803ee18: e0bffd17 ldw r2,-12(fp) + 803ee1c: 10c00005 stb r3,0(r2) + return (0); + 803ee20: 0005883a mov r2,zero + 803ee24: 00000f06 br 803ee64 + + case IP_MULTICAST_LOOP: + loop = (u_char *)val; + 803ee28: e0bff917 ldw r2,-28(fp) + 803ee2c: e0bffc15 stw r2,-16(fp) + if (imo == NULL) + 803ee30: e0bfff17 ldw r2,-4(fp) + 803ee34: 1000041e bne r2,zero,803ee48 + *loop = IP_DEFAULT_MULTICAST_LOOP; + 803ee38: e0bffc17 ldw r2,-16(fp) + 803ee3c: 00c00044 movi r3,1 + 803ee40: 10c00005 stb r3,0(r2) + 803ee44: 00000406 br 803ee58 + else + *loop = imo->imo_multicast_loop; + 803ee48: e0bfff17 ldw r2,-4(fp) + 803ee4c: 10c00143 ldbu r3,5(r2) + 803ee50: e0bffc17 ldw r2,-16(fp) + 803ee54: 10c00005 stb r3,0(r2) + return (0); + 803ee58: 0005883a mov r2,zero + 803ee5c: 00000106 br 803ee64 + + default: + return (EOPNOTSUPP); + 803ee60: 008017c4 movi r2,95 + } +} + 803ee64: e037883a mov sp,fp + 803ee68: df000017 ldw fp,0(sp) + 803ee6c: dec00104 addi sp,sp,4 + 803ee70: f800283a ret + +0803ee74 : + * RETURNS: + */ + +void +ip_freemoptions(struct ip_moptions * imo) +{ + 803ee74: defffc04 addi sp,sp,-16 + 803ee78: dfc00315 stw ra,12(sp) + 803ee7c: df000215 stw fp,8(sp) + 803ee80: df000204 addi fp,sp,8 + 803ee84: e13ffe15 stw r4,-8(fp) + u_short i; + + if (imo != NULL) + 803ee88: e0bffe17 ldw r2,-8(fp) + 803ee8c: 10001426 beq r2,zero,803eee0 + { + for (i = 0; i < imo->imo_num_memberships; ++i) + 803ee90: e03fff8d sth zero,-2(fp) + 803ee94: 00000b06 br 803eec4 + in_delmulti(imo->imo_membership[i]); + 803ee98: e0bfff8b ldhu r2,-2(fp) + 803ee9c: e0fffe17 ldw r3,-8(fp) + 803eea0: 10800084 addi r2,r2,2 + 803eea4: 100490ba slli r2,r2,2 + 803eea8: 1885883a add r2,r3,r2 + 803eeac: 10800017 ldw r2,0(r2) + 803eeb0: 1009883a mov r4,r2 + 803eeb4: 803c3f80 call 803c3f8 + for (i = 0; i < imo->imo_num_memberships; ++i) + 803eeb8: e0bfff8b ldhu r2,-2(fp) + 803eebc: 10800044 addi r2,r2,1 + 803eec0: e0bfff8d sth r2,-2(fp) + 803eec4: e0bffe17 ldw r2,-8(fp) + 803eec8: 1080018b ldhu r2,6(r2) + 803eecc: e0ffff8b ldhu r3,-2(fp) + 803eed0: 10bfffcc andi r2,r2,65535 + 803eed4: 18bff036 bltu r3,r2,803ee98 + npfree(imo); + 803eed8: e13ffe17 ldw r4,-8(fp) + 803eedc: 80298600 call 8029860 + } +} + 803eee0: 0001883a nop + 803eee4: e037883a mov sp,fp + 803eee8: dfc00117 ldw ra,4(sp) + 803eeec: df000017 ldw fp,0(sp) + 803eef0: dec00204 addi sp,sp,8 + 803eef4: f800283a ret + +0803eef8 : + * + * RETURNS: + */ + +void u_mctest_init() +{ + 803eef8: defffe04 addi sp,sp,-8 + 803eefc: dfc00115 stw ra,4(sp) + 803ef00: df000015 stw fp,0(sp) + 803ef04: d839883a mov fp,sp + printf("mctest init called\n"); + 803ef08: 01020174 movhi r4,2053 + 803ef0c: 212d2e04 addi r4,r4,-19272 + 803ef10: 8002d9c0 call 8002d9c +// altera changes end (cadler@altera.com) + install_menu(u_mctest_menu); +// altera changes begin (cadler@altera.com) +#endif //IN_MENUS +// altera changes end (cadler@altera.com) +} + 803ef14: 0001883a nop + 803ef18: e037883a mov sp,fp + 803ef1c: dfc00117 ldw ra,4(sp) + 803ef20: df000017 ldw fp,0(sp) + 803ef24: dec00204 addi sp,sp,8 + 803ef28: f800283a ret + +0803ef2c : + * + * RETURNS: + */ + +int u_mctest_run(void * pio) +{ + 803ef2c: defede04 addi sp,sp,-1160 + 803ef30: dfc12115 stw ra,1156(sp) + 803ef34: df012015 stw fp,1152(sp) + 803ef38: df012004 addi fp,sp,1152 + 803ef3c: e13ee215 stw r4,-1144(fp) + struct sockaddr_in stLocal, stTo, stFrom; + char achIn[BUFSIZE]; + char achOut[] = "Message number: "; + 803ef40: e0fee884 addi r3,fp,-1118 + 803ef44: 00820174 movhi r2,2053 + 803ef48: 10adda04 addi r2,r2,-18584 + 803ef4c: 01000784 movi r4,30 + 803ef50: 200d883a mov r6,r4 + 803ef54: 100b883a mov r5,r2 + 803ef58: 1809883a mov r4,r3 + 803ef5c: 80086b80 call 80086b8 + struct ip_mreq stMreq; + u_char cTmp; + unsigned long endtime; + + /* get a datagram socket */ + s = t_socket(AF_INET,SOCK_DGRAM, 0); + 803ef60: 000d883a mov r6,zero + 803ef64: 01400084 movi r5,2 + 803ef68: 01000084 movi r4,2 + 803ef6c: 802ba700 call 802ba70 + 803ef70: e0bffe15 stw r2,-8(fp) + + if (s == INVALID_SOCKET) + 803ef74: e0bffe17 ldw r2,-8(fp) + 803ef78: 10bfffd8 cmpnei r2,r2,-1 + 803ef7c: 1000091e bne r2,zero,803efa4 + { + ns_printf (pio,"t_socket() failed, Err: %d\n", t_errno(s)); + 803ef80: e13ffe17 ldw r4,-8(fp) + 803ef84: 802cfbc0 call 802cfbc + 803ef88: 100d883a mov r6,r2 + 803ef8c: 01420174 movhi r5,2053 + 803ef90: 296d3304 addi r5,r5,-19252 + 803ef94: e13ee217 ldw r4,-1144(fp) + 803ef98: 80273900 call 8027390 + exit(1); + 803ef9c: 01000044 movi r4,1 + 803efa0: 8042abc0 call 8042abc + } + + /* avoid EADDRINUSE error on bind() */ + iTmp = 1; + 803efa4: 00800044 movi r2,1 + 803efa8: e0bee715 stw r2,-1124(fp) + iRet = t_setsockopt(s, SOL_SOCKET, SO_REUSEADDR, (char *)&iTmp, sizeof(iTmp)); + 803efac: e0fee704 addi r3,fp,-1124 + 803efb0: 00800104 movi r2,4 + 803efb4: d8800015 stw r2,0(sp) + 803efb8: 180f883a mov r7,r3 + 803efbc: 01800104 movi r6,4 + 803efc0: 017fffc4 movi r5,-1 + 803efc4: e13ffe17 ldw r4,-8(fp) + 803efc8: 802c44c0 call 802c44c + 803efcc: e0bffd15 stw r2,-12(fp) + if (iRet == SOCKET_ERROR) + 803efd0: e0bffd17 ldw r2,-12(fp) + 803efd4: 10bfffd8 cmpnei r2,r2,-1 + 803efd8: 1000071e bne r2,zero,803eff8 + { + ns_printf (pio,"t_setsockopt() SO_REUSEADDR failed, Err: %d\n", + 803efdc: e13ffe17 ldw r4,-8(fp) + 803efe0: 802cfbc0 call 802cfbc + 803efe4: 100d883a mov r6,r2 + 803efe8: 01420174 movhi r5,2053 + 803efec: 296d3a04 addi r5,r5,-19224 + 803eff0: e13ee217 ldw r4,-1144(fp) + 803eff4: 80273900 call 8027390 + t_errno(s)); + } + + /* name the socket */ + stLocal.sin_family = AF_INET; + 803eff8: 00800084 movi r2,2 + 803effc: e0bff80d sth r2,-32(fp) + stLocal.sin_addr.s_addr = htonl(INADDR_ANY); + 803f000: e03ff915 stw zero,-28(fp) + stLocal.sin_port = htons(TEST_PORT); + 803f004: 00a00344 movi r2,-32755 + 803f008: e0bff88d sth r2,-30(fp) + iRet = t_bind(s, (struct sockaddr*) &stLocal, sizeof(struct sockaddr_in)); + 803f00c: e0bff804 addi r2,fp,-32 + 803f010: 01800404 movi r6,16 + 803f014: 100b883a mov r5,r2 + 803f018: e13ffe17 ldw r4,-8(fp) + 803f01c: 802baf00 call 802baf0 + 803f020: e0bffd15 stw r2,-12(fp) + if (iRet == SOCKET_ERROR) + 803f024: e0bffd17 ldw r2,-12(fp) + 803f028: 10bfffd8 cmpnei r2,r2,-1 + 803f02c: 1000061e bne r2,zero,803f048 + { + printf ("t_bind() failed, Err: %d\n", + 803f030: e13ffe17 ldw r4,-8(fp) + 803f034: 802cfbc0 call 802cfbc + 803f038: 100b883a mov r5,r2 + 803f03c: 01020174 movhi r4,2053 + 803f040: 212d4604 addi r4,r4,-19176 + 803f044: 8002c780 call 8002c78 + t_errno(s)); + } + + /* join the multicast group. TEST_ADDR */ + + ns_printf (pio,"Joining multicast group: %s\n", TEST_ADDR); + 803f048: 01820174 movhi r6,2053 + 803f04c: 31ad4d04 addi r6,r6,-19148 + 803f050: 01420174 movhi r5,2053 + 803f054: 296d5004 addi r5,r5,-19136 + 803f058: e13ee217 ldw r4,-1144(fp) + 803f05c: 80273900 call 8027390 + stMreq.imr_multiaddr = inet_addr(TEST_ADDR); + 803f060: 01020174 movhi r4,2053 + 803f064: 212d4d04 addi r4,r4,-19148 + 803f068: 803fc380 call 803fc38 + 803f06c: e0bee515 stw r2,-1132(fp) + stMreq.imr_interface = netstatic[0].n_ipaddr; + 803f070: 008201b4 movhi r2,2054 + 803f074: 10b6ba17 ldw r2,-9496(r2) + 803f078: e0bee615 stw r2,-1128(fp) + iRet = t_setsockopt(s, IPPROTO_IP, IP_ADD_MEMBERSHIP, + 803f07c: e0fee504 addi r3,fp,-1132 + 803f080: 00800204 movi r2,8 + 803f084: d8800015 stw r2,0(sp) + 803f088: 180f883a mov r7,r3 + 803f08c: 01800304 movi r6,12 + 803f090: 000b883a mov r5,zero + 803f094: e13ffe17 ldw r4,-8(fp) + 803f098: 802c44c0 call 802c44c + 803f09c: e0bffd15 stw r2,-12(fp) + (char *)&stMreq, sizeof(stMreq)); + if (iRet == SOCKET_ERROR) + 803f0a0: e0bffd17 ldw r2,-12(fp) + 803f0a4: 10bfffd8 cmpnei r2,r2,-1 + 803f0a8: 1000071e bne r2,zero,803f0c8 + { + ns_printf (pio,"t_setsockopt() IP_ADD_MEMBERSHIP failed, Err: %d\n", + 803f0ac: e13ffe17 ldw r4,-8(fp) + 803f0b0: 802cfbc0 call 802cfbc + 803f0b4: 100d883a mov r6,r2 + 803f0b8: 01420174 movhi r5,2053 + 803f0bc: 296d5804 addi r5,r5,-19104 + 803f0c0: e13ee217 ldw r4,-1144(fp) + 803f0c4: 80273900 call 8027390 + t_errno(s)); + } + tk_yield(); + 803f0c8: 8027ce40 call 8027ce4 + + /* join the multicast group. TEST_ADDR1 */ + + ns_printf (pio,"Joining multicast group: %s\n", TEST_ADDR1); + 803f0cc: 01820174 movhi r6,2053 + 803f0d0: 31ad6504 addi r6,r6,-19052 + 803f0d4: 01420174 movhi r5,2053 + 803f0d8: 296d5004 addi r5,r5,-19136 + 803f0dc: e13ee217 ldw r4,-1144(fp) + 803f0e0: 80273900 call 8027390 + stMreq.imr_multiaddr = inet_addr(TEST_ADDR1); + 803f0e4: 01020174 movhi r4,2053 + 803f0e8: 212d6504 addi r4,r4,-19052 + 803f0ec: 803fc380 call 803fc38 + 803f0f0: e0bee515 stw r2,-1132(fp) + stMreq.imr_interface = netstatic[0].n_ipaddr; + 803f0f4: 008201b4 movhi r2,2054 + 803f0f8: 10b6ba17 ldw r2,-9496(r2) + 803f0fc: e0bee615 stw r2,-1128(fp) + iRet = t_setsockopt(s, IPPROTO_IP, IP_ADD_MEMBERSHIP, + 803f100: e0fee504 addi r3,fp,-1132 + 803f104: 00800204 movi r2,8 + 803f108: d8800015 stw r2,0(sp) + 803f10c: 180f883a mov r7,r3 + 803f110: 01800304 movi r6,12 + 803f114: 000b883a mov r5,zero + 803f118: e13ffe17 ldw r4,-8(fp) + 803f11c: 802c44c0 call 802c44c + 803f120: e0bffd15 stw r2,-12(fp) + (char *)&stMreq, sizeof(stMreq)); + if (iRet == SOCKET_ERROR) + 803f124: e0bffd17 ldw r2,-12(fp) + 803f128: 10bfffd8 cmpnei r2,r2,-1 + 803f12c: 1000071e bne r2,zero,803f14c + { + ns_printf (pio,"t_setsockopt() IP_ADD_MEMBERSHIP failed, Err: %d\n", + 803f130: e13ffe17 ldw r4,-8(fp) + 803f134: 802cfbc0 call 802cfbc + 803f138: 100d883a mov r6,r2 + 803f13c: 01420174 movhi r5,2053 + 803f140: 296d5804 addi r5,r5,-19104 + 803f144: e13ee217 ldw r4,-1144(fp) + 803f148: 80273900 call 8027390 + t_errno(s)); + } + tk_yield(); + 803f14c: 8027ce40 call 8027ce4 + + /* join the multicast group. TEST_ADDR2 */ + + ns_printf (pio,"Joining multicast group: %s\n", TEST_ADDR2); + 803f150: 01820174 movhi r6,2053 + 803f154: 31ad6804 addi r6,r6,-19040 + 803f158: 01420174 movhi r5,2053 + 803f15c: 296d5004 addi r5,r5,-19136 + 803f160: e13ee217 ldw r4,-1144(fp) + 803f164: 80273900 call 8027390 + stMreq.imr_multiaddr = inet_addr(TEST_ADDR2); + 803f168: 01020174 movhi r4,2053 + 803f16c: 212d6804 addi r4,r4,-19040 + 803f170: 803fc380 call 803fc38 + 803f174: e0bee515 stw r2,-1132(fp) + stMreq.imr_interface = netstatic[0].n_ipaddr; + 803f178: 008201b4 movhi r2,2054 + 803f17c: 10b6ba17 ldw r2,-9496(r2) + 803f180: e0bee615 stw r2,-1128(fp) + iRet = t_setsockopt(s, IPPROTO_IP, IP_ADD_MEMBERSHIP, + 803f184: e0fee504 addi r3,fp,-1132 + 803f188: 00800204 movi r2,8 + 803f18c: d8800015 stw r2,0(sp) + 803f190: 180f883a mov r7,r3 + 803f194: 01800304 movi r6,12 + 803f198: 000b883a mov r5,zero + 803f19c: e13ffe17 ldw r4,-8(fp) + 803f1a0: 802c44c0 call 802c44c + 803f1a4: e0bffd15 stw r2,-12(fp) + (char *)&stMreq, sizeof(stMreq)); + if (iRet == SOCKET_ERROR) + 803f1a8: e0bffd17 ldw r2,-12(fp) + 803f1ac: 10bfffd8 cmpnei r2,r2,-1 + 803f1b0: 1000071e bne r2,zero,803f1d0 + { + ns_printf (pio,"t_setsockopt() IP_ADD_MEMBERSHIP failed, Err: %d\n", + 803f1b4: e13ffe17 ldw r4,-8(fp) + 803f1b8: 802cfbc0 call 802cfbc + 803f1bc: 100d883a mov r6,r2 + 803f1c0: 01420174 movhi r5,2053 + 803f1c4: 296d5804 addi r5,r5,-19104 + 803f1c8: e13ee217 ldw r4,-1144(fp) + 803f1cc: 80273900 call 8027390 + t_errno(s)); + } + tk_yield(); + 803f1d0: 8027ce40 call 8027ce4 + + /* set TTL to traverse up to multiple routers */ + cTmp = TTL_VALUE; + 803f1d4: 00800084 movi r2,2 + 803f1d8: e0bee4c5 stb r2,-1133(fp) + iRet = t_setsockopt(s, IPPROTO_IP, IP_MULTICAST_TTL, (char *)&cTmp, sizeof(cTmp)); + 803f1dc: e0fee4c4 addi r3,fp,-1133 + 803f1e0: 00800044 movi r2,1 + 803f1e4: d8800015 stw r2,0(sp) + 803f1e8: 180f883a mov r7,r3 + 803f1ec: 01800284 movi r6,10 + 803f1f0: 000b883a mov r5,zero + 803f1f4: e13ffe17 ldw r4,-8(fp) + 803f1f8: 802c44c0 call 802c44c + 803f1fc: e0bffd15 stw r2,-12(fp) + if (iRet == SOCKET_ERROR) + 803f200: e0bffd17 ldw r2,-12(fp) + 803f204: 10bfffd8 cmpnei r2,r2,-1 + 803f208: 1000071e bne r2,zero,803f228 + { + ns_printf (pio,"t_setsockopt() IP_MULTICAST_TTL failed, Err: %d\n", + 803f20c: e13ffe17 ldw r4,-8(fp) + 803f210: 802cfbc0 call 802cfbc + 803f214: 100d883a mov r6,r2 + 803f218: 01420174 movhi r5,2053 + 803f21c: 296d6b04 addi r5,r5,-19028 + 803f220: e13ee217 ldw r4,-1144(fp) + 803f224: 80273900 call 8027390 + t_errno(s)); + } + + /* enable loopback */ + cTmp = 1; + 803f228: 00800044 movi r2,1 + 803f22c: e0bee4c5 stb r2,-1133(fp) + iRet = t_setsockopt(s, IPPROTO_IP, IP_MULTICAST_LOOP, (char *)&cTmp, sizeof(cTmp)); + 803f230: e0fee4c4 addi r3,fp,-1133 + 803f234: 00800044 movi r2,1 + 803f238: d8800015 stw r2,0(sp) + 803f23c: 180f883a mov r7,r3 + 803f240: 018002c4 movi r6,11 + 803f244: 000b883a mov r5,zero + 803f248: e13ffe17 ldw r4,-8(fp) + 803f24c: 802c44c0 call 802c44c + 803f250: e0bffd15 stw r2,-12(fp) + if (iRet == SOCKET_ERROR) + 803f254: e0bffd17 ldw r2,-12(fp) + 803f258: 10bfffd8 cmpnei r2,r2,-1 + 803f25c: 1000071e bne r2,zero,803f27c + { + ns_printf (pio,"t_setsockopt() IP_MULTICAST_LOOP failed, Err: %d\n", + 803f260: e13ffe17 ldw r4,-8(fp) + 803f264: 802cfbc0 call 802cfbc + 803f268: 100d883a mov r6,r2 + 803f26c: 01420174 movhi r5,2053 + 803f270: 296d7804 addi r5,r5,-18976 + 803f274: e13ee217 ldw r4,-1144(fp) + 803f278: 80273900 call 8027390 + t_errno(s)); + } + + /* assign our destination address */ + stTo.sin_family = AF_INET; + 803f27c: 00800084 movi r2,2 + 803f280: e0bff40d sth r2,-48(fp) + stTo.sin_addr.s_addr = inet_addr(TEST_ADDR1); + 803f284: 01020174 movhi r4,2053 + 803f288: 212d6504 addi r4,r4,-19052 + 803f28c: 803fc380 call 803fc38 + 803f290: e0bff515 stw r2,-44(fp) + stTo.sin_port = htons(TEST_PORT); + 803f294: 00a00344 movi r2,-32755 + 803f298: e0bff48d sth r2,-46(fp) + ns_printf (pio,"Now sending to (and receiving from) multicast group: %s\n", + 803f29c: 01820174 movhi r6,2053 + 803f2a0: 31ad6504 addi r6,r6,-19052 + 803f2a4: 01420174 movhi r5,2053 + 803f2a8: 296d8504 addi r5,r5,-18924 + 803f2ac: e13ee217 ldw r4,-1144(fp) + 803f2b0: 80273900 call 8027390 + TEST_ADDR1); + + for (i = 0; i < LOOPMAX; i++) + 803f2b4: e03fff15 stw zero,-4(fp) + 803f2b8: 00008606 br 803f4d4 + { + static int iCounter = 1; + + /* send to the multicast address */ + sprintf(&achOut[16], "%d", iCounter++); + 803f2bc: d0a03117 ldw r2,-32572(gp) + 803f2c0: 10c00044 addi r3,r2,1 + 803f2c4: d0e03115 stw r3,-32572(gp) + 803f2c8: e0fee884 addi r3,fp,-1118 + 803f2cc: 18c00404 addi r3,r3,16 + 803f2d0: 100d883a mov r6,r2 + 803f2d4: 01420174 movhi r5,2053 + 803f2d8: 296d9404 addi r5,r5,-18864 + 803f2dc: 1809883a mov r4,r3 + 803f2e0: 8042d980 call 8042d98 + iRet = t_sendto(s, achOut, sizeof(achOut), 0, (struct sockaddr*)&stTo, + 803f2e4: e0fee884 addi r3,fp,-1118 + 803f2e8: 00800404 movi r2,16 + 803f2ec: d8800115 stw r2,4(sp) + 803f2f0: e0bff404 addi r2,fp,-48 + 803f2f4: d8800015 stw r2,0(sp) + 803f2f8: 000f883a mov r7,zero + 803f2fc: 01800784 movi r6,30 + 803f300: 180b883a mov r5,r3 + 803f304: e13ffe17 ldw r4,-8(fp) + 803f308: 802c9ac0 call 802c9ac + 803f30c: e0bffd15 stw r2,-12(fp) + sizeof(struct sockaddr_in)); + if (iRet < 0) + 803f310: e0bffd17 ldw r2,-12(fp) + 803f314: 1000080e bge r2,zero,803f338 + { + /* perror("sendto() failed\n"); */ + ns_printf (pio,"t_sendto() failed, Error: %d\n", t_errno(s)); + 803f318: e13ffe17 ldw r4,-8(fp) + 803f31c: 802cfbc0 call 802cfbc + 803f320: 100d883a mov r6,r2 + 803f324: 01420174 movhi r5,2053 + 803f328: 296d9504 addi r5,r5,-18860 + 803f32c: e13ee217 ldw r4,-1144(fp) + 803f330: 80273900 call 8027390 + /* exit(1); */ + goto exitloop; + 803f334: 00006b06 br 803f4e4 + } + + /* make the socket non-blocking */ + iTmp = 1; + 803f338: 00800044 movi r2,1 + 803f33c: e0bee715 stw r2,-1124(fp) + iRet = t_setsockopt(s, SOL_SOCKET, SO_NONBLOCK, (char *)&iTmp, sizeof(iTmp)); + 803f340: e0fee704 addi r3,fp,-1124 + 803f344: 00800104 movi r2,4 + 803f348: d8800015 stw r2,0(sp) + 803f34c: 180f883a mov r7,r3 + 803f350: 01840584 movi r6,4118 + 803f354: 017fffc4 movi r5,-1 + 803f358: e13ffe17 ldw r4,-8(fp) + 803f35c: 802c44c0 call 802c44c + 803f360: e0bffd15 stw r2,-12(fp) + if (iRet == SOCKET_ERROR) + 803f364: e0bffd17 ldw r2,-12(fp) + 803f368: 10bfffd8 cmpnei r2,r2,-1 + 803f36c: 1000071e bne r2,zero,803f38c + { + ns_printf (pio,"t_setsockopt() SO_NONBLOCK (1) failed, Err: %d\n", + 803f370: e13ffe17 ldw r4,-8(fp) + 803f374: 802cfbc0 call 802cfbc + 803f378: 100d883a mov r6,r2 + 803f37c: 01420174 movhi r5,2053 + 803f380: 296d9d04 addi r5,r5,-18828 + 803f384: e13ee217 ldw r4,-1144(fp) + 803f388: 80273900 call 8027390 + t_errno(s)); + } + + /* loop around for 5 seconds waiting to receive datagrams */ + endtime = cticks + (TPS * 5); + 803f38c: d0a07d17 ldw r2,-32268(gp) + 803f390: 10807d04 addi r2,r2,500 + 803f394: e0bffc15 stw r2,-16(fp) + + while (cticks < endtime) + 803f398: 00003406 br 803f46c + { + int sa_size = sizeof(struct sockaddr_in); + 803f39c: 00800404 movi r2,16 + 803f3a0: e0bee315 stw r2,-1140(fp) + tk_yield(); + 803f3a4: 8027ce40 call 8027ce4 + + iRet = t_recvfrom(s, achIn, BUFSIZE, 0, (struct sockaddr*)&stFrom, &sa_size); + 803f3a8: e0fef004 addi r3,fp,-1088 + 803f3ac: e0bee304 addi r2,fp,-1140 + 803f3b0: d8800115 stw r2,4(sp) + 803f3b4: e0bff004 addi r2,fp,-64 + 803f3b8: d8800015 stw r2,0(sp) + 803f3bc: 000f883a mov r7,zero + 803f3c0: 01810004 movi r6,1024 + 803f3c4: 180b883a mov r5,r3 + 803f3c8: e13ffe17 ldw r4,-8(fp) + 803f3cc: 802c8700 call 802c870 + 803f3d0: e0bffd15 stw r2,-12(fp) + if (iRet < 0) + 803f3d4: e0bffd17 ldw r2,-12(fp) + 803f3d8: 10000c0e bge r2,zero,803f40c + { + if (t_errno(s) != EWOULDBLOCK) + 803f3dc: e13ffe17 ldw r4,-8(fp) + 803f3e0: 802cfbc0 call 802cfbc + 803f3e4: 108002e0 cmpeqi r2,r2,11 + 803f3e8: 1000081e bne r2,zero,803f40c + { + /* perror("recvfrom() failed\n"); */ + ns_printf (pio,"t_recvfrom() failed, Error: %d\n", t_errno(s)); + 803f3ec: e13ffe17 ldw r4,-8(fp) + 803f3f0: 802cfbc0 call 802cfbc + 803f3f4: 100d883a mov r6,r2 + 803f3f8: 01420174 movhi r5,2053 + 803f3fc: 296da904 addi r5,r5,-18780 + 803f400: e13ee217 ldw r4,-1144(fp) + 803f404: 80273900 call 8027390 + 803f408: 00003606 br 803f4e4 + /* exit(1); */ + goto exitloop; + } + } + if (iRet > 0) + 803f40c: e0bffd17 ldw r2,-12(fp) + 803f410: 0080160e bge zero,r2,803f46c + { + ns_printf(pio,"From host:%s port:%d, %s\n", + 803f414: e0bff117 ldw r2,-60(fp) + 803f418: 1009883a mov r4,r2 + 803f41c: 8026fbc0 call 8026fbc + 803f420: 1009883a mov r4,r2 + print_ipad(stFrom.sin_addr.s_addr), + ntohs(stFrom.sin_port), achIn); + 803f424: e0bff08b ldhu r2,-62(fp) + 803f428: 10bfffcc andi r2,r2,65535 + 803f42c: 1004d23a srli r2,r2,8 + 803f430: 10bfffcc andi r2,r2,65535 + 803f434: 10c03fcc andi r3,r2,255 + 803f438: e0bff08b ldhu r2,-62(fp) + 803f43c: 10bfffcc andi r2,r2,65535 + 803f440: 1004923a slli r2,r2,8 + 803f444: 10bfffcc andi r2,r2,65535 + ns_printf(pio,"From host:%s port:%d, %s\n", + 803f448: 1886b03a or r3,r3,r2 + 803f44c: e0bef004 addi r2,fp,-1088 + 803f450: d8800015 stw r2,0(sp) + 803f454: 180f883a mov r7,r3 + 803f458: 200d883a mov r6,r4 + 803f45c: 01420174 movhi r5,2053 + 803f460: 296db104 addi r5,r5,-18748 + 803f464: e13ee217 ldw r4,-1144(fp) + 803f468: 80273900 call 8027390 + while (cticks < endtime) + 803f46c: d0e07d17 ldw r3,-32268(gp) + 803f470: e0bffc17 ldw r2,-16(fp) + 803f474: 18bfc936 bltu r3,r2,803f39c + } + } /* end while (cticks...) */ + + /* make the socket blocking */ + cTmp = 0; + 803f478: e03ee4c5 stb zero,-1133(fp) + iRet = t_setsockopt(s, SOL_SOCKET, SO_NONBLOCK, (char *)&cTmp, sizeof(cTmp)); + 803f47c: e0fee4c4 addi r3,fp,-1133 + 803f480: 00800044 movi r2,1 + 803f484: d8800015 stw r2,0(sp) + 803f488: 180f883a mov r7,r3 + 803f48c: 01840584 movi r6,4118 + 803f490: 017fffc4 movi r5,-1 + 803f494: e13ffe17 ldw r4,-8(fp) + 803f498: 802c44c0 call 802c44c + 803f49c: e0bffd15 stw r2,-12(fp) + if (iRet == SOCKET_ERROR) + 803f4a0: e0bffd17 ldw r2,-12(fp) + 803f4a4: 10bfffd8 cmpnei r2,r2,-1 + 803f4a8: 1000071e bne r2,zero,803f4c8 + { + ns_printf (pio,"t_setsockopt() SO_NONBLOCK (0) failed, Err: %d\n", + 803f4ac: e13ffe17 ldw r4,-8(fp) + 803f4b0: 802cfbc0 call 802cfbc + 803f4b4: 100d883a mov r6,r2 + 803f4b8: 01420174 movhi r5,2053 + 803f4bc: 296db804 addi r5,r5,-18720 + 803f4c0: e13ee217 ldw r4,-1144(fp) + 803f4c4: 80273900 call 8027390 + for (i = 0; i < LOOPMAX; i++) + 803f4c8: e0bfff17 ldw r2,-4(fp) + 803f4cc: 10800044 addi r2,r2,1 + 803f4d0: e0bfff15 stw r2,-4(fp) + 803f4d4: e0bfff17 ldw r2,-4(fp) + 803f4d8: 108000d0 cmplti r2,r2,3 + 803f4dc: 103f771e bne r2,zero,803f2bc + t_errno(s)); + } + } /* end for(;;) */ + +exitloop: + 803f4e0: 0001883a nop + /* delete the multicast group. */ + stMreq.imr_multiaddr = inet_addr(TEST_ADDR); + 803f4e4: 01020174 movhi r4,2053 + 803f4e8: 212d4d04 addi r4,r4,-19148 + 803f4ec: 803fc380 call 803fc38 + 803f4f0: e0bee515 stw r2,-1132(fp) + stMreq.imr_interface = netstatic[0].n_ipaddr; + 803f4f4: 008201b4 movhi r2,2054 + 803f4f8: 10b6ba17 ldw r2,-9496(r2) + 803f4fc: e0bee615 stw r2,-1128(fp) + iRet = t_setsockopt(s, IPPROTO_IP, IP_DROP_MEMBERSHIP, (char *)&stMreq, sizeof(stMreq)); + 803f500: e0fee504 addi r3,fp,-1132 + 803f504: 00800204 movi r2,8 + 803f508: d8800015 stw r2,0(sp) + 803f50c: 180f883a mov r7,r3 + 803f510: 01800344 movi r6,13 + 803f514: 000b883a mov r5,zero + 803f518: e13ffe17 ldw r4,-8(fp) + 803f51c: 802c44c0 call 802c44c + 803f520: e0bffd15 stw r2,-12(fp) + if (iRet == SOCKET_ERROR) + 803f524: e0bffd17 ldw r2,-12(fp) + 803f528: 10bfffd8 cmpnei r2,r2,-1 + 803f52c: 1000071e bne r2,zero,803f54c + { + ns_printf (pio,"t_setsockopt() IP_DROP_MEMBERSHIP failed, Err: %d\n", + 803f530: e13ffe17 ldw r4,-8(fp) + 803f534: 802cfbc0 call 802cfbc + 803f538: 100d883a mov r6,r2 + 803f53c: 01420174 movhi r5,2053 + 803f540: 296dc404 addi r5,r5,-18672 + 803f544: e13ee217 ldw r4,-1144(fp) + 803f548: 80273900 call 8027390 + { + ns_printf (pio,"t_shutdown failed. Err: %d\n", t_errno(s)); + } +#endif + + iRet = t_socketclose(s); + 803f54c: e13ffe17 ldw r4,-8(fp) + 803f550: 802ce700 call 802ce70 + 803f554: e0bffd15 stw r2,-12(fp) + if (iRet == SOCKET_ERROR) + 803f558: e0bffd17 ldw r2,-12(fp) + 803f55c: 10bfffd8 cmpnei r2,r2,-1 + 803f560: 1000071e bne r2,zero,803f580 + { + ns_printf (pio,"t_socketclose() failed. Err: %d\n", t_errno(s)); + 803f564: e13ffe17 ldw r4,-8(fp) + 803f568: 802cfbc0 call 802cfbc + 803f56c: 100d883a mov r6,r2 + 803f570: 01420174 movhi r5,2053 + 803f574: 296dd104 addi r5,r5,-18620 + 803f578: e13ee217 ldw r4,-1144(fp) + 803f57c: 80273900 call 8027390 + } + + return(0); + 803f580: 0005883a mov r2,zero +} /* end main() */ + 803f584: e037883a mov sp,fp + 803f588: dfc00117 ldw ra,4(sp) + 803f58c: df000017 ldw fp,0(sp) + 803f590: dec00204 addi sp,sp,8 + 803f594: f800283a ret + +0803f598 : + * RETURNS: + */ + +int +init_memdev(void) +{ + 803f598: deffff04 addi sp,sp,-4 + 803f59c: df000015 stw fp,0(sp) + 803f5a0: d839883a mov fp,sp + /* add our IO pointer to master list */ + mdio.next = vfsystems; + 803f5a4: d0e0a117 ldw r3,-32124(gp) + 803f5a8: 00820174 movhi r2,2053 + 803f5ac: 10f25915 stw r3,-13980(r2) + vfsystems = &mdio; + 803f5b0: 00820174 movhi r2,2053 + 803f5b4: 10b25904 addi r2,r2,-13980 + 803f5b8: d0a0a115 stw r2,-32124(gp) + + /* add the memory device files to vfs list */ + mdlist[0].next = vfsfiles; + 803f5bc: d0e0a317 ldw r3,-32116(gp) + 803f5c0: 00820174 movhi r2,2053 + 803f5c4: 10f26215 stw r3,-13944(r2) + vfsfiles = &mdlist[3]; + 803f5c8: 00820174 movhi r2,2053 + 803f5cc: 10b28304 addi r2,r2,-13812 + 803f5d0: d0a0a315 stw r2,-32116(gp) + + return 0; + 803f5d4: 0005883a mov r2,zero +} + 803f5d8: e037883a mov sp,fp + 803f5dc: df000017 ldw fp,0(sp) + 803f5e0: dec00104 addi sp,sp,4 + 803f5e4: f800283a ret + +0803f5e8 : + * RETURNS: + */ + +VFILE* +md_fopen(char * name, char * mode) +{ + 803f5e8: defffd04 addi sp,sp,-12 + 803f5ec: df000215 stw fp,8(sp) + 803f5f0: df000204 addi fp,sp,8 + 803f5f4: e13fff15 stw r4,-4(fp) + 803f5f8: e17ffe15 stw r5,-8(fp) + USE_ARG(mode); + USE_ARG(name); + return NULL; + 803f5fc: 0005883a mov r2,zero +} + 803f600: e037883a mov sp,fp + 803f604: df000017 ldw fp,0(sp) + 803f608: dec00104 addi sp,sp,4 + 803f60c: f800283a ret + +0803f610 : + * RETURNS: + */ + +void +md_fclose(VFILE * vfd) +{ + 803f610: defffe04 addi sp,sp,-8 + 803f614: df000115 stw fp,4(sp) + 803f618: df000104 addi fp,sp,4 + 803f61c: e13fff15 stw r4,-4(fp) + USE_ARG(vfd); +} + 803f620: 0001883a nop + 803f624: e037883a mov sp,fp + 803f628: df000017 ldw fp,0(sp) + 803f62c: dec00104 addi sp,sp,4 + 803f630: f800283a ret + +0803f634 : + * RETURNS: + */ + +int +md_fread(char * buf, unsigned size, unsigned items, VFILE * vfd) +{ + 803f634: defff704 addi sp,sp,-36 + 803f638: dfc00815 stw ra,32(sp) + 803f63c: df000715 stw fp,28(sp) + 803f640: df000704 addi fp,sp,28 + 803f644: e13ffc15 stw r4,-16(fp) + 803f648: e17ffb15 stw r5,-20(fp) + 803f64c: e1bffa15 stw r6,-24(fp) + 803f650: e1fff915 stw r7,-28(fp) + u_long bcount; /* number of bytes put in caller's buffer */ + u_long location; /* current offset into file */ + unsigned long file_size = MEMDEV_SIZE; + 803f654: 00800834 movhi r2,32 + 803f658: e0bffe15 stw r2,-8(fp) + if(vfd && vfd->file) + 803f65c: e0bff917 ldw r2,-28(fp) + 803f660: 10000726 beq r2,zero,803f680 + 803f664: e0bff917 ldw r2,-28(fp) + 803f668: 10800117 ldw r2,4(r2) + 803f66c: 10000426 beq r2,zero,803f680 + { + file_size = vfd->file->real_size; + 803f670: e0bff917 ldw r2,-28(fp) + 803f674: 10800117 ldw r2,4(r2) + 803f678: 10800717 ldw r2,28(r2) + 803f67c: e0bffe15 stw r2,-8(fp) +#ifdef SEG16_16 /* 16-bit x86 must include segment. */ + if(vfd->cmploc == (u_char*)0xFFFFFFFF) /* at EOF */ + return 0; + location = (u_long)(((char huge *)vfd->cmploc) - ((char huge *)vfd->file->data)); +#else + location = (u_long)(vfd->cmploc - vfd->file->data); + 803f680: e0bff917 ldw r2,-28(fp) + 803f684: 10c00217 ldw r3,8(r2) + 803f688: e0bff917 ldw r2,-28(fp) + 803f68c: 10800117 ldw r2,4(r2) + 803f690: 10800617 ldw r2,24(r2) + 803f694: 1885c83a sub r2,r3,r2 + 803f698: e0bffd15 stw r2,-12(fp) +#endif /* SEG16_16 */ + + bcount = (items * (u_long)size); /* number of bytes to transfer */ + 803f69c: e0fffa17 ldw r3,-24(fp) + 803f6a0: e0bffb17 ldw r2,-20(fp) + 803f6a4: 1885383a mul r2,r3,r2 + 803f6a8: e0bfff15 stw r2,-4(fp) + + /* if near end of memory, trim read count accordingly */ + if ((location + bcount) > file_size) + 803f6ac: e0fffd17 ldw r3,-12(fp) + 803f6b0: e0bfff17 ldw r2,-4(fp) + 803f6b4: 1885883a add r2,r3,r2 + 803f6b8: e0fffe17 ldw r3,-8(fp) + 803f6bc: 1880042e bgeu r3,r2,803f6d0 + bcount = ((u_long)file_size - location); + 803f6c0: e0fffe17 ldw r3,-8(fp) + 803f6c4: e0bffd17 ldw r2,-12(fp) + 803f6c8: 1885c83a sub r2,r3,r2 + 803f6cc: e0bfff15 stw r2,-4(fp) + + /* trap bogus size items and end-of-x86 memory conditions */ + if((location >= file_size) || + 803f6d0: e0fffd17 ldw r3,-12(fp) + 803f6d4: e0bffe17 ldw r2,-8(fp) + 803f6d8: 1880052e bgeu r3,r2,803f6f0 + (bcount & 0xFFFF0000) || + 803f6dc: e0bfff17 ldw r2,-4(fp) + 803f6e0: 10bfffec andhi r2,r2,65535 + if((location >= file_size) || + 803f6e4: 1000021e bne r2,zero,803f6f0 + (bcount & 0xFFFF0000) || + 803f6e8: e0bfff17 ldw r2,-4(fp) + 803f6ec: 1000021e bne r2,zero,803f6f8 + (bcount == 0)) + { + return 0; + 803f6f0: 0005883a mov r2,zero + 803f6f4: 00002006 br 803f778 + /* Use VF_NODATA if memory devices have a size, but no + data. This can be used to measure file read speed + without introducing an undefined data copy. */ + /* VF_NODATA is defined in ../h/vfsfiles.h */ + + if (!(vfd->file->flags & VF_NODATA)) + 803f6f8: e0bff917 ldw r2,-28(fp) + 803f6fc: 10800117 ldw r2,4(r2) + 803f700: 1080058b ldhu r2,22(r2) + 803f704: 10bfffcc andi r2,r2,65535 + 803f708: 10a0001c xori r2,r2,32768 + 803f70c: 10a00004 addi r2,r2,-32768 + 803f710: 10001016 blt r2,zero,803f754 + { + if (vfd->file->name[0] == 'm') /* memory device */ + 803f714: e0bff917 ldw r2,-28(fp) + 803f718: 10800117 ldw r2,4(r2) + 803f71c: 10800103 ldbu r2,4(r2) + 803f720: 10803fcc andi r2,r2,255 + 803f724: 1080201c xori r2,r2,128 + 803f728: 10bfe004 addi r2,r2,-128 + 803f72c: 10801b58 cmpnei r2,r2,109 + 803f730: 1000081e bne r2,zero,803f754 + MEMCPY(buf, vfd->cmploc + MEMDEV_BASE, (unsigned)bcount); + 803f734: e0bff917 ldw r2,-28(fp) + 803f738: 10c00217 ldw r3,8(r2) + 803f73c: 00800834 movhi r2,32 + 803f740: 1885883a add r2,r3,r2 + 803f744: e1bfff17 ldw r6,-4(fp) + 803f748: 100b883a mov r5,r2 + 803f74c: e13ffc17 ldw r4,-16(fp) + 803f750: 80086b80 call 80086b8 + vfd->cmploc = (u_char *)cp; + else /* read wrapped memory, set pointer to EOF value */ + vfd->cmploc = (u_char*)(0xFFFFFFFF); /* EOF */ + } +#else + vfd->cmploc += bcount; /* adjust location */ + 803f754: e0bff917 ldw r2,-28(fp) + 803f758: 10c00217 ldw r3,8(r2) + 803f75c: e0bfff17 ldw r2,-4(fp) + 803f760: 1887883a add r3,r3,r2 + 803f764: e0bff917 ldw r2,-28(fp) + 803f768: 10c00215 stw r3,8(r2) +#endif + + return ((int)bcount/size); + 803f76c: e17ffb17 ldw r5,-20(fp) + 803f770: e13fff17 ldw r4,-4(fp) + 803f774: 800cff80 call 800cff8 <__udivsi3> +} + 803f778: e037883a mov sp,fp + 803f77c: dfc00117 ldw ra,4(sp) + 803f780: df000017 ldw fp,0(sp) + 803f784: dec00204 addi sp,sp,8 + 803f788: f800283a ret + +0803f78c : + * RETURNS: + */ + +int +md_fwrite(char * buf, unsigned size, unsigned items, VFILE * vfd) +{ + 803f78c: defffb04 addi sp,sp,-20 + 803f790: df000415 stw fp,16(sp) + 803f794: df000404 addi fp,sp,16 + 803f798: e13fff15 stw r4,-4(fp) + 803f79c: e17ffe15 stw r5,-8(fp) + 803f7a0: e1bffd15 stw r6,-12(fp) + 803f7a4: e1fffc15 stw r7,-16(fp) + if (vfd->file->name[0] == 'm') /* memory device */ + 803f7a8: e0bffc17 ldw r2,-16(fp) + 803f7ac: 10800117 ldw r2,4(r2) + 803f7b0: 10800103 ldbu r2,4(r2) + 803f7b4: 10803fcc andi r2,r2,255 + 803f7b8: 1080201c xori r2,r2,128 + 803f7bc: 10bfe004 addi r2,r2,-128 + 803f7c0: 10801b58 cmpnei r2,r2,109 + 803f7c4: 1000021e bne r2,zero,803f7d0 + return 0; /* not writable device */ + 803f7c8: 0005883a mov r2,zero + 803f7cc: 00000906 br 803f7f4 + + vfd->cmploc += (items * size); /* adjust location */ + 803f7d0: e0bffc17 ldw r2,-16(fp) + 803f7d4: 10c00217 ldw r3,8(r2) + 803f7d8: e13ffd17 ldw r4,-12(fp) + 803f7dc: e0bffe17 ldw r2,-8(fp) + 803f7e0: 2085383a mul r2,r4,r2 + 803f7e4: 1887883a add r3,r3,r2 + 803f7e8: e0bffc17 ldw r2,-16(fp) + 803f7ec: 10c00215 stw r3,8(r2) + + USE_ARG(buf); /* supress compiler warnings */ + + return (items); + 803f7f0: e0bffd17 ldw r2,-12(fp) +} + 803f7f4: e037883a mov sp,fp + 803f7f8: df000017 ldw fp,0(sp) + 803f7fc: dec00104 addi sp,sp,4 + 803f800: f800283a ret + +0803f804 : + * RETURNS: + */ + +int +md_fseek(VFILE * vfd, long offset, int mode) +{ + 803f804: defffc04 addi sp,sp,-16 + 803f808: df000315 stw fp,12(sp) + 803f80c: df000304 addi fp,sp,12 + 803f810: e13fff15 stw r4,-4(fp) + 803f814: e17ffe15 stw r5,-8(fp) + 803f818: e1bffd15 stw r6,-12(fp) + USE_ARG(vfd); /* supress compiler warnings */ + USE_ARG(offset); + USE_ARG(mode); + return 0; + 803f81c: 0005883a mov r2,zero +} + 803f820: e037883a mov sp,fp + 803f824: df000017 ldw fp,0(sp) + 803f828: dec00104 addi sp,sp,4 + 803f82c: f800283a ret + +0803f830 : + * RETURNS: + */ + +long +md_ftell(VFILE * vfd) +{ + 803f830: defffe04 addi sp,sp,-8 + 803f834: df000115 stw fp,4(sp) + 803f838: df000104 addi fp,sp,4 + 803f83c: e13fff15 stw r4,-4(fp) + USE_ARG(vfd); /* supress compiler warnings */ + return MEMDEV_SIZE; + 803f840: 00800834 movhi r2,32 +} + 803f844: e037883a mov sp,fp + 803f848: df000017 ldw fp,0(sp) + 803f84c: dec00104 addi sp,sp,4 + 803f850: f800283a ret + +0803f854 : + * RETURNS: + */ + +int +md_fgetc(VFILE * vfd) +{ + 803f854: defffc04 addi sp,sp,-16 + 803f858: df000315 stw fp,12(sp) + 803f85c: df000304 addi fp,sp,12 + 803f860: e13ffd15 stw r4,-12(fp) + unsigned location; /* current offset infile */ + int retval = 0; + 803f864: e03fff15 stw zero,-4(fp) + + location = vfd->cmploc - vfd->file->data; + 803f868: e0bffd17 ldw r2,-12(fp) + 803f86c: 10c00217 ldw r3,8(r2) + 803f870: e0bffd17 ldw r2,-12(fp) + 803f874: 10800117 ldw r2,4(r2) + 803f878: 10800617 ldw r2,24(r2) + 803f87c: 1885c83a sub r2,r3,r2 + 803f880: e0bffe15 stw r2,-8(fp) + if (location >= vfd->file->real_size) /* at end of file? */ + 803f884: e0bffd17 ldw r2,-12(fp) + 803f888: 10800117 ldw r2,4(r2) + 803f88c: 10800717 ldw r2,28(r2) + 803f890: e0fffe17 ldw r3,-8(fp) + 803f894: 18800236 bltu r3,r2,803f8a0 + return EOF; + 803f898: 00bfffc4 movi r2,-1 + 803f89c: 00001a06 br 803f908 + + if (!(vfd->file->flags & VF_NODATA)) + 803f8a0: e0bffd17 ldw r2,-12(fp) + 803f8a4: 10800117 ldw r2,4(r2) + 803f8a8: 1080058b ldhu r2,22(r2) + 803f8ac: 10bfffcc andi r2,r2,65535 + 803f8b0: 10a0001c xori r2,r2,32768 + 803f8b4: 10a00004 addi r2,r2,-32768 + 803f8b8: 10000d16 blt r2,zero,803f8f0 + { + if (vfd->file->name[0] == 'm') /* memory device */ + 803f8bc: e0bffd17 ldw r2,-12(fp) + 803f8c0: 10800117 ldw r2,4(r2) + 803f8c4: 10800103 ldbu r2,4(r2) + 803f8c8: 10803fcc andi r2,r2,255 + 803f8cc: 1080201c xori r2,r2,128 + 803f8d0: 10bfe004 addi r2,r2,-128 + 803f8d4: 10801b58 cmpnei r2,r2,109 + 803f8d8: 1000051e bne r2,zero,803f8f0 + retval = (int)(*vfd->cmploc) & 0xFF ; + 803f8dc: e0bffd17 ldw r2,-12(fp) + 803f8e0: 10800217 ldw r2,8(r2) + 803f8e4: 10800003 ldbu r2,0(r2) + 803f8e8: 10803fcc andi r2,r2,255 + 803f8ec: e0bfff15 stw r2,-4(fp) + } + + /* else for null device or files without data, + use whatever is in retval */ + + vfd->cmploc++; /* adjust location */ + 803f8f0: e0bffd17 ldw r2,-12(fp) + 803f8f4: 10800217 ldw r2,8(r2) + 803f8f8: 10c00044 addi r3,r2,1 + 803f8fc: e0bffd17 ldw r2,-12(fp) + 803f900: 10c00215 stw r3,8(r2) + return retval; + 803f904: e0bfff17 ldw r2,-4(fp) +} + 803f908: e037883a mov sp,fp + 803f90c: df000017 ldw fp,0(sp) + 803f910: dec00104 addi sp,sp,4 + 803f914: f800283a ret + +0803f918 : + * RETURNS: + */ + +int +md_unlink(char * filename) +{ + 803f918: defffe04 addi sp,sp,-8 + 803f91c: df000115 stw fp,4(sp) + 803f920: df000104 addi fp,sp,4 + 803f924: e13fff15 stw r4,-4(fp) + USE_ARG(filename); /* supress compiler warnings */ + return 0; + 803f928: 0005883a mov r2,zero +} + 803f92c: e037883a mov sp,fp + 803f930: df000017 ldw fp,0(sp) + 803f934: dec00104 addi sp,sp,4 + 803f938: f800283a ret + +0803f93c : + +char * +parse_ipad(ip_addr * ipout, /* pointer to IP address to set */ + unsigned * sbits, /* default subnet bit number */ + char * stringin) /* buffer with ascii to parse */ +{ + 803f93c: defff604 addi sp,sp,-40 + 803f940: dfc00915 stw ra,36(sp) + 803f944: df000815 stw fp,32(sp) + 803f948: df000804 addi fp,sp,32 + 803f94c: e13ffa15 stw r4,-24(fp) + 803f950: e17ff915 stw r5,-28(fp) + 803f954: e1bff815 stw r6,-32(fp) + char * cp; + int dots = 0; /* periods imbedded in input string */ + 803f958: e03ffe15 stw zero,-8(fp) + union + { + u_char c[4]; + u_long l; + } retval; + char * toobig = "each number must be less than 255"; + 803f95c: 00820174 movhi r2,2053 + 803f960: 10ade204 addi r2,r2,-18552 + 803f964: e0bffd15 stw r2,-12(fp) + + cp = stringin; + 803f968: e0bff817 ldw r2,-32(fp) + 803f96c: e0bfff15 stw r2,-4(fp) + while (*cp) + 803f970: 00002506 br 803fa08 + { + if (*cp > '9' || *cp < '.' || *cp == '/') + 803f974: e0bfff17 ldw r2,-4(fp) + 803f978: 10800003 ldbu r2,0(r2) + 803f97c: 10803fcc andi r2,r2,255 + 803f980: 1080201c xori r2,r2,128 + 803f984: 10bfe004 addi r2,r2,-128 + 803f988: 10800e88 cmpgei r2,r2,58 + 803f98c: 10000e1e bne r2,zero,803f9c8 + 803f990: e0bfff17 ldw r2,-4(fp) + 803f994: 10800003 ldbu r2,0(r2) + 803f998: 10803fcc andi r2,r2,255 + 803f99c: 1080201c xori r2,r2,128 + 803f9a0: 10bfe004 addi r2,r2,-128 + 803f9a4: 10800b90 cmplti r2,r2,46 + 803f9a8: 1000071e bne r2,zero,803f9c8 + 803f9ac: e0bfff17 ldw r2,-4(fp) + 803f9b0: 10800003 ldbu r2,0(r2) + 803f9b4: 10803fcc andi r2,r2,255 + 803f9b8: 1080201c xori r2,r2,128 + 803f9bc: 10bfe004 addi r2,r2,-128 + 803f9c0: 10800bd8 cmpnei r2,r2,47 + 803f9c4: 1000031e bne r2,zero,803f9d4 + return("all chars must be digits (0-9) or dots (.)"); + 803f9c8: 00820174 movhi r2,2053 + 803f9cc: 10adeb04 addi r2,r2,-18516 + 803f9d0: 00009406 br 803fc24 + if (*cp == '.')dots++; + 803f9d4: e0bfff17 ldw r2,-4(fp) + 803f9d8: 10800003 ldbu r2,0(r2) + 803f9dc: 10803fcc andi r2,r2,255 + 803f9e0: 1080201c xori r2,r2,128 + 803f9e4: 10bfe004 addi r2,r2,-128 + 803f9e8: 10800b98 cmpnei r2,r2,46 + 803f9ec: 1000031e bne r2,zero,803f9fc + 803f9f0: e0bffe17 ldw r2,-8(fp) + 803f9f4: 10800044 addi r2,r2,1 + 803f9f8: e0bffe15 stw r2,-8(fp) + cp++; + 803f9fc: e0bfff17 ldw r2,-4(fp) + 803fa00: 10800044 addi r2,r2,1 + 803fa04: e0bfff15 stw r2,-4(fp) + while (*cp) + 803fa08: e0bfff17 ldw r2,-4(fp) + 803fa0c: 10800003 ldbu r2,0(r2) + 803fa10: 10803fcc andi r2,r2,255 + 803fa14: 1080201c xori r2,r2,128 + 803fa18: 10bfe004 addi r2,r2,-128 + 803fa1c: 103fd51e bne r2,zero,803f974 + } + + if ( dots < 1 || dots > 3 ) + 803fa20: e0bffe17 ldw r2,-8(fp) + 803fa24: 0080030e bge zero,r2,803fa34 + 803fa28: e0bffe17 ldw r2,-8(fp) + 803fa2c: 10800110 cmplti r2,r2,4 + 803fa30: 1000031e bne r2,zero,803fa40 + return("string must contain 1 - 3 dots (.)"); + 803fa34: 00820174 movhi r2,2053 + 803fa38: 10adf604 addi r2,r2,-18472 + 803fa3c: 00007906 br 803fc24 + + cp = stringin; + 803fa40: e0bff817 ldw r2,-32(fp) + 803fa44: e0bfff15 stw r2,-4(fp) + if ((number = atoi(cp)) > 255) /* set net number */ + 803fa48: e13fff17 ldw r4,-4(fp) + 803fa4c: 8042aa40 call 8042aa4 + 803fa50: e0bffc15 stw r2,-16(fp) + 803fa54: e0bffc17 ldw r2,-16(fp) + 803fa58: 10804010 cmplti r2,r2,256 + 803fa5c: 1000021e bne r2,zero,803fa68 + return(toobig); + 803fa60: e0bffd17 ldw r2,-12(fp) + 803fa64: 00006f06 br 803fc24 + + retval.c[0] = (u_char)number; + 803fa68: e0bffc17 ldw r2,-16(fp) + 803fa6c: e0bffb05 stb r2,-20(fp) + + while (*cp != '.')cp++; /* find dot (end of number) */ + 803fa70: 00000306 br 803fa80 + 803fa74: e0bfff17 ldw r2,-4(fp) + 803fa78: 10800044 addi r2,r2,1 + 803fa7c: e0bfff15 stw r2,-4(fp) + 803fa80: e0bfff17 ldw r2,-4(fp) + 803fa84: 10800003 ldbu r2,0(r2) + 803fa88: 10803fcc andi r2,r2,255 + 803fa8c: 1080201c xori r2,r2,128 + 803fa90: 10bfe004 addi r2,r2,-128 + 803fa94: 10800b98 cmpnei r2,r2,46 + 803fa98: 103ff61e bne r2,zero,803fa74 + cp++; /* point past dot */ + 803fa9c: e0bfff17 ldw r2,-4(fp) + 803faa0: 10800044 addi r2,r2,1 + 803faa4: e0bfff15 stw r2,-4(fp) + + if (dots == 1 || dots == 2) retval.c[1] = 0; + 803faa8: e0bffe17 ldw r2,-8(fp) + 803faac: 10800060 cmpeqi r2,r2,1 + 803fab0: 1000031e bne r2,zero,803fac0 + 803fab4: e0bffe17 ldw r2,-8(fp) + 803fab8: 10800098 cmpnei r2,r2,2 + 803fabc: 1000021e bne r2,zero,803fac8 + 803fac0: e03ffb45 stb zero,-19(fp) + 803fac4: 00001806 br 803fb28 + else + { + number = atoi(cp); + 803fac8: e13fff17 ldw r4,-4(fp) + 803facc: 8042aa40 call 8042aa4 + 803fad0: e0bffc15 stw r2,-16(fp) + while (*cp != '.')cp++; /* find dot (end of number) */ + 803fad4: 00000306 br 803fae4 + 803fad8: e0bfff17 ldw r2,-4(fp) + 803fadc: 10800044 addi r2,r2,1 + 803fae0: e0bfff15 stw r2,-4(fp) + 803fae4: e0bfff17 ldw r2,-4(fp) + 803fae8: 10800003 ldbu r2,0(r2) + 803faec: 10803fcc andi r2,r2,255 + 803faf0: 1080201c xori r2,r2,128 + 803faf4: 10bfe004 addi r2,r2,-128 + 803faf8: 10800b98 cmpnei r2,r2,46 + 803fafc: 103ff61e bne r2,zero,803fad8 + cp++; /* point past dot */ + 803fb00: e0bfff17 ldw r2,-4(fp) + 803fb04: 10800044 addi r2,r2,1 + 803fb08: e0bfff15 stw r2,-4(fp) + if (number > 255) return(toobig); + 803fb0c: e0bffc17 ldw r2,-16(fp) + 803fb10: 10804010 cmplti r2,r2,256 + 803fb14: 1000021e bne r2,zero,803fb20 + 803fb18: e0bffd17 ldw r2,-12(fp) + 803fb1c: 00004106 br 803fc24 + retval.c[1] = (u_char)number; + 803fb20: e0bffc17 ldw r2,-16(fp) + 803fb24: e0bffb45 stb r2,-19(fp) + } + + if (dots == 1) retval.c[2] = 0; + 803fb28: e0bffe17 ldw r2,-8(fp) + 803fb2c: 10800058 cmpnei r2,r2,1 + 803fb30: 1000021e bne r2,zero,803fb3c + 803fb34: e03ffb85 stb zero,-18(fp) + 803fb38: 00001806 br 803fb9c + else + { + number = atoi(cp); + 803fb3c: e13fff17 ldw r4,-4(fp) + 803fb40: 8042aa40 call 8042aa4 + 803fb44: e0bffc15 stw r2,-16(fp) + while (*cp != '.')cp++; /* find dot (end of number) */ + 803fb48: 00000306 br 803fb58 + 803fb4c: e0bfff17 ldw r2,-4(fp) + 803fb50: 10800044 addi r2,r2,1 + 803fb54: e0bfff15 stw r2,-4(fp) + 803fb58: e0bfff17 ldw r2,-4(fp) + 803fb5c: 10800003 ldbu r2,0(r2) + 803fb60: 10803fcc andi r2,r2,255 + 803fb64: 1080201c xori r2,r2,128 + 803fb68: 10bfe004 addi r2,r2,-128 + 803fb6c: 10800b98 cmpnei r2,r2,46 + 803fb70: 103ff61e bne r2,zero,803fb4c + cp++; /* point past dot */ + 803fb74: e0bfff17 ldw r2,-4(fp) + 803fb78: 10800044 addi r2,r2,1 + 803fb7c: e0bfff15 stw r2,-4(fp) + if (number > 255) return(toobig); + 803fb80: e0bffc17 ldw r2,-16(fp) + 803fb84: 10804010 cmplti r2,r2,256 + 803fb88: 1000021e bne r2,zero,803fb94 + 803fb8c: e0bffd17 ldw r2,-12(fp) + 803fb90: 00002406 br 803fc24 + retval.c[2] = (u_char)number; + 803fb94: e0bffc17 ldw r2,-16(fp) + 803fb98: e0bffb85 stb r2,-18(fp) + } + + if ((number = atoi(cp)) > 255) + 803fb9c: e13fff17 ldw r4,-4(fp) + 803fba0: 8042aa40 call 8042aa4 + 803fba4: e0bffc15 stw r2,-16(fp) + 803fba8: e0bffc17 ldw r2,-16(fp) + 803fbac: 10804010 cmplti r2,r2,256 + 803fbb0: 1000021e bne r2,zero,803fbbc + return(toobig); + 803fbb4: e0bffd17 ldw r2,-12(fp) + 803fbb8: 00001a06 br 803fc24 + retval.c[3] = (u_char)number; + 803fbbc: e0bffc17 ldw r2,-16(fp) + 803fbc0: e0bffbc5 stb r2,-17(fp) + + if (retval.c[0] < 128) *sbits = 8; + 803fbc4: e0bffb03 ldbu r2,-20(fp) + 803fbc8: 10803fcc andi r2,r2,255 + 803fbcc: 1080201c xori r2,r2,128 + 803fbd0: 10bfe004 addi r2,r2,-128 + 803fbd4: 10000416 blt r2,zero,803fbe8 + 803fbd8: e0bff917 ldw r2,-28(fp) + 803fbdc: 00c00204 movi r3,8 + 803fbe0: 10c00015 stw r3,0(r2) + 803fbe4: 00000b06 br 803fc14 + else if(retval.c[0] < 192) *sbits = 16; + 803fbe8: e0bffb03 ldbu r2,-20(fp) + 803fbec: 10803fcc andi r2,r2,255 + 803fbf0: 10803028 cmpgeui r2,r2,192 + 803fbf4: 1000041e bne r2,zero,803fc08 + 803fbf8: e0bff917 ldw r2,-28(fp) + 803fbfc: 00c00404 movi r3,16 + 803fc00: 10c00015 stw r3,0(r2) + 803fc04: 00000306 br 803fc14 + else *sbits = 24; + 803fc08: e0bff917 ldw r2,-28(fp) + 803fc0c: 00c00604 movi r3,24 + 803fc10: 10c00015 stw r3,0(r2) + + *ipout = retval.l; /* everything went OK, return number */ + 803fc14: e0fffb17 ldw r3,-20(fp) + 803fc18: e0bffa17 ldw r2,-24(fp) + 803fc1c: 10c00015 stw r3,0(r2) + return(NULL); /* return OK code (no error string) */ + 803fc20: 0005883a mov r2,zero +} + 803fc24: e037883a mov sp,fp + 803fc28: dfc00117 ldw ra,4(sp) + 803fc2c: df000017 ldw fp,0(sp) + 803fc30: dec00204 addi sp,sp,8 + 803fc34: f800283a ret + +0803fc38 : + * RETURNS: u_long ipaddr + */ + +u_long +inet_addr(char FAR * str) +{ + 803fc38: defffb04 addi sp,sp,-20 + 803fc3c: dfc00415 stw ra,16(sp) + 803fc40: df000315 stw fp,12(sp) + 803fc44: df000304 addi fp,sp,12 + 803fc48: e13ffd15 stw r4,-12(fp) + * we need to make the conversion. Usually this function will be + * used for debugging, so I think we can bear the STRCPY overhead. + */ + static char nearBuf[30]; + + strcpy((char FAR *)nearBuf,str); + 803fc4c: e17ffd17 ldw r5,-12(fp) + 803fc50: 01020174 movhi r4,2053 + 803fc54: 21338304 addi r4,r4,-12788 + 803fc58: 8042f600 call 8042f60 + if ( parse_ipad(&ipaddr,&bits,nearBuf) == NULL ) + 803fc5c: e0fffe04 addi r3,fp,-8 + 803fc60: e0bfff04 addi r2,fp,-4 + 803fc64: 01820174 movhi r6,2053 + 803fc68: 31b38304 addi r6,r6,-12788 + 803fc6c: 180b883a mov r5,r3 + 803fc70: 1009883a mov r4,r2 + 803fc74: 803f93c0 call 803f93c + 803fc78: 1000021e bne r2,zero,803fc84 + { + return ipaddr ; + 803fc7c: e0bfff17 ldw r2,-4(fp) + 803fc80: 00000106 br 803fc88 + } + else + { + return (u_long)NULL ; + 803fc84: 0005883a mov r2,zero + } +} + 803fc88: e037883a mov sp,fp + 803fc8c: dfc00117 ldw ra,4(sp) + 803fc90: df000017 ldw fp,0(sp) + 803fc94: dec00204 addi sp,sp,8 + 803fc98: f800283a ret + +0803fc9c : + * RETURNS: character 0-9 or A-F + */ + +char +hextoa(int val) +{ + 803fc9c: defffe04 addi sp,sp,-8 + 803fca0: df000115 stw fp,4(sp) + 803fca4: df000104 addi fp,sp,4 + 803fca8: e13fff15 stw r4,-4(fp) + val &= 0x0f; + 803fcac: e0bfff17 ldw r2,-4(fp) + 803fcb0: 108003cc andi r2,r2,15 + 803fcb4: e0bfff15 stw r2,-4(fp) + if(val < 10) + 803fcb8: e0bfff17 ldw r2,-4(fp) + 803fcbc: 10800288 cmpgei r2,r2,10 + 803fcc0: 1000031e bne r2,zero,803fcd0 + return (char)(val + '0'); + 803fcc4: e0bfff17 ldw r2,-4(fp) + 803fcc8: 10800c04 addi r2,r2,48 + 803fccc: 00000206 br 803fcd8 + else + return (char)(val + 55); /* converts 10-15 -> "A-F" */ + 803fcd0: e0bfff17 ldw r2,-4(fp) + 803fcd4: 10800dc4 addi r2,r2,55 +} + 803fcd8: e037883a mov sp,fp + 803fcdc: df000017 ldw fp,0(sp) + 803fce0: dec00104 addi sp,sp,4 + 803fce4: f800283a ret + +0803fce8 : + +char * pton_error = ""; + +int +inet_pton(int af, const char * src, void * dst) +{ + 803fce8: defff804 addi sp,sp,-32 + 803fcec: dfc00715 stw ra,28(sp) + 803fcf0: df000615 stw fp,24(sp) + 803fcf4: df000604 addi fp,sp,24 + 803fcf8: e13ffc15 stw r4,-16(fp) + 803fcfc: e17ffb15 stw r5,-20(fp) + 803fd00: e1bffa15 stw r6,-24(fp) + int words; /* count of words written to dest */ +#endif + +#if defined(IP_V4) || defined(MINI_IP) + /* RFC 2133 wants us to support both types of address */ + if(af == AF_INET) /* wants a v4 address */ + 803fd04: e0bffc17 ldw r2,-16(fp) + 803fd08: 10800098 cmpnei r2,r2,2 + 803fd0c: 1000151e bne r2,zero,803fd64 + { + u_long ip4addr; + unsigned sbits; + char * err; + + err = parse_ipad(&ip4addr, &sbits, (char *) src); + 803fd10: e0fffd04 addi r3,fp,-12 + 803fd14: e0bffe04 addi r2,fp,-8 + 803fd18: e1bffb17 ldw r6,-20(fp) + 803fd1c: 180b883a mov r5,r3 + 803fd20: 1009883a mov r4,r2 + 803fd24: 803f93c0 call 803f93c + 803fd28: e0bfff15 stw r2,-4(fp) + if(err == NULL) + 803fd2c: e0bfff17 ldw r2,-4(fp) + 803fd30: 1000071e bne r2,zero,803fd50 + { + /* copy the parsed address into caller's buffer, and + * return success + */ + MEMCPY(dst, &ip4addr, sizeof (u_long)); + 803fd34: e0bffe04 addi r2,fp,-8 + 803fd38: 01800104 movi r6,4 + 803fd3c: 100b883a mov r5,r2 + 803fd40: e13ffa17 ldw r4,-24(fp) + 803fd44: 80086b80 call 80086b8 + return 0; + 803fd48: 0005883a mov r2,zero + 803fd4c: 00000606 br 803fd68 + } + else + { + /* return failure */ + pton_error = "IPv4 address parse failure"; + 803fd50: 00820174 movhi r2,2053 + 803fd54: 10ae0004 addi r2,r2,-18432 + 803fd58: d0a03315 stw r2,-32564(gp) + return 1; + 803fd5c: 00800044 movi r2,1 + 803fd60: 00000106 br 803fd68 + pton_error = "too short - missing colon?"; + return 1; + } + +#endif /* IP_V6 */ + return 0; + 803fd64: 0005883a mov r2,zero +} + 803fd68: e037883a mov sp,fp + 803fd6c: dfc00117 ldw ra,4(sp) + 803fd70: df000017 ldw fp,0(sp) + 803fd74: dec00204 addi sp,sp,8 + 803fd78: f800283a ret + +0803fd7c : + * address output (40 bytes). + */ + +const char * +inet_ntop(int af, const void *addr, char *str, size_t size) +{ + 803fd7c: defff804 addi sp,sp,-32 + 803fd80: dfc00715 stw ra,28(sp) + 803fd84: df000615 stw fp,24(sp) + 803fd88: df000604 addi fp,sp,24 + 803fd8c: e13ffd15 stw r4,-12(fp) + 803fd90: e17ffc15 stw r5,-16(fp) + 803fd94: e1bffb15 stw r6,-20(fp) + 803fd98: e1fffa15 stw r7,-24(fp) + char *cp; + +#if defined(IP_V4) || defined(MINI_IP) + if (af == AF_INET) + 803fd9c: e0bffd17 ldw r2,-12(fp) + 803fda0: 10800098 cmpnei r2,r2,2 + 803fda4: 1000101e bne r2,zero,803fde8 + { + u_long ip4addr; + + ip4addr = *(u_long*)addr; + 803fda8: e0bffc17 ldw r2,-16(fp) + 803fdac: 10800017 ldw r2,0(r2) + 803fdb0: e0bfff15 stw r2,-4(fp) + cp = print_ipad(ip4addr); + 803fdb4: e13fff17 ldw r4,-4(fp) + 803fdb8: 8026fbc0 call 8026fbc + 803fdbc: e0bffe15 stw r2,-8(fp) + if (strlen(cp) < size) + 803fdc0: e13ffe17 ldw r4,-8(fp) + 803fdc4: 8002dac0 call 8002dac + 803fdc8: 1007883a mov r3,r2 + 803fdcc: e0bffa17 ldw r2,-24(fp) + 803fdd0: 1880052e bgeu r3,r2,803fde8 + { + strcpy(str, cp); + 803fdd4: e17ffe17 ldw r5,-8(fp) + 803fdd8: e13ffb17 ldw r4,-20(fp) + 803fddc: 8042f600 call 8042f60 + return (str); + 803fde0: e0bffb17 ldw r2,-20(fp) + 803fde4: 00000106 br 803fdec + return (str); + } + } +#endif + + return ((const char *)NULL); + 803fde8: 0005883a mov r2,zero +} + 803fdec: e037883a mov sp,fp + 803fdf0: dfc00117 ldw ra,4(sp) + 803fdf4: df000017 ldw fp,0(sp) + 803fdf8: dec00204 addi sp,sp,8 + 803fdfc: f800283a ret + +0803fe00 : + * + * RETURNS: Pointer to string with the address in readable format. + */ + +char * print46_addr(struct sockaddr *ipaddr) +{ + 803fe00: defffc04 addi sp,sp,-16 + 803fe04: dfc00315 stw ra,12(sp) + 803fe08: df000215 stw fp,8(sp) + 803fe0c: df000204 addi fp,sp,8 + 803fe10: e13ffe15 stw r4,-8(fp) + if (ipaddr->sa_family == AF_INET) + 803fe14: e0bffe17 ldw r2,-8(fp) + 803fe18: 1080000b ldhu r2,0(r2) + 803fe1c: 10bfffcc andi r2,r2,65535 + 803fe20: 10800098 cmpnei r2,r2,2 + 803fe24: 1000071e bne r2,zero,803fe44 + { + struct sockaddr_in * addr = (struct sockaddr_in *)ipaddr; + 803fe28: e0bffe17 ldw r2,-8(fp) + 803fe2c: e0bfff15 stw r2,-4(fp) + return print_ipad(addr->sin_addr.s_addr); + 803fe30: e0bfff17 ldw r2,-4(fp) + 803fe34: 10800117 ldw r2,4(r2) + 803fe38: 1009883a mov r4,r2 + 803fe3c: 8026fbc0 call 8026fbc + 803fe40: 00000106 br 803fe48 + static char namebuf[46]; /* max len of IPv6 addr */ + return (char *)inet_ntop(AF_INET6,&addr->sin6_addr, namebuf, sizeof(namebuf)); + } +#endif + + return NULL; + 803fe44: 0005883a mov r2,zero +} + 803fe48: e037883a mov sp,fp + 803fe4c: dfc00117 ldw ra,4(sp) + 803fe50: df000017 ldw fp,0(sp) + 803fe54: dec00204 addi sp,sp,8 + 803fe58: f800283a ret + +0803fe5c : + * + */ + +int +inet46_addr(char * str, struct sockaddr *address) +{ + 803fe5c: defffb04 addi sp,sp,-20 + 803fe60: dfc00415 stw ra,16(sp) + 803fe64: df000315 stw fp,12(sp) + 803fe68: df000304 addi fp,sp,12 + 803fe6c: e13ffe15 stw r4,-8(fp) + 803fe70: e17ffd15 stw r5,-12(fp) + /* Read the IPv4/IPv6 address */ + address->sa_family = AF_INET; /* assume IPv4 address by default */ + 803fe74: e0bffd17 ldw r2,-12(fp) + 803fe78: 00c00084 movi r3,2 + 803fe7c: 10c0000d sth r3,0(r2) + + if ((str[1] == '.') || (str[2] == '.') || (str[3] == '.')) + 803fe80: e0bffe17 ldw r2,-8(fp) + 803fe84: 10800044 addi r2,r2,1 + 803fe88: 10800003 ldbu r2,0(r2) + 803fe8c: 10803fcc andi r2,r2,255 + 803fe90: 1080201c xori r2,r2,128 + 803fe94: 10bfe004 addi r2,r2,-128 + 803fe98: 10800ba0 cmpeqi r2,r2,46 + 803fe9c: 1000101e bne r2,zero,803fee0 + 803fea0: e0bffe17 ldw r2,-8(fp) + 803fea4: 10800084 addi r2,r2,2 + 803fea8: 10800003 ldbu r2,0(r2) + 803feac: 10803fcc andi r2,r2,255 + 803feb0: 1080201c xori r2,r2,128 + 803feb4: 10bfe004 addi r2,r2,-128 + 803feb8: 10800ba0 cmpeqi r2,r2,46 + 803febc: 1000081e bne r2,zero,803fee0 + 803fec0: e0bffe17 ldw r2,-8(fp) + 803fec4: 108000c4 addi r2,r2,3 + 803fec8: 10800003 ldbu r2,0(r2) + 803fecc: 10803fcc andi r2,r2,255 + 803fed0: 1080201c xori r2,r2,128 + 803fed4: 10bfe004 addi r2,r2,-128 + 803fed8: 10800b98 cmpnei r2,r2,46 + 803fedc: 10000a1e bne r2,zero,803ff08 + { + struct sockaddr_in *addr = (struct sockaddr_in *)address; + 803fee0: e0bffd17 ldw r2,-12(fp) + 803fee4: e0bfff15 stw r2,-4(fp) + addr->sin_addr.s_addr = inet_addr(str); + 803fee8: e13ffe17 ldw r4,-8(fp) + 803feec: 803fc380 call 803fc38 + 803fef0: 1007883a mov r3,r2 + 803fef4: e0bfff17 ldw r2,-4(fp) + 803fef8: 10c00115 stw r3,4(r2) + addr->sin_family = AF_INET; + 803fefc: e0bfff17 ldw r2,-4(fp) + 803ff00: 00c00084 movi r3,2 + 803ff04: 10c0000d sth r3,0(r2) + inet_pton(AF_INET6, str, &addr->sin6_addr); + addr->sin6_family = AF_INET6; + } +#endif + + return 0; + 803ff08: 0005883a mov r2,zero +} + 803ff0c: e037883a mov sp,fp + 803ff10: dfc00117 ldw ra,4(sp) + 803ff14: df000017 ldw fp,0(sp) + 803ff18: dec00204 addi sp,sp,8 + 803ff1c: f800283a ret + +0803ff20 : + * + * RETURNS: - + */ + +void inet_setport(struct sockaddr *addr,int port) +{ + 803ff20: defffc04 addi sp,sp,-16 + 803ff24: df000315 stw fp,12(sp) + 803ff28: df000304 addi fp,sp,12 + 803ff2c: e13ffe15 stw r4,-8(fp) + 803ff30: e17ffd15 stw r5,-12(fp) + if (addr->sa_family == AF_INET) + 803ff34: e0bffe17 ldw r2,-8(fp) + 803ff38: 1080000b ldhu r2,0(r2) + 803ff3c: 10bfffcc andi r2,r2,65535 + 803ff40: 10800098 cmpnei r2,r2,2 + 803ff44: 10000c1e bne r2,zero,803ff78 + { + struct sockaddr_in *si = (struct sockaddr_in *)addr; + 803ff48: e0bffe17 ldw r2,-8(fp) + 803ff4c: e0bfff15 stw r2,-4(fp) + si->sin_port = htons(port); + 803ff50: e0bffd17 ldw r2,-12(fp) + 803ff54: 1005d23a srai r2,r2,8 + 803ff58: 10803fcc andi r2,r2,255 + 803ff5c: 1007883a mov r3,r2 + 803ff60: e0bffd17 ldw r2,-12(fp) + 803ff64: 1004923a slli r2,r2,8 + 803ff68: 1884b03a or r2,r3,r2 + 803ff6c: 1007883a mov r3,r2 + 803ff70: e0bfff17 ldw r2,-4(fp) + 803ff74: 10c0008d sth r3,2(r2) + struct sockaddr_in6 *si = (struct sockaddr_in6 *)addr; + si->sin6_port = htons(port); + } +#endif + +} + 803ff78: 0001883a nop + 803ff7c: e037883a mov sp,fp + 803ff80: df000017 ldw fp,0(sp) + 803ff84: dec00104 addi sp,sp,4 + 803ff88: f800283a ret + +0803ff8c : + *Returns: + * + */ + +unsigned long convert_ip(const char *p) +{ + 803ff8c: defff904 addi sp,sp,-28 + 803ff90: df000615 stw fp,24(sp) + 803ff94: df000604 addi fp,sp,24 + 803ff98: e13ffa15 stw r4,-24(fp) + const char *cp = p; + 803ff9c: e0bffa17 ldw r2,-24(fp) + 803ffa0: e0bfff15 stw r2,-4(fp) + unsigned long dw; + unsigned char *lpb = (unsigned char *) &dw; + 803ffa4: e0bffb04 addi r2,fp,-20 + 803ffa8: e0bffc15 stw r2,-16(fp) + int n = 0; + 803ffac: e03ffe15 stw zero,-8(fp) + unsigned short v = 0; + 803ffb0: e03ffd8d sth zero,-10(fp) + dw = 0; + 803ffb4: e03ffb15 stw zero,-20(fp) + while(*cp) + 803ffb8: 00003106 br 8040080 + { + if( *cp == '.') + 803ffbc: e0bfff17 ldw r2,-4(fp) + 803ffc0: 10800003 ldbu r2,0(r2) + 803ffc4: 10803fcc andi r2,r2,255 + 803ffc8: 1080201c xori r2,r2,128 + 803ffcc: 10bfe004 addi r2,r2,-128 + 803ffd0: 10800b98 cmpnei r2,r2,46 + 803ffd4: 10000e1e bne r2,zero,8040010 + { + lpb[n] = (unsigned char) v; + 803ffd8: e0bffe17 ldw r2,-8(fp) + 803ffdc: e0fffc17 ldw r3,-16(fp) + 803ffe0: 1885883a add r2,r3,r2 + 803ffe4: e0fffd8b ldhu r3,-10(fp) + 803ffe8: 10c00005 stb r3,0(r2) + v = 0; + 803ffec: e03ffd8d sth zero,-10(fp) + n++; + 803fff0: e0bffe17 ldw r2,-8(fp) + 803fff4: 10800044 addi r2,r2,1 + 803fff8: e0bffe15 stw r2,-8(fp) + if(n > 3) + 803fffc: e0bffe17 ldw r2,-8(fp) + 8040000: 10800110 cmplti r2,r2,4 + 8040004: 10001b1e bne r2,zero,8040074 + { + return dw; + 8040008: e0bffb17 ldw r2,-20(fp) + 804000c: 00002806 br 80400b0 + } + } + else if(((*cp >= '0') && (*cp <= '9'))) + 8040010: e0bfff17 ldw r2,-4(fp) + 8040014: 10800003 ldbu r2,0(r2) + 8040018: 10803fcc andi r2,r2,255 + 804001c: 1080201c xori r2,r2,128 + 8040020: 10bfe004 addi r2,r2,-128 + 8040024: 10800c10 cmplti r2,r2,48 + 8040028: 1000121e bne r2,zero,8040074 + 804002c: e0bfff17 ldw r2,-4(fp) + 8040030: 10800003 ldbu r2,0(r2) + 8040034: 10803fcc andi r2,r2,255 + 8040038: 1080201c xori r2,r2,128 + 804003c: 10bfe004 addi r2,r2,-128 + 8040040: 10800e88 cmpgei r2,r2,58 + 8040044: 10000b1e bne r2,zero,8040074 + { + v = (v * 10) + (*cp - '0'); + 8040048: e0bffd8b ldhu r2,-10(fp) + 804004c: 108002a4 muli r2,r2,10 + 8040050: 1007883a mov r3,r2 + 8040054: e0bfff17 ldw r2,-4(fp) + 8040058: 10800003 ldbu r2,0(r2) + 804005c: 10803fcc andi r2,r2,255 + 8040060: 1080201c xori r2,r2,128 + 8040064: 10bfe004 addi r2,r2,-128 + 8040068: 1885883a add r2,r3,r2 + 804006c: 10bff404 addi r2,r2,-48 + 8040070: e0bffd8d sth r2,-10(fp) + } + cp++; + 8040074: e0bfff17 ldw r2,-4(fp) + 8040078: 10800044 addi r2,r2,1 + 804007c: e0bfff15 stw r2,-4(fp) + while(*cp) + 8040080: e0bfff17 ldw r2,-4(fp) + 8040084: 10800003 ldbu r2,0(r2) + 8040088: 10803fcc andi r2,r2,255 + 804008c: 1080201c xori r2,r2,128 + 8040090: 10bfe004 addi r2,r2,-128 + 8040094: 103fc91e bne r2,zero,803ffbc + } + lpb[n] = (unsigned char) v; + 8040098: e0bffe17 ldw r2,-8(fp) + 804009c: e0fffc17 ldw r3,-16(fp) + 80400a0: 1885883a add r2,r3,r2 + 80400a4: e0fffd8b ldhu r3,-10(fp) + 80400a8: 10c00005 stb r3,0(r2) + return dw; + 80400ac: e0bffb17 ldw r2,-20(fp) +} /* convert_ip() */ + 80400b0: e037883a mov sp,fp + 80400b4: df000017 ldw fp,0(sp) + 80400b8: dec00104 addi sp,sp,4 + 80400bc: f800283a ret + +080400c0 : + * RETURNS: + */ + +unshort +tcp_cksum(struct ip * pip) +{ + 80400c0: defff704 addi sp,sp,-36 + 80400c4: dfc00815 stw ra,32(sp) + 80400c8: df000715 stw fp,28(sp) + 80400cc: df000704 addi fp,sp,28 + 80400d0: e13ff915 stw r4,-28(fp) + unshort oldsum; + unshort newsum; + struct tcphdr * tp; + +#ifdef MUTE_WARNS /* stifle compiler warnings */ + tcpdata = (char *)NULL; + 80400d4: e03ffe15 stw zero,-8(fp) +#endif /* MUTE_WARNS */ + + IN_PROFILER(PF_TSUM, PF_ENTRY); + + oddchar = 0; + 80400d8: e03ffdc5 stb zero,-9(fp) + + iphlen = (unshort)ip_hlen(pip); + 80400dc: e0bff917 ldw r2,-28(fp) + 80400e0: 10800003 ldbu r2,0(r2) + 80400e4: 10803fcc andi r2,r2,255 + 80400e8: 100490ba slli r2,r2,2 + 80400ec: 10800f0c andi r2,r2,60 + 80400f0: e0bffc8d sth r2,-14(fp) + tcplen = htons(pip->ip_len) - iphlen; + 80400f4: e0bff917 ldw r2,-28(fp) + 80400f8: 1080008b ldhu r2,2(r2) + 80400fc: 10bfffcc andi r2,r2,65535 + 8040100: 1004d23a srli r2,r2,8 + 8040104: 1007883a mov r3,r2 + 8040108: e0bff917 ldw r2,-28(fp) + 804010c: 1080008b ldhu r2,2(r2) + 8040110: 10bfffcc andi r2,r2,65535 + 8040114: 1004923a slli r2,r2,8 + 8040118: 1884b03a or r2,r3,r2 + 804011c: 1007883a mov r3,r2 + 8040120: e0bffc8b ldhu r2,-14(fp) + 8040124: 1885c83a sub r2,r3,r2 + 8040128: e0bfff8d sth r2,-2(fp) + + tp = (struct tcphdr*)ip_data(pip); /* get TCP header */ + 804012c: e0bff917 ldw r2,-28(fp) + 8040130: 10800003 ldbu r2,0(r2) + 8040134: 10803fcc andi r2,r2,255 + 8040138: 100490ba slli r2,r2,2 + 804013c: 10800f0c andi r2,r2,60 + 8040140: e0fff917 ldw r3,-28(fp) + 8040144: 1885883a add r2,r3,r2 + 8040148: e0bffb15 stw r2,-20(fp) + oldsum = tp->th_sum; /* Save passed checksum */ + 804014c: e0bffb17 ldw r2,-20(fp) + 8040150: 1080040b ldhu r2,16(r2) + 8040154: e0bffa8d sth r2,-22(fp) + * cannot overflow a 16 bit field) and put them in the cksum field. + * We include the IP addresses by passing them to the lower level + * fast sum routine. This results in their values being factored into + * the sum and the cksum field contributes zero. + */ + tp->th_sum = htons(tcplen + 6); + 8040158: e0bfff8b ldhu r2,-2(fp) + 804015c: 10800184 addi r2,r2,6 + 8040160: 1005d23a srai r2,r2,8 + 8040164: 10803fcc andi r2,r2,255 + 8040168: 1007883a mov r3,r2 + 804016c: e0bfff8b ldhu r2,-2(fp) + 8040170: 10800184 addi r2,r2,6 + 8040174: 1004923a slli r2,r2,8 + 8040178: 1884b03a or r2,r3,r2 + 804017c: 1007883a mov r3,r2 + 8040180: e0bffb17 ldw r2,-20(fp) + 8040184: 10c0040d sth r3,16(r2) + + /* zero pad odd sized packets for checksumming */ + if (tcplen & 1) + 8040188: e0bfff8b ldhu r2,-2(fp) + 804018c: 1080004c andi r2,r2,1 + 8040190: 10000e26 beq r2,zero,80401cc + { + tcpdata = ((char*)pip) + iphlen + tcplen; /* end of packet */ + 8040194: e0fffc8b ldhu r3,-14(fp) + 8040198: e0bfff8b ldhu r2,-2(fp) + 804019c: 1885883a add r2,r3,r2 + 80401a0: e0fff917 ldw r3,-28(fp) + 80401a4: 1885883a add r2,r3,r2 + 80401a8: e0bffe15 stw r2,-8(fp) + oddchar = *tcpdata; + 80401ac: e0bffe17 ldw r2,-8(fp) + 80401b0: 10800003 ldbu r2,0(r2) + 80401b4: e0bffdc5 stb r2,-9(fp) + *tcpdata = '\0'; /* zero out pad byte */ + 80401b8: e0bffe17 ldw r2,-8(fp) + 80401bc: 10000005 stb zero,0(r2) + tcplen++; /* bump length to pass to cksum() */ + 80401c0: e0bfff8b ldhu r2,-2(fp) + 80401c4: 10800044 addi r2,r2,1 + 80401c8: e0bfff8d sth r2,-2(fp) + + /* Pass a pointer to the beginning of the IP address area into the IP header + * the the low level sum routine. Add the size of these two IP addresses to + * the length, and convert the length to 16 bit words. + */ + newsum = ~cksum(((char*)tp) - 8, (tcplen + 8) >> 1); + 80401cc: e0bffb17 ldw r2,-20(fp) + 80401d0: 10fffe04 addi r3,r2,-8 + 80401d4: e0bfff8b ldhu r2,-2(fp) + 80401d8: 10800204 addi r2,r2,8 + 80401dc: 1005d07a srai r2,r2,1 + 80401e0: 100b883a mov r5,r2 + 80401e4: 1809883a mov r4,r3 + 80401e8: 8026d7c0 call 8026d7c + 80401ec: 0084303a nor r2,zero,r2 + 80401f0: e0bffd0d sth r2,-12(fp) + + /* If the old checksum is 0xffff, but the actual checksum is 0x0000, + * declare that to be a match. + */ + if ((newsum != oldsum) && (oldsum == 0xffff) && (newsum == 0x0000)) + 80401f4: e0fffd0b ldhu r3,-12(fp) + 80401f8: e0bffa8b ldhu r2,-22(fp) + 80401fc: 18800726 beq r3,r2,804021c + 8040200: e0fffa8b ldhu r3,-22(fp) + 8040204: 00bfffd4 movui r2,65535 + 8040208: 1880041e bne r3,r2,804021c + 804020c: e0bffd0b ldhu r2,-12(fp) + 8040210: 1000021e bne r2,zero,804021c + newsum = 0xffff; + 8040214: 00bfffc4 movi r2,-1 + 8040218: e0bffd0d sth r2,-12(fp) + + /* restore what we clobbered */ + tp->th_sum = oldsum; /* put back passed checksum */ + 804021c: e0bffb17 ldw r2,-20(fp) + 8040220: e0fffa8b ldhu r3,-22(fp) + 8040224: 10c0040d sth r3,16(r2) + if (oddchar) + 8040228: e0bffdc7 ldb r2,-9(fp) + 804022c: 10000326 beq r2,zero,804023c + *tcpdata = oddchar; /* restore odd byte if we zeroed it */ + 8040230: e0bffe17 ldw r2,-8(fp) + 8040234: e0fffdc3 ldbu r3,-9(fp) + 8040238: 10c00005 stb r3,0(r2) + + IN_PROFILER(PF_TSUM, PF_EXIT); + + return newsum; + 804023c: e0bffd0b ldhu r2,-12(fp) +} + 8040240: e037883a mov sp,fp + 8040244: dfc00117 ldw ra,4(sp) + 8040248: df000017 ldw fp,0(sp) + 804024c: dec00204 addi sp,sp,8 + 8040250: f800283a ret + +08040254 : + ip_addr fhost, /* foreign host, 0L for any */ + unshort fsock, /* foreign socket, 0 for any */ + unshort lsock, /* local socket */ + int (*handler)(PACKET, void*), /* rcv upcall */ + void * data) /* random data, returned on upcalls to aid demuxing */ +{ + 8040254: defff404 addi sp,sp,-48 + 8040258: dfc00b15 stw ra,44(sp) + 804025c: df000a15 stw fp,40(sp) + 8040260: df000a04 addi fp,sp,40 + 8040264: e13ffd15 stw r4,-12(fp) + 8040268: 2805883a mov r2,r5 + 804026c: 3007883a mov r3,r6 + 8040270: e1fffa15 stw r7,-24(fp) + 8040274: e0bffc0d sth r2,-16(fp) + 8040278: 1805883a mov r2,r3 + 804027c: e0bffb0d sth r2,-20(fp) +/* + * Altera Niche Stack Nios port modification: + * cast 'data' to remove build warning + */ +#ifdef NPDEBUG + if (NDEBUG & INFOMSG) + 8040280: d0a06617 ldw r2,-32360(gp) + 8040284: 1080010c andi r2,r2,4 + 8040288: 10001526 beq r2,zero,80402e0 + dprintf("udp_open: host %u.%u.%u.%u, lsock %u, fsock %u, foo %04x\n", + 804028c: e0bffd17 ldw r2,-12(fp) + 8040290: 12003fcc andi r8,r2,255 + PUSH_IPADDR(fhost),lsock, fsock, (unsigned int)data); + 8040294: e0bffd17 ldw r2,-12(fp) + 8040298: 1004d23a srli r2,r2,8 + dprintf("udp_open: host %u.%u.%u.%u, lsock %u, fsock %u, foo %04x\n", + 804029c: 11803fcc andi r6,r2,255 + PUSH_IPADDR(fhost),lsock, fsock, (unsigned int)data); + 80402a0: e0bffd17 ldw r2,-12(fp) + 80402a4: 1004d43a srli r2,r2,16 + dprintf("udp_open: host %u.%u.%u.%u, lsock %u, fsock %u, foo %04x\n", + 80402a8: 11c03fcc andi r7,r2,255 + PUSH_IPADDR(fhost),lsock, fsock, (unsigned int)data); + 80402ac: e0bffd17 ldw r2,-12(fp) + 80402b0: 1004d63a srli r2,r2,24 + dprintf("udp_open: host %u.%u.%u.%u, lsock %u, fsock %u, foo %04x\n", + 80402b4: e0fffb0b ldhu r3,-20(fp) + 80402b8: e13ffc0b ldhu r4,-16(fp) + 80402bc: e1400217 ldw r5,8(fp) + 80402c0: d9400315 stw r5,12(sp) + 80402c4: d9000215 stw r4,8(sp) + 80402c8: d8c00115 stw r3,4(sp) + 80402cc: d8800015 stw r2,0(sp) + 80402d0: 400b883a mov r5,r8 + 80402d4: 01020174 movhi r4,2053 + 80402d8: 212e0704 addi r4,r4,-18404 + 80402dc: 8002c780 call 8002c78 +#endif + + LOCK_NET_RESOURCE(NET_RESID); + 80402e0: 0009883a mov r4,zero + 80402e4: 8028f380 call 8028f38 + ocon = NULL; + 80402e8: e03ffe15 stw zero,-8(fp) + for (con = firstudp; con; con = con->u_next) + 80402ec: d0a09e17 ldw r2,-32136(gp) + 80402f0: e0bfff15 stw r2,-4(fp) + 80402f4: 00002006 br 8040378 + { + ocon = con; /* remember last con in list */ + 80402f8: e0bfff17 ldw r2,-4(fp) + 80402fc: e0bffe15 stw r2,-8(fp) + /* we only want to check UDP-over-IPv4 connections */ + if (!(con->u_flags & UDPCF_V4)) + continue; +#endif + + if (con->u_lport == lsock && con->u_fport == fsock && + 8040300: e0bfff17 ldw r2,-4(fp) + 8040304: 1080018b ldhu r2,6(r2) + 8040308: e0fffb0b ldhu r3,-20(fp) + 804030c: 10bfffcc andi r2,r2,65535 + 8040310: 1880161e bne r3,r2,804036c + 8040314: e0bfff17 ldw r2,-4(fp) + 8040318: 1080020b ldhu r2,8(r2) + 804031c: e0fffc0b ldhu r3,-16(fp) + 8040320: 10bfffcc andi r2,r2,65535 + 8040324: 1880111e bne r3,r2,804036c + con->u_lhost == 0 && con->u_fhost == fhost) + 8040328: e0bfff17 ldw r2,-4(fp) + 804032c: 10800317 ldw r2,12(r2) + if (con->u_lport == lsock && con->u_fport == fsock && + 8040330: 10000e1e bne r2,zero,804036c + con->u_lhost == 0 && con->u_fhost == fhost) + 8040334: e0bfff17 ldw r2,-4(fp) + 8040338: 10800417 ldw r2,16(r2) + 804033c: e0fffd17 ldw r3,-12(fp) + 8040340: 18800a1e bne r3,r2,804036c + { +#ifdef NPDEBUG + if (NDEBUG & (INFOMSG|PROTERR)) + 8040344: d0a06617 ldw r2,-32360(gp) + 8040348: 1080050c andi r2,r2,20 + 804034c: 10000326 beq r2,zero,804035c + dprintf("UDP: Connection already exists.\n"); + 8040350: 01020174 movhi r4,2053 + 8040354: 212e1604 addi r4,r4,-18344 + 8040358: 8002d9c0 call 8002d9c +#endif + UNLOCK_NET_RESOURCE(NET_RESID); + 804035c: 0009883a mov r4,zero + 8040360: 8028ff40 call 8028ff4 + return(NULL); + 8040364: 0005883a mov r2,zero + 8040368: 00003506 br 8040440 + for (con = firstudp; con; con = con->u_next) + 804036c: e0bfff17 ldw r2,-4(fp) + 8040370: 10800017 ldw r2,0(r2) + 8040374: e0bfff15 stw r2,-4(fp) + 8040378: e0bfff17 ldw r2,-4(fp) + 804037c: 103fde1e bne r2,zero,80402f8 + } + } + + con = (UDPCONN)UC_ALLOC(sizeof(struct udp_conn)); + 8040380: 01000804 movi r4,32 + 8040384: 802982c0 call 802982c + 8040388: e0bfff15 stw r2,-4(fp) + if (con == 0) + 804038c: e0bfff17 ldw r2,-4(fp) + 8040390: 10000a1e bne r2,zero,80403bc + { +#ifdef NPDEBUG + if (NDEBUG & INFOMSG) + 8040394: d0a06617 ldw r2,-32360(gp) + 8040398: 1080010c andi r2,r2,4 + 804039c: 10000326 beq r2,zero,80403ac + dprintf("UDP: Couldn't allocate conn storage.\n"); + 80403a0: 01020174 movhi r4,2053 + 80403a4: 212e1e04 addi r4,r4,-18312 + 80403a8: 8002d9c0 call 8002d9c +#endif + UNLOCK_NET_RESOURCE(NET_RESID); + 80403ac: 0009883a mov r4,zero + 80403b0: 8028ff40 call 8028ff4 + return(NULL); + 80403b4: 0005883a mov r2,zero + 80403b8: 00002106 br 8040440 + } + + if (ocon) /* ocon is end of list */ + 80403bc: e0bffe17 ldw r2,-8(fp) + 80403c0: 10000426 beq r2,zero,80403d4 + ocon->u_next = con; /* add new connection to end */ + 80403c4: e0bffe17 ldw r2,-8(fp) + 80403c8: e0ffff17 ldw r3,-4(fp) + 80403cc: 10c00015 stw r3,0(r2) + 80403d0: 00000206 br 80403dc + else /* no list, start one */ + firstudp = con; + 80403d4: e0bfff17 ldw r2,-4(fp) + 80403d8: d0a09e15 stw r2,-32136(gp) + + con->u_next = 0; + 80403dc: e0bfff17 ldw r2,-4(fp) + 80403e0: 10000015 stw zero,0(r2) + + con->u_lport = lsock; /* fill in connection info */ + 80403e4: e0bfff17 ldw r2,-4(fp) + 80403e8: e0fffb0b ldhu r3,-20(fp) + 80403ec: 10c0018d sth r3,6(r2) + con->u_fport = fsock; + 80403f0: e0bfff17 ldw r2,-4(fp) + 80403f4: e0fffc0b ldhu r3,-16(fp) + 80403f8: 10c0020d sth r3,8(r2) + con->u_lhost = 0; + 80403fc: e0bfff17 ldw r2,-4(fp) + 8040400: 10000315 stw zero,12(r2) + con->u_fhost = fhost; + 8040404: e0bfff17 ldw r2,-4(fp) + 8040408: e0fffd17 ldw r3,-12(fp) + 804040c: 10c00415 stw r3,16(r2) + con->u_rcv = handler; + 8040410: e0bfff17 ldw r2,-4(fp) + 8040414: e0fffa17 ldw r3,-24(fp) + 8040418: 10c00515 stw r3,20(r2) + con->u_data = data; + 804041c: e0bfff17 ldw r2,-4(fp) + 8040420: e0c00217 ldw r3,8(fp) + 8040424: 10c00615 stw r3,24(r2) + con->u_flags = UDPCF_V4; + 8040428: e0bfff17 ldw r2,-4(fp) + 804042c: 00c00044 movi r3,1 + 8040430: 10c0010d sth r3,4(r2) + + UNLOCK_NET_RESOURCE(NET_RESID); + 8040434: 0009883a mov r4,zero + 8040438: 8028ff40 call 8028ff4 + return(con); + 804043c: e0bfff17 ldw r2,-4(fp) +} + 8040440: e037883a mov sp,fp + 8040444: dfc00117 ldw ra,4(sp) + 8040448: df000017 ldw fp,0(sp) + 804044c: dec00204 addi sp,sp,8 + 8040450: f800283a ret + +08040454 : + * RETURNS: void + */ + +void +udp_close(UDPCONN con) +{ + 8040454: defffb04 addi sp,sp,-20 + 8040458: dfc00415 stw ra,16(sp) + 804045c: df000315 stw fp,12(sp) + 8040460: df000304 addi fp,sp,12 + 8040464: e13ffd15 stw r4,-12(fp) + UDPCONN pcon; + UDPCONN lcon; + +#ifdef NPDEBUG + if ((con == NULL) || (firstudp == NULL)) + 8040468: e0bffd17 ldw r2,-12(fp) + 804046c: 10000226 beq r2,zero,8040478 + 8040470: d0a09e17 ldw r2,-32136(gp) + 8040474: 1000021e bne r2,zero,8040480 + { + dtrap(); /* bad programming! */ + 8040478: 8028cd40 call 8028cd4 + return; + 804047c: 00002606 br 8040518 + } +#endif /* NPDEBUG */ + + LOCK_NET_RESOURCE(NET_RESID); + 8040480: 0009883a mov r4,zero + 8040484: 8028f380 call 8028f38 + /* find connection in list and unlink it */ + lcon = NULL; /* clear ptr to last connection */ + 8040488: e03ffe15 stw zero,-8(fp) + for (pcon = firstudp; pcon; pcon = pcon->u_next) + 804048c: d0a09e17 ldw r2,-32136(gp) + 8040490: e0bfff15 stw r2,-4(fp) + 8040494: 00000806 br 80404b8 + { + if (pcon == con) /* found connection to delete */ + 8040498: e0ffff17 ldw r3,-4(fp) + 804049c: e0bffd17 ldw r2,-12(fp) + 80404a0: 18800826 beq r3,r2,80404c4 + break; + lcon = pcon; /* remember last connection */ + 80404a4: e0bfff17 ldw r2,-4(fp) + 80404a8: e0bffe15 stw r2,-8(fp) + for (pcon = firstudp; pcon; pcon = pcon->u_next) + 80404ac: e0bfff17 ldw r2,-4(fp) + 80404b0: 10800017 ldw r2,0(r2) + 80404b4: e0bfff15 stw r2,-4(fp) + 80404b8: e0bfff17 ldw r2,-4(fp) + 80404bc: 103ff61e bne r2,zero,8040498 + 80404c0: 00000106 br 80404c8 + break; + 80404c4: 0001883a nop + } + + if (!pcon) + 80404c8: e0bfff17 ldw r2,-4(fp) + 80404cc: 1000041e bne r2,zero,80404e0 + { + dtrap(); /* prog error - connenction not in list */ + 80404d0: 8028cd40 call 8028cd4 + UNLOCK_NET_RESOURCE(NET_RESID); + 80404d4: 0009883a mov r4,zero + 80404d8: 8028ff40 call 8028ff4 + return; + 80404dc: 00000e06 br 8040518 + } + + if (lcon) /* in con is not head of list */ + 80404e0: e0bffe17 ldw r2,-8(fp) + 80404e4: 10000526 beq r2,zero,80404fc + lcon->u_next = con->u_next; /* unlink */ + 80404e8: e0bffd17 ldw r2,-12(fp) + 80404ec: 10c00017 ldw r3,0(r2) + 80404f0: e0bffe17 ldw r2,-8(fp) + 80404f4: 10c00015 stw r3,0(r2) + 80404f8: 00000306 br 8040508 + else + firstudp = con->u_next; /* remove from head */ + 80404fc: e0bffd17 ldw r2,-12(fp) + 8040500: 10800017 ldw r2,0(r2) + 8040504: d0a09e15 stw r2,-32136(gp) + + UC_FREE(con); /* free memory for structure */ + 8040508: e13ffd17 ldw r4,-12(fp) + 804050c: 80298600 call 8029860 + UNLOCK_NET_RESOURCE(NET_RESID); + 8040510: 0009883a mov r4,zero + 8040514: 8028ff40 call 8028ff4 +} + 8040518: e037883a mov sp,fp + 804051c: dfc00117 ldw ra,4(sp) + 8040520: df000017 ldw fp,0(sp) + 8040524: dec00204 addi sp,sp,8 + 8040528: f800283a ret + +0804052c : + */ + +int +in_pcballoc(struct socket * so, + struct inpcb * head) +{ + 804052c: defffb04 addi sp,sp,-20 + 8040530: dfc00415 stw ra,16(sp) + 8040534: df000315 stw fp,12(sp) + 8040538: df000304 addi fp,sp,12 + 804053c: e13ffe15 stw r4,-8(fp) + 8040540: e17ffd15 stw r5,-12(fp) + struct inpcb * inp; + + inp = INP_ALLOC (sizeof (*inp)); + 8040544: 01000b04 movi r4,44 + 8040548: 802982c0 call 802982c + 804054c: e0bfff15 stw r2,-4(fp) + if (inp == 0) + 8040550: e0bfff17 ldw r2,-4(fp) + 8040554: 1000021e bne r2,zero,8040560 + return ENOMEM; + 8040558: 00800304 movi r2,12 + 804055c: 00001006 br 80405a0 + inp->inp_head = head; + 8040560: e0bfff17 ldw r2,-4(fp) + 8040564: e0fffd17 ldw r3,-12(fp) + 8040568: 10c00215 stw r3,8(r2) + inp->inp_socket = so; + 804056c: e0bfff17 ldw r2,-4(fp) + 8040570: e0fffe17 ldw r3,-8(fp) + 8040574: 10c00815 stw r3,32(r2) + + /* Set Path MTU to a very small default. It should get expanded + * later by v4 or v6 specific SYN code. We don't want it zero + * in case it doesn't get expanded promptly. + */ + inp->inp_pmtu = 512; + 8040578: e0bfff17 ldw r2,-4(fp) + 804057c: 00c08004 movi r3,512 + 8040580: 10c00615 stw r3,24(r2) + insque(inp, head); + 8040584: e17ffd17 ldw r5,-12(fp) + 8040588: e13fff17 ldw r4,-4(fp) + 804058c: 802a3340 call 802a334 + so->so_pcb = inp; + 8040590: e0bffe17 ldw r2,-8(fp) + 8040594: e0ffff17 ldw r3,-4(fp) + 8040598: 10c00115 stw r3,4(r2) + return 0; + 804059c: 0005883a mov r2,zero +} + 80405a0: e037883a mov sp,fp + 80405a4: dfc00117 ldw ra,4(sp) + 80405a8: df000017 ldw fp,0(sp) + 80405ac: dec00204 addi sp,sp,8 + 80405b0: f800283a ret + +080405b4 : + * RETURNS: + */ + +void +in_pcbdetach(struct inpcb * inp) +{ + 80405b4: defffc04 addi sp,sp,-16 + 80405b8: dfc00315 stw ra,12(sp) + 80405bc: df000215 stw fp,8(sp) + 80405c0: df000204 addi fp,sp,8 + 80405c4: e13ffe15 stw r4,-8(fp) + struct socket * so = inp->inp_socket; + 80405c8: e0bffe17 ldw r2,-8(fp) + 80405cc: 10800817 ldw r2,32(r2) + 80405d0: e0bfff15 stw r2,-4(fp) + + so->so_pcb = 0; + 80405d4: e0bfff17 ldw r2,-4(fp) + 80405d8: 10000115 stw zero,4(r2) + sofree(so); + 80405dc: e13fff17 ldw r4,-4(fp) + 80405e0: 802d3240 call 802d324 + remque(inp); + 80405e4: e13ffe17 ldw r4,-8(fp) + 80405e8: 802a2c40 call 802a2c4 + INP_FREE (inp); + 80405ec: e13ffe17 ldw r4,-8(fp) + 80405f0: 80298600 call 8029860 +} + 80405f4: 0001883a nop + 80405f8: e037883a mov sp,fp + 80405fc: dfc00117 ldw ra,4(sp) + 8040600: df000017 ldw fp,0(sp) + 8040604: dec00204 addi sp,sp,8 + 8040608: f800283a ret + +0804060c : + +int +in_pcbbind( + struct inpcb * inp, + struct mbuf * nam) +{ + 804060c: defff504 addi sp,sp,-44 + 8040610: dfc00a15 stw ra,40(sp) + 8040614: df000915 stw fp,36(sp) + 8040618: df000904 addi fp,sp,36 + 804061c: e13ffa15 stw r4,-24(fp) + 8040620: e17ff915 stw r5,-28(fp) + struct socket * so = inp->inp_socket; + 8040624: e0bffa17 ldw r2,-24(fp) + 8040628: 10800817 ldw r2,32(r2) + 804062c: e0bffd15 stw r2,-12(fp) + struct inpcb * head = inp->inp_head; + 8040630: e0bffa17 ldw r2,-24(fp) + 8040634: 10800217 ldw r2,8(r2) + 8040638: e0bffc15 stw r2,-16(fp) + struct sockaddr_in * sin; + u_short lport = 0; + 804063c: e03fff8d sth zero,-2(fp) + + + if (inp->inp_lport || inp->inp_laddr.s_addr != INADDR_ANY) + 8040640: e0bffa17 ldw r2,-24(fp) + 8040644: 1080078b ldhu r2,30(r2) + 8040648: 10bfffcc andi r2,r2,65535 + 804064c: 1000031e bne r2,zero,804065c + 8040650: e0bffa17 ldw r2,-24(fp) + 8040654: 10800417 ldw r2,16(r2) + 8040658: 10000226 beq r2,zero,8040664 + return (EINVAL); + 804065c: 00800584 movi r2,22 + 8040660: 00006906 br 8040808 + if (nam == 0) + 8040664: e0bff917 ldw r2,-28(fp) + 8040668: 10003926 beq r2,zero,8040750 + goto noname; + sin = mtod(nam, struct sockaddr_in *); + 804066c: e0bff917 ldw r2,-28(fp) + 8040670: 10800317 ldw r2,12(r2) + 8040674: e0bffb15 stw r2,-20(fp) + /* + * removed test here for "if (nam->m_len != sizeof (*sin))" + * since it really complicatges supporting dual IPv4/v6, and + * the 2.0 stack now checks this in t_bind(). -JB- + */ + if (sin->sin_addr.s_addr != INADDR_ANY) + 8040678: e0bffb17 ldw r2,-20(fp) + 804067c: 10800117 ldw r2,4(r2) + 8040680: 10000a26 beq r2,zero,80406ac + { + if (ip_mymach(sin->sin_addr.s_addr) != sin->sin_addr.s_addr) + 8040684: e0bffb17 ldw r2,-20(fp) + 8040688: 10800117 ldw r2,4(r2) + 804068c: 1009883a mov r4,r2 + 8040690: 803b0280 call 803b028 + 8040694: 1007883a mov r3,r2 + 8040698: e0bffb17 ldw r2,-20(fp) + 804069c: 10800117 ldw r2,4(r2) + 80406a0: 18800226 beq r3,r2,80406ac + return (EADDRNOTAVAIL); + 80406a4: 00801f44 movi r2,125 + 80406a8: 00005706 br 8040808 + } + lport = sin->sin_port; + 80406ac: e0bffb17 ldw r2,-20(fp) + 80406b0: 1080008b ldhu r2,2(r2) + 80406b4: e0bfff8d sth r2,-2(fp) + if (lport) + 80406b8: e0bfff8b ldhu r2,-2(fp) + 80406bc: 10001f26 beq r2,zero,804073c + { + int wild = 0; + 80406c0: e03ffe15 stw zero,-8(fp) + + /* even GROSSER, but this is the Internet */ + if ((so->so_options & SO_REUSEADDR) == 0 && + 80406c4: e0bffd17 ldw r2,-12(fp) + 80406c8: 10800417 ldw r2,16(r2) + 80406cc: 1080010c andi r2,r2,4 + 80406d0: 10000c1e bne r2,zero,8040704 + ((so->so_proto->pr_flags & PR_CONNREQUIRED) == 0 || + 80406d4: e0bffd17 ldw r2,-12(fp) + 80406d8: 10800217 ldw r2,8(r2) + 80406dc: 1080010b ldhu r2,4(r2) + 80406e0: 10bfffcc andi r2,r2,65535 + 80406e4: 1080010c andi r2,r2,4 + if ((so->so_options & SO_REUSEADDR) == 0 && + 80406e8: 10000426 beq r2,zero,80406fc + (so->so_options & SO_ACCEPTCONN) == 0)) + 80406ec: e0bffd17 ldw r2,-12(fp) + 80406f0: 10800417 ldw r2,16(r2) + 80406f4: 1080008c andi r2,r2,2 + ((so->so_proto->pr_flags & PR_CONNREQUIRED) == 0 || + 80406f8: 1000021e bne r2,zero,8040704 + { + wild = INPLOOKUP_WILDCARD; + 80406fc: 00800044 movi r2,1 + 8040700: e0bffe15 stw r2,-8(fp) + } + if (in_pcblookup(head, + 8040704: e0bffb17 ldw r2,-20(fp) + 8040708: 11000117 ldw r4,4(r2) + 804070c: e0bfff8b ldhu r2,-2(fp) + 8040710: e0fffe17 ldw r3,-8(fp) + 8040714: d8c00115 stw r3,4(sp) + 8040718: d8800015 stw r2,0(sp) + 804071c: 200f883a mov r7,r4 + 8040720: 000d883a mov r6,zero + 8040724: 000b883a mov r5,zero + 8040728: e13ffc17 ldw r4,-16(fp) + 804072c: 8040b600 call 8040b60 + 8040730: 10000226 beq r2,zero,804073c + 0L, 0, sin->sin_addr.s_addr, lport, wild)) + { + return (EADDRINUSE); + 8040734: 00801c04 movi r2,112 + 8040738: 00003306 br 8040808 + } + } + inp->inp_laddr = sin->sin_addr; + 804073c: e0bffa17 ldw r2,-24(fp) + 8040740: e0fffb17 ldw r3,-20(fp) + 8040744: 18c00117 ldw r3,4(r3) + 8040748: 10c00415 stw r3,16(r2) + 804074c: 00000106 br 8040754 + goto noname; + 8040750: 0001883a nop +noname: + if (lport == 0) + 8040754: e0bfff8b ldhu r2,-2(fp) + 8040758: 1000271e bne r2,zero,80407f8 + { + do + { + if (head->inp_lport++ < IPPORT_RESERVED || + 804075c: e0bffc17 ldw r2,-16(fp) + 8040760: 1080078b ldhu r2,30(r2) + 8040764: 10c00044 addi r3,r2,1 + 8040768: 1809883a mov r4,r3 + 804076c: e0fffc17 ldw r3,-16(fp) + 8040770: 1900078d sth r4,30(r3) + 8040774: 10bfffcc andi r2,r2,65535 + 8040778: 10810030 cmpltui r2,r2,1024 + 804077c: 1000051e bne r2,zero,8040794 + head->inp_lport > IPPORT_USERRESERVED) + 8040780: e0bffc17 ldw r2,-16(fp) + 8040784: 1080078b ldhu r2,30(r2) + if (head->inp_lport++ < IPPORT_RESERVED || + 8040788: 10bfffcc andi r2,r2,65535 + 804078c: 1084e270 cmpltui r2,r2,5001 + 8040790: 1000031e bne r2,zero,80407a0 + { + head->inp_lport = IPPORT_RESERVED; + 8040794: e0bffc17 ldw r2,-16(fp) + 8040798: 00c10004 movi r3,1024 + 804079c: 10c0078d sth r3,30(r2) + } + lport = htons(head->inp_lport); + 80407a0: e0bffc17 ldw r2,-16(fp) + 80407a4: 1080078b ldhu r2,30(r2) + 80407a8: 10bfffcc andi r2,r2,65535 + 80407ac: 1004d23a srli r2,r2,8 + 80407b0: 1007883a mov r3,r2 + 80407b4: e0bffc17 ldw r2,-16(fp) + 80407b8: 1080078b ldhu r2,30(r2) + 80407bc: 10bfffcc andi r2,r2,65535 + 80407c0: 1004923a slli r2,r2,8 + 80407c4: 1884b03a or r2,r3,r2 + 80407c8: e0bfff8d sth r2,-2(fp) + } while(in_pcblookup(head, 0L, 0, inp->inp_laddr.s_addr, lport, 0)); + 80407cc: e0bffa17 ldw r2,-24(fp) + 80407d0: 10c00417 ldw r3,16(r2) + 80407d4: e0bfff8b ldhu r2,-2(fp) + 80407d8: d8000115 stw zero,4(sp) + 80407dc: d8800015 stw r2,0(sp) + 80407e0: 180f883a mov r7,r3 + 80407e4: 000d883a mov r6,zero + 80407e8: 000b883a mov r5,zero + 80407ec: e13ffc17 ldw r4,-16(fp) + 80407f0: 8040b600 call 8040b60 + 80407f4: 103fd91e bne r2,zero,804075c + } + inp->inp_lport = lport; + 80407f8: e0bffa17 ldw r2,-24(fp) + 80407fc: e0ffff8b ldhu r3,-2(fp) + 8040800: 10c0078d sth r3,30(r2) + return (0); + 8040804: 0005883a mov r2,zero +} + 8040808: e037883a mov sp,fp + 804080c: dfc00117 ldw ra,4(sp) + 8040810: df000017 ldw fp,0(sp) + 8040814: dec00204 addi sp,sp,8 + 8040818: f800283a ret + +0804081c : + */ + +int +in_pcbconnect(struct inpcb * inp, + struct mbuf * nam) +{ + 804081c: defff604 addi sp,sp,-40 + 8040820: dfc00915 stw ra,36(sp) + 8040824: df000815 stw fp,32(sp) + 8040828: df000804 addi fp,sp,32 + 804082c: e13ffb15 stw r4,-20(fp) + 8040830: e17ffa15 stw r5,-24(fp) + unsigned long ifaddr; + struct sockaddr_in * sin = mtod(nam, struct sockaddr_in *); + 8040834: e0bffa17 ldw r2,-24(fp) + 8040838: 10800317 ldw r2,12(r2) + 804083c: e0bffe15 stw r2,-8(fp) + + if (nam->m_len < sizeof (*sin)) + 8040840: e0bffa17 ldw r2,-24(fp) + 8040844: 10800217 ldw r2,8(r2) + 8040848: 10800428 cmpgeui r2,r2,16 + 804084c: 1000021e bne r2,zero,8040858 + return (EINVAL); + 8040850: 00800584 movi r2,22 + 8040854: 00006406 br 80409e8 + if (sin->sin_family != AF_INET) + 8040858: e0bffe17 ldw r2,-8(fp) + 804085c: 1080000b ldhu r2,0(r2) + 8040860: 10bfffcc andi r2,r2,65535 + 8040864: 10a0001c xori r2,r2,32768 + 8040868: 10a00004 addi r2,r2,-32768 + 804086c: 108000a0 cmpeqi r2,r2,2 + 8040870: 1000021e bne r2,zero,804087c + return (EAFNOSUPPORT); + 8040874: 00801a84 movi r2,106 + 8040878: 00005b06 br 80409e8 + if (sin->sin_port == 0) + 804087c: e0bffe17 ldw r2,-8(fp) + 8040880: 1080008b ldhu r2,2(r2) + 8040884: 10bfffcc andi r2,r2,65535 + 8040888: 1000021e bne r2,zero,8040894 + return (EADDRNOTAVAIL); + 804088c: 00801f44 movi r2,125 + 8040890: 00005506 br 80409e8 + * use the primary local address. + * If the supplied address is INADDR_BROADCAST, + * and the primary interface supports broadcast, + * choose the broadcast address for that interface. + */ + if (sin->sin_addr.s_addr == INADDR_ANY) + 8040894: e0bffe17 ldw r2,-8(fp) + 8040898: 10800117 ldw r2,4(r2) + 804089c: 10000d1e bne r2,zero,80408d4 + { + if (inp && inp->ifp) + 80408a0: e0bffb17 ldw r2,-20(fp) + 80408a4: 10000926 beq r2,zero,80408cc + 80408a8: e0bffb17 ldw r2,-20(fp) + 80408ac: 10800a17 ldw r2,40(r2) + 80408b0: 10000626 beq r2,zero,80408cc + sin->sin_addr.s_addr = inp->ifp->n_ipaddr; + 80408b4: e0bffb17 ldw r2,-20(fp) + 80408b8: 10800a17 ldw r2,40(r2) + 80408bc: 10c00a17 ldw r3,40(r2) + 80408c0: e0bffe17 ldw r2,-8(fp) + 80408c4: 10c00115 stw r3,4(r2) + 80408c8: 00000806 br 80408ec + else + return (EADDRNOTAVAIL); + 80408cc: 00801f44 movi r2,125 + 80408d0: 00004506 br 80409e8 + } + else if (sin->sin_addr.s_addr == INADDR_BROADCAST) + 80408d4: e0bffe17 ldw r2,-8(fp) + 80408d8: 10800117 ldw r2,4(r2) + 80408dc: 10bfffd8 cmpnei r2,r2,-1 + 80408e0: 1000021e bne r2,zero,80408ec + return (EADDRNOTAVAIL); + 80408e4: 00801f44 movi r2,125 + 80408e8: 00003f06 br 80409e8 + + + if (inp->inp_laddr.s_addr == INADDR_ANY) + 80408ec: e0bffb17 ldw r2,-20(fp) + 80408f0: 10800417 ldw r2,16(r2) + 80408f4: 10000f1e bne r2,zero,8040934 + { +#ifdef MULTI_HOMED + ip_addr hop1; /* dummy for pass to iproute() */ + NET npnet; /* the netport iface we can send on */ + /* call netport stack's IP routing */ + npnet = iproute(sin->sin_addr.s_addr, &hop1); + 80408f8: e0bffe17 ldw r2,-8(fp) + 80408fc: 10800117 ldw r2,4(r2) + 8040900: e0fffc04 addi r3,fp,-16 + 8040904: 180b883a mov r5,r3 + 8040908: 1009883a mov r4,r2 + 804090c: 803b3700 call 803b370 + 8040910: e0bffd15 stw r2,-12(fp) + if (!npnet) + 8040914: e0bffd17 ldw r2,-12(fp) + 8040918: 1000021e bne r2,zero,8040924 + return EADDRNOTAVAIL; + 804091c: 00801f44 movi r2,125 + 8040920: 00003106 br 80409e8 + ifaddr = npnet->n_ipaddr; /* local address for this host */ + 8040924: e0bffd17 ldw r2,-12(fp) + 8040928: 10800a17 ldw r2,40(r2) + 804092c: e0bfff15 stw r2,-4(fp) + 8040930: 00000306 br 8040940 +#else /* not netport MULTI_HOMED, use 0th (only) iface */ + ifaddr = nets[0]->n_ipaddr; +#endif /* MULTI_HOMED */ + } + else /* inp->inp_laddr.s_addr != INADDR_ANY */ + ifaddr = inp->inp_laddr.s_addr; /* use address passed */ + 8040934: e0bffb17 ldw r2,-20(fp) + 8040938: 10800417 ldw r2,16(r2) + 804093c: e0bfff15 stw r2,-4(fp) + + if (in_pcblookup(inp->inp_head, + 8040940: e0bffb17 ldw r2,-20(fp) + 8040944: 10c00217 ldw r3,8(r2) + 8040948: e0bffe17 ldw r2,-8(fp) + 804094c: 11000117 ldw r4,4(r2) + sin->sin_addr.s_addr, + sin->sin_port, + 8040950: e0bffe17 ldw r2,-8(fp) + 8040954: 1080008b ldhu r2,2(r2) + if (in_pcblookup(inp->inp_head, + 8040958: 117fffcc andi r5,r2,65535 + ifaddr, + inp->inp_lport, + 804095c: e0bffb17 ldw r2,-20(fp) + 8040960: 1080078b ldhu r2,30(r2) + if (in_pcblookup(inp->inp_head, + 8040964: 10bfffcc andi r2,r2,65535 + 8040968: d8000115 stw zero,4(sp) + 804096c: d8800015 stw r2,0(sp) + 8040970: e1ffff17 ldw r7,-4(fp) + 8040974: 280d883a mov r6,r5 + 8040978: 200b883a mov r5,r4 + 804097c: 1809883a mov r4,r3 + 8040980: 8040b600 call 8040b60 + 8040984: 10000226 beq r2,zero,8040990 + 0)) + { + return (EADDRINUSE); + 8040988: 00801c04 movi r2,112 + 804098c: 00001606 br 80409e8 + } + if (inp->inp_laddr.s_addr == INADDR_ANY) + 8040990: e0bffb17 ldw r2,-20(fp) + 8040994: 10800417 ldw r2,16(r2) + 8040998: 10000a1e bne r2,zero,80409c4 + { + if (inp->inp_lport == 0) + 804099c: e0bffb17 ldw r2,-20(fp) + 80409a0: 1080078b ldhu r2,30(r2) + 80409a4: 10bfffcc andi r2,r2,65535 + 80409a8: 1000031e bne r2,zero,80409b8 + (void)in_pcbbind(inp, (struct mbuf *)0); + 80409ac: 000b883a mov r5,zero + 80409b0: e13ffb17 ldw r4,-20(fp) + 80409b4: 804060c0 call 804060c + inp->inp_laddr.s_addr = ifaddr; + 80409b8: e0bffb17 ldw r2,-20(fp) + 80409bc: e0ffff17 ldw r3,-4(fp) + 80409c0: 10c00415 stw r3,16(r2) + } + inp->inp_faddr = sin->sin_addr; + 80409c4: e0bffb17 ldw r2,-20(fp) + 80409c8: e0fffe17 ldw r3,-8(fp) + 80409cc: 18c00117 ldw r3,4(r3) + 80409d0: 10c00315 stw r3,12(r2) + inp->inp_fport = sin->sin_port; + 80409d4: e0bffe17 ldw r2,-8(fp) + 80409d8: 10c0008b ldhu r3,2(r2) + 80409dc: e0bffb17 ldw r2,-20(fp) + 80409e0: 10c0070d sth r3,28(r2) + return 0; + 80409e4: 0005883a mov r2,zero +} + 80409e8: e037883a mov sp,fp + 80409ec: dfc00117 ldw ra,4(sp) + 80409f0: df000017 ldw fp,0(sp) + 80409f4: dec00204 addi sp,sp,8 + 80409f8: f800283a ret + +080409fc : + * RETURNS: + */ + +void +in_pcbdisconnect(struct inpcb * inp) +{ + 80409fc: defffd04 addi sp,sp,-12 + 8040a00: dfc00215 stw ra,8(sp) + 8040a04: df000115 stw fp,4(sp) + 8040a08: df000104 addi fp,sp,4 + 8040a0c: e13fff15 stw r4,-4(fp) + + inp->inp_faddr.s_addr = INADDR_ANY; + 8040a10: e0bfff17 ldw r2,-4(fp) + 8040a14: 10000315 stw zero,12(r2) + inp->inp_fport = 0; + 8040a18: e0bfff17 ldw r2,-4(fp) + 8040a1c: 1000070d sth zero,28(r2) + if (inp->inp_socket->so_state & SS_NOFDREF) + 8040a20: e0bfff17 ldw r2,-4(fp) + 8040a24: 10800817 ldw r2,32(r2) + 8040a28: 1080088b ldhu r2,34(r2) + 8040a2c: 10bfffcc andi r2,r2,65535 + 8040a30: 1080004c andi r2,r2,1 + 8040a34: 10000226 beq r2,zero,8040a40 + in_pcbdetach (inp); + 8040a38: e13fff17 ldw r4,-4(fp) + 8040a3c: 80405b40 call 80405b4 +} + 8040a40: 0001883a nop + 8040a44: e037883a mov sp,fp + 8040a48: dfc00117 ldw ra,4(sp) + 8040a4c: df000017 ldw fp,0(sp) + 8040a50: dec00204 addi sp,sp,8 + 8040a54: f800283a ret + +08040a58 : + */ + +void +in_setsockaddr(struct inpcb * inp, + struct mbuf * nam) +{ + 8040a58: defffb04 addi sp,sp,-20 + 8040a5c: dfc00415 stw ra,16(sp) + 8040a60: df000315 stw fp,12(sp) + 8040a64: df000304 addi fp,sp,12 + 8040a68: e13ffe15 stw r4,-8(fp) + 8040a6c: e17ffd15 stw r5,-12(fp) + struct sockaddr_in * sin; + + nam->m_len = sizeof (*sin); + 8040a70: e0bffd17 ldw r2,-12(fp) + 8040a74: 00c00404 movi r3,16 + 8040a78: 10c00215 stw r3,8(r2) + sin = mtod(nam, struct sockaddr_in *); + 8040a7c: e0bffd17 ldw r2,-12(fp) + 8040a80: 10800317 ldw r2,12(r2) + 8040a84: e0bfff15 stw r2,-4(fp) + MEMSET(sin, 0, sizeof (*sin)); + 8040a88: 01800404 movi r6,16 + 8040a8c: 000b883a mov r5,zero + 8040a90: e13fff17 ldw r4,-4(fp) + 8040a94: 80088e40 call 80088e4 + sin->sin_family = AF_INET; + 8040a98: e0bfff17 ldw r2,-4(fp) + 8040a9c: 00c00084 movi r3,2 + 8040aa0: 10c0000d sth r3,0(r2) + sin->sin_port = inp->inp_lport; + 8040aa4: e0bffe17 ldw r2,-8(fp) + 8040aa8: 10c0078b ldhu r3,30(r2) + 8040aac: e0bfff17 ldw r2,-4(fp) + 8040ab0: 10c0008d sth r3,2(r2) + sin->sin_addr = inp->inp_laddr; + 8040ab4: e0bfff17 ldw r2,-4(fp) + 8040ab8: e0fffe17 ldw r3,-8(fp) + 8040abc: 18c00417 ldw r3,16(r3) + 8040ac0: 10c00115 stw r3,4(r2) +} + 8040ac4: 0001883a nop + 8040ac8: e037883a mov sp,fp + 8040acc: dfc00117 ldw ra,4(sp) + 8040ad0: df000017 ldw fp,0(sp) + 8040ad4: dec00204 addi sp,sp,8 + 8040ad8: f800283a ret + +08040adc : + +void +in_setpeeraddr( + struct inpcb * inp, + struct mbuf * nam) +{ + 8040adc: defffb04 addi sp,sp,-20 + 8040ae0: dfc00415 stw ra,16(sp) + 8040ae4: df000315 stw fp,12(sp) + 8040ae8: df000304 addi fp,sp,12 + 8040aec: e13ffe15 stw r4,-8(fp) + 8040af0: e17ffd15 stw r5,-12(fp) + struct sockaddr_in * sin; + + nam->m_len = sizeof (*sin); + 8040af4: e0bffd17 ldw r2,-12(fp) + 8040af8: 00c00404 movi r3,16 + 8040afc: 10c00215 stw r3,8(r2) + sin = mtod(nam, struct sockaddr_in *); + 8040b00: e0bffd17 ldw r2,-12(fp) + 8040b04: 10800317 ldw r2,12(r2) + 8040b08: e0bfff15 stw r2,-4(fp) + MEMSET(sin, 0, sizeof (*sin)); + 8040b0c: 01800404 movi r6,16 + 8040b10: 000b883a mov r5,zero + 8040b14: e13fff17 ldw r4,-4(fp) + 8040b18: 80088e40 call 80088e4 + sin->sin_family = AF_INET; + 8040b1c: e0bfff17 ldw r2,-4(fp) + 8040b20: 00c00084 movi r3,2 + 8040b24: 10c0000d sth r3,0(r2) + sin->sin_port = inp->inp_fport; + 8040b28: e0bffe17 ldw r2,-8(fp) + 8040b2c: 10c0070b ldhu r3,28(r2) + 8040b30: e0bfff17 ldw r2,-4(fp) + 8040b34: 10c0008d sth r3,2(r2) + sin->sin_addr = inp->inp_faddr; + 8040b38: e0bfff17 ldw r2,-4(fp) + 8040b3c: e0fffe17 ldw r3,-8(fp) + 8040b40: 18c00317 ldw r3,12(r3) + 8040b44: 10c00115 stw r3,4(r2) +} + 8040b48: 0001883a nop + 8040b4c: e037883a mov sp,fp + 8040b50: dfc00117 ldw ra,4(sp) + 8040b54: df000017 ldw fp,0(sp) + 8040b58: dec00204 addi sp,sp,8 + 8040b5c: f800283a ret + +08040b60 : + u_long faddr, + unshort xfport, + u_long laddr, + unshort xlport, + int flags) +{ + 8040b60: defff504 addi sp,sp,-44 + 8040b64: df000a15 stw fp,40(sp) + 8040b68: df000a04 addi fp,sp,40 + 8040b6c: e13ffa15 stw r4,-24(fp) + 8040b70: e17ff915 stw r5,-28(fp) + 8040b74: 3007883a mov r3,r6 + 8040b78: e1fff715 stw r7,-36(fp) + 8040b7c: e0800117 ldw r2,4(fp) + 8040b80: e0fff80d sth r3,-32(fp) + 8040b84: e0bff60d sth r2,-40(fp) + struct inpcb * inp, * match = 0; + 8040b88: e03ffe15 stw zero,-8(fp) + unshort fport = xfport; + 8040b8c: e0bff80b ldhu r2,-32(fp) + 8040b90: e0bffb8d sth r2,-18(fp) + unshort lport = xlport; + 8040b94: e0bff60b ldhu r2,-40(fp) + 8040b98: e0bffb0d sth r2,-20(fp) + int matchwild = 3; + 8040b9c: 008000c4 movi r2,3 + 8040ba0: e0bffd15 stw r2,-12(fp) + int wildcard; + + for (inp = head->inp_next; inp != head; inp = inp->inp_next) + 8040ba4: e0bffa17 ldw r2,-24(fp) + 8040ba8: 10800017 ldw r2,0(r2) + 8040bac: e0bfff15 stw r2,-4(fp) + 8040bb0: 00004f06 br 8040cf0 + { + if (inp->inp_lport != lport) + 8040bb4: e0bfff17 ldw r2,-4(fp) + 8040bb8: 1080078b ldhu r2,30(r2) + 8040bbc: e0fffb0b ldhu r3,-20(fp) + 8040bc0: 10bfffcc andi r2,r2,65535 + 8040bc4: 1880401e bne r3,r2,8040cc8 + continue; + + /* Skip non IPv4 sockets */ + if(inp->inp_socket->so_domain != AF_INET) + 8040bc8: e0bfff17 ldw r2,-4(fp) + 8040bcc: 10800817 ldw r2,32(r2) + 8040bd0: 10800517 ldw r2,20(r2) + 8040bd4: 108000a0 cmpeqi r2,r2,2 + 8040bd8: 10003d26 beq r2,zero,8040cd0 + continue; + + wildcard = 0; + 8040bdc: e03ffc15 stw zero,-16(fp) + if (inp->inp_laddr.s_addr != INADDR_ANY) + 8040be0: e0bfff17 ldw r2,-4(fp) + 8040be4: 10800417 ldw r2,16(r2) + 8040be8: 10000b26 beq r2,zero,8040c18 + { + if (laddr == INADDR_ANY) + 8040bec: e0bff717 ldw r2,-36(fp) + 8040bf0: 1000041e bne r2,zero,8040c04 + wildcard++; + 8040bf4: e0bffc17 ldw r2,-16(fp) + 8040bf8: 10800044 addi r2,r2,1 + 8040bfc: e0bffc15 stw r2,-16(fp) + 8040c00: 00000a06 br 8040c2c + else if (inp->inp_laddr.s_addr != laddr) + 8040c04: e0bfff17 ldw r2,-4(fp) + 8040c08: 10800417 ldw r2,16(r2) + 8040c0c: e0fff717 ldw r3,-36(fp) + 8040c10: 18800626 beq r3,r2,8040c2c + continue; + 8040c14: 00003306 br 8040ce4 + } + else + { + if (laddr != INADDR_ANY) + 8040c18: e0bff717 ldw r2,-36(fp) + 8040c1c: 10000326 beq r2,zero,8040c2c + wildcard++; + 8040c20: e0bffc17 ldw r2,-16(fp) + 8040c24: 10800044 addi r2,r2,1 + 8040c28: e0bffc15 stw r2,-16(fp) + } + if (inp->inp_faddr.s_addr != INADDR_ANY) + 8040c2c: e0bfff17 ldw r2,-4(fp) + 8040c30: 10800317 ldw r2,12(r2) + 8040c34: 10001026 beq r2,zero,8040c78 + { + if (faddr == INADDR_ANY) + 8040c38: e0bff917 ldw r2,-28(fp) + 8040c3c: 1000041e bne r2,zero,8040c50 + wildcard++; + 8040c40: e0bffc17 ldw r2,-16(fp) + 8040c44: 10800044 addi r2,r2,1 + 8040c48: e0bffc15 stw r2,-16(fp) + 8040c4c: 00000f06 br 8040c8c + else if (inp->inp_faddr.s_addr != faddr || + 8040c50: e0bfff17 ldw r2,-4(fp) + 8040c54: 10800317 ldw r2,12(r2) + 8040c58: e0fff917 ldw r3,-28(fp) + 8040c5c: 18801e1e bne r3,r2,8040cd8 + inp->inp_fport != fport) + 8040c60: e0bfff17 ldw r2,-4(fp) + 8040c64: 1080070b ldhu r2,28(r2) + else if (inp->inp_faddr.s_addr != faddr || + 8040c68: e0fffb8b ldhu r3,-18(fp) + 8040c6c: 10bfffcc andi r2,r2,65535 + 8040c70: 18800626 beq r3,r2,8040c8c + { + continue; + 8040c74: 00001806 br 8040cd8 + } + } else + { + if (faddr != INADDR_ANY) + 8040c78: e0bff917 ldw r2,-28(fp) + 8040c7c: 10000326 beq r2,zero,8040c8c + wildcard++; + 8040c80: e0bffc17 ldw r2,-16(fp) + 8040c84: 10800044 addi r2,r2,1 + 8040c88: e0bffc15 stw r2,-16(fp) + } + if (wildcard && (flags & INPLOOKUP_WILDCARD) == 0) + 8040c8c: e0bffc17 ldw r2,-16(fp) + 8040c90: 10000326 beq r2,zero,8040ca0 + 8040c94: e0800217 ldw r2,8(fp) + 8040c98: 1080004c andi r2,r2,1 + 8040c9c: 10001026 beq r2,zero,8040ce0 + continue; + if (wildcard < matchwild) + 8040ca0: e0fffc17 ldw r3,-16(fp) + 8040ca4: e0bffd17 ldw r2,-12(fp) + 8040ca8: 18800e0e bge r3,r2,8040ce4 + { + match = inp; + 8040cac: e0bfff17 ldw r2,-4(fp) + 8040cb0: e0bffe15 stw r2,-8(fp) + matchwild = wildcard; + 8040cb4: e0bffc17 ldw r2,-16(fp) + 8040cb8: e0bffd15 stw r2,-12(fp) + if (matchwild == 0) + 8040cbc: e0bffd17 ldw r2,-12(fp) + 8040cc0: 10000f26 beq r2,zero,8040d00 + 8040cc4: 00000706 br 8040ce4 + continue; + 8040cc8: 0001883a nop + 8040ccc: 00000506 br 8040ce4 + continue; + 8040cd0: 0001883a nop + 8040cd4: 00000306 br 8040ce4 + continue; + 8040cd8: 0001883a nop + 8040cdc: 00000106 br 8040ce4 + continue; + 8040ce0: 0001883a nop + for (inp = head->inp_next; inp != head; inp = inp->inp_next) + 8040ce4: e0bfff17 ldw r2,-4(fp) + 8040ce8: 10800017 ldw r2,0(r2) + 8040cec: e0bfff15 stw r2,-4(fp) + 8040cf0: e0ffff17 ldw r3,-4(fp) + 8040cf4: e0bffa17 ldw r2,-24(fp) + 8040cf8: 18bfae1e bne r3,r2,8040bb4 + 8040cfc: 00000106 br 8040d04 + break; + 8040d00: 0001883a nop + } + } + if (match == NULL) + 8040d04: e0bffe17 ldw r2,-8(fp) + 8040d08: 1000021e bne r2,zero,8040d14 + return match; + 8040d0c: e0bffe17 ldw r2,-8(fp) + 8040d10: 00002406 br 8040da4 + + if (head->inp_next == match) /* got cache hit? */ + 8040d14: e0bffa17 ldw r2,-24(fp) + 8040d18: 10800017 ldw r2,0(r2) + 8040d1c: e0fffe17 ldw r3,-8(fp) + 8040d20: 1880041e bne r3,r2,8040d34 + { + inpcb_cachehits++; + 8040d24: d0a09f17 ldw r2,-32132(gp) + 8040d28: 10800044 addi r2,r2,1 + 8040d2c: d0a09f15 stw r2,-32132(gp) + 8040d30: 00001b06 br 8040da0 + } + else + { + inpcb_cachemiss++; + 8040d34: d0a0a017 ldw r2,-32128(gp) + 8040d38: 10800044 addi r2,r2,1 + 8040d3c: d0a0a015 stw r2,-32128(gp) + /* "cache" the match to be first checked next time. */ + match->inp_next->inp_prev = match->inp_prev; /*unlink match */ + 8040d40: e0bffe17 ldw r2,-8(fp) + 8040d44: 10800017 ldw r2,0(r2) + 8040d48: e0fffe17 ldw r3,-8(fp) + 8040d4c: 18c00117 ldw r3,4(r3) + 8040d50: 10c00115 stw r3,4(r2) + match->inp_prev->inp_next = match->inp_next; + 8040d54: e0bffe17 ldw r2,-8(fp) + 8040d58: 10800117 ldw r2,4(r2) + 8040d5c: e0fffe17 ldw r3,-8(fp) + 8040d60: 18c00017 ldw r3,0(r3) + 8040d64: 10c00015 stw r3,0(r2) + + /* relink match as head->inp_next */ + match->inp_next = head->inp_next; + 8040d68: e0bffa17 ldw r2,-24(fp) + 8040d6c: 10c00017 ldw r3,0(r2) + 8040d70: e0bffe17 ldw r2,-8(fp) + 8040d74: 10c00015 stw r3,0(r2) + head->inp_next = match; + 8040d78: e0bffa17 ldw r2,-24(fp) + 8040d7c: e0fffe17 ldw r3,-8(fp) + 8040d80: 10c00015 stw r3,0(r2) + match->inp_prev = head; + 8040d84: e0bffe17 ldw r2,-8(fp) + 8040d88: e0fffa17 ldw r3,-24(fp) + 8040d8c: 10c00115 stw r3,4(r2) + match->inp_next->inp_prev = match; + 8040d90: e0bffe17 ldw r2,-8(fp) + 8040d94: 10800017 ldw r2,0(r2) + 8040d98: e0fffe17 ldw r3,-8(fp) + 8040d9c: 10c00115 stw r3,4(r2) + } + return (match); + 8040da0: e0bffe17 ldw r2,-8(fp) +} + 8040da4: e037883a mov sp,fp + 8040da8: df000017 ldw fp,0(sp) + 8040dac: dec00104 addi sp,sp,4 + 8040db0: f800283a ret + +08040db4 : + * + * RETURNS: + */ + +void set_vfopen_error(int error) +{ + 8040db4: defffe04 addi sp,sp,-8 + 8040db8: df000115 stw fp,4(sp) + 8040dbc: df000104 addi fp,sp,4 + 8040dc0: e13fff15 stw r4,-4(fp) + vfopen_error = error; + 8040dc4: e0bfff17 ldw r2,-4(fp) + 8040dc8: d0a0a415 stw r2,-32112(gp) +} + 8040dcc: 0001883a nop + 8040dd0: e037883a mov sp,fp + 8040dd4: df000017 ldw fp,0(sp) + 8040dd8: dec00104 addi sp,sp,4 + 8040ddc: f800283a ret + +08040de0 : + * + * RETURNS: + */ + +int get_vfopen_error() +{ + 8040de0: deffff04 addi sp,sp,-4 + 8040de4: df000015 stw fp,0(sp) + 8040de8: d839883a mov fp,sp + return vfopen_error; + 8040dec: d0a0a417 ldw r2,-32112(gp) +} + 8040df0: e037883a mov sp,fp + 8040df4: df000017 ldw fp,0(sp) + 8040df8: dec00104 addi sp,sp,4 + 8040dfc: f800283a ret + +08040e00 : + * + * RETURNS: + */ + +VFILE * vf_alloc_and_link_vop() +{ + 8040e00: defffd04 addi sp,sp,-12 + 8040e04: dfc00215 stw ra,8(sp) + 8040e08: df000115 stw fp,4(sp) + 8040e0c: df000104 addi fp,sp,4 + struct vfs_open * vop; + + /* enforce maximum number of simultaneously open files */ + if (vfs_open_files >= VFS_MAX_OPEN_FILES) + 8040e10: d0a0a617 ldw r2,-32104(gp) + 8040e14: 10803ff0 cmpltui r2,r2,255 + 8040e18: 1000021e bne r2,zero,8040e24 + { +#ifdef VFS_VERBOSE + dprintf("vfs_open_files too big (%ld) in vf_alloc_and_link_vop()\n", + vfs_open_files); +#endif /* VFS_VERBOSE */ + return NULL; + 8040e1c: 0005883a mov r2,zero + 8040e20: 00000e06 br 8040e5c + } + + /* allocate a structure to represent the open file */ + vop = VFS_VFS_OPEN_ALLOC(); + 8040e24: 01000504 movi r4,20 + 8040e28: 802982c0 call 802982c + 8040e2c: e0bfff15 stw r2,-4(fp) + + /* if the allocation succeeded */ + if (vop) + 8040e30: e0bfff17 ldw r2,-4(fp) + 8040e34: 10000826 beq r2,zero,8040e58 + { + /* add to the beginning of the list of open files */ + vop->next = vfiles; + 8040e38: d0e0a217 ldw r3,-32120(gp) + 8040e3c: e0bfff17 ldw r2,-4(fp) + 8040e40: 10c00015 stw r3,0(r2) + vfiles = vop; + 8040e44: e0bfff17 ldw r2,-4(fp) + 8040e48: d0a0a215 stw r2,-32120(gp) + /* increment the count of open files */ + vfs_open_files++; + 8040e4c: d0a0a617 ldw r2,-32104(gp) + 8040e50: 10800044 addi r2,r2,1 + 8040e54: d0a0a615 stw r2,-32104(gp) +#ifdef VFS_VERBOSE + else + dprintf("VFS_VFS_OPEN_ALLOC() failed in vf_alloc_and_link_vop()\n"); +#endif /* VFS_VERBOSE */ + + return vop; + 8040e58: e0bfff17 ldw r2,-4(fp) +} + 8040e5c: e037883a mov sp,fp + 8040e60: dfc00117 ldw ra,4(sp) + 8040e64: df000017 ldw fp,0(sp) + 8040e68: dec00204 addi sp,sp,8 + 8040e6c: f800283a ret + +08040e70 : + * + * RETURNS: + */ + +unsigned char * vf_alloc_buffer(unsigned long size) +{ + 8040e70: defff904 addi sp,sp,-28 + 8040e74: dfc00615 stw ra,24(sp) + 8040e78: df000515 stw fp,20(sp) + 8040e7c: df000504 addi fp,sp,20 + 8040e80: e13ffb15 stw r4,-20(fp) + unsigned int long_size,int_size; +#endif /* MUTE_WARNS */ + + /* make sure the requested allocation does not exceed the total + memory space reserved for file buffers */ + if ((vfs_total_rw_space + size) > VFS_MAX_TOTAL_RW_SPACE) + 8040e84: d0e0a717 ldw r3,-32100(gp) + 8040e88: e0bffb17 ldw r2,-20(fp) + 8040e8c: 1885883a add r2,r3,r2 + 8040e90: 00ffffd4 movui r3,65535 + 8040e94: 1880022e bgeu r3,r2,8040ea0 + return NULL; + 8040e98: 0005883a mov r2,zero + 8040e9c: 00002106 br 8040f24 + * any bigger than what will fit in an unsigned int + */ +#ifdef MUTE_WARNS + /* the idiotic hoops you got to jump through to suppress compiler + warnings */ + long_size = sizeof(unsigned long); + 8040ea0: 00800104 movi r2,4 + 8040ea4: e0bfff15 stw r2,-4(fp) + int_size = sizeof(unsigned int); + 8040ea8: 00800104 movi r2,4 + 8040eac: e0bffe15 stw r2,-8(fp) + if (long_size > int_size) + 8040eb0: e0bfff17 ldw r2,-4(fp) + 8040eb4: e0fffe17 ldw r3,-8(fp) + 8040eb8: 1880102e bgeu r3,r2,8040efc + * most systems where this "if" expression will evaluate to + * true (2 byte ints, 4 byte longs). if any of those upper bits + * are on in your requested size, you otta luck. + */ +#ifdef MUTE_WARNS + switch (int_size) + 8040ebc: e0bffe17 ldw r2,-8(fp) + 8040ec0: 10800098 cmpnei r2,r2,2 + 8040ec4: 1000081e bne r2,zero,8040ee8 +#else + switch (sizeof(unsigned int)) +#endif /* MUTE_WARNS */ + { + case 2 : + mem_mask = 0xffff0000; + 8040ec8: 00bffff4 movhi r2,65535 + 8040ecc: e0bffd15 stw r2,-12(fp) + break; + 8040ed0: 0001883a nop + default : + dtrap(); /* you have a weird compiler */ + return NULL; + } + + if (size & mem_mask) + 8040ed4: e0fffb17 ldw r3,-20(fp) + 8040ed8: e0bffd17 ldw r2,-12(fp) + 8040edc: 1884703a and r2,r3,r2 + 8040ee0: 10000626 beq r2,zero,8040efc + 8040ee4: 00000306 br 8040ef4 + dtrap(); /* you have a weird compiler */ + 8040ee8: 8028cd40 call 8028cd4 + return NULL; + 8040eec: 0005883a mov r2,zero + 8040ef0: 00000c06 br 8040f24 + return NULL; + 8040ef4: 0005883a mov r2,zero + 8040ef8: 00000a06 br 8040f24 + } + + /* try to allocate a buffer of the requested size */ + buffer = (unsigned char *) npalloc((unsigned int) size); + 8040efc: e13ffb17 ldw r4,-20(fp) + 8040f00: 802982c0 call 802982c + 8040f04: e0bffc15 stw r2,-16(fp) + + /* if the allocation succeeded */ + if (buffer) + 8040f08: e0bffc17 ldw r2,-16(fp) + 8040f0c: 10000426 beq r2,zero,8040f20 + { + /* add size to the count of total buffer space allocated */ + vfs_total_rw_space += size; + 8040f10: d0e0a717 ldw r3,-32100(gp) + 8040f14: e0bffb17 ldw r2,-20(fp) + 8040f18: 1885883a add r2,r3,r2 + 8040f1c: d0a0a715 stw r2,-32100(gp) + } + + return buffer; + 8040f20: e0bffc17 ldw r2,-16(fp) +} + 8040f24: e037883a mov sp,fp + 8040f28: dfc00117 ldw ra,4(sp) + 8040f2c: df000017 ldw fp,0(sp) + 8040f30: dec00204 addi sp,sp,8 + 8040f34: f800283a ret + +08040f38 : + * + * RETURNS: + */ + +void vf_free_buffer(unsigned char * buffer, unsigned long size) +{ + 8040f38: defffc04 addi sp,sp,-16 + 8040f3c: dfc00315 stw ra,12(sp) + 8040f40: df000215 stw fp,8(sp) + 8040f44: df000204 addi fp,sp,8 + 8040f48: e13fff15 stw r4,-4(fp) + 8040f4c: e17ffe15 stw r5,-8(fp) + /* free the buffer */ + if (buffer) + 8040f50: e0bfff17 ldw r2,-4(fp) + 8040f54: 10000226 beq r2,zero,8040f60 + npfree(buffer); + 8040f58: e13fff17 ldw r4,-4(fp) + 8040f5c: 80298600 call 8029860 + + /* and subtract its size from the total buffer space count */ + vfs_total_rw_space -= size; + 8040f60: d0e0a717 ldw r3,-32100(gp) + 8040f64: e0bffe17 ldw r2,-8(fp) + 8040f68: 1885c83a sub r2,r3,r2 + 8040f6c: d0a0a715 stw r2,-32100(gp) +} + 8040f70: 0001883a nop + 8040f74: e037883a mov sp,fp + 8040f78: dfc00117 ldw ra,4(sp) + 8040f7c: df000017 ldw fp,0(sp) + 8040f80: dec00204 addi sp,sp,8 + 8040f84: f800283a ret + +08040f88 : + * RETURNS: + */ + +VFILE * +vfopen_locked(char * name, char * mode) +{ + 8040f88: defff904 addi sp,sp,-28 + 8040f8c: dfc00615 stw ra,24(sp) + 8040f90: df000515 stw fp,20(sp) + 8040f94: df000504 addi fp,sp,20 + 8040f98: e13ffc15 stw r4,-16(fp) + 8040f9c: e17ffb15 stw r5,-20(fp) + struct vfs_file * vfp; + struct vfs_open * vop; + + /* clear any previous vfopen() error */ + set_vfopen_error(0); + 8040fa0: 0009883a mov r4,zero + 8040fa4: 8040db40 call 8040db4 + + /* the old code used to do special handling of '?' in files for + * the benefit of the web server. the web server should be doing + * this now. this is here to make sure that its doing it + */ + if (strchr(name,'?')) + 8040fa8: 01400fc4 movi r5,63 + 8040fac: e13ffc17 ldw r4,-16(fp) + 8040fb0: 8042dfc0 call 8042dfc + 8040fb4: 10000326 beq r2,zero,8040fc4 + { + dtrap(); + 8040fb8: 8028cd40 call 8028cd4 + return NULL; + 8040fbc: 0005883a mov r2,zero + 8040fc0: 0000ba06 br 80412ac + } + + /* determine if the file exists */ + /* if the directory exists, vfp will point to its directory entry + structure else vfp will be NULL */ + vfp = vfslookup_locked(name); + 8040fc4: e13ffc17 ldw r4,-16(fp) + 8040fc8: 80422080 call 8042208 + 8040fcc: e0bffe15 stw r2,-8(fp) + + /* if the file exists */ + if (vfp) + 8040fd0: e0bffe17 ldw r2,-8(fp) + 8040fd4: 10004a26 beq r2,zero,8041100 + +#ifdef HT_RWVFS + + /* if mode begins with 'w' we will truncate to end of file */ + /* make sure the file is writable before proceeding */ + if ((*mode == 'w') && !(vfp->flags & VF_WRITE)) + 8040fd8: e0bffb17 ldw r2,-20(fp) + 8040fdc: 10800003 ldbu r2,0(r2) + 8040fe0: 10803fcc andi r2,r2,255 + 8040fe4: 1080201c xori r2,r2,128 + 8040fe8: 10bfe004 addi r2,r2,-128 + 8040fec: 10801dd8 cmpnei r2,r2,119 + 8040ff0: 1000091e bne r2,zero,8041018 + 8040ff4: e0bffe17 ldw r2,-8(fp) + 8040ff8: 1080058b ldhu r2,22(r2) + 8040ffc: 10bfffcc andi r2,r2,65535 + 8041000: 1080080c andi r2,r2,32 + 8041004: 1000041e bne r2,zero,8041018 + { + set_vfopen_error(ENP_FILEIO); + 8041008: 013ff984 movi r4,-26 + 804100c: 8040db40 call 8040db4 +#ifdef VFS_VERBOSE + dprintf("mode w with no VF_WRITE\n"); +#endif /* VFS_VERBOSE */ + return NULL; + 8041010: 0005883a mov r2,zero + 8041014: 0000a506 br 80412ac + } + +#endif /* HT_RWVFS */ + + /* allocate a VFILE structure to represent the open file */ + vop = vf_alloc_and_link_vop(); + 8041018: 8040e000 call 8040e00 + 804101c: e0bffd15 stw r2,-12(fp) + + /* check for failure */ + if (!vop) + 8041020: e0bffd17 ldw r2,-12(fp) + 8041024: 1000041e bne r2,zero,8041038 + { + set_vfopen_error(ENP_NOMEM); + 8041028: 013ffb04 movi r4,-20 + 804102c: 8040db40 call 8040db4 +#ifdef VFS_VERBOSE + dprintf("vf_alloc_and_link_vop() failed 1\n"); +#endif /* VFS_VERBOSE */ + return NULL; + 8041030: 0005883a mov r2,zero + 8041034: 00009d06 br 80412ac + } + + /* link to the file's directory entry structure */ + vop->file = vfp; + 8041038: e0bffd17 ldw r2,-12(fp) + 804103c: e0fffe17 ldw r3,-8(fp) + 8041040: 10c00115 stw r3,4(r2) + + /* by default start at the beginning of the file */ + /* note that vfp->data could be NULL at this point since empty + files might have no data buffer allocated to them */ + vop->cmploc = vfp->data; /* start at beginning of file */ + 8041044: e0bffe17 ldw r2,-8(fp) + 8041048: 10c00617 ldw r3,24(r2) + 804104c: e0bffd17 ldw r2,-12(fp) + 8041050: 10c00215 stw r3,8(r2) + +#ifdef HT_RWVFS + + /* if mode begins with 'a', seek to end of file */ + if (*mode == 'a') + 8041054: e0bffb17 ldw r2,-20(fp) + 8041058: 10800003 ldbu r2,0(r2) + 804105c: 10803fcc andi r2,r2,255 + 8041060: 1080201c xori r2,r2,128 + 8041064: 10bfe004 addi r2,r2,-128 + 8041068: 10801858 cmpnei r2,r2,97 + 804106c: 10000a1e bne r2,zero,8041098 + { + if (vfp->data) + 8041070: e0bffe17 ldw r2,-8(fp) + 8041074: 10800617 ldw r2,24(r2) + 8041078: 10000726 beq r2,zero,8041098 + { + vop->cmploc = vfp->data + vfp->comp_size; + 804107c: e0bffe17 ldw r2,-8(fp) + 8041080: 10c00617 ldw r3,24(r2) + 8041084: e0bffe17 ldw r2,-8(fp) + 8041088: 10800817 ldw r2,32(r2) + 804108c: 1887883a add r3,r3,r2 + 8041090: e0bffd17 ldw r2,-12(fp) + 8041094: 10c00215 stw r3,8(r2) + } + } + + /* if mode begins with 'w', truncate to end of file */ + if (*mode == 'w') + 8041098: e0bffb17 ldw r2,-20(fp) + 804109c: 10800003 ldbu r2,0(r2) + 80410a0: 10803fcc andi r2,r2,255 + 80410a4: 1080201c xori r2,r2,128 + 80410a8: 10bfe004 addi r2,r2,-128 + 80410ac: 10801dd8 cmpnei r2,r2,119 + 80410b0: 1000111e bne r2,zero,80410f8 + { + /* set the size of the file before compression to 0 */ + vfp->real_size = 0; + 80410b4: e0bffe17 ldw r2,-8(fp) + 80410b8: 10000715 stw zero,28(r2) + /* set the size of the compressed data to 0 */ + vfp->comp_size = 0; + 80410bc: e0bffe17 ldw r2,-8(fp) + 80410c0: 10000815 stw zero,32(r2) + /* note we leave the pointer to the file buffer and its length + alone since first writes will go to it */ + /* flag that the file has been modified */ + vfp->flags |= VF_STALE; + 80410c4: e0bffe17 ldw r2,-8(fp) + 80410c8: 1080058b ldhu r2,22(r2) + 80410cc: 10808014 ori r2,r2,512 + 80410d0: 1007883a mov r3,r2 + 80410d4: e0bffe17 ldw r2,-8(fp) + 80410d8: 10c0058d sth r3,22(r2) + + /* turn off the compression flag */ + vfp->flags &= ~VF_HTMLCOMPRESSED; + 80410dc: e0bffe17 ldw r2,-8(fp) + 80410e0: 10c0058b ldhu r3,22(r2) + 80410e4: 00bfff84 movi r2,-2 + 80410e8: 1884703a and r2,r3,r2 + 80410ec: 1007883a mov r3,r2 + 80410f0: e0bffe17 ldw r2,-8(fp) + 80410f4: 10c0058d sth r3,22(r2) + } + +#endif /* HT_RWVFS */ + + return vop; + 80410f8: e0bffd17 ldw r2,-12(fp) + 80410fc: 00006b06 br 80412ac + +#ifdef HT_EXTDEV + + /* if the mode implies that the file should be created if it + does not exist */ + if (*mode != 'r') + 8041100: e0bffb17 ldw r2,-20(fp) + 8041104: 10800003 ldbu r2,0(r2) + 8041108: 10803fcc andi r2,r2,255 + 804110c: 1080201c xori r2,r2,128 + 8041110: 10bfe004 addi r2,r2,-128 + 8041114: 10801ca0 cmpeqi r2,r2,114 + 8041118: 1000121e bne r2,zero,8041164 + { + /* see if one of the other systems wants to create this file */ + /* if none of the below devices can open the file, continue on */ + struct vfroutines * vfs; + + for (vfs = vfsystems; vfs; vfs = vfs->next) + 804111c: d0a0a117 ldw r2,-32124(gp) + 8041120: e0bfff15 stw r2,-4(fp) + 8041124: 00000d06 br 804115c + { + if ((vop = vfs->r_fopen(name, mode)) != NULL) + 8041128: e0bfff17 ldw r2,-4(fp) + 804112c: 10800117 ldw r2,4(r2) + 8041130: e17ffb17 ldw r5,-20(fp) + 8041134: e13ffc17 ldw r4,-16(fp) + 8041138: 103ee83a callr r2 + 804113c: e0bffd15 stw r2,-12(fp) + 8041140: e0bffd17 ldw r2,-12(fp) + 8041144: 10000226 beq r2,zero,8041150 + { + return vop; + 8041148: e0bffd17 ldw r2,-12(fp) + 804114c: 00005706 br 80412ac + for (vfs = vfsystems; vfs; vfs = vfs->next) + 8041150: e0bfff17 ldw r2,-4(fp) + 8041154: 10800017 ldw r2,0(r2) + 8041158: e0bfff15 stw r2,-4(fp) + 804115c: e0bfff17 ldw r2,-4(fp) + 8041160: 103ff11e bne r2,zero,8041128 + +#ifdef HT_RWVFS + + /* if the mode implies that the file should be created if it + does not exist */ + if (*mode != 'r') + 8041164: e0bffb17 ldw r2,-20(fp) + 8041168: 10800003 ldbu r2,0(r2) + 804116c: 10803fcc andi r2,r2,255 + 8041170: 1080201c xori r2,r2,128 + 8041174: 10bfe004 addi r2,r2,-128 + 8041178: 10801ca0 cmpeqi r2,r2,114 + 804117c: 1000481e bne r2,zero,80412a0 + { + /* enforce maximum number of files */ + if (vfs_total_dyna_files >= VFS_MAX_DYNA_FILES) + 8041180: d0a0a817 ldw r2,-32096(gp) + 8041184: 10803ff0 cmpltui r2,r2,255 + 8041188: 1000041e bne r2,zero,804119c + { + set_vfopen_error(ENP_NOMEM); + 804118c: 013ffb04 movi r4,-20 + 8041190: 8040db40 call 8040db4 +#ifdef VFS_VERBOSE + dprintf("vf_total_dyna_files too big in vfopen_locked()\n"); +#endif /* VFS_VERBOSE */ + return NULL; + 8041194: 0005883a mov r2,zero + 8041198: 00004406 br 80412ac + } + + /* make sure the file name is not too long for the VFS */ + if (strlen(name) > FILENAMEMAX) + 804119c: e13ffc17 ldw r4,-16(fp) + 80411a0: 8002dac0 call 8002dac + 80411a4: 10800470 cmpltui r2,r2,17 + 80411a8: 1000041e bne r2,zero,80411bc + { + set_vfopen_error(ENP_PARAM); + 80411ac: 013ffd84 movi r4,-10 + 80411b0: 8040db40 call 8040db4 +#ifdef VFS_VERBOSE + dprintf("file name too long in vfopen_locked()\n"); +#endif /* VFS_VERBOSE */ + return NULL; + 80411b4: 0005883a mov r2,zero + 80411b8: 00003c06 br 80412ac + } + + /* allocate a vfs_file structure to hold the new file entry in */ + vfp = VFS_VFS_FILE_ALLOC(); + 80411bc: 01000b04 movi r4,44 + 80411c0: 802982c0 call 802982c + 80411c4: e0bffe15 stw r2,-8(fp) + + /* check for memory allocation failure */ + if (!vfp) + 80411c8: e0bffe17 ldw r2,-8(fp) + 80411cc: 1000041e bne r2,zero,80411e0 + { + set_vfopen_error(ENP_NOMEM); + 80411d0: 013ffb04 movi r4,-20 + 80411d4: 8040db40 call 8040db4 +#ifdef VFS_VERBOSE + dprintf("VFS_VFS_FILE_ALLOC() failed in vfopen_locked()\n"); +#endif /* VFS_VERBOSE */ + return NULL; + 80411d8: 0005883a mov r2,zero + 80411dc: 00003306 br 80412ac + } + + /* allocate a VFILE structure to represent the open file */ + vop = vf_alloc_and_link_vop(); + 80411e0: 8040e000 call 8040e00 + 80411e4: e0bffd15 stw r2,-12(fp) + + /* check for memory allocation failure */ + if (!vop) + 80411e8: e0bffd17 ldw r2,-12(fp) + 80411ec: 1000061e bne r2,zero,8041208 + { + VFS_VFS_FILE_FREE(vfp); /* free the allocated vfs_file entry */ + 80411f0: e13ffe17 ldw r4,-8(fp) + 80411f4: 80298600 call 8029860 + set_vfopen_error(ENP_NOMEM); + 80411f8: 013ffb04 movi r4,-20 + 80411fc: 8040db40 call 8040db4 +#ifdef VFS_VERBOSE + dprintf("vf_alloc_and_link_vop() failed 2\n"); +#endif /* VFS_VERBOSE */ + return NULL; + 8041200: 0005883a mov r2,zero + 8041204: 00002906 br 80412ac + } + + /* add the vfs_file structure to the head of the list */ + + vfp->next = vfsfiles; + 8041208: d0e0a317 ldw r3,-32116(gp) + 804120c: e0bffe17 ldw r2,-8(fp) + 8041210: 10c00015 stw r3,0(r2) + vfsfiles = vfp; + 8041214: e0bffe17 ldw r2,-8(fp) + 8041218: d0a0a315 stw r2,-32116(gp) + + /* increment count of total files */ + vfs_total_dyna_files++; + 804121c: d0a0a817 ldw r2,-32096(gp) + 8041220: 10800044 addi r2,r2,1 + 8041224: d0a0a815 stw r2,-32096(gp) + + /* remove leading directory separator before storing name */ + if (*name == '/' || *name == '\\') + 8041228: e0bffc17 ldw r2,-16(fp) + 804122c: 10800003 ldbu r2,0(r2) + 8041230: 10803fcc andi r2,r2,255 + 8041234: 1080201c xori r2,r2,128 + 8041238: 10bfe004 addi r2,r2,-128 + 804123c: 10800be0 cmpeqi r2,r2,47 + 8041240: 1000071e bne r2,zero,8041260 + 8041244: e0bffc17 ldw r2,-16(fp) + 8041248: 10800003 ldbu r2,0(r2) + 804124c: 10803fcc andi r2,r2,255 + 8041250: 1080201c xori r2,r2,128 + 8041254: 10bfe004 addi r2,r2,-128 + 8041258: 10801718 cmpnei r2,r2,92 + 804125c: 1000031e bne r2,zero,804126c + name++; + 8041260: e0bffc17 ldw r2,-16(fp) + 8041264: 10800044 addi r2,r2,1 + 8041268: e0bffc15 stw r2,-16(fp) + + /* store the converted name in the directory entry structure */ + strcpy(vfp->name,name); + 804126c: e0bffe17 ldw r2,-8(fp) + 8041270: 10800104 addi r2,r2,4 + 8041274: e17ffc17 ldw r5,-16(fp) + 8041278: 1009883a mov r4,r2 + 804127c: 8042f600 call 8042f60 + + /* set the flags */ + vfp->flags = VF_DYNAMICINFO /* the directory entry was allocated */ + 8041280: e0bffe17 ldw r2,-8(fp) + 8041284: 00c0d804 movi r3,864 + 8041288: 10c0058d sth r3,22(r2) + * note that this means the data pointer contains a null + * because we don't allocate any buffer to hold the data + * in until the first write + */ + /* link to the file's directory entry structure */ + vop->file = vfp; + 804128c: e0bffd17 ldw r2,-12(fp) + 8041290: e0fffe17 ldw r3,-8(fp) + 8041294: 10c00115 stw r3,4(r2) + /* the cmploc and tag fields of the vop retain their NULLs from + * npalloc(). cmploc contains NULL because there is no data + * buffer to point to yet. tag contains NULL because no + * decompression operation has started yet + */ + return vop; + 8041298: e0bffd17 ldw r2,-12(fp) + 804129c: 00000306 br 80412ac + /* pass the open to the local file system */ + return (VFILE *) fopen(name,mode); + +#else + + set_vfopen_error(ENP_NOFILE); + 80412a0: 013ff9c4 movi r4,-25 + 80412a4: 8040db40 call 8040db4 +#ifdef VFS_VERBOSE + dprintf("fell thru to end of vfopen_locked()\n"); +#endif /* VFS_VERBOSE */ + return NULL; + 80412a8: 0005883a mov r2,zero + +#endif /* HT_LOCALFS */ +} + 80412ac: e037883a mov sp,fp + 80412b0: dfc00117 ldw ra,4(sp) + 80412b4: df000017 ldw fp,0(sp) + 80412b8: dec00204 addi sp,sp,8 + 80412bc: f800283a ret + +080412c0 : + * RETURNS: + */ + +VFILE * +vfopen(char * name, char * mode) +{ + 80412c0: defffb04 addi sp,sp,-20 + 80412c4: dfc00415 stw ra,16(sp) + 80412c8: df000315 stw fp,12(sp) + 80412cc: df000304 addi fp,sp,12 + 80412d0: e13ffe15 stw r4,-8(fp) + 80412d4: e17ffd15 stw r5,-12(fp) + if (vfs_log_file_name) + dprintf("vfopen() passed >%s<,%s\n",name,mode); +#endif /* VFS_UNIT_TEST */ + + /* lock the VFS */ + vfs_lock(); + 80412d8: 01000144 movi r4,5 + 80412dc: 80292b40 call 80292b4 + + vfd = vfopen_locked(name,mode); + 80412e0: e17ffd17 ldw r5,-12(fp) + 80412e4: e13ffe17 ldw r4,-8(fp) + 80412e8: 8040f880 call 8040f88 + 80412ec: e0bfff15 stw r2,-4(fp) + + vfs_unlock(); + 80412f0: 01000144 movi r4,5 + 80412f4: 80293680 call 8029368 + + return vfd; + 80412f8: e0bfff17 ldw r2,-4(fp) +} + 80412fc: e037883a mov sp,fp + 8041300: dfc00117 ldw ra,4(sp) + 8041304: df000017 ldw fp,0(sp) + 8041308: dec00204 addi sp,sp,8 + 804130c: f800283a ret + +08041310 : + * RETURNS: + */ + +void +vfclose_locked(VFILE * vfd) +{ + 8041310: defff804 addi sp,sp,-32 + 8041314: dfc00715 stw ra,28(sp) + 8041318: df000615 stw fp,24(sp) + 804131c: df000604 addi fp,sp,24 + 8041320: e13ffa15 stw r4,-24(fp) + VFILE * vtmp; + VFILE * vlast; + + vlast = NULL; + 8041324: e03ffe15 stw zero,-8(fp) + + /* see if vfd is in our list of open virtual files. We + can't use isvfile() since we need a pointer to last. */ + vtmp = vfiles; + 8041328: d0a0a217 ldw r2,-32120(gp) + 804132c: e0bfff15 stw r2,-4(fp) + while (vtmp) + 8041330: 00000806 br 8041354 + { + /* if this is the one we are looking for, exist search loop */ + if (vfd == vtmp) + 8041334: e0fffa17 ldw r3,-24(fp) + 8041338: e0bfff17 ldw r2,-4(fp) + 804133c: 18800826 beq r3,r2,8041360 + break; + + /* bump the next and previous pointers along to try the next one */ + vlast = vtmp; + 8041340: e0bfff17 ldw r2,-4(fp) + 8041344: e0bffe15 stw r2,-8(fp) + vtmp = vtmp->next; + 8041348: e0bfff17 ldw r2,-4(fp) + 804134c: 10800017 ldw r2,0(r2) + 8041350: e0bfff15 stw r2,-4(fp) + while (vtmp) + 8041354: e0bfff17 ldw r2,-4(fp) + 8041358: 103ff61e bne r2,zero,8041334 + 804135c: 00000106 br 8041364 + break; + 8041360: 0001883a nop + } + + /* if the passed in handle was not in the list we maintain */ + if (vfd != vtmp) + 8041364: e0fffa17 ldw r3,-24(fp) + 8041368: e0bfff17 ldw r2,-4(fp) + 804136c: 1880511e bne r3,r2,80414b4 + + /* this not really a forever loop. it exists so we can break easily + and deal with all the ifdefs */ + while (1) + { + struct vfs_file * vfp = vfd->file; + 8041370: e0bffa17 ldw r2,-24(fp) + 8041374: 10800117 ldw r2,4(r2) + 8041378: e0bffd15 stw r2,-12(fp) + /* vfd->file will be null if somebody unlinked the file after + * this handle was created to point to it. if the file itself + * is gone there is nothing left to do, so break to list + * deletion code at bottom of loop + */ + if (vfp == NULL) + 804137c: e0bffd17 ldw r2,-12(fp) + 8041380: 10003826 beq r2,zero,8041464 + break; +#endif /* HT_RWVFS */ + +#ifdef HT_EXTDEV + /* if the file was created by an external file system */ + if (vfp->method) + 8041384: e0bffd17 ldw r2,-12(fp) + 8041388: 10800a17 ldw r2,40(r2) + 804138c: 10000826 beq r2,zero,80413b0 + { + /* call that file system's fclose() */ + struct vfroutines * vfs = (struct vfroutines*)(vfp->method); + 8041390: e0bffd17 ldw r2,-12(fp) + 8041394: 10800a17 ldw r2,40(r2) + 8041398: e0bffc15 stw r2,-16(fp) + + vfs->r_fclose(vfd); + 804139c: e0bffc17 ldw r2,-16(fp) + 80413a0: 10800217 ldw r2,8(r2) + 80413a4: e13ffa17 ldw r4,-24(fp) + 80413a8: 103ee83a callr r2 + break; /* break to list deletion code after end of phoney loop */ + 80413ac: 00003006 br 8041470 + + /* if the buffer containing the data was allocated dynamically, + * and there are VFS_CLOSE_FRAG_FLOOR bytes of unused data + * between the end of the file and the end of the buffer + */ + if ((vfp->flags & VF_DYNAMICDATA) && + 80413b0: e0bffd17 ldw r2,-12(fp) + 80413b4: 1080058b ldhu r2,22(r2) + 80413b8: 10bfffcc andi r2,r2,65535 + 80413bc: 1080200c andi r2,r2,128 + 80413c0: 10002a26 beq r2,zero,804146c + ((vfp->buf_size - vfp->comp_size) > VFS_CLOSE_FRAG_FLOOR) && + 80413c4: e0bffd17 ldw r2,-12(fp) + 80413c8: 10c00917 ldw r3,36(r2) + 80413cc: e0bffd17 ldw r2,-12(fp) + 80413d0: 10800817 ldw r2,32(r2) + 80413d4: 1885c83a sub r2,r3,r2 + if ((vfp->flags & VF_DYNAMICDATA) && + 80413d8: 10804030 cmpltui r2,r2,256 + 80413dc: 1000231e bne r2,zero,804146c + vfp->data) /* this last test is a sanity check */ + 80413e0: e0bffd17 ldw r2,-12(fp) + 80413e4: 10800617 ldw r2,24(r2) + ((vfp->buf_size - vfp->comp_size) > VFS_CLOSE_FRAG_FLOOR) && + 80413e8: 10002026 beq r2,zero,804146c + { + /* try to reclaim the unused data */ + + /* allocate a new buffer just big enough for the data */ + new_buffer = vf_alloc_buffer(vfp->comp_size); + 80413ec: e0bffd17 ldw r2,-12(fp) + 80413f0: 10800817 ldw r2,32(r2) + 80413f4: 1009883a mov r4,r2 + 80413f8: 8040e700 call 8040e70 + 80413fc: e0bffb15 stw r2,-20(fp) + + /* if the allocation worked */ + if (new_buffer) + 8041400: e0bffb17 ldw r2,-20(fp) + 8041404: 10001926 beq r2,zero,804146c + { + /* copy the old buffer to the new one */ + MEMCPY(new_buffer,vfp->data,(unsigned int) (vfp->comp_size)); + 8041408: e0bffd17 ldw r2,-12(fp) + 804140c: 10c00617 ldw r3,24(r2) + 8041410: e0bffd17 ldw r2,-12(fp) + 8041414: 10800817 ldw r2,32(r2) + 8041418: 100d883a mov r6,r2 + 804141c: 180b883a mov r5,r3 + 8041420: e13ffb17 ldw r4,-20(fp) + 8041424: 80086b80 call 80086b8 + /* free the old buffer */ + vf_free_buffer(vfp->data,vfp->buf_size); + 8041428: e0bffd17 ldw r2,-12(fp) + 804142c: 10c00617 ldw r3,24(r2) + 8041430: e0bffd17 ldw r2,-12(fp) + 8041434: 10800917 ldw r2,36(r2) + 8041438: 100b883a mov r5,r2 + 804143c: 1809883a mov r4,r3 + 8041440: 8040f380 call 8040f38 + /* update the buffer pointer and size to reflect the + just big enough buffer */ + vfp->data = new_buffer; + 8041444: e0bffd17 ldw r2,-12(fp) + 8041448: e0fffb17 ldw r3,-20(fp) + 804144c: 10c00615 stw r3,24(r2) + vfp->buf_size = vfp->comp_size; + 8041450: e0bffd17 ldw r2,-12(fp) + 8041454: 10c00817 ldw r3,32(r2) + 8041458: e0bffd17 ldw r2,-12(fp) + 804145c: 10c00915 stw r3,36(r2) +#endif /* VFS_AUTO_SYNC */ + +#endif /* HT_RWVFS */ + + /* break to list deletion code below */ + break; + 8041460: 00000206 br 804146c + break; + 8041464: 0001883a nop + 8041468: 00000106 br 8041470 + break; + 804146c: 0001883a nop + + } + + if (vlast) /* unlink from list of open files */ + 8041470: e0bffe17 ldw r2,-8(fp) + 8041474: 10000526 beq r2,zero,804148c + vlast->next = vtmp->next; + 8041478: e0bfff17 ldw r2,-4(fp) + 804147c: 10c00017 ldw r3,0(r2) + 8041480: e0bffe17 ldw r2,-8(fp) + 8041484: 10c00015 stw r3,0(r2) + 8041488: 00000306 br 8041498 + else + vfiles = vtmp->next; + 804148c: e0bfff17 ldw r2,-4(fp) + 8041490: 10800017 ldw r2,0(r2) + 8041494: d0a0a215 stw r2,-32120(gp) + + /* free structure addressed by open handle */ + VFS_VFS_OPEN_FREE(vtmp); + 8041498: e13fff17 ldw r4,-4(fp) + 804149c: 80298600 call 8029860 + /* decrement the number of open files */ + vfs_open_files--; + 80414a0: d0a0a617 ldw r2,-32104(gp) + 80414a4: 10bfffc4 addi r2,r2,-1 + 80414a8: d0a0a615 stw r2,-32104(gp) + return; + 80414ac: 0001883a nop + 80414b0: 00000106 br 80414b8 + return; + 80414b4: 0001883a nop +} + 80414b8: e037883a mov sp,fp + 80414bc: dfc00117 ldw ra,4(sp) + 80414c0: df000017 ldw fp,0(sp) + 80414c4: dec00204 addi sp,sp,8 + 80414c8: f800283a ret + +080414cc : + * + * RETURNS: + */ + +void vfclose(VFILE * vfd) +{ + 80414cc: defffd04 addi sp,sp,-12 + 80414d0: dfc00215 stw ra,8(sp) + 80414d4: df000115 stw fp,4(sp) + 80414d8: df000104 addi fp,sp,4 + 80414dc: e13fff15 stw r4,-4(fp) + vfs_lock(); + 80414e0: 01000144 movi r4,5 + 80414e4: 80292b40 call 80292b4 + + vfclose_locked(vfd); + 80414e8: e13fff17 ldw r4,-4(fp) + 80414ec: 80413100 call 8041310 + + vfs_unlock(); + 80414f0: 01000144 movi r4,5 + 80414f4: 80293680 call 8029368 +} + 80414f8: 0001883a nop + 80414fc: e037883a mov sp,fp + 8041500: dfc00117 ldw ra,4(sp) + 8041504: df000017 ldw fp,0(sp) + 8041508: dec00204 addi sp,sp,8 + 804150c: f800283a ret + +08041510 : + * + * RETURNS: + */ + +int vfflush(VFILE * vfd) +{ + 8041510: defffd04 addi sp,sp,-12 + 8041514: dfc00215 stw ra,8(sp) + 8041518: df000115 stw fp,4(sp) + 804151c: df000104 addi fp,sp,4 + 8041520: e13fff15 stw r4,-4(fp) + vfs_lock(); + 8041524: 01000144 movi r4,5 + 8041528: 80292b40 call 80292b4 + + printf("vfflush(): This function needs to be implemented\n"); + 804152c: 01020174 movhi r4,2053 + 8041530: 212e2804 addi r4,r4,-18272 + 8041534: 8002d9c0 call 8002d9c + + vfs_unlock(); + 8041538: 01000144 movi r4,5 + 804153c: 80293680 call 8029368 + return(0); + 8041540: 0005883a mov r2,zero +} + 8041544: e037883a mov sp,fp + 8041548: dfc00117 ldw ra,4(sp) + 804154c: df000017 ldw fp,0(sp) + 8041550: dec00204 addi sp,sp,8 + 8041554: f800283a ret + +08041558 : + +char * vfgets(char * s, int lim, VFILE * fp) +{ + 8041558: defff904 addi sp,sp,-28 + 804155c: dfc00615 stw ra,24(sp) + 8041560: df000515 stw fp,20(sp) + 8041564: df000504 addi fp,sp,20 + 8041568: e13ffd15 stw r4,-12(fp) + 804156c: e17ffc15 stw r5,-16(fp) + 8041570: e1bffb15 stw r6,-20(fp) + int c = EOF; + 8041574: 00bfffc4 movi r2,-1 + 8041578: e0bfff15 stw r2,-4(fp) + char* ret = s; + 804157c: e0bffd17 ldw r2,-12(fp) + 8041580: e0bffe15 stw r2,-8(fp) + + while ( --lim > 0 && (c = vgetc(fp)) != EOF) + 8041584: 00000b06 br 80415b4 + if (( *ret ++ = c) == '\n') + 8041588: e0bffe17 ldw r2,-8(fp) + 804158c: 10c00044 addi r3,r2,1 + 8041590: e0fffe15 stw r3,-8(fp) + 8041594: e0ffff17 ldw r3,-4(fp) + 8041598: 10c00005 stb r3,0(r2) + 804159c: 10800003 ldbu r2,0(r2) + 80415a0: 10803fcc andi r2,r2,255 + 80415a4: 1080201c xori r2,r2,128 + 80415a8: 10bfe004 addi r2,r2,-128 + 80415ac: 10800298 cmpnei r2,r2,10 + 80415b0: 10000c26 beq r2,zero,80415e4 + while ( --lim > 0 && (c = vgetc(fp)) != EOF) + 80415b4: e0bffc17 ldw r2,-16(fp) + 80415b8: 10bfffc4 addi r2,r2,-1 + 80415bc: e0bffc15 stw r2,-16(fp) + 80415c0: e0bffc17 ldw r2,-16(fp) + 80415c4: 0080080e bge zero,r2,80415e8 + 80415c8: e13ffb17 ldw r4,-20(fp) + 80415cc: 80421c00 call 80421c0 + 80415d0: e0bfff15 stw r2,-4(fp) + 80415d4: e0bfff17 ldw r2,-4(fp) + 80415d8: 10bfffd8 cmpnei r2,r2,-1 + 80415dc: 103fea1e bne r2,zero,8041588 + 80415e0: 00000106 br 80415e8 + break; + 80415e4: 0001883a nop + *ret = '\0'; + 80415e8: e0bffe17 ldw r2,-8(fp) + 80415ec: 10000005 stb zero,0(r2) + return ( c == EOF && ret == s) ? NULL : s; + 80415f0: e0bfff17 ldw r2,-4(fp) + 80415f4: 10bfffd8 cmpnei r2,r2,-1 + 80415f8: 1000031e bne r2,zero,8041608 + 80415fc: e0fffe17 ldw r3,-8(fp) + 8041600: e0bffd17 ldw r2,-12(fp) + 8041604: 18800226 beq r3,r2,8041610 + 8041608: e0bffd17 ldw r2,-12(fp) + 804160c: 00000106 br 8041614 + 8041610: 0005883a mov r2,zero +} + 8041614: e037883a mov sp,fp + 8041618: dfc00117 ldw ra,4(sp) + 804161c: df000017 ldw fp,0(sp) + 8041620: dec00204 addi sp,sp,8 + 8041624: f800283a ret + +08041628 : + * + * RETURNS: 1 if the file pointer is at EOF, otherwise 0 + */ + +int vfeof(VFILE * vfd) +{ + 8041628: defffc04 addi sp,sp,-16 + 804162c: dfc00315 stw ra,12(sp) + 8041630: df000215 stw fp,8(sp) + 8041634: df000204 addi fp,sp,8 + 8041638: e13ffe15 stw r4,-8(fp) + int c = 0; + 804163c: e03fff15 stw zero,-4(fp) + +#ifdef HT_LOCALFS + return(feof((FILE*)vfd)); +#endif + if ((c = vgetc(vfd)) == EOF ) + 8041640: e13ffe17 ldw r4,-8(fp) + 8041644: 80421c00 call 80421c0 + 8041648: e0bfff15 stw r2,-4(fp) + 804164c: e0bfff17 ldw r2,-4(fp) + 8041650: 10bfffd8 cmpnei r2,r2,-1 + 8041654: 1000021e bne r2,zero,8041660 + { + return 1; + 8041658: 00800044 movi r2,1 + 804165c: 00000106 br 8041664 + } + return 0; + 8041660: 0005883a mov r2,zero +} + 8041664: e037883a mov sp,fp + 8041668: dfc00117 ldw ra,4(sp) + 804166c: df000017 ldw fp,0(sp) + 8041670: dec00204 addi sp,sp,8 + 8041674: f800283a ret + +08041678 : + * + * RETURNS: + */ + +void vunlink_flag_open_files(struct vfs_file * vfp) +{ + 8041678: defffd04 addi sp,sp,-12 + 804167c: df000215 stw fp,8(sp) + 8041680: df000204 addi fp,sp,8 + 8041684: e13ffe15 stw r4,-8(fp) + VFILE * vtmp; + + /* for all open files */ + for (vtmp = vfiles; vtmp; vtmp = vtmp->next) + 8041688: d0a0a217 ldw r2,-32120(gp) + 804168c: e0bfff15 stw r2,-4(fp) + 8041690: 00000906 br 80416b8 + { + /* if the open file handle is referencing the file we are + deleting, set that reference to NULL */ + if (vtmp->file == vfp) + 8041694: e0bfff17 ldw r2,-4(fp) + 8041698: 10800117 ldw r2,4(r2) + 804169c: e0fffe17 ldw r3,-8(fp) + 80416a0: 1880021e bne r3,r2,80416ac + vtmp->file = NULL; + 80416a4: e0bfff17 ldw r2,-4(fp) + 80416a8: 10000115 stw zero,4(r2) + for (vtmp = vfiles; vtmp; vtmp = vtmp->next) + 80416ac: e0bfff17 ldw r2,-4(fp) + 80416b0: 10800017 ldw r2,0(r2) + 80416b4: e0bfff15 stw r2,-4(fp) + 80416b8: e0bfff17 ldw r2,-4(fp) + 80416bc: 103ff51e bne r2,zero,8041694 + } +} + 80416c0: 0001883a nop + 80416c4: e037883a mov sp,fp + 80416c8: df000017 ldw fp,0(sp) + 80416cc: dec00104 addi sp,sp,4 + 80416d0: f800283a ret + +080416d4 : + * Change prototype from char * name to const char to + * follow C library standard. + */ +int +vunlink(const char * const_name) +{ + 80416d4: defff604 addi sp,sp,-40 + 80416d8: dfc00915 stw ra,36(sp) + 80416dc: df000815 stw fp,32(sp) + 80416e0: df000804 addi fp,sp,32 + 80416e4: e13ff815 stw r4,-32(fp) + struct vfs_file * vfp; + int rc = 0; + 80416e8: e03fff15 stw zero,-4(fp) +/* + * Altera Niche Stack Nios port modification: + * Change prototype from char * name to const char to + * follow C library standard. + */ + char * name = malloc(strlen(const_name)+1); + 80416ec: e13ff817 ldw r4,-32(fp) + 80416f0: 8002dac0 call 8002dac + 80416f4: 10800044 addi r2,r2,1 + 80416f8: 1009883a mov r4,r2 + 80416fc: 8042c980 call 8042c98 + 8041700: e0bffc15 stw r2,-16(fp) + strcpy(name, const_name); + 8041704: e17ff817 ldw r5,-32(fp) + 8041708: e13ffc17 ldw r4,-16(fp) + 804170c: 8042f600 call 8042f60 + if (vfs_log_file_name) + dprintf("vunlink() passed >%s<\n",name); +#endif /* VFS_UNIT_TEST */ + + /* lock the VFS */ + vfs_lock(); + 8041710: 01000144 movi r4,5 + 8041714: 80292b40 call 80292b4 + + /* see if the converted name is one of the one's in our list */ + /* if it isn't */ + if ((vfp = vfslookup_locked(name)) == NULL) + 8041718: e13ffc17 ldw r4,-16(fp) + 804171c: 80422080 call 8042208 + 8041720: e0bffb15 stw r2,-20(fp) + 8041724: e0bffb17 ldw r2,-20(fp) + 8041728: 1000061e bne r2,zero,8041744 + { + vfs_unlock(); + 804172c: 01000144 movi r4,5 + 8041730: 80293680 call 8029368 +#ifdef HT_LOCALFS + /* default to call on local system */ + return remove(name); +#else + /* no local file system, so return error condition */ + free(name); + 8041734: e13ffc17 ldw r4,-16(fp) + 8041738: 8042ca80 call 8042ca8 + return -1; + 804173c: 00bfffc4 movi r2,-1 + 8041740: 00005f06 br 80418c0 +#ifdef HT_RWVFS + /* save the next link pointer since in one path through the code, + * the vfs_file structure gets freed before its unlinked from the + * list + */ + vfnext = vfp->next; + 8041744: e0bffb17 ldw r2,-20(fp) + 8041748: 10800017 ldw r2,0(r2) + 804174c: e0bffa15 stw r2,-24(fp) + + /* search list of files to determine predecessor in list */ + vflast = NULL; + 8041750: e03ffd15 stw zero,-12(fp) + for (vtmp = vfsfiles; vtmp != NULL; vtmp = vtmp->next) + 8041754: d0a0a317 ldw r2,-32116(gp) + 8041758: e0bffe15 stw r2,-8(fp) + 804175c: 00000806 br 8041780 + { + if (vtmp == vfp) + 8041760: e0fffe17 ldw r3,-8(fp) + 8041764: e0bffb17 ldw r2,-20(fp) + 8041768: 18800826 beq r3,r2,804178c + break; + vflast = vtmp; + 804176c: e0bffe17 ldw r2,-8(fp) + 8041770: e0bffd15 stw r2,-12(fp) + for (vtmp = vfsfiles; vtmp != NULL; vtmp = vtmp->next) + 8041774: e0bffe17 ldw r2,-8(fp) + 8041778: 10800017 ldw r2,0(r2) + 804177c: e0bffe15 stw r2,-8(fp) + 8041780: e0bffe17 ldw r2,-8(fp) + 8041784: 103ff61e bne r2,zero,8041760 + 8041788: 00000106 br 8041790 + break; + 804178c: 0001883a nop + } + + /* this shouldn't happen since vfslookup_locked() already searched + the list, but just in case */ + if (vtmp == NULL) + 8041790: e0bffe17 ldw r2,-8(fp) + 8041794: 1000071e bne r2,zero,80417b4 + { + dtrap(); + 8041798: 8028cd40 call 8028cd4 + vfs_unlock(); + 804179c: 01000144 movi r4,5 + 80417a0: 80293680 call 8029368 + free(name); + 80417a4: e13ffc17 ldw r4,-16(fp) + 80417a8: 8042ca80 call 8042ca8 + return -1; + 80417ac: 00bfffc4 movi r2,-1 + 80417b0: 00004306 br 80418c0 + while (1) + { + +#ifdef HT_EXTDEV + /* if the file was created by an external file system */ + if (vfp->method) + 80417b4: e0bffb17 ldw r2,-20(fp) + 80417b8: 10800a17 ldw r2,40(r2) + 80417bc: 10000926 beq r2,zero,80417e4 + { + /* call that file system's unlink() */ + struct vfroutines * vfs = (struct vfroutines*) (vfp->method); + 80417c0: e0bffb17 ldw r2,-20(fp) + 80417c4: 10800a17 ldw r2,40(r2) + 80417c8: e0bff915 stw r2,-28(fp) + + rc = vfs->r_unlink(name); + 80417cc: e0bff917 ldw r2,-28(fp) + 80417d0: 10800817 ldw r2,32(r2) + 80417d4: e13ffc17 ldw r4,-16(fp) + 80417d8: 103ee83a callr r2 + 80417dc: e0bfff15 stw r2,-4(fp) + break; /* break to list deletion code after end of phoney loop */ + 80417e0: 00002606 br 804187c + } +#endif /* HT_EXTDEV */ + + /* if the file is not write enabled, return error condition */ + if (!(vfp->flags & VF_WRITE)) + 80417e4: e0bffb17 ldw r2,-20(fp) + 80417e8: 1080058b ldhu r2,22(r2) + 80417ec: 10bfffcc andi r2,r2,65535 + 80417f0: 1080080c andi r2,r2,32 + 80417f4: 1000061e bne r2,zero,8041810 + { + vfs_unlock(); + 80417f8: 01000144 movi r4,5 + 80417fc: 80293680 call 8029368 + free(name); + 8041800: e13ffc17 ldw r4,-16(fp) + 8041804: 8042ca80 call 8042ca8 + return -1; + 8041808: 00bfffc4 movi r2,-1 + 804180c: 00002c06 br 80418c0 + } + + /* if the data buffer containing the file's data was dynamically + allocated and is not null */ + if ((vfp->flags & VF_DYNAMICDATA) && (vfp->data)) + 8041810: e0bffb17 ldw r2,-20(fp) + 8041814: 1080058b ldhu r2,22(r2) + 8041818: 10bfffcc andi r2,r2,65535 + 804181c: 1080200c andi r2,r2,128 + 8041820: 10000a26 beq r2,zero,804184c + 8041824: e0bffb17 ldw r2,-20(fp) + 8041828: 10800617 ldw r2,24(r2) + 804182c: 10000726 beq r2,zero,804184c + { + /* free the buffer */ + vf_free_buffer(vfp->data,vfp->buf_size); + 8041830: e0bffb17 ldw r2,-20(fp) + 8041834: 10c00617 ldw r3,24(r2) + 8041838: e0bffb17 ldw r2,-20(fp) + 804183c: 10800917 ldw r2,36(r2) + 8041840: 100b883a mov r5,r2 + 8041844: 1809883a mov r4,r3 + 8041848: 8040f380 call 8040f38 + } + + /* if the vfs_file structure itself was allocated dynamically */ + if (vfp->flags & VF_DYNAMICINFO) + 804184c: e0bffb17 ldw r2,-20(fp) + 8041850: 1080058b ldhu r2,22(r2) + 8041854: 10bfffcc andi r2,r2,65535 + 8041858: 1080100c andi r2,r2,64 + 804185c: 10000526 beq r2,zero,8041874 + { + /* decrement count of total files */ + vfs_total_dyna_files--; + 8041860: d0a0a817 ldw r2,-32096(gp) + 8041864: 10bfffc4 addi r2,r2,-1 + 8041868: d0a0a815 stw r2,-32096(gp) + + /* free the vfs_file structure */ + VFS_VFS_FILE_FREE(vfp); + 804186c: e13ffb17 ldw r4,-20(fp) + 8041870: 80298600 call 8029860 + the vfs_file has been deleted from the list */ +#ifdef VFS_AUTO_SYNC + do_sync = 1; +#endif + /* we were successful at our unlink */ + rc = 0; + 8041874: e03fff15 stw zero,-4(fp) + + break; + 8041878: 0001883a nop + } + + /* delete the vfs_file structure from the list headed by vfsfiles */ + if (vflast) + 804187c: e0bffd17 ldw r2,-12(fp) + 8041880: 10000426 beq r2,zero,8041894 + vflast->next = vfnext; + 8041884: e0bffd17 ldw r2,-12(fp) + 8041888: e0fffa17 ldw r3,-24(fp) + 804188c: 10c00015 stw r3,0(r2) + 8041890: 00000206 br 804189c + else + vfsfiles = vfnext; + 8041894: e0bffa17 ldw r2,-24(fp) + 8041898: d0a0a315 stw r2,-32116(gp) + + /* fix up references to deleted file in list of currently open VFILEs */ + vunlink_flag_open_files(vfp); + 804189c: e13ffb17 ldw r4,-20(fp) + 80418a0: 80416780 call 8041678 + + /* flag that the directory is stale so vfs_sync() knows it has to do + something */ + vfs_dir_stale = TRUE; + 80418a4: 00800044 movi r2,1 + 80418a8: d0a0a515 stw r2,-32108(gp) + + /* unlinks not allowed on read-only VFS */ + rc = -1; + +#endif /* HT_RWVFS */ + vfs_unlock(); + 80418ac: 01000144 movi r4,5 + 80418b0: 80293680 call 8029368 + free(name); + 80418b4: e13ffc17 ldw r4,-16(fp) + 80418b8: 8042ca80 call 8042ca8 + return rc; + 80418bc: e0bfff17 ldw r2,-4(fp) +} + 80418c0: e037883a mov sp,fp + 80418c4: dfc00117 ldw ra,4(sp) + 80418c8: df000017 ldw fp,0(sp) + 80418cc: dec00204 addi sp,sp,8 + 80418d0: f800283a ret + +080418d4 : + * RETURNS: + */ + +int +vfread(char * buf, unsigned size, unsigned items, VFILE * vfd) +{ + 80418d4: defff604 addi sp,sp,-40 + 80418d8: dfc00915 stw ra,36(sp) + 80418dc: df000815 stw fp,32(sp) + 80418e0: df000804 addi fp,sp,32 + 80418e4: e13ffb15 stw r4,-20(fp) + 80418e8: e17ffa15 stw r5,-24(fp) + 80418ec: e1bff915 stw r6,-28(fp) + 80418f0: e1fff815 stw r7,-32(fp) + unsigned bcount; /* number of bytes put in caller's buffer */ + + IN_PROFILER(PF_FS, PF_ENTRY); + + /* lock the VFS */ + vfs_lock(); + 80418f4: 01000144 movi r4,5 + 80418f8: 80292b40 call 80292b4 + + /* if the file is in our list of open files */ + if (isvfile_locked(vfd)) + 80418fc: e13ff817 ldw r4,-32(fp) + 8041900: 80425400 call 8042540 + 8041904: 10004d26 beq r2,zero,8041a3c + { + +#ifdef HT_RWVFS + /* the caller is trying to read a handle to a file that's been + deleted, so he gets 0 data back */ + if (vfd->file == NULL) + 8041908: e0bff817 ldw r2,-32(fp) + 804190c: 10800117 ldw r2,4(r2) + 8041910: 1000041e bne r2,zero,8041924 + { + vfs_unlock(); + 8041914: 01000144 movi r4,5 + 8041918: 80293680 call 8029368 + IN_PROFILER(PF_FS, PF_EXIT); + return 0; + 804191c: 0005883a mov r2,zero + 8041920: 00004906 br 8041a48 + } +#endif /* HT_RWVFS */ + +#ifdef HT_EXTDEV + /* if the file was created by an external file system */ + if (vfd->file->method) + 8041924: e0bff817 ldw r2,-32(fp) + 8041928: 10800117 ldw r2,4(r2) + 804192c: 10800a17 ldw r2,40(r2) + 8041930: 10001026 beq r2,zero,8041974 + { + struct vfroutines * vfs = (struct vfroutines*) (vfd->file->method); + 8041934: e0bff817 ldw r2,-32(fp) + 8041938: 10800117 ldw r2,4(r2) + 804193c: 10800a17 ldw r2,40(r2) + 8041940: e0bffe15 stw r2,-8(fp) + int rc; + + /* call that system's fread() */ + rc = vfs->r_fread(buf,size,items,vfd); + 8041944: e0bffe17 ldw r2,-8(fp) + 8041948: 10800317 ldw r2,12(r2) + 804194c: e1fff817 ldw r7,-32(fp) + 8041950: e1bff917 ldw r6,-28(fp) + 8041954: e17ffa17 ldw r5,-24(fp) + 8041958: e13ffb17 ldw r4,-20(fp) + 804195c: 103ee83a callr r2 + 8041960: e0bffd15 stw r2,-12(fp) + vfs_unlock(); + 8041964: 01000144 movi r4,5 + 8041968: 80293680 call 8029368 + IN_PROFILER(PF_FS, PF_EXIT); + return rc; + 804196c: e0bffd17 ldw r2,-12(fp) + 8041970: 00003506 br 8041a48 +#ifdef HT_RWVFS + /* the data pointer can be NULL if somebody tries to read from + * a freshly created file, in which case there is no data in + * the file, so return 0 + */ + if (!(vfd->file->data)) + 8041974: e0bff817 ldw r2,-32(fp) + 8041978: 10800117 ldw r2,4(r2) + 804197c: 10800617 ldw r2,24(r2) + 8041980: 1000041e bne r2,zero,8041994 + { + vfs_unlock(); + 8041984: 01000144 movi r4,5 + 8041988: 80293680 call 8029368 + IN_PROFILER(PF_FS, PF_EXIT); + return 0; + 804198c: 0005883a mov r2,zero + 8041990: 00002d06 br 8041a48 + } +#endif /* HT_RWVFS */ + + bcount = items * size; /* number of bytes to transfer */ + 8041994: e0fff917 ldw r3,-28(fp) + 8041998: e0bffa17 ldw r2,-24(fp) + 804199c: 1885383a mul r2,r3,r2 + 80419a0: e0bfff15 stw r2,-4(fp) + return(items); /* filled user buffer, return # items copied */ + } + else /* else fall to faster non-compression code */ +#endif /* HTML_COMPRESSION */ + { /* get here to do simple uncompressed data read */ + unsigned location = vfd->cmploc - vfd->file->data; + 80419a4: e0bff817 ldw r2,-32(fp) + 80419a8: 10c00217 ldw r3,8(r2) + 80419ac: e0bff817 ldw r2,-32(fp) + 80419b0: 10800117 ldw r2,4(r2) + 80419b4: 10800617 ldw r2,24(r2) + 80419b8: 1885c83a sub r2,r3,r2 + 80419bc: e0bffc15 stw r2,-16(fp) + + if (((unsigned long)location + bcount) > vfd->file->comp_size) + 80419c0: e0fffc17 ldw r3,-16(fp) + 80419c4: e0bfff17 ldw r2,-4(fp) + 80419c8: 1885883a add r2,r3,r2 + 80419cc: e0fff817 ldw r3,-32(fp) + 80419d0: 18c00117 ldw r3,4(r3) + 80419d4: 18c00817 ldw r3,32(r3) + 80419d8: 1880062e bgeu r3,r2,80419f4 + bcount = (unsigned)(vfd->file->comp_size - location); + 80419dc: e0bff817 ldw r2,-32(fp) + 80419e0: 10800117 ldw r2,4(r2) + 80419e4: 10c00817 ldw r3,32(r2) + 80419e8: e0bffc17 ldw r2,-16(fp) + 80419ec: 1885c83a sub r2,r3,r2 + 80419f0: e0bfff15 stw r2,-4(fp) + MEMCPY(buf, vfd->cmploc, bcount); + 80419f4: e0bff817 ldw r2,-32(fp) + 80419f8: 10800217 ldw r2,8(r2) + 80419fc: e1bfff17 ldw r6,-4(fp) + 8041a00: 100b883a mov r5,r2 + 8041a04: e13ffb17 ldw r4,-20(fp) + 8041a08: 80086b80 call 80086b8 + vfd->cmploc += bcount; + 8041a0c: e0bff817 ldw r2,-32(fp) + 8041a10: 10c00217 ldw r3,8(r2) + 8041a14: e0bfff17 ldw r2,-4(fp) + 8041a18: 1887883a add r3,r3,r2 + 8041a1c: e0bff817 ldw r2,-32(fp) + 8041a20: 10c00215 stw r3,8(r2) + } + vfs_unlock(); + 8041a24: 01000144 movi r4,5 + 8041a28: 80293680 call 8029368 + IN_PROFILER(PF_FS, PF_EXIT); + return (bcount/size); + 8041a2c: e17ffa17 ldw r5,-24(fp) + 8041a30: e13fff17 ldw r4,-4(fp) + 8041a34: 800cff80 call 800cff8 <__udivsi3> + 8041a38: 00000306 br 8041a48 + } + + vfs_unlock(); + 8041a3c: 01000144 movi r4,5 + 8041a40: 80293680 call 8029368 + +#ifdef HT_LOCALFS + /* default to call on local system */ + return(fread(buf, size, items, (FILE*)vfd)); +#else + return 0; + 8041a44: 0005883a mov r2,zero +#endif /* HT_LOCALFS */ +} + 8041a48: e037883a mov sp,fp + 8041a4c: dfc00117 ldw ra,4(sp) + 8041a50: df000017 ldw fp,0(sp) + 8041a54: dec00204 addi sp,sp,8 + 8041a58: f800283a ret + +08041a5c : + * RETURNS: + */ + +int +vfwrite_locked(char * buf, unsigned size, unsigned items, VFILE * vfd) +{ + 8041a5c: defff204 addi sp,sp,-56 + 8041a60: dfc00d15 stw ra,52(sp) + 8041a64: df000c15 stw fp,48(sp) + 8041a68: df000c04 addi fp,sp,48 + 8041a6c: e13ff715 stw r4,-36(fp) + 8041a70: e17ff615 stw r5,-40(fp) + 8041a74: e1bff515 stw r6,-44(fp) + 8041a78: e1fff415 stw r7,-48(fp) + unsigned long current_offset; + struct vfs_file * vfp; +#endif /* HT_RWVFS */ + + /* if the file is not in our list of files */ + if (!isvfile_locked(vfd)) + 8041a7c: e13ff417 ldw r4,-48(fp) + 8041a80: 80425400 call 8042540 + 8041a84: 1000021e bne r2,zero,8041a90 + { +#ifdef HT_LOCALFS + /* default to call on local system */ + return(fwrite(buf, size, items, (FILE*)vfd)); +#else + return EBADF; + 8041a88: 00800244 movi r2,9 + 8041a8c: 0000d906 br 8041df4 + } + /* this file is in our list of files */ + +#ifdef HT_EXTDEV + /* if the file was created by an external file system */ + if (vfd->file->method) + 8041a90: e0bff417 ldw r2,-48(fp) + 8041a94: 10800117 ldw r2,4(r2) + 8041a98: 10800a17 ldw r2,40(r2) + 8041a9c: 10000e26 beq r2,zero,8041ad8 + { + struct vfroutines * vfs = (struct vfroutines*) (vfd->file->method); + 8041aa0: e0bff417 ldw r2,-48(fp) + 8041aa4: 10800117 ldw r2,4(r2) + 8041aa8: 10800a17 ldw r2,40(r2) + 8041aac: e0bfff15 stw r2,-4(fp) + int rc; + + /* call that system's fwrite() */ + rc = vfs->r_fwrite(buf,size,items,vfd); + 8041ab0: e0bfff17 ldw r2,-4(fp) + 8041ab4: 10800417 ldw r2,16(r2) + 8041ab8: e1fff417 ldw r7,-48(fp) + 8041abc: e1bff517 ldw r6,-44(fp) + 8041ac0: e17ff617 ldw r5,-40(fp) + 8041ac4: e13ff717 ldw r4,-36(fp) + 8041ac8: 103ee83a callr r2 + 8041acc: e0bffe15 stw r2,-8(fp) + return rc; + 8041ad0: e0bffe17 ldw r2,-8(fp) + 8041ad4: 0000c706 br 8041df4 + +#else /* HT_RWVFS */ + + /* the caller is trying to write to a file that's been deleted, + so he writes 0 data */ + if (vfd->file == NULL) + 8041ad8: e0bff417 ldw r2,-48(fp) + 8041adc: 10800117 ldw r2,4(r2) + 8041ae0: 1000021e bne r2,zero,8041aec + { + return 0; + 8041ae4: 0005883a mov r2,zero + 8041ae8: 0000c206 br 8041df4 + } + + vfp = vfd->file; + 8041aec: e0bff417 ldw r2,-48(fp) + 8041af0: 10800117 ldw r2,4(r2) + 8041af4: e0bffd15 stw r2,-12(fp) + + /* if the file is not writable, return error condition */ + if (!(vfp->flags & VF_WRITE)) + 8041af8: e0bffd17 ldw r2,-12(fp) + 8041afc: 1080058b ldhu r2,22(r2) + 8041b00: 10bfffcc andi r2,r2,65535 + 8041b04: 1080080c andi r2,r2,32 + 8041b08: 1000051e bne r2,zero,8041b20 + { + vfd->error = ENP_FILEIO; + 8041b0c: e0bff417 ldw r2,-48(fp) + 8041b10: 00fff984 movi r3,-26 + 8041b14: 10c00415 stw r3,16(r2) + return 0; + 8041b18: 0005883a mov r2,zero + 8041b1c: 0000b506 br 8041df4 + } + + /* compute number of bytes to write */ + bcount = size * items; + 8041b20: e0fff617 ldw r3,-40(fp) + 8041b24: e0bff517 ldw r2,-44(fp) + 8041b28: 1885383a mul r2,r3,r2 + 8041b2c: e0bffc15 stw r2,-16(fp) + + /* get rid of this degenerate case up front */ + if (bcount == 0) + 8041b30: e0bffc17 ldw r2,-16(fp) + 8041b34: 1000021e bne r2,zero,8041b40 + { + return 0; + 8041b38: 0005883a mov r2,zero + 8041b3c: 0000ad06 br 8041df4 + } + + /* if the file currently has no data buffer */ + if (vfp->data == NULL) + 8041b40: e0bffd17 ldw r2,-12(fp) + 8041b44: 10800617 ldw r2,24(r2) + 8041b48: 10003d1e bne r2,zero,8041c40 + { + /* compute the size of the buffer to be created */ + /* we round up the size of the data to be written so we dont have + the overhead of a memory allocation on every write */ + unsigned long buf_size = VFS_ROUND_UP((unsigned long)bcount); + 8041b4c: e0bffc17 ldw r2,-16(fp) + 8041b50: 10ffffc4 addi r3,r2,-1 + 8041b54: 00b80004 movi r2,-8192 + 8041b58: 1884703a and r2,r3,r2 + 8041b5c: 10880004 addi r2,r2,8192 + 8041b60: e0bffb15 stw r2,-20(fp) + + /* allocate a buffer of that size */ + vfp->data = vf_alloc_buffer(buf_size); + 8041b64: e13ffb17 ldw r4,-20(fp) + 8041b68: 8040e700 call 8040e70 + 8041b6c: 1007883a mov r3,r2 + 8041b70: e0bffd17 ldw r2,-12(fp) + 8041b74: 10c00615 stw r3,24(r2) + + /* if the allocation failed */ + if (!(vfp->data)) + 8041b78: e0bffd17 ldw r2,-12(fp) + 8041b7c: 10800617 ldw r2,24(r2) + 8041b80: 1000051e bne r2,zero,8041b98 + { + vfd->error = ENP_NOMEM; + 8041b84: e0bff417 ldw r2,-48(fp) + 8041b88: 00fffb04 movi r3,-20 + 8041b8c: 10c00415 stw r3,16(r2) + return 0; + 8041b90: 0005883a mov r2,zero + 8041b94: 00009706 br 8041df4 + } + + /* store the size of the allocated buffer */ + vfp->buf_size = buf_size; + 8041b98: e0bffd17 ldw r2,-12(fp) + 8041b9c: e0fffb17 ldw r3,-20(fp) + 8041ba0: 10c00915 stw r3,36(r2) + + /* store the number of bytes written in the real and compressed + file sizes */ + vfp->real_size = bcount; + 8041ba4: e0bffd17 ldw r2,-12(fp) + 8041ba8: e0fffc17 ldw r3,-16(fp) + 8041bac: 10c00715 stw r3,28(r2) + vfp->comp_size = bcount; + 8041bb0: e0bffd17 ldw r2,-12(fp) + 8041bb4: e0fffc17 ldw r3,-16(fp) + 8041bb8: 10c00815 stw r3,32(r2) + + /* set the file pointer to the first byte following the last + byte written */ + vfd->cmploc = vfp->data + bcount; + 8041bbc: e0bffd17 ldw r2,-12(fp) + 8041bc0: 10c00617 ldw r3,24(r2) + 8041bc4: e0bffc17 ldw r2,-16(fp) + 8041bc8: 1887883a add r3,r3,r2 + 8041bcc: e0bff417 ldw r2,-48(fp) + 8041bd0: 10c00215 stw r3,8(r2) + + /* turn off the compression flag */ + vfp->flags &= ~VF_HTMLCOMPRESSED; + 8041bd4: e0bffd17 ldw r2,-12(fp) + 8041bd8: 10c0058b ldhu r3,22(r2) + 8041bdc: 00bfff84 movi r2,-2 + 8041be0: 1884703a and r2,r3,r2 + 8041be4: 1007883a mov r3,r2 + 8041be8: e0bffd17 ldw r2,-12(fp) + 8041bec: 10c0058d sth r3,22(r2) + + /* the data in the file is stale */ + vfp->flags |= VF_STALE; + 8041bf0: e0bffd17 ldw r2,-12(fp) + 8041bf4: 1080058b ldhu r2,22(r2) + 8041bf8: 10808014 ori r2,r2,512 + 8041bfc: 1007883a mov r3,r2 + 8041c00: e0bffd17 ldw r2,-12(fp) + 8041c04: 10c0058d sth r3,22(r2) + + /* the buffer data was dynamically allocated */ + vfp->flags |= VF_DYNAMICDATA; + 8041c08: e0bffd17 ldw r2,-12(fp) + 8041c0c: 1080058b ldhu r2,22(r2) + 8041c10: 10802014 ori r2,r2,128 + 8041c14: 1007883a mov r3,r2 + 8041c18: e0bffd17 ldw r2,-12(fp) + 8041c1c: 10c0058d sth r3,22(r2) + + /* copy the data to be written to the file buffer */ + MEMCPY(vfp->data,buf,bcount); + 8041c20: e0bffd17 ldw r2,-12(fp) + 8041c24: 10800617 ldw r2,24(r2) + 8041c28: e1bffc17 ldw r6,-16(fp) + 8041c2c: e17ff717 ldw r5,-36(fp) + 8041c30: 1009883a mov r4,r2 + 8041c34: 80086b80 call 80086b8 + + /* return the number of "items" written */ + return items; + 8041c38: e0bff517 ldw r2,-44(fp) + 8041c3c: 00006d06 br 8041df4 + } + + /* compute the current offset into the file */ + current_offset = vfd->cmploc - vfp->data; + 8041c40: e0bff417 ldw r2,-48(fp) + 8041c44: 10c00217 ldw r3,8(r2) + 8041c48: e0bffd17 ldw r2,-12(fp) + 8041c4c: 10800617 ldw r2,24(r2) + 8041c50: 1885c83a sub r2,r3,r2 + 8041c54: e0bffa15 stw r2,-24(fp) + + /* if the data to be written wont fit into the file buffer */ + if ((current_offset + bcount) > vfp->buf_size) + 8041c58: e0fffa17 ldw r3,-24(fp) + 8041c5c: e0bffc17 ldw r2,-16(fp) + 8041c60: 1885883a add r2,r3,r2 + 8041c64: e0fffd17 ldw r3,-12(fp) + 8041c68: 18c00917 ldw r3,36(r3) + 8041c6c: 1880382e bgeu r3,r2,8041d50 + { + /* compute the size of a new buffer to hold the data */ + unsigned long new_buf_size = VFS_ROUND_UP(current_offset + bcount); + 8041c70: e0fffa17 ldw r3,-24(fp) + 8041c74: e0bffc17 ldw r2,-16(fp) + 8041c78: 1885883a add r2,r3,r2 + 8041c7c: 10ffffc4 addi r3,r2,-1 + 8041c80: 00b80004 movi r2,-8192 + 8041c84: 1884703a and r2,r3,r2 + 8041c88: 10880004 addi r2,r2,8192 + 8041c8c: e0bff915 stw r2,-28(fp) + unsigned char *new_buffer; + + /* allocate a new buffer */ + new_buffer = vf_alloc_buffer(new_buf_size); + 8041c90: e13ff917 ldw r4,-28(fp) + 8041c94: 8040e700 call 8040e70 + 8041c98: e0bff815 stw r2,-32(fp) + + /* check for allocation failure */ + if (!new_buffer) + 8041c9c: e0bff817 ldw r2,-32(fp) + 8041ca0: 1000051e bne r2,zero,8041cb8 + { + vfd->error = ENP_NOMEM; + 8041ca4: e0bff417 ldw r2,-48(fp) + 8041ca8: 00fffb04 movi r3,-20 + 8041cac: 10c00415 stw r3,16(r2) + return 0; + 8041cb0: 0005883a mov r2,zero + 8041cb4: 00004f06 br 8041df4 + } + + /* copy the old buffer contents to the new buffer */ + MEMCPY(new_buffer,vfp->data,(unsigned int) (vfp->comp_size)); + 8041cb8: e0bffd17 ldw r2,-12(fp) + 8041cbc: 10c00617 ldw r3,24(r2) + 8041cc0: e0bffd17 ldw r2,-12(fp) + 8041cc4: 10800817 ldw r2,32(r2) + 8041cc8: 100d883a mov r6,r2 + 8041ccc: 180b883a mov r5,r3 + 8041cd0: e13ff817 ldw r4,-32(fp) + 8041cd4: 80086b80 call 80086b8 + + /* if the old buffer had been dynamically allocated */ + if (vfp->flags & VF_DYNAMICDATA) + 8041cd8: e0bffd17 ldw r2,-12(fp) + 8041cdc: 1080058b ldhu r2,22(r2) + 8041ce0: 10bfffcc andi r2,r2,65535 + 8041ce4: 1080200c andi r2,r2,128 + 8041ce8: 10000726 beq r2,zero,8041d08 + { + /* free it */ + vf_free_buffer(vfp->data,vfp->buf_size); + 8041cec: e0bffd17 ldw r2,-12(fp) + 8041cf0: 10c00617 ldw r3,24(r2) + 8041cf4: e0bffd17 ldw r2,-12(fp) + 8041cf8: 10800917 ldw r2,36(r2) + 8041cfc: 100b883a mov r5,r2 + 8041d00: 1809883a mov r4,r3 + 8041d04: 8040f380 call 8040f38 + } + + /* store the new buffer in the file structure */ + vfp->data = new_buffer; + 8041d08: e0bffd17 ldw r2,-12(fp) + 8041d0c: e0fff817 ldw r3,-32(fp) + 8041d10: 10c00615 stw r3,24(r2) + + /* store the new buffer size in the file structure */ + vfp->buf_size = new_buf_size; + 8041d14: e0bffd17 ldw r2,-12(fp) + 8041d18: e0fff917 ldw r3,-28(fp) + 8041d1c: 10c00915 stw r3,36(r2) + + /* the new buffer was dynamically allocated */ + vfp->flags |= VF_DYNAMICDATA; + 8041d20: e0bffd17 ldw r2,-12(fp) + 8041d24: 1080058b ldhu r2,22(r2) + 8041d28: 10802014 ori r2,r2,128 + 8041d2c: 1007883a mov r3,r2 + 8041d30: e0bffd17 ldw r2,-12(fp) + 8041d34: 10c0058d sth r3,22(r2) + * buffer note that this means the VFS does not support + * simultaneous opens of the same file, since for that to work, + * all the other cmploc's that point to this file would + * have to be updated also + */ + vfd->cmploc = vfp->data + current_offset; + 8041d38: e0bffd17 ldw r2,-12(fp) + 8041d3c: 10c00617 ldw r3,24(r2) + 8041d40: e0bffa17 ldw r2,-24(fp) + 8041d44: 1887883a add r3,r3,r2 + 8041d48: e0bff417 ldw r2,-48(fp) + 8041d4c: 10c00215 stw r3,8(r2) + } + + /* copy the data to the current file pointer */ + MEMCPY(vfd->cmploc,buf,bcount); + 8041d50: e0bff417 ldw r2,-48(fp) + 8041d54: 10800217 ldw r2,8(r2) + 8041d58: e1bffc17 ldw r6,-16(fp) + 8041d5c: e17ff717 ldw r5,-36(fp) + 8041d60: 1009883a mov r4,r2 + 8041d64: 80086b80 call 80086b8 + + /* update the current file pointer */ + vfd->cmploc += bcount; + 8041d68: e0bff417 ldw r2,-48(fp) + 8041d6c: 10c00217 ldw r3,8(r2) + 8041d70: e0bffc17 ldw r2,-16(fp) + 8041d74: 1887883a add r3,r3,r2 + 8041d78: e0bff417 ldw r2,-48(fp) + 8041d7c: 10c00215 stw r3,8(r2) + + /* if the resulting current offset is greater than the file size */ + if (current_offset + bcount > vfp->comp_size) + 8041d80: e0fffa17 ldw r3,-24(fp) + 8041d84: e0bffc17 ldw r2,-16(fp) + 8041d88: 1885883a add r2,r3,r2 + 8041d8c: e0fffd17 ldw r3,-12(fp) + 8041d90: 18c00817 ldw r3,32(r3) + 8041d94: 1880052e bgeu r3,r2,8041dac + { + /* update the "compressed" file size */ + vfp->comp_size = current_offset + bcount; + 8041d98: e0fffa17 ldw r3,-24(fp) + 8041d9c: e0bffc17 ldw r2,-16(fp) + 8041da0: 1887883a add r3,r3,r2 + 8041da4: e0bffd17 ldw r2,-12(fp) + 8041da8: 10c00815 stw r3,32(r2) + } + + /* since we turn off the compression bit below, the "real" size and + the compressed size must be the same */ + vfp->real_size = vfp->comp_size; + 8041dac: e0bffd17 ldw r2,-12(fp) + 8041db0: 10c00817 ldw r3,32(r2) + 8041db4: e0bffd17 ldw r2,-12(fp) + 8041db8: 10c00715 stw r3,28(r2) + + /* turn off the compression flag */ + vfp->flags &= ~VF_HTMLCOMPRESSED; + 8041dbc: e0bffd17 ldw r2,-12(fp) + 8041dc0: 10c0058b ldhu r3,22(r2) + 8041dc4: 00bfff84 movi r2,-2 + 8041dc8: 1884703a and r2,r3,r2 + 8041dcc: 1007883a mov r3,r2 + 8041dd0: e0bffd17 ldw r2,-12(fp) + 8041dd4: 10c0058d sth r3,22(r2) + + /* the data in the file is stale */ + vfp->flags |= VF_STALE; + 8041dd8: e0bffd17 ldw r2,-12(fp) + 8041ddc: 1080058b ldhu r2,22(r2) + 8041de0: 10808014 ori r2,r2,512 + 8041de4: 1007883a mov r3,r2 + 8041de8: e0bffd17 ldw r2,-12(fp) + 8041dec: 10c0058d sth r3,22(r2) + + /* return the number of "items" written */ + return items; + 8041df0: e0bff517 ldw r2,-44(fp) + +#endif /* HT_RWVFS */ +} + 8041df4: e037883a mov sp,fp + 8041df8: dfc00117 ldw ra,4(sp) + 8041dfc: df000017 ldw fp,0(sp) + 8041e00: dec00204 addi sp,sp,8 + 8041e04: f800283a ret + +08041e08 : + * RETURNS: + */ + +int +vfwrite(char * buf, unsigned size, unsigned items, VFILE * vfd) +{ + 8041e08: defff904 addi sp,sp,-28 + 8041e0c: dfc00615 stw ra,24(sp) + 8041e10: df000515 stw fp,20(sp) + 8041e14: df000504 addi fp,sp,20 + 8041e18: e13ffe15 stw r4,-8(fp) + 8041e1c: e17ffd15 stw r5,-12(fp) + 8041e20: e1bffc15 stw r6,-16(fp) + 8041e24: e1fffb15 stw r7,-20(fp) + int rc; + + IN_PROFILER(PF_FS, PF_ENTRY); + + /* lock the VFS */ + vfs_lock(); + 8041e28: 01000144 movi r4,5 + 8041e2c: 80292b40 call 80292b4 + + /* do the write */ + rc = vfwrite_locked(buf, size, items, vfd); + 8041e30: e1fffb17 ldw r7,-20(fp) + 8041e34: e1bffc17 ldw r6,-16(fp) + 8041e38: e17ffd17 ldw r5,-12(fp) + 8041e3c: e13ffe17 ldw r4,-8(fp) + 8041e40: 8041a5c0 call 8041a5c + 8041e44: e0bfff15 stw r2,-4(fp) + + /* unlock the VFS */ + vfs_unlock(); + 8041e48: 01000144 movi r4,5 + 8041e4c: 80293680 call 8029368 + + IN_PROFILER(PF_FS, PF_EXIT); + + return rc; + 8041e50: e0bfff17 ldw r2,-4(fp) +} + 8041e54: e037883a mov sp,fp + 8041e58: dfc00117 ldw ra,4(sp) + 8041e5c: df000017 ldw fp,0(sp) + 8041e60: dec00204 addi sp,sp,8 + 8041e64: f800283a ret + +08041e68 : + * RETURNS: + */ + +int +vfseek(VFILE * vfd, long offset, int mode) +{ + 8041e68: defff904 addi sp,sp,-28 + 8041e6c: dfc00615 stw ra,24(sp) + 8041e70: df000515 stw fp,20(sp) + 8041e74: df000504 addi fp,sp,20 + 8041e78: e13ffd15 stw r4,-12(fp) + 8041e7c: e17ffc15 stw r5,-16(fp) + 8041e80: e1bffb15 stw r6,-20(fp) + /* lock the VFS */ + vfs_lock(); + 8041e84: 01000144 movi r4,5 + 8041e88: 80292b40 call 80292b4 + + if (isvfile_locked(vfd)) + 8041e8c: e13ffd17 ldw r4,-12(fp) + 8041e90: 80425400 call 8042540 + 8041e94: 10004126 beq r2,zero,8041f9c + { +#ifdef HT_RWVFS + /* the caller is trying to seek a file that's been deleted, + so return an error indication */ + if (vfd->file == NULL) + 8041e98: e0bffd17 ldw r2,-12(fp) + 8041e9c: 10800117 ldw r2,4(r2) + 8041ea0: 1000041e bne r2,zero,8041eb4 + { + vfs_unlock(); + 8041ea4: 01000144 movi r4,5 + 8041ea8: 80293680 call 8029368 + return -1; + 8041eac: 00bfffc4 movi r2,-1 + 8041eb0: 00003d06 br 8041fa8 + } +#endif /* HT_RWVFS */ + +#ifdef HT_EXTDEV + if (vfd->file->method) + 8041eb4: e0bffd17 ldw r2,-12(fp) + 8041eb8: 10800117 ldw r2,4(r2) + 8041ebc: 10800a17 ldw r2,40(r2) + 8041ec0: 10000f26 beq r2,zero,8041f00 + { + struct vfroutines *vfp = (struct vfroutines*)(vfd->file->method); + 8041ec4: e0bffd17 ldw r2,-12(fp) + 8041ec8: 10800117 ldw r2,4(r2) + 8041ecc: 10800a17 ldw r2,40(r2) + 8041ed0: e0bfff15 stw r2,-4(fp) + int rc; + + rc = vfp->r_fseek(vfd, offset, mode); + 8041ed4: e0bfff17 ldw r2,-4(fp) + 8041ed8: 10800517 ldw r2,20(r2) + 8041edc: e1bffb17 ldw r6,-20(fp) + 8041ee0: e17ffc17 ldw r5,-16(fp) + 8041ee4: e13ffd17 ldw r4,-12(fp) + 8041ee8: 103ee83a callr r2 + 8041eec: e0bffe15 stw r2,-8(fp) + vfs_unlock(); + 8041ef0: 01000144 movi r4,5 + 8041ef4: 80293680 call 8029368 + return rc; + 8041ef8: e0bffe17 ldw r2,-8(fp) + 8041efc: 00002a06 br 8041fa8 + } +#endif /* HT_EXTDEV */ + /* this vfseek() currently only supports seek to exact + end or begining of file */ + switch (mode) + 8041f00: e0bffb17 ldw r2,-20(fp) + 8041f04: 10800060 cmpeqi r2,r2,1 + 8041f08: 10000d1e bne r2,zero,8041f40 + 8041f0c: e0bffb17 ldw r2,-20(fp) + 8041f10: 108000a0 cmpeqi r2,r2,2 + 8041f14: 1000111e bne r2,zero,8041f5c + 8041f18: e0bffb17 ldw r2,-20(fp) + 8041f1c: 10001b1e bne r2,zero,8041f8c + { + case SEEK_SET: + vfd->cmploc = vfd->file->data + offset; + 8041f20: e0bffd17 ldw r2,-12(fp) + 8041f24: 10800117 ldw r2,4(r2) + 8041f28: 10c00617 ldw r3,24(r2) + 8041f2c: e0bffc17 ldw r2,-16(fp) + 8041f30: 1887883a add r3,r3,r2 + 8041f34: e0bffd17 ldw r2,-12(fp) + 8041f38: 10c00215 stw r3,8(r2) + break; + 8041f3c: 00001306 br 8041f8c + case SEEK_CUR: + /* If the file is compressed, then the following + * adjustment is inaccurate. Currently we don't have + * any scenario where this happens. - handle later */ + vfd->cmploc += offset; + 8041f40: e0bffd17 ldw r2,-12(fp) + 8041f44: 10c00217 ldw r3,8(r2) + 8041f48: e0bffc17 ldw r2,-16(fp) + 8041f4c: 1887883a add r3,r3,r2 + 8041f50: e0bffd17 ldw r2,-12(fp) + 8041f54: 10c00215 stw r3,8(r2) + break; + 8041f58: 00000c06 br 8041f8c + case SEEK_END: + vfd->cmploc = vfd->file->data + vfd->file->comp_size + offset; + 8041f5c: e0bffd17 ldw r2,-12(fp) + 8041f60: 10800117 ldw r2,4(r2) + 8041f64: 10c00617 ldw r3,24(r2) + 8041f68: e0bffd17 ldw r2,-12(fp) + 8041f6c: 10800117 ldw r2,4(r2) + 8041f70: 11000817 ldw r4,32(r2) + 8041f74: e0bffc17 ldw r2,-16(fp) + 8041f78: 2085883a add r2,r4,r2 + 8041f7c: 1887883a add r3,r3,r2 + 8041f80: e0bffd17 ldw r2,-12(fp) + 8041f84: 10c00215 stw r3,8(r2) + break; + 8041f88: 0001883a nop + } + vfs_unlock(); + 8041f8c: 01000144 movi r4,5 + 8041f90: 80293680 call 8029368 + return(0); + 8041f94: 0005883a mov r2,zero + 8041f98: 00000306 br 8041fa8 + } + + vfs_unlock(); + 8041f9c: 01000144 movi r4,5 + 8041fa0: 80293680 call 8029368 + +#ifdef HT_LOCALFS + /* default to call on local system */ + return(fseek((FILE*)vfd, offset, mode)); +#else + return -1; + 8041fa4: 00bfffc4 movi r2,-1 +#endif /* HT_LOCALFS */ +} + 8041fa8: e037883a mov sp,fp + 8041fac: dfc00117 ldw ra,4(sp) + 8041fb0: df000017 ldw fp,0(sp) + 8041fb4: dec00204 addi sp,sp,8 + 8041fb8: f800283a ret + +08041fbc : + * RETURNS: + */ + +long +vftell(VFILE * vfd) +{ + 8041fbc: defffb04 addi sp,sp,-20 + 8041fc0: dfc00415 stw ra,16(sp) + 8041fc4: df000315 stw fp,12(sp) + 8041fc8: df000304 addi fp,sp,12 + 8041fcc: e13ffd15 stw r4,-12(fp) + /* lock the VFS */ + vfs_lock(); + 8041fd0: 01000144 movi r4,5 + 8041fd4: 80292b40 call 80292b4 + + if (isvfile_locked(vfd)) + 8041fd8: e13ffd17 ldw r4,-12(fp) + 8041fdc: 80425400 call 8042540 + 8041fe0: 10003126 beq r2,zero,80420a8 + { +#ifdef HT_RWVFS + /* the caller is trying to ftell a deleted file, + so return an error condition */ + if (vfd->file == NULL) + 8041fe4: e0bffd17 ldw r2,-12(fp) + 8041fe8: 10800117 ldw r2,4(r2) + 8041fec: 1000041e bne r2,zero,8042000 + { + vfs_unlock(); + 8041ff0: 01000144 movi r4,5 + 8041ff4: 80293680 call 8029368 + return -1; + 8041ff8: 00bfffc4 movi r2,-1 + 8041ffc: 00002d06 br 80420b4 + } +#endif /* HT_RWVFS */ + +#ifdef HT_EXTDEV + if (vfd->file->method) + 8042000: e0bffd17 ldw r2,-12(fp) + 8042004: 10800117 ldw r2,4(r2) + 8042008: 10800a17 ldw r2,40(r2) + 804200c: 10000d26 beq r2,zero,8042044 + { + struct vfroutines * vfp = (struct vfroutines*) (vfd->file->method); + 8042010: e0bffd17 ldw r2,-12(fp) + 8042014: 10800117 ldw r2,4(r2) + 8042018: 10800a17 ldw r2,40(r2) + 804201c: e0bfff15 stw r2,-4(fp) + long rc; + + rc = vfp->r_ftell(vfd); + 8042020: e0bfff17 ldw r2,-4(fp) + 8042024: 10800617 ldw r2,24(r2) + 8042028: e13ffd17 ldw r4,-12(fp) + 804202c: 103ee83a callr r2 + 8042030: e0bffe15 stw r2,-8(fp) + vfs_unlock(); + 8042034: 01000144 movi r4,5 + 8042038: 80293680 call 8029368 + return rc; + 804203c: e0bffe17 ldw r2,-8(fp) + 8042040: 00001c06 br 80420b4 + } +#endif /* HT_EXTDEV */ + /* if file has been fseeked to end, return uncompressed size. + else return current location in compression stream */ + if (vfd->cmploc == vfd->file->data + vfd->file->comp_size) + 8042044: e0bffd17 ldw r2,-12(fp) + 8042048: 10c00217 ldw r3,8(r2) + 804204c: e0bffd17 ldw r2,-12(fp) + 8042050: 10800117 ldw r2,4(r2) + 8042054: 11000617 ldw r4,24(r2) + 8042058: e0bffd17 ldw r2,-12(fp) + 804205c: 10800117 ldw r2,4(r2) + 8042060: 10800817 ldw r2,32(r2) + 8042064: 2085883a add r2,r4,r2 + 8042068: 1880061e bne r3,r2,8042084 + { + vfs_unlock(); + 804206c: 01000144 movi r4,5 + 8042070: 80293680 call 8029368 + + return vfd->file->comp_size; + 8042074: e0bffd17 ldw r2,-12(fp) + 8042078: 10800117 ldw r2,4(r2) + 804207c: 10800817 ldw r2,32(r2) + 8042080: 00000c06 br 80420b4 + } + else + { + vfs_unlock(); + 8042084: 01000144 movi r4,5 + 8042088: 80293680 call 8029368 + + return (vfd->cmploc - vfd->file->data); + 804208c: e0bffd17 ldw r2,-12(fp) + 8042090: 10c00217 ldw r3,8(r2) + 8042094: e0bffd17 ldw r2,-12(fp) + 8042098: 10800117 ldw r2,4(r2) + 804209c: 10800617 ldw r2,24(r2) + 80420a0: 1885c83a sub r2,r3,r2 + 80420a4: 00000306 br 80420b4 + } + } + + vfs_unlock(); + 80420a8: 01000144 movi r4,5 + 80420ac: 80293680 call 8029368 + +#ifdef HT_LOCALFS + /* default to call on local system */ + return(ftell((FILE*)vfd)); +#else + return EBADF; + 80420b0: 00800244 movi r2,9 +#endif /* HT_LOCALFS */ +} + 80420b4: e037883a mov sp,fp + 80420b8: dfc00117 ldw ra,4(sp) + 80420bc: df000017 ldw fp,0(sp) + 80420c0: dec00204 addi sp,sp,8 + 80420c4: f800283a ret + +080420c8 : + * RETURNS: + */ + +int +vgetc_locked(VFILE * vfd) +{ + 80420c8: defffb04 addi sp,sp,-20 + 80420cc: dfc00415 stw ra,16(sp) + 80420d0: df000315 stw fp,12(sp) + 80420d4: df000304 addi fp,sp,12 + 80420d8: e13ffd15 stw r4,-12(fp) + int chr; + + if (isvfile_locked(vfd)) + 80420dc: e13ffd17 ldw r4,-12(fp) + 80420e0: 80425400 call 8042540 + 80420e4: 10002f26 beq r2,zero,80421a4 + { +#ifdef HT_RWVFS + /* the caller is trying to read a file that's been deleted, + so return an error condition */ + if (vfd->file == NULL) + 80420e8: e0bffd17 ldw r2,-12(fp) + 80420ec: 10800117 ldw r2,4(r2) + 80420f0: 1000021e bne r2,zero,80420fc + { + return EOF; + 80420f4: 00bfffc4 movi r2,-1 + 80420f8: 00002c06 br 80421ac + } +#endif /* HT_RWVFS */ + +#ifdef HT_EXTDEV + if (vfd->file->method) + 80420fc: e0bffd17 ldw r2,-12(fp) + 8042100: 10800117 ldw r2,4(r2) + 8042104: 10800a17 ldw r2,40(r2) + 8042108: 10000926 beq r2,zero,8042130 + { + struct vfroutines * vfp = (struct vfroutines*) (vfd->file->method); + 804210c: e0bffd17 ldw r2,-12(fp) + 8042110: 10800117 ldw r2,4(r2) + 8042114: 10800a17 ldw r2,40(r2) + 8042118: e0bffe15 stw r2,-8(fp) + return (vfp->r_fgetc(vfd)); + 804211c: e0bffe17 ldw r2,-8(fp) + 8042120: 10800717 ldw r2,28(r2) + 8042124: e13ffd17 ldw r4,-12(fp) + 8042128: 103ee83a callr r2 + 804212c: 00001f06 br 80421ac +#endif /* HT_EXTDEV */ + +#ifdef HT_RWVFS + /* a freshly created file might not have a data buffer associated + with it yet */ + if (vfd->file->data == NULL) + 8042130: e0bffd17 ldw r2,-12(fp) + 8042134: 10800117 ldw r2,4(r2) + 8042138: 10800617 ldw r2,24(r2) + 804213c: 1000021e bne r2,zero,8042148 + return EOF; + 8042140: 00bfffc4 movi r2,-1 + 8042144: 00001906 br 80421ac + } + else /* HTML compression flag not set */ + { +#endif /* HTML_COMPRESSION */ + /* Check to see if read has advanced to end of file */ + if (vfd->cmploc >= (vfd->file->data + vfd->file->comp_size)) + 8042148: e0bffd17 ldw r2,-12(fp) + 804214c: 10c00217 ldw r3,8(r2) + 8042150: e0bffd17 ldw r2,-12(fp) + 8042154: 10800117 ldw r2,4(r2) + 8042158: 11000617 ldw r4,24(r2) + 804215c: e0bffd17 ldw r2,-12(fp) + 8042160: 10800117 ldw r2,4(r2) + 8042164: 10800817 ldw r2,32(r2) + 8042168: 2085883a add r2,r4,r2 + 804216c: 18800336 bltu r3,r2,804217c + chr = EOF; + 8042170: 00bfffc4 movi r2,-1 + 8042174: e0bfff15 stw r2,-4(fp) + 8042178: 00000806 br 804219c + else /* else just get next char to return */ + chr = *(vfd->cmploc++); + 804217c: e0bffd17 ldw r2,-12(fp) + 8042180: 10800217 ldw r2,8(r2) + 8042184: 11000044 addi r4,r2,1 + 8042188: e0fffd17 ldw r3,-12(fp) + 804218c: 19000215 stw r4,8(r3) + 8042190: 10800003 ldbu r2,0(r2) + 8042194: 10803fcc andi r2,r2,255 + 8042198: e0bfff15 stw r2,-4(fp) +#ifdef HTML_COMPRESSION + } /* need to close brace form if...else; */ +#endif /* HTML_COMPRESSION */ + + return chr; + 804219c: e0bfff17 ldw r2,-4(fp) + 80421a0: 00000206 br 80421ac + +#ifdef HT_LOCALFS + /* default to call on local system */ + return(getc((FILE*)vfd)); +#else + dtrap(); /* can this happen? */ + 80421a4: 8028cd40 call 8028cd4 + return EOF; + 80421a8: 00bfffc4 movi r2,-1 +#endif /* HT_LOCALFS */ +} + 80421ac: e037883a mov sp,fp + 80421b0: dfc00117 ldw ra,4(sp) + 80421b4: df000017 ldw fp,0(sp) + 80421b8: dec00204 addi sp,sp,8 + 80421bc: f800283a ret + +080421c0 : + * RETURNS: + */ + +int +vgetc(VFILE * vfd) +{ + 80421c0: defffc04 addi sp,sp,-16 + 80421c4: dfc00315 stw ra,12(sp) + 80421c8: df000215 stw fp,8(sp) + 80421cc: df000204 addi fp,sp,8 + 80421d0: e13ffe15 stw r4,-8(fp) + int rc; + + /* lock the VFS */ + vfs_lock(); + 80421d4: 01000144 movi r4,5 + 80421d8: 80292b40 call 80292b4 + + /* get the character */ + rc = vgetc_locked(vfd); + 80421dc: e13ffe17 ldw r4,-8(fp) + 80421e0: 80420c80 call 80420c8 + 80421e4: e0bfff15 stw r2,-4(fp) + + /* unlock the VFS */ + vfs_unlock(); + 80421e8: 01000144 movi r4,5 + 80421ec: 80293680 call 8029368 + return rc; + 80421f0: e0bfff17 ldw r2,-4(fp) +} + 80421f4: e037883a mov sp,fp + 80421f8: dfc00117 ldw ra,4(sp) + 80421fc: df000017 ldw fp,0(sp) + 8042200: dec00204 addi sp,sp,8 + 8042204: f800283a ret + +08042208 : + * RETURNS: + */ + +struct vfs_file * +vfslookup_locked(char * name) +{ + 8042208: defffb04 addi sp,sp,-20 + 804220c: dfc00415 stw ra,16(sp) + 8042210: df000315 stw fp,12(sp) + 8042214: df000304 addi fp,sp,12 + 8042218: e13ffd15 stw r4,-12(fp) + +#ifdef VFS_STRIPPATH + char * cp; + + /* If root path is prepended to name, skip past it */ + if (*name == '/' || *name == '\\') + 804221c: e0bffd17 ldw r2,-12(fp) + 8042220: 10800003 ldbu r2,0(r2) + 8042224: 10803fcc andi r2,r2,255 + 8042228: 1080201c xori r2,r2,128 + 804222c: 10bfe004 addi r2,r2,-128 + 8042230: 10800be0 cmpeqi r2,r2,47 + 8042234: 1000071e bne r2,zero,8042254 + 8042238: e0bffd17 ldw r2,-12(fp) + 804223c: 10800003 ldbu r2,0(r2) + 8042240: 10803fcc andi r2,r2,255 + 8042244: 1080201c xori r2,r2,128 + 8042248: 10bfe004 addi r2,r2,-128 + 804224c: 10801718 cmpnei r2,r2,92 + 8042250: 1000191e bne r2,zero,80422b8 + { + cp = strippath(name); + 8042254: e13ffd17 ldw r4,-12(fp) + 8042258: 80423740 call 8042374 + 804225c: e0bffe15 stw r2,-8(fp) + + if (!cp) /* strippath coundn't match our path */ + 8042260: e0bffe17 ldw r2,-8(fp) + 8042264: 1000121e bne r2,zero,80422b0 + { + /* Files like "/hub47.gif" need to be taken care of */ + if (*name == '/' || *name == '\\') + 8042268: e0bffd17 ldw r2,-12(fp) + 804226c: 10800003 ldbu r2,0(r2) + 8042270: 10803fcc andi r2,r2,255 + 8042274: 1080201c xori r2,r2,128 + 8042278: 10bfe004 addi r2,r2,-128 + 804227c: 10800be0 cmpeqi r2,r2,47 + 8042280: 1000071e bne r2,zero,80422a0 + 8042284: e0bffd17 ldw r2,-12(fp) + 8042288: 10800003 ldbu r2,0(r2) + 804228c: 10803fcc andi r2,r2,255 + 8042290: 1080201c xori r2,r2,128 + 8042294: 10bfe004 addi r2,r2,-128 + 8042298: 10801718 cmpnei r2,r2,92 + 804229c: 1000061e bne r2,zero,80422b8 + name++; + 80422a0: e0bffd17 ldw r2,-12(fp) + 80422a4: 10800044 addi r2,r2,1 + 80422a8: e0bffd15 stw r2,-12(fp) + 80422ac: 00000206 br 80422b8 + } + else + name = cp ; + 80422b0: e0bffe17 ldw r2,-8(fp) + 80422b4: e0bffd15 stw r2,-12(fp) + } +#endif /* VFS_STRIPPATH */ + + /* see if there is a question mark in the file name */ + if (strchr(name,'?')) + 80422b8: 01400fc4 movi r5,63 + 80422bc: e13ffd17 ldw r4,-12(fp) + 80422c0: 8042dfc0 call 8042dfc + 80422c4: 10000326 beq r2,zero,80422d4 + { + dtrap(); /* is this still allowed? */ + 80422c8: 8028cd40 call 8028cd4 + return NULL; + 80422cc: 0005883a mov r2,zero + 80422d0: 00001106 br 8042318 + } + + for (vp = vfsfiles; vp; vp = vp->next) /* search vfs list for name */ + 80422d4: d0a0a317 ldw r2,-32116(gp) + 80422d8: e0bfff15 stw r2,-4(fp) + 80422dc: 00000b06 br 804230c + { + if (strcmp(name, vp->name) == 0) + 80422e0: e0bfff17 ldw r2,-4(fp) + 80422e4: 10800104 addi r2,r2,4 + 80422e8: 100b883a mov r5,r2 + 80422ec: e13ffd17 ldw r4,-12(fp) + 80422f0: 800c2240 call 800c224 + 80422f4: 1000021e bne r2,zero,8042300 + return vp; + 80422f8: e0bfff17 ldw r2,-4(fp) + 80422fc: 00000606 br 8042318 + for (vp = vfsfiles; vp; vp = vp->next) /* search vfs list for name */ + 8042300: e0bfff17 ldw r2,-4(fp) + 8042304: 10800017 ldw r2,0(r2) + 8042308: e0bfff15 stw r2,-4(fp) + 804230c: e0bfff17 ldw r2,-4(fp) + 8042310: 103ff31e bne r2,zero,80422e0 + } + + return NULL; /* fall to here if not found in for loop */ + 8042314: 0005883a mov r2,zero +} + 8042318: e037883a mov sp,fp + 804231c: dfc00117 ldw ra,4(sp) + 8042320: df000017 ldw fp,0(sp) + 8042324: dec00204 addi sp,sp,8 + 8042328: f800283a ret + +0804232c : + * RETURNS: + */ + +struct vfs_file * +vfslookup(char * name) +{ + 804232c: defffc04 addi sp,sp,-16 + 8042330: dfc00315 stw ra,12(sp) + 8042334: df000215 stw fp,8(sp) + 8042338: df000204 addi fp,sp,8 + 804233c: e13ffe15 stw r4,-8(fp) + if (vfs_log_file_name) + dprintf("vfslookup() passed >%s<\n",name); +#endif /* VFS_UNIT_TEST */ + + /* lock the VFS */ + vfs_lock(); + 8042340: 01000144 movi r4,5 + 8042344: 80292b40 call 80292b4 + + /* do the lookup */ + vp = vfslookup_locked(name); + 8042348: e13ffe17 ldw r4,-8(fp) + 804234c: 80422080 call 8042208 + 8042350: e0bfff15 stw r2,-4(fp) + + /* unlock the VFS */ + vfs_unlock(); + 8042354: 01000144 movi r4,5 + 8042358: 80293680 call 8029368 + return vp; + 804235c: e0bfff17 ldw r2,-4(fp) +} + 8042360: e037883a mov sp,fp + 8042364: dfc00117 ldw ra,4(sp) + 8042368: df000017 ldw fp,0(sp) + 804236c: dec00204 addi sp,sp,8 + 8042370: f800283a ret + +08042374 : + * have the http_root_path prepended; or on any error. + */ + +char * +strippath(char * name) +{ + 8042374: defff904 addi sp,sp,-28 + 8042378: dfc00615 stw ra,24(sp) + 804237c: df000515 stw fp,20(sp) + 8042380: df000504 addi fp,sp,20 + 8042384: e13ffb15 stw r4,-20(fp) + char * path; /* pointer into system path */ + char * ptmp; /* another pointer into path */ + char * ntmp; /* pointer into name text */ + int dirlen; + + ntmp = uslash(name); /* uslash() is defined in misclib\in_utils.c */ + 8042388: e13ffb17 ldw r4,-20(fp) + 804238c: 80273140 call 8027314 + 8042390: e0bffe15 stw r2,-8(fp) + path = http_root_path; /* The servers root path, at least one UNIX slash */ + 8042394: d0a03417 ldw r2,-32560(gp) + 8042398: e0bfff15 stw r2,-4(fp) + while (*path && *ntmp) + 804239c: 00003a06 br 8042488 + { + while (*path == '/') path++; /* strip leading slash */ + 80423a0: e0bfff17 ldw r2,-4(fp) + 80423a4: 10800044 addi r2,r2,1 + 80423a8: e0bfff15 stw r2,-4(fp) + 80423ac: e0bfff17 ldw r2,-4(fp) + 80423b0: 10800003 ldbu r2,0(r2) + 80423b4: 10803fcc andi r2,r2,255 + 80423b8: 1080201c xori r2,r2,128 + 80423bc: 10bfe004 addi r2,r2,-128 + 80423c0: 10800be0 cmpeqi r2,r2,47 + 80423c4: 103ff61e bne r2,zero,80423a0 + if (*path == 0) + 80423c8: e0bfff17 ldw r2,-4(fp) + 80423cc: 10800003 ldbu r2,0(r2) + 80423d0: 10803fcc andi r2,r2,255 + 80423d4: 1080201c xori r2,r2,128 + 80423d8: 10bfe004 addi r2,r2,-128 + 80423dc: 10003726 beq r2,zero,80424bc + break; + /* find number of chars in this directory layer's name */ + ptmp = strchr(path, '/'); /* location of next slash in path */ + 80423e0: 01400bc4 movi r5,47 + 80423e4: e13fff17 ldw r4,-4(fp) + 80423e8: 8042dfc0 call 8042dfc + 80423ec: e0bffc15 stw r2,-16(fp) + if (ptmp) + 80423f0: e0bffc17 ldw r2,-16(fp) + 80423f4: 10000526 beq r2,zero,804240c + dirlen = ptmp - path; + 80423f8: e0fffc17 ldw r3,-16(fp) + 80423fc: e0bfff17 ldw r2,-4(fp) + 8042400: 1885c83a sub r2,r3,r2 + 8042404: e0bffd15 stw r2,-12(fp) + 8042408: 00000706 br 8042428 + else + dirlen = strlen(path); + 804240c: e13fff17 ldw r4,-4(fp) + 8042410: 8002dac0 call 8002dac + 8042414: e0bffd15 stw r2,-12(fp) + + while (*ntmp == '/') ntmp++; /* strip leading slash */ + 8042418: 00000306 br 8042428 + 804241c: e0bffe17 ldw r2,-8(fp) + 8042420: 10800044 addi r2,r2,1 + 8042424: e0bffe15 stw r2,-8(fp) + 8042428: e0bffe17 ldw r2,-8(fp) + 804242c: 10800003 ldbu r2,0(r2) + 8042430: 10803fcc andi r2,r2,255 + 8042434: 1080201c xori r2,r2,128 + 8042438: 10bfe004 addi r2,r2,-128 + 804243c: 10800be0 cmpeqi r2,r2,47 + 8042440: 103ff61e bne r2,zero,804241c + if (strncmp(ntmp, path, dirlen) == 0) + 8042444: e0bffd17 ldw r2,-12(fp) + 8042448: 100d883a mov r6,r2 + 804244c: e17fff17 ldw r5,-4(fp) + 8042450: e13ffe17 ldw r4,-8(fp) + 8042454: 8042fec0 call 8042fec + 8042458: 1000091e bne r2,zero,8042480 + { + path += dirlen; + 804245c: e0bffd17 ldw r2,-12(fp) + 8042460: e0ffff17 ldw r3,-4(fp) + 8042464: 1885883a add r2,r3,r2 + 8042468: e0bfff15 stw r2,-4(fp) + ntmp += dirlen; + 804246c: e0bffd17 ldw r2,-12(fp) + 8042470: e0fffe17 ldw r3,-8(fp) + 8042474: 1885883a add r2,r3,r2 + 8042478: e0bffe15 stw r2,-8(fp) + 804247c: 00000206 br 8042488 + } + else + return NULL; /* didn't match */ + 8042480: 0005883a mov r2,zero + 8042484: 00002906 br 804252c + while (*path && *ntmp) + 8042488: e0bfff17 ldw r2,-4(fp) + 804248c: 10800003 ldbu r2,0(r2) + 8042490: 10803fcc andi r2,r2,255 + 8042494: 1080201c xori r2,r2,128 + 8042498: 10bfe004 addi r2,r2,-128 + 804249c: 10000826 beq r2,zero,80424c0 + 80424a0: e0bffe17 ldw r2,-8(fp) + 80424a4: 10800003 ldbu r2,0(r2) + 80424a8: 10803fcc andi r2,r2,255 + 80424ac: 1080201c xori r2,r2,128 + 80424b0: 10bfe004 addi r2,r2,-128 + 80424b4: 103fbd1e bne r2,zero,80423ac + 80424b8: 00000106 br 80424c0 + break; + 80424bc: 0001883a nop + } + if (*path == '\0') + 80424c0: e0bfff17 ldw r2,-4(fp) + 80424c4: 10800003 ldbu r2,0(r2) + 80424c8: 10803fcc andi r2,r2,255 + 80424cc: 1080201c xori r2,r2,128 + 80424d0: 10bfe004 addi r2,r2,-128 + 80424d4: 1000141e bne r2,zero,8042528 + { + while (*ntmp == '\\' || *ntmp == '/') + 80424d8: 00000306 br 80424e8 + ntmp++; + 80424dc: e0bffe17 ldw r2,-8(fp) + 80424e0: 10800044 addi r2,r2,1 + 80424e4: e0bffe15 stw r2,-8(fp) + while (*ntmp == '\\' || *ntmp == '/') + 80424e8: e0bffe17 ldw r2,-8(fp) + 80424ec: 10800003 ldbu r2,0(r2) + 80424f0: 10803fcc andi r2,r2,255 + 80424f4: 1080201c xori r2,r2,128 + 80424f8: 10bfe004 addi r2,r2,-128 + 80424fc: 10801720 cmpeqi r2,r2,92 + 8042500: 103ff61e bne r2,zero,80424dc + 8042504: e0bffe17 ldw r2,-8(fp) + 8042508: 10800003 ldbu r2,0(r2) + 804250c: 10803fcc andi r2,r2,255 + 8042510: 1080201c xori r2,r2,128 + 8042514: 10bfe004 addi r2,r2,-128 + 8042518: 10800be0 cmpeqi r2,r2,47 + 804251c: 103fef1e bne r2,zero,80424dc + return ntmp; + 8042520: e0bffe17 ldw r2,-8(fp) + 8042524: 00000106 br 804252c + } + else + return NULL; + 8042528: 0005883a mov r2,zero +} + 804252c: e037883a mov sp,fp + 8042530: dfc00117 ldw ra,4(sp) + 8042534: df000017 ldw fp,0(sp) + 8042538: dec00204 addi sp,sp,8 + 804253c: f800283a ret + +08042540 : + * RETURNS: + */ + +int +isvfile_locked(VFILE * vfp) +{ + 8042540: defffd04 addi sp,sp,-12 + 8042544: df000215 stw fp,8(sp) + 8042548: df000204 addi fp,sp,8 + 804254c: e13ffe15 stw r4,-8(fp) + VFILE * vtmp; + + for (vtmp = vfiles; vtmp; vtmp = vtmp->next) + 8042550: d0a0a217 ldw r2,-32120(gp) + 8042554: e0bfff15 stw r2,-4(fp) + 8042558: 00000806 br 804257c + if (vtmp == vfp) + 804255c: e0ffff17 ldw r3,-4(fp) + 8042560: e0bffe17 ldw r2,-8(fp) + 8042564: 1880021e bne r3,r2,8042570 + return TRUE; + 8042568: 00800044 movi r2,1 + 804256c: 00000606 br 8042588 + for (vtmp = vfiles; vtmp; vtmp = vtmp->next) + 8042570: e0bfff17 ldw r2,-4(fp) + 8042574: 10800017 ldw r2,0(r2) + 8042578: e0bfff15 stw r2,-4(fp) + 804257c: e0bfff17 ldw r2,-4(fp) + 8042580: 103ff61e bne r2,zero,804255c + + return FALSE; /* passed pointer not found in list */ + 8042584: 0005883a mov r2,zero +} + 8042588: e037883a mov sp,fp + 804258c: df000017 ldw fp,0(sp) + 8042590: dec00104 addi sp,sp,4 + 8042594: f800283a ret + +08042598 : + * RETURNS: + */ + +int +isvfile(VFILE * vfp) +{ + 8042598: defffc04 addi sp,sp,-16 + 804259c: dfc00315 stw ra,12(sp) + 80425a0: df000215 stw fp,8(sp) + 80425a4: df000204 addi fp,sp,8 + 80425a8: e13ffe15 stw r4,-8(fp) + int rc; + + /* lock the VFS */ + vfs_lock(); + 80425ac: 01000144 movi r4,5 + 80425b0: 80292b40 call 80292b4 + + /* do the lookup */ + rc = isvfile_locked(vfp); + 80425b4: e13ffe17 ldw r4,-8(fp) + 80425b8: 80425400 call 8042540 + 80425bc: e0bfff15 stw r2,-4(fp) + + /* unlock the VFS */ + vfs_unlock(); + 80425c0: 01000144 movi r4,5 + 80425c4: 80293680 call 8029368 + return rc; + 80425c8: e0bfff17 ldw r2,-4(fp) +} + 80425cc: e037883a mov sp,fp + 80425d0: dfc00117 ldw ra,4(sp) + 80425d4: df000017 ldw fp,0(sp) + 80425d8: dec00204 addi sp,sp,8 + 80425dc: f800283a ret + +080425e0 : + * RETURNS: + */ + +int +vferror(VFILE * vfd) +{ + 80425e0: defffd04 addi sp,sp,-12 + 80425e4: dfc00215 stw ra,8(sp) + 80425e8: df000115 stw fp,4(sp) + 80425ec: df000104 addi fp,sp,4 + 80425f0: e13fff15 stw r4,-4(fp) + /* lock the VFS */ + vfs_lock(); + 80425f4: 01000144 movi r4,5 + 80425f8: 80292b40 call 80292b4 + + if (isvfile_locked(vfd)) + 80425fc: e13fff17 ldw r4,-4(fp) + 8042600: 80425400 call 8042540 + 8042604: 10000526 beq r2,zero,804261c + { + vfs_unlock(); + 8042608: 01000144 movi r4,5 + 804260c: 80293680 call 8029368 + + return vfd->error; + 8042610: e0bfff17 ldw r2,-4(fp) + 8042614: 10800417 ldw r2,16(r2) + 8042618: 00000306 br 8042628 + } + + vfs_unlock(); + 804261c: 01000144 movi r4,5 + 8042620: 80293680 call 8029368 + +#ifdef HT_LOCALFS + return(ferror((FILE*)vfd)); +#else /* not a VFILE, and no local FS */ + return -1; /* should this be an error? */ + 8042624: 00bfffc4 movi r2,-1 +#endif /* HT_LOCALFS */ +} + 8042628: e037883a mov sp,fp + 804262c: dfc00117 ldw ra,4(sp) + 8042630: df000017 ldw fp,0(sp) + 8042634: dec00204 addi sp,sp,8 + 8042638: f800283a ret + +0804263c : + * + * RETURNS: + */ + +void vclearerr(VFILE * vfd) +{ + 804263c: defffd04 addi sp,sp,-12 + 8042640: dfc00215 stw ra,8(sp) + 8042644: df000115 stw fp,4(sp) + 8042648: df000104 addi fp,sp,4 + 804264c: e13fff15 stw r4,-4(fp) + /* lock the VFS */ + vfs_lock(); + 8042650: 01000144 movi r4,5 + 8042654: 80292b40 call 80292b4 + + if (isvfile_locked(vfd)) + 8042658: e13fff17 ldw r4,-4(fp) + 804265c: 80425400 call 8042540 + 8042660: 10000526 beq r2,zero,8042678 + { + vfs_unlock(); + 8042664: 01000144 movi r4,5 + 8042668: 80293680 call 8029368 + + vfd->error = 0; + 804266c: e0bfff17 ldw r2,-4(fp) + 8042670: 10000415 stw zero,16(r2) + return; + 8042674: 00000206 br 8042680 + } + + vfs_unlock(); + 8042678: 01000144 movi r4,5 + 804267c: 80293680 call 8029368 + +#ifdef HT_LOCALFS + clearerr((FILE *) vfd); +#endif /* HT_LOCALFS */ +} + 8042680: e037883a mov sp,fp + 8042684: dfc00117 ldw ra,4(sp) + 8042688: df000017 ldw fp,0(sp) + 804268c: dec00204 addi sp,sp,8 + 8042690: f800283a ret + +08042694 : + * PARAMS: NONE + * + * RETURNS: Error Code or 0 for OK + */ +int prep_vfs(void) +{ + 8042694: defffe04 addi sp,sp,-8 + 8042698: df000115 stw fp,4(sp) + 804269c: df000104 addi fp,sp,4 +int e = 0; + 80426a0: e03fff15 stw zero,-4(fp) + { + dprintf("unable to install VFS NVPARMS, reconfigure nv_formats[]\n"); + dtrap(); + } +#endif /* INCLUDE_NVPARMS */ + return e; + 80426a4: e0bfff17 ldw r2,-4(fp) +} + 80426a8: e037883a mov sp,fp + 80426ac: df000017 ldw fp,0(sp) + 80426b0: dec00104 addi sp,sp,4 + 80426b4: f800283a ret + +080426b8 : +{ + 80426b8: defffe04 addi sp,sp,-8 + 80426bc: dfc00115 stw ra,4(sp) + 80426c0: df000015 stw fp,0(sp) + 80426c4: d839883a mov fp,sp + return ((alt_errno) ? alt_errno() : &errno); + 80426c8: d0a02717 ldw r2,-32612(gp) + 80426cc: 10000326 beq r2,zero,80426dc + 80426d0: d0a02717 ldw r2,-32612(gp) + 80426d4: 103ee83a callr r2 + 80426d8: 00000106 br 80426e0 + 80426dc: d0a04204 addi r2,gp,-32504 +} + 80426e0: e037883a mov sp,fp + 80426e4: dfc00117 ldw ra,4(sp) + 80426e8: df000017 ldw fp,0(sp) + 80426ec: dec00204 addi sp,sp,8 + 80426f0: f800283a ret + +080426f4 : + * + * ALT_FCNTL is mapped onto the fcntl() system call in alt_syscall.h + */ + +int ALT_FCNTL (int file, int cmd, ...) +{ + 80426f4: defff704 addi sp,sp,-36 + 80426f8: dfc00615 stw ra,24(sp) + 80426fc: df000515 stw fp,20(sp) + 8042700: df000504 addi fp,sp,20 + 8042704: e13ffc15 stw r4,-16(fp) + 8042708: e17ffb15 stw r5,-20(fp) + 804270c: e1800215 stw r6,8(fp) + 8042710: e1c00315 stw r7,12(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 8042714: e0bffc17 ldw r2,-16(fp) + 8042718: 10000616 blt r2,zero,8042734 + 804271c: e0bffc17 ldw r2,-16(fp) + 8042720: 10c00324 muli r3,r2,12 + 8042724: 00820174 movhi r2,2053 + 8042728: 10b21a04 addi r2,r2,-14232 + 804272c: 1885883a add r2,r3,r2 + 8042730: 00000106 br 8042738 + 8042734: 0005883a mov r2,zero + 8042738: e0bfff15 stw r2,-4(fp) + + if (fd) + 804273c: e0bfff17 ldw r2,-4(fp) + 8042740: 10002b26 beq r2,zero,80427f0 + { + switch (cmd) + 8042744: e0bffb17 ldw r2,-20(fp) + 8042748: 108000e0 cmpeqi r2,r2,3 + 804274c: 1000041e bne r2,zero,8042760 + 8042750: e0bffb17 ldw r2,-20(fp) + 8042754: 10800120 cmpeqi r2,r2,4 + 8042758: 1000071e bne r2,zero,8042778 + 804275c: 00001e06 br 80427d8 + { + case F_GETFL: + return fd->fd_flags & ~((alt_u32) ALT_FD_FLAGS_MASK); + 8042760: e0bfff17 ldw r2,-4(fp) + 8042764: 10c00217 ldw r3,8(r2) + 8042768: 00900034 movhi r2,16384 + 804276c: 10bfffc4 addi r2,r2,-1 + 8042770: 1884703a and r2,r3,r2 + 8042774: 00002306 br 8042804 + case F_SETFL: + va_start(argp, cmd); + 8042778: e0800204 addi r2,fp,8 + 804277c: e0bffd15 stw r2,-12(fp) + flags = va_arg(argp, long); + 8042780: e0bffd17 ldw r2,-12(fp) + 8042784: 10c00104 addi r3,r2,4 + 8042788: e0fffd15 stw r3,-12(fp) + 804278c: 10800017 ldw r2,0(r2) + 8042790: e0bffe15 stw r2,-8(fp) + fd->fd_flags &= ~ALT_FCNTL_FLAGS_MASK; + 8042794: e0bfff17 ldw r2,-4(fp) + 8042798: 10c00217 ldw r3,8(r2) + 804279c: 00affdc4 movi r2,-16393 + 80427a0: 1886703a and r3,r3,r2 + 80427a4: e0bfff17 ldw r2,-4(fp) + 80427a8: 10c00215 stw r3,8(r2) + fd->fd_flags |= (flags & ALT_FCNTL_FLAGS_MASK); + 80427ac: e0bfff17 ldw r2,-4(fp) + 80427b0: 10800217 ldw r2,8(r2) + 80427b4: 1007883a mov r3,r2 + 80427b8: e0bffe17 ldw r2,-8(fp) + 80427bc: 1090020c andi r2,r2,16392 + 80427c0: 1884b03a or r2,r3,r2 + 80427c4: 1007883a mov r3,r2 + 80427c8: e0bfff17 ldw r2,-4(fp) + 80427cc: 10c00215 stw r3,8(r2) + va_end(argp); + return 0; + 80427d0: 0005883a mov r2,zero + 80427d4: 00000b06 br 8042804 + default: + ALT_ERRNO = EINVAL; + 80427d8: 80426b80 call 80426b8 + 80427dc: 1007883a mov r3,r2 + 80427e0: 00800584 movi r2,22 + 80427e4: 18800015 stw r2,0(r3) + return -1; + 80427e8: 00bfffc4 movi r2,-1 + 80427ec: 00000506 br 8042804 + } + } + + ALT_ERRNO = EBADFD; + 80427f0: 80426b80 call 80426b8 + 80427f4: 1007883a mov r3,r2 + 80427f8: 00801444 movi r2,81 + 80427fc: 18800015 stw r2,0(r3) + return -1; + 8042800: 00bfffc4 movi r2,-1 +} + 8042804: e037883a mov sp,fp + 8042808: dfc00117 ldw ra,4(sp) + 804280c: df000017 ldw fp,0(sp) + 8042810: dec00404 addi sp,sp,16 + 8042814: f800283a ret + +08042818 : + * either '/' or '\0' is the prefix of the filename. For example the filename: + * "/myfilesystem/junk.txt" would match: "/myfilesystem", but not: "/myfile". + */ + +alt_dev* alt_find_file (const char* name) +{ + 8042818: defffb04 addi sp,sp,-20 + 804281c: dfc00415 stw ra,16(sp) + 8042820: df000315 stw fp,12(sp) + 8042824: df000304 addi fp,sp,12 + 8042828: e13ffd15 stw r4,-12(fp) + alt_dev* next = (alt_dev*) alt_fs_list.next; + 804282c: d0a02217 ldw r2,-32632(gp) + 8042830: e0bfff15 stw r2,-4(fp) + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) &alt_fs_list) + 8042834: 00003106 br 80428fc + { + len = strlen(next->name); + 8042838: e0bfff17 ldw r2,-4(fp) + 804283c: 10800217 ldw r2,8(r2) + 8042840: 1009883a mov r4,r2 + 8042844: 8002dac0 call 8002dac + 8042848: e0bffe15 stw r2,-8(fp) + + if (next->name[len-1] == '/') + 804284c: e0bfff17 ldw r2,-4(fp) + 8042850: 10c00217 ldw r3,8(r2) + 8042854: e0bffe17 ldw r2,-8(fp) + 8042858: 10bfffc4 addi r2,r2,-1 + 804285c: 1885883a add r2,r3,r2 + 8042860: 10800003 ldbu r2,0(r2) + 8042864: 10803fcc andi r2,r2,255 + 8042868: 1080201c xori r2,r2,128 + 804286c: 10bfe004 addi r2,r2,-128 + 8042870: 10800bd8 cmpnei r2,r2,47 + 8042874: 1000031e bne r2,zero,8042884 + { + len -= 1; + 8042878: e0bffe17 ldw r2,-8(fp) + 804287c: 10bfffc4 addi r2,r2,-1 + 8042880: e0bffe15 stw r2,-8(fp) + } + + if (((name[len] == '/') || (name[len] == '\0')) && + 8042884: e0bffe17 ldw r2,-8(fp) + 8042888: e0fffd17 ldw r3,-12(fp) + 804288c: 1885883a add r2,r3,r2 + 8042890: 10800003 ldbu r2,0(r2) + 8042894: 10803fcc andi r2,r2,255 + 8042898: 1080201c xori r2,r2,128 + 804289c: 10bfe004 addi r2,r2,-128 + 80428a0: 10800be0 cmpeqi r2,r2,47 + 80428a4: 1000081e bne r2,zero,80428c8 + 80428a8: e0bffe17 ldw r2,-8(fp) + 80428ac: e0fffd17 ldw r3,-12(fp) + 80428b0: 1885883a add r2,r3,r2 + 80428b4: 10800003 ldbu r2,0(r2) + 80428b8: 10803fcc andi r2,r2,255 + 80428bc: 1080201c xori r2,r2,128 + 80428c0: 10bfe004 addi r2,r2,-128 + 80428c4: 10000a1e bne r2,zero,80428f0 + !memcmp (next->name, name, len)) + 80428c8: e0bfff17 ldw r2,-4(fp) + 80428cc: 10800217 ldw r2,8(r2) + 80428d0: e0fffe17 ldw r3,-8(fp) + 80428d4: 180d883a mov r6,r3 + 80428d8: e17ffd17 ldw r5,-12(fp) + 80428dc: 1009883a mov r4,r2 + 80428e0: 8042cb80 call 8042cb8 + if (((name[len] == '/') || (name[len] == '\0')) && + 80428e4: 1000021e bne r2,zero,80428f0 + { + /* match found */ + + return next; + 80428e8: e0bfff17 ldw r2,-4(fp) + 80428ec: 00000706 br 804290c + } + next = (alt_dev*) next->llist.next; + 80428f0: e0bfff17 ldw r2,-4(fp) + 80428f4: 10800017 ldw r2,0(r2) + 80428f8: e0bfff15 stw r2,-4(fp) + while (next != (alt_dev*) &alt_fs_list) + 80428fc: e0ffff17 ldw r3,-4(fp) + 8042900: d0a02204 addi r2,gp,-32632 + 8042904: 18bfcc1e bne r3,r2,8042838 + } + + /* No match found */ + + return NULL; + 8042908: 0005883a mov r2,zero +} + 804290c: e037883a mov sp,fp + 8042910: dfc00117 ldw ra,4(sp) + 8042914: df000017 ldw fp,0(sp) + 8042918: dec00204 addi sp,sp,8 + 804291c: f800283a ret + +08042920 : + * the offset of the file descriptor within the file descriptor array). A + * negative value indicates failure. + */ + +int alt_get_fd (alt_dev* dev) +{ + 8042920: defff904 addi sp,sp,-28 + 8042924: dfc00615 stw ra,24(sp) + 8042928: df000515 stw fp,20(sp) + 804292c: df000504 addi fp,sp,20 + 8042930: e13ffb15 stw r4,-20(fp) + alt_32 i; + int rc = -EMFILE; + 8042934: 00bffa04 movi r2,-24 + 8042938: e0bffe15 stw r2,-8(fp) + /* + * Take the alt_fd_list_lock semaphore in order to avoid races when + * accessing the file descriptor pool. + */ + + ALT_SEM_PEND(alt_fd_list_lock, 0); + 804293c: d0a08b17 ldw r2,-32212(gp) + 8042940: e0bffd15 stw r2,-12(fp) + 8042944: e03ffc8d sth zero,-14(fp) + OSSemPend (sem, timeout, &err); + 8042948: e0bffc8b ldhu r2,-14(fp) + 804294c: e0fffc44 addi r3,fp,-15 + 8042950: 180d883a mov r6,r3 + 8042954: 100b883a mov r5,r2 + 8042958: e13ffd17 ldw r4,-12(fp) + 804295c: 8015a600 call 8015a60 + * indicates the highest file descriptor ever allocated. This is used to + * improve efficency when searching the file descriptor list, and + * therefore reduce contention on the alt_fd_list_lock semaphore. + */ + + for (i = 0; i < ALT_MAX_FD; i++) + 8042960: e03fff15 stw zero,-4(fp) + 8042964: 00001706 br 80429c4 + { + if (!alt_fd_list[i].dev) + 8042968: e0bfff17 ldw r2,-4(fp) + 804296c: 10c00324 muli r3,r2,12 + 8042970: 00820174 movhi r2,2053 + 8042974: 1885883a add r2,r3,r2 + 8042978: 10b21a17 ldw r2,-14232(r2) + 804297c: 10000e1e bne r2,zero,80429b8 + { + alt_fd_list[i].dev = dev; + 8042980: e0bfff17 ldw r2,-4(fp) + 8042984: 11000324 muli r4,r2,12 + 8042988: e0fffb17 ldw r3,-20(fp) + 804298c: 00820174 movhi r2,2053 + 8042990: 2085883a add r2,r4,r2 + 8042994: 10f21a15 stw r3,-14232(r2) + if (i > alt_max_fd) + 8042998: d0e02617 ldw r3,-32616(gp) + 804299c: e0bfff17 ldw r2,-4(fp) + 80429a0: 1880020e bge r3,r2,80429ac + { + alt_max_fd = i; + 80429a4: e0bfff17 ldw r2,-4(fp) + 80429a8: d0a02615 stw r2,-32616(gp) + } + rc = i; + 80429ac: e0bfff17 ldw r2,-4(fp) + 80429b0: e0bffe15 stw r2,-8(fp) + goto alt_get_fd_exit; + 80429b4: 00000706 br 80429d4 + for (i = 0; i < ALT_MAX_FD; i++) + 80429b8: e0bfff17 ldw r2,-4(fp) + 80429bc: 10800044 addi r2,r2,1 + 80429c0: e0bfff15 stw r2,-4(fp) + 80429c4: e0bfff17 ldw r2,-4(fp) + 80429c8: 10800410 cmplti r2,r2,16 + 80429cc: 103fe61e bne r2,zero,8042968 + } + } + + alt_get_fd_exit: + 80429d0: 0001883a nop + /* + * Release the alt_fd_list_lock semaphore now that we are done with the + * file descriptor pool. + */ + + ALT_SEM_POST(alt_fd_list_lock); + 80429d4: d0a08b17 ldw r2,-32212(gp) + 80429d8: 1009883a mov r4,r2 + 80429dc: 8015d840 call 8015d84 + + return rc; + 80429e0: e0bffe17 ldw r2,-8(fp) +} + 80429e4: e037883a mov sp,fp + 80429e8: dfc00117 ldw ra,4(sp) + 80429ec: df000017 ldw fp,0(sp) + 80429f0: dec00204 addi sp,sp,8 + 80429f4: f800283a ret + +080429f8 : + * Return: 1: BADADDR (bad_addr argument to handler) is valid + * 0: BADADDR is not valid + */ +int +alt_exception_cause_generated_bad_addr(alt_exception_cause cause) +{ + 80429f8: defffe04 addi sp,sp,-8 + 80429fc: df000115 stw fp,4(sp) + 8042a00: df000104 addi fp,sp,4 + 8042a04: e13fff15 stw r4,-4(fp) + switch (cause) { + 8042a08: e0bfff17 ldw r2,-4(fp) + 8042a0c: 10bffe84 addi r2,r2,-6 + 8042a10: 10c00428 cmpgeui r3,r2,16 + 8042a14: 1800191e bne r3,zero,8042a7c + 8042a18: 100690ba slli r3,r2,2 + 8042a1c: 00820134 movhi r2,2052 + 8042a20: 1885883a add r2,r3,r2 + 8042a24: 108a8b17 ldw r2,10796(r2) + 8042a28: 1000683a jmp r2 + 8042a2c: 08042a6c andhi zero,at,4265 + 8042a30: 08042a6c andhi zero,at,4265 + 8042a34: 08042a7c xorhi zero,at,4265 + 8042a38: 08042a7c xorhi zero,at,4265 + 8042a3c: 08042a7c xorhi zero,at,4265 + 8042a40: 08042a6c andhi zero,at,4265 + 8042a44: 08042a74 orhi zero,at,4265 + 8042a48: 08042a7c xorhi zero,at,4265 + 8042a4c: 08042a6c andhi zero,at,4265 + 8042a50: 08042a6c andhi zero,at,4265 + 8042a54: 08042a7c xorhi zero,at,4265 + 8042a58: 08042a6c andhi zero,at,4265 + 8042a5c: 08042a74 orhi zero,at,4265 + 8042a60: 08042a7c xorhi zero,at,4265 + 8042a64: 08042a7c xorhi zero,at,4265 + 8042a68: 08042a6c andhi zero,at,4265 + case NIOS2_EXCEPTION_MISALIGNED_TARGET_PC: + case NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION: + case NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION: + case NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION: + case NIOS2_EXCEPTION_ECC_DATA_ERR: + return 1; + 8042a6c: 00800044 movi r2,1 + 8042a70: 00000306 br 8042a80 + + case NIOS2_EXCEPTION_TLB_MISS: + case NIOS2_EXCEPTION_ECC_TLB_ERR: + return 0; + 8042a74: 0005883a mov r2,zero + 8042a78: 00000106 br 8042a80 + + default: + return 0; + 8042a7c: 0005883a mov r2,zero + } +} + 8042a80: e037883a mov sp,fp + 8042a84: df000017 ldw fp,0(sp) + 8042a88: dec00104 addi sp,sp,4 + 8042a8c: f800283a ret + +08042a90 : + 8042a90: 200b883a mov r5,r4 + 8042a94: 000f883a mov r7,zero + 8042a98: 000d883a mov r6,zero + 8042a9c: 0009883a mov r4,zero + 8042aa0: 80454e81 jmpi 80454e8 <__register_exitproc> + +08042aa4 : + 8042aa4: 01800284 movi r6,10 + 8042aa8: 000b883a mov r5,zero + 8042aac: 80433281 jmpi 8043328 + +08042ab0 <_atoi_r>: + 8042ab0: 01c00284 movi r7,10 + 8042ab4: 000d883a mov r6,zero + 8042ab8: 804330c1 jmpi 804330c <_strtol_r> + +08042abc : + 8042abc: defffe04 addi sp,sp,-8 + 8042ac0: 000b883a mov r5,zero + 8042ac4: dc000015 stw r16,0(sp) + 8042ac8: dfc00115 stw ra,4(sp) + 8042acc: 2021883a mov r16,r4 + 8042ad0: 80455780 call 8045578 <__call_exitprocs> + 8042ad4: 00820174 movhi r2,2053 + 8042ad8: 1132ae17 ldw r4,-13640(r2) + 8042adc: 20800f17 ldw r2,60(r4) + 8042ae0: 10000126 beq r2,zero,8042ae8 + 8042ae4: 103ee83a callr r2 + 8042ae8: 8009883a mov r4,r16 + 8042aec: 80469740 call 8046974 <_exit> + +08042af0 : + 8042af0: 00820174 movhi r2,2053 + 8042af4: 280d883a mov r6,r5 + 8042af8: 200b883a mov r5,r4 + 8042afc: 1132af17 ldw r4,-13636(r2) + 8042b00: 8042b041 jmpi 8042b04 <_memalign_r> + +08042b04 <_memalign_r>: + 8042b04: 28800268 cmpgeui r2,r5,9 + 8042b08: 10005226 beq r2,zero,8042c54 <_memalign_r+0x150> + 8042b0c: defffa04 addi sp,sp,-24 + 8042b10: dc400115 stw r17,4(sp) + 8042b14: 344002c4 addi r17,r6,11 + 8042b18: dcc00315 stw r19,12(sp) + 8042b1c: dfc00515 stw ra,20(sp) + 8042b20: dd000415 stw r20,16(sp) + 8042b24: dc800215 stw r18,8(sp) + 8042b28: dc000015 stw r16,0(sp) + 8042b2c: 888005f0 cmpltui r2,r17,23 + 8042b30: 2027883a mov r19,r4 + 8042b34: 1000391e bne r2,zero,8042c1c <_memalign_r+0x118> + 8042b38: 00bffe04 movi r2,-8 + 8042b3c: 88a2703a and r17,r17,r2 + 8042b40: 88003816 blt r17,zero,8042c24 <_memalign_r+0x120> + 8042b44: 89803736 bltu r17,r6,8042c24 <_memalign_r+0x120> + 8042b48: 28800428 cmpgeui r2,r5,16 + 8042b4c: 2821883a mov r16,r5 + 8042b50: 1000011e bne r2,zero,8042b58 <_memalign_r+0x54> + 8042b54: 04000404 movi r16,16 + 8042b58: 81400404 addi r5,r16,16 + 8042b5c: 2c4b883a add r5,r5,r17 + 8042b60: 9809883a mov r4,r19 + 8042b64: 8007ddc0 call 8007ddc <_malloc_r> + 8042b68: 1025883a mov r18,r2 + 8042b6c: 10003026 beq r2,zero,8042c30 <_memalign_r+0x12c> + 8042b70: 9809883a mov r4,r19 + 8042b74: 800fe0c0 call 800fe0c <__malloc_lock> + 8042b78: 800b883a mov r5,r16 + 8042b7c: 9009883a mov r4,r18 + 8042b80: 953ffe04 addi r20,r18,-8 + 8042b84: 800d05c0 call 800d05c <__umodsi3> + 8042b88: 10001b26 beq r2,zero,8042bf8 <_memalign_r+0xf4> + 8042b8c: 817fffc4 addi r5,r16,-1 + 8042b90: 0405c83a sub r2,zero,r16 + 8042b94: 914b883a add r5,r18,r5 + 8042b98: 288a703a and r5,r5,r2 + 8042b9c: 297ffe04 addi r5,r5,-8 + 8042ba0: 2d07c83a sub r3,r5,r20 + 8042ba4: 18800408 cmpgei r2,r3,16 + 8042ba8: 10002c26 beq r2,zero,8042c5c <_memalign_r+0x158> + 8042bac: 2829883a mov r20,r5 + 8042bb0: 90bfff17 ldw r2,-4(r18) + 8042bb4: 013fff04 movi r4,-4 + 8042bb8: 900b883a mov r5,r18 + 8042bbc: 1104703a and r2,r2,r4 + 8042bc0: 10c5c83a sub r2,r2,r3 + 8042bc4: 11000054 ori r4,r2,1 + 8042bc8: a1000115 stw r4,4(r20) + 8042bcc: a085883a add r2,r20,r2 + 8042bd0: 11800117 ldw r6,4(r2) + 8042bd4: 9809883a mov r4,r19 + 8042bd8: 31800054 ori r6,r6,1 + 8042bdc: 11800115 stw r6,4(r2) + 8042be0: 90bfff17 ldw r2,-4(r18) + 8042be4: 1080004c andi r2,r2,1 + 8042be8: 10c4b03a or r2,r2,r3 + 8042bec: 90bfff15 stw r2,-4(r18) + 8042bf0: 80071c40 call 80071c4 <_free_r> + 8042bf4: a4800204 addi r18,r20,8 + 8042bf8: a0800117 ldw r2,4(r20) + 8042bfc: 00ffff04 movi r3,-4 + 8042c00: 10c4703a and r2,r2,r3 + 8042c04: 1445c83a sub r2,r2,r17 + 8042c08: 10c00410 cmplti r3,r2,16 + 8042c0c: 18001726 beq r3,zero,8042c6c <_memalign_r+0x168> + 8042c10: 9809883a mov r4,r19 + 8042c14: 800ff2c0 call 800ff2c <__malloc_unlock> + 8042c18: 00000506 br 8042c30 <_memalign_r+0x12c> + 8042c1c: 04400404 movi r17,16 + 8042c20: 89bfc92e bgeu r17,r6,8042b48 <_memalign_r+0x44> + 8042c24: 00800304 movi r2,12 + 8042c28: 98800015 stw r2,0(r19) + 8042c2c: 0025883a mov r18,zero + 8042c30: 9005883a mov r2,r18 + 8042c34: dfc00517 ldw ra,20(sp) + 8042c38: dd000417 ldw r20,16(sp) + 8042c3c: dcc00317 ldw r19,12(sp) + 8042c40: dc800217 ldw r18,8(sp) + 8042c44: dc400117 ldw r17,4(sp) + 8042c48: dc000017 ldw r16,0(sp) + 8042c4c: dec00604 addi sp,sp,24 + 8042c50: f800283a ret + 8042c54: 300b883a mov r5,r6 + 8042c58: 8007ddc1 jmpi 8007ddc <_malloc_r> + 8042c5c: 2c0b883a add r5,r5,r16 + 8042c60: 2d07c83a sub r3,r5,r20 + 8042c64: 2829883a mov r20,r5 + 8042c68: 003fd106 br 8042bb0 <_memalign_r+0xac> + 8042c6c: a44b883a add r5,r20,r17 + 8042c70: 10800054 ori r2,r2,1 + 8042c74: 28800115 stw r2,4(r5) + 8042c78: a0800117 ldw r2,4(r20) + 8042c7c: 29400204 addi r5,r5,8 + 8042c80: 9809883a mov r4,r19 + 8042c84: 1080004c andi r2,r2,1 + 8042c88: 1462b03a or r17,r2,r17 + 8042c8c: a4400115 stw r17,4(r20) + 8042c90: 80071c40 call 80071c4 <_free_r> + 8042c94: 003fde06 br 8042c10 <_memalign_r+0x10c> + +08042c98 : + 8042c98: 00820174 movhi r2,2053 + 8042c9c: 200b883a mov r5,r4 + 8042ca0: 1132af17 ldw r4,-13636(r2) + 8042ca4: 8007ddc1 jmpi 8007ddc <_malloc_r> + +08042ca8 : + 8042ca8: 00820174 movhi r2,2053 + 8042cac: 200b883a mov r5,r4 + 8042cb0: 1132af17 ldw r4,-13636(r2) + 8042cb4: 80071c41 jmpi 80071c4 <_free_r> + +08042cb8 : + 8042cb8: 30800130 cmpltui r2,r6,4 + 8042cbc: 10000b1e bne r2,zero,8042cec + 8042cc0: 2144b03a or r2,r4,r5 + 8042cc4: 108000cc andi r2,r2,3 + 8042cc8: 10001a1e bne r2,zero,8042d34 + 8042ccc: 20c00017 ldw r3,0(r4) + 8042cd0: 28800017 ldw r2,0(r5) + 8042cd4: 1880171e bne r3,r2,8042d34 + 8042cd8: 31bfff04 addi r6,r6,-4 + 8042cdc: 30800128 cmpgeui r2,r6,4 + 8042ce0: 21000104 addi r4,r4,4 + 8042ce4: 29400104 addi r5,r5,4 + 8042ce8: 103ff81e bne r2,zero,8042ccc + 8042cec: 30ffffc4 addi r3,r6,-1 + 8042cf0: 30000e26 beq r6,zero,8042d2c + 8042cf4: 29800003 ldbu r6,0(r5) + 8042cf8: 20800003 ldbu r2,0(r4) + 8042cfc: 30800f1e bne r6,r2,8042d3c + 8042d00: 18800044 addi r2,r3,1 + 8042d04: 20c00044 addi r3,r4,1 + 8042d08: 2089883a add r4,r4,r2 + 8042d0c: 00000506 br 8042d24 + 8042d10: 18800003 ldbu r2,0(r3) + 8042d14: 29800003 ldbu r6,0(r5) + 8042d18: 18c00044 addi r3,r3,1 + 8042d1c: 10803fcc andi r2,r2,255 + 8042d20: 1180061e bne r2,r6,8042d3c + 8042d24: 29400044 addi r5,r5,1 + 8042d28: 193ff91e bne r3,r4,8042d10 + 8042d2c: 0005883a mov r2,zero + 8042d30: f800283a ret + 8042d34: 30ffffc4 addi r3,r6,-1 + 8042d38: 003fee06 br 8042cf4 + 8042d3c: 1185c83a sub r2,r2,r6 + 8042d40: f800283a ret + +08042d44 <_sprintf_r>: + 8042d44: deffe404 addi sp,sp,-112 + 8042d48: 2811883a mov r8,r5 + 8042d4c: dfc01a15 stw ra,104(sp) + 8042d50: d9c01b15 stw r7,108(sp) + 8042d54: 00a00034 movhi r2,32768 + 8042d58: 00fffff4 movhi r3,65535 + 8042d5c: 10bfffc4 addi r2,r2,-1 + 8042d60: 18c08204 addi r3,r3,520 + 8042d64: d9c01b04 addi r7,sp,108 + 8042d68: d80b883a mov r5,sp + 8042d6c: d8c00315 stw r3,12(sp) + 8042d70: da000015 stw r8,0(sp) + 8042d74: da000415 stw r8,16(sp) + 8042d78: d8800515 stw r2,20(sp) + 8042d7c: d8800215 stw r2,8(sp) + 8042d80: 80433400 call 8043340 <___svfprintf_internal_r> + 8042d84: d8c00017 ldw r3,0(sp) + 8042d88: 18000005 stb zero,0(r3) + 8042d8c: dfc01a17 ldw ra,104(sp) + 8042d90: dec01c04 addi sp,sp,112 + 8042d94: f800283a ret + +08042d98 : + 8042d98: deffe304 addi sp,sp,-116 + 8042d9c: 2011883a mov r8,r4 + 8042da0: dfc01a15 stw ra,104(sp) + 8042da4: d9801b15 stw r6,108(sp) + 8042da8: d9c01c15 stw r7,112(sp) + 8042dac: 00820174 movhi r2,2053 + 8042db0: 1132af17 ldw r4,-13636(r2) + 8042db4: 00fffff4 movhi r3,65535 + 8042db8: 00a00034 movhi r2,32768 + 8042dbc: 10bfffc4 addi r2,r2,-1 + 8042dc0: 18c08204 addi r3,r3,520 + 8042dc4: 280d883a mov r6,r5 + 8042dc8: d9c01b04 addi r7,sp,108 + 8042dcc: d80b883a mov r5,sp + 8042dd0: d8c00315 stw r3,12(sp) + 8042dd4: da000015 stw r8,0(sp) + 8042dd8: da000415 stw r8,16(sp) + 8042ddc: d8800515 stw r2,20(sp) + 8042de0: d8800215 stw r2,8(sp) + 8042de4: 80433400 call 8043340 <___svfprintf_internal_r> + 8042de8: d8c00017 ldw r3,0(sp) + 8042dec: 18000005 stb zero,0(r3) + 8042df0: dfc01a17 ldw ra,104(sp) + 8042df4: dec01d04 addi sp,sp,116 + 8042df8: f800283a ret + +08042dfc : + 8042dfc: 2a403fcc andi r9,r5,255 + 8042e00: 2811883a mov r8,r5 + 8042e04: 208000cc andi r2,r4,3 + 8042e08: 48003726 beq r9,zero,8042ee8 + 8042e0c: 10000b26 beq r2,zero,8042e3c + 8042e10: 20800003 ldbu r2,0(r4) + 8042e14: 10003226 beq r2,zero,8042ee0 + 8042e18: 48804f26 beq r9,r2,8042f58 + 8042e1c: 4807883a mov r3,r9 + 8042e20: 00000306 br 8042e30 + 8042e24: 20800003 ldbu r2,0(r4) + 8042e28: 10002d26 beq r2,zero,8042ee0 + 8042e2c: 10c04a26 beq r2,r3,8042f58 + 8042e30: 21000044 addi r4,r4,1 + 8042e34: 208000cc andi r2,r4,3 + 8042e38: 103ffa1e bne r2,zero,8042e24 + 8042e3c: 29403fcc andi r5,r5,255 + 8042e40: 2804923a slli r2,r5,8 + 8042e44: 20c00017 ldw r3,0(r4) + 8042e48: 01ffbff4 movhi r7,65279 + 8042e4c: 288ab03a or r5,r5,r2 + 8042e50: 2816943a slli r11,r5,16 + 8042e54: 39ffbfc4 addi r7,r7,-257 + 8042e58: 19c5883a add r2,r3,r7 + 8042e5c: 5956b03a or r11,r11,r5 + 8042e60: 58caf03a xor r5,r11,r3 + 8042e64: 29cd883a add r6,r5,r7 + 8042e68: 00c6303a nor r3,zero,r3 + 8042e6c: 014a303a nor r5,zero,r5 + 8042e70: 10c4703a and r2,r2,r3 + 8042e74: 314a703a and r5,r6,r5 + 8042e78: 02a02074 movhi r10,32897 + 8042e7c: 1144b03a or r2,r2,r5 + 8042e80: 52a02004 addi r10,r10,-32640 + 8042e84: 1284703a and r2,r2,r10 + 8042e88: 10000c1e bne r2,zero,8042ebc + 8042e8c: 21000104 addi r4,r4,4 + 8042e90: 20c00017 ldw r3,0(r4) + 8042e94: 1acaf03a xor r5,r3,r11 + 8042e98: 19c5883a add r2,r3,r7 + 8042e9c: 29cd883a add r6,r5,r7 + 8042ea0: 00c6303a nor r3,zero,r3 + 8042ea4: 014a303a nor r5,zero,r5 + 8042ea8: 10c4703a and r2,r2,r3 + 8042eac: 314a703a and r5,r6,r5 + 8042eb0: 1144b03a or r2,r2,r5 + 8042eb4: 1284703a and r2,r2,r10 + 8042eb8: 103ff426 beq r2,zero,8042e8c + 8042ebc: 20800003 ldbu r2,0(r4) + 8042ec0: 10000726 beq r2,zero,8042ee0 + 8042ec4: 48802426 beq r9,r2,8042f58 + 8042ec8: 42003fcc andi r8,r8,255 + 8042ecc: 00000106 br 8042ed4 + 8042ed0: 12002126 beq r2,r8,8042f58 + 8042ed4: 21000044 addi r4,r4,1 + 8042ed8: 20800003 ldbu r2,0(r4) + 8042edc: 103ffc1e bne r2,zero,8042ed0 + 8042ee0: 0005883a mov r2,zero + 8042ee4: f800283a ret + 8042ee8: 10000526 beq r2,zero,8042f00 + 8042eec: 20800003 ldbu r2,0(r4) + 8042ef0: 10001926 beq r2,zero,8042f58 + 8042ef4: 21000044 addi r4,r4,1 + 8042ef8: 208000cc andi r2,r4,3 + 8042efc: 103ffb1e bne r2,zero,8042eec + 8042f00: 20c00017 ldw r3,0(r4) + 8042f04: 01bfbff4 movhi r6,65279 + 8042f08: 31bfbfc4 addi r6,r6,-257 + 8042f0c: 1985883a add r2,r3,r6 + 8042f10: 01602074 movhi r5,32897 + 8042f14: 00c6303a nor r3,zero,r3 + 8042f18: 10c4703a and r2,r2,r3 + 8042f1c: 29602004 addi r5,r5,-32640 + 8042f20: 1144703a and r2,r2,r5 + 8042f24: 1000071e bne r2,zero,8042f44 + 8042f28: 21000104 addi r4,r4,4 + 8042f2c: 20c00017 ldw r3,0(r4) + 8042f30: 1985883a add r2,r3,r6 + 8042f34: 00c6303a nor r3,zero,r3 + 8042f38: 10c4703a and r2,r2,r3 + 8042f3c: 1144703a and r2,r2,r5 + 8042f40: 103ff926 beq r2,zero,8042f28 + 8042f44: 20800003 ldbu r2,0(r4) + 8042f48: 10000326 beq r2,zero,8042f58 + 8042f4c: 21000044 addi r4,r4,1 + 8042f50: 20800003 ldbu r2,0(r4) + 8042f54: 103ffd1e bne r2,zero,8042f4c + 8042f58: 2005883a mov r2,r4 + 8042f5c: f800283a ret + +08042f60 : + 8042f60: 2906b03a or r3,r5,r4 + 8042f64: 18c000cc andi r3,r3,3 + 8042f68: 2005883a mov r2,r4 + 8042f6c: 18001d1e bne r3,zero,8042fe4 + 8042f70: 29c00017 ldw r7,0(r5) + 8042f74: 02bfbff4 movhi r10,65279 + 8042f78: 52bfbfc4 addi r10,r10,-257 + 8042f7c: 3a87883a add r3,r7,r10 + 8042f80: 01c8303a nor r4,zero,r7 + 8042f84: 02602074 movhi r9,32897 + 8042f88: 1906703a and r3,r3,r4 + 8042f8c: 4a602004 addi r9,r9,-32640 + 8042f90: 1a46703a and r3,r3,r9 + 8042f94: 100d883a mov r6,r2 + 8042f98: 1800091e bne r3,zero,8042fc0 + 8042f9c: 31800104 addi r6,r6,4 + 8042fa0: 29400104 addi r5,r5,4 + 8042fa4: 31ffff15 stw r7,-4(r6) + 8042fa8: 29c00017 ldw r7,0(r5) + 8042fac: 3a87883a add r3,r7,r10 + 8042fb0: 01d0303a nor r8,zero,r7 + 8042fb4: 1a06703a and r3,r3,r8 + 8042fb8: 1a46703a and r3,r3,r9 + 8042fbc: 183ff726 beq r3,zero,8042f9c + 8042fc0: 29400044 addi r5,r5,1 + 8042fc4: 28ffffc3 ldbu r3,-1(r5) + 8042fc8: 31800044 addi r6,r6,1 + 8042fcc: 30ffffc5 stb r3,-1(r6) + 8042fd0: 18c03fcc andi r3,r3,255 + 8042fd4: 18c0201c xori r3,r3,128 + 8042fd8: 18ffe004 addi r3,r3,-128 + 8042fdc: 183ff81e bne r3,zero,8042fc0 + 8042fe0: f800283a ret + 8042fe4: 200d883a mov r6,r4 + 8042fe8: 003ff506 br 8042fc0 + +08042fec : + 8042fec: 30003726 beq r6,zero,80430cc + 8042ff0: 2144b03a or r2,r4,r5 + 8042ff4: 108000cc andi r2,r2,3 + 8042ff8: 10001f1e bne r2,zero,8043078 + 8042ffc: 30800130 cmpltui r2,r6,4 + 8043000: 10001d1e bne r2,zero,8043078 + 8043004: 20800017 ldw r2,0(r4) + 8043008: 28c00017 ldw r3,0(r5) + 804300c: 10c0311e bne r2,r3,80430d4 + 8043010: 31bfff04 addi r6,r6,-4 + 8043014: 30002d26 beq r6,zero,80430cc + 8043018: 02bfbff4 movhi r10,65279 + 804301c: 52bfbfc4 addi r10,r10,-257 + 8043020: 1287883a add r3,r2,r10 + 8043024: 02602074 movhi r9,32897 + 8043028: 0084303a nor r2,zero,r2 + 804302c: 1884703a and r2,r3,r2 + 8043030: 4a602004 addi r9,r9,-32640 + 8043034: 1244703a and r2,r2,r9 + 8043038: 10000b26 beq r2,zero,8043068 + 804303c: 00002306 br 80430cc + 8043040: 20c00017 ldw r3,0(r4) + 8043044: 29c00017 ldw r7,0(r5) + 8043048: 1a85883a add r2,r3,r10 + 804304c: 00d0303a nor r8,zero,r3 + 8043050: 1204703a and r2,r2,r8 + 8043054: 1244703a and r2,r2,r9 + 8043058: 19c01e1e bne r3,r7,80430d4 + 804305c: 31bfff04 addi r6,r6,-4 + 8043060: 30001a26 beq r6,zero,80430cc + 8043064: 1000191e bne r2,zero,80430cc + 8043068: 30800130 cmpltui r2,r6,4 + 804306c: 21000104 addi r4,r4,4 + 8043070: 29400104 addi r5,r5,4 + 8043074: 103ff226 beq r2,zero,8043040 + 8043078: 20800007 ldb r2,0(r4) + 804307c: 28c00007 ldb r3,0(r5) + 8043080: 31bfffc4 addi r6,r6,-1 + 8043084: 10c00d1e bne r2,r3,80430bc + 8043088: 30001026 beq r6,zero,80430cc + 804308c: 10000f26 beq r2,zero,80430cc + 8043090: 20800044 addi r2,r4,1 + 8043094: 218d883a add r6,r4,r6 + 8043098: 00000306 br 80430a8 + 804309c: 11800b26 beq r2,r6,80430cc + 80430a0: 10800044 addi r2,r2,1 + 80430a4: 18000926 beq r3,zero,80430cc + 80430a8: 29400044 addi r5,r5,1 + 80430ac: 10c00007 ldb r3,0(r2) + 80430b0: 29c00007 ldb r7,0(r5) + 80430b4: 1009883a mov r4,r2 + 80430b8: 19fff826 beq r3,r7,804309c + 80430bc: 20800003 ldbu r2,0(r4) + 80430c0: 28c00003 ldbu r3,0(r5) + 80430c4: 10c5c83a sub r2,r2,r3 + 80430c8: f800283a ret + 80430cc: 0005883a mov r2,zero + 80430d0: f800283a ret + 80430d4: 28c00007 ldb r3,0(r5) + 80430d8: 20800007 ldb r2,0(r4) + 80430dc: 31bfffc4 addi r6,r6,-1 + 80430e0: 18bfea26 beq r3,r2,804308c + 80430e4: 003ff506 br 80430bc + +080430e8 <_strtol_l.isra.0>: + 80430e8: defff504 addi sp,sp,-44 + 80430ec: dd400615 stw r21,24(sp) + 80430f0: dd000515 stw r20,20(sp) + 80430f4: dcc00415 stw r19,16(sp) + 80430f8: d9000015 stw r4,0(sp) + 80430fc: dfc00a15 stw ra,40(sp) + 8043100: df000915 stw fp,36(sp) + 8043104: ddc00815 stw r23,32(sp) + 8043108: dd800715 stw r22,28(sp) + 804310c: dc800315 stw r18,12(sp) + 8043110: dc400215 stw r17,8(sp) + 8043114: dc000115 stw r16,4(sp) + 8043118: 2827883a mov r19,r5 + 804311c: 3029883a mov r20,r6 + 8043120: 382b883a mov r21,r7 + 8043124: 2809883a mov r4,r5 + 8043128: 00000106 br 8043130 <_strtol_l.isra.0+0x48> + 804312c: 8009883a mov r4,r16 + 8043130: 24000044 addi r16,r4,1 + 8043134: 80ffffc3 ldbu r3,-1(r16) + 8043138: 00820134 movhi r2,2052 + 804313c: 1885883a add r2,r3,r2 + 8043140: 109c75c3 ldbu r2,29143(r2) + 8043144: 1080020c andi r2,r2,8 + 8043148: 103ff81e bne r2,zero,804312c <_strtol_l.isra.0+0x44> + 804314c: 18800b58 cmpnei r2,r3,45 + 8043150: 10005226 beq r2,zero,804329c <_strtol_l.isra.0+0x1b4> + 8043154: 18800ae0 cmpeqi r2,r3,43 + 8043158: 1000251e bne r2,zero,80431f0 <_strtol_l.isra.0+0x108> + 804315c: 1823883a mov r17,r3 + 8043160: 0039883a mov fp,zero + 8043164: a8002626 beq r21,zero,8043200 <_strtol_l.isra.0+0x118> + 8043168: a8800420 cmpeqi r2,r21,16 + 804316c: 10004f1e bne r2,zero,80432ac <_strtol_l.isra.0+0x1c4> + 8043170: a82d883a mov r22,r21 + 8043174: 05e00034 movhi r23,32768 + 8043178: e000011e bne fp,zero,8043180 <_strtol_l.isra.0+0x98> + 804317c: bdffffc4 addi r23,r23,-1 + 8043180: b00b883a mov r5,r22 + 8043184: b809883a mov r4,r23 + 8043188: 800d05c0 call 800d05c <__umodsi3> + 804318c: b00b883a mov r5,r22 + 8043190: b809883a mov r4,r23 + 8043194: 1025883a mov r18,r2 + 8043198: 800cff80 call 800cff8 <__udivsi3> + 804319c: 100f883a mov r7,r2 + 80431a0: 000b883a mov r5,zero + 80431a4: 0005883a mov r2,zero + 80431a8: 88fff404 addi r3,r17,-48 + 80431ac: 190002a8 cmpgeui r4,r3,10 + 80431b0: 20000426 beq r4,zero,80431c4 <_strtol_l.isra.0+0xdc> + 80431b4: 88ffefc4 addi r3,r17,-65 + 80431b8: 18c006a8 cmpgeui r3,r3,26 + 80431bc: 1800181e bne r3,zero,8043220 <_strtol_l.isra.0+0x138> + 80431c0: 88fff244 addi r3,r17,-55 + 80431c4: 1d401b0e bge r3,r21,8043234 <_strtol_l.isra.0+0x14c> + 80431c8: 293fffe0 cmpeqi r4,r5,-1 + 80431cc: 2000051e bne r4,zero,80431e4 <_strtol_l.isra.0+0xfc> + 80431d0: 38801136 bltu r7,r2,8043218 <_strtol_l.isra.0+0x130> + 80431d4: 38800f26 beq r7,r2,8043214 <_strtol_l.isra.0+0x12c> + 80431d8: b089383a mul r4,r22,r2 + 80431dc: 01400044 movi r5,1 + 80431e0: 1905883a add r2,r3,r4 + 80431e4: 84000044 addi r16,r16,1 + 80431e8: 847fffc3 ldbu r17,-1(r16) + 80431ec: 003fee06 br 80431a8 <_strtol_l.isra.0+0xc0> + 80431f0: 84400003 ldbu r17,0(r16) + 80431f4: 0039883a mov fp,zero + 80431f8: 24000084 addi r16,r4,2 + 80431fc: a83fda1e bne r21,zero,8043168 <_strtol_l.isra.0+0x80> + 8043200: 88800c20 cmpeqi r2,r17,48 + 8043204: 1000361e bne r2,zero,80432e0 <_strtol_l.isra.0+0x1f8> + 8043208: 05800284 movi r22,10 + 804320c: 05400284 movi r21,10 + 8043210: 003fd806 br 8043174 <_strtol_l.isra.0+0x8c> + 8043214: 90fff00e bge r18,r3,80431d8 <_strtol_l.isra.0+0xf0> + 8043218: 017fffc4 movi r5,-1 + 804321c: 003ff106 br 80431e4 <_strtol_l.isra.0+0xfc> + 8043220: 88ffe7c4 addi r3,r17,-97 + 8043224: 18c006a8 cmpgeui r3,r3,26 + 8043228: 1800021e bne r3,zero,8043234 <_strtol_l.isra.0+0x14c> + 804322c: 88ffea44 addi r3,r17,-87 + 8043230: 1d7fe516 blt r3,r21,80431c8 <_strtol_l.isra.0+0xe0> + 8043234: 28ffffd8 cmpnei r3,r5,-1 + 8043238: 18001126 beq r3,zero,8043280 <_strtol_l.isra.0+0x198> + 804323c: e0000126 beq fp,zero,8043244 <_strtol_l.isra.0+0x15c> + 8043240: 0085c83a sub r2,zero,r2 + 8043244: a0000226 beq r20,zero,8043250 <_strtol_l.isra.0+0x168> + 8043248: 28002e1e bne r5,zero,8043304 <_strtol_l.isra.0+0x21c> + 804324c: a4c00015 stw r19,0(r20) + 8043250: dfc00a17 ldw ra,40(sp) + 8043254: df000917 ldw fp,36(sp) + 8043258: ddc00817 ldw r23,32(sp) + 804325c: dd800717 ldw r22,28(sp) + 8043260: dd400617 ldw r21,24(sp) + 8043264: dd000517 ldw r20,20(sp) + 8043268: dcc00417 ldw r19,16(sp) + 804326c: dc800317 ldw r18,12(sp) + 8043270: dc400217 ldw r17,8(sp) + 8043274: dc000117 ldw r16,4(sp) + 8043278: dec00b04 addi sp,sp,44 + 804327c: f800283a ret + 8043280: d8c00017 ldw r3,0(sp) + 8043284: 00800884 movi r2,34 + 8043288: 18800015 stw r2,0(r3) + 804328c: a0001b26 beq r20,zero,80432fc <_strtol_l.isra.0+0x214> + 8043290: 84ffffc4 addi r19,r16,-1 + 8043294: b805883a mov r2,r23 + 8043298: 003fec06 br 804324c <_strtol_l.isra.0+0x164> + 804329c: 84400003 ldbu r17,0(r16) + 80432a0: 07000044 movi fp,1 + 80432a4: 24000084 addi r16,r4,2 + 80432a8: 003fae06 br 8043164 <_strtol_l.isra.0+0x7c> + 80432ac: 88800c18 cmpnei r2,r17,48 + 80432b0: 1000041e bne r2,zero,80432c4 <_strtol_l.isra.0+0x1dc> + 80432b4: 80800003 ldbu r2,0(r16) + 80432b8: 108037cc andi r2,r2,223 + 80432bc: 10801620 cmpeqi r2,r2,88 + 80432c0: 1000021e bne r2,zero,80432cc <_strtol_l.isra.0+0x1e4> + 80432c4: 05800404 movi r22,16 + 80432c8: 003faa06 br 8043174 <_strtol_l.isra.0+0x8c> + 80432cc: 84400043 ldbu r17,1(r16) + 80432d0: 05800404 movi r22,16 + 80432d4: 84000084 addi r16,r16,2 + 80432d8: 05400404 movi r21,16 + 80432dc: 003fa506 br 8043174 <_strtol_l.isra.0+0x8c> + 80432e0: 80800003 ldbu r2,0(r16) + 80432e4: 108037cc andi r2,r2,223 + 80432e8: 10801620 cmpeqi r2,r2,88 + 80432ec: 103ff71e bne r2,zero,80432cc <_strtol_l.isra.0+0x1e4> + 80432f0: 05800204 movi r22,8 + 80432f4: 05400204 movi r21,8 + 80432f8: 003f9e06 br 8043174 <_strtol_l.isra.0+0x8c> + 80432fc: b805883a mov r2,r23 + 8043300: 003fd306 br 8043250 <_strtol_l.isra.0+0x168> + 8043304: 102f883a mov r23,r2 + 8043308: 003fe106 br 8043290 <_strtol_l.isra.0+0x1a8> + +0804330c <_strtol_r>: + 804330c: 80430e81 jmpi 80430e8 <_strtol_l.isra.0> + +08043310 : + 8043310: 00820174 movhi r2,2053 + 8043314: 300f883a mov r7,r6 + 8043318: 280d883a mov r6,r5 + 804331c: 200b883a mov r5,r4 + 8043320: 1132af17 ldw r4,-13636(r2) + 8043324: 80430e81 jmpi 80430e8 <_strtol_l.isra.0> + +08043328 : + 8043328: 00820174 movhi r2,2053 + 804332c: 300f883a mov r7,r6 + 8043330: 280d883a mov r6,r5 + 8043334: 200b883a mov r5,r4 + 8043338: 1132af17 ldw r4,-13636(r2) + 804333c: 80430e81 jmpi 80430e8 <_strtol_l.isra.0> + +08043340 <___svfprintf_internal_r>: + 8043340: deffbd04 addi sp,sp,-268 + 8043344: dfc04215 stw ra,264(sp) + 8043348: dd403e15 stw r21,248(sp) + 804334c: dcc03c15 stw r19,240(sp) + 8043350: d9000515 stw r4,20(sp) + 8043354: 2827883a mov r19,r5 + 8043358: 302b883a mov r21,r6 + 804335c: d9c00615 stw r7,24(sp) + 8043360: df004115 stw fp,260(sp) + 8043364: ddc04015 stw r23,256(sp) + 8043368: dd803f15 stw r22,252(sp) + 804336c: dd003d15 stw r20,244(sp) + 8043370: dc803b15 stw r18,236(sp) + 8043374: dc403a15 stw r17,232(sp) + 8043378: dc003915 stw r16,228(sp) + 804337c: 8007bf00 call 8007bf0 <_localeconv_r> + 8043380: 10800017 ldw r2,0(r2) + 8043384: 1009883a mov r4,r2 + 8043388: d8800d15 stw r2,52(sp) + 804338c: 8002dac0 call 8002dac + 8043390: d8800b15 stw r2,44(sp) + 8043394: 9880030b ldhu r2,12(r19) + 8043398: 1080200c andi r2,r2,128 + 804339c: 10000226 beq r2,zero,80433a8 <___svfprintf_internal_r+0x68> + 80433a0: 98800417 ldw r2,16(r19) + 80433a4: 10059a26 beq r2,zero,8044a10 <___svfprintf_internal_r+0x16d0> + 80433a8: ddc02904 addi r23,sp,164 + 80433ac: ddc01c15 stw r23,112(sp) + 80433b0: d8001e15 stw zero,120(sp) + 80433b4: d8001d15 stw zero,116(sp) + 80433b8: d8000815 stw zero,32(sp) + 80433bc: d8000915 stw zero,36(sp) + 80433c0: d8000a15 stw zero,40(sp) + 80433c4: b811883a mov r8,r23 + 80433c8: d8000c15 stw zero,48(sp) + 80433cc: d8001115 stw zero,68(sp) + 80433d0: d8000415 stw zero,16(sp) + 80433d4: a82d883a mov r22,r21 + 80433d8: b0800007 ldb r2,0(r22) + 80433dc: 10009126 beq r2,zero,8043624 <___svfprintf_internal_r+0x2e4> + 80433e0: 10800960 cmpeqi r2,r2,37 + 80433e4: 1004f61e bne r2,zero,80447c0 <___svfprintf_internal_r+0x1480> + 80433e8: b021883a mov r16,r22 + 80433ec: 00000206 br 80433f8 <___svfprintf_internal_r+0xb8> + 80433f0: 18008226 beq r3,zero,80435fc <___svfprintf_internal_r+0x2bc> + 80433f4: 9021883a mov r16,r18 + 80433f8: 80800047 ldb r2,1(r16) + 80433fc: 84800044 addi r18,r16,1 + 8043400: 10c00958 cmpnei r3,r2,37 + 8043404: 103ffa1e bne r2,zero,80433f0 <___svfprintf_internal_r+0xb0> + 8043408: 95a3c83a sub r17,r18,r22 + 804340c: 88008526 beq r17,zero,8043624 <___svfprintf_internal_r+0x2e4> + 8043410: d8c01e17 ldw r3,120(sp) + 8043414: d8801d17 ldw r2,116(sp) + 8043418: 45800015 stw r22,0(r8) + 804341c: 1c47883a add r3,r3,r17 + 8043420: 10800044 addi r2,r2,1 + 8043424: d8801d15 stw r2,116(sp) + 8043428: 44400115 stw r17,4(r8) + 804342c: d8c01e15 stw r3,120(sp) + 8043430: 10800208 cmpgei r2,r2,8 + 8043434: 1000741e bne r2,zero,8043608 <___svfprintf_internal_r+0x2c8> + 8043438: 42000204 addi r8,r8,8 + 804343c: d8c00417 ldw r3,16(sp) + 8043440: 80800047 ldb r2,1(r16) + 8043444: 1c47883a add r3,r3,r17 + 8043448: d8c00415 stw r3,16(sp) + 804344c: 10007526 beq r2,zero,8043624 <___svfprintf_internal_r+0x2e4> + 8043450: 92800047 ldb r10,1(r18) + 8043454: 95800044 addi r22,r18,1 + 8043458: d8001545 stb zero,85(sp) + 804345c: 0009883a mov r4,zero + 8043460: 000b883a mov r5,zero + 8043464: 02ffffc4 movi r11,-1 + 8043468: 0023883a mov r17,zero + 804346c: 0019883a mov r12,zero + 8043470: b5800044 addi r22,r22,1 + 8043474: 5039883a mov fp,r10 + 8043478: e0bff804 addi r2,fp,-32 + 804347c: 10c01668 cmpgeui r3,r2,89 + 8043480: 18008a1e bne r3,zero,80436ac <___svfprintf_internal_r+0x36c> + 8043484: 100490ba slli r2,r2,2 + 8043488: 00c20134 movhi r3,2052 + 804348c: 10c7883a add r3,r2,r3 + 8043490: 188d2617 ldw r2,13464(r3) + 8043494: 1000683a jmp r2 + 8043498: 0804377c xorhi zero,at,4317 + 804349c: 080436ac andhi zero,at,4314 + 80434a0: 080436ac andhi zero,at,4314 + 80434a4: 08043770 cmpltui zero,at,4317 + 80434a8: 080436ac andhi zero,at,4314 + 80434ac: 080436ac andhi zero,at,4314 + 80434b0: 080436ac andhi zero,at,4314 + 80434b4: 080436ac andhi zero,at,4314 + 80434b8: 080436ac andhi zero,at,4314 + 80434bc: 080436ac andhi zero,at,4314 + 80434c0: 08043748 cmpgei zero,at,4317 + 80434c4: 08043738 rdprs zero,at,4316 + 80434c8: 080436ac andhi zero,at,4314 + 80434cc: 08043720 cmpeqi zero,at,4316 + 80434d0: 080436dc xori zero,at,4315 + 80434d4: 080436ac andhi zero,at,4314 + 80434d8: 080436d0 cmplti zero,at,4315 + 80434dc: 0804367c xorhi zero,at,4313 + 80434e0: 0804367c xorhi zero,at,4313 + 80434e4: 0804367c xorhi zero,at,4313 + 80434e8: 0804367c xorhi zero,at,4313 + 80434ec: 0804367c xorhi zero,at,4313 + 80434f0: 0804367c xorhi zero,at,4313 + 80434f4: 0804367c xorhi zero,at,4313 + 80434f8: 0804367c xorhi zero,at,4313 + 80434fc: 0804367c xorhi zero,at,4313 + 8043500: 080436ac andhi zero,at,4314 + 8043504: 080436ac andhi zero,at,4314 + 8043508: 080436ac andhi zero,at,4314 + 804350c: 080436ac andhi zero,at,4314 + 8043510: 080436ac andhi zero,at,4314 + 8043514: 080436ac andhi zero,at,4314 + 8043518: 080436ac andhi zero,at,4314 + 804351c: 080436ac andhi zero,at,4314 + 8043520: 080436ac andhi zero,at,4314 + 8043524: 080436ac andhi zero,at,4314 + 8043528: 08043d30 cmpltui zero,at,4340 + 804352c: 08043c50 cmplti zero,at,4337 + 8043530: 080436ac andhi zero,at,4314 + 8043534: 08043c50 cmplti zero,at,4337 + 8043538: 080436ac andhi zero,at,4314 + 804353c: 080436ac andhi zero,at,4314 + 8043540: 080436ac andhi zero,at,4314 + 8043544: 080436ac andhi zero,at,4314 + 8043548: 08043e84 addi zero,at,4346 + 804354c: 080436ac andhi zero,at,4314 + 8043550: 080436ac andhi zero,at,4314 + 8043554: 08043c1c xori zero,at,4336 + 8043558: 080436ac andhi zero,at,4314 + 804355c: 080436ac andhi zero,at,4314 + 8043560: 080436ac andhi zero,at,4314 + 8043564: 080436ac andhi zero,at,4314 + 8043568: 080436ac andhi zero,at,4314 + 804356c: 08043e50 cmplti zero,at,4345 + 8043570: 080436ac andhi zero,at,4314 + 8043574: 080436ac andhi zero,at,4314 + 8043578: 08043e08 cmpgei zero,at,4344 + 804357c: 080436ac andhi zero,at,4314 + 8043580: 080436ac andhi zero,at,4314 + 8043584: 080436ac andhi zero,at,4314 + 8043588: 080436ac andhi zero,at,4314 + 804358c: 080436ac andhi zero,at,4314 + 8043590: 080436ac andhi zero,at,4314 + 8043594: 080436ac andhi zero,at,4314 + 8043598: 080436ac andhi zero,at,4314 + 804359c: 080436ac andhi zero,at,4314 + 80435a0: 080436ac andhi zero,at,4314 + 80435a4: 08043904 addi zero,at,4324 + 80435a8: 08043890 cmplti zero,at,4322 + 80435ac: 08043c50 cmplti zero,at,4337 + 80435b0: 08043c50 cmplti zero,at,4337 + 80435b4: 08043c50 cmplti zero,at,4337 + 80435b8: 08043b88 cmpgei zero,at,4334 + 80435bc: 08043890 cmplti zero,at,4322 + 80435c0: 080436ac andhi zero,at,4314 + 80435c4: 080436ac andhi zero,at,4314 + 80435c8: 08043b74 orhi zero,at,4333 + 80435cc: 080436ac andhi zero,at,4314 + 80435d0: 08043b34 orhi zero,at,4332 + 80435d4: 08043af4 orhi zero,at,4331 + 80435d8: 08043ba0 cmpeqi zero,at,4334 + 80435dc: 08043b94 ori zero,at,4334 + 80435e0: 080436ac andhi zero,at,4314 + 80435e4: 08043830 cmpltui zero,at,4320 + 80435e8: 080436ac andhi zero,at,4314 + 80435ec: 080437f0 cmpltui zero,at,4319 + 80435f0: 080436ac andhi zero,at,4314 + 80435f4: 080436ac andhi zero,at,4314 + 80435f8: 080437a8 cmpgeui zero,at,4318 + 80435fc: 95a3c83a sub r17,r18,r22 + 8043600: 883f9326 beq r17,zero,8043450 <___svfprintf_internal_r+0x110> + 8043604: 003f8206 br 8043410 <___svfprintf_internal_r+0xd0> + 8043608: d9000517 ldw r4,20(sp) + 804360c: d9801c04 addi r6,sp,112 + 8043610: 980b883a mov r5,r19 + 8043614: 80456900 call 8045690 <__ssprint_r> + 8043618: 1000081e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 804361c: b811883a mov r8,r23 + 8043620: 003f8606 br 804343c <___svfprintf_internal_r+0xfc> + 8043624: d8801e17 ldw r2,120(sp) + 8043628: 10000426 beq r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 804362c: d9000517 ldw r4,20(sp) + 8043630: d9801c04 addi r6,sp,112 + 8043634: 980b883a mov r5,r19 + 8043638: 80456900 call 8045690 <__ssprint_r> + 804363c: 9880030b ldhu r2,12(r19) + 8043640: 1080100c andi r2,r2,64 + 8043644: 10072d1e bne r2,zero,80452fc <___svfprintf_internal_r+0x1fbc> + 8043648: d8800417 ldw r2,16(sp) + 804364c: dfc04217 ldw ra,264(sp) + 8043650: df004117 ldw fp,260(sp) + 8043654: ddc04017 ldw r23,256(sp) + 8043658: dd803f17 ldw r22,252(sp) + 804365c: dd403e17 ldw r21,248(sp) + 8043660: dd003d17 ldw r20,244(sp) + 8043664: dcc03c17 ldw r19,240(sp) + 8043668: dc803b17 ldw r18,236(sp) + 804366c: dc403a17 ldw r17,232(sp) + 8043670: dc003917 ldw r16,228(sp) + 8043674: dec04304 addi sp,sp,268 + 8043678: f800283a ret + 804367c: 0023883a mov r17,zero + 8043680: e0bff404 addi r2,fp,-48 + 8043684: b5800044 addi r22,r22,1 + 8043688: 8c4002a4 muli r17,r17,10 + 804368c: b73fffc7 ldb fp,-1(r22) + 8043690: 1463883a add r17,r2,r17 + 8043694: e0bff404 addi r2,fp,-48 + 8043698: 10c002b0 cmpltui r3,r2,10 + 804369c: 183ff91e bne r3,zero,8043684 <___svfprintf_internal_r+0x344> + 80436a0: e0bff804 addi r2,fp,-32 + 80436a4: 10c01668 cmpgeui r3,r2,89 + 80436a8: 183f7626 beq r3,zero,8043484 <___svfprintf_internal_r+0x144> + 80436ac: 21003fcc andi r4,r4,255 + 80436b0: 20068c1e bne r4,zero,80450e4 <___svfprintf_internal_r+0x1da4> + 80436b4: e03fdb26 beq fp,zero,8043624 <___svfprintf_internal_r+0x2e4> + 80436b8: df001f05 stb fp,124(sp) + 80436bc: d8001545 stb zero,85(sp) + 80436c0: 05000044 movi r20,1 + 80436c4: 05400044 movi r21,1 + 80436c8: dc001f04 addi r16,sp,124 + 80436cc: 00009606 br 8043928 <___svfprintf_internal_r+0x5e8> + 80436d0: 63002014 ori r12,r12,128 + 80436d4: b2800007 ldb r10,0(r22) + 80436d8: 003f6506 br 8043470 <___svfprintf_internal_r+0x130> + 80436dc: b7000007 ldb fp,0(r22) + 80436e0: b0c00044 addi r3,r22,1 + 80436e4: e0800aa0 cmpeqi r2,fp,42 + 80436e8: 1007491e bne r2,zero,8045410 <___svfprintf_internal_r+0x20d0> + 80436ec: e0bff404 addi r2,fp,-48 + 80436f0: 118002b0 cmpltui r6,r2,10 + 80436f4: 182d883a mov r22,r3 + 80436f8: 0017883a mov r11,zero + 80436fc: 303f5e26 beq r6,zero,8043478 <___svfprintf_internal_r+0x138> + 8043700: b5800044 addi r22,r22,1 + 8043704: 5ac002a4 muli r11,r11,10 + 8043708: b73fffc7 ldb fp,-1(r22) + 804370c: 5897883a add r11,r11,r2 + 8043710: e0bff404 addi r2,fp,-48 + 8043714: 10c002b0 cmpltui r3,r2,10 + 8043718: 183ff91e bne r3,zero,8043700 <___svfprintf_internal_r+0x3c0> + 804371c: 003f5606 br 8043478 <___svfprintf_internal_r+0x138> + 8043720: b7000003 ldbu fp,0(r22) + 8043724: e2803fcc andi r10,fp,255 + 8043728: 5280201c xori r10,r10,128 + 804372c: 63000114 ori r12,r12,4 + 8043730: 52bfe004 addi r10,r10,-128 + 8043734: 003f4e06 br 8043470 <___svfprintf_internal_r+0x130> + 8043738: 01000044 movi r4,1 + 804373c: 01400ac4 movi r5,43 + 8043740: b2800007 ldb r10,0(r22) + 8043744: 003f4a06 br 8043470 <___svfprintf_internal_r+0x130> + 8043748: d8800617 ldw r2,24(sp) + 804374c: b7000003 ldbu fp,0(r22) + 8043750: 14400017 ldw r17,0(r2) + 8043754: 10800104 addi r2,r2,4 + 8043758: 88049016 blt r17,zero,804499c <___svfprintf_internal_r+0x165c> + 804375c: d8800615 stw r2,24(sp) + 8043760: e2803fcc andi r10,fp,255 + 8043764: 5280201c xori r10,r10,128 + 8043768: 52bfe004 addi r10,r10,-128 + 804376c: 003f4006 br 8043470 <___svfprintf_internal_r+0x130> + 8043770: 63000054 ori r12,r12,1 + 8043774: b2800007 ldb r10,0(r22) + 8043778: 003f3d06 br 8043470 <___svfprintf_internal_r+0x130> + 804377c: 28803fcc andi r2,r5,255 + 8043780: 1080201c xori r2,r2,128 + 8043784: 10bfe004 addi r2,r2,-128 + 8043788: b7000003 ldbu fp,0(r22) + 804378c: 103ff41e bne r2,zero,8043760 <___svfprintf_internal_r+0x420> + 8043790: e2803fcc andi r10,fp,255 + 8043794: 5280201c xori r10,r10,128 + 8043798: 01000044 movi r4,1 + 804379c: 01400804 movi r5,32 + 80437a0: 52bfe004 addi r10,r10,-128 + 80437a4: 003f3206 br 8043470 <___svfprintf_internal_r+0x130> + 80437a8: 21003fcc andi r4,r4,255 + 80437ac: 2006b01e bne r4,zero,8045270 <___svfprintf_internal_r+0x1f30> + 80437b0: 00820134 movhi r2,2052 + 80437b4: 109d2004 addi r2,r2,29824 + 80437b8: d8800c15 stw r2,48(sp) + 80437bc: 6080080c andi r2,r12,32 + 80437c0: 10019826 beq r2,zero,8043e24 <___svfprintf_internal_r+0xae4> + 80437c4: d8800617 ldw r2,24(sp) + 80437c8: 15000017 ldw r20,0(r2) + 80437cc: 15400117 ldw r21,4(r2) + 80437d0: 10800204 addi r2,r2,8 + 80437d4: d8800615 stw r2,24(sp) + 80437d8: 6080004c andi r2,r12,1 + 80437dc: 10000226 beq r2,zero,80437e8 <___svfprintf_internal_r+0x4a8> + 80437e0: a544b03a or r2,r20,r21 + 80437e4: 1004671e bne r2,zero,8044984 <___svfprintf_internal_r+0x1644> + 80437e8: 00800084 movi r2,2 + 80437ec: 0000fb06 br 8043bdc <___svfprintf_internal_r+0x89c> + 80437f0: 21003fcc andi r4,r4,255 + 80437f4: 20069a1e bne r4,zero,8045260 <___svfprintf_internal_r+0x1f20> + 80437f8: 6080080c andi r2,r12,32 + 80437fc: 1001a41e bne r2,zero,8043e90 <___svfprintf_internal_r+0xb50> + 8043800: d8800617 ldw r2,24(sp) + 8043804: 60c0040c andi r3,r12,16 + 8043808: 15000017 ldw r20,0(r2) + 804380c: 10800104 addi r2,r2,4 + 8043810: 1801961e bne r3,zero,8043e6c <___svfprintf_internal_r+0xb2c> + 8043814: 60c0100c andi r3,r12,64 + 8043818: 1805ab26 beq r3,zero,8044ec8 <___svfprintf_internal_r+0x1b88> + 804381c: d8800615 stw r2,24(sp) + 8043820: a53fffcc andi r20,r20,65535 + 8043824: 002b883a mov r21,zero + 8043828: 00800044 movi r2,1 + 804382c: 0000eb06 br 8043bdc <___svfprintf_internal_r+0x89c> + 8043830: d8800617 ldw r2,24(sp) + 8043834: d8001545 stb zero,85(sp) + 8043838: 14000017 ldw r16,0(r2) + 804383c: 14800104 addi r18,r2,4 + 8043840: 80051226 beq r16,zero,8044c8c <___svfprintf_internal_r+0x194c> + 8043844: da000e15 stw r8,56(sp) + 8043848: db000715 stw r12,28(sp) + 804384c: 58bfffe0 cmpeqi r2,r11,-1 + 8043850: 1004671e bne r2,zero,80449f0 <___svfprintf_internal_r+0x16b0> + 8043854: 580d883a mov r6,r11 + 8043858: 000b883a mov r5,zero + 804385c: 8009883a mov r4,r16 + 8043860: dac00615 stw r11,24(sp) + 8043864: 80085d00 call 80085d0 + 8043868: dac00617 ldw r11,24(sp) + 804386c: db000717 ldw r12,28(sp) + 8043870: da000e17 ldw r8,56(sp) + 8043874: 10066826 beq r2,zero,8045218 <___svfprintf_internal_r+0x1ed8> + 8043878: 142bc83a sub r21,r2,r16 + 804387c: a829883a mov r20,r21 + 8043880: a800010e bge r21,zero,8043888 <___svfprintf_internal_r+0x548> + 8043884: 0029883a mov r20,zero + 8043888: dc800615 stw r18,24(sp) + 804388c: 00002606 br 8043928 <___svfprintf_internal_r+0x5e8> + 8043890: 21003fcc andi r4,r4,255 + 8043894: 20067c1e bne r4,zero,8045288 <___svfprintf_internal_r+0x1f48> + 8043898: 6080080c andi r2,r12,32 + 804389c: 1001831e bne r2,zero,8043eac <___svfprintf_internal_r+0xb6c> + 80438a0: d8800617 ldw r2,24(sp) + 80438a4: 60c0040c andi r3,r12,16 + 80438a8: 10800104 addi r2,r2,4 + 80438ac: 1801271e bne r3,zero,8043d4c <___svfprintf_internal_r+0xa0c> + 80438b0: 60c0100c andi r3,r12,64 + 80438b4: 18012526 beq r3,zero,8043d4c <___svfprintf_internal_r+0xa0c> + 80438b8: d8c00617 ldw r3,24(sp) + 80438bc: d8800615 stw r2,24(sp) + 80438c0: 1d00000f ldh r20,0(r3) + 80438c4: a02bd7fa srai r21,r20,31 + 80438c8: a805883a mov r2,r21 + 80438cc: 10012516 blt r2,zero,8043d64 <___svfprintf_internal_r+0xa24> + 80438d0: 58bfffd8 cmpnei r2,r11,-1 + 80438d4: db401543 ldbu r13,85(sp) + 80438d8: 10018226 beq r2,zero,8043ee4 <___svfprintf_internal_r+0xba4> + 80438dc: 00ffdfc4 movi r3,-129 + 80438e0: a544b03a or r2,r20,r21 + 80438e4: 60d8703a and r12,r12,r3 + 80438e8: 10017e1e bne r2,zero,8043ee4 <___svfprintf_internal_r+0xba4> + 80438ec: 5801801e bne r11,zero,8043ef0 <___svfprintf_internal_r+0xbb0> + 80438f0: 6025883a mov r18,r12 + 80438f4: 0017883a mov r11,zero + 80438f8: 002b883a mov r21,zero + 80438fc: b821883a mov r16,r23 + 8043900: 00018006 br 8043f04 <___svfprintf_internal_r+0xbc4> + 8043904: d8c00617 ldw r3,24(sp) + 8043908: d8001545 stb zero,85(sp) + 804390c: 05000044 movi r20,1 + 8043910: 18800017 ldw r2,0(r3) + 8043914: 18c00104 addi r3,r3,4 + 8043918: d8c00615 stw r3,24(sp) + 804391c: d8801f05 stb r2,124(sp) + 8043920: 05400044 movi r21,1 + 8043924: dc001f04 addi r16,sp,124 + 8043928: 6025883a mov r18,r12 + 804392c: 0017883a mov r11,zero + 8043930: d8000715 stw zero,28(sp) + 8043934: 9380008c andi r14,r18,2 + 8043938: 70000126 beq r14,zero,8043940 <___svfprintf_internal_r+0x600> + 804393c: a5000084 addi r20,r20,2 + 8043940: 9340210c andi r13,r18,132 + 8043944: d8c01e17 ldw r3,120(sp) + 8043948: 6800021e bne r13,zero,8043954 <___svfprintf_internal_r+0x614> + 804394c: 8d0fc83a sub r7,r17,r20 + 8043950: 01c2a616 blt zero,r7,80443ec <___svfprintf_internal_r+0x10ac> + 8043954: d8801547 ldb r2,85(sp) + 8043958: 10000c26 beq r2,zero,804398c <___svfprintf_internal_r+0x64c> + 804395c: d8801d17 ldw r2,116(sp) + 8043960: d9001544 addi r4,sp,85 + 8043964: 18c00044 addi r3,r3,1 + 8043968: 10800044 addi r2,r2,1 + 804396c: 41000015 stw r4,0(r8) + 8043970: 01000044 movi r4,1 + 8043974: d8801d15 stw r2,116(sp) + 8043978: 41000115 stw r4,4(r8) + 804397c: d8c01e15 stw r3,120(sp) + 8043980: 10800208 cmpgei r2,r2,8 + 8043984: 1002d31e bne r2,zero,80444d4 <___svfprintf_internal_r+0x1194> + 8043988: 42000204 addi r8,r8,8 + 804398c: 70000c26 beq r14,zero,80439c0 <___svfprintf_internal_r+0x680> + 8043990: d8801d17 ldw r2,116(sp) + 8043994: d9001584 addi r4,sp,86 + 8043998: 18c00084 addi r3,r3,2 + 804399c: 10800044 addi r2,r2,1 + 80439a0: 41000015 stw r4,0(r8) + 80439a4: 01000084 movi r4,2 + 80439a8: d8801d15 stw r2,116(sp) + 80439ac: 41000115 stw r4,4(r8) + 80439b0: d8c01e15 stw r3,120(sp) + 80439b4: 10800208 cmpgei r2,r2,8 + 80439b8: 1002d41e bne r2,zero,804450c <___svfprintf_internal_r+0x11cc> + 80439bc: 42000204 addi r8,r8,8 + 80439c0: 6b402018 cmpnei r13,r13,128 + 80439c4: 6801ca26 beq r13,zero,80440f0 <___svfprintf_internal_r+0xdb0> + 80439c8: 5d4fc83a sub r7,r11,r21 + 80439cc: 01c20116 blt zero,r7,80441d4 <___svfprintf_internal_r+0xe94> + 80439d0: 9080400c andi r2,r18,256 + 80439d4: 1001791e bne r2,zero,8043fbc <___svfprintf_internal_r+0xc7c> + 80439d8: d8801d17 ldw r2,116(sp) + 80439dc: 1d47883a add r3,r3,r21 + 80439e0: 44000015 stw r16,0(r8) + 80439e4: 10800044 addi r2,r2,1 + 80439e8: d8801d15 stw r2,116(sp) + 80439ec: 45400115 stw r21,4(r8) + 80439f0: d8c01e15 stw r3,120(sp) + 80439f4: 10800208 cmpgei r2,r2,8 + 80439f8: 1002721e bne r2,zero,80443c4 <___svfprintf_internal_r+0x1084> + 80439fc: 42000204 addi r8,r8,8 + 8043a00: 9480010c andi r18,r18,4 + 8043a04: 90000226 beq r18,zero,8043a10 <___svfprintf_internal_r+0x6d0> + 8043a08: 8d21c83a sub r16,r17,r20 + 8043a0c: 04000916 blt zero,r16,8043a34 <___svfprintf_internal_r+0x6f4> + 8043a10: 8d00010e bge r17,r20,8043a18 <___svfprintf_internal_r+0x6d8> + 8043a14: a023883a mov r17,r20 + 8043a18: d8800417 ldw r2,16(sp) + 8043a1c: 1445883a add r2,r2,r17 + 8043a20: d8800415 stw r2,16(sp) + 8043a24: 18021f1e bne r3,zero,80442a4 <___svfprintf_internal_r+0xf64> + 8043a28: d8001d15 stw zero,116(sp) + 8043a2c: b811883a mov r8,r23 + 8043a30: 003e6906 br 80433d8 <___svfprintf_internal_r+0x98> + 8043a34: 03020174 movhi r12,2053 + 8043a38: 81000450 cmplti r4,r16,17 + 8043a3c: 632e3844 addi r12,r12,-18207 + 8043a40: d8801d17 ldw r2,116(sp) + 8043a44: 20001c1e bne r4,zero,8043ab8 <___svfprintf_internal_r+0x778> + 8043a48: 04800404 movi r18,16 + 8043a4c: dd400517 ldw r21,20(sp) + 8043a50: 6039883a mov fp,r12 + 8043a54: 00000406 br 8043a68 <___svfprintf_internal_r+0x728> + 8043a58: 843ffc04 addi r16,r16,-16 + 8043a5c: 81000448 cmpgei r4,r16,17 + 8043a60: 42000204 addi r8,r8,8 + 8043a64: 20001326 beq r4,zero,8043ab4 <___svfprintf_internal_r+0x774> + 8043a68: 10800044 addi r2,r2,1 + 8043a6c: 18c00404 addi r3,r3,16 + 8043a70: 47000015 stw fp,0(r8) + 8043a74: 44800115 stw r18,4(r8) + 8043a78: d8c01e15 stw r3,120(sp) + 8043a7c: d8801d15 stw r2,116(sp) + 8043a80: 11000208 cmpgei r4,r2,8 + 8043a84: 203ff426 beq r4,zero,8043a58 <___svfprintf_internal_r+0x718> + 8043a88: d9801c04 addi r6,sp,112 + 8043a8c: 980b883a mov r5,r19 + 8043a90: a809883a mov r4,r21 + 8043a94: 80456900 call 8045690 <__ssprint_r> + 8043a98: 103ee81e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 8043a9c: 843ffc04 addi r16,r16,-16 + 8043aa0: 81000448 cmpgei r4,r16,17 + 8043aa4: d8c01e17 ldw r3,120(sp) + 8043aa8: d8801d17 ldw r2,116(sp) + 8043aac: b811883a mov r8,r23 + 8043ab0: 203fed1e bne r4,zero,8043a68 <___svfprintf_internal_r+0x728> + 8043ab4: e019883a mov r12,fp + 8043ab8: 10800044 addi r2,r2,1 + 8043abc: 1c07883a add r3,r3,r16 + 8043ac0: d8801d15 stw r2,116(sp) + 8043ac4: 43000015 stw r12,0(r8) + 8043ac8: 44000115 stw r16,4(r8) + 8043acc: d8c01e15 stw r3,120(sp) + 8043ad0: 10800210 cmplti r2,r2,8 + 8043ad4: 103fce1e bne r2,zero,8043a10 <___svfprintf_internal_r+0x6d0> + 8043ad8: d9000517 ldw r4,20(sp) + 8043adc: d9801c04 addi r6,sp,112 + 8043ae0: 980b883a mov r5,r19 + 8043ae4: 80456900 call 8045690 <__ssprint_r> + 8043ae8: 103ed41e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 8043aec: d8c01e17 ldw r3,120(sp) + 8043af0: 003fc706 br 8043a10 <___svfprintf_internal_r+0x6d0> + 8043af4: 21003fcc andi r4,r4,255 + 8043af8: 2005e11e bne r4,zero,8045280 <___svfprintf_internal_r+0x1f40> + 8043afc: 6080080c andi r2,r12,32 + 8043b00: 1000f11e bne r2,zero,8043ec8 <___svfprintf_internal_r+0xb88> + 8043b04: d8800617 ldw r2,24(sp) + 8043b08: 60c0040c andi r3,r12,16 + 8043b0c: 15000017 ldw r20,0(r2) + 8043b10: 10800104 addi r2,r2,4 + 8043b14: 1800481e bne r3,zero,8043c38 <___svfprintf_internal_r+0x8f8> + 8043b18: 60c0100c andi r3,r12,64 + 8043b1c: 18053326 beq r3,zero,8044fec <___svfprintf_internal_r+0x1cac> + 8043b20: d8800615 stw r2,24(sp) + 8043b24: a53fffcc andi r20,r20,65535 + 8043b28: 002b883a mov r21,zero + 8043b2c: 0005883a mov r2,zero + 8043b30: 00002a06 br 8043bdc <___svfprintf_internal_r+0x89c> + 8043b34: 21003fcc andi r4,r4,255 + 8043b38: 2005d71e bne r4,zero,8045298 <___svfprintf_internal_r+0x1f58> + 8043b3c: d9000617 ldw r4,24(sp) + 8043b40: 6080080c andi r2,r12,32 + 8043b44: 20c00104 addi r3,r4,4 + 8043b48: 1003871e bne r2,zero,8044968 <___svfprintf_internal_r+0x1628> + 8043b4c: 6080040c andi r2,r12,16 + 8043b50: 1003dc1e bne r2,zero,8044ac4 <___svfprintf_internal_r+0x1784> + 8043b54: 6300100c andi r12,r12,64 + 8043b58: 6003da26 beq r12,zero,8044ac4 <___svfprintf_internal_r+0x1784> + 8043b5c: d8800617 ldw r2,24(sp) + 8043b60: d8c00615 stw r3,24(sp) + 8043b64: d8c00417 ldw r3,16(sp) + 8043b68: 10800017 ldw r2,0(r2) + 8043b6c: 10c0000d sth r3,0(r2) + 8043b70: 003e1906 br 80433d8 <___svfprintf_internal_r+0x98> + 8043b74: b2800007 ldb r10,0(r22) + 8043b78: 50801b18 cmpnei r2,r10,108 + 8043b7c: 10043426 beq r2,zero,8044c50 <___svfprintf_internal_r+0x1910> + 8043b80: 63000414 ori r12,r12,16 + 8043b84: 003e3a06 br 8043470 <___svfprintf_internal_r+0x130> + 8043b88: 63001014 ori r12,r12,64 + 8043b8c: b2800007 ldb r10,0(r22) + 8043b90: 003e3706 br 8043470 <___svfprintf_internal_r+0x130> + 8043b94: 63000814 ori r12,r12,32 + 8043b98: b2800007 ldb r10,0(r22) + 8043b9c: 003e3406 br 8043470 <___svfprintf_internal_r+0x130> + 8043ba0: d8c00617 ldw r3,24(sp) + 8043ba4: 00800c04 movi r2,48 + 8043ba8: d8801585 stb r2,86(sp) + 8043bac: 00801e04 movi r2,120 + 8043bb0: 01020134 movhi r4,2052 + 8043bb4: d88015c5 stb r2,87(sp) + 8043bb8: 1d000017 ldw r20,0(r3) + 8043bbc: 18800104 addi r2,r3,4 + 8043bc0: d8800615 stw r2,24(sp) + 8043bc4: 209d2004 addi r2,r4,29824 + 8043bc8: d8800c15 stw r2,48(sp) + 8043bcc: 002b883a mov r21,zero + 8043bd0: 63000094 ori r12,r12,2 + 8043bd4: 00800084 movi r2,2 + 8043bd8: 07001e04 movi fp,120 + 8043bdc: d8001545 stb zero,85(sp) + 8043be0: 58ffffe0 cmpeqi r3,r11,-1 + 8043be4: 001b883a mov r13,zero + 8043be8: 1800681e bne r3,zero,8043d8c <___svfprintf_internal_r+0xa4c> + 8043bec: 04bfdfc4 movi r18,-129 + 8043bf0: a546b03a or r3,r20,r21 + 8043bf4: 64a4703a and r18,r12,r18 + 8043bf8: 1801fa1e bne r3,zero,80443e4 <___svfprintf_internal_r+0x10a4> + 8043bfc: 5804101e bne r11,zero,8044c40 <___svfprintf_internal_r+0x1900> + 8043c00: 103f3c1e bne r2,zero,80438f4 <___svfprintf_internal_r+0x5b4> + 8043c04: 6540004c andi r21,r12,1 + 8043c08: a8030126 beq r21,zero,8044810 <___svfprintf_internal_r+0x14d0> + 8043c0c: 00800c04 movi r2,48 + 8043c10: d88028c5 stb r2,163(sp) + 8043c14: dc0028c4 addi r16,sp,163 + 8043c18: 0000ba06 br 8043f04 <___svfprintf_internal_r+0xbc4> + 8043c1c: 21003fcc andi r4,r4,255 + 8043c20: 2005951e bne r4,zero,8045278 <___svfprintf_internal_r+0x1f38> + 8043c24: 6080080c andi r2,r12,32 + 8043c28: 63000414 ori r12,r12,16 + 8043c2c: 1000a61e bne r2,zero,8043ec8 <___svfprintf_internal_r+0xb88> + 8043c30: d8800617 ldw r2,24(sp) + 8043c34: 10800104 addi r2,r2,4 + 8043c38: d8c00617 ldw r3,24(sp) + 8043c3c: 002b883a mov r21,zero + 8043c40: d8800615 stw r2,24(sp) + 8043c44: 1d000017 ldw r20,0(r3) + 8043c48: 0005883a mov r2,zero + 8043c4c: 003fe306 br 8043bdc <___svfprintf_internal_r+0x89c> + 8043c50: 21003fcc andi r4,r4,255 + 8043c54: 20058e1e bne r4,zero,8045290 <___svfprintf_internal_r+0x1f50> + 8043c58: d8c00617 ldw r3,24(sp) + 8043c5c: 00a00034 movhi r2,32768 + 8043c60: 10bfffc4 addi r2,r2,-1 + 8043c64: 1d000117 ldw r20,4(r3) + 8043c68: 1c800017 ldw r18,0(r3) + 8043c6c: 01dffc34 movhi r7,32752 + 8043c70: a0a0703a and r16,r20,r2 + 8043c74: 01bfffc4 movi r6,-1 + 8043c78: 18800204 addi r2,r3,8 + 8043c7c: 39ffffc4 addi r7,r7,-1 + 8043c80: 9009883a mov r4,r18 + 8043c84: 800b883a mov r5,r16 + 8043c88: da000f15 stw r8,60(sp) + 8043c8c: dac00e15 stw r11,56(sp) + 8043c90: db000715 stw r12,28(sp) + 8043c94: dd000a15 stw r20,40(sp) + 8043c98: dc800915 stw r18,36(sp) + 8043c9c: d8800615 stw r2,24(sp) + 8043ca0: 800f5580 call 800f558 <__unorddf2> + 8043ca4: db000717 ldw r12,28(sp) + 8043ca8: dac00e17 ldw r11,56(sp) + 8043cac: da000f17 ldw r8,60(sp) + 8043cb0: 1002d91e bne r2,zero,8044818 <___svfprintf_internal_r+0x14d8> + 8043cb4: 01dffc34 movhi r7,32752 + 8043cb8: 01bfffc4 movi r6,-1 + 8043cbc: 39ffffc4 addi r7,r7,-1 + 8043cc0: 9009883a mov r4,r18 + 8043cc4: 800b883a mov r5,r16 + 8043cc8: 800e4700 call 800e470 <__ledf2> + 8043ccc: db000717 ldw r12,28(sp) + 8043cd0: dac00e17 ldw r11,56(sp) + 8043cd4: da000f17 ldw r8,60(sp) + 8043cd8: 0082cf0e bge zero,r2,8044818 <___svfprintf_internal_r+0x14d8> + 8043cdc: 000d883a mov r6,zero + 8043ce0: 000f883a mov r7,zero + 8043ce4: 9009883a mov r4,r18 + 8043ce8: a00b883a mov r5,r20 + 8043cec: da000e15 stw r8,56(sp) + 8043cf0: 800e4700 call 800e470 <__ledf2> + 8043cf4: db000717 ldw r12,28(sp) + 8043cf8: da000e17 ldw r8,56(sp) + 8043cfc: 1004db16 blt r2,zero,804506c <___svfprintf_internal_r+0x1d2c> + 8043d00: db401543 ldbu r13,85(sp) + 8043d04: e0801210 cmplti r2,fp,72 + 8043d08: 1004b51e bne r2,zero,8044fe0 <___svfprintf_internal_r+0x1ca0> + 8043d0c: 04020134 movhi r16,2052 + 8043d10: 841d1804 addi r16,r16,29792 + 8043d14: 04bfdfc4 movi r18,-129 + 8043d18: 64a4703a and r18,r12,r18 + 8043d1c: 050000c4 movi r20,3 + 8043d20: 054000c4 movi r21,3 + 8043d24: 0017883a mov r11,zero + 8043d28: d8000715 stw zero,28(sp) + 8043d2c: 00007906 br 8043f14 <___svfprintf_internal_r+0xbd4> + 8043d30: 21003fcc andi r4,r4,255 + 8043d34: 20054c1e bne r4,zero,8045268 <___svfprintf_internal_r+0x1f28> + 8043d38: 6080080c andi r2,r12,32 + 8043d3c: 63000414 ori r12,r12,16 + 8043d40: 10005a1e bne r2,zero,8043eac <___svfprintf_internal_r+0xb6c> + 8043d44: d8800617 ldw r2,24(sp) + 8043d48: 10800104 addi r2,r2,4 + 8043d4c: d8c00617 ldw r3,24(sp) + 8043d50: 1d000017 ldw r20,0(r3) + 8043d54: d8800615 stw r2,24(sp) + 8043d58: a02bd7fa srai r21,r20,31 + 8043d5c: a805883a mov r2,r21 + 8043d60: 103edb0e bge r2,zero,80438d0 <___svfprintf_internal_r+0x590> + 8043d64: 0529c83a sub r20,zero,r20 + 8043d68: a004c03a cmpne r2,r20,zero + 8043d6c: 056bc83a sub r21,zero,r21 + 8043d70: a8abc83a sub r21,r21,r2 + 8043d74: 00800b44 movi r2,45 + 8043d78: d8801545 stb r2,85(sp) + 8043d7c: 58ffffe0 cmpeqi r3,r11,-1 + 8043d80: 03400b44 movi r13,45 + 8043d84: 00800044 movi r2,1 + 8043d88: 183f9826 beq r3,zero,8043bec <___svfprintf_internal_r+0x8ac> + 8043d8c: 10c00060 cmpeqi r3,r2,1 + 8043d90: 1800541e bne r3,zero,8043ee4 <___svfprintf_internal_r+0xba4> + 8043d94: 108000a0 cmpeqi r2,r2,2 + 8043d98: 1001e81e bne r2,zero,804453c <___svfprintf_internal_r+0x11fc> + 8043d9c: b807883a mov r3,r23 + 8043da0: 00000106 br 8043da8 <___svfprintf_internal_r+0xa68> + 8043da4: 8007883a mov r3,r16 + 8043da8: a008d0fa srli r4,r20,3 + 8043dac: a80a977a slli r5,r21,29 + 8043db0: a82ad0fa srli r21,r21,3 + 8043db4: a50001cc andi r20,r20,7 + 8043db8: a0800c04 addi r2,r20,48 + 8043dbc: 2928b03a or r20,r5,r4 + 8043dc0: 18bfffc5 stb r2,-1(r3) + 8043dc4: a548b03a or r4,r20,r21 + 8043dc8: 1c3fffc4 addi r16,r3,-1 + 8043dcc: 203ff51e bne r4,zero,8043da4 <___svfprintf_internal_r+0xa64> + 8043dd0: 6100004c andi r4,r12,1 + 8043dd4: 20007626 beq r4,zero,8043fb0 <___svfprintf_internal_r+0xc70> + 8043dd8: 10803fcc andi r2,r2,255 + 8043ddc: 1080201c xori r2,r2,128 + 8043de0: 10bfe004 addi r2,r2,-128 + 8043de4: 10800c18 cmpnei r2,r2,48 + 8043de8: 10007126 beq r2,zero,8043fb0 <___svfprintf_internal_r+0xc70> + 8043dec: 18ffff84 addi r3,r3,-2 + 8043df0: 00800c04 movi r2,48 + 8043df4: 80bfffc5 stb r2,-1(r16) + 8043df8: b8ebc83a sub r21,r23,r3 + 8043dfc: 6025883a mov r18,r12 + 8043e00: 1821883a mov r16,r3 + 8043e04: 00003f06 br 8043f04 <___svfprintf_internal_r+0xbc4> + 8043e08: 21003fcc andi r4,r4,255 + 8043e0c: 2005121e bne r4,zero,8045258 <___svfprintf_internal_r+0x1f18> + 8043e10: 00820134 movhi r2,2052 + 8043e14: 109d1b04 addi r2,r2,29804 + 8043e18: d8800c15 stw r2,48(sp) + 8043e1c: 6080080c andi r2,r12,32 + 8043e20: 103e681e bne r2,zero,80437c4 <___svfprintf_internal_r+0x484> + 8043e24: d8c00617 ldw r3,24(sp) + 8043e28: 6080040c andi r2,r12,16 + 8043e2c: 1d000017 ldw r20,0(r3) + 8043e30: 18c00104 addi r3,r3,4 + 8043e34: d8c00615 stw r3,24(sp) + 8043e38: 10025f1e bne r2,zero,80447b8 <___svfprintf_internal_r+0x1478> + 8043e3c: 6080100c andi r2,r12,64 + 8043e40: 10025d26 beq r2,zero,80447b8 <___svfprintf_internal_r+0x1478> + 8043e44: a53fffcc andi r20,r20,65535 + 8043e48: 002b883a mov r21,zero + 8043e4c: 003e6206 br 80437d8 <___svfprintf_internal_r+0x498> + 8043e50: 21003fcc andi r4,r4,255 + 8043e54: 2005121e bne r4,zero,80452a0 <___svfprintf_internal_r+0x1f60> + 8043e58: 6080080c andi r2,r12,32 + 8043e5c: 63000414 ori r12,r12,16 + 8043e60: 10000b1e bne r2,zero,8043e90 <___svfprintf_internal_r+0xb50> + 8043e64: d8800617 ldw r2,24(sp) + 8043e68: 10800104 addi r2,r2,4 + 8043e6c: d8c00617 ldw r3,24(sp) + 8043e70: 002b883a mov r21,zero + 8043e74: d8800615 stw r2,24(sp) + 8043e78: 1d000017 ldw r20,0(r3) + 8043e7c: 00800044 movi r2,1 + 8043e80: 003f5606 br 8043bdc <___svfprintf_internal_r+0x89c> + 8043e84: 63000214 ori r12,r12,8 + 8043e88: b2800007 ldb r10,0(r22) + 8043e8c: 003d7806 br 8043470 <___svfprintf_internal_r+0x130> + 8043e90: d8c00617 ldw r3,24(sp) + 8043e94: 00800044 movi r2,1 + 8043e98: 1d000017 ldw r20,0(r3) + 8043e9c: 1d400117 ldw r21,4(r3) + 8043ea0: 18c00204 addi r3,r3,8 + 8043ea4: d8c00615 stw r3,24(sp) + 8043ea8: 003f4c06 br 8043bdc <___svfprintf_internal_r+0x89c> + 8043eac: d8c00617 ldw r3,24(sp) + 8043eb0: 18800117 ldw r2,4(r3) + 8043eb4: 1d000017 ldw r20,0(r3) + 8043eb8: 18c00204 addi r3,r3,8 + 8043ebc: d8c00615 stw r3,24(sp) + 8043ec0: 102b883a mov r21,r2 + 8043ec4: 003e8106 br 80438cc <___svfprintf_internal_r+0x58c> + 8043ec8: d8c00617 ldw r3,24(sp) + 8043ecc: 0005883a mov r2,zero + 8043ed0: 1d000017 ldw r20,0(r3) + 8043ed4: 1d400117 ldw r21,4(r3) + 8043ed8: 18c00204 addi r3,r3,8 + 8043edc: d8c00615 stw r3,24(sp) + 8043ee0: 003f3e06 br 8043bdc <___svfprintf_internal_r+0x89c> + 8043ee4: a800111e bne r21,zero,8043f2c <___svfprintf_internal_r+0xbec> + 8043ee8: a08002a8 cmpgeui r2,r20,10 + 8043eec: 10000f1e bne r2,zero,8043f2c <___svfprintf_internal_r+0xbec> + 8043ef0: a5000c04 addi r20,r20,48 + 8043ef4: dd0028c5 stb r20,163(sp) + 8043ef8: 6025883a mov r18,r12 + 8043efc: 05400044 movi r21,1 + 8043f00: dc0028c4 addi r16,sp,163 + 8043f04: 5829883a mov r20,r11 + 8043f08: 5d40010e bge r11,r21,8043f10 <___svfprintf_internal_r+0xbd0> + 8043f0c: a829883a mov r20,r21 + 8043f10: d8000715 stw zero,28(sp) + 8043f14: 6b403fcc andi r13,r13,255 + 8043f18: 6b40201c xori r13,r13,128 + 8043f1c: 6b7fe004 addi r13,r13,-128 + 8043f20: 683e8426 beq r13,zero,8043934 <___svfprintf_internal_r+0x5f4> + 8043f24: a5000044 addi r20,r20,1 + 8043f28: 003e8206 br 8043934 <___svfprintf_internal_r+0x5f4> + 8043f2c: dc400e15 stw r17,56(sp) + 8043f30: b821883a mov r16,r23 + 8043f34: a823883a mov r17,r21 + 8043f38: db000715 stw r12,28(sp) + 8043f3c: 982b883a mov r21,r19 + 8043f40: dac00f15 stw r11,60(sp) + 8043f44: 4025883a mov r18,r8 + 8043f48: 6827883a mov r19,r13 + 8043f4c: 00000206 br 8043f58 <___svfprintf_internal_r+0xc18> + 8043f50: 1029883a mov r20,r2 + 8043f54: 1823883a mov r17,r3 + 8043f58: a009883a mov r4,r20 + 8043f5c: 880b883a mov r5,r17 + 8043f60: 01800284 movi r6,10 + 8043f64: 000f883a mov r7,zero + 8043f68: 800c9c00 call 800c9c0 <__umoddi3> + 8043f6c: 10800c04 addi r2,r2,48 + 8043f70: 843fffc4 addi r16,r16,-1 + 8043f74: a009883a mov r4,r20 + 8043f78: 880b883a mov r5,r17 + 8043f7c: 80800005 stb r2,0(r16) + 8043f80: 01800284 movi r6,10 + 8043f84: 000f883a mov r7,zero + 8043f88: 800c4280 call 800c428 <__udivdi3> + 8043f8c: 883ff01e bne r17,zero,8043f50 <___svfprintf_internal_r+0xc10> + 8043f90: a50002a8 cmpgeui r20,r20,10 + 8043f94: a03fee1e bne r20,zero,8043f50 <___svfprintf_internal_r+0xc10> + 8043f98: db000717 ldw r12,28(sp) + 8043f9c: dc400e17 ldw r17,56(sp) + 8043fa0: dac00f17 ldw r11,60(sp) + 8043fa4: 981b883a mov r13,r19 + 8043fa8: 9011883a mov r8,r18 + 8043fac: a827883a mov r19,r21 + 8043fb0: bc2bc83a sub r21,r23,r16 + 8043fb4: 6025883a mov r18,r12 + 8043fb8: 003fd206 br 8043f04 <___svfprintf_internal_r+0xbc4> + 8043fbc: e2801990 cmplti r10,fp,102 + 8043fc0: 5000be1e bne r10,zero,80442bc <___svfprintf_internal_r+0xf7c> + 8043fc4: d9000917 ldw r4,36(sp) + 8043fc8: d9400a17 ldw r5,40(sp) + 8043fcc: 000d883a mov r6,zero + 8043fd0: 000f883a mov r7,zero + 8043fd4: da000f15 stw r8,60(sp) + 8043fd8: d8c00e15 stw r3,56(sp) + 8043fdc: 800e3000 call 800e300 <__eqdf2> + 8043fe0: d8c00e17 ldw r3,56(sp) + 8043fe4: da000f17 ldw r8,60(sp) + 8043fe8: 1001641e bne r2,zero,804457c <___svfprintf_internal_r+0x123c> + 8043fec: d8801d17 ldw r2,116(sp) + 8043ff0: 01020134 movhi r4,2052 + 8043ff4: 211d2704 addi r4,r4,29852 + 8043ff8: 10800044 addi r2,r2,1 + 8043ffc: 18c00044 addi r3,r3,1 + 8044000: 41000015 stw r4,0(r8) + 8044004: 01000044 movi r4,1 + 8044008: d8801d15 stw r2,116(sp) + 804400c: 41000115 stw r4,4(r8) + 8044010: d8c01e15 stw r3,120(sp) + 8044014: 10800208 cmpgei r2,r2,8 + 8044018: 1002f81e bne r2,zero,8044bfc <___svfprintf_internal_r+0x18bc> + 804401c: 42000204 addi r8,r8,8 + 8044020: d8801617 ldw r2,88(sp) + 8044024: d8c00817 ldw r3,32(sp) + 8044028: 10c00216 blt r2,r3,8044034 <___svfprintf_internal_r+0xcf4> + 804402c: 9080004c andi r2,r18,1 + 8044030: 10026826 beq r2,zero,80449d4 <___svfprintf_internal_r+0x1694> + 8044034: d8800d17 ldw r2,52(sp) + 8044038: d8c01e17 ldw r3,120(sp) + 804403c: d9000b17 ldw r4,44(sp) + 8044040: 40800015 stw r2,0(r8) + 8044044: d8801d17 ldw r2,116(sp) + 8044048: 20c7883a add r3,r4,r3 + 804404c: 41000115 stw r4,4(r8) + 8044050: 10800044 addi r2,r2,1 + 8044054: d8801d15 stw r2,116(sp) + 8044058: d8c01e15 stw r3,120(sp) + 804405c: 10800208 cmpgei r2,r2,8 + 8044060: 1003021e bne r2,zero,8044c6c <___svfprintf_internal_r+0x192c> + 8044064: 42000204 addi r8,r8,8 + 8044068: d8800817 ldw r2,32(sp) + 804406c: 143fffc4 addi r16,r2,-1 + 8044070: 043e630e bge zero,r16,8043a00 <___svfprintf_internal_r+0x6c0> + 8044074: 03020174 movhi r12,2053 + 8044078: 81000450 cmplti r4,r16,17 + 804407c: 632e3444 addi r12,r12,-18223 + 8044080: d8801d17 ldw r2,116(sp) + 8044084: 2003381e bne r4,zero,8044d68 <___svfprintf_internal_r+0x1a28> + 8044088: dc400715 stw r17,28(sp) + 804408c: 05400404 movi r21,16 + 8044090: df000517 ldw fp,20(sp) + 8044094: 6023883a mov r17,r12 + 8044098: 00000406 br 80440ac <___svfprintf_internal_r+0xd6c> + 804409c: 42000204 addi r8,r8,8 + 80440a0: 843ffc04 addi r16,r16,-16 + 80440a4: 81000448 cmpgei r4,r16,17 + 80440a8: 20032d26 beq r4,zero,8044d60 <___svfprintf_internal_r+0x1a20> + 80440ac: 10800044 addi r2,r2,1 + 80440b0: 18c00404 addi r3,r3,16 + 80440b4: 44400015 stw r17,0(r8) + 80440b8: 45400115 stw r21,4(r8) + 80440bc: d8c01e15 stw r3,120(sp) + 80440c0: d8801d15 stw r2,116(sp) + 80440c4: 11000208 cmpgei r4,r2,8 + 80440c8: 203ff426 beq r4,zero,804409c <___svfprintf_internal_r+0xd5c> + 80440cc: d9801c04 addi r6,sp,112 + 80440d0: 980b883a mov r5,r19 + 80440d4: e009883a mov r4,fp + 80440d8: 80456900 call 8045690 <__ssprint_r> + 80440dc: 103d571e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 80440e0: d8c01e17 ldw r3,120(sp) + 80440e4: d8801d17 ldw r2,116(sp) + 80440e8: b811883a mov r8,r23 + 80440ec: 003fec06 br 80440a0 <___svfprintf_internal_r+0xd60> + 80440f0: 8d0fc83a sub r7,r17,r20 + 80440f4: 01fe340e bge zero,r7,80439c8 <___svfprintf_internal_r+0x688> + 80440f8: 03020174 movhi r12,2053 + 80440fc: 39000450 cmplti r4,r7,17 + 8044100: 632e3444 addi r12,r12,-18223 + 8044104: d8801d17 ldw r2,116(sp) + 8044108: 2000271e bne r4,zero,80441a8 <___svfprintf_internal_r+0xe68> + 804410c: dc800e15 stw r18,56(sp) + 8044110: dc000f15 stw r16,60(sp) + 8044114: dc401015 stw r17,64(sp) + 8044118: 03400404 movi r13,16 + 804411c: 3821883a mov r16,r7 + 8044120: dac01215 stw r11,72(sp) + 8044124: dc400517 ldw r17,20(sp) + 8044128: 6025883a mov r18,r12 + 804412c: 00000406 br 8044140 <___svfprintf_internal_r+0xe00> + 8044130: 843ffc04 addi r16,r16,-16 + 8044134: 81000448 cmpgei r4,r16,17 + 8044138: 42000204 addi r8,r8,8 + 804413c: 20001426 beq r4,zero,8044190 <___svfprintf_internal_r+0xe50> + 8044140: 10800044 addi r2,r2,1 + 8044144: 18c00404 addi r3,r3,16 + 8044148: 44800015 stw r18,0(r8) + 804414c: 43400115 stw r13,4(r8) + 8044150: d8c01e15 stw r3,120(sp) + 8044154: d8801d15 stw r2,116(sp) + 8044158: 11000208 cmpgei r4,r2,8 + 804415c: 203ff426 beq r4,zero,8044130 <___svfprintf_internal_r+0xdf0> + 8044160: d9801c04 addi r6,sp,112 + 8044164: 980b883a mov r5,r19 + 8044168: 8809883a mov r4,r17 + 804416c: 80456900 call 8045690 <__ssprint_r> + 8044170: 103d321e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 8044174: 843ffc04 addi r16,r16,-16 + 8044178: 81000448 cmpgei r4,r16,17 + 804417c: d8c01e17 ldw r3,120(sp) + 8044180: d8801d17 ldw r2,116(sp) + 8044184: b811883a mov r8,r23 + 8044188: 03400404 movi r13,16 + 804418c: 203fec1e bne r4,zero,8044140 <___svfprintf_internal_r+0xe00> + 8044190: 800f883a mov r7,r16 + 8044194: 9019883a mov r12,r18 + 8044198: dc000f17 ldw r16,60(sp) + 804419c: dc401017 ldw r17,64(sp) + 80441a0: dac01217 ldw r11,72(sp) + 80441a4: dc800e17 ldw r18,56(sp) + 80441a8: 10800044 addi r2,r2,1 + 80441ac: 19c7883a add r3,r3,r7 + 80441b0: d8801d15 stw r2,116(sp) + 80441b4: 43000015 stw r12,0(r8) + 80441b8: 41c00115 stw r7,4(r8) + 80441bc: d8c01e15 stw r3,120(sp) + 80441c0: 10800208 cmpgei r2,r2,8 + 80441c4: 1002941e bne r2,zero,8044c18 <___svfprintf_internal_r+0x18d8> + 80441c8: 5d4fc83a sub r7,r11,r21 + 80441cc: 42000204 addi r8,r8,8 + 80441d0: 01fdff0e bge zero,r7,80439d0 <___svfprintf_internal_r+0x690> + 80441d4: 03020174 movhi r12,2053 + 80441d8: 39000450 cmplti r4,r7,17 + 80441dc: 632e3444 addi r12,r12,-18223 + 80441e0: d8801d17 ldw r2,116(sp) + 80441e4: 2000251e bne r4,zero,804427c <___svfprintf_internal_r+0xf3c> + 80441e8: dc800e15 stw r18,56(sp) + 80441ec: dc000f15 stw r16,60(sp) + 80441f0: dc401015 stw r17,64(sp) + 80441f4: 02c00404 movi r11,16 + 80441f8: 3821883a mov r16,r7 + 80441fc: dc400517 ldw r17,20(sp) + 8044200: 6025883a mov r18,r12 + 8044204: 00000406 br 8044218 <___svfprintf_internal_r+0xed8> + 8044208: 843ffc04 addi r16,r16,-16 + 804420c: 81000448 cmpgei r4,r16,17 + 8044210: 42000204 addi r8,r8,8 + 8044214: 20001426 beq r4,zero,8044268 <___svfprintf_internal_r+0xf28> + 8044218: 10800044 addi r2,r2,1 + 804421c: 18c00404 addi r3,r3,16 + 8044220: 44800015 stw r18,0(r8) + 8044224: 42c00115 stw r11,4(r8) + 8044228: d8c01e15 stw r3,120(sp) + 804422c: d8801d15 stw r2,116(sp) + 8044230: 11000208 cmpgei r4,r2,8 + 8044234: 203ff426 beq r4,zero,8044208 <___svfprintf_internal_r+0xec8> + 8044238: d9801c04 addi r6,sp,112 + 804423c: 980b883a mov r5,r19 + 8044240: 8809883a mov r4,r17 + 8044244: 80456900 call 8045690 <__ssprint_r> + 8044248: 103cfc1e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 804424c: 843ffc04 addi r16,r16,-16 + 8044250: 81000448 cmpgei r4,r16,17 + 8044254: d8c01e17 ldw r3,120(sp) + 8044258: d8801d17 ldw r2,116(sp) + 804425c: b811883a mov r8,r23 + 8044260: 02c00404 movi r11,16 + 8044264: 203fec1e bne r4,zero,8044218 <___svfprintf_internal_r+0xed8> + 8044268: 800f883a mov r7,r16 + 804426c: 9019883a mov r12,r18 + 8044270: dc401017 ldw r17,64(sp) + 8044274: dc000f17 ldw r16,60(sp) + 8044278: dc800e17 ldw r18,56(sp) + 804427c: 10800044 addi r2,r2,1 + 8044280: 19c7883a add r3,r3,r7 + 8044284: d8801d15 stw r2,116(sp) + 8044288: 43000015 stw r12,0(r8) + 804428c: 41c00115 stw r7,4(r8) + 8044290: d8c01e15 stw r3,120(sp) + 8044294: 10800208 cmpgei r2,r2,8 + 8044298: 10013f1e bne r2,zero,8044798 <___svfprintf_internal_r+0x1458> + 804429c: 42000204 addi r8,r8,8 + 80442a0: 003dcb06 br 80439d0 <___svfprintf_internal_r+0x690> + 80442a4: d9000517 ldw r4,20(sp) + 80442a8: d9801c04 addi r6,sp,112 + 80442ac: 980b883a mov r5,r19 + 80442b0: 80456900 call 8045690 <__ssprint_r> + 80442b4: 103ddc26 beq r2,zero,8043a28 <___svfprintf_internal_r+0x6e8> + 80442b8: 003ce006 br 804363c <___svfprintf_internal_r+0x2fc> + 80442bc: d8800817 ldw r2,32(sp) + 80442c0: df001d17 ldw fp,116(sp) + 80442c4: 18c00044 addi r3,r3,1 + 80442c8: 10800088 cmpgei r2,r2,2 + 80442cc: e5400044 addi r21,fp,1 + 80442d0: 42800204 addi r10,r8,8 + 80442d4: 10010226 beq r2,zero,80446e0 <___svfprintf_internal_r+0x13a0> + 80442d8: 00800044 movi r2,1 + 80442dc: 40800115 stw r2,4(r8) + 80442e0: 44000015 stw r16,0(r8) + 80442e4: d8c01e15 stw r3,120(sp) + 80442e8: dd401d15 stw r21,116(sp) + 80442ec: a8800210 cmplti r2,r21,8 + 80442f0: 10013e26 beq r2,zero,80447ec <___svfprintf_internal_r+0x14ac> + 80442f4: d8800b17 ldw r2,44(sp) + 80442f8: d9000d17 ldw r4,52(sp) + 80442fc: ad400044 addi r21,r21,1 + 8044300: 1887883a add r3,r3,r2 + 8044304: 50800115 stw r2,4(r10) + 8044308: 51000015 stw r4,0(r10) + 804430c: d8c01e15 stw r3,120(sp) + 8044310: dd401d15 stw r21,116(sp) + 8044314: a8800208 cmpgei r2,r21,8 + 8044318: 10012b1e bne r2,zero,80447c8 <___svfprintf_internal_r+0x1488> + 804431c: 52800204 addi r10,r10,8 + 8044320: d8800817 ldw r2,32(sp) + 8044324: d9000917 ldw r4,36(sp) + 8044328: d9400a17 ldw r5,40(sp) + 804432c: 52000204 addi r8,r10,8 + 8044330: 12ffffc4 addi r11,r2,-1 + 8044334: af000044 addi fp,r21,1 + 8044338: 000d883a mov r6,zero + 804433c: 000f883a mov r7,zero + 8044340: d8c01215 stw r3,72(sp) + 8044344: da800f15 stw r10,60(sp) + 8044348: da000e15 stw r8,56(sp) + 804434c: dac00715 stw r11,28(sp) + 8044350: df001015 stw fp,64(sp) + 8044354: 800e3000 call 800e300 <__eqdf2> + 8044358: dac00717 ldw r11,28(sp) + 804435c: da000e17 ldw r8,56(sp) + 8044360: da800f17 ldw r10,60(sp) + 8044364: db401017 ldw r13,64(sp) + 8044368: d8c01217 ldw r3,72(sp) + 804436c: 1000e826 beq r2,zero,8044710 <___svfprintf_internal_r+0x13d0> + 8044370: 84000044 addi r16,r16,1 + 8044374: 1ac7883a add r3,r3,r11 + 8044378: df001d15 stw fp,116(sp) + 804437c: 54000015 stw r16,0(r10) + 8044380: 52c00115 stw r11,4(r10) + 8044384: d8c01e15 stw r3,120(sp) + 8044388: e7000208 cmpgei fp,fp,8 + 804438c: e001da1e bne fp,zero,8044af8 <___svfprintf_internal_r+0x17b8> + 8044390: 50800404 addi r2,r10,16 + 8044394: af000084 addi fp,r21,2 + 8044398: 4015883a mov r10,r8 + 804439c: 1011883a mov r8,r2 + 80443a0: d9001117 ldw r4,68(sp) + 80443a4: d8801844 addi r2,sp,97 + 80443a8: df001d15 stw fp,116(sp) + 80443ac: 20c7883a add r3,r4,r3 + 80443b0: 50800015 stw r2,0(r10) + 80443b4: 51000115 stw r4,4(r10) + 80443b8: d8c01e15 stw r3,120(sp) + 80443bc: e7000210 cmplti fp,fp,8 + 80443c0: e03d8f1e bne fp,zero,8043a00 <___svfprintf_internal_r+0x6c0> + 80443c4: d9000517 ldw r4,20(sp) + 80443c8: d9801c04 addi r6,sp,112 + 80443cc: 980b883a mov r5,r19 + 80443d0: 80456900 call 8045690 <__ssprint_r> + 80443d4: 103c991e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 80443d8: d8c01e17 ldw r3,120(sp) + 80443dc: b811883a mov r8,r23 + 80443e0: 003d8706 br 8043a00 <___svfprintf_internal_r+0x6c0> + 80443e4: 9019883a mov r12,r18 + 80443e8: 003e6806 br 8043d8c <___svfprintf_internal_r+0xa4c> + 80443ec: 03020174 movhi r12,2053 + 80443f0: 39000450 cmplti r4,r7,17 + 80443f4: 632e3844 addi r12,r12,-18207 + 80443f8: d8801d17 ldw r2,116(sp) + 80443fc: 20002b1e bne r4,zero,80444ac <___svfprintf_internal_r+0x116c> + 8044400: dc801015 stw r18,64(sp) + 8044404: dc001215 stw r16,72(sp) + 8044408: dc401315 stw r17,76(sp) + 804440c: 03c00404 movi r15,16 + 8044410: db800e15 stw r14,56(sp) + 8044414: db400f15 stw r13,60(sp) + 8044418: dac01415 stw r11,80(sp) + 804441c: 3821883a mov r16,r7 + 8044420: dc400517 ldw r17,20(sp) + 8044424: 6025883a mov r18,r12 + 8044428: 00000406 br 804443c <___svfprintf_internal_r+0x10fc> + 804442c: 843ffc04 addi r16,r16,-16 + 8044430: 81000448 cmpgei r4,r16,17 + 8044434: 42000204 addi r8,r8,8 + 8044438: 20001426 beq r4,zero,804448c <___svfprintf_internal_r+0x114c> + 804443c: 10800044 addi r2,r2,1 + 8044440: 18c00404 addi r3,r3,16 + 8044444: 44800015 stw r18,0(r8) + 8044448: 43c00115 stw r15,4(r8) + 804444c: d8c01e15 stw r3,120(sp) + 8044450: d8801d15 stw r2,116(sp) + 8044454: 11000208 cmpgei r4,r2,8 + 8044458: 203ff426 beq r4,zero,804442c <___svfprintf_internal_r+0x10ec> + 804445c: d9801c04 addi r6,sp,112 + 8044460: 980b883a mov r5,r19 + 8044464: 8809883a mov r4,r17 + 8044468: 80456900 call 8045690 <__ssprint_r> + 804446c: 103c731e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 8044470: 843ffc04 addi r16,r16,-16 + 8044474: 81000448 cmpgei r4,r16,17 + 8044478: d8c01e17 ldw r3,120(sp) + 804447c: d8801d17 ldw r2,116(sp) + 8044480: b811883a mov r8,r23 + 8044484: 03c00404 movi r15,16 + 8044488: 203fec1e bne r4,zero,804443c <___svfprintf_internal_r+0x10fc> + 804448c: 800f883a mov r7,r16 + 8044490: 9019883a mov r12,r18 + 8044494: db800e17 ldw r14,56(sp) + 8044498: db400f17 ldw r13,60(sp) + 804449c: dc401317 ldw r17,76(sp) + 80444a0: dac01417 ldw r11,80(sp) + 80444a4: dc001217 ldw r16,72(sp) + 80444a8: dc801017 ldw r18,64(sp) + 80444ac: 10800044 addi r2,r2,1 + 80444b0: 19c7883a add r3,r3,r7 + 80444b4: d8801d15 stw r2,116(sp) + 80444b8: 43000015 stw r12,0(r8) + 80444bc: 41c00115 stw r7,4(r8) + 80444c0: d8c01e15 stw r3,120(sp) + 80444c4: 10800208 cmpgei r2,r2,8 + 80444c8: 1001be1e bne r2,zero,8044bc4 <___svfprintf_internal_r+0x1884> + 80444cc: 42000204 addi r8,r8,8 + 80444d0: 003d2006 br 8043954 <___svfprintf_internal_r+0x614> + 80444d4: d9000517 ldw r4,20(sp) + 80444d8: d9801c04 addi r6,sp,112 + 80444dc: 980b883a mov r5,r19 + 80444e0: dac01015 stw r11,64(sp) + 80444e4: db400f15 stw r13,60(sp) + 80444e8: db800e15 stw r14,56(sp) + 80444ec: 80456900 call 8045690 <__ssprint_r> + 80444f0: 103c521e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 80444f4: d8c01e17 ldw r3,120(sp) + 80444f8: b811883a mov r8,r23 + 80444fc: dac01017 ldw r11,64(sp) + 8044500: db400f17 ldw r13,60(sp) + 8044504: db800e17 ldw r14,56(sp) + 8044508: 003d2006 br 804398c <___svfprintf_internal_r+0x64c> + 804450c: d9000517 ldw r4,20(sp) + 8044510: d9801c04 addi r6,sp,112 + 8044514: 980b883a mov r5,r19 + 8044518: dac00f15 stw r11,60(sp) + 804451c: db400e15 stw r13,56(sp) + 8044520: 80456900 call 8045690 <__ssprint_r> + 8044524: 103c451e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 8044528: d8c01e17 ldw r3,120(sp) + 804452c: b811883a mov r8,r23 + 8044530: dac00f17 ldw r11,60(sp) + 8044534: db400e17 ldw r13,56(sp) + 8044538: 003d2106 br 80439c0 <___svfprintf_internal_r+0x680> + 804453c: d9000c17 ldw r4,48(sp) + 8044540: b821883a mov r16,r23 + 8044544: a08003cc andi r2,r20,15 + 8044548: a806973a slli r3,r21,28 + 804454c: 2085883a add r2,r4,r2 + 8044550: a028d13a srli r20,r20,4 + 8044554: 10800003 ldbu r2,0(r2) + 8044558: a82ad13a srli r21,r21,4 + 804455c: 843fffc4 addi r16,r16,-1 + 8044560: 1d28b03a or r20,r3,r20 + 8044564: 80800005 stb r2,0(r16) + 8044568: a544b03a or r2,r20,r21 + 804456c: 103ff51e bne r2,zero,8044544 <___svfprintf_internal_r+0x1204> + 8044570: bc2bc83a sub r21,r23,r16 + 8044574: 6025883a mov r18,r12 + 8044578: 003e6206 br 8043f04 <___svfprintf_internal_r+0xbc4> + 804457c: d9001617 ldw r4,88(sp) + 8044580: 0101680e bge zero,r4,8044b24 <___svfprintf_internal_r+0x17e4> + 8044584: d8800817 ldw r2,32(sp) + 8044588: d9000717 ldw r4,28(sp) + 804458c: 1039883a mov fp,r2 + 8044590: 20810516 blt r4,r2,80449a8 <___svfprintf_internal_r+0x1668> + 8044594: 07000a0e bge zero,fp,80445c0 <___svfprintf_internal_r+0x1280> + 8044598: d8801d17 ldw r2,116(sp) + 804459c: 1f07883a add r3,r3,fp + 80445a0: 44000015 stw r16,0(r8) + 80445a4: 10800044 addi r2,r2,1 + 80445a8: d8801d15 stw r2,116(sp) + 80445ac: 47000115 stw fp,4(r8) + 80445b0: d8c01e15 stw r3,120(sp) + 80445b4: 10800208 cmpgei r2,r2,8 + 80445b8: 1003011e bne r2,zero,80451c0 <___svfprintf_internal_r+0x1e80> + 80445bc: 42000204 addi r8,r8,8 + 80445c0: e0010616 blt fp,zero,80449dc <___svfprintf_internal_r+0x169c> + 80445c4: d8800717 ldw r2,28(sp) + 80445c8: 1739c83a sub fp,r2,fp + 80445cc: 07011916 blt zero,fp,8044a34 <___svfprintf_internal_r+0x16f4> + 80445d0: d9001617 ldw r4,88(sp) + 80445d4: d8800817 ldw r2,32(sp) + 80445d8: 2080f60e bge r4,r2,80449b4 <___svfprintf_internal_r+0x1674> + 80445dc: d8800d17 ldw r2,52(sp) + 80445e0: d9400b17 ldw r5,44(sp) + 80445e4: 40800015 stw r2,0(r8) + 80445e8: d8801d17 ldw r2,116(sp) + 80445ec: 1947883a add r3,r3,r5 + 80445f0: 41400115 stw r5,4(r8) + 80445f4: 10800044 addi r2,r2,1 + 80445f8: d8801d15 stw r2,116(sp) + 80445fc: d8c01e15 stw r3,120(sp) + 8044600: 10800208 cmpgei r2,r2,8 + 8044604: 1002a61e bne r2,zero,80450a0 <___svfprintf_internal_r+0x1d60> + 8044608: 42000204 addi r8,r8,8 + 804460c: d8800817 ldw r2,32(sp) + 8044610: d9400717 ldw r5,28(sp) + 8044614: 1105c83a sub r2,r2,r4 + 8044618: 2901300e bge r5,r4,8044adc <___svfprintf_internal_r+0x179c> + 804461c: 1039883a mov fp,r2 + 8044620: 07000c0e bge zero,fp,8044654 <___svfprintf_internal_r+0x1314> + 8044624: d9000717 ldw r4,28(sp) + 8044628: 1f07883a add r3,r3,fp + 804462c: 47000115 stw fp,4(r8) + 8044630: 8121883a add r16,r16,r4 + 8044634: d9001d17 ldw r4,116(sp) + 8044638: 44000015 stw r16,0(r8) + 804463c: d8c01e15 stw r3,120(sp) + 8044640: 21000044 addi r4,r4,1 + 8044644: d9001d15 stw r4,116(sp) + 8044648: 21000208 cmpgei r4,r4,8 + 804464c: 2002e71e bne r4,zero,80451ec <___svfprintf_internal_r+0x1eac> + 8044650: 42000204 addi r8,r8,8 + 8044654: e000010e bge fp,zero,804465c <___svfprintf_internal_r+0x131c> + 8044658: 0039883a mov fp,zero + 804465c: 1739c83a sub fp,r2,fp + 8044660: 073ce70e bge zero,fp,8043a00 <___svfprintf_internal_r+0x6c0> + 8044664: 03020174 movhi r12,2053 + 8044668: e1000450 cmplti r4,fp,17 + 804466c: 632e3444 addi r12,r12,-18223 + 8044670: d8801d17 ldw r2,116(sp) + 8044674: 2002741e bne r4,zero,8045048 <___svfprintf_internal_r+0x1d08> + 8044678: dc400715 stw r17,28(sp) + 804467c: 05400404 movi r21,16 + 8044680: dc000517 ldw r16,20(sp) + 8044684: 6023883a mov r17,r12 + 8044688: 00000406 br 804469c <___svfprintf_internal_r+0x135c> + 804468c: 42000204 addi r8,r8,8 + 8044690: e73ffc04 addi fp,fp,-16 + 8044694: e1000448 cmpgei r4,fp,17 + 8044698: 20026926 beq r4,zero,8045040 <___svfprintf_internal_r+0x1d00> + 804469c: 10800044 addi r2,r2,1 + 80446a0: 18c00404 addi r3,r3,16 + 80446a4: 44400015 stw r17,0(r8) + 80446a8: 45400115 stw r21,4(r8) + 80446ac: d8c01e15 stw r3,120(sp) + 80446b0: d8801d15 stw r2,116(sp) + 80446b4: 11000208 cmpgei r4,r2,8 + 80446b8: 203ff426 beq r4,zero,804468c <___svfprintf_internal_r+0x134c> + 80446bc: d9801c04 addi r6,sp,112 + 80446c0: 980b883a mov r5,r19 + 80446c4: 8009883a mov r4,r16 + 80446c8: 80456900 call 8045690 <__ssprint_r> + 80446cc: 103bdb1e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 80446d0: d8c01e17 ldw r3,120(sp) + 80446d4: d8801d17 ldw r2,116(sp) + 80446d8: b811883a mov r8,r23 + 80446dc: 003fec06 br 8044690 <___svfprintf_internal_r+0x1350> + 80446e0: 9080004c andi r2,r18,1 + 80446e4: 103efc1e bne r2,zero,80442d8 <___svfprintf_internal_r+0xf98> + 80446e8: 00800044 movi r2,1 + 80446ec: dd401d15 stw r21,116(sp) + 80446f0: 44000015 stw r16,0(r8) + 80446f4: 40800115 stw r2,4(r8) + 80446f8: d8c01e15 stw r3,120(sp) + 80446fc: ad400208 cmpgei r21,r21,8 + 8044700: a800fd1e bne r21,zero,8044af8 <___svfprintf_internal_r+0x17b8> + 8044704: e7000084 addi fp,fp,2 + 8044708: 42000404 addi r8,r8,16 + 804470c: 003f2406 br 80443a0 <___svfprintf_internal_r+0x1060> + 8044710: 02ff230e bge zero,r11,80443a0 <___svfprintf_internal_r+0x1060> + 8044714: 58800450 cmplti r2,r11,17 + 8044718: 03020174 movhi r12,2053 + 804471c: 10032f1e bne r2,zero,80453dc <___svfprintf_internal_r+0x209c> + 8044720: 632e3444 addi r12,r12,-18223 + 8044724: dc800715 stw r18,28(sp) + 8044728: dc400e15 stw r17,56(sp) + 804472c: 04000404 movi r16,16 + 8044730: 5823883a mov r17,r11 + 8044734: df000517 ldw fp,20(sp) + 8044738: 6025883a mov r18,r12 + 804473c: 682b883a mov r21,r13 + 8044740: 00000506 br 8044758 <___svfprintf_internal_r+0x1418> + 8044744: 52800204 addi r10,r10,8 + 8044748: 8c7ffc04 addi r17,r17,-16 + 804474c: 88800448 cmpgei r2,r17,17 + 8044750: 10018e26 beq r2,zero,8044d8c <___svfprintf_internal_r+0x1a4c> + 8044754: ad400044 addi r21,r21,1 + 8044758: 18c00404 addi r3,r3,16 + 804475c: 54800015 stw r18,0(r10) + 8044760: 54000115 stw r16,4(r10) + 8044764: d8c01e15 stw r3,120(sp) + 8044768: dd401d15 stw r21,116(sp) + 804476c: a8800208 cmpgei r2,r21,8 + 8044770: 103ff426 beq r2,zero,8044744 <___svfprintf_internal_r+0x1404> + 8044774: d9801c04 addi r6,sp,112 + 8044778: 980b883a mov r5,r19 + 804477c: e009883a mov r4,fp + 8044780: 80456900 call 8045690 <__ssprint_r> + 8044784: 103bad1e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 8044788: dd401d17 ldw r21,116(sp) + 804478c: d8c01e17 ldw r3,120(sp) + 8044790: b815883a mov r10,r23 + 8044794: 003fec06 br 8044748 <___svfprintf_internal_r+0x1408> + 8044798: d9000517 ldw r4,20(sp) + 804479c: d9801c04 addi r6,sp,112 + 80447a0: 980b883a mov r5,r19 + 80447a4: 80456900 call 8045690 <__ssprint_r> + 80447a8: 103ba41e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 80447ac: d8c01e17 ldw r3,120(sp) + 80447b0: b811883a mov r8,r23 + 80447b4: 003c8606 br 80439d0 <___svfprintf_internal_r+0x690> + 80447b8: 002b883a mov r21,zero + 80447bc: 003c0606 br 80437d8 <___svfprintf_internal_r+0x498> + 80447c0: b025883a mov r18,r22 + 80447c4: 003b2206 br 8043450 <___svfprintf_internal_r+0x110> + 80447c8: d9000517 ldw r4,20(sp) + 80447cc: d9801c04 addi r6,sp,112 + 80447d0: 980b883a mov r5,r19 + 80447d4: 80456900 call 8045690 <__ssprint_r> + 80447d8: 103b981e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 80447dc: d8c01e17 ldw r3,120(sp) + 80447e0: dd401d17 ldw r21,116(sp) + 80447e4: b815883a mov r10,r23 + 80447e8: 003ecd06 br 8044320 <___svfprintf_internal_r+0xfe0> + 80447ec: d9000517 ldw r4,20(sp) + 80447f0: d9801c04 addi r6,sp,112 + 80447f4: 980b883a mov r5,r19 + 80447f8: 80456900 call 8045690 <__ssprint_r> + 80447fc: 103b8f1e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 8044800: d8c01e17 ldw r3,120(sp) + 8044804: dd401d17 ldw r21,116(sp) + 8044808: b815883a mov r10,r23 + 804480c: 003eb906 br 80442f4 <___svfprintf_internal_r+0xfb4> + 8044810: b821883a mov r16,r23 + 8044814: 003dbb06 br 8043f04 <___svfprintf_internal_r+0xbc4> + 8044818: d9000917 ldw r4,36(sp) + 804481c: d9400a17 ldw r5,40(sp) + 8044820: da000f15 stw r8,60(sp) + 8044824: 200d883a mov r6,r4 + 8044828: 280f883a mov r7,r5 + 804482c: dac00e15 stw r11,56(sp) + 8044830: db000715 stw r12,28(sp) + 8044834: 800f5580 call 800f558 <__unorddf2> + 8044838: db000717 ldw r12,28(sp) + 804483c: dac00e17 ldw r11,56(sp) + 8044840: da000f17 ldw r8,60(sp) + 8044844: 1002d91e bne r2,zero,80453ac <___svfprintf_internal_r+0x206c> + 8044848: 00fff7c4 movi r3,-33 + 804484c: e0c6703a and r3,fp,r3 + 8044850: 58bfffe0 cmpeqi r2,r11,-1 + 8044854: d8c00715 stw r3,28(sp) + 8044858: 1002621e bne r2,zero,80451e4 <___svfprintf_internal_r+0x1ea4> + 804485c: 188011d8 cmpnei r2,r3,71 + 8044860: 1000a226 beq r2,zero,8044aec <___svfprintf_internal_r+0x17ac> + 8044864: d8800a17 ldw r2,40(sp) + 8044868: 64804014 ori r18,r12,256 + 804486c: 10021516 blt r2,zero,80450c4 <___svfprintf_internal_r+0x1d84> + 8044870: dd000a17 ldw r20,40(sp) + 8044874: d8000e05 stb zero,56(sp) + 8044878: e08019a0 cmpeqi r2,fp,102 + 804487c: d8800f15 stw r2,60(sp) + 8044880: 1001531e bne r2,zero,8044dd0 <___svfprintf_internal_r+0x1a90> + 8044884: e08011a0 cmpeqi r2,fp,70 + 8044888: 1001511e bne r2,zero,8044dd0 <___svfprintf_internal_r+0x1a90> + 804488c: d8800717 ldw r2,28(sp) + 8044890: da001215 stw r8,72(sp) + 8044894: db001015 stw r12,64(sp) + 8044898: 10801158 cmpnei r2,r2,69 + 804489c: 10022b26 beq r2,zero,804514c <___svfprintf_internal_r+0x1e0c> + 80448a0: d8801a04 addi r2,sp,104 + 80448a4: d8800315 stw r2,12(sp) + 80448a8: d9400917 ldw r5,36(sp) + 80448ac: d8801704 addi r2,sp,92 + 80448b0: d9000517 ldw r4,20(sp) + 80448b4: d8800215 stw r2,8(sp) + 80448b8: d8801604 addi r2,sp,88 + 80448bc: dac00015 stw r11,0(sp) + 80448c0: d8800115 stw r2,4(sp) + 80448c4: 01c00084 movi r7,2 + 80448c8: a00d883a mov r6,r20 + 80448cc: dac00815 stw r11,32(sp) + 80448d0: 80053ec0 call 80053ec <_dtoa_r> + 80448d4: dac00817 ldw r11,32(sp) + 80448d8: 1021883a mov r16,r2 + 80448dc: e08019d8 cmpnei r2,fp,103 + 80448e0: db001017 ldw r12,64(sp) + 80448e4: da001217 ldw r8,72(sp) + 80448e8: 582b883a mov r21,r11 + 80448ec: 1002291e bne r2,zero,8045194 <___svfprintf_internal_r+0x1e54> + 80448f0: 6080004c andi r2,r12,1 + 80448f4: 1002291e bne r2,zero,804519c <___svfprintf_internal_r+0x1e5c> + 80448f8: d8c01617 ldw r3,88(sp) + 80448fc: d8800717 ldw r2,28(sp) + 8044900: d8c00715 stw r3,28(sp) + 8044904: d8c01a17 ldw r3,104(sp) + 8044908: 108011e0 cmpeqi r2,r2,71 + 804490c: 1c07c83a sub r3,r3,r16 + 8044910: d8c00815 stw r3,32(sp) + 8044914: 10017126 beq r2,zero,8044edc <___svfprintf_internal_r+0x1b9c> + 8044918: d8c00717 ldw r3,28(sp) + 804491c: 18bfff50 cmplti r2,r3,-3 + 8044920: 10016d1e bne r2,zero,8044ed8 <___svfprintf_internal_r+0x1b98> + 8044924: 58c16c16 blt r11,r3,8044ed8 <___svfprintf_internal_r+0x1b98> + 8044928: d8800717 ldw r2,28(sp) + 804492c: d8c00817 ldw r3,32(sp) + 8044930: 10c23d16 blt r2,r3,8045228 <___svfprintf_internal_r+0x1ee8> + 8044934: 6300004c andi r12,r12,1 + 8044938: 6002731e bne r12,zero,8045308 <___svfprintf_internal_r+0x1fc8> + 804493c: 1029883a mov r20,r2 + 8044940: 1000010e bge r2,zero,8044948 <___svfprintf_internal_r+0x1608> + 8044944: 0029883a mov r20,zero + 8044948: dd400717 ldw r21,28(sp) + 804494c: 070019c4 movi fp,103 + 8044950: d8800e07 ldb r2,56(sp) + 8044954: 10021726 beq r2,zero,80451b4 <___svfprintf_internal_r+0x1e74> + 8044958: 00800b44 movi r2,45 + 804495c: d8801545 stb r2,85(sp) + 8044960: 0017883a mov r11,zero + 8044964: 003d6f06 br 8043f24 <___svfprintf_internal_r+0xbe4> + 8044968: d9400417 ldw r5,16(sp) + 804496c: 20800017 ldw r2,0(r4) + 8044970: d8c00615 stw r3,24(sp) + 8044974: 2809d7fa srai r4,r5,31 + 8044978: 11400015 stw r5,0(r2) + 804497c: 11000115 stw r4,4(r2) + 8044980: 003a9506 br 80433d8 <___svfprintf_internal_r+0x98> + 8044984: 00800c04 movi r2,48 + 8044988: d8801585 stb r2,86(sp) + 804498c: df0015c5 stb fp,87(sp) + 8044990: 63000094 ori r12,r12,2 + 8044994: 00800084 movi r2,2 + 8044998: 003c9006 br 8043bdc <___svfprintf_internal_r+0x89c> + 804499c: 0463c83a sub r17,zero,r17 + 80449a0: d8800615 stw r2,24(sp) + 80449a4: 003b5f06 br 8043724 <___svfprintf_internal_r+0x3e4> + 80449a8: 2039883a mov fp,r4 + 80449ac: 073efa16 blt zero,fp,8044598 <___svfprintf_internal_r+0x1258> + 80449b0: 003f0306 br 80445c0 <___svfprintf_internal_r+0x1280> + 80449b4: 9080004c andi r2,r18,1 + 80449b8: 103f081e bne r2,zero,80445dc <___svfprintf_internal_r+0x129c> + 80449bc: d8800817 ldw r2,32(sp) + 80449c0: d9400717 ldw r5,28(sp) + 80449c4: 1105c83a sub r2,r2,r4 + 80449c8: 2900440e bge r5,r4,8044adc <___svfprintf_internal_r+0x179c> + 80449cc: 1039883a mov fp,r2 + 80449d0: 003f2006 br 8044654 <___svfprintf_internal_r+0x1314> + 80449d4: d8c01e17 ldw r3,120(sp) + 80449d8: 003c0906 br 8043a00 <___svfprintf_internal_r+0x6c0> + 80449dc: d8800717 ldw r2,28(sp) + 80449e0: 0039883a mov fp,zero + 80449e4: 1739c83a sub fp,r2,fp + 80449e8: 073ef90e bge zero,fp,80445d0 <___svfprintf_internal_r+0x1290> + 80449ec: 00001106 br 8044a34 <___svfprintf_internal_r+0x16f4> + 80449f0: 8009883a mov r4,r16 + 80449f4: 8002dac0 call 8002dac + 80449f8: 102b883a mov r21,r2 + 80449fc: 1029883a mov r20,r2 + 8044a00: dc800615 stw r18,24(sp) + 8044a04: db000717 ldw r12,28(sp) + 8044a08: da000e17 ldw r8,56(sp) + 8044a0c: 003bc606 br 8043928 <___svfprintf_internal_r+0x5e8> + 8044a10: d9000517 ldw r4,20(sp) + 8044a14: 01401004 movi r5,64 + 8044a18: 8007ddc0 call 8007ddc <_malloc_r> + 8044a1c: 98800015 stw r2,0(r19) + 8044a20: 98800415 stw r2,16(r19) + 8044a24: 10028626 beq r2,zero,8045440 <___svfprintf_internal_r+0x2100> + 8044a28: 00801004 movi r2,64 + 8044a2c: 98800515 stw r2,20(r19) + 8044a30: 003a5d06 br 80433a8 <___svfprintf_internal_r+0x68> + 8044a34: 03020174 movhi r12,2053 + 8044a38: e1000450 cmplti r4,fp,17 + 8044a3c: 632e3444 addi r12,r12,-18223 + 8044a40: d8801d17 ldw r2,116(sp) + 8044a44: 2001741e bne r4,zero,8045018 <___svfprintf_internal_r+0x1cd8> + 8044a48: b009883a mov r4,r22 + 8044a4c: dc800e15 stw r18,56(sp) + 8044a50: dc000f15 stw r16,60(sp) + 8044a54: 882d883a mov r22,r17 + 8044a58: 05400404 movi r21,16 + 8044a5c: e023883a mov r17,fp + 8044a60: dc000517 ldw r16,20(sp) + 8044a64: 6025883a mov r18,r12 + 8044a68: 2039883a mov fp,r4 + 8044a6c: 00000406 br 8044a80 <___svfprintf_internal_r+0x1740> + 8044a70: 42000204 addi r8,r8,8 + 8044a74: 8c7ffc04 addi r17,r17,-16 + 8044a78: 89000448 cmpgei r4,r17,17 + 8044a7c: 20015f26 beq r4,zero,8044ffc <___svfprintf_internal_r+0x1cbc> + 8044a80: 10800044 addi r2,r2,1 + 8044a84: 18c00404 addi r3,r3,16 + 8044a88: 44800015 stw r18,0(r8) + 8044a8c: 45400115 stw r21,4(r8) + 8044a90: d8c01e15 stw r3,120(sp) + 8044a94: d8801d15 stw r2,116(sp) + 8044a98: 11000208 cmpgei r4,r2,8 + 8044a9c: 203ff426 beq r4,zero,8044a70 <___svfprintf_internal_r+0x1730> + 8044aa0: d9801c04 addi r6,sp,112 + 8044aa4: 980b883a mov r5,r19 + 8044aa8: 8009883a mov r4,r16 + 8044aac: 80456900 call 8045690 <__ssprint_r> + 8044ab0: 103ae21e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 8044ab4: d8c01e17 ldw r3,120(sp) + 8044ab8: d8801d17 ldw r2,116(sp) + 8044abc: b811883a mov r8,r23 + 8044ac0: 003fec06 br 8044a74 <___svfprintf_internal_r+0x1734> + 8044ac4: d8800617 ldw r2,24(sp) + 8044ac8: 10800017 ldw r2,0(r2) + 8044acc: d8c00615 stw r3,24(sp) + 8044ad0: d8c00417 ldw r3,16(sp) + 8044ad4: 10c00015 stw r3,0(r2) + 8044ad8: 003a3f06 br 80433d8 <___svfprintf_internal_r+0x98> + 8044adc: d9000817 ldw r4,32(sp) + 8044ae0: d9400717 ldw r5,28(sp) + 8044ae4: 2179c83a sub fp,r4,r5 + 8044ae8: 003ecd06 br 8044620 <___svfprintf_internal_r+0x12e0> + 8044aec: 583f5d1e bne r11,zero,8044864 <___svfprintf_internal_r+0x1524> + 8044af0: 02c00044 movi r11,1 + 8044af4: 003f5b06 br 8044864 <___svfprintf_internal_r+0x1524> + 8044af8: d9000517 ldw r4,20(sp) + 8044afc: d9801c04 addi r6,sp,112 + 8044b00: 980b883a mov r5,r19 + 8044b04: 80456900 call 8045690 <__ssprint_r> + 8044b08: 103acc1e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 8044b0c: df001d17 ldw fp,116(sp) + 8044b10: d8c01e17 ldw r3,120(sp) + 8044b14: da002b04 addi r8,sp,172 + 8044b18: e7000044 addi fp,fp,1 + 8044b1c: b815883a mov r10,r23 + 8044b20: 003e1f06 br 80443a0 <___svfprintf_internal_r+0x1060> + 8044b24: d8801d17 ldw r2,116(sp) + 8044b28: 01420134 movhi r5,2052 + 8044b2c: 295d2704 addi r5,r5,29852 + 8044b30: 10800044 addi r2,r2,1 + 8044b34: 18c00044 addi r3,r3,1 + 8044b38: 41400015 stw r5,0(r8) + 8044b3c: 01400044 movi r5,1 + 8044b40: d8801d15 stw r2,116(sp) + 8044b44: 41400115 stw r5,4(r8) + 8044b48: d8c01e15 stw r3,120(sp) + 8044b4c: 10800208 cmpgei r2,r2,8 + 8044b50: 10014a1e bne r2,zero,804507c <___svfprintf_internal_r+0x1d3c> + 8044b54: 42000204 addi r8,r8,8 + 8044b58: 2000541e bne r4,zero,8044cac <___svfprintf_internal_r+0x196c> + 8044b5c: d9000817 ldw r4,32(sp) + 8044b60: 9080004c andi r2,r18,1 + 8044b64: 1104b03a or r2,r2,r4 + 8044b68: 103ba526 beq r2,zero,8043a00 <___svfprintf_internal_r+0x6c0> + 8044b6c: d8800d17 ldw r2,52(sp) + 8044b70: d9000b17 ldw r4,44(sp) + 8044b74: 40800015 stw r2,0(r8) + 8044b78: d8801d17 ldw r2,116(sp) + 8044b7c: 20c7883a add r3,r4,r3 + 8044b80: 41000115 stw r4,4(r8) + 8044b84: 10800044 addi r2,r2,1 + 8044b88: d8c01e15 stw r3,120(sp) + 8044b8c: d8801d15 stw r2,116(sp) + 8044b90: 11000208 cmpgei r4,r2,8 + 8044b94: 2001551e bne r4,zero,80450ec <___svfprintf_internal_r+0x1dac> + 8044b98: 42000204 addi r8,r8,8 + 8044b9c: d9000817 ldw r4,32(sp) + 8044ba0: 10800044 addi r2,r2,1 + 8044ba4: d8801d15 stw r2,116(sp) + 8044ba8: 20c7883a add r3,r4,r3 + 8044bac: 44000015 stw r16,0(r8) + 8044bb0: 41000115 stw r4,4(r8) + 8044bb4: d8c01e15 stw r3,120(sp) + 8044bb8: 10800208 cmpgei r2,r2,8 + 8044bbc: 103b8f26 beq r2,zero,80439fc <___svfprintf_internal_r+0x6bc> + 8044bc0: 003e0006 br 80443c4 <___svfprintf_internal_r+0x1084> + 8044bc4: d9000517 ldw r4,20(sp) + 8044bc8: d9801c04 addi r6,sp,112 + 8044bcc: 980b883a mov r5,r19 + 8044bd0: dac01015 stw r11,64(sp) + 8044bd4: db400f15 stw r13,60(sp) + 8044bd8: db800e15 stw r14,56(sp) + 8044bdc: 80456900 call 8045690 <__ssprint_r> + 8044be0: 103a961e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 8044be4: d8c01e17 ldw r3,120(sp) + 8044be8: b811883a mov r8,r23 + 8044bec: dac01017 ldw r11,64(sp) + 8044bf0: db400f17 ldw r13,60(sp) + 8044bf4: db800e17 ldw r14,56(sp) + 8044bf8: 003b5606 br 8043954 <___svfprintf_internal_r+0x614> + 8044bfc: d9000517 ldw r4,20(sp) + 8044c00: d9801c04 addi r6,sp,112 + 8044c04: 980b883a mov r5,r19 + 8044c08: 80456900 call 8045690 <__ssprint_r> + 8044c0c: 103a8b1e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 8044c10: b811883a mov r8,r23 + 8044c14: 003d0206 br 8044020 <___svfprintf_internal_r+0xce0> + 8044c18: d9000517 ldw r4,20(sp) + 8044c1c: d9801c04 addi r6,sp,112 + 8044c20: 980b883a mov r5,r19 + 8044c24: dac00e15 stw r11,56(sp) + 8044c28: 80456900 call 8045690 <__ssprint_r> + 8044c2c: 103a831e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 8044c30: d8c01e17 ldw r3,120(sp) + 8044c34: b811883a mov r8,r23 + 8044c38: dac00e17 ldw r11,56(sp) + 8044c3c: 003b6206 br 80439c8 <___svfprintf_internal_r+0x688> + 8044c40: 10c00060 cmpeqi r3,r2,1 + 8044c44: 9019883a mov r12,r18 + 8044c48: 183c5226 beq r3,zero,8043d94 <___svfprintf_internal_r+0xa54> + 8044c4c: 003ca806 br 8043ef0 <___svfprintf_internal_r+0xbb0> + 8044c50: b7000043 ldbu fp,1(r22) + 8044c54: 63000814 ori r12,r12,32 + 8044c58: b5800044 addi r22,r22,1 + 8044c5c: e2803fcc andi r10,fp,255 + 8044c60: 5280201c xori r10,r10,128 + 8044c64: 52bfe004 addi r10,r10,-128 + 8044c68: 003a0106 br 8043470 <___svfprintf_internal_r+0x130> + 8044c6c: d9000517 ldw r4,20(sp) + 8044c70: d9801c04 addi r6,sp,112 + 8044c74: 980b883a mov r5,r19 + 8044c78: 80456900 call 8045690 <__ssprint_r> + 8044c7c: 103a6f1e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 8044c80: d8c01e17 ldw r3,120(sp) + 8044c84: b811883a mov r8,r23 + 8044c88: 003cf706 br 8044068 <___svfprintf_internal_r+0xd28> + 8044c8c: 588001f0 cmpltui r2,r11,7 + 8044c90: 582b883a mov r21,r11 + 8044c94: 10011126 beq r2,zero,80450dc <___svfprintf_internal_r+0x1d9c> + 8044c98: 04020134 movhi r16,2052 + 8044c9c: a829883a mov r20,r21 + 8044ca0: dc800615 stw r18,24(sp) + 8044ca4: 841d2504 addi r16,r16,29844 + 8044ca8: 003b1f06 br 8043928 <___svfprintf_internal_r+0x5e8> + 8044cac: d8800d17 ldw r2,52(sp) + 8044cb0: d9400b17 ldw r5,44(sp) + 8044cb4: 40800015 stw r2,0(r8) + 8044cb8: d8801d17 ldw r2,116(sp) + 8044cbc: 28c7883a add r3,r5,r3 + 8044cc0: 41400115 stw r5,4(r8) + 8044cc4: 10800044 addi r2,r2,1 + 8044cc8: d8c01e15 stw r3,120(sp) + 8044ccc: d8801d15 stw r2,116(sp) + 8044cd0: 11400208 cmpgei r5,r2,8 + 8044cd4: 2801051e bne r5,zero,80450ec <___svfprintf_internal_r+0x1dac> + 8044cd8: 42000204 addi r8,r8,8 + 8044cdc: 203faf0e bge r4,zero,8044b9c <___svfprintf_internal_r+0x185c> + 8044ce0: 03020174 movhi r12,2053 + 8044ce4: 217ffc08 cmpgei r5,r4,-16 + 8044ce8: 632e3444 addi r12,r12,-18223 + 8044cec: 012bc83a sub r21,zero,r4 + 8044cf0: 2801711e bne r5,zero,80452b8 <___svfprintf_internal_r+0x1f78> + 8044cf4: dc000715 stw r16,28(sp) + 8044cf8: 07000404 movi fp,16 + 8044cfc: a821883a mov r16,r21 + 8044d00: 882b883a mov r21,r17 + 8044d04: 6023883a mov r17,r12 + 8044d08: 00000406 br 8044d1c <___svfprintf_internal_r+0x19dc> + 8044d0c: 42000204 addi r8,r8,8 + 8044d10: 843ffc04 addi r16,r16,-16 + 8044d14: 81000448 cmpgei r4,r16,17 + 8044d18: 20016326 beq r4,zero,80452a8 <___svfprintf_internal_r+0x1f68> + 8044d1c: 10800044 addi r2,r2,1 + 8044d20: 18c00404 addi r3,r3,16 + 8044d24: 44400015 stw r17,0(r8) + 8044d28: 47000115 stw fp,4(r8) + 8044d2c: d8c01e15 stw r3,120(sp) + 8044d30: d8801d15 stw r2,116(sp) + 8044d34: 11000208 cmpgei r4,r2,8 + 8044d38: 203ff426 beq r4,zero,8044d0c <___svfprintf_internal_r+0x19cc> + 8044d3c: d9000517 ldw r4,20(sp) + 8044d40: d9801c04 addi r6,sp,112 + 8044d44: 980b883a mov r5,r19 + 8044d48: 80456900 call 8045690 <__ssprint_r> + 8044d4c: 103a3b1e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 8044d50: d8c01e17 ldw r3,120(sp) + 8044d54: d8801d17 ldw r2,116(sp) + 8044d58: b811883a mov r8,r23 + 8044d5c: 003fec06 br 8044d10 <___svfprintf_internal_r+0x19d0> + 8044d60: 8819883a mov r12,r17 + 8044d64: dc400717 ldw r17,28(sp) + 8044d68: 10800044 addi r2,r2,1 + 8044d6c: 1c07883a add r3,r3,r16 + 8044d70: d8801d15 stw r2,116(sp) + 8044d74: 43000015 stw r12,0(r8) + 8044d78: 44000115 stw r16,4(r8) + 8044d7c: d8c01e15 stw r3,120(sp) + 8044d80: 10800208 cmpgei r2,r2,8 + 8044d84: 103b1d26 beq r2,zero,80439fc <___svfprintf_internal_r+0x6bc> + 8044d88: 003d8e06 br 80443c4 <___svfprintf_internal_r+0x1084> + 8044d8c: 8817883a mov r11,r17 + 8044d90: 9019883a mov r12,r18 + 8044d94: dc400e17 ldw r17,56(sp) + 8044d98: dc800717 ldw r18,28(sp) + 8044d9c: af000044 addi fp,r21,1 + 8044da0: 50800204 addi r2,r10,8 + 8044da4: 1ac7883a add r3,r3,r11 + 8044da8: 53000015 stw r12,0(r10) + 8044dac: 52c00115 stw r11,4(r10) + 8044db0: d8c01e15 stw r3,120(sp) + 8044db4: df001d15 stw fp,116(sp) + 8044db8: e1000208 cmpgei r4,fp,8 + 8044dbc: 203f4e1e bne r4,zero,8044af8 <___svfprintf_internal_r+0x17b8> + 8044dc0: e7000044 addi fp,fp,1 + 8044dc4: 12000204 addi r8,r2,8 + 8044dc8: 1015883a mov r10,r2 + 8044dcc: 003d7406 br 80443a0 <___svfprintf_internal_r+0x1060> + 8044dd0: d8801a04 addi r2,sp,104 + 8044dd4: d8800315 stw r2,12(sp) + 8044dd8: d9400917 ldw r5,36(sp) + 8044ddc: d8801704 addi r2,sp,92 + 8044de0: d9000517 ldw r4,20(sp) + 8044de4: d8800215 stw r2,8(sp) + 8044de8: d8801604 addi r2,sp,88 + 8044dec: dac00015 stw r11,0(sp) + 8044df0: d8800115 stw r2,4(sp) + 8044df4: 01c000c4 movi r7,3 + 8044df8: a00d883a mov r6,r20 + 8044dfc: da001215 stw r8,72(sp) + 8044e00: db001015 stw r12,64(sp) + 8044e04: dac00815 stw r11,32(sp) + 8044e08: 80053ec0 call 80053ec <_dtoa_r> + 8044e0c: dac00817 ldw r11,32(sp) + 8044e10: 1021883a mov r16,r2 + 8044e14: db001017 ldw r12,64(sp) + 8044e18: 12eb883a add r21,r2,r11 + 8044e1c: 80800007 ldb r2,0(r16) + 8044e20: da001217 ldw r8,72(sp) + 8044e24: 10800c20 cmpeqi r2,r2,48 + 8044e28: 10013e1e bne r2,zero,8045324 <___svfprintf_internal_r+0x1fe4> + 8044e2c: d8801617 ldw r2,88(sp) + 8044e30: a8ab883a add r21,r21,r2 + 8044e34: d9000917 ldw r4,36(sp) + 8044e38: 000d883a mov r6,zero + 8044e3c: 000f883a mov r7,zero + 8044e40: a00b883a mov r5,r20 + 8044e44: da001215 stw r8,72(sp) + 8044e48: dac01015 stw r11,64(sp) + 8044e4c: db000815 stw r12,32(sp) + 8044e50: 800e3000 call 800e300 <__eqdf2> + 8044e54: db000817 ldw r12,32(sp) + 8044e58: dac01017 ldw r11,64(sp) + 8044e5c: da001217 ldw r8,72(sp) + 8044e60: 10009c26 beq r2,zero,80450d4 <___svfprintf_internal_r+0x1d94> + 8044e64: d8801a17 ldw r2,104(sp) + 8044e68: 01000c04 movi r4,48 + 8044e6c: 1540052e bgeu r2,r21,8044e84 <___svfprintf_internal_r+0x1b44> + 8044e70: 10c00044 addi r3,r2,1 + 8044e74: d8c01a15 stw r3,104(sp) + 8044e78: 11000005 stb r4,0(r2) + 8044e7c: d8801a17 ldw r2,104(sp) + 8044e80: 157ffb36 bltu r2,r21,8044e70 <___svfprintf_internal_r+0x1b30> + 8044e84: 1405c83a sub r2,r2,r16 + 8044e88: d8c00717 ldw r3,28(sp) + 8044e8c: d8800815 stw r2,32(sp) + 8044e90: d8801617 ldw r2,88(sp) + 8044e94: 18c011d8 cmpnei r3,r3,71 + 8044e98: d8800715 stw r2,28(sp) + 8044e9c: 183e9e26 beq r3,zero,8044918 <___svfprintf_internal_r+0x15d8> + 8044ea0: d8800f17 ldw r2,60(sp) + 8044ea4: 10000d26 beq r2,zero,8044edc <___svfprintf_internal_r+0x1b9c> + 8044ea8: d8c00717 ldw r3,28(sp) + 8044eac: 6080004c andi r2,r12,1 + 8044eb0: 12c4b03a or r2,r2,r11 + 8044eb4: 00c0bb0e bge zero,r3,80451a4 <___svfprintf_internal_r+0x1e64> + 8044eb8: 1001381e bne r2,zero,804539c <___svfprintf_internal_r+0x205c> + 8044ebc: dd400717 ldw r21,28(sp) + 8044ec0: a829883a mov r20,r21 + 8044ec4: 003ea206 br 8044950 <___svfprintf_internal_r+0x1610> + 8044ec8: d8800615 stw r2,24(sp) + 8044ecc: 002b883a mov r21,zero + 8044ed0: 00800044 movi r2,1 + 8044ed4: 003b4106 br 8043bdc <___svfprintf_internal_r+0x89c> + 8044ed8: e73fff84 addi fp,fp,-2 + 8044edc: d8800717 ldw r2,28(sp) + 8044ee0: df001845 stb fp,97(sp) + 8044ee4: 157fffc4 addi r21,r2,-1 + 8044ee8: dd401615 stw r21,88(sp) + 8044eec: a8009216 blt r21,zero,8045138 <___svfprintf_internal_r+0x1df8> + 8044ef0: 00800ac4 movi r2,43 + 8044ef4: d8801885 stb r2,98(sp) + 8044ef8: a8800290 cmplti r2,r21,10 + 8044efc: 1001191e bne r2,zero,8045364 <___svfprintf_internal_r+0x2024> + 8044f00: dc000715 stw r16,28(sp) + 8044f04: dd001bc4 addi r20,sp,111 + 8044f08: a821883a mov r16,r21 + 8044f0c: db000f15 stw r12,60(sp) + 8044f10: 982b883a mov r21,r19 + 8044f14: 4027883a mov r19,r8 + 8044f18: 00000206 br 8044f24 <___svfprintf_internal_r+0x1be4> + 8044f1c: 2029883a mov r20,r4 + 8044f20: 1021883a mov r16,r2 + 8044f24: 8009883a mov r4,r16 + 8044f28: 01400284 movi r5,10 + 8044f2c: 800cf800 call 800cf80 <__modsi3> + 8044f30: 10800c04 addi r2,r2,48 + 8044f34: 8009883a mov r4,r16 + 8044f38: a0bfffc5 stb r2,-1(r20) + 8044f3c: 01400284 movi r5,10 + 8044f40: 800cf000 call 800cf00 <__divsi3> + 8044f44: 80c01908 cmpgei r3,r16,100 + 8044f48: a13fffc4 addi r4,r20,-1 + 8044f4c: 183ff31e bne r3,zero,8044f1c <___svfprintf_internal_r+0x1bdc> + 8044f50: 10800c04 addi r2,r2,48 + 8044f54: 20bfffc5 stb r2,-1(r4) + 8044f58: a0ffff84 addi r3,r20,-2 + 8044f5c: d9001bc4 addi r4,sp,111 + 8044f60: 9811883a mov r8,r19 + 8044f64: dc000717 ldw r16,28(sp) + 8044f68: db000f17 ldw r12,60(sp) + 8044f6c: a827883a mov r19,r21 + 8044f70: 1901242e bgeu r3,r4,8045404 <___svfprintf_internal_r+0x20c4> + 8044f74: d90018c4 addi r4,sp,99 + 8044f78: 00000106 br 8044f80 <___svfprintf_internal_r+0x1c40> + 8044f7c: 18800003 ldbu r2,0(r3) + 8044f80: 21000044 addi r4,r4,1 + 8044f84: 20bfffc5 stb r2,-1(r4) + 8044f88: 18c00044 addi r3,r3,1 + 8044f8c: d8801bc4 addi r2,sp,111 + 8044f90: 18bffa1e bne r3,r2,8044f7c <___svfprintf_internal_r+0x1c3c> + 8044f94: d8801c44 addi r2,sp,113 + 8044f98: d8c018c4 addi r3,sp,99 + 8044f9c: 1505c83a sub r2,r2,r20 + 8044fa0: 1885883a add r2,r3,r2 + 8044fa4: d8c01844 addi r3,sp,97 + 8044fa8: 10c5c83a sub r2,r2,r3 + 8044fac: d8801115 stw r2,68(sp) + 8044fb0: d8c00817 ldw r3,32(sp) + 8044fb4: d9001117 ldw r4,68(sp) + 8044fb8: 18800088 cmpgei r2,r3,2 + 8044fbc: 192b883a add r21,r3,r4 + 8044fc0: 1000ef26 beq r2,zero,8045380 <___svfprintf_internal_r+0x2040> + 8044fc4: d8800b17 ldw r2,44(sp) + 8044fc8: a8ab883a add r21,r21,r2 + 8044fcc: a829883a mov r20,r21 + 8044fd0: a800010e bge r21,zero,8044fd8 <___svfprintf_internal_r+0x1c98> + 8044fd4: 0029883a mov r20,zero + 8044fd8: d8000715 stw zero,28(sp) + 8044fdc: 003e5c06 br 8044950 <___svfprintf_internal_r+0x1610> + 8044fe0: 04020134 movhi r16,2052 + 8044fe4: 841d1704 addi r16,r16,29788 + 8044fe8: 003b4a06 br 8043d14 <___svfprintf_internal_r+0x9d4> + 8044fec: d8800615 stw r2,24(sp) + 8044ff0: 002b883a mov r21,zero + 8044ff4: 0005883a mov r2,zero + 8044ff8: 003af806 br 8043bdc <___svfprintf_internal_r+0x89c> + 8044ffc: 9019883a mov r12,r18 + 8045000: dc000f17 ldw r16,60(sp) + 8045004: dc800e17 ldw r18,56(sp) + 8045008: e009883a mov r4,fp + 804500c: 8839883a mov fp,r17 + 8045010: b023883a mov r17,r22 + 8045014: 202d883a mov r22,r4 + 8045018: 10800044 addi r2,r2,1 + 804501c: 1f07883a add r3,r3,fp + 8045020: d8801d15 stw r2,116(sp) + 8045024: 43000015 stw r12,0(r8) + 8045028: 47000115 stw fp,4(r8) + 804502c: d8c01e15 stw r3,120(sp) + 8045030: 10800208 cmpgei r2,r2,8 + 8045034: 1000381e bne r2,zero,8045118 <___svfprintf_internal_r+0x1dd8> + 8045038: 42000204 addi r8,r8,8 + 804503c: 003d6406 br 80445d0 <___svfprintf_internal_r+0x1290> + 8045040: 8819883a mov r12,r17 + 8045044: dc400717 ldw r17,28(sp) + 8045048: 10800044 addi r2,r2,1 + 804504c: 1f07883a add r3,r3,fp + 8045050: d8801d15 stw r2,116(sp) + 8045054: 43000015 stw r12,0(r8) + 8045058: 47000115 stw fp,4(r8) + 804505c: d8c01e15 stw r3,120(sp) + 8045060: 10800208 cmpgei r2,r2,8 + 8045064: 103a6526 beq r2,zero,80439fc <___svfprintf_internal_r+0x6bc> + 8045068: 003cd606 br 80443c4 <___svfprintf_internal_r+0x1084> + 804506c: 00800b44 movi r2,45 + 8045070: d8801545 stb r2,85(sp) + 8045074: 03400b44 movi r13,45 + 8045078: 003b2206 br 8043d04 <___svfprintf_internal_r+0x9c4> + 804507c: d9000517 ldw r4,20(sp) + 8045080: d9801c04 addi r6,sp,112 + 8045084: 980b883a mov r5,r19 + 8045088: 80456900 call 8045690 <__ssprint_r> + 804508c: 10396b1e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 8045090: d9001617 ldw r4,88(sp) + 8045094: d8c01e17 ldw r3,120(sp) + 8045098: b811883a mov r8,r23 + 804509c: 003eae06 br 8044b58 <___svfprintf_internal_r+0x1818> + 80450a0: d9000517 ldw r4,20(sp) + 80450a4: d9801c04 addi r6,sp,112 + 80450a8: 980b883a mov r5,r19 + 80450ac: 80456900 call 8045690 <__ssprint_r> + 80450b0: 1039621e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 80450b4: d9001617 ldw r4,88(sp) + 80450b8: d8c01e17 ldw r3,120(sp) + 80450bc: b811883a mov r8,r23 + 80450c0: 003d5206 br 804460c <___svfprintf_internal_r+0x12cc> + 80450c4: 1520003c xorhi r20,r2,32768 + 80450c8: 00800b44 movi r2,45 + 80450cc: d8800e05 stb r2,56(sp) + 80450d0: 003de906 br 8044878 <___svfprintf_internal_r+0x1538> + 80450d4: a805883a mov r2,r21 + 80450d8: 003f6a06 br 8044e84 <___svfprintf_internal_r+0x1b44> + 80450dc: 05400184 movi r21,6 + 80450e0: 003eed06 br 8044c98 <___svfprintf_internal_r+0x1958> + 80450e4: d9401545 stb r5,85(sp) + 80450e8: 00397206 br 80436b4 <___svfprintf_internal_r+0x374> + 80450ec: d9000517 ldw r4,20(sp) + 80450f0: d9801c04 addi r6,sp,112 + 80450f4: 980b883a mov r5,r19 + 80450f8: 80456900 call 8045690 <__ssprint_r> + 80450fc: 10394f1e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 8045100: d9001617 ldw r4,88(sp) + 8045104: d8c01e17 ldw r3,120(sp) + 8045108: d8801d17 ldw r2,116(sp) + 804510c: b811883a mov r8,r23 + 8045110: 203ea20e bge r4,zero,8044b9c <___svfprintf_internal_r+0x185c> + 8045114: 003ef206 br 8044ce0 <___svfprintf_internal_r+0x19a0> + 8045118: d9000517 ldw r4,20(sp) + 804511c: d9801c04 addi r6,sp,112 + 8045120: 980b883a mov r5,r19 + 8045124: 80456900 call 8045690 <__ssprint_r> + 8045128: 1039441e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 804512c: d8c01e17 ldw r3,120(sp) + 8045130: b811883a mov r8,r23 + 8045134: 003d2606 br 80445d0 <___svfprintf_internal_r+0x1290> + 8045138: 00c00044 movi r3,1 + 804513c: 18abc83a sub r21,r3,r2 + 8045140: 00800b44 movi r2,45 + 8045144: d8801885 stb r2,98(sp) + 8045148: 003f6b06 br 8044ef8 <___svfprintf_internal_r+0x1bb8> + 804514c: d8801a04 addi r2,sp,104 + 8045150: d8800315 stw r2,12(sp) + 8045154: d9400917 ldw r5,36(sp) + 8045158: d8801704 addi r2,sp,92 + 804515c: d9000517 ldw r4,20(sp) + 8045160: 5d400044 addi r21,r11,1 + 8045164: d8800215 stw r2,8(sp) + 8045168: d8801604 addi r2,sp,88 + 804516c: d8800115 stw r2,4(sp) + 8045170: dd400015 stw r21,0(sp) + 8045174: 01c00084 movi r7,2 + 8045178: a00d883a mov r6,r20 + 804517c: dac00815 stw r11,32(sp) + 8045180: 80053ec0 call 80053ec <_dtoa_r> + 8045184: dac00817 ldw r11,32(sp) + 8045188: db001017 ldw r12,64(sp) + 804518c: da001217 ldw r8,72(sp) + 8045190: 1021883a mov r16,r2 + 8045194: e08011d8 cmpnei r2,fp,71 + 8045198: 103dd526 beq r2,zero,80448f0 <___svfprintf_internal_r+0x15b0> + 804519c: 856b883a add r21,r16,r21 + 80451a0: 003f2406 br 8044e34 <___svfprintf_internal_r+0x1af4> + 80451a4: 1000891e bne r2,zero,80453cc <___svfprintf_internal_r+0x208c> + 80451a8: 05000044 movi r20,1 + 80451ac: 05400044 movi r21,1 + 80451b0: 003de706 br 8044950 <___svfprintf_internal_r+0x1610> + 80451b4: db401543 ldbu r13,85(sp) + 80451b8: 0017883a mov r11,zero + 80451bc: 003b5506 br 8043f14 <___svfprintf_internal_r+0xbd4> + 80451c0: d9000517 ldw r4,20(sp) + 80451c4: d9801c04 addi r6,sp,112 + 80451c8: 980b883a mov r5,r19 + 80451cc: 80456900 call 8045690 <__ssprint_r> + 80451d0: 10391a1e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 80451d4: d8c01e17 ldw r3,120(sp) + 80451d8: b811883a mov r8,r23 + 80451dc: e03cf90e bge fp,zero,80445c4 <___svfprintf_internal_r+0x1284> + 80451e0: 003dfe06 br 80449dc <___svfprintf_internal_r+0x169c> + 80451e4: 02c00184 movi r11,6 + 80451e8: 003d9e06 br 8044864 <___svfprintf_internal_r+0x1524> + 80451ec: d9000517 ldw r4,20(sp) + 80451f0: d9801c04 addi r6,sp,112 + 80451f4: 980b883a mov r5,r19 + 80451f8: 80456900 call 8045690 <__ssprint_r> + 80451fc: 10390f1e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 8045200: d8801617 ldw r2,88(sp) + 8045204: d9000817 ldw r4,32(sp) + 8045208: d8c01e17 ldw r3,120(sp) + 804520c: b811883a mov r8,r23 + 8045210: 2085c83a sub r2,r4,r2 + 8045214: 003d0f06 br 8044654 <___svfprintf_internal_r+0x1314> + 8045218: 5829883a mov r20,r11 + 804521c: dc800615 stw r18,24(sp) + 8045220: 582b883a mov r21,r11 + 8045224: 0039c006 br 8043928 <___svfprintf_internal_r+0x5e8> + 8045228: d8800817 ldw r2,32(sp) + 804522c: d8c00b17 ldw r3,44(sp) + 8045230: 10eb883a add r21,r2,r3 + 8045234: d8800717 ldw r2,28(sp) + 8045238: 00800316 blt zero,r2,8045248 <___svfprintf_internal_r+0x1f08> + 804523c: d8800717 ldw r2,28(sp) + 8045240: a8b9c83a sub fp,r21,r2 + 8045244: e5400044 addi r21,fp,1 + 8045248: a829883a mov r20,r21 + 804524c: a8003316 blt r21,zero,804531c <___svfprintf_internal_r+0x1fdc> + 8045250: 070019c4 movi fp,103 + 8045254: 003dbe06 br 8044950 <___svfprintf_internal_r+0x1610> + 8045258: d9401545 stb r5,85(sp) + 804525c: 003aec06 br 8043e10 <___svfprintf_internal_r+0xad0> + 8045260: d9401545 stb r5,85(sp) + 8045264: 00396406 br 80437f8 <___svfprintf_internal_r+0x4b8> + 8045268: d9401545 stb r5,85(sp) + 804526c: 003ab206 br 8043d38 <___svfprintf_internal_r+0x9f8> + 8045270: d9401545 stb r5,85(sp) + 8045274: 00394e06 br 80437b0 <___svfprintf_internal_r+0x470> + 8045278: d9401545 stb r5,85(sp) + 804527c: 003a6906 br 8043c24 <___svfprintf_internal_r+0x8e4> + 8045280: d9401545 stb r5,85(sp) + 8045284: 003a1d06 br 8043afc <___svfprintf_internal_r+0x7bc> + 8045288: d9401545 stb r5,85(sp) + 804528c: 00398206 br 8043898 <___svfprintf_internal_r+0x558> + 8045290: d9401545 stb r5,85(sp) + 8045294: 003a7006 br 8043c58 <___svfprintf_internal_r+0x918> + 8045298: d9401545 stb r5,85(sp) + 804529c: 003a2706 br 8043b3c <___svfprintf_internal_r+0x7fc> + 80452a0: d9401545 stb r5,85(sp) + 80452a4: 003aec06 br 8043e58 <___svfprintf_internal_r+0xb18> + 80452a8: 8819883a mov r12,r17 + 80452ac: a823883a mov r17,r21 + 80452b0: 802b883a mov r21,r16 + 80452b4: dc000717 ldw r16,28(sp) + 80452b8: 10800044 addi r2,r2,1 + 80452bc: 1d47883a add r3,r3,r21 + 80452c0: 43000015 stw r12,0(r8) + 80452c4: 45400115 stw r21,4(r8) + 80452c8: d8c01e15 stw r3,120(sp) + 80452cc: d8801d15 stw r2,116(sp) + 80452d0: 11000208 cmpgei r4,r2,8 + 80452d4: 203e3026 beq r4,zero,8044b98 <___svfprintf_internal_r+0x1858> + 80452d8: d9000517 ldw r4,20(sp) + 80452dc: d9801c04 addi r6,sp,112 + 80452e0: 980b883a mov r5,r19 + 80452e4: 80456900 call 8045690 <__ssprint_r> + 80452e8: 1038d41e bne r2,zero,804363c <___svfprintf_internal_r+0x2fc> + 80452ec: d8c01e17 ldw r3,120(sp) + 80452f0: d8801d17 ldw r2,116(sp) + 80452f4: b811883a mov r8,r23 + 80452f8: 003e2806 br 8044b9c <___svfprintf_internal_r+0x185c> + 80452fc: 00bfffc4 movi r2,-1 + 8045300: d8800415 stw r2,16(sp) + 8045304: 0038d006 br 8043648 <___svfprintf_internal_r+0x308> + 8045308: d8800717 ldw r2,28(sp) + 804530c: d8c00b17 ldw r3,44(sp) + 8045310: 10eb883a add r21,r2,r3 + 8045314: a829883a mov r20,r21 + 8045318: a83fcd0e bge r21,zero,8045250 <___svfprintf_internal_r+0x1f10> + 804531c: 0029883a mov r20,zero + 8045320: 003fcb06 br 8045250 <___svfprintf_internal_r+0x1f10> + 8045324: d9000917 ldw r4,36(sp) + 8045328: 000d883a mov r6,zero + 804532c: 000f883a mov r7,zero + 8045330: a00b883a mov r5,r20 + 8045334: da001215 stw r8,72(sp) + 8045338: dac01015 stw r11,64(sp) + 804533c: db000815 stw r12,32(sp) + 8045340: 800e3000 call 800e300 <__eqdf2> + 8045344: db000817 ldw r12,32(sp) + 8045348: dac01017 ldw r11,64(sp) + 804534c: da001217 ldw r8,72(sp) + 8045350: 103eb626 beq r2,zero,8044e2c <___svfprintf_internal_r+0x1aec> + 8045354: 00800044 movi r2,1 + 8045358: 12c5c83a sub r2,r2,r11 + 804535c: d8801615 stw r2,88(sp) + 8045360: 003eb306 br 8044e30 <___svfprintf_internal_r+0x1af0> + 8045364: 00800c04 movi r2,48 + 8045368: a8c00c04 addi r3,r21,48 + 804536c: d88018c5 stb r2,99(sp) + 8045370: 00800104 movi r2,4 + 8045374: d8c01905 stb r3,100(sp) + 8045378: d8801115 stw r2,68(sp) + 804537c: 003f0c06 br 8044fb0 <___svfprintf_internal_r+0x1c70> + 8045380: 6080004c andi r2,r12,1 + 8045384: d8800715 stw r2,28(sp) + 8045388: 103f0e1e bne r2,zero,8044fc4 <___svfprintf_internal_r+0x1c84> + 804538c: a829883a mov r20,r21 + 8045390: a83d6f0e bge r21,zero,8044950 <___svfprintf_internal_r+0x1610> + 8045394: 0029883a mov r20,zero + 8045398: 003d6d06 br 8044950 <___svfprintf_internal_r+0x1610> + 804539c: d8800b17 ldw r2,44(sp) + 80453a0: 1885883a add r2,r3,r2 + 80453a4: 12eb883a add r21,r2,r11 + 80453a8: 003ff806 br 804538c <___svfprintf_internal_r+0x204c> + 80453ac: d8800a17 ldw r2,40(sp) + 80453b0: 10001016 blt r2,zero,80453f4 <___svfprintf_internal_r+0x20b4> + 80453b4: db401543 ldbu r13,85(sp) + 80453b8: e0801210 cmplti r2,fp,72 + 80453bc: 10000a1e bne r2,zero,80453e8 <___svfprintf_internal_r+0x20a8> + 80453c0: 04020134 movhi r16,2052 + 80453c4: 841d1a04 addi r16,r16,29800 + 80453c8: 003a5206 br 8043d14 <___svfprintf_internal_r+0x9d4> + 80453cc: d8800b17 ldw r2,44(sp) + 80453d0: 10800044 addi r2,r2,1 + 80453d4: 12eb883a add r21,r2,r11 + 80453d8: 003fec06 br 804538c <___svfprintf_internal_r+0x204c> + 80453dc: 4005883a mov r2,r8 + 80453e0: 632e3444 addi r12,r12,-18223 + 80453e4: 003e6f06 br 8044da4 <___svfprintf_internal_r+0x1a64> + 80453e8: 04020134 movhi r16,2052 + 80453ec: 841d1904 addi r16,r16,29796 + 80453f0: 003a4806 br 8043d14 <___svfprintf_internal_r+0x9d4> + 80453f4: 00800b44 movi r2,45 + 80453f8: d8801545 stb r2,85(sp) + 80453fc: 03400b44 movi r13,45 + 8045400: 003fed06 br 80453b8 <___svfprintf_internal_r+0x2078> + 8045404: 00800084 movi r2,2 + 8045408: d8801115 stw r2,68(sp) + 804540c: 003ee806 br 8044fb0 <___svfprintf_internal_r+0x1c70> + 8045410: d8800617 ldw r2,24(sp) + 8045414: 12c00017 ldw r11,0(r2) + 8045418: 10800104 addi r2,r2,4 + 804541c: 5800010e bge r11,zero,8045424 <___svfprintf_internal_r+0x20e4> + 8045420: 02ffffc4 movi r11,-1 + 8045424: b7000043 ldbu fp,1(r22) + 8045428: d8800615 stw r2,24(sp) + 804542c: 182d883a mov r22,r3 + 8045430: e2803fcc andi r10,fp,255 + 8045434: 5280201c xori r10,r10,128 + 8045438: 52bfe004 addi r10,r10,-128 + 804543c: 00380c06 br 8043470 <___svfprintf_internal_r+0x130> + 8045440: d8c00517 ldw r3,20(sp) + 8045444: 00800304 movi r2,12 + 8045448: 18800015 stw r2,0(r3) + 804544c: 00bfffc4 movi r2,-1 + 8045450: d8800415 stw r2,16(sp) + 8045454: 00387c06 br 8043648 <___svfprintf_internal_r+0x308> + +08045458 : + 8045458: 00820174 movhi r2,2053 + 804545c: 10b2af17 ldw r2,-13636(r2) + 8045460: 280f883a mov r7,r5 + 8045464: 200d883a mov r6,r4 + 8045468: 11400217 ldw r5,8(r2) + 804546c: 1009883a mov r4,r2 + 8045470: 80469701 jmpi 8046970 <_vfprintf_r> + +08045474 <_vprintf_r>: + 8045474: 300f883a mov r7,r6 + 8045478: 280d883a mov r6,r5 + 804547c: 21400217 ldw r5,8(r4) + 8045480: 80469701 jmpi 8046970 <_vfprintf_r> + +08045484 <_vsprintf_r>: + 8045484: deffe504 addi sp,sp,-108 + 8045488: 00a00034 movhi r2,32768 + 804548c: 00fffff4 movhi r3,65535 + 8045490: 2811883a mov r8,r5 + 8045494: 10bfffc4 addi r2,r2,-1 + 8045498: 18c08204 addi r3,r3,520 + 804549c: d80b883a mov r5,sp + 80454a0: dfc01a15 stw ra,104(sp) + 80454a4: d8c00315 stw r3,12(sp) + 80454a8: da000015 stw r8,0(sp) + 80454ac: da000415 stw r8,16(sp) + 80454b0: d8800515 stw r2,20(sp) + 80454b4: d8800215 stw r2,8(sp) + 80454b8: 80433400 call 8043340 <___svfprintf_internal_r> + 80454bc: d8c00017 ldw r3,0(sp) + 80454c0: 18000005 stb zero,0(r3) + 80454c4: dfc01a17 ldw ra,104(sp) + 80454c8: dec01b04 addi sp,sp,108 + 80454cc: f800283a ret + +080454d0 : + 80454d0: 00820174 movhi r2,2053 + 80454d4: 300f883a mov r7,r6 + 80454d8: 280d883a mov r6,r5 + 80454dc: 200b883a mov r5,r4 + 80454e0: 1132af17 ldw r4,-13636(r2) + 80454e4: 80454841 jmpi 8045484 <_vsprintf_r> + +080454e8 <__register_exitproc>: + 80454e8: 00820174 movhi r2,2053 + 80454ec: 10f2ae17 ldw r3,-13640(r2) + 80454f0: 18805217 ldw r2,328(r3) + 80454f4: 10001726 beq r2,zero,8045554 <__register_exitproc+0x6c> + 80454f8: 10c00117 ldw r3,4(r2) + 80454fc: 1a000808 cmpgei r8,r3,32 + 8045500: 40001b1e bne r8,zero,8045570 <__register_exitproc+0x88> + 8045504: 20000b26 beq r4,zero,8045534 <__register_exitproc+0x4c> + 8045508: 181090ba slli r8,r3,2 + 804550c: 02400044 movi r9,1 + 8045510: 48d2983a sll r9,r9,r3 + 8045514: 1211883a add r8,r2,r8 + 8045518: 41802215 stw r6,136(r8) + 804551c: 11806217 ldw r6,392(r2) + 8045520: 21000098 cmpnei r4,r4,2 + 8045524: 324cb03a or r6,r6,r9 + 8045528: 11806215 stw r6,392(r2) + 804552c: 41c04215 stw r7,264(r8) + 8045530: 20000b26 beq r4,zero,8045560 <__register_exitproc+0x78> + 8045534: 19000084 addi r4,r3,2 + 8045538: 200890ba slli r4,r4,2 + 804553c: 18c00044 addi r3,r3,1 + 8045540: 10c00115 stw r3,4(r2) + 8045544: 1105883a add r2,r2,r4 + 8045548: 11400015 stw r5,0(r2) + 804554c: 0005883a mov r2,zero + 8045550: f800283a ret + 8045554: 18805304 addi r2,r3,332 + 8045558: 18805215 stw r2,328(r3) + 804555c: 003fe606 br 80454f8 <__register_exitproc+0x10> + 8045560: 11006317 ldw r4,396(r2) + 8045564: 2252b03a or r9,r4,r9 + 8045568: 12406315 stw r9,396(r2) + 804556c: 003ff106 br 8045534 <__register_exitproc+0x4c> + 8045570: 00bfffc4 movi r2,-1 + 8045574: f800283a ret + +08045578 <__call_exitprocs>: + 8045578: defff704 addi sp,sp,-36 + 804557c: 00820174 movhi r2,2053 + 8045580: ddc00715 stw r23,28(sp) + 8045584: 15f2ae17 ldw r23,-13640(r2) + 8045588: dd400515 stw r21,20(sp) + 804558c: dd000415 stw r20,16(sp) + 8045590: dcc00315 stw r19,12(sp) + 8045594: dfc00815 stw ra,32(sp) + 8045598: dd800615 stw r22,24(sp) + 804559c: dc800215 stw r18,8(sp) + 80455a0: dc400115 stw r17,4(sp) + 80455a4: dc000015 stw r16,0(sp) + 80455a8: 2029883a mov r20,r4 + 80455ac: 282b883a mov r21,r5 + 80455b0: 04c00044 movi r19,1 + 80455b4: bc805217 ldw r18,328(r23) + 80455b8: 90000d26 beq r18,zero,80455f0 <__call_exitprocs+0x78> + 80455bc: 94000117 ldw r16,4(r18) + 80455c0: 847fffc4 addi r17,r16,-1 + 80455c4: 88000a16 blt r17,zero,80455f0 <__call_exitprocs+0x78> + 80455c8: 84000044 addi r16,r16,1 + 80455cc: 802090ba slli r16,r16,2 + 80455d0: 9421883a add r16,r18,r16 + 80455d4: a8001126 beq r21,zero,804561c <__call_exitprocs+0xa4> + 80455d8: 80804017 ldw r2,256(r16) + 80455dc: 15400f26 beq r2,r21,804561c <__call_exitprocs+0xa4> + 80455e0: 8c7fffc4 addi r17,r17,-1 + 80455e4: 88bfffd8 cmpnei r2,r17,-1 + 80455e8: 843fff04 addi r16,r16,-4 + 80455ec: 103ff91e bne r2,zero,80455d4 <__call_exitprocs+0x5c> + 80455f0: dfc00817 ldw ra,32(sp) + 80455f4: ddc00717 ldw r23,28(sp) + 80455f8: dd800617 ldw r22,24(sp) + 80455fc: dd400517 ldw r21,20(sp) + 8045600: dd000417 ldw r20,16(sp) + 8045604: dcc00317 ldw r19,12(sp) + 8045608: dc800217 ldw r18,8(sp) + 804560c: dc400117 ldw r17,4(sp) + 8045610: dc000017 ldw r16,0(sp) + 8045614: dec00904 addi sp,sp,36 + 8045618: f800283a ret + 804561c: 90800117 ldw r2,4(r18) + 8045620: 81800017 ldw r6,0(r16) + 8045624: 10bfffc4 addi r2,r2,-1 + 8045628: 14401526 beq r2,r17,8045680 <__call_exitprocs+0x108> + 804562c: 80000015 stw zero,0(r16) + 8045630: 303feb26 beq r6,zero,80455e0 <__call_exitprocs+0x68> + 8045634: 9c46983a sll r3,r19,r17 + 8045638: 90806217 ldw r2,392(r18) + 804563c: 95800117 ldw r22,4(r18) + 8045640: 1884703a and r2,r3,r2 + 8045644: 1000061e bne r2,zero,8045660 <__call_exitprocs+0xe8> + 8045648: 303ee83a callr r6 + 804564c: 90800117 ldw r2,4(r18) + 8045650: 15bfd81e bne r2,r22,80455b4 <__call_exitprocs+0x3c> + 8045654: b8805217 ldw r2,328(r23) + 8045658: 14bfe126 beq r2,r18,80455e0 <__call_exitprocs+0x68> + 804565c: 003fd506 br 80455b4 <__call_exitprocs+0x3c> + 8045660: 90806317 ldw r2,396(r18) + 8045664: 81002017 ldw r4,128(r16) + 8045668: 1886703a and r3,r3,r2 + 804566c: 1800061e bne r3,zero,8045688 <__call_exitprocs+0x110> + 8045670: 200b883a mov r5,r4 + 8045674: a009883a mov r4,r20 + 8045678: 303ee83a callr r6 + 804567c: 003ff306 br 804564c <__call_exitprocs+0xd4> + 8045680: 94400115 stw r17,4(r18) + 8045684: 003fea06 br 8045630 <__call_exitprocs+0xb8> + 8045688: 303ee83a callr r6 + 804568c: 003fef06 br 804564c <__call_exitprocs+0xd4> + +08045690 <__ssprint_r>: + 8045690: 30800217 ldw r2,8(r6) + 8045694: defff604 addi sp,sp,-40 + 8045698: dcc00315 stw r19,12(sp) + 804569c: dfc00915 stw ra,36(sp) + 80456a0: df000815 stw fp,32(sp) + 80456a4: ddc00715 stw r23,28(sp) + 80456a8: dd800615 stw r22,24(sp) + 80456ac: dd400515 stw r21,20(sp) + 80456b0: dd000415 stw r20,16(sp) + 80456b4: dc800215 stw r18,8(sp) + 80456b8: dc400115 stw r17,4(sp) + 80456bc: dc000015 stw r16,0(sp) + 80456c0: 3027883a mov r19,r6 + 80456c4: 10005426 beq r2,zero,8045818 <__ssprint_r+0x188> + 80456c8: 2029883a mov r20,r4 + 80456cc: 2821883a mov r16,r5 + 80456d0: 35800017 ldw r22,0(r6) + 80456d4: 29000017 ldw r4,0(r5) + 80456d8: 2c400217 ldw r17,8(r5) + 80456dc: 057edfc4 movi r21,-1153 + 80456e0: 00003406 br 80457b4 <__ssprint_r+0x124> + 80456e4: 8080030b ldhu r2,12(r16) + 80456e8: 10c1200c andi r3,r2,1152 + 80456ec: 18002426 beq r3,zero,8045780 <__ssprint_r+0xf0> + 80456f0: 81800517 ldw r6,20(r16) + 80456f4: 81400417 ldw r5,16(r16) + 80456f8: 90c00044 addi r3,r18,1 + 80456fc: 318000e4 muli r6,r6,3 + 8045700: 216fc83a sub r23,r4,r5 + 8045704: 1dc7883a add r3,r3,r23 + 8045708: 3022d7fa srli r17,r6,31 + 804570c: 89a3883a add r17,r17,r6 + 8045710: 8823d07a srai r17,r17,1 + 8045714: 880d883a mov r6,r17 + 8045718: 88c0022e bgeu r17,r3,8045724 <__ssprint_r+0x94> + 804571c: 1823883a mov r17,r3 + 8045720: 180d883a mov r6,r3 + 8045724: 1081000c andi r2,r2,1024 + 8045728: 10002b26 beq r2,zero,80457d8 <__ssprint_r+0x148> + 804572c: 300b883a mov r5,r6 + 8045730: a009883a mov r4,r20 + 8045734: 8007ddc0 call 8007ddc <_malloc_r> + 8045738: 10002e26 beq r2,zero,80457f4 <__ssprint_r+0x164> + 804573c: 81400417 ldw r5,16(r16) + 8045740: b80d883a mov r6,r23 + 8045744: 1009883a mov r4,r2 + 8045748: 80086b80 call 80086b8 + 804574c: 1007883a mov r3,r2 + 8045750: 8080030b ldhu r2,12(r16) + 8045754: 1544703a and r2,r2,r21 + 8045758: 10802014 ori r2,r2,128 + 804575c: 8080030d sth r2,12(r16) + 8045760: 8dc5c83a sub r2,r17,r23 + 8045764: 1dc9883a add r4,r3,r23 + 8045768: 84400515 stw r17,20(r16) + 804576c: 80c00415 stw r3,16(r16) + 8045770: 81000015 stw r4,0(r16) + 8045774: 9023883a mov r17,r18 + 8045778: 80800215 stw r2,8(r16) + 804577c: 902f883a mov r23,r18 + 8045780: b80d883a mov r6,r23 + 8045784: e00b883a mov r5,fp + 8045788: 80087b80 call 80087b8 + 804578c: 80c00217 ldw r3,8(r16) + 8045790: 81000017 ldw r4,0(r16) + 8045794: 98800217 ldw r2,8(r19) + 8045798: 1c63c83a sub r17,r3,r17 + 804579c: 25c9883a add r4,r4,r23 + 80457a0: 84400215 stw r17,8(r16) + 80457a4: 81000015 stw r4,0(r16) + 80457a8: 14a5c83a sub r18,r2,r18 + 80457ac: 9c800215 stw r18,8(r19) + 80457b0: 90001926 beq r18,zero,8045818 <__ssprint_r+0x188> + 80457b4: b4800117 ldw r18,4(r22) + 80457b8: b7000017 ldw fp,0(r22) + 80457bc: 882f883a mov r23,r17 + 80457c0: b5800204 addi r22,r22,8 + 80457c4: 903ffb26 beq r18,zero,80457b4 <__ssprint_r+0x124> + 80457c8: 947fc62e bgeu r18,r17,80456e4 <__ssprint_r+0x54> + 80457cc: 9023883a mov r17,r18 + 80457d0: 902f883a mov r23,r18 + 80457d4: 003fea06 br 8045780 <__ssprint_r+0xf0> + 80457d8: a009883a mov r4,r20 + 80457dc: 8009abc0 call 8009abc <_realloc_r> + 80457e0: 1007883a mov r3,r2 + 80457e4: 103fde1e bne r2,zero,8045760 <__ssprint_r+0xd0> + 80457e8: 81400417 ldw r5,16(r16) + 80457ec: a009883a mov r4,r20 + 80457f0: 80071c40 call 80071c4 <_free_r> + 80457f4: 80c0030b ldhu r3,12(r16) + 80457f8: 00800304 movi r2,12 + 80457fc: a0800015 stw r2,0(r20) + 8045800: 18c01014 ori r3,r3,64 + 8045804: 80c0030d sth r3,12(r16) + 8045808: 00bfffc4 movi r2,-1 + 804580c: 98000215 stw zero,8(r19) + 8045810: 98000115 stw zero,4(r19) + 8045814: 00000206 br 8045820 <__ssprint_r+0x190> + 8045818: 98000115 stw zero,4(r19) + 804581c: 0005883a mov r2,zero + 8045820: dfc00917 ldw ra,36(sp) + 8045824: df000817 ldw fp,32(sp) + 8045828: ddc00717 ldw r23,28(sp) + 804582c: dd800617 ldw r22,24(sp) + 8045830: dd400517 ldw r21,20(sp) + 8045834: dd000417 ldw r20,16(sp) + 8045838: dcc00317 ldw r19,12(sp) + 804583c: dc800217 ldw r18,8(sp) + 8045840: dc400117 ldw r17,4(sp) + 8045844: dc000017 ldw r16,0(sp) + 8045848: dec00a04 addi sp,sp,40 + 804584c: f800283a ret + +08045850 <___svfiprintf_internal_r>: + 8045850: 2880030b ldhu r2,12(r5) + 8045854: deffd004 addi sp,sp,-192 + 8045858: df002e15 stw fp,184(sp) + 804585c: dd802c15 stw r22,176(sp) + 8045860: dd002a15 stw r20,168(sp) + 8045864: dfc02f15 stw ra,188(sp) + 8045868: ddc02d15 stw r23,180(sp) + 804586c: dd402b15 stw r21,172(sp) + 8045870: dcc02915 stw r19,164(sp) + 8045874: dc802815 stw r18,160(sp) + 8045878: dc402715 stw r17,156(sp) + 804587c: dc002615 stw r16,152(sp) + 8045880: 1080200c andi r2,r2,128 + 8045884: d9c00315 stw r7,12(sp) + 8045888: 2829883a mov r20,r5 + 804588c: 202d883a mov r22,r4 + 8045890: 3039883a mov fp,r6 + 8045894: 10000226 beq r2,zero,80458a0 <___svfiprintf_internal_r+0x50> + 8045898: 28800417 ldw r2,16(r5) + 804589c: 10039b26 beq r2,zero,804670c <___svfiprintf_internal_r+0xebc> + 80458a0: dc801604 addi r18,sp,88 + 80458a4: dc800915 stw r18,36(sp) + 80458a8: d8000b15 stw zero,44(sp) + 80458ac: d8000a15 stw zero,40(sp) + 80458b0: 9011883a mov r8,r18 + 80458b4: d8000415 stw zero,16(sp) + 80458b8: d8000015 stw zero,0(sp) + 80458bc: e0800007 ldb r2,0(fp) + 80458c0: 10009026 beq r2,zero,8045b04 <___svfiprintf_internal_r+0x2b4> + 80458c4: 10800960 cmpeqi r2,r2,37 + 80458c8: 1003751e bne r2,zero,80466a0 <___svfiprintf_internal_r+0xe50> + 80458cc: e021883a mov r16,fp + 80458d0: 00000206 br 80458dc <___svfiprintf_internal_r+0x8c> + 80458d4: 18008126 beq r3,zero,8045adc <___svfiprintf_internal_r+0x28c> + 80458d8: 8821883a mov r16,r17 + 80458dc: 80800047 ldb r2,1(r16) + 80458e0: 84400044 addi r17,r16,1 + 80458e4: 10c00958 cmpnei r3,r2,37 + 80458e8: 103ffa1e bne r2,zero,80458d4 <___svfiprintf_internal_r+0x84> + 80458ec: 8f27c83a sub r19,r17,fp + 80458f0: 98008426 beq r19,zero,8045b04 <___svfiprintf_internal_r+0x2b4> + 80458f4: d8c00b17 ldw r3,44(sp) + 80458f8: d8800a17 ldw r2,40(sp) + 80458fc: 47000015 stw fp,0(r8) + 8045900: 1cc7883a add r3,r3,r19 + 8045904: 10800044 addi r2,r2,1 + 8045908: d8800a15 stw r2,40(sp) + 804590c: 44c00115 stw r19,4(r8) + 8045910: d8c00b15 stw r3,44(sp) + 8045914: 10800208 cmpgei r2,r2,8 + 8045918: 1000731e bne r2,zero,8045ae8 <___svfiprintf_internal_r+0x298> + 804591c: 42000204 addi r8,r8,8 + 8045920: d8c00017 ldw r3,0(sp) + 8045924: 80800047 ldb r2,1(r16) + 8045928: 1cc7883a add r3,r3,r19 + 804592c: d8c00015 stw r3,0(sp) + 8045930: 10007426 beq r2,zero,8045b04 <___svfiprintf_internal_r+0x2b4> + 8045934: 88800047 ldb r2,1(r17) + 8045938: 8f000044 addi fp,r17,1 + 804593c: d8000845 stb zero,33(sp) + 8045940: 000b883a mov r5,zero + 8045944: 000d883a mov r6,zero + 8045948: 027fffc4 movi r9,-1 + 804594c: 0021883a mov r16,zero + 8045950: 0019883a mov r12,zero + 8045954: e7000044 addi fp,fp,1 + 8045958: 10fff804 addi r3,r2,-32 + 804595c: 19001668 cmpgeui r4,r3,89 + 8045960: 20008a1e bne r4,zero,8045b8c <___svfiprintf_internal_r+0x33c> + 8045964: 180690ba slli r3,r3,2 + 8045968: 01020134 movhi r4,2052 + 804596c: 1909883a add r4,r3,r4 + 8045970: 20d65e17 ldw r3,22904(r4) + 8045974: 1800683a jmp r3 + 8045978: 08045c5c xori zero,at,4465 + 804597c: 08045b8c andi zero,at,4462 + 8045980: 08045b8c andi zero,at,4462 + 8045984: 08045c50 cmplti zero,at,4465 + 8045988: 08045b8c andi zero,at,4462 + 804598c: 08045b8c andi zero,at,4462 + 8045990: 08045b8c andi zero,at,4462 + 8045994: 08045b8c andi zero,at,4462 + 8045998: 08045b8c andi zero,at,4462 + 804599c: 08045b8c andi zero,at,4462 + 80459a0: 08045c28 cmpgeui zero,at,4464 + 80459a4: 08045c18 cmpnei zero,at,4464 + 80459a8: 08045b8c andi zero,at,4462 + 80459ac: 08045c00 call 8045c0 + 80459b0: 08045bbc xorhi zero,at,4462 + 80459b4: 08045b8c andi zero,at,4462 + 80459b8: 08045bb0 cmpltui zero,at,4462 + 80459bc: 08045b5c xori zero,at,4461 + 80459c0: 08045b5c xori zero,at,4461 + 80459c4: 08045b5c xori zero,at,4461 + 80459c8: 08045b5c xori zero,at,4461 + 80459cc: 08045b5c xori zero,at,4461 + 80459d0: 08045b5c xori zero,at,4461 + 80459d4: 08045b5c xori zero,at,4461 + 80459d8: 08045b5c xori zero,at,4461 + 80459dc: 08045b5c xori zero,at,4461 + 80459e0: 08045b8c andi zero,at,4462 + 80459e4: 08045b8c andi zero,at,4462 + 80459e8: 08045b8c andi zero,at,4462 + 80459ec: 08045b8c andi zero,at,4462 + 80459f0: 08045b8c andi zero,at,4462 + 80459f4: 08045b8c andi zero,at,4462 + 80459f8: 08045b8c andi zero,at,4462 + 80459fc: 08045b8c andi zero,at,4462 + 8045a00: 08045b8c andi zero,at,4462 + 8045a04: 08045b8c andi zero,at,4462 + 8045a08: 080461c8 cmpgei zero,at,4487 + 8045a0c: 08045b8c andi zero,at,4462 + 8045a10: 08045b8c andi zero,at,4462 + 8045a14: 08045b8c andi zero,at,4462 + 8045a18: 08045b8c andi zero,at,4462 + 8045a1c: 08045b8c andi zero,at,4462 + 8045a20: 08045b8c andi zero,at,4462 + 8045a24: 08045b8c andi zero,at,4462 + 8045a28: 08045b8c andi zero,at,4462 + 8045a2c: 08045b8c andi zero,at,4462 + 8045a30: 08045b8c andi zero,at,4462 + 8045a34: 08046194 ori zero,at,4486 + 8045a38: 08045b8c andi zero,at,4462 + 8045a3c: 08045b8c andi zero,at,4462 + 8045a40: 08045b8c andi zero,at,4462 + 8045a44: 08045b8c andi zero,at,4462 + 8045a48: 08045b8c andi zero,at,4462 + 8045a4c: 08046160 cmpeqi zero,at,4485 + 8045a50: 08045b8c andi zero,at,4462 + 8045a54: 08045b8c andi zero,at,4462 + 8045a58: 08046118 cmpnei zero,at,4484 + 8045a5c: 08045b8c andi zero,at,4462 + 8045a60: 08045b8c andi zero,at,4462 + 8045a64: 08045b8c andi zero,at,4462 + 8045a68: 08045b8c andi zero,at,4462 + 8045a6c: 08045b8c andi zero,at,4462 + 8045a70: 08045b8c andi zero,at,4462 + 8045a74: 08045b8c andi zero,at,4462 + 8045a78: 08045b8c andi zero,at,4462 + 8045a7c: 08045b8c andi zero,at,4462 + 8045a80: 08045b8c andi zero,at,4462 + 8045a84: 080460e8 cmpgeui zero,at,4483 + 8045a88: 08046074 orhi zero,at,4481 + 8045a8c: 08045b8c andi zero,at,4462 + 8045a90: 08045b8c andi zero,at,4462 + 8045a94: 08045b8c andi zero,at,4462 + 8045a98: 08046068 cmpgeui zero,at,4481 + 8045a9c: 08046074 orhi zero,at,4481 + 8045aa0: 08045b8c andi zero,at,4462 + 8045aa4: 08045b8c andi zero,at,4462 + 8045aa8: 08046054 ori zero,at,4481 + 8045aac: 08045b8c andi zero,at,4462 + 8045ab0: 08046014 ori zero,at,4480 + 8045ab4: 08045fd4 ori zero,at,4479 + 8045ab8: 08045d7c xorhi zero,at,4469 + 8045abc: 08045d70 cmpltui zero,at,4469 + 8045ac0: 08045b8c andi zero,at,4462 + 8045ac4: 08045d10 cmplti zero,at,4468 + 8045ac8: 08045b8c andi zero,at,4462 + 8045acc: 08045cd0 cmplti zero,at,4467 + 8045ad0: 08045b8c andi zero,at,4462 + 8045ad4: 08045b8c andi zero,at,4462 + 8045ad8: 08045c88 cmpgei zero,at,4466 + 8045adc: 8f27c83a sub r19,r17,fp + 8045ae0: 983f9426 beq r19,zero,8045934 <___svfiprintf_internal_r+0xe4> + 8045ae4: 003f8306 br 80458f4 <___svfiprintf_internal_r+0xa4> + 8045ae8: d9800904 addi r6,sp,36 + 8045aec: a00b883a mov r5,r20 + 8045af0: b009883a mov r4,r22 + 8045af4: 80456900 call 8045690 <__ssprint_r> + 8045af8: 1000081e bne r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc> + 8045afc: 9011883a mov r8,r18 + 8045b00: 003f8706 br 8045920 <___svfiprintf_internal_r+0xd0> + 8045b04: d8800b17 ldw r2,44(sp) + 8045b08: 10000426 beq r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc> + 8045b0c: d9800904 addi r6,sp,36 + 8045b10: a00b883a mov r5,r20 + 8045b14: b009883a mov r4,r22 + 8045b18: 80456900 call 8045690 <__ssprint_r> + 8045b1c: a080030b ldhu r2,12(r20) + 8045b20: 1080100c andi r2,r2,64 + 8045b24: 10037e1e bne r2,zero,8046920 <___svfiprintf_internal_r+0x10d0> + 8045b28: d8800017 ldw r2,0(sp) + 8045b2c: dfc02f17 ldw ra,188(sp) + 8045b30: df002e17 ldw fp,184(sp) + 8045b34: ddc02d17 ldw r23,180(sp) + 8045b38: dd802c17 ldw r22,176(sp) + 8045b3c: dd402b17 ldw r21,172(sp) + 8045b40: dd002a17 ldw r20,168(sp) + 8045b44: dcc02917 ldw r19,164(sp) + 8045b48: dc802817 ldw r18,160(sp) + 8045b4c: dc402717 ldw r17,156(sp) + 8045b50: dc002617 ldw r16,152(sp) + 8045b54: dec03004 addi sp,sp,192 + 8045b58: f800283a ret + 8045b5c: 0021883a mov r16,zero + 8045b60: 10fff404 addi r3,r2,-48 + 8045b64: e7000044 addi fp,fp,1 + 8045b68: 840002a4 muli r16,r16,10 + 8045b6c: e0bfffc7 ldb r2,-1(fp) + 8045b70: 1c21883a add r16,r3,r16 + 8045b74: 10fff404 addi r3,r2,-48 + 8045b78: 190002b0 cmpltui r4,r3,10 + 8045b7c: 203ff91e bne r4,zero,8045b64 <___svfiprintf_internal_r+0x314> + 8045b80: 10fff804 addi r3,r2,-32 + 8045b84: 19001668 cmpgeui r4,r3,89 + 8045b88: 203f7626 beq r4,zero,8045964 <___svfiprintf_internal_r+0x114> + 8045b8c: 29403fcc andi r5,r5,255 + 8045b90: 2803471e bne r5,zero,80468b0 <___svfiprintf_internal_r+0x1060> + 8045b94: 103fdb26 beq r2,zero,8045b04 <___svfiprintf_internal_r+0x2b4> + 8045b98: d8800c05 stb r2,48(sp) + 8045b9c: d8000845 stb zero,33(sp) + 8045ba0: 04c00044 movi r19,1 + 8045ba4: 05400044 movi r21,1 + 8045ba8: ddc00c04 addi r23,sp,48 + 8045bac: 00015706 br 804610c <___svfiprintf_internal_r+0x8bc> + 8045bb0: 63002014 ori r12,r12,128 + 8045bb4: e0800007 ldb r2,0(fp) + 8045bb8: 003f6606 br 8045954 <___svfiprintf_internal_r+0x104> + 8045bbc: e0800007 ldb r2,0(fp) + 8045bc0: e1000044 addi r4,fp,1 + 8045bc4: 10c00aa0 cmpeqi r3,r2,42 + 8045bc8: 1803581e bne r3,zero,804692c <___svfiprintf_internal_r+0x10dc> + 8045bcc: 10fff404 addi r3,r2,-48 + 8045bd0: 19c002b0 cmpltui r7,r3,10 + 8045bd4: 2039883a mov fp,r4 + 8045bd8: 0013883a mov r9,zero + 8045bdc: 383f5e26 beq r7,zero,8045958 <___svfiprintf_internal_r+0x108> + 8045be0: e7000044 addi fp,fp,1 + 8045be4: 4a4002a4 muli r9,r9,10 + 8045be8: e0bfffc7 ldb r2,-1(fp) + 8045bec: 48d3883a add r9,r9,r3 + 8045bf0: 10fff404 addi r3,r2,-48 + 8045bf4: 190002b0 cmpltui r4,r3,10 + 8045bf8: 203ff91e bne r4,zero,8045be0 <___svfiprintf_internal_r+0x390> + 8045bfc: 003f5606 br 8045958 <___svfiprintf_internal_r+0x108> + 8045c00: e0800003 ldbu r2,0(fp) + 8045c04: 10803fcc andi r2,r2,255 + 8045c08: 1080201c xori r2,r2,128 + 8045c0c: 63000114 ori r12,r12,4 + 8045c10: 10bfe004 addi r2,r2,-128 + 8045c14: 003f4f06 br 8045954 <___svfiprintf_internal_r+0x104> + 8045c18: 01400044 movi r5,1 + 8045c1c: 01800ac4 movi r6,43 + 8045c20: e0800007 ldb r2,0(fp) + 8045c24: 003f4b06 br 8045954 <___svfiprintf_internal_r+0x104> + 8045c28: d8800317 ldw r2,12(sp) + 8045c2c: 14000017 ldw r16,0(r2) + 8045c30: 15c00104 addi r23,r2,4 + 8045c34: e0800003 ldbu r2,0(fp) + 8045c38: 8002ee16 blt r16,zero,80467f4 <___svfiprintf_internal_r+0xfa4> + 8045c3c: ddc00315 stw r23,12(sp) + 8045c40: 10803fcc andi r2,r2,255 + 8045c44: 1080201c xori r2,r2,128 + 8045c48: 10bfe004 addi r2,r2,-128 + 8045c4c: 003f4106 br 8045954 <___svfiprintf_internal_r+0x104> + 8045c50: 63000054 ori r12,r12,1 + 8045c54: e0800007 ldb r2,0(fp) + 8045c58: 003f3e06 br 8045954 <___svfiprintf_internal_r+0x104> + 8045c5c: 30c03fcc andi r3,r6,255 + 8045c60: 18c0201c xori r3,r3,128 + 8045c64: 18ffe004 addi r3,r3,-128 + 8045c68: e0800003 ldbu r2,0(fp) + 8045c6c: 183ff41e bne r3,zero,8045c40 <___svfiprintf_internal_r+0x3f0> + 8045c70: 10803fcc andi r2,r2,255 + 8045c74: 1080201c xori r2,r2,128 + 8045c78: 01400044 movi r5,1 + 8045c7c: 01800804 movi r6,32 + 8045c80: 10bfe004 addi r2,r2,-128 + 8045c84: 003f3306 br 8045954 <___svfiprintf_internal_r+0x104> + 8045c88: 29403fcc andi r5,r5,255 + 8045c8c: 28030e1e bne r5,zero,80468c8 <___svfiprintf_internal_r+0x1078> + 8045c90: 00c20134 movhi r3,2052 + 8045c94: 18dd2004 addi r3,r3,29824 + 8045c98: d8c00415 stw r3,16(sp) + 8045c9c: 60c0080c andi r3,r12,32 + 8045ca0: 18012426 beq r3,zero,8046134 <___svfiprintf_internal_r+0x8e4> + 8045ca4: d8c00317 ldw r3,12(sp) + 8045ca8: 1cc00017 ldw r19,0(r3) + 8045cac: 1d400117 ldw r21,4(r3) + 8045cb0: 18c00204 addi r3,r3,8 + 8045cb4: d8c00315 stw r3,12(sp) + 8045cb8: 60c0004c andi r3,r12,1 + 8045cbc: 18000226 beq r3,zero,8045cc8 <___svfiprintf_internal_r+0x478> + 8045cc0: 9d46b03a or r3,r19,r21 + 8045cc4: 1802811e bne r3,zero,80466cc <___svfiprintf_internal_r+0xe7c> + 8045cc8: 00800084 movi r2,2 + 8045ccc: 00003906 br 8045db4 <___svfiprintf_internal_r+0x564> + 8045cd0: 29403fcc andi r5,r5,255 + 8045cd4: 2803081e bne r5,zero,80468f8 <___svfiprintf_internal_r+0x10a8> + 8045cd8: 6080080c andi r2,r12,32 + 8045cdc: 10017e1e bne r2,zero,80462d8 <___svfiprintf_internal_r+0xa88> + 8045ce0: d8800317 ldw r2,12(sp) + 8045ce4: 60c0040c andi r3,r12,16 + 8045ce8: 14c00017 ldw r19,0(r2) + 8045cec: 10800104 addi r2,r2,4 + 8045cf0: 1801221e bne r3,zero,804617c <___svfiprintf_internal_r+0x92c> + 8045cf4: 60c0100c andi r3,r12,64 + 8045cf8: 1802e626 beq r3,zero,8046894 <___svfiprintf_internal_r+0x1044> + 8045cfc: d8800315 stw r2,12(sp) + 8045d00: 9cffffcc andi r19,r19,65535 + 8045d04: 002b883a mov r21,zero + 8045d08: 00800044 movi r2,1 + 8045d0c: 00002906 br 8045db4 <___svfiprintf_internal_r+0x564> + 8045d10: d8800317 ldw r2,12(sp) + 8045d14: d8000845 stb zero,33(sp) + 8045d18: 15c00017 ldw r23,0(r2) + 8045d1c: 14400104 addi r17,r2,4 + 8045d20: b802cf26 beq r23,zero,8046860 <___svfiprintf_internal_r+0x1010> + 8045d24: 48bfffe0 cmpeqi r2,r9,-1 + 8045d28: 10026e1e bne r2,zero,80466e4 <___svfiprintf_internal_r+0xe94> + 8045d2c: 480d883a mov r6,r9 + 8045d30: 000b883a mov r5,zero + 8045d34: b809883a mov r4,r23 + 8045d38: da000315 stw r8,12(sp) + 8045d3c: db000215 stw r12,8(sp) + 8045d40: da400115 stw r9,4(sp) + 8045d44: 80085d00 call 80085d0 + 8045d48: da400117 ldw r9,4(sp) + 8045d4c: db000217 ldw r12,8(sp) + 8045d50: da000317 ldw r8,12(sp) + 8045d54: 1002d826 beq r2,zero,80468b8 <___svfiprintf_internal_r+0x1068> + 8045d58: 15ebc83a sub r21,r2,r23 + 8045d5c: a827883a mov r19,r21 + 8045d60: a800010e bge r21,zero,8045d68 <___svfiprintf_internal_r+0x518> + 8045d64: 0027883a mov r19,zero + 8045d68: dc400315 stw r17,12(sp) + 8045d6c: 0000e706 br 804610c <___svfiprintf_internal_r+0x8bc> + 8045d70: 63000814 ori r12,r12,32 + 8045d74: e0800007 ldb r2,0(fp) + 8045d78: 003ef606 br 8045954 <___svfiprintf_internal_r+0x104> + 8045d7c: d8c00317 ldw r3,12(sp) + 8045d80: 00800c04 movi r2,48 + 8045d84: d8800885 stb r2,34(sp) + 8045d88: 00801e04 movi r2,120 + 8045d8c: 01020134 movhi r4,2052 + 8045d90: d88008c5 stb r2,35(sp) + 8045d94: 1cc00017 ldw r19,0(r3) + 8045d98: 18800104 addi r2,r3,4 + 8045d9c: d8800315 stw r2,12(sp) + 8045da0: 209d2004 addi r2,r4,29824 + 8045da4: d8800415 stw r2,16(sp) + 8045da8: 002b883a mov r21,zero + 8045dac: 63000094 ori r12,r12,2 + 8045db0: 00800084 movi r2,2 + 8045db4: d8000845 stb zero,33(sp) + 8045db8: 48ffffe0 cmpeqi r3,r9,-1 + 8045dbc: 001b883a mov r13,zero + 8045dc0: 1801181e bne r3,zero,8046224 <___svfiprintf_internal_r+0x9d4> + 8045dc4: 047fdfc4 movi r17,-129 + 8045dc8: 9d46b03a or r3,r19,r21 + 8045dcc: 6462703a and r17,r12,r17 + 8045dd0: 1801d21e bne r3,zero,804651c <___svfiprintf_internal_r+0xccc> + 8045dd4: 48028a1e bne r9,zero,8046800 <___svfiprintf_internal_r+0xfb0> + 8045dd8: 1000bf1e bne r2,zero,80460d8 <___svfiprintf_internal_r+0x888> + 8045ddc: 6540004c andi r21,r12,1 + 8045de0: a8023126 beq r21,zero,80466a8 <___svfiprintf_internal_r+0xe58> + 8045de4: 00800c04 movi r2,48 + 8045de8: d88015c5 stb r2,87(sp) + 8045dec: ddc015c4 addi r23,sp,87 + 8045df0: 4827883a mov r19,r9 + 8045df4: 4d40010e bge r9,r21,8045dfc <___svfiprintf_internal_r+0x5ac> + 8045df8: a827883a mov r19,r21 + 8045dfc: 6b403fcc andi r13,r13,255 + 8045e00: 6b40201c xori r13,r13,128 + 8045e04: 6b7fe004 addi r13,r13,-128 + 8045e08: 68000126 beq r13,zero,8045e10 <___svfiprintf_internal_r+0x5c0> + 8045e0c: 9cc00044 addi r19,r19,1 + 8045e10: 8b40008c andi r13,r17,2 + 8045e14: 68000126 beq r13,zero,8045e1c <___svfiprintf_internal_r+0x5cc> + 8045e18: 9cc00084 addi r19,r19,2 + 8045e1c: 8b00210c andi r12,r17,132 + 8045e20: d8800b17 ldw r2,44(sp) + 8045e24: d9000a17 ldw r4,40(sp) + 8045e28: 6000021e bne r12,zero,8045e34 <___svfiprintf_internal_r+0x5e4> + 8045e2c: 84c7c83a sub r3,r16,r19 + 8045e30: 00c1bc16 blt zero,r3,8046524 <___svfiprintf_internal_r+0xcd4> + 8045e34: d9800847 ldb r6,33(sp) + 8045e38: 21400044 addi r5,r4,1 + 8045e3c: 40c00204 addi r3,r8,8 + 8045e40: 30000f26 beq r6,zero,8045e80 <___svfiprintf_internal_r+0x630> + 8045e44: d9800844 addi r6,sp,33 + 8045e48: 10800044 addi r2,r2,1 + 8045e4c: 41800015 stw r6,0(r8) + 8045e50: 01800044 movi r6,1 + 8045e54: 41800115 stw r6,4(r8) + 8045e58: d8800b15 stw r2,44(sp) + 8045e5c: d9400a15 stw r5,40(sp) + 8045e60: 29800208 cmpgei r6,r5,8 + 8045e64: 3001e11e bne r6,zero,80465ec <___svfiprintf_internal_r+0xd9c> + 8045e68: 21c00084 addi r7,r4,2 + 8045e6c: 41800404 addi r6,r8,16 + 8045e70: 2809883a mov r4,r5 + 8045e74: 1811883a mov r8,r3 + 8045e78: 380b883a mov r5,r7 + 8045e7c: 3007883a mov r3,r6 + 8045e80: 68000d26 beq r13,zero,8045eb8 <___svfiprintf_internal_r+0x668> + 8045e84: d9000884 addi r4,sp,34 + 8045e88: 10800084 addi r2,r2,2 + 8045e8c: 41000015 stw r4,0(r8) + 8045e90: 01000084 movi r4,2 + 8045e94: 41000115 stw r4,4(r8) + 8045e98: d8800b15 stw r2,44(sp) + 8045e9c: d9400a15 stw r5,40(sp) + 8045ea0: 29000208 cmpgei r4,r5,8 + 8045ea4: 2001e21e bne r4,zero,8046630 <___svfiprintf_internal_r+0xde0> + 8045ea8: 2809883a mov r4,r5 + 8045eac: 1811883a mov r8,r3 + 8045eb0: 29400044 addi r5,r5,1 + 8045eb4: 18c00204 addi r3,r3,8 + 8045eb8: 63002018 cmpnei r12,r12,128 + 8045ebc: 60011626 beq r12,zero,8046318 <___svfiprintf_internal_r+0xac8> + 8045ec0: 4d53c83a sub r9,r9,r21 + 8045ec4: 02414816 blt zero,r9,80463e8 <___svfiprintf_internal_r+0xb98> + 8045ec8: a885883a add r2,r21,r2 + 8045ecc: 45c00015 stw r23,0(r8) + 8045ed0: 45400115 stw r21,4(r8) + 8045ed4: d8800b15 stw r2,44(sp) + 8045ed8: d9400a15 stw r5,40(sp) + 8045edc: 29000210 cmplti r4,r5,8 + 8045ee0: 20017026 beq r4,zero,80464a4 <___svfiprintf_internal_r+0xc54> + 8045ee4: 8c40010c andi r17,r17,4 + 8045ee8: 88000226 beq r17,zero,8045ef4 <___svfiprintf_internal_r+0x6a4> + 8045eec: 84e3c83a sub r17,r16,r19 + 8045ef0: 04400916 blt zero,r17,8045f18 <___svfiprintf_internal_r+0x6c8> + 8045ef4: 84c0010e bge r16,r19,8045efc <___svfiprintf_internal_r+0x6ac> + 8045ef8: 9821883a mov r16,r19 + 8045efc: d8c00017 ldw r3,0(sp) + 8045f00: 1c07883a add r3,r3,r16 + 8045f04: d8c00015 stw r3,0(sp) + 8045f08: 10017e1e bne r2,zero,8046504 <___svfiprintf_internal_r+0xcb4> + 8045f0c: d8000a15 stw zero,40(sp) + 8045f10: 9011883a mov r8,r18 + 8045f14: 003e6906 br 80458bc <___svfiprintf_internal_r+0x6c> + 8045f18: 01c20174 movhi r7,2053 + 8045f1c: 89400450 cmplti r5,r17,17 + 8045f20: 39ee4044 addi r7,r7,-18175 + 8045f24: d9000a17 ldw r4,40(sp) + 8045f28: 05400404 movi r21,16 + 8045f2c: 28000526 beq r5,zero,8045f44 <___svfiprintf_internal_r+0x6f4> + 8045f30: 00001906 br 8045f98 <___svfiprintf_internal_r+0x748> + 8045f34: 8c7ffc04 addi r17,r17,-16 + 8045f38: 89400448 cmpgei r5,r17,17 + 8045f3c: 18c00204 addi r3,r3,8 + 8045f40: 28001526 beq r5,zero,8045f98 <___svfiprintf_internal_r+0x748> + 8045f44: 21000044 addi r4,r4,1 + 8045f48: 10800404 addi r2,r2,16 + 8045f4c: 19c00015 stw r7,0(r3) + 8045f50: 1d400115 stw r21,4(r3) + 8045f54: d8800b15 stw r2,44(sp) + 8045f58: d9000a15 stw r4,40(sp) + 8045f5c: 21400208 cmpgei r5,r4,8 + 8045f60: 283ff426 beq r5,zero,8045f34 <___svfiprintf_internal_r+0x6e4> + 8045f64: d9800904 addi r6,sp,36 + 8045f68: a00b883a mov r5,r20 + 8045f6c: b009883a mov r4,r22 + 8045f70: d9c00115 stw r7,4(sp) + 8045f74: 80456900 call 8045690 <__ssprint_r> + 8045f78: 103ee81e bne r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc> + 8045f7c: 8c7ffc04 addi r17,r17,-16 + 8045f80: 89400448 cmpgei r5,r17,17 + 8045f84: d8800b17 ldw r2,44(sp) + 8045f88: d9000a17 ldw r4,40(sp) + 8045f8c: 9007883a mov r3,r18 + 8045f90: d9c00117 ldw r7,4(sp) + 8045f94: 283feb1e bne r5,zero,8045f44 <___svfiprintf_internal_r+0x6f4> + 8045f98: 21000044 addi r4,r4,1 + 8045f9c: 1445883a add r2,r2,r17 + 8045fa0: d9000a15 stw r4,40(sp) + 8045fa4: 19c00015 stw r7,0(r3) + 8045fa8: 1c400115 stw r17,4(r3) + 8045fac: d8800b15 stw r2,44(sp) + 8045fb0: 21000210 cmplti r4,r4,8 + 8045fb4: 203fcf1e bne r4,zero,8045ef4 <___svfiprintf_internal_r+0x6a4> + 8045fb8: d9800904 addi r6,sp,36 + 8045fbc: a00b883a mov r5,r20 + 8045fc0: b009883a mov r4,r22 + 8045fc4: 80456900 call 8045690 <__ssprint_r> + 8045fc8: 103ed41e bne r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc> + 8045fcc: d8800b17 ldw r2,44(sp) + 8045fd0: 003fc806 br 8045ef4 <___svfiprintf_internal_r+0x6a4> + 8045fd4: 29403fcc andi r5,r5,255 + 8045fd8: 28024b1e bne r5,zero,8046908 <___svfiprintf_internal_r+0x10b8> + 8045fdc: 6080080c andi r2,r12,32 + 8045fe0: 1000af1e bne r2,zero,80462a0 <___svfiprintf_internal_r+0xa50> + 8045fe4: d8800317 ldw r2,12(sp) + 8045fe8: 60c0040c andi r3,r12,16 + 8045fec: 14c00017 ldw r19,0(r2) + 8045ff0: 10800104 addi r2,r2,4 + 8045ff4: 18006e1e bne r3,zero,80461b0 <___svfiprintf_internal_r+0x960> + 8045ff8: 60c0100c andi r3,r12,64 + 8045ffc: 18022126 beq r3,zero,8046884 <___svfiprintf_internal_r+0x1034> + 8046000: d8800315 stw r2,12(sp) + 8046004: 9cffffcc andi r19,r19,65535 + 8046008: 002b883a mov r21,zero + 804600c: 0005883a mov r2,zero + 8046010: 003f6806 br 8045db4 <___svfiprintf_internal_r+0x564> + 8046014: 29403fcc andi r5,r5,255 + 8046018: 2802391e bne r5,zero,8046900 <___svfiprintf_internal_r+0x10b0> + 804601c: d9000317 ldw r4,12(sp) + 8046020: 6080080c andi r2,r12,32 + 8046024: 20c00104 addi r3,r4,4 + 8046028: 1001a11e bne r2,zero,80466b0 <___svfiprintf_internal_r+0xe60> + 804602c: 6080040c andi r2,r12,16 + 8046030: 1001be1e bne r2,zero,804672c <___svfiprintf_internal_r+0xedc> + 8046034: 6300100c andi r12,r12,64 + 8046038: 6001bc26 beq r12,zero,804672c <___svfiprintf_internal_r+0xedc> + 804603c: d8800317 ldw r2,12(sp) + 8046040: d8c00315 stw r3,12(sp) + 8046044: d8c00017 ldw r3,0(sp) + 8046048: 10800017 ldw r2,0(r2) + 804604c: 10c0000d sth r3,0(r2) + 8046050: 003e1a06 br 80458bc <___svfiprintf_internal_r+0x6c> + 8046054: e0800007 ldb r2,0(fp) + 8046058: 10c01b18 cmpnei r3,r2,108 + 804605c: 1801ec26 beq r3,zero,8046810 <___svfiprintf_internal_r+0xfc0> + 8046060: 63000414 ori r12,r12,16 + 8046064: 003e3b06 br 8045954 <___svfiprintf_internal_r+0x104> + 8046068: 63001014 ori r12,r12,64 + 804606c: e0800007 ldb r2,0(fp) + 8046070: 003e3806 br 8045954 <___svfiprintf_internal_r+0x104> + 8046074: 29403fcc andi r5,r5,255 + 8046078: 28021d1e bne r5,zero,80468f0 <___svfiprintf_internal_r+0x10a0> + 804607c: 6080080c andi r2,r12,32 + 8046080: 10008e1e bne r2,zero,80462bc <___svfiprintf_internal_r+0xa6c> + 8046084: d8800317 ldw r2,12(sp) + 8046088: 60c0040c andi r3,r12,16 + 804608c: 10800104 addi r2,r2,4 + 8046090: 1800541e bne r3,zero,80461e4 <___svfiprintf_internal_r+0x994> + 8046094: 60c0100c andi r3,r12,64 + 8046098: 18005226 beq r3,zero,80461e4 <___svfiprintf_internal_r+0x994> + 804609c: d8c00317 ldw r3,12(sp) + 80460a0: d8800315 stw r2,12(sp) + 80460a4: 1cc0000f ldh r19,0(r3) + 80460a8: 982bd7fa srai r21,r19,31 + 80460ac: a805883a mov r2,r21 + 80460b0: 10005216 blt r2,zero,80461fc <___svfiprintf_internal_r+0x9ac> + 80460b4: 48bfffd8 cmpnei r2,r9,-1 + 80460b8: db400843 ldbu r13,33(sp) + 80460bc: 10008d26 beq r2,zero,80462f4 <___svfiprintf_internal_r+0xaa4> + 80460c0: 00ffdfc4 movi r3,-129 + 80460c4: 9d44b03a or r2,r19,r21 + 80460c8: 60d8703a and r12,r12,r3 + 80460cc: 1000891e bne r2,zero,80462f4 <___svfiprintf_internal_r+0xaa4> + 80460d0: 48008b1e bne r9,zero,8046300 <___svfiprintf_internal_r+0xab0> + 80460d4: 6023883a mov r17,r12 + 80460d8: 0013883a mov r9,zero + 80460dc: 002b883a mov r21,zero + 80460e0: 902f883a mov r23,r18 + 80460e4: 003f4206 br 8045df0 <___svfiprintf_internal_r+0x5a0> + 80460e8: d8c00317 ldw r3,12(sp) + 80460ec: d8000845 stb zero,33(sp) + 80460f0: 04c00044 movi r19,1 + 80460f4: 18800017 ldw r2,0(r3) + 80460f8: 18c00104 addi r3,r3,4 + 80460fc: d8c00315 stw r3,12(sp) + 8046100: d8800c05 stb r2,48(sp) + 8046104: 05400044 movi r21,1 + 8046108: ddc00c04 addi r23,sp,48 + 804610c: 6023883a mov r17,r12 + 8046110: 0013883a mov r9,zero + 8046114: 003f3e06 br 8045e10 <___svfiprintf_internal_r+0x5c0> + 8046118: 29403fcc andi r5,r5,255 + 804611c: 2801ec1e bne r5,zero,80468d0 <___svfiprintf_internal_r+0x1080> + 8046120: 00c20134 movhi r3,2052 + 8046124: 18dd1b04 addi r3,r3,29804 + 8046128: d8c00415 stw r3,16(sp) + 804612c: 60c0080c andi r3,r12,32 + 8046130: 183edc1e bne r3,zero,8045ca4 <___svfiprintf_internal_r+0x454> + 8046134: d9000317 ldw r4,12(sp) + 8046138: 60c0040c andi r3,r12,16 + 804613c: 24c00017 ldw r19,0(r4) + 8046140: 21000104 addi r4,r4,4 + 8046144: d9000315 stw r4,12(sp) + 8046148: 1801481e bne r3,zero,804666c <___svfiprintf_internal_r+0xe1c> + 804614c: 60c0100c andi r3,r12,64 + 8046150: 18014626 beq r3,zero,804666c <___svfiprintf_internal_r+0xe1c> + 8046154: 9cffffcc andi r19,r19,65535 + 8046158: 002b883a mov r21,zero + 804615c: 003ed606 br 8045cb8 <___svfiprintf_internal_r+0x468> + 8046160: 29403fcc andi r5,r5,255 + 8046164: 2801dc1e bne r5,zero,80468d8 <___svfiprintf_internal_r+0x1088> + 8046168: 6080080c andi r2,r12,32 + 804616c: 63000414 ori r12,r12,16 + 8046170: 1000591e bne r2,zero,80462d8 <___svfiprintf_internal_r+0xa88> + 8046174: d8800317 ldw r2,12(sp) + 8046178: 10800104 addi r2,r2,4 + 804617c: d8c00317 ldw r3,12(sp) + 8046180: 002b883a mov r21,zero + 8046184: d8800315 stw r2,12(sp) + 8046188: 1cc00017 ldw r19,0(r3) + 804618c: 00800044 movi r2,1 + 8046190: 003f0806 br 8045db4 <___svfiprintf_internal_r+0x564> + 8046194: 29403fcc andi r5,r5,255 + 8046198: 2801d11e bne r5,zero,80468e0 <___svfiprintf_internal_r+0x1090> + 804619c: 6080080c andi r2,r12,32 + 80461a0: 63000414 ori r12,r12,16 + 80461a4: 10003e1e bne r2,zero,80462a0 <___svfiprintf_internal_r+0xa50> + 80461a8: d8800317 ldw r2,12(sp) + 80461ac: 10800104 addi r2,r2,4 + 80461b0: d8c00317 ldw r3,12(sp) + 80461b4: 002b883a mov r21,zero + 80461b8: d8800315 stw r2,12(sp) + 80461bc: 1cc00017 ldw r19,0(r3) + 80461c0: 0005883a mov r2,zero + 80461c4: 003efb06 br 8045db4 <___svfiprintf_internal_r+0x564> + 80461c8: 29403fcc andi r5,r5,255 + 80461cc: 2801c61e bne r5,zero,80468e8 <___svfiprintf_internal_r+0x1098> + 80461d0: 6080080c andi r2,r12,32 + 80461d4: 63000414 ori r12,r12,16 + 80461d8: 1000381e bne r2,zero,80462bc <___svfiprintf_internal_r+0xa6c> + 80461dc: d8800317 ldw r2,12(sp) + 80461e0: 10800104 addi r2,r2,4 + 80461e4: d8c00317 ldw r3,12(sp) + 80461e8: 1cc00017 ldw r19,0(r3) + 80461ec: d8800315 stw r2,12(sp) + 80461f0: 982bd7fa srai r21,r19,31 + 80461f4: a805883a mov r2,r21 + 80461f8: 103fae0e bge r2,zero,80460b4 <___svfiprintf_internal_r+0x864> + 80461fc: 04e7c83a sub r19,zero,r19 + 8046200: 9804c03a cmpne r2,r19,zero + 8046204: 056bc83a sub r21,zero,r21 + 8046208: a8abc83a sub r21,r21,r2 + 804620c: 00800b44 movi r2,45 + 8046210: d8800845 stb r2,33(sp) + 8046214: 48ffffe0 cmpeqi r3,r9,-1 + 8046218: 03400b44 movi r13,45 + 804621c: 00800044 movi r2,1 + 8046220: 183ee826 beq r3,zero,8045dc4 <___svfiprintf_internal_r+0x574> + 8046224: 10c00060 cmpeqi r3,r2,1 + 8046228: 1800321e bne r3,zero,80462f4 <___svfiprintf_internal_r+0xaa4> + 804622c: 108000a0 cmpeqi r2,r2,2 + 8046230: 1000a41e bne r2,zero,80464c4 <___svfiprintf_internal_r+0xc74> + 8046234: 9007883a mov r3,r18 + 8046238: 00000106 br 8046240 <___svfiprintf_internal_r+0x9f0> + 804623c: b807883a mov r3,r23 + 8046240: 9808d0fa srli r4,r19,3 + 8046244: a80a977a slli r5,r21,29 + 8046248: a82ad0fa srli r21,r21,3 + 804624c: 9cc001cc andi r19,r19,7 + 8046250: 98800c04 addi r2,r19,48 + 8046254: 2926b03a or r19,r5,r4 + 8046258: 18bfffc5 stb r2,-1(r3) + 804625c: 9d48b03a or r4,r19,r21 + 8046260: 1dffffc4 addi r23,r3,-1 + 8046264: 203ff51e bne r4,zero,804623c <___svfiprintf_internal_r+0x9ec> + 8046268: 6100004c andi r4,r12,1 + 804626c: 2000a226 beq r4,zero,80464f8 <___svfiprintf_internal_r+0xca8> + 8046270: 10803fcc andi r2,r2,255 + 8046274: 1080201c xori r2,r2,128 + 8046278: 10bfe004 addi r2,r2,-128 + 804627c: 10800c18 cmpnei r2,r2,48 + 8046280: 10009d26 beq r2,zero,80464f8 <___svfiprintf_internal_r+0xca8> + 8046284: 18ffff84 addi r3,r3,-2 + 8046288: 00800c04 movi r2,48 + 804628c: b8bfffc5 stb r2,-1(r23) + 8046290: 90ebc83a sub r21,r18,r3 + 8046294: 6023883a mov r17,r12 + 8046298: 182f883a mov r23,r3 + 804629c: 003ed406 br 8045df0 <___svfiprintf_internal_r+0x5a0> + 80462a0: d8c00317 ldw r3,12(sp) + 80462a4: 0005883a mov r2,zero + 80462a8: 1cc00017 ldw r19,0(r3) + 80462ac: 1d400117 ldw r21,4(r3) + 80462b0: 18c00204 addi r3,r3,8 + 80462b4: d8c00315 stw r3,12(sp) + 80462b8: 003ebe06 br 8045db4 <___svfiprintf_internal_r+0x564> + 80462bc: d8c00317 ldw r3,12(sp) + 80462c0: 18800117 ldw r2,4(r3) + 80462c4: 1cc00017 ldw r19,0(r3) + 80462c8: 18c00204 addi r3,r3,8 + 80462cc: d8c00315 stw r3,12(sp) + 80462d0: 102b883a mov r21,r2 + 80462d4: 003f7606 br 80460b0 <___svfiprintf_internal_r+0x860> + 80462d8: d8c00317 ldw r3,12(sp) + 80462dc: 00800044 movi r2,1 + 80462e0: 1cc00017 ldw r19,0(r3) + 80462e4: 1d400117 ldw r21,4(r3) + 80462e8: 18c00204 addi r3,r3,8 + 80462ec: d8c00315 stw r3,12(sp) + 80462f0: 003eb006 br 8045db4 <___svfiprintf_internal_r+0x564> + 80462f4: a801131e bne r21,zero,8046744 <___svfiprintf_internal_r+0xef4> + 80462f8: 988002a8 cmpgeui r2,r19,10 + 80462fc: 1001111e bne r2,zero,8046744 <___svfiprintf_internal_r+0xef4> + 8046300: 9cc00c04 addi r19,r19,48 + 8046304: dcc015c5 stb r19,87(sp) + 8046308: 6023883a mov r17,r12 + 804630c: 05400044 movi r21,1 + 8046310: ddc015c4 addi r23,sp,87 + 8046314: 003eb606 br 8045df0 <___svfiprintf_internal_r+0x5a0> + 8046318: 84d9c83a sub r12,r16,r19 + 804631c: 033ee80e bge zero,r12,8045ec0 <___svfiprintf_internal_r+0x670> + 8046320: 61800450 cmplti r6,r12,17 + 8046324: 01c20174 movhi r7,2053 + 8046328: 3001791e bne r6,zero,8046910 <___svfiprintf_internal_r+0x10c0> + 804632c: 39ee3c44 addi r7,r7,-18191 + 8046330: 03400404 movi r13,16 + 8046334: 00000406 br 8046348 <___svfiprintf_internal_r+0xaf8> + 8046338: 633ffc04 addi r12,r12,-16 + 804633c: 60c00448 cmpgei r3,r12,17 + 8046340: 42000204 addi r8,r8,8 + 8046344: 18001a26 beq r3,zero,80463b0 <___svfiprintf_internal_r+0xb60> + 8046348: 21000044 addi r4,r4,1 + 804634c: 10800404 addi r2,r2,16 + 8046350: 41c00015 stw r7,0(r8) + 8046354: 43400115 stw r13,4(r8) + 8046358: d8800b15 stw r2,44(sp) + 804635c: d9000a15 stw r4,40(sp) + 8046360: 20c00208 cmpgei r3,r4,8 + 8046364: 183ff426 beq r3,zero,8046338 <___svfiprintf_internal_r+0xae8> + 8046368: d9800904 addi r6,sp,36 + 804636c: a00b883a mov r5,r20 + 8046370: b009883a mov r4,r22 + 8046374: d9c00515 stw r7,20(sp) + 8046378: db000215 stw r12,8(sp) + 804637c: da400115 stw r9,4(sp) + 8046380: 80456900 call 8045690 <__ssprint_r> + 8046384: 103de51e bne r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc> + 8046388: db000217 ldw r12,8(sp) + 804638c: d8800b17 ldw r2,44(sp) + 8046390: d9000a17 ldw r4,40(sp) + 8046394: 633ffc04 addi r12,r12,-16 + 8046398: 60c00448 cmpgei r3,r12,17 + 804639c: 9011883a mov r8,r18 + 80463a0: d9c00517 ldw r7,20(sp) + 80463a4: 03400404 movi r13,16 + 80463a8: da400117 ldw r9,4(sp) + 80463ac: 183fe61e bne r3,zero,8046348 <___svfiprintf_internal_r+0xaf8> + 80463b0: 21000044 addi r4,r4,1 + 80463b4: 41800204 addi r6,r8,8 + 80463b8: 1305883a add r2,r2,r12 + 80463bc: 41c00015 stw r7,0(r8) + 80463c0: 43000115 stw r12,4(r8) + 80463c4: d8800b15 stw r2,44(sp) + 80463c8: d9000a15 stw r4,40(sp) + 80463cc: 20c00208 cmpgei r3,r4,8 + 80463d0: 1801161e bne r3,zero,804682c <___svfiprintf_internal_r+0xfdc> + 80463d4: 4d53c83a sub r9,r9,r21 + 80463d8: 21400044 addi r5,r4,1 + 80463dc: 30c00204 addi r3,r6,8 + 80463e0: 3011883a mov r8,r6 + 80463e4: 027eb80e bge zero,r9,8045ec8 <___svfiprintf_internal_r+0x678> + 80463e8: 49800450 cmplti r6,r9,17 + 80463ec: 01c20174 movhi r7,2053 + 80463f0: 30012c1e bne r6,zero,80468a4 <___svfiprintf_internal_r+0x1054> + 80463f4: 39ee3c44 addi r7,r7,-18191 + 80463f8: 03000404 movi r12,16 + 80463fc: 00000406 br 8046410 <___svfiprintf_internal_r+0xbc0> + 8046400: 4a7ffc04 addi r9,r9,-16 + 8046404: 48c00448 cmpgei r3,r9,17 + 8046408: 42000204 addi r8,r8,8 + 804640c: 18001826 beq r3,zero,8046470 <___svfiprintf_internal_r+0xc20> + 8046410: 21000044 addi r4,r4,1 + 8046414: 10800404 addi r2,r2,16 + 8046418: 41c00015 stw r7,0(r8) + 804641c: 43000115 stw r12,4(r8) + 8046420: d8800b15 stw r2,44(sp) + 8046424: d9000a15 stw r4,40(sp) + 8046428: 20c00208 cmpgei r3,r4,8 + 804642c: 183ff426 beq r3,zero,8046400 <___svfiprintf_internal_r+0xbb0> + 8046430: d9800904 addi r6,sp,36 + 8046434: a00b883a mov r5,r20 + 8046438: b009883a mov r4,r22 + 804643c: d9c00215 stw r7,8(sp) + 8046440: da400115 stw r9,4(sp) + 8046444: 80456900 call 8045690 <__ssprint_r> + 8046448: 103db41e bne r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc> + 804644c: da400117 ldw r9,4(sp) + 8046450: d8800b17 ldw r2,44(sp) + 8046454: d9000a17 ldw r4,40(sp) + 8046458: 4a7ffc04 addi r9,r9,-16 + 804645c: 48c00448 cmpgei r3,r9,17 + 8046460: 9011883a mov r8,r18 + 8046464: d9c00217 ldw r7,8(sp) + 8046468: 03000404 movi r12,16 + 804646c: 183fe81e bne r3,zero,8046410 <___svfiprintf_internal_r+0xbc0> + 8046470: 21400044 addi r5,r4,1 + 8046474: 41000204 addi r4,r8,8 + 8046478: 1245883a add r2,r2,r9 + 804647c: 41c00015 stw r7,0(r8) + 8046480: 42400115 stw r9,4(r8) + 8046484: d8800b15 stw r2,44(sp) + 8046488: d9400a15 stw r5,40(sp) + 804648c: 28c00208 cmpgei r3,r5,8 + 8046490: 1800781e bne r3,zero,8046674 <___svfiprintf_internal_r+0xe24> + 8046494: 29400044 addi r5,r5,1 + 8046498: 20c00204 addi r3,r4,8 + 804649c: 2011883a mov r8,r4 + 80464a0: 003e8906 br 8045ec8 <___svfiprintf_internal_r+0x678> + 80464a4: d9800904 addi r6,sp,36 + 80464a8: a00b883a mov r5,r20 + 80464ac: b009883a mov r4,r22 + 80464b0: 80456900 call 8045690 <__ssprint_r> + 80464b4: 103d991e bne r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc> + 80464b8: d8800b17 ldw r2,44(sp) + 80464bc: 9007883a mov r3,r18 + 80464c0: 003e8806 br 8045ee4 <___svfiprintf_internal_r+0x694> + 80464c4: 902f883a mov r23,r18 + 80464c8: d9000417 ldw r4,16(sp) + 80464cc: 988003cc andi r2,r19,15 + 80464d0: a806973a slli r3,r21,28 + 80464d4: 2085883a add r2,r4,r2 + 80464d8: 9826d13a srli r19,r19,4 + 80464dc: 10800003 ldbu r2,0(r2) + 80464e0: a82ad13a srli r21,r21,4 + 80464e4: bdffffc4 addi r23,r23,-1 + 80464e8: 1ce6b03a or r19,r3,r19 + 80464ec: b8800005 stb r2,0(r23) + 80464f0: 9d44b03a or r2,r19,r21 + 80464f4: 103ff41e bne r2,zero,80464c8 <___svfiprintf_internal_r+0xc78> + 80464f8: 95ebc83a sub r21,r18,r23 + 80464fc: 6023883a mov r17,r12 + 8046500: 003e3b06 br 8045df0 <___svfiprintf_internal_r+0x5a0> + 8046504: d9800904 addi r6,sp,36 + 8046508: a00b883a mov r5,r20 + 804650c: b009883a mov r4,r22 + 8046510: 80456900 call 8045690 <__ssprint_r> + 8046514: 103e7d26 beq r2,zero,8045f0c <___svfiprintf_internal_r+0x6bc> + 8046518: 003d8006 br 8045b1c <___svfiprintf_internal_r+0x2cc> + 804651c: 8819883a mov r12,r17 + 8046520: 003f4006 br 8046224 <___svfiprintf_internal_r+0x9d4> + 8046524: 01c20174 movhi r7,2053 + 8046528: 19400450 cmplti r5,r3,17 + 804652c: 39ee4044 addi r7,r7,-18175 + 8046530: 03800404 movi r14,16 + 8046534: 28000526 beq r5,zero,804654c <___svfiprintf_internal_r+0xcfc> + 8046538: 00002206 br 80465c4 <___svfiprintf_internal_r+0xd74> + 804653c: 18fffc04 addi r3,r3,-16 + 8046540: 19400448 cmpgei r5,r3,17 + 8046544: 42000204 addi r8,r8,8 + 8046548: 28001e26 beq r5,zero,80465c4 <___svfiprintf_internal_r+0xd74> + 804654c: 21000044 addi r4,r4,1 + 8046550: 10800404 addi r2,r2,16 + 8046554: 41c00015 stw r7,0(r8) + 8046558: 43800115 stw r14,4(r8) + 804655c: d8800b15 stw r2,44(sp) + 8046560: d9000a15 stw r4,40(sp) + 8046564: 21400208 cmpgei r5,r4,8 + 8046568: 283ff426 beq r5,zero,804653c <___svfiprintf_internal_r+0xcec> + 804656c: d9800904 addi r6,sp,36 + 8046570: a00b883a mov r5,r20 + 8046574: b009883a mov r4,r22 + 8046578: d9c00715 stw r7,28(sp) + 804657c: d8c00615 stw r3,24(sp) + 8046580: da400515 stw r9,20(sp) + 8046584: db000215 stw r12,8(sp) + 8046588: db400115 stw r13,4(sp) + 804658c: 80456900 call 8045690 <__ssprint_r> + 8046590: 103d621e bne r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc> + 8046594: d8c00617 ldw r3,24(sp) + 8046598: d8800b17 ldw r2,44(sp) + 804659c: d9000a17 ldw r4,40(sp) + 80465a0: 18fffc04 addi r3,r3,-16 + 80465a4: 19400448 cmpgei r5,r3,17 + 80465a8: 9011883a mov r8,r18 + 80465ac: d9c00717 ldw r7,28(sp) + 80465b0: 03800404 movi r14,16 + 80465b4: da400517 ldw r9,20(sp) + 80465b8: db000217 ldw r12,8(sp) + 80465bc: db400117 ldw r13,4(sp) + 80465c0: 283fe21e bne r5,zero,804654c <___svfiprintf_internal_r+0xcfc> + 80465c4: 21000044 addi r4,r4,1 + 80465c8: 10c5883a add r2,r2,r3 + 80465cc: 40c00115 stw r3,4(r8) + 80465d0: 41c00015 stw r7,0(r8) + 80465d4: d8800b15 stw r2,44(sp) + 80465d8: d9000a15 stw r4,40(sp) + 80465dc: 20c00208 cmpgei r3,r4,8 + 80465e0: 1800751e bne r3,zero,80467b8 <___svfiprintf_internal_r+0xf68> + 80465e4: 42000204 addi r8,r8,8 + 80465e8: 003e1206 br 8045e34 <___svfiprintf_internal_r+0x5e4> + 80465ec: d9800904 addi r6,sp,36 + 80465f0: a00b883a mov r5,r20 + 80465f4: b009883a mov r4,r22 + 80465f8: da400515 stw r9,20(sp) + 80465fc: db000215 stw r12,8(sp) + 8046600: db400115 stw r13,4(sp) + 8046604: 80456900 call 8045690 <__ssprint_r> + 8046608: 103d441e bne r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc> + 804660c: d9000a17 ldw r4,40(sp) + 8046610: d8800b17 ldw r2,44(sp) + 8046614: d8c01804 addi r3,sp,96 + 8046618: 21400044 addi r5,r4,1 + 804661c: 9011883a mov r8,r18 + 8046620: da400517 ldw r9,20(sp) + 8046624: db000217 ldw r12,8(sp) + 8046628: db400117 ldw r13,4(sp) + 804662c: 003e1406 br 8045e80 <___svfiprintf_internal_r+0x630> + 8046630: d9800904 addi r6,sp,36 + 8046634: a00b883a mov r5,r20 + 8046638: b009883a mov r4,r22 + 804663c: da400215 stw r9,8(sp) + 8046640: db000115 stw r12,4(sp) + 8046644: 80456900 call 8045690 <__ssprint_r> + 8046648: 103d341e bne r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc> + 804664c: d9000a17 ldw r4,40(sp) + 8046650: d8800b17 ldw r2,44(sp) + 8046654: d8c01804 addi r3,sp,96 + 8046658: 21400044 addi r5,r4,1 + 804665c: 9011883a mov r8,r18 + 8046660: da400217 ldw r9,8(sp) + 8046664: db000117 ldw r12,4(sp) + 8046668: 003e1306 br 8045eb8 <___svfiprintf_internal_r+0x668> + 804666c: 002b883a mov r21,zero + 8046670: 003d9106 br 8045cb8 <___svfiprintf_internal_r+0x468> + 8046674: d9800904 addi r6,sp,36 + 8046678: a00b883a mov r5,r20 + 804667c: b009883a mov r4,r22 + 8046680: 80456900 call 8045690 <__ssprint_r> + 8046684: 103d251e bne r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc> + 8046688: d9000a17 ldw r4,40(sp) + 804668c: d8800b17 ldw r2,44(sp) + 8046690: d8c01804 addi r3,sp,96 + 8046694: 21400044 addi r5,r4,1 + 8046698: 9011883a mov r8,r18 + 804669c: 003e0a06 br 8045ec8 <___svfiprintf_internal_r+0x678> + 80466a0: e023883a mov r17,fp + 80466a4: 003ca306 br 8045934 <___svfiprintf_internal_r+0xe4> + 80466a8: 902f883a mov r23,r18 + 80466ac: 003dd006 br 8045df0 <___svfiprintf_internal_r+0x5a0> + 80466b0: d9400017 ldw r5,0(sp) + 80466b4: 20800017 ldw r2,0(r4) + 80466b8: d8c00315 stw r3,12(sp) + 80466bc: 2809d7fa srai r4,r5,31 + 80466c0: 11400015 stw r5,0(r2) + 80466c4: 11000115 stw r4,4(r2) + 80466c8: 003c7c06 br 80458bc <___svfiprintf_internal_r+0x6c> + 80466cc: 00c00c04 movi r3,48 + 80466d0: d88008c5 stb r2,35(sp) + 80466d4: d8c00885 stb r3,34(sp) + 80466d8: 63000094 ori r12,r12,2 + 80466dc: 00800084 movi r2,2 + 80466e0: 003db406 br 8045db4 <___svfiprintf_internal_r+0x564> + 80466e4: b809883a mov r4,r23 + 80466e8: da000215 stw r8,8(sp) + 80466ec: db000115 stw r12,4(sp) + 80466f0: 8002dac0 call 8002dac + 80466f4: 102b883a mov r21,r2 + 80466f8: 1027883a mov r19,r2 + 80466fc: dc400315 stw r17,12(sp) + 8046700: db000117 ldw r12,4(sp) + 8046704: da000217 ldw r8,8(sp) + 8046708: 003e8006 br 804610c <___svfiprintf_internal_r+0x8bc> + 804670c: 01401004 movi r5,64 + 8046710: 8007ddc0 call 8007ddc <_malloc_r> + 8046714: a0800015 stw r2,0(r20) + 8046718: a0800415 stw r2,16(r20) + 804671c: 10008f26 beq r2,zero,804695c <___svfiprintf_internal_r+0x110c> + 8046720: 00801004 movi r2,64 + 8046724: a0800515 stw r2,20(r20) + 8046728: 003c5d06 br 80458a0 <___svfiprintf_internal_r+0x50> + 804672c: d8800317 ldw r2,12(sp) + 8046730: 10800017 ldw r2,0(r2) + 8046734: d8c00315 stw r3,12(sp) + 8046738: d8c00017 ldw r3,0(sp) + 804673c: 10c00015 stw r3,0(r2) + 8046740: 003c5e06 br 80458bc <___svfiprintf_internal_r+0x6c> + 8046744: 902f883a mov r23,r18 + 8046748: 00000206 br 8046754 <___svfiprintf_internal_r+0xf04> + 804674c: 1027883a mov r19,r2 + 8046750: 182b883a mov r21,r3 + 8046754: 9809883a mov r4,r19 + 8046758: a80b883a mov r5,r21 + 804675c: 01800284 movi r6,10 + 8046760: 000f883a mov r7,zero + 8046764: db400615 stw r13,24(sp) + 8046768: da000515 stw r8,20(sp) + 804676c: da400215 stw r9,8(sp) + 8046770: db000115 stw r12,4(sp) + 8046774: 800c9c00 call 800c9c0 <__umoddi3> + 8046778: 10800c04 addi r2,r2,48 + 804677c: bdffffc4 addi r23,r23,-1 + 8046780: 9809883a mov r4,r19 + 8046784: a80b883a mov r5,r21 + 8046788: b8800005 stb r2,0(r23) + 804678c: 01800284 movi r6,10 + 8046790: 000f883a mov r7,zero + 8046794: 800c4280 call 800c428 <__udivdi3> + 8046798: db000117 ldw r12,4(sp) + 804679c: da400217 ldw r9,8(sp) + 80467a0: da000517 ldw r8,20(sp) + 80467a4: db400617 ldw r13,24(sp) + 80467a8: a83fe81e bne r21,zero,804674c <___svfiprintf_internal_r+0xefc> + 80467ac: 9cc002a8 cmpgeui r19,r19,10 + 80467b0: 983fe61e bne r19,zero,804674c <___svfiprintf_internal_r+0xefc> + 80467b4: 003f5006 br 80464f8 <___svfiprintf_internal_r+0xca8> + 80467b8: d9800904 addi r6,sp,36 + 80467bc: a00b883a mov r5,r20 + 80467c0: b009883a mov r4,r22 + 80467c4: da400515 stw r9,20(sp) + 80467c8: db000215 stw r12,8(sp) + 80467cc: db400115 stw r13,4(sp) + 80467d0: 80456900 call 8045690 <__ssprint_r> + 80467d4: 103cd11e bne r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc> + 80467d8: d8800b17 ldw r2,44(sp) + 80467dc: d9000a17 ldw r4,40(sp) + 80467e0: 9011883a mov r8,r18 + 80467e4: da400517 ldw r9,20(sp) + 80467e8: db000217 ldw r12,8(sp) + 80467ec: db400117 ldw r13,4(sp) + 80467f0: 003d9006 br 8045e34 <___svfiprintf_internal_r+0x5e4> + 80467f4: 0421c83a sub r16,zero,r16 + 80467f8: ddc00315 stw r23,12(sp) + 80467fc: 003d0106 br 8045c04 <___svfiprintf_internal_r+0x3b4> + 8046800: 10c00060 cmpeqi r3,r2,1 + 8046804: 8819883a mov r12,r17 + 8046808: 183e8826 beq r3,zero,804622c <___svfiprintf_internal_r+0x9dc> + 804680c: 003ebc06 br 8046300 <___svfiprintf_internal_r+0xab0> + 8046810: e0800043 ldbu r2,1(fp) + 8046814: 63000814 ori r12,r12,32 + 8046818: e7000044 addi fp,fp,1 + 804681c: 10803fcc andi r2,r2,255 + 8046820: 1080201c xori r2,r2,128 + 8046824: 10bfe004 addi r2,r2,-128 + 8046828: 003c4a06 br 8045954 <___svfiprintf_internal_r+0x104> + 804682c: d9800904 addi r6,sp,36 + 8046830: a00b883a mov r5,r20 + 8046834: b009883a mov r4,r22 + 8046838: da400115 stw r9,4(sp) + 804683c: 80456900 call 8045690 <__ssprint_r> + 8046840: 103cb61e bne r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc> + 8046844: d9000a17 ldw r4,40(sp) + 8046848: d8800b17 ldw r2,44(sp) + 804684c: d8c01804 addi r3,sp,96 + 8046850: 21400044 addi r5,r4,1 + 8046854: 9011883a mov r8,r18 + 8046858: da400117 ldw r9,4(sp) + 804685c: 003d9806 br 8045ec0 <___svfiprintf_internal_r+0x670> + 8046860: 488001f0 cmpltui r2,r9,7 + 8046864: 482b883a mov r21,r9 + 8046868: 1000011e bne r2,zero,8046870 <___svfiprintf_internal_r+0x1020> + 804686c: 05400184 movi r21,6 + 8046870: 05c20134 movhi r23,2052 + 8046874: a827883a mov r19,r21 + 8046878: dc400315 stw r17,12(sp) + 804687c: bddd2504 addi r23,r23,29844 + 8046880: 003e2206 br 804610c <___svfiprintf_internal_r+0x8bc> + 8046884: d8800315 stw r2,12(sp) + 8046888: 002b883a mov r21,zero + 804688c: 0005883a mov r2,zero + 8046890: 003d4806 br 8045db4 <___svfiprintf_internal_r+0x564> + 8046894: d8800315 stw r2,12(sp) + 8046898: 002b883a mov r21,zero + 804689c: 00800044 movi r2,1 + 80468a0: 003d4406 br 8045db4 <___svfiprintf_internal_r+0x564> + 80468a4: 1809883a mov r4,r3 + 80468a8: 39ee3c44 addi r7,r7,-18191 + 80468ac: 003ef206 br 8046478 <___svfiprintf_internal_r+0xc28> + 80468b0: d9800845 stb r6,33(sp) + 80468b4: 003cb706 br 8045b94 <___svfiprintf_internal_r+0x344> + 80468b8: 4827883a mov r19,r9 + 80468bc: dc400315 stw r17,12(sp) + 80468c0: 482b883a mov r21,r9 + 80468c4: 003e1106 br 804610c <___svfiprintf_internal_r+0x8bc> + 80468c8: d9800845 stb r6,33(sp) + 80468cc: 003cf006 br 8045c90 <___svfiprintf_internal_r+0x440> + 80468d0: d9800845 stb r6,33(sp) + 80468d4: 003e1206 br 8046120 <___svfiprintf_internal_r+0x8d0> + 80468d8: d9800845 stb r6,33(sp) + 80468dc: 003e2206 br 8046168 <___svfiprintf_internal_r+0x918> + 80468e0: d9800845 stb r6,33(sp) + 80468e4: 003e2d06 br 804619c <___svfiprintf_internal_r+0x94c> + 80468e8: d9800845 stb r6,33(sp) + 80468ec: 003e3806 br 80461d0 <___svfiprintf_internal_r+0x980> + 80468f0: d9800845 stb r6,33(sp) + 80468f4: 003de106 br 804607c <___svfiprintf_internal_r+0x82c> + 80468f8: d9800845 stb r6,33(sp) + 80468fc: 003cf606 br 8045cd8 <___svfiprintf_internal_r+0x488> + 8046900: d9800845 stb r6,33(sp) + 8046904: 003dc506 br 804601c <___svfiprintf_internal_r+0x7cc> + 8046908: d9800845 stb r6,33(sp) + 804690c: 003db306 br 8045fdc <___svfiprintf_internal_r+0x78c> + 8046910: 180d883a mov r6,r3 + 8046914: 2809883a mov r4,r5 + 8046918: 39ee3c44 addi r7,r7,-18191 + 804691c: 003ea606 br 80463b8 <___svfiprintf_internal_r+0xb68> + 8046920: 00bfffc4 movi r2,-1 + 8046924: d8800015 stw r2,0(sp) + 8046928: 003c7f06 br 8045b28 <___svfiprintf_internal_r+0x2d8> + 804692c: d8800317 ldw r2,12(sp) + 8046930: 12400017 ldw r9,0(r2) + 8046934: 15c00104 addi r23,r2,4 + 8046938: 4800010e bge r9,zero,8046940 <___svfiprintf_internal_r+0x10f0> + 804693c: 027fffc4 movi r9,-1 + 8046940: e0800043 ldbu r2,1(fp) + 8046944: ddc00315 stw r23,12(sp) + 8046948: 2039883a mov fp,r4 + 804694c: 10803fcc andi r2,r2,255 + 8046950: 1080201c xori r2,r2,128 + 8046954: 10bfe004 addi r2,r2,-128 + 8046958: 003bfe06 br 8045954 <___svfiprintf_internal_r+0x104> + 804695c: 00800304 movi r2,12 + 8046960: b0800015 stw r2,0(r22) + 8046964: 00bfffc4 movi r2,-1 + 8046968: d8800015 stw r2,0(sp) + 804696c: 003c6e06 br 8045b28 <___svfiprintf_internal_r+0x2d8> + +08046970 <_vfprintf_r>: + 8046970: 8002e441 jmpi 8002e44 <___vfprintf_internal_r> + +08046974 <_exit>: + * + * ALT_EXIT is mapped onto the _exit() system call in alt_syscall.h + */ + +void ALT_EXIT (int exit_code) +{ + 8046974: defffd04 addi sp,sp,-12 + 8046978: df000215 stw fp,8(sp) + 804697c: df000204 addi fp,sp,8 + 8046980: e13ffe15 stw r4,-8(fp) + ALT_LOG_PRINT_BOOT("[alt_exit.c] Entering _exit() function.\r\n"); + ALT_LOG_PRINT_BOOT("[alt_exit.c] Exit code from main was %d.\r\n",exit_code); + /* Stop all other threads */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_OS_STOP().\r\n"); + ALT_OS_STOP(); + 8046984: d0204b45 stb zero,-32467(gp) + 8046988: e0bffe17 ldw r2,-8(fp) + 804698c: e0bfff15 stw r2,-4(fp) +/* + * Routine called on exit. + */ +static ALT_INLINE ALT_ALWAYS_INLINE void alt_sim_halt(int exit_code) +{ + register int r2 asm ("r2") = exit_code; + 8046990: e0bfff17 ldw r2,-4(fp) + __asm__ volatile ("\n0:\n\taddi %0,%0, -1\n\tbgt %0,zero,0b" : : "r" (ALT_CPU_FREQ/100) ); /* Delay for >30ms */ + + __asm__ volatile ("break 2" : : "r"(r2), "r"(r3) ALT_GMON_DATA ); + +#else /* !DEBUG_STUB */ + if (r2) { + 8046994: 10000226 beq r2,zero,80469a0 <_exit+0x2c> + ALT_SIM_FAIL(); + 8046998: 002af070 cmpltui zero,zero,43969 + 804699c: 00000106 br 80469a4 <_exit+0x30> + } else { + ALT_SIM_PASS(); + 80469a0: 002af0b0 cmpltui zero,zero,43970 + ALT_SIM_HALT(exit_code); + + /* spin forever, since there's no where to go back to */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Spinning forever.\r\n"); + while (1); + 80469a4: 003fff06 br 80469a4 <_exit+0x30> diff --git a/FPGA_nios/hit_pat/inc/control.h b/FPGA_nios/hit_pat/inc/control.h new file mode 100644 index 0000000..12a69f3 --- /dev/null +++ b/FPGA_nios/hit_pat/inc/control.h @@ -0,0 +1,39 @@ +/* + * control.h + * + * Created on: Aug 14, 2017 + * Author: mdziewiecki + */ + +#ifndef CONTROL_H_ +#define CONTROL_H_ + +//************************** + +#include "dev_commands.h" + +//************************** + +#define CONTROL_TASK_PRIORITY 10 +#define CONTROL_STACK_SIZE (6144+8192) + +#define CONTROL_MAX_DATA_LENGTH 16 //maximum command data length in WORDS (16-bit) +#define CONTROL_TIMEOUT 1000 //timeout to get command data in unknown time units + +#define CONTROL_PORT 4000 +#define DATA_PORT 4001 + +#define CONTROL_SWAP_BYTES 1 //playing around endianness in PC communication + +typedef struct +{ + unsigned short marker; //must be 0x5555 + unsigned short command; + unsigned short length; +} command_header; + + //Initialize control task +void control_init(); + + +#endif /* CONTROL_H_ */ diff --git a/FPGA_nios/hit_pat/inc/dev_commands.h b/FPGA_nios/hit_pat/inc/dev_commands.h new file mode 100644 index 0000000..378fef7 --- /dev/null +++ b/FPGA_nios/hit_pat/inc/dev_commands.h @@ -0,0 +1,136 @@ +#ifndef DEV_COMMANDS_H +#define DEV_COMMANDS_H + +//This file is derived from v.1 version and it's great if it's kept compatible +//All sizes are in HALF-WORDS (16-bit)! + +#define COMMAND_PING 0x0001 + //L: 0 + //D: [] + //Return the same + +#define COMMAND_DEBUG_LED_OFF 0x0010 + //L: 0 + //D: []; + //Turn off LED 0 + +#define COMMAND_DEBUG_LED_ON 0x0011 + //L: 0 + //D: []; + //Turn on LED 0 + +// ***DEVICE CONTROL*** + +#define COMMAND_LEDS_DISABLE 0x0110 + //L: 0 + //D: []; + //Disable LED4 blinking. Other LEDs must be explicitly switched off + +#define COMMAND_LEDS_ENABLE 0x0111 + //L: 0 + //D: []; + //Enable LED4 blinking + +// ***TRIGGER SETTING*** + +#define COMMAND_TRIGGER_DISABLE 0x0210 + //L: 0 + //D: []; + //Disable trigger generation in master mode + +#define COMMAND_TRIGGER_ENABLE 0x0211 + //L: 0 + //D: []; + //Enable trigger generation in master mode + +#define COMMAND_TRIGGER_SET_SLAVE 0x0220 + //L: 0 + //D: []; + //Set trigger to slave mode + +#define COMMAND_TRIGGER_SET_MASTER 0x0221 + //L: 0 + //D: []; + //Set trigger to master mode + +#define COMMAND_TRIGGER_SET_PERIOD 0x0230 + //L: 1 L: 0 + //D: [Period_ticks] D: [] + //Set trigger period for master mode in timer ticks + +#define COMMAND_TRIGGER_SET_TINT 0x0240 + //L: 1 L: 0 + //D: [Tint_ticks] D: [] + //Set integration time in timer ticks + +#define COMMAND_SET_GAIN 0x0250 + //L: 1 L:0 + //D: [gain] D: [] + +#define COMMAND_TRIGGER_SET_MASTER_DELAY 0x0260 + //L: 1 L: 0 + //D: [Tdelay_ticks] D: [] + //Set trigger delay time in timer ticks for master mode. + +#define COMMAND_TRIGGER_SET_SLAVE_DELAY 0x0270 + //L: 1 L: 0 + //D: [Tdelay_ticks] D: [] + //Set trigger delay time in timer ticks for slave mode. + + +// ***DAQ CONTROL*** + +#define COMMAND_DAQ_DISABLE 0x0310 + //L: 0 + //D: []; + //Disable sending data + +#define COMMAND_DAQ_ENABLE 0x0311 + //L: 0 + //D: []; + //Enable sending data + +#define COMMAND_DAQ_RESET_COUNTERS 0x0321 + //L: 0 + //D: [] + //Reset synchronization counters + +#define COMMAND_DAQ_FLUSH_DATA 0x0322 + //L: 0 + //D: [] + //Send all remaining data over data socket + +#define COMMAND_DAQ_CONFIG_PEER 0x0331 + //L: 5 L: 0 + //D: [ip ip ip ip port] D: [] + //Set connection settings (peer IP and port) for data transfer + //Warning: IP is sent as 4 shorts with MSB=0! + +// ***SLOW CONTROL*** + +#define COMMAND_SLOWCTRL_SNAPSHOT 0x0410 + //L: 0 L: 10 + //D:[] D: [(Readout of 5 ADC channels as 32-bit integers)] + //Slow control snapshot - read all channels of ADC + + +// ***DATA TRANSFER - SOCKET 1!!!!*** + +#define COMMAND_DATA_TRANSFER 0x8000 + //(no incoming packet) L: 64*5*2 + 6 + //(no incoming packet) D: [Read out single frame] + + +// *** SET_CLUSTER_THRESHOLD *** // +#define COMMAND_SET_CLUSTER_THRESHOLD 0x4001 + //L: 1 +#define COMMAND_SET_CLUSTER_SIZE 0x4002 + //L: 1 +#define COMMAND_SET_CALIBRATION_FACTOR 0x4003 + //L: 2* 16bit + + + + + +#endif // DEV_COMMANDS_H diff --git a/FPGA_nios/hit_pat/inc/network_utilities.h b/FPGA_nios/hit_pat/inc/network_utilities.h new file mode 100644 index 0000000..635bc05 --- /dev/null +++ b/FPGA_nios/hit_pat/inc/network_utilities.h @@ -0,0 +1,49 @@ +/****************************************************************************** +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. All use of this software and documentation is * +* subject to the License Agreement located at the end of this file below. * +****************************************************************************** +* Date - October 24, 2006 * +* Module - network_utilities.h * +* * +******************************************************************************/ + +#ifndef __NETWORK_UTILITIES_H__ +#define __NETWORK_UTILITIES_H__ + +#include + +error_t get_board_mac_addr(unsigned char mac_addr[6]); + +#endif /*__NETWORK_UTILITIES_H__ */ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ diff --git a/FPGA_nios/hit_pat/inc/sensor.h b/FPGA_nios/hit_pat/inc/sensor.h new file mode 100644 index 0000000..6338921 --- /dev/null +++ b/FPGA_nios/hit_pat/inc/sensor.h @@ -0,0 +1,67 @@ +/* + * sensor.h + * + * Created on: Aug 19, 2019 + * Author: mdziewiecki + */ + +#ifndef SENSOR_H_ +#define SENSOR_H_ + +//SENSOR_INTERFACE_BASE - this is the base address of the interface + + //byte offsets for registers + #define SENSOR_REG_COMMAND 0 //8 bits + #define SENSOR_REG_STATUS 1 //8 bits + #define SENSOR_REG_SENSORCLK 2 //16 bits, 6 used divider for producing sensor clock ('4' MHz) + #define SESNOR_REG_ADCCNV 3 //8 bits, 6 used time of conversion pulse in ADC clocks, should be > 500 ns + #define SENSOR_REG_DELAY 4 //16 bits, 12 used reset signal delay in 50 MHz clocks + #define SENSOR_REG_SHUTTER 6 //16 bits, 12 used sensor reset ('shutter') time in sensor clocks + #define SENSOR_REG_SERSPEED 8 //8 bits synchro baudrate, 50 for 1 Mbps + #define SENSOR_REG_HEADER_ANYDATA 9 //8 bits any data transmitted with SMA state (8 bits SMA + 8 bits anydata) + #define SENSOR_REG_HEADER_CMD 10 //16 bits command field of the command header transmitted in packet + #define SENSOR_REG_CLUSTER_THRESHOLD 12 //8 bits the threshold for cluster locate, range 0~255 + #define SENSOR_REG_CLUSTER_SIZE 13 //8 bits the size for clluster locate, range 0~255 + #define SENSOR_REG_IN_ALGO_THRESHOLD 14 //8 bits the threshold inside Linear Regression, range 0~255 + #define SENSOR_REG_RESERVED 15 //8 bits not used + + //CSR bitmasks + #define SENSOR_CSR_EN_BITMASK 0x01 //enable operation + #define SENSOR_CSR_GAIN_BITMASK 0x02 //gain selection + #define SENSOR_CSR_ADCK_BITMASK 0x04 //ADC clock divider on/off + #define SENSOR_CSR_RESET_BITMASK 0x08 //Reset all logic + + //Status bitmasks + #define SENSOR_STATUS_SEND 0x01 //Sending over Avalon-ST + #define SENSOR_STATUS_TRG_WAITING 0x02 //The trigger came and is being delayed now + #define SENSOR_STATUS_RESET_ACTIVE 0x04 //The RESET signal for the sensor is active now + #define SENSOR_STATUS_ADC_ACTIVE 0x08 //The ADC is converting data (signal high over all 64 channels) or just finished and waits for reset high + #define SESNOR_STATUS_ADC_FINISHED 0x10 //The ADC waits for reset high + #define SESNOR_STATUS_TX_ACTIVE 0x20 //Sync port is sending + #define SESNOR_STATUS_RX_ACTIVE 0x40 //Sync port is receiving + + + //Register access functions/macros +void sensor_command_bit(alt_u32 base, alt_u8 bitmask, alt_u8 state); +#define sensor_command(base, val) IOWR_8DIRECT(base, SENSOR_REG_COMMAND, val) +#define sensor_set_enable(base, val) sensor_command_bit(base, SENSOR_CSR_EN_BITMASK, val); +#define sensor_set_gain(base, val) sensor_command_bit(base, SENSOR_CSR_GAIN_BITMASK, val); +#define sensor_set_adck(base, val) sensor_command_bit(base, SENSOR_CSR_ADCK_BITMASK, val); +#define sensor_reset(base) { sensor_command_bit(base,SENSOR_CSR_RESET_BITMASK,1); sensor_command_bit(base,SENSOR_CSR_RESET_BITMASK,0); } +#define sensor_set_sensorclk(base, val) IOWR_8DIRECT(base, SENSOR_REG_SENSORCLK, val) +#define sensor_set_adccnv(base, val) IOWR_8DIRECT(base, SESNOR_REG_ADCCNV, val) +#define sensor_set_delay(base, val) IOWR_16DIRECT(base, SENSOR_REG_DELAY, val) +#define sensor_set_shutter(base, val) IOWR_16DIRECT(base, SENSOR_REG_SHUTTER, val) +#define sensor_set_serspeed(base, val) IOWR_8DIRECT(base, SENSOR_REG_SERSPEED, val) +#define sensor_set_header_anydata(base, val) IOWR_8DIRECT(base, SENSOR_REG_HEADER_ANYDATA, val) +#define sensor_set_header_cmd(base, val) IOWR_16DIRECT(base, SENSOR_REG_HEADER_CMD, val) +#define sensor_set_cluster_threshold(base, val) IOWR_8DIRECT(base, SENSOR_REG_CLUSTER_THRESHOLD, val) +#define sensor_set_cluster_size(base, val) IOWR_8DIRECT(base, SENSOR_REG_CLUSTER_SIZE, val) +#define sensor_set_in_algo_threshold(base, val) IOWR_8DIRECT(base, SENSOR_REG_IN_ALGO_THRESHOLD, val) + +//write calibration factor: CALIBRATION_RAM_BASE +#define calibration_ram_set_factor(base, channelID, val) IOWR_16DIRECT(base, channelID*2, val) + +void sensor_preconfigure(alt_u32 base); + +#endif /* SENSOR_H_ */ diff --git a/FPGA_nios/hit_pat/inc/socket_server.h b/FPGA_nios/hit_pat/inc/socket_server.h new file mode 100644 index 0000000..5a9c8ed --- /dev/null +++ b/FPGA_nios/hit_pat/inc/socket_server.h @@ -0,0 +1,144 @@ +/****************************************************************************** +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. All use of this software and documentation is * +* subject to the License Agreement located at the end of this file below. * +******************************************************************************* * +* Date - October 24, 2006 * +* Module - simple_socket_server.h * +* EXTENSIVELY REWRITTEN by M.D. 2019 * * +******************************************************************************/ + +/* + SO THIS IS HOW IT WORKS: + + User can use up to NR_CHANNELS sockets. + First, ethernet_init() must be called from any task. + It will start a special 'listener' thread which is responsible for serving connection requests. + Then: + For each 'channel' (a placeholder for one socket), user may call ethernet_listen() to start listening on a specified port. + After that, ethernet_read() and ethernet_write() can be used. These functions are non-blocking and return 0 if no client is connected. + User can explicitly close connection to a client by calling ethernet_close(); + If another connection request comes when a client is already connected, the old client will be disconnected in favor of the new one. + It means, that only one client can be connected to one channel at a given time. + This weird behaviour is implemented to enable easy killing 'hanging' connections. + Channel re-configuration (i.e. repeated calls of ethernet_listen() for the same channel) is not allowed. + VERY IMPORTANT: + All the above functions (excluding ethernet_init()) must be called from a socket-compatible thread (created with TK_NEWTASK). + All ethernet_* calls are served directly in user's task. Ethernet_init() can be called from any thread after hardware configuration. + */ + + /* Validate supported Software components specified on system library properties page. + */ +#ifndef __SOCKET_SERVER_H__ +#define __SOCKET_SERVER_H__ + +#if !defined (ALT_INICHE) + #error The Simple Socket Server example requires the + #error NicheStack TCP/IP Stack Software Component. Please see the Nichestack + #error Tutorial for details on Nichestack TCP/IP Stack - Nios II Edition, + #error including notes on migrating applications from lwIP to NicheStack. +#endif + +#ifndef __ucosii__ + #error This Simple Socket Server example requires + #error the MicroC/OS-II Intellectual Property Software Component. +#endif + +#if defined (ALT_LWIP) + #error The Simple Socket Server example requires the + #error NicheStack TCP/IP Stack Software Component, and no longer works + #error with the lwIP networking stack. Please see the Altera Nichstack + #error Tutorial for details on Nichestack TCP/IP Stack - Nios II Edition, + #error including notes on migrating applications from lwIP to NicheStack. +#endif + + + + +/* + * Task Priorities: + * MicroC/OS-II only allows one task (thread) per priority number. + */ +#define SS_LISTENER_TASK_PRIORITY 9 //Also, another priority just below this one will be reserved for mutex +#define SS_LISTENER_STACK_SIZE (6144+8192) + +#define NR_CHANNELS 1 //number of listening sockets - as in Wiznet + //Each socket listens on its own port and is able to open one "talking" connection at a time + //If a new connection request comes, the old one gets preempted. This allows us killing dead connections. + + +/* + * If DHCP will not be used, select valid static _BASE_ IP addresses here: + * The contents of DIPSW[3:0] will be added to the last byte of the IP. + * DIPSW[4] is used to enable/disable DHCP. + */ +#define IPADDR0 10 +#define IPADDR1 0 +#define IPADDR2 7 +#define IPADDR3 16 + +#define GWADDR0 10 +#define GWADDR1 0 +#define GWADDR2 7 +#define GWADDR3 1 + +#define MSKADDR0 255 +#define MSKADDR1 255 +#define MSKADDR2 255 +#define MSKADDR3 0 + + +/* + * Here we structure to manage sss communication for a single connection + */ +typedef struct SS_SOCKET +{ + enum { FREE, LISTENING, CONNECTED} state; + int fd_listen; + int fd_conn; + int listenport; +} SSConn; + +// *** User's interface *** + +int ethernet_init(); +/*REMARK: All the below functions can be used ONLY: + 1: After ethernet_init(); + 2: From a task created by TK_NEWTASK. */ +int ethernet_listen(int channel, int port); //Remark: Once we listen on a port, we can not change it +int ethernet_write(int channel, int size, unsigned char* data); +int ethernet_read(int channel, int size, unsigned char* data); //Non-blocking. Returns the number of characters read. +int ethernet_close(int channel); + +#endif /* __SOCKET_SERVER_H__ */ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ diff --git a/FPGA_nios/hit_pat/inc/udpgen.h b/FPGA_nios/hit_pat/inc/udpgen.h new file mode 100644 index 0000000..bd69f56 --- /dev/null +++ b/FPGA_nios/hit_pat/inc/udpgen.h @@ -0,0 +1,54 @@ +/* + * udpgen.h + * + * Created on: Aug 7, 2019 + * Author: mdziewiecki + */ + +#ifndef UDPGEN_H_ +#define UDPGEN_H_ + +//UDP_GENERATOR_0_BASE + + //byte offsets for registers +#define UDPGEN_REG_CSR 0 //16 bits 8 bits command + 8 bits status +#define UDPGEN_REG_SIZE 2 //16 bits payload size in words +#define UDPGEN_REG_SRCIP 4 //32 bits source IP, last octet first +#define UDPGEN_REG_DSTIP 8 //32 bits destination IP. last octet first +#define UDPGEN_REG_DSTPORT 12 //16 bits destination port +#define UDPGEN_REG_SRCPORT 14 //16 bits source port +#define UDPGEN_REG_DSTMAC 16 //2*32 bits destination MAC, last octet first +#define UDPGEN_REG_RES1 24 //32 bits reserved +#define UDPGEN_REG_RES2 28 //32 bits reserved + + //csr bitmasks +#define UDPGEN_CSR_EN_BITMASK 0x0001 + + + //Register access macros +void udpgen_command_bit(alt_u32 base, alt_u8 bitmask, alt_u8 state); +#define udpgen_command(base, val) IOWR_8DIRECT(base, UDPGEN_REG_CSR, val) +#define udpgen_set_size(base, val) IOWR_16DIRECT(base, UDPGEN_REG_SIZE, val) +#define udpgen_set_srcip(base, val) IOWR_32DIRECT(base, UDPGEN_REG_SRCIP, val) +#define udpgen_set_dstip(base, val) IOWR_32DIRECT(base, UDPGEN_REG_DSTIP, val) +#define udpgen_set_srcip_a(base, val) { for(int i = 0; i < 4; i++) IOWR_8DIRECT(base, UDPGEN_REG_SRCIP+i, val[3-i]); } +#define udpgen_set_dstip_a(base, val) { for(int i = 0; i < 4; i++) IOWR_8DIRECT(base, UDPGEN_REG_DSTIP+i, val[3-i]); } +#define udpgen_set_srcport(base, val) IOWR_16DIRECT(base, UDPGEN_REG_SRCPORT, val) +#define udpgen_set_dstport(base, val) IOWR_16DIRECT(base, UDPGEN_REG_DSTPORT, val) +#define udpgen_set_dstmac_a(base, val) { for(int i = 0; i < 6; i++) IOWR_8DIRECT(base, UDPGEN_REG_DSTMAC+i, val[5-i]); } + +#define udpgen_status(base) IORD_16DIRECT(base, UDPGEN_REG_CSR) +#define udpgen_get_size(base, val) IORD_16DIRECT(base, UDPGEN_REG_SIZE) +#define udpgen_get_srcip(base, val) IORD_32DIRECT(base, UDPGEN_REG_SRCIP) +#define udpgen_get_dstip(base, val) IORD_32DIRECT(base, UDPGEN_REG_DSTIP) +#define udpgen_get_srcport(base, val) IORD_16DIRECT(base, UDPGEN_REG_SRCPORT) +#define udpgen_get_dstport(base, val) IORD_16DIRECT(base, UDPGEN_REG_DSTPORT) +#define udpgen_get_dstmac(base, val) { for(int i = 0; i < 6; i++) val[i] = IORD_8DIRECT(base, UDPGEN_REG_DSTMAC+i); } + + +//****************************************************** + +void udpgen_test(alt_u32 base); + + +#endif /* UDPGEN_H_ */ diff --git a/FPGA_nios/hit_pat/inc/utils.h b/FPGA_nios/hit_pat/inc/utils.h new file mode 100644 index 0000000..eafe646 --- /dev/null +++ b/FPGA_nios/hit_pat/inc/utils.h @@ -0,0 +1,34 @@ +/* + * utils.h + * + * Created on: Jul 31, 2019 + * Author: mdziewiecki + * Various utils for various purposes + * Mainly wrappers on hardware + */ + + + +#ifndef UTILS_H_ +#define UTILS_H_ + +//Swap opdd/even bytes in a bunch of data to align endianness of shorts +void swap_bytes(unsigned char* array, int size_bytes); +void swap_quad(unsigned char* array, int size_bytes); + +void reload_fpga(); //trigger FPGA reload + +#define TRIGGER_MASTER 1 +#define TRIGGER_SLAVE 0 +void masterslave(alt_u8 master); //set trigger system to master or slave operation +void master_clock_period(alt_u32 period); //set period of the master frame timer +void master_clock_enable(alt_u8 en); //enable/disable pulse generation + +void led_set(alt_u8 led_nr); +void led_clear(alt_u8 led_nr); +void led_toggle(alt_u8 led_nr); +void led4_blink_enable(alt_u8 en); + +void set_delay(alt_u8 master, alt_u16 value); + +#endif /* UTILS_H_ */ diff --git a/FPGA_nios/hit_pat/mem_init/hdl_sim/onchip_flash.dat b/FPGA_nios/hit_pat/mem_init/hdl_sim/onchip_flash.dat new file mode 100644 index 0000000..e69de29 diff --git a/FPGA_nios/hit_pat/mem_init/hdl_sim/onchip_flash.sym b/FPGA_nios/hit_pat/mem_init/hdl_sim/onchip_flash.sym new file mode 100644 index 0000000..d508ca2 --- /dev/null +++ b/FPGA_nios/hit_pat/mem_init/hdl_sim/onchip_flash.sym @@ -0,0 +1,1138 @@ +00000000 a OSTCBStkPtr_OFFSET +00000014 a OSTCBNext_OFFSET +00000032 a OSTCBPrio_OFFSET +00000040 a OSCtxSw_SWITCH_PC +08000000 A __alt_mem_ddr3_ram +08000120 T alt_exception +08000120 T alt_irq_entry +080001fc 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___svfiprintf_internal_r +08046970 T _vfprintf_r +08046974 T _exit +080469a8 A __CTOR_END__ +080469a8 A __CTOR_LIST__ +080469a8 A __DTOR_END__ +080469a8 A __DTOR_LIST__ +080471d6 R _ctype_ +080472d7 R _ctype_b +0804749e r zeroes.5227 +080474ae r blanks.5226 +080474d0 r p05.4024 +080474dc R __mprec_tinytens +08047504 R __mprec_bigtens +0804752c R __mprec_tens +080475f4 r zeroes.5204 +08047604 r blanks.5203 +08047624 R __clz_tab +08047734 R OSUnMapTbl +0804b8d1 r zeroes.5208 +0804b8e1 r blanks.5207 +0804b8f1 r zeroes.5188 +0804b901 r blanks.5187 +0804b920 G controltask +0804b938 G sslistenertask +0804b950 G tse_mac_device +0804ba80 g impure_data +0804bea4 G __malloc_av_ +0804c2ac G __global_locale +0804c420 g debug_uart +0804c4f0 g ext_flash +0804c5d0 g msgdma_rx +0804c640 g msgdma_tx +0804c6b0 g onchip_flash +0804c7b0 G nettasks +0804c7e0 G tcp_protosw +0804c7f8 G udp_protosw +0804c810 G rawip_protosw +0804c828 G tcp_outflags +0804c833 G tcp_backoff +0804c840 G alt_dev_null +0804c868 G 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to_nettick +0804cc7c B tcp_sleep_timeout +0804cc80 B cticks_initialized +0804cc84 B irq_level +0804cc88 b cpu_statusreg +0804cc8c b kbd_init.4507 +0804cc90 B cticks_factor +0804cc94 B OS_TPS +0804cc98 B tcp_sleep_count +0804cc9c B tcp_wakeup_count +0804cca0 B netq_intmask +0804cca4 B old_mode +0804cca8 B global_TCPwakeup_setIndx +0804ccac B cticks +0804ccb0 B memtrapsize +0804ccb4 B mheap_sem_ptr +0804ccb8 B rcvdq_sem_ptr +0804ccbc B nextslow +0804ccc0 b in_tcptick +0804ccc4 B mbstat +0804cccc B select_wait +0804ccd0 B tcpprintfs +0804ccd4 B dropline +0804ccd8 B tcp_optionbuf +0804ccdc B tcp_maxidle +0804cce0 B tcp_iss +0804cce4 B alt_fd_list_lock +0804cce8 B alt_irq_active +0804ccec B _alt_tick_rate +0804ccf0 B _alt_nticks +0804ccf4 B activehost +0804ccf8 b inside_pktdemux +0804ccfc B nextppp +0804cd00 B port_1s_callout +0804cd04 b numtimers +0804cd08 B icmpdu_hook +0804cd0c B rt_mib +0804cd10 B port_prep +0804cd14 B net_system_exit +0804cd18 B so_evtmap_create +0804cd1c B so_evtmap_delete +0804cd20 B so_evtmap +0804cd24 B ipraw_eps +0804cd28 B cachedRoute +0804cd2c b usocket +0804cd30 B firstudp +0804cd34 B inpcb_cachehits +0804cd38 B inpcb_cachemiss +0804cd3c B vfsystems +0804cd40 B vfiles +0804cd44 B vfsfiles +0804cd48 B vfopen_error +0804cd4c B vfs_dir_stale +0804cd50 B vfs_open_files +0804cd54 B vfs_total_rw_space +0804cd58 B vfs_total_dyna_files +0804cd5c B alt_instruction_exception_handler +0804cd60 b packet_data.5855 +0804cd80 b connections +0804cd90 B __malloc_current_mallinfo +0804cdb8 b closers +0804cdf4 b tistring +0804ce0c b nearBuf.4931 +0804ce2c B InitialTaskStk +08054ab8 A _gp +0805ae2c B OSFlagTbl +0805b19c B OSMemTbl +0805bdcc B OSQTbl +0805bfac B OSTaskIdleStk +0805c7ac B OSEventTbl +0805d2ec B OSTCBTbl +0805d574 B OSTCBPrioTbl +0805d5c8 B eth_tse_if +0805d6a8 B pmac_groups +0805d6b8 B pphy_profiles +0805d6d8 B tse_iniche_dev_driver_data +0805d708 B tse +0805d998 B arp_table +0805da98 B netlist +0805daac B rcvdq +0805dac0 B netstatic +0805ddc0 B nets +0805ddd0 B igmpstats +0805de34 B eth_prt_buf +0805de46 B ipreturn +0805de58 B lilfreeq +0805de6c B memestats +0805de7c B pktlog +0805df6c B bigfreeq +0805df80 B global_tcb_ext +0805e07c B global_TCPwakeup_set +0805e16c B resid_semaphore +0805e1ac B app_semaphore +0805e1c4 B soq +0805e1d8 B tcpmib +0805e214 B mbufq +0805e228 B mfreeq +0805e23c B tcp_saveti +0805e264 B tcb +0805e290 B tcpstat +0805e370 B alt_irq +0805e470 B intimers +0805e4d4 B icmp_mib +0805e53c B ip_mib +0805e58c B udp_mib +0805e59c A __alt_heap_start +0805e59c A __alt_stack_base +0805e59c A __bss_end +0805e59c A _end +0805e59c A end +10000000 A __alt_data_end +10000000 A __alt_heap_limit +10000000 A __alt_stack_pointer +14000000 A __alt_mem_ext_flash_avl_mem +14000000 T __reset +18200000 A __alt_mem_onchip_flash_data +18400000 A __alt_mem_descriptor_memory +18403400 A __alt_mem_calibration_ram diff --git a/FPGA_nios/hit_pat/mem_init/meminit.qip b/FPGA_nios/hit_pat/mem_init/meminit.qip new file mode 100644 index 0000000..7589c13 --- /dev/null +++ b/FPGA_nios/hit_pat/mem_init/meminit.qip @@ -0,0 +1 @@ +set_global_assignment -name SEARCH_PATH $::quartus(qip_path) diff --git a/FPGA_nios/hit_pat/mem_init/meminit.spd b/FPGA_nios/hit_pat/mem_init/meminit.spd new file mode 100644 index 0000000..b546ac5 --- /dev/null +++ b/FPGA_nios/hit_pat/mem_init/meminit.spd @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/FPGA_nios/hit_pat/onchip_flash.flash b/FPGA_nios/hit_pat/onchip_flash.flash new file mode 100644 index 0000000..974c5a9 --- /dev/null +++ b/FPGA_nios/hit_pat/onchip_flash.flash @@ -0,0 +1,2 @@ +S00600002D454C3B +S70500000000FA \ No newline at end of file diff --git a/FPGA_nios/hit_pat/readme.txt b/FPGA_nios/hit_pat/readme.txt new file mode 100644 index 0000000..953ca77 --- /dev/null +++ b/FPGA_nios/hit_pat/readme.txt @@ -0,0 +1,101 @@ +Readme - Simple Socket Server Software Example + +DESCRIPTION: +A Simple Socket Server that controls development board LEDs. + +This software application may be targeted for TSE design having RGMII interface +media between Ethernet MAC and Ethernet Phy. + +RGMII (Reduced Gigabit Media Independent Interface) is intended to be an +alternative to GMII. The principle objective of RGMII is to reduce the number +of pins from 22 (GMII) down to 12 in a cost-effective manner. RGMII interface +require a 1.5 to 2ns delay (90 degree phase shift) on the transmitted clock +over the data bus. This timing requirement can be achieved through a PCB trace +delay, or optionally of introducing the delay on-chip at the physical layer +transceiver chip. This example software include a configuration file to enable +the on-chip delay method. + +Requirements: + -RTOS Type - MicroC/OS-II + -Software Component - NicheStack TCP/IP Stack - Nios II Edition + -Period System Timer - SYS_CLK_TIMER + +PERIPHERALS USED: +This example exercises the following peripherals: +- Ethernet MAC +- PIO, 8-bit output (named "led_pio" in SOPC Builder) +- PIO, 16-bit output (named "seven_seg_pio" in SOPC Builder) (optional) +- STDOUT device (UART or JTAG UART) + +SOFTWARE SOURCE FILES: +This example includes the following software source files: + +- iniche_init.c: Contains main() and SSSInitialTask() to initialize NicheStack +and then create the other tasks once network has been properly initialized. +Tasks which will use sockets, such as the SSSSimpleSocketServerTask() in this +example, must be created with TK_NEWTASK. All other tasks can be created by directly +calling the MicroC/OS-II API to create a task, i.e. OSTaskCreateExt(). + +- simple_socket_server.c: Implementation of a simple_socket_server including all necessary sockets +calls to handle a single socket connection & process received commands. + +- network_utilities.c: Contains MAC address and IP address routines to +manage addressing. These are used by NicheStack during initialization, but are +implementation-specific (you set your MAC address to whatever you want.. or read +it from your own special non-volatile memory. + +- network_utilities.h: Contains prototype for function get_board_mac_addr(). + +- led.c: Contains tasks to manage board LED commands and update LED displays. +LEDManagementTask interprets commands, and toggles the row of 8 LEDS or signals the +LED7SegLightshowTask in response to commands received from the host running telnet. +The LEDManagementTask reads data from a MicroC/OS-II SSSLEDCommandQ Queue which +receives its data from the SSSSimpleSocketServerTask. LED7SegLightshowTask controls the +7-segment display. + +- simple_socket_server.h: Definitions for the entire example application. + +- alt_error_handler.h: Definitions for 3 error handlers, one each for MicroC-OS/II, Network, +and Simple Socket Server Application. + +- alt_error_handler.c: Implementation for 3 error handlers, one each for MicroC-OS/II, +Network, and Simple Socket Server Application. + +- tse_my_system.c: Allow customization of tse_mac_device[] structure through global array initialization. +If using marvell phy, this can be set to RGMII mode in this file. Other Phys will operate in one mode or +the other depending on thier implementation in driver file altera_avalon_tse.c. + +BOARD/HOST REQUIREMENTS: +Must contain a supported phy, and use a quartus project that uses tse and msgdma. + +This example requires an Ethernet cable connected to the development board's +RJ-45 jack, and a JTAG connection with the development board. If the host +communication settings are changed from JTAG UART (default) to use a +conventional UART, a serial cable between board DB-9 connector and the host is +required. + +If DHCP is available (and enabled in the Software component configuration page, from +the BSP properties configuration), NicheStack TCP/IP Stack will attempt +to obtain an IP address from a DHCP server. Otherwise, a static IP address (defined in +Simple_Socket_Server.h) will be assigned after a DHCP timeout. + +ADDITIONAL INFORMATION: + +This is an example socket server using NicheStack TCP/IP Stack on MicroC/OS-II. The server +implements simple commands to control board LEDs through a separate MicroC/OS-II +task. It is in no way a complete implementation of a telnet server. + +A good introduction to sockets programming is the book "Unix Network Programming" by +Richard Stevens. Additionally, the text "Sockets in C", by Donahoo & Calvert, is a concise +& inexpensive text for getting started with sockets programming. + +This example will not run on the Instruction Set Simulator (ISS). + +Once the simple socket server example is running and has obtained an IP address (shown +in the terminal window of Nios II Software Build Tools for Eclipse), +you can connect to it over a network by typing the +following command in a command shell on a development host: + + telnet 30 + +This command will try to connect to the Simple Socket Server using port 30. diff --git a/FPGA_nios/hit_pat/src/control.c b/FPGA_nios/hit_pat/src/control.c new file mode 100644 index 0000000..4611a64 --- /dev/null +++ b/FPGA_nios/hit_pat/src/control.c @@ -0,0 +1,390 @@ +/* + * control.c + * + * Created on: Aug 14, 2017 + * Author: mdziewiecki + */ + + +#include +#include +#include + +/* MicroC/OS-II definitions */ +#include "includes.h" + +#include +#include + +/* Nichestack definitions */ +#include "ipport.h" +#include "tcpport.h" +#include "libport.h" +#include "osport.h" + +#include "socket_server.h" +#include "control.h" +#include "sensor.h" +#include "udpgen.h" +#include "utils.h" + +// **************************** + +extern NET nets[MAXNETS]; /* pointers to the static network structs */ + +// **************************** + +void control_delay() +{ + TK_SLEEP(1); +} + + +// **************************** + + //simple reply +void control_pong(command_header* header) +{ + command_header tmp; + tmp = *header; + swap_bytes((char*)(void*)(&tmp), sizeof(tmp)); + ethernet_write(0, sizeof(command_header), (unsigned char*)(header)); +} + +void control_process_snapshot() +{ + command_header header = {.marker = 0x5555, .command = COMMAND_SLOWCTRL_SNAPSHOT, + .length = 0}; //SLOWCTRL_ADC_CHANNEL_COUNT * sizeof(SLOWCTRL_ADC_DATA_TYPE) / sizeof(unsigned short)}; + swap_bytes((char*)(void*)(&header), sizeof(header)); + ethernet_write(0, sizeof(command_header), (unsigned char*)(&header)); + //ethernet_write(0, SLOWCTRL_ADC_CHANNEL_COUNT*sizeof(SLOWCTRL_ADC_DATA_TYPE), (unsigned char*)slowctrl_adc_buffer); +} + + //helper for the one below +int check_arp(struct arptabent * arp_entry, ip_addr ip) +{ + if (arp_entry->t_pro_addr != ip) + return 0; //bad IP + + for (int i = 0; i < 6; i++) + if (arp_entry->t_phy_addr[i] != 0) + return 1; //non-zero MAC + + return 0; +} + +void control_process_config_peer(unsigned short* data) +{ + ip_addr ip = 0; + ip_addr srcip = 0; + int i; + command_header header = {.marker = 0x5555, .command = COMMAND_DAQ_CONFIG_PEER, .length = 0}; + + for (i = 0; i < 4; i++) + ip = (ip << 8) | (unsigned char)(data[3-i] & 0x00FF); + + //daq_configure_peer_addr(ip, data[4]); + + printf("Querying ARP for %d.%d.%d.%d ...\n",data[0],data[1],data[2],data[3]); + + struct arptabent * arp_entry = find_oldest_arp(ip); + + int pingseq = 0; + while (!check_arp(arp_entry, ip)) //big loop for pinging 10 times + { + printf("ARP entry could not be found, pinging!\n"); + //ping the peer to ARP it. + icmpEcho(ip, NULL, 8, pingseq++); + + for (int i = 0; (i < 5) && (!check_arp(arp_entry, ip)); i++) //small loop for waiting 5 times after each ping + { + TK_SLEEP(10); + arp_entry = find_oldest_arp(ip); + } + + if (pingseq > 10) + { + printf("Could not resolve MAC! The result below is random!\n"); + break; + } + } + + printf("Peer MAC is %02x %02x %02x %02x %02x %02x\n", + arp_entry->t_phy_addr[0], arp_entry->t_phy_addr[1], arp_entry->t_phy_addr[2], + arp_entry->t_phy_addr[3], arp_entry->t_phy_addr[4], arp_entry->t_phy_addr[5]); + + srcip = nets[0]->n_ipaddr; + swap_quad((unsigned char*)(void*)(&srcip), 4); //UDP generator needs such a format + swap_quad((unsigned char*)(void*)(&ip), 4); + + //set up udpgen with correct values + udpgen_set_size(UDP_GENERATOR_BASE, 167); //sensor_interface.v:39 + udpgen_set_srcip(UDP_GENERATOR_BASE, srcip); + udpgen_set_dstip(UDP_GENERATOR_BASE, ip); + udpgen_set_srcport(UDP_GENERATOR_BASE, DATA_PORT); + udpgen_set_dstport(UDP_GENERATOR_BASE, data[4]); + udpgen_set_dstmac_a(UDP_GENERATOR_BASE, arp_entry->t_phy_addr); + + swap_bytes((unsigned char*)(void*)(&header), sizeof(header)); + ethernet_write(0, sizeof(command_header), (unsigned char*)(&header)); +} + + + +// **************************** + + //Receive command header. Return (without loosing data!) if number of received bytes is insufficient. +unsigned char control_get_header(command_header** result) +{ + static command_header header; + static unsigned int bytes_received = 0; + + bytes_received += ethernet_read(0, sizeof(command_header)-bytes_received, (unsigned char*)(&header) + bytes_received); + + if (bytes_received < sizeof(command_header)) + return 0; + + swap_bytes((unsigned char*)(void*)(&header),sizeof(header)); //if the header is complete, swap bytes and return it + *result = &header; + bytes_received = 0; + return 1; +} + + //Receive command data. Return (without loosing data!) if number of received bytes is insufficient. + //Expected data length is given in words! +unsigned char control_get_data(unsigned short expected_length, unsigned short** data) +{ + static unsigned short packet_data[CONTROL_MAX_DATA_LENGTH]; + static unsigned int bytes_received = 0; + + bytes_received += ethernet_read(0, 2*expected_length - bytes_received, (unsigned char*)(&packet_data) + bytes_received); + + if (bytes_received < (2*expected_length)) + return 0; + + *data = packet_data; + bytes_received = 0; + return 1; +} + +// **************************** + +void control_step() +{ + command_header* header; + unsigned short* data; + unsigned int loop_ctr = 0; + + + //get header - at this moment this is blocking! + while (!control_get_header(&header)) + { + control_delay(); + + if (++loop_ctr > CONTROL_TIMEOUT) + { + return; + } + } + + //check start marker + if (header->marker != 0x5555) + return; + + + //get packet data - at this moment this is blocking! + while (!control_get_data(header->length, &data)) + { + control_delay(); + + if (++loop_ctr > CONTROL_TIMEOUT) + { + return; + } + } + //swap data bytes + swap_bytes((unsigned char*)(void*)data, header->length*2); + + switch(header->command) + { + case COMMAND_PING: + printf("COMMAND_PING\n"); + control_pong(header); + break; + case COMMAND_DEBUG_LED_OFF: + printf("COMMAND_DEBUG_LED_OFF\n"); + led_clear(0); + control_pong(header); + break; + case COMMAND_DEBUG_LED_ON: + printf("COMMAND_DEBUG_LED_ON\n"); + led_set(0); + control_pong(header); + break; + + case COMMAND_LEDS_DISABLE: + printf("COMMAND_LEDS_DISABLE\n"); + led4_blink_enable(0); + control_pong(header); + break; + case COMMAND_LEDS_ENABLE: + printf("COMMAND_LEDS_ENABLE\n"); + led4_blink_enable(1); + control_pong(header); + break; + + case COMMAND_TRIGGER_DISABLE: + printf("COMMAND_TRIGGER_DISABLE\n"); + master_clock_enable(0); + control_pong(header); + break; + case COMMAND_TRIGGER_ENABLE: + printf("COMMAND_TRIGGER_ENABLE\n"); + master_clock_enable(1); + control_pong(header); + break; + case COMMAND_TRIGGER_SET_SLAVE: + printf("COMMAND_TRIGGER_SET_SLAVE\n"); + masterslave(TRIGGER_SLAVE); + control_pong(header); + break; + case COMMAND_TRIGGER_SET_MASTER: + printf("COMMAND_TRIGGER_SET_MASTER\n"); + masterslave(TRIGGER_MASTER); + control_pong(header); + break; + case COMMAND_TRIGGER_SET_PERIOD: + printf("COMMAND_TRIGGER_SET_PERIOD: %d\n", data[0]); + master_clock_period((alt_u32)data[0]); //we set only 16 lsbs! + header->length = 0; + control_pong(header); + break; + case COMMAND_TRIGGER_SET_TINT: + printf("COMMAND_TRIGGER_SET_TINT: %d\n", data[0]); + sensor_set_shutter(SENSOR_INTERFACE_BASE, data[0]); + header->length = 0; + control_pong(header); + break; + case COMMAND_SET_GAIN: + printf("COMMAND_SET_GAIN: %d\n", data[0]); + sensor_set_gain(SENSOR_INTERFACE_BASE, data[0]); + header->length = 0; + control_pong(header); + break; + case COMMAND_TRIGGER_SET_MASTER_DELAY: + printf("COMMAND_TRIGGER_SET_MASTER_DELAY: %d\n", data[0]); + set_delay(TRIGGER_MASTER, data[0]); + header->length = 0; + control_pong(header); + break; + case COMMAND_TRIGGER_SET_SLAVE_DELAY: + printf("COMMAND_TRIGGER_SET_SLAVE_DELAY: %d\n", data[0]); + set_delay(TRIGGER_SLAVE, data[0]); + header->length = 0; + control_pong(header); + break; + + case COMMAND_DAQ_DISABLE: + printf("COMMAND_DAQ_DISABLE\n"); + sensor_set_enable(SENSOR_INTERFACE_BASE, 0); + udpgen_command_bit(UDP_GENERATOR_BASE, UDPGEN_CSR_EN_BITMASK,0); + control_pong(header); + break; + case COMMAND_DAQ_ENABLE: + printf("COMMAND_DAQ_ENABLE\n"); + udpgen_command_bit(UDP_GENERATOR_BASE, UDPGEN_CSR_EN_BITMASK,1); + sensor_set_enable(SENSOR_INTERFACE_BASE, 1); + control_pong(header); + break; + case COMMAND_DAQ_RESET_COUNTERS: + printf("COMMAND_DAQ_RESET_COUNTERS\n"); + sensor_reset(SENSOR_INTERFACE_BASE); + control_pong(header); + break; + case COMMAND_DAQ_FLUSH_DATA: + printf("COMMAND_DAQ_FLUSH_DATA\n"); + //nothing + control_pong(header); + break; + case COMMAND_DAQ_CONFIG_PEER: + printf("COMMAND_DAQ_CONFIG_PEER\n"); + control_process_config_peer(data); + break; + + case COMMAND_SLOWCTRL_SNAPSHOT: + printf("COMMAND_SLOWCTRL_SNAPSHOT\n"); + control_process_snapshot(); + break; + + case COMMAND_SET_CLUSTER_THRESHOLD: + printf("COMMAND_SET_CLUSTER_THRESHOLD: %d\n", data[0]); + sensor_set_cluster_threshold(SENSOR_INTERFACE_BASE,data[0]); + header->length = 0; + control_pong(header); + break; + + case COMMAND_SET_CLUSTER_SIZE: + printf("COMMAND_SET_CLUSTER_SIZE: %d\n", data[0]); + sensor_set_cluster_size(SENSOR_INTERFACE_BASE,data[0]); + header->length = 0; + control_pong(header); + break; + + case COMMAND_SET_CALIBRATION_FACTOR: //data[i] is 16 bit unsigned short; calibration factor is 16 bit + if (header->length>=2){ + calibration_ram_set_factor(CALIBRATION_RAM_BASE,data[0],data[1]); //i is channelID + printf("COMMAND_SET_CALIBRATION_FACTOR ChannelIP%d : %d\n", data[0],data[1]); + }else{ + printf("COMMAND_SET_CALIBRATION_FACTOR length: %d\n", header->length); + } + header->length = 0; + control_pong(header); + break; + + + default: + break; + } + +} + +// ******************** The task ***************** + +TK_OBJECT(to_controltask); +TK_ENTRY(ControlTask); + +struct inet_taskinfo controltask = +{ + &to_controltask, + "Control thread", + ControlTask, + CONTROL_TASK_PRIORITY, + CONTROL_STACK_SIZE, +}; + + +void ControlTask(void* param) +{ + printf ("::: Control task started ::: \n"); + ethernet_listen(0, CONTROL_PORT); + + sensor_preconfigure(SENSOR_INTERFACE_BASE); + + //initial calibration factor here + printf("Initiate Calibration Factor 1 to 320 from channel1 to channel320 \n"); + + + for (alt_u32 i = 0; i < 320; i++) { + //pow(2,13)=8192. represent calibration factor 1; range[0.00012,8) + //default calibration factor is 1. + calibration_ram_set_factor(CALIBRATION_RAM_BASE,i,8192); //i is channelID + } + + while(1) + control_step(); +} + +void control_init() +{ + TK_NEWTASK(&controltask); +} diff --git a/FPGA_nios/hit_pat/src/main.c b/FPGA_nios/hit_pat/src/main.c new file mode 100644 index 0000000..e41efc4 --- /dev/null +++ b/FPGA_nios/hit_pat/src/main.c @@ -0,0 +1,161 @@ +/****************************************************************************** +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. All use of this software and documentation is * +* subject to the License Agreement located at the end of this file below. * +******************************************************************************* * +* Date - October 24, 2006 * +* Module - iniche_init.c * +* * * +******************************************************************************/ + +/****************************************************************************** + * NicheStack TCP/IP stack initialization and Operating System Start in main() + * for Simple Socket Server (SSS) example. + * + * This example demonstrates the use of MicroC/OS-II running on NIOS II. + * In addition it is to serve as a good starting point for designs using + * MicroC/OS-II and Altera NicheStack TCP/IP Stack - NIOS II Edition. + * + * Please refer to the Altera NicheStack Tutorial documentation for details on + * this software example, as well as details on how to configure the NicheStack + * TCP/IP networking stack and MicroC/OS-II Real-Time Operating System. + */ + + +#include + +/* MicroC/OS-II definitions */ +#include "includes.h" + +/* Simple Socket Server definitions */ +#include "socket_server.h" +#include "control.h" +//#include "alt_error_handler.h" + + +/* Nichestack definitions */ +#include "ipport.h" +#include "libport.h" +#include "osport.h" + +#define SS_INITIAL_TASK_PRIORITY 5 +/* Definition of task stack for the initial task which will initialize the NicheStack + * TCP/IP Stack and then initialize the rest of the Simple Socket Server example tasks. + */ +OS_STK InitialTaskStk[APP_STACK_SIZE]; + +/* InitialTask will initialize the NicheStack + * TCP/IP Stack and then initialize the rest of the Simple Socket Server example + * RTOS structures and tasks. + */ +void InitialTask(void *task_data) +{ + INT8U error_code; + + /* + * Initialize Altera NicheStack TCP/IP Stack - Nios II Edition specific code. + * NicheStack is initialized from a task, so that RTOS will have started, and + * I/O drivers are available. Two tasks are created: + * "Inet main" task with priority 2 + * "clock tick" task with priority 3 + */ + + alt_iniche_init(); + netmain(); + + /* Wait for the network stack to be ready before proceeding. + * iniche_net_ready indicates that TCP/IP stack is ready, and IP address is obtained. + */ + while (!iniche_net_ready){ + TK_SLEEP(1); + } + + /* Now that the stack is running, perform the application initialization steps */ + + /* Application Specific Task Launching Code Block Begin */ + + printf("\nSocket Server starting up\n"); + + /* Create tasks */ + ethernet_init(); + control_init(); + //TK_NEWTASK(&ssconntask); + + /* Application Specific Task Launching Code Block End */ + + /*This task is deleted because there is no need for it to run again */ + error_code = OSTaskDel(OS_PRIO_SELF); + //alt_uCOSIIErrorHandler(error_code, 0); + + while (1); /* Correct Program Flow should never get here */ +} + +/* Main creates a single task, SSSInitialTask, and starts task scheduler. + */ + +int main (int argc, char* argv[], char* envp[]) +{ + + INT8U error_code; + + /* Clear the RTOS timer */ + OSTimeSet(0); + + /* SSSInitialTask will initialize the NicheStack + * TCP/IP Stack and then initialize the rest of the Simple Socket Server example + * RTOS structures and tasks. + */ + error_code = OSTaskCreateExt(InitialTask, + NULL, + (void *)&InitialTaskStk[APP_STACK_SIZE], + SS_INITIAL_TASK_PRIORITY, + SS_INITIAL_TASK_PRIORITY, + InitialTaskStk, + APP_STACK_SIZE, + NULL, + 0); + //alt_uCOSIIErrorHandler(error_code, 0); + + /* + * As with all MicroC/OS-II designs, once the initial thread(s) and + * associated RTOS resources are declared, we start the RTOS. That's it! + */ + OSStart(); + + + + while(1); /* Correct Program Flow never gets here. */ + + return -1; +} + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ diff --git a/FPGA_nios/hit_pat/src/network_utilities.c b/FPGA_nios/hit_pat/src/network_utilities.c new file mode 100644 index 0000000..1b54881 --- /dev/null +++ b/FPGA_nios/hit_pat/src/network_utilities.c @@ -0,0 +1,456 @@ +/****************************************************************************** +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. All use of this software and documentation is * +* subject to the License Agreement located at the end of this file below. * +****************************************************************************** +* Date - October 24, 2006 * +* Module - network_utilities.c * +* * +******************************************************************************/ + +#include +#include +#include +#include +#include +#include "includes.h" +#include "io.h" +#include + +#include "ipport.h" +#include "tcpport.h" +#include "network_utilities.h" + +#include +#include + +#define IP4_ADDR(ipaddr, a,b,c,d) ipaddr = \ + htonl((((alt_u32)(a & 0xff) << 24) | ((alt_u32)(b & 0xff) << 16) | \ + ((alt_u32)(c & 0xff) << 8) | (alt_u32)(d & 0xff))) + +error_t generate_mac_addr(unsigned char mac_addr[6]); + +/* +* get_mac_addr +* +* Read the MAC address in a board specific way. Prompt user to enter serial +* number to generate MAC address if failed to read from flash. +* +*/ +int get_mac_addr(NET net, unsigned char mac_addr[6]) +{ + error_t error = 0; + + error = get_board_mac_addr(mac_addr); + + if(error) + { + /* Failed read MAC address from flash, prompt user to enter serial + number to generate MAC address. */ + error = generate_mac_addr(mac_addr); + } + return error; +} + +/* + * get_ip_addr() + * + * This routine is called by InterNiche to obtain an IP address for the + * specified network adapter. Like the MAC address, obtaining an IP address is + * very system-dependant and therefore this function is exported for the + * developer to control. + * + * In our system, we are either attempting DHCP auto-negotiation of IP address, + * or we are setting our own static IP, Gateway, and Subnet Mask addresses our + * self. This routine is where that happens. + */ +int get_ip_addr(alt_iniche_dev *p_dev, + ip_addr* ipaddr, + ip_addr* netmask, + ip_addr* gw, + int* use_dhcp) +{ + + alt_u32 sw_state = ~(IORD_ALTERA_AVALON_PIO_DATA(BUTTON_PIO_BASE)); + + printf("Input state: 0x%08lx\n", sw_state); + + /*if (sw_state & 0x100) + { + *use_dhcp = 1; + IP4_ADDR(*ipaddr, 0, 0, 0, 0); + IP4_ADDR(*gw, 0, 0, 0, 0); + IP4_ADDR(*netmask, 0, 0, 0, 0); + printf("DHCP enabled.\n"); + } + else + {*/ + *use_dhcp = 0; + IP4_ADDR(*ipaddr, IPADDR0, IPADDR1, IPADDR2, IPADDR3+((sw_state>>4)&0x0F)); + IP4_ADDR(*gw, GWADDR0, GWADDR1, GWADDR2, GWADDR3); + IP4_ADDR(*netmask, MSKADDR0, MSKADDR1, MSKADDR2, MSKADDR3); + printf("DHCP disabled.\n"); + printf("Static IP Address is %d.%d.%d.%d\n", + ip4_addr1(*ipaddr), + ip4_addr2(*ipaddr), + ip4_addr3(*ipaddr), + ip4_addr4(*ipaddr)); + //} + + + /* Non-standard API: return 1 for success */ + return 1; +} + +int FindLastFlashSectorOffset( + alt_u32 *pLastFlashSectorOffset); + +alt_u32 last_flash_sector_offset; +alt_u32 last_flash_sector; + +/* +* get_serial_number +* +* Prompt user to enter 9-digit serial number. +* +*/ +alt_u32 get_serial_number (void) +{ + alt_u32 ser_num = 0; + char serial_number[9]; + int i = 0; + + while(!ser_num) + { + printf("Please enter your 9-digit serial number. This is printed on a \n"); + printf("label under your Nios dev. board. The first 3 digits of the \n"); + printf("label are ASJ and the serial number follows this.\n -->"); + + for(i=0; i<9; i++) + { + serial_number[i] = getchar(); + putchar(serial_number[i]); + + /* Handle backspaces. How civilized. */ + if ((serial_number[i] == 0x08) && (i >= 0)) + { + i--; + } + } + printf("\n"); + + for(i=0; i<9; i++) + { + if (isdigit(serial_number[i])) + { + ser_num *= 10; + ser_num += serial_number[i] - '0'; + } + else + { + ser_num = 0; + printf("Serial number only contains decimal digits and is non-zero\n"); + break; + } + } + } + + return ser_num; +} + +/* + * generate_and_store_mac_addr() + * + * This routine is called when, upon program initialization, we discover + * that there is no valid network settings (including MAC address) programmed + * into flash memory at the last flash sector. If it is not safe to use the + * contents of this last sector of flash, the user is prompted to + * enter the serial number at the console. A MAC address is then + * generated using 0xFF followed by the last 2 bytes of the serial number + * appended to Altera's Vendor ID, an assigned MAC address range with the first + * 3 bytes of 00:07:ED. For example, if the Nios Development Board serial + * number is 040800017, the corresponding ethernet number generated will be + * 00:07:ED:FF:8F:11. + * + * It should be noted that this number, while unique, will likely differ from + * the also unique (but now lost forever) MAC address programmed into the + * development board on the production line. + * + * As we are erasing the entire flash sector, we'll re-program it with not + * only the MAC address, but static IP, subnet, gateway, and "Use DHCP" + * sections. These fail-safe static settings are compatible with previous + * Nios Ethernet designs, and allow the "factory-safe" design to behave + * as expected if the last flash sector is erased. + */ +error_t generate_and_store_mac_addr() +{ + error_t error = -1; + alt_u32 ser_num = 0; + char flash_content[32]; + alt_flash_fd* flash_handle; + + printf("Can't read the MAC address from your board (this probably means\n"); + printf("that your flash was erased). We will assign you a MAC address and\n"); + printf("static network settings\n\n"); + + ser_num = get_serial_number(); + + if (ser_num) + { + /* This says the image is safe */ + flash_content[0] = 0xfe; + flash_content[1] = 0x5a; + flash_content[2] = 0x0; + flash_content[3] = 0x0; + + /* This is the Altera Vendor ID */ + flash_content[4] = 0x0; + flash_content[5] = 0x7; + flash_content[6] = 0xed; + + /* Reserverd Board identifier for erase boards */ + flash_content[7] = 0xFF; + flash_content[8] = (ser_num & 0xff00) >> 8; + flash_content[9] = ser_num & 0xff; + + /* Then comes a 16-bit "flags" field */ + flash_content[10] = 0xFF; + flash_content[11] = 0xFF; + + /* Then comes the static IP address */ + flash_content[12] = IPADDR0; + flash_content[13] = IPADDR1; + flash_content[14] = IPADDR2; + flash_content[15] = IPADDR3; + + /* Then comes the static nameserver address */ + flash_content[16] = 0xFF; + flash_content[17] = 0xFF; + flash_content[18] = 0xFF; + flash_content[19] = 0xFF; + + /* Then comes the static subnet mask */ + flash_content[20] = MSKADDR0; + flash_content[21] = MSKADDR1; + flash_content[22] = MSKADDR2; + flash_content[23] = MSKADDR3; + + /* Then comes the static gateway address */ + flash_content[24] = GWADDR0; + flash_content[25] = GWADDR1; + flash_content[26] = GWADDR2; + flash_content[27] = GWADDR3; + + /* And finally whether to use DHCP - set all bits to be safe */ + flash_content[28] = 0xFF; + flash_content[29] = 0xFF; + flash_content[30] = 0xFF; + flash_content[31] = 0xFF; + + /* Write the MAC address to flash */ + flash_handle = alt_flash_open_dev(EXT_FLASH_AVL_MEM_NAME); + if (flash_handle) + { + alt_write_flash(flash_handle, + last_flash_sector_offset, + flash_content, + 32); + alt_flash_close_dev(flash_handle); + error = 0; + } + } + + return error; +} + +/* + * generate_mac_addr() + * + * This routine is called when failed to read MAC address from flash (i.e: no + * flash on the board). The user is prompted to enter the serial number at the + * console. A MAC address is then generated using 0xFF followed by the last 2 + * bytes of the serial number appended to Altera's Vendor ID, an assigned MAC + * address range with the first 3 bytes of 00:07:ED. For example, if the Nios + * Development Board serial number is 040800017, the corresponding ethernet + * number generated will be 00:07:ED:FF:8F:11. + * + */ +error_t generate_mac_addr(unsigned char mac_addr[6]) +{ + error_t error = -1; + alt_u32 ser_num = 0; + + printf("\nCan't read the MAC address from your board. We will assign you\n"); + printf("a MAC address.\n\n"); + + ser_num = get_serial_number(); + + if (ser_num) + { + /* This is the Altera Vendor ID */ + mac_addr[0] = 0x0; + mac_addr[1] = 0x7; + mac_addr[2] = 0xed; + + /* Reserverd Board identifier */ + mac_addr[3] = 0xFF; + mac_addr[4] = (ser_num & 0xff00) >> 8; + mac_addr[5] = ser_num & 0xff; + + printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", + mac_addr[0], + mac_addr[1], + mac_addr[2], + mac_addr[3], + mac_addr[4], + mac_addr[5]); + + error = 0; + } + + return error; +} + +/* +* get_board_mac_addr +* +* Read the MAC address in a board specific way +* +*/ +error_t get_board_mac_addr(unsigned char mac_addr[6]) +{ + error_t error = 0; + alt_u32 signature; + + /* Get the flash sector with the MAC address. */ + error = FindLastFlashSectorOffset(&last_flash_sector_offset); + if (!error) + last_flash_sector = EXT_FLASH_AVL_MEM_BASE + last_flash_sector_offset; + + /* This last_flash_sector region of flash is examined to see if + * valid network settings are present, indicated by a signature of 0x00005afe at + * the first address of the last flash sector. This hex value is chosen as the + * signature since it looks like the english word "SAFE", meaning that it is + * safe to use these network address values. + */ + if (!error) + { + signature = IORD_32DIRECT(last_flash_sector, 0); + if (signature != 0x00005afe) + { + error = generate_and_store_mac_addr(); + } + } + + if (!error) + { + mac_addr[0] = IORD_8DIRECT(last_flash_sector, 4); + mac_addr[1] = IORD_8DIRECT(last_flash_sector, 5); + mac_addr[2] = IORD_8DIRECT(last_flash_sector, 6); + mac_addr[3] = IORD_8DIRECT(last_flash_sector, 7); + mac_addr[4] = IORD_8DIRECT(last_flash_sector, 8); + mac_addr[5] = IORD_8DIRECT(last_flash_sector, 9); + + printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", + mac_addr[0], + mac_addr[1], + mac_addr[2], + mac_addr[3], + mac_addr[4], + mac_addr[5]); + + } + + return error; +} + +/******************************************************************************* + * + * Flash service functions. + * + ******************************************************************************/ + +#include "sys/alt_flash.h" +#include "sys/alt_flash_dev.h" + +/* + * FindLastFlashSectorOffset + * + * <-- pLastFlashSectorOffset Offset of last sector in flash. + * + * This function finds the offset to the last sector in flash and returns it + * in pLastFlashSectorOffset. + */ + +int FindLastFlashSectorOffset( + alt_u32 *pLastFlashSectorOffset) +{ + alt_flash_fd *fd; + flash_region *regions; + int numRegions; + flash_region *pLastRegion; + int lastFlashSectorOffset; + int n; + int error = 0; + + /* Open the flash device. */ + fd = alt_flash_open_dev(EXT_FLASH_AVL_MEM_NAME); + if (fd <= 0) + error = -1; + + /* Get the flash info. */ + if (!error) + error = alt_get_flash_info(fd, ®ions, &numRegions); + + /* Find the last flash sector. */ + if (!error) + { + pLastRegion = &(regions[0]); + for (n = 1; n < numRegions; n++) + { + if (regions[n].offset > pLastRegion->offset) + pLastRegion = &(regions[n]); + } + lastFlashSectorOffset = pLastRegion->offset + + pLastRegion->region_size + - pLastRegion->block_size; + } + + /* Return results. */ + if (!error) + *pLastFlashSectorOffset = lastFlashSectorOffset; + + return (error); +} + + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ diff --git a/FPGA_nios/hit_pat/src/sensor.c b/FPGA_nios/hit_pat/src/sensor.c new file mode 100644 index 0000000..ca468d8 --- /dev/null +++ b/FPGA_nios/hit_pat/src/sensor.c @@ -0,0 +1,53 @@ +/* + * sensor.c + * + * Created on: Aug 19, 2019 + * Author: mdziewiecki + */ + +#include +#include "includes.h" +#include +#include +#include + +/* Nichestack definitions */ +#include "ipport.h" +#include "libport.h" +#include "osport.h" + +#include "utils.h" +#include "dev_commands.h" +#include "sensor.h" + + +void sensor_command_bit(alt_u32 base, alt_u8 bitmask, alt_u8 state) +{ + alt_u8 tmp = IORD_8DIRECT(base, SENSOR_REG_COMMAND); + if (state) + tmp |= bitmask; + else + tmp &= ~bitmask; + IOWR_8DIRECT(base, SENSOR_REG_COMMAND, tmp); +} + + +void sensor_preconfigure(alt_u32 base) +{ + printf(" *** Preconfiguring sensor module... \n"); + + sensor_command(base, 0); //disable + sensor_set_sensorclk(base, 6); //sensor clock - 3.57 MHz + sensor_set_adccnv(base, 31); //conversion delay - default + sensor_set_delay(base, 1); //trigger delay - default + sensor_set_shutter(base, 100); //integration time - dummy default + sensor_set_serspeed(base, 50); //synchro serial port - 1 Mbps + sensor_set_header_anydata(base, 0x00); //should be 0 + sensor_set_header_cmd(base, COMMAND_DATA_TRANSFER); //command header, must be this one + sensor_command(base, 1); //enable, gain low, SCLK full + + sensor_set_cluster_threshold(base, 10); //default cluster threshold 10 + sensor_set_cluster_size(base, 4); //default cluster size 4 + sensor_set_in_algo_threshold(base, 4); //default algo threshold 4 + +} diff --git a/FPGA_nios/hit_pat/src/socket_server.c b/FPGA_nios/hit_pat/src/socket_server.c new file mode 100644 index 0000000..ba4f205 --- /dev/null +++ b/FPGA_nios/hit_pat/src/socket_server.c @@ -0,0 +1,332 @@ +/****************************************************************************** +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. All use of this software and documentation is * +* subject to the License Agreement located at the end of this file below. * +******************************************************************************* +* Date - October 24, 2006 * +* Module - simple_socket_server.c * +* * +******************************************************************************/ + +/****************************************************************************** + * Simple Socket Server (SSS) example. + * + * This example demonstrates the use of MicroC/OS-II running on NIOS II. + * In addition it is to serve as a good starting point for designs using + * MicroC/OS-II and Altera NicheStack TCP/IP Stack - NIOS II Edition. + * + * -Known Issues + * None. + * + * Please refer to the Altera NicheStack Tutorial documentation for details on this + * software example, as well as details on how to configure the NicheStack TCP/IP + * networking stack and MicroC/OS-II Real-Time Operating System. + */ + +#include +#include +#include + +/* MicroC/OS-II definitions */ +#include "includes.h" + +/* Simple Socket Server definitions */ +#include "socket_server.h" +//#include "alt_error_handler.h" + +/* Nichestack definitions */ +#include "ipport.h" +#include "tcpport.h" +#include "libport.h" +#include "osport.h" + + +static OS_EVENT *mutex; + +static SSConn connections[NR_CHANNELS]; + +TK_OBJECT(to_sslistenertask); +TK_ENTRY(SSListenerTask); + +struct inet_taskinfo sslistenertask = +{ + &to_sslistenertask, + "socket server listener", + SSListenerTask, + SS_LISTENER_TASK_PRIORITY, + SS_LISTENER_STACK_SIZE, +}; + +// ******************************************************** + + + +void ss_reset_connection(SSConn* conn) //called e.g. after closing a socket +{ + conn->fd_conn = -1; + conn->state = LISTENING; + return; +} + +void ss_initialize_connection(SSConn* conn) //called only at initialization +{ + conn->fd_conn = -1; + conn->fd_listen = -1; + conn->listenport = -1; + conn->state = FREE; + return; +} + +void ss_handle_accept(SSConn* conn) +{ + int socket; + int len; + struct sockaddr_in incoming_addr; + + INT8U err; + OSMutexPend(mutex, 0, &err); + + len = sizeof(incoming_addr); + + //Close old connection if needed + if ((conn)->fd_conn != -1) + { + printf("[ss_handle_accept] closing old connection\n"); + close(conn->fd_conn); + ss_reset_connection(conn); + } + + if((socket=accept(conn->fd_listen,(struct sockaddr*)&incoming_addr,&len))<0) + { + //alt_NetworkErrorHandler(EXPANDED_DIAGNOSIS_CODE, + // "[ss_handle_accept] accept failed"); + } + else + { + (conn)->fd_conn = socket; + (conn)->state = CONNECTED; + printf("[ss_handle_accept] accepted connection request from %s\n", + inet_ntoa(incoming_addr.sin_addr)); + } + + OSMutexPost(mutex); + return; +} + +/* + * Listener Task() + */ +void SSListenerTask(void* param) +{ + + int max_socket = 0; + BSD_TIMEVAL_T timeout; + + INT8U err; + OSMutexPend(mutex, 0, &err); //wrap initialization in a mutex - just in case... + + timeout.tv_sec = 0; + timeout.tv_usec = 100000; + + fd_set readfds; //set of descriptors + + for (int ch = 0; ch < NR_CHANNELS; ch++) + if ((connections[ch].fd_listen = socket(AF_INET, SOCK_STREAM, 0)) < 0) + { + //printf("Errot initializing socket #%d!\n", ch); + //alt_NetworkErrorHandler(EXPANDED_DIAGNOSIS_CODE,"[sss_task] Socket creation failed"); + } + + //Binding etc. is done by ethernet_listen() + + OSMutexPost(mutex); + + //Now run in loop to handle incoming requests on all listening ports + while(1) + { + FD_ZERO(&readfds); + + for (int ch = 0; ch < NR_CHANNELS; ch++) + if (connections[ch].listenport >= 0) + { + FD_SET(connections[ch].fd_listen, &readfds); + if (connections[ch].fd_listen >= max_socket) + max_socket = connections[ch].fd_listen+1; + } + + if (max_socket == 0) + TK_SLEEP(10); //just sleep a bit if nothing to do + else + { + select(max_socket, &readfds, NULL, NULL, &timeout); //we must timeout from time to time to find newly set-up channels + + for (int ch = 0; ch < NR_CHANNELS; ch++) + if (FD_ISSET(connections[ch].fd_listen, &readfds)) + ss_handle_accept(&(connections[ch])); + } + } /* while(1) */ + + //never come here +} + + +// ****************** User interface ******************** + +int ethernet_init() +{ + INT8U err; + mutex = OSMutexCreate(SS_LISTENER_TASK_PRIORITY-1, &err); + + + for (int ch = 0; ch < NR_CHANNELS; ch++) + ss_initialize_connection(&(connections[ch])); + + TK_NEWTASK(&sslistenertask); + return 0; +} + +int ethernet_listen(int channel, int port) +{ + struct sockaddr_in addr; + + INT8U err; + OSMutexPend(mutex, 0, &err); + + addr.sin_family = AF_INET; + addr.sin_port = htons(port); + addr.sin_addr.s_addr = INADDR_ANY; + + if (bind(connections[channel].fd_listen,(struct sockaddr *)&addr,sizeof(addr)) < 0) + { + //alt_NetworkErrorHandler(EXPANDED_DIAGNOSIS_CODE,"[sss_task] Bind failed"); + OSMutexPost(mutex); + return -1; + } + + if (listen(connections[channel].fd_listen,1) < 0) + { + //alt_NetworkErrorHandler(EXPANDED_DIAGNOSIS_CODE,"[sss_task] Listen failed"); + OSMutexPost(mutex); + return -2; + } + + ss_reset_connection(&(connections[channel])); + connections[channel].listenport = port; + printf("[sss_task] Simple Socket Server listening on port %d\n", port); + + OSMutexPost(mutex); + return 0; +} + +int ethernet_write(int channel, int size, unsigned char* data) +{ + int result; + + INT8U err; + OSMutexPend(mutex, 0, &err); + + if (connections[channel].fd_conn == -1) //socket is closed or channel unconfigured + { + OSMutexPost(mutex); + return 0; + } + + result = (int)send(connections[channel].fd_conn, data, size, 0); + if (result == -1) + { + printf("[ethernet_write] closing connection due to error\n"); + close(connections[channel].fd_conn); //close connection on error + ss_reset_connection(&(connections[channel])); + result = 0; + } + + OSMutexPost(mutex); + return result; +} + +int ethernet_read(int channel, int size, unsigned char* data) +{ + fd_set readfds; //set of descriptors + int max_socket; + BSD_TIMEVAL_T timeout; + int result; + + INT8U err; + OSMutexPend(mutex, 0, &err); + + if (connections[channel].fd_conn == -1) //socket is closed or channel unconfigured + { + OSMutexPost(mutex); + return 0; + } + + //prepare call parameters + FD_ZERO(&readfds); + FD_SET(connections[channel].fd_conn, &readfds); + max_socket = connections[channel].fd_conn+1; + timeout.tv_sec = 0; + timeout.tv_usec = 0; + + //check for data + if (select(max_socket, &readfds, NULL, NULL, &timeout)) + if (FD_ISSET(connections[channel].fd_conn, &readfds)) + { + result = (int)recv(connections[channel].fd_conn, data, size, 0); + if (result == -1) + { + printf("[ethernet_read] closing connection due to error\n"); + close(connections[channel].fd_conn); //close connection on error + ss_reset_connection(&(connections[channel])); + result = 0; + } + OSMutexPost(mutex); + return result; + } + + OSMutexPost(mutex); + return 0; +} + +int ethernet_close(int channel) +{ + INT8U err; + OSMutexPend(mutex, 0, &err); + + close(connections[channel].fd_conn); + ss_reset_connection(&(connections[channel])); + + OSMutexPost(mutex); + return 0; +} + + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ diff --git a/FPGA_nios/hit_pat/src/tse_my_system.c b/FPGA_nios/hit_pat/src/tse_my_system.c new file mode 100644 index 0000000..a6cbb18 --- /dev/null +++ b/FPGA_nios/hit_pat/src/tse_my_system.c @@ -0,0 +1,12 @@ +#ifdef ALT_INICHE + #include "ipport.h" +#endif + +#include "system.h" +#include "altera_avalon_tse.h" +#include "altera_avalon_tse_system_info.h" + +alt_tse_system_info tse_mac_device[MAXNETS] = { + TSE_SYSTEM_EXT_MEM_NO_SHARED_FIFO(ETH_TSE, 0, MSGDMA_TX, MSGDMA_RX, TSE_PHY_AUTO_ADDRESS, &marvell_cfg_rgmii, DESCRIPTOR_MEMORY) + +}; diff --git a/FPGA_nios/hit_pat/src/udpgen.c b/FPGA_nios/hit_pat/src/udpgen.c new file mode 100644 index 0000000..0f2bf44 --- /dev/null +++ b/FPGA_nios/hit_pat/src/udpgen.c @@ -0,0 +1,51 @@ +/* + * udpgen.c + * + * Created on: Aug 7, 2019 + * Author: mdziewiecki + */ + +#include +#include "includes.h" +#include +#include +#include + +/* Nichestack definitions */ +#include "ipport.h" +#include "libport.h" +#include "osport.h" + +#include "utils.h" + +#include "udpgen.h" + +//******************************************************************* + + +void udpgen_command_bit(alt_u32 base, alt_u8 bitmask, alt_u8 state) +{ + alt_u8 tmp = IORD_8DIRECT(base, UDPGEN_REG_CSR); + if (state) + tmp |= bitmask; + else + tmp &= ~bitmask; + IOWR_8DIRECT(base, UDPGEN_REG_CSR, tmp); +} + +void udpgen_test(alt_u32 base) +{ + printf (" *** Setting up UDP generator... \n"); + + unsigned char dstmac[] = {0x18, 0xd6, 0xc7, 0x05, 0xaa, 0x63}; + unsigned char srcip[] = {10,0,7,17}; + unsigned char dstip[] = {10,0,7,1}; + + udpgen_command(UDP_GENERATOR_BASE, 0x01); + udpgen_set_size(UDP_GENERATOR_BASE, 16); + udpgen_set_srcip_a(UDP_GENERATOR_BASE, srcip); + udpgen_set_dstip_a(UDP_GENERATOR_BASE, dstip); + udpgen_set_srcport(UDP_GENERATOR_BASE, 4096); + udpgen_set_dstport(UDP_GENERATOR_BASE, 4097); + udpgen_set_dstmac_a(UDP_GENERATOR_BASE, dstmac); +} diff --git a/FPGA_nios/hit_pat/src/utils.c b/FPGA_nios/hit_pat/src/utils.c new file mode 100644 index 0000000..926a6cc --- /dev/null +++ b/FPGA_nios/hit_pat/src/utils.c @@ -0,0 +1,131 @@ +/* + * utils.c + * + * Created on: Jul 31, 2019 + * Author: mdziewiecki + */ + + +#include +#include "includes.h" +#include +#include + +/* Nichestack definitions */ +#include "ipport.h" +#include "libport.h" +#include "osport.h" + +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_timer_regs.h" +#include "utils.h" + +#include "sensor.h" + +alt_u16 delays[2]; +alt_u8 mastermode; + +//****************************************************** + +//Swap odd/even bytes in a bunch of data to align endianness of shorts +void swap_bytes(unsigned char* array, int size_bytes) +{ + for (int i = 0; i < size_bytes; i+= 2) + { + unsigned char tmp = array[i]; + array[i] = array[i+1]; + array[i+1] = tmp; + } +} +//The same, but four-byte-wise +void swap_quad(unsigned char* array, int size_bytes) +{ + unsigned char buf[4]; + + for (int i = 0; i < size_bytes; i+= 4) + { + memcpy(buf, array+i, 4); + for (int j = 0; j < 4; j++) + array[i+j] = buf[3-j]; + } +} + + //trigger FPGA reload +void reload_fpga() +{ + printf("$$$$ RECONFIGURING FPGA!!! $$$$\n"); + //TK_SLEEP(100); //let it print the message before dying + //IOWR(DUAL_BOOT_BASE, 0, 0x1); + printf("*** DISABLED! ***\n"); +} + +void masterslave(alt_u8 master) +{ + if (master) + IOWR_ALTERA_AVALON_PIO_SET_BITS(OUTPUT_PIO_BASE, 0x80); + else + IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(OUTPUT_PIO_BASE, 0x80); + mastermode = master; + set_delay(mastermode, delays[mastermode]); //update sensor delay setting +} + +void master_clock_period(alt_u32 period) +{ + //set period + IOWR_ALTERA_AVALON_TIMER_PERIODL(FRAME_TIMER_BASE, (alt_u16)(period & 0xFFFF)); + IOWR_ALTERA_AVALON_TIMER_PERIODH(FRAME_TIMER_BASE, (alt_u16)((period>>16) & 0xFFFF)); + //start timer in continuous mode + //IOWR_ALTERA_AVALON_TIMER_CONTROL(FRAME_TIMER_BASE, + // ALTERA_AVALON_TIMER_CONTROL_CONT_MSK); +} + +void master_clock_enable(alt_u8 en) +{ + alt_u16 tmp = 0; // = IORD_ALTERA_AVALON_TIMER_CONTROL(FRAME_TIMER_BASE); + + if (en) + tmp |= ALTERA_AVALON_TIMER_CONTROL_START_MSK | ALTERA_AVALON_TIMER_CONTROL_CONT_MSK; + else + tmp |= ALTERA_AVALON_TIMER_CONTROL_STOP_MSK; + + IOWR_ALTERA_AVALON_TIMER_CONTROL(FRAME_TIMER_BASE,tmp); +} + +void led_set(alt_u8 led_nr) +{ + if (led_nr > 4) + return; + IOWR_ALTERA_AVALON_PIO_SET_BITS(OUTPUT_PIO_BASE, 1< 4) + return; + IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(OUTPUT_PIO_BASE, 1< 4) + return; + alt_u32 tmp = IORD_ALTERA_AVALON_PIO_DATA(OUTPUT_PIO_BASE); + tmp ^= (1< + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/alt_types.h b/FPGA_nios/hit_pat_bsp/HAL/inc/alt_types.h new file mode 100644 index 0000000..8eb438f --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/alt_types.h @@ -0,0 +1,54 @@ +#ifndef __ALT_TYPES_H__ +#define __ALT_TYPES_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* + * Don't declare these typedefs if this file is included by assembly source. + */ +#ifndef ALT_ASM_SRC +typedef signed char alt_8; +typedef unsigned char alt_u8; +typedef signed short alt_16; +typedef unsigned short alt_u16; +typedef signed long alt_32; +typedef unsigned long alt_u32; +typedef long long alt_64; +typedef unsigned long long alt_u64; +#endif + +#define ALT_INLINE __inline__ +#define ALT_ALWAYS_INLINE __attribute__ ((always_inline)) +#define ALT_WEAK __attribute__((weak)) + +#endif /* __ALT_TYPES_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/altera_nios2_gen2_irq.h b/FPGA_nios/hit_pat_bsp/HAL/inc/altera_nios2_gen2_irq.h new file mode 100644 index 0000000..048e02f --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/altera_nios2_gen2_irq.h @@ -0,0 +1,80 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * Support for the Nios II internal interrupt controller. + */ + +#ifndef __ALT_NIOS2_GEN2_IRQ_H__ +#define __ALT_NIOS2_GEN2_IRQ_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The macro ALTERA_NIOS2_GEN2_IRQ_INSTANCE is used by the alt_irq_init() + * function in the auto-generated file alt_sys_init.c to create an + * instance of this interrupt controller device driver state if this + * module contains an interrupt controller. + * Only one instance of a Nios II is allowed so this macro is just empty. + */ + +#define ALTERA_NIOS2_GEN2_IRQ_INSTANCE(name, state) + +/* + * altera_nios2_gen2_irq_init() is called by the auto-generated function + * alt_irq_init() once for the Nios II if it contains an interrupt controller. + * The altera_nios2_gen2_irq_init() routine is called using the + * ALTERA_NIOS2_GEN2_IRQ_INIT macro given below. + * + * This function initializes the internal interrupt controller + * so is not called if the Nios II contains an external interrupt + * controller port (because the internal interrupt controller + * is removed if this port is present). + */ + +extern void altera_nios2_gen2_irq_init( void ); + +/* + * The macro ALTERA_NIOS2_GEN2_IRQ_INIT is used by the alt_irq_init() routine + * in the auto-generated file alt_sys_init.c to initialize an instance + * of the interrupt controller device driver state. + */ + +#define ALTERA_NIOS2_GEN2_IRQ_INIT(name, state) altera_nios2_gen2_irq_init() + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_NIOS2_ULTRA_IRQ_H__ */ + diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/includes.h b/FPGA_nios/hit_pat_bsp/HAL/inc/includes.h new file mode 100644 index 0000000..ac95016 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/includes.h @@ -0,0 +1,65 @@ +#ifndef __INCLUDES_H__ +#define __INCLUDES_H__ + +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* +* (c) Copyright 1992-1998, Jean J. Labrosse, Plantation, FL +* All Rights Reserved +* +* MASTER INCLUDE FILE +********************************************************************************************************* +*/ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +#include "os_cpu.h" +#include "os_cfg.h" +#include "ucos_ii.h" + +#ifdef ONT_GLOBALS +#define ONT_EXT +#else +#define ONT_EXT extern +#endif + +/* +********************************************************************************************************* +* DATA TYPES +********************************************************************************************************* +*/ + +typedef struct { + char TaskName[30]; + INT16U TaskCtr; + INT16U TaskExecTime; + INT32U TaskTotExecTime; +} TASK_USER_DATA; + +/* +********************************************************************************************************* +* VARIABLES +********************************************************************************************************* +*/ + +ONT_EXT TASK_USER_DATA TaskUserData[10]; + +/* +********************************************************************************************************* +* FUNCTION PROTOTYPES +********************************************************************************************************* +*/ + +void DispTaskStat(INT8U id); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCLUDES_H__ */ + diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/io.h b/FPGA_nios/hit_pat_bsp/HAL/inc/io.h new file mode 100644 index 0000000..05efdd0 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/io.h @@ -0,0 +1,81 @@ +#ifndef __IO_H__ +#define __IO_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* IO Header file for Nios II Toolchain */ + +#include "alt_types.h" +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +#ifndef SYSTEM_BUS_WIDTH +#define SYSTEM_BUS_WIDTH 32 +#endif + +/* Dynamic bus access functions */ + +#define __IO_CALC_ADDRESS_DYNAMIC(BASE, OFFSET) \ + ((void *)(((alt_u8*)BASE) + (OFFSET))) + +#define IORD_32DIRECT(BASE, OFFSET) \ + __builtin_ldwio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET))) +#define IORD_16DIRECT(BASE, OFFSET) \ + __builtin_ldhuio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET))) +#define IORD_8DIRECT(BASE, OFFSET) \ + __builtin_ldbuio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET))) + +#define IOWR_32DIRECT(BASE, OFFSET, DATA) \ + __builtin_stwio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)), (DATA)) +#define IOWR_16DIRECT(BASE, OFFSET, DATA) \ + __builtin_sthio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)), (DATA)) +#define IOWR_8DIRECT(BASE, OFFSET, DATA) \ + __builtin_stbio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)), (DATA)) + +/* Native bus access functions */ + +#define __IO_CALC_ADDRESS_NATIVE(BASE, REGNUM) \ + ((void *)(((alt_u8*)BASE) + ((REGNUM) * (SYSTEM_BUS_WIDTH/8)))) + +#define IORD(BASE, REGNUM) \ + __builtin_ldwio (__IO_CALC_ADDRESS_NATIVE ((BASE), (REGNUM))) +#define IOWR(BASE, REGNUM, DATA) \ + __builtin_stwio (__IO_CALC_ADDRESS_NATIVE ((BASE), (REGNUM)), (DATA)) + +#ifdef __cplusplus +} +#endif + +#endif /* __IO_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/nios2.h b/FPGA_nios/hit_pat_bsp/HAL/inc/nios2.h new file mode 100644 index 0000000..7d4a550 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/nios2.h @@ -0,0 +1,300 @@ +#ifndef __NIOS2_H__ +#define __NIOS2_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This header provides processor specific macros for accessing the Nios2 + * control registers. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Number of available IRQs in internal interrupt controller. + */ +#define NIOS2_NIRQ 32 + +/* + * Macros for accessing select Nios II general-purpose registers. + */ + +/* ET (Exception Temporary) register */ +#define NIOS2_READ_ET(et) \ + do { __asm ("mov %0, et" : "=r" (et) ); } while (0) + +#define NIOS2_WRITE_ET(et) \ + do { __asm volatile ("mov et, %z0" : : "rM" (et)); } while (0) + +/* SP (Stack Pointer) register */ +#define NIOS2_READ_SP(sp) \ + do { __asm ("mov %0, sp" : "=r" (sp) ); } while (0) + +/* + * Macros for useful processor instructions. + */ +#define NIOS2_BREAK() \ + do { __asm volatile ("break"); } while (0) + +#define NIOS2_REPORT_STACK_OVERFLOW() \ + do { __asm volatile("break 3"); } while (0) + +/* + * Macros for accessing Nios II control registers. + */ +#define NIOS2_READ_STATUS(dest) \ + do { dest = __builtin_rdctl(0); } while (0) + +#define NIOS2_WRITE_STATUS(src) \ + do { __builtin_wrctl(0, src); } while (0) + +#define NIOS2_READ_ESTATUS(dest) \ + do { dest = __builtin_rdctl(1); } while (0) + +#define NIOS2_READ_BSTATUS(dest) \ + do { dest = __builtin_rdctl(2); } while (0) + +#define NIOS2_READ_IENABLE(dest) \ + do { dest = __builtin_rdctl(3); } while (0) + +#define NIOS2_WRITE_IENABLE(src) \ + do { __builtin_wrctl(3, src); } while (0) + +#define NIOS2_READ_IPENDING(dest) \ + do { dest = __builtin_rdctl(4); } while (0) + +#define NIOS2_READ_CPUID(dest) \ + do { dest = __builtin_rdctl(5); } while (0) + +#define NIOS2_READ_EXCEPTION(dest) \ + do { dest = __builtin_rdctl(7); } while (0) + +#define NIOS2_READ_PTEADDR(dest) \ + do { dest = __builtin_rdctl(8); } while (0) + +#define NIOS2_WRITE_PTEADDR(src) \ + do { __builtin_wrctl(8, src); } while (0) + +#define NIOS2_READ_TLBACC(dest) \ + do { dest = __builtin_rdctl(9); } while (0) + +#define NIOS2_WRITE_TLBACC(src) \ + do { __builtin_wrctl(9, src); } while (0) + +#define NIOS2_READ_TLBMISC(dest) \ + do { dest = __builtin_rdctl(10); } while (0) + +#define NIOS2_WRITE_TLBMISC(src) \ + do { __builtin_wrctl(10, src); } while (0) + +#define NIOS2_READ_ECCINJ(dest) \ + do { dest = __builtin_rdctl(11); } while (0) + +#define NIOS2_WRITE_ECCINJ(src) \ + do { __builtin_wrctl(11, src); } while (0) + +#define NIOS2_READ_BADADDR(dest) \ + do { dest = __builtin_rdctl(12); } while (0) + +#define NIOS2_WRITE_CONFIG(src) \ + do { __builtin_wrctl(13, src); } while (0) + +#define NIOS2_READ_CONFIG(dest) \ + do { dest = __builtin_rdctl(13); } while (0) + +#define NIOS2_WRITE_MPUBASE(src) \ + do { __builtin_wrctl(14, src); } while (0) + +#define NIOS2_READ_MPUBASE(dest) \ + do { dest = __builtin_rdctl(14); } while (0) + +#define NIOS2_WRITE_MPUACC(src) \ + do { __builtin_wrctl(15, src); } while (0) + +#define NIOS2_READ_MPUACC(dest) \ + do { dest = __builtin_rdctl(15); } while (0) + +/* + * Nios II control registers that are always present + */ +#define NIOS2_STATUS status +#define NIOS2_ESTATUS estatus +#define NIOS2_BSTATUS bstatus +#define NIOS2_IENABLE ienable +#define NIOS2_IPENDING ipending +#define NIOS2_CPUID cpuid + +/* + * Bit masks & offsets for Nios II control registers. + * The presence and size of a field is sometimes dependent on the Nios II + * configuration. Bit masks for every possible field and the maximum size of + * that field are defined. + * + * All bit-masks are expressed relative to the position + * of the data with a register. To read data that is LSB- + * aligned, the register read data should be masked, then + * right-shifted by the designated "OFST" macro value. The + * opposite should be used for register writes when starting + * with LSB-aligned data. + */ + +/* STATUS, ESTATUS, BSTATUS, and SSTATUS registers */ +#define NIOS2_STATUS_PIE_MSK (0x00000001) +#define NIOS2_STATUS_PIE_OFST (0) +#define NIOS2_STATUS_U_MSK (0x00000002) +#define NIOS2_STATUS_U_OFST (1) +#define NIOS2_STATUS_EH_MSK (0x00000004) +#define NIOS2_STATUS_EH_OFST (2) +#define NIOS2_STATUS_IH_MSK (0x00000008) +#define NIOS2_STATUS_IH_OFST (3) +#define NIOS2_STATUS_IL_MSK (0x000003f0) +#define NIOS2_STATUS_IL_OFST (4) +#define NIOS2_STATUS_CRS_MSK (0x0000fc00) +#define NIOS2_STATUS_CRS_OFST (10) +#define NIOS2_STATUS_PRS_MSK (0x003f0000) +#define NIOS2_STATUS_PRS_OFST (16) +#define NIOS2_STATUS_NMI_MSK (0x00400000) +#define NIOS2_STATUS_NMI_OFST (22) +#define NIOS2_STATUS_RSIE_MSK (0x00800000) +#define NIOS2_STATUS_RSIE_OFST (23) +#define NIOS2_STATUS_SRS_MSK (0x80000000) +#define NIOS2_STATUS_SRS_OFST (31) + +/* EXCEPTION register */ +#define NIOS2_EXCEPTION_REG_CAUSE_MASK (0x0000007c) +#define NIOS2_EXCEPTION_REG_CAUSE_OFST (2) +#define NIOS2_EXCEPTION_REG_ECCFTL_MASK (0x80000000) +#define NIOS2_EXCEPTION_REG_ECCFTL_OFST (31) + +/* PTEADDR (Page Table Entry Address) register */ +#define NIOS2_PTEADDR_REG_VPN_OFST 2 +#define NIOS2_PTEADDR_REG_VPN_MASK 0x3ffffc +#define NIOS2_PTEADDR_REG_PTBASE_OFST 22 +#define NIOS2_PTEADDR_REG_PTBASE_MASK 0xffc00000 + +/* TLBACC (TLB Access) register */ +#define NIOS2_TLBACC_REG_PFN_OFST 0 +#define NIOS2_TLBACC_REG_PFN_MASK 0xfffff +#define NIOS2_TLBACC_REG_G_OFST 20 +#define NIOS2_TLBACC_REG_G_MASK 0x100000 +#define NIOS2_TLBACC_REG_X_OFST 21 +#define NIOS2_TLBACC_REG_X_MASK 0x200000 +#define NIOS2_TLBACC_REG_W_OFST 22 +#define NIOS2_TLBACC_REG_W_MASK 0x400000 +#define NIOS2_TLBACC_REG_R_OFST 23 +#define NIOS2_TLBACC_REG_R_MASK 0x800000 +#define NIOS2_TLBACC_REG_C_OFST 24 +#define NIOS2_TLBACC_REG_C_MASK 0x1000000 +#define NIOS2_TLBACC_REG_IG_OFST 25 +#define NIOS2_TLBACC_REG_IG_MASK 0xfe000000 + +/* TLBMISC (TLB Miscellaneous) register */ +#define NIOS2_TLBMISC_REG_D_OFST 0 +#define NIOS2_TLBMISC_REG_D_MASK 0x1 +#define NIOS2_TLBMISC_REG_PERM_OFST 1 +#define NIOS2_TLBMISC_REG_PERM_MASK 0x2 +#define NIOS2_TLBMISC_REG_BAD_OFST 2 +#define NIOS2_TLBMISC_REG_BAD_MASK 0x4 +#define NIOS2_TLBMISC_REG_DBL_OFST 3 +#define NIOS2_TLBMISC_REG_DBL_MASK 0x8 +#define NIOS2_TLBMISC_REG_PID_OFST 4 +#define NIOS2_TLBMISC_REG_PID_MASK 0x3fff0 +#define NIOS2_TLBMISC_REG_WE_OFST 18 +#define NIOS2_TLBMISC_REG_WE_MASK 0x40000 +#define NIOS2_TLBMISC_REG_RD_OFST 19 +#define NIOS2_TLBMISC_REG_RD_MASK 0x80000 +#define NIOS2_TLBMISC_REG_WAY_OFST 20 +#define NIOS2_TLBMISC_REG_WAY_MASK 0xf00000 +#define NIOS2_TLBMISC_REG_EE_OFST 24 +#define NIOS2_TLBMISC_REG_EE_MASK 0x1000000 + +/* ECCINJ (ECC Inject) register */ +#define NIOS2_ECCINJ_REG_RF_OFST 0 +#define NIOS2_ECCINJ_REG_RF_MASK 0x3 +#define NIOS2_ECCINJ_REG_ICTAG_OFST 2 +#define NIOS2_ECCINJ_REG_ICTAG_MASK 0xc +#define NIOS2_ECCINJ_REG_ICDAT_OFST 4 +#define NIOS2_ECCINJ_REG_ICDAT_MASK 0x30 +#define NIOS2_ECCINJ_REG_DCTAG_OFST 6 +#define NIOS2_ECCINJ_REG_DCTAG_MASK 0xc0 +#define NIOS2_ECCINJ_REG_DCDAT_OFST 8 +#define NIOS2_ECCINJ_REG_DCDAT_MASK 0x300 +#define NIOS2_ECCINJ_REG_TLB_OFST 10 +#define NIOS2_ECCINJ_REG_TLB_MASK 0xc00 +#define NIOS2_ECCINJ_REG_DTCM0_OFST 12 +#define NIOS2_ECCINJ_REG_DTCM0_MASK 0x3000 +#define NIOS2_ECCINJ_REG_DTCM1_OFST 14 +#define NIOS2_ECCINJ_REG_DTCM1_MASK 0xc000 +#define NIOS2_ECCINJ_REG_DTCM2_OFST 16 +#define NIOS2_ECCINJ_REG_DTCM2_MASK 0x30000 +#define NIOS2_ECCINJ_REG_DTCM3_OFST 18 +#define NIOS2_ECCINJ_REG_DTCM3_MASK 0xc0000 + +/* CONFIG register */ +#define NIOS2_CONFIG_REG_PE_MASK (0x00000001) +#define NIOS2_CONFIG_REG_PE_OFST (0) +#define NIOS2_CONFIG_REG_ANI_MASK (0x00000002) +#define NIOS2_CONFIG_REG_ANI_OFST (1) +#define NIOS2_CONFIG_REG_ECCEN_MASK (0x00000004) +#define NIOS2_CONFIG_REG_ECCEN_OFST (2) +#define NIOS2_CONFIG_REG_ECCEXC_MASK (0x00000008) +#define NIOS2_CONFIG_REG_ECCEXC_OFST (3) + +/* MPUBASE (MPU Base Address) Register */ +#define NIOS2_MPUBASE_D_MASK (0x00000001) +#define NIOS2_MPUBASE_D_OFST (0) +#define NIOS2_MPUBASE_INDEX_MASK (0x0000003e) +#define NIOS2_MPUBASE_INDEX_OFST (1) +#define NIOS2_MPUBASE_BASE_ADDR_MASK (0xffffffc0) +#define NIOS2_MPUBASE_BASE_ADDR_OFST (6) + +/* MPUACC (MPU Access) Register */ +#define NIOS2_MPUACC_LIMIT_MASK (0xffffffc0) +#define NIOS2_MPUACC_LIMIT_OFST (6) +#define NIOS2_MPUACC_MASK_MASK (0xffffffc0) +#define NIOS2_MPUACC_MASK_OFST (6) +#define NIOS2_MPUACC_C_MASK (0x00000020) +#define NIOS2_MPUACC_C_OFST (5) +#define NIOS2_MPUACC_PERM_MASK (0x0000001c) +#define NIOS2_MPUACC_PERM_OFST (2) +#define NIOS2_MPUACC_RD_MASK (0x00000002) +#define NIOS2_MPUACC_RD_OFST (1) +#define NIOS2_MPUACC_WR_MASK (0x00000001) +#define NIOS2_MPUACC_WR_OFST (0) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __NIOS2_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/os_cpu.h b/FPGA_nios/hit_pat_bsp/HAL/inc/os_cpu.h new file mode 100644 index 0000000..d7591fe --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/os_cpu.h @@ -0,0 +1,145 @@ +#ifndef __OS_CPU_H__ +#define __OS_CPU_H__ + +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* +* (c) Copyright 1992-1999, Jean J. Labrosse, Weston, FL +* All Rights Reserved +* +* 80x86/80x88 Specific code +* LARGE MEMORY MODEL +* +* Borland C/C++ V4.51 +* +* File : OS_CPU.H +* By : IS (modified from version by Jean J. Labrosse) +********************************************************************************************************* +*/ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-5 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +#include "sys/alt_irq.h" + +#ifdef OS_CPU_GLOBALS +#define OS_CPU_EXT +#else +#define OS_CPU_EXT extern +#endif + +/***************************************************************************************** +/ REVISION HISTORY +/ +*****************************************************************************************/ + +/***************************************************************************************** +/ DATA TYPES +/ (Compiler Specific) +*****************************************************************************************/ + +/* This is the definition for Nios32. */ +typedef unsigned char BOOLEAN; +typedef unsigned char INT8U; /* Unsigned 8 bit quantity */ +typedef signed char INT8S; /* Signed 8 bit quantity */ +typedef unsigned short INT16U; /* Unsigned 16 bit quantity */ +typedef signed short INT16S; /* Signed 16 bit quantity */ +typedef unsigned long INT32U; /* Unsigned 32 bit quantity */ +typedef signed long INT32S; /* Signed 32 bit quantity */ +typedef float FP32; /* Single precision floating point */ +typedef double FP64; /* Double precision floating point */ +typedef unsigned int OS_STK; /* Each stack entry is 32-bits */ + +/**************************************************************************** +* Nios2 Miscellaneous defines +****************************************************************************/ + +#define OS_STK_GROWTH 1 /* Stack grows from HIGH to LOW memory */ +#define OS_TASK_SW OSCtxSw + +/****************************************************************************************** + * Disable and Enable Interrupts - 2 methods + * + * Method #1: Disable/Enable interrupts using simple instructions. After critical + * section, interrupts will be enabled even if they were disabled before + * entering the critical section. + * + * Method #2: Disable/Enable interrupts by preserving the state of interrupts. In + * other words, if interrupts were disabled before entering the critical + * section, they will be disabled when leaving the critical section. + * + * Method #3: Disable/Enable interrupts by preserving the state of interrupts. Generally speaking you + * would store the state of the interrupt disable flag in the local variable 'cpu_sr' and then + * disable interrupts. 'cpu_sr' is allocated in all of uC/OS-II's functions that need to + * disable interrupts. You would restore the interrupt disable state by copying back 'cpu_sr' + * into the CPU's status register. + * + *****************************************************************************************/ + +#define OS_CRITICAL_METHOD 3 + +#if OS_CRITICAL_METHOD == 1 +#error OS_CRITICAL_METHOD == 1 not supported, please use method 3 instead. +#endif + +#if OS_CRITICAL_METHOD == 2 +#error OS_CRITICAL_METHOD == 2 not supported, please use method 3 instead. +#endif + +#if OS_CRITICAL_METHOD == 3 +#define OS_CPU_SR alt_irq_context +#define OS_ENTER_CRITICAL() \ + cpu_sr = alt_irq_disable_all () +#define OS_EXIT_CRITICAL() \ + alt_irq_enable_all (cpu_sr); +#endif + +/* Prototypes */ +void OSStartHighRdy(void); +void OSCtxSw(void); +void OSIntCtxSw(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __OS_CPU_H__ */ + + + diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_alarm.h b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_alarm.h new file mode 100644 index 0000000..ae687bb --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_alarm.h @@ -0,0 +1,101 @@ +#ifndef __ALT_PRIV_ALARM_H__ +#define __ALT_PRIV_ALARM_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_types.h" + +/* + * This header provides the internal defenitions required by the public + * interface alt_alarm.h. These variables and structures are not guaranteed to + * exist in future implementations of the HAL. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * "alt_alarm_s" is a structure type used to maintain lists of alarm callback + * functions. + */ + +struct alt_alarm_s +{ + alt_llist llist; /* linked list */ + alt_u32 time; /* time in system ticks of the callback */ + alt_u32 (*callback) (void* context); /* callback function. The return + * value is the period for the next callback; where + * zero indicates that the alarm should be removed + * from the list. + */ + alt_u8 rollover; /* set when desired alarm time + current time causes + overflow, to prevent premature alarm */ + void* context; /* Argument for the callback */ +}; + +/* + * "_alt_tick_rate" is a global variable used to store the system clock rate + * in ticks per second. This is initialised to zero, which coresponds to there + * being no system clock available. + * + * It is then set to it's final value by the system clock driver through a call + * to alt_sysclk_init(). + */ + +extern alt_u32 _alt_tick_rate; + +/* + * "_alt_nticks" is a global variable which records the elapsed number of + * system clock ticks since the last call to settimeofday() or since reset if + * settimeofday() has not been called. + */ + +extern volatile alt_u32 _alt_nticks; + +/* The list of registered alarms. */ + +extern alt_llist alt_alarm_list; + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_PRIV_ALARM_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_busy_sleep.h b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_busy_sleep.h new file mode 100644 index 0000000..a165e93 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_busy_sleep.h @@ -0,0 +1,35 @@ +#ifndef __ALT_BUSY_SLEEP_H +#define __ALT_BUSY_SLEEP_H + +/* + * Copyright (c) 2003 Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * The function alt_busy_sleep provides a busy loop implementation of usleep. + * This is used to provide usleep for the standalone HAL, or when the timer is + * unavailable in uC/OS-II. + */ + +extern unsigned int alt_busy_sleep (unsigned int us); + +#endif /* __ALT_BUSY_SLEEP_H */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_dev_llist.h b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_dev_llist.h new file mode 100644 index 0000000..0ab7a28 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_dev_llist.h @@ -0,0 +1,77 @@ +#ifndef __ALT_DEV_LLIST_H__ +#define __ALT_DEV_LLIST_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "sys/alt_llist.h" +#include "alt_types.h" + +/* + * This header provides the internal defenitions required to control file + * access. These variables and functions are not guaranteed to exist in + * future implementations of the HAL. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The alt_dev_llist is an internal structure used to form a common base + * class for all device types. The use of this structure allows common code + * to be used to manipulate the various device lists. + */ + +typedef struct { + alt_llist llist; + const char* name; +} alt_dev_llist; + +/* + * + */ + +extern int alt_dev_llist_insert (alt_dev_llist* dev, alt_llist* list); + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_DEV_LLIST_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_exception_handler_registry.h b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_exception_handler_registry.h new file mode 100644 index 0000000..4502ea7 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_exception_handler_registry.h @@ -0,0 +1,39 @@ +#ifndef __ALT_EXCEPTION_HANDLER_REGISTRY_H__ +#define __ALT_EXCEPTION_HANDLER_REGISTRY_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "sys/alt_exceptions.h" + +/* Function pointer to exception callback routine */ +extern alt_exception_result (*alt_instruction_exception_handler) + (alt_exception_cause, alt_u32, alt_u32); + +#endif /* __ALT_EXCEPTION_HANDLER_REGISTRY_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_file.h b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_file.h new file mode 100644 index 0000000..94007a6 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_file.h @@ -0,0 +1,179 @@ +#ifndef __ALT_FILE_H__ +#define __ALT_FILE_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "sys/alt_dev.h" +#include "sys/alt_llist.h" +#include "os/alt_sem.h" + +#include "alt_types.h" + +/* + * This header provides the internal defenitions required to control file + * access. These variables and functions are not guaranteed to exist in + * future implementations of the HAL. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The function alt_find_dev() is used to search the device list "list" to + * locate a device named "name". If a match is found, then a pointer to the + * device is returned, otherwise NULL is returned. + */ + +extern alt_dev* alt_find_dev (const char* name, alt_llist* list); + +/* + * alt_find_file() is used to search the list of registered file systems to + * find the filesystem that the file named "name" belongs to. If a match is + * found, then a pointer to the filesystems alt_dev structure is returned, + * otherwise NULL is returned. + * + * Note that a match does not indicate that the file exists, only that a + * filesystem exists that is registered for a partition that could contain + * the file. The filesystems open() function would need to be called in order + * to determine if the file exists. + */ + +extern alt_dev* alt_find_file (const char* name); + +/* + * alt_get_fd() is used to allocate a file descriptor for the device or + * filesystem "dev". A negative return value indicates an error, otherwise the + * return value is the index of the file descriptor within the file descriptor + * pool. + */ + +extern int alt_get_fd (alt_dev* dev); + +/* + * alt_release_fd() is called to free the file descriptor with index "fd". + */ + +extern void alt_release_fd (int fd); + +/* + * alt_fd_lock() is called by ioctl() to mark the file descriptor "fd" as + * being open for exclusive access. Subsequent calls to open() for the device + * associated with "fd" will fail. A device is unlocked by either calling + * close() for "fd", or by an alternate call to ioctl() (see ioctl.c for + * details). + */ + +extern int alt_fd_lock (alt_fd* fd); + +/* + * alt_fd_unlock() is called by ioctl() to unlock a descriptor previously + * locked by a call to alt_fd_lock(). + */ + +extern int alt_fd_unlock (alt_fd* fd); + +/* + * "alt_fd_list" is the pool of file descriptors. + */ + +extern alt_fd alt_fd_list[]; + +/* + * flags used by alt_fd. + * + * ALT_FD_EXCL is used to mark a file descriptor as locked for exclusive + * access, i.e. further calls to open() for the associated device should + * fail. + * + * ALT_FD_DEV marks a dile descriptor as belonging to a device as oposed to a + * filesystem. + */ + +#define ALT_FD_EXCL 0x80000000 +#define ALT_FD_DEV 0x40000000 + +#define ALT_FD_FLAGS_MASK (ALT_FD_EXCL | ALT_FD_DEV) + +/* + * "alt_dev_list" is the head of the linked list of registered devices. + */ + +extern alt_llist alt_dev_list; + +/* + * "alt_fs_list" is the head of the linked list of registered filesystems. + */ + +extern alt_llist alt_fs_list; + +/* + * "alt_fd_list_lock" is a semaphore used to ensure that access to the pool + * of file descriptors is thread safe. + */ + +ALT_EXTERN_SEM(alt_fd_list_lock) + +/* + * "alt_max_fd" is a 'high water mark'. It indicates the highest file + * descriptor allocated. Use of this can save searching the entire pool + * for active file descriptors, which helps avoid contention on access + * to the file descriptor pool. + */ + +extern alt_32 alt_max_fd; + +/* + * alt_io_redirect() is called at startup to redirect stdout, stdin, and + * stderr to the devices named in the input arguments. By default these streams + * are directed at /dev/null, and are then redirected using this function once + * all of the devices have been registered within the system. + */ + +extern void alt_io_redirect(const char* stdout_dev, + const char* stdin_dev, + const char* stderr_dev); + + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_FILE_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_iic_isr_register.h b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_iic_isr_register.h new file mode 100644 index 0000000..6c53c86 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_iic_isr_register.h @@ -0,0 +1,39 @@ +#ifndef __ALT_IIC_ISR_REGISTER_H_ +#define __ALT_IIC_ISR_REGISTER_H_ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "alt_types.h" +#include "sys/alt_irq.h" + +extern int alt_iic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, + void *isr_context, void *flags); + +#endif /* __ALT_IIC_ISR_REGISTER_H_ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_irq_table.h b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_irq_table.h new file mode 100644 index 0000000..5b4a787 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_irq_table.h @@ -0,0 +1,59 @@ +#ifndef __ALT_IRQ_TABLE_H__ +#define __ALT_IRQ_TABLE_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * Definition of a table describing each interrupt handler. The index into + * the array is the interrupt id associated with the handler. + * + * When an interrupt occurs, the associated handler is called with + * the argument stored in the context member. + * + * The table is physically created in alt_irq_handler.c + */ +extern struct ALT_IRQ_HANDLER +{ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + void (*handler)(void*); +#else + void (*handler)(void*, alt_u32); +#endif + void *context; +} alt_irq[ALT_NIRQ]; + +#endif diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_legacy_irq.h b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_legacy_irq.h new file mode 100644 index 0000000..0e19af2 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_legacy_irq.h @@ -0,0 +1,158 @@ +#ifndef __ALT_LEGACY_IRQ_H__ +#define __ALT_LEGACY_IRQ_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This file provides prototypes and inline implementations of certain routines + * used by the legacy interrupt API. Do not include this in your driver or + * application source files, use "sys/alt_irq.h" instead to access the proper + * public API. + */ + +#include +#include "system.h" + +#ifndef NIOS2_EIC_PRESENT + +#include "nios2.h" +#include "alt_types.h" + +#include "sys/alt_irq.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * alt_irq_register() can be used to register an interrupt handler. If the + * function is succesful, then the requested interrupt will be enabled upon + * return. + */ +extern int alt_irq_register (alt_u32 id, + void* context, + alt_isr_func handler); + +/* + * alt_irq_disable() disables the individual interrupt indicated by "id". + */ +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_disable (alt_u32 id) +{ + alt_irq_context status; + extern volatile alt_u32 alt_irq_active; + + status = alt_irq_disable_all (); + + alt_irq_active &= ~(1 << id); + NIOS2_WRITE_IENABLE (alt_irq_active); + + alt_irq_enable_all(status); + + return 0; +} + +/* + * alt_irq_enable() enables the individual interrupt indicated by "id". + */ +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_enable (alt_u32 id) +{ + alt_irq_context status; + extern volatile alt_u32 alt_irq_active; + + status = alt_irq_disable_all (); + + alt_irq_active |= (1 << id); + NIOS2_WRITE_IENABLE (alt_irq_active); + + alt_irq_enable_all(status); + + return 0; +} + +#ifndef ALT_EXCEPTION_STACK +/* + * alt_irq_initerruptable() should only be called from within an ISR. It is used + * to allow higer priority interrupts to interrupt the current ISR. The input + * argument, "priority", is the priority, i.e. interrupt number of the current + * interrupt. + * + * If this function is called, then the ISR is required to make a call to + * alt_irq_non_interruptible() before returning. The input argument to + * alt_irq_non_interruptible() is the return value from alt_irq_interruptible(). + * + * Care should be taken when using this pair of functions, since they increasing + * the system overhead associated with interrupt handling. + * + * If you are using an exception stack then nested interrupts won't work, so + * these functions are not available in that case. + */ +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_interruptible (alt_u32 priority) +{ + extern volatile alt_u32 alt_priority_mask; + extern volatile alt_u32 alt_irq_active; + + alt_u32 old_priority; + + old_priority = alt_priority_mask; + alt_priority_mask = (1 << priority) - 1; + + NIOS2_WRITE_IENABLE (alt_irq_active & alt_priority_mask); + + NIOS2_WRITE_STATUS (1); + + return old_priority; +} + +/* + * See Comments above for alt_irq_interruptible() for an explanation of the use of this + * function. + */ +static ALT_INLINE void ALT_ALWAYS_INLINE alt_irq_non_interruptible (alt_u32 mask) +{ + extern volatile alt_u32 alt_priority_mask; + extern volatile alt_u32 alt_irq_active; + + NIOS2_WRITE_STATUS (0); + + alt_priority_mask = mask; + + NIOS2_WRITE_IENABLE (mask & alt_irq_active); +} +#endif /* ALT_EXCEPTION_STACK */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* NIOS2_EIC_PRESENT */ + +#endif /* __ALT_LEGACY_IRQ_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_no_error.h b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_no_error.h new file mode 100644 index 0000000..06a036c --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_no_error.h @@ -0,0 +1,77 @@ +#ifndef __ALT_NO_ERROR_H__ +#define __ALT_NO_ERROR_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * alt_no_error() is a dummy function used by alt_sem.h and alt_flag.h. It + * substitutes for functions that have a return code by creating a function + * that always returns zero. + * + * This may seem a little obscure, but what happens is that the compiler can + * then optomise away the call to this function, and any code written which + * handles the error path (i.e. non zero return values). + * + * This allows code to be written which correctly use the uC/OS-II semaphore + * and flag utilities, without the use of those utilities impacting on + * excutables built for a single threaded HAL environment. + * + * This function is considered to be part of the internal implementation of + * the HAL, and should not be called directly by application code or device + * drivers. It is not guaranteed to be preserved in future versions of the + * HAL. + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_no_error (void) +{ + return 0; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_NO_ERROR_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/priv/nios2_gmon_data.h b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/nios2_gmon_data.h new file mode 100644 index 0000000..4bc058d --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/nios2_gmon_data.h @@ -0,0 +1,47 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#ifndef NIOS2_GMON_DATA_H +#define NIOS2_GMON_DATA_H + +#define GMON_DATA_SIG 0 +#define GMON_DATA_WORDS 1 +#define GMON_DATA_PROFILE_DATA 2 +#define GMON_DATA_PROFILE_LOWPC 3 +#define GMON_DATA_PROFILE_HIGHPC 4 +#define GMON_DATA_PROFILE_BUCKET 5 +#define GMON_DATA_PROFILE_RATE 6 +#define GMON_DATA_MCOUNT_START 7 +#define GMON_DATA_MCOUNT_LIMIT 8 + +#define GMON_DATA_SIZE 9 + +extern unsigned int alt_gmon_data[GMON_DATA_SIZE]; + +#endif diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_alarm.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_alarm.h new file mode 100644 index 0000000..9093080 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_alarm.h @@ -0,0 +1,126 @@ +#ifndef __ALT_ALARM_H__ +#define __ALT_ALARM_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_llist.h" +#include "alt_types.h" + +#include "priv/alt_alarm.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * "alt_alarm" is a structure type used by applications to register an alarm + * callback function. An instance of this type must be passed as an input + * argument to alt_alarm_start(). The user is not responsible for initialising + * the contents of the instance. This is done by alt_alarm_start(). + */ + +typedef struct alt_alarm_s alt_alarm; + +/* + * alt_alarm_start() can be called by an application/driver in order to register + * a function for periodic callback at the system clock frequency. Be aware that + * this callback is likely to occur in interrupt context. + */ + +extern int alt_alarm_start (alt_alarm* the_alarm, + alt_u32 nticks, + alt_u32 (*callback) (void* context), + void* context); + +/* + * alt_alarm_stop() is used to unregister a callback. Alternatively the callback + * can return zero to unregister. + */ + +extern void alt_alarm_stop (alt_alarm* the_alarm); + +/* + * Obtain the system clock rate in ticks/s. + */ + +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_ticks_per_second (void) +{ + return _alt_tick_rate; +} + +/* + * alt_sysclk_init() is intended to be only used by the system clock driver + * in order to initialise the value of the clock frequency. + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sysclk_init (alt_u32 nticks) +{ + if (! _alt_tick_rate) + { + _alt_tick_rate = nticks; + return 0; + } + else + { + return -1; + } +} + +/* + * alt_nticks() returns the elapsed number of system clock ticks since reset. + */ + +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_nticks (void) +{ + return _alt_nticks; +} + +/* + * alt_tick() should only be called by the system clock driver. This is used + * to notify the system that the system timer period has expired. + */ + +extern void alt_tick (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_ALARM_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_cache.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_cache.h new file mode 100644 index 0000000..44d976c --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_cache.h @@ -0,0 +1,117 @@ +#ifndef __ALT_CACHE_H__ +#define __ALT_CACHE_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003, 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include + +#include "alt_types.h" + +/* + * alt_cache.h defines the processor specific functions for manipulating the + * cache. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * alt_icache_flush() is called to flush the instruction cache for a memory + * region of length "len" bytes, starting at address "start". + */ + +extern void alt_icache_flush (void* start, alt_u32 len); + +/* + * alt_dcache_flush() is called to flush the data cache for a memory + * region of length "len" bytes, starting at address "start". + * Any dirty lines in the data cache are written back to memory. + */ + +extern void alt_dcache_flush (void* start, alt_u32 len); + +/* + * alt_dcache_flush() is called to flush the data cache for a memory + * region of length "len" bytes, starting at address "start". + * Any dirty lines in the data cache are NOT written back to memory. + */ + +extern void alt_dcache_flush_no_writeback (void* start, alt_u32 len); + +/* + * Flush the entire instruction cache. + */ + +extern void alt_icache_flush_all (void); + +/* + * Flush the entire data cache. + */ + +extern void alt_dcache_flush_all (void); + +/* + * Allocate a block of uncached memory. + */ + +extern volatile void* alt_uncached_malloc (size_t size); + +/* + * Free a block of uncached memory. + */ + +extern void alt_uncached_free (volatile void* ptr); + +/* + * Convert a pointer to a block of cached memory, into a block of + * uncached memory. + */ + +extern volatile void* alt_remap_uncached (void* ptr, alt_u32 len); + +/* + * Convert a pointer to a block of uncached memory, into a block of + * cached memory. + */ + +extern void* alt_remap_cached (volatile void* ptr, alt_u32 len); + +/* + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_CACHE_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_debug.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_debug.h new file mode 100644 index 0000000..af509d8 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_debug.h @@ -0,0 +1,45 @@ +#ifndef __ALT_DEBUG_H__ +#define __ALT_DEBUG_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * The ALT_DEVUG_ASSERT macro can be used to generate a debugger break + * from within software. The break is generated if "condition" evaluates to + * false. + */ + +#define ALT_DEBUG_ASSERT(condition) if (!condition) \ +{ \ + __asm__ volatile ("break"); \ +} + +#endif /* __ALT_DEBUG_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_dev.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_dev.h new file mode 100644 index 0000000..d96327e --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_dev.h @@ -0,0 +1,115 @@ +#ifndef __ALT_DEV_H__ +#define __ALT_DEV_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "system.h" +#include "sys/alt_llist.h" +#include "priv/alt_dev_llist.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The value ALT_IRQ_NOT_CONNECTED is used to represent an unconnected + * interrupt line. It cannot evaluate to a valid interrupt number. + */ + +#define ALT_IRQ_NOT_CONNECTED (-1) + +typedef struct alt_dev_s alt_dev; + +struct stat; + +/* + * The file descriptor structure definition. + */ + +typedef struct alt_fd_s +{ + alt_dev* dev; + alt_u8* priv; + int fd_flags; +} alt_fd; + +/* + * The device structure definition. + */ + +struct alt_dev_s { + alt_llist llist; /* for internal use */ + const char* name; + int (*open) (alt_fd* fd, const char* name, int flags, int mode); + int (*close) (alt_fd* fd); + int (*read) (alt_fd* fd, char* ptr, int len); + int (*write) (alt_fd* fd, const char* ptr, int len); + int (*lseek) (alt_fd* fd, int ptr, int dir); + int (*fstat) (alt_fd* fd, struct stat* buf); + int (*ioctl) (alt_fd* fd, int req, void* arg); +}; + +/* + * Functions used to register device for access through the C standard + * library. + * + * The only difference between alt_dev_reg() and alt_fs_reg() is the + * interpretation that open() places on the device name. In the case of + * alt_dev_reg the device is assumed to be a particular character device, + * and so there must be an exact match in the name for open to succeed. + * In the case of alt_fs_reg() the name of the device is treated as the + * mount point for a directory, and so any call to open() where the name + * is the root of the device filename will succeed. + */ + +extern int alt_fs_reg (alt_dev* dev); + +static ALT_INLINE int alt_dev_reg (alt_dev* dev) +{ + extern alt_llist alt_dev_list; + + return alt_dev_llist_insert ((alt_dev_llist*) dev, &alt_dev_list); +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_DEV_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_dma.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_dma.h new file mode 100644 index 0000000..88dcda0 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_dma.h @@ -0,0 +1,226 @@ +#ifndef __ALT_DMA_H__ +#define __ALT_DMA_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "sys/alt_dma_dev.h" +#include "alt_types.h" + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * This header contains the application side interface for accessing DMA + * resources. See alt_dma_dev.h for the dma device driver interface. + * + * The interface model treats a DMA transaction as being composed of two + * halves (read and write). + * + * The application can supply data for transmit using an "alt_dma_txchan" + * descriptor. Alternatively an "alt_dma_rxchan" descriptor can be used to + * receive data. + */ + +/* + * alt_dma_txchan_open() is used to obtain an "alt_dma_txchan" descriptor for + * a DMA transmit device. The name is the name of the associated physical + * device (e.g. "/dev/dma_0"). + * + * The return value will be NULL on failure, and non-NULL otherwise. + */ + +extern alt_dma_txchan alt_dma_txchan_open (const char* name); + +/* + * alt_dma_txchan_close() is provided so that an application can notify the + * system that it has finished with a given DMA transmit channel. This is only + * provided for completness. + */ + +static ALT_INLINE int alt_dma_txchan_close (alt_dma_txchan dma) +{ + return 0; +} + +/* + * alt_dma_txchan_send() posts a transmit request to a DMA transmit channel. + * The input arguments are: + * + * dma: the channel to use. + * from: a pointer to the start of the data to send. + * length: the length of the data to send in bytes. + * done: callback function that will be called once the data has been sent. + * handle: opaque value passed to "done". + * + * The return value will be negative if the request cannot be posted, and + * zero otherwise. + */ + +static ALT_INLINE int alt_dma_txchan_send (alt_dma_txchan dma, + const void* from, + alt_u32 length, + alt_txchan_done* done, + void* handle) +{ + return dma ? dma->dma_send (dma, + from, + length, + done, + handle) : -ENODEV; +} + +/* + * alt_dma_txchan_space() returns the number of tranmit requests that can be + * posted to the specified DMA transmit channel. + * + * A negative value indicates that the value could not be determined. + */ + +static ALT_INLINE int alt_dma_txchan_space (alt_dma_txchan dma) +{ + return dma ? dma->space (dma) : -ENODEV; +} + +/* + * alt_dma_txchan_ioctl() can be used to perform device specific I/O + * operations on the indicated DMA transmit channel. For example some drivers + * support options to control the width of the transfer operations. See + * alt_dma_dev.h for the list of generic requests. + * + * A negative return value indicates failure, otherwise the interpretation + * of the return value is request specific. + */ + +static ALT_INLINE int alt_dma_txchan_ioctl (alt_dma_txchan dma, + int req, + void* arg) +{ + return dma ? dma->ioctl (dma, req, arg) : -ENODEV; +} + +/* + * alt_dma_rxchan_open() is used to obtain an "alt_dma_rxchan" descriptor for + * a DMA receive channel. The name is the name of the associated physical + * device (e.g. "/dev/dma_0"). + * + * The return value will be NULL on failure, and non-NULL otherwise. + */ + +extern alt_dma_rxchan alt_dma_rxchan_open (const char* dev); + +/* + * alt_dma_rxchan_close() is provided so that an application can notify the + * system that it has finished with a given DMA receive channel. This is only + * provided for completness. + */ + +static ALT_INLINE int alt_dma_rxchan_close (alt_dma_rxchan dma) +{ + return 0; +} + +/* + * + */ + +/* + * alt_dma_rxchan_prepare() posts a receive request to a DMA receive channel. + * + * The input arguments are: + * + * dma: the channel to use. + * data: a pointer to the location that data is to be received to. + * len: the maximum length of the data to receive. + * done: callback function that will be called once the data has been + * received. + * handle: opaque value passed to "done". + * + * The return value will be negative if the request cannot be posted, and + * zero otherwise. + */ + +static ALT_INLINE int alt_dma_rxchan_prepare (alt_dma_rxchan dma, + void* data, + alt_u32 len, + alt_rxchan_done* done, + void* handle) +{ + return dma ? dma->prepare (dma, data, len, done, handle) : -ENODEV; +} + +/* + * alt_dma_rxchan_ioctl() can be used to perform device specific I/O + * operations on the indicated DMA receive channel. For example some drivers + * support options to control the width of the transfer operations. See + * alt_dma_dev.h for the list of generic requests. + * + * A negative return value indicates failure, otherwise the interpretation + * of the return value is request specific. + */ + +static ALT_INLINE int alt_dma_rxchan_ioctl (alt_dma_rxchan dma, + int req, + void* arg) +{ + return dma ? dma->ioctl (dma, req, arg) : -ENODEV; +} + +/* + * alt_dma_rxchan_depth() returns the depth of the receive FIFO used to store + * receive requests. + */ + +static ALT_INLINE alt_u32 alt_dma_rxchan_depth(alt_dma_rxchan dma) +{ + return dma->depth; +} + +/* + * + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_DMA_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_dma_dev.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_dma_dev.h new file mode 100644 index 0000000..65063bd --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_dma_dev.h @@ -0,0 +1,200 @@ +#ifndef __ALT_DMA_DEV_H__ +#define __ALT_DMA_DEV_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "priv/alt_dev_llist.h" + +#include "alt_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * This header contains the device driver interface for accessing DMA + * resources. See alt_dma.h for the DMA application side interface. + * + * The interface model treats a DMA transaction as being composed of two + * halves (read and write). + * + * An "alt_dma_txchan_dev" is used to describe the device associated with a + * DMA transmit channel. An "alt_dma_rxchan_dev" is used to describe the + * device associated with a DMA receive channel. + */ + +/* + * List of generic ioctl requests that may be supported by a DMA device. + * + * ALT_DMA_RX_ONLY_ON: This causes a DMA channel to operate in a mode + * where only the receiver is under software control. + * The other side reads continously from a single + * location. The address to read is the argument to + * this request. + * ALT_DMA_RX_ONLY_OFF: Return to the default mode where both the receive + * and transmit sides of the DMA can be under software + * control. + * ALT_DMA_TX_ONLY_ON: This causes a DMA channel to operate in a mode + * where only the transmitter is under software control. + * The other side writes continously to a single + * location. The address to write to is the argument to + * this request. + * ALT_DMA_TX_ONLY_OFF: Return to the default mode where both the receive + * and transmit sides of the DMA can be under software + * control. + * ALT_DMA_SET_MODE_8: Transfer data in units of 8 bits. + * ALT_DMA_SET_MODE_16: Transfer data in units of 16 bits. + * ALT_DMA_SET_MODE_32: Transfer data in units of 32 bits. + * ALT_DMA_SET_MODE_64: Transfer data in units of 64 bits. + * ALT_DMA_SET_MODE_128: Transfer data in units of 128 bits. + * ALT_DMA_GET_MODE: Get the current transfer mode. + * + * The use of the macros: ALT_DMA_TX_STREAM_ON, ALT_DMA_TX_STREAM_OFF + * ALT_DMA_RX_STREAM_OFF and ALT_DMA_RX_STREAM_ON are depreciated. You should + * instead use the macros: ALT_DMA_RX_ONLY_ON, ALT_DMA_RX_ONLY_OFF, + * ALT_DMA_TX_ONLY_ON and ALT_DMA_TX_ONLY_OFF. + */ + +#define ALT_DMA_TX_STREAM_ON (0x1) +#define ALT_DMA_TX_STREAM_OFF (0x2) +#define ALT_DMA_RX_STREAM_ON (0x3) +#define ALT_DMA_RX_STREAM_OFF (0x4) +#define ALT_DMA_SET_MODE_8 (0x5) +#define ALT_DMA_SET_MODE_16 (0x6) +#define ALT_DMA_SET_MODE_32 (0x7) +#define ALT_DMA_SET_MODE_64 (0x8) +#define ALT_DMA_SET_MODE_128 (0x9) +#define ALT_DMA_GET_MODE (0xa) + +#define ALT_DMA_RX_ONLY_ON ALT_DMA_TX_STREAM_ON +#define ALT_DMA_RX_ONLY_OFF ALT_DMA_TX_STREAM_OFF +#define ALT_DMA_TX_ONLY_ON ALT_DMA_RX_STREAM_ON +#define ALT_DMA_TX_ONLY_OFF ALT_DMA_RX_STREAM_OFF + +/* + * + */ + +typedef struct alt_dma_txchan_dev_s alt_dma_txchan_dev; +typedef struct alt_dma_rxchan_dev_s alt_dma_rxchan_dev; + +typedef alt_dma_txchan_dev* alt_dma_txchan; +typedef alt_dma_rxchan_dev* alt_dma_rxchan; + +typedef void (alt_txchan_done)(void* handle); +typedef void (alt_rxchan_done)(void* handle, void* data); + +/* + * devices that provide a DMA transmit channel are required to provide an + * instance of the "alt_dma_txchan_dev" structure. + */ + +struct alt_dma_txchan_dev_s { + alt_llist llist; /* for internal use */ + const char* name; /* name of the device instance + * (e.g. "/dev/dma_0"). + */ + int (*space) (alt_dma_txchan dma); /* returns the maximum number of + * transmit requests that can be posted + */ + int (*dma_send) (alt_dma_txchan dma, + const void* from, + alt_u32 len, + alt_txchan_done* done, + void* handle); /* post a transmit request */ + int (*ioctl) (alt_dma_txchan dma, int req, void* arg); /* perform device + * specific I/O control. + */ +}; + +/* + * devices that provide a DMA receive channel are required to provide an + * instance of the "alt_dma_rxchan_dev" structure. + */ + +struct alt_dma_rxchan_dev_s { + alt_llist list; /* for internal use */ + const char* name; /* name of the device instance + * (e.g. "/dev/dma_0"). + */ + alt_u32 depth; /* maximum number of receive requests that + * can be posted. + */ + int (*prepare) (alt_dma_rxchan dma, + void* data, + alt_u32 len, + alt_rxchan_done* done, + void* handle); /* post a receive request */ + int (*ioctl) (alt_dma_rxchan dma, int req, void* arg); /* perform device + * specific I/O control. + */ +}; + +/* + * Register a DMA transmit channel with the system. + */ + +static ALT_INLINE int alt_dma_txchan_reg (alt_dma_txchan_dev* dev) +{ + extern alt_llist alt_dma_txchan_list; + + return alt_dev_llist_insert((alt_dev_llist*) dev, &alt_dma_txchan_list); +} + +/* + * Register a DMA receive channel with the system. + */ + +static ALT_INLINE int alt_dma_rxchan_reg (alt_dma_rxchan_dev* dev) +{ + extern alt_llist alt_dma_rxchan_list; + + return alt_dev_llist_insert((alt_dev_llist*) dev, &alt_dma_rxchan_list); +} + +/* + * + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_DMA_DEV_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_driver.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_driver.h new file mode 100644 index 0000000..ca7aea1 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_driver.h @@ -0,0 +1,168 @@ +#ifndef __ALT_DRIVER_H__ +#define __ALT_DRIVER_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* + * Macros used to access a driver without HAL file descriptors. + */ + +/* + * ALT_MODULE_CLASS + * + * This macro returns the module class name for the specified module instance. + * It uses information in the system.h file. + * Neither the instance name or class name are quoted (so that they can + * be used with other pre-processor macros). + * + * Example: + * Assume the design has an instance of an altera_avalon_uart called uart1. + * Calling ALT_MODULE_CLASS(uart1) returns altera_avalon_uart. + */ + +#define ALT_MODULE_CLASS(instance) ALT_MODULE_CLASS_ ## instance + + +/* + * ALT_DRIVER_FUNC_NAME + * + * --> instance Instance name. + * --> func Function name. + * + * This macro returns the device driver function name of the specified + * module instance for the specified function name. + * + * Example: + * Assume the design has an instance of an altera_avalon_uart called uart1. + * Calling ALT_DRIVER_FUNC_NAME(uart1, write) returns + * altera_avalon_uart_write. + */ + +#define ALT_DRIVER_FUNC_NAME(instance, func) \ + ALT_DRIVER_FUNC_NAME1(ALT_MODULE_CLASS(instance), func) +#define ALT_DRIVER_FUNC_NAME1(module_class, func) \ + ALT_DRIVER_FUNC_NAME2(module_class, func) +#define ALT_DRIVER_FUNC_NAME2(module_class, func) \ + module_class ## _ ## func + +/* + * ALT_DRIVER_STATE_STRUCT + * + * --> instance Instance name. + * + * This macro returns the device driver state type name of the specified + * module instance. + * + * Example: + * Assume the design has an instance of an altera_avalon_uart called uart1. + * Calling ALT_DRIVER_STATE_STRUCT(uart1) returns: + * struct altera_avalon_uart_state_s + * + * Note that the ALT_DRIVER_FUNC_NAME macro is used even though "state" isn't + * really a function but it does match the required naming convention. + */ +#define ALT_DRIVER_STATE_STRUCT(instance) \ + struct ALT_DRIVER_FUNC_NAME(instance, state_s) + +/* + * ALT_DRIVER_STATE + * + * --> instance Instance name. + * + * This macro returns the device driver state name of the specified + * module instance. + * + * Example: + * Assume the design has an instance of an altera_avalon_uart called uart1. + * Calling ALT_DRIVER_STATE(uart1) returns uart1. + */ +#define ALT_DRIVER_STATE(instance) instance + +/* + * ALT_DRIVER_WRITE + * + * --> instance Instance name. + * --> buffer Write buffer. + * --> len Length of write buffer data. + * --> flags Control flags (e.g. O_NONBLOCK) + * + * This macro calls the "write" function of the specified driver instance. + */ + +#define ALT_DRIVER_WRITE_EXTERNS(instance) \ + extern ALT_DRIVER_STATE_STRUCT(instance) ALT_DRIVER_STATE(instance); \ + extern int ALT_DRIVER_FUNC_NAME(instance, write) \ + (ALT_DRIVER_STATE_STRUCT(instance) *, const char *, int, int); + +#define ALT_DRIVER_WRITE(instance, buffer, len, flags) \ + ALT_DRIVER_FUNC_NAME(instance, write)(&ALT_DRIVER_STATE(instance), buffer, len, flags) + + +/* + * ALT_DRIVER_READ + * + * --> instance Instance name. + * <-- buffer Read buffer. + * --> len Length of read buffer. + * --> flags Control flags (e.g. O_NONBLOCK) + * + * This macro calls the "read" function of the specified driver instance. + */ + +#define ALT_DRIVER_READ_EXTERNS(instance) \ + extern ALT_DRIVER_STATE_STRUCT(instance) ALT_DRIVER_STATE(instance); \ + extern int ALT_DRIVER_FUNC_NAME(instance, read) \ + (ALT_DRIVER_STATE_STRUCT(instance) *, const char *, int, int); + +#define ALT_DRIVER_READ(instance, buffer, len, flags) \ + ALT_DRIVER_FUNC_NAME(instance, read)(&ALT_DRIVER_STATE(instance), buffer, len, flags) + +/* + * ALT_DRIVER_IOCTL + * + * --> instance Instance name. + * --> req ioctl request (e.g. TIOCSTIMEOUT) + * --> arg Optional argument (void*) + * + * This macro calls the "ioctl" function of the specified driver instance + */ + +#define ALT_DRIVER_IOCTL_EXTERNS(instance) \ + extern ALT_DRIVER_STATE_STRUCT(instance) ALT_DRIVER_STATE(instance); \ + extern int ALT_DRIVER_FUNC_NAME(instance, ioctl) \ + (ALT_DRIVER_STATE_STRUCT(instance) *, int, void*); + +#define ALT_DRIVER_IOCTL(instance, req, arg) \ + ALT_DRIVER_FUNC_NAME(instance, ioctl)(&ALT_DRIVER_STATE(instance), req, arg) + +#endif /* __ALT_DRIVER_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_errno.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_errno.h new file mode 100644 index 0000000..23e3096 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_errno.h @@ -0,0 +1,87 @@ +#ifndef __ALT_ERRNO_H__ +#define __ALT_ERRNO_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * errno is defined in so that it uses the thread local version + * stored in the location pointed to by "_impure_ptr". This means that the + * accesses to errno within the HAL library can cause the entirety of + * of the structure pointed to by "_impure_ptr" to be added to the + * users application. This can be undesirable in very small footprint systems. + * + * To avoid this happening, the HAL uses the macro ALT_ERRNO, defined below, + * to access errno, rather than accessing it directly. This macro will only + * use the thread local version if some other code has already caused it to be + * included into the system, otherwise it will use the global errno value. + * + * This causes a slight increases in code size where errno is accessed, but + * can lead to significant overall benefits in very small systems. The + * increase is inconsequential when compared to the size of the structure + * pointed to by _impure_ptr. + * + * Note that this macro accesses __errno() using an externally declared + * function pointer (alt_errno). This is done so that the function call uses the + * subroutine call instruction via a register rather than an immediate address. + * This is important in the case that the code has been linked for a high + * address, but __errno() is not being used. In this case the weak linkage + * would have resulted in the instruction: "call 0" which would fail to link. + */ + +extern int* (*alt_errno) (void); + +/* Must define this so that values such as EBADFD are defined in errno.h. */ +#define __LINUX_ERRNO_EXTENSIONS__ + +#include + +#include "alt_types.h" + +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + return ((alt_errno) ? alt_errno() : &errno); +} + +#define ALT_ERRNO *alt_get_errno() + +#endif /* __ALT_ERRNO_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_exceptions.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_exceptions.h new file mode 100644 index 0000000..9c938b9 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_exceptions.h @@ -0,0 +1,166 @@ +#ifndef __ALT_EXCEPTIONS_H__ +#define __ALT_EXCEPTIONS_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "alt_types.h" +#include "system.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * This file defines instruction-generated exception handling and registry + * API, exception type enumeration, and handler return value enumeration for + * Nios II. + */ + +/* + * The following enumeration describes the value in the CPU EXCEPTION + * register CAUSE bit field. + */ +enum alt_exception_cause_e { + /* + * This value is passed to an exception handler's cause argument if + * "extra exceptions" information (EXECPTION) register is not + * present in the processor hardware configuration. + */ + NIOS2_EXCEPTION_CAUSE_NOT_PRESENT = -1, + + /* + * Real values + */ + NIOS2_EXCEPTION_RESET = 0, + NIOS2_EXCEPTION_CPU_ONLY_RESET_REQUEST = 1, + NIOS2_EXCEPTION_INTERRUPT = 2, + NIOS2_EXCEPTION_TRAP_INST = 3, + NIOS2_EXCEPTION_UNIMPLEMENTED_INST = 4, + NIOS2_EXCEPTION_ILLEGAL_INST = 5, + NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR = 6, + NIOS2_EXCEPTION_MISALIGNED_TARGET_PC = 7, + NIOS2_EXCEPTION_DIVISION_ERROR = 8, + NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST_ADDR = 9, + NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST = 10, + NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR = 11, + NIOS2_EXCEPTION_TLB_MISS = 12, + NIOS2_EXCEPTION_TLB_EXECUTE_PERM_VIOLATION = 13, + NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION = 14, + NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION = 15, + NIOS2_EXCEPTION_MPU_INST_REGION_VIOLATION = 16, + NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION = 17, + NIOS2_EXCEPTION_ECC_TLB_ERR = 18, + NIOS2_EXCEPTION_ECC_FETCH_ERR = 19, + NIOS2_EXCEPTION_ECC_REGISTER_FILE_ERR = 20, + NIOS2_EXCEPTION_ECC_DATA_ERR = 21, + NIOS2_EXCEPTION_ECC_DATA_CACHE_WRITEBACK_ERR = 22 +}; +typedef enum alt_exception_cause_e alt_exception_cause; + +/* + * These define valid return values for a user-defined instruction-generated + * exception handler. The handler should return one of these to indicate + * whether to re-issue the instruction that triggered the exception, or to + * skip it. + */ +enum alt_exception_result_e { + NIOS2_EXCEPTION_RETURN_REISSUE_INST = 0, + NIOS2_EXCEPTION_RETURN_SKIP_INST = 1 +}; +typedef enum alt_exception_result_e alt_exception_result; + +/* + * alt_instruction_exception_register() can be used to register an exception + * handler for instruction-generated exceptions that are not handled by the + * built-in exception handler (i.e. for interrupts). + * + * The registry API is optionally enabled through the "Enable + * Instruction-related Exception API" HAL BSP setting, which will + * define the macro below. + */ +#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API +void alt_instruction_exception_register ( + alt_exception_result (*exception_handler)( + alt_exception_cause cause, + alt_u32 exception_pc, + alt_u32 bad_addr) ); +#endif /*ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */ + +/* + * alt_exception_cause_generated_bad_addr() indicates whether a particular + * exception cause value was from an exception-type that generated a valid + * address in the BADADDR register. The contents of BADADDR is passed to + * a user-registered exception handler in all cases, whether valid or not. + * This routine should be called to validate the bad_addr argument to + * your exception handler. + * + * Note that this routine will return false (0) for causes + * NIOS2_EXCEPTION_TLB_MISS and NIOS2_EXCEPTION_ECC_TLB_ERR. + * You must read the TLBMISC.D field to determine if BADADDR + * is valid for these (valid if TLBMISC.D = 1). + */ +int alt_exception_cause_generated_bad_addr(alt_exception_cause cause); + +/* + * alt_ecc_fatal_exception_register() is called to register a handler to + * service likely fatal ECC error exceptions. Likely the handler will + * assume that correct execution of the running software is not possible + * and re-initialize the processor (e.g. jump to reset address). + * + * Passing null (0x0) in the handler argument will disable a previously- + * registered handler. + * + * Note that if no handler is registered, just normal exception processing + * occurs on a likely fatal ECC exception and the exception processing + * code might trigger an infinite exception loop. + * + * Note that the handler isn't a C function: it must be written in + * assembly-code because it doesn't support C language calling conventions + * and it can't return. + * + * The handler code must be carefully written to avoid triggering + * another fatal ECC exception and creating an infinite exception loop. + * The handler must avoid reading registers in case the fatal ECC + * error is a register file ECC error. + * If a data cache is present, the handler must avoid instructions that + * access the data cache in case the fatal ECC error is a data cache + * related ECC error. This includes cacheable load, cacheable store, + * non-cacheable store (because it looks in the data cache to update the + * data cache if it hits), and all data cache management instructions except + * for INITD. + */ +void alt_ecc_fatal_exception_register(alt_u32 handler); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_EXCEPTIONS_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_flash.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_flash.h new file mode 100644 index 0000000..f1ab10d --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_flash.h @@ -0,0 +1,181 @@ +#ifndef __ALT_FLASH_H__ +#define __ALT_FLASH_H__ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2015 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/****************************************************************************** +* * +* Alt_flash.h - User interface for flash code * +* * +* Use this interface to avoid being exposed to the internals of the device * +* driver architecture. If you chose to use the flash driver internal * +* structures we don't guarantee not to change them * +* * +* Author PRR * +* * +******************************************************************************/ + + + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +#include "alt_types.h" +#include "alt_flash_types.h" +#include "alt_flash_dev.h" +#include "sys/alt_cache.h" + +alt_flash_fd* alt_flash_open_dev(const char* name); +void alt_flash_close_dev(alt_flash_fd* fd ); + +/* + * alt_flash_lock + * + * Locks the range of the memory sectors, which + * protected from write and erase. + * + */ +static __inline__ int __attribute__ ((always_inline)) alt_lock_flash( + alt_flash_fd* fd, alt_u32 sectors_to_lock) +{ + return fd->lock( fd, sectors_to_lock); +} + +/* + * alt_write_flash + * + * Program a buffer into flash. + * + * This routine erases all the affected erase blocks (if necessary) + * and then programs the data. However it does not read the data out first + * and preserve and none overwritten data, because this would require very + * large buffers on the target. If you need + * that functionality use the functions below. + */ +static __inline__ int __attribute__ ((always_inline)) alt_write_flash( + alt_flash_fd* fd, + int offset, + const void* src_addr, + int length ) +{ + return fd->write( fd, offset, src_addr, length ); +} + +/* + * alt_read_flash + * + * Read a block of flash for most flashes this is just memcpy + * it's here for completeness in case we need it for some serial flash device + * + */ +static __inline__ int __attribute__ ((always_inline)) alt_read_flash( + alt_flash_fd* fd, int offset, + void* dest_addr, int length ) +{ + return fd->read( fd, offset, dest_addr, length ); +} + +/* + * alt_get_flash_info + * + * Return the information on the flash sectors. + * + */ +static __inline__ int __attribute__ ((always_inline)) alt_get_flash_info( + alt_flash_fd* fd, flash_region** info, + int* number_of_regions) +{ + return fd->get_info( fd, info, number_of_regions); +} + +/* + * alt_erase_flash_block + * + * Erase a particular erase block, pass in the offset to the start of + * the block and it's size + */ +static __inline__ int __attribute__ ((always_inline)) alt_erase_flash_block( + alt_flash_fd* fd, int offset, int length) +{ + int ret_code; + ret_code = fd->erase_block( fd, offset ); + +/* remove dcache_flush call for FB330552 + if(!ret_code) + alt_dcache_flush((alt_u8*)fd->base_addr + offset, length); +*/ + return ret_code; +} + +/* + * alt_write_flash_block + * + * Write a particular flash block, block_offset is the offset + * (from the base of flash) to start of the block + * data_offset is the offset (from the base of flash) + * where you wish to start programming + * + * NB this function DOES NOT check that you are only writing a single + * block of data as that would slow down this function. + * + * Use alt_write_flash if you want that level of error checking. + */ + +static __inline__ int __attribute__ ((always_inline)) alt_write_flash_block( + alt_flash_fd* fd, int block_offset, + int data_offset, + const void *data, int length) +{ + + int ret_code; + ret_code = fd->write_block( fd, block_offset, data_offset, data, length ); + +/* remove dcache_flush call for FB330552 + if(!ret_code) + alt_dcache_flush((alt_u8*)fd->base_addr + data_offset, length); +*/ + return ret_code; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_FLASH_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_flash_dev.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_flash_dev.h new file mode 100644 index 0000000..6d06725 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_flash_dev.h @@ -0,0 +1,100 @@ +#ifndef __ALT_FLASH_DEV_H__ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2015 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/****************************************************************************** +* * +* Alt_flash_dev.h - Generic Flash device interfaces * +* * +* Author PRR * +* * +******************************************************************************/ +#define __ALT_FLASH_DEV_H__ + +#include "alt_flash_types.h" +#include "sys/alt_llist.h" +#include "priv/alt_dev_llist.h" + +#include "alt_types.h" + +typedef struct alt_flash_dev alt_flash_dev; +typedef alt_flash_dev alt_flash_fd; + +static ALT_INLINE int alt_flash_device_register( alt_flash_fd* fd) +{ + extern alt_llist alt_flash_dev_list; + + return alt_dev_llist_insert ((alt_dev_llist*) fd, &alt_flash_dev_list); +} + +typedef alt_flash_dev* (*alt_flash_open)(alt_flash_dev* flash, + const char* name ); +typedef int (*alt_flash_close)(alt_flash_dev* flash_info); + +typedef int (*alt_flash_write)( alt_flash_dev* flash, int offset, + const void* src_addr, int length ); + +typedef int (*alt_flash_get_flash_info)( alt_flash_dev* flash, flash_region** info, + int* number_of_regions); +typedef int (*alt_flash_write_block)( alt_flash_dev* flash, int block_offset, + int data_offset, const void* data, + int length); +typedef int (*alt_flash_erase_block)( alt_flash_dev* flash, int offset); +typedef int (*alt_flash_read)(alt_flash_dev* flash, int offset, + void* dest_addr, int length ); +typedef int (*alt_flash_lock)(alt_flash_dev* flash, alt_u32 sectors_to_lock); + +struct alt_flash_dev +{ + alt_llist llist; + const char* name; + alt_flash_open open; + alt_flash_close close; + alt_flash_write write; + alt_flash_read read; + alt_flash_get_flash_info get_info; + alt_flash_erase_block erase_block; + alt_flash_write_block write_block; + void* base_addr; + int length; + int number_of_regions; + flash_region region_info[ALT_MAX_NUMBER_OF_FLASH_REGIONS]; + alt_flash_lock lock; +}; + +#endif /* __ALT_FLASH_DEV_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_flash_types.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_flash_types.h new file mode 100644 index 0000000..10f1f01 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_flash_types.h @@ -0,0 +1,64 @@ +#ifndef __ALT_FLASH_TYPES_H__ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/****************************************************************************** +* * +* Alt_flash_types.h - Some generic types and defines used by the flash code * +* * +* Author PRR * +* * +******************************************************************************/ +#define __ALT_FLASH_TYPES_H__ + +#ifndef ALT_MAX_NUMBER_OF_FLASH_REGIONS +#define ALT_MAX_NUMBER_OF_FLASH_REGIONS 8 +#endif /* ALT_MAX_NUMBER_OF_FLASH_REGIONS */ + +/* + * Description of a single Erase region + */ +typedef struct flash_region +{ + int offset; + int region_size; + int number_of_blocks; + int block_size; +}flash_region; + +#endif /* __ALT_FLASH_TYPES_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_irq.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_irq.h new file mode 100644 index 0000000..94a556a --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_irq.h @@ -0,0 +1,245 @@ +#ifndef __ALT_IRQ_H__ +#define __ALT_IRQ_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * alt_irq.h is the Nios II specific implementation of the interrupt controller + * interface. + * + * Nios II includes optional support for an external interrupt controller. + * When an external controller is present, the "Enhanced" interrupt API + * must be used to manage individual interrupts. The enhanced API also + * supports the processor's internal interrupt controller. Certain API + * members are accessible from either the "legacy" or "enhanced" interrpt + * API. + * + * Regardless of which API is in use, this file should be included by + * application code and device drivers that register ISRs or manage interrpts. + */ +#include + +#include "nios2.h" +#include "alt_types.h" +#include "system.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Macros used by alt_irq_enabled + */ +#define ALT_IRQ_ENABLED 1 +#define ALT_IRQ_DISABLED 0 + +/* + * Number of available interrupts in internal interrupt controller. + */ +#define ALT_NIRQ NIOS2_NIRQ + +/* + * Used by alt_irq_disable_all() and alt_irq_enable_all(). + */ +typedef int alt_irq_context; + +/* ISR Prototype */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +typedef void (*alt_isr_func)(void* isr_context); +#else +typedef void (*alt_isr_func)(void* isr_context, alt_u32 id); +#endif + +/* + * The following protypes and routines are supported by both + * the enhanced and legacy interrupt APIs + */ + +/* + * alt_irq_enabled can be called to determine if the processor's global + * interrupt enable is asserted. The return value is zero if interrupts + * are disabled, and non-zero otherwise. + * + * Whether the internal or external interrupt controller is present, + * individual interrupts may still be disabled. Use the other API to query + * a specific interrupt. + */ +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_enabled (void) +{ + int status; + + NIOS2_READ_STATUS (status); + + return status & NIOS2_STATUS_PIE_MSK; +} + +/* + * alt_irq_disable_all() + * + * This routine inhibits all interrupts by negating the status register PIE + * bit. It returns the previous contents of the CPU status register (IRQ + * context) which can be used to restore the status register PIE bit to its + * state before this routine was called. + */ +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + + return context; +} + +/* + * alt_irq_enable_all() + * + * Enable all interrupts that were previously disabled by alt_irq_disable_all() + * + * This routine accepts a context to restore the CPU status register PIE bit + * to the state prior to a call to alt_irq_disable_all(). + + * In the case of nested calls to alt_irq_disable_all()/alt_irq_enable_all(), + * this means that alt_irq_enable_all() does not necessarily re-enable + * interrupts. + * + * This routine will perform a read-modify-write sequence to restore only + * status.PIE if the processor is configured with options that add additional + * writeable status register bits. These include the MMU, MPU, the enhanced + * interrupt controller port, and shadow registers. Otherwise, as a performance + * enhancement, status is overwritten with the prior context. + */ +static ALT_INLINE void ALT_ALWAYS_INLINE + alt_irq_enable_all (alt_irq_context context) +{ +#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) || (defined NIOS2_EIC_PRESENT) || \ + (defined NIOS2_MMU_PRESENT) || (defined NIOS2_MPU_PRESENT) + alt_irq_context status; + + NIOS2_READ_STATUS (status); + + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); +#endif +} + +/* + * The function alt_irq_init() is defined within the auto-generated file + * alt_sys_init.c. This function calls the initilization macros for all + * interrupt controllers in the system at config time, before any other + * non-interrupt controller driver is initialized. + * + * The "base" parameter is ignored and only present for backwards-compatibility. + * It is recommended that NULL is passed in for the "base" parameter. + */ +extern void alt_irq_init (const void* base); + +/* + * alt_irq_cpu_enable_interrupts() enables the CPU to start taking interrupts. + */ +static ALT_INLINE void ALT_ALWAYS_INLINE + alt_irq_cpu_enable_interrupts (void) +{ + NIOS2_WRITE_STATUS(NIOS2_STATUS_PIE_MSK +#if defined(NIOS2_EIC_PRESENT) && (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) + | NIOS2_STATUS_RSIE_MSK +#endif + ); +} + + +/* + * Prototypes for the enhanced interrupt API. + */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +/* + * alt_ic_isr_register() can be used to register an interrupt handler. If the + * function is succesful, then the requested interrupt will be enabled upon + * return. + */ +extern int alt_ic_isr_register(alt_u32 ic_id, + alt_u32 irq, + alt_isr_func isr, + void *isr_context, + void *flags); + +/* + * alt_ic_irq_enable() and alt_ic_irq_disable() enable/disable a specific + * interrupt by using IRQ port and interrupt controller instance. + */ +int alt_ic_irq_enable (alt_u32 ic_id, alt_u32 irq); +int alt_ic_irq_disable(alt_u32 ic_id, alt_u32 irq); + + /* + * alt_ic_irq_enabled() indicates whether a specific interrupt, as + * specified by IRQ port and interrupt controller instance is enabled. + */ +alt_u32 alt_ic_irq_enabled(alt_u32 ic_id, alt_u32 irq); + +#else +/* + * Prototypes for the legacy interrupt API. + */ +#include "priv/alt_legacy_irq.h" +#endif + + +/* + * alt_irq_pending() returns a bit list of the current pending interrupts. + * This is used by alt_irq_handler() to determine which registered interrupt + * handlers should be called. + * + * This routine is only available for the Nios II internal interrupt + * controller. + */ +#ifndef NIOS2_EIC_PRESENT +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void) +{ + alt_u32 active; + + NIOS2_READ_IPENDING (active); + + return active; +} +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_IRQ_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_irq_entry.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_irq_entry.h new file mode 100644 index 0000000..549811c --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_irq_entry.h @@ -0,0 +1,39 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This file pulls in the IRQ entry assembler and C code, which is only + * required if there are any interruptes in the system. + */ + +__asm__( "\n\t.globl alt_irq_entry" ); + +__asm__( "\n\t.globl alt_irq_handler" ); + diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h new file mode 100644 index 0000000..1d1f16f --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h @@ -0,0 +1,77 @@ +#ifndef __ALT_LICENSE_REMINDER_UCOSII_H__ +#define __ALT_LICENSE_REMINDER_UCOSII_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include + +#define ALT_LICENSE_REMINDER_UCOSII_STRING \ + "============== Software License Reminder ===============\n" \ + "\n" \ + "uC/OS-II is provided in source form for FREE evaluation,\n" \ + "for educational use, or for peaceful research. If you\n" \ + "plan on using uC/OS-II in a commercial product you need\n" \ + "to contact Micrium to properly license its use in your\n" \ + "product. Micrium provides ALL the source code on the\n" \ + "Altera distribution for your convenience and to help you\n" \ + "experience uC/OS-II. The fact that the source is provided\n" \ + "does NOT mean that you can use it without paying a\n" \ + "licensing fee. Please help us continue to provide the\n" \ + "Embedded community with the finest software available.\n" \ + "Your honesty is greatly appreciated.\n" \ + "\n" \ + "Please contact:\n" \ + "\n" \ + "M I C R I U M\n" \ + "949 Crestview Circle\n" \ + "Weston, FL 33327-1848\n" \ + "U.S.A.\n" \ + "\n" \ + "Phone : +1 954 217 2036\n" \ + "FAX : +1 954 217 2037\n" \ + "WEB : www.micrium.com\n" \ + "E-mail: Sales@Micrium.com\n" \ + "\n" \ + "========================================================\n" + +#define alt_license_reminder_ucosii() puts(ALT_LICENSE_REMINDER_UCOSII_STRING) + + +#endif /* __ALT_LICENSE_REMINDER_UCOSII_H__ */ + diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_llist.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_llist.h new file mode 100644 index 0000000..84cb051 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_llist.h @@ -0,0 +1,123 @@ +#ifndef __ALT_LIST_H__ +#define __ALT_LIST_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_types.h" + +/* + * alt_llist.h defines structures and functions for use in manipulating linked + * lists. A list is considered to be constructed from a chain of objects of + * type alt_llist, with one object being defined to be the head element. + * + * A list is considered to be empty if it only contains the head element. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * alt_llist is the structure used to represent an element within a linked + * list. + */ + +typedef struct alt_llist_s alt_llist; + +struct alt_llist_s { + alt_llist* next; /* Pointer to the next element in the list. */ + alt_llist* previous; /* Pointer to the previous element in the list. */ +}; + +/* + * ALT_LLIST_HEAD is a macro that can be used to create the head of a new + * linked list. This is named "head". The head element is initialised to + * represent an empty list. + */ + +#define ALT_LLIST_HEAD(head) alt_llist head = {&head, &head} + +/* + * ALT_LLIST_ENTRY is a macro used to define an uninitialised linked list + * entry. This is used to reserve space in structure initialisation for + * structures that inherit form alt_llist. + */ + +#define ALT_LLIST_ENTRY {0, 0} + +/* + * alt_llist_insert() insert adds the linked list entry "entry" as the + * first entry in the linked list "list". "list" is the list head element. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_insert(alt_llist* list, + alt_llist* entry) +{ + entry->previous = list; + entry->next = list->next; + + list->next->previous = entry; + list->next = entry; +} + +/* + * alt_llist_remove() is called to remove an element from a linked list. The + * input argument is the element to remove. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_remove(alt_llist* entry) +{ + entry->next->previous = entry->previous; + entry->previous->next = entry->next; + + /* + * Set the entry to point to itself, so that any further calls to + * alt_llist_remove() are harmless. + */ + + entry->previous = entry; + entry->next = entry; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_LLIST_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_load.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_load.h new file mode 100644 index 0000000..e4c4c46 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_load.h @@ -0,0 +1,78 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "alt_types.h" + +/* + * This macro is used to load code/data from its load address to its + * execution address for a given section. The section name is the input + * argument. Note that a leading '.' is assumed in the name. For example + * to load the section .onchip_ram, use: + * + * ALT_LOAD_SECTION_BY_NAME(onchip_ram); + * + * This requires that the apropriate linker symbols have been generated + * for the section in question. This will be the case if you are using the + * default linker script. + */ + +#define ALT_LOAD_SECTION_BY_NAME(name) \ + { \ + extern void _alt_partition_##name##_start; \ + extern void _alt_partition_##name##_end; \ + extern void _alt_partition_##name##_load_addr; \ + \ + alt_load_section(&_alt_partition_##name##_load_addr, \ + &_alt_partition_##name##_start, \ + &_alt_partition_##name##_end); \ + } + +/* + * Function used to load an individual section from flash to RAM. + * + * There is an implicit assumption here that the linker script will ensure + * that all sections are word aligned. + * + */ + +static void ALT_INLINE alt_load_section (alt_u32* from, + alt_u32* to, + alt_u32* end) +{ + if (to != from) + { + while( to != end ) + { + *to++ = *from++; + } + } +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_log_printf.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_log_printf.h new file mode 100644 index 0000000..1536d8f --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_log_printf.h @@ -0,0 +1,354 @@ +/* alt_log_printf.h + * + * ALT_LOG is designed to provide extra logging/debugging messages from HAL + * through a different port than stdout. It is enabled by the ALT_LOG_ENABLE + * define, which needs to supplied at compile time. When logging is turned off, + * code size is unaffected. Thus, this should be transparent to the user + * when it is not actively turned on, and should not affect projects in any way. + * + * There are macros sprinkled within different components, such as the jtag uart + * and timer, in the HAL code. They are always named ALT_LOG_, and can be + * safely ignored if ALT_LOG is turned off. + * + * To turn on ALT_LOG, ALT_LOG_ENABLE must be defined, and ALT_LOG_PORT_TYPE and + * ALT_LOG_PORT_BASE must be set in system.h. This is done through editing + * .ptf, by editing the alt_log_port_type & alt_log_port_base settings. + * See the documentation html file for examples. + * + * When it is turned on, it will output extra HAL messages to a port specified + * in system.h. This can be a UART or JTAG UART port. By default it will + * output boot messages, detailing every step of the boot process. + * + * Extra logging is designed to be enabled by flags, which are defined in + * alt_log_printf.c. The default value is that all flags are off, so only the + * boot up logging messages show up. ALT_LOG_FLAGS can be set to enable certain + * groupings of flags, and that grouping is done in this file. Each flag can + * also be overridden with a -D at compile time. + * + * This header file includes the necessary prototypes for using the alt_log + * functions. It also contains all the macros that are used to remove the code + * from alt log is turned off. Also, the macros in other HAL files are defined + * here at the bottom. These macros all call some C function that is in + * alt_log_printf.c. + * + * The logging has functions for printing in C (ALT_LOG_PRINTF) and in assembly + * (ALT_LOG_PUTS). This was needed because the assembly printing occurs before + * the device is initialized. The assembly function corrupts register R4-R7, + * which are not used in the normal boot process. For this reason, do not call + * the assembly function in C. + * + * author: gkwan + */ + + +#ifndef __ALT_LOG_PRINTF_H__ +#define __ALT_LOG_PRINTF_H__ + +#include + +/* Global switch to turn on logging functions */ +#ifdef ALT_LOG_ENABLE + + /* ALT_LOG_PORT_TYPE values as defined in system.h. They are defined as + * numbers here first becasue the C preprocessor does not handle string + * comparisons. */ + #define ALTERA_AVALON_JTAG_UART 1 + #define ALTERA_AVALON_UART 0 + + /* If this .h file is included by an assembly file, skip over include files + * that won't compile in assembly. */ + #ifndef ALT_ASM_SRC + #include + #include "sys/alt_alarm.h" + #include "sys/alt_dev.h" + #ifdef __ALTERA_AVALON_JTAG_UART + #include "altera_avalon_jtag_uart.h" + #endif + #endif /* ALT_ASM_SRC */ + + /* These are included for the port register offsets and masks, needed + * to write to the port. Only include if the port type is set correctly, + * otherwise error. If alt_log is turned on and the port to output to is + * incorrect or does not exist, then should exit. */ + #if ALT_LOG_PORT_TYPE == ALTERA_AVALON_JTAG_UART + #ifdef __ALTERA_AVALON_JTAG_UART + #include + #else + #error ALT_LOG: JTAG_UART port chosen, but no JTAG_UART in system. + #endif + #elif ALT_LOG_PORT_TYPE == ALTERA_AVALON_UART + #ifdef __ALTERA_AVALON_UART + #include + #else + #error ALT_LOG: UART Port chosen, but no UART in system. + #endif + #else + #error ALT_LOG: alt_log_port_type declaration invalid! + #endif + + /* ALT_LOG_ENABLE turns on the basic printing function */ + #define ALT_LOG_PRINTF(...) do {alt_log_printf_proc(__VA_ARGS__);} while (0) + + /* Assembly macro for printing in assembly, calls tx_log_str + * which is in alt_log_macro.S. + * If alt_log_boot_on_flag is 0, skips the printing */ + #define ALT_LOG_PUTS(str) movhi r4, %hiadj(alt_log_boot_on_flag) ; \ + addi r4, r4, %lo(alt_log_boot_on_flag) ; \ + ldwio r5, 0(r4) ; \ + beq r0, r5, 0f ; \ + movhi r4, %hiadj(str) ; \ + addi r4, r4, %lo(str) ; \ + call tx_log_str ; \ + 0: + + /* These defines are here to faciliate the use of one output function + * (alt_log_txchar) to print to both the JTAG UART or the UART. Depending + * on the port type, the status register, read mask, and output register + * are set to the appropriate value for the port. */ + #if ALT_LOG_PORT_TYPE == ALTERA_AVALON_JTAG_UART + #define ALT_LOG_PRINT_REG_RD IORD_ALTERA_AVALON_JTAG_UART_CONTROL + #define ALT_LOG_PRINT_MSK ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK + #define ALT_LOG_PRINT_TXDATA_WR IOWR_ALTERA_AVALON_JTAG_UART_DATA + #define ALT_LOG_PRINT_REG_OFFSET (ALTERA_AVALON_JTAG_UART_CONTROL_REG*0x4) + #define ALT_LOG_PRINT_TXDATA_REG_OFFSET (ALTERA_AVALON_JTAG_UART_DATA_REG*0x4) + #elif ALT_LOG_PORT_TYPE == ALTERA_AVALON_UART + #define ALT_LOG_PRINT_REG_RD IORD_ALTERA_AVALON_UART_STATUS + #define ALT_LOG_PRINT_MSK ALTERA_AVALON_UART_STATUS_TRDY_MSK + #define ALT_LOG_PRINT_TXDATA_WR IOWR_ALTERA_AVALON_UART_TXDATA + #define ALT_LOG_PRINT_REG_OFFSET (ALTERA_AVALON_UART_STATUS_REG*0x4) + #define ALT_LOG_PRINT_TXDATA_REG_OFFSET (ALTERA_AVALON_UART_TXDATA_REG*0x4) + #endif /* ALT_LOG_PORT */ + + /* Grouping of flags via ALT_LOG_FLAGS. Each specific flag can be set via + * -D at compile time, or else they'll be set to a default value according + * to ALT_LOG_FLAGS. ALT_LOG_FLAGS = 0 or not set is the default, where + * only the boot messages will be printed. As ALT_LOG_FLAGS increase, they + * increase in intrusiveness to the program, and will affect performance. + * + * Flag Level 1 - turns on system clock and JTAG UART startup status + * 2 - turns on write echo and JTAG_UART alarm (periodic report) + * 3 - turns on JTAG UART ISR logging - will slow performance + * significantly. + * -1 - All logging output is off, but if ALT_LOG_ENABLE is + * defined all logging function is built and code size + * remains constant + * + * Flag settings - 1 = on, 0 = off. */ + + /* This flag turns on "boot" messages for printing. This includes messages + * during crt0.S, then alt_main, and finally alt_exit. */ + #ifndef ALT_LOG_BOOT_ON_FLAG_SETTING + #if ALT_LOG_FLAGS == 1 + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1 + #endif + #endif /* ALT_LOG_BOOT_ON_FLAG_SETTING */ + + #ifndef ALT_LOG_SYS_CLK_ON_FLAG_SETTING + #if ALT_LOG_FLAGS == 1 + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_SYS_CLK_ON_FLAG_SETTING */ + + #ifndef ALT_LOG_WRITE_ON_FLAG_SETTING + #if ALT_LOG_FLAGS == 1 + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_WRITE_ON_FLAG_SETTING */ + + #ifndef ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING + #ifndef __ALTERA_AVALON_JTAG_UART + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 1 + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING */ + + #ifndef ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING + #ifndef __ALTERA_AVALON_JTAG_UART + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 1 + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_JTAG_UART_STARTUP_INFO_FLAG_SETTING */ + + #ifndef ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING + #ifndef __ALTERA_AVALON_JTAG_UART + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 1 + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING */ + +#ifndef ALT_ASM_SRC + /* Function Prototypes */ + void alt_log_txchar(int c,char *uartBase); + void alt_log_private_printf(const char *fmt,int base,va_list args); + void alt_log_repchar(char c,int r,int base); + int alt_log_printf_proc(const char *fmt, ... ); + void alt_log_system_clock(); + #ifdef __ALTERA_AVALON_JTAG_UART + alt_u32 altera_avalon_jtag_uart_report_log(void * context); + void alt_log_jtag_uart_startup_info(altera_avalon_jtag_uart_state* dev, int base); + void alt_log_jtag_uart_print_control_reg(altera_avalon_jtag_uart_state* dev, \ + int base, const char* header); + void alt_log_jtag_uart_isr_proc(int base, altera_avalon_jtag_uart_state* dev); + #endif + void alt_log_write(const void *ptr, size_t len); + + /* extern all global variables */ + /* CASE:368514 - The boot message flag is linked into the sdata section + * because if it is zero, it would otherwise be placed in the bss section. + * alt_log examines this variable before the BSS is cleared in the boot-up + * process. + */ + extern volatile alt_u32 alt_log_boot_on_flag __attribute__ ((section (".sdata"))); + extern volatile alt_u8 alt_log_write_on_flag; + extern volatile alt_u8 alt_log_sys_clk_on_flag; + extern volatile alt_u8 alt_log_jtag_uart_alarm_on_flag; + extern volatile alt_u8 alt_log_jtag_uart_isr_on_flag; + extern volatile alt_u8 alt_log_jtag_uart_startup_info_on_flag; + extern volatile int alt_log_sys_clk_count; + extern volatile int alt_system_clock_in_sec; + extern alt_alarm alt_log_jtag_uart_alarm_1; +#endif /* ALT_ASM_SRC */ + + + /* Below are the MACRO defines used in various HAL files. They check + * if their specific flag is turned on; if it is, then it executes its + * code. + * + * To keep this file reasonable, most of these macros calls functions, + * which are defined in alt_log_printf.c. Look there for implementation + * details. */ + + /* Boot Messages Logging */ + #define ALT_LOG_PRINT_BOOT(...) \ + do { if (alt_log_boot_on_flag==1) {ALT_LOG_PRINTF(__VA_ARGS__);} \ + } while (0) + + /* JTAG UART Logging */ + /* number of ticks before alarm runs logging function */ + #ifndef ALT_LOG_JTAG_UART_TICKS_DIVISOR + #define ALT_LOG_JTAG_UART_TICKS_DIVISOR 10 + #endif + #ifndef ALT_LOG_JTAG_UART_TICKS + #define ALT_LOG_JTAG_UART_TICKS \ + (alt_ticks_per_second()/ALT_LOG_JTAG_UART_TICKS_DIVISOR) + #endif + + /* if there's a JTAG UART defined, then enable these macros */ + #ifdef __ALTERA_AVALON_JTAG_UART + + /* Macro in altera_avalon_jtag_uart.c, to register the alarm function. + * Also, the startup register info is also printed here, as this is + * called within the device driver initialization. */ + #define ALT_LOG_JTAG_UART_ALARM_REGISTER(dev, base) \ + do { if (alt_log_jtag_uart_alarm_on_flag==1) { \ + alt_alarm_start(&alt_log_jtag_uart_alarm_1, \ + ALT_LOG_JTAG_UART_TICKS, &altera_avalon_jtag_uart_report_log,\ + dev);} \ + if (alt_log_jtag_uart_startup_info_on_flag==1) {\ + alt_log_jtag_uart_startup_info(dev, base);} \ + } while (0) + + /* JTAG UART IRQ Logging (when buffer is empty) + * Inserted in the ISR in altera_avalon_jtag_uart.c */ + #define ALT_LOG_JTAG_UART_ISR_FUNCTION(base, dev) \ + do { alt_log_jtag_uart_isr_proc(base, dev); } while (0) + /* else, define macros to nothing. Or else the jtag_uart specific types + * will throw compiler errors */ + #else + #define ALT_LOG_JTAG_UART_ALARM_REGISTER(dev, base) + #define ALT_LOG_JTAG_UART_ISR_FUNCTION(base, dev) + #endif + + /* System clock logging + * How often (in seconds) the system clock logging prints. + * The default value is every 1 second */ + #ifndef ALT_LOG_SYS_CLK_INTERVAL_MULTIPLIER + #define ALT_LOG_SYS_CLK_INTERVAL_MULTIPLIER 1 + #endif + #ifndef ALT_LOG_SYS_CLK_INTERVAL + #define ALT_LOG_SYS_CLK_INTERVAL \ + (alt_ticks_per_second()*ALT_LOG_SYS_CLK_INTERVAL_MULTIPLIER) + #endif + + /* System clock logging - prints a message every interval (set above) + * to show that the system clock is alive. + * This macro is used in altera_avalon_timer_sc.c */ + #define ALT_LOG_SYS_CLK_HEARTBEAT() \ + do { alt_log_system_clock(); } while (0) + + /* alt_write_logging - echos a message every time write() is called, + * displays the first ALT_LOG_WRITE_ECHO_LEN characters. + * This macro is used in alt_write.c */ + #ifndef ALT_LOG_WRITE_ECHO_LEN + #define ALT_LOG_WRITE_ECHO_LEN 15 + #endif + + #define ALT_LOG_WRITE_FUNCTION(ptr,len) \ + do { alt_log_write(ptr,len); } while (0) + +#else /* ALT_LOG_ENABLE not defined */ + + /* logging is off, set all relevant macros to null */ + #define ALT_LOG_PRINT_BOOT(...) + #define ALT_LOG_PRINTF(...) + #define ALT_LOG_JTAG_UART_ISR_FUNCTION(base, dev) + #define ALT_LOG_JTAG_UART_ALARM_REGISTER(dev, base) + #define ALT_LOG_SYS_CLK_HEARTBEAT() + #define ALT_LOG_PUTS(str) + #define ALT_LOG_WRITE_FUNCTION(ptr,len) + +#endif /* ALT_LOG_ENABLE */ + +#endif /* __ALT_LOG_PRINTF_H__ */ + diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_set_args.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_set_args.h new file mode 100644 index 0000000..a9372c5 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_set_args.h @@ -0,0 +1,71 @@ +#ifndef __ALT_SET_ARGS_H__ +#define __ALT_SET_ARGS_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The function alt_set_args() is provided in order to define the input + * arguments to main(). If this function is not called before main() then the + * argument list passed to main() will be empty. + * + * It is expected that this function will only be used by the ihost/iclient + * utility. + */ + +static inline void alt_set_args (int argc, char** argv, char** envp) +{ + extern int alt_argc; + extern char** alt_argv; + extern char** alt_envp; + + alt_argc = argc; + alt_argv = argv; + alt_envp = envp; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_SET_ARGS_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_sim.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_sim.h new file mode 100644 index 0000000..b41da40 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_sim.h @@ -0,0 +1,91 @@ +#ifndef __ALT_SIM_H__ +#define __ALT_SIM_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "system.h" +#include "alt_types.h" + +/* + * Instructions that might mean something special to a simulator. + * These have no special effect on real hardware (they are just nops). + */ +#define ALT_SIM_FAIL() \ + do { __asm volatile ("cmpltui r0, r0, 0xabc1"); } while (0) + +#define ALT_SIM_PASS() \ + do { __asm volatile ("cmpltui r0, r0, 0xabc2"); } while (0) + +#define ALT_SIM_IN_TOP_OF_HOT_LOOP() \ + do { __asm volatile ("cmpltui r0, r0, 0xabc3"); } while (0) + +/* + * Routine called on exit. + */ +static ALT_INLINE ALT_ALWAYS_INLINE void alt_sim_halt(int exit_code) +{ + register int r2 asm ("r2") = exit_code; + +#if defined(NIOS2_HAS_DEBUG_STUB) && (defined(ALT_BREAK_ON_EXIT) || defined(ALT_PROVIDE_GMON)) + + register int r3 asm ("r3") = (1 << 2); + +#ifdef ALT_PROVIDE_GMON + extern unsigned int alt_gmon_data[]; + register int r4 asm ("r4") = (int)alt_gmon_data; + r3 |= (1 << 4); +#define ALT_GMON_DATA ,"r"(r4) +#else +#define ALT_GMON_DATA +#endif /* ALT_PROVIDE_GMON */ + + if (r2) { + ALT_SIM_FAIL(); + } else { + ALT_SIM_PASS(); + } + + __asm__ volatile ("\n0:\n\taddi %0,%0, -1\n\tbgt %0,zero,0b" : : "r" (ALT_CPU_FREQ/100) ); /* Delay for >30ms */ + + __asm__ volatile ("break 2" : : "r"(r2), "r"(r3) ALT_GMON_DATA ); + +#else /* !DEBUG_STUB */ + if (r2) { + ALT_SIM_FAIL(); + } else { + ALT_SIM_PASS(); + } +#endif /* DEBUG_STUB */ +} + +#define ALT_SIM_HALT(exit_code) \ + alt_sim_halt(exit_code) + +#endif /* __ALT_SIM_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_stack.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_stack.h new file mode 100644 index 0000000..ebcad7a --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_stack.h @@ -0,0 +1,126 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALT_STACK_H__ +#define __ALT_STACK_H__ + +/* + * alt_stack.h is the nios2 specific implementation of functions used by the + * stack overflow code. + */ + +#include "nios2.h" + +#include "alt_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + + +extern char * alt_stack_limit_value; + +#ifdef ALT_EXCEPTION_STACK +extern char __alt_exception_stack_pointer[]; /* set by the linker */ +#endif /* ALT_EXCEPTION_STACK */ + + +/* + * alt_stack_limit can be called to determine the current value of the stack + * limit register. + */ + +static ALT_INLINE char * ALT_ALWAYS_INLINE alt_stack_limit (void) +{ + char * limit; + NIOS2_READ_ET(limit); + + return limit; +} + +/* + * alt_stack_pointer can be called to determine the current value of the stack + * pointer register. + */ + +static ALT_INLINE char * ALT_ALWAYS_INLINE alt_stack_pointer (void) +{ + char * pointer; + NIOS2_READ_SP(pointer); + + return pointer; +} + + +#ifdef ALT_EXCEPTION_STACK + +/* + * alt_exception_stack_pointer returns the normal stack pointer from + * where it is stored on the exception stack (uppermost 4 bytes). This + * is really only useful during exception processing, and is only + * available if a separate exception stack has been configured. + */ + +static ALT_INLINE char * ALT_ALWAYS_INLINE alt_exception_stack_pointer (void) +{ + return (char *) *(alt_u32 *)(__alt_exception_stack_pointer - sizeof(alt_u32)); +} + +#endif /* ALT_EXCEPTION_STACK */ + + +/* + * alt_set_stack_limit can be called to update the current value of the stack + * limit register. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_set_stack_limit (char * limit) +{ + alt_stack_limit_value = limit; + NIOS2_WRITE_ET(limit); +} + +/* + * alt_report_stack_overflow reports that a stack overflow happened. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_report_stack_overflow (void) +{ + NIOS2_REPORT_STACK_OVERFLOW(); +} + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_STACK_H__ */ + diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_stdio.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_stdio.h new file mode 100644 index 0000000..a3d1f48 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_stdio.h @@ -0,0 +1,66 @@ +#ifndef __ALT_STDIO_H__ +#define __ALT_STDIO_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2015 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * Definitions for ALT stdio routines. + */ + +#include + + +#ifdef __cplusplus +extern "C" { +#endif + +int alt_getchar(); +int alt_putchar(int c); +int alt_putstr(const char* str); +void alt_printf(const char *fmt, ...); +#ifdef ALT_SEMIHOSTING +int alt_putcharbuf(int c); +int alt_putstrbuf(const char* str); +int alt_putbufflush(); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_STDIO_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_sys_init.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_sys_init.h new file mode 100644 index 0000000..3b18059 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_sys_init.h @@ -0,0 +1,62 @@ +#ifndef __ALT_SYS_INIT_H__ +#define __ALT_SYS_INIT_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The function alt_sys_init() is defined within the auto-generated file: + * alt_sys_init.c. This function calls the initilisation macros for all + * devices, file systems, and software components within the system. + * + * The list of initilisation macros to use is constructed using the PTF and + * STF files associated with the system. + */ + +extern void alt_sys_init (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_SYS_INIT_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_sys_wrappers.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_sys_wrappers.h new file mode 100644 index 0000000..eea552d --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_sys_wrappers.h @@ -0,0 +1,100 @@ +#ifndef __ALT_SYS_WRAPPERS_H__ +#define __ALT_SYS_WRAPPERS_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This file provides the prototypes for the HAL 'UNIX style functions. The + * names of these functions are defined in alt_syscall.h. THese are defined to + * be the standard names when running the standalone HAL, e.g. open(), close() + * etc., but the names may be redefined as a part of an operating system port + * in order to avoid name clashes. + */ + +#include "os/alt_syscall.h" + +#include +#include +#include +#include +#include +#include + +extern int ALT_CLOSE (int __fd); +extern int ALT_EXECVE (const char *__path, + char * const __argv[], + char * const __envp[]); +extern void ALT_EXIT (int __status); +extern int ALT_FSTAT (int file, struct stat *st); +extern int ALT_FCNTL (int file, int cmd, ...); +extern pid_t ALT_FORK (void); +extern pid_t ALT_GETPID (void); + +#if defined (__GNUC__) && __GNUC__ >= 4 +extern int ALT_GETTIMEOFDAY (struct timeval *ptimeval, + void *ptimezone); +#else +extern int ALT_GETTIMEOFDAY (struct timeval *ptimeval, + struct timezone *ptimezone); +#endif + +extern int ALT_IOCTL (int file, int req, void* arg); +extern int ALT_ISATTY (int file); +extern int ALT_KILL (int pid, int sig); +extern int ALT_LINK (const char *existing, const char *new); +extern off_t ALT_LSEEK (int file, off_t ptr, int dir); +extern int ALT_OPEN (const char* file, int flags, ...); +extern int ALT_READ (int file, void *ptr, size_t len); +extern int ALT_RENAME (char *existing, char *new); +extern void* ALT_SBRK (ptrdiff_t incr); +extern int ALT_SETTIMEOFDAY (const struct timeval *t, + const struct timezone *tz); +extern int ALT_STAT (const char *file, struct stat *st); +extern clock_t ALT_TIMES (struct tms *buf); +extern int ALT_UNLINK (const char *name); + +#if defined (__GNUC__) && __GNUC__ >= 4 +int ALT_USLEEP (useconds_t us); +#else +unsigned int ALT_USLEEP (unsigned int us); +#endif + +extern int ALT_WAIT (int *status); +extern int ALT_WRITE (int file, const void *ptr, size_t len); + + +extern char** ALT_ENVIRON; + +/* + * + */ + +#endif /* __ALT_SYS_WRAPPERS_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_timestamp.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_timestamp.h new file mode 100644 index 0000000..ec704ba --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_timestamp.h @@ -0,0 +1,60 @@ +#ifndef __ALT_TIMESTAMP_H__ +#define __ALT_TIMESTAMP_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_types.h" +#include "altera_avalon_timer.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +extern int alt_timestamp_start (void); + +extern alt_timestamp_type alt_timestamp (void); + +extern alt_u32 alt_timestamp_freq (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_TIMESTAMP_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_warning.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_warning.h new file mode 100644 index 0000000..01318bd --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_warning.h @@ -0,0 +1,75 @@ +#ifndef __WARNING_H__ +#define __WARNING_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * alt_warning.h provides macro definitions that can be used to generate link + * time warnings. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The symbol "__alt_invalid" is used to force a link error. There should be + * no corresponding implementation of this function. + */ + +extern void __alt_invalid (void); + +#define ALT_LINK_WARNING(symbol, msg) \ + __asm__(".ifndef __evoke_link_warning_" #symbol \ + "\n\t .section .gnu.warning." #symbol \ + "\n__evoke_link_warning_" #symbol ":\n\t .string \x22" msg "\x22 \n\t .previous" \ + "\n .endif"); + +/* A canned warning for sysdeps/stub functions. */ + +#define ALT_STUB_WARNING(name) \ + ALT_LINK_WARNING (name, \ + "warning: " #name " is not implemented and will always fail") + +#define ALT_OBSOLETE_FUNCTION_WARNING(name) \ + ALT_LINK_WARNING (name, \ + "warning: " #name " is a deprecated function") + +#define ALT_LINK_ERROR(msg) \ + ALT_LINK_WARNING (__alt_invalid, msg); \ + __alt_invalid() + +#ifdef __cplusplus +} +#endif + +#endif /* __WARNING_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/ioctl.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/ioctl.h new file mode 100644 index 0000000..453283b --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/ioctl.h @@ -0,0 +1,90 @@ +#ifndef __IOCTL_H__ +#define __IOCTL_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The ioctl() system call be used to initiate a variety of control operations + * on a file descriptor. For the most part this simply translates to a call to + * the ioctl() function of the associated device driver (TIOCEXCL and + * TIOCNXCL are notable exceptions - see ioctl.c for details). + * + * The interpretation of the ioctl requests are therefore device specific. + * + * This function is equivalent to the standard Posix ioctl() call. + */ + +extern int ioctl (int fd, int req, void* arg); + +/* + * list of ioctl calls handled by the system ioctl implementation. + */ + +#define TIOCEXCL 0x740d /* exclusive use of the device */ +#define TIOCNXCL 0x740e /* allow multiple use of the device */ + +/* + * ioctl calls which can be handled by device drivers. + */ + +#define TIOCOUTQ 0x7472 /* get output queue size */ +#define TIOCMGET 0x741d /* get termios flags */ +#define TIOCMSET 0x741a /* set termios flags */ + +/* + * ioctl calls specific to JTAG UART. + */ + +#define TIOCSTIMEOUT 0x6a01 /* Set Timeout before assuming no host present */ +#define TIOCGCONNECTED 0x6a02 /* Get indication of whether host is connected */ + +/* + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __IOCTL_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/termios.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/termios.h new file mode 100644 index 0000000..d271387 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/termios.h @@ -0,0 +1,181 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * This is the termios.h file provided with newlib. The only modification has + * been to the baud rate macro definitions, and an increase in the size of the + * termios structure to accomodate this. + */ + + +#ifndef _SYS_TERMIOS_H +# define _SYS_TERMIOS_H + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +# define _XCGETA (('x'<<8)|1) +# define _XCSETA (('x'<<8)|2) +# define _XCSETAW (('x'<<8)|3) +# define _XCSETAF (('x'<<8)|4) +# define _TCSBRK (('T'<<8)|5) +# define _TCFLSH (('T'<<8)|7) +# define _TCXONC (('T'<<8)|6) + +# define TCOOFF 0 +# define TCOON 1 +# define TCIOFF 2 +# define TCION 3 + +# define TCIFLUSH 0 +# define TCOFLUSH 1 +# define TCIOFLUSH 2 + +# define NCCS 13 + +# define TCSAFLUSH _XCSETAF +# define TCSANOW _XCSETA +# define TCSADRAIN _XCSETAW +# define TCSADFLUSH _XCSETAF + +# define IGNBRK 000001 +# define BRKINT 000002 +# define IGNPAR 000004 +# define INPCK 000020 +# define ISTRIP 000040 +# define INLCR 000100 +# define IGNCR 000200 +# define ICRNL 000400 +# define IXON 002000 +# define IXOFF 010000 + +# define OPOST 000001 +# define OCRNL 000004 +# define ONLCR 000010 +# define ONOCR 000020 +# define TAB3 014000 + +# define CLOCAL 004000 +# define CREAD 000200 +# define CSIZE 000060 +# define CS5 0 +# define CS6 020 +# define CS7 040 +# define CS8 060 +# define CSTOPB 000100 +# define HUPCL 002000 +# define PARENB 000400 +# define PAODD 001000 + +#define CCTS_OFLOW 010000 +#define CRTS_IFLOW 020000 +#define CRTSCTS (CCTS_OFLOW | CRTS_IFLOW) + +# define ECHO 0000010 +# define ECHOE 0000020 +# define ECHOK 0000040 +# define ECHONL 0000100 +# define ICANON 0000002 +# define IEXTEN 0000400 /* anybody know *what* this does?! */ +# define ISIG 0000001 +# define NOFLSH 0000200 +# define TOSTOP 0001000 + +# define VEOF 4 /* also VMIN -- thanks, AT&T */ +# define VEOL 5 /* also VTIME -- thanks again */ +# define VERASE 2 +# define VINTR 0 +# define VKILL 3 +# define VMIN 4 /* also VEOF */ +# define VQUIT 1 +# define VSUSP 10 +# define VTIME 5 /* also VEOL */ +# define VSTART 11 +# define VSTOP 12 + +# define B0 0 +# define B50 50 +# define B75 75 +# define B110 110 +# define B134 134 +# define B150 150 +# define B200 200 +# define B300 300 +# define B600 600 +# define B1200 1200 +# define B1800 1800 +# define B2400 2400 +# define B4800 4800 +# define B9600 9600 +# define B19200 19200 +# define B38400 38400 +# define B57600 57600 +# define B115200 115200 + +typedef unsigned char cc_t; +typedef unsigned short tcflag_t; +typedef unsigned long speed_t; + +struct termios { + tcflag_t c_iflag; + tcflag_t c_oflag; + tcflag_t c_cflag; + tcflag_t c_lflag; + char c_line; + cc_t c_cc[NCCS]; + speed_t c_ispeed; + speed_t c_ospeed; +}; + +# ifndef _NO_MACROS + +# define cfgetospeed(tp) ((tp)->c_ospeed) +# define cfgetispeed(tp) ((tp)->c_ispeed) +# define cfsetospeed(tp,s) (((tp)->c_ospeed = (s)), 0) +# define cfsetispeed(tp,s) (((tp)->c_ispeed = (s)), 0) +# define tcdrain(fd) _ioctl (fd, _TCSBRK, 1) +# endif /* _NO_MACROS */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_TERMIOS_H */ + diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_alarm_start.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_alarm_start.c new file mode 100644 index 0000000..2bd672f --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_alarm_start.c @@ -0,0 +1,112 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/alt_alarm.h" +#include "sys/alt_irq.h" + +/* + * alt_alarm_start is called to register an alarm with the system. The + * "alarm" structure passed as an input argument does not need to be + * initialised by the user. This is done within this function. + * + * The remaining input arguments are: + * + * nticks - The time to elapse until the alarm executes. This is specified in + * system clock ticks. + * callback - The function to run when the indicated time has elapsed. + * context - An opaque value, passed to the callback function. +* + * Care should be taken when defining the callback function since it is + * likely to execute in interrupt context. In particular, this mean that + * library calls like printf() should not be made, since they can result in + * deadlock. + * + * The interval to be used for the next callback is the return + * value from the callback function. A return value of zero indicates that the + * alarm should be unregistered. + * + * alt_alarm_start() will fail if the timer facility has not been enabled + * (i.e. there is no system clock). Failure is indicated by a negative return + * value. + */ + +int alt_alarm_start (alt_alarm* alarm, alt_u32 nticks, + alt_u32 (*callback) (void* context), + void* context) +{ + alt_irq_context irq_context; + alt_u32 current_nticks = 0; + + if (alt_ticks_per_second ()) + { + if (alarm) + { + alarm->callback = callback; + alarm->context = context; + + irq_context = alt_irq_disable_all (); + + current_nticks = alt_nticks(); + + alarm->time = nticks + current_nticks + 1; + + /* + * If the desired alarm time causes a roll-over, set the rollover + * flag. This will prevent the subsequent tick event from causing + * an alarm too early. + */ + if(alarm->time < current_nticks) + { + alarm->rollover = 1; + } + else + { + alarm->rollover = 0; + } + + alt_llist_insert (&alt_alarm_list, &alarm->llist); + alt_irq_enable_all (irq_context); + + return 0; + } + else + { + return -EINVAL; + } + } + else + { + return -ENOTSUP; + } +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_busy_sleep.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_busy_sleep.c new file mode 100644 index 0000000..1b910a5 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_busy_sleep.c @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2003-2004 Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * ------------ + * + * Altera does not recommend, suggest or require that this reference design + * file be used in conjunction or combination with any other product. + * + * alt_busy_sleep.c - Microsecond delay routine which uses a calibrated busy + * loop to perform the delay. This is used to implement + * usleep for both uC/OS-II and the standalone HAL. + * + * Author PRR + * + * Calibrated delay with no timer required + * + * The ASM instructions in the routine are equivalent to + * + * for (i=0;i +#include + +#include "system.h" +#include "alt_types.h" + +#include "priv/alt_busy_sleep.h" + +unsigned int alt_busy_sleep (unsigned int us) +{ +/* + * Only delay if ALT_SIM_OPTIMIZE is not defined; i.e., if software + * is built targetting ModelSim RTL simulation, the delay will be + * skipped to speed up simulation. + */ +#ifndef ALT_SIM_OPTIMIZE + int i; + int big_loops; + alt_u32 cycles_per_loop; + + if (!strcmp(NIOS2_CPU_IMPLEMENTATION,"tiny")) + { + cycles_per_loop = 9; + } + else + { + cycles_per_loop = 3; + } + + + big_loops = us / (INT_MAX/ + (ALT_CPU_FREQ/(cycles_per_loop * 1000000))); + + if (big_loops) + { + for(i=0;i + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +#ifdef ALT_USE_DIRECT_DRIVERS + +int ALT_CLOSE (int fildes) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(close); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +/* + * close() is called by an application to release a file descriptor. If the + * associated file system/device has a close() callback function registered + * then this called. The file descriptor is then marked as free. + * + * ALT_CLOSE is mapped onto the close() system call in alt_syscall.h + */ + +int ALT_CLOSE (int fildes) +{ + alt_fd* fd; + int rval; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (fildes < 0) ? NULL : &alt_fd_list[fildes]; + + if (fd) + { + /* + * If the associated file system/device has a close function, call it so + * that any necessary cleanup code can run. + */ + + rval = (fd->dev->close) ? fd->dev->close(fd) : 0; + + /* Free the file descriptor structure and return. */ + + alt_release_fd (fildes); + if (rval < 0) + { + ALT_ERRNO = -rval; + return -1; + } + return 0; + } + else + { + ALT_ERRNO = EBADFD; + return -1; + } +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_dcache_flush.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dcache_flush.c new file mode 100644 index 0000000..4326634 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dcache_flush.c @@ -0,0 +1,70 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +#define ALT_FLUSH_DATA(i) __asm__ volatile ("flushda (%0)" :: "r" (i)); + +/* + * alt_dcache_flush() is called to flush the data cache for a memory + * region of length "len" bytes, starting at address "start". + * + * Any dirty lines in the data cache are written back to memory. + */ + +void alt_dcache_flush (void* start, alt_u32 len) +{ +#if NIOS2_DCACHE_SIZE > 0 + + char* i; + char* end = ((char*) start) + len; + + for (i = start; i < end; i+= NIOS2_DCACHE_LINE_SIZE) + { + ALT_FLUSH_DATA(i); + } + + /* + * For an unaligned flush request, we've got one more line left. + * Note that this is dependent on NIOS2_DCACHE_LINE_SIZE to be a + * multiple of 2 (which it always is). + */ + + if (((alt_u32) start) & (NIOS2_DCACHE_LINE_SIZE - 1)) + { + ALT_FLUSH_DATA(i); + } + +#endif /* NIOS2_DCACHE_SIZE > 0 */ +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_dcache_flush_all.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dcache_flush_all.c new file mode 100644 index 0000000..80735b7 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dcache_flush_all.c @@ -0,0 +1,51 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +/* + * alt_dcache_flush_all() is called to flush the entire data cache. + */ + +void alt_dcache_flush_all (void) +{ +#if NIOS2_DCACHE_SIZE > 0 + char* i; + + for (i = (char*) 0; i < (char*) NIOS2_DCACHE_SIZE; i+= NIOS2_DCACHE_LINE_SIZE) + { + __asm__ volatile ("flushd (%0)" :: "r" (i)); + } +#endif /* NIOS2_DCACHE_SIZE > 0 */ +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_dcache_flush_no_writeback.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dcache_flush_no_writeback.c new file mode 100644 index 0000000..76b1618 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dcache_flush_no_writeback.c @@ -0,0 +1,69 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +#define ALT_FLUSH_DATA_NO_WRITEBACK(i) \ + __asm__ volatile ("initda (%0)" :: "r" (i)); + +/* + * alt_dcache_flush_no_writeback() is called to flush the data cache for a + * memory region of length "len" bytes, starting at address "start". + * + * Any dirty lines in the data cache are NOT written back to memory. + * Make sure you really want this behavior. If you aren't 100% sure, + * use the alt_dcache_flush() routine instead. + */ + +void alt_dcache_flush_no_writeback (void* start, alt_u32 len) +{ + char* i; + char* end = ((char*) start) + len; + + for (i = start; i < end; i+= NIOS2_DCACHE_LINE_SIZE) + { + ALT_FLUSH_DATA_NO_WRITEBACK(i); + } + + /* + * For an unaligned flush request, we've got one more line left. + * Note that this is dependent on NIOS2_DCACHE_LINE_SIZE to be a + * multiple of 2 (which it always is). + */ + + if (((alt_u32) start) & (NIOS2_DCACHE_LINE_SIZE - 1)) + { + ALT_FLUSH_DATA_NO_WRITEBACK(i); + } +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_dev.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dev.c new file mode 100644 index 0000000..92f3f2a --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dev.c @@ -0,0 +1,149 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +#include "alt_types.h" + +#include "system.h" + +/* + * This file contains the data constructs used to control access to device and + * filesytems. + */ + +/* + * "alt_fs_list" is the head of a linked list of registered filesystems. It is + * initialised as an empty list. New entries can be added using the + * alt_fs_reg() function. + */ + +ALT_LLIST_HEAD(alt_fs_list); + + +/* + * "alt_dev_list" is the head of a linked list of registered devices. It is + * configured at startup to include a single device, "alt_dev_null". This + * device is discussed below. + */ + +extern alt_dev alt_dev_null; /* forward declaration */ + +alt_llist alt_dev_list = {&alt_dev_null.llist, &alt_dev_null.llist}; + +/* + * alt_dev_null_write() is the implementation of the write() function used + * by the alt_dev_null device. It simple discards all data passed to it, and + * indicates that the data has been successfully transmitted. + */ + +static int alt_dev_null_write (alt_fd* fd, const char* ptr, int len) +{ + return len; +} + +/* + * "alt_dev_null" is used to allow output to be redirected to nowhere. It is + * the only device registered before the call to alt_sys_init(). At startup + * stin, stdout & stderr are all directed towards this device so that library + * calls like printf() will be safe but inefectual. + */ + +alt_dev alt_dev_null = { + { + &alt_dev_list, + &alt_dev_list + }, + "/dev/null", + NULL, /* open */ + NULL, /* close */ + NULL, /* write */ + alt_dev_null_write, /* write */ + NULL, /* lseek */ + NULL, /* fstat */ + NULL /* ioctl */ + }; + +/* + * "alt_fd_list_lock" is a semaphore used to control access to the file + * descriptor list. This is used to ensure that access to the list is thread + * safe. + */ + +ALT_SEM(alt_fd_list_lock) + +/* + * "alt_max_fd" is used to make access to the file descriptor list more + * efficent. It is set to be the value of the highest allocated file + * descriptor. This saves having to search the entire pool of unallocated + * file descriptors when looking for a match. + */ + +alt_32 alt_max_fd = -1; + +/* + * "alt_fd_list" is the file descriptor pool. The first three entries in the + * array are configured as standard in, standard out, and standard error. These + * are all initialised so that accesses are directed to the alt_dev_null + * device. The remaining file descriptors are initialised as unallocated. + * + * The maximum number of file descriptors within the system is specified by the + * user defined macro "ALT_MAX_FD". This is defined in "system.h", which is + * auto-genereated using the projects PTF and STF files. + */ + +alt_fd alt_fd_list[ALT_MAX_FD] = + { + { + &alt_dev_null, /* standard in */ + 0, + 0 + }, + { + &alt_dev_null, /* standard out */ + 0, + 0 + }, + { + &alt_dev_null, /* standard error */ + 0, + 0 + } + /* all other elements are set to zero */ + }; diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_dev_llist_insert.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dev_llist_insert.c new file mode 100644 index 0000000..5e8a952 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dev_llist_insert.c @@ -0,0 +1,59 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "priv/alt_dev_llist.h" +#include "sys/alt_errno.h" + +/* + * + */ + +int alt_dev_llist_insert (alt_dev_llist* dev, alt_llist* list) +{ + /* + * check that the device exists, and that it has a valid name. + */ + + if (!dev || !dev->name) + { + ALT_ERRNO = EINVAL; + return -EINVAL; + } + + /* + * register the device. + */ + + alt_llist_insert(list, &dev->llist); + + return 0; +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_dma_rxchan_open.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dma_rxchan_open.c new file mode 100644 index 0000000..5d461d9 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dma_rxchan_open.c @@ -0,0 +1,63 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_dma.h" +#include "sys/alt_errno.h" +#include "priv/alt_file.h" + +/* + * The list of registered DMA receive channels. + */ + +ALT_LLIST_HEAD(alt_dma_rxchan_list); + +/* + * alt_dma_txchan_open() is used to obtain an "alt_dma_txchan" descriptor for + * a DMA transmit device. The name is the name of the associated physical + * device (e.g. "/dev/dma_0"). + * + * The return value will be NULL on failure, and non-NULL otherwise. + */ + +alt_dma_rxchan alt_dma_rxchan_open (const char* name) +{ + alt_dma_rxchan dev; + + dev = (alt_dma_rxchan) alt_find_dev (name, &alt_dma_rxchan_list); + + if (!dev) + { + ALT_ERRNO = ENODEV; + } + + return dev; +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_dma_txchan_open.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dma_txchan_open.c new file mode 100644 index 0000000..99f9181 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dma_txchan_open.c @@ -0,0 +1,63 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_dma.h" +#include "sys/alt_errno.h" +#include "priv/alt_file.h" + +/* + * The list of registered receive channels. + */ + +ALT_LLIST_HEAD(alt_dma_txchan_list); + +/* + * alt_dma_txchan_open() is used to obtain an "alt_dma_txchan" descriptor for + * a DMA transmit device. The name is the name of the associated physical + * device (e.g. "/dev/dma_0"). + * + * The return value will be NULL on failure, and non-NULL otherwise. + */ + +alt_dma_txchan alt_dma_txchan_open (const char* name) +{ + alt_dma_txchan dev; + + dev = (alt_dma_txchan) alt_find_dev (name, &alt_dma_txchan_list); + + if (!dev) + { + ALT_ERRNO = ENODEV; + } + + return dev; +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_do_ctors.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_do_ctors.c new file mode 100644 index 0000000..be1c134 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_do_ctors.c @@ -0,0 +1,64 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT IT DIRECTLY. * +* * +* Overriding HAL Functions * +* * +* To provide your own implementation of a HAL function, include the file in * +* your Nios II IDE application project. When building the executable, the * +* Nios II IDE finds your function first, and uses it in place of the HAL * +* version. * +* * +******************************************************************************/ + +/* + * + */ + +typedef void (*constructor) (void); +extern constructor __CTOR_LIST__[]; +extern constructor __CTOR_END__[]; + +/* + * Run the C++ static constructors. + */ + +void _do_ctors(void) +{ + constructor* ctor; + + for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--) + (*ctor) (); +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_do_dtors.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_do_dtors.c new file mode 100644 index 0000000..b61166a --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_do_dtors.c @@ -0,0 +1,64 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT IT DIRECTLY. * +* * +* Overriding HAL Functions * +* * +* To provide your own implementation of a HAL function, include the file in * +* your Nios II IDE application project. When building the executable, the * +* Nios II IDE finds your function first, and uses it in place of the HAL * +* version. * +* * +******************************************************************************/ + +/* + * + */ + +typedef void (*destructor) (void); +extern destructor __DTOR_LIST__[]; +extern destructor __DTOR_END__[]; + +/* + * Run the C++ static destructors. + */ + +void _do_dtors(void) +{ + destructor* dtor; + + for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--) + (*dtor) (); +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_ecc_fatal_entry.S b/FPGA_nios/hit_pat_bsp/HAL/src/alt_ecc_fatal_entry.S new file mode 100644 index 0000000..43fedc0 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_ecc_fatal_entry.S @@ -0,0 +1,102 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2013 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This is the code called at the beginning of the exception handler + * to detect a likely fatal ECC error exception and then jump to + * user-provided code to handle it. + * + * This code is pulled in from a .globl in alt_ecc_fatal_exception.c. + * This scheme is used so that if a handler is never registered, then this + * code will not appear in the generated executable, thereby improving + * code footprint. + * + * This code is located in its own section that the linker script + * explicitly mentions and ensures it gets linked at the beginning + * of the exception handler. + */ + + /* + * Pull in the exception handler register save code. + */ + .globl alt_exception + + .section .exceptions.entry.ecc_fatal, "xa" + + /* + * This might be handling an unrecoverable ECC error exception + * in the register file and/or data cache. + * Must avoid reading registers or performing load/store instructions + * before this is determined because they could trigger another + * unrecoverable ECC error exception and create an infinite loop. + * + * The EXCEPTION register is always present when ECC is present. + * Bit 31 of this register indicates that there was an unrecoverable + * ECC error exception in the register file and/or data cache. + * Test this (using blt to check sign bit) to determine if this is + * what we are dealing with. Otherwise, just do normal processing. + * + * Jump to an application-provided routine to handle this condition. + * Pass in the return address in the et register in case this code + * can clean up the ECC error and then return here (unlikely). + * + * Runtime stack checking can't be enabled when ECC is present + * because they both want to use the et register. + */ + rdctl et, exception + bge et, r0, alt_exception_not_ecc_fatal /* Not ECCFTL if bit 31 is 0 */ + + /* + * Load ECC fatal handler pointer into et register. + * Using a ldwio is safe because it completely bypasses the data cache. + */ + movhi et, %hi(alt_exception_ecc_fatal_handler) + ori et, et, %lo(alt_exception_ecc_fatal_handler) + ldwio et, 0(et) + + /* + * If ECC fatal handler pointer is not 0, assume a handler + * has been provided by the application. + */ + beq et, r0, alt_exception_not_ecc_fatal + + /* + * The et register contains the address of the ECC fatal handler. + * Jump to this address to invoke the handler. + */ + jmp et + + /* + * An ECC fatal handler can jump to this label if it able + * to recover from the fatal error (rare) and wants to continue + * with normal exception processing. + */ +.globl alt_exception_not_ecc_fatal +alt_exception_not_ecc_fatal: diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_ecc_fatal_exception.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_ecc_fatal_exception.c new file mode 100644 index 0000000..9d40ff5 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_ecc_fatal_exception.c @@ -0,0 +1,75 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2013 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ +#include "io.h" +#include "sys/alt_exceptions.h" +#include "sys/alt_cache.h" + +/* + * This file implements support for calling a user-registered handler + * when a likely fatal ECC error exception occurs. + */ + +/* + * Global variable containing address to jump to when likely fatal + * ECC error exception occurs. + */ +alt_u32 alt_exception_ecc_fatal_handler = 0x0; + +/* + * Pull in the exception entry assembly code. This will not be linked in + * unless this object is linked into the executable (i.e. only if + * alt_ecc_fatal_exception_register() is called). + */ +__asm__( "\n\t.globl alt_exception" ); + +/* + * alt_ecc_fatal_exception_register() is called to register a handler to + * service likely fatal ECC error exceptions. + * + * Passing null (0x0) in the handler argument will disable a previously- + * registered handler. + * + * Note that if no handler is registered, just normal exception processing + * occurs on a likely fatal ECC exception and the exception processing + * code might trigger an infinite exception loop. + */ +void +alt_ecc_fatal_exception_register(alt_u32 handler) +{ + alt_exception_ecc_fatal_handler = handler; + + /* + * Flush this from the cache. Required because the exception handler uses ldwio + * to read this value to avoid trigger another data cache ECC error exception. + */ + alt_dcache_flush(&alt_exception_ecc_fatal_handler, sizeof(alt_exception_ecc_fatal_handler)); +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_environ.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_environ.c new file mode 100644 index 0000000..780635a --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_environ.c @@ -0,0 +1,42 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "os/alt_syscall.h" + +/* + * These are the environment variables passed to the C code. By default there + * are no variables registered. An application can manipulate this list using + * getenv() and setenv(). + */ + +char *__env[1] = { 0 }; +char **ALT_ENVIRON = __env; diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_errno.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_errno.c new file mode 100644 index 0000000..4c5ca3e --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_errno.c @@ -0,0 +1,44 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* + * This file defines the alt_errno global variable. See comments in + * alt_errno.h for the use of this variable. + */ + + +#include "sys/alt_errno.h" +#include "alt_types.h" + +extern int ALT_WEAK *__errno (void); + +int* (*alt_errno) (void) = __errno; diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_exception_entry.S b/FPGA_nios/hit_pat_bsp/HAL/src/alt_exception_entry.S new file mode 100644 index 0000000..3740a0d --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_exception_entry.S @@ -0,0 +1,402 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "system.h" + +/* + * This is the exception entry point code, which saves all the caller saved + * registers and then handles the appropriate exception. It should be pulled + * in using a .globl from all the exception handler routines. This scheme is + * used so that if an interrupt is never registered, then this code will not + * appear in the generated executable, thereby improving code footprint. + * + * If an external interrpt controller (EIC) is present, it will supply an + * interrupt vector address to the processor when an interrupt occurs. For + * The Altera Vectored Interrupt Controller (VIC) driver will establish a + * vector table and the processor will jump directly to the appropriate + * table entry, funnel routine, and then user ISR. This will bypass this code + * in entirety. This code might still be linked into a system with an EIC, + * but would then be used only for non-interrupt exceptions. + */ + + /* + * Explicitly allow the use of r1 (the assembler temporary register) + * within this code. This register is normally reserved for the use of + * the assembler. + */ + .set noat + + /* + * The top and bottom of the exception stack. + */ +#ifdef ALT_EXCEPTION_STACK + .globl __alt_exception_stack_pointer + +#ifdef ALT_STACK_CHECK + .globl __alt_exception_stack_limit + + /* + * Store the value of the stack limit after interrupt somewhere. + */ + .globl alt_exception_old_stack_limit +#endif /* ALT_STACK_CHECK */ +#endif /* ALT_EXCEPTION_STACK */ + +/* + * The code at alt_exception is located at the Nios II exception + * handler address. + */ + .section .exceptions.entry.label, "xa" + .globl alt_exception + .type alt_exception, @function +alt_exception: + + /* + * The code for detecting a likely fatal ECC exception is + * linked here before the normal exception handler code if required. + * This is handled by the linker script and putting that code + * in the .exceptions.entry.ecc_fatal section. + */ + + /* + * Now start the normal exception handler code. + */ + .section .exceptions.entry, "xa" + +#ifdef ALT_EXCEPTION_STACK +#ifdef ALT_STACK_CHECK + /* + * When runtime stack checking is enabled, the et register + * contains the stack limit. Save this in memory before + * overwriting the et register. + */ + stw et, %gprel(alt_exception_old_stack_limit)(gp) +#endif /* ALT_STACK_CHECK */ + + /* + * Switch to the exception stack and save the current stack pointer + * in memory. Uses the et register as a scratch register. + */ + movhi et, %hi(__alt_exception_stack_pointer - 80) + ori et, et, %lo(__alt_exception_stack_pointer - 80) + stw sp, 76(et) + mov sp, et + +#ifdef ALT_STACK_CHECK + /* + * Restore the stack limit from memory to the et register. + */ + movhi et, %hi(__alt_exception_stack_limit) + ori et, et, %lo(__alt_exception_stack_limit) + stw et, %gprel(alt_stack_limit_value)(gp) +#endif /* ALT_STACK_CHECK */ + +#else /* ALT_EXCEPTION_STACK disabled */ + /* + * Reserve space on normal stack for registers about to be pushed. + */ + addi sp, sp, -76 + +#ifdef ALT_STACK_CHECK + /* Ensure stack didn't just overflow. */ + bltu sp, et, .Lstack_overflow +#endif /* ALT_STACK_CHECK */ + +#endif /* ALT_EXCEPTION_STACK */ + + /* + * Process an exception. For all exceptions we must preserve all + * caller saved registers on the stack (See the Nios II ABI + * documentation for details). + * + * Leave a gap in the stack frame at 4(sp) for the muldiv handler to + * store zero into. + */ + stw ra, 0(sp) + stw r1, 8(sp) + stw r2, 12(sp) + stw r3, 16(sp) + stw r4, 20(sp) + stw r5, 24(sp) + stw r6, 28(sp) + stw r7, 32(sp) + rdctl r5, estatus /* Read early to avoid usage stall */ + stw r8, 36(sp) + stw r9, 40(sp) + stw r10, 44(sp) + stw r11, 48(sp) + stw r12, 52(sp) + stw r13, 56(sp) + stw r14, 60(sp) + stw r15, 64(sp) + + /* + * ea-4 contains the address of the instruction being executed + * when the exception occured. For interrupt exceptions, we will + * will be re-issue the isntruction. Store it in 72(sp) + */ + stw r5, 68(sp) /* estatus */ + addi r15, ea, -4 /* instruction that caused exception */ + stw r15, 72(sp) + + /* + * The interrupt testing code (.exceptions.irqtest) will be + * linked here. If the Internal Interrupt Controller (IIC) is + * present (an EIC is not present), the presense of an interrupt + * is determined by examining CPU control registers or an interrupt + * custom instruction, if present. + * + * If the IIC is used and an interrupt is active, the code linked + * here will call the HAL IRQ handler (alt_irq_handler()) which + * successively calls registered interrupt handler(s) until no + * interrupts remain pending. It then jumps to .exceptions.exit. If + * there is no interrupt then it continues to .exception.notirq, below. + */ + + .section .exceptions.notirq, "xa" + + /* + * Prepare to service unimplemtned instructions or traps, + * each of which is optionally inked into section .exceptions.soft, + * which will preceed .exceptions.unknown below. + * + * Unlike interrupts, we want to skip the exception-causing instructon + * upon completion, so we write ea (address of instruction *after* + * the one where the exception occured) into 72(sp). The actual + * instruction that caused the exception is written in r2, which these + * handlers will utilize. + */ + stw ea, 72(sp) /* EA is PC+4 so will skip over instruction causing exception */ + +#ifdef NIOS2_CDX_PRESENT + mov.n r4, ea /* EA contains PC+4 of instruction that caused the exception */ + subi.n r4, r4, 4 /* Calculate PC */ + ldhu.n r2, 0(r4) /* Load least-significant 16 bits of instruction */ + andi r5, r2, 0x7 /* Mask off all bits except the 3 most-significant bits of OP field */ + + /* + * These instructions compare the MSB 3 bits of OP to 0x1, 0x3, and 0x5 + * which is where all the 16-bit instructions live. + */ + subi.n r5, r5, 1 + beqz.n r5, .Lunknown_16bit + subi.n r5, r5, 2 + beqz.n r5, .Lunknown_16bit + subi.n r5, r5, 2 + beqz.n r5, .Lunknown_16bit + +.Lunknown_32bit: + stw ea, 72(sp) /* EA is PC+4 so will skip over instruction causing exception */ + + /* Load most-significant 16 bits of instruction */ + ldhu.n r3, 2(r4) + slli.n r3, r3, 16 + or.n r2, r2, r3 /* 32-bit instruction value that caused exception */ + br.n .Lunknown_inst_loaded + +.Lunknown_16bit: + addi.n r4, r4, 2 /* Need PC+2 to skip over instruction causing exception */ + stw r4, 72(sp) + +#else /* CDX is not Enabled and all instructions are 32bits */ + ldw r2, -4(ea) /* Instruction value that caused exception */ +#endif + +.Lunknown_inst_loaded: + + /* + * Other exception handling code, if enabled, will be linked here. + * This includes unimplemted (multiply/divide) instruction support + * (a BSP generaton option), and a trap handler (that would typically + * be augmented with user-specific code). These are not linked in by + * default. + */ + + /* + * In the context of linker sections, "unknown" are all exceptions + * not handled by the built-in handlers above (interupt, and trap or + * unimplemented instruction decoding, if enabled). + * + * Advanced exception types can be serviced by registering a handler. + * To do so, enable the "Enable Instruction-related Exception API" HAL + * BSP setting. If this setting is disabled, this handler code will + * either break (if the debug core is present) or enter an infinite + * loop because we don't how how to handle the exception. + */ + .section .exceptions.unknown +#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API + /* + * The C-based HAL routine alt_instruction_exception_entry() will + * attempt to service the exception by calling a user-registered + * exception handler using alt_instruction_exception_register(). + * If no handler was registered it will either break (if the + * debugger is present) or go into an infinite loop since the + * handling behavior is undefined; in that case we will not return here. + */ + + /* Load exception-causing address as first argument (r4) */ + addi r4, ea, -4 + + /* Call the instruction-exception entry */ + call alt_instruction_exception_entry + + /* + * If alt_instruction_exception_entry() returned, the exception was + * serviced by a user-registered routine. Its return code (now in r2) + * indicates whether to re-issue or skip the exception-causing + * instruction + * + * Return code was 0: Skip. The instruction after the exception is + * already stored in 72(sp). + */ + bne r2, r0, .Lexception_exit + + /* + * Otherwise, modify 72(sp) to re-issue the instruction that caused the + * exception. + */ + addi r15, ea, -4 /* instruction that caused exception */ + stw r15, 72(sp) + +#else /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API disabled */ + + /* + * We got here because an instruction-related exception occured, but the + * handler API was not compiled in. We do not presume to know how to + * handle it. If the debugger is present, break, otherwise hang. + * + * If you get here then one of the following could have happened: + * + * - An instruction-generated exception occured, and the processor + * does not have the extra exceptions feature enabled, or you + * have not registered a handler using + * alt_instruction_exception_register() + * + * Some examples of instruction-generated exceptions and why they + * might occur: + * + * - Your program could have been compiled for a full-featured + * Nios II core, but it is running on a smaller core, and + * instruction emulation has been disabled by defining + * ALT_NO_INSTRUCTION_EMULATION. + * + * You can work around the problem by re-enabling instruction + * emulation, or you can figure out why your program is being + * compiled for a system other than the one that it is running on. + * + * - Your program has executed a trap instruction, but has not + * implemented a handler for this instruction. + * + * - Your program has executed an illegal instruction (one which is + * not defined in the instruction set). + * + * - Your processor includes an MMU or MPU, and you have enabled it + * before registering an exception handler to service exceptions it + * generates. + * + * The problem could also be hardware related: + * - If your hardware is broken and is generating spurious interrupts + * (a peripheral which negates its interrupt output before its + * interrupt handler has been executed will cause spurious + * interrupts) + */ +alt_exception_unknown: +#ifdef NIOS2_HAS_DEBUG_STUB + /* + * Either tell the user now (if there is a debugger attached) or go into + * the debug monitor which will loop until a debugger is attached. + */ + break +#else /* NIOS2_HAS_DEBUG_STUB disabled */ + /* + * If there is no debug stub, an infinite loop is more useful. + */ + br alt_exception_unknown +#endif /* NIOS2_HAS_DEBUG_STUB */ +#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */ + + .section .exceptions.exit.label +.Lexception_exit: + + .section .exceptions.exit, "xa" + + /* + * Restore the saved registers, so that all general purpose registers + * have been restored to their state at the time the interrupt occured. + */ + + ldw r5, 68(sp) + ldw ea, 72(sp) /* This becomes the PC once eret is executed */ + ldw ra, 0(sp) + + wrctl estatus, r5 + + ldw r1, 8(sp) + ldw r2, 12(sp) + ldw r3, 16(sp) + ldw r4, 20(sp) + ldw r5, 24(sp) + ldw r6, 28(sp) + ldw r7, 32(sp) + +#if defined(ALT_EXCEPTION_STACK) && defined(ALT_STACK_CHECK) + ldw et, %gprel(alt_exception_old_stack_limit)(gp) +#endif + + ldw r8, 36(sp) + ldw r9, 40(sp) + ldw r10, 44(sp) + ldw r11, 48(sp) + ldw r12, 52(sp) + ldw r13, 56(sp) + ldw r14, 60(sp) + ldw r15, 64(sp) + +#ifdef ALT_EXCEPTION_STACK +#ifdef ALT_STACK_CHECK + stw et, %gprel(alt_stack_limit_value)(gp) + stw zero, %gprel(alt_exception_old_stack_limit)(gp) +#endif /* ALT_STACK_CHECK */ + ldw sp, 76(sp) +#else /* ALT_EXCEPTION_STACK disabled */ + addi sp, sp, 76 +#endif /* ALT_EXCEPTION_STACK */ + + /* + * Return to the interrupted instruction. + */ + + eret + +#ifdef ALT_STACK_CHECK +.Lstack_overflow: + break 3 +#endif /* ALT_STACK_CHECK */ + diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_exception_muldiv.S b/FPGA_nios/hit_pat_bsp/HAL/src/alt_exception_muldiv.S new file mode 100644 index 0000000..6a794a3 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_exception_muldiv.S @@ -0,0 +1,583 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + + /* + * This is the software multiply/divide handler for Nios2. + */ + + /* + * Provide a label which can be used to pull this file in. + */ + + .section .exceptions.start + .globl alt_exception_muldiv +alt_exception_muldiv: + + /* + * Pull in the entry/exit code. + */ + .globl alt_exception + + + .section .exceptions.soft, "xa" + + + /* INSTRUCTION EMULATION + * --------------------- + * + * Nios II processors generate exceptions for unimplemented instructions. + * The routines below emulate these instructions. Depending on the + * processor core, the only instructions that might need to be emulated + * are div, divu, mul, muli, mulxss, mulxsu, and mulxuu. + * + * The emulations match the instructions, except for the following + * limitations: + * + * 1) The emulation routines do not emulate the use of the exception + * temporary register (et) as a source operand because the exception + * handler already has modified it. + * + * 2) The routines do not emulate the use of the stack pointer (sp) or the + * exception return address register (ea) as a destination because + * modifying these registers crashes the exception handler or the + * interrupted routine. + * + * 3) To save code size, the routines do not emulate the use of the + * breakpoint registers (ba and bt) as operands. + * + * Detailed Design + * --------------- + * + * The emulation routines expect the contents of integer registers r0-r31 + * to be on the stack at addresses sp, 4(sp), 8(sp), ... 124(sp). The + * routines retrieve source operands from the stack and modify the + * destination register's value on the stack prior to the end of the + * exception handler. Then all registers except the destination register + * are restored to their previous values. + * + * The instruction that causes the exception is found at address -4(ea). + * The instruction's OP and OPX fields identify the operation to be + * performed. + * + * One instruction, muli, is an I-type instruction that is identified by + * an OP field of 0x24. + * + * muli AAAAA,BBBBB,IIIIIIIIIIIIIIII,-0x24- + * 27 22 6 0 <-- LSB of field + * + * The remaining emulated instructions are R-type and have an OP field + * of 0x3a. Their OPX fields identify them. + * + * R-type AAAAA,BBBBB,CCCCC,XXXXXX,NNNNN,-0x3a- + * 27 22 17 11 6 0 <-- LSB of field + * + * + */ + + + /* + * Split the instruction into its fields. We need 4*A, 4*B, and 4*C as + * offsets to the stack pointer for access to the stored register values. + */ + /* r2 = AAAAA,BBBBB,IIIIIIIIIIIIIIII,PPPPPP */ + roli r3, r2, 7 /* r3 = BBB,IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BB */ + roli r4, r3, 3 /* r4 = IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB */ + roli r6, r4, 2 /* r6 = IIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB,II */ + srai r4, r4, 16 /* r4 = (sign-extended) IMM16 */ + xori r6, r6, 0x42 /* r6 = CCC,XXXXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cC */ + roli r7, r6, 5 /* r7 = XXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cCCCC,XX */ + andi r5, r2, 0x3f /* r5 = 00000000000000000000000000,PPPPPP */ + xori r3, r3, 0x40 + andi r3, r3, 0x7c /* r3 = 0000000000000000000000000,aAAAA,00 */ + andi r6, r6, 0x7c /* r6 = 0000000000000000000000000,bBBBB,00 */ + andi r7, r7, 0x7c /* r7 = 0000000000000000000000000,cCCCC,00 */ + + /* Now either + * r5 = OP + * r3 = 4*(A^16) + * r4 = IMM16 (sign extended) + * r6 = 4*(B^16) + * r7 = 4*(C^16) + * or + * r5 = OP + */ + + + /* + * Save everything on the stack to make it easy for the emulation routines + * to retrieve the source register operands. The exception entry code has + * already saved some of this so we don't need to do it all again. + */ + + addi sp, sp, -60 + stw zero, 64(sp) /* Save zero on stack to avoid special case for r0. */ + /* Register at and r2-r15 have already been saved. */ + + stw r16, 0(sp) + stw r17, 4(sp) + stw r18, 8(sp) + stw r19, 12(sp) + stw r20, 16(sp) + stw r21, 20(sp) + stw r22, 24(sp) + stw r23, 28(sp) + /* et @ 32 - Has already been changed.*/ + /* bt @ 36 - Usually isn't an operand. */ + stw gp, 40(sp) + stw sp, 44(sp) + stw fp, 48(sp) + /* ea @ 52 - Don't bother to save - it's already been changed */ + /* ba @ 56 - Breakpoint register usually isn't an operand */ + /* ra @ 60 - Has already been saved */ + + + /* + * Prepare for either multiplication or division loop. + * They both loop 32 times. + */ + movi r14, 32 + + + /* + * Get the operands. + * + * It is necessary to check for muli because it uses an I-type instruction + * format, while the other instructions are have an R-type format. + */ + add r3, r3, sp /* r3 = address of A-operand. */ + ldw r3, 0(r3) /* r3 = A-operand. */ + movi r15, 0x24 /* muli opcode (I-type instruction format) */ + beq r5, r15, .Lmul_immed /* muli doesn't use the B register as a source */ + + add r6, r6, sp /* r6 = address of B-operand. */ + ldw r6, 0(r6) /* r6 = B-operand. */ + /* r4 = SSSSSSSSSSSSSSSS,-----IMM16------ */ + /* IMM16 not needed, align OPX portion */ + /* r4 = SSSSSSSSSSSSSSSS,CCCCC,-OPX--,00000 */ + srli r4, r4, 5 /* r4 = 00000,SSSSSSSSSSSSSSSS,CCCCC,-OPX-- */ + andi r4, r4, 0x3f /* r4 = 00000000000000000000000000,-OPX-- */ + + /* Now + * r5 = OP + * r3 = src1 + * r6 = src2 + * r4 = OPX (no longer can be muli) + * r7 = 4*(C^16) + * r14 = loop counter + */ + + /* ILLEGAL-INSTRUCTION EXCEPTION + * ----------------------------- + * + * This code is for Nios II cores that generate exceptions when attempting + * to execute illegal instructions. Nios II cores that support an + * illegal-instruction exception are identified by the presence of the + * macro definition NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION in system.h . + * + * Remember that illegal instructions are different than unimplemented + * instructions. Illegal instructions are instruction encodings that + * have not been defined by the Nios II ISA. Unimplemented instructions + * are legal instructions that must be emulated by some Nios II cores. + * + * If we get here, all instructions except multiplies and divides + * are illegal. + * + * This code assumes that OP is not muli (because muli was tested above). + * All other multiplies and divides are legal. Anything else is illegal. + */ + + movi r8, 0x3a /* OP for R-type mul* and div* */ + bne r5, r8, .Lnot_muldiv + + /* r15 already is 0x24 */ /* OPX of divu */ + beq r4, r15, .Ldivide + + movi r15,0x27 /* OPX of mul */ + beq r4, r15, .Lmultiply + + movi r15,0x07 /* OPX of mulxuu */ + beq r4, r15, .Lmultiply + + movi r15,0x17 /* OPX of mulxsu */ + beq r4, r15, .Lmultiply + + movi r15,0x1f /* OPX of mulxss */ + beq r4, r15, .Lmultiply + + movi r15,0x25 /* OPX of div */ + bne r4, r15, .Lnot_muldiv + + + /* DIVISION + * + * Divide an unsigned dividend by an unsigned divisor using + * a shift-and-subtract algorithm. The example below shows + * 43 div 7 = 6 for 8-bit integers. This classic algorithm uses a + * single register to store both the dividend and the quotient, + * allowing both values to be shifted with a single instruction. + * + * remainder dividend:quotient + * --------- ----------------- + * initialize 00000000 00101011: + * shift 00000000 0101011:_ + * remainder >= divisor? no 00000000 0101011:0 + * shift 00000000 101011:0_ + * remainder >= divisor? no 00000000 101011:00 + * shift 00000001 01011:00_ + * remainder >= divisor? no 00000001 01011:000 + * shift 00000010 1011:000_ + * remainder >= divisor? no 00000010 1011:0000 + * shift 00000101 011:0000_ + * remainder >= divisor? no 00000101 011:00000 + * shift 00001010 11:00000_ + * remainder >= divisor? yes 00001010 11:000001 + * remainder -= divisor - 00000111 + * ---------- + * 00000011 11:000001 + * shift 00000111 1:000001_ + * remainder >= divisor? yes 00000111 1:0000011 + * remainder -= divisor - 00000111 + * ---------- + * 00000000 1:0000011 + * shift 00000001 :0000011_ + * remainder >= divisor? no 00000001 :00000110 + * + * The quotient is 00000110. + */ + +.Ldivide: + /* + * Prepare for division by assuming the result + * is unsigned, and storing its "sign" as 0. + */ + movi r17, 0 + + + /* Which division opcode? */ + xori r15, r4, 0x25 /* OPX of div */ + bne r15, zero, .Lunsigned_division + + + /* + * OPX is div. Determine and store the sign of the quotient. + * Then take the absolute value of both operands. + */ + xor r17, r3, r6 /* MSB contains sign of quotient */ + bge r3, zero, 0f + sub r3, zero, r3 /* -r3 */ +0: + bge r6, zero, 0f + sub r6, zero, r6 /* -r6 */ +0: + + +.Lunsigned_division: + /* Initialize the unsigned-division loop. */ + movi r13, 0 /* remainder = 0 */ + + /* Now + * r3 = dividend : quotient + * r4 = 0x25 for div, 0x24 for divu + * r6 = divisor + * r13 = remainder + * r14 = loop counter (already initialized to 32) + * r17 = MSB contains sign of quotient + */ + + + /* + * for (count = 32; count > 0; --count) + * { + */ +.Ldivide_loop: + + /* + * Division: + * + * (remainder:dividend:quotient) <<= 1; + */ + slli r13, r13, 1 + cmplt r15, r3, zero /* r15 = MSB of r3 */ + or r13, r13, r15 + slli r3, r3, 1 + + + /* + * if (remainder >= divisor) + * { + * set LSB of quotient + * remainder -= divisor; + * } + */ + bltu r13, r6, .Ldiv_skip + ori r3, r3, 1 + sub r13, r13, r6 +.Ldiv_skip: + + /* + * } + */ + subi r14, r14, 1 + bne r14, zero, .Ldivide_loop + + mov r9, r3 + + + /* Now + * r9 = quotient + * r4 = 0x25 for div, 0x24 for divu + * r7 = 4*(C^16) + * r17 = MSB contains sign of quotient + */ + + + /* + * Conditionally negate signed quotient. If quotient is unsigned, + * the sign already is initialized to 0. + */ + bge r17, zero, .Lstore_result + sub r9, zero, r9 /* -r9 */ + + br .Lstore_result + + + + + /* MULTIPLICATION + * + * A "product" is the number that one gets by summing a "multiplicand" + * several times. The "multiplier" specifies the number of copies of the + * multiplicand that are summed. + * + * Actual multiplication algorithms don't use repeated addition, however. + * Shift-and-add algorithms get the same answer as repeated addition, and + * they are faster. To compute the lower half of a product (pppp below) + * one shifts the product left before adding in each of the partial products + * (a * mmmm) through (d * mmmm). + * + * To compute the upper half of a product (PPPP below), one adds in the + * partial products (d * mmmm) through (a * mmmm), each time following the + * add by a right shift of the product. + * + * mmmm + * * abcd + * ------ + * #### = d * mmmm + * #### = c * mmmm + * #### = b * mmmm + * #### = a * mmmm + * -------- + * PPPPpppp + * + * The example above shows 4 partial products. Computing actual Nios II + * products requires 32 partials. + * + * It is possible to compute the result of mulxsu from the result of mulxuu + * because the only difference between the results of these two opcodes is + * the value of the partial product associated with the sign bit of rA. + * + * mulxsu = mulxuu - ((rA < 0) ? rB : 0); + * + * It is possible to compute the result of mulxss from the result of mulxsu + * because the only difference between the results of these two opcodes is + * the value of the partial product associated with the sign bit of rB. + * + * mulxss = mulxsu - ((rB < 0) ? rA : 0); + * + */ + +.Lmul_immed: + /* Opcode is muli. Change it into mul for remainder of algorithm. */ + mov r7, r6 /* Field B is dest register, not field C. */ + mov r6, r4 /* Field IMM16 is src2, not field B. */ + movi r4, 0x27 /* OPX of mul is 0x27 */ + +.Lmultiply: + /* Initialize the multiplication loop. */ + movi r9, 0 /* mul_product = 0 */ + movi r10, 0 /* mulxuu_product = 0 */ + mov r11, r6 /* save original multiplier for mulxsu and mulxss */ + mov r12, r6 /* mulxuu_multiplier (will be shifted) */ + movi r16, 1 /* used to create "rori B,A,1" from "ror B,A,r16" */ + + /* Now + * r3 = multiplicand + * r6 = mul_multiplier + * r7 = 4 * dest_register (used later as offset to sp) + * r9 = mul_product + * r10 = mulxuu_product + * r11 = original multiplier + * r12 = mulxuu_multiplier + * r14 = loop counter (already initialized) + * r15 = temp + * r16 = 1 + */ + + + /* + * for (count = 32; count > 0; --count) + * { + */ +.Lmultiply_loop: + + /* + * mul_product <<= 1; + * lsb = multiplier & 1; + */ + slli r9, r9, 1 + andi r15, r12, 1 + + /* + * if (lsb == 1) + * { + * mulxuu_product += multiplicand; + * } + */ + beq r15, zero, .Lmulx_skip + add r10, r10, r3 + cmpltu r15, r10, r3 /* Save the carry from the MSB of mulxuu_product. */ + ror r15, r15, r16 /* r15 = 0x80000000 on carry, or else 0x00000000 */ +.Lmulx_skip: + + /* + * if (MSB of mul_multiplier == 1) + * { + * mul_product += multiplicand; + * } + */ + bge r6, zero, .Lmul_skip + add r9, r9, r3 +.Lmul_skip: + + /* + * mulxuu_product >>= 1; logical shift + * mul_multiplier <<= 1; done with MSB + * mulx_multiplier >>= 1; done with LSB + */ + srli r10, r10, 1 + or r10, r10, r15 /* OR in the saved carry bit. */ + slli r6, r6, 1 + srli r12, r12, 1 + + + /* + * } + */ + subi r14, r14, 1 + bne r14, zero, .Lmultiply_loop + + + /* + * Multiply emulation loop done. + */ + + /* Now + * r3 = multiplicand + * r4 = OPX + * r7 = 4 * dest_register (used later as offset to sp) + * r9 = mul_product + * r10 = mulxuu_product + * r11 = original multiplier + * r15 = temp + */ + + + /* + * Select/compute the result based on OPX. + */ + + + /* OPX == mul? Then store. */ + xori r15, r4, 0x27 + beq r15, zero, .Lstore_result + + /* It's one of the mulx.. opcodes. Move over the result. */ + mov r9, r10 + + /* OPX == mulxuu? Then store. */ + xori r15, r4, 0x07 + beq r15, zero, .Lstore_result + + /* Compute mulxsu + * + * mulxsu = mulxuu - ((rA < 0) ? rB : 0); + */ + bge r3, zero, .Lmulxsu_skip + sub r9, r9, r11 +.Lmulxsu_skip: + + /* OPX == mulxsu? Then store. */ + xori r15, r4, 0x17 + beq r15, zero, .Lstore_result + + /* Compute mulxss + * + * mulxss = mulxsu - ((rB < 0) ? rA : 0); + */ + bge r11, zero, .Lmulxss_skip + sub r9, r9, r3 +.Lmulxss_skip: + /* At this point, assume that OPX is mulxss, so store */ + + +.Lstore_result: + add r7, r7, sp + stw r9, 0(r7) + + ldw r16, 0(sp) + ldw r17, 4(sp) + ldw r18, 8(sp) + ldw r19, 12(sp) + ldw r20, 16(sp) + ldw r21, 20(sp) + ldw r22, 24(sp) + ldw r23, 28(sp) + + /* bt @ 32 - Breakpoint register usually isn't an operand. */ + /* et @ 36 - Don't corrupt et. */ + /* gp @ 40 - Don't corrupt gp. */ + /* sp @ 44 - Don't corrupt sp. */ + ldw fp, 48(sp) + /* ea @ 52 - Don't corrupt ea. */ + /* ba @ 56 - Breakpoint register usually isn't an operand. */ + + addi sp, sp, 60 + + br .Lexception_exit + + +.Lnot_muldiv: + + addi sp, sp, 60 + + + .section .exceptions.exit.label +.Lexception_exit: + diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_exception_trap.S b/FPGA_nios/hit_pat_bsp/HAL/src/alt_exception_trap.S new file mode 100644 index 0000000..730e893 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_exception_trap.S @@ -0,0 +1,95 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + + /* + * This is the trap exception handler for Nios2. + */ + + /* + * Provide a label which can be used to pull this file in. + */ + + .section .exceptions.start + .globl alt_exception_trap +alt_exception_trap: + + /* + * Pull in the entry/exit code. + */ + .globl alt_exception + + .section .exceptions.soft, "xa" + +.Ltrap_handler: + + /* + * Did a trap instruction cause the exception? + * + * The instruction which the exception occurred on has been loaded + * into r2 by code in alt_exception_entry.S + * + */ + +#ifdef ALT_CPU_CPU_ARCH_NIOS2_R2 + movhi r3,0xb41d /* upper half of trap opcode */ + ori r3,r3,0x0020 /* lower half of trap opcode */ + beq r2,r3,.Lis_trap +#ifdef NIOS2_CDX_PRESENT + mov r3,r2 + andhi r3,r3,0xffff + ori r3,r3,0xd009 /* trap.n opcode */ + beq r2,r3,.Lis_trap +#endif + br .Lnot_trap +#else + movhi r3,0x003b /* upper half of trap opcode */ + ori r3,r3,0x683a /* lower half of trap opcode */ + bne r2,r3,.Lnot_trap +#endif + +.Lis_trap: + /* + * There is no trap handler defined here, and so executing a trap + * instruction causes a software break. If you provide a trap handler, + * then you must replace the break instruction below with your handler. + * Your handler must preserve ea and the usual callee saved registers. + */ + + break + + br .Lexception_exit + +.Lnot_trap: + + + .section .exceptions.exit.label +.Lexception_exit: + + diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_execve.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_execve.c new file mode 100644 index 0000000..51bfcc4 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_execve.c @@ -0,0 +1,55 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "os/alt_syscall.h" + +/* + * execve() is used by newlib to launch new processes. This is unsupported in + * the HAL environment. However a "do-nothing" implementation is still + * provied for newlib compatability. + * + * ALT_EXECVE is mapped onto the execve() system call in alt_syscall.h + */ + +int ALT_EXECVE (char *name, char ** argv, char** env) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(execve); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_exit.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_exit.c new file mode 100644 index 0000000..46cbe18 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_exit.c @@ -0,0 +1,71 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_irq.h" +#include "sys/alt_sim.h" +#include "os/alt_hooks.h" +#include "os/alt_syscall.h" + +#include "alt_types.h" +#include "sys/alt_log_printf.h" +/* + * _exit() is called by exit() in order to terminate the current process. + * Typically this is called when main() completes. It should never return. + * Since there is nowhere to go once this process completes, this + * implementation simply blocks forever. + * + * Note that interrupts are not disabled so that execution outside of this + * thread is allowed to continue. + * + * ALT_EXIT is mapped onto the _exit() system call in alt_syscall.h + */ + +void ALT_EXIT (int exit_code) +{ + /* ALT_LOG - please see HAL/inc/alt_log_printf.h for details */ + ALT_LOG_PRINT_BOOT("[alt_exit.c] Entering _exit() function.\r\n"); + ALT_LOG_PRINT_BOOT("[alt_exit.c] Exit code from main was %d.\r\n",exit_code); + /* Stop all other threads */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_OS_STOP().\r\n"); + ALT_OS_STOP(); + + /* Provide notification to the simulator that we've stopped */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_SIM_HALT().\r\n"); + ALT_SIM_HALT(exit_code); + + /* spin forever, since there's no where to go back to */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Spinning forever.\r\n"); + while (1); +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_fcntl.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_fcntl.c new file mode 100644 index 0000000..382fa43 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_fcntl.c @@ -0,0 +1,101 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include +#include + +#include "sys/alt_errno.h" +#include "priv/alt_file.h" +#include "alt_types.h" +#include "os/alt_syscall.h" + +#define ALT_FCNTL_FLAGS_MASK ((alt_u32) (O_APPEND | O_NONBLOCK)) + +/* + * fcntl() is a limited implementation of the standard fcntl() system call. + * It can be used to change the state of the flags associated with an open + * file descriptor. Normally these flags are set during the call to + * open(). It is anticipated that the main use of this function will be to + * change the state of a device from blocking to non-blocking (where this is + * supported). + * + * The input argument "fd" is the file descriptor to be manipulated. "cmd" + * is the command to execute. This can be either F_GETFL (return the + * current value of the flags) or F_SETFL (set the value of the flags). + * + * If "cmd" is F_SETFL then the argument "arg" is the new value of flags, + * otherwise "arg" is ignored. Only the flags: O_APPEND and O_NONBLOCK + * can be updated by a call to fcntl(). All other flags remain + * unchanged. + * + * ALT_FCNTL is mapped onto the fcntl() system call in alt_syscall.h + */ + +int ALT_FCNTL (int file, int cmd, ...) +{ + alt_fd* fd; + long flags; + va_list argp; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + switch (cmd) + { + case F_GETFL: + return fd->fd_flags & ~((alt_u32) ALT_FD_FLAGS_MASK); + case F_SETFL: + va_start(argp, cmd); + flags = va_arg(argp, long); + fd->fd_flags &= ~ALT_FCNTL_FLAGS_MASK; + fd->fd_flags |= (flags & ALT_FCNTL_FLAGS_MASK); + va_end(argp); + return 0; + default: + ALT_ERRNO = EINVAL; + return -1; + } + } + + ALT_ERRNO = EBADFD; + return -1; +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_fd_lock.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_fd_lock.c new file mode 100644 index 0000000..162295a --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_fd_lock.c @@ -0,0 +1,75 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "priv/alt_file.h" + +/* + * alt_fd_lock() is called as a consequence of an ioctl call to gain exclusive + * access to a device, i.e.: + * + * ioctl (fd, TIOCEXCL, NULL); + * + * If there are no other open file descriptors which reference the same + * device, then alt_fd_lock() will grant the lock. Further calls to open() + * for this device will fail until the lock is released. + * + * This is done by calling close() for this file descriptor, or by calling: + * + * ioctl (fd, TIOCNXCL, NULL); + * + * The return value is zero for success, or negative in the case of failure. + */ + +int alt_fd_lock (alt_fd* fd) +{ + int i; + int rc = 0; + + ALT_SEM_PEND(alt_fd_list_lock, 0); + + for (i = 0; i < alt_max_fd; i++) + { + if ((&alt_fd_list[i] != fd) && (alt_fd_list[i].dev == fd->dev)) + { + rc = -EACCES; + goto alt_fd_lock_exit; + } + } + fd->fd_flags |= ALT_FD_EXCL; + + alt_fd_lock_exit: + + ALT_SEM_POST(alt_fd_list_lock); + return rc; +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_fd_unlock.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_fd_unlock.c new file mode 100644 index 0000000..5f50386 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_fd_unlock.c @@ -0,0 +1,56 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "priv/alt_file.h" + +/* + * alt_fd_unlock() is the inverse of alt_fd_lock(). It is called as a + * consequence of a TIOCNXCL ioctl request, e.g: + * + * ioctl (fd, TIOCNXCL, NULL); + * + * It enables multiple file descriptors to exist for the same device. This + * is normally the case, but it may have been disabled by a previous call to + * alt_fd_lock(). + * + * Return zero on sucess, and a negative value on failure. + * + * The current implementation always succeeds. + */ + +int alt_fd_unlock (alt_fd* fd) +{ + fd->fd_flags &= ~ALT_FD_EXCL; + return 0; +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_find_dev.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_find_dev.c new file mode 100644 index 0000000..964f63f --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_find_dev.c @@ -0,0 +1,88 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +#include "alt_types.h" + +/* + * alt_find_dev() is used by open() in order to locate a previously registered + * device with the name "name". The input argument "llist" is a pointer to the + * head of the device list to search. + * + * The return value is a pointer to the matching device, or NULL if there is + * no match. + * + * "name" must be an exact match for the devices registered name for a match to + * be found. + */ + +alt_dev* alt_find_dev(const char* name, alt_llist* llist) +{ + alt_dev* next = (alt_dev*) llist->next; + alt_32 len; + + len = strlen(name) + 1; + + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) llist) + { + + /* + * memcmp() is used here rather than strcmp() in order to reduce the size + * of the executable. + */ + + if (!memcmp (next->name, name, len)) + { + /* match found */ + + return next; + } + next = (alt_dev*) next->llist.next; + } + + /* No match found */ + + return NULL; +} + + diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_find_file.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_find_file.c new file mode 100644 index 0000000..ae30e93 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_find_file.c @@ -0,0 +1,89 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +#include "alt_types.h" + +/* + * alt_find_file() is used by open() in order to locate a previously registered + * filesystem that owns that mount point that contains the file named "name". + * + * The return value is a pointer to the matching filesystem, or NULL if there is + * no match. + * + * A match is considered to have been found if the filesystem name followed by + * either '/' or '\0' is the prefix of the filename. For example the filename: + * "/myfilesystem/junk.txt" would match: "/myfilesystem", but not: "/myfile". + */ + +alt_dev* alt_find_file (const char* name) +{ + alt_dev* next = (alt_dev*) alt_fs_list.next; + + alt_32 len; + + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) &alt_fs_list) + { + len = strlen(next->name); + + if (next->name[len-1] == '/') + { + len -= 1; + } + + if (((name[len] == '/') || (name[len] == '\0')) && + !memcmp (next->name, name, len)) + { + /* match found */ + + return next; + } + next = (alt_dev*) next->llist.next; + } + + /* No match found */ + + return NULL; +} + + diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_flash_dev.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_flash_dev.c new file mode 100644 index 0000000..0acffc7 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_flash_dev.c @@ -0,0 +1,69 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* Alt_flash.c - Functions to register a flash device to the "generic" flash * +* interface * +* * +* Author PRR * +* * +******************************************************************************/ + +#include +#include "sys/alt_llist.h" +#include "sys/alt_flash_dev.h" +#include "priv/alt_file.h" + +ALT_LLIST_HEAD(alt_flash_dev_list); + +alt_flash_fd* alt_flash_open_dev(const char* name) +{ + alt_flash_dev* dev = (alt_flash_dev*)alt_find_dev(name, &alt_flash_dev_list); + + if ((dev) && dev->open) + { + return dev->open(dev, name); + } + + return dev; +} + +void alt_flash_close_dev(alt_flash_fd* fd) +{ + if (fd && fd->close) + { + fd->close(fd); + } + return; +} + diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_fork.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_fork.c new file mode 100644 index 0000000..b6edbb5 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_fork.c @@ -0,0 +1,57 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_warning.h" +#include "sys/alt_errno.h" +#include "os/alt_syscall.h" + +/* + * The fork() system call is used by newlib to create a duplicate copy of the + * curent process. This is unsupported in the HAL environment. However a + * "do-nothing" implementation is still provied for newlib compatability. + * + * ALT_FORK is mapped onto the fork() system call in alt_syscall.h + */ + +int ALT_FORK (void) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(fork); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + + diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_fs_reg.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_fs_reg.c new file mode 100644 index 0000000..e88a340 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_fs_reg.c @@ -0,0 +1,75 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +/* + * The alt_fs_reg() function is used to register a file system. Once registered + * a device can be accessed using the standard posix calls: open(), read(), + * write() etc. + * + * System behaviour is undefined in the event that a file system is registered + * with a name that conflicts with an existing device or file system. + * + * alt_fs_reg() is not thread safe in the sense that there should be no other + * thread using the file system list at the time that alt_dev_reg() is called. In + * practice this means that alt_fs_reg() should only be called while operating + * in a single threaded mode. The expectation is that it will only be called + * by the file system initilisation functions invoked by alt_sys_init(), which in + * turn should only be called by the single threaded C startup code. + * + * A return value of zero indicates success. A negative return value indicates + * failure. + */ + +int alt_fs_reg (alt_dev* dev) +{ + /* + * check that the device has a name. + */ + + if (!dev->name) + { + return -ENODEV; + } + + /* + * register the file system. + */ + + alt_llist_insert(&alt_fs_list, &dev->llist); + + return 0; +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_fstat.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_fstat.c new file mode 100644 index 0000000..3248764 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_fstat.c @@ -0,0 +1,128 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_dev.h" +#include "sys/alt_warning.h" +#include "sys/alt_errno.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +/* + * The fstat() system call is used to obtain information about the capabilities + * of an open file descriptor. By default file descriptors are marked as + * being character devices. If a device or file system wishes to advertise + * alternative capabilities then they can register an fstat() function within + * their associated alt_dev structure. This will be called to fill in the + * entries in the imput "st" structure. + * + * This function is provided for compatability with newlib. + * + * ALT_FSTAT is mapped onto the fstat() system call in alt_syscall.h + */ + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" + +/* + * Provide minimal version that just describes all file descriptors + * as character devices for provided stdio devices. + */ +int ALT_FSTAT (int file, struct stat *st) +{ + switch (file) { +#ifdef ALT_STDIN_PRESENT + case 0: /* stdin file descriptor */ +#endif /* ALT_STDIN_PRESENT */ +#ifdef ALT_STDOUT_PRESENT + case 1: /* stdout file descriptor */ +#endif /* ALT_STDOUT_PRESENT */ +#ifdef ALT_STDERR_PRESENT + case 2: /* stderr file descriptor */ +#endif /* ALT_STDERR_PRESENT */ + st->st_mode = _IFCHR; + return 0; + default: + return -1; + } + +#if !defined(ALT_STDIN_PRESENT) && !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(fstat); +#endif +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_FSTAT (int file, struct stat *st) +{ + alt_fd* fd; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* Call the drivers fstat() function to fill out the "st" structure. */ + + if (fd->dev->fstat) + { + return fd->dev->fstat(fd, st); + } + + /* + * If no function is provided, mark the fd as belonging to a character + * device. + */ + + else + { + st->st_mode = _IFCHR; + return 0; + } + } + else + { + ALT_ERRNO = EBADFD; + return -1; + } +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_get_fd.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_get_fd.c new file mode 100644 index 0000000..f42944b --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_get_fd.c @@ -0,0 +1,105 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +#include "alt_types.h" + +#include "system.h" + +/* + * alt_get_fd() is called to allocate a new file descriptor from the file + * descriptor pool. If a file descriptor is succesfully allocated, it is + * configured to refer to device "dev". + * + * The return value is the index of the file descriptor structure (i.e. + * the offset of the file descriptor within the file descriptor array). A + * negative value indicates failure. + */ + +int alt_get_fd (alt_dev* dev) +{ + alt_32 i; + int rc = -EMFILE; + + /* + * Take the alt_fd_list_lock semaphore in order to avoid races when + * accessing the file descriptor pool. + */ + + ALT_SEM_PEND(alt_fd_list_lock, 0); + + /* + * Search through the list of file descriptors, and allocate the first + * free descriptor that's found. + * + * If a free descriptor is found, then the value of "alt_max_fd" is + * updated accordingly. "alt_max_fd" is a 'highwater mark' which + * indicates the highest file descriptor ever allocated. This is used to + * improve efficency when searching the file descriptor list, and + * therefore reduce contention on the alt_fd_list_lock semaphore. + */ + + for (i = 0; i < ALT_MAX_FD; i++) + { + if (!alt_fd_list[i].dev) + { + alt_fd_list[i].dev = dev; + if (i > alt_max_fd) + { + alt_max_fd = i; + } + rc = i; + goto alt_get_fd_exit; + } + } + + alt_get_fd_exit: + + /* + * Release the alt_fd_list_lock semaphore now that we are done with the + * file descriptor pool. + */ + + ALT_SEM_POST(alt_fd_list_lock); + + return rc; +} + + + + diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_getchar.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_getchar.c new file mode 100644 index 0000000..fe5cb32 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_getchar.c @@ -0,0 +1,70 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2015 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#ifdef ALT_USE_DIRECT_DRIVERS +#include "system.h" +#include "sys/alt_driver.h" +#include "sys/alt_stdio.h" +#include "priv/alt_file.h" +#include "unistd.h" +#endif +#ifdef ALT_SEMIHOSTING +#include "sys/alt_stdio.h" +#include "unistd.h" +#endif +/* + * Uses the ALT_DRIVER_READ() macro to call directly to driver if available. + * Otherwise, uses newlib provided getchar() routine. + */ +int +alt_getchar(void) +{ +#ifdef ALT_SEMIHOSTING + char c; + read(STDIN_FILENO,&c,1); + return c; +#else +#ifdef ALT_USE_DIRECT_DRIVERS + ALT_DRIVER_READ_EXTERNS(ALT_STDIN_DEV); + char c; + + if (ALT_DRIVER_READ(ALT_STDIN_DEV, &c, 1, alt_fd_list[STDIN_FILENO].fd_flags) <= 0) { + return -1; + } + return c; +#else + return getchar(); +#endif +#endif +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_getpid.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_getpid.c new file mode 100644 index 0000000..b63ec33 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_getpid.c @@ -0,0 +1,47 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "os/alt_syscall.h" + +/* + * The getpid() system call is used by newlib to obtain the current process + * id. Since there is only ever a single process in the HAL environment, + * this just returns a constant. + * + * ALT_GETPID is mapped onto the getpid() system call in alt_syscall.h + */ + +int ALT_GETPID (void) +{ + return 0; +} + diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_gettod.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_gettod.c new file mode 100644 index 0000000..46b12c2 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_gettod.c @@ -0,0 +1,125 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include + +#include "sys/alt_alarm.h" +#include "alt_types.h" +#include "os/alt_syscall.h" + +/* + * Macro defining the number of micoseconds in a second. + */ + +#define ALT_US (1000000) + +/* + * "alt_timezone" and "alt_resettime" are the values of the the reset time and + * time zone set through the last call to settimeofday(). By default they are + * zero initialised. + */ + +struct timezone alt_timezone = {0, 0}; +struct timeval alt_resettime = {0, 0}; + +/* + * gettimeofday() can be called to obtain a time structure which indicates the + * current "wall clock" time. This is calculated using the elapsed number of + * system clock ticks, and the value of "alt_resettime" and "alt_timezone" set + * through the last call to settimeofday(). + * + * Warning: if this function is called concurrently with a call to + * settimeofday(), the value returned by gettimeofday() will be unreliable. + * + * ALT_GETTIMEOFDAY is mapped onto the gettimeofday() system call in + * alt_syscall.h + */ + + +#if defined (__GNUC__) && (__GNUC__ >= 4) +int ALT_GETTIMEOFDAY (struct timeval *ptimeval, void *ptimezone_vptr) +{ + struct timezone *ptimezone = (struct timezone*)ptimezone_vptr; +#else +int ALT_GETTIMEOFDAY (struct timeval *ptimeval, struct timezone *ptimezone) +{ +#endif + + alt_u32 nticks = alt_nticks (); + alt_u32 tick_rate = alt_ticks_per_second (); + + /* + * Check to see if the system clock is running. This is indicated by a + * non-zero system clock rate. If the system clock is not running, an error + * is generated and the contents of "ptimeval" and "ptimezone" are not + * updated. + */ + + if (tick_rate) + { + ptimeval->tv_sec = alt_resettime.tv_sec + nticks/tick_rate; + ptimeval->tv_usec = alt_resettime.tv_usec + + (alt_u32)(((alt_u64)nticks*(ALT_US/tick_rate))%ALT_US); + + while(ptimeval->tv_usec < 0) { + if (ptimeval->tv_sec <= 0) + { + ptimeval->tv_sec = 0; + ptimeval->tv_usec = 0; + break; + } + else + { + ptimeval->tv_sec--; + ptimeval->tv_usec += ALT_US; + } + } + + while(ptimeval->tv_usec >= ALT_US) { + ptimeval->tv_sec++; + ptimeval->tv_usec -= ALT_US; + } + + if (ptimezone) + { + ptimezone->tz_minuteswest = alt_timezone.tz_minuteswest; + ptimezone->tz_dsttime = alt_timezone.tz_dsttime; + } + + return 0; + } + + return -ENOTSUP; +} + diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_gmon.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_gmon.c new file mode 100644 index 0000000..fa1cb1d --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_gmon.c @@ -0,0 +1,272 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include +#include + +#include "priv/nios2_gmon_data.h" + +#include "sys/alt_irq.h" +#include "sys/alt_alarm.h" + + +/* Macros */ + +/* How large should the bins be which we use to generate the histogram */ +#define PCSAMPLE_BYTES_PER_BUCKET 32 + +#define NIOS2_READ_EA(dest) __asm__ ("mov %0, ea" : "=r" (dest)) + +/* The compiler inserts calls to mcount() at the start of + * every function call. The structure mcount_fn_arc records t + * he return address of the function called (in from_pc) + * and the return address of the mcount function + * (in self_pc). The number of times this arc is executed is + * recorded in the field count. + */ +struct mcount_fn_arc +{ + struct mcount_fn_arc * next; + void * from_pc; + unsigned int count; +}; + +/* We need to maintain a list of pointers to the heads of each adjacency + * list so that we can find them when writing out the gmon.out file. Since + * we don't know at the start of program execution how many functions will + * be called we use a list structure to do this. + */ +struct mcount_fn_entry +{ + struct mcount_fn_entry * next; + void * self_pc; + struct mcount_fn_arc * arc_head; +}; + +/* function prototypes */ + +void __mcount_record(void * self_pc, void * from_pc, struct mcount_fn_entry * fn_entry, struct mcount_fn_entry * * fn_head) __attribute__ ((no_instrument_function)); + +static __inline__ void * mcount_allocate(unsigned int size) __attribute__ ((no_instrument_function)); +static int nios2_pcsample_init(void) __attribute__ ((no_instrument_function)); +static alt_u32 nios2_pcsample(void* alarm) __attribute__ ((no_instrument_function)); + +/* global variables */ + +/* stext and etext are defined in the linker script */ +extern char stext[]; +extern char etext[]; + +/* Is the PC sampling stuff enabled yet? */ +static int pcsample_need_init = 1; + +#define HASH_BUCKETS 64 /* Must be a power of 2 */ + +/* This points to the list of adjacency list pointers. */ +struct mcount_fn_entry * __mcount_fn_head[HASH_BUCKETS]; + +/* pointer to the in-memory buffer containing the histogram */ +static unsigned short* s_pcsamples = 0; + +/* the address of the start and end of text section */ +static const unsigned int s_low_pc = (unsigned int)stext; +static const unsigned int s_high_pc = (unsigned int)etext; + +/* the alarm structure to register for pc sampling */ +static alt_alarm s_nios2_pcsample_alarm; + +unsigned int alt_gmon_data[GMON_DATA_SIZE] = +{ + 0x6e6f6d67, /* "gmon" */ + GMON_DATA_SIZE, + 0, + (unsigned int)stext, + (unsigned int)etext, + PCSAMPLE_BYTES_PER_BUCKET, + 0, + (unsigned int)__mcount_fn_head, + (unsigned int)(__mcount_fn_head + HASH_BUCKETS) +}; + +/* This holds the current slab of memory we're allocating out of */ +static char * mcount_slab_ptr = 0; +static int mcount_slab_size = 0; + +#define MCOUNT_SLAB_INCREMENT 1020 + + +/* + * We can't use malloc to allocate memory because that's too complicated, and + * can't be called at interrupt time. Use the lower level allocator instead + * because that's interrupt safe (and because we never free anything). + * + * For speed, we allocate a block of data at once. + */ +static __inline__ void * mcount_allocate(unsigned int size) +{ + void * data; + + if (size > mcount_slab_size) + { + mcount_slab_ptr = sbrk(MCOUNT_SLAB_INCREMENT); + mcount_slab_size = MCOUNT_SLAB_INCREMENT; + } + + data = mcount_slab_ptr; + mcount_slab_ptr += size; + mcount_slab_size -= size; + + return data; +} + + +/* + * Add the arc with the values of frompc and topc given to the graph. + * This function might be called at interrupt time so must be able to + * cope with reentrancy. + * + * The fast case, where we have already allocated a function arc, has been + * handled by the assmebler code. + */ +void __mcount_record(void * self_pc, void * from_pc, struct mcount_fn_entry * fn_entry, struct mcount_fn_entry * * fn_head) +{ + alt_irq_context context; + struct mcount_fn_arc * arc_entry; + + /* Keep trying to start up the PC sampler until it is running. + * (It can't start until the timer is going). + */ + if (pcsample_need_init) + { + pcsample_need_init = 0; + pcsample_need_init = nios2_pcsample_init(); + } + + /* + * We must disable interrupts around the allocation and the list update to + * prevent corruption if the instrumented function is re-entrant. + * + * It's safe for the code above to be stepping through the chain and be + * interrupted by this code modifying it - there is an edge case which will + * leave two copies of the same arc on the list (both with count=1), but + * this is dealt with on the host. + */ + context = alt_irq_disable_all(); + + if (fn_entry == NULL) + { + /* Add it to the list of functions we must output later. */ + fn_entry = (struct mcount_fn_entry *)mcount_allocate(sizeof(struct mcount_fn_entry)); + + fn_entry->self_pc = self_pc; + fn_entry->arc_head = NULL; + + fn_entry->next = *fn_head; + *fn_head = fn_entry; + } + + /* We will need a new list entry - if there was a list entry before + * then the assembler code would have handled it. */ + arc_entry = (struct mcount_fn_arc *)mcount_allocate(sizeof(struct mcount_fn_arc)); + + arc_entry->from_pc = from_pc; + arc_entry->count = 1; + + arc_entry->next = fn_entry->arc_head; + fn_entry->arc_head = arc_entry; + + alt_irq_enable_all(context); +} + + +/* + * nios2_pcsample_init starts profiling. + * It is called the first time mcount is called, and on subsequent calls to + * mcount until it returns zero. It initializes the pc histogram and turns on + * timer driven pc sampling. + */ +static int nios2_pcsample_init(void) +{ + unsigned int pcsamples_size; + + /* We sample the PC every tick */ + unsigned int prof_rate = alt_ticks_per_second(); + if (prof_rate == 0) + return 1; + + /* allocate the histogram buffer s_pcsamples */ + pcsamples_size = (s_high_pc - s_low_pc)/PCSAMPLE_BYTES_PER_BUCKET; + s_pcsamples = (unsigned short*)sbrk(pcsamples_size * sizeof(unsigned short)); + + if (s_pcsamples != 0) + { + /* initialize the buffer to zero */ + memset(s_pcsamples, 0, pcsamples_size * sizeof(unsigned short)); + + alt_gmon_data[GMON_DATA_PROFILE_DATA] = (int)s_pcsamples; + alt_gmon_data[GMON_DATA_PROFILE_RATE] = prof_rate; + + /* Sample every tick (it's cheap) */ + alt_alarm_start(&s_nios2_pcsample_alarm, 1, nios2_pcsample, 0); + } + + return 0; +} + + +/* + * Sample the PC value and store it in the histogram + */ +static alt_u32 nios2_pcsample(void* context) +{ + unsigned int pc=0; + unsigned int bucket; + + /* read the exception return address - this will be + * inaccurate if there are nested interrupts but we + * assume that this is rare and the inaccuracy will + * not be great */ + NIOS2_READ_EA(pc); + + /* + * If we're within the profilable range then increment the relevant + * bucket in the histogram + */ + if (pc >= s_low_pc && pc < s_high_pc && s_pcsamples != 0) + { + bucket = (pc - s_low_pc)/PCSAMPLE_BYTES_PER_BUCKET; + s_pcsamples[bucket]++; + } + + /* Sample every tick */ + return 1; +} + diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_icache_flush.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_icache_flush.c new file mode 100644 index 0000000..1662991 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_icache_flush.c @@ -0,0 +1,84 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +/* + * alt_icache_flush() is called to flush the instruction cache for a memory + * region of length "len" bytes, starting at address "start". + */ + +void alt_icache_flush (void* start, alt_u32 len) +{ +#if NIOS2_ICACHE_SIZE > 0 + + char* i; + char* end; + + /* + * This is the most we would ever need to flush. + */ + + if (len > NIOS2_ICACHE_SIZE) + { + len = NIOS2_ICACHE_SIZE; + } + + end = ((char*) start) + len; + + for (i = start; i < end; i+= NIOS2_ICACHE_LINE_SIZE) + { + __asm__ volatile ("flushi %0" :: "r" (i)); + } + + /* + * For an unaligned flush request, we've got one more line left. + * Note that this is dependent on NIOS2_ICACHE_LINE_SIZE to be a + * multiple of 2 (which it always is). + */ + + if (((alt_u32) start) & (NIOS2_ICACHE_LINE_SIZE - 1)) + { + __asm__ volatile ("flushi %0" :: "r" (i)); + } + + /* + * Having flushed the cache, flush any stale instructions in the + * pipeline + */ + + __asm__ volatile ("flushp"); + +#endif /* NIOS2_ICACHE_SIZE > 0 */ +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_icache_flush_all.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_icache_flush_all.c new file mode 100644 index 0000000..dc40ea8 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_icache_flush_all.c @@ -0,0 +1,46 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +/* + * alt_icache_flush_all() is called to flush the entire instruction cache. + */ + +void alt_icache_flush_all (void) +{ +#if NIOS2_ICACHE_SIZE > 0 + alt_icache_flush (0, NIOS2_ICACHE_SIZE); +#endif +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_iic.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_iic.c new file mode 100644 index 0000000..4821f25 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_iic.c @@ -0,0 +1,106 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "system.h" + +/* + * This file implements the HAL Enhanced interrupt API for Nios II processors + * with an internal interrupt controller (IIC). For most routines, this serves + * as a wrapper layer over the legacy interrupt API (which must be used with + * the IIC only). + * + * Use of the enhanced API is recommended so that application and device + * drivers are compatible with a Nios II system configured with an external + * interrupt controller (EIC), or IIC. This will afford maximum portability. + * + * If an EIC is present, the EIC device driver must provide these routines, + * because their operation will be specific to that EIC type. + */ +#ifndef NIOS2_EIC_PRESENT +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + +#include "sys/alt_irq.h" +#include "priv/alt_iic_isr_register.h" +#include "priv/alt_legacy_irq.h" + +/** @Function Description: This function registers an interrupt handler. + * If the function is succesful, then the requested interrupt will be enabled upon + * return. Registering a NULL handler will disable the interrupt. + * @API Type: External + * @param ic_id Ignored. + * @param irq IRQ number + * @return 0 if successful, else error (-1) + */ +int alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, + void *isr_context, void *flags) +{ + return alt_iic_isr_register(ic_id, irq, isr, isr_context, flags); +} + +/** @Function Description: This function enables a single interrupt. + * @API Type: External + * @param ic_id Ignored. + * @param irq IRQ number + * @return 0 if successful, else error (-1) + */ +int alt_ic_irq_enable (alt_u32 ic_id, alt_u32 irq) +{ + return alt_irq_enable(irq); +} + +/** @Function Description: This function disables a single interrupt. + * @API Type: External + * @param ic_id Ignored. + * @param irq IRQ number + * @return 0 if successful, else error (-1) + */ +int alt_ic_irq_disable(alt_u32 ic_id, alt_u32 irq) +{ + return alt_irq_disable(irq); +} + +/** @Function Description: This function to determine if corresponding + * interrupt is enabled. + * @API Type: External + * @param ic_id Ignored. + * @param irq IRQ number + * @return Zero if corresponding interrupt is disabled and + * non-zero otherwise. + */ +alt_u32 alt_ic_irq_enabled(alt_u32 ic_id, alt_u32 irq) +{ + alt_u32 irq_enabled; + + NIOS2_READ_IENABLE(irq_enabled); + + return (irq_enabled & (1 << irq)) ? 1: 0; +} + +#endif /* ALT_ENHANCED_INTERRUPT_API_PRESENT */ +#endif /* NIOS2_EIC_PRESENT */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_iic_isr_register.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_iic_isr_register.c new file mode 100644 index 0000000..2e6bf5b --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_iic_isr_register.c @@ -0,0 +1,104 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ +#include +#include "system.h" + +/* + * Provides an interrupt registry mechanism for the any CPUs internal interrupt + * controller (IIC) when the enhanced interrupt API is active. + */ +#ifndef ALT_CPU_EIC_PRESENT +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + +#include "alt_types.h" +#include "sys/alt_irq.h" +#include "priv/alt_iic_isr_register.h" + +/* + * The header, alt_irq_entry.h, contains the exception entry point, and is + * provided by the processor component. It is included here, so that the code + * will be added to the executable only if alt_irq_register() is present, i.e. + * if no interrupts are registered - there's no need to provide any + * interrupt handling. + */ + +#include "sys/alt_irq_entry.h" + +/* + * The header, alt_irq_table.h contains a table describing which function + * handles each interrupt. + */ + +#include "priv/alt_irq_table.h" + +/** @Function Description: This function registers an interrupt handler. + * If the function is succesful, then the requested interrupt will be enabled + * upon return. Registering a NULL handler will disable the interrupt. + * + * @API Type: External + * @param ic_id Interrupt controller ID + * @param irq IRQ ID number + * @param isr Pointer to interrupt service routine + * @param isr_context Opaque pointer passed to ISR + * @param flags + * @return 0 if successful, else error (-1) + */ +int alt_iic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, + void *isr_context, void *flags) +{ + int rc = -EINVAL; + int id = irq; /* IRQ interpreted as the interrupt ID. */ + alt_irq_context status; + + if (id < ALT_NIRQ) + { + /* + * interrupts are disabled while the handler tables are updated to ensure + * that an interrupt doesn't occur while the tables are in an inconsistant + * state. + */ + + status = alt_irq_disable_all(); + + alt_irq[id].handler = isr; + alt_irq[id].context = isr_context; + + rc = (isr) ? alt_ic_irq_enable(ic_id, id) : alt_ic_irq_disable(ic_id, id); + + alt_irq_enable_all(status); + } + + return rc; +} + +#endif /* ALT_ENHANCED_INTERRUPT_API_PRESENT */ +#endif /* ALT_CPU_EIC_PRESENT */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_instruction_exception_entry.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_instruction_exception_entry.c new file mode 100644 index 0000000..b993811 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_instruction_exception_entry.c @@ -0,0 +1,206 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ +#include "sys/alt_exceptions.h" +#include "nios2.h" +#include "alt_types.h" +#include "system.h" + +/* + * This file implements support for calling user-registered handlers for + * instruction-generated exceptions. This handler could also be reached + * in the event of a spurious interrupt. + * + * The handler code is optionally enabled through the "Enable + * Instruction-related Exception API" HAL BSP setting, which will + * define the macro below. + */ +#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API + +/* Function pointer to exception callback routine */ +alt_exception_result (*alt_instruction_exception_handler) + (alt_exception_cause, alt_u32, alt_u32) = 0x0; + +/* Link entry routine to .exceptions section */ +int alt_instruction_exception_entry (alt_u32 exception_pc) + __attribute__ ((section (".exceptions"))); + +/* + * This is the entry point for instruction-generated exceptions handling. + * This routine will be called by alt_exceptions_entry.S, after it determines + * that an exception could not be handled by handlers that preceed that + * of instruction-generated exceptions (such as interrupts). + * + * For this to function properly, you must register an exception handler + * using alt_instruction_exception_register(). This routine will call + * that handler if it has been registered. Absent a handler, it will + * break break or hang as discussed below. + */ +int +alt_instruction_exception_entry (alt_u32 exception_pc) +{ + alt_u32 cause, badaddr; + +/* + * If the processor hardware has the optional EXCEPTIONS & BADADDR registers, + * read them and pass their content to the user handler. These are always + * present if the MMU or MPU is enabled, and optionally for other advanced + * exception types via the "Extra exceptions information" setting in the + * processor (hardware) configuration. + * + * If these registers are not present, the cause field will be set to + * NIOS2_EXCEPTION_CAUSE_NOT_PRESENT. Your handling routine should + * check the validity of the cause argument before proceeding. + */ +#ifdef NIOS2_HAS_EXTRA_EXCEPTION_INFO + /* Get exception cause & "badaddr" */ + NIOS2_READ_EXCEPTION(cause); + cause = ( (cause & NIOS2_EXCEPTION_REG_CAUSE_MASK) >> + NIOS2_EXCEPTION_REG_CAUSE_OFST ); + + NIOS2_READ_BADADDR(badaddr); +#else + cause = NIOS2_EXCEPTION_CAUSE_NOT_PRESENT; + badaddr = 0; +#endif /* NIOS2_HAS_EXTRA_EXCEPTION_INFO */ + + if(alt_instruction_exception_handler) { + /* + * Call handler. Its return value indicates whether the exception-causing + * instruction should be re-issued. The code that called us, + * alt_eceptions_entry.S, will look at this value and adjust the ea + * register as necessary + */ + return alt_instruction_exception_handler(cause, exception_pc, badaddr); + } + /* + * We got here because an instruction-generated exception occured, but no + * handler is present. We do not presume to know how to handle it. If the + * debugger is present, break, otherwise hang. + * + * If you've reached here in the debugger, consider examining the + * EXCEPTIONS register cause bit-field, which was read into the 'cause' + * variable above, and compare it against the exceptions-type enumeration + * in alt_exceptions.h. This register is availabe if the MMU or MPU is + * present, or if the "Extra exceptions information" hardware option is + * selected. + * + * If you get here then one of the following could have happened: + * + * - An instruction-generated exception occured, and the processor + * does not have the extra exceptions feature enabled, or you + * have not registered a handler using + * alt_instruction_exception_register() + * + * Some examples of instruction-generated exceptions and why they + * might occur: + * + * - Your program could have been compiled for a full-featured + * Nios II core, but it is running on a smaller core, and + * instruction emulation has been disabled by defining + * ALT_NO_INSTRUCTION_EMULATION. + * + * You can work around the problem by re-enabling instruction + * emulation, or you can figure out why your program is being + * compiled for a system other than the one that it is running on. + * + * - Your program has executed a trap instruction, but has not + * implemented a handler for this instruction. + * + * - Your program has executed an illegal instruction (one which is + * not defined in the instruction set). + * + * - Your processor includes an MMU or MPU, and you have enabled it + * before registering an exception handler to service exceptions it + * generates. + * + * The problem could also be hardware related: + * - If your hardware is broken and is generating spurious interrupts + * (a peripheral which negates its interrupt output before its + * interrupt handler has been executed will cause spurious interrupts) + */ + else { +#ifdef NIOS2_HAS_DEBUG_STUB + NIOS2_BREAK(); +#else + while(1) + ; +#endif /* NIOS2_HAS_DEBUG_STUB */ + } + + /* We should not get here. Remove compiler warning. */ + return NIOS2_EXCEPTION_RETURN_REISSUE_INST; +} + +#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */ + +/* + * This routine indicates whether a particular exception cause will have + * set a valid address into the BADADDR register, which is included + * in the arguments to a user-registered instruction-generated exception + * handler. Many exception types do not set valid contents in BADADDR; + * this is a convenience routine to easily test the validity of that + * argument in your handler. + * + * Note that this routine will return false (0) for causes + * NIOS2_EXCEPTION_TLB_MISS and NIOS2_EXCEPTION_ECC_TLB_ERR. + * You must read the TLBMISC.D field to determine if BADADDR + * is valid for these (valid if TLBMISC.D = 1). + * + * Arguments: + * cause: The 5-bit exception cause field of the EXCEPTIONS register, + * shifted to the LSB position. You may pass the 'cause' argument + * in a handler you registered directy to this routine. + * + * Return: 1: BADADDR (bad_addr argument to handler) is valid + * 0: BADADDR is not valid + */ +int +alt_exception_cause_generated_bad_addr(alt_exception_cause cause) +{ + switch (cause) { + case NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR: + case NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR: + case NIOS2_EXCEPTION_MISALIGNED_TARGET_PC: + case NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION: + case NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION: + case NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION: + case NIOS2_EXCEPTION_ECC_DATA_ERR: + return 1; + + case NIOS2_EXCEPTION_TLB_MISS: + case NIOS2_EXCEPTION_ECC_TLB_ERR: + return 0; + + default: + return 0; + } +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_instruction_exception_register.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_instruction_exception_register.c new file mode 100644 index 0000000..395c644 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_instruction_exception_register.c @@ -0,0 +1,82 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ +#include "sys/alt_exceptions.h" +#include "alt_types.h" +#include "system.h" + +/* + * This file implements support for calling user-registered handlers for + * instruction-generated exceptions. + * + * The registry API is optionally enabled through the "Enable + * Instruction-related Exception API" HAL BSP setting, which will + * define the macro below. + */ +#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API + +/* + * The header, alt_exception_handler_registry.h contains a struct describing + * the registered exception handler + */ +#include "priv/alt_exception_handler_registry.h" + +/* + * Pull in the exception entry assembly code. This will not be linked in + * unless this object is linked into the executable (i.e. only if + * alt_instruction_exception_register() is called). + */ +__asm__( "\n\t.globl alt_exception" ); + +/* + * alt_instruction_exception_register() is called to register a handler to + * service instruction-generated exceptions that are not handled by the + * default exception handler code (interrupts, and optionally unimplemented + * instructions and traps). + * + * Passing null (0x0) in the handler argument will disable a previously- + * registered handler. + * + * Note that if no handler is registered, exceptions that are not processed + * using the built-in handler (interrupts, and optionally unimplemented + * instructions and traps) are treated as unknown exceptions, resulting + * in either a break or an infinite loop. + */ +void alt_instruction_exception_register ( + alt_exception_result (*exception_handler)( + alt_exception_cause cause, + alt_u32 exception_pc, + alt_u32 bad_addr) ) +{ + alt_instruction_exception_handler = exception_handler; +} + +#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_io_redirect.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_io_redirect.c new file mode 100644 index 0000000..049ed62 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_io_redirect.c @@ -0,0 +1,98 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + + +/* + * alt_open_fd() is similar to open() in that it is used to obtain a file + * descriptor for the file named "name". The "flags" and "mode" arguments are + * identical to the "flags" and "mode" arguments of open(). + * + * The distinction between the two functions is that the file descriptor + * structure to use is passed in as an argument, rather than allocated from the + * list of free file descriptors. + * + * This is used by alt_io_redirect() to redirect the stdin, stdout and stderr + * file descriptors to point to new devices. + * + * If the device can not be succesfully opened, then the input file descriptor + * remains unchanged. + */ + +static void alt_open_fd(alt_fd* fd, const char* name, int flags, int mode) +{ + int old; + + old = open (name, flags, mode); + + if (old >= 0) + { + fd->dev = alt_fd_list[old].dev; + fd->priv = alt_fd_list[old].priv; + fd->fd_flags = alt_fd_list[old].fd_flags; + + alt_release_fd (old); + } +} + +/* + * alt_io_redirect() is called once the device/filesystem lists have been + * initialised, but before main(). Its function is to redirect standard in, + * standard out and standard error so that they point to the devices selected by + * the user (as defined in system.h). + * + * Prior to the call to this function, io is directed towards /dev/null. If + * i/o can not be redirected to the requested device, for example if the device + * does not exist, then it remains directed at /dev/null. + */ + +void alt_io_redirect(const char* stdout_dev, + const char* stdin_dev, + const char* stderr_dev) +{ + /* Redirect the channels */ + + alt_open_fd (&alt_fd_list[STDOUT_FILENO], stdout_dev, O_WRONLY, 0777); + alt_open_fd (&alt_fd_list[STDIN_FILENO], stdin_dev, O_RDONLY, 0777); + alt_open_fd (&alt_fd_list[STDERR_FILENO], stderr_dev, O_WRONLY, 0777); +} + + + + diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_ioctl.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_ioctl.c new file mode 100644 index 0000000..510b40d --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_ioctl.c @@ -0,0 +1,170 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/ioctl.h" +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +/* + * The ioctl() system call is provided so that application code can manipulate + * the i/o capabilities of a device in device specific ways. This is identical + * to the standard posix ioctl() function. + * + * In general this implementation simply vectors ioctl requests to the + * apropriate drivers ioctl function (as registered in the drivers alt_dev + * structure). + * + * However in the case of devices (as oposed to filesystem), the TIOCEXCL and + * TIOCNXCL requests are handled without reference to the driver. These + * requests are used to lock/release a device for exclusive access. + * + * Handling these requests centrally eases the task of device driver + * development. + * + * ALT_IOCTL is mapped onto the ioctl() system call in alt_syscall.h + */ + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" +#include "sys/alt_driver.h" + +/* + * Provide minimal version that calls ioctl routine of provided stdio devices. + */ +int ALT_IOCTL (int file, int req, void* arg) +{ +#ifdef ALT_STDIN_PRESENT + ALT_DRIVER_IOCTL_EXTERNS(ALT_STDIN_DEV); +#endif +#ifdef ALT_STDOUT_PRESENT + ALT_DRIVER_IOCTL_EXTERNS(ALT_STDOUT_DEV); +#endif +#ifdef ALT_STDERR_PRESENT + ALT_DRIVER_IOCTL_EXTERNS(ALT_STDERR_DEV); +#endif + +#if !defined(ALT_STDIN_PRESENT) && !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(ioctl); +#endif + + switch (file) { +#ifdef ALT_STDIN_PRESENT + case 0: /* stdin file descriptor */ + return ALT_DRIVER_IOCTL(ALT_STDIN_DEV, req, arg); +#endif /* ALT_STDIN_PRESENT */ +#ifdef ALT_STDOUT_PRESENT + case 1: /* stdout file descriptor */ + return ALT_DRIVER_IOCTL(ALT_STDOUT_DEV, req, arg); +#endif /* ALT_STDOUT_PRESENT */ +#ifdef ALT_STDERR_PRESENT + case 2: /* stderr file descriptor */ + return ALT_DRIVER_IOCTL(ALT_STDERR_DEV, req, arg); +#endif /* ALT_STDERR_PRESENT */ + default: + ALT_ERRNO = EBADFD; + return -1; + } +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_IOCTL (int file, int req, void* arg) +{ + alt_fd* fd; + int rc; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + + /* + * In the case of device drivers (not file systems) handle the TIOCEXCL + * and TIOCNXCL requests as special cases. + */ + + if (fd->fd_flags & ALT_FD_DEV) + { + if (req == TIOCEXCL) + { + rc = alt_fd_lock (fd); + goto ioctl_done; + } + else if (req == TIOCNXCL) + { + rc = alt_fd_unlock (fd); + goto ioctl_done; + } + } + + /* + * If the driver provides an ioctl() function, call that to handle the + * request, otherwise set the return code to indicate that the request + * could not be processed. + */ + + if (fd->dev->ioctl) + { + rc = fd->dev->ioctl(fd, req, arg); + } + else + { + rc = -ENOTTY; + } + } + else + { + rc = -EBADFD; + } + +ioctl_done: + + if (rc < 0) + { + ALT_ERRNO = -rc; + } + return rc; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_entry.S b/FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_entry.S new file mode 100644 index 0000000..8ee89e1 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_entry.S @@ -0,0 +1,108 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "system.h" + +/* + * This is the interrupt exception entry point code, which saves all the + * registers and calls the interrupt handler. It should be pulled in using + * a .globl from alt_irq_register.c. This scheme is used so that if an + * interrupt is never registered, then this code will not appear in the + * generated executable, thereby improving code footprint. + */ + + /* + * Explicitly allow the use of r1 (the assembler temporary register) + * within this code. This register is normally reserved for the use of + * the compiler. + */ + .set noat + + /* + * Pull in the exception handler register save code. + */ + .globl alt_exception + + .globl alt_irq_entry + .section .exceptions.entry.label, "xa" +alt_irq_entry: + + /* + * Section .exceptions.entry is in alt_exception_entry.S + * This saves all the caller saved registers and reads estatus into r5 + */ + + .section .exceptions.irqtest, "xa" + +#ifdef ALT_CI_INTERRUPT_VECTOR_N + /* + * Use the interrupt vector custom instruction if present to accelerate + * this code. + * If the interrupt vector custom instruction returns a negative + * value, there are no interrupts active (estatus.pie is 0 + * or ipending is 0) so assume it is a software exception. + */ + custom ALT_CI_INTERRUPT_VECTOR_N, r4, r0, r0 + blt r4, r0, .Lnot_irq +#else + /* + * Test to see if the exception was a software exception or caused + * by an external interrupt, and vector accordingly. + */ + rdctl r4, ipending + andi r2, r5, 1 + beq r2, zero, .Lnot_irq + beq r4, zero, .Lnot_irq +#endif /* ALT_CI_INTERRUPT_VECTOR_N */ + + .section .exceptions.irqhandler, "xa" + /* + * Now that all necessary registers have been preserved, call + * alt_irq_handler() to process the interrupts. + */ + + call alt_irq_handler + + .section .exceptions.irqreturn, "xa" + + br .Lexception_exit + + .section .exceptions.notirq.label, "xa" + +.Lnot_irq: + + /* + * Section .exceptions.exit is in alt_exception_entry.S + * This restores all the caller saved registers + */ + + .section .exceptions.exit.label +.Lexception_exit: + diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_handler.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_handler.c new file mode 100644 index 0000000..bb52fc8 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_handler.c @@ -0,0 +1,169 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include "system.h" + +/* + * This interrupt handler only works with an internal interrupt controller + * (IIC). Processors with an external interrupt controller (EIC) use an + * implementation provided by an EIC driver. + */ +#ifndef ALT_CPU_EIC_PRESENT + +#include "sys/alt_irq.h" +#include "os/alt_hooks.h" + +#include "alt_types.h" + +/* + * A table describing each interrupt handler. The index into the array is the + * interrupt id associated with the handler. + * + * When an interrupt occurs, the associated handler is called with + * the argument stored in the context member. + */ +struct ALT_IRQ_HANDLER +{ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + void (*handler)(void*); +#else + void (*handler)(void*, alt_u32); +#endif + void *context; +} alt_irq[ALT_NIRQ]; + +/* + * alt_irq_handler() is called by the interrupt exception handler in order to + * process any outstanding interrupts. + * + * It is defined here since it is linked in using weak linkage. + * This means that if there is never a call to alt_irq_register() (above) then + * this function will not get linked in to the executable. This is acceptable + * since if no handler is ever registered, then an interrupt can never occur. + * + * If Nios II interrupt vector custom instruction exists, use it to accelerate + * the dispatch of interrupt handlers. The Nios II interrupt vector custom + * instruction is present if the macro ALT_CI_INTERRUPT_VECTOR defined. + */ + +void alt_irq_handler (void) __attribute__ ((section (".exceptions"))); +void alt_irq_handler (void) +{ +#ifdef ALT_CI_INTERRUPT_VECTOR + alt_32 offset; + char* alt_irq_base = (char*)alt_irq; +#else + alt_u32 active; + alt_u32 mask; + alt_u32 i; +#endif /* ALT_CI_INTERRUPT_VECTOR */ + + /* + * Notify the operating system that we are at interrupt level. + */ + + ALT_OS_INT_ENTER(); + +#ifdef ALT_CI_INTERRUPT_VECTOR + /* + * Call the interrupt vector custom instruction using the + * ALT_CI_INTERRUPT_VECTOR macro. + * It returns the offset into the vector table of the lowest-valued pending + * interrupt (corresponds to highest priority) or a negative value if none. + * The custom instruction assumes that each table entry is eight bytes. + */ + while ((offset = ALT_CI_INTERRUPT_VECTOR) >= 0) { + struct ALT_IRQ_HANDLER* handler_entry = + (struct ALT_IRQ_HANDLER*)(alt_irq_base + offset); +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + handler_entry->handler(handler_entry->context); +#else + handler_entry->handler(handler_entry->context, offset >> 3); +#endif + } +#else /* ALT_CI_INTERRUPT_VECTOR */ + /* + * Obtain from the interrupt controller a bit list of pending interrupts, + * and then process the highest priority interrupt. This process loops, + * loading the active interrupt list on each pass until alt_irq_pending() + * return zero. + * + * The maximum interrupt latency for the highest priority interrupt is + * reduced by finding out which interrupts are pending as late as possible. + * Consider the case where the high priority interupt is asserted during + * the interrupt entry sequence for a lower priority interrupt to see why + * this is the case. + */ + + active = alt_irq_pending (); + + do + { + i = 0; + mask = 1; + + /* + * Test each bit in turn looking for an active interrupt. Once one is + * found, the interrupt handler asigned by a call to alt_irq_register() is + * called to clear the interrupt condition. + */ + + do + { + if (active & mask) + { +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_irq[i].handler(alt_irq[i].context); +#else + alt_irq[i].handler(alt_irq[i].context, i); +#endif + break; + } + mask <<= 1; + i++; + + } while (1); + + active = alt_irq_pending (); + + } while (active); +#endif /* ALT_CI_INTERRUPT_VECTOR */ + + /* + * Notify the operating system that interrupt processing is complete. + */ + + ALT_OS_INT_EXIT(); +} + +#endif /* ALT_CPU_EIC_PRESENT */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_register.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_register.c new file mode 100644 index 0000000..cf7261e --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_register.c @@ -0,0 +1,102 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ +#include +#include "system.h" + +/* + * This interrupt registry mechanism works with the Nios II internal interrupt + * controller (IIC) only. Systems with an external interrupt controller (EIC), + * or those with the IIC who are using the enhanced interrupt API will + * utilize the alt_ic_isr_register() routine to register an interrupt. + */ +#ifndef NIOS2_EIC_PRESENT + +#include "sys/alt_irq.h" +#include "priv/alt_legacy_irq.h" +#include "os/alt_hooks.h" + +#include "alt_types.h" + +/* + * The header, alt_irq_entry.h, contains the exception entry point, and is + * provided by the processor component. It is included here, so that the code + * will be added to the executable only if alt_irq_register() is present, i.e. + * if no interrupts are registered - there's no need to provide any + * interrupt handling. + */ + +#include "sys/alt_irq_entry.h" + +/* + * The header, alt_irq_table.h contains a table describing which function + * handles each interrupt. + */ + +#include "priv/alt_irq_table.h" + +/* + * alt_irq_handler() is called to register an interrupt handler. If the + * function is succesful, then the requested interrupt will be enabled upon + * return. Registering a NULL handler will disable the interrupt. + * + * The return value is 0 if the interrupt handler was registered and the + * interrupt was enabled, otherwise it is negative. + */ + +int alt_irq_register (alt_u32 id, + void* context, + alt_isr_func handler) +{ + int rc = -EINVAL; + alt_irq_context status; + + if (id < ALT_NIRQ) + { + /* + * interrupts are disabled while the handler tables are updated to ensure + * that an interrupt doesn't occur while the tables are in an inconsistant + * state. + */ + + status = alt_irq_disable_all (); + + alt_irq[id].handler = handler; + alt_irq[id].context = context; + + rc = (handler) ? alt_irq_enable (id): alt_irq_disable (id); + + alt_irq_enable_all(status); + } + return rc; +} +#endif /* NIOS2_EIC_PRESENT */ + diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_vars.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_vars.c new file mode 100644 index 0000000..4f4d140 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_vars.c @@ -0,0 +1,47 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "alt_types.h" + +#include "system.h" + +/* + * These global variables are used to save the current list of enabled + * interrupts. See alt_irq.h for further details. + */ + +volatile alt_u32 alt_irq_active = 0; + +#ifndef ALT_EXCEPTION_STACK + +volatile alt_u32 alt_priority_mask = (alt_u32) -1; + +#endif + diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_isatty.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_isatty.c new file mode 100644 index 0000000..73677dd --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_isatty.c @@ -0,0 +1,125 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_dev.h" +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" + +/* + * Provide minimal version that just describes all file descriptors + * as tty devices for provided stdio devices. + */ +int ALT_ISATTY (int file) +{ + switch (file) { +#ifdef ALT_STDIN_PRESENT + case 0: /* stdin file descriptor */ +#endif /* ALT_STDIN_PRESENT */ +#ifdef ALT_STDOUT_PRESENT + case 1: /* stdout file descriptor */ +#endif /* ALT_STDOUT_PRESENT */ +#ifdef ALT_STDERR_PRESENT + case 2: /* stderr file descriptor */ +#endif /* ALT_STDERR_PRESENT */ + return 1; + default: + return 0; + } + +#if !defined(ALT_STDIN_PRESENT) && !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(isatty); +#endif +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ +/* + * isatty() can be used to determine whether the input file descriptor "file" + * refers to a terminal device or not. If it is a terminal device then the + * return value is one, otherwise it is zero. + * + * ALT_ISATTY is mapped onto the isatty() system call in alt_syscall.h + */ + +int ALT_ISATTY (int file) +{ + alt_fd* fd; + struct stat stat; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* + * If a device driver does not provide an fstat() function, then it is + * treated as a terminal device by default. + */ + + if (!fd->dev->fstat) + { + return 1; + } + + /* + * If a driver does provide an implementation of the fstat() function, then + * this is called so that the device can identify itself. + */ + + else + { + fstat (file, &stat); + return (stat.st_mode == _IFCHR) ? 1 : 0; + } + } + else + { + ALT_ERRNO = EBADFD; + return 0; + } +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_kill.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_kill.c new file mode 100644 index 0000000..58097d1 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_kill.c @@ -0,0 +1,121 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_errno.h" +#include "os/alt_syscall.h" + + +/* + * kill() is used by newlib in order to send signals to processes. Since there + * is only a single process in the HAL, the only valid values for pid are + * either the current process id, or the broadcast values, i.e. pid must be + * less than or equal to zero. + * + * ALT_KILL is mapped onto the kill() system call in alt_syscall.h + */ + +int ALT_KILL (int pid, int sig) +{ + int status = 0; + + if (pid <= 0) + { + switch (sig) + { + case 0: + + /* The null signal is used to check that a pid is valid. */ + + break; + + case SIGABRT: + case SIGALRM: + case SIGFPE: + case SIGILL: + case SIGKILL: + case SIGPIPE: + case SIGQUIT: + case SIGSEGV: + case SIGTERM: + case SIGUSR1: + case SIGUSR2: + case SIGBUS: + case SIGPOLL: + case SIGPROF: + case SIGSYS: + case SIGTRAP: + case SIGVTALRM: + case SIGXCPU: + case SIGXFSZ: + + /* + * The Posix standard defines the default behaviour for all these signals + * as being eqivalent to a call to _exit(). No mechanism is provided to + * change this behaviour. + */ + + _exit(0); + case SIGCHLD: + case SIGURG: + + /* + * The Posix standard defines these signals to be ignored by default. No + * mechanism is provided to change this behaviour. + */ + + break; + default: + + /* Tried to send an unsupported signal */ + + status = EINVAL; + } + } + + else if (pid > 0) + { + /* Attempted to signal a non-existant process */ + + status = ESRCH; + } + + if (status) + { + ALT_ERRNO = status; + return -1; + } + + return 0; +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_link.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_link.c new file mode 100644 index 0000000..a57a5c4 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_link.c @@ -0,0 +1,56 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_warning.h" +#include "sys/alt_errno.h" +#include "os/alt_syscall.h" + +/* + * link() is used by newlib to create a new link to an existing file. This is + * unsupported in the HAL environment. However a "do-nothing" implementation + * is still provied for newlib compatability. + * + * ALT_LINK is mapped onto the link() system call in alt_syscall.h + */ + +int ALT_LINK ( char *existing, char *new) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(link); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_load.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_load.c new file mode 100644 index 0000000..38d9618 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_load.c @@ -0,0 +1,99 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_load.h" +#include "sys/alt_cache.h" + +/* + * Linker defined symbols. + These used to be + * extern alt_u32 __flash_rwdata_start; + * extern alt_u32 __ram_rwdata_start; + * extern alt_u32 __ram_rwdata_end; + * but that results in a fatal error when compiling -mgpopt=global + * because gcc assumes they are normal C variables in .sdata + * and therefore addressable from gp using a 16-bit offset, + * when in fact they are special values defined by linker.x + * and located nowhere near .sdata. + * Specifying __attribute__((section(".data"))) will force these + * in .data. (CASE:258384.) + */ + +extern alt_u32 __flash_rwdata_start __attribute__((section(".data"))); +extern alt_u32 __ram_rwdata_start __attribute__((section(".data"))); +extern alt_u32 __ram_rwdata_end __attribute__((section(".data"))); +extern alt_u32 __flash_rodata_start __attribute__((section(".data"))); +extern alt_u32 __ram_rodata_start __attribute__((section(".data"))); +extern alt_u32 __ram_rodata_end __attribute__((section(".data"))); +extern alt_u32 __flash_exceptions_start __attribute__((section(".data"))); +extern alt_u32 __ram_exceptions_start __attribute__((section(".data"))); +extern alt_u32 __ram_exceptions_end __attribute__((section(".data"))); + +/* + * alt_load() is called when the code is executing from flash. In this case + * there is no bootloader, so this application is responsible for loading to + * RAM any sections that are required. + */ + +void alt_load (void) +{ + /* + * Copy the .rwdata section. + */ + + alt_load_section (&__flash_rwdata_start, + &__ram_rwdata_start, + &__ram_rwdata_end); + + /* + * Copy the exception handler. + */ + + alt_load_section (&__flash_exceptions_start, + &__ram_exceptions_start, + &__ram_exceptions_end); + + /* + * Copy the .rodata section. + */ + + alt_load_section (&__flash_rodata_start, + &__ram_rodata_start, + &__ram_rodata_end); + + /* + * Now ensure that the caches are in synch. + */ + + alt_dcache_flush_all(); + alt_icache_flush_all(); +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_log_macro.S b/FPGA_nios/hit_pat_bsp/HAL/src/alt_log_macro.S new file mode 100644 index 0000000..d6b0a90 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_log_macro.S @@ -0,0 +1,60 @@ +/* alt_log_macro.S + * + * Implements the function tx_log_str, called by the assembly macro + * ALT_LOG_PUTS(). The macro will be empty when logging is turned off, + * and this function will not be compiled. When logging is on, + * this function is used to print out the strings defined in the beginning + * of alt_log_printf.c, using port information taken from system.h and + * alt_log_printf.h. + * + * This routine only handles strings, and sends a character into the defined + * output device's output buffer when the device is ready. It's intended for + * debugging purposes, where messages can be set to print out at certain + * points in the boot code to indicate the progress of the program. + * + */ + +#ifndef __ALT_LOG_MACROS__ +#define __ALT_LOG_MACROS__ + +/* define this flag to skip assembly-incompatible parts + * of various include files. */ +#define ALT_ASM_SRC + +#ifdef ALT_LOG_ENABLE // only compile this function if this flag is defined. + + #include "system.h" + #include "sys/alt_log_printf.h" + + .global tx_log_str +tx_log_str: + /* load base uart / jtag uart address into r6 */ + movhi r6, %hiadj(ALT_LOG_PORT_BASE) + addi r6, r6, %lo(ALT_LOG_PORT_BASE) +tx_next_char: + /* if pointer points to null, return + * r4 is the pointer to the str to be printed, set by ALT_LOG_PUTS */ + ldb r7, (r4) + beq r0, r7, end_tx + + /* check device transmit ready */ +wait_tx_ready_loop: + ldwio r8, ALT_LOG_PRINT_REG_OFFSET(r6) + /*UART, ALT_LOG_PRINT_MSK == 0x40 + JTAG UART, ALT_LOG_PRINT_MSK == 0xFFFF0000 */ + andhi r5, r8, %hi(ALT_LOG_PRINT_MSK) + andi r8, r8, %lo(ALT_LOG_PRINT_MSK) + or r5, r5, r8 + beq r5, r0, wait_tx_ready_loop + /* write char */ + stwio r7, ALT_LOG_PRINT_TXDATA_REG_OFFSET (r6) + /* advance string pointer */ + addi r4, r4, 1 + br tx_next_char +end_tx: + ret + +#endif + +#endif /* __ALT_LOG_MACROS__ */ + diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_log_printf.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_log_printf.c new file mode 100644 index 0000000..7464185 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_log_printf.c @@ -0,0 +1,479 @@ + +/* alt_log_printf.c + * + * This file implements the various C functions used for the + * alt_log logging/debugging print functions. The functions + * sit as is here - the job of hiding them from the compiler + * if logging is disabled is accomplished in the .h file. + * + * All the global variables for alt_log are defined here. + * These include the various flags that turn on additional + * logging options; the strings for assembly printing; and + * other globals needed by different logging options. + * + * There are 4 functions that handle the actual printing: + * alt_log_txchar: Actual function that puts 1 char to UART/JTAG UART. + * alt_log_repchar: Calls alt_log_txchar 'n' times - used by + * alt_log_private_printf for formatting. + * alt_log_private_printf: + * Stripped down implementation of printf - no floats. + * alt_log_printf_proc: + * Wrapper function for private_printf. + * + * The rest of the functions are called by the macros which + * were called by code in the other components. Each function + * is preceded by a comment, about which file it gets called + * in, and what its purpose is. + * + * author: gkwan + */ + +/* skip all code if enable is off */ +#ifdef ALT_LOG_ENABLE + +#include +#include +#include +#ifdef __ALTERA_AVALON_JTAG_UART + #include "altera_avalon_jtag_uart.h" + #include +#endif +#include "sys/alt_log_printf.h" + +/* strings for assembly puts */ +char alt_log_msg_bss[] = "[crt0.S] Clearing BSS \r\n";; +char alt_log_msg_alt_main[] = "[crt0.S] Calling alt_main.\r\n"; +char alt_log_msg_stackpointer[] \ + = "[crt0.S] Setting up stack and global pointers.\r\n"; +char alt_log_msg_cache[] = "[crt0.S] Inst & Data Cache Initialized.\r\n"; +/* char array allocation for alt_write */ +char alt_log_write_buf[ALT_LOG_WRITE_ECHO_LEN+2]; + +/* global variables for all 'on' flags */ + +/* + * CASE:368514 - The boot message flag is linked into the sdata section + * because if it is zero, it would otherwise be placed in the bss section. + * alt_log examines this variable before the BSS is cleared in the boot-up + * process. + */ +volatile alt_u32 alt_log_boot_on_flag \ + __attribute__ ((section (".sdata"))) = ALT_LOG_BOOT_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_write_on_flag = ALT_LOG_WRITE_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_sys_clk_on_flag = ALT_LOG_SYS_CLK_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_jtag_uart_alarm_on_flag = \ + ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_jtag_uart_isr_on_flag = \ + ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_jtag_uart_startup_info_on_flag = \ + ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING; + +/* Global alarm object for recurrent JTAG UART status printing */ +alt_alarm alt_log_jtag_uart_alarm_1; + +/* Global ints for system clock printing and count */ +volatile int alt_log_sys_clk_count; +volatile int alt_system_clock_in_sec; + +/* enum used by alt_log_private_printf */ +enum +{ + pfState_chars, + pfState_firstFmtChar, + pfState_otherFmtChar +}; + + + + +/* Function to put one char onto the UART/JTAG UART txdata register. */ +void alt_log_txchar(int c,char *base) +{ + /* Wait until the device is ready for a character */ + while((ALT_LOG_PRINT_REG_RD(base) & ALT_LOG_PRINT_MSK) == 0) + ; + /* And pop the character into the register */ + ALT_LOG_PRINT_TXDATA_WR(base,c); +} + + +/* Called by alt_log_private_printf to print out characters repeatedly */ +void alt_log_repchar(char c,int r,int base) +{ + while(r-- > 0) + alt_log_txchar(c,(char*) base); +} + + +/* Stripped down printf function */ +void alt_log_private_printf(const char *fmt,int base,va_list args) + { + const char *w; + char c; + int state; + int fmtLeadingZero = 0; /* init these all to 0 for -W warnings. */ + int fmtLong = 0; + int fmtBeforeDecimal = 0; + int fmtAfterDecimal = 0; + int fmtBase = 0; + int fmtSigned = 0; + int fmtCase = 0; /* For hex format, if 1, A-F, else a-f. */ + + w = fmt; + state = pfState_chars; + + while(0 != (c = *w++)) + { + switch(state) + { + case pfState_chars: + if(c == '%') + { + fmtLeadingZero = 0; + fmtLong = 0; + fmtBase = 10; + fmtSigned = 1; + fmtCase = 0; /* Only %X sets this. */ + fmtBeforeDecimal = -1; + fmtAfterDecimal = -1; + state = pfState_firstFmtChar; + } + else + { + alt_log_txchar(c,(char*)base); + } + break; + + case pfState_firstFmtChar: + if(c == '0') + { + fmtLeadingZero = 1; + state = pfState_otherFmtChar; + } + else if(c == '%') + { + alt_log_txchar(c,(char*)base); + state = pfState_chars; + } + else + { + state = pfState_otherFmtChar; + goto otherFmtChar; + } + break; + + case pfState_otherFmtChar: +otherFmtChar: + if(c == '.') + { + fmtAfterDecimal = 0; + } + else if('0' <= c && c <= '9') + { + c -= '0'; + if(fmtAfterDecimal < 0) /* still before decimal */ + { + if(fmtBeforeDecimal < 0) + { + fmtBeforeDecimal = 0; + } + else + { + fmtBeforeDecimal *= 10; + } + fmtBeforeDecimal += c; + } + else + { + fmtAfterDecimal = (fmtAfterDecimal * 10) + c; + } + } + else if(c == 'l') + { + fmtLong = 1; + } + else /* we're up to the letter which determines type */ + { + switch(c) + { + case 'd': + case 'i': +doIntegerPrint: + { + unsigned long v; + unsigned long p; /* biggest power of fmtBase */ + unsigned long vShrink; /* used to count digits */ + int sign; + int digitCount; + + /* Get the value */ + if(fmtLong) + { + if (fmtSigned) + { + v = va_arg(args,long); + } + else + { + v = va_arg(args,unsigned long); + } + } + else + { + if (fmtSigned) + { + v = va_arg(args,int); + } + else + { + v = va_arg(args,unsigned int); + } + } + + /* Strip sign */ + sign = 0; + /* (assumes sign bit is #31) */ + if( fmtSigned && (v & (0x80000000)) ) + { + v = ~v + 1; + sign = 1; + } + + /* Count digits, and get largest place value */ + vShrink = v; + p = 1; + digitCount = 1; + while( (vShrink = vShrink / fmtBase) > 0 ) + { + digitCount++; + p *= fmtBase; + } + + /* Print leading characters & sign */ + fmtBeforeDecimal -= digitCount; + if(fmtLeadingZero) + { + if(sign) + { + alt_log_txchar('-',(char*)base); + fmtBeforeDecimal--; + } + alt_log_repchar('0',fmtBeforeDecimal,base); + } + else + { + if(sign) + { + fmtBeforeDecimal--; + } + alt_log_repchar(' ',fmtBeforeDecimal,base); + if(sign) + { + alt_log_txchar('-',(char*)base); + } + } + + /* Print numbery parts */ + while(p) + { + unsigned char d; + + d = v / p; + d += '0'; + if(d > '9') + { + d += (fmtCase ? 'A' : 'a') - '0' - 10; + } + alt_log_txchar(d,(char*)base); + + v = v % p; + p = p / fmtBase; + } + } + + state = pfState_chars; + break; + + case 'u': + fmtSigned = 0; + goto doIntegerPrint; + case 'o': + fmtSigned = 0; + fmtBase = 8; + goto doIntegerPrint; + case 'x': + fmtSigned = 0; + fmtBase = 16; + goto doIntegerPrint; + case 'X': + fmtSigned = 0; + fmtBase = 16; + fmtCase = 1; + goto doIntegerPrint; + + case 'c': + alt_log_repchar(' ',fmtBeforeDecimal-1,base); + alt_log_txchar(va_arg(args,int),(char*)base); + break; + + case 's': + { + char *s; + + s = va_arg(args,char *); + alt_log_repchar(' ',fmtBeforeDecimal-strlen(s),base); + + while(*s) + alt_log_txchar(*s++,(char*)base); + } + break; + } /* switch last letter of fmt */ + state=pfState_chars; + } + break; + } /* switch */ + } /* while chars left */ + } /* printf */ + +/* Main logging printf function */ +int alt_log_printf_proc(const char *fmt, ... ) +{ + va_list args; + + va_start (args, fmt); + alt_log_private_printf(fmt,ALT_LOG_PORT_BASE,args); + return (0); +} + +/* Below are the functions called by different macros in various components. */ + +/* If the system has a JTAG_UART, include JTAG_UART debugging functions */ +#ifdef __ALTERA_AVALON_JTAG_UART + +/* The alarm function in altera_avalon_jtag_uart.c. + * This function, when turned on, prints out the status + * of the JTAG UART Control register, every ALT_LOG_JTAG_UART_TICKS. + * If the flag is off, the alarm should never be registered, and this + * function should never run */ +alt_u32 altera_avalon_jtag_uart_report_log(void * context) +{ + if (alt_log_jtag_uart_alarm_on_flag) { + altera_avalon_jtag_uart_state* dev = (altera_avalon_jtag_uart_state*) context; + const char* header="JTAG Alarm:"; + alt_log_jtag_uart_print_control_reg(dev, dev->base, header); + return ALT_LOG_JTAG_UART_TICKS; + } + else + { + /* If flag is not on, return 0 to disable future alarms. + * Should never be here, alarm should not be enabled at all. */ + return 0; + } +} + +void alt_log_jtag_uart_print_control_reg(altera_avalon_jtag_uart_state* dev, int base, const char* header) +{ + unsigned int control, space, ac, wi, ri, we, re; + control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST; + we= (control & ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_WE_OFST; + re= (control & ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_RE_OFST; + ri= (control & ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_RI_OFST; + wi= (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_WI_OFST; + ac= (control & ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_AC_OFST; + +#ifdef ALTERA_AVALON_JTAG_UART_SMALL + ALT_LOG_PRINTF( + "%s HW FIFO wspace=%d AC=%d WI=%d RI=%d WE=%d RE=%d\r\n", + header,space,ac,wi,ri,we,re); +#else + ALT_LOG_PRINTF( + "%s SW CirBuf = %d, HW FIFO wspace=%d AC=%d WI=%d RI=%d WE=%d RE=%d\r\n", + header,(dev->tx_out-dev->tx_in),space,ac,wi,ri,we,re); +#endif + + return; + +} + +/* In altera_avalon_jtag_uart.c + * Same output as the alarm function above, but this is called in the driver + * init function. Hence, it gives the status of the JTAG UART control register + * right at the initialization of the driver */ +void alt_log_jtag_uart_startup_info(altera_avalon_jtag_uart_state* dev, int base) +{ + const char* header="JTAG Startup Info:"; + alt_log_jtag_uart_print_control_reg(dev, base, header); + return; +} + +/* In altera_avalon_jtag_uart.c + * When turned on, this function will print out the status of the jtag uart + * control register every time there is a jtag uart "almost-empty" interrupt. */ +void alt_log_jtag_uart_isr_proc(int base, altera_avalon_jtag_uart_state* dev) +{ + if (alt_log_jtag_uart_isr_on_flag) { + const char* header="JTAG IRQ:"; + alt_log_jtag_uart_print_control_reg(dev, base, header); + } + return; +} + +#endif /* __ALTERA_AVALON_JTAG_UART */ + +/* In alt_write.c + * When the alt_log_write_on_flag is turned on, this function gets called + * every time alt_write gets called. The first + * ALT_LOG_WRITE_ECHO_LEN characters of every printf command (or any command + * that eventually calls write()) gets echoed to the alt_log output. */ +void alt_log_write(const void *ptr, size_t len) +{ + if (alt_log_write_on_flag) { + int temp_cnt; + int length=(ALT_LOG_WRITE_ECHO_LEN>len) ? len : ALT_LOG_WRITE_ECHO_LEN; + + if (length < 2) return; + + strncpy (alt_log_write_buf,ptr,length); + alt_log_write_buf[length-1]='\n'; + alt_log_write_buf[length]='\r'; + alt_log_write_buf[length+1]='\0'; + + /* Escape Ctrl-D's. If the Ctrl-D gets sent it might kill the terminal + * connection of alt_log. It will get replaced by 'D'. */ + for (temp_cnt=0;temp_cnt < length; temp_cnt++) { + if (alt_log_write_buf[temp_cnt]== 0x4) { + alt_log_write_buf[temp_cnt]='D'; + } + } + ALT_LOG_PRINTF("Write Echo: %s",alt_log_write_buf); + } +} + +/* In altera_avalon_timer_sc + * This function prints out a system clock is alive message + * every ALT_LOG_SYS_CLK_INTERVAL (in ticks). */ +void alt_log_system_clock() +{ + if (alt_log_sys_clk_on_flag) { + alt_log_sys_clk_count++; + if (alt_log_sys_clk_count > ALT_LOG_SYS_CLK_INTERVAL) { + alt_log_sys_clk_count = 0; + ALT_LOG_PRINTF("System Clock On %u\r\n",alt_system_clock_in_sec++); + } + } +} + + +#endif diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_lseek.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_lseek.c new file mode 100644 index 0000000..a56dbfb --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_lseek.c @@ -0,0 +1,117 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +#ifdef ALT_USE_DIRECT_DRIVERS + +off_t ALT_LSEEK (int file, off_t ptr, int dir) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(lseek); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +/* + * lseek() can be called to move the read/write pointer associated with the + * file descriptor "file". This function simply vectors the call to the lseek() + * function provided by the driver associated with the file descriptor. + * + * If the driver does not provide an implementation of lseek() an error is + * indicated. + * + * lseek() corresponds to the standard lseek() function. + * + * ALT_LSEEK is mapped onto the lseek() system call in alt_syscall.h + * + */ + +off_t ALT_LSEEK (int file, off_t ptr, int dir) +{ + alt_fd* fd; + off_t rc = 0; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* + * If the device driver provides an implementation of the lseek() function, + * then call that to process the request. + */ + + if (fd->dev->lseek) + { + rc = fd->dev->lseek(fd, ptr, dir); + } + /* + * Otherwise return an error. + */ + + else + { + rc = -ENOTSUP; + } + } + else + { + rc = -EBADFD; + } + + if (rc < 0) + { + ALT_ERRNO = -rc; + rc = -1; + } + + return rc; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_main.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_main.c new file mode 100644 index 0000000..33e3463 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_main.c @@ -0,0 +1,161 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include "sys/alt_dev.h" +#include "sys/alt_sys_init.h" +#include "sys/alt_irq.h" +#include "sys/alt_dev.h" + +#include "os/alt_hooks.h" + +#include "priv/alt_file.h" +#include "alt_types.h" + +#include "system.h" + +#include "sys/alt_log_printf.h" + +extern void _do_ctors(void); +extern void _do_dtors(void); + +/* + * Standard arguments for main. By default, no arguments are passed to main. + * However a device driver may choose to configure these arguments by calling + * alt_set_args(). The expectation is that this facility will only be used by + * the iclient/ihost utility. + */ + +int alt_argc = 0; +char** alt_argv = {NULL}; +char** alt_envp = {NULL}; + +/* + * Prototype for the entry point to the users application. + */ + +extern int main (int, char **, char **); + +/* + * alt_main is the C entry point for the HAL. It is called by the assembler + * startup code in the processor specific crt0.S. It is responsible for: + * completing the C runtime configuration; configuring all the + * devices/filesystems/components in the system; and call the entry point for + * the users application, i.e. main(). + */ + +void alt_main (void) +{ +#ifndef ALT_NO_EXIT + int result; +#endif + + /* ALT LOG - please see HAL/sys/alt_log_printf.h for details */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Entering alt_main, calling alt_irq_init.\r\n"); + /* Initialize the interrupt controller. */ + alt_irq_init (NULL); + + /* Initialize the operating system */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Done alt_irq_init, calling alt_os_init.\r\n"); + ALT_OS_INIT(); + + /* + * Initialize the semaphore used to control access to the file descriptor + * list. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Done OS Init, calling alt_sem_create.\r\n"); + ALT_SEM_CREATE (&alt_fd_list_lock, 1); + + /* Initialize the device drivers/software components. */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling alt_sys_init.\r\n"); + alt_sys_init(); + ALT_LOG_PRINT_BOOT("[alt_main.c] Done alt_sys_init.\r\n"); + +#if !defined(ALT_USE_DIRECT_DRIVERS) && (defined(ALT_STDIN_PRESENT) || defined(ALT_STDOUT_PRESENT) || defined(ALT_STDERR_PRESENT)) + + /* + * Redirect stdio to the apropriate devices now that the devices have + * been initialized. This is only done if the user has requested these + * devices be present (not equal to /dev/null) and if direct drivers + * aren't being used. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Redirecting IO.\r\n"); + alt_io_redirect(ALT_STDOUT, ALT_STDIN, ALT_STDERR); +#endif + +#ifndef ALT_NO_C_PLUS_PLUS + /* + * Call the C++ constructors + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling C++ constructors.\r\n"); + _do_ctors (); +#endif /* ALT_NO_C_PLUS_PLUS */ + +#if !defined(ALT_NO_C_PLUS_PLUS) && !defined(ALT_NO_CLEAN_EXIT) && !defined(ALT_NO_EXIT) + /* + * Set the C++ destructors to be called at system shutdown. This is only done + * if a clean exit has been requested (i.e. the exit() function has not been + * redefined as _exit()). This is in the interest of reducing code footprint, + * in that the atexit() overhead is removed when it's not needed. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling atexit.\r\n"); + atexit (_do_dtors); +#endif + + /* + * Finally, call main(). The return code is then passed to a subsequent + * call to exit() unless the application is never supposed to exit. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling main.\r\n"); + +#ifdef ALT_NO_EXIT + main (alt_argc, alt_argv, alt_envp); +#else + result = main (alt_argc, alt_argv, alt_envp); + close(STDOUT_FILENO); + exit (result); +#endif + + ALT_LOG_PRINT_BOOT("[alt_main.c] After main - we should not be here?.\r\n"); +} + diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_mcount.S b/FPGA_nios/hit_pat_bsp/HAL/src/alt_mcount.S new file mode 100644 index 0000000..cf510da --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_mcount.S @@ -0,0 +1,198 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2010 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* mcount or _mcount is inserted by GCC before the function prologue of every + * function when a program is compiled for profiling. At the start of mcount, + * we guarantee that: + * ra = self_pc (an address in the function which called mcount) + * r8 = from_pc (an address in the function which called mcount's caller) + * + * Because this is always called at the start of a function we can corrupt + * r2,r3 and r11-r15. We must not corrupt r4-r7 (because they might contain + * function arguments for the instrumented function) or r8 (which holds ra + * for the instrumented function). + */ + + .global __mcount_fn_head + + .global mcount + + /* _mcount is used by gcc4 */ + .global _mcount + +_mcount: +mcount: + /* Use a hash to speed up locating fn_entry. We use bits 5 upwards to choose + * the bucket because bits 1:0 will always be 0, and because the distribution + * of values for bits 4:2 won't be even (aligning on cache line boundaries + * will skew it). Higher bits should be fairly random. + */ + /* fn_head = mcount_fn_head + (((unsigned int)self_pc >> 5) & (HASH_BUCKETS - 1)); */ + + srli r2, ra, 3 + movhi r3, %hiadj(__mcount_fn_head) + addi r3, r3, %lo(__mcount_fn_head) + andi r2, r2, 0xFC + add r11, r2, r3 + + /* The fast case is where we have already allocated a function arc, and so + * also a function pointer. + */ + + /* First find the function being called (using self_pc) */ + mov r10, r11 +0: + ldw r10, 0(r10) + beq r10, zero, .Lnew_arc + ldw r2, 4(r10) + bne r2, ra, 0b + + /* Found a function entry for this PC. Now look for an arc with a matching + * from_pc value. There will always be at least one arc. */ + ldw r3, 8(r10) +0: + ldw r2, 4(r3) + beq r2, r8, .Lfound_arc + ldw r3, 0(r3) + bne r3, zero, 0b + +.Lnew_arc: + addi sp, sp, -24 + +.LCFI0: + stw ra, 0(sp) + stw r4, 4(sp) + stw r5, 8(sp) + stw r6, 12(sp) + stw r7, 16(sp) + stw r8, 20(sp) + +.LCFI1: + /* __mcount_record(orig_ra, orig_r8, fn_entry, *fn_head); */ + mov r4, ra + mov r5, r8 + mov r6, r10 + mov r7, r11 + call __mcount_record + + /* restore registers from the stack */ + ldw ra, 0(sp) + ldw r4, 4(sp) + ldw r5, 8(sp) + ldw r6, 12(sp) + ldw r7, 16(sp) + ldw r8, 20(sp) + + addi sp, sp, 24 + +.LCFI2: + ret + +.Lfound_arc: + /* We've found the correct arc record. Increment the count and return */ + ldw r2, 8(r3) + addi r2, r2, 1 + stw r2, 8(r3) + ret + +.Lmcount_end: + + + +/* + * Dwarf2 debug information for the function. This provides GDB with the + * information it needs to backtrace out of this function. + */ + + .section .debug_frame,"",@progbits +.LCIE: + .4byte 2f - 1f /* Length */ +1: + .4byte 0xffffffff /* CIE id */ + .byte 0x1 /* Version */ + .string "" /* Augmentation */ + .uleb128 0x1 /* Code alignment factor */ + .sleb128 -4 /* Data alignment factor */ + .byte 0x1f /* Return address register */ + + .byte 0xc /* Define CFA */ + .uleb128 0x1b /* Register 27 (sp) */ + .uleb128 0x0 /* Offset 0 */ + + .align 2 /* Padding */ +2: + +.LFDE_mcount: + .4byte 2f - 1f /* Length */ +1: + .4byte .LCIE /* Pointer to CIE */ + .4byte mcount /* Start of table entry */ + .4byte .Lmcount_end - mcount /* Size of table entry */ + + .byte 0x4 /* Advance location */ + .4byte .LCFI0 - mcount /* to .LCFI0 */ + .byte 0xe /* Define CFA offset */ + .uleb128 24 /* to 24 */ + + .byte 0x4 /* Advance location */ + .4byte .LCFI1 - .LCFI0 /* to .LCFI1 */ + .byte 0x9f /* Store ra */ + .uleb128 0x6 /* at CFA-24 */ + .byte 0x84 /* Store r4 */ + .uleb128 0x5 /* at CFA-20 */ + .byte 0x85 /* Store r5 */ + .uleb128 0x4 /* at CFA-16 */ + .byte 0x86 /* Store r6 */ + .uleb128 0x3 /* at CFA-12 */ + .byte 0x87 /* Store r7 */ + .uleb128 0x2 /* at CFA-8 */ + .byte 0x88 /* Store r8 */ + .uleb128 0x1 /* at CFA-4 */ + + .byte 0x4 /* Advance location */ + .4byte .LCFI2 - .LCFI1 /* to .LCFI2 */ + .byte 0xe /* Define CFA offset */ + .uleb128 0 /* to 0 */ + .byte 0x8 /* Same value */ + .uleb128 31 /* for ra */ + .byte 0x8 /* Same value */ + .uleb128 4 /* for r4 */ + .byte 0x8 /* Same value */ + .uleb128 5 /* for r5 */ + .byte 0x8 /* Same value */ + .uleb128 6 /* for r6 */ + .byte 0x8 /* Same value */ + .uleb128 7 /* for r7 */ + .byte 0x8 /* Same value */ + .uleb128 8 /* for r8 */ + + .align 2 +2: + diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_open.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_open.c new file mode 100644 index 0000000..d7040bc --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_open.c @@ -0,0 +1,173 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "alt_types.h" +#include "os/alt_syscall.h" + +#ifdef ALT_USE_DIRECT_DRIVERS + +int ALT_OPEN (const char* file, int flags, int mode) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(open); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +extern alt_llist alt_dev_list; + +/* + * alt_file_locked() is used by open() to ensure that a device has not been + * previously locked for exclusive access using ioctl(). This test is only + * performed for devices. Filesystems are required to handle the ioctl() call + * themselves, and report the error from the filesystems open() function. + */ + +static int alt_file_locked (alt_fd* fd) +{ + alt_u32 i; + + /* + * Mark the file descriptor as belonging to a device. + */ + + fd->fd_flags |= ALT_FD_DEV; + + /* + * Loop through all current file descriptors searching for one that's locked + * for exclusive access. If a match is found, generate an error. + */ + + for (i = 0; i <= alt_max_fd; i++) + { + if ((alt_fd_list[i].dev == fd->dev) && + (alt_fd_list[i].fd_flags & ALT_FD_EXCL) && + (&alt_fd_list[i] != fd)) + { + return -EACCES; + } + } + + /* The device is not locked */ + + return 0; +} + +/* + * open() is called in order to get a file descriptor that reference the file + * or device named "name". This descriptor can then be used to manipulate the + * file/device using the standard system calls, e.g. write(), read(), ioctl() + * etc. + * + * This is equivalent to the standard open() system call. + * + * ALT_OPEN is mapped onto the open() system call in alt_syscall.h + */ + +int ALT_OPEN (const char* file, int flags, int mode) +{ + alt_dev* dev; + alt_fd* fd; + int index = -1; + int status = -ENODEV; + int isafs = 0; + + /* + * Check the device list, to see if a device with a matching name is + * registered. + */ + + if (!(dev = alt_find_dev (file, &alt_dev_list))) + { + /* No matching device, so try the filesystem list */ + + dev = alt_find_file (file); + isafs = 1; + } + + /* + * If a matching device or filesystem is found, allocate a file descriptor. + */ + + if (dev) + { + if ((index = alt_get_fd (dev)) < 0) + { + status = index; + } + else + { + fd = &alt_fd_list[index]; + fd->fd_flags = (flags & ~ALT_FD_FLAGS_MASK); + + /* If this is a device, ensure it isn't already locked */ + + if (isafs || ((status = alt_file_locked (fd)) >= 0)) + { + /* + * If the device or filesystem provides an open() callback function, + * call it now to perform any device/filesystem specific operations. + */ + + status = (dev->open) ? dev->open(fd, file, flags, mode): 0; + } + } + } + else + { + status = -ENODEV; + } + + /* Allocation failed, so clean up and return an error */ + + if (status < 0) + { + alt_release_fd (index); + ALT_ERRNO = -status; + return -1; + } + + /* return the reference upon success */ + + return index; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_printf.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_printf.c new file mode 100644 index 0000000..f81b290 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_printf.c @@ -0,0 +1,132 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2015 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* + * This file provides a very minimal printf implementation for use with very + * small applications. Only the following format strings are supported: + * %x + * %s + * %c + * %% + */ + +#include +#include "sys/alt_stdio.h" +#ifdef ALT_SEMIHOSTING +#define alt_putchar(x) alt_putcharbuf(x) +#endif +/* + * ALT printf function + */ +void +alt_printf(const char* fmt, ... ) +{ + va_list args; + va_start(args, fmt); + const char *w; + char c; + + /* Process format string. */ + w = fmt; + while ((c = *w++) != 0) + { + /* If not a format escape character, just print */ + /* character. Otherwise, process format string. */ + if (c != '%') + { + alt_putchar(c); + } + else + { + /* Get format character. If none */ + /* available, processing is complete. */ + if ((c = *w++) != 0) + { + if (c == '%') + { + /* Process "%" escape sequence. */ + alt_putchar(c); + } + else if (c == 'c') + { + int v = va_arg(args, int); + alt_putchar(v); + } + else if (c == 'x') + { + /* Process hexadecimal number format. */ + unsigned long v = va_arg(args, unsigned long); + unsigned long digit; + int digit_shift; + + /* If the number value is zero, just print and continue. */ + if (v == 0) + { + alt_putchar('0'); + continue; + } + + /* Find first non-zero digit. */ + digit_shift = 28; + while (!(v & (0xF << digit_shift))) + digit_shift -= 4; + + /* Print digits. */ + for (; digit_shift >= 0; digit_shift -= 4) + { + digit = (v & (0xF << digit_shift)) >> digit_shift; + if (digit <= 9) + c = '0' + digit; + else + c = 'a' + digit - 10; + alt_putchar(c); + } + } + else if (c == 's') + { + /* Process string format. */ + char *s = va_arg(args, char *); + + while(*s) + alt_putchar(*s++); + } + } + else + { + break; + } + } + } +#ifdef ALT_SEMIHOSTING + alt_putbufflush(); +#endif +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_putchar.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_putchar.c new file mode 100644 index 0000000..a8049d7 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_putchar.c @@ -0,0 +1,68 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2015 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#ifdef ALT_USE_DIRECT_DRIVERS +#include "system.h" +#include "sys/alt_driver.h" +#include "sys/alt_stdio.h" +#endif +#ifdef ALT_SEMIHOSTING +#include "sys/alt_stdio.h" +#include "unistd.h" +#endif + +/* + * Uses the ALT_DRIVER_WRITE() macro to call directly to driver if available. + * Otherwise, uses newlib provided putchar() routine. + */ +int +alt_putchar(int c) +{ +#ifdef ALT_SEMIHOSTING + char c1 = (char)(c & 0xff); + return write(STDOUT_FILENO,&c1,1); +#else +#ifdef ALT_USE_DIRECT_DRIVERS + ALT_DRIVER_WRITE_EXTERNS(ALT_STDOUT_DEV); + char c1 = (char)(c & 0xff); + + if (ALT_DRIVER_WRITE(ALT_STDOUT_DEV, &c1, 1, 0) == -1) { + return -1; + } + return c; +#else + return putchar(c); +#endif +#endif +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_putcharbuf.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_putcharbuf.c new file mode 100644 index 0000000..a0e4f2b --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_putcharbuf.c @@ -0,0 +1,80 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2015 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + + +#ifdef ALT_SEMIHOSTING +#include "sys/alt_stdio.h" +#include "unistd.h" + +#ifndef ALT_PUTBUF_SIZE +#define ALT_PUTBUF_SIZE 64 +#endif + +// Buffer for the printed chars +static char buf[ALT_PUTBUF_SIZE] ={0}; +// index into the buffer +static unsigned int fill_index; + +/* + * ALT putcharbuf funtion + * Used only for semihosting. + * Not thread safe! + * This fucntion buffers up chars to be printed until either alt_putbufflush() + * is called or the buffer is full. + * It is called by alt_printf when semihosting is turned on + * Its purpose is to minimize the number of Break 1 issuesd by the semihosting + * libraries. + */ +int +alt_putcharbuf(int c) +{ + buf[fill_index++] = (char)(c & 0xff); + if(fill_index >= ALT_PUTBUF_SIZE) + alt_putbufflush(); + return c; +} + +/* + * ALT putbufflush + * used only for smehosting + * Not thread safe! + * Dumps all the chars in the buffer to STDOUT + */ +int +alt_putbufflush() +{ + int results; + results = write(STDOUT_FILENO,buf,fill_index); + fill_index = 0; + return results; +} +#endif diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_putstr.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_putstr.c new file mode 100644 index 0000000..add3402 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_putstr.c @@ -0,0 +1,64 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2015 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#ifdef ALT_USE_DIRECT_DRIVERS +#include +#include "system.h" +#include "sys/alt_driver.h" +#include "sys/alt_stdio.h" +#endif +#ifdef ALT_SEMIHOSTING +#include +#include "sys/alt_stdio.h" +#include "unistd.h" +#endif + +/* + * Uses the ALT_DRIVER_WRITE() macro to call directly to driver if available. + * Otherwise, uses newlib provided fputs() routine. + */ +int +alt_putstr(const char* str) +{ +#ifdef ALT_SEMIHOSTING + return write(STDOUT_FILENO,str,strlen(str)); +#else +#ifdef ALT_USE_DIRECT_DRIVERS + ALT_DRIVER_WRITE_EXTERNS(ALT_STDOUT_DEV); + return ALT_DRIVER_WRITE(ALT_STDOUT_DEV, str, strlen(str), 0); +#else + return fputs(str, stdout); +#endif +#endif +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_read.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_read.c new file mode 100644 index 0000000..920ab13 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_read.c @@ -0,0 +1,125 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +/* + * The read() system call is used to read a block of data from a file or device. + * This function simply vectors the request to the device driver associated + * with the input file descriptor "file". + * + * ALT_READ is mapped onto the read() system call in alt_syscall.h + */ + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" +#include "sys/alt_driver.h" + +/* + * Provide minimal version that just reads from the stdin device when provided. + */ + +int ALT_READ (int file, void *ptr, size_t len) +{ +#ifdef ALT_STDIN_PRESENT + ALT_DRIVER_READ_EXTERNS(ALT_STDIN_DEV); +#endif + +#if !defined(ALT_STDIN_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(read); +#endif + + switch (file) { +#ifdef ALT_STDIN_PRESENT + case 0: /* stdin file descriptor */ + return ALT_DRIVER_READ(ALT_STDIN_DEV, ptr, len, 0); +#endif /* ALT_STDIN_PRESENT */ + default: + ALT_ERRNO = EBADFD; + return -1; + } +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_READ (int file, void *ptr, size_t len) +{ + alt_fd* fd; + int rval; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* + * If the file has not been opened with read access, or if the driver does + * not provide an implementation of read(), generate an error. Otherwise + * call the drivers read() function to process the request. + */ + + if (((fd->fd_flags & O_ACCMODE) != O_WRONLY) && + (fd->dev->read)) + { + if ((rval = fd->dev->read(fd, ptr, len)) < 0) + { + ALT_ERRNO = -rval; + return -1; + } + return rval; + } + else + { + ALT_ERRNO = EACCES; + } + } + else + { + ALT_ERRNO = EBADFD; + } + return -1; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_release_fd.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_release_fd.c new file mode 100644 index 0000000..c22a97f --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_release_fd.c @@ -0,0 +1,54 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +/* + * alt_release_fd() is called to free an allocated file descriptor. This is + * done by setting the device pointer in the file descriptor structure to zero. + * + * File descriptors correcponding to standard in, standard out and standard + * error cannont be released backed to the pool. They are always reserved. + */ + +void alt_release_fd (int fd) +{ + if (fd > 2) + { + alt_fd_list[fd].fd_flags = 0; + alt_fd_list[fd].dev = 0; + } +} + + + diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_remap_cached.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_remap_cached.c new file mode 100644 index 0000000..6d7c137 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_remap_cached.c @@ -0,0 +1,55 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "sys/alt_warning.h" +#include "sys/alt_cache.h" +#include "system.h" + +/* + * Convert a pointer to a block of uncached memory into a block of cached memory. + * Return a pointer that should be used to access the cached memory. + */ + +void* +alt_remap_cached(volatile void* ptr, alt_u32 len) +{ +#if ALT_CPU_DCACHE_SIZE > 0 +#ifdef ALT_CPU_DCACHE_BYPASS_MASK + return (void*) (((alt_u32)ptr) & ~ALT_CPU_DCACHE_BYPASS_MASK); +#else /* No address mask option enabled. */ + /* Generate a link time error, should this function ever be called. */ + ALT_LINK_ERROR("alt_remap_cached() is not available because CPU is not configured to use bit 31 of address to bypass data cache"); + return NULL; +#endif /* No address mask option enabled. */ +#else /* No data cache */ + /* Nothing needs to be done to the pointer. */ + return (void*) ptr; +#endif /* No data cache */ +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_remap_uncached.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_remap_uncached.c new file mode 100644 index 0000000..7b3a216 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_remap_uncached.c @@ -0,0 +1,54 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "sys/alt_warning.h" +#include "sys/alt_cache.h" +#include "system.h" + +/* + * Convert a pointer to a block of cached memory into a block of uncached memory. + * Return a pointer that should be used to access the uncached memory. + * + * This routine was created for Nios II Gen1 cores which allow mixing cacheable and + * uncachable data in the same data cache line. So, they could take any memory region + * and make it uncached. However, Nios II Gen2 cores don't support mixing cacheable + * and uncachable data in the same data cache line so require the memory region to + * be aligned to a cache line boundary and must be an integer number of cache line + * bytes in size. So, software on a Nios II Gen2 core shouldn't really be using this + * function so it fails with a link error. + */ + +volatile void* +alt_remap_uncached(void* ptr, alt_u32 len) +{ + /* Generate a link time error, should this function ever be called. */ + ALT_LINK_ERROR("alt_remap_uncached() is not available because Nios II Gen2 cores with data caches don't support mixing cacheable and uncacheable data on the same line."); + return NULL; +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_rename.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_rename.c new file mode 100644 index 0000000..26db44d --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_rename.c @@ -0,0 +1,55 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "os/alt_syscall.h" + +/* + * _rename() is used by newlib to rename an existing file. This is unsupported + * in the HAL environment. However a "do-nothing" implementation is still + * provied for newlib compatability. + * + * ALT_RENAME is mapped onto the _rename() system call in alt_syscall.h + */ + +int ALT_RENAME (char *existing, char *new) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(_rename); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_sbrk.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_sbrk.c new file mode 100644 index 0000000..7ab3367 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_sbrk.c @@ -0,0 +1,136 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "os/alt_syscall.h" + +#include "sys/alt_irq.h" +#include "sys/alt_stack.h" + +#include "system.h" + +/* + * sbrk() is called to dynamically extend the data segment for the application. + * Thie input argument "incr" is the size of the block to allocate. + * + * This simple implementation does not perform any bounds checking. Memory will + * be allocated, even if the request region colides with the stack or overflows + * the available physical memory. + * + * ALT_SBRK is mapped onto the sbrk() system call in alt_syscall.h + * + * This function is called by the profiling code to allocate memory so must be + * safe if called from an interrupt context. It must also not be instrumented + * because that would lead to an infinate loop. + */ + +extern char __alt_heap_start[]; /* set by linker */ +extern char __alt_heap_limit[]; /* set by linker */ + +static char *heap_end = __alt_heap_start; + +#if defined(ALT_EXCEPTION_STACK) && defined(ALT_STACK_CHECK) +char * alt_exception_old_stack_limit = NULL; +#endif + +caddr_t ALT_SBRK (int incr) __attribute__ ((no_instrument_function )); + +caddr_t ALT_SBRK (int incr) +{ + alt_irq_context context; + char *prev_heap_end; + + context = alt_irq_disable_all(); + + /* Always return data aligned on a word boundary */ + heap_end = (char *)(((unsigned int)heap_end + 3) & ~3); + +#ifdef ALT_MAX_HEAP_BYTES + /* + * User specified a maximum heap size. Return -1 if it would + * be exceeded by this sbrk call. + */ + if (((heap_end + incr) - __alt_heap_start) > ALT_MAX_HEAP_BYTES) { + alt_irq_enable_all(context); + return (caddr_t)-1; + } +#else + if ((heap_end + incr) > __alt_heap_limit) { + alt_irq_enable_all(context); + return (caddr_t)-1; + } +#endif + + prev_heap_end = heap_end; + heap_end += incr; + +#ifdef ALT_STACK_CHECK + /* + * If the stack and heap are contiguous then extending the heap reduces the + * space available for the stack. If we are still using the default stack + * then adjust the stack limit to note this, while checking for stack + * pointer overflow. + * If the stack limit isn't pointing at the top of the heap then the code + * is using a different stack so none of this needs to be done. + */ + + if (alt_stack_limit() == prev_heap_end) + { + if (alt_stack_pointer() <= heap_end) + alt_report_stack_overflow(); + + alt_set_stack_limit(heap_end); + } + +#ifdef ALT_EXCEPTION_STACK + /* + * If we are executing from the exception stack then compare against the + * stack we switched away from as well. The exception stack is a fixed + * size so doesn't need to be checked. + */ + + if (alt_exception_old_stack_limit == prev_heap_end) + { + if (alt_exception_old_stack_limit <= heap_end) + alt_report_stack_overflow(); + + alt_exception_old_stack_limit = heap_end; + } +#endif + +#endif + + alt_irq_enable_all(context); + + return (caddr_t) prev_heap_end; +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_settod.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_settod.c new file mode 100644 index 0000000..13349b8 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_settod.c @@ -0,0 +1,96 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_errno.h" +#include "sys/alt_alarm.h" +#include "os/alt_syscall.h" + +/* + * "alt_timezone" and "alt_resettime" are the values of the the reset time and + * time zone set through the last call to settimeofday(). By default they are + * zero initialised. + */ + +extern struct timezone alt_timezone; +extern struct timeval alt_resettime; + +/* + * Macro defining the number of micoseconds in a second. + */ + +#define ALT_US (1000000) + + +/* + * settimeofday() can be called to calibrate the system clock, so that + * subsequent calls to gettimeofday() will return the elapsed "wall clock" + * time. + * + * This is done by updating the global structures "alt_resettime" and + * "alt_timezone" so that an immediate call to gettimeofday() would return + * the value specified by "t" and "tz". + * + * Warning: if this function is called concurrently with a call to + * gettimeofday(), the value returned by gettimeofday() will be unreliable. + * + * ALT_SETTIMEOFDAY is mapped onto the settimeofday() system call in + * alt_syscall.h + */ + +int ALT_SETTIMEOFDAY (const struct timeval *t, + const struct timezone *tz) +{ + alt_u32 nticks = alt_nticks (); + alt_u32 tick_rate = alt_ticks_per_second (); + + /* If there is a system clock available, update the current time */ + + if (tick_rate) + { + alt_resettime.tv_sec = t->tv_sec - nticks/tick_rate; + alt_resettime.tv_usec = t->tv_usec - + ((nticks*(ALT_US/tick_rate))%ALT_US); + + alt_timezone.tz_minuteswest = tz->tz_minuteswest; + alt_timezone.tz_dsttime = tz->tz_dsttime; + + return 0; + } + + /* There's no system clock available */ + + ALT_ERRNO = ENOSYS; + return -1; +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_software_exception.S b/FPGA_nios/hit_pat_bsp/HAL/src/alt_software_exception.S new file mode 100644 index 0000000..0a9381e --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_software_exception.S @@ -0,0 +1,53 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + + /* + * This file provides the global symbol: software_exception. It is provided to + * support legacy code, and should not be used by new software. + * + * It is used by legacy code to invoke the software exception handler as + * defined by version 1.0 of the Nios II kit. It should only be used when you + * are providing your own interrupt entry point, i.e. you are not using + * alt_irq_entry. + */ + +#include "system.h" + + /* + * Pull in the exception handler. + */ + + .globl alt_exception + + .section .exceptions.entry.label, "xa" + + .globl software_exception + .type software_exception, @function +software_exception: diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_stat.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_stat.c new file mode 100644 index 0000000..c196d0c --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_stat.c @@ -0,0 +1,59 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include +#include + +#include "os/alt_syscall.h" + +/* + * The stat() function is similar to the fstat() function in that it is used to + * obtain status information about a file. Instead of using an open file + * descriptor (like fstat()), stat() takes the name of a file as an input + * argument. + * + * ALT_STAT is mapped onto the stat() system call in alt_syscall.h + */ + +int ALT_STAT (const char *file, struct stat *st) +{ + int fd; + int rc; + + fd = open (file, 0); + rc = fstat (fd, st); + close (fd); + + return rc; +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_tick.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_tick.c new file mode 100644 index 0000000..23719b1 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_tick.c @@ -0,0 +1,149 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_irq.h" +#include "sys/alt_alarm.h" +#include "os/alt_hooks.h" +#include "alt_types.h" + +/* + * "_alt_tick_rate" is used to store the value of the system clock frequency + * in ticks per second. It is initialised to zero, which corresponds to there + * being no system clock facility available. + */ + +alt_u32 _alt_tick_rate = 0; + +/* + * "_alt_nticks" is the number of system clock ticks that have elapsed since + * reset. + */ + +volatile alt_u32 _alt_nticks = 0; + +/* + * "alt_alarm_list" is the head of a linked list of registered alarms. This is + * initialised to be an empty list. + */ + +ALT_LLIST_HEAD(alt_alarm_list); + +/* + * alt_alarm_stop() is called to remove an alarm from the list of registered + * alarms. Alternatively an alarm can unregister itself by returning zero when + * the alarm executes. + */ + +void alt_alarm_stop (alt_alarm* alarm) +{ + alt_irq_context irq_context; + + irq_context = alt_irq_disable_all(); + alt_llist_remove (&alarm->llist); + alt_irq_enable_all (irq_context); +} + +/* + * alt_tick() is periodically called by the system clock driver in order to + * process the registered list of alarms. Each alarm is registed with a + * callback interval, and a callback function, "callback". + * + * The return value of the callback function indicates how many ticks are to + * elapse until the next callback. A return value of zero indicates that the + * alarm should be deactivated. + * + * alt_tick() is expected to run at interrupt level. + */ + +void alt_tick (void) +{ + alt_alarm* next; + alt_alarm* alarm = (alt_alarm*) alt_alarm_list.next; + + alt_u32 next_callback; + + /* update the tick counter */ + + _alt_nticks++; + + /* process the registered callbacks */ + + while (alarm != (alt_alarm*) &alt_alarm_list) + { + next = (alt_alarm*) alarm->llist.next; + + /* + * Upon the tick-counter rolling over it is safe to clear the + * roll-over flag; once the flag is cleared this (or subsequnt) + * tick events are enabled to generate an alarm event. + */ + if ((alarm->rollover) && (_alt_nticks == 0)) + { + alarm->rollover = 0; + } + + /* if the alarm period has expired, make the callback */ + if ((alarm->time <= _alt_nticks) && (alarm->rollover == 0)) + { + next_callback = alarm->callback (alarm->context); + + /* deactivate the alarm if the return value is zero */ + + if (next_callback == 0) + { + alt_alarm_stop (alarm); + } + else + { + alarm->time += next_callback; + + /* + * If the desired alarm time causes a roll-over, set the rollover + * flag. This will prevent the subsequent tick event from causing + * an alarm too early. + */ + if(alarm->time < _alt_nticks) + { + alarm->rollover = 1; + } + } + } + alarm = next; + } + + /* + * Update the operating system specific timer facilities. + */ + + ALT_OS_TIME_TICK(); +} + diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_times.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_times.c new file mode 100644 index 0000000..6543164 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_times.c @@ -0,0 +1,71 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/alt_errno.h" +#include "sys/alt_alarm.h" +#include "os/alt_syscall.h" + +/* + * The times() function is used by newlib to obtain elapsed time information. + * The return value is the elapsed time since reset in system clock ticks. Note + * that this is distinct from the strict Posix version of times(), which should + * return the time since: 0 hours, 0 minutes, 0 seconds, January 1, 1970, GMT. + * + * The input structure is filled in with time accounting information. This + * implementation attributes all cpu time to the system. + * + * ALT_TIMES is mapped onto the times() system call in alt_syscall.h + */ + +clock_t ALT_TIMES (struct tms *buf) +{ + clock_t ticks = alt_nticks(); + + /* If there is no system clock present, generate an error */ + + if (!alt_ticks_per_second()) + { + ALT_ERRNO = ENOSYS; + return 0; + } + + /* Otherwise return the elapsed time */ + + buf->tms_utime = 0; + buf->tms_stime = ticks; + buf->tms_cutime = 0; + buf->tms_cstime = 0; + + return ticks; +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_uncached_free.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_uncached_free.c new file mode 100644 index 0000000..0d725c0 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_uncached_free.c @@ -0,0 +1,53 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "sys/alt_warning.h" +#include "sys/alt_cache.h" +#include "system.h" + +/* + * Free a block of uncached memory. + */ + +void +alt_uncached_free(volatile void* ptr) +{ +#if ALT_CPU_DCACHE_SIZE > 0 +#ifdef ALT_CPU_DCACHE_BYPASS_MASK + free((void*) (((alt_u32)ptr) & ~ALT_CPU_DCACHE_BYPASS_MASK)); +#else /* No address mask option enabled. */ + /* Generate a link time error, should this function ever be called. */ + ALT_LINK_ERROR("alt_uncached_free() is not available because CPU is not configured to use bit 31 of address to bypass data cache"); +#endif /* No address mask option enabled. */ +#else /* No data cache */ + /* Nothing needs to be done to the pointer. */ + free((void*)ptr); +#endif /* No data cache */ +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_uncached_malloc.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_uncached_malloc.c new file mode 100644 index 0000000..75af9b0 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_uncached_malloc.c @@ -0,0 +1,77 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include "sys/alt_warning.h" +#include "sys/alt_cache.h" +#include "system.h" + +/* + * Allocate a block of uncached memory. + * Return pointer to the block of memory or NULL if can't allocate it. + */ + +volatile void* +alt_uncached_malloc(size_t size) +{ +#if ALT_CPU_DCACHE_SIZE > 0 +#ifdef ALT_CPU_DCACHE_BYPASS_MASK + + void* ptr; + + /* Round up size to an integer number of data cache lines. Required to guarantee that + * cacheable and non-cacheable data won't be mixed on the same cache line. */ + const size_t num_lines = (size + ALT_CPU_DCACHE_LINE_SIZE - 1) / ALT_CPU_DCACHE_LINE_SIZE; + const size_t aligned_size = num_lines * ALT_CPU_DCACHE_LINE_SIZE; + + /* Use memalign() Newlib routine to allocate starting on a data cache aligned address. + * Required to guarantee that cacheable and non-cacheable data won't be mixed on the + * same cache line. */ + ptr = memalign(ALT_CPU_DCACHE_LINE_SIZE, aligned_size); + + if (ptr == NULL) { + return NULL; /* Out of memory */ + } + + /* Ensure that the memory region isn't in the data cache. */ + alt_dcache_flush(ptr, aligned_size); + + return (volatile void*) (((alt_u32)ptr) | ALT_CPU_DCACHE_BYPASS_MASK); + +#else /* No address mask option enabled. */ + /* Generate a link time error, should this function ever be called. */ + ALT_LINK_ERROR("alt_uncached_malloc() is not available because CPU is not configured to use bit 31 of address to bypass data cache"); + return NULL; +#endif /* No address mask option enabled. */ +#else /* No data cache */ + /* Just use regular malloc. */ + return malloc(size); +#endif /* No data cache */ +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_unlink.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_unlink.c new file mode 100644 index 0000000..606f019 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_unlink.c @@ -0,0 +1,55 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "os/alt_syscall.h" + +/* + * unlink() is used by newlib to delete an existing link to a file. This is + * unsupported in the HAL environment. However a "do-nothing" implementation + * is still provied for newlib compatability. + * + * ALT_UNLINK is mapped onto the unlink() system call in alt_syscall.h + */ + +int ALT_UNLINK (char *name) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(unlink); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_usleep.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_usleep.c new file mode 100644 index 0000000..86533cb --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_usleep.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2003 Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * ------------ + * + * Altera does not recommend, suggest or require that this reference design + * file be used in conjunction or combination with any other product. + */ + +#include +#include +#include + +#include "sys/alt_alarm.h" +#include "priv/alt_busy_sleep.h" +#include "os/alt_syscall.h" + +#include "includes.h" + +/* + * Macro defining the number of micoseconds in a second. + */ + +#define ALT_US (1000000) + +/* + * This implementation of usleep overrides the default provided in the HAL/src + * directory of the altera_nios2 component. When possible, this + * implementation uses the uC/OS-II OSTimeDly function to block the current + * thread, rather than using a busy loop. This allows other threads to execute + * while the current thread is sleeping. + * + * ALT_USLEEP is mapped onto the usleep() system call in alt_syscall.h + */ + +#if defined (__GNUC__) && __GNUC__ >= 4 +int ALT_USLEEP (useconds_t us) +#else +unsigned int ALT_USLEEP (unsigned int us) +#endif +{ + alt_u32 ticks; + alt_u32 tick_rate; + + /* + * If the O/S hasn't started yet, then we delay using a busy loop, rather than + * OSTimeDly (since this would fail). The use of a busy loop is acceptable, + * since the system is still running in a single-threaded mode. + */ + + if (OSRunning == OS_FALSE) + { + return alt_busy_sleep (us); + } + + /* + * Calculate the number of whole system clock ticks to delay. + */ + + tick_rate = alt_ticks_per_second (); + ticks = (us/ALT_US)* tick_rate + ((us%ALT_US)*tick_rate)/ALT_US; + + /* + * OSTimeDly can only delay for a maximum of 0xffff ticks, so if the requested + * delay is greater than that, we need to break it down into a number of + * seperate delays. + */ + + while (ticks > 0xffff) + { + OSTimeDly(0xffff); + ticks -= 0xffff; + } + + OSTimeDly ((INT16U) (ticks)); + + /* + * Now delay by the remainder using a busy loop. This is here in order to + * provide very short delays of less than one clock tick. + */ + + alt_busy_sleep (us%(ALT_US/tick_rate)); + + return 0; +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_wait.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_wait.c new file mode 100644 index 0000000..dd768ad --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_wait.c @@ -0,0 +1,52 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "os/alt_syscall.h" + +/* + * wait() is used by newlib to wait for all child processes to exit. Since the + * HAL does not support spawning child processes, this returns immediately as + * there can't be anythign to wait for. + * + * ALT_WAIT is mapped onto the wait() system call in alt_syscall.h + */ + +int ALT_WAIT (int *status) +{ + *status = 0; + + ALT_ERRNO = ECHILD; + + return -1; +} + diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_write.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_write.c new file mode 100644 index 0000000..d161cdf --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_write.c @@ -0,0 +1,138 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +#include "sys/alt_log_printf.h" + +/* + * The write() system call is used to write a block of data to a file or + * device. This function simply vectors the request to the device driver + * associated with the input file descriptor "file". + * + * ALT_WRITE is mapped onto the write() system call in alt_syscall.h + */ + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" +#include "sys/alt_driver.h" + +/* + * Provide minimal version that just writes to the stdout/stderr devices + * when provided. + */ + +int ALT_WRITE (int file, const void *ptr, size_t len) +{ +#ifdef ALT_STDOUT_PRESENT + ALT_DRIVER_WRITE_EXTERNS(ALT_STDOUT_DEV); +#endif +#ifdef ALT_STDERR_PRESENT + ALT_DRIVER_WRITE_EXTERNS(ALT_STDERR_DEV); +#endif + +#if !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(write); +#endif + + switch (file) { +#ifdef ALT_STDOUT_PRESENT + case 1: /* stdout file descriptor */ + return ALT_DRIVER_WRITE(ALT_STDOUT_DEV, ptr, len, 0); +#endif /* ALT_STDOUT_PRESENT */ +#ifdef ALT_STDERR_PRESENT + case 2: /* stderr file descriptor */ + return ALT_DRIVER_WRITE(ALT_STDERR_DEV, ptr, len, 0); +#endif /* ALT_STDERR_PRESENT */ + default: + ALT_ERRNO = EBADFD; + return -1; + } +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_WRITE (int file, const void *ptr, size_t len) +{ + alt_fd* fd; + int rval; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* + * If the file has not been opened with write access, or if the driver does + * not provide an implementation of write(), generate an error. Otherwise + * call the drivers write() function to process the request. + */ + + if (((fd->fd_flags & O_ACCMODE) != O_RDONLY) && fd->dev->write) + { + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_WRITE_FUNCTION(ptr,len); + + if ((rval = fd->dev->write(fd, ptr, len)) < 0) + { + ALT_ERRNO = -rval; + return -1; + } + return rval; + } + else + { + ALT_ERRNO = EACCES; + } + } + else + { + ALT_ERRNO = EBADFD; + } + return -1; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/altera_nios2_gen2_irq.c b/FPGA_nios/hit_pat_bsp/HAL/src/altera_nios2_gen2_irq.c new file mode 100644 index 0000000..4dfd940 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/altera_nios2_gen2_irq.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2009 Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * altera_nios2_gen2_irq.c - Support for Nios II internal interrupt controller. + * + */ + +#include "sys/alt_irq.h" +#include "altera_nios2_gen2_irq.h" + +/* + * To initialize the internal interrupt controller, just clear the IENABLE + * register so that all possible IRQs are disabled. + */ +void altera_nios2_gen2_irq_init(void) +{ + NIOS2_WRITE_IENABLE(0); +} diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/crt0.S b/FPGA_nios/hit_pat_bsp/HAL/src/crt0.S new file mode 100644 index 0000000..f12623b --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/crt0.S @@ -0,0 +1,521 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "system.h" +#include "nios2.h" + +/* Setup header files to work with assembler code. */ +#define ALT_ASM_SRC + +/* Debug logging facility */ +#include "sys/alt_log_printf.h" + +/*************************************************************************\ +| MACROS | +\*************************************************************************/ + +/* + * The new build tools explicitly define macros when alt_load() + * must be called. The define ALT_LOAD_EXPLICITLY_CONTROLLED tells us that + * those macros are controlling if alt_load() needs to be called. + */ +#ifdef ALT_LOAD_EXPLICITLY_CONTROLLED + +/* Need to call alt_load() if any of these sections are being copied. */ +#if defined(ALT_LOAD_COPY_RODATA) || defined(ALT_LOAD_COPY_RWDATA) || defined(ALT_LOAD_COPY_EXCEPTIONS) +#define CALL_ALT_LOAD +#endif + +#else /* !ALT_LOAD_EXPLICITLY_CONTROLLED */ + +/* + * The legacy build tools use the following macros to detect when alt_load() + * needs to be called. + */ + +#define __ALT_LOAD_SECTIONS(res, text, rodata, exc) \ + ((res##_BASE != rodata##_BASE) || \ + (res##_BASE != rwdata##_BASE) || \ + (res##_BASE != exc##_BASE)) + +#define _ALT_LOAD_SECTIONS(res, text, rodata, exc) \ + __ALT_LOAD_SECTIONS(res, text, rodata, exc) + +#define ALT_LOAD_SECTIONS _ALT_LOAD_SECTIONS(ALT_RESET_DEVICE, \ + ALT_RODATA_DEVICE, \ + ALT_RWDATA_DEVICE, \ + ALT_EXCEPTIONS_DEVICE) + +/* Call alt_load() if there is no bootloader and ALT_LOAD_SECTIONS isn't 0. */ +#if defined(ALT_NO_BOOTLOADER) && ALT_LOAD_SECTIONS +#define CALL_ALT_LOAD +#endif + +#endif /* !ALT_LOAD_EXPLICITLY_CONTROLLED */ + +/* + * When the legacy build tools define a macro called ALT_NO_BOOTLOADER, + * it indicates that initialization code is allowed at the reset address. + * The new build tools define a macro called ALT_ALLOW_CODE_AT_RESET for + * the same purpose. + */ +#ifdef ALT_NO_BOOTLOADER +#define ALT_ALLOW_CODE_AT_RESET +#endif + +/*************************************************************************\ +| EXTERNAL REFERENCES | +\*************************************************************************/ + +/* + * The entry point for user code is either "main" in hosted mode, or + * "alt_main" in standalone mode. These are explicitly referenced here, + * to ensure they are built into the executable. This allows the user + * to build them into libraries, rather than supplying them in object + * files at link time. + */ + .globl main + .globl alt_main + +/* + * Create a reference to the software multiply/divide and trap handers, + * so that if they are provided, they will appear in the executable. + */ +#ifndef ALT_NO_INSTRUCTION_EMULATION + .globl alt_exception_muldiv +#endif +#ifdef ALT_TRAP_HANDLER + .globl alt_exception_trap +#endif + +/* + * Linker defined symbols used to initialize bss. + */ +.globl __bss_start +.globl __bss_end + +/*************************************************************************\ +| RESET SECTION (.entry) | +\*************************************************************************/ + +/* + * This is the reset entry point for Nios II. + * + * At reset, only the cache line which contain the reset vector is + * initialized by the hardware. The code within the first cache line + * initializes the remainder of the instruction cache. + */ + + .section .entry, "xa" + .align 5 + +/* + * Explicitly allow the use of r1 (the assembler temporary register) + * within this code. This register is normally reserved for the use of + * the assembler. + */ + .set noat + +/* + * Some tools want to know where the reset vector is. + * Code isn't always provided at the reset vector but at least the + * __reset label always contains the reset vector address because + * it is defined at the start of the .entry section. + */ + + .globl __reset + .type __reset, @function +__reset: + +/* + * Initialize the instruction cache if present (i.e. size > 0) and + * reset code is allowed unless optimizing for RTL simulation. + * RTL simulations can ensure the instruction cache is already initialized + * so skipping this loop speeds up RTL simulation. + * + * When ECC is present, need to execute initi for each word address + * to ensure ECC parity bits in cache RAM get initialized. + */ + +#if NIOS2_ICACHE_SIZE > 0 && defined(ALT_ALLOW_CODE_AT_RESET) && (!defined(ALT_SIM_OPTIMIZE) || defined(NIOS2_ECC_PRESENT)) + /* Assume the instruction cache size is always a power of two. */ +#if NIOS2_ICACHE_SIZE > 0x8000 + movhi r2, %hi(NIOS2_ICACHE_SIZE) +#else + movui r2, NIOS2_ICACHE_SIZE +#endif + +0: + initi r2 + addi r2, r2, -NIOS2_ICACHE_LINE_SIZE + bgt r2, zero, 0b +1: + + /* + * The following debug information tells the ISS not to run the loop above + * but to perform its actions using faster internal code. + */ + .pushsection .debug_alt_sim_info + .int 1, 1, 0b, 1b + .popsection +#endif /* Initialize Instruction Cache */ + +/* + * Jump to the _start entry point in the .text section if reset code + * is allowed or if optimizing for RTL simulation. + */ +#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE) + /* Jump to the _start entry point in the .text section. */ + movhi r1, %hi(_start) + ori r1, r1, %lo(_start) + jmp r1 + + .size __reset, . - __reset +#endif /* Jump to _start */ + +/* + * When not using exit, provide an _exit symbol to prevent unresolved + * references to _exit from the linker script. + */ +#ifdef ALT_NO_EXIT + .globl _exit +_exit: +#endif + +/*************************************************************************\ +| TEXT SECTION (.text) | +\*************************************************************************/ + +/* + * Start of the .text section, and also the code entry point when + * the code is executed by a bootloader rather than directly from reset. + */ + .section .text + .align 2 + + .globl _start + .type _start, @function +_start: + +#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) + /* + * Ensure that the current register set is 0 upon + * entry to this code. Switch register set to 0 by + * writing zero to SSTATUS register and executing an ERET instruction + * to set STATUS.CRS to 0. + */ + + /* Get the current register set number (STATUS.CRS). */ + rdctl r2, status + andi r2, r2, NIOS2_STATUS_CRS_MSK + + /* Skip switching register set if STATUS.CRS is 0. */ + beq r2, zero, 0f + + /* Set SSTATUS to 0 to get to set SSTATUS.PRS to 0. */ + .set nobreak + movui sstatus, 0 + .set break + + /* Switch to register set 0 and jump to label. */ + movhi ea, %hi(0f) + ori ea, ea, %lo(0f) + eret + +0: +#endif /* NIOS2_NUM_OF_SHADOW_REG_SETS > 0 */ + +/* + * Initialize the data cache if present (i.e. size > 0). + * Skip initialization if optimizing for RTL simulation and ECC isn't present. + * RTL simulations can ensure the data cache tag RAM is already initialized + * (but not the data RAM for ECC) so skipping this speeds up RTL simulation. + * + * When ECC is present, need to execute initd for each word address + * to ensure ECC parity bits in data RAM get initialized. + * Otherwise, only need to execute initd for each line address. + */ + +#if NIOS2_DCACHE_SIZE > 0 && (!defined(ALT_SIM_OPTIMIZE) || defined(NIOS2_ECC_PRESENT)) + + /* Assume the data cache size is always a power of two. */ +#if NIOS2_DCACHE_SIZE > 0x8000 + movhi r2, %hi(NIOS2_DCACHE_SIZE) +#else + movui r2, NIOS2_DCACHE_SIZE +#endif + +0: + initd 0(r2) +#ifdef NIOS2_ECC_PRESENT + addi r2, r2, -4 +#else + addi r2, r2, -NIOS2_DCACHE_LINE_SIZE +#endif + bgt r2, zero, 0b +1: + + /* + * The following debug information tells the ISS not to run the loop above + * but to perform its actions using faster internal code. + */ + .pushsection .debug_alt_sim_info + .int 2, 1, 0b, 1b + .popsection +#endif /* Initialize Data Cache */ + + /* Log that caches have been initialized. */ + ALT_LOG_PUTS(alt_log_msg_cache) + + /* Log that the stack pointer is about to be setup. */ + ALT_LOG_PUTS(alt_log_msg_stackpointer) + + /* + * Now that the caches are initialized, set up the stack pointer and global pointer. + * The values provided by the linker are assumed to be correctly aligned. + */ + movhi sp, %hi(__alt_stack_pointer) + ori sp, sp, %lo(__alt_stack_pointer) + movhi gp, %hi(_gp) + ori gp, gp, %lo(_gp) + +#ifdef NIOS2_ECC_PRESENT + /* + * Initialize all general-purpose registers so that ECC can be enabled + * later without accidentally triggering a spurious ECC error. + */ + movui r1, 0 + movui r2, 0 + movui r3, 0 + movui r4, 0 + movui r5, 0 + movui r6, 0 + movui r7, 0 + movui r8, 0 + movui r9, 0 + movui r10, 0 + movui r11, 0 + movui r12, 0 + movui r13, 0 + movui r14, 0 + movui r15, 0 + movui r16, 0 + movui r17, 0 + movui r18, 0 + movui r19, 0 + movui r20, 0 + movui r21, 0 + movui r22, 0 + movui r23, 0 + /* Skip r24 (et) because only exception handler should write it. */ + /* Skip r25 (bt) because only debugger should write it. */ + /* Skip r26 (gp) because it is already been initialized. */ + /* Skip r27 (sp) because it is already been initialized. */ + movui r28, 0 /* fp */ + movui r29, 0 /* ea */ + .set nobreak + movui r30, 0 /* sstatus */ + .set break + movui r31, 0 /* ra */ + +#endif /* NIOS2_ECC_PRESENT */ + +#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) + /* + * Setup registers in shadow register sets + * from 1 to NIOS2_NUM_OF_SHADOW_REG_SETS. + */ + + movui r2, 0 /* Contains value written into STATUS */ + movui r3, NIOS2_NUM_OF_SHADOW_REG_SETS /* counter */ + movhi r4, 1 /* Constant to increment STATUS.PRS */ + +.Linitialize_shadow_registers: + /* Increment STATUS.PRS */ + add r2, r2, r4 + wrctl status, r2 + + /* Clear r0 in the shadow register set (not done by hardware) */ + wrprs r0, r0 + + /* Write the GP in previous register set */ + wrprs gp, gp + + /* + * Only write the SP in previous register set + * if using the separate exception stack. For normal case (single stack), + * funnel code would read the SP from previous register set with a RDPRS. + */ +#ifdef ALT_INTERRUPT_STACK + movhi et, %hiadj(__alt_interrupt_stack_pointer) + addi et, et, %lo(__alt_interrupt_stack_pointer) + wrprs sp, et +#endif /* ALT_INTERRUPT_STACK */ + +#ifdef NIOS2_ECC_PRESENT + /* + * Initialize all general-purpose registers so that ECC can be enabled + * later without accidentally triggering a spurious ECC error. + */ + wrprs r1, r0 + wrprs r2, r0 + wrprs r3, r0 + wrprs r4, r0 + wrprs r5, r0 + wrprs r6, r0 + wrprs r7, r0 + wrprs r8, r0 + wrprs r9, r0 + wrprs r10, r0 + wrprs r11, r0 + wrprs r12, r0 + wrprs r13, r0 + wrprs r14, r0 + wrprs r15, r0 + wrprs r16, r0 + wrprs r17, r0 + wrprs r18, r0 + wrprs r19, r0 + wrprs r20, r0 + wrprs r21, r0 + wrprs r22, r0 + wrprs r23, r0 + /* Skip r24 (et) because only exception handler should write it. */ + /* Skip r25 (bt) because only debugger should write it. */ + /* Skip r26 (gp) because it is already been initialized. */ + /* Skip r27 (sp) because it was initialized above or will be by a rdprs if not above */ + wrprs r28, r0 /* fp */ + wrprs r29, r0 /* ea */ + wrprs r30, r0 /* ba */ + wrprs r31, r0 /* ra */ +#endif /* NIOS2_ECC_PRESENT */ + + /* Decrement shadow register set counter */ + addi r3, r3, -1 + + /* Done if index is 0. */ + bne r3, zero, .Linitialize_shadow_registers +#endif /* (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) */ + +/* + * Clear the BSS if not optimizing for RTL simulation. + * + * This uses the symbols: __bss_start and __bss_end, which are defined + * by the linker script. They mark the begining and the end of the bss + * region. The linker script guarantees that these values are word aligned. + */ +#ifndef ALT_SIM_OPTIMIZE + /* Log that the BSS is about to be cleared. */ + ALT_LOG_PUTS(alt_log_msg_bss) + + movhi r2, %hi(__bss_start) + ori r2, r2, %lo(__bss_start) + + movhi r3, %hi(__bss_end) + ori r3, r3, %lo(__bss_end) + + beq r2, r3, 1f + +0: + stw zero, (r2) + addi r2, r2, 4 + bltu r2, r3, 0b + +1: + + /* + * The following debug information tells the ISS not to run the loop above + * but to perform its actions using faster internal code. + */ + .pushsection .debug_alt_sim_info + .int 3, 1, 0b, 1b + .popsection +#endif /* ALT_SIM_OPTIMIZE */ + +/* + * Turn off the use of r1 (the assembler temporary register) + * so that call instructions can be safely relaxed across a + * 256MB boundary if needed + */ + .set at + +/* + * The alt_load() facility is normally used when there is no bootloader. + * It copies some sections into RAM so it acts like a mini-bootloader. + */ +#ifdef CALL_ALT_LOAD + +#ifdef ALT_STACK_CHECK + /* + * If the user has selected stack checking then we need to set up a safe + * value in the stack limit register so that the relocation functions + * don't think the stack has overflowed (the contents of the rwdata + * section aren't defined until alt_load() has been called). + */ + mov et, zero +#endif + + call alt_load + +#endif /* CALL_ALT_LOAD */ + +#ifdef ALT_STACK_CHECK + /* + * Set up the stack limit (if required). The linker has set up the + * copy of the variable which is in memory. + */ + + ldw et, %gprel(alt_stack_limit_value)(gp) +#endif + + /* Log that alt_main is about to be called. */ + ALT_LOG_PUTS(alt_log_msg_alt_main) + + /* Call the C entry point. It should never return. */ + call alt_main + + /* Wait in infinite loop in case alt_main does return. */ +alt_after_alt_main: + br alt_after_alt_main + + .size _start, . - _start + +/* + * Add information about the stack base if stack overflow checking is enabled. + */ +#ifdef ALT_STACK_CHECK + .globl alt_stack_limit_value + .section .sdata,"aws",@progbits + .align 2 + .type alt_stack_limit_value, @object + .size alt_stack_limit_value, 4 +alt_stack_limit_value: + .long __alt_stack_limit +#endif diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/os_cpu_a.S b/FPGA_nios/hit_pat_bsp/HAL/src/os_cpu_a.S new file mode 100644 index 0000000..ce05145 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/os_cpu_a.S @@ -0,0 +1,270 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/********************************************************************************************************* + * uC/OS-II + * The Real-Time Kernel + * File : os_cpu_a.S + * For : uC/OS Real-time multitasking kernel for the Nios2 SoftCore Processor + * Written by : IS + * + *********************************************************************************************************/ + +#include "os_cfg.h" + + .text + +/********************************************************************************************************* + * PERFORM A CONTEXT SWITCH + * void OSCtxSw(void) - from task level + * void OSIntCtxSw(void) - from interrupt level + * + * Note(s): 1) Upon entry, + * OSTCBCur points to the OS_TCB of the task to suspend + * OSTCBHighRdy points to the OS_TCB of the task to resume + * + *********************************************************************************************************/ + .global OSIntCtxSw + .global OSCtxSw + +OSIntCtxSw: +OSCtxSw: + + /* + * Save the remaining registers to the stack. + */ + + addi sp, sp, -44 + +#ifdef ALT_STACK_CHECK + + bltu sp, et, .Lstack_overflow + +#endif + +#if OS_THREAD_SAFE_NEWLIB + ldw r3, %gprel(_impure_ptr)(gp) /* load the pointer */ +#endif /* OS_THREAD_SAFE_NEWLIB */ + + ldw r4, %gprel(OSTCBCur)(gp) + + stw ra, 0(sp) + stw fp, 4(sp) + stw r23, 8(sp) + stw r22, 12(sp) + stw r21, 16(sp) + stw r20, 20(sp) + stw r19, 24(sp) + stw r18, 28(sp) + stw r17, 32(sp) + stw r16, 36(sp) + +#if OS_THREAD_SAFE_NEWLIB + /* + * store the current value of _impure_ptr so it can be restored + * later; _impure_ptr is asigned on a per task basis. It is used + * by Newlib to achieve reentrancy. + */ + + stw r3, 40(sp) /* save the impure pointer */ +#endif /* OS_THREAD_SAFE_NEWLIB */ + + /* + * Save the current tasks stack pointer into the current tasks OS_TCB. + * i.e. OSTCBCur->OSTCBStkPtr = sp; + */ + + stw sp, (r4) /* save the stack pointer (OSTCBStkPtr */ + /* is the first element in the OS_TCB */ + /* structure. */ + + /* + * Call the user definable OSTaskSWHook() + */ + + call OSTaskSwHook + +0: + +9: + + /* + * OSTCBCur = OSTCBHighRdy; + * OSPrioCur = OSPrioHighRdy; + */ + + ldw r4, %gprel(OSTCBHighRdy)(gp) + ldb r5, %gprel(OSPrioHighRdy)(gp) + + stw r4, %gprel(OSTCBCur)(gp) /* set the current task to be the new task */ + stb r5, %gprel(OSPrioCur)(gp) /* store the new task's priority as the current */ + /* task's priority */ + + /* + * Set the stack pointer to point to the new task's stack + */ + + ldw sp, (r4) /* the stack pointer is the first entry in the OS_TCB structure */ + +#if defined(ALT_STACK_CHECK) && (OS_TASK_CREATE_EXT_EN > 0) + + ldw et, 8(r4) /* load the new stack limit */ + +#endif + +#if OS_THREAD_SAFE_NEWLIB + /* + * restore the value of _impure_ptr ; _impure_ptr is asigned on a + * per task basis. It is used by Newlib to achieve reentrancy. + */ + + ldw r3, 40(sp) /* load the new impure pointer */ +#endif /* OS_THREAD_SAFE_NEWLIB */ + + /* + * Restore the saved registers for the new task. + */ + + ldw ra, 0(sp) + ldw fp, 4(sp) + ldw r23, 8(sp) + ldw r22, 12(sp) + ldw r21, 16(sp) + ldw r20, 20(sp) + ldw r19, 24(sp) + ldw r18, 28(sp) + ldw r17, 32(sp) + ldw r16, 36(sp) + +#if OS_THREAD_SAFE_NEWLIB + + stw r3, %gprel(_impure_ptr)(gp) /* update _impure_ptr */ + +#endif /* OS_THREAD_SAFE_NEWLIB */ + +#if defined(ALT_STACK_CHECK) && (OS_TASK_CREATE_EXT_EN > 0) + + stw et, %gprel(alt_stack_limit_value)(gp) + +#endif + + addi sp, sp, 44 + + /* + * resume execution of the new task. + */ + + ret + +#ifdef ALT_STACK_CHECK + +.Lstack_overflow: + break 3 + +#endif + +.set OSCtxSw_SWITCH_PC,0b-OSCtxSw + +/********************************************************************************************************* + * START THE HIGHEST PRIORITY TASK + * void OSStartHighRdy(void) + * + * Note(s): 1) Upon entry, + * OSTCBCur points to the OS_TCB of the task to suspend + * OSTCBHighRdy points to the OS_TCB of the task to resume + * + *********************************************************************************************************/ + .global OSStartHighRdy + +OSStartHighRdy: + + /* + * disable interrupts so that the scheduler doesn't run while + * we're initialising this task. + */ + rdctl r18, status + subi r17, zero, 2 /* r17 = 0xfffffffe */ + and r18, r18, r17 + wrctl status, r18 + + /* + * Call the user definable OSTaskSWHook() + */ + + call OSTaskSwHook + + /* + * set OSRunning = TRUE. + */ + + movi r18, 1 /* set r18 to the value 'TRUE' */ + stb r18, %gprel(OSRunning)(gp) /* save this to OSRunning */ + +#if defined(ALT_STACK_CHECK) && (OS_TASK_CREATE_EXT_EN == 0) + + mov et, zero /* Don't check stack limits */ + stw et, %gprel(alt_stack_limit_value)(gp) + +#endif + + /* + * start execution of the new task. + */ + + br 9b + +/********************************************************************************************************* + * CALL THE TASK INITILISATION FUNCTION + * void OSStartTsk(void) + *********************************************************************************************************/ + + .global OSStartTsk + +OSStartTsk: + /* This instruction is never executed. Its here to make the + * backtrace work right + */ + movi sp, 0 + + /* Enable interrupts */ + rdctl r2, status + ori r2, r2, 0x1 + wrctl status, r2 + + ldw r2, 4(sp) + ldw r4, 0(sp) + + addi sp, sp, 8 + + callr r2 + + nop diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/os_cpu_c.c b/FPGA_nios/hit_pat_bsp/HAL/src/os_cpu_c.c new file mode 100644 index 0000000..86648e0 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/HAL/src/os_cpu_c.c @@ -0,0 +1,243 @@ +/*********************************************************************************************** + * uC/OS-II + * The Real-Time Kernel + * File : os_cpu_c.c + * For : uC/OS Real-time multitasking kernel for the Nios2 SoftCore Processor + * Written by : IS + * Based on : Nios port done by JS + * + * Functions defined in this module: + * + ***********************************************************************************************/ + +#include +#include + +#include + +#define OS_CPU_GLOBALS +#include "includes.h" /* Standard includes for uC/OS-II */ + +#include "system.h" + +/* This used to be + * extern alt_u32 OSStartTsk; + * but that results in a fatal error when compiling -mgpopt=global + * because gcc assumes they are normal C variables in .sdata + * and therefore addressable from gp using a 16-bit offset, + * when in fact they are special values defined by linker.x + * and located nowhere near .sdata. + * Specifying __attribute__((section(".data"))) will force these + * in .data. (CASE:258384 or CASE:362640) + */ +extern alt_u32 OSStartTsk __attribute__((section(".data"))); /* The entry point for all tasks. */ + +#if OS_TMR_EN > 0 +static INT16U OSTmrCtr; +#endif + +#ifdef ALT_CPU_EIC_PRESENT +#error Nios II does not support uC/OS-II if EIC is enabled. +#endif + +/*********************************************************************************************** + * INITIALIZE A TASK'S STACK + * + * Description: This function is called by either OSTaskCreate() or OSTaskCreateExt() to + * initialize the stack frame of the task being created. This function is + * highly processor specific. + * + * What it does: It builds up initial stack for a task. + * + * Arguments : task is a pointer to the task code + * + * pdata is a pointer to a user supplied data area that will be passed to the task + * when the task first executes. + * + * ptos is a pointer to the top of stack. It is assumed that 'ptos' points to + * a 'free' entry on the task stack. If OS_STK_GROWTH is set to 1 then + * 'ptos' will contain the HIGHEST valid address of the stack. Similarly, if + * OS_STK_GROWTH is set to 0, the 'ptos' will contains the LOWEST valid address + * of the stack. + * + * opt specifies options that can be used to alter the behavior of OSTaskStkInit(). + * (see uCOS_II.H for OS_TASK_OPT_???). + * + * Returns : Always returns the location of the new top-of-stack' once the processor registers have + * been placed on the stack in the proper order. + * + ***********************************************************************************************/ + +OS_STK *OSTaskStkInit(void (*task)(void *pd), void *pdata, OS_STK *pstk, INT16U opt) +{ + INT32U *frame_pointer; + INT32U *stk; + +#if OS_THREAD_SAFE_NEWLIB + struct _reent* local_impure_ptr; + + /* + * create and initialise the impure pointer used for Newlib thread local storage. + * This is only done if the C library is being used in a thread safe mode. Otherwise + * a single reent structure is used for all threads, which saves memory. + */ + + local_impure_ptr = (struct _reent*)((((INT32U)(pstk)) & ~0x3) - sizeof(struct _reent)); + + _REENT_INIT_PTR (local_impure_ptr); + + /* + * create a stack frame at the top of the stack (leaving space for the + * reentrant data structure). + */ + + frame_pointer = (INT32U*) local_impure_ptr; +#else + frame_pointer = (INT32U*) (((INT32U)(pstk)) & ~0x3); +#endif /* OS_THREAD_SAFE_NEWLIB */ + stk = frame_pointer - 13; + + /* Now fill the stack frame. */ + + stk[12] = (INT32U)task; /* task address (ra) */ + stk[11] = (INT32U) pdata; /* first register argument (r4) */ + +#if OS_THREAD_SAFE_NEWLIB + stk[10] = (INT32U) local_impure_ptr; /* value of _impure_ptr for this thread */ +#endif /* OS_THREAD_SAFE_NEWLIB */ + stk[0] = ((INT32U)&OSStartTsk) + 4;/* exception return address (ea) */ + + /* The next three lines don't generate any code, they just put symbols into + * the debug information which will later be used to navigate the thread + * data structures + */ + __asm__ (".set OSTCBNext_OFFSET,%0" :: "i" (offsetof(OS_TCB, OSTCBNext))); + __asm__ (".set OSTCBPrio_OFFSET,%0" :: "i" (offsetof(OS_TCB, OSTCBPrio))); + __asm__ (".set OSTCBStkPtr_OFFSET,%0" :: "i" (offsetof(OS_TCB, OSTCBStkPtr))); + + return((OS_STK *)stk); +} + +#if OS_CPU_HOOKS_EN +/* +********************************************************************************************************* +* TASK CREATION HOOK +* +* Description: This function is called when a task is created. +* +* Arguments : ptcb is a pointer to the task control block of the task being created. +* +* Note(s) : 1) Interrupts are disabled during this call. +********************************************************************************************************* +*/ +void OSTaskCreateHook (OS_TCB *ptcb) +{ + ptcb = ptcb; /* Prevent compiler warning */ +} + + +/* +********************************************************************************************************* +* TASK DELETION HOOK +* +* Description: This function is called when a task is deleted. +* +* Arguments : ptcb is a pointer to the task control block of the task being deleted. +* +* Note(s) : 1) Interrupts are disabled during this call. +********************************************************************************************************* +*/ +void OSTaskDelHook (OS_TCB *ptcb) +{ + ptcb = ptcb; /* Prevent compiler warning */ +} + +/* +********************************************************************************************************* +* TASK SWITCH HOOK +* +* Description: This function is called when a task switch is performed. This allows you to perform other +* operations during a context switch. +* +* Arguments : none +* +* Note(s) : 1) Interrupts are disabled during this call. +* 2) It is assumed that the global pointer 'OSTCBHighRdy' points to the TCB of the task that +* will be 'switched in' (i.e. the highest priority task) and, 'OSTCBCur' points to the +* task being switched out (i.e. the preempted task). +********************************************************************************************************* +*/ +void OSTaskSwHook (void) +{ +} + +/* +********************************************************************************************************* +* STATISTIC TASK HOOK +* +* Description: This function is called every second by uC/OS-II's statistics task. This allows your +* application to add functionality to the statistics task. +* +* Arguments : none +********************************************************************************************************* +*/ +void OSTaskStatHook (void) +{ +} + +/* +********************************************************************************************************* +* TICK HOOK +* +* Description: This function is called every tick. +* +* Arguments : none +* +* Note(s) : 1) Interrupts may or may not be ENABLED during this call. +********************************************************************************************************* +*/ + +/* + * Iniche stack has no header declaration for its timer 'hook'. + * Do that here to avoid build warnings. + */ +#ifdef ALT_INICHE +void cticks_hook(void); +#endif + +void OSTimeTickHook (void) +{ +#if OS_TMR_EN > 0 + OSTmrCtr++; + if (OSTmrCtr >= (OS_TICKS_PER_SEC / OS_TMR_CFG_TICKS_PER_SEC)) { + OSTmrCtr = 0; + OSTmrSignal(); + } +#endif + +#ifdef ALT_INICHE + /* Service the Interniche timer */ + cticks_hook(); +#endif +} + +void OSInitHookBegin(void) +{ +#if OS_TMR_EN > 0 + OSTmrCtr = 0; +#endif +} + +void OSInitHookEnd(void) +{ +} + +void OSTaskIdleHook(void) +{ +} + +void OSTCBInitHook(OS_TCB *ptcb) +{ +} + +#endif diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/Micrium_45_Day_Evaluation_License.pdf b/FPGA_nios/hit_pat_bsp/UCOSII/Micrium_45_Day_Evaluation_License.pdf new file mode 100644 index 0000000..de49fda Binary files /dev/null and b/FPGA_nios/hit_pat_bsp/UCOSII/Micrium_45_Day_Evaluation_License.pdf differ diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/inc/os/alt_flag.h b/FPGA_nios/hit_pat_bsp/UCOSII/inc/os/alt_flag.h new file mode 100644 index 0000000..50758c1 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/UCOSII/inc/os/alt_flag.h @@ -0,0 +1,87 @@ +#ifndef __ALT_FLAG_H__ +#define __ALT_FLAG_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This header provides macro definitions that can be used to create and use + * uc/OS-II style event flags. These macros can be used in both a uC/OS-II based + * environment, and a single threaded HAL based environment. + * + * The motivation for these macros is to allow code to be developed which is + * thread safe under uC/OS-II, but incurs no additional overhead when used in a + * single threaded HAL environment. + * + * In the case of a single threaded HAL environment, they compile to + * "do nothing" directives, which ensures they do not contribute to the final + * executable. The definitions used in that case are provided with the HAL. + * + * The following macros are available: + * + * ALT_FLAG_GRP - Create a flag group instance. + * ALT_EXTERN_FLAG_GRP - Create a reference to an external flag group instance. + * ALT_STATIC_FLAG_GRP - Create a static flag group instance. + * ALT_FLAG_CREATE - Initialise a flag group. + * ALT_FLAG_PEND - Pend on a flag group. + * ALT_FLAG_POST - Set a flag condition. + + * + * Input arguments and return codes are all consistant with the equivalent + * uC/OS-II function. + * + * It's important to be careful in the use of the macros: ALT_FLAG_GRP, + * ALT_EXTERN_FLAG_GRP, and ALT_STATIC_FLAG_GRP. In these three cases the + * semi-colon is included in the macro definition; so, for example, you should + * use: + * + * ALT_FLAG_GRP(mygroup) + * + * not: + * + * ALT_FLAG_GRP(mygroup); + * + * The inclusion of the semi-colon has been necessary to ensure the macros can + * compile with no warnings when used in a single threaded HAL environment. + * + */ + +#include "priv/alt_flag_ucosii.h" + +#define ALT_FLAG_GRP(group) OS_FLAG_GRP* group; +#define ALT_EXTERN_FLAG_GRP(group) extern OS_FLAG_GRP* group; +#define ALT_STATIC_FLAG_GRP(group) OS_FLAG_GRP* group; + +#define ALT_FLAG_CREATE(pgroup, flags) alt_flag_create (pgroup, flags) +#define ALT_FLAG_PEND(group, flags, wait_type, timeout) \ + alt_flag_pend(group, flags, wait_type, timeout) +#define ALT_FLAG_POST(group, flags, opt) alt_flag_post (group, flags, opt) + +#endif /* __ALT_FLAG_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/inc/os/alt_hooks.h b/FPGA_nios/hit_pat_bsp/UCOSII/inc/os/alt_hooks.h new file mode 100644 index 0000000..9c647a2 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/UCOSII/inc/os/alt_hooks.h @@ -0,0 +1,69 @@ +#ifndef __ALT_HOOKS_H__ +#define __ALT_HOOKS_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This file is included by the Altera Vectored Interrpt Controller's + * interrpt funnel assembly code. Only those macros relevant to the funnel + * should be seen by the assembler. The funnel code defines the ALT_ASM_SRC + * macro. + */ +#ifndef ALT_ASM_SRC + +#include "includes.h" + +/* + * Semaphores used to protect the heap and environment + */ +extern OS_EVENT *alt_envsem; +extern OS_EVENT *alt_heapsem; + +/* + * This header provides definitions for the operating system hooks used by the + * HAL. + */ + +#define ALT_OS_TIME_TICK OSTimeTick +#define ALT_OS_INIT() OSInit(); \ + alt_envsem = OSSemCreate(1); \ + alt_heapsem = OSSemCreate(1) +#define ALT_OS_STOP() OSRunning = OS_FALSE +#define ALT_OS_INT_ENTER OSIntEnter +#define ALT_OS_INT_EXIT OSIntExit + +#endif /* ALT_ASM_SRC */ + +/* These macros are used by the VIC funnel assembly code */ +#define ALT_OS_INT_ENTER_ASM call OSIntEnter +#define ALT_OS_INT_EXIT_ASM call OSIntExit + +#endif /* __ALT_HOOKS_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/inc/os/alt_sem.h b/FPGA_nios/hit_pat_bsp/UCOSII/inc/os/alt_sem.h new file mode 100644 index 0000000..a554b8c --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/UCOSII/inc/os/alt_sem.h @@ -0,0 +1,85 @@ +#ifndef __ALT_SEM_H__ +#define __ALT_SEM_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This header provides macro definitions that can be used to create and use + * semaphores. These macros can be used in both a uC/OS-II based environment, + * and a single threaded HAL based environment. + * + * The motivation for these macros is to allow code to be developed which is + * thread safe under uC/OS-II, but incurs no additional overhead when used in a + * single threaded HAL environment. + * + * In the case of a single threaded HAL environment, they compile to + * "do nothing" directives, which ensures they do not contribute to the final + * executable. The macro definitions used in that case are supplied with the + * HAL. + * + * The following macros are available: + * + * ALT_SEM - Create a semaphore instance. + * ALT_EXTERN_SEM - Create a reference to an external semaphore instance. + * ALT_STATIC_SEM - Create a static semaphore instance. + * ALT_SEM_CREATE - Initialise a semaphore. + * ALT_SEM_PEND - Pend on a semaphore. + * ALT_SEM_POST - Increment a semaphore. + * + * Input arguments and return codes are all consistant with the equivalent + * uC/OS-II function. + * + * It's important to be careful in the use of the macros: ALT_SEM, + * ALT_EXTERN_SEM, and ALT_STATIC_SEM. In these three cases the semi-colon is + * included in the macro definition; so, for example, you should use: + * + * ALT_SEM(mysem) + * + * not: + * + * ALT_SEM(mysem); + * + * The inclusion of the semi-colon has been necessary to ensure the macros can + * compile with no warnings when used in a single threaded HAL environment. + * + */ + +#include "priv/alt_sem_ucosii.h" + +#define ALT_SEM(sem) OS_EVENT* sem; +#define ALT_EXTERN_SEM(sem) extern OS_EVENT* sem; +#define ALT_STATIC_SEM(sem) static OS_EVENT* sem; + +#define ALT_SEM_CREATE(sem, value) alt_sem_create (sem, value) +#define ALT_SEM_PEND(sem, timeout) alt_sem_pend (sem, timeout) +#define ALT_SEM_POST(sem) OSSemPost (sem) + +#endif /* __ALT_SEM_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/inc/os_cfg.h b/FPGA_nios/hit_pat_bsp/UCOSII/inc/os_cfg.h new file mode 100644 index 0000000..8feb1af --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/UCOSII/inc/os_cfg.h @@ -0,0 +1,65 @@ +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* uC/OS-II Configuration File for V2.8x +* +* (c) Copyright 2005-2007, Micrium, Weston, FL +* All Rights Reserved +* +* +* File : OS_CFG.H +* By : Jean J. Labrosse +* Version : V2.86 +* +* LICENSING TERMS: +* --------------- +* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. +* If you plan on using uC/OS-II in a commercial product you need to contact Micrim to properly license +* its use in your product. We provide ALL the source code for your convenience and to help you experience +* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a +* licensing fee. +********************************************************************************************************* +*/ + +#ifndef OS_CFG_H +#define OS_CFG_H + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +#ifndef __ASSEMBLER__ +#include "sys/alt_alarm.h" +#endif /* __ASSEMBLER__ */ + + +/* + * The following uC/OS configuration options have not been defined as + * configuration options in Nios II IDE or BSP tools; therefore they are + * defined here rather than in the generated system.h content. As long + * as they appear here, you may change their values in this file to change + * the setting + */ + /* ---------------------- MISCELLANEOUS ----------------------- */ +#define OS_APP_HOOKS_EN 1 /* Application-defined hooks are called from the uC/OS-II hooks */ +#define OS_EVENT_MULTI_EN 1 /* Include code for OSEventPendMulti() */ + + /* -------------------- MESSAGE MAILBOXES --------------------- */ +#define OS_MBOX_PEND_ABORT_EN 1 /* Include code for OSMboxPendAbort() */ + + /* ---------------------- MESSAGE QUEUES ---------------------- */ +#define OS_Q_PEND_ABORT_EN 1 /* Include code for OSQPendAbort() */ + + /* ------------------------ SEMAPHORES ------------------------ */ +#define OS_SEM_PEND_ABORT_EN 1 /* Include code for OSSemPendAbort() */ + + +#include "system.h" + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __OS_CFG_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/inc/priv/alt_flag_ucosii.h b/FPGA_nios/hit_pat_bsp/UCOSII/inc/priv/alt_flag_ucosii.h new file mode 100644 index 0000000..e65a73f --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/UCOSII/inc/priv/alt_flag_ucosii.h @@ -0,0 +1,109 @@ +#ifndef __ALT_FLAG_UCOSII_H__ +#define __ALT_FLAG_UCOSII_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This file provides the uC/OS-II specific functions used to implement the + * macros in alt_flag.h. These functions are simply wrappers for the uc/OS-II + * flags API. + * + * These functions are considered to be part of the internal implementation of + * the HAL, and should not be called directly by application code or device + * drivers. They are not guaranteed to be preserved in future versions of the + * HAL. + */ + +#include "includes.h" +#include "alt_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * alt_flag_create() is a wrapper for OSFlagCreate(), with the error code + * converted into the functions return value. + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_flag_create (OS_FLAG_GRP** pgroup, + OS_FLAGS flags) +{ + INT8U err; + *pgroup = OSFlagCreate (flags, &err); + return err; +} + +/* + * alt_flag_pend() is a wrapper for OSFlagPend(), with the error code + * converted into the functions return value. + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_flag_pend (OS_FLAG_GRP* group, + OS_FLAGS flags, + INT8U wait_type, + INT16U timeout) +{ + INT8U err; + if (OSRunning) + { + OSFlagPend (group, flags, wait_type, timeout, &err); + return err; + } + return OS_ERR_PEND_ISR; +} + + +/* + * alt_flag_post() is a wrapper for OSFlagPost(), with the error code + * converted into the functions return value. + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_flag_post (OS_FLAG_GRP* group, + OS_FLAGS flags, + INT8U opt) +{ + INT8U err; + + if (OSRunning) + { + OSFlagPost (group, flags, opt, &err); + return err; + } + return OS_ERR_PEND_ISR; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_FLAG_UCOSII_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/inc/priv/alt_sem_ucosii.h b/FPGA_nios/hit_pat_bsp/UCOSII/inc/priv/alt_sem_ucosii.h new file mode 100644 index 0000000..7c383bb --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/UCOSII/inc/priv/alt_sem_ucosii.h @@ -0,0 +1,82 @@ +#ifndef __ALT_SEM_UCOSII_H__ +#define __ALT_SEM_UCOSII_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This file provides the uC/OS-II specific functions used to implement the + * macros in alt_sem.h. These functions are simply wrappers for the uc/OS-II + * semaphore API. + * + * These functions are considered to be part of the internal implementation of + * the HAL, and should not be called directly by application code or device + * drivers. They are not guaranteed to be preserved in future versions of the + * HAL. + */ + +#include "includes.h" +#include "alt_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * alt_sem_create() is a wrapper for OSSemCreate(). The return value is 0 if + * the semaphore has been successfully created, or non-zero otherwise. + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sem_create (OS_EVENT** sem, + INT16U value) +{ + *sem = OSSemCreate (value); + return *sem ? 0 : -1; +} + +/* + * alt_sem_pend() is a wrapper for OSSemPend(), with the error code + * converted into the functions return value. + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sem_pend (OS_EVENT* sem, + INT16U timeout) +{ + INT8U err; + OSSemPend (sem, timeout, &err); + return err; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_SEM_UCOSII_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/inc/ucos_ii.h b/FPGA_nios/hit_pat_bsp/UCOSII/inc/ucos_ii.h new file mode 100644 index 0000000..62d1ca3 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/UCOSII/inc/ucos_ii.h @@ -0,0 +1,1930 @@ +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* +* (c) Copyright 1992-2007, Micrium, Weston, FL +* All Rights Reserved +* +* File : uCOS_II.H +* By : Jean J. Labrosse +* Version : V2.86 +* +* LICENSING TERMS: +* --------------- +* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. +* If you plan on using uC/OS-II in a commercial product you need to contact Micrim to properly license +* its use in your product. We provide ALL the source code for your convenience and to help you experience +* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a +* licensing fee. +********************************************************************************************************* +*/ + +#ifndef OS_uCOS_II_H +#define OS_uCOS_II_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* +********************************************************************************************************* +* uC/OS-II VERSION NUMBER +********************************************************************************************************* +*/ + +#define OS_VERSION 286u /* Version of uC/OS-II (Vx.yy mult. by 100) */ + +/* +********************************************************************************************************* +* INCLUDE HEADER FILES +********************************************************************************************************* +*/ + +// #include +#include +#include + +/* +********************************************************************************************************* +* MISCELLANEOUS +********************************************************************************************************* +*/ + +#ifdef OS_GLOBALS +#define OS_EXT +#else +#define OS_EXT extern +#endif + +#ifndef OS_FALSE +#define OS_FALSE 0u +#endif + +#ifndef OS_TRUE +#define OS_TRUE 1u +#endif + +#define OS_ASCII_NUL (INT8U)0 + +#define OS_PRIO_SELF 0xFFu /* Indicate SELF priority */ + +#if OS_TASK_STAT_EN > 0 +#define OS_N_SYS_TASKS 2u /* Number of system tasks */ +#else +#define OS_N_SYS_TASKS 1u +#endif + +#define OS_TASK_STAT_PRIO (OS_LOWEST_PRIO - 1) /* Statistic task priority */ +#define OS_TASK_IDLE_PRIO (OS_LOWEST_PRIO) /* IDLE task priority */ + +#if OS_LOWEST_PRIO <= 63 +#define OS_EVENT_TBL_SIZE ((OS_LOWEST_PRIO) / 8 + 1) /* Size of event table */ +#define OS_RDY_TBL_SIZE ((OS_LOWEST_PRIO) / 8 + 1) /* Size of ready table */ +#else +#define OS_EVENT_TBL_SIZE ((OS_LOWEST_PRIO) / 16 + 1) /* Size of event table */ +#define OS_RDY_TBL_SIZE ((OS_LOWEST_PRIO) / 16 + 1) /* Size of ready table */ +#endif + +#define OS_TASK_IDLE_ID 65535u /* ID numbers for Idle, Stat and Timer tasks */ +#define OS_TASK_STAT_ID 65534u +#define OS_TASK_TMR_ID 65533u + +#define OS_EVENT_EN (((OS_Q_EN > 0) && (OS_MAX_QS > 0)) || (OS_MBOX_EN > 0) || (OS_SEM_EN > 0) || (OS_MUTEX_EN > 0)) + +#define OS_TCB_RESERVED ((OS_TCB *)1) + +/*$PAGE*/ +/* +********************************************************************************************************* +* TASK STATUS (Bit definition for OSTCBStat) +********************************************************************************************************* +*/ +#define OS_STAT_RDY 0x00u /* Ready to run */ +#define OS_STAT_SEM 0x01u /* Pending on semaphore */ +#define OS_STAT_MBOX 0x02u /* Pending on mailbox */ +#define OS_STAT_Q 0x04u /* Pending on queue */ +#define OS_STAT_SUSPEND 0x08u /* Task is suspended */ +#define OS_STAT_MUTEX 0x10u /* Pending on mutual exclusion semaphore */ +#define OS_STAT_FLAG 0x20u /* Pending on event flag group */ +#define OS_STAT_MULTI 0x80u /* Pending on multiple events */ + +#define OS_STAT_PEND_ANY (OS_STAT_SEM | OS_STAT_MBOX | OS_STAT_Q | OS_STAT_MUTEX | OS_STAT_FLAG) + +/* +********************************************************************************************************* +* TASK PEND STATUS (Status codes for OSTCBStatPend) +********************************************************************************************************* +*/ +#define OS_STAT_PEND_OK 0u /* Pending status OK, not pending, or pending complete */ +#define OS_STAT_PEND_TO 1u /* Pending timed out */ +#define OS_STAT_PEND_ABORT 2u /* Pending aborted */ + +/* +********************************************************************************************************* +* OS_EVENT types +********************************************************************************************************* +*/ +#define OS_EVENT_TYPE_UNUSED 0u +#define OS_EVENT_TYPE_MBOX 1u +#define OS_EVENT_TYPE_Q 2u +#define OS_EVENT_TYPE_SEM 3u +#define OS_EVENT_TYPE_MUTEX 4u +#define OS_EVENT_TYPE_FLAG 5u + +#define OS_TMR_TYPE 100u /* Used to identify Timers ... */ + /* ... (Must be different value than OS_EVENT_TYPE_xxx) */ + +/* +********************************************************************************************************* +* EVENT FLAGS +********************************************************************************************************* +*/ +#define OS_FLAG_WAIT_CLR_ALL 0u /* Wait for ALL the bits specified to be CLR (i.e. 0) */ +#define OS_FLAG_WAIT_CLR_AND 0u + +#define OS_FLAG_WAIT_CLR_ANY 1u /* Wait for ANY of the bits specified to be CLR (i.e. 0) */ +#define OS_FLAG_WAIT_CLR_OR 1u + +#define OS_FLAG_WAIT_SET_ALL 2u /* Wait for ALL the bits specified to be SET (i.e. 1) */ +#define OS_FLAG_WAIT_SET_AND 2u + +#define OS_FLAG_WAIT_SET_ANY 3u /* Wait for ANY of the bits specified to be SET (i.e. 1) */ +#define OS_FLAG_WAIT_SET_OR 3u + + +#define OS_FLAG_CONSUME 0x80u /* Consume the flags if condition(s) satisfied */ + + +#define OS_FLAG_CLR 0u +#define OS_FLAG_SET 1u + +/* +********************************************************************************************************* +* Values for OSTickStepState +* +* Note(s): This feature is used by uC/OS-View. +********************************************************************************************************* +*/ + +#if OS_TICK_STEP_EN > 0 +#define OS_TICK_STEP_DIS 0u /* Stepping is disabled, tick runs as mormal */ +#define OS_TICK_STEP_WAIT 1u /* Waiting for uC/OS-View to set OSTickStepState to _ONCE */ +#define OS_TICK_STEP_ONCE 2u /* Process tick once and wait for next cmd from uC/OS-View */ +#endif + +/* +********************************************************************************************************* +* Possible values for 'opt' argument of OSSemDel(), OSMboxDel(), OSQDel() and OSMutexDel() +********************************************************************************************************* +*/ +#define OS_DEL_NO_PEND 0u +#define OS_DEL_ALWAYS 1u + +/* +********************************************************************************************************* +* OS???Pend() OPTIONS +* +* These #defines are used to establish the options for OS???PendAbort(). +********************************************************************************************************* +*/ +#define OS_PEND_OPT_NONE 0u /* NO option selected */ +#define OS_PEND_OPT_BROADCAST 1u /* Broadcast action to ALL tasks waiting */ + +/* +********************************************************************************************************* +* OS???PostOpt() OPTIONS +* +* These #defines are used to establish the options for OSMboxPostOpt() and OSQPostOpt(). +********************************************************************************************************* +*/ +#define OS_POST_OPT_NONE 0x00u /* NO option selected */ +#define OS_POST_OPT_BROADCAST 0x01u /* Broadcast message to ALL tasks waiting */ +#define OS_POST_OPT_FRONT 0x02u /* Post to highest priority task waiting */ +#define OS_POST_OPT_NO_SCHED 0x04u /* Do not call the scheduler if this option is selected */ + +/* +********************************************************************************************************* +* TASK OPTIONS (see OSTaskCreateExt()) +********************************************************************************************************* +*/ +#define OS_TASK_OPT_NONE 0x0000u /* NO option selected */ +#define OS_TASK_OPT_STK_CHK 0x0001u /* Enable stack checking for the task */ +#define OS_TASK_OPT_STK_CLR 0x0002u /* Clear the stack when the task is create */ +#define OS_TASK_OPT_SAVE_FP 0x0004u /* Save the contents of any floating-point registers */ + +/* +********************************************************************************************************* +* TIMER OPTIONS (see OSTmrStart() and OSTmrStop()) +********************************************************************************************************* +*/ +#define OS_TMR_OPT_NONE 0u /* No option selected */ + +#define OS_TMR_OPT_ONE_SHOT 1u /* Timer will not automatically restart when it expires */ +#define OS_TMR_OPT_PERIODIC 2u /* Timer will automatically restart when it expires */ + +#define OS_TMR_OPT_CALLBACK 3u /* OSTmrStop() option to call 'callback' w/ timer arg. */ +#define OS_TMR_OPT_CALLBACK_ARG 4u /* OSTmrStop() option to call 'callback' w/ new arg. */ + +/* +********************************************************************************************************* +* TIMER STATES +********************************************************************************************************* +*/ +#define OS_TMR_STATE_UNUSED 0u +#define OS_TMR_STATE_STOPPED 1u +#define OS_TMR_STATE_COMPLETED 2u +#define OS_TMR_STATE_RUNNING 3u + +/* +********************************************************************************************************* +* ERROR CODES +********************************************************************************************************* +*/ +#define OS_ERR_NONE 0u + +#define OS_ERR_EVENT_TYPE 1u +#define OS_ERR_PEND_ISR 2u +#define OS_ERR_POST_NULL_PTR 3u +#define OS_ERR_PEVENT_NULL 4u +#define OS_ERR_POST_ISR 5u +#define OS_ERR_QUERY_ISR 6u +#define OS_ERR_INVALID_OPT 7u +#define OS_ERR_PDATA_NULL 9u + +#define OS_ERR_TIMEOUT 10u +#define OS_ERR_EVENT_NAME_TOO_LONG 11u +#define OS_ERR_PNAME_NULL 12u +#define OS_ERR_PEND_LOCKED 13u +#define OS_ERR_PEND_ABORT 14u +#define OS_ERR_DEL_ISR 15u +#define OS_ERR_CREATE_ISR 16u +#define OS_ERR_NAME_GET_ISR 17u +#define OS_ERR_NAME_SET_ISR 18u + +#define OS_ERR_MBOX_FULL 20u + +#define OS_ERR_Q_FULL 30u +#define OS_ERR_Q_EMPTY 31u + +#define OS_ERR_PRIO_EXIST 40u +#define OS_ERR_PRIO 41u +#define OS_ERR_PRIO_INVALID 42u + +#define OS_ERR_SEM_OVF 50u + +#define OS_ERR_TASK_CREATE_ISR 60u +#define OS_ERR_TASK_DEL 61u +#define OS_ERR_TASK_DEL_IDLE 62u +#define OS_ERR_TASK_DEL_REQ 63u +#define OS_ERR_TASK_DEL_ISR 64u +#define OS_ERR_TASK_NAME_TOO_LONG 65u +#define OS_ERR_TASK_NO_MORE_TCB 66u +#define OS_ERR_TASK_NOT_EXIST 67u +#define OS_ERR_TASK_NOT_SUSPENDED 68u +#define OS_ERR_TASK_OPT 69u +#define OS_ERR_TASK_RESUME_PRIO 70u +#define OS_ERR_TASK_SUSPEND_IDLE 71u +#define OS_ERR_TASK_SUSPEND_PRIO 72u +#define OS_ERR_TASK_WAITING 73u + +#define OS_ERR_TIME_NOT_DLY 80u +#define OS_ERR_TIME_INVALID_MINUTES 81u +#define OS_ERR_TIME_INVALID_SECONDS 82u +#define OS_ERR_TIME_INVALID_MS 83u +#define OS_ERR_TIME_ZERO_DLY 84u +#define OS_ERR_TIME_DLY_ISR 85u + +#define OS_ERR_MEM_INVALID_PART 90u +#define OS_ERR_MEM_INVALID_BLKS 91u +#define OS_ERR_MEM_INVALID_SIZE 92u +#define OS_ERR_MEM_NO_FREE_BLKS 93u +#define OS_ERR_MEM_FULL 94u +#define OS_ERR_MEM_INVALID_PBLK 95u +#define OS_ERR_MEM_INVALID_PMEM 96u +#define OS_ERR_MEM_INVALID_PDATA 97u +#define OS_ERR_MEM_INVALID_ADDR 98u +#define OS_ERR_MEM_NAME_TOO_LONG 99u + +#define OS_ERR_NOT_MUTEX_OWNER 100u + +#define OS_ERR_FLAG_INVALID_PGRP 110u +#define OS_ERR_FLAG_WAIT_TYPE 111u +#define OS_ERR_FLAG_NOT_RDY 112u +#define OS_ERR_FLAG_INVALID_OPT 113u +#define OS_ERR_FLAG_GRP_DEPLETED 114u +#define OS_ERR_FLAG_NAME_TOO_LONG 115u + +#define OS_ERR_PIP_LOWER 120u + +#define OS_ERR_TMR_INVALID_DLY 130u +#define OS_ERR_TMR_INVALID_PERIOD 131u +#define OS_ERR_TMR_INVALID_OPT 132u +#define OS_ERR_TMR_INVALID_NAME 133u +#define OS_ERR_TMR_NON_AVAIL 134u +#define OS_ERR_TMR_INACTIVE 135u +#define OS_ERR_TMR_INVALID_DEST 136u +#define OS_ERR_TMR_INVALID_TYPE 137u +#define OS_ERR_TMR_INVALID 138u +#define OS_ERR_TMR_ISR 139u +#define OS_ERR_TMR_NAME_TOO_LONG 140u +#define OS_ERR_TMR_INVALID_STATE 141u +#define OS_ERR_TMR_STOPPED 142u +#define OS_ERR_TMR_NO_CALLBACK 143u + +/* +********************************************************************************************************* +* OLD ERROR CODE NAMES (< V2.84) +********************************************************************************************************* +*/ +#define OS_NO_ERR OS_ERR_NONE +#define OS_TIMEOUT OS_ERR_TIMEOUT +#define OS_TASK_NOT_EXIST OS_ERR_TASK_NOT_EXIST +#define OS_MBOX_FULL OS_ERR_MBOX_FULL +#define OS_Q_FULL OS_ERR_Q_FULL +#define OS_Q_EMPTY OS_ERR_Q_EMPTY +#define OS_PRIO_EXIST OS_ERR_PRIO_EXIST +#define OS_PRIO_ERR OS_ERR_PRIO +#define OS_PRIO_INVALID OS_ERR_PRIO_INVALID +#define OS_SEM_OVF OS_ERR_SEM_OVF +#define OS_TASK_DEL_ERR OS_ERR_TASK_DEL +#define OS_TASK_DEL_IDLE OS_ERR_TASK_DEL_IDLE +#define OS_TASK_DEL_REQ OS_ERR_TASK_DEL_REQ +#define OS_TASK_DEL_ISR OS_ERR_TASK_DEL_ISR +#define OS_NO_MORE_TCB OS_ERR_TASK_NO_MORE_TCB +#define OS_TIME_NOT_DLY OS_ERR_TIME_NOT_DLY +#define OS_TIME_INVALID_MINUTES OS_ERR_TIME_INVALID_MINUTES +#define OS_TIME_INVALID_SECONDS OS_ERR_TIME_INVALID_SECONDS +#define OS_TIME_INVALID_MS OS_ERR_TIME_INVALID_MS +#define OS_TIME_ZERO_DLY OS_ERR_TIME_ZERO_DLY +#define OS_TASK_SUSPEND_PRIO OS_ERR_TASK_SUSPEND_PRIO +#define OS_TASK_SUSPEND_IDLE OS_ERR_TASK_SUSPEND_IDLE +#define OS_TASK_RESUME_PRIO OS_ERR_TASK_RESUME_PRIO +#define OS_TASK_NOT_SUSPENDED OS_ERR_TASK_NOT_SUSPENDED +#define OS_MEM_INVALID_PART OS_ERR_MEM_INVALID_PART +#define OS_MEM_INVALID_BLKS OS_ERR_MEM_INVALID_BLKS +#define OS_MEM_INVALID_SIZE OS_ERR_MEM_INVALID_SIZE +#define OS_MEM_NO_FREE_BLKS OS_ERR_MEM_NO_FREE_BLKS +#define OS_MEM_FULL OS_ERR_MEM_FULL +#define OS_MEM_INVALID_PBLK OS_ERR_MEM_INVALID_PBLK +#define OS_MEM_INVALID_PMEM OS_ERR_MEM_INVALID_PMEM +#define OS_MEM_INVALID_PDATA OS_ERR_MEM_INVALID_PDATA +#define OS_MEM_INVALID_ADDR OS_ERR_MEM_INVALID_ADDR +#define OS_MEM_NAME_TOO_LONG OS_ERR_MEM_NAME_TOO_LONG +#define OS_TASK_OPT_ERR OS_ERR_TASK_OPT +#define OS_FLAG_INVALID_PGRP OS_ERR_FLAG_INVALID_PGRP +#define OS_FLAG_ERR_WAIT_TYPE OS_ERR_FLAG_WAIT_TYPE +#define OS_FLAG_ERR_NOT_RDY OS_ERR_FLAG_NOT_RDY +#define OS_FLAG_INVALID_OPT OS_ERR_FLAG_INVALID_OPT +#define OS_FLAG_GRP_DEPLETED OS_ERR_FLAG_GRP_DEPLETED + +/*$PAGE*/ +/* +********************************************************************************************************* +* EVENT CONTROL BLOCK +********************************************************************************************************* +*/ + +#if (OS_EVENT_EN) && (OS_MAX_EVENTS > 0) +typedef struct os_event { + INT8U OSEventType; /* Type of event control block (see OS_EVENT_TYPE_xxxx) */ + void *OSEventPtr; /* Pointer to message or queue structure */ + INT16U OSEventCnt; /* Semaphore Count (not used if other EVENT type) */ +#if OS_LOWEST_PRIO <= 63 + INT8U OSEventGrp; /* Group corresponding to tasks waiting for event to occur */ + INT8U OSEventTbl[OS_EVENT_TBL_SIZE]; /* List of tasks waiting for event to occur */ +#else + INT16U OSEventGrp; /* Group corresponding to tasks waiting for event to occur */ + INT16U OSEventTbl[OS_EVENT_TBL_SIZE]; /* List of tasks waiting for event to occur */ +#endif + +#if OS_EVENT_NAME_SIZE > 1 + INT8U OSEventName[OS_EVENT_NAME_SIZE]; +#endif +} OS_EVENT; +#endif + + +/* +********************************************************************************************************* +* EVENT FLAGS CONTROL BLOCK +********************************************************************************************************* +*/ + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) + +#if OS_FLAGS_NBITS == 8 /* Determine the size of OS_FLAGS (8, 16 or 32 bits) */ +typedef INT8U OS_FLAGS; +#endif + +#if OS_FLAGS_NBITS == 16 +typedef INT16U OS_FLAGS; +#endif + +#if OS_FLAGS_NBITS == 32 +typedef INT32U OS_FLAGS; +#endif + + +typedef struct os_flag_grp { /* Event Flag Group */ + INT8U OSFlagType; /* Should be set to OS_EVENT_TYPE_FLAG */ + void *OSFlagWaitList; /* Pointer to first NODE of task waiting on event flag */ + OS_FLAGS OSFlagFlags; /* 8, 16 or 32 bit flags */ +#if OS_FLAG_NAME_SIZE > 1 + INT8U OSFlagName[OS_FLAG_NAME_SIZE]; +#endif +} OS_FLAG_GRP; + + + +typedef struct os_flag_node { /* Event Flag Wait List Node */ + void *OSFlagNodeNext; /* Pointer to next NODE in wait list */ + void *OSFlagNodePrev; /* Pointer to previous NODE in wait list */ + void *OSFlagNodeTCB; /* Pointer to TCB of waiting task */ + void *OSFlagNodeFlagGrp; /* Pointer to Event Flag Group */ + OS_FLAGS OSFlagNodeFlags; /* Event flag to wait on */ + INT8U OSFlagNodeWaitType; /* Type of wait: */ + /* OS_FLAG_WAIT_AND */ + /* OS_FLAG_WAIT_ALL */ + /* OS_FLAG_WAIT_OR */ + /* OS_FLAG_WAIT_ANY */ +} OS_FLAG_NODE; +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* MESSAGE MAILBOX DATA +********************************************************************************************************* +*/ + +#if OS_MBOX_EN > 0 +typedef struct os_mbox_data { + void *OSMsg; /* Pointer to message in mailbox */ +#if OS_LOWEST_PRIO <= 63 + INT8U OSEventTbl[OS_EVENT_TBL_SIZE]; /* List of tasks waiting for event to occur */ + INT8U OSEventGrp; /* Group corresponding to tasks waiting for event to occur */ +#else + INT16U OSEventTbl[OS_EVENT_TBL_SIZE]; /* List of tasks waiting for event to occur */ + INT16U OSEventGrp; /* Group corresponding to tasks waiting for event to occur */ +#endif +} OS_MBOX_DATA; +#endif + +/* +********************************************************************************************************* +* MEMORY PARTITION DATA STRUCTURES +********************************************************************************************************* +*/ + +#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0) +typedef struct os_mem { /* MEMORY CONTROL BLOCK */ + void *OSMemAddr; /* Pointer to beginning of memory partition */ + void *OSMemFreeList; /* Pointer to list of free memory blocks */ + INT32U OSMemBlkSize; /* Size (in bytes) of each block of memory */ + INT32U OSMemNBlks; /* Total number of blocks in this partition */ + INT32U OSMemNFree; /* Number of memory blocks remaining in this partition */ +#if OS_MEM_NAME_SIZE > 1 + INT8U OSMemName[OS_MEM_NAME_SIZE]; /* Memory partition name */ +#endif +} OS_MEM; + + +typedef struct os_mem_data { + void *OSAddr; /* Pointer to the beginning address of the memory partition */ + void *OSFreeList; /* Pointer to the beginning of the free list of memory blocks */ + INT32U OSBlkSize; /* Size (in bytes) of each memory block */ + INT32U OSNBlks; /* Total number of blocks in the partition */ + INT32U OSNFree; /* Number of memory blocks free */ + INT32U OSNUsed; /* Number of memory blocks used */ +} OS_MEM_DATA; +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* MUTUAL EXCLUSION SEMAPHORE DATA +********************************************************************************************************* +*/ + +#if OS_MUTEX_EN > 0 +typedef struct os_mutex_data { +#if OS_LOWEST_PRIO <= 63 + INT8U OSEventTbl[OS_EVENT_TBL_SIZE]; /* List of tasks waiting for event to occur */ + INT8U OSEventGrp; /* Group corresponding to tasks waiting for event to occur */ +#else + INT16U OSEventTbl[OS_EVENT_TBL_SIZE]; /* List of tasks waiting for event to occur */ + INT16U OSEventGrp; /* Group corresponding to tasks waiting for event to occur */ +#endif + BOOLEAN OSValue; /* Mutex value (OS_FALSE = used, OS_TRUE = available) */ + INT8U OSOwnerPrio; /* Mutex owner's task priority or 0xFF if no owner */ + INT8U OSMutexPIP; /* Priority Inheritance Priority or 0xFF if no owner */ +} OS_MUTEX_DATA; +#endif + +/* +********************************************************************************************************* +* MESSAGE QUEUE DATA +********************************************************************************************************* +*/ + +#if OS_Q_EN > 0 +typedef struct os_q { /* QUEUE CONTROL BLOCK */ + struct os_q *OSQPtr; /* Link to next queue control block in list of free blocks */ + void **OSQStart; /* Pointer to start of queue data */ + void **OSQEnd; /* Pointer to end of queue data */ + void **OSQIn; /* Pointer to where next message will be inserted in the Q */ + void **OSQOut; /* Pointer to where next message will be extracted from the Q */ + INT16U OSQSize; /* Size of queue (maximum number of entries) */ + INT16U OSQEntries; /* Current number of entries in the queue */ +} OS_Q; + + +typedef struct os_q_data { + void *OSMsg; /* Pointer to next message to be extracted from queue */ + INT16U OSNMsgs; /* Number of messages in message queue */ + INT16U OSQSize; /* Size of message queue */ +#if OS_LOWEST_PRIO <= 63 + INT8U OSEventTbl[OS_EVENT_TBL_SIZE]; /* List of tasks waiting for event to occur */ + INT8U OSEventGrp; /* Group corresponding to tasks waiting for event to occur */ +#else + INT16U OSEventTbl[OS_EVENT_TBL_SIZE]; /* List of tasks waiting for event to occur */ + INT16U OSEventGrp; /* Group corresponding to tasks waiting for event to occur */ +#endif +} OS_Q_DATA; +#endif + +/* +********************************************************************************************************* +* SEMAPHORE DATA +********************************************************************************************************* +*/ + +#if OS_SEM_EN > 0 +typedef struct os_sem_data { + INT16U OSCnt; /* Semaphore count */ +#if OS_LOWEST_PRIO <= 63 + INT8U OSEventTbl[OS_EVENT_TBL_SIZE]; /* List of tasks waiting for event to occur */ + INT8U OSEventGrp; /* Group corresponding to tasks waiting for event to occur */ +#else + INT16U OSEventTbl[OS_EVENT_TBL_SIZE]; /* List of tasks waiting for event to occur */ + INT16U OSEventGrp; /* Group corresponding to tasks waiting for event to occur */ +#endif +} OS_SEM_DATA; +#endif + +/* +********************************************************************************************************* +* TASK STACK DATA +********************************************************************************************************* +*/ + +#if OS_TASK_CREATE_EXT_EN > 0 +typedef struct os_stk_data { + INT32U OSFree; /* Number of free bytes on the stack */ + INT32U OSUsed; /* Number of bytes used on the stack */ +} OS_STK_DATA; +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* TASK CONTROL BLOCK +********************************************************************************************************* +*/ + +typedef struct os_tcb { + OS_STK *OSTCBStkPtr; /* Pointer to current top of stack */ + +#if OS_TASK_CREATE_EXT_EN > 0 + void *OSTCBExtPtr; /* Pointer to user definable data for TCB extension */ + OS_STK *OSTCBStkBottom; /* Pointer to bottom of stack */ + INT32U OSTCBStkSize; /* Size of task stack (in number of stack elements) */ + INT16U OSTCBOpt; /* Task options as passed by OSTaskCreateExt() */ + INT16U OSTCBId; /* Task ID (0..65535) */ +#endif + + struct os_tcb *OSTCBNext; /* Pointer to next TCB in the TCB list */ + struct os_tcb *OSTCBPrev; /* Pointer to previous TCB in the TCB list */ + +#if (OS_EVENT_EN) || (OS_FLAG_EN > 0) + OS_EVENT *OSTCBEventPtr; /* Pointer to event control block */ +#endif + +#if (OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0) + OS_EVENT **OSTCBEventMultiPtr; /* Pointer to multiple event control blocks */ +#endif + +#if ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) || (OS_MBOX_EN > 0) + void *OSTCBMsg; /* Message received from OSMboxPost() or OSQPost() */ +#endif + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) +#if OS_TASK_DEL_EN > 0 + OS_FLAG_NODE *OSTCBFlagNode; /* Pointer to event flag node */ +#endif + OS_FLAGS OSTCBFlagsRdy; /* Event flags that made task ready to run */ +#endif + + INT16U OSTCBDly; /* Nbr ticks to delay task or, timeout waiting for event */ + INT8U OSTCBStat; /* Task status */ + INT8U OSTCBStatPend; /* Task PEND status */ + INT8U OSTCBPrio; /* Task priority (0 == highest) */ + + INT8U OSTCBX; /* Bit position in group corresponding to task priority */ + INT8U OSTCBY; /* Index into ready table corresponding to task priority */ +#if OS_LOWEST_PRIO <= 63 + INT8U OSTCBBitX; /* Bit mask to access bit position in ready table */ + INT8U OSTCBBitY; /* Bit mask to access bit position in ready group */ +#else + INT16U OSTCBBitX; /* Bit mask to access bit position in ready table */ + INT16U OSTCBBitY; /* Bit mask to access bit position in ready group */ +#endif + +#if OS_TASK_DEL_EN > 0 + INT8U OSTCBDelReq; /* Indicates whether a task needs to delete itself */ +#endif + +#if OS_TASK_PROFILE_EN > 0 + INT32U OSTCBCtxSwCtr; /* Number of time the task was switched in */ + INT32U OSTCBCyclesTot; /* Total number of clock cycles the task has been running */ + INT32U OSTCBCyclesStart; /* Snapshot of cycle counter at start of task resumption */ + OS_STK *OSTCBStkBase; /* Pointer to the beginning of the task stack */ + INT32U OSTCBStkUsed; /* Number of bytes used from the stack */ +#endif + +#if OS_TASK_NAME_SIZE > 1 + INT8U OSTCBTaskName[OS_TASK_NAME_SIZE]; +#endif +} OS_TCB; + +/*$PAGE*/ +/* +************************************************************************************************************************ +* TIMER DATA TYPES +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +typedef void (*OS_TMR_CALLBACK)(void *ptmr, void *parg); + + + +typedef struct os_tmr { + INT8U OSTmrType; /* Should be set to OS_TMR_TYPE */ + OS_TMR_CALLBACK OSTmrCallback; /* Function to call when timer expires */ + void *OSTmrCallbackArg; /* Argument to pass to function when timer expires */ + void *OSTmrNext; /* Double link list pointers */ + void *OSTmrPrev; + INT32U OSTmrMatch; /* Timer expires when OSTmrTime == OSTmrMatch */ + INT32U OSTmrDly; /* Delay time before periodic update starts */ + INT32U OSTmrPeriod; /* Period to repeat timer */ +#if OS_TMR_CFG_NAME_SIZE > 0 + INT8U OSTmrName[OS_TMR_CFG_NAME_SIZE]; /* Name to give the timer */ +#endif + INT8U OSTmrOpt; /* Options (see OS_TMR_OPT_xxx) */ + INT8U OSTmrState; /* Indicates the state of the timer: */ + /* OS_TMR_STATE_UNUSED */ + /* OS_TMR_STATE_RUNNING */ + /* OS_TMR_STATE_STOPPED */ +} OS_TMR; + + + +typedef struct os_tmr_wheel { + OS_TMR *OSTmrFirst; /* Pointer to first timer in linked list */ + INT16U OSTmrEntries; +} OS_TMR_WHEEL; +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* GLOBAL VARIABLES +********************************************************************************************************* +*/ + +OS_EXT INT32U OSCtxSwCtr; /* Counter of number of context switches */ + +#if (OS_EVENT_EN) && (OS_MAX_EVENTS > 0) +OS_EXT OS_EVENT *OSEventFreeList; /* Pointer to list of free EVENT control blocks */ +OS_EXT OS_EVENT OSEventTbl[OS_MAX_EVENTS];/* Table of EVENT control blocks */ +#endif + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) +OS_EXT OS_FLAG_GRP OSFlagTbl[OS_MAX_FLAGS]; /* Table containing event flag groups */ +OS_EXT OS_FLAG_GRP *OSFlagFreeList; /* Pointer to free list of event flag groups */ +#endif + +#if OS_TASK_STAT_EN > 0 +OS_EXT INT8U OSCPUUsage; /* Percentage of CPU used */ +OS_EXT INT32U OSIdleCtrMax; /* Max. value that idle ctr can take in 1 sec. */ +OS_EXT INT32U OSIdleCtrRun; /* Val. reached by idle ctr at run time in 1 sec. */ +OS_EXT BOOLEAN OSStatRdy; /* Flag indicating that the statistic task is rdy */ +OS_EXT OS_STK OSTaskStatStk[OS_TASK_STAT_STK_SIZE]; /* Statistics task stack */ +#endif + +OS_EXT INT8U OSIntNesting; /* Interrupt nesting level */ + +OS_EXT INT8U OSLockNesting; /* Multitasking lock nesting level */ + +OS_EXT INT8U OSPrioCur; /* Priority of current task */ +OS_EXT INT8U OSPrioHighRdy; /* Priority of highest priority task */ + +#if OS_LOWEST_PRIO <= 63 +OS_EXT INT8U OSRdyGrp; /* Ready list group */ +OS_EXT INT8U OSRdyTbl[OS_RDY_TBL_SIZE]; /* Table of tasks which are ready to run */ +#else +OS_EXT INT16U OSRdyGrp; /* Ready list group */ +OS_EXT INT16U OSRdyTbl[OS_RDY_TBL_SIZE]; /* Table of tasks which are ready to run */ +#endif + +OS_EXT BOOLEAN OSRunning; /* Flag indicating that kernel is running */ + +OS_EXT INT8U OSTaskCtr; /* Number of tasks created */ + +OS_EXT volatile INT32U OSIdleCtr; /* Idle counter */ + +OS_EXT OS_STK OSTaskIdleStk[OS_TASK_IDLE_STK_SIZE]; /* Idle task stack */ + + +OS_EXT OS_TCB *OSTCBCur; /* Pointer to currently running TCB */ +OS_EXT OS_TCB *OSTCBFreeList; /* Pointer to list of free TCBs */ +OS_EXT OS_TCB *OSTCBHighRdy; /* Pointer to highest priority TCB R-to-R */ +OS_EXT OS_TCB *OSTCBList; /* Pointer to doubly linked list of TCBs */ +OS_EXT OS_TCB *OSTCBPrioTbl[OS_LOWEST_PRIO + 1];/* Table of pointers to created TCBs */ +OS_EXT OS_TCB OSTCBTbl[OS_MAX_TASKS + OS_N_SYS_TASKS]; /* Table of TCBs */ + +#if OS_TICK_STEP_EN > 0 +OS_EXT INT8U OSTickStepState; /* Indicates the state of the tick step feature */ +#endif + +#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0) +OS_EXT OS_MEM *OSMemFreeList; /* Pointer to free list of memory partitions */ +OS_EXT OS_MEM OSMemTbl[OS_MAX_MEM_PART];/* Storage for memory partition manager */ +#endif + +#if (OS_Q_EN > 0) && (OS_MAX_QS > 0) +OS_EXT OS_Q *OSQFreeList; /* Pointer to list of free QUEUE control blocks */ +OS_EXT OS_Q OSQTbl[OS_MAX_QS]; /* Table of QUEUE control blocks */ +#endif + +#if OS_TIME_GET_SET_EN > 0 +OS_EXT volatile INT32U OSTime; /* Current value of system time (in ticks) */ +#endif + +#if OS_TMR_EN > 0 +OS_EXT INT16U OSTmrFree; /* Number of free entries in the timer pool */ +OS_EXT INT16U OSTmrUsed; /* Number of timers used */ +OS_EXT INT32U OSTmrTime; /* Current timer time */ + +OS_EXT OS_EVENT *OSTmrSem; /* Sem. used to gain exclusive access to timers */ +OS_EXT OS_EVENT *OSTmrSemSignal; /* Sem. used to signal the update of timers */ + +OS_EXT OS_TMR OSTmrTbl[OS_TMR_CFG_MAX]; /* Table containing pool of timers */ +OS_EXT OS_TMR *OSTmrFreeList; /* Pointer to free list of timers */ +OS_EXT OS_STK OSTmrTaskStk[OS_TASK_TMR_STK_SIZE]; + +OS_EXT OS_TMR_WHEEL OSTmrWheelTbl[OS_TMR_CFG_WHEEL_SIZE]; +#endif + +extern INT8U const OSUnMapTbl[256]; /* Priority->Index lookup table */ + +/*$PAGE*/ +/* +********************************************************************************************************* +* FUNCTION PROTOTYPES +* (Target Independent Functions) +********************************************************************************************************* +*/ + +/* +********************************************************************************************************* +* MISCELLANEOUS +********************************************************************************************************* +*/ + +#if (OS_EVENT_EN) + +#if (OS_EVENT_NAME_SIZE > 1) +INT8U OSEventNameGet (OS_EVENT *pevent, + INT8U *pname, + INT8U *perr); + +void OSEventNameSet (OS_EVENT *pevent, + INT8U *pname, + INT8U *perr); +#endif + +#if (OS_EVENT_MULTI_EN > 0) +INT16U OSEventPendMulti (OS_EVENT **pevents_pend, + OS_EVENT **pevents_rdy, + void **pmsgs_rdy, + INT16U timeout, + INT8U *perr); +#endif + +#endif + +/* +********************************************************************************************************* +* EVENT FLAGS MANAGEMENT +********************************************************************************************************* +*/ + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) + +#if OS_FLAG_ACCEPT_EN > 0 +OS_FLAGS OSFlagAccept (OS_FLAG_GRP *pgrp, + OS_FLAGS flags, + INT8U wait_type, + INT8U *perr); +#endif + +OS_FLAG_GRP *OSFlagCreate (OS_FLAGS flags, + INT8U *perr); + +#if OS_FLAG_DEL_EN > 0 +OS_FLAG_GRP *OSFlagDel (OS_FLAG_GRP *pgrp, + INT8U opt, + INT8U *perr); +#endif + +#if (OS_FLAG_EN > 0) && (OS_FLAG_NAME_SIZE > 1) +INT8U OSFlagNameGet (OS_FLAG_GRP *pgrp, + INT8U *pname, + INT8U *perr); + +void OSFlagNameSet (OS_FLAG_GRP *pgrp, + INT8U *pname, + INT8U *perr); +#endif + +OS_FLAGS OSFlagPend (OS_FLAG_GRP *pgrp, + OS_FLAGS flags, + INT8U wait_type, + INT16U timeout, + INT8U *perr); + +OS_FLAGS OSFlagPendGetFlagsRdy (void); +OS_FLAGS OSFlagPost (OS_FLAG_GRP *pgrp, + OS_FLAGS flags, + INT8U opt, + INT8U *perr); + +#if OS_FLAG_QUERY_EN > 0 +OS_FLAGS OSFlagQuery (OS_FLAG_GRP *pgrp, + INT8U *perr); +#endif +#endif + +/* +********************************************************************************************************* +* MESSAGE MAILBOX MANAGEMENT +********************************************************************************************************* +*/ + +#if OS_MBOX_EN > 0 + +#if OS_MBOX_ACCEPT_EN > 0 +void *OSMboxAccept (OS_EVENT *pevent); +#endif + +OS_EVENT *OSMboxCreate (void *pmsg); + +#if OS_MBOX_DEL_EN > 0 +OS_EVENT *OSMboxDel (OS_EVENT *pevent, + INT8U opt, + INT8U *perr); +#endif + +void *OSMboxPend (OS_EVENT *pevent, + INT16U timeout, + INT8U *perr); + +#if OS_MBOX_PEND_ABORT_EN > 0 +INT8U OSMboxPendAbort (OS_EVENT *pevent, + INT8U opt, + INT8U *perr); +#endif + +#if OS_MBOX_POST_EN > 0 +INT8U OSMboxPost (OS_EVENT *pevent, + void *pmsg); +#endif + +#if OS_MBOX_POST_OPT_EN > 0 +INT8U OSMboxPostOpt (OS_EVENT *pevent, + void *pmsg, + INT8U opt); +#endif + +#if OS_MBOX_QUERY_EN > 0 +INT8U OSMboxQuery (OS_EVENT *pevent, + OS_MBOX_DATA *p_mbox_data); +#endif +#endif + +/* +********************************************************************************************************* +* MEMORY MANAGEMENT +********************************************************************************************************* +*/ + +#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0) + +OS_MEM *OSMemCreate (void *addr, + INT32U nblks, + INT32U blksize, + INT8U *perr); + +void *OSMemGet (OS_MEM *pmem, + INT8U *perr); +#if OS_MEM_NAME_SIZE > 1 +INT8U OSMemNameGet (OS_MEM *pmem, + INT8U *pname, + INT8U *perr); + +void OSMemNameSet (OS_MEM *pmem, + INT8U *pname, + INT8U *perr); +#endif +INT8U OSMemPut (OS_MEM *pmem, + void *pblk); + +#if OS_MEM_QUERY_EN > 0 +INT8U OSMemQuery (OS_MEM *pmem, + OS_MEM_DATA *p_mem_data); +#endif + +#endif + +/* +********************************************************************************************************* +* MUTUAL EXCLUSION SEMAPHORE MANAGEMENT +********************************************************************************************************* +*/ + +#if OS_MUTEX_EN > 0 + +#if OS_MUTEX_ACCEPT_EN > 0 +BOOLEAN OSMutexAccept (OS_EVENT *pevent, + INT8U *perr); +#endif + +OS_EVENT *OSMutexCreate (INT8U prio, + INT8U *perr); + +#if OS_MUTEX_DEL_EN > 0 +OS_EVENT *OSMutexDel (OS_EVENT *pevent, + INT8U opt, + INT8U *perr); +#endif + +void OSMutexPend (OS_EVENT *pevent, + INT16U timeout, + INT8U *perr); + +INT8U OSMutexPost (OS_EVENT *pevent); + +#if OS_MUTEX_QUERY_EN > 0 +INT8U OSMutexQuery (OS_EVENT *pevent, + OS_MUTEX_DATA *p_mutex_data); +#endif + +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* MESSAGE QUEUE MANAGEMENT +********************************************************************************************************* +*/ + +#if (OS_Q_EN > 0) && (OS_MAX_QS > 0) + +#if OS_Q_ACCEPT_EN > 0 +void *OSQAccept (OS_EVENT *pevent, + INT8U *perr); +#endif + +OS_EVENT *OSQCreate (void **start, + INT16U size); + +#if OS_Q_DEL_EN > 0 +OS_EVENT *OSQDel (OS_EVENT *pevent, + INT8U opt, + INT8U *perr); +#endif + +#if OS_Q_FLUSH_EN > 0 +INT8U OSQFlush (OS_EVENT *pevent); +#endif + +void *OSQPend (OS_EVENT *pevent, + INT16U timeout, + INT8U *perr); + +#if OS_Q_PEND_ABORT_EN > 0 +INT8U OSQPendAbort (OS_EVENT *pevent, + INT8U opt, + INT8U *perr); +#endif + +#if OS_Q_POST_EN > 0 +INT8U OSQPost (OS_EVENT *pevent, + void *pmsg); +#endif + +#if OS_Q_POST_FRONT_EN > 0 +INT8U OSQPostFront (OS_EVENT *pevent, + void *pmsg); +#endif + +#if OS_Q_POST_OPT_EN > 0 +INT8U OSQPostOpt (OS_EVENT *pevent, + void *pmsg, + INT8U opt); +#endif + +#if OS_Q_QUERY_EN > 0 +INT8U OSQQuery (OS_EVENT *pevent, + OS_Q_DATA *p_q_data); +#endif + +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* SEMAPHORE MANAGEMENT +********************************************************************************************************* +*/ +#if OS_SEM_EN > 0 + +#if OS_SEM_ACCEPT_EN > 0 +INT16U OSSemAccept (OS_EVENT *pevent); +#endif + +OS_EVENT *OSSemCreate (INT16U cnt); + +#if OS_SEM_DEL_EN > 0 +OS_EVENT *OSSemDel (OS_EVENT *pevent, + INT8U opt, + INT8U *perr); +#endif + +void OSSemPend (OS_EVENT *pevent, + INT16U timeout, + INT8U *perr); + +#if OS_SEM_PEND_ABORT_EN > 0 +INT8U OSSemPendAbort (OS_EVENT *pevent, + INT8U opt, + INT8U *perr); +#endif + +INT8U OSSemPost (OS_EVENT *pevent); + +#if OS_SEM_QUERY_EN > 0 +INT8U OSSemQuery (OS_EVENT *pevent, + OS_SEM_DATA *p_sem_data); +#endif + +#if OS_SEM_SET_EN > 0 +void OSSemSet (OS_EVENT *pevent, + INT16U cnt, + INT8U *perr); +#endif + +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* TASK MANAGEMENT +********************************************************************************************************* +*/ +#if OS_TASK_CHANGE_PRIO_EN > 0 +INT8U OSTaskChangePrio (INT8U oldprio, + INT8U newprio); +#endif + +#if OS_TASK_CREATE_EN > 0 +INT8U OSTaskCreate (void (*task)(void *p_arg), + void *p_arg, + OS_STK *ptos, + INT8U prio); +#endif + +#if OS_TASK_CREATE_EXT_EN > 0 +INT8U OSTaskCreateExt (void (*task)(void *p_arg), + void *p_arg, + OS_STK *ptos, + INT8U prio, + INT16U id, + OS_STK *pbos, + INT32U stk_size, + void *pext, + INT16U opt); +#endif + +#if OS_TASK_DEL_EN > 0 +INT8U OSTaskDel (INT8U prio); +INT8U OSTaskDelReq (INT8U prio); +#endif + +#if OS_TASK_NAME_SIZE > 1 +INT8U OSTaskNameGet (INT8U prio, + INT8U *pname, + INT8U *perr); + +void OSTaskNameSet (INT8U prio, + INT8U *pname, + INT8U *perr); +#endif + +#if OS_TASK_SUSPEND_EN > 0 +INT8U OSTaskResume (INT8U prio); +INT8U OSTaskSuspend (INT8U prio); +#endif + +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) +INT8U OSTaskStkChk (INT8U prio, + OS_STK_DATA *p_stk_data); +#endif + +#if OS_TASK_QUERY_EN > 0 +INT8U OSTaskQuery (INT8U prio, + OS_TCB *p_task_data); +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* TIME MANAGEMENT +********************************************************************************************************* +*/ + +void OSTimeDly (INT16U ticks); + +#if OS_TIME_DLY_HMSM_EN > 0 +INT8U OSTimeDlyHMSM (INT8U hours, + INT8U minutes, + INT8U seconds, + INT16U milli); +#endif + +#if OS_TIME_DLY_RESUME_EN > 0 +INT8U OSTimeDlyResume (INT8U prio); +#endif + +#if OS_TIME_GET_SET_EN > 0 +INT32U OSTimeGet (void); +void OSTimeSet (INT32U ticks); +#endif + +void OSTimeTick (void); + +/* +********************************************************************************************************* +* TIMER MANAGEMENT +********************************************************************************************************* +*/ + +#if OS_TMR_EN > 0 +OS_TMR *OSTmrCreate (INT32U dly, + INT32U period, + INT8U opt, + OS_TMR_CALLBACK callback, + void *callback_arg, + INT8U *pname, + INT8U *perr); + +BOOLEAN OSTmrDel (OS_TMR *ptmr, + INT8U *perr); + +#if OS_TMR_CFG_NAME_SIZE > 0 +INT8U OSTmrNameGet (OS_TMR *ptmr, + INT8U *pdest, + INT8U *perr); +#endif +INT32U OSTmrRemainGet (OS_TMR *ptmr, + INT8U *perr); + +INT8U OSTmrStateGet (OS_TMR *ptmr, + INT8U *perr); + +BOOLEAN OSTmrStart (OS_TMR *ptmr, + INT8U *perr); + +BOOLEAN OSTmrStop (OS_TMR *ptmr, + INT8U opt, + void *callback_arg, + INT8U *perr); + +INT8U OSTmrSignal (void); +#endif + +/* +********************************************************************************************************* +* MISCELLANEOUS +********************************************************************************************************* +*/ + +void OSInit (void); + +void OSIntEnter (void); +void OSIntExit (void); + +#if OS_SCHED_LOCK_EN > 0 +void OSSchedLock (void); +void OSSchedUnlock (void); +#endif + +void OSStart (void); + +void OSStatInit (void); + +INT16U OSVersion (void); + +/*$PAGE*/ +/* +********************************************************************************************************* +* INTERNAL FUNCTION PROTOTYPES +* (Your application MUST NOT call these functions) +********************************************************************************************************* +*/ + +#if OS_TASK_DEL_EN > 0 +void OS_Dummy (void); +#endif + +#if (OS_EVENT_EN) +INT8U OS_EventTaskRdy (OS_EVENT *pevent, + void *pmsg, + INT8U msk, + INT8U pend_stat); + +void OS_EventTaskWait (OS_EVENT *pevent); + +void OS_EventTaskRemove (OS_TCB *ptcb, + OS_EVENT *pevent); + +#if (OS_EVENT_MULTI_EN > 0) +void OS_EventTaskWaitMulti (OS_EVENT **pevents_wait); + +void OS_EventTaskRemoveMulti (OS_TCB *ptcb, + OS_EVENT **pevents_multi); +#endif + +void OS_EventWaitListInit (OS_EVENT *pevent); +#endif + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) +void OS_FlagInit (void); +void OS_FlagUnlink (OS_FLAG_NODE *pnode); +#endif + +void OS_MemClr (INT8U *pdest, + INT16U size); + +void OS_MemCopy (INT8U *pdest, + INT8U *psrc, + INT16U size); + +#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0) +void OS_MemInit (void); +#endif + +#if OS_Q_EN > 0 +void OS_QInit (void); +#endif + +void OS_Sched (void); + +#if (OS_EVENT_NAME_SIZE > 1) || (OS_FLAG_NAME_SIZE > 1) || (OS_MEM_NAME_SIZE > 1) || (OS_TASK_NAME_SIZE > 1) +INT8U OS_StrCopy (INT8U *pdest, + INT8U *psrc); + +INT8U OS_StrLen (INT8U *psrc); +#endif + +void OS_TaskIdle (void *p_arg); + +#if OS_TASK_STAT_EN > 0 +void OS_TaskStat (void *p_arg); +#endif + +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) +void OS_TaskStkClr (OS_STK *pbos, + INT32U size, + INT16U opt); +#endif + +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) +void OS_TaskStatStkChk (void); +#endif + +INT8U OS_TCBInit (INT8U prio, + OS_STK *ptos, + OS_STK *pbos, + INT16U id, + INT32U stk_size, + void *pext, + INT16U opt); + +#if OS_TMR_EN > 0 +void OSTmr_Init (void); +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* FUNCTION PROTOTYPES +* (Target Specific Functions) +********************************************************************************************************* +*/ + +#if OS_DEBUG_EN > 0 +void OSDebugInit (void); +#endif + +void OSInitHookBegin (void); +void OSInitHookEnd (void); + +void OSTaskCreateHook (OS_TCB *ptcb); +void OSTaskDelHook (OS_TCB *ptcb); + +void OSTaskIdleHook (void); + +void OSTaskStatHook (void); +OS_STK *OSTaskStkInit (void (*task)(void *p_arg), + void *p_arg, + OS_STK *ptos, + INT16U opt); + +#if OS_TASK_SW_HOOK_EN > 0 +void OSTaskSwHook (void); +#endif + +void OSTCBInitHook (OS_TCB *ptcb); + +#if OS_TIME_TICK_HOOK_EN > 0 +void OSTimeTickHook (void); +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* FUNCTION PROTOTYPES +* (Application Specific Functions) +********************************************************************************************************* +*/ + +#if OS_APP_HOOKS_EN > 0 +void App_TaskCreateHook (OS_TCB *ptcb); +void App_TaskDelHook (OS_TCB *ptcb); +void App_TaskIdleHook (void); + +void App_TaskStatHook (void); + +#if OS_TASK_SW_HOOK_EN > 0 +void App_TaskSwHook (void); +#endif + +void App_TCBInitHook (OS_TCB *ptcb); + +#if OS_TIME_TICK_HOOK_EN > 0 +void App_TimeTickHook (void); +#endif +#endif + +/* +********************************************************************************************************* +* FUNCTION PROTOTYPES +* +* IMPORTANT: These prototypes MUST be placed in OS_CPU.H +********************************************************************************************************* +*/ + +#if 0 +void OSStartHighRdy (void); +void OSIntCtxSw (void); +void OSCtxSw (void); +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* LOOK FOR MISSING #define CONSTANTS +* +* This section is used to generate ERROR messages at compile time if certain #define constants are +* MISSING in OS_CFG.H. This allows you to quickly determine the source of the error. +* +* You SHOULD NOT change this section UNLESS you would like to add more comments as to the source of the +* compile time error. +********************************************************************************************************* +*/ + +/* +********************************************************************************************************* +* EVENT FLAGS +********************************************************************************************************* +*/ + +#ifndef OS_FLAG_EN +#error "OS_CFG.H, Missing OS_FLAG_EN: Enable (1) or Disable (0) code generation for Event Flags" +#else + #ifndef OS_MAX_FLAGS + #error "OS_CFG.H, Missing OS_MAX_FLAGS: Max. number of Event Flag Groups in your application" + #else + #if OS_MAX_FLAGS > 65500u + #error "OS_CFG.H, OS_MAX_FLAGS must be <= 65500" + #endif + #endif + + #ifndef OS_FLAGS_NBITS + #error "OS_CFG.H, Missing OS_FLAGS_NBITS: Determine #bits used for event flags, MUST be either 8, 16 or 32" + #endif + + #ifndef OS_FLAG_WAIT_CLR_EN + #error "OS_CFG.H, Missing OS_FLAG_WAIT_CLR_EN: Include code for Wait on Clear EVENT FLAGS" + #endif + + #ifndef OS_FLAG_ACCEPT_EN + #error "OS_CFG.H, Missing OS_FLAG_ACCEPT_EN: Include code for OSFlagAccept()" + #endif + + #ifndef OS_FLAG_DEL_EN + #error "OS_CFG.H, Missing OS_FLAG_DEL_EN: Include code for OSFlagDel()" + #endif + + #ifndef OS_FLAG_NAME_SIZE + #error "OS_CFG.H, Missing OS_FLAG_NAME_SIZE: Determines the size of flag group names" + #endif + + #ifndef OS_FLAG_QUERY_EN + #error "OS_CFG.H, Missing OS_FLAG_QUERY_EN: Include code for OSFlagQuery()" + #endif +#endif + +/* +********************************************************************************************************* +* MESSAGE MAILBOXES +********************************************************************************************************* +*/ + +#ifndef OS_MBOX_EN +#error "OS_CFG.H, Missing OS_MBOX_EN: Enable (1) or Disable (0) code generation for MAILBOXES" +#else + #ifndef OS_MBOX_ACCEPT_EN + #error "OS_CFG.H, Missing OS_MBOX_ACCEPT_EN: Include code for OSMboxAccept()" + #endif + + #ifndef OS_MBOX_DEL_EN + #error "OS_CFG.H, Missing OS_MBOX_DEL_EN: Include code for OSMboxDel()" + #endif + + #ifndef OS_MBOX_PEND_ABORT_EN + #error "OS_CFG.H, Missing OS_MBOX_PEND_ABORT_EN: Include code for OSMboxPendAbort()" + #endif + + #ifndef OS_MBOX_POST_EN + #error "OS_CFG.H, Missing OS_MBOX_POST_EN: Include code for OSMboxPost()" + #endif + + #ifndef OS_MBOX_POST_OPT_EN + #error "OS_CFG.H, Missing OS_MBOX_POST_OPT_EN: Include code for OSMboxPostOpt()" + #endif + + #ifndef OS_MBOX_QUERY_EN + #error "OS_CFG.H, Missing OS_MBOX_QUERY_EN: Include code for OSMboxQuery()" + #endif +#endif + +/* +********************************************************************************************************* +* MEMORY MANAGEMENT +********************************************************************************************************* +*/ + +#ifndef OS_MEM_EN +#error "OS_CFG.H, Missing OS_MEM_EN: Enable (1) or Disable (0) code generation for MEMORY MANAGER" +#else + #ifndef OS_MAX_MEM_PART + #error "OS_CFG.H, Missing OS_MAX_MEM_PART: Max. number of memory partitions" + #else + #if OS_MAX_MEM_PART > 65500u + #error "OS_CFG.H, OS_MAX_MEM_PART must be <= 65500" + #endif + #endif + + #ifndef OS_MEM_NAME_SIZE + #error "OS_CFG.H, Missing OS_MEM_NAME_SIZE: Determines the size of memory partition names" + #endif + + #ifndef OS_MEM_QUERY_EN + #error "OS_CFG.H, Missing OS_MEM_QUERY_EN: Include code for OSMemQuery()" + #endif +#endif + +/* +********************************************************************************************************* +* MUTUAL EXCLUSION SEMAPHORES +********************************************************************************************************* +*/ + +#ifndef OS_MUTEX_EN +#error "OS_CFG.H, Missing OS_MUTEX_EN: Enable (1) or Disable (0) code generation for MUTEX" +#else + #ifndef OS_MUTEX_ACCEPT_EN + #error "OS_CFG.H, Missing OS_MUTEX_ACCEPT_EN: Include code for OSMutexAccept()" + #endif + + #ifndef OS_MUTEX_DEL_EN + #error "OS_CFG.H, Missing OS_MUTEX_DEL_EN: Include code for OSMutexDel()" + #endif + + #ifndef OS_MUTEX_QUERY_EN + #error "OS_CFG.H, Missing OS_MUTEX_QUERY_EN: Include code for OSMutexQuery()" + #endif +#endif + +/* +********************************************************************************************************* +* MESSAGE QUEUES +********************************************************************************************************* +*/ + +#ifndef OS_Q_EN +#error "OS_CFG.H, Missing OS_Q_EN: Enable (1) or Disable (0) code generation for QUEUES" +#else + #ifndef OS_MAX_QS + #error "OS_CFG.H, Missing OS_MAX_QS: Max. number of queue control blocks" + #else + #if OS_MAX_QS > 65500u + #error "OS_CFG.H, OS_MAX_QS must be <= 65500" + #endif + #endif + + #ifndef OS_Q_ACCEPT_EN + #error "OS_CFG.H, Missing OS_Q_ACCEPT_EN: Include code for OSQAccept()" + #endif + + #ifndef OS_Q_DEL_EN + #error "OS_CFG.H, Missing OS_Q_DEL_EN: Include code for OSQDel()" + #endif + + #ifndef OS_Q_FLUSH_EN + #error "OS_CFG.H, Missing OS_Q_FLUSH_EN: Include code for OSQFlush()" + #endif + + #ifndef OS_Q_PEND_ABORT_EN + #error "OS_CFG.H, Missing OS_Q_PEND_ABORT_EN: Include code for OSQPendAbort()" + #endif + + #ifndef OS_Q_POST_EN + #error "OS_CFG.H, Missing OS_Q_POST_EN: Include code for OSQPost()" + #endif + + #ifndef OS_Q_POST_FRONT_EN + #error "OS_CFG.H, Missing OS_Q_POST_FRONT_EN: Include code for OSQPostFront()" + #endif + + #ifndef OS_Q_POST_OPT_EN + #error "OS_CFG.H, Missing OS_Q_POST_OPT_EN: Include code for OSQPostOpt()" + #endif + + #ifndef OS_Q_QUERY_EN + #error "OS_CFG.H, Missing OS_Q_QUERY_EN: Include code for OSQQuery()" + #endif +#endif + +/* +********************************************************************************************************* +* SEMAPHORES +********************************************************************************************************* +*/ + +#ifndef OS_SEM_EN +#error "OS_CFG.H, Missing OS_SEM_EN: Enable (1) or Disable (0) code generation for SEMAPHORES" +#else + #ifndef OS_SEM_ACCEPT_EN + #error "OS_CFG.H, Missing OS_SEM_ACCEPT_EN: Include code for OSSemAccept()" + #endif + + #ifndef OS_SEM_DEL_EN + #error "OS_CFG.H, Missing OS_SEM_DEL_EN: Include code for OSSemDel()" + #endif + + #ifndef OS_SEM_PEND_ABORT_EN + #error "OS_CFG.H, Missing OS_SEM_PEND_ABORT_EN: Include code for OSSemPendAbort()" + #endif + + #ifndef OS_SEM_QUERY_EN + #error "OS_CFG.H, Missing OS_SEM_QUERY_EN: Include code for OSSemQuery()" + #endif + + #ifndef OS_SEM_SET_EN + #error "OS_CFG.H, Missing OS_SEM_SET_EN: Include code for OSSemSet()" + #endif +#endif + +/* +********************************************************************************************************* +* TASK MANAGEMENT +********************************************************************************************************* +*/ + +#ifndef OS_MAX_TASKS +#error "OS_CFG.H, Missing OS_MAX_TASKS: Max. number of tasks in your application" +#else + #if OS_MAX_TASKS < 2 + #error "OS_CFG.H, OS_MAX_TASKS must be >= 2" + #endif + + #if OS_MAX_TASKS > ((OS_LOWEST_PRIO - OS_N_SYS_TASKS) + 1) + #error "OS_CFG.H, OS_MAX_TASKS must be <= OS_LOWEST_PRIO - OS_N_SYS_TASKS + 1" + #endif + +#endif + +#if OS_LOWEST_PRIO > 254 +#error "OS_CFG.H, OS_LOWEST_PRIO must be <= 254 in V2.8x and higher" +#endif + +#ifndef OS_TASK_IDLE_STK_SIZE +#error "OS_CFG.H, Missing OS_TASK_IDLE_STK_SIZE: Idle task stack size" +#endif + +#ifndef OS_TASK_STAT_EN +#error "OS_CFG.H, Missing OS_TASK_STAT_EN: Enable (1) or Disable(0) the statistics task" +#endif + +#ifndef OS_TASK_STAT_STK_SIZE +#error "OS_CFG.H, Missing OS_TASK_STAT_STK_SIZE: Statistics task stack size" +#endif + +#ifndef OS_TASK_STAT_STK_CHK_EN +#error "OS_CFG.H, Missing OS_TASK_STAT_STK_CHK_EN: Check task stacks from statistics task" +#endif + +#ifndef OS_TASK_CHANGE_PRIO_EN +#error "OS_CFG.H, Missing OS_TASK_CHANGE_PRIO_EN: Include code for OSTaskChangePrio()" +#endif + +#ifndef OS_TASK_CREATE_EN +#error "OS_CFG.H, Missing OS_TASK_CREATE_EN: Include code for OSTaskCreate()" +#endif + +#ifndef OS_TASK_CREATE_EXT_EN +#error "OS_CFG.H, Missing OS_TASK_CREATE_EXT_EN: Include code for OSTaskCreateExt()" +#endif + +#ifndef OS_TASK_DEL_EN +#error "OS_CFG.H, Missing OS_TASK_DEL_EN: Include code for OSTaskDel()" +#endif + +#ifndef OS_TASK_NAME_SIZE +#error "OS_CFG.H, Missing OS_TASK_NAME_SIZE: Determine the size of task names" +#endif + +#ifndef OS_TASK_SUSPEND_EN +#error "OS_CFG.H, Missing OS_TASK_SUSPEND_EN: Include code for OSTaskSuspend() and OSTaskResume()" +#endif + +#ifndef OS_TASK_QUERY_EN +#error "OS_CFG.H, Missing OS_TASK_QUERY_EN: Include code for OSTaskQuery()" +#endif + +/* +********************************************************************************************************* +* TIME MANAGEMENT +********************************************************************************************************* +*/ + +#ifndef OS_TICKS_PER_SEC +#error "OS_CFG.H, Missing OS_TICKS_PER_SEC: Sets the number of ticks in one second" +#endif + +#ifndef OS_TIME_DLY_HMSM_EN +#error "OS_CFG.H, Missing OS_TIME_DLY_HMSM_EN: Include code for OSTimeDlyHMSM()" +#endif + +#ifndef OS_TIME_DLY_RESUME_EN +#error "OS_CFG.H, Missing OS_TIME_DLY_RESUME_EN: Include code for OSTimeDlyResume()" +#endif + +#ifndef OS_TIME_GET_SET_EN +#error "OS_CFG.H, Missing OS_TIME_GET_SET_EN: Include code for OSTimeGet() and OSTimeSet()" +#endif + +/* +********************************************************************************************************* +* TIMER MANAGEMENT +********************************************************************************************************* +*/ + +#ifndef OS_TMR_EN +#error "OS_CFG.H, Missing OS_TMR_EN: When (1) enables code generation for Timer Management" +#elif OS_TMR_EN > 0 + #if OS_SEM_EN == 0 + #error "OS_CFG.H, Semaphore management is required (set OS_SEM_EN to 1) when enabling Timer Management." + #error " Timer management require TWO semaphores." + #endif + + #ifndef OS_TMR_CFG_MAX + #error "OS_CFG.H, Missing OS_TMR_CFG_MAX: Determines the total number of timers in an application (2 .. 65500)" + #else + #if OS_TMR_CFG_MAX < 2 + #error "OS_CFG.H, OS_TMR_CFG_MAX should be between 2 and 65500" + #endif + + #if OS_TMR_CFG_MAX > 65500 + #error "OS_CFG.H, OS_TMR_CFG_MAX should be between 2 and 65500" + #endif + #endif + + #ifndef OS_TMR_CFG_WHEEL_SIZE + #error "OS_CFG.H, Missing OS_TMR_CFG_WHEEL_SIZE: Sets the size of the timer wheel (1 .. 1023)" + #else + #if OS_TMR_CFG_WHEEL_SIZE < 2 + #error "OS_CFG.H, OS_TMR_CFG_WHEEL_SIZE should be between 2 and 1024" + #endif + + #if OS_TMR_CFG_WHEEL_SIZE > 1024 + #error "OS_CFG.H, OS_TMR_CFG_WHEEL_SIZE should be between 2 and 1024" + #endif + #endif + + #ifndef OS_TMR_CFG_NAME_SIZE + #error "OS_CFG.H, Missing OS_TMR_CFG_NAME_SIZE: Determines the number of characters used for Timer names" + #endif + + #ifndef OS_TMR_CFG_TICKS_PER_SEC + #error "OS_CFG.H, Missing OS_TMR_CFG_TICKS_PER_SEC: Determines the rate at which tiem timer management task will run (Hz)" + #endif + + #ifndef OS_TASK_TMR_STK_SIZE + #error "OS_CFG.H, Missing OS_TASK_TMR_STK_SIZE: Determines the size of the Timer Task's stack" + #endif +#endif + + +/* +********************************************************************************************************* +* MISCELLANEOUS +********************************************************************************************************* +*/ + +#ifndef OS_ARG_CHK_EN +#error "OS_CFG.H, Missing OS_ARG_CHK_EN: Enable (1) or Disable (0) argument checking" +#endif + + +#ifndef OS_CPU_HOOKS_EN +#error "OS_CFG.H, Missing OS_CPU_HOOKS_EN: uC/OS-II hooks are found in the processor port files when 1" +#endif + + +#ifndef OS_APP_HOOKS_EN +#error "OS_CFG.H, Missing OS_APP_HOOKS_EN: Application-defined hooks are called from the uC/OS-II hooks" +#endif + + +#ifndef OS_DEBUG_EN +#error "OS_CFG.H, Missing OS_DEBUG_EN: Allows you to include variables for debugging or not" +#endif + + +#ifndef OS_LOWEST_PRIO +#error "OS_CFG.H, Missing OS_LOWEST_PRIO: Defines the lowest priority that can be assigned" +#endif + + +#ifndef OS_MAX_EVENTS +#error "OS_CFG.H, Missing OS_MAX_EVENTS: Max. number of event control blocks in your application" +#else + #if OS_MAX_EVENTS > 65500u + #error "OS_CFG.H, OS_MAX_EVENTS must be <= 65500" + #endif +#endif + + +#ifndef OS_SCHED_LOCK_EN +#error "OS_CFG.H, Missing OS_SCHED_LOCK_EN: Include code for OSSchedLock() and OSSchedUnlock()" +#endif + + +#ifndef OS_EVENT_MULTI_EN +#error "OS_CFG.H, Missing OS_EVENT_MULTI_EN: Include code for OSEventPendMulti()" +#endif + + +#ifndef OS_TASK_PROFILE_EN +#error "OS_CFG.H, Missing OS_TASK_PROFILE_EN: Include data structure for run-time task profiling" +#endif + + +#ifndef OS_TASK_SW_HOOK_EN +#error "OS_CFG.H, Missing OS_TASK_SW_HOOK_EN: Allows you to include the code for OSTaskSwHook() or not" +#endif + + +#ifndef OS_TICK_STEP_EN +#error "OS_CFG.H, Missing OS_TICK_STEP_EN: Allows to 'step' one tick at a time with uC/OS-View" +#endif + + +#ifndef OS_TIME_TICK_HOOK_EN +#error "OS_CFG.H, Missing OS_TIME_TICK_HOOK_EN: Allows you to include the code for OSTimeTickHook() or not" +#endif + +/* +********************************************************************************************************* +* SAFETY CRITICAL USE +********************************************************************************************************* +*/ + +#ifdef SAFETY_CRITICAL_RELEASE + +#if OS_ARG_CHK_EN < 1 +#error "OS_CFG.H, OS_ARG_CHK_EN must be enabled for safety-critical release code" +#endif + +#if OS_APP_HOOKS_EN > 0 +#error "OS_CFG.H, OS_APP_HOOKS_EN must be disabled for safety-critical release code" +#endif + +#if OS_DEBUG_EN > 0 +#error "OS_CFG.H, OS_DEBUG_EN must be disabled for safety-critical release code" +#endif + +#ifdef CANTATA +#error "OS_CFG.H, CANTATA must be disabled for safety-critical release code" +#endif + +#ifdef OS_SCHED_LOCK_EN +#error "OS_CFG.H, OS_SCHED_LOCK_EN must be disabled for safety-critical release code" +#endif + +#ifdef VSC_VALIDATION_MODE +#error "OS_CFG.H, VSC_VALIDATION_MODE must be disabled for safety-critical release code" +#endif + +#if OS_TASK_STAT_EN > 0 +#error "OS_CFG.H, OS_TASK_STAT_EN must be disabled for safety-critical release code" +#endif + +#if OS_TICK_STEP_EN > 0 +#error "OS_CFG.H, OS_TICK_STEP_EN must be disabled for safety-critical release code" +#endif + +#if OS_FLAG_EN > 0 + #if OS_FLAG_DEL_EN > 0 + #error "OS_CFG.H, OS_FLAG_DEL_EN must be disabled for safety-critical release code" + #endif +#endif + +#if OS_MBOX_EN > 0 + #if OS_MBOX_DEL_EN > 0 + #error "OS_CFG.H, OS_MBOX_DEL_EN must be disabled for safety-critical release code" + #endif +#endif + +#if OS_MUTEX_EN > 0 + #if OS_MUTEX_DEL_EN > 0 + #error "OS_CFG.H, OS_MUTEX_DEL_EN must be disabled for safety-critical release code" + #endif +#endif + +#if OS_Q_EN > 0 + #if OS_Q_DEL_EN > 0 + #error "OS_CFG.H, OS_Q_DEL_EN must be disabled for safety-critical release code" + #endif +#endif + +#if OS_SEM_EN > 0 + #if OS_SEM_DEL_EN > 0 + #error "OS_CFG.H, OS_SEM_DEL_EN must be disabled for safety-critical release code" + #endif +#endif + +#if OS_TASK_EN > 0 + #if OS_TASK_DEL_EN > 0 + #error "OS_CFG.H, OS_TASK_DEL_EN must be disabled for safety-critical release code" + #endif +#endif + +#if OS_CRITICAL_METHOD != 3 +#error "OS_CPU.H, OS_CRITICAL_METHOD must be type 3 for safety-critical release code" +#endif + +#endif /* ------------------------ SAFETY_CRITICAL_RELEASE ------------------------ */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/license-ucosii.txt b/FPGA_nios/hit_pat_bsp/UCOSII/license-ucosii.txt new file mode 100644 index 0000000..3872d99 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/UCOSII/license-ucosii.txt @@ -0,0 +1,20 @@ +MicroC/OS-II Licensing Terms +============================ + +Micrium's uC/OS-II is a real-time operating system (RTOS) available in source code. +This is not open-source software. + +This RTOS can be used free of charge for non-commercial purposes and academic projects only, +any other use of the code is subject to the terms of an end-user license agreement +for more information please see the license file included in the BSP project or contact Micrium. + +Anyone planning to use a Micrium RTOS in a commercial product must purchase a commercial license +from the owner of the software, Silicon Laboratories Inc. + +Licensing information is available at: + +Phone: +1 954-217-2036 +Email: sales@micrium.com +URL: www.micrium.com + +Do not use this code if you do not agree to these conditions. diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/alt_env_lock.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/alt_env_lock.c new file mode 100644 index 0000000..03ed46d --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/alt_env_lock.c @@ -0,0 +1,122 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * These are the env lock/unlock stubs required by newlib. These are + * used to make accesses to environment variables thread safe. Note that + * this implementation requires that environment variables are never manipulated + * by an interrupt service routine. + */ + + +#include + +#include "includes.h" +#include "system.h" + +/* semaphore to protect the environment */ + +OS_EVENT *alt_envsem; + +#if OS_THREAD_SAFE_NEWLIB +/* id of the task that is currently manipulating the environment */ + +static int lockid = -1; + +/* number of times __env_lock has recursed */ + +static int locks; +#endif /* OS_THREAD_SAFE_NEWLIB */ + +/* + * + */ + +void __env_lock ( struct _reent *_r ) +{ +#if OS_THREAD_SAFE_NEWLIB + OS_TCB tcb; + OS_SEM_DATA semdata; + INT8U err; + int id; + + /* use our priority as a task id */ + + err = OSTaskQuery( OS_PRIO_SELF, &tcb ); + if (err != OS_NO_ERR) + return; + + id = tcb.OSTCBPrio; + + /* see if we own the environment already */ + + OSSemQuery( alt_envsem, &semdata ); + if( semdata.OSEventGrp && id == lockid ) + { + /* we do; just count the recursion */ + + locks++; + } + else + { + /* wait on the other task to yield, then claim ownership */ + + OSSemPend( alt_envsem, 0, &err ); + locks = 1; + lockid = id; + } + +#endif /* OS_THREAD_SAFE_NEWLIB */ + return; +} + +/* + * + */ + +void __env_unlock ( struct _reent *_r ) +{ +#if OS_THREAD_SAFE_NEWLIB + if (locks == 0) + return; + + /* + * release the environment once the number of locks == the number + * of unlocks + */ + + if( (--locks) == 0 ) + { + lockid = -1; + OSSemPost( alt_envsem ); + } +#endif /* OS_THREAD_SAFE_NEWLIB */ +} + diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/alt_malloc_lock.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/alt_malloc_lock.c new file mode 100644 index 0000000..0f050ca --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/alt_malloc_lock.c @@ -0,0 +1,147 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "system.h" + +/* + * These are the malloc lock/unlock stubs required by newlib. These are + * used to make accesses to the heap thread safe. Note that + * this implementation requires that the heap is never manipulated + * by an interrupt service routine. + */ + +#include + +#include "includes.h" + +/* semaphore to protect the heap */ + +OS_EVENT *alt_heapsem; + + +#if OS_THREAD_SAFE_NEWLIB +/* id of the task that is currently manipulating the heap */ + +static int lockid = -1; + +/* number of times __malloc_lock has recursed */ + +static int locks; +#endif /* OS_THREAD_SAFE_NEWLIB */ + +/* + * + */ + +void __malloc_lock ( struct _reent *_r ) +{ +#if OS_THREAD_SAFE_NEWLIB + OS_TCB tcb; + OS_SEM_DATA semdata; + INT8U err; + int id; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + if (OSRunning != OS_TRUE) + return; + + /* use our priority as a task id */ + + err = OSTaskQuery( OS_PRIO_SELF, &tcb ); + if (err != OS_NO_ERR) + return; + + id = tcb.OSTCBPrio; + + /* see if we own the heap already */ + + OSSemQuery( alt_heapsem, &semdata ); + + OS_ENTER_CRITICAL(); + + if( !semdata.OSCnt && id == lockid ) + { + /* we do; just count the recursion */ + locks++; + OS_EXIT_CRITICAL(); + } + else + { + /* wait on the other task to yield the heap, then claim ownership of it */ + OS_EXIT_CRITICAL(); + + OSSemPend( alt_heapsem, 0, &err ); + locks = 1; + lockid = id; + } + +#endif /* OS_THREAD_SAFE_NEWLIB */ + return; +} + +/* + * + */ + +void __malloc_unlock ( struct _reent *_r ) +{ +#if OS_THREAD_SAFE_NEWLIB + +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + if (OSRunning != OS_TRUE) + return; + + OS_ENTER_CRITICAL(); + if (locks == 0) + { + OS_EXIT_CRITICAL(); + return; + } + + /* release the heap once the number of locks == the number of unlocks */ + if( (--locks) == 0 ) + { + lockid = -1; + OS_EXIT_CRITICAL(); + OSSemPost( alt_heapsem ); + } + else + { + OS_EXIT_CRITICAL(); + } + +#endif /* OS_THREAD_SAFE_NEWLIB */ +} + diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/os_core.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_core.c new file mode 100644 index 0000000..8c88045 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_core.c @@ -0,0 +1,2018 @@ +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* CORE FUNCTIONS +* +* (c) Copyright 1992-2007, Micrium, Weston, FL +* All Rights Reserved +* +* File : OS_CORE.C +* By : Jean J. Labrosse +* Version : V2.86 +* +* LICENSING TERMS: +* --------------- +* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. +* If you plan on using uC/OS-II in a commercial product you need to contact Micri�m to properly license +* its use in your product. We provide ALL the source code for your convenience and to help you experience +* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a +* licensing fee. +********************************************************************************************************* +*/ + +#ifndef OS_MASTER_FILE +#define OS_GLOBALS +#include +#endif + +/* +********************************************************************************************************* +* PRIORITY RESOLUTION TABLE +* +* Note: Index into table is bit pattern to resolve highest priority +* Indexed value corresponds to highest priority bit position (i.e. 0..7) +********************************************************************************************************* +*/ + +INT8U const OSUnMapTbl[256] = { + 0, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0x00 to 0x0F */ + 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0x10 to 0x1F */ + 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0x20 to 0x2F */ + 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0x30 to 0x3F */ + 6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0x40 to 0x4F */ + 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0x50 to 0x5F */ + 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0x60 to 0x6F */ + 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0x70 to 0x7F */ + 7, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0x80 to 0x8F */ + 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0x90 to 0x9F */ + 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0xA0 to 0xAF */ + 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0xB0 to 0xBF */ + 6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0xC0 to 0xCF */ + 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0xD0 to 0xDF */ + 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0xE0 to 0xEF */ + 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0 /* 0xF0 to 0xFF */ +}; + +/*$PAGE*/ +/* +********************************************************************************************************* +* FUNCTION PROTOTYPES +********************************************************************************************************* +*/ + +static void OS_InitEventList(void); + +static void OS_InitMisc(void); + +static void OS_InitRdyList(void); + +static void OS_InitTaskIdle(void); + +#if OS_TASK_STAT_EN > 0 +static void OS_InitTaskStat(void); +#endif + +static void OS_InitTCBList(void); + +static void OS_SchedNew(void); + +/*$PAGE*/ +/* +********************************************************************************************************* +* GET THE NAME OF A SEMAPHORE, MUTEX, MAILBOX or QUEUE +* +* Description: This function is used to obtain the name assigned to a semaphore, mutex, mailbox or queue. +* +* Arguments : pevent is a pointer to the event group. 'pevent' can point either to a semaphore, +* a mutex, a mailbox or a queue. Where this function is concerned, the actual +* type is irrelevant. +* +* pname is a pointer to an ASCII string that will receive the name of the semaphore, +* mutex, mailbox or queue. The string must be able to hold at least +* OS_EVENT_NAME_SIZE characters. +* +* perr is a pointer to an error code that can contain one of the following values: +* +* OS_ERR_NONE if the name was copied to 'pname' +* OS_ERR_EVENT_TYPE if 'pevent' is not pointing to the proper event +* control block type. +* OS_ERR_PNAME_NULL You passed a NULL pointer for 'pname' +* OS_ERR_PEVENT_NULL if you passed a NULL pointer for 'pevent' +* OS_ERR_NAME_GET_ISR if you are trying to call this function from an ISR +* +* Returns : The length of the string or 0 if the 'pevent' is a NULL pointer. +********************************************************************************************************* +*/ + +#if (OS_EVENT_EN) && (OS_EVENT_NAME_SIZE > 1) +INT8U OSEventNameGet (OS_EVENT *pevent, INT8U *pname, INT8U *perr) +{ + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (0); + } + if (pevent == (OS_EVENT *)0) { /* Is 'pevent' a NULL pointer? */ + *perr = OS_ERR_PEVENT_NULL; + return (0); + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + *perr = OS_ERR_PNAME_NULL; + return (0); + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_NAME_GET_ISR; + return (0); + } + switch (pevent->OSEventType) { + case OS_EVENT_TYPE_SEM: + case OS_EVENT_TYPE_MUTEX: + case OS_EVENT_TYPE_MBOX: + case OS_EVENT_TYPE_Q: + break; + + default: + *perr = OS_ERR_EVENT_TYPE; + return (0); + } + OS_ENTER_CRITICAL(); + len = OS_StrCopy(pname, pevent->OSEventName); /* Copy name from OS_EVENT */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (len); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* ASSIGN A NAME TO A SEMAPHORE, MUTEX, MAILBOX or QUEUE +* +* Description: This function assigns a name to a semaphore, mutex, mailbox or queue. +* +* Arguments : pevent is a pointer to the event group. 'pevent' can point either to a semaphore, +* a mutex, a mailbox or a queue. Where this function is concerned, it doesn't +* matter the actual type. +* +* pname is a pointer to an ASCII string that will be used as the name of the semaphore, +* mutex, mailbox or queue. The string must be able to hold at least +* OS_EVENT_NAME_SIZE characters. +* +* perr is a pointer to an error code that can contain one of the following values: +* +* OS_ERR_NONE if the requested task is resumed +* OS_ERR_EVENT_TYPE if 'pevent' is not pointing to the proper event +* control block type. +* OS_ERR_PNAME_NULL You passed a NULL pointer for 'pname' +* OS_ERR_PEVENT_NULL if you passed a NULL pointer for 'pevent' +* OS_ERR_NAME_SET_ISR if you called this function from an ISR +* +* Returns : None +********************************************************************************************************* +*/ + +#if (OS_EVENT_EN) && (OS_EVENT_NAME_SIZE > 1) +void OSEventNameSet (OS_EVENT *pevent, INT8U *pname, INT8U *perr) +{ + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return; + } + if (pevent == (OS_EVENT *)0) { /* Is 'pevent' a NULL pointer? */ + *perr = OS_ERR_PEVENT_NULL; + return; + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + *perr = OS_ERR_PNAME_NULL; + return; + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_NAME_SET_ISR; + return; + } + switch (pevent->OSEventType) { + case OS_EVENT_TYPE_SEM: + case OS_EVENT_TYPE_MUTEX: + case OS_EVENT_TYPE_MBOX: + case OS_EVENT_TYPE_Q: + break; + + default: + *perr = OS_ERR_EVENT_TYPE; + return; + } + OS_ENTER_CRITICAL(); + len = OS_StrLen(pname); /* Can we fit the string in the storage area? */ + if (len > (OS_EVENT_NAME_SIZE - 1)) { /* No */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_EVENT_NAME_TOO_LONG; + return; + } + (void)OS_StrCopy(pevent->OSEventName, pname); /* Yes, copy name to the event control block */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* PEND ON MULTIPLE EVENTS +* +* Description: This function waits for multiple events. If multiple events are ready at the start of the +* pend call, then all available events are returned as ready. If the task must pend on the +* multiple events, then only the first posted or aborted event is returned as ready. +* +* Arguments : pevents_pend is a pointer to a NULL-terminated array of event control blocks to wait for. +* +* pevents_rdy is a pointer to an array to return which event control blocks are available +* or ready. The size of the array MUST be greater than or equal to the size +* of the 'pevents_pend' array, including terminating NULL. +* +* pmsgs_rdy is a pointer to an array to return messages from any available message-type +* events. The size of the array MUST be greater than or equal to the size of +* the 'pevents_pend' array, excluding the terminating NULL. Since NULL +* messages are valid messages, this array cannot be NULL-terminated. Instead, +* every available message-type event returns its messages in the 'pmsgs_rdy' +* array at the same index as the event is returned in the 'pevents_rdy' array. +* All other 'pmsgs_rdy' array indices are filled with NULL messages. +* +* timeout is an optional timeout period (in clock ticks). If non-zero, your task will +* wait for the resources up to the amount of time specified by this argument. +* If you specify 0, however, your task will wait forever for the specified +* events or, until the resources becomes available (or the events occur). +* +* perr is a pointer to where an error message will be deposited. Possible error +* messages are: +* +* OS_ERR_NONE The call was successful and your task owns the resources +* or, the events you are waiting for occurred; check the +* 'pevents_rdy' array for which events are available. +* OS_ERR_PEND_ABORT The wait on the events was aborted; check the +* 'pevents_rdy' array for which events were aborted. +* OS_ERR_TIMEOUT The events were not received within the specified +* 'timeout'. +* OS_ERR_PEVENT_NULL If 'pevents_pend', 'pevents_rdy', or 'pmsgs_rdy' is a +* NULL pointer. +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to an array of semaphores, +* mailboxes, and/or queues. +* OS_ERR_PEND_ISR If you called this function from an ISR and the result +* would lead to a suspension. +* OS_ERR_PEND_LOCKED If you called this function when the scheduler is locked. +* +* Returns : > 0 the number of events returned as ready or aborted. +* == 0 if no events are returned as ready because of timeout or upon error. +* +* Notes : 1) a. Validate 'pevents_pend' array as valid OS_EVENTs : +* +* semaphores, mailboxes, queues +* +* b. Return ALL available events and messages, if any +* +* c. Add current task priority as pending to each events's wait list +* Performed in OS_EventTaskWaitMulti() +* +* d. Wait on any of multiple events +* +* e. Remove current task priority as pending from each events's wait list +* Performed in OS_EventTaskRdy(), if events posted or aborted +* +* f. Return any event posted or aborted, if any +* else +* Return timeout +* +* 2) 'pevents_rdy' initialized to NULL PRIOR to all other validation or function handling in +* case of any error(s). +********************************************************************************************************* +*/ +/*$PAGE*/ +#if ((OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0)) +INT16U OSEventPendMulti (OS_EVENT **pevents_pend, OS_EVENT **pevents_rdy, void **pmsgs_rdy, INT16U timeout, INT8U *perr) +{ + OS_EVENT **pevents; + OS_EVENT *pevent; +#if ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) + OS_Q *pq; +#endif + BOOLEAN events_rdy; + INT16U events_rdy_nbr; + INT8U events_stat; +#if (OS_CRITICAL_METHOD == 3) /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if (OS_ARG_CHK_EN > 0) + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (0); + } + if (pevents_pend == (OS_EVENT **)0) { /* Validate 'pevents_pend' */ + *perr = OS_ERR_PEVENT_NULL; + return (0); + } + if (pevents_rdy == (OS_EVENT **)0) { /* Validate 'pevents_rdy' */ + *perr = OS_ERR_PEVENT_NULL; + return (0); + } + if (pmsgs_rdy == (void **)0) { /* Validate 'pmsgs_rdy' */ + *perr = OS_ERR_PEVENT_NULL; + return (0); + } +#endif + + *pevents_rdy = (OS_EVENT *)0; /* Init array to NULL in case of errors */ + + pevents = pevents_pend; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { + switch (pevent->OSEventType) { /* Validate event block types */ +#if (OS_SEM_EN > 0) + case OS_EVENT_TYPE_SEM: + break; +#endif +#if (OS_MBOX_EN > 0) + case OS_EVENT_TYPE_MBOX: + break; +#endif +#if ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) + case OS_EVENT_TYPE_Q: + break; +#endif + + case OS_EVENT_TYPE_MUTEX: + case OS_EVENT_TYPE_FLAG: + default: + *perr = OS_ERR_EVENT_TYPE; + return (0); + } + pevents++; + pevent = *pevents; + } + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + return (0); + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + return (0); + } + +/*$PAGE*/ + OS_ENTER_CRITICAL(); + events_rdy = OS_FALSE; + events_rdy_nbr = 0; + events_stat = OS_STAT_RDY; + pevents = pevents_pend; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { /* See if any events already available */ + switch (pevent->OSEventType) { +#if (OS_SEM_EN > 0) + case OS_EVENT_TYPE_SEM: + if (pevent->OSEventCnt > 0) { /* If semaphore count > 0, resource available; */ + pevent->OSEventCnt--; /* ... decrement semaphore, ... */ + *pevents_rdy++ = pevent; /* ... and return available semaphore event */ + events_rdy = OS_TRUE; + *pmsgs_rdy++ = (void *)0; /* NO message returned for semaphores */ + events_rdy_nbr++; + + } else { + events_stat |= OS_STAT_SEM; /* Configure multi-pend for semaphore events */ + } + break; +#endif + +#if (OS_MBOX_EN > 0) + case OS_EVENT_TYPE_MBOX: + if (pevent->OSEventPtr != (void *)0) { /* If mailbox NOT empty; ... */ + /* ... return available message, ... */ + *pmsgs_rdy++ = (void *)pevent->OSEventPtr; + pevent->OSEventPtr = (void *)0; + *pevents_rdy++ = pevent; /* ... and return available mailbox event */ + events_rdy = OS_TRUE; + events_rdy_nbr++; + + } else { + events_stat |= OS_STAT_MBOX; /* Configure multi-pend for mailbox events */ + } + break; +#endif + +#if ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) + case OS_EVENT_TYPE_Q: + pq = (OS_Q *)pevent->OSEventPtr; + if (pq->OSQEntries > 0) { /* If queue NOT empty; ... */ + /* ... return available message, ... */ + *pmsgs_rdy++ = (void *)*pq->OSQOut++; + if (pq->OSQOut == pq->OSQEnd) { /* If OUT ptr at queue end, ... */ + pq->OSQOut = pq->OSQStart; /* ... wrap to queue start */ + } + pq->OSQEntries--; /* Update number of queue entries */ + *pevents_rdy++ = pevent; /* ... and return available queue event */ + events_rdy = OS_TRUE; + events_rdy_nbr++; + + } else { + events_stat |= OS_STAT_Q; /* Configure multi-pend for queue events */ + } + break; +#endif + + case OS_EVENT_TYPE_MUTEX: + case OS_EVENT_TYPE_FLAG: + default: + OS_EXIT_CRITICAL(); + *pevents_rdy = (OS_EVENT *)0; /* NULL terminate return event array */ + *perr = OS_ERR_EVENT_TYPE; + return (events_rdy_nbr); + } + pevents++; + pevent = *pevents; + } + + if ( events_rdy == OS_TRUE) { /* Return any events already available */ + *pevents_rdy = (OS_EVENT *)0; /* NULL terminate return event array */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (events_rdy_nbr); + } +/*$PAGE*/ + /* Otherwise, must wait until any event occurs */ + OSTCBCur->OSTCBStat |= events_stat | /* Resource not available, ... */ + OS_STAT_MULTI; /* ... pend on multiple events */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + OSTCBCur->OSTCBDly = timeout; /* Store pend timeout in TCB */ + OS_EventTaskWaitMulti(pevents_pend); /* Suspend task until events or timeout occurs */ + + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next highest priority task ready */ + OS_ENTER_CRITICAL(); + + switch (OSTCBCur->OSTCBStatPend) { /* Handle event posted, aborted, or timed-out */ + case OS_STAT_PEND_OK: + case OS_STAT_PEND_ABORT: + pevent = OSTCBCur->OSTCBEventPtr; + if (pevent != (OS_EVENT *)0) { /* If task event ptr != NULL, ... */ + *pevents_rdy++ = pevent; /* ... return available event ... */ + *pevents_rdy = (OS_EVENT *)0; /* ... & NULL terminate return event array */ + events_rdy_nbr++; + + } else { /* Else NO event available, handle as timeout */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_TO; + OS_EventTaskRemoveMulti(OSTCBCur, pevents_pend); + } + break; + + case OS_STAT_PEND_TO: + default: /* ... remove task from events' wait lists */ + OS_EventTaskRemoveMulti(OSTCBCur, pevents_pend); + break; + } + + switch (OSTCBCur->OSTCBStatPend) { + case OS_STAT_PEND_OK: + switch (pevent->OSEventType) { /* Return event's message */ +#if (OS_SEM_EN > 0) + case OS_EVENT_TYPE_SEM: + *pmsgs_rdy++ = (void *)0; /* NO message returned for semaphores */ + break; +#endif + +#if ((OS_MBOX_EN > 0) || \ + ((OS_Q_EN > 0) && (OS_MAX_QS > 0))) + case OS_EVENT_TYPE_MBOX: + case OS_EVENT_TYPE_Q: + *pmsgs_rdy++ = (void *)OSTCBCur->OSTCBMsg; /* Return received message */ + break; +#endif + + case OS_EVENT_TYPE_MUTEX: + case OS_EVENT_TYPE_FLAG: + default: + OS_EXIT_CRITICAL(); + *pevents_rdy = (OS_EVENT *)0; /* NULL terminate return event array */ + *perr = OS_ERR_EVENT_TYPE; + return (events_rdy_nbr); + } + *perr = OS_ERR_NONE; + break; + + case OS_STAT_PEND_ABORT: + *pmsgs_rdy++ = (void *)0; /* NO message returned for abort */ + *perr = OS_ERR_PEND_ABORT; /* Indicate that event aborted */ + break; + + case OS_STAT_PEND_TO: + default: + *pmsgs_rdy++ = (void *)0; /* NO message returned for timeout */ + *perr = OS_ERR_TIMEOUT; /* Indicate that events timed out */ + break; + } + + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Set task status to ready */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; /* Clear event pointers */ + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0; + OSTCBCur->OSTCBMsg = (void *)0; /* Clear task message */ + OS_EXIT_CRITICAL(); + + return (events_rdy_nbr); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* INITIALIZATION +* +* Description: This function is used to initialize the internals of uC/OS-II and MUST be called prior to +* creating any uC/OS-II object and, prior to calling OSStart(). +* +* Arguments : none +* +* Returns : none +********************************************************************************************************* +*/ + +void OSInit (void) +{ + OSInitHookBegin(); /* Call port specific initialization code */ + + OS_InitMisc(); /* Initialize miscellaneous variables */ + + OS_InitRdyList(); /* Initialize the Ready List */ + + OS_InitTCBList(); /* Initialize the free list of OS_TCBs */ + + OS_InitEventList(); /* Initialize the free list of OS_EVENTs */ + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) + OS_FlagInit(); /* Initialize the event flag structures */ +#endif + +#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0) + OS_MemInit(); /* Initialize the memory manager */ +#endif + +#if (OS_Q_EN > 0) && (OS_MAX_QS > 0) + OS_QInit(); /* Initialize the message queue structures */ +#endif + + OS_InitTaskIdle(); /* Create the Idle Task */ +#if OS_TASK_STAT_EN > 0 + OS_InitTaskStat(); /* Create the Statistic Task */ +#endif + +#if OS_TMR_EN > 0 + OSTmr_Init(); /* Initialize the Timer Manager */ +#endif + + OSInitHookEnd(); /* Call port specific init. code */ + +#if OS_DEBUG_EN > 0 + OSDebugInit(); +#endif +} +/*$PAGE*/ +/* +********************************************************************************************************* +* ENTER ISR +* +* Description: This function is used to notify uC/OS-II that you are about to service an interrupt +* service routine (ISR). This allows uC/OS-II to keep track of interrupt nesting and thus +* only perform rescheduling at the last nested ISR. +* +* Arguments : none +* +* Returns : none +* +* Notes : 1) This function should be called ith interrupts already disabled +* 2) Your ISR can directly increment OSIntNesting without calling this function because +* OSIntNesting has been declared 'global'. +* 3) You MUST still call OSIntExit() even though you increment OSIntNesting directly. +* 4) You MUST invoke OSIntEnter() and OSIntExit() in pair. In other words, for every call +* to OSIntEnter() at the beginning of the ISR you MUST have a call to OSIntExit() at the +* end of the ISR. +* 5) You are allowed to nest interrupts up to 255 levels deep. +********************************************************************************************************* +*/ + +void OSIntEnter (void) +{ + if (OSRunning == OS_TRUE) { + if (OSIntNesting < 255u) { + OSIntNesting++; /* Increment ISR nesting level */ + } + } +} +/*$PAGE*/ +/* +********************************************************************************************************* +* EXIT ISR +* +* Description: This function is used to notify uC/OS-II that you have completed serviving an ISR. When +* the last nested ISR has completed, uC/OS-II will call the scheduler to determine whether +* a new, high-priority task, is ready to run. +* +* Arguments : none +* +* Returns : none +* +* Notes : 1) You MUST invoke OSIntEnter() and OSIntExit() in pair. In other words, for every call +* to OSIntEnter() at the beginning of the ISR you MUST have a call to OSIntExit() at the +* end of the ISR. +* 2) Rescheduling is prevented when the scheduler is locked (see OS_SchedLock()) +********************************************************************************************************* +*/ + +void OSIntExit (void) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + if (OSRunning == OS_TRUE) { + OS_ENTER_CRITICAL(); + if (OSIntNesting > 0) { /* Prevent OSIntNesting from wrapping */ + OSIntNesting--; + } + if (OSIntNesting == 0) { /* Reschedule only if all ISRs complete ... */ + if (OSLockNesting == 0) { /* ... and not locked. */ + OS_SchedNew(); + if (OSPrioHighRdy != OSPrioCur) { /* No Ctx Sw if current task is highest rdy */ + OSTCBHighRdy = OSTCBPrioTbl[OSPrioHighRdy]; +#if OS_TASK_PROFILE_EN > 0 + OSTCBHighRdy->OSTCBCtxSwCtr++; /* Inc. # of context switches to this task */ +#endif + OSCtxSwCtr++; /* Keep track of the number of ctx switches */ + OSIntCtxSw(); /* Perform interrupt level ctx switch */ + } + } + } + OS_EXIT_CRITICAL(); + } +} +/*$PAGE*/ +/* +********************************************************************************************************* +* PREVENT SCHEDULING +* +* Description: This function is used to prevent rescheduling to take place. This allows your application +* to prevent context switches until you are ready to permit context switching. +* +* Arguments : none +* +* Returns : none +* +* Notes : 1) You MUST invoke OSSchedLock() and OSSchedUnlock() in pair. In other words, for every +* call to OSSchedLock() you MUST have a call to OSSchedUnlock(). +********************************************************************************************************* +*/ + +#if OS_SCHED_LOCK_EN > 0 +void OSSchedLock (void) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + if (OSRunning == OS_TRUE) { /* Make sure multitasking is running */ + OS_ENTER_CRITICAL(); + if (OSIntNesting == 0) { /* Can't call from an ISR */ + if (OSLockNesting < 255u) { /* Prevent OSLockNesting from wrapping back to 0 */ + OSLockNesting++; /* Increment lock nesting level */ + } + } + OS_EXIT_CRITICAL(); + } +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* ENABLE SCHEDULING +* +* Description: This function is used to re-allow rescheduling. +* +* Arguments : none +* +* Returns : none +* +* Notes : 1) You MUST invoke OSSchedLock() and OSSchedUnlock() in pair. In other words, for every +* call to OSSchedLock() you MUST have a call to OSSchedUnlock(). +********************************************************************************************************* +*/ + +#if OS_SCHED_LOCK_EN > 0 +void OSSchedUnlock (void) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + if (OSRunning == OS_TRUE) { /* Make sure multitasking is running */ + OS_ENTER_CRITICAL(); + if (OSLockNesting > 0) { /* Do not decrement if already 0 */ + OSLockNesting--; /* Decrement lock nesting level */ + if (OSLockNesting == 0) { /* See if scheduler is enabled and ... */ + if (OSIntNesting == 0) { /* ... not in an ISR */ + OS_EXIT_CRITICAL(); + OS_Sched(); /* See if a HPT is ready */ + } else { + OS_EXIT_CRITICAL(); + } + } else { + OS_EXIT_CRITICAL(); + } + } else { + OS_EXIT_CRITICAL(); + } + } +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* START MULTITASKING +* +* Description: This function is used to start the multitasking process which lets uC/OS-II manages the +* task that you have created. Before you can call OSStart(), you MUST have called OSInit() +* and you MUST have created at least one task. +* +* Arguments : none +* +* Returns : none +* +* Note : OSStartHighRdy() MUST: +* a) Call OSTaskSwHook() then, +* b) Set OSRunning to OS_TRUE. +* c) Load the context of the task pointed to by OSTCBHighRdy. +* d_ Execute the task. +********************************************************************************************************* +*/ + +void OSStart (void) +{ + if (OSRunning == OS_FALSE) { + OS_SchedNew(); /* Find highest priority's task priority number */ + OSPrioCur = OSPrioHighRdy; + OSTCBHighRdy = OSTCBPrioTbl[OSPrioHighRdy]; /* Point to highest priority task ready to run */ + OSTCBCur = OSTCBHighRdy; + OSStartHighRdy(); /* Execute target specific code to start task */ + } +} +/*$PAGE*/ +/* +********************************************************************************************************* +* STATISTICS INITIALIZATION +* +* Description: This function is called by your application to establish CPU usage by first determining +* how high a 32-bit counter would count to in 1 second if no other tasks were to execute +* during that time. CPU usage is then determined by a low priority task which keeps track +* of this 32-bit counter every second but this time, with other tasks running. CPU usage is +* determined by: +* +* OSIdleCtr +* CPU Usage (%) = 100 * (1 - ------------) +* OSIdleCtrMax +* +* Arguments : none +* +* Returns : none +********************************************************************************************************* +*/ + +#if OS_TASK_STAT_EN > 0 +void OSStatInit (void) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + OSTimeDly(2); /* Synchronize with clock tick */ + OS_ENTER_CRITICAL(); + OSIdleCtr = 0L; /* Clear idle counter */ + OS_EXIT_CRITICAL(); + OSTimeDly(OS_TICKS_PER_SEC / 10); /* Determine MAX. idle counter value for 1/10 second */ + OS_ENTER_CRITICAL(); + OSIdleCtrMax = OSIdleCtr; /* Store maximum idle counter count in 1/10 second */ + OSStatRdy = OS_TRUE; + OS_EXIT_CRITICAL(); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* PROCESS SYSTEM TICK +* +* Description: This function is used to signal to uC/OS-II the occurrence of a 'system tick' (also known +* as a 'clock tick'). This function should be called by the ticker ISR but, can also be +* called by a high priority task. +* +* Arguments : none +* +* Returns : none +********************************************************************************************************* +*/ + +void OSTimeTick (void) +{ + OS_TCB *ptcb; +#if OS_TICK_STEP_EN > 0 + BOOLEAN step; +#endif +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_TIME_TICK_HOOK_EN > 0 + OSTimeTickHook(); /* Call user definable hook */ +#endif +#if OS_TIME_GET_SET_EN > 0 + OS_ENTER_CRITICAL(); /* Update the 32-bit tick counter */ + OSTime++; + OS_EXIT_CRITICAL(); +#endif + if (OSRunning == OS_TRUE) { +#if OS_TICK_STEP_EN > 0 + switch (OSTickStepState) { /* Determine whether we need to process a tick */ + case OS_TICK_STEP_DIS: /* Yes, stepping is disabled */ + step = OS_TRUE; + break; + + case OS_TICK_STEP_WAIT: /* No, waiting for uC/OS-View to set ... */ + step = OS_FALSE; /* .. OSTickStepState to OS_TICK_STEP_ONCE */ + break; + + case OS_TICK_STEP_ONCE: /* Yes, process tick once and wait for next ... */ + step = OS_TRUE; /* ... step command from uC/OS-View */ + OSTickStepState = OS_TICK_STEP_WAIT; + break; + + default: /* Invalid case, correct situation */ + step = OS_TRUE; + OSTickStepState = OS_TICK_STEP_DIS; + break; + } + if (step == OS_FALSE) { /* Return if waiting for step command */ + return; + } +#endif + ptcb = OSTCBList; /* Point at first TCB in TCB list */ + while (ptcb->OSTCBPrio != OS_TASK_IDLE_PRIO) { /* Go through all TCBs in TCB list */ + OS_ENTER_CRITICAL(); + if (ptcb->OSTCBDly != 0) { /* No, Delayed or waiting for event with TO */ + if (--ptcb->OSTCBDly == 0) { /* Decrement nbr of ticks to end of delay */ + /* Check for timeout */ + if ((ptcb->OSTCBStat & OS_STAT_PEND_ANY) != OS_STAT_RDY) { + ptcb->OSTCBStat &= ~(INT8U)OS_STAT_PEND_ANY; /* Yes, Clear status flag */ + ptcb->OSTCBStatPend = OS_STAT_PEND_TO; /* Indicate PEND timeout */ + } else { + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; + } + + if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) == OS_STAT_RDY) { /* Is task suspended? */ + OSRdyGrp |= ptcb->OSTCBBitY; /* No, Make ready */ + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + } + } + } + ptcb = ptcb->OSTCBNext; /* Point at next TCB in TCB list */ + OS_EXIT_CRITICAL(); + } + } +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* GET VERSION +* +* Description: This function is used to return the version number of uC/OS-II. The returned value +* corresponds to uC/OS-II's version number multiplied by 100. In other words, version 2.00 +* would be returned as 200. +* +* Arguments : none +* +* Returns : the version number of uC/OS-II multiplied by 100. +********************************************************************************************************* +*/ + +INT16U OSVersion (void) +{ + return (OS_VERSION); +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* DUMMY FUNCTION +* +* Description: This function doesn't do anything. It is called by OSTaskDel(). +* +* Arguments : none +* +* Returns : none +********************************************************************************************************* +*/ + +#if OS_TASK_DEL_EN > 0 +void OS_Dummy (void) +{ +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* MAKE TASK READY TO RUN BASED ON EVENT OCCURING +* +* Description: This function is called by other uC/OS-II services and is used to ready a task that was +* waiting for an event to occur. +* +* Arguments : pevent is a pointer to the event control block corresponding to the event. +* +* pmsg is a pointer to a message. This pointer is used by message oriented services +* such as MAILBOXEs and QUEUEs. The pointer is not used when called by other +* service functions. +* +* msk is a mask that is used to clear the status byte of the TCB. For example, +* OSSemPost() will pass OS_STAT_SEM, OSMboxPost() will pass OS_STAT_MBOX etc. +* +* pend_stat is used to indicate the readied task's pending status: +* +* OS_STAT_PEND_OK Task ready due to a post (or delete), not a timeout or +* an abort. +* OS_STAT_PEND_ABORT Task ready due to an abort. +* +* Returns : none +* +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if (OS_EVENT_EN) +INT8U OS_EventTaskRdy (OS_EVENT *pevent, void *pmsg, INT8U msk, INT8U pend_stat) +{ + OS_TCB *ptcb; + INT8U y; + INT8U x; + INT8U prio; +#if OS_LOWEST_PRIO > 63 + INT16U *ptbl; +#endif + + +#if OS_LOWEST_PRIO <= 63 + y = OSUnMapTbl[pevent->OSEventGrp]; /* Find HPT waiting for message */ + x = OSUnMapTbl[pevent->OSEventTbl[y]]; + prio = (INT8U)((y << 3) + x); /* Find priority of task getting the msg */ +#else + if ((pevent->OSEventGrp & 0xFF) != 0) { /* Find HPT waiting for message */ + y = OSUnMapTbl[ pevent->OSEventGrp & 0xFF]; + } else { + y = OSUnMapTbl[(pevent->OSEventGrp >> 8) & 0xFF] + 8; + } + ptbl = &pevent->OSEventTbl[y]; + if ((*ptbl & 0xFF) != 0) { + x = OSUnMapTbl[*ptbl & 0xFF]; + } else { + x = OSUnMapTbl[(*ptbl >> 8) & 0xFF] + 8; + } + prio = (INT8U)((y << 4) + x); /* Find priority of task getting the msg */ +#endif + + ptcb = OSTCBPrioTbl[prio]; /* Point to this task's OS_TCB */ + ptcb->OSTCBDly = 0; /* Prevent OSTimeTick() from readying task */ +#if ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) || (OS_MBOX_EN > 0) + ptcb->OSTCBMsg = pmsg; /* Send message directly to waiting task */ +#else + pmsg = pmsg; /* Prevent compiler warning if not used */ +#endif + ptcb->OSTCBStat &= ~msk; /* Clear bit associated with event type */ + ptcb->OSTCBStatPend = pend_stat; /* Set pend status of post or abort */ + /* See if task is ready (could be susp'd) */ + if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) == OS_STAT_RDY) { + OSRdyGrp |= ptcb->OSTCBBitY; /* Put task in the ready to run list */ + OSRdyTbl[y] |= ptcb->OSTCBBitX; + } + + OS_EventTaskRemove(ptcb, pevent); /* Remove this task from event wait list */ +#if (OS_EVENT_MULTI_EN > 0) + if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) { /* Remove this task from events' wait lists */ + OS_EventTaskRemoveMulti(ptcb, ptcb->OSTCBEventMultiPtr); + ptcb->OSTCBEventPtr = (OS_EVENT *)pevent;/* Return event as first multi-pend event ready*/ + } +#endif + + return (prio); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* MAKE TASK WAIT FOR EVENT TO OCCUR +* +* Description: This function is called by other uC/OS-II services to suspend a task because an event has +* not occurred. +* +* Arguments : pevent is a pointer to the event control block for which the task will be waiting for. +* +* Returns : none +* +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if (OS_EVENT_EN) +void OS_EventTaskWait (OS_EVENT *pevent) +{ + INT8U y; + + + OSTCBCur->OSTCBEventPtr = pevent; /* Store ptr to ECB in TCB */ + + pevent->OSEventTbl[OSTCBCur->OSTCBY] |= OSTCBCur->OSTCBBitX; /* Put task in waiting list */ + pevent->OSEventGrp |= OSTCBCur->OSTCBBitY; + + y = OSTCBCur->OSTCBY; /* Task no longer ready */ + OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX; + if (OSRdyTbl[y] == 0) { + OSRdyGrp &= ~OSTCBCur->OSTCBBitY; /* Clear event grp bit if this was only task pending */ + } +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* MAKE TASK WAIT FOR ANY OF MULTIPLE EVENTS TO OCCUR +* +* Description: This function is called by other uC/OS-II services to suspend a task because any one of +* multiple events has not occurred. +* +* Arguments : pevents_wait is a pointer to an array of event control blocks, NULL-terminated, for +* which the task will be waiting for. +* +* Returns : none. +* +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if ((OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0)) +void OS_EventTaskWaitMulti (OS_EVENT **pevents_wait) +{ + OS_EVENT **pevents; + OS_EVENT *pevent; + INT8U y; + + + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)pevents_wait; /* Store ptr to ECBs in TCB */ + + pevents = pevents_wait; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { /* Put task in waiting lists */ + pevent->OSEventTbl[OSTCBCur->OSTCBY] |= OSTCBCur->OSTCBBitX; + pevent->OSEventGrp |= OSTCBCur->OSTCBBitY; + pevents++; + pevent = *pevents; + } + + y = OSTCBCur->OSTCBY; /* Task no longer ready */ + OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX; + if (OSRdyTbl[y] == 0) { + OSRdyGrp &= ~OSTCBCur->OSTCBBitY; /* Clear event grp bit if this was only task pending */ + } +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* REMOVE TASK FROM EVENT WAIT LIST +* +* Description: Remove a task from an event's wait list. +* +* Arguments : ptcb is a pointer to the task to remove. +* +* pevent is a pointer to the event control block. +* +* Returns : none +* +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if (OS_EVENT_EN) +void OS_EventTaskRemove (OS_TCB *ptcb, + OS_EVENT *pevent) +{ + INT8U y; + + + y = ptcb->OSTCBY; + pevent->OSEventTbl[y] &= ~ptcb->OSTCBBitX; /* Remove task from wait list */ + if (pevent->OSEventTbl[y] == 0) { + pevent->OSEventGrp &= ~ptcb->OSTCBBitY; + } +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* REMOVE TASK FROM MULTIPLE EVENTS WAIT LISTS +* +* Description: Remove a task from multiple events' wait lists. +* +* Arguments : ptcb is a pointer to the task to remove. +* +* pevents_multi is a pointer to the array of event control blocks, NULL-terminated. +* +* Returns : none +* +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if ((OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0)) +void OS_EventTaskRemoveMulti (OS_TCB *ptcb, + OS_EVENT **pevents_multi) +{ + OS_EVENT **pevents; + OS_EVENT *pevent; + INT8U y; +#if (OS_LOWEST_PRIO <= 63) + INT8U bity; + INT8U bitx; +#else + INT16U bity; + INT16U bitx; +#endif + + + y = ptcb->OSTCBY; + bity = ptcb->OSTCBBitY; + bitx = ptcb->OSTCBBitX; + pevents = pevents_multi; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { /* Remove task from all events' wait lists */ + pevent->OSEventTbl[y] &= ~bitx; + if (pevent->OSEventTbl[y] == 0) { + pevent->OSEventGrp &= ~bity; + } + pevents++; + pevent = *pevents; + } +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* INITIALIZE EVENT CONTROL BLOCK'S WAIT LIST +* +* Description: This function is called by other uC/OS-II services to initialize the event wait list. +* +* Arguments : pevent is a pointer to the event control block allocated to the event. +* +* Returns : none +* +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if (OS_EVENT_EN) +void OS_EventWaitListInit (OS_EVENT *pevent) +{ +#if OS_LOWEST_PRIO <= 63 + INT8U *ptbl; +#else + INT16U *ptbl; +#endif + INT8U i; + + + pevent->OSEventGrp = 0; /* No task waiting on event */ + ptbl = &pevent->OSEventTbl[0]; + + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + *ptbl++ = 0; + } +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* INITIALIZATION +* INITIALIZE THE FREE LIST OF EVENT CONTROL BLOCKS +* +* Description: This function is called by OSInit() to initialize the free list of event control blocks. +* +* Arguments : none +* +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitEventList (void) +{ +#if (OS_EVENT_EN) && (OS_MAX_EVENTS > 0) +#if (OS_MAX_EVENTS > 1) + INT16U i; + OS_EVENT *pevent1; + OS_EVENT *pevent2; + + + OS_MemClr((INT8U *)&OSEventTbl[0], sizeof(OSEventTbl)); /* Clear the event table */ + pevent1 = &OSEventTbl[0]; + pevent2 = &OSEventTbl[1]; + for (i = 0; i < (OS_MAX_EVENTS - 1); i++) { /* Init. list of free EVENT control blocks */ + pevent1->OSEventType = OS_EVENT_TYPE_UNUSED; + pevent1->OSEventPtr = pevent2; +#if OS_EVENT_NAME_SIZE > 1 + pevent1->OSEventName[0] = '?'; /* Unknown name */ + pevent1->OSEventName[1] = OS_ASCII_NUL; +#endif + pevent1++; + pevent2++; + } + pevent1->OSEventType = OS_EVENT_TYPE_UNUSED; + pevent1->OSEventPtr = (OS_EVENT *)0; +#if OS_EVENT_NAME_SIZE > 1 + pevent1->OSEventName[0] = '?'; + pevent1->OSEventName[1] = OS_ASCII_NUL; +#endif + OSEventFreeList = &OSEventTbl[0]; +#else + OSEventFreeList = &OSEventTbl[0]; /* Only have ONE event control block */ + OSEventFreeList->OSEventType = OS_EVENT_TYPE_UNUSED; + OSEventFreeList->OSEventPtr = (OS_EVENT *)0; +#if OS_EVENT_NAME_SIZE > 1 + OSEventFreeList->OSEventName[0] = '?'; /* Unknown name */ + OSEventFreeList->OSEventName[1] = OS_ASCII_NUL; +#endif +#endif +#endif +} +/*$PAGE*/ +/* +********************************************************************************************************* +* INITIALIZATION +* INITIALIZE MISCELLANEOUS VARIABLES +* +* Description: This function is called by OSInit() to initialize miscellaneous variables. +* +* Arguments : none +* +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitMisc (void) +{ +#if OS_TIME_GET_SET_EN > 0 + OSTime = 0L; /* Clear the 32-bit system clock */ +#endif + + OSIntNesting = 0; /* Clear the interrupt nesting counter */ + OSLockNesting = 0; /* Clear the scheduling lock counter */ + + OSTaskCtr = 0; /* Clear the number of tasks */ + + OSRunning = OS_FALSE; /* Indicate that multitasking not started */ + + OSCtxSwCtr = 0; /* Clear the context switch counter */ + OSIdleCtr = 0L; /* Clear the 32-bit idle counter */ + +#if OS_TASK_STAT_EN > 0 + OSIdleCtrRun = 0L; + OSIdleCtrMax = 0L; + OSStatRdy = OS_FALSE; /* Statistic task is not ready */ +#endif +} +/*$PAGE*/ +/* +********************************************************************************************************* +* INITIALIZATION +* INITIALIZE THE READY LIST +* +* Description: This function is called by OSInit() to initialize the Ready List. +* +* Arguments : none +* +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitRdyList (void) +{ + INT8U i; +#if OS_LOWEST_PRIO <= 63 + INT8U *prdytbl; +#else + INT16U *prdytbl; +#endif + + + OSRdyGrp = 0; /* Clear the ready list */ + prdytbl = &OSRdyTbl[0]; + for (i = 0; i < OS_RDY_TBL_SIZE; i++) { + *prdytbl++ = 0; + } + + OSPrioCur = 0; + OSPrioHighRdy = 0; + + OSTCBHighRdy = (OS_TCB *)0; + OSTCBCur = (OS_TCB *)0; +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* INITIALIZATION +* CREATING THE IDLE TASK +* +* Description: This function creates the Idle Task. +* +* Arguments : none +* +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitTaskIdle (void) +{ +#if OS_TASK_NAME_SIZE > 7 + INT8U err; +#endif + + +#if OS_TASK_CREATE_EXT_EN > 0 + #if OS_STK_GROWTH == 1 + (void)OSTaskCreateExt(OS_TaskIdle, + (void *)0, /* No arguments passed to OS_TaskIdle() */ + &OSTaskIdleStk[OS_TASK_IDLE_STK_SIZE - 1], /* Set Top-Of-Stack */ + OS_TASK_IDLE_PRIO, /* Lowest priority level */ + OS_TASK_IDLE_ID, + &OSTaskIdleStk[0], /* Set Bottom-Of-Stack */ + OS_TASK_IDLE_STK_SIZE, + (void *)0, /* No TCB extension */ + OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR);/* Enable stack checking + clear stack */ + #else + (void)OSTaskCreateExt(OS_TaskIdle, + (void *)0, /* No arguments passed to OS_TaskIdle() */ + &OSTaskIdleStk[0], /* Set Top-Of-Stack */ + OS_TASK_IDLE_PRIO, /* Lowest priority level */ + OS_TASK_IDLE_ID, + &OSTaskIdleStk[OS_TASK_IDLE_STK_SIZE - 1], /* Set Bottom-Of-Stack */ + OS_TASK_IDLE_STK_SIZE, + (void *)0, /* No TCB extension */ + OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR);/* Enable stack checking + clear stack */ + #endif +#else + #if OS_STK_GROWTH == 1 + (void)OSTaskCreate(OS_TaskIdle, + (void *)0, + &OSTaskIdleStk[OS_TASK_IDLE_STK_SIZE - 1], + OS_TASK_IDLE_PRIO); + #else + (void)OSTaskCreate(OS_TaskIdle, + (void *)0, + &OSTaskIdleStk[0], + OS_TASK_IDLE_PRIO); + #endif +#endif + +#if OS_TASK_NAME_SIZE > 14 + OSTaskNameSet(OS_TASK_IDLE_PRIO, (INT8U *)"uC/OS-II Idle", &err); +#else +#if OS_TASK_NAME_SIZE > 7 + OSTaskNameSet(OS_TASK_IDLE_PRIO, (INT8U *)"OS-Idle", &err); +#endif +#endif +} +/*$PAGE*/ +/* +********************************************************************************************************* +* INITIALIZATION +* CREATING THE STATISTIC TASK +* +* Description: This function creates the Statistic Task. +* +* Arguments : none +* +* Returns : none +********************************************************************************************************* +*/ + +#if OS_TASK_STAT_EN > 0 +static void OS_InitTaskStat (void) +{ +#if OS_TASK_NAME_SIZE > 7 + INT8U err; +#endif + + +#if OS_TASK_CREATE_EXT_EN > 0 + #if OS_STK_GROWTH == 1 + (void)OSTaskCreateExt(OS_TaskStat, + (void *)0, /* No args passed to OS_TaskStat()*/ + &OSTaskStatStk[OS_TASK_STAT_STK_SIZE - 1], /* Set Top-Of-Stack */ + OS_TASK_STAT_PRIO, /* One higher than the idle task */ + OS_TASK_STAT_ID, + &OSTaskStatStk[0], /* Set Bottom-Of-Stack */ + OS_TASK_STAT_STK_SIZE, + (void *)0, /* No TCB extension */ + OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR); /* Enable stack checking + clear */ + #else + (void)OSTaskCreateExt(OS_TaskStat, + (void *)0, /* No args passed to OS_TaskStat()*/ + &OSTaskStatStk[0], /* Set Top-Of-Stack */ + OS_TASK_STAT_PRIO, /* One higher than the idle task */ + OS_TASK_STAT_ID, + &OSTaskStatStk[OS_TASK_STAT_STK_SIZE - 1], /* Set Bottom-Of-Stack */ + OS_TASK_STAT_STK_SIZE, + (void *)0, /* No TCB extension */ + OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR); /* Enable stack checking + clear */ + #endif +#else + #if OS_STK_GROWTH == 1 + (void)OSTaskCreate(OS_TaskStat, + (void *)0, /* No args passed to OS_TaskStat()*/ + &OSTaskStatStk[OS_TASK_STAT_STK_SIZE - 1], /* Set Top-Of-Stack */ + OS_TASK_STAT_PRIO); /* One higher than the idle task */ + #else + (void)OSTaskCreate(OS_TaskStat, + (void *)0, /* No args passed to OS_TaskStat()*/ + &OSTaskStatStk[0], /* Set Top-Of-Stack */ + OS_TASK_STAT_PRIO); /* One higher than the idle task */ + #endif +#endif + +#if OS_TASK_NAME_SIZE > 14 + OSTaskNameSet(OS_TASK_STAT_PRIO, (INT8U *)"uC/OS-II Stat", &err); +#else +#if OS_TASK_NAME_SIZE > 7 + OSTaskNameSet(OS_TASK_STAT_PRIO, (INT8U *)"OS-Stat", &err); +#endif +#endif +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* INITIALIZATION +* INITIALIZE THE FREE LIST OF TASK CONTROL BLOCKS +* +* Description: This function is called by OSInit() to initialize the free list of OS_TCBs. +* +* Arguments : none +* +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitTCBList (void) +{ + INT8U i; + OS_TCB *ptcb1; + OS_TCB *ptcb2; + + + OS_MemClr((INT8U *)&OSTCBTbl[0], sizeof(OSTCBTbl)); /* Clear all the TCBs */ + OS_MemClr((INT8U *)&OSTCBPrioTbl[0], sizeof(OSTCBPrioTbl)); /* Clear the priority table */ + ptcb1 = &OSTCBTbl[0]; + ptcb2 = &OSTCBTbl[1]; + for (i = 0; i < (OS_MAX_TASKS + OS_N_SYS_TASKS - 1); i++) { /* Init. list of free TCBs */ + ptcb1->OSTCBNext = ptcb2; +#if OS_TASK_NAME_SIZE > 1 + ptcb1->OSTCBTaskName[0] = '?'; /* Unknown name */ + ptcb1->OSTCBTaskName[1] = OS_ASCII_NUL; +#endif + ptcb1++; + ptcb2++; + } + ptcb1->OSTCBNext = (OS_TCB *)0; /* Last OS_TCB */ +#if OS_TASK_NAME_SIZE > 1 + ptcb1->OSTCBTaskName[0] = '?'; /* Unknown name */ + ptcb1->OSTCBTaskName[1] = OS_ASCII_NUL; +#endif + OSTCBList = (OS_TCB *)0; /* TCB lists initializations */ + OSTCBFreeList = &OSTCBTbl[0]; +} +/*$PAGE*/ +/* +********************************************************************************************************* +* CLEAR A SECTION OF MEMORY +* +* Description: This function is called by other uC/OS-II services to clear a contiguous block of RAM. +* +* Arguments : pdest is the start of the RAM to clear (i.e. write 0x00 to) +* +* size is the number of bytes to clear. +* +* Returns : none +* +* Notes : 1) This function is INTERNAL to uC/OS-II and your application should not call it. +* 2) Note that we can only clear up to 64K bytes of RAM. This is not an issue because none +* of the uses of this function gets close to this limit. +* 3) The clear is done one byte at a time since this will work on any processor irrespective +* of the alignment of the destination. +********************************************************************************************************* +*/ + +void OS_MemClr (INT8U *pdest, INT16U size) +{ + while (size > 0) { + *pdest++ = (INT8U)0; + size--; + } +} +/*$PAGE*/ +/* +********************************************************************************************************* +* COPY A BLOCK OF MEMORY +* +* Description: This function is called by other uC/OS-II services to copy a block of memory from one +* location to another. +* +* Arguments : pdest is a pointer to the 'destination' memory block +* +* psrc is a pointer to the 'source' memory block +* +* size is the number of bytes to copy. +* +* Returns : none +* +* Notes : 1) This function is INTERNAL to uC/OS-II and your application should not call it. There is +* no provision to handle overlapping memory copy. However, that's not a problem since this +* is not a situation that will happen. +* 2) Note that we can only copy up to 64K bytes of RAM +* 3) The copy is done one byte at a time since this will work on any processor irrespective +* of the alignment of the source and destination. +********************************************************************************************************* +*/ + +void OS_MemCopy (INT8U *pdest, INT8U *psrc, INT16U size) +{ + while (size > 0) { + *pdest++ = *psrc++; + size--; + } +} +/*$PAGE*/ +/* +********************************************************************************************************* +* SCHEDULER +* +* Description: This function is called by other uC/OS-II services to determine whether a new, high +* priority task has been made ready to run. This function is invoked by TASK level code +* and is not used to reschedule tasks from ISRs (see OSIntExit() for ISR rescheduling). +* +* Arguments : none +* +* Returns : none +* +* Notes : 1) This function is INTERNAL to uC/OS-II and your application should not call it. +* 2) Rescheduling is prevented when the scheduler is locked (see OS_SchedLock()) +********************************************************************************************************* +*/ + +void OS_Sched (void) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + OS_ENTER_CRITICAL(); + if (OSIntNesting == 0) { /* Schedule only if all ISRs done and ... */ + if (OSLockNesting == 0) { /* ... scheduler is not locked */ + OS_SchedNew(); + if (OSPrioHighRdy != OSPrioCur) { /* No Ctx Sw if current task is highest rdy */ + OSTCBHighRdy = OSTCBPrioTbl[OSPrioHighRdy]; +#if OS_TASK_PROFILE_EN > 0 + OSTCBHighRdy->OSTCBCtxSwCtr++; /* Inc. # of context switches to this task */ +#endif + OSCtxSwCtr++; /* Increment context switch counter */ + OS_TASK_SW(); /* Perform a context switch */ + } + } + } + OS_EXIT_CRITICAL(); +} + + +/* +********************************************************************************************************* +* FIND HIGHEST PRIORITY TASK READY TO RUN +* +* Description: This function is called by other uC/OS-II services to determine the highest priority task +* that is ready to run. The global variable 'OSPrioHighRdy' is changed accordingly. +* +* Arguments : none +* +* Returns : none +* +* Notes : 1) This function is INTERNAL to uC/OS-II and your application should not call it. +* 2) Interrupts are assumed to be disabled when this function is called. +********************************************************************************************************* +*/ + +static void OS_SchedNew (void) +{ +#if OS_LOWEST_PRIO <= 63 /* See if we support up to 64 tasks */ + INT8U y; + + + y = OSUnMapTbl[OSRdyGrp]; + OSPrioHighRdy = (INT8U)((y << 3) + OSUnMapTbl[OSRdyTbl[y]]); +#else /* We support up to 256 tasks */ + INT8U y; + INT16U *ptbl; + + + if ((OSRdyGrp & 0xFF) != 0) { + y = OSUnMapTbl[OSRdyGrp & 0xFF]; + } else { + y = OSUnMapTbl[(OSRdyGrp >> 8) & 0xFF] + 8; + } + ptbl = &OSRdyTbl[y]; + if ((*ptbl & 0xFF) != 0) { + OSPrioHighRdy = (INT8U)((y << 4) + OSUnMapTbl[(*ptbl & 0xFF)]); + } else { + OSPrioHighRdy = (INT8U)((y << 4) + OSUnMapTbl[(*ptbl >> 8) & 0xFF] + 8); + } +#endif +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* COPY AN ASCII STRING +* +* Description: This function is called by other uC/OS-II services to copy an ASCII string from a 'source' +* string to a 'destination' string. +* +* Arguments : pdest is a pointer to the string that will be receiving the copy. Note that there MUST +* be sufficient space in the destination storage area to receive this string. +* +* psrc is a pointer to the source string. The source string MUST NOT be greater than +* 254 characters. +* +* Returns : The size of the string (excluding the NUL terminating character) +* +* Notes : 1) This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +#if (OS_EVENT_NAME_SIZE > 1) || (OS_FLAG_NAME_SIZE > 1) || (OS_MEM_NAME_SIZE > 1) || (OS_TASK_NAME_SIZE > 1) || (OS_TMR_CFG_NAME_SIZE > 1) +INT8U OS_StrCopy (INT8U *pdest, INT8U *psrc) +{ + INT8U len; + + + len = 0; + while (*psrc != OS_ASCII_NUL) { + *pdest++ = *psrc++; + len++; + } + *pdest = OS_ASCII_NUL; + return (len); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* DETERMINE THE LENGTH OF AN ASCII STRING +* +* Description: This function is called by other uC/OS-II services to determine the size of an ASCII string +* (excluding the NUL character). +* +* Arguments : psrc is a pointer to the string for which we need to know the size. +* +* Returns : The size of the string (excluding the NUL terminating character) +* +* Notes : 1) This function is INTERNAL to uC/OS-II and your application should not call it. +* 2) The string to check must be less than 255 characters long. +********************************************************************************************************* +*/ + +#if (OS_EVENT_NAME_SIZE > 1) || (OS_FLAG_NAME_SIZE > 1) || (OS_MEM_NAME_SIZE > 1) || (OS_TASK_NAME_SIZE > 1) || (OS_TMR_CFG_NAME_SIZE > 1) +INT8U OS_StrLen (INT8U *psrc) +{ + INT8U len; + + + len = 0; + while (*psrc != OS_ASCII_NUL) { + psrc++; + len++; + } + return (len); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* IDLE TASK +* +* Description: This task is internal to uC/OS-II and executes whenever no other higher priority tasks +* executes because they are ALL waiting for event(s) to occur. +* +* Arguments : none +* +* Returns : none +* +* Note(s) : 1) OSTaskIdleHook() is called after the critical section to ensure that interrupts will be +* enabled for at least a few instructions. On some processors (ex. Philips XA), enabling +* and then disabling interrupts didn't allow the processor enough time to have interrupts +* enabled before they were disabled again. uC/OS-II would thus never recognize +* interrupts. +* 2) This hook has been added to allow you to do such things as STOP the CPU to conserve +* power. +********************************************************************************************************* +*/ + +void OS_TaskIdle (void *p_arg) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + (void)p_arg; /* Prevent compiler warning for not using 'p_arg' */ + for (;;) { + OS_ENTER_CRITICAL(); + OSIdleCtr++; + OS_EXIT_CRITICAL(); + OSTaskIdleHook(); /* Call user definable HOOK */ + } +} +/*$PAGE*/ +/* +********************************************************************************************************* +* STATISTICS TASK +* +* Description: This task is internal to uC/OS-II and is used to compute some statistics about the +* multitasking environment. Specifically, OS_TaskStat() computes the CPU usage. +* CPU usage is determined by: +* +* OSIdleCtr +* OSCPUUsage = 100 * (1 - ------------) (units are in %) +* OSIdleCtrMax +* +* Arguments : parg this pointer is not used at this time. +* +* Returns : none +* +* Notes : 1) This task runs at a priority level higher than the idle task. In fact, it runs at the +* next higher priority, OS_TASK_IDLE_PRIO-1. +* 2) You can disable this task by setting the configuration #define OS_TASK_STAT_EN to 0. +* 3) You MUST have at least a delay of 2/10 seconds to allow for the system to establish the +* maximum value for the idle counter. +********************************************************************************************************* +*/ + +#if OS_TASK_STAT_EN > 0 +void OS_TaskStat (void *p_arg) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + (void)p_arg; /* Prevent compiler warning for not using 'p_arg' */ + while (OSStatRdy == OS_FALSE) { + OSTimeDly(2 * OS_TICKS_PER_SEC / 10); /* Wait until statistic task is ready */ + } + OSIdleCtrMax /= 100L; + if (OSIdleCtrMax == 0L) { + OSCPUUsage = 0; + (void)OSTaskSuspend(OS_PRIO_SELF); + } + for (;;) { + OS_ENTER_CRITICAL(); + OSIdleCtrRun = OSIdleCtr; /* Obtain the of the idle counter for the past second */ + OSIdleCtr = 0L; /* Reset the idle counter for the next second */ + OS_EXIT_CRITICAL(); + OSCPUUsage = (INT8U)(100L - OSIdleCtrRun / OSIdleCtrMax); + OSTaskStatHook(); /* Invoke user definable hook */ +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) + OS_TaskStatStkChk(); /* Check the stacks for each task */ +#endif + OSTimeDly(OS_TICKS_PER_SEC / 10); /* Accumulate OSIdleCtr for the next 1/10 second */ + } +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* CHECK ALL TASK STACKS +* +* Description: This function is called by OS_TaskStat() to check the stacks of each active task. +* +* Arguments : none +* +* Returns : none +********************************************************************************************************* +*/ + +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) +void OS_TaskStatStkChk (void) +{ + OS_TCB *ptcb; + OS_STK_DATA stk_data; + INT8U err; + INT8U prio; + + + for (prio = 0; prio <= OS_TASK_IDLE_PRIO; prio++) { + err = OSTaskStkChk(prio, &stk_data); + if (err == OS_ERR_NONE) { + ptcb = OSTCBPrioTbl[prio]; + if (ptcb != (OS_TCB *)0) { /* Make sure task 'ptcb' is ... */ + if (ptcb != OS_TCB_RESERVED) { /* ... still valid. */ +#if OS_TASK_PROFILE_EN > 0 + #if OS_STK_GROWTH == 1 + ptcb->OSTCBStkBase = ptcb->OSTCBStkBottom + ptcb->OSTCBStkSize; + #else + ptcb->OSTCBStkBase = ptcb->OSTCBStkBottom - ptcb->OSTCBStkSize; + #endif + ptcb->OSTCBStkUsed = stk_data.OSUsed; /* Store the number of bytes used */ +#endif + } + } + } + } +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* INITIALIZE TCB +* +* Description: This function is internal to uC/OS-II and is used to initialize a Task Control Block when +* a task is created (see OSTaskCreate() and OSTaskCreateExt()). +* +* Arguments : prio is the priority of the task being created +* +* ptos is a pointer to the task's top-of-stack assuming that the CPU registers +* have been placed on the stack. Note that the top-of-stack corresponds to a +* 'high' memory location is OS_STK_GROWTH is set to 1 and a 'low' memory +* location if OS_STK_GROWTH is set to 0. Note that stack growth is CPU +* specific. +* +* pbos is a pointer to the bottom of stack. A NULL pointer is passed if called by +* 'OSTaskCreate()'. +* +* id is the task's ID (0..65535) +* +* stk_size is the size of the stack (in 'stack units'). If the stack units are INT8Us +* then, 'stk_size' contains the number of bytes for the stack. If the stack +* units are INT32Us then, the stack contains '4 * stk_size' bytes. The stack +* units are established by the #define constant OS_STK which is CPU +* specific. 'stk_size' is 0 if called by 'OSTaskCreate()'. +* +* pext is a pointer to a user supplied memory area that is used to extend the task +* control block. This allows you to store the contents of floating-point +* registers, MMU registers or anything else you could find useful during a +* context switch. You can even assign a name to each task and store this name +* in this TCB extension. A NULL pointer is passed if called by OSTaskCreate(). +* +* opt options as passed to 'OSTaskCreateExt()' or, +* 0 if called from 'OSTaskCreate()'. +* +* Returns : OS_ERR_NONE if the call was successful +* OS_ERR_TASK_NO_MORE_TCB if there are no more free TCBs to be allocated and thus, the task cannot +* be created. +* +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +INT8U OS_TCBInit (INT8U prio, OS_STK *ptos, OS_STK *pbos, INT16U id, INT32U stk_size, void *pext, INT16U opt) +{ + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + OS_ENTER_CRITICAL(); + ptcb = OSTCBFreeList; /* Get a free TCB from the free TCB list */ + if (ptcb != (OS_TCB *)0) { + OSTCBFreeList = ptcb->OSTCBNext; /* Update pointer to free TCB list */ + OS_EXIT_CRITICAL(); + ptcb->OSTCBStkPtr = ptos; /* Load Stack pointer in TCB */ + ptcb->OSTCBPrio = prio; /* Load task priority into TCB */ + ptcb->OSTCBStat = OS_STAT_RDY; /* Task is ready to run */ + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + ptcb->OSTCBDly = 0; /* Task is not delayed */ + +#if OS_TASK_CREATE_EXT_EN > 0 + ptcb->OSTCBExtPtr = pext; /* Store pointer to TCB extension */ + ptcb->OSTCBStkSize = stk_size; /* Store stack size */ + ptcb->OSTCBStkBottom = pbos; /* Store pointer to bottom of stack */ + ptcb->OSTCBOpt = opt; /* Store task options */ + ptcb->OSTCBId = id; /* Store task ID */ +#else + pext = pext; /* Prevent compiler warning if not used */ + stk_size = stk_size; + pbos = pbos; + opt = opt; + id = id; +#endif + +#if OS_TASK_DEL_EN > 0 + ptcb->OSTCBDelReq = OS_ERR_NONE; +#endif + +#if OS_LOWEST_PRIO <= 63 + ptcb->OSTCBY = (INT8U)(prio >> 3); /* Pre-compute X, Y, BitX and BitY */ + ptcb->OSTCBX = (INT8U)(prio & 0x07); + ptcb->OSTCBBitY = (INT8U)(1 << ptcb->OSTCBY); + ptcb->OSTCBBitX = (INT8U)(1 << ptcb->OSTCBX); +#else + ptcb->OSTCBY = (INT8U)((prio >> 4) & 0xFF); /* Pre-compute X, Y, BitX and BitY */ + ptcb->OSTCBX = (INT8U) (prio & 0x0F); + ptcb->OSTCBBitY = (INT16U)(1 << ptcb->OSTCBY); + ptcb->OSTCBBitX = (INT16U)(1 << ptcb->OSTCBX); +#endif + +#if (OS_EVENT_EN) + ptcb->OSTCBEventPtr = (OS_EVENT *)0; /* Task is not pending on an event */ +#if (OS_EVENT_MULTI_EN > 0) + ptcb->OSTCBEventMultiPtr = (OS_EVENT **)0; /* Task is not pending on any events */ +#endif +#endif + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) && (OS_TASK_DEL_EN > 0) + ptcb->OSTCBFlagNode = (OS_FLAG_NODE *)0; /* Task is not pending on an event flag */ +#endif + +#if (OS_MBOX_EN > 0) || ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) + ptcb->OSTCBMsg = (void *)0; /* No message received */ +#endif + +#if OS_TASK_PROFILE_EN > 0 + ptcb->OSTCBCtxSwCtr = 0L; /* Initialize profiling variables */ + ptcb->OSTCBCyclesStart = 0L; + ptcb->OSTCBCyclesTot = 0L; + ptcb->OSTCBStkBase = (OS_STK *)0; + ptcb->OSTCBStkUsed = 0L; +#endif + +#if OS_TASK_NAME_SIZE > 1 + ptcb->OSTCBTaskName[0] = '?'; /* Unknown name at task creation */ + ptcb->OSTCBTaskName[1] = OS_ASCII_NUL; +#endif + + OSTCBInitHook(ptcb); + + OSTaskCreateHook(ptcb); /* Call user defined hook */ + + OS_ENTER_CRITICAL(); + OSTCBPrioTbl[prio] = ptcb; + ptcb->OSTCBNext = OSTCBList; /* Link into TCB chain */ + ptcb->OSTCBPrev = (OS_TCB *)0; + if (OSTCBList != (OS_TCB *)0) { + OSTCBList->OSTCBPrev = ptcb; + } + OSTCBList = ptcb; + OSRdyGrp |= ptcb->OSTCBBitY; /* Make task ready to run */ + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + OSTaskCtr++; /* Increment the #tasks counter */ + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + } + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NO_MORE_TCB); +} diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/os_dbg.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_dbg.c new file mode 100644 index 0000000..fb84a6d --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_dbg.c @@ -0,0 +1,312 @@ +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* DEBUGGER CONSTANTS +* +* (c) Copyright 1992-2007, Micrium, Weston, FL +* All Rights Reserved +* +* File : OS_DBG.C +* By : Jean J. Labrosse +* Version : V2.86 +* +* LICENSING TERMS: +* --------------- +* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. +* If you plan on using uC/OS-II in a commercial product you need to contact Micriµm to properly license +* its use in your product. We provide ALL the source code for your convenience and to help you experience +* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a +* licensing fee. +********************************************************************************************************* +*/ + +#include + +/* +********************************************************************************************************* +* DEBUG DATA +********************************************************************************************************* +*/ + +INT16U const OSDebugEn = OS_DEBUG_EN; /* Debug constants are defined below */ + +#if OS_DEBUG_EN > 0 + +INT32U const OSEndiannessTest = 0x12345678L; /* Variable to test CPU endianness */ + +INT16U const OSEventEn = OS_EVENT_EN; +INT16U const OSEventMax = OS_MAX_EVENTS; /* Number of event control blocks */ +INT16U const OSEventNameSize = OS_EVENT_NAME_SIZE; /* Size (in bytes) of event names */ +#if (OS_EVENT_EN) && (OS_MAX_EVENTS > 0) +INT16U const OSEventSize = sizeof(OS_EVENT); /* Size in Bytes of OS_EVENT */ +INT16U const OSEventTblSize = sizeof(OSEventTbl); /* Size of OSEventTbl[] in bytes */ +#else +INT16U const OSEventSize = 0; +INT16U const OSEventTblSize = 0; +#endif +INT16U const OSEventMultiEn = OS_EVENT_MULTI_EN; + + +INT16U const OSFlagEn = OS_FLAG_EN; +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) +INT16U const OSFlagGrpSize = sizeof(OS_FLAG_GRP); /* Size in Bytes of OS_FLAG_GRP */ +INT16U const OSFlagNodeSize = sizeof(OS_FLAG_NODE); /* Size in Bytes of OS_FLAG_NODE */ +INT16U const OSFlagWidth = sizeof(OS_FLAGS); /* Width (in bytes) of OS_FLAGS */ +#else +INT16U const OSFlagGrpSize = 0; +INT16U const OSFlagNodeSize = 0; +INT16U const OSFlagWidth = 0; +#endif +INT16U const OSFlagMax = OS_MAX_FLAGS; +INT16U const OSFlagNameSize = OS_FLAG_NAME_SIZE; /* Size (in bytes) of flag names */ + +INT16U const OSLowestPrio = OS_LOWEST_PRIO; + +INT16U const OSMboxEn = OS_MBOX_EN; + +INT16U const OSMemEn = OS_MEM_EN; +INT16U const OSMemMax = OS_MAX_MEM_PART; /* Number of memory partitions */ +INT16U const OSMemNameSize = OS_MEM_NAME_SIZE; /* Size (in bytes) of partition names */ +#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0) +INT16U const OSMemSize = sizeof(OS_MEM); /* Mem. Partition header sine (bytes) */ +INT16U const OSMemTblSize = sizeof(OSMemTbl); +#else +INT16U const OSMemSize = 0; +INT16U const OSMemTblSize = 0; +#endif +INT16U const OSMutexEn = OS_MUTEX_EN; + +INT16U const OSPtrSize = sizeof(void *); /* Size in Bytes of a pointer */ + +INT16U const OSQEn = OS_Q_EN; +INT16U const OSQMax = OS_MAX_QS; /* Number of queues */ +#if (OS_Q_EN > 0) && (OS_MAX_QS > 0) +INT16U const OSQSize = sizeof(OS_Q); /* Size in bytes of OS_Q structure */ +#else +INT16U const OSQSize = 0; +#endif + +INT16U const OSRdyTblSize = OS_RDY_TBL_SIZE; /* Number of bytes in the ready table */ + +INT16U const OSSemEn = OS_SEM_EN; + +INT16U const OSStkWidth = sizeof(OS_STK); /* Size in Bytes of a stack entry */ + +INT16U const OSTaskCreateEn = OS_TASK_CREATE_EN; +INT16U const OSTaskCreateExtEn = OS_TASK_CREATE_EXT_EN; +INT16U const OSTaskDelEn = OS_TASK_DEL_EN; +INT16U const OSTaskIdleStkSize = OS_TASK_IDLE_STK_SIZE; +INT16U const OSTaskProfileEn = OS_TASK_PROFILE_EN; +INT16U const OSTaskMax = OS_MAX_TASKS + OS_N_SYS_TASKS; /* Total max. number of tasks */ +INT16U const OSTaskNameSize = OS_TASK_NAME_SIZE; /* Size (in bytes) of task names */ +INT16U const OSTaskStatEn = OS_TASK_STAT_EN; +INT16U const OSTaskStatStkSize = OS_TASK_STAT_STK_SIZE; +INT16U const OSTaskStatStkChkEn = OS_TASK_STAT_STK_CHK_EN; +INT16U const OSTaskSwHookEn = OS_TASK_SW_HOOK_EN; + +INT16U const OSTCBPrioTblMax = OS_LOWEST_PRIO + 1; /* Number of entries in OSTCBPrioTbl[] */ +INT16U const OSTCBSize = sizeof(OS_TCB); /* Size in Bytes of OS_TCB */ +INT16U const OSTicksPerSec = OS_TICKS_PER_SEC; +INT16U const OSTimeTickHookEn = OS_TIME_TICK_HOOK_EN; +INT16U const OSVersionNbr = OS_VERSION; + +INT16U const OSTmrEn = OS_TMR_EN; +INT16U const OSTmrCfgMax = OS_TMR_CFG_MAX; +INT16U const OSTmrCfgNameSize = OS_TMR_CFG_NAME_SIZE; +INT16U const OSTmrCfgWheelSize = OS_TMR_CFG_WHEEL_SIZE; +INT16U const OSTmrCfgTicksPerSec = OS_TMR_CFG_TICKS_PER_SEC; + +#if (OS_TMR_EN > 0) && (OS_TMR_CFG_MAX > 0) +INT16U const OSTmrSize = sizeof(OS_TMR); +INT16U const OSTmrTblSize = sizeof(OSTmrTbl); +INT16U const OSTmrWheelSize = sizeof(OS_TMR_WHEEL); +INT16U const OSTmrWheelTblSize = sizeof(OSTmrWheelTbl); +#else +INT16U const OSTmrSize = 0; +INT16U const OSTmrTblSize = 0; +INT16U const OSTmrWheelSize = 0; +INT16U const OSTmrWheelTblSize = 0; +#endif + +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* DEBUG DATA +* TOTAL DATA SPACE (i.e. RAM) USED BY uC/OS-II +********************************************************************************************************* +*/ +#if OS_DEBUG_EN > 0 + +INT16U const OSDataSize = sizeof(OSCtxSwCtr) +#if (OS_EVENT_EN) && (OS_MAX_EVENTS > 0) + + sizeof(OSEventFreeList) + + sizeof(OSEventTbl) +#endif +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) + + sizeof(OSFlagTbl) + + sizeof(OSFlagFreeList) +#endif +#if OS_TASK_STAT_EN > 0 + + sizeof(OSCPUUsage) + + sizeof(OSIdleCtrMax) + + sizeof(OSIdleCtrRun) + + sizeof(OSStatRdy) + + sizeof(OSTaskStatStk) +#endif +#if OS_TICK_STEP_EN > 0 + + sizeof(OSTickStepState) +#endif +#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0) + + sizeof(OSMemFreeList) + + sizeof(OSMemTbl) +#endif +#if (OS_Q_EN > 0) && (OS_MAX_QS > 0) + + sizeof(OSQFreeList) + + sizeof(OSQTbl) +#endif +#if OS_TIME_GET_SET_EN > 0 + + sizeof(OSTime) +#endif +#if (OS_TMR_EN > 0) && (OS_TMR_CFG_MAX > 0) + + sizeof(OSTmrFree) + + sizeof(OSTmrUsed) + + sizeof(OSTmrTime) + + sizeof(OSTmrSem) + + sizeof(OSTmrSemSignal) + + sizeof(OSTmrTbl) + + sizeof(OSTmrFreeList) + + sizeof(OSTmrTaskStk) + + sizeof(OSTmrWheelTbl) +#endif + + sizeof(OSIntNesting) + + sizeof(OSLockNesting) + + sizeof(OSPrioCur) + + sizeof(OSPrioHighRdy) + + sizeof(OSRdyGrp) + + sizeof(OSRdyTbl) + + sizeof(OSRunning) + + sizeof(OSTaskCtr) + + sizeof(OSIdleCtr) + + sizeof(OSTaskIdleStk) + + sizeof(OSTCBCur) + + sizeof(OSTCBFreeList) + + sizeof(OSTCBHighRdy) + + sizeof(OSTCBList) + + sizeof(OSTCBPrioTbl) + + sizeof(OSTCBTbl); + +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* OS DEBUG INITIALIZATION +* +* Description: This function is used to make sure that debug variables that are unused in the application +* are not optimized away. This function might not be necessary for all compilers. In this +* case, you should simply DELETE the code in this function while still leaving the declaration +* of the function itself. +* +* Arguments : none +* +* Returns : none +* +* Note(s) : (1) This code doesn't do anything, it simply prevents the compiler from optimizing out +* the 'const' variables which are declared in this file. +* (2) You may decide to 'compile out' the code (by using #if 0/#endif) INSIDE the function +* if your compiler DOES NOT optimize out the 'const' variables above. +********************************************************************************************************* +*/ + +#if OS_DEBUG_EN > 0 +void OSDebugInit (void) +{ + void *ptemp; + + + ptemp = (void *)&OSDebugEn; + + ptemp = (void *)&OSEndiannessTest; + + ptemp = (void *)&OSEventMax; + ptemp = (void *)&OSEventNameSize; + ptemp = (void *)&OSEventEn; + ptemp = (void *)&OSEventSize; + ptemp = (void *)&OSEventTblSize; + ptemp = (void *)&OSEventMultiEn; + + ptemp = (void *)&OSFlagEn; + ptemp = (void *)&OSFlagGrpSize; + ptemp = (void *)&OSFlagNodeSize; + ptemp = (void *)&OSFlagWidth; + ptemp = (void *)&OSFlagMax; + ptemp = (void *)&OSFlagNameSize; + + ptemp = (void *)&OSLowestPrio; + + ptemp = (void *)&OSMboxEn; + + ptemp = (void *)&OSMemEn; + ptemp = (void *)&OSMemMax; + ptemp = (void *)&OSMemNameSize; + ptemp = (void *)&OSMemSize; + ptemp = (void *)&OSMemTblSize; + + ptemp = (void *)&OSMutexEn; + + ptemp = (void *)&OSPtrSize; + + ptemp = (void *)&OSQEn; + ptemp = (void *)&OSQMax; + ptemp = (void *)&OSQSize; + + ptemp = (void *)&OSRdyTblSize; + + ptemp = (void *)&OSSemEn; + + ptemp = (void *)&OSStkWidth; + + ptemp = (void *)&OSTaskCreateEn; + ptemp = (void *)&OSTaskCreateExtEn; + ptemp = (void *)&OSTaskDelEn; + ptemp = (void *)&OSTaskIdleStkSize; + ptemp = (void *)&OSTaskProfileEn; + ptemp = (void *)&OSTaskMax; + ptemp = (void *)&OSTaskNameSize; + ptemp = (void *)&OSTaskStatEn; + ptemp = (void *)&OSTaskStatStkSize; + ptemp = (void *)&OSTaskStatStkChkEn; + ptemp = (void *)&OSTaskSwHookEn; + + ptemp = (void *)&OSTCBPrioTblMax; + ptemp = (void *)&OSTCBSize; + + ptemp = (void *)&OSTicksPerSec; + ptemp = (void *)&OSTimeTickHookEn; + +#if OS_TMR_EN > 0 + ptemp = (void *)&OSTmrTbl[0]; + ptemp = (void *)&OSTmrWheelTbl[0]; + + ptemp = (void *)&OSTmrEn; + ptemp = (void *)&OSTmrCfgMax; + ptemp = (void *)&OSTmrCfgNameSize; + ptemp = (void *)&OSTmrCfgWheelSize; + ptemp = (void *)&OSTmrCfgTicksPerSec; + ptemp = (void *)&OSTmrSize; + ptemp = (void *)&OSTmrTblSize; + + ptemp = (void *)&OSTmrWheelSize; + ptemp = (void *)&OSTmrWheelTblSize; +#endif + + ptemp = (void *)&OSVersionNbr; + + ptemp = (void *)&OSDataSize; + + ptemp = ptemp; /* Prevent compiler warning for 'ptemp' not being used! */ +} +#endif diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/os_flag.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_flag.c new file mode 100644 index 0000000..b77ef1d --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_flag.c @@ -0,0 +1,1174 @@ +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* EVENT FLAG MANAGEMENT +* +* (c) Copyright 1992-2007, Micrium, Weston, FL +* All Rights Reserved +* +* File : OS_FLAG.C +* By : Jean J. Labrosse +* Version : V2.86 +* +* LICENSING TERMS: +* --------------- +* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. +* If you plan on using uC/OS-II in a commercial product you need to contact Micriµm to properly license +* its use in your product. We provide ALL the source code for your convenience and to help you experience +* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a +* licensing fee. +********************************************************************************************************* +*/ + +#ifndef OS_MASTER_FILE +#include +#endif + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) +/* +********************************************************************************************************* +* LOCAL PROTOTYPES +********************************************************************************************************* +*/ + +static void OS_FlagBlock(OS_FLAG_GRP *pgrp, OS_FLAG_NODE *pnode, OS_FLAGS flags, INT8U wait_type, INT16U timeout); +static BOOLEAN OS_FlagTaskRdy(OS_FLAG_NODE *pnode, OS_FLAGS flags_rdy); + +/*$PAGE*/ +/* +********************************************************************************************************* +* CHECK THE STATUS OF FLAGS IN AN EVENT FLAG GROUP +* +* Description: This function is called to check the status of a combination of bits to be set or cleared +* in an event flag group. Your application can check for ANY bit to be set/cleared or ALL +* bits to be set/cleared. +* +* This call does not block if the desired flags are not present. +* +* Arguments : pgrp is a pointer to the desired event flag group. +* +* flags Is a bit pattern indicating which bit(s) (i.e. flags) you wish to check. +* The bits you want are specified by setting the corresponding bits in +* 'flags'. e.g. if your application wants to wait for bits 0 and 1 then +* 'flags' would contain 0x03. +* +* wait_type specifies whether you want ALL bits to be set/cleared or ANY of the bits +* to be set/cleared. +* You can specify the following argument: +* +* OS_FLAG_WAIT_CLR_ALL You will check ALL bits in 'flags' to be clear (0) +* OS_FLAG_WAIT_CLR_ANY You will check ANY bit in 'flags' to be clear (0) +* OS_FLAG_WAIT_SET_ALL You will check ALL bits in 'flags' to be set (1) +* OS_FLAG_WAIT_SET_ANY You will check ANY bit in 'flags' to be set (1) +* +* NOTE: Add OS_FLAG_CONSUME if you want the event flag to be 'consumed' by +* the call. Example, to wait for any flag in a group AND then clear +* the flags that are present, set 'wait_type' to: +* +* OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME +* +* perr is a pointer to an error code and can be: +* OS_ERR_NONE No error +* OS_ERR_EVENT_TYPE You are not pointing to an event flag group +* OS_ERR_FLAG_WAIT_TYPE You didn't specify a proper 'wait_type' argument. +* OS_ERR_FLAG_INVALID_PGRP You passed a NULL pointer instead of the event flag +* group handle. +* OS_ERR_FLAG_NOT_RDY The desired flags you are waiting for are not +* available. +* +* Returns : The flags in the event flag group that made the task ready or, 0 if a timeout or an error +* occurred. +* +* Called from: Task or ISR +* +* Note(s) : 1) IMPORTANT, the behavior of this function has changed from PREVIOUS versions. The +* function NOW returns the flags that were ready INSTEAD of the current state of the +* event flags. +********************************************************************************************************* +*/ + +#if OS_FLAG_ACCEPT_EN > 0 +OS_FLAGS OSFlagAccept (OS_FLAG_GRP *pgrp, OS_FLAGS flags, INT8U wait_type, INT8U *perr) +{ + OS_FLAGS flags_rdy; + INT8U result; + BOOLEAN consume; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return ((OS_FLAGS)0); + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + *perr = OS_ERR_FLAG_INVALID_PGRP; + return ((OS_FLAGS)0); + } +#endif + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return ((OS_FLAGS)0); + } + result = (INT8U)(wait_type & OS_FLAG_CONSUME); + if (result != (INT8U)0) { /* See if we need to consume the flags */ + wait_type &= ~OS_FLAG_CONSUME; + consume = OS_TRUE; + } else { + consume = OS_FALSE; + } +/*$PAGE*/ + *perr = OS_ERR_NONE; /* Assume NO error until proven otherwise. */ + OS_ENTER_CRITICAL(); + switch (wait_type) { + case OS_FLAG_WAIT_SET_ALL: /* See if all required flags are set */ + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + if (flags_rdy == flags) { /* Must match ALL the bits that we want */ + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + pgrp->OSFlagFlags &= ~flags_rdy; /* Clear ONLY the flags that we wanted */ + } + } else { + *perr = OS_ERR_FLAG_NOT_RDY; + } + OS_EXIT_CRITICAL(); + break; + + case OS_FLAG_WAIT_SET_ANY: + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + if (flags_rdy != (OS_FLAGS)0) { /* See if any flag set */ + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + pgrp->OSFlagFlags &= ~flags_rdy; /* Clear ONLY the flags that we got */ + } + } else { + *perr = OS_ERR_FLAG_NOT_RDY; + } + OS_EXIT_CRITICAL(); + break; + +#if OS_FLAG_WAIT_CLR_EN > 0 + case OS_FLAG_WAIT_CLR_ALL: /* See if all required flags are cleared */ + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + if (flags_rdy == flags) { /* Must match ALL the bits that we want */ + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + pgrp->OSFlagFlags |= flags_rdy; /* Set ONLY the flags that we wanted */ + } + } else { + *perr = OS_ERR_FLAG_NOT_RDY; + } + OS_EXIT_CRITICAL(); + break; + + case OS_FLAG_WAIT_CLR_ANY: + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + if (flags_rdy != (OS_FLAGS)0) { /* See if any flag cleared */ + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + pgrp->OSFlagFlags |= flags_rdy; /* Set ONLY the flags that we got */ + } + } else { + *perr = OS_ERR_FLAG_NOT_RDY; + } + OS_EXIT_CRITICAL(); + break; +#endif + + default: + OS_EXIT_CRITICAL(); + flags_rdy = (OS_FLAGS)0; + *perr = OS_ERR_FLAG_WAIT_TYPE; + break; + } + return (flags_rdy); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* CREATE AN EVENT FLAG +* +* Description: This function is called to create an event flag group. +* +* Arguments : flags Contains the initial value to store in the event flag group. +* +* perr is a pointer to an error code which will be returned to your application: +* OS_ERR_NONE if the call was successful. +* OS_ERR_CREATE_ISR if you attempted to create an Event Flag from an +* ISR. +* OS_ERR_FLAG_GRP_DEPLETED if there are no more event flag groups +* +* Returns : A pointer to an event flag group or a NULL pointer if no more groups are available. +* +* Called from: Task ONLY +********************************************************************************************************* +*/ + +OS_FLAG_GRP *OSFlagCreate (OS_FLAGS flags, INT8U *perr) +{ + OS_FLAG_GRP *pgrp; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return ((OS_FLAG_GRP *)0); + } +#endif + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_CREATE_ISR; /* ... can't CREATE from an ISR */ + return ((OS_FLAG_GRP *)0); + } + OS_ENTER_CRITICAL(); + pgrp = OSFlagFreeList; /* Get next free event flag */ + if (pgrp != (OS_FLAG_GRP *)0) { /* See if we have event flag groups available */ + /* Adjust free list */ + OSFlagFreeList = (OS_FLAG_GRP *)OSFlagFreeList->OSFlagWaitList; + pgrp->OSFlagType = OS_EVENT_TYPE_FLAG; /* Set to event flag group type */ + pgrp->OSFlagFlags = flags; /* Set to desired initial value */ + pgrp->OSFlagWaitList = (void *)0; /* Clear list of tasks waiting on flags */ +#if OS_FLAG_NAME_SIZE > 1 + pgrp->OSFlagName[0] = '?'; + pgrp->OSFlagName[1] = OS_ASCII_NUL; +#endif + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_FLAG_GRP_DEPLETED; + } + return (pgrp); /* Return pointer to event flag group */ +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* DELETE AN EVENT FLAG GROUP +* +* Description: This function deletes an event flag group and readies all tasks pending on the event flag +* group. +* +* Arguments : pgrp is a pointer to the desired event flag group. +* +* opt determines delete options as follows: +* opt == OS_DEL_NO_PEND Deletes the event flag group ONLY if no task pending +* opt == OS_DEL_ALWAYS Deletes the event flag group even if tasks are +* waiting. In this case, all the tasks pending will be +* readied. +* +* perr is a pointer to an error code that can contain one of the following values: +* OS_ERR_NONE The call was successful and the event flag group was +* deleted +* OS_ERR_DEL_ISR If you attempted to delete the event flag group from +* an ISR +* OS_ERR_FLAG_INVALID_PGRP If 'pgrp' is a NULL pointer. +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to an event flag group +* OS_ERR_INVALID_OPT An invalid option was specified +* OS_ERR_TASK_WAITING One or more tasks were waiting on the event flag +* group. +* +* Returns : pgrp upon error +* (OS_EVENT *)0 if the event flag group was successfully deleted. +* +* Note(s) : 1) This function must be used with care. Tasks that would normally expect the presence of +* the event flag group MUST check the return code of OSFlagAccept() and OSFlagPend(). +* 2) This call can potentially disable interrupts for a long time. The interrupt disable +* time is directly proportional to the number of tasks waiting on the event flag group. +********************************************************************************************************* +*/ + +#if OS_FLAG_DEL_EN > 0 +OS_FLAG_GRP *OSFlagDel (OS_FLAG_GRP *pgrp, INT8U opt, INT8U *perr) +{ + BOOLEAN tasks_waiting; + OS_FLAG_NODE *pnode; + OS_FLAG_GRP *pgrp_return; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (pgrp); + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + *perr = OS_ERR_FLAG_INVALID_PGRP; + return (pgrp); + } +#endif + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_DEL_ISR; /* ... can't DELETE from an ISR */ + return (pgrp); + } + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event group type */ + *perr = OS_ERR_EVENT_TYPE; + return (pgrp); + } + OS_ENTER_CRITICAL(); + if (pgrp->OSFlagWaitList != (void *)0) { /* See if any tasks waiting on event flags */ + tasks_waiting = OS_TRUE; /* Yes */ + } else { + tasks_waiting = OS_FALSE; /* No */ + } + switch (opt) { + case OS_DEL_NO_PEND: /* Delete group if no task waiting */ + if (tasks_waiting == OS_FALSE) { +#if OS_FLAG_NAME_SIZE > 1 + pgrp->OSFlagName[0] = '?'; /* Unknown name */ + pgrp->OSFlagName[1] = OS_ASCII_NUL; +#endif + pgrp->OSFlagType = OS_EVENT_TYPE_UNUSED; + pgrp->OSFlagWaitList = (void *)OSFlagFreeList; /* Return group to free list */ + pgrp->OSFlagFlags = (OS_FLAGS)0; + OSFlagFreeList = pgrp; + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + pgrp_return = (OS_FLAG_GRP *)0; /* Event Flag Group has been deleted */ + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_WAITING; + pgrp_return = pgrp; + } + break; + + case OS_DEL_ALWAYS: /* Always delete the event flag group */ + pnode = (OS_FLAG_NODE *)pgrp->OSFlagWaitList; + while (pnode != (OS_FLAG_NODE *)0) { /* Ready ALL tasks waiting for flags */ + (void)OS_FlagTaskRdy(pnode, (OS_FLAGS)0); + pnode = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; + } +#if OS_FLAG_NAME_SIZE > 1 + pgrp->OSFlagName[0] = '?'; /* Unknown name */ + pgrp->OSFlagName[1] = OS_ASCII_NUL; +#endif + pgrp->OSFlagType = OS_EVENT_TYPE_UNUSED; + pgrp->OSFlagWaitList = (void *)OSFlagFreeList;/* Return group to free list */ + pgrp->OSFlagFlags = (OS_FLAGS)0; + OSFlagFreeList = pgrp; + OS_EXIT_CRITICAL(); + if (tasks_waiting == OS_TRUE) { /* Reschedule only if task(s) were waiting */ + OS_Sched(); /* Find highest priority task ready to run */ + } + *perr = OS_ERR_NONE; + pgrp_return = (OS_FLAG_GRP *)0; /* Event Flag Group has been deleted */ + break; + + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_INVALID_OPT; + pgrp_return = pgrp; + break; + } + return (pgrp_return); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* GET THE NAME OF AN EVENT FLAG GROUP +* +* Description: This function is used to obtain the name assigned to an event flag group +* +* Arguments : pgrp is a pointer to the event flag group. +* +* pname is a pointer to an ASCII string that will receive the name of the event flag +* group. The string must be able to hold at least OS_FLAG_NAME_SIZE characters. +* +* perr is a pointer to an error code that can contain one of the following values: +* +* OS_ERR_NONE if the requested task is resumed +* OS_ERR_EVENT_TYPE if 'pevent' is not pointing to an event flag group +* OS_ERR_PNAME_NULL You passed a NULL pointer for 'pname' +* OS_ERR_FLAG_INVALID_PGRP if you passed a NULL pointer for 'pgrp' +* OS_ERR_NAME_GET_ISR if you called this function from an ISR +* +* Returns : The length of the string or 0 if the 'pgrp' is a NULL pointer. +********************************************************************************************************* +*/ + +#if OS_FLAG_NAME_SIZE > 1 +INT8U OSFlagNameGet (OS_FLAG_GRP *pgrp, INT8U *pname, INT8U *perr) +{ + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (0); + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Is 'pgrp' a NULL pointer? */ + *perr = OS_ERR_FLAG_INVALID_PGRP; + return (0); + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + *perr = OS_ERR_PNAME_NULL; + return (0); + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_NAME_GET_ISR; + return (0); + } + OS_ENTER_CRITICAL(); + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_EVENT_TYPE; + return (0); + } + len = OS_StrCopy(pname, pgrp->OSFlagName); /* Copy name from OS_FLAG_GRP */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (len); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* ASSIGN A NAME TO AN EVENT FLAG GROUP +* +* Description: This function assigns a name to an event flag group. +* +* Arguments : pgrp is a pointer to the event flag group. +* +* pname is a pointer to an ASCII string that will be used as the name of the event flag +* group. The string must be able to hold at least OS_FLAG_NAME_SIZE characters. +* +* perr is a pointer to an error code that can contain one of the following values: +* +* OS_ERR_NONE if the requested task is resumed +* OS_ERR_EVENT_TYPE if 'pevent' is not pointing to an event flag group +* OS_ERR_PNAME_NULL You passed a NULL pointer for 'pname' +* OS_ERR_FLAG_INVALID_PGRP if you passed a NULL pointer for 'pgrp' +* OS_ERR_NAME_SET_ISR if you called this function from an ISR +* +* Returns : None +********************************************************************************************************* +*/ + +#if OS_FLAG_NAME_SIZE > 1 +void OSFlagNameSet (OS_FLAG_GRP *pgrp, INT8U *pname, INT8U *perr) +{ + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return; + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Is 'pgrp' a NULL pointer? */ + *perr = OS_ERR_FLAG_INVALID_PGRP; + return; + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + *perr = OS_ERR_PNAME_NULL; + return; + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_NAME_SET_ISR; + return; + } + OS_ENTER_CRITICAL(); + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_EVENT_TYPE; + return; + } + len = OS_StrLen(pname); /* Can we fit the string in the storage area? */ + if (len > (OS_FLAG_NAME_SIZE - 1)) { /* No */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_FLAG_NAME_TOO_LONG; + return; + } + (void)OS_StrCopy(pgrp->OSFlagName, pname); /* Yes, copy name from OS_FLAG_GRP */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return; +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* WAIT ON AN EVENT FLAG GROUP +* +* Description: This function is called to wait for a combination of bits to be set in an event flag +* group. Your application can wait for ANY bit to be set or ALL bits to be set. +* +* Arguments : pgrp is a pointer to the desired event flag group. +* +* flags Is a bit pattern indicating which bit(s) (i.e. flags) you wish to wait for. +* The bits you want are specified by setting the corresponding bits in +* 'flags'. e.g. if your application wants to wait for bits 0 and 1 then +* 'flags' would contain 0x03. +* +* wait_type specifies whether you want ALL bits to be set or ANY of the bits to be set. +* You can specify the following argument: +* +* OS_FLAG_WAIT_CLR_ALL You will wait for ALL bits in 'mask' to be clear (0) +* OS_FLAG_WAIT_SET_ALL You will wait for ALL bits in 'mask' to be set (1) +* OS_FLAG_WAIT_CLR_ANY You will wait for ANY bit in 'mask' to be clear (0) +* OS_FLAG_WAIT_SET_ANY You will wait for ANY bit in 'mask' to be set (1) +* +* NOTE: Add OS_FLAG_CONSUME if you want the event flag to be 'consumed' by +* the call. Example, to wait for any flag in a group AND then clear +* the flags that are present, set 'wait_type' to: +* +* OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME +* +* timeout is an optional timeout (in clock ticks) that your task will wait for the +* desired bit combination. If you specify 0, however, your task will wait +* forever at the specified event flag group or, until a message arrives. +* +* perr is a pointer to an error code and can be: +* OS_ERR_NONE The desired bits have been set within the specified +* 'timeout'. +* OS_ERR_PEND_ISR If you tried to PEND from an ISR +* OS_ERR_FLAG_INVALID_PGRP If 'pgrp' is a NULL pointer. +* OS_ERR_EVENT_TYPE You are not pointing to an event flag group +* OS_ERR_TIMEOUT The bit(s) have not been set in the specified +* 'timeout'. +* OS_ERR_PEND_ABORT The wait on the flag was aborted. +* OS_ERR_FLAG_WAIT_TYPE You didn't specify a proper 'wait_type' argument. +* +* Returns : The flags in the event flag group that made the task ready or, 0 if a timeout or an error +* occurred. +* +* Called from: Task ONLY +* +* Note(s) : 1) IMPORTANT, the behavior of this function has changed from PREVIOUS versions. The +* function NOW returns the flags that were ready INSTEAD of the current state of the +* event flags. +********************************************************************************************************* +*/ + +OS_FLAGS OSFlagPend (OS_FLAG_GRP *pgrp, OS_FLAGS flags, INT8U wait_type, INT16U timeout, INT8U *perr) +{ + OS_FLAG_NODE node; + OS_FLAGS flags_rdy; + INT8U result; + INT8U pend_stat; + BOOLEAN consume; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return ((OS_FLAGS)0); + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + *perr = OS_ERR_FLAG_INVALID_PGRP; + return ((OS_FLAGS)0); + } +#endif + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + return ((OS_FLAGS)0); + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + return ((OS_FLAGS)0); + } + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return ((OS_FLAGS)0); + } + result = (INT8U)(wait_type & OS_FLAG_CONSUME); + if (result != (INT8U)0) { /* See if we need to consume the flags */ + wait_type &= ~(INT8U)OS_FLAG_CONSUME; + consume = OS_TRUE; + } else { + consume = OS_FALSE; + } +/*$PAGE*/ + OS_ENTER_CRITICAL(); + switch (wait_type) { + case OS_FLAG_WAIT_SET_ALL: /* See if all required flags are set */ + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + if (flags_rdy == flags) { /* Must match ALL the bits that we want */ + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + pgrp->OSFlagFlags &= ~flags_rdy; /* Clear ONLY the flags that we wanted */ + } + OSTCBCur->OSTCBFlagsRdy = flags_rdy; /* Save flags that were ready */ + OS_EXIT_CRITICAL(); /* Yes, condition met, return to caller */ + *perr = OS_ERR_NONE; + return (flags_rdy); + } else { /* Block task until events occur or timeout */ + OS_FlagBlock(pgrp, &node, flags, wait_type, timeout); + OS_EXIT_CRITICAL(); + } + break; + + case OS_FLAG_WAIT_SET_ANY: + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + if (flags_rdy != (OS_FLAGS)0) { /* See if any flag set */ + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + pgrp->OSFlagFlags &= ~flags_rdy; /* Clear ONLY the flags that we got */ + } + OSTCBCur->OSTCBFlagsRdy = flags_rdy; /* Save flags that were ready */ + OS_EXIT_CRITICAL(); /* Yes, condition met, return to caller */ + *perr = OS_ERR_NONE; + return (flags_rdy); + } else { /* Block task until events occur or timeout */ + OS_FlagBlock(pgrp, &node, flags, wait_type, timeout); + OS_EXIT_CRITICAL(); + } + break; + +#if OS_FLAG_WAIT_CLR_EN > 0 + case OS_FLAG_WAIT_CLR_ALL: /* See if all required flags are cleared */ + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + if (flags_rdy == flags) { /* Must match ALL the bits that we want */ + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + pgrp->OSFlagFlags |= flags_rdy; /* Set ONLY the flags that we wanted */ + } + OSTCBCur->OSTCBFlagsRdy = flags_rdy; /* Save flags that were ready */ + OS_EXIT_CRITICAL(); /* Yes, condition met, return to caller */ + *perr = OS_ERR_NONE; + return (flags_rdy); + } else { /* Block task until events occur or timeout */ + OS_FlagBlock(pgrp, &node, flags, wait_type, timeout); + OS_EXIT_CRITICAL(); + } + break; + + case OS_FLAG_WAIT_CLR_ANY: + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + if (flags_rdy != (OS_FLAGS)0) { /* See if any flag cleared */ + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + pgrp->OSFlagFlags |= flags_rdy; /* Set ONLY the flags that we got */ + } + OSTCBCur->OSTCBFlagsRdy = flags_rdy; /* Save flags that were ready */ + OS_EXIT_CRITICAL(); /* Yes, condition met, return to caller */ + *perr = OS_ERR_NONE; + return (flags_rdy); + } else { /* Block task until events occur or timeout */ + OS_FlagBlock(pgrp, &node, flags, wait_type, timeout); + OS_EXIT_CRITICAL(); + } + break; +#endif + + default: + OS_EXIT_CRITICAL(); + flags_rdy = (OS_FLAGS)0; + *perr = OS_ERR_FLAG_WAIT_TYPE; + return (flags_rdy); + } +/*$PAGE*/ + OS_Sched(); /* Find next HPT ready to run */ + OS_ENTER_CRITICAL(); + if (OSTCBCur->OSTCBStatPend != OS_STAT_PEND_OK) { /* Have we timed-out or aborted? */ + pend_stat = OSTCBCur->OSTCBStatPend; + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + OS_FlagUnlink(&node); + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Yes, make task ready-to-run */ + OS_EXIT_CRITICAL(); + flags_rdy = (OS_FLAGS)0; + switch (pend_stat) { + case OS_STAT_PEND_ABORT: + *perr = OS_ERR_PEND_ABORT; /* Indicate that we aborted waiting */ + break; + + case OS_STAT_PEND_TO: + default: + *perr = OS_ERR_TIMEOUT; /* Indicate that we timed-out waiting */ + break; + } + return (flags_rdy); + } + flags_rdy = OSTCBCur->OSTCBFlagsRdy; + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + switch (wait_type) { + case OS_FLAG_WAIT_SET_ALL: + case OS_FLAG_WAIT_SET_ANY: /* Clear ONLY the flags we got */ + pgrp->OSFlagFlags &= ~flags_rdy; + break; + +#if OS_FLAG_WAIT_CLR_EN > 0 + case OS_FLAG_WAIT_CLR_ALL: + case OS_FLAG_WAIT_CLR_ANY: /* Set ONLY the flags we got */ + pgrp->OSFlagFlags |= flags_rdy; + break; +#endif + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_FLAG_WAIT_TYPE; + return ((OS_FLAGS)0); + } + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; /* Event(s) must have occurred */ + return (flags_rdy); +} +/*$PAGE*/ +/* +********************************************************************************************************* +* GET FLAGS WHO CAUSED TASK TO BECOME READY +* +* Description: This function is called to obtain the flags that caused the task to become ready to run. +* In other words, this function allows you to tell "Who done it!". +* +* Arguments : None +* +* Returns : The flags that caused the task to be ready. +* +* Called from: Task ONLY +********************************************************************************************************* +*/ + +OS_FLAGS OSFlagPendGetFlagsRdy (void) +{ + OS_FLAGS flags; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + OS_ENTER_CRITICAL(); + flags = OSTCBCur->OSTCBFlagsRdy; + OS_EXIT_CRITICAL(); + return (flags); +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* POST EVENT FLAG BIT(S) +* +* Description: This function is called to set or clear some bits in an event flag group. The bits to +* set or clear are specified by a 'bit mask'. +* +* Arguments : pgrp is a pointer to the desired event flag group. +* +* flags If 'opt' (see below) is OS_FLAG_SET, each bit that is set in 'flags' will +* set the corresponding bit in the event flag group. e.g. to set bits 0, 4 +* and 5 you would set 'flags' to: +* +* 0x31 (note, bit 0 is least significant bit) +* +* If 'opt' (see below) is OS_FLAG_CLR, each bit that is set in 'flags' will +* CLEAR the corresponding bit in the event flag group. e.g. to clear bits 0, +* 4 and 5 you would specify 'flags' as: +* +* 0x31 (note, bit 0 is least significant bit) +* +* opt indicates whether the flags will be: +* set (OS_FLAG_SET) or +* cleared (OS_FLAG_CLR) +* +* perr is a pointer to an error code and can be: +* OS_ERR_NONE The call was successfull +* OS_ERR_FLAG_INVALID_PGRP You passed a NULL pointer +* OS_ERR_EVENT_TYPE You are not pointing to an event flag group +* OS_ERR_FLAG_INVALID_OPT You specified an invalid option +* +* Returns : the new value of the event flags bits that are still set. +* +* Called From: Task or ISR +* +* WARNING(s) : 1) The execution time of this function depends on the number of tasks waiting on the event +* flag group. +* 2) The amount of time interrupts are DISABLED depends on the number of tasks waiting on +* the event flag group. +********************************************************************************************************* +*/ +OS_FLAGS OSFlagPost (OS_FLAG_GRP *pgrp, OS_FLAGS flags, INT8U opt, INT8U *perr) +{ + OS_FLAG_NODE *pnode; + BOOLEAN sched; + OS_FLAGS flags_cur; + OS_FLAGS flags_rdy; + BOOLEAN rdy; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return ((OS_FLAGS)0); + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + *perr = OS_ERR_FLAG_INVALID_PGRP; + return ((OS_FLAGS)0); + } +#endif + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Make sure we are pointing to an event flag grp */ + *perr = OS_ERR_EVENT_TYPE; + return ((OS_FLAGS)0); + } +/*$PAGE*/ + OS_ENTER_CRITICAL(); + switch (opt) { + case OS_FLAG_CLR: + pgrp->OSFlagFlags &= ~flags; /* Clear the flags specified in the group */ + break; + + case OS_FLAG_SET: + pgrp->OSFlagFlags |= flags; /* Set the flags specified in the group */ + break; + + default: + OS_EXIT_CRITICAL(); /* INVALID option */ + *perr = OS_ERR_FLAG_INVALID_OPT; + return ((OS_FLAGS)0); + } + sched = OS_FALSE; /* Indicate that we don't need rescheduling */ + pnode = (OS_FLAG_NODE *)pgrp->OSFlagWaitList; + while (pnode != (OS_FLAG_NODE *)0) { /* Go through all tasks waiting on event flag(s) */ + switch (pnode->OSFlagNodeWaitType) { + case OS_FLAG_WAIT_SET_ALL: /* See if all req. flags are set for current node */ + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & pnode->OSFlagNodeFlags); + if (flags_rdy == pnode->OSFlagNodeFlags) { + rdy = OS_FlagTaskRdy(pnode, flags_rdy); /* Make task RTR, event(s) Rx'd */ + if (rdy == OS_TRUE) { + sched = OS_TRUE; /* When done we will reschedule */ + } + } + break; + + case OS_FLAG_WAIT_SET_ANY: /* See if any flag set */ + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & pnode->OSFlagNodeFlags); + if (flags_rdy != (OS_FLAGS)0) { + rdy = OS_FlagTaskRdy(pnode, flags_rdy); /* Make task RTR, event(s) Rx'd */ + if (rdy == OS_TRUE) { + sched = OS_TRUE; /* When done we will reschedule */ + } + } + break; + +#if OS_FLAG_WAIT_CLR_EN > 0 + case OS_FLAG_WAIT_CLR_ALL: /* See if all req. flags are set for current node */ + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & pnode->OSFlagNodeFlags); + if (flags_rdy == pnode->OSFlagNodeFlags) { + rdy = OS_FlagTaskRdy(pnode, flags_rdy); /* Make task RTR, event(s) Rx'd */ + if (rdy == OS_TRUE) { + sched = OS_TRUE; /* When done we will reschedule */ + } + } + break; + + case OS_FLAG_WAIT_CLR_ANY: /* See if any flag set */ + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & pnode->OSFlagNodeFlags); + if (flags_rdy != (OS_FLAGS)0) { + rdy = OS_FlagTaskRdy(pnode, flags_rdy); /* Make task RTR, event(s) Rx'd */ + if (rdy == OS_TRUE) { + sched = OS_TRUE; /* When done we will reschedule */ + } + } + break; +#endif + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_FLAG_WAIT_TYPE; + return ((OS_FLAGS)0); + } + pnode = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; /* Point to next task waiting for event flag(s) */ + } + OS_EXIT_CRITICAL(); + if (sched == OS_TRUE) { + OS_Sched(); + } + OS_ENTER_CRITICAL(); + flags_cur = pgrp->OSFlagFlags; + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (flags_cur); +} +/*$PAGE*/ +/* +********************************************************************************************************* +* QUERY EVENT FLAG +* +* Description: This function is used to check the value of the event flag group. +* +* Arguments : pgrp is a pointer to the desired event flag group. +* +* perr is a pointer to an error code returned to the called: +* OS_ERR_NONE The call was successfull +* OS_ERR_FLAG_INVALID_PGRP You passed a NULL pointer +* OS_ERR_EVENT_TYPE You are not pointing to an event flag group +* +* Returns : The current value of the event flag group. +* +* Called From: Task or ISR +********************************************************************************************************* +*/ + +#if OS_FLAG_QUERY_EN > 0 +OS_FLAGS OSFlagQuery (OS_FLAG_GRP *pgrp, INT8U *perr) +{ + OS_FLAGS flags; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return ((OS_FLAGS)0); + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + *perr = OS_ERR_FLAG_INVALID_PGRP; + return ((OS_FLAGS)0); + } +#endif + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return ((OS_FLAGS)0); + } + OS_ENTER_CRITICAL(); + flags = pgrp->OSFlagFlags; + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (flags); /* Return the current value of the event flags */ +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* SUSPEND TASK UNTIL EVENT FLAG(s) RECEIVED OR TIMEOUT OCCURS +* +* Description: This function is internal to uC/OS-II and is used to put a task to sleep until the desired +* event flag bit(s) are set. +* +* Arguments : pgrp is a pointer to the desired event flag group. +* +* pnode is a pointer to a structure which contains data about the task waiting for +* event flag bit(s) to be set. +* +* flags Is a bit pattern indicating which bit(s) (i.e. flags) you wish to check. +* The bits you want are specified by setting the corresponding bits in +* 'flags'. e.g. if your application wants to wait for bits 0 and 1 then +* 'flags' would contain 0x03. +* +* wait_type specifies whether you want ALL bits to be set/cleared or ANY of the bits +* to be set/cleared. +* You can specify the following argument: +* +* OS_FLAG_WAIT_CLR_ALL You will check ALL bits in 'mask' to be clear (0) +* OS_FLAG_WAIT_CLR_ANY You will check ANY bit in 'mask' to be clear (0) +* OS_FLAG_WAIT_SET_ALL You will check ALL bits in 'mask' to be set (1) +* OS_FLAG_WAIT_SET_ANY You will check ANY bit in 'mask' to be set (1) +* +* timeout is the desired amount of time that the task will wait for the event flag +* bit(s) to be set. +* +* Returns : none +* +* Called by : OSFlagPend() OS_FLAG.C +* +* Note(s) : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +static void OS_FlagBlock (OS_FLAG_GRP *pgrp, OS_FLAG_NODE *pnode, OS_FLAGS flags, INT8U wait_type, INT16U timeout) +{ + OS_FLAG_NODE *pnode_next; + INT8U y; + + + OSTCBCur->OSTCBStat |= OS_STAT_FLAG; + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + OSTCBCur->OSTCBDly = timeout; /* Store timeout in task's TCB */ +#if OS_TASK_DEL_EN > 0 + OSTCBCur->OSTCBFlagNode = pnode; /* TCB to link to node */ +#endif + pnode->OSFlagNodeFlags = flags; /* Save the flags that we need to wait for */ + pnode->OSFlagNodeWaitType = wait_type; /* Save the type of wait we are doing */ + pnode->OSFlagNodeTCB = (void *)OSTCBCur; /* Link to task's TCB */ + pnode->OSFlagNodeNext = pgrp->OSFlagWaitList; /* Add node at beginning of event flag wait list */ + pnode->OSFlagNodePrev = (void *)0; + pnode->OSFlagNodeFlagGrp = (void *)pgrp; /* Link to Event Flag Group */ + pnode_next = (OS_FLAG_NODE *)pgrp->OSFlagWaitList; + if (pnode_next != (void *)0) { /* Is this the first NODE to insert? */ + pnode_next->OSFlagNodePrev = pnode; /* No, link in doubly linked list */ + } + pgrp->OSFlagWaitList = (void *)pnode; + + y = OSTCBCur->OSTCBY; /* Suspend current task until flag(s) received */ + OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX; + if (OSRdyTbl[y] == 0x00) { + OSRdyGrp &= ~OSTCBCur->OSTCBBitY; + } +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* INITIALIZE THE EVENT FLAG MODULE +* +* Description: This function is called by uC/OS-II to initialize the event flag module. Your application +* MUST NOT call this function. In other words, this function is internal to uC/OS-II. +* +* Arguments : none +* +* Returns : none +* +* WARNING : You MUST NOT call this function from your code. This is an INTERNAL function to uC/OS-II. +********************************************************************************************************* +*/ + +void OS_FlagInit (void) +{ +#if OS_MAX_FLAGS == 1 + OSFlagFreeList = (OS_FLAG_GRP *)&OSFlagTbl[0]; /* Only ONE event flag group! */ + OSFlagFreeList->OSFlagType = OS_EVENT_TYPE_UNUSED; + OSFlagFreeList->OSFlagWaitList = (void *)0; + OSFlagFreeList->OSFlagFlags = (OS_FLAGS)0; +#if OS_FLAG_NAME_SIZE > 1 + OSFlagFreeList->OSFlagName[0] = '?'; + OSFlagFreeList->OSFlagName[1] = OS_ASCII_NUL; +#endif +#endif + +#if OS_MAX_FLAGS >= 2 + INT16U i; + OS_FLAG_GRP *pgrp1; + OS_FLAG_GRP *pgrp2; + + + OS_MemClr((INT8U *)&OSFlagTbl[0], sizeof(OSFlagTbl)); /* Clear the flag group table */ + pgrp1 = &OSFlagTbl[0]; + pgrp2 = &OSFlagTbl[1]; + for (i = 0; i < (OS_MAX_FLAGS - 1); i++) { /* Init. list of free EVENT FLAGS */ + pgrp1->OSFlagType = OS_EVENT_TYPE_UNUSED; + pgrp1->OSFlagWaitList = (void *)pgrp2; +#if OS_FLAG_NAME_SIZE > 1 + pgrp1->OSFlagName[0] = '?'; /* Unknown name */ + pgrp1->OSFlagName[1] = OS_ASCII_NUL; +#endif + pgrp1++; + pgrp2++; + } + pgrp1->OSFlagType = OS_EVENT_TYPE_UNUSED; + pgrp1->OSFlagWaitList = (void *)0; +#if OS_FLAG_NAME_SIZE > 1 + pgrp1->OSFlagName[0] = '?'; /* Unknown name */ + pgrp1->OSFlagName[1] = OS_ASCII_NUL; +#endif + OSFlagFreeList = &OSFlagTbl[0]; +#endif +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* MAKE TASK READY-TO-RUN, EVENT(s) OCCURRED +* +* Description: This function is internal to uC/OS-II and is used to make a task ready-to-run because the +* desired event flag bits have been set. +* +* Arguments : pnode is a pointer to a structure which contains data about the task waiting for +* event flag bit(s) to be set. +* +* flags_rdy contains the bit pattern of the event flags that cause the task to become +* ready-to-run. +* +* Returns : OS_TRUE If the task has been placed in the ready list and thus needs scheduling +* OS_FALSE The task is still not ready to run and thus scheduling is not necessary +* +* Called by : OSFlagsPost() OS_FLAG.C +* +* Note(s) : 1) This function assumes that interrupts are disabled. +* 2) This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +static BOOLEAN OS_FlagTaskRdy (OS_FLAG_NODE *pnode, OS_FLAGS flags_rdy) +{ + OS_TCB *ptcb; + BOOLEAN sched; + + + ptcb = (OS_TCB *)pnode->OSFlagNodeTCB; /* Point to TCB of waiting task */ + ptcb->OSTCBDly = 0; + ptcb->OSTCBFlagsRdy = flags_rdy; + ptcb->OSTCBStat &= ~(INT8U)OS_STAT_FLAG; + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; + if (ptcb->OSTCBStat == OS_STAT_RDY) { /* Task now ready? */ + OSRdyGrp |= ptcb->OSTCBBitY; /* Put task into ready list */ + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + sched = OS_TRUE; + } else { + sched = OS_FALSE; + } + OS_FlagUnlink(pnode); + return (sched); +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* UNLINK EVENT FLAG NODE FROM WAITING LIST +* +* Description: This function is internal to uC/OS-II and is used to unlink an event flag node from a +* list of tasks waiting for the event flag. +* +* Arguments : pnode is a pointer to a structure which contains data about the task waiting for +* event flag bit(s) to be set. +* +* Returns : none +* +* Called by : OS_FlagTaskRdy() OS_FLAG.C +* OSFlagPend() OS_FLAG.C +* OSTaskDel() OS_TASK.C +* +* Note(s) : 1) This function assumes that interrupts are disabled. +* 2) This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +void OS_FlagUnlink (OS_FLAG_NODE *pnode) +{ +#if OS_TASK_DEL_EN > 0 + OS_TCB *ptcb; +#endif + OS_FLAG_GRP *pgrp; + OS_FLAG_NODE *pnode_prev; + OS_FLAG_NODE *pnode_next; + + + pnode_prev = (OS_FLAG_NODE *)pnode->OSFlagNodePrev; + pnode_next = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; + if (pnode_prev == (OS_FLAG_NODE *)0) { /* Is it first node in wait list? */ + pgrp = (OS_FLAG_GRP *)pnode->OSFlagNodeFlagGrp; + pgrp->OSFlagWaitList = (void *)pnode_next; /* Update list for new 1st node */ + if (pnode_next != (OS_FLAG_NODE *)0) { + pnode_next->OSFlagNodePrev = (OS_FLAG_NODE *)0; /* Link new 1st node PREV to NULL */ + } + } else { /* No, A node somewhere in the list */ + pnode_prev->OSFlagNodeNext = pnode_next; /* Link around the node to unlink */ + if (pnode_next != (OS_FLAG_NODE *)0) { /* Was this the LAST node? */ + pnode_next->OSFlagNodePrev = pnode_prev; /* No, Link around current node */ + } + } +#if OS_TASK_DEL_EN > 0 + ptcb = (OS_TCB *)pnode->OSFlagNodeTCB; + ptcb->OSTCBFlagNode = (OS_FLAG_NODE *)0; +#endif +} +#endif diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/os_mbox.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_mbox.c new file mode 100644 index 0000000..0ee0c51 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_mbox.c @@ -0,0 +1,629 @@ +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* MESSAGE MAILBOX MANAGEMENT +* +* (c) Copyright 1992-2007, Micrium, Weston, FL +* All Rights Reserved +* +* File : OS_MBOX.C +* By : Jean J. Labrosse +* Version : V2.86 +* +* LICENSING TERMS: +* --------------- +* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. +* If you plan on using uC/OS-II in a commercial product you need to contact Micriµm to properly license +* its use in your product. We provide ALL the source code for your convenience and to help you experience +* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a +* licensing fee. +********************************************************************************************************* +*/ + +#ifndef OS_MASTER_FILE +#include +#endif + +#if OS_MBOX_EN > 0 +/* +********************************************************************************************************* +* ACCEPT MESSAGE FROM MAILBOX +* +* Description: This function checks the mailbox to see if a message is available. Unlike OSMboxPend(), +* OSMboxAccept() does not suspend the calling task if a message is not available. +* +* Arguments : pevent is a pointer to the event control block +* +* Returns : != (void *)0 is the message in the mailbox if one is available. The mailbox is cleared +* so the next time OSMboxAccept() is called, the mailbox will be empty. +* == (void *)0 if the mailbox is empty or, +* if 'pevent' is a NULL pointer or, +* if you didn't pass the proper event pointer. +********************************************************************************************************* +*/ + +#if OS_MBOX_ACCEPT_EN > 0 +void *OSMboxAccept (OS_EVENT *pevent) +{ + void *pmsg; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return ((void *)0); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) { /* Validate event block type */ + return ((void *)0); + } + OS_ENTER_CRITICAL(); + pmsg = pevent->OSEventPtr; + pevent->OSEventPtr = (void *)0; /* Clear the mailbox */ + OS_EXIT_CRITICAL(); + return (pmsg); /* Return the message received (or NULL) */ +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* CREATE A MESSAGE MAILBOX +* +* Description: This function creates a message mailbox if free event control blocks are available. +* +* Arguments : pmsg is a pointer to a message that you wish to deposit in the mailbox. If +* you set this value to the NULL pointer (i.e. (void *)0) then the mailbox +* will be considered empty. +* +* Returns : != (OS_EVENT *)0 is a pointer to the event control clock (OS_EVENT) associated with the +* created mailbox +* == (OS_EVENT *)0 if no event control blocks were available +********************************************************************************************************* +*/ + +OS_EVENT *OSMboxCreate (void *pmsg) +{ + OS_EVENT *pevent; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + return ((OS_EVENT *)0); /* ... can't CREATE from an ISR */ + } + OS_ENTER_CRITICAL(); + pevent = OSEventFreeList; /* Get next free event control block */ + if (OSEventFreeList != (OS_EVENT *)0) { /* See if pool of free ECB pool was empty */ + OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr; + } + OS_EXIT_CRITICAL(); + if (pevent != (OS_EVENT *)0) { + pevent->OSEventType = OS_EVENT_TYPE_MBOX; + pevent->OSEventCnt = 0; + pevent->OSEventPtr = pmsg; /* Deposit message in event control block */ +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; + pevent->OSEventName[1] = OS_ASCII_NUL; +#endif + OS_EventWaitListInit(pevent); + } + return (pevent); /* Return pointer to event control block */ +} +/*$PAGE*/ +/* +********************************************************************************************************* +* DELETE A MAIBOX +* +* Description: This function deletes a mailbox and readies all tasks pending on the mailbox. +* +* Arguments : pevent is a pointer to the event control block associated with the desired +* mailbox. +* +* opt determines delete options as follows: +* opt == OS_DEL_NO_PEND Delete the mailbox ONLY if no task pending +* opt == OS_DEL_ALWAYS Deletes the mailbox even if tasks are waiting. +* In this case, all the tasks pending will be readied. +* +* perr is a pointer to an error code that can contain one of the following values: +* OS_ERR_NONE The call was successful and the mailbox was deleted +* OS_ERR_DEL_ISR If you attempted to delete the mailbox from an ISR +* OS_ERR_INVALID_OPT An invalid option was specified +* OS_ERR_TASK_WAITING One or more tasks were waiting on the mailbox +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a mailbox +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +* +* Returns : pevent upon error +* (OS_EVENT *)0 if the mailbox was successfully deleted. +* +* Note(s) : 1) This function must be used with care. Tasks that would normally expect the presence of +* the mailbox MUST check the return code of OSMboxPend(). +* 2) OSMboxAccept() callers will not know that the intended mailbox has been deleted! +* 3) This call can potentially disable interrupts for a long time. The interrupt disable +* time is directly proportional to the number of tasks waiting on the mailbox. +* 4) Because ALL tasks pending on the mailbox will be readied, you MUST be careful in +* applications where the mailbox is used for mutual exclusion because the resource(s) +* will no longer be guarded by the mailbox. +********************************************************************************************************* +*/ + +#if OS_MBOX_DEL_EN > 0 +OS_EVENT *OSMboxDel (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + BOOLEAN tasks_waiting; + OS_EVENT *pevent_return; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (pevent); + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return (pevent); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return (pevent); + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_DEL_ISR; /* ... can't DELETE from an ISR */ + return (pevent); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any tasks waiting on mailbox */ + tasks_waiting = OS_TRUE; /* Yes */ + } else { + tasks_waiting = OS_FALSE; /* No */ + } + switch (opt) { + case OS_DEL_NO_PEND: /* Delete mailbox only if no task waiting */ + if (tasks_waiting == OS_FALSE) { +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + pevent->OSEventName[1] = OS_ASCII_NUL; +#endif + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + pevent->OSEventCnt = 0; + OSEventFreeList = pevent; /* Get next free event control block */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + pevent_return = (OS_EVENT *)0; /* Mailbox has been deleted */ + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_WAITING; + pevent_return = pevent; + } + break; + + case OS_DEL_ALWAYS: /* Always delete the mailbox */ + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for mailbox */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_MBOX, OS_STAT_PEND_OK); + } +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + pevent->OSEventName[1] = OS_ASCII_NUL; +#endif + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + pevent->OSEventCnt = 0; + OSEventFreeList = pevent; /* Get next free event control block */ + OS_EXIT_CRITICAL(); + if (tasks_waiting == OS_TRUE) { /* Reschedule only if task(s) were waiting */ + OS_Sched(); /* Find highest priority task ready to run */ + } + *perr = OS_ERR_NONE; + pevent_return = (OS_EVENT *)0; /* Mailbox has been deleted */ + break; + + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_INVALID_OPT; + pevent_return = pevent; + break; + } + return (pevent_return); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* PEND ON MAILBOX FOR A MESSAGE +* +* Description: This function waits for a message to be sent to a mailbox +* +* Arguments : pevent is a pointer to the event control block associated with the desired mailbox +* +* timeout is an optional timeout period (in clock ticks). If non-zero, your task will +* wait for a message to arrive at the mailbox up to the amount of time +* specified by this argument. If you specify 0, however, your task will wait +* forever at the specified mailbox or, until a message arrives. +* +* perr is a pointer to where an error message will be deposited. Possible error +* messages are: +* +* OS_ERR_NONE The call was successful and your task received a +* message. +* OS_ERR_TIMEOUT A message was not received within the specified 'timeout'. +* OS_ERR_PEND_ABORT The wait on the mailbox was aborted. +* OS_ERR_EVENT_TYPE Invalid event type +* OS_ERR_PEND_ISR If you called this function from an ISR and the result +* would lead to a suspension. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer +* OS_ERR_PEND_LOCKED If you called this function when the scheduler is locked +* +* Returns : != (void *)0 is a pointer to the message received +* == (void *)0 if no message was received or, +* if 'pevent' is a NULL pointer or, +* if you didn't pass the proper pointer to the event control block. +********************************************************************************************************* +*/ +/*$PAGE*/ +void *OSMboxPend (OS_EVENT *pevent, INT16U timeout, INT8U *perr) +{ + void *pmsg; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return ((void *)0); + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return ((void *)0); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return ((void *)0); + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + return ((void *)0); + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + return ((void *)0); + } + OS_ENTER_CRITICAL(); + pmsg = pevent->OSEventPtr; + if (pmsg != (void *)0) { /* See if there is already a message */ + pevent->OSEventPtr = (void *)0; /* Clear the mailbox */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (pmsg); /* Return the message received (or NULL) */ + } + OSTCBCur->OSTCBStat |= OS_STAT_MBOX; /* Message not available, task will pend */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + OSTCBCur->OSTCBDly = timeout; /* Load timeout in TCB */ + OS_EventTaskWait(pevent); /* Suspend task until event or timeout occurs */ + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next highest priority task ready to run */ + OS_ENTER_CRITICAL(); + switch (OSTCBCur->OSTCBStatPend) { /* See if we timed-out or aborted */ + case OS_STAT_PEND_OK: + pmsg = OSTCBCur->OSTCBMsg; + *perr = OS_ERR_NONE; + break; + + case OS_STAT_PEND_ABORT: + pmsg = (void *)0; + *perr = OS_ERR_PEND_ABORT; /* Indicate that we aborted */ + break; + + case OS_STAT_PEND_TO: + default: + OS_EventTaskRemove(OSTCBCur, pevent); + pmsg = (void *)0; + *perr = OS_ERR_TIMEOUT; /* Indicate that we didn't get event within TO */ + break; + } + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Set task status to ready */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; /* Clear event pointers */ +#if (OS_EVENT_MULTI_EN > 0) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0; +#endif + OSTCBCur->OSTCBMsg = (void *)0; /* Clear received message */ + OS_EXIT_CRITICAL(); + return (pmsg); /* Return received message */ +} +/*$PAGE*/ +/* +********************************************************************************************************* +* ABORT WAITING ON A MESSAGE MAILBOX +* +* Description: This function aborts & readies any tasks currently waiting on a mailbox. This function +* should be used to fault-abort the wait on the mailbox, rather than to normally signal +* the mailbox via OSMboxPost() or OSMboxPostOpt(). +* +* Arguments : pevent is a pointer to the event control block associated with the desired mailbox. +* +* opt determines the type of ABORT performed: +* OS_PEND_OPT_NONE ABORT wait for a single task (HPT) waiting on the +* mailbox +* OS_PEND_OPT_BROADCAST ABORT wait for ALL tasks that are waiting on the +* mailbox +* +* perr is a pointer to where an error message will be deposited. Possible error +* messages are: +* +* OS_ERR_NONE No tasks were waiting on the mailbox. +* OS_ERR_PEND_ABORT At least one task waiting on the mailbox was readied +* and informed of the aborted wait; check return value +* for the number of tasks whose wait on the mailbox +* was aborted. +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a mailbox. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +* +* Returns : == 0 if no tasks were waiting on the mailbox, or upon error. +* > 0 if one or more tasks waiting on the mailbox are now readied and informed. +********************************************************************************************************* +*/ + +#if OS_MBOX_PEND_ABORT_EN > 0 +INT8U OSMboxPendAbort (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + INT8U nbr_tasks; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (0); + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return (0); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return (0); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any task waiting on mailbox? */ + nbr_tasks = 0; + switch (opt) { + case OS_PEND_OPT_BROADCAST: /* Do we need to abort ALL waiting tasks? */ + while (pevent->OSEventGrp != 0) { /* Yes, ready ALL tasks waiting on mailbox */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_MBOX, OS_STAT_PEND_ABORT); + nbr_tasks++; + } + break; + + case OS_PEND_OPT_NONE: + default: /* No, ready HPT waiting on mailbox */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_MBOX, OS_STAT_PEND_ABORT); + nbr_tasks++; + break; + } + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find HPT ready to run */ + *perr = OS_ERR_PEND_ABORT; + return (nbr_tasks); + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (0); /* No tasks waiting on mailbox */ +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* POST MESSAGE TO A MAILBOX +* +* Description: This function sends a message to a mailbox +* +* Arguments : pevent is a pointer to the event control block associated with the desired mailbox +* +* pmsg is a pointer to the message to send. You MUST NOT send a NULL pointer. +* +* Returns : OS_ERR_NONE The call was successful and the message was sent +* OS_ERR_MBOX_FULL If the mailbox already contains a message. You can can only send one +* message at a time and thus, the message MUST be consumed before you +* are allowed to send another one. +* OS_ERR_EVENT_TYPE If you are attempting to post to a non mailbox. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer +* OS_ERR_POST_NULL_PTR If you are attempting to post a NULL pointer +* +* Note(s) : 1) HPT means Highest Priority Task +********************************************************************************************************* +*/ + +#if OS_MBOX_POST_EN > 0 +INT8U OSMboxPost (OS_EVENT *pevent, void *pmsg) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } + if (pmsg == (void *)0) { /* Make sure we are not posting a NULL pointer */ + return (OS_ERR_POST_NULL_PTR); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any task pending on mailbox */ + /* Ready HPT waiting on event */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_MBOX, OS_STAT_PEND_OK); + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find highest priority task ready to run */ + return (OS_ERR_NONE); + } + if (pevent->OSEventPtr != (void *)0) { /* Make sure mailbox doesn't already have a msg */ + OS_EXIT_CRITICAL(); + return (OS_ERR_MBOX_FULL); + } + pevent->OSEventPtr = pmsg; /* Place message in mailbox */ + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* POST MESSAGE TO A MAILBOX +* +* Description: This function sends a message to a mailbox +* +* Arguments : pevent is a pointer to the event control block associated with the desired mailbox +* +* pmsg is a pointer to the message to send. You MUST NOT send a NULL pointer. +* +* opt determines the type of POST performed: +* OS_POST_OPT_NONE POST to a single waiting task +* (Identical to OSMboxPost()) +* OS_POST_OPT_BROADCAST POST to ALL tasks that are waiting on the mailbox +* +* OS_POST_OPT_NO_SCHED Indicates that the scheduler will NOT be invoked +* +* Returns : OS_ERR_NONE The call was successful and the message was sent +* OS_ERR_MBOX_FULL If the mailbox already contains a message. You can can only send one +* message at a time and thus, the message MUST be consumed before you +* are allowed to send another one. +* OS_ERR_EVENT_TYPE If you are attempting to post to a non mailbox. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer +* OS_ERR_POST_NULL_PTR If you are attempting to post a NULL pointer +* +* Note(s) : 1) HPT means Highest Priority Task +* +* Warning : Interrupts can be disabled for a long time if you do a 'broadcast'. In fact, the +* interrupt disable time is proportional to the number of tasks waiting on the mailbox. +********************************************************************************************************* +*/ + +#if OS_MBOX_POST_OPT_EN > 0 +INT8U OSMboxPostOpt (OS_EVENT *pevent, void *pmsg, INT8U opt) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } + if (pmsg == (void *)0) { /* Make sure we are not posting a NULL pointer */ + return (OS_ERR_POST_NULL_PTR); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any task pending on mailbox */ + if ((opt & OS_POST_OPT_BROADCAST) != 0x00) { /* Do we need to post msg to ALL waiting tasks ? */ + while (pevent->OSEventGrp != 0) { /* Yes, Post to ALL tasks waiting on mailbox */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_MBOX, OS_STAT_PEND_OK); + } + } else { /* No, Post to HPT waiting on mbox */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_MBOX, OS_STAT_PEND_OK); + } + OS_EXIT_CRITICAL(); + if ((opt & OS_POST_OPT_NO_SCHED) == 0) { /* See if scheduler needs to be invoked */ + OS_Sched(); /* Find HPT ready to run */ + } + return (OS_ERR_NONE); + } + if (pevent->OSEventPtr != (void *)0) { /* Make sure mailbox doesn't already have a msg */ + OS_EXIT_CRITICAL(); + return (OS_ERR_MBOX_FULL); + } + pevent->OSEventPtr = pmsg; /* Place message in mailbox */ + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* QUERY A MESSAGE MAILBOX +* +* Description: This function obtains information about a message mailbox. +* +* Arguments : pevent is a pointer to the event control block associated with the desired mailbox +* +* p_mbox_data is a pointer to a structure that will contain information about the message +* mailbox. +* +* Returns : OS_ERR_NONE The call was successful and the message was sent +* OS_ERR_EVENT_TYPE If you are attempting to obtain data from a non mailbox. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer +* OS_ERR_PDATA_NULL If 'p_mbox_data' is a NULL pointer +********************************************************************************************************* +*/ + +#if OS_MBOX_QUERY_EN > 0 +INT8U OSMboxQuery (OS_EVENT *pevent, OS_MBOX_DATA *p_mbox_data) +{ + INT8U i; +#if OS_LOWEST_PRIO <= 63 + INT8U *psrc; + INT8U *pdest; +#else + INT16U *psrc; + INT16U *pdest; +#endif +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } + if (p_mbox_data == (OS_MBOX_DATA *)0) { /* Validate 'p_mbox_data' */ + return (OS_ERR_PDATA_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + p_mbox_data->OSEventGrp = pevent->OSEventGrp; /* Copy message mailbox wait list */ + psrc = &pevent->OSEventTbl[0]; + pdest = &p_mbox_data->OSEventTbl[0]; + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + *pdest++ = *psrc++; + } + p_mbox_data->OSMsg = pevent->OSEventPtr; /* Get message from mailbox */ + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +#endif /* OS_MBOX_QUERY_EN */ +#endif /* OS_MBOX_EN */ diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/os_mem.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_mem.c new file mode 100644 index 0000000..72c8b84 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_mem.c @@ -0,0 +1,434 @@ +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* MEMORY MANAGEMENT +* +* (c) Copyright 1992-2007, Micrium, Weston, FL +* All Rights Reserved +* +* File : OS_MEM.C +* By : Jean J. Labrosse +* Version : V2.86 +* +* LICENSING TERMS: +* --------------- +* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. +* If you plan on using uC/OS-II in a commercial product you need to contact Micriµm to properly license +* its use in your product. We provide ALL the source code for your convenience and to help you experience +* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a +* licensing fee. +********************************************************************************************************* +*/ + +#ifndef OS_MASTER_FILE +#include +#endif + +#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0) +/* +********************************************************************************************************* +* CREATE A MEMORY PARTITION +* +* Description : Create a fixed-sized memory partition that will be managed by uC/OS-II. +* +* Arguments : addr is the starting address of the memory partition +* +* nblks is the number of memory blocks to create from the partition. +* +* blksize is the size (in bytes) of each block in the memory partition. +* +* perr is a pointer to a variable containing an error message which will be set by +* this function to either: +* +* OS_ERR_NONE if the memory partition has been created correctly. +* OS_ERR_MEM_INVALID_ADDR if you are specifying an invalid address for the memory +* storage of the partition or, the block does not align +* on a pointer boundary +* OS_ERR_MEM_INVALID_PART no free partitions available +* OS_ERR_MEM_INVALID_BLKS user specified an invalid number of blocks (must be >= 2) +* OS_ERR_MEM_INVALID_SIZE user specified an invalid block size +* - must be greater than the size of a pointer +* - must be able to hold an integral number of pointers +* Returns : != (OS_MEM *)0 is the partition was created +* == (OS_MEM *)0 if the partition was not created because of invalid arguments or, no +* free partition is available. +********************************************************************************************************* +*/ + +OS_MEM *OSMemCreate (void *addr, INT32U nblks, INT32U blksize, INT8U *perr) +{ + OS_MEM *pmem; + INT8U *pblk; + void **plink; + INT32U i; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return ((OS_MEM *)0); + } + if (addr == (void *)0) { /* Must pass a valid address for the memory part.*/ + *perr = OS_ERR_MEM_INVALID_ADDR; + return ((OS_MEM *)0); + } + if (((INT32U)addr & (sizeof(void *) - 1)) != 0){ /* Must be pointer size aligned */ + *perr = OS_ERR_MEM_INVALID_ADDR; + return ((OS_MEM *)0); + } + if (nblks < 2) { /* Must have at least 2 blocks per partition */ + *perr = OS_ERR_MEM_INVALID_BLKS; + return ((OS_MEM *)0); + } + if (blksize < sizeof(void *)) { /* Must contain space for at least a pointer */ + *perr = OS_ERR_MEM_INVALID_SIZE; + return ((OS_MEM *)0); + } +#endif + OS_ENTER_CRITICAL(); + pmem = OSMemFreeList; /* Get next free memory partition */ + if (OSMemFreeList != (OS_MEM *)0) { /* See if pool of free partitions was empty */ + OSMemFreeList = (OS_MEM *)OSMemFreeList->OSMemFreeList; + } + OS_EXIT_CRITICAL(); + if (pmem == (OS_MEM *)0) { /* See if we have a memory partition */ + *perr = OS_ERR_MEM_INVALID_PART; + return ((OS_MEM *)0); + } + plink = (void **)addr; /* Create linked list of free memory blocks */ + pblk = (INT8U *)((INT32U)addr + blksize); + for (i = 0; i < (nblks - 1); i++) { + *plink = (void *)pblk; /* Save pointer to NEXT block in CURRENT block */ + plink = (void **)pblk; /* Position to NEXT block */ + pblk = (INT8U *)((INT32U)pblk + blksize); /* Point to the FOLLOWING block */ + } + *plink = (void *)0; /* Last memory block points to NULL */ + pmem->OSMemAddr = addr; /* Store start address of memory partition */ + pmem->OSMemFreeList = addr; /* Initialize pointer to pool of free blocks */ + pmem->OSMemNFree = nblks; /* Store number of free blocks in MCB */ + pmem->OSMemNBlks = nblks; + pmem->OSMemBlkSize = blksize; /* Store block size of each memory blocks */ + *perr = OS_ERR_NONE; + return (pmem); +} +/*$PAGE*/ +/* +********************************************************************************************************* +* GET A MEMORY BLOCK +* +* Description : Get a memory block from a partition +* +* Arguments : pmem is a pointer to the memory partition control block +* +* perr is a pointer to a variable containing an error message which will be set by this +* function to either: +* +* OS_ERR_NONE if the memory partition has been created correctly. +* OS_ERR_MEM_NO_FREE_BLKS if there are no more free memory blocks to allocate to caller +* OS_ERR_MEM_INVALID_PMEM if you passed a NULL pointer for 'pmem' +* +* Returns : A pointer to a memory block if no error is detected +* A pointer to NULL if an error is detected +********************************************************************************************************* +*/ + +void *OSMemGet (OS_MEM *pmem, INT8U *perr) +{ + void *pblk; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return ((void *)0); + } + if (pmem == (OS_MEM *)0) { /* Must point to a valid memory partition */ + *perr = OS_ERR_MEM_INVALID_PMEM; + return ((void *)0); + } +#endif + OS_ENTER_CRITICAL(); + if (pmem->OSMemNFree > 0) { /* See if there are any free memory blocks */ + pblk = pmem->OSMemFreeList; /* Yes, point to next free memory block */ + pmem->OSMemFreeList = *(void **)pblk; /* Adjust pointer to new free list */ + pmem->OSMemNFree--; /* One less memory block in this partition */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; /* No error */ + return (pblk); /* Return memory block to caller */ + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_MEM_NO_FREE_BLKS; /* No, Notify caller of empty memory partition */ + return ((void *)0); /* Return NULL pointer to caller */ +} +/*$PAGE*/ +/* +********************************************************************************************************* +* GET THE NAME OF A MEMORY PARTITION +* +* Description: This function is used to obtain the name assigned to a memory partition. +* +* Arguments : pmem is a pointer to the memory partition +* +* pname is a pointer to an ASCII string that will receive the name of the memory partition. +* +* perr is a pointer to an error code that can contain one of the following values: +* +* OS_ERR_NONE if the name was copied to 'pname' +* OS_ERR_MEM_INVALID_PMEM if you passed a NULL pointer for 'pmem' +* OS_ERR_PNAME_NULL You passed a NULL pointer for 'pname' +* OS_ERR_NAME_GET_ISR You called this function from an ISR +* +* Returns : The length of the string or 0 if 'pmem' is a NULL pointer. +********************************************************************************************************* +*/ + +#if OS_MEM_NAME_SIZE > 1 +INT8U OSMemNameGet (OS_MEM *pmem, INT8U *pname, INT8U *perr) +{ + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (0); + } + if (pmem == (OS_MEM *)0) { /* Is 'pmem' a NULL pointer? */ + *perr = OS_ERR_MEM_INVALID_PMEM; + return (0); + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + *perr = OS_ERR_PNAME_NULL; + return (0); + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_NAME_GET_ISR; + return (0); + } + OS_ENTER_CRITICAL(); + len = OS_StrCopy(pname, pmem->OSMemName); /* Copy name from OS_MEM */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (len); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* ASSIGN A NAME TO A MEMORY PARTITION +* +* Description: This function assigns a name to a memory partition. +* +* Arguments : pmem is a pointer to the memory partition +* +* pname is a pointer to an ASCII string that contains the name of the memory partition. +* +* perr is a pointer to an error code that can contain one of the following values: +* +* OS_ERR_NONE if the name was copied to 'pname' +* OS_ERR_MEM_INVALID_PMEM if you passed a NULL pointer for 'pmem' +* OS_ERR_PNAME_NULL You passed a NULL pointer for 'pname' +* OS_ERR_MEM_NAME_TOO_LONG if the name doesn't fit in the storage area +* OS_ERR_NAME_SET_ISR if you called this function from an ISR +* +* Returns : None +********************************************************************************************************* +*/ + +#if OS_MEM_NAME_SIZE > 1 +void OSMemNameSet (OS_MEM *pmem, INT8U *pname, INT8U *perr) +{ + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return; + } + if (pmem == (OS_MEM *)0) { /* Is 'pmem' a NULL pointer? */ + *perr = OS_ERR_MEM_INVALID_PMEM; + return; + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + *perr = OS_ERR_PNAME_NULL; + return; + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_NAME_SET_ISR; + return; + } + OS_ENTER_CRITICAL(); + len = OS_StrLen(pname); /* Can we fit the string in the storage area? */ + if (len > (OS_MEM_NAME_SIZE - 1)) { /* No */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_MEM_NAME_TOO_LONG; + return; + } + (void)OS_StrCopy(pmem->OSMemName, pname); /* Yes, copy name to the memory partition header */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* RELEASE A MEMORY BLOCK +* +* Description : Returns a memory block to a partition +* +* Arguments : pmem is a pointer to the memory partition control block +* +* pblk is a pointer to the memory block being released. +* +* Returns : OS_ERR_NONE if the memory block was inserted into the partition +* OS_ERR_MEM_FULL if you are returning a memory block to an already FULL memory +* partition (You freed more blocks than you allocated!) +* OS_ERR_MEM_INVALID_PMEM if you passed a NULL pointer for 'pmem' +* OS_ERR_MEM_INVALID_PBLK if you passed a NULL pointer for the block to release. +********************************************************************************************************* +*/ + +INT8U OSMemPut (OS_MEM *pmem, void *pblk) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pmem == (OS_MEM *)0) { /* Must point to a valid memory partition */ + return (OS_ERR_MEM_INVALID_PMEM); + } + if (pblk == (void *)0) { /* Must release a valid block */ + return (OS_ERR_MEM_INVALID_PBLK); + } +#endif + OS_ENTER_CRITICAL(); + if (pmem->OSMemNFree >= pmem->OSMemNBlks) { /* Make sure all blocks not already returned */ + OS_EXIT_CRITICAL(); + return (OS_ERR_MEM_FULL); + } + *(void **)pblk = pmem->OSMemFreeList; /* Insert released block into free block list */ + pmem->OSMemFreeList = pblk; + pmem->OSMemNFree++; /* One more memory block in this partition */ + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); /* Notify caller that memory block was released */ +} +/*$PAGE*/ +/* +********************************************************************************************************* +* QUERY MEMORY PARTITION +* +* Description : This function is used to determine the number of free memory blocks and the number of +* used memory blocks from a memory partition. +* +* Arguments : pmem is a pointer to the memory partition control block +* +* p_mem_data is a pointer to a structure that will contain information about the memory +* partition. +* +* Returns : OS_ERR_NONE if no errors were found. +* OS_ERR_MEM_INVALID_PMEM if you passed a NULL pointer for 'pmem' +* OS_ERR_MEM_INVALID_PDATA if you passed a NULL pointer to the data recipient. +********************************************************************************************************* +*/ + +#if OS_MEM_QUERY_EN > 0 +INT8U OSMemQuery (OS_MEM *pmem, OS_MEM_DATA *p_mem_data) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pmem == (OS_MEM *)0) { /* Must point to a valid memory partition */ + return (OS_ERR_MEM_INVALID_PMEM); + } + if (p_mem_data == (OS_MEM_DATA *)0) { /* Must release a valid storage area for the data */ + return (OS_ERR_MEM_INVALID_PDATA); + } +#endif + OS_ENTER_CRITICAL(); + p_mem_data->OSAddr = pmem->OSMemAddr; + p_mem_data->OSFreeList = pmem->OSMemFreeList; + p_mem_data->OSBlkSize = pmem->OSMemBlkSize; + p_mem_data->OSNBlks = pmem->OSMemNBlks; + p_mem_data->OSNFree = pmem->OSMemNFree; + OS_EXIT_CRITICAL(); + p_mem_data->OSNUsed = p_mem_data->OSNBlks - p_mem_data->OSNFree; + return (OS_ERR_NONE); +} +#endif /* OS_MEM_QUERY_EN */ +/*$PAGE*/ +/* +********************************************************************************************************* +* INITIALIZE MEMORY PARTITION MANAGER +* +* Description : This function is called by uC/OS-II to initialize the memory partition manager. Your +* application MUST NOT call this function. +* +* Arguments : none +* +* Returns : none +* +* Note(s) : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +void OS_MemInit (void) +{ +#if OS_MAX_MEM_PART == 1 + OS_MemClr((INT8U *)&OSMemTbl[0], sizeof(OSMemTbl)); /* Clear the memory partition table */ + OSMemFreeList = (OS_MEM *)&OSMemTbl[0]; /* Point to beginning of free list */ +#if OS_MEM_NAME_SIZE > 1 + OSMemFreeList->OSMemName[0] = '?'; /* Unknown name */ + OSMemFreeList->OSMemName[1] = OS_ASCII_NUL; +#endif +#endif + +#if OS_MAX_MEM_PART >= 2 + OS_MEM *pmem; + INT16U i; + + + OS_MemClr((INT8U *)&OSMemTbl[0], sizeof(OSMemTbl)); /* Clear the memory partition table */ + pmem = &OSMemTbl[0]; /* Point to memory control block (MCB) */ + for (i = 0; i < (OS_MAX_MEM_PART - 1); i++) { /* Init. list of free memory partitions */ + pmem->OSMemFreeList = (void *)&OSMemTbl[i+1]; /* Chain list of free partitions */ +#if OS_MEM_NAME_SIZE > 1 + pmem->OSMemName[0] = '?'; /* Unknown name */ + pmem->OSMemName[1] = OS_ASCII_NUL; +#endif + pmem++; + } + pmem->OSMemFreeList = (void *)0; /* Initialize last node */ +#if OS_MEM_NAME_SIZE > 1 + pmem->OSMemName[0] = '?'; /* Unknown name */ + pmem->OSMemName[1] = OS_ASCII_NUL; +#endif + + OSMemFreeList = &OSMemTbl[0]; /* Point to beginning of free list */ +#endif +} +#endif /* OS_MEM_EN */ diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/os_mutex.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_mutex.c new file mode 100644 index 0000000..c33d589 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_mutex.c @@ -0,0 +1,715 @@ +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* MUTUAL EXCLUSION SEMAPHORE MANAGEMENT +* +* (c) Copyright 1992-2007, Micrium, Weston, FL +* All Rights Reserved +* +* File : OS_MUTEX.C +* By : Jean J. Labrosse +* Version : V2.86 +* +* LICENSING TERMS: +* --------------- +* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. +* If you plan on using uC/OS-II in a commercial product you need to contact Micriµm to properly license +* its use in your product. We provide ALL the source code for your convenience and to help you experience +* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a +* licensing fee. +********************************************************************************************************* +*/ + +#ifndef OS_MASTER_FILE +#include +#endif + + +#if OS_MUTEX_EN > 0 +/* +********************************************************************************************************* +* LOCAL CONSTANTS +********************************************************************************************************* +*/ + +#define OS_MUTEX_KEEP_LOWER_8 ((INT16U)0x00FFu) +#define OS_MUTEX_KEEP_UPPER_8 ((INT16U)0xFF00u) + +#define OS_MUTEX_AVAILABLE ((INT16U)0x00FFu) + +/* +********************************************************************************************************* +* LOCAL CONSTANTS +********************************************************************************************************* +*/ + +static void OSMutex_RdyAtPrio(OS_TCB *ptcb, INT8U prio); + +/*$PAGE*/ +/* +********************************************************************************************************* +* ACCEPT MUTUAL EXCLUSION SEMAPHORE +* +* Description: This function checks the mutual exclusion semaphore to see if a resource is available. +* Unlike OSMutexPend(), OSMutexAccept() does not suspend the calling task if the resource is +* not available or the event did not occur. +* +* Arguments : pevent is a pointer to the event control block +* +* perr is a pointer to an error code which will be returned to your application: +* OS_ERR_NONE if the call was successful. +* OS_ERR_EVENT_TYPE if 'pevent' is not a pointer to a mutex +* OS_ERR_PEVENT_NULL 'pevent' is a NULL pointer +* OS_ERR_PEND_ISR if you called this function from an ISR +* OS_ERR_PIP_LOWER If the priority of the task that owns the Mutex is +* HIGHER (i.e. a lower number) than the PIP. This error +* indicates that you did not set the PIP higher (lower +* number) than ALL the tasks that compete for the Mutex. +* Unfortunately, this is something that could not be +* detected when the Mutex is created because we don't know +* what tasks will be using the Mutex. +* +* Returns : == OS_TRUE if the resource is available, the mutual exclusion semaphore is acquired +* == OS_FALSE a) if the resource is not available +* b) you didn't pass a pointer to a mutual exclusion semaphore +* c) you called this function from an ISR +* +* Warning(s) : This function CANNOT be called from an ISR because mutual exclusion semaphores are +* intended to be used by tasks only. +********************************************************************************************************* +*/ + +#if OS_MUTEX_ACCEPT_EN > 0 +BOOLEAN OSMutexAccept (OS_EVENT *pevent, INT8U *perr) +{ + INT8U pip; /* Priority Inheritance Priority (PIP) */ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (OS_FALSE); + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return (OS_FALSE); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return (OS_FALSE); + } + if (OSIntNesting > 0) { /* Make sure it's not called from an ISR */ + *perr = OS_ERR_PEND_ISR; + return (OS_FALSE); + } + OS_ENTER_CRITICAL(); /* Get value (0 or 1) of Mutex */ + pip = (INT8U)(pevent->OSEventCnt >> 8); /* Get PIP from mutex */ + if ((pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8) == OS_MUTEX_AVAILABLE) { + pevent->OSEventCnt &= OS_MUTEX_KEEP_UPPER_8; /* Mask off LSByte (Acquire Mutex) */ + pevent->OSEventCnt |= OSTCBCur->OSTCBPrio; /* Save current task priority in LSByte */ + pevent->OSEventPtr = (void *)OSTCBCur; /* Link TCB of task owning Mutex */ + if (OSTCBCur->OSTCBPrio <= pip) { /* PIP 'must' have a SMALLER prio ... */ + OS_EXIT_CRITICAL(); /* ... than current task! */ + *perr = OS_ERR_PIP_LOWER; + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + } + return (OS_TRUE); + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (OS_FALSE); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* CREATE A MUTUAL EXCLUSION SEMAPHORE +* +* Description: This function creates a mutual exclusion semaphore. +* +* Arguments : prio is the priority to use when accessing the mutual exclusion semaphore. In +* other words, when the semaphore is acquired and a higher priority task +* attempts to obtain the semaphore then the priority of the task owning the +* semaphore is raised to this priority. It is assumed that you will specify +* a priority that is LOWER in value than ANY of the tasks competing for the +* mutex. +* +* perr is a pointer to an error code which will be returned to your application: +* OS_ERR_NONE if the call was successful. +* OS_ERR_CREATE_ISR if you attempted to create a MUTEX from an ISR +* OS_ERR_PRIO_EXIST if a task at the priority inheritance priority +* already exist. +* OS_ERR_PEVENT_NULL No more event control blocks available. +* OS_ERR_PRIO_INVALID if the priority you specify is higher that the +* maximum allowed (i.e. > OS_LOWEST_PRIO) +* +* Returns : != (void *)0 is a pointer to the event control clock (OS_EVENT) associated with the +* created mutex. +* == (void *)0 if an error is detected. +* +* Note(s) : 1) The LEAST significant 8 bits of '.OSEventCnt' are used to hold the priority number +* of the task owning the mutex or 0xFF if no task owns the mutex. +* +* 2) The MOST significant 8 bits of '.OSEventCnt' are used to hold the priority number +* to use to reduce priority inversion. +********************************************************************************************************* +*/ + +OS_EVENT *OSMutexCreate (INT8U prio, INT8U *perr) +{ + OS_EVENT *pevent; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return ((OS_EVENT *)0); + } + if (prio >= OS_LOWEST_PRIO) { /* Validate PIP */ + *perr = OS_ERR_PRIO_INVALID; + return ((OS_EVENT *)0); + } +#endif + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_CREATE_ISR; /* ... can't CREATE mutex from an ISR */ + return ((OS_EVENT *)0); + } + OS_ENTER_CRITICAL(); + if (OSTCBPrioTbl[prio] != (OS_TCB *)0) { /* Mutex priority must not already exist */ + OS_EXIT_CRITICAL(); /* Task already exist at priority ... */ + *perr = OS_ERR_PRIO_EXIST; /* ... inheritance priority */ + return ((OS_EVENT *)0); + } + OSTCBPrioTbl[prio] = OS_TCB_RESERVED; /* Reserve the table entry */ + pevent = OSEventFreeList; /* Get next free event control block */ + if (pevent == (OS_EVENT *)0) { /* See if an ECB was available */ + OSTCBPrioTbl[prio] = (OS_TCB *)0; /* No, Release the table entry */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_PEVENT_NULL; /* No more event control blocks */ + return (pevent); + } + OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr; /* Adjust the free list */ + OS_EXIT_CRITICAL(); + pevent->OSEventType = OS_EVENT_TYPE_MUTEX; + pevent->OSEventCnt = (INT16U)((INT16U)prio << 8) | OS_MUTEX_AVAILABLE; /* Resource is avail. */ + pevent->OSEventPtr = (void *)0; /* No task owning the mutex */ +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; + pevent->OSEventName[1] = OS_ASCII_NUL; +#endif + OS_EventWaitListInit(pevent); + *perr = OS_ERR_NONE; + return (pevent); +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* DELETE A MUTEX +* +* Description: This function deletes a mutual exclusion semaphore and readies all tasks pending on the it. +* +* Arguments : pevent is a pointer to the event control block associated with the desired mutex. +* +* opt determines delete options as follows: +* opt == OS_DEL_NO_PEND Delete mutex ONLY if no task pending +* opt == OS_DEL_ALWAYS Deletes the mutex even if tasks are waiting. +* In this case, all the tasks pending will be readied. +* +* perr is a pointer to an error code that can contain one of the following values: +* OS_ERR_NONE The call was successful and the mutex was deleted +* OS_ERR_DEL_ISR If you attempted to delete the MUTEX from an ISR +* OS_ERR_INVALID_OPT An invalid option was specified +* OS_ERR_TASK_WAITING One or more tasks were waiting on the mutex +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a mutex +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +* +* Returns : pevent upon error +* (OS_EVENT *)0 if the mutex was successfully deleted. +* +* Note(s) : 1) This function must be used with care. Tasks that would normally expect the presence of +* the mutex MUST check the return code of OSMutexPend(). +* +* 2) This call can potentially disable interrupts for a long time. The interrupt disable +* time is directly proportional to the number of tasks waiting on the mutex. +* +* 3) Because ALL tasks pending on the mutex will be readied, you MUST be careful because the +* resource(s) will no longer be guarded by the mutex. +* +* 4) IMPORTANT: In the 'OS_DEL_ALWAYS' case, we assume that the owner of the Mutex (if there +* is one) is ready-to-run and is thus NOT pending on another kernel object or +* has delayed itself. In other words, if a task owns the mutex being deleted, +* that task will be made ready-to-run at its original priority. +********************************************************************************************************* +*/ + +#if OS_MUTEX_DEL_EN +OS_EVENT *OSMutexDel (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + BOOLEAN tasks_waiting; + OS_EVENT *pevent_return; + INT8U pip; /* Priority inheritance priority */ + INT8U prio; + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (pevent); + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return (pevent); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return (pevent); + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_DEL_ISR; /* ... can't DELETE from an ISR */ + return (pevent); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any tasks waiting on mutex */ + tasks_waiting = OS_TRUE; /* Yes */ + } else { + tasks_waiting = OS_FALSE; /* No */ + } + switch (opt) { + case OS_DEL_NO_PEND: /* DELETE MUTEX ONLY IF NO TASK WAITING --- */ + if (tasks_waiting == OS_FALSE) { +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + pevent->OSEventName[1] = OS_ASCII_NUL; +#endif + pip = (INT8U)(pevent->OSEventCnt >> 8); + OSTCBPrioTbl[pip] = (OS_TCB *)0; /* Free up the PIP */ + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + pevent->OSEventCnt = 0; + OSEventFreeList = pevent; + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + pevent_return = (OS_EVENT *)0; /* Mutex has been deleted */ + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_WAITING; + pevent_return = pevent; + } + break; + + case OS_DEL_ALWAYS: /* ALWAYS DELETE THE MUTEX ---------------- */ + pip = (INT8U)(pevent->OSEventCnt >> 8); /* Get PIP of mutex */ + prio = (INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8); /* Get owner's original prio */ + ptcb = (OS_TCB *)pevent->OSEventPtr; + if (ptcb != (OS_TCB *)0) { /* See if any task owns the mutex */ + if (ptcb->OSTCBPrio == pip) { /* See if original prio was changed */ + OSMutex_RdyAtPrio(ptcb, prio); /* Yes, Restore the task's original prio */ + } + } + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for mutex */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_MUTEX, OS_STAT_PEND_OK); + } +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + pevent->OSEventName[1] = OS_ASCII_NUL; +#endif + pip = (INT8U)(pevent->OSEventCnt >> 8); + OSTCBPrioTbl[pip] = (OS_TCB *)0; /* Free up the PIP */ + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + pevent->OSEventCnt = 0; + OSEventFreeList = pevent; /* Get next free event control block */ + OS_EXIT_CRITICAL(); + if (tasks_waiting == OS_TRUE) { /* Reschedule only if task(s) were waiting */ + OS_Sched(); /* Find highest priority task ready to run */ + } + *perr = OS_ERR_NONE; + pevent_return = (OS_EVENT *)0; /* Mutex has been deleted */ + break; + + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_INVALID_OPT; + pevent_return = pevent; + break; + } + return (pevent_return); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* PEND ON MUTUAL EXCLUSION SEMAPHORE +* +* Description: This function waits for a mutual exclusion semaphore. +* +* Arguments : pevent is a pointer to the event control block associated with the desired +* mutex. +* +* timeout is an optional timeout period (in clock ticks). If non-zero, your task will +* wait for the resource up to the amount of time specified by this argument. +* If you specify 0, however, your task will wait forever at the specified +* mutex or, until the resource becomes available. +* +* perr is a pointer to where an error message will be deposited. Possible error +* messages are: +* OS_ERR_NONE The call was successful and your task owns the mutex +* OS_ERR_TIMEOUT The mutex was not available within the specified 'timeout'. +* OS_ERR_PEND_ABORT The wait on the mutex was aborted. +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a mutex +* OS_ERR_PEVENT_NULL 'pevent' is a NULL pointer +* OS_ERR_PEND_ISR If you called this function from an ISR and the result +* would lead to a suspension. +* OS_ERR_PIP_LOWER If the priority of the task that owns the Mutex is +* HIGHER (i.e. a lower number) than the PIP. This error +* indicates that you did not set the PIP higher (lower +* number) than ALL the tasks that compete for the Mutex. +* Unfortunately, this is something that could not be +* detected when the Mutex is created because we don't know +* what tasks will be using the Mutex. +* OS_ERR_PEND_LOCKED If you called this function when the scheduler is locked +* +* Returns : none +* +* Note(s) : 1) The task that owns the Mutex MUST NOT pend on any other event while it owns the mutex. +* +* 2) You MUST NOT change the priority of the task that owns the mutex +********************************************************************************************************* +*/ + +void OSMutexPend (OS_EVENT *pevent, INT16U timeout, INT8U *perr) +{ + INT8U pip; /* Priority Inheritance Priority (PIP) */ + INT8U mprio; /* Mutex owner priority */ + BOOLEAN rdy; /* Flag indicating task was ready */ + OS_TCB *ptcb; + OS_EVENT *pevent2; + INT8U y; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return; + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return; + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return; + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + return; + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + return; + } +/*$PAGE*/ + OS_ENTER_CRITICAL(); + pip = (INT8U)(pevent->OSEventCnt >> 8); /* Get PIP from mutex */ + /* Is Mutex available? */ + if ((INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8) == OS_MUTEX_AVAILABLE) { + pevent->OSEventCnt &= OS_MUTEX_KEEP_UPPER_8; /* Yes, Acquire the resource */ + pevent->OSEventCnt |= OSTCBCur->OSTCBPrio; /* Save priority of owning task */ + pevent->OSEventPtr = (void *)OSTCBCur; /* Point to owning task's OS_TCB */ + if (OSTCBCur->OSTCBPrio <= pip) { /* PIP 'must' have a SMALLER prio ... */ + OS_EXIT_CRITICAL(); /* ... than current task! */ + *perr = OS_ERR_PIP_LOWER; + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + } + return; + } + mprio = (INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8); /* No, Get priority of mutex owner */ + ptcb = (OS_TCB *)(pevent->OSEventPtr); /* Point to TCB of mutex owner */ + if (ptcb->OSTCBPrio > pip) { /* Need to promote prio of owner?*/ + if (mprio > OSTCBCur->OSTCBPrio) { + y = ptcb->OSTCBY; + if ((OSRdyTbl[y] & ptcb->OSTCBBitX) != 0) { /* See if mutex owner is ready */ + OSRdyTbl[y] &= ~ptcb->OSTCBBitX; /* Yes, Remove owner from Rdy ...*/ + if (OSRdyTbl[y] == 0) { /* ... list at current prio */ + OSRdyGrp &= ~ptcb->OSTCBBitY; + } + rdy = OS_TRUE; + } else { + pevent2 = ptcb->OSTCBEventPtr; + if (pevent2 != (OS_EVENT *)0) { /* Remove from event wait list */ + if ((pevent2->OSEventTbl[ptcb->OSTCBY] &= ~ptcb->OSTCBBitX) == 0) { + pevent2->OSEventGrp &= ~ptcb->OSTCBBitY; + } + } + rdy = OS_FALSE; /* No */ + } + ptcb->OSTCBPrio = pip; /* Change owner task prio to PIP */ +#if OS_LOWEST_PRIO <= 63 + ptcb->OSTCBY = (INT8U)( ptcb->OSTCBPrio >> 3); + ptcb->OSTCBX = (INT8U)( ptcb->OSTCBPrio & 0x07); + ptcb->OSTCBBitY = (INT8U)(1 << ptcb->OSTCBY); + ptcb->OSTCBBitX = (INT8U)(1 << ptcb->OSTCBX); +#else + ptcb->OSTCBY = (INT8U)((ptcb->OSTCBPrio >> 4) & 0xFF); + ptcb->OSTCBX = (INT8U)( ptcb->OSTCBPrio & 0x0F); + ptcb->OSTCBBitY = (INT16U)(1 << ptcb->OSTCBY); + ptcb->OSTCBBitX = (INT16U)(1 << ptcb->OSTCBX); +#endif + if (rdy == OS_TRUE) { /* If task was ready at owner's priority ...*/ + OSRdyGrp |= ptcb->OSTCBBitY; /* ... make it ready at new priority. */ + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + } else { + pevent2 = ptcb->OSTCBEventPtr; + if (pevent2 != (OS_EVENT *)0) { /* Add to event wait list */ + pevent2->OSEventGrp |= ptcb->OSTCBBitY; + pevent2->OSEventTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + } + } + OSTCBPrioTbl[pip] = ptcb; + } + } + OSTCBCur->OSTCBStat |= OS_STAT_MUTEX; /* Mutex not available, pend current task */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + OSTCBCur->OSTCBDly = timeout; /* Store timeout in current task's TCB */ + OS_EventTaskWait(pevent); /* Suspend task until event or timeout occurs */ + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next highest priority task ready */ + OS_ENTER_CRITICAL(); + switch (OSTCBCur->OSTCBStatPend) { /* See if we timed-out or aborted */ + case OS_STAT_PEND_OK: + *perr = OS_ERR_NONE; + break; + + case OS_STAT_PEND_ABORT: + *perr = OS_ERR_PEND_ABORT; /* Indicate that we aborted getting mutex */ + break; + + case OS_STAT_PEND_TO: + default: + OS_EventTaskRemove(OSTCBCur, pevent); + *perr = OS_ERR_TIMEOUT; /* Indicate that we didn't get mutex within TO */ + break; + } + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Set task status to ready */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; /* Clear event pointers */ +#if (OS_EVENT_MULTI_EN > 0) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0; +#endif + OS_EXIT_CRITICAL(); +} +/*$PAGE*/ +/* +********************************************************************************************************* +* POST TO A MUTUAL EXCLUSION SEMAPHORE +* +* Description: This function signals a mutual exclusion semaphore +* +* Arguments : pevent is a pointer to the event control block associated with the desired +* mutex. +* +* Returns : OS_ERR_NONE The call was successful and the mutex was signaled. +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a mutex +* OS_ERR_PEVENT_NULL 'pevent' is a NULL pointer +* OS_ERR_POST_ISR Attempted to post from an ISR (not valid for MUTEXes) +* OS_ERR_NOT_MUTEX_OWNER The task that did the post is NOT the owner of the MUTEX. +* OS_ERR_PIP_LOWER If the priority of the new task that owns the Mutex is +* HIGHER (i.e. a lower number) than the PIP. This error +* indicates that you did not set the PIP higher (lower +* number) than ALL the tasks that compete for the Mutex. +* Unfortunately, this is something that could not be +* detected when the Mutex is created because we don't know +* what tasks will be using the Mutex. +********************************************************************************************************* +*/ + +INT8U OSMutexPost (OS_EVENT *pevent) +{ + INT8U pip; /* Priority inheritance priority */ + INT8U prio; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + return (OS_ERR_POST_ISR); /* ... can't POST mutex from an ISR */ + } +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + pip = (INT8U)(pevent->OSEventCnt >> 8); /* Get priority inheritance priority of mutex */ + prio = (INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8); /* Get owner's original priority */ + if (OSTCBCur != (OS_TCB *)pevent->OSEventPtr) { /* See if posting task owns the MUTEX */ + OS_EXIT_CRITICAL(); + return (OS_ERR_NOT_MUTEX_OWNER); + } + if (OSTCBCur->OSTCBPrio == pip) { /* Did we have to raise current task's priority? */ + OSMutex_RdyAtPrio(OSTCBCur, prio); /* Restore the task's original priority */ + } + OSTCBPrioTbl[pip] = OS_TCB_RESERVED; /* Reserve table entry */ + if (pevent->OSEventGrp != 0) { /* Any task waiting for the mutex? */ + /* Yes, Make HPT waiting for mutex ready */ + prio = OS_EventTaskRdy(pevent, (void *)0, OS_STAT_MUTEX, OS_STAT_PEND_OK); + pevent->OSEventCnt &= OS_MUTEX_KEEP_UPPER_8; /* Save priority of mutex's new owner */ + pevent->OSEventCnt |= prio; + pevent->OSEventPtr = OSTCBPrioTbl[prio]; /* Link to new mutex owner's OS_TCB */ + if (prio <= pip) { /* PIP 'must' have a SMALLER prio ... */ + OS_EXIT_CRITICAL(); /* ... than current task! */ + OS_Sched(); /* Find highest priority task ready to run */ + return (OS_ERR_PIP_LOWER); + } else { + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find highest priority task ready to run */ + return (OS_ERR_NONE); + } + } + pevent->OSEventCnt |= OS_MUTEX_AVAILABLE; /* No, Mutex is now available */ + pevent->OSEventPtr = (void *)0; + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +/*$PAGE*/ +/* +********************************************************************************************************* +* QUERY A MUTUAL EXCLUSION SEMAPHORE +* +* Description: This function obtains information about a mutex +* +* Arguments : pevent is a pointer to the event control block associated with the desired mutex +* +* p_mutex_data is a pointer to a structure that will contain information about the mutex +* +* Returns : OS_ERR_NONE The call was successful and the message was sent +* OS_ERR_QUERY_ISR If you called this function from an ISR +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer +* OS_ERR_PDATA_NULL If 'p_mutex_data' is a NULL pointer +* OS_ERR_EVENT_TYPE If you are attempting to obtain data from a non mutex. +********************************************************************************************************* +*/ + +#if OS_MUTEX_QUERY_EN > 0 +INT8U OSMutexQuery (OS_EVENT *pevent, OS_MUTEX_DATA *p_mutex_data) +{ + INT8U i; +#if OS_LOWEST_PRIO <= 63 + INT8U *psrc; + INT8U *pdest; +#else + INT16U *psrc; + INT16U *pdest; +#endif +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + return (OS_ERR_QUERY_ISR); /* ... can't QUERY mutex from an ISR */ + } +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } + if (p_mutex_data == (OS_MUTEX_DATA *)0) { /* Validate 'p_mutex_data' */ + return (OS_ERR_PDATA_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + p_mutex_data->OSMutexPIP = (INT8U)(pevent->OSEventCnt >> 8); + p_mutex_data->OSOwnerPrio = (INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8); + if (p_mutex_data->OSOwnerPrio == 0xFF) { + p_mutex_data->OSValue = OS_TRUE; + } else { + p_mutex_data->OSValue = OS_FALSE; + } + p_mutex_data->OSEventGrp = pevent->OSEventGrp; /* Copy wait list */ + psrc = &pevent->OSEventTbl[0]; + pdest = &p_mutex_data->OSEventTbl[0]; + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + *pdest++ = *psrc++; + } + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +#endif /* OS_MUTEX_QUERY_EN */ + +/*$PAGE*/ +/* +********************************************************************************************************* +* RESTORE A TASK BACK TO ITS ORIGINAL PRIORITY +* +* Description: This function makes a task ready at the specified priority +* +* Arguments : ptcb is a pointer to OS_TCB of the task to make ready +* +* prio is the desired priority +* +* Returns : none +********************************************************************************************************* +*/ + +static void OSMutex_RdyAtPrio (OS_TCB *ptcb, INT8U prio) +{ + INT8U y; + + + y = ptcb->OSTCBY; /* Remove owner from ready list at 'pip' */ + OSRdyTbl[y] &= ~ptcb->OSTCBBitX; + if (OSRdyTbl[y] == 0) { + OSRdyGrp &= ~ptcb->OSTCBBitY; + } + ptcb->OSTCBPrio = prio; +#if OS_LOWEST_PRIO <= 63 + ptcb->OSTCBY = (INT8U)((prio >> (INT8U)3) & (INT8U)0x07); + ptcb->OSTCBX = (INT8U) (prio & (INT8U)0x07); + ptcb->OSTCBBitY = (INT8U)(1 << ptcb->OSTCBY); + ptcb->OSTCBBitX = (INT8U)(1 << ptcb->OSTCBX); +#else + ptcb->OSTCBY = (INT8U)((prio >> (INT8U)4) & (INT8U)0x0F); + ptcb->OSTCBX = (INT8U) (prio & (INT8U)0x0F); + ptcb->OSTCBBitY = (INT16U)(1 << ptcb->OSTCBY); + ptcb->OSTCBBitX = (INT16U)(1 << ptcb->OSTCBX); +#endif + OSRdyGrp |= ptcb->OSTCBBitY; /* Make task ready at original priority */ + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + OSTCBPrioTbl[prio] = ptcb; +} + + +#endif /* OS_MUTEX_EN */ diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/os_q.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_q.c new file mode 100644 index 0000000..4d3c8a7 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_q.c @@ -0,0 +1,868 @@ +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* MESSAGE QUEUE MANAGEMENT +* +* (c) Copyright 1992-2007, Micrium, Weston, FL +* All Rights Reserved +* +* File : OS_Q.C +* By : Jean J. Labrosse +* Version : V2.86 +* +* LICENSING TERMS: +* --------------- +* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. +* If you plan on using uC/OS-II in a commercial product you need to contact Micriµm to properly license +* its use in your product. We provide ALL the source code for your convenience and to help you experience +* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a +* licensing fee. +********************************************************************************************************* +*/ + +#ifndef OS_MASTER_FILE +#include +#endif + +#if (OS_Q_EN > 0) && (OS_MAX_QS > 0) +/* +********************************************************************************************************* +* ACCEPT MESSAGE FROM QUEUE +* +* Description: This function checks the queue to see if a message is available. Unlike OSQPend(), +* OSQAccept() does not suspend the calling task if a message is not available. +* +* Arguments : pevent is a pointer to the event control block +* +* perr is a pointer to where an error message will be deposited. Possible error +* messages are: +* +* OS_ERR_NONE The call was successful and your task received a +* message. +* OS_ERR_EVENT_TYPE You didn't pass a pointer to a queue +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer +* OS_ERR_Q_EMPTY The queue did not contain any messages +* +* Returns : != (void *)0 is the message in the queue if one is available. The message is removed +* from the so the next time OSQAccept() is called, the queue will contain +* one less entry. +* == (void *)0 if you received a NULL pointer message +* if the queue is empty or, +* if 'pevent' is a NULL pointer or, +* if you passed an invalid event type +* +* Note(s) : As of V2.60, you can now pass NULL pointers through queues. Because of this, the argument +* 'perr' has been added to the API to tell you about the outcome of the call. +********************************************************************************************************* +*/ + +#if OS_Q_ACCEPT_EN > 0 +void *OSQAccept (OS_EVENT *pevent, INT8U *perr) +{ + void *pmsg; + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return ((void *)0); + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return ((void *)0); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) {/* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return ((void *)0); + } + OS_ENTER_CRITICAL(); + pq = (OS_Q *)pevent->OSEventPtr; /* Point at queue control block */ + if (pq->OSQEntries > 0) { /* See if any messages in the queue */ + pmsg = *pq->OSQOut++; /* Yes, extract oldest message from the queue */ + pq->OSQEntries--; /* Update the number of entries in the queue */ + if (pq->OSQOut == pq->OSQEnd) { /* Wrap OUT pointer if we are at the end of the queue */ + pq->OSQOut = pq->OSQStart; + } + *perr = OS_ERR_NONE; + } else { + *perr = OS_ERR_Q_EMPTY; + pmsg = (void *)0; /* Queue is empty */ + } + OS_EXIT_CRITICAL(); + return (pmsg); /* Return message received (or NULL) */ +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* CREATE A MESSAGE QUEUE +* +* Description: This function creates a message queue if free event control blocks are available. +* +* Arguments : start is a pointer to the base address of the message queue storage area. The +* storage area MUST be declared as an array of pointers to 'void' as follows +* +* void *MessageStorage[size] +* +* size is the number of elements in the storage area +* +* Returns : != (OS_EVENT *)0 is a pointer to the event control clock (OS_EVENT) associated with the +* created queue +* == (OS_EVENT *)0 if no event control blocks were available or an error was detected +********************************************************************************************************* +*/ + +OS_EVENT *OSQCreate (void **start, INT16U size) +{ + OS_EVENT *pevent; + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + return ((OS_EVENT *)0); /* ... can't CREATE from an ISR */ + } + OS_ENTER_CRITICAL(); + pevent = OSEventFreeList; /* Get next free event control block */ + if (OSEventFreeList != (OS_EVENT *)0) { /* See if pool of free ECB pool was empty */ + OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr; + } + OS_EXIT_CRITICAL(); + if (pevent != (OS_EVENT *)0) { /* See if we have an event control block */ + OS_ENTER_CRITICAL(); + pq = OSQFreeList; /* Get a free queue control block */ + if (pq != (OS_Q *)0) { /* Were we able to get a queue control block ? */ + OSQFreeList = OSQFreeList->OSQPtr; /* Yes, Adjust free list pointer to next free*/ + OS_EXIT_CRITICAL(); + pq->OSQStart = start; /* Initialize the queue */ + pq->OSQEnd = &start[size]; + pq->OSQIn = start; + pq->OSQOut = start; + pq->OSQSize = size; + pq->OSQEntries = 0; + pevent->OSEventType = OS_EVENT_TYPE_Q; + pevent->OSEventCnt = 0; + pevent->OSEventPtr = pq; +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + pevent->OSEventName[1] = OS_ASCII_NUL; +#endif + OS_EventWaitListInit(pevent); /* Initalize the wait list */ + } else { + pevent->OSEventPtr = (void *)OSEventFreeList; /* No, Return event control block on error */ + OSEventFreeList = pevent; + OS_EXIT_CRITICAL(); + pevent = (OS_EVENT *)0; + } + } + return (pevent); +} +/*$PAGE*/ +/* +********************************************************************************************************* +* DELETE A MESSAGE QUEUE +* +* Description: This function deletes a message queue and readies all tasks pending on the queue. +* +* Arguments : pevent is a pointer to the event control block associated with the desired +* queue. +* +* opt determines delete options as follows: +* opt == OS_DEL_NO_PEND Delete the queue ONLY if no task pending +* opt == OS_DEL_ALWAYS Deletes the queue even if tasks are waiting. +* In this case, all the tasks pending will be readied. +* +* perr is a pointer to an error code that can contain one of the following values: +* OS_ERR_NONE The call was successful and the queue was deleted +* OS_ERR_DEL_ISR If you tried to delete the queue from an ISR +* OS_ERR_INVALID_OPT An invalid option was specified +* OS_ERR_TASK_WAITING One or more tasks were waiting on the queue +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a queue +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +* +* Returns : pevent upon error +* (OS_EVENT *)0 if the queue was successfully deleted. +* +* Note(s) : 1) This function must be used with care. Tasks that would normally expect the presence of +* the queue MUST check the return code of OSQPend(). +* 2) OSQAccept() callers will not know that the intended queue has been deleted unless +* they check 'pevent' to see that it's a NULL pointer. +* 3) This call can potentially disable interrupts for a long time. The interrupt disable +* time is directly proportional to the number of tasks waiting on the queue. +* 4) Because ALL tasks pending on the queue will be readied, you MUST be careful in +* applications where the queue is used for mutual exclusion because the resource(s) +* will no longer be guarded by the queue. +* 5) If the storage for the message queue was allocated dynamically (i.e. using a malloc() +* type call) then your application MUST release the memory storage by call the counterpart +* call of the dynamic allocation scheme used. If the queue storage was created statically +* then, the storage can be reused. +********************************************************************************************************* +*/ + +#if OS_Q_DEL_EN > 0 +OS_EVENT *OSQDel (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + BOOLEAN tasks_waiting; + OS_EVENT *pevent_return; + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (pevent); + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return (pevent); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return (pevent); + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_DEL_ISR; /* ... can't DELETE from an ISR */ + return (pevent); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any tasks waiting on queue */ + tasks_waiting = OS_TRUE; /* Yes */ + } else { + tasks_waiting = OS_FALSE; /* No */ + } + switch (opt) { + case OS_DEL_NO_PEND: /* Delete queue only if no task waiting */ + if (tasks_waiting == OS_FALSE) { +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + pevent->OSEventName[1] = OS_ASCII_NUL; +#endif + pq = (OS_Q *)pevent->OSEventPtr; /* Return OS_Q to free list */ + pq->OSQPtr = OSQFreeList; + OSQFreeList = pq; + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + pevent->OSEventCnt = 0; + OSEventFreeList = pevent; /* Get next free event control block */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + pevent_return = (OS_EVENT *)0; /* Queue has been deleted */ + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_WAITING; + pevent_return = pevent; + } + break; + + case OS_DEL_ALWAYS: /* Always delete the queue */ + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for queue */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_OK); + } +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + pevent->OSEventName[1] = OS_ASCII_NUL; +#endif + pq = (OS_Q *)pevent->OSEventPtr; /* Return OS_Q to free list */ + pq->OSQPtr = OSQFreeList; + OSQFreeList = pq; + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + pevent->OSEventCnt = 0; + OSEventFreeList = pevent; /* Get next free event control block */ + OS_EXIT_CRITICAL(); + if (tasks_waiting == OS_TRUE) { /* Reschedule only if task(s) were waiting */ + OS_Sched(); /* Find highest priority task ready to run */ + } + *perr = OS_ERR_NONE; + pevent_return = (OS_EVENT *)0; /* Queue has been deleted */ + break; + + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_INVALID_OPT; + pevent_return = pevent; + break; + } + return (pevent_return); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* FLUSH QUEUE +* +* Description : This function is used to flush the contents of the message queue. +* +* Arguments : none +* +* Returns : OS_ERR_NONE upon success +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a queue +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer +* +* WARNING : You should use this function with great care because, when to flush the queue, you LOOSE +* the references to what the queue entries are pointing to and thus, you could cause +* 'memory leaks'. In other words, the data you are pointing to that's being referenced +* by the queue entries should, most likely, need to be de-allocated (i.e. freed). +********************************************************************************************************* +*/ + +#if OS_Q_FLUSH_EN > 0 +INT8U OSQFlush (OS_EVENT *pevent) +{ + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } +#endif + OS_ENTER_CRITICAL(); + pq = (OS_Q *)pevent->OSEventPtr; /* Point to queue storage structure */ + pq->OSQIn = pq->OSQStart; + pq->OSQOut = pq->OSQStart; + pq->OSQEntries = 0; + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* PEND ON A QUEUE FOR A MESSAGE +* +* Description: This function waits for a message to be sent to a queue +* +* Arguments : pevent is a pointer to the event control block associated with the desired queue +* +* timeout is an optional timeout period (in clock ticks). If non-zero, your task will +* wait for a message to arrive at the queue up to the amount of time +* specified by this argument. If you specify 0, however, your task will wait +* forever at the specified queue or, until a message arrives. +* +* perr is a pointer to where an error message will be deposited. Possible error +* messages are: +* +* OS_ERR_NONE The call was successful and your task received a +* message. +* OS_ERR_TIMEOUT A message was not received within the specified 'timeout'. +* OS_ERR_PEND_ABORT The wait on the queue was aborted. +* OS_ERR_EVENT_TYPE You didn't pass a pointer to a queue +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer +* OS_ERR_PEND_ISR If you called this function from an ISR and the result +* would lead to a suspension. +* OS_ERR_PEND_LOCKED If you called this function with the scheduler is locked +* +* Returns : != (void *)0 is a pointer to the message received +* == (void *)0 if you received a NULL pointer message or, +* if no message was received or, +* if 'pevent' is a NULL pointer or, +* if you didn't pass a pointer to a queue. +* +* Note(s) : As of V2.60, this function allows you to receive NULL pointer messages. +********************************************************************************************************* +*/ + +void *OSQPend (OS_EVENT *pevent, INT16U timeout, INT8U *perr) +{ + void *pmsg; + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return ((void *)0); + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return ((void *)0); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) {/* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return ((void *)0); + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + return ((void *)0); + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + return ((void *)0); + } + OS_ENTER_CRITICAL(); + pq = (OS_Q *)pevent->OSEventPtr; /* Point at queue control block */ + if (pq->OSQEntries > 0) { /* See if any messages in the queue */ + pmsg = *pq->OSQOut++; /* Yes, extract oldest message from the queue */ + pq->OSQEntries--; /* Update the number of entries in the queue */ + if (pq->OSQOut == pq->OSQEnd) { /* Wrap OUT pointer if we are at the end of the queue */ + pq->OSQOut = pq->OSQStart; + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (pmsg); /* Return message received */ + } + OSTCBCur->OSTCBStat |= OS_STAT_Q; /* Task will have to pend for a message to be posted */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + OSTCBCur->OSTCBDly = timeout; /* Load timeout into TCB */ + OS_EventTaskWait(pevent); /* Suspend task until event or timeout occurs */ + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next highest priority task ready to run */ + OS_ENTER_CRITICAL(); + switch (OSTCBCur->OSTCBStatPend) { /* See if we timed-out or aborted */ + case OS_STAT_PEND_OK: /* Extract message from TCB (Put there by QPost) */ + pmsg = OSTCBCur->OSTCBMsg; + *perr = OS_ERR_NONE; + break; + + case OS_STAT_PEND_ABORT: + pmsg = (void *)0; + *perr = OS_ERR_PEND_ABORT; /* Indicate that we aborted */ + break; + + case OS_STAT_PEND_TO: + default: + OS_EventTaskRemove(OSTCBCur, pevent); + pmsg = (void *)0; + *perr = OS_ERR_TIMEOUT; /* Indicate that we didn't get event within TO */ + break; + } + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Set task status to ready */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; /* Clear event pointers */ +#if (OS_EVENT_MULTI_EN > 0) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0; +#endif + OSTCBCur->OSTCBMsg = (void *)0; /* Clear received message */ + OS_EXIT_CRITICAL(); + return (pmsg); /* Return received message */ +} +/*$PAGE*/ +/* +********************************************************************************************************* +* ABORT WAITING ON A MESSAGE QUEUE +* +* Description: This function aborts & readies any tasks currently waiting on a queue. This function +* should be used to fault-abort the wait on the queue, rather than to normally signal +* the queue via OSQPost(), OSQPostFront() or OSQPostOpt(). +* +* Arguments : pevent is a pointer to the event control block associated with the desired queue. +* +* opt determines the type of ABORT performed: +* OS_PEND_OPT_NONE ABORT wait for a single task (HPT) waiting on the +* queue +* OS_PEND_OPT_BROADCAST ABORT wait for ALL tasks that are waiting on the +* queue +* +* perr is a pointer to where an error message will be deposited. Possible error +* messages are: +* +* OS_ERR_NONE No tasks were waiting on the queue. +* OS_ERR_PEND_ABORT At least one task waiting on the queue was readied +* and informed of the aborted wait; check return value +* for the number of tasks whose wait on the queue +* was aborted. +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a queue. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +* +* Returns : == 0 if no tasks were waiting on the queue, or upon error. +* > 0 if one or more tasks waiting on the queue are now readied and informed. +********************************************************************************************************* +*/ + +#if OS_Q_PEND_ABORT_EN > 0 +INT8U OSQPendAbort (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + INT8U nbr_tasks; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (0); + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return (0); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return (0); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any task waiting on queue? */ + nbr_tasks = 0; + switch (opt) { + case OS_PEND_OPT_BROADCAST: /* Do we need to abort ALL waiting tasks? */ + while (pevent->OSEventGrp != 0) { /* Yes, ready ALL tasks waiting on queue */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_ABORT); + nbr_tasks++; + } + break; + + case OS_PEND_OPT_NONE: + default: /* No, ready HPT waiting on queue */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_ABORT); + nbr_tasks++; + break; + } + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find HPT ready to run */ + *perr = OS_ERR_PEND_ABORT; + return (nbr_tasks); + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (0); /* No tasks waiting on queue */ +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* POST MESSAGE TO A QUEUE +* +* Description: This function sends a message to a queue +* +* Arguments : pevent is a pointer to the event control block associated with the desired queue +* +* pmsg is a pointer to the message to send. +* +* Returns : OS_ERR_NONE The call was successful and the message was sent +* OS_ERR_Q_FULL If the queue cannot accept any more messages because it is full. +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a queue. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer +* +* Note(s) : As of V2.60, this function allows you to send NULL pointer messages. +********************************************************************************************************* +*/ + +#if OS_Q_POST_EN > 0 +INT8U OSQPost (OS_EVENT *pevent, void *pmsg) +{ + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any task pending on queue */ + /* Ready highest priority task waiting on event */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find highest priority task ready to run */ + return (OS_ERR_NONE); + } + pq = (OS_Q *)pevent->OSEventPtr; /* Point to queue control block */ + if (pq->OSQEntries >= pq->OSQSize) { /* Make sure queue is not full */ + OS_EXIT_CRITICAL(); + return (OS_ERR_Q_FULL); + } + *pq->OSQIn++ = pmsg; /* Insert message into queue */ + pq->OSQEntries++; /* Update the nbr of entries in the queue */ + if (pq->OSQIn == pq->OSQEnd) { /* Wrap IN ptr if we are at end of queue */ + pq->OSQIn = pq->OSQStart; + } + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* POST MESSAGE TO THE FRONT OF A QUEUE +* +* Description: This function sends a message to a queue but unlike OSQPost(), the message is posted at +* the front instead of the end of the queue. Using OSQPostFront() allows you to send +* 'priority' messages. +* +* Arguments : pevent is a pointer to the event control block associated with the desired queue +* +* pmsg is a pointer to the message to send. +* +* Returns : OS_ERR_NONE The call was successful and the message was sent +* OS_ERR_Q_FULL If the queue cannot accept any more messages because it is full. +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a queue. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer +* +* Note(s) : As of V2.60, this function allows you to send NULL pointer messages. +********************************************************************************************************* +*/ + +#if OS_Q_POST_FRONT_EN > 0 +INT8U OSQPostFront (OS_EVENT *pevent, void *pmsg) +{ + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any task pending on queue */ + /* Ready highest priority task waiting on event */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find highest priority task ready to run */ + return (OS_ERR_NONE); + } + pq = (OS_Q *)pevent->OSEventPtr; /* Point to queue control block */ + if (pq->OSQEntries >= pq->OSQSize) { /* Make sure queue is not full */ + OS_EXIT_CRITICAL(); + return (OS_ERR_Q_FULL); + } + if (pq->OSQOut == pq->OSQStart) { /* Wrap OUT ptr if we are at the 1st queue entry */ + pq->OSQOut = pq->OSQEnd; + } + pq->OSQOut--; + *pq->OSQOut = pmsg; /* Insert message into queue */ + pq->OSQEntries++; /* Update the nbr of entries in the queue */ + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* POST MESSAGE TO A QUEUE +* +* Description: This function sends a message to a queue. This call has been added to reduce code size +* since it can replace both OSQPost() and OSQPostFront(). Also, this function adds the +* capability to broadcast a message to ALL tasks waiting on the message queue. +* +* Arguments : pevent is a pointer to the event control block associated with the desired queue +* +* pmsg is a pointer to the message to send. +* +* opt determines the type of POST performed: +* OS_POST_OPT_NONE POST to a single waiting task +* (Identical to OSQPost()) +* OS_POST_OPT_BROADCAST POST to ALL tasks that are waiting on the queue +* OS_POST_OPT_FRONT POST as LIFO (Simulates OSQPostFront()) +* OS_POST_OPT_NO_SCHED Indicates that the scheduler will NOT be invoked +* +* Returns : OS_ERR_NONE The call was successful and the message was sent +* OS_ERR_Q_FULL If the queue cannot accept any more messages because it is full. +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a queue. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer +* +* Warning : Interrupts can be disabled for a long time if you do a 'broadcast'. In fact, the +* interrupt disable time is proportional to the number of tasks waiting on the queue. +********************************************************************************************************* +*/ + +#if OS_Q_POST_OPT_EN > 0 +INT8U OSQPostOpt (OS_EVENT *pevent, void *pmsg, INT8U opt) +{ + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0x00) { /* See if any task pending on queue */ + if ((opt & OS_POST_OPT_BROADCAST) != 0x00) { /* Do we need to post msg to ALL waiting tasks ? */ + while (pevent->OSEventGrp != 0) { /* Yes, Post to ALL tasks waiting on queue */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + } + } else { /* No, Post to HPT waiting on queue */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + } + OS_EXIT_CRITICAL(); + if ((opt & OS_POST_OPT_NO_SCHED) == 0) { /* See if scheduler needs to be invoked */ + OS_Sched(); /* Find highest priority task ready to run */ + } + return (OS_ERR_NONE); + } + pq = (OS_Q *)pevent->OSEventPtr; /* Point to queue control block */ + if (pq->OSQEntries >= pq->OSQSize) { /* Make sure queue is not full */ + OS_EXIT_CRITICAL(); + return (OS_ERR_Q_FULL); + } + if ((opt & OS_POST_OPT_FRONT) != 0x00) { /* Do we post to the FRONT of the queue? */ + if (pq->OSQOut == pq->OSQStart) { /* Yes, Post as LIFO, Wrap OUT pointer if we ... */ + pq->OSQOut = pq->OSQEnd; /* ... are at the 1st queue entry */ + } + pq->OSQOut--; + *pq->OSQOut = pmsg; /* Insert message into queue */ + } else { /* No, Post as FIFO */ + *pq->OSQIn++ = pmsg; /* Insert message into queue */ + if (pq->OSQIn == pq->OSQEnd) { /* Wrap IN ptr if we are at end of queue */ + pq->OSQIn = pq->OSQStart; + } + } + pq->OSQEntries++; /* Update the nbr of entries in the queue */ + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* QUERY A MESSAGE QUEUE +* +* Description: This function obtains information about a message queue. +* +* Arguments : pevent is a pointer to the event control block associated with the desired queue +* +* p_q_data is a pointer to a structure that will contain information about the message +* queue. +* +* Returns : OS_ERR_NONE The call was successful and the message was sent +* OS_ERR_EVENT_TYPE If you are attempting to obtain data from a non queue. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer +* OS_ERR_PDATA_NULL If 'p_q_data' is a NULL pointer +********************************************************************************************************* +*/ + +#if OS_Q_QUERY_EN > 0 +INT8U OSQQuery (OS_EVENT *pevent, OS_Q_DATA *p_q_data) +{ + OS_Q *pq; + INT8U i; +#if OS_LOWEST_PRIO <= 63 + INT8U *psrc; + INT8U *pdest; +#else + INT16U *psrc; + INT16U *pdest; +#endif +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } + if (p_q_data == (OS_Q_DATA *)0) { /* Validate 'p_q_data' */ + return (OS_ERR_PDATA_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + p_q_data->OSEventGrp = pevent->OSEventGrp; /* Copy message queue wait list */ + psrc = &pevent->OSEventTbl[0]; + pdest = &p_q_data->OSEventTbl[0]; + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + *pdest++ = *psrc++; + } + pq = (OS_Q *)pevent->OSEventPtr; + if (pq->OSQEntries > 0) { + p_q_data->OSMsg = *pq->OSQOut; /* Get next message to return if available */ + } else { + p_q_data->OSMsg = (void *)0; + } + p_q_data->OSNMsgs = pq->OSQEntries; + p_q_data->OSQSize = pq->OSQSize; + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +#endif /* OS_Q_QUERY_EN */ + +/*$PAGE*/ +/* +********************************************************************************************************* +* QUEUE MODULE INITIALIZATION +* +* Description : This function is called by uC/OS-II to initialize the message queue module. Your +* application MUST NOT call this function. +* +* Arguments : none +* +* Returns : none +* +* Note(s) : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +void OS_QInit (void) +{ +#if OS_MAX_QS == 1 + OSQFreeList = &OSQTbl[0]; /* Only ONE queue! */ + OSQFreeList->OSQPtr = (OS_Q *)0; +#endif + +#if OS_MAX_QS >= 2 + INT16U i; + OS_Q *pq1; + OS_Q *pq2; + + + + OS_MemClr((INT8U *)&OSQTbl[0], sizeof(OSQTbl)); /* Clear the queue table */ + pq1 = &OSQTbl[0]; + pq2 = &OSQTbl[1]; + for (i = 0; i < (OS_MAX_QS - 1); i++) { /* Init. list of free QUEUE control blocks */ + pq1->OSQPtr = pq2; + pq1++; + pq2++; + } + pq1->OSQPtr = (OS_Q *)0; + OSQFreeList = &OSQTbl[0]; +#endif +} +#endif /* OS_Q_EN */ diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/os_sem.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_sem.c new file mode 100644 index 0000000..b8e159b --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_sem.c @@ -0,0 +1,609 @@ +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* SEMAPHORE MANAGEMENT +* +* (c) Copyright 1992-2007, Micrium, Weston, FL +* All Rights Reserved +* +* File : OS_SEM.C +* By : Jean J. Labrosse +* Version : V2.86 +* +* LICENSING TERMS: +* --------------- +* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. +* If you plan on using uC/OS-II in a commercial product you need to contact Micriµm to properly license +* its use in your product. We provide ALL the source code for your convenience and to help you experience +* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a +* licensing fee. +********************************************************************************************************* +*/ + +#ifndef OS_MASTER_FILE +#include +#endif + +#if OS_SEM_EN > 0 +/*$PAGE*/ +/* +********************************************************************************************************* +* ACCEPT SEMAPHORE +* +* Description: This function checks the semaphore to see if a resource is available or, if an event +* occurred. Unlike OSSemPend(), OSSemAccept() does not suspend the calling task if the +* resource is not available or the event did not occur. +* +* Arguments : pevent is a pointer to the event control block +* +* Returns : > 0 if the resource is available or the event did not occur the semaphore is +* decremented to obtain the resource. +* == 0 if the resource is not available or the event did not occur or, +* if 'pevent' is a NULL pointer or, +* if you didn't pass a pointer to a semaphore +********************************************************************************************************* +*/ + +#if OS_SEM_ACCEPT_EN > 0 +INT16U OSSemAccept (OS_EVENT *pevent) +{ + INT16U cnt; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (0); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + return (0); + } + OS_ENTER_CRITICAL(); + cnt = pevent->OSEventCnt; + if (cnt > 0) { /* See if resource is available */ + pevent->OSEventCnt--; /* Yes, decrement semaphore and notify caller */ + } + OS_EXIT_CRITICAL(); + return (cnt); /* Return semaphore count */ +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* CREATE A SEMAPHORE +* +* Description: This function creates a semaphore. +* +* Arguments : cnt is the initial value for the semaphore. If the value is 0, no resource is +* available (or no event has occurred). You initialize the semaphore to a +* non-zero value to specify how many resources are available (e.g. if you have +* 10 resources, you would initialize the semaphore to 10). +* +* Returns : != (void *)0 is a pointer to the event control block (OS_EVENT) associated with the +* created semaphore +* == (void *)0 if no event control blocks were available +********************************************************************************************************* +*/ + +OS_EVENT *OSSemCreate (INT16U cnt) +{ + OS_EVENT *pevent; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + return ((OS_EVENT *)0); /* ... can't CREATE from an ISR */ + } + OS_ENTER_CRITICAL(); + pevent = OSEventFreeList; /* Get next free event control block */ + if (OSEventFreeList != (OS_EVENT *)0) { /* See if pool of free ECB pool was empty */ + OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr; + } + OS_EXIT_CRITICAL(); + if (pevent != (OS_EVENT *)0) { /* Get an event control block */ + pevent->OSEventType = OS_EVENT_TYPE_SEM; + pevent->OSEventCnt = cnt; /* Set semaphore value */ + pevent->OSEventPtr = (void *)0; /* Unlink from ECB free list */ +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + pevent->OSEventName[1] = OS_ASCII_NUL; +#endif + OS_EventWaitListInit(pevent); /* Initialize to 'nobody waiting' on sem. */ + } + return (pevent); +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* DELETE A SEMAPHORE +* +* Description: This function deletes a semaphore and readies all tasks pending on the semaphore. +* +* Arguments : pevent is a pointer to the event control block associated with the desired +* semaphore. +* +* opt determines delete options as follows: +* opt == OS_DEL_NO_PEND Delete semaphore ONLY if no task pending +* opt == OS_DEL_ALWAYS Deletes the semaphore even if tasks are waiting. +* In this case, all the tasks pending will be readied. +* +* perr is a pointer to an error code that can contain one of the following values: +* OS_ERR_NONE The call was successful and the semaphore was deleted +* OS_ERR_DEL_ISR If you attempted to delete the semaphore from an ISR +* OS_ERR_INVALID_OPT An invalid option was specified +* OS_ERR_TASK_WAITING One or more tasks were waiting on the semaphore +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a semaphore +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +* +* Returns : pevent upon error +* (OS_EVENT *)0 if the semaphore was successfully deleted. +* +* Note(s) : 1) This function must be used with care. Tasks that would normally expect the presence of +* the semaphore MUST check the return code of OSSemPend(). +* 2) OSSemAccept() callers will not know that the intended semaphore has been deleted unless +* they check 'pevent' to see that it's a NULL pointer. +* 3) This call can potentially disable interrupts for a long time. The interrupt disable +* time is directly proportional to the number of tasks waiting on the semaphore. +* 4) Because ALL tasks pending on the semaphore will be readied, you MUST be careful in +* applications where the semaphore is used for mutual exclusion because the resource(s) +* will no longer be guarded by the semaphore. +********************************************************************************************************* +*/ + +#if OS_SEM_DEL_EN > 0 +OS_EVENT *OSSemDel (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + BOOLEAN tasks_waiting; + OS_EVENT *pevent_return; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (pevent); + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return (pevent); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return (pevent); + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_DEL_ISR; /* ... can't DELETE from an ISR */ + return (pevent); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any tasks waiting on semaphore */ + tasks_waiting = OS_TRUE; /* Yes */ + } else { + tasks_waiting = OS_FALSE; /* No */ + } + switch (opt) { + case OS_DEL_NO_PEND: /* Delete semaphore only if no task waiting */ + if (tasks_waiting == OS_FALSE) { +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + pevent->OSEventName[1] = OS_ASCII_NUL; +#endif + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + pevent->OSEventCnt = 0; + OSEventFreeList = pevent; /* Get next free event control block */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + pevent_return = (OS_EVENT *)0; /* Semaphore has been deleted */ + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_WAITING; + pevent_return = pevent; + } + break; + + case OS_DEL_ALWAYS: /* Always delete the semaphore */ + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for semaphore */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_OK); + } +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + pevent->OSEventName[1] = OS_ASCII_NUL; +#endif + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + pevent->OSEventCnt = 0; + OSEventFreeList = pevent; /* Get next free event control block */ + OS_EXIT_CRITICAL(); + if (tasks_waiting == OS_TRUE) { /* Reschedule only if task(s) were waiting */ + OS_Sched(); /* Find highest priority task ready to run */ + } + *perr = OS_ERR_NONE; + pevent_return = (OS_EVENT *)0; /* Semaphore has been deleted */ + break; + + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_INVALID_OPT; + pevent_return = pevent; + break; + } + return (pevent_return); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* PEND ON SEMAPHORE +* +* Description: This function waits for a semaphore. +* +* Arguments : pevent is a pointer to the event control block associated with the desired +* semaphore. +* +* timeout is an optional timeout period (in clock ticks). If non-zero, your task will +* wait for the resource up to the amount of time specified by this argument. +* If you specify 0, however, your task will wait forever at the specified +* semaphore or, until the resource becomes available (or the event occurs). +* +* perr is a pointer to where an error message will be deposited. Possible error +* messages are: +* +* OS_ERR_NONE The call was successful and your task owns the resource +* or, the event you are waiting for occurred. +* OS_ERR_TIMEOUT The semaphore was not received within the specified +* 'timeout'. +* OS_ERR_PEND_ABORT The wait on the semaphore was aborted. +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a semaphore. +* OS_ERR_PEND_ISR If you called this function from an ISR and the result +* would lead to a suspension. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +* OS_ERR_PEND_LOCKED If you called this function when the scheduler is locked +* +* Returns : none +********************************************************************************************************* +*/ +/*$PAGE*/ +void OSSemPend (OS_EVENT *pevent, INT16U timeout, INT8U *perr) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return; + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return; + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return; + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + return; + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + return; + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventCnt > 0) { /* If sem. is positive, resource available ... */ + pevent->OSEventCnt--; /* ... decrement semaphore only if positive. */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return; + } + /* Otherwise, must wait until event occurs */ + OSTCBCur->OSTCBStat |= OS_STAT_SEM; /* Resource not available, pend on semaphore */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + OSTCBCur->OSTCBDly = timeout; /* Store pend timeout in TCB */ + OS_EventTaskWait(pevent); /* Suspend task until event or timeout occurs */ + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next highest priority task ready */ + OS_ENTER_CRITICAL(); + switch (OSTCBCur->OSTCBStatPend) { /* See if we timed-out or aborted */ + case OS_STAT_PEND_OK: + *perr = OS_ERR_NONE; + break; + + case OS_STAT_PEND_ABORT: + *perr = OS_ERR_PEND_ABORT; /* Indicate that we aborted */ + break; + + case OS_STAT_PEND_TO: + default: + OS_EventTaskRemove(OSTCBCur, pevent); + *perr = OS_ERR_TIMEOUT; /* Indicate that we didn't get event within TO */ + break; + } + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Set task status to ready */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; /* Clear event pointers */ +#if (OS_EVENT_MULTI_EN > 0) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0; +#endif + OS_EXIT_CRITICAL(); +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* ABORT WAITING ON A SEMAPHORE +* +* Description: This function aborts & readies any tasks currently waiting on a semaphore. This function +* should be used to fault-abort the wait on the semaphore, rather than to normally signal +* the semaphore via OSSemPost(). +* +* Arguments : pevent is a pointer to the event control block associated with the desired +* semaphore. +* +* opt determines the type of ABORT performed: +* OS_PEND_OPT_NONE ABORT wait for a single task (HPT) waiting on the +* semaphore +* OS_PEND_OPT_BROADCAST ABORT wait for ALL tasks that are waiting on the +* semaphore +* +* perr is a pointer to where an error message will be deposited. Possible error +* messages are: +* +* OS_ERR_NONE No tasks were waiting on the semaphore. +* OS_ERR_PEND_ABORT At least one task waiting on the semaphore was readied +* and informed of the aborted wait; check return value +* for the number of tasks whose wait on the semaphore +* was aborted. +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a semaphore. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +* +* Returns : == 0 if no tasks were waiting on the semaphore, or upon error. +* > 0 if one or more tasks waiting on the semaphore are now readied and informed. +********************************************************************************************************* +*/ + +#if OS_SEM_PEND_ABORT_EN > 0 +INT8U OSSemPendAbort (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + INT8U nbr_tasks; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (0); + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return (0); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return (0); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any task waiting on semaphore? */ + nbr_tasks = 0; + switch (opt) { + case OS_PEND_OPT_BROADCAST: /* Do we need to abort ALL waiting tasks? */ + while (pevent->OSEventGrp != 0) { /* Yes, ready ALL tasks waiting on semaphore */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_ABORT); + nbr_tasks++; + } + break; + + case OS_PEND_OPT_NONE: + default: /* No, ready HPT waiting on semaphore */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_ABORT); + nbr_tasks++; + break; + } + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find HPT ready to run */ + *perr = OS_ERR_PEND_ABORT; + return (nbr_tasks); + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (0); /* No tasks waiting on semaphore */ +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* POST TO A SEMAPHORE +* +* Description: This function signals a semaphore +* +* Arguments : pevent is a pointer to the event control block associated with the desired +* semaphore. +* +* Returns : OS_ERR_NONE The call was successful and the semaphore was signaled. +* OS_ERR_SEM_OVF If the semaphore count exceeded its limit. In other words, you have +* signalled the semaphore more often than you waited on it with either +* OSSemAccept() or OSSemPend(). +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a semaphore +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +********************************************************************************************************* +*/ + +INT8U OSSemPost (OS_EVENT *pevent) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any task waiting for semaphore */ + /* Ready HPT waiting on event */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_OK); + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find HPT ready to run */ + return (OS_ERR_NONE); + } + if (pevent->OSEventCnt < 65535u) { /* Make sure semaphore will not overflow */ + pevent->OSEventCnt++; /* Increment semaphore count to register event */ + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + } + OS_EXIT_CRITICAL(); /* Semaphore value has reached its maximum */ + return (OS_ERR_SEM_OVF); +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* QUERY A SEMAPHORE +* +* Description: This function obtains information about a semaphore +* +* Arguments : pevent is a pointer to the event control block associated with the desired +* semaphore +* +* p_sem_data is a pointer to a structure that will contain information about the +* semaphore. +* +* Returns : OS_ERR_NONE The call was successful and the message was sent +* OS_ERR_EVENT_TYPE If you are attempting to obtain data from a non semaphore. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +* OS_ERR_PDATA_NULL If 'p_sem_data' is a NULL pointer +********************************************************************************************************* +*/ + +#if OS_SEM_QUERY_EN > 0 +INT8U OSSemQuery (OS_EVENT *pevent, OS_SEM_DATA *p_sem_data) +{ +#if OS_LOWEST_PRIO <= 63 + INT8U *psrc; + INT8U *pdest; +#else + INT16U *psrc; + INT16U *pdest; +#endif + INT8U i; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } + if (p_sem_data == (OS_SEM_DATA *)0) { /* Validate 'p_sem_data' */ + return (OS_ERR_PDATA_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + p_sem_data->OSEventGrp = pevent->OSEventGrp; /* Copy message mailbox wait list */ + psrc = &pevent->OSEventTbl[0]; + pdest = &p_sem_data->OSEventTbl[0]; + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + *pdest++ = *psrc++; + } + p_sem_data->OSCnt = pevent->OSEventCnt; /* Get semaphore count */ + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +#endif /* OS_SEM_QUERY_EN */ + +/*$PAGE*/ +/* +********************************************************************************************************* +* SET SEMAPHORE +* +* Description: This function sets the semaphore count to the value specified as an argument. Typically, +* this value would be 0. +* +* You would typically use this function when a semaphore is used as a signaling mechanism +* and, you want to reset the count value. +* +* Arguments : pevent is a pointer to the event control block +* +* cnt is the new value for the semaphore count. You would pass 0 to reset the +* semaphore count. +* +* perr is a pointer to an error code returned by the function as follows: +* +* OS_ERR_NONE The call was successful and the semaphore value was set. +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a semaphore. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +* OS_ERR_TASK_WAITING If tasks are waiting on the semaphore. +********************************************************************************************************* +*/ + +#if OS_SEM_SET_EN > 0 +void OSSemSet (OS_EVENT *pevent, INT16U cnt, INT8U *perr) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return; + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return; + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return; + } + OS_ENTER_CRITICAL(); + *perr = OS_ERR_NONE; + if (pevent->OSEventCnt > 0) { /* See if semaphore already has a count */ + pevent->OSEventCnt = cnt; /* Yes, set it to the new value specified. */ + } else { /* No */ + if (pevent->OSEventGrp == 0) { /* See if task(s) waiting? */ + pevent->OSEventCnt = cnt; /* No, OK to set the value */ + } else { + *perr = OS_ERR_TASK_WAITING; + } + } + OS_EXIT_CRITICAL(); +} +#endif + +#endif /* OS_SEM_EN */ diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/os_task.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_task.c new file mode 100644 index 0000000..72bac53 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_task.c @@ -0,0 +1,1095 @@ +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* TASK MANAGEMENT +* +* (c) Copyright 1992-2007, Micrium, Weston, FL +* All Rights Reserved +* +* File : OS_TASK.C +* By : Jean J. Labrosse +* Version : V2.86 +* +* LICENSING TERMS: +* --------------- +* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. +* If you plan on using uC/OS-II in a commercial product you need to contact Micriµm to properly license +* its use in your product. We provide ALL the source code for your convenience and to help you experience +* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a +* licensing fee. +********************************************************************************************************* +*/ + +#ifndef OS_MASTER_FILE +#include +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* CHANGE PRIORITY OF A TASK +* +* Description: This function allows you to change the priority of a task dynamically. Note that the new +* priority MUST be available. +* +* Arguments : oldp is the old priority +* +* newp is the new priority +* +* Returns : OS_ERR_NONE is the call was successful +* OS_ERR_PRIO_INVALID if the priority you specify is higher that the maximum allowed +* (i.e. >= OS_LOWEST_PRIO) +* OS_ERR_PRIO_EXIST if the new priority already exist. +* OS_ERR_PRIO there is no task with the specified OLD priority (i.e. the OLD task does +* not exist. +* OS_ERR_TASK_NOT_EXIST if the task is assigned to a Mutex PIP. +********************************************************************************************************* +*/ + +#if OS_TASK_CHANGE_PRIO_EN > 0 +INT8U OSTaskChangePrio (INT8U oldprio, INT8U newprio) +{ +#if (OS_EVENT_EN) + OS_EVENT *pevent; +#if (OS_EVENT_MULTI_EN > 0) + OS_EVENT **pevents; +#endif +#endif + OS_TCB *ptcb; + INT8U y_new; + INT8U x_new; + INT8U y_old; +#if OS_LOWEST_PRIO <= 63 + INT8U bity_new; + INT8U bitx_new; + INT8U bity_old; + INT8U bitx_old; +#else + INT16U bity_new; + INT16U bitx_new; + INT16U bity_old; + INT16U bitx_old; +#endif +#if OS_CRITICAL_METHOD == 3 + OS_CPU_SR cpu_sr = 0; /* Storage for CPU status register */ +#endif + + +/*$PAGE*/ +#if OS_ARG_CHK_EN > 0 + if (oldprio >= OS_LOWEST_PRIO) { + if (oldprio != OS_PRIO_SELF) { + return (OS_ERR_PRIO_INVALID); + } + } + if (newprio >= OS_LOWEST_PRIO) { + return (OS_ERR_PRIO_INVALID); + } +#endif + OS_ENTER_CRITICAL(); + if (OSTCBPrioTbl[newprio] != (OS_TCB *)0) { /* New priority must not already exist */ + OS_EXIT_CRITICAL(); + return (OS_ERR_PRIO_EXIST); + } + if (oldprio == OS_PRIO_SELF) { /* See if changing self */ + oldprio = OSTCBCur->OSTCBPrio; /* Yes, get priority */ + } + ptcb = OSTCBPrioTbl[oldprio]; + if (ptcb == (OS_TCB *)0) { /* Does task to change exist? */ + OS_EXIT_CRITICAL(); /* No, can't change its priority! */ + return (OS_ERR_PRIO); + } + if (ptcb == OS_TCB_RESERVED) { /* Is task assigned to Mutex */ + OS_EXIT_CRITICAL(); /* No, can't change its priority! */ + return (OS_ERR_TASK_NOT_EXIST); + } +#if OS_LOWEST_PRIO <= 63 + y_new = (INT8U)(newprio >> 3); /* Yes, compute new TCB fields */ + x_new = (INT8U)(newprio & 0x07); + bity_new = (INT8U)(1 << y_new); + bitx_new = (INT8U)(1 << x_new); +#else + y_new = (INT8U)((newprio >> 4) & 0x0F); + x_new = (INT8U)( newprio & 0x0F); + bity_new = (INT16U)(1 << y_new); + bitx_new = (INT16U)(1 << x_new); +#endif + + OSTCBPrioTbl[oldprio] = (OS_TCB *)0; /* Remove TCB from old priority */ + OSTCBPrioTbl[newprio] = ptcb; /* Place pointer to TCB @ new priority */ + y_old = ptcb->OSTCBY; + bity_old = ptcb->OSTCBBitY; + bitx_old = ptcb->OSTCBBitX; + if ((OSRdyTbl[y_old] & bitx_old) != 0) { /* If task is ready make it not */ + OSRdyTbl[y_old] &= ~bitx_old; + if (OSRdyTbl[y_old] == 0) { + OSRdyGrp &= ~bity_old; + } + OSRdyGrp |= bity_new; /* Make new priority ready to run */ + OSRdyTbl[y_new] |= bitx_new; + } + +#if (OS_EVENT_EN) + pevent = ptcb->OSTCBEventPtr; + if (pevent != (OS_EVENT *)0) { + pevent->OSEventTbl[y_old] &= ~bitx_old; /* Remove old task prio from wait list */ + if (pevent->OSEventTbl[y_old] == 0) { + pevent->OSEventGrp &= ~bity_old; + } + pevent->OSEventGrp |= bity_new; /* Add new task prio to wait list */ + pevent->OSEventTbl[y_new] |= bitx_new; + } +#if (OS_EVENT_MULTI_EN > 0) + if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) { + pevents = ptcb->OSTCBEventMultiPtr; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { + pevent->OSEventTbl[y_old] &= ~bitx_old; /* Remove old task prio from wait lists */ + if (pevent->OSEventTbl[y_old] == 0) { + pevent->OSEventGrp &= ~bity_old; + } + pevent->OSEventGrp |= bity_new; /* Add new task prio to wait lists */ + pevent->OSEventTbl[y_new] |= bitx_new; + pevents++; + pevent = *pevents; + } + } +#endif +#endif + + ptcb->OSTCBPrio = newprio; /* Set new task priority */ + ptcb->OSTCBY = y_new; + ptcb->OSTCBX = x_new; + ptcb->OSTCBBitY = bity_new; + ptcb->OSTCBBitX = bitx_new; + OS_EXIT_CRITICAL(); + if (OSRunning == OS_TRUE) { + OS_Sched(); /* Find new highest priority task */ + } + return (OS_ERR_NONE); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* CREATE A TASK +* +* Description: This function is used to have uC/OS-II manage the execution of a task. Tasks can either +* be created prior to the start of multitasking or by a running task. A task cannot be +* created by an ISR. +* +* Arguments : task is a pointer to the task's code +* +* p_arg is a pointer to an optional data area which can be used to pass parameters to +* the task when the task first executes. Where the task is concerned it thinks +* it was invoked and passed the argument 'p_arg' as follows: +* +* void Task (void *p_arg) +* { +* for (;;) { +* Task code; +* } +* } +* +* ptos is a pointer to the task's top of stack. If the configuration constant +* OS_STK_GROWTH is set to 1, the stack is assumed to grow downward (i.e. from high +* memory to low memory). 'pstk' will thus point to the highest (valid) memory +* location of the stack. If OS_STK_GROWTH is set to 0, 'pstk' will point to the +* lowest memory location of the stack and the stack will grow with increasing +* memory locations. +* +* prio is the task's priority. A unique priority MUST be assigned to each task and the +* lower the number, the higher the priority. +* +* Returns : OS_ERR_NONE if the function was successful. +* OS_PRIO_EXIT if the task priority already exist +* (each task MUST have a unique priority). +* OS_ERR_PRIO_INVALID if the priority you specify is higher that the maximum allowed +* (i.e. >= OS_LOWEST_PRIO) +* OS_ERR_TASK_CREATE_ISR if you tried to create a task from an ISR. +********************************************************************************************************* +*/ + +#if OS_TASK_CREATE_EN > 0 +INT8U OSTaskCreate (void (*task)(void *p_arg), void *p_arg, OS_STK *ptos, INT8U prio) +{ + OS_STK *psp; + INT8U err; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio > OS_LOWEST_PRIO) { /* Make sure priority is within allowable range */ + return (OS_ERR_PRIO_INVALID); + } +#endif + OS_ENTER_CRITICAL(); + if (OSIntNesting > 0) { /* Make sure we don't create the task from within an ISR */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_CREATE_ISR); + } + if (OSTCBPrioTbl[prio] == (OS_TCB *)0) { /* Make sure task doesn't already exist at this priority */ + OSTCBPrioTbl[prio] = OS_TCB_RESERVED;/* Reserve the priority to prevent others from doing ... */ + /* ... the same thing until task is created. */ + OS_EXIT_CRITICAL(); + psp = OSTaskStkInit(task, p_arg, ptos, 0); /* Initialize the task's stack */ + err = OS_TCBInit(prio, psp, (OS_STK *)0, 0, 0, (void *)0, 0); + if (err == OS_ERR_NONE) { + if (OSRunning == OS_TRUE) { /* Find highest priority task if multitasking has started */ + OS_Sched(); + } + } else { + OS_ENTER_CRITICAL(); + OSTCBPrioTbl[prio] = (OS_TCB *)0;/* Make this priority available to others */ + OS_EXIT_CRITICAL(); + } + return (err); + } + OS_EXIT_CRITICAL(); + return (OS_ERR_PRIO_EXIST); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* CREATE A TASK (Extended Version) +* +* Description: This function is used to have uC/OS-II manage the execution of a task. Tasks can either +* be created prior to the start of multitasking or by a running task. A task cannot be +* created by an ISR. This function is similar to OSTaskCreate() except that it allows +* additional information about a task to be specified. +* +* Arguments : task is a pointer to the task's code +* +* p_arg is a pointer to an optional data area which can be used to pass parameters to +* the task when the task first executes. Where the task is concerned it thinks +* it was invoked and passed the argument 'p_arg' as follows: +* +* void Task (void *p_arg) +* { +* for (;;) { +* Task code; +* } +* } +* +* ptos is a pointer to the task's top of stack. If the configuration constant +* OS_STK_GROWTH is set to 1, the stack is assumed to grow downward (i.e. from high +* memory to low memory). 'ptos' will thus point to the highest (valid) memory +* location of the stack. If OS_STK_GROWTH is set to 0, 'ptos' will point to the +* lowest memory location of the stack and the stack will grow with increasing +* memory locations. 'ptos' MUST point to a valid 'free' data item. +* +* prio is the task's priority. A unique priority MUST be assigned to each task and the +* lower the number, the higher the priority. +* +* id is the task's ID (0..65535) +* +* pbos is a pointer to the task's bottom of stack. If the configuration constant +* OS_STK_GROWTH is set to 1, the stack is assumed to grow downward (i.e. from high +* memory to low memory). 'pbos' will thus point to the LOWEST (valid) memory +* location of the stack. If OS_STK_GROWTH is set to 0, 'pbos' will point to the +* HIGHEST memory location of the stack and the stack will grow with increasing +* memory locations. 'pbos' MUST point to a valid 'free' data item. +* +* stk_size is the size of the stack in number of elements. If OS_STK is set to INT8U, +* 'stk_size' corresponds to the number of bytes available. If OS_STK is set to +* INT16U, 'stk_size' contains the number of 16-bit entries available. Finally, if +* OS_STK is set to INT32U, 'stk_size' contains the number of 32-bit entries +* available on the stack. +* +* pext is a pointer to a user supplied memory location which is used as a TCB extension. +* For example, this user memory can hold the contents of floating-point registers +* during a context switch, the time each task takes to execute, the number of times +* the task has been switched-in, etc. +* +* opt contains additional information (or options) about the behavior of the task. The +* LOWER 8-bits are reserved by uC/OS-II while the upper 8 bits can be application +* specific. See OS_TASK_OPT_??? in uCOS-II.H. Current choices are: +* +* OS_TASK_OPT_STK_CHK Stack checking to be allowed for the task +* OS_TASK_OPT_STK_CLR Clear the stack when the task is created +* OS_TASK_OPT_SAVE_FP If the CPU has floating-point registers, save them +* during a context switch. +* +* Returns : OS_ERR_NONE if the function was successful. +* OS_PRIO_EXIT if the task priority already exist +* (each task MUST have a unique priority). +* OS_ERR_PRIO_INVALID if the priority you specify is higher that the maximum allowed +* (i.e. > OS_LOWEST_PRIO) +* OS_ERR_TASK_CREATE_ISR if you tried to create a task from an ISR. +********************************************************************************************************* +*/ +/*$PAGE*/ +#if OS_TASK_CREATE_EXT_EN > 0 +INT8U OSTaskCreateExt (void (*task)(void *p_arg), + void *p_arg, + OS_STK *ptos, + INT8U prio, + INT16U id, + OS_STK *pbos, + INT32U stk_size, + void *pext, + INT16U opt) +{ + OS_STK *psp; + INT8U err; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio > OS_LOWEST_PRIO) { /* Make sure priority is within allowable range */ + return (OS_ERR_PRIO_INVALID); + } +#endif + OS_ENTER_CRITICAL(); + if (OSIntNesting > 0) { /* Make sure we don't create the task from within an ISR */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_CREATE_ISR); + } + if (OSTCBPrioTbl[prio] == (OS_TCB *)0) { /* Make sure task doesn't already exist at this priority */ + OSTCBPrioTbl[prio] = OS_TCB_RESERVED;/* Reserve the priority to prevent others from doing ... */ + /* ... the same thing until task is created. */ + OS_EXIT_CRITICAL(); + +#if (OS_TASK_STAT_STK_CHK_EN > 0) + OS_TaskStkClr(pbos, stk_size, opt); /* Clear the task stack (if needed) */ +#endif + + psp = OSTaskStkInit(task, p_arg, ptos, opt); /* Initialize the task's stack */ + err = OS_TCBInit(prio, psp, pbos, id, stk_size, pext, opt); + if (err == OS_ERR_NONE) { + if (OSRunning == OS_TRUE) { /* Find HPT if multitasking has started */ + OS_Sched(); + } + } else { + OS_ENTER_CRITICAL(); + OSTCBPrioTbl[prio] = (OS_TCB *)0; /* Make this priority avail. to others */ + OS_EXIT_CRITICAL(); + } + return (err); + } + OS_EXIT_CRITICAL(); + return (OS_ERR_PRIO_EXIST); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* DELETE A TASK +* +* Description: This function allows you to delete a task. The calling task can delete itself by +* its own priority number. The deleted task is returned to the dormant state and can be +* re-activated by creating the deleted task again. +* +* Arguments : prio is the priority of the task to delete. Note that you can explicitely delete +* the current task without knowing its priority level by setting 'prio' to +* OS_PRIO_SELF. +* +* Returns : OS_ERR_NONE if the call is successful +* OS_ERR_TASK_DEL_IDLE if you attempted to delete uC/OS-II's idle task +* OS_ERR_PRIO_INVALID if the priority you specify is higher that the maximum allowed +* (i.e. >= OS_LOWEST_PRIO) or, you have not specified OS_PRIO_SELF. +* OS_ERR_TASK_DEL if the task is assigned to a Mutex PIP. +* OS_ERR_TASK_NOT_EXIST if the task you want to delete does not exist. +* OS_ERR_TASK_DEL_ISR if you tried to delete a task from an ISR +* +* Notes : 1) To reduce interrupt latency, OSTaskDel() 'disables' the task: +* a) by making it not ready +* b) by removing it from any wait lists +* c) by preventing OSTimeTick() from making the task ready to run. +* The task can then be 'unlinked' from the miscellaneous structures in uC/OS-II. +* 2) The function OS_Dummy() is called after OS_EXIT_CRITICAL() because, on most processors, +* the next instruction following the enable interrupt instruction is ignored. +* 3) An ISR cannot delete a task. +* 4) The lock nesting counter is incremented because, for a brief instant, if the current +* task is being deleted, the current task would not be able to be rescheduled because it +* is removed from the ready list. Incrementing the nesting counter prevents another task +* from being schedule. This means that an ISR would return to the current task which is +* being deleted. The rest of the deletion would thus be able to be completed. +********************************************************************************************************* +*/ + +#if OS_TASK_DEL_EN > 0 +INT8U OSTaskDel (INT8U prio) +{ +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) + OS_FLAG_NODE *pnode; +#endif + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + if (OSIntNesting > 0) { /* See if trying to delete from ISR */ + return (OS_ERR_TASK_DEL_ISR); + } + if (prio == OS_TASK_IDLE_PRIO) { /* Not allowed to delete idle task */ + return (OS_ERR_TASK_DEL_IDLE); + } +#if OS_ARG_CHK_EN > 0 + if (prio >= OS_LOWEST_PRIO) { /* Task priority valid ? */ + if (prio != OS_PRIO_SELF) { + return (OS_ERR_PRIO_INVALID); + } + } +#endif + +/*$PAGE*/ + OS_ENTER_CRITICAL(); + if (prio == OS_PRIO_SELF) { /* See if requesting to delete self */ + prio = OSTCBCur->OSTCBPrio; /* Set priority to delete to current */ + } + ptcb = OSTCBPrioTbl[prio]; + if (ptcb == (OS_TCB *)0) { /* Task to delete must exist */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + } + if (ptcb == OS_TCB_RESERVED) { /* Must not be assigned to Mutex */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_DEL); + } + + OSRdyTbl[ptcb->OSTCBY] &= ~ptcb->OSTCBBitX; + if (OSRdyTbl[ptcb->OSTCBY] == 0) { /* Make task not ready */ + OSRdyGrp &= ~ptcb->OSTCBBitY; + } + +#if (OS_EVENT_EN) + if (ptcb->OSTCBEventPtr != (OS_EVENT *)0) { + OS_EventTaskRemove(ptcb, ptcb->OSTCBEventPtr); /* Remove this task from any event wait list */ + } +#if (OS_EVENT_MULTI_EN > 0) + if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) { /* Remove this task from any events' wait lists*/ + OS_EventTaskRemoveMulti(ptcb, ptcb->OSTCBEventMultiPtr); + } +#endif +#endif + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) + pnode = ptcb->OSTCBFlagNode; + if (pnode != (OS_FLAG_NODE *)0) { /* If task is waiting on event flag */ + OS_FlagUnlink(pnode); /* Remove from wait list */ + } +#endif + + ptcb->OSTCBDly = 0; /* Prevent OSTimeTick() from updating */ + ptcb->OSTCBStat = OS_STAT_RDY; /* Prevent task from being resumed */ + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; + if (OSLockNesting < 255u) { /* Make sure we don't context switch */ + OSLockNesting++; + } + OS_EXIT_CRITICAL(); /* Enabling INT. ignores next instruc. */ + OS_Dummy(); /* ... Dummy ensures that INTs will be */ + OS_ENTER_CRITICAL(); /* ... disabled HERE! */ + if (OSLockNesting > 0) { /* Remove context switch lock */ + OSLockNesting--; + } + OSTaskDelHook(ptcb); /* Call user defined hook */ + OSTaskCtr--; /* One less task being managed */ + OSTCBPrioTbl[prio] = (OS_TCB *)0; /* Clear old priority entry */ + if (ptcb->OSTCBPrev == (OS_TCB *)0) { /* Remove from TCB chain */ + ptcb->OSTCBNext->OSTCBPrev = (OS_TCB *)0; + OSTCBList = ptcb->OSTCBNext; + } else { + ptcb->OSTCBPrev->OSTCBNext = ptcb->OSTCBNext; + ptcb->OSTCBNext->OSTCBPrev = ptcb->OSTCBPrev; + } + ptcb->OSTCBNext = OSTCBFreeList; /* Return TCB to free TCB list */ + OSTCBFreeList = ptcb; +#if OS_TASK_NAME_SIZE > 1 + ptcb->OSTCBTaskName[0] = '?'; /* Unknown name */ + ptcb->OSTCBTaskName[1] = OS_ASCII_NUL; +#endif + OS_EXIT_CRITICAL(); + if (OSRunning == OS_TRUE) { + OS_Sched(); /* Find new highest priority task */ + } + return (OS_ERR_NONE); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* REQUEST THAT A TASK DELETE ITSELF +* +* Description: This function is used to: +* a) notify a task to delete itself. +* b) to see if a task requested that the current task delete itself. +* This function is a little tricky to understand. Basically, you have a task that needs +* to be deleted however, this task has resources that it has allocated (memory buffers, +* semaphores, mailboxes, queues etc.). The task cannot be deleted otherwise these +* resources would not be freed. The requesting task calls OSTaskDelReq() to indicate that +* the task needs to be deleted. Deleting of the task is however, deferred to the task to +* be deleted. For example, suppose that task #10 needs to be deleted. The requesting task +* example, task #5, would call OSTaskDelReq(10). When task #10 gets to execute, it calls +* this function by specifying OS_PRIO_SELF and monitors the returned value. If the return +* value is OS_ERR_TASK_DEL_REQ, another task requested a task delete. Task #10 would look like +* this: +* +* void Task(void *p_arg) +* { +* . +* . +* while (1) { +* OSTimeDly(1); +* if (OSTaskDelReq(OS_PRIO_SELF) == OS_ERR_TASK_DEL_REQ) { +* Release any owned resources; +* De-allocate any dynamic memory; +* OSTaskDel(OS_PRIO_SELF); +* } +* } +* } +* +* Arguments : prio is the priority of the task to request the delete from +* +* Returns : OS_ERR_NONE if the task exist and the request has been registered +* OS_ERR_TASK_NOT_EXIST if the task has been deleted. This allows the caller to know whether +* the request has been executed. +* OS_ERR_TASK_DEL if the task is assigned to a Mutex. +* OS_ERR_TASK_DEL_IDLE if you requested to delete uC/OS-II's idle task +* OS_ERR_PRIO_INVALID if the priority you specify is higher that the maximum allowed +* (i.e. >= OS_LOWEST_PRIO) or, you have not specified OS_PRIO_SELF. +* OS_ERR_TASK_DEL_REQ if a task (possibly another task) requested that the running task be +* deleted. +********************************************************************************************************* +*/ +/*$PAGE*/ +#if OS_TASK_DEL_EN > 0 +INT8U OSTaskDelReq (INT8U prio) +{ + INT8U stat; + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + if (prio == OS_TASK_IDLE_PRIO) { /* Not allowed to delete idle task */ + return (OS_ERR_TASK_DEL_IDLE); + } +#if OS_ARG_CHK_EN > 0 + if (prio >= OS_LOWEST_PRIO) { /* Task priority valid ? */ + if (prio != OS_PRIO_SELF) { + return (OS_ERR_PRIO_INVALID); + } + } +#endif + if (prio == OS_PRIO_SELF) { /* See if a task is requesting to ... */ + OS_ENTER_CRITICAL(); /* ... this task to delete itself */ + stat = OSTCBCur->OSTCBDelReq; /* Return request status to caller */ + OS_EXIT_CRITICAL(); + return (stat); + } + OS_ENTER_CRITICAL(); + ptcb = OSTCBPrioTbl[prio]; + if (ptcb == (OS_TCB *)0) { /* Task to delete must exist */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); /* Task must already be deleted */ + } + if (ptcb == OS_TCB_RESERVED) { /* Must NOT be assigned to a Mutex */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_DEL); + } + ptcb->OSTCBDelReq = OS_ERR_TASK_DEL_REQ; /* Set flag indicating task to be DEL. */ + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* GET THE NAME OF A TASK +* +* Description: This function is called to obtain the name of a task. +* +* Arguments : prio is the priority of the task that you want to obtain the name from. +* +* pname is a pointer to an ASCII string that will receive the name of the task. The +* string must be able to hold at least OS_TASK_NAME_SIZE characters. +* +* perr is a pointer to an error code that can contain one of the following values: +* +* OS_ERR_NONE if the requested task is resumed +* OS_ERR_TASK_NOT_EXIST if the task has not been created or is assigned to a Mutex +* OS_ERR_PRIO_INVALID if you specified an invalid priority: +* A higher value than the idle task or not OS_PRIO_SELF. +* OS_ERR_PNAME_NULL You passed a NULL pointer for 'pname' +* OS_ERR_NAME_GET_ISR You called this function from an ISR +* +* +* Returns : The length of the string or 0 if the task does not exist. +********************************************************************************************************* +*/ + +#if OS_TASK_NAME_SIZE > 1 +INT8U OSTaskNameGet (INT8U prio, INT8U *pname, INT8U *perr) +{ + OS_TCB *ptcb; + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (0); + } + if (prio > OS_LOWEST_PRIO) { /* Task priority valid ? */ + if (prio != OS_PRIO_SELF) { + *perr = OS_ERR_PRIO_INVALID; /* No */ + return (0); + } + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + *perr = OS_ERR_PNAME_NULL; /* Yes */ + return (0); + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_NAME_GET_ISR; + return (0); + } + OS_ENTER_CRITICAL(); + if (prio == OS_PRIO_SELF) { /* See if caller desires it's own name */ + prio = OSTCBCur->OSTCBPrio; + } + ptcb = OSTCBPrioTbl[prio]; + if (ptcb == (OS_TCB *)0) { /* Does task exist? */ + OS_EXIT_CRITICAL(); /* No */ + *perr = OS_ERR_TASK_NOT_EXIST; + return (0); + } + if (ptcb == OS_TCB_RESERVED) { /* Task assigned to a Mutex? */ + OS_EXIT_CRITICAL(); /* Yes */ + *perr = OS_ERR_TASK_NOT_EXIST; + return (0); + } + len = OS_StrCopy(pname, ptcb->OSTCBTaskName); /* Yes, copy name from TCB */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (len); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* ASSIGN A NAME TO A TASK +* +* Description: This function is used to set the name of a task. +* +* Arguments : prio is the priority of the task that you want the assign a name to. +* +* pname is a pointer to an ASCII string that contains the name of the task. The ASCII +* string must be NUL terminated. +* +* perr is a pointer to an error code that can contain one of the following values: +* +* OS_ERR_NONE if the requested task is resumed +* OS_ERR_TASK_NOT_EXIST if the task has not been created or is assigned to a Mutex +* OS_ERR_TASK_NAME_TOO_LONG if the name you are giving to the task exceeds the +* storage capacity of a task name as specified by +* OS_TASK_NAME_SIZE. +* OS_ERR_PNAME_NULL You passed a NULL pointer for 'pname' +* OS_ERR_PRIO_INVALID if you specified an invalid priority: +* A higher value than the idle task or not OS_PRIO_SELF. +* OS_ERR_NAME_SET_ISR if you called this function from an ISR +* +* Returns : None +********************************************************************************************************* +*/ +#if OS_TASK_NAME_SIZE > 1 +void OSTaskNameSet (INT8U prio, INT8U *pname, INT8U *perr) +{ + INT8U len; + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return; + } + if (prio > OS_LOWEST_PRIO) { /* Task priority valid ? */ + if (prio != OS_PRIO_SELF) { + *perr = OS_ERR_PRIO_INVALID; /* No */ + return; + } + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + *perr = OS_ERR_PNAME_NULL; /* Yes */ + return; + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_NAME_SET_ISR; + return; + } + OS_ENTER_CRITICAL(); + if (prio == OS_PRIO_SELF) { /* See if caller desires to set it's own name */ + prio = OSTCBCur->OSTCBPrio; + } + ptcb = OSTCBPrioTbl[prio]; + if (ptcb == (OS_TCB *)0) { /* Does task exist? */ + OS_EXIT_CRITICAL(); /* No */ + *perr = OS_ERR_TASK_NOT_EXIST; + return; + } + if (ptcb == OS_TCB_RESERVED) { /* Task assigned to a Mutex? */ + OS_EXIT_CRITICAL(); /* Yes */ + *perr = OS_ERR_TASK_NOT_EXIST; + return; + } + len = OS_StrLen(pname); /* Yes, Can we fit the string in the TCB? */ + if (len > (OS_TASK_NAME_SIZE - 1)) { /* No */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_NAME_TOO_LONG; + return; + } + (void)OS_StrCopy(ptcb->OSTCBTaskName, pname); /* Yes, copy to TCB */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* RESUME A SUSPENDED TASK +* +* Description: This function is called to resume a previously suspended task. This is the only call that +* will remove an explicit task suspension. +* +* Arguments : prio is the priority of the task to resume. +* +* Returns : OS_ERR_NONE if the requested task is resumed +* OS_ERR_PRIO_INVALID if the priority you specify is higher that the maximum allowed +* (i.e. >= OS_LOWEST_PRIO) +* OS_ERR_TASK_RESUME_PRIO if the task to resume does not exist +* OS_ERR_TASK_NOT_EXIST if the task is assigned to a Mutex PIP +* OS_ERR_TASK_NOT_SUSPENDED if the task to resume has not been suspended +********************************************************************************************************* +*/ + +#if OS_TASK_SUSPEND_EN > 0 +INT8U OSTaskResume (INT8U prio) +{ + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio >= OS_LOWEST_PRIO) { /* Make sure task priority is valid */ + return (OS_ERR_PRIO_INVALID); + } +#endif + OS_ENTER_CRITICAL(); + ptcb = OSTCBPrioTbl[prio]; + if (ptcb == (OS_TCB *)0) { /* Task to suspend must exist */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_RESUME_PRIO); + } + if (ptcb == OS_TCB_RESERVED) { /* See if assigned to Mutex */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + } + if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) != OS_STAT_RDY) { /* Task must be suspended */ + ptcb->OSTCBStat &= ~(INT8U)OS_STAT_SUSPEND; /* Remove suspension */ + if (ptcb->OSTCBStat == OS_STAT_RDY) { /* See if task is now ready */ + if (ptcb->OSTCBDly == 0) { + OSRdyGrp |= ptcb->OSTCBBitY; /* Yes, Make task ready to run */ + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + OS_EXIT_CRITICAL(); + if (OSRunning == OS_TRUE) { + OS_Sched(); /* Find new highest priority task */ + } + } else { + OS_EXIT_CRITICAL(); + } + } else { /* Must be pending on event */ + OS_EXIT_CRITICAL(); + } + return (OS_ERR_NONE); + } + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_SUSPENDED); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* STACK CHECKING +* +* Description: This function is called to check the amount of free memory left on the specified task's +* stack. +* +* Arguments : prio is the task priority +* +* p_stk_data is a pointer to a data structure of type OS_STK_DATA. +* +* Returns : OS_ERR_NONE upon success +* OS_ERR_PRIO_INVALID if the priority you specify is higher that the maximum allowed +* (i.e. > OS_LOWEST_PRIO) or, you have not specified OS_PRIO_SELF. +* OS_ERR_TASK_NOT_EXIST if the desired task has not been created or is assigned to a Mutex PIP +* OS_ERR_TASK_OPT if you did NOT specified OS_TASK_OPT_STK_CHK when the task was created +* OS_ERR_PDATA_NULL if 'p_stk_data' is a NULL pointer +********************************************************************************************************* +*/ +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) +INT8U OSTaskStkChk (INT8U prio, OS_STK_DATA *p_stk_data) +{ + OS_TCB *ptcb; + OS_STK *pchk; + INT32U nfree; + INT32U size; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio > OS_LOWEST_PRIO) { /* Make sure task priority is valid */ + if (prio != OS_PRIO_SELF) { + return (OS_ERR_PRIO_INVALID); + } + } + if (p_stk_data == (OS_STK_DATA *)0) { /* Validate 'p_stk_data' */ + return (OS_ERR_PDATA_NULL); + } +#endif + p_stk_data->OSFree = 0; /* Assume failure, set to 0 size */ + p_stk_data->OSUsed = 0; + OS_ENTER_CRITICAL(); + if (prio == OS_PRIO_SELF) { /* See if check for SELF */ + prio = OSTCBCur->OSTCBPrio; + } + ptcb = OSTCBPrioTbl[prio]; + if (ptcb == (OS_TCB *)0) { /* Make sure task exist */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + } + if (ptcb == OS_TCB_RESERVED) { + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + } + if ((ptcb->OSTCBOpt & OS_TASK_OPT_STK_CHK) == 0) { /* Make sure stack checking option is set */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_OPT); + } + nfree = 0; + size = ptcb->OSTCBStkSize; + pchk = ptcb->OSTCBStkBottom; + OS_EXIT_CRITICAL(); +#if OS_STK_GROWTH == 1 + while (*pchk++ == (OS_STK)0) { /* Compute the number of zero entries on the stk */ + nfree++; + } +#else + while (*pchk-- == (OS_STK)0) { + nfree++; + } +#endif + p_stk_data->OSFree = nfree * sizeof(OS_STK); /* Compute number of free bytes on the stack */ + p_stk_data->OSUsed = (size - nfree) * sizeof(OS_STK); /* Compute number of bytes used on the stack */ + return (OS_ERR_NONE); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* SUSPEND A TASK +* +* Description: This function is called to suspend a task. The task can be the calling task if the +* priority passed to OSTaskSuspend() is the priority of the calling task or OS_PRIO_SELF. +* +* Arguments : prio is the priority of the task to suspend. If you specify OS_PRIO_SELF, the +* calling task will suspend itself and rescheduling will occur. +* +* Returns : OS_ERR_NONE if the requested task is suspended +* OS_ERR_TASK_SUSPEND_IDLE if you attempted to suspend the idle task which is not allowed. +* OS_ERR_PRIO_INVALID if the priority you specify is higher that the maximum allowed +* (i.e. >= OS_LOWEST_PRIO) or, you have not specified OS_PRIO_SELF. +* OS_ERR_TASK_SUSPEND_PRIO if the task to suspend does not exist +* OS_ERR_TASK_NOT_EXITS if the task is assigned to a Mutex PIP +* +* Note : You should use this function with great care. If you suspend a task that is waiting for +* an event (i.e. a message, a semaphore, a queue ...) you will prevent this task from +* running when the event arrives. +********************************************************************************************************* +*/ + +#if OS_TASK_SUSPEND_EN > 0 +INT8U OSTaskSuspend (INT8U prio) +{ + BOOLEAN self; + OS_TCB *ptcb; + INT8U y; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio == OS_TASK_IDLE_PRIO) { /* Not allowed to suspend idle task */ + return (OS_ERR_TASK_SUSPEND_IDLE); + } + if (prio >= OS_LOWEST_PRIO) { /* Task priority valid ? */ + if (prio != OS_PRIO_SELF) { + return (OS_ERR_PRIO_INVALID); + } + } +#endif + OS_ENTER_CRITICAL(); + if (prio == OS_PRIO_SELF) { /* See if suspend SELF */ + prio = OSTCBCur->OSTCBPrio; + self = OS_TRUE; + } else if (prio == OSTCBCur->OSTCBPrio) { /* See if suspending self */ + self = OS_TRUE; + } else { + self = OS_FALSE; /* No suspending another task */ + } + ptcb = OSTCBPrioTbl[prio]; + if (ptcb == (OS_TCB *)0) { /* Task to suspend must exist */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_SUSPEND_PRIO); + } + if (ptcb == OS_TCB_RESERVED) { /* See if assigned to Mutex */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + } + y = ptcb->OSTCBY; + OSRdyTbl[y] &= ~ptcb->OSTCBBitX; /* Make task not ready */ + if (OSRdyTbl[y] == 0) { + OSRdyGrp &= ~ptcb->OSTCBBitY; + } + ptcb->OSTCBStat |= OS_STAT_SUSPEND; /* Status of task is 'SUSPENDED' */ + OS_EXIT_CRITICAL(); + if (self == OS_TRUE) { /* Context switch only if SELF */ + OS_Sched(); /* Find new highest priority task */ + } + return (OS_ERR_NONE); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* QUERY A TASK +* +* Description: This function is called to obtain a copy of the desired task's TCB. +* +* Arguments : prio is the priority of the task to obtain information from. +* +* p_task_data is a pointer to where the desired task's OS_TCB will be stored. +* +* Returns : OS_ERR_NONE if the requested task is suspended +* OS_ERR_PRIO_INVALID if the priority you specify is higher that the maximum allowed +* (i.e. > OS_LOWEST_PRIO) or, you have not specified OS_PRIO_SELF. +* OS_ERR_PRIO if the desired task has not been created +* OS_ERR_TASK_NOT_EXIST if the task is assigned to a Mutex PIP +* OS_ERR_PDATA_NULL if 'p_task_data' is a NULL pointer +********************************************************************************************************* +*/ + +#if OS_TASK_QUERY_EN > 0 +INT8U OSTaskQuery (INT8U prio, OS_TCB *p_task_data) +{ + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio > OS_LOWEST_PRIO) { /* Task priority valid ? */ + if (prio != OS_PRIO_SELF) { + return (OS_ERR_PRIO_INVALID); + } + } + if (p_task_data == (OS_TCB *)0) { /* Validate 'p_task_data' */ + return (OS_ERR_PDATA_NULL); + } +#endif + OS_ENTER_CRITICAL(); + if (prio == OS_PRIO_SELF) { /* See if suspend SELF */ + prio = OSTCBCur->OSTCBPrio; + } + ptcb = OSTCBPrioTbl[prio]; + if (ptcb == (OS_TCB *)0) { /* Task to query must exist */ + OS_EXIT_CRITICAL(); + return (OS_ERR_PRIO); + } + if (ptcb == OS_TCB_RESERVED) { /* Task to query must not be assigned to a Mutex */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + } + /* Copy TCB into user storage area */ + OS_MemCopy((INT8U *)p_task_data, (INT8U *)ptcb, sizeof(OS_TCB)); + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* CLEAR TASK STACK +* +* Description: This function is used to clear the stack of a task (i.e. write all zeros) +* +* Arguments : pbos is a pointer to the task's bottom of stack. If the configuration constant +* OS_STK_GROWTH is set to 1, the stack is assumed to grow downward (i.e. from high +* memory to low memory). 'pbos' will thus point to the lowest (valid) memory +* location of the stack. If OS_STK_GROWTH is set to 0, 'pbos' will point to the +* highest memory location of the stack and the stack will grow with increasing +* memory locations. 'pbos' MUST point to a valid 'free' data item. +* +* size is the number of 'stack elements' to clear. +* +* opt contains additional information (or options) about the behavior of the task. The +* LOWER 8-bits are reserved by uC/OS-II while the upper 8 bits can be application +* specific. See OS_TASK_OPT_??? in uCOS-II.H. +* +* Returns : none +********************************************************************************************************* +*/ +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) +void OS_TaskStkClr (OS_STK *pbos, INT32U size, INT16U opt) +{ + if ((opt & OS_TASK_OPT_STK_CHK) != 0x0000) { /* See if stack checking has been enabled */ + if ((opt & OS_TASK_OPT_STK_CLR) != 0x0000) { /* See if stack needs to be cleared */ +#if OS_STK_GROWTH == 1 + while (size > 0) { /* Stack grows from HIGH to LOW memory */ + size--; + *pbos++ = (OS_STK)0; /* Clear from bottom of stack and up! */ + } +#else + while (size > 0) { /* Stack grows from LOW to HIGH memory */ + size--; + *pbos-- = (OS_STK)0; /* Clear from bottom of stack and down */ + } +#endif + } + } +} + +#endif diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/os_time.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_time.c new file mode 100644 index 0000000..540384e --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_time.c @@ -0,0 +1,268 @@ +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* TIME MANAGEMENT +* +* (c) Copyright 1992-2007, Micrium, Weston, FL +* All Rights Reserved +* +* File : OS_TIME.C +* By : Jean J. Labrosse +* Version : V2.86 +* +* LICENSING TERMS: +* --------------- +* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. +* If you plan on using uC/OS-II in a commercial product you need to contact Micriµm to properly license +* its use in your product. We provide ALL the source code for your convenience and to help you experience +* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a +* licensing fee. +********************************************************************************************************* +*/ + +#ifndef OS_MASTER_FILE +#include +#endif + +/* +********************************************************************************************************* +* DELAY TASK 'n' TICKS (n from 0 to 65535) +* +* Description: This function is called to delay execution of the currently running task until the +* specified number of system ticks expires. This, of course, directly equates to delaying +* the current task for some time to expire. No delay will result If the specified delay is +* 0. If the specified delay is greater than 0 then, a context switch will result. +* +* Arguments : ticks is the time delay that the task will be suspended in number of clock 'ticks'. +* Note that by specifying 0, the task will not be delayed. +* +* Returns : none +********************************************************************************************************* +*/ + +void OSTimeDly (INT16U ticks) +{ + INT8U y; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + return; + } + if (ticks > 0) { /* 0 means no delay! */ + OS_ENTER_CRITICAL(); + y = OSTCBCur->OSTCBY; /* Delay current task */ + OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX; + if (OSRdyTbl[y] == 0) { + OSRdyGrp &= ~OSTCBCur->OSTCBBitY; + } + OSTCBCur->OSTCBDly = ticks; /* Load ticks in TCB */ + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next task to run! */ + } +} +/*$PAGE*/ +/* +********************************************************************************************************* +* DELAY TASK FOR SPECIFIED TIME +* +* Description: This function is called to delay execution of the currently running task until some time +* expires. This call allows you to specify the delay time in HOURS, MINUTES, SECONDS and +* MILLISECONDS instead of ticks. +* +* Arguments : hours specifies the number of hours that the task will be delayed (max. is 255) +* minutes specifies the number of minutes (max. 59) +* seconds specifies the number of seconds (max. 59) +* milli specifies the number of milliseconds (max. 999) +* +* Returns : OS_ERR_NONE +* OS_ERR_TIME_INVALID_MINUTES +* OS_ERR_TIME_INVALID_SECONDS +* OS_ERR_TIME_INVALID_MS +* OS_ERR_TIME_ZERO_DLY +* OS_ERR_TIME_DLY_ISR +* +* Note(s) : The resolution on the milliseconds depends on the tick rate. For example, you can't do +* a 10 mS delay if the ticker interrupts every 100 mS. In this case, the delay would be +* set to 0. The actual delay is rounded to the nearest tick. +********************************************************************************************************* +*/ + +#if OS_TIME_DLY_HMSM_EN > 0 +INT8U OSTimeDlyHMSM (INT8U hours, INT8U minutes, INT8U seconds, INT16U ms) +{ + INT32U ticks; + INT16U loops; + + + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + return (OS_ERR_TIME_DLY_ISR); + } +#if OS_ARG_CHK_EN > 0 + if (hours == 0) { + if (minutes == 0) { + if (seconds == 0) { + if (ms == 0) { + return (OS_ERR_TIME_ZERO_DLY); + } + } + } + } + if (minutes > 59) { + return (OS_ERR_TIME_INVALID_MINUTES); /* Validate arguments to be within range */ + } + if (seconds > 59) { + return (OS_ERR_TIME_INVALID_SECONDS); + } + if (ms > 999) { + return (OS_ERR_TIME_INVALID_MS); + } +#endif + /* Compute the total number of clock ticks required.. */ + /* .. (rounded to the nearest tick) */ + ticks = ((INT32U)hours * 3600L + (INT32U)minutes * 60L + (INT32U)seconds) * OS_TICKS_PER_SEC + + OS_TICKS_PER_SEC * ((INT32U)ms + 500L / OS_TICKS_PER_SEC) / 1000L; + loops = (INT16U)(ticks >> 16); /* Compute the integral number of 65536 tick delays */ + ticks = ticks & 0xFFFFL; /* Obtain the fractional number of ticks */ + OSTimeDly((INT16U)ticks); + while (loops > 0) { + OSTimeDly((INT16U)32768u); + OSTimeDly((INT16U)32768u); + loops--; + } + return (OS_ERR_NONE); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* RESUME A DELAYED TASK +* +* Description: This function is used resume a task that has been delayed through a call to either +* OSTimeDly() or OSTimeDlyHMSM(). Note that you can call this function to resume a +* task that is waiting for an event with timeout. This would make the task look +* like a timeout occurred. +* +* Also, you cannot resume a task that has called OSTimeDlyHMSM() with a combined time that +* exceeds 65535 clock ticks. In other words, if the clock tick runs at 100 Hz then, you will +* not be able to resume a delayed task that called OSTimeDlyHMSM(0, 10, 55, 350) or higher: +* +* (10 Minutes * 60 + 55 Seconds + 0.35) * 100 ticks/second. +* +* Arguments : prio specifies the priority of the task to resume +* +* Returns : OS_ERR_NONE Task has been resumed +* OS_ERR_PRIO_INVALID if the priority you specify is higher that the maximum allowed +* (i.e. >= OS_LOWEST_PRIO) +* OS_ERR_TIME_NOT_DLY Task is not waiting for time to expire +* OS_ERR_TASK_NOT_EXIST The desired task has not been created or has been assigned to a Mutex. +********************************************************************************************************* +*/ + +#if OS_TIME_DLY_RESUME_EN > 0 +INT8U OSTimeDlyResume (INT8U prio) +{ + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + if (prio >= OS_LOWEST_PRIO) { + return (OS_ERR_PRIO_INVALID); + } + OS_ENTER_CRITICAL(); + ptcb = OSTCBPrioTbl[prio]; /* Make sure that task exist */ + if (ptcb == (OS_TCB *)0) { + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); /* The task does not exist */ + } + if (ptcb == OS_TCB_RESERVED) { + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); /* The task does not exist */ + } + if (ptcb->OSTCBDly == 0) { /* See if task is delayed */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TIME_NOT_DLY); /* Indicate that task was not delayed */ + } + + ptcb->OSTCBDly = 0; /* Clear the time delay */ + if ((ptcb->OSTCBStat & OS_STAT_PEND_ANY) != OS_STAT_RDY) { + ptcb->OSTCBStat &= ~OS_STAT_PEND_ANY; /* Yes, Clear status flag */ + ptcb->OSTCBStatPend = OS_STAT_PEND_TO; /* Indicate PEND timeout */ + } else { + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; + } + if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) == OS_STAT_RDY) { /* Is task suspended? */ + OSRdyGrp |= ptcb->OSTCBBitY; /* No, Make ready */ + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + OS_EXIT_CRITICAL(); + OS_Sched(); /* See if this is new highest priority */ + } else { + OS_EXIT_CRITICAL(); /* Task may be suspended */ + } + return (OS_ERR_NONE); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* GET CURRENT SYSTEM TIME +* +* Description: This function is used by your application to obtain the current value of the 32-bit +* counter which keeps track of the number of clock ticks. +* +* Arguments : none +* +* Returns : The current value of OSTime +********************************************************************************************************* +*/ + +#if OS_TIME_GET_SET_EN > 0 +INT32U OSTimeGet (void) +{ + INT32U ticks; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + OS_ENTER_CRITICAL(); + ticks = OSTime; + OS_EXIT_CRITICAL(); + return (ticks); +} +#endif + +/* +********************************************************************************************************* +* SET SYSTEM CLOCK +* +* Description: This function sets the 32-bit counter which keeps track of the number of clock ticks. +* +* Arguments : ticks specifies the new value that OSTime needs to take. +* +* Returns : none +********************************************************************************************************* +*/ + +#if OS_TIME_GET_SET_EN > 0 +void OSTimeSet (INT32U ticks) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + OS_ENTER_CRITICAL(); + OSTime = ticks; + OS_EXIT_CRITICAL(); +} +#endif diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/os_tmr.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_tmr.c new file mode 100644 index 0000000..c80811f --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_tmr.c @@ -0,0 +1,1116 @@ +/* +************************************************************************************************************************ +* uC/OS-II +* The Real-Time Kernel +* TIMER MANAGEMENT +* +* (c) Copyright 1992-2007, Micrium, Weston, FL +* All Rights Reserved +* +* +* File : OS_TMR.C +* By : Jean J. Labrosse +* Version : V2.86 +* +* LICENSING TERMS: +* --------------- +* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. +* If you plan on using uC/OS-II in a commercial product you need to contact Micriµm to properly license +* its use in your product. We provide ALL the source code for your convenience and to help you experience +* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a +* licensing fee. +************************************************************************************************************************ +*/ + +#include + +/* +************************************************************************************************************************ +* NOTES +* +* 1) Your application MUST define the following #define constants: +* +* OS_TASK_TMR_PRIO The priority of the Timer management task +* OS_TASK_TMR_STK_SIZE The size of the Timer management task's stack +* +* 2) You must call OSTmrSignal() to notify the Timer management task that it's time to update the timers. +************************************************************************************************************************ +*/ + +/* +************************************************************************************************************************ +* CONSTANTS +************************************************************************************************************************ +*/ + +#define OS_TMR_LINK_DLY 0 +#define OS_TMR_LINK_PERIODIC 1 + +/* +************************************************************************************************************************ +* LOCAL PROTOTYPES +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +static OS_TMR *OSTmr_Alloc (void); +static void OSTmr_Free (OS_TMR *ptmr); +static void OSTmr_InitTask (void); +static void OSTmr_Link (OS_TMR *ptmr, INT8U type); +static void OSTmr_Unlink (OS_TMR *ptmr); +static void OSTmr_Lock (void); +static void OSTmr_Unlock (void); +static void OSTmr_Task (void *p_arg); +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* CREATE A TIMER +* +* Description: This function is called by your application code to create a timer. +* +* Arguments : dly Initial delay. +* If the timer is configured for ONE-SHOT mode, this is the timeout used +* If the timer is configured for PERIODIC mode, this is the first timeout to wait for +* before the timer starts entering periodic mode +* +* period The 'period' being repeated for the timer. +* If you specified 'OS_TMR_OPT_PERIODIC' as an option, when the timer expires, it will +* automatically restart with the same period. +* +* opt Specifies either: +* OS_TMR_OPT_ONE_SHOT The timer counts down only once +* OS_TMR_OPT_PERIODIC The timer counts down and then reloads itself +* +* callback Is a pointer to a callback function that will be called when the timer expires. The +* callback function must be declared as follows: +* +* void MyCallback (OS_TMR *ptmr, void *p_arg); +* +* callback_arg Is an argument (a pointer) that is passed to the callback function when it is called. +* +* pname Is a pointer to an ASCII string that is used to name the timer. Names are useful for +* debugging. The length of the ASCII string for the name can be as big as: +* +* OS_TMR_CFG_NAME_SIZE and should be found in OS_CFG.H +* +* perr Is a pointer to an error code. '*perr' will contain one of the following: +* OS_ERR_NONE +* OS_ERR_TMR_INVALID_DLY you specified an invalid delay +* OS_ERR_TMR_INVALID_PERIOD you specified an invalid period +* OS_ERR_TMR_INVALID_OPT you specified an invalid option +* OS_ERR_TMR_ISR if the call was made from an ISR +* OS_ERR_TMR_NON_AVAIL if there are no free timers from the timer pool +* OS_ERR_TMR_NAME_TOO_LONG if the timer name is too long to fit +* +* Returns : A pointer to an OS_TMR data structure. +* This is the 'handle' that your application will use to reference the timer created. +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +OS_TMR *OSTmrCreate (INT32U dly, + INT32U period, + INT8U opt, + OS_TMR_CALLBACK callback, + void *callback_arg, + INT8U *pname, + INT8U *perr) +{ + OS_TMR *ptmr; +#if OS_TMR_CFG_NAME_SIZE > 0 + INT8U len; +#endif + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate arguments */ + return ((OS_TMR *)0); + } + switch (opt) { + case OS_TMR_OPT_PERIODIC: + if (period == 0) { + *perr = OS_ERR_TMR_INVALID_PERIOD; + return ((OS_TMR *)0); + } + break; + + case OS_TMR_OPT_ONE_SHOT: + if (dly == 0) { + *perr = OS_ERR_TMR_INVALID_DLY; + return ((OS_TMR *)0); + } + break; + + default: + *perr = OS_ERR_TMR_INVALID_OPT; + return ((OS_TMR *)0); + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_TMR_ISR; + return ((OS_TMR *)0); + } + OSTmr_Lock(); + ptmr = OSTmr_Alloc(); /* Obtain a timer from the free pool */ + if (ptmr == (OS_TMR *)0) { + OSTmr_Unlock(); + *perr = OS_ERR_TMR_NON_AVAIL; + return ((OS_TMR *)0); + } + ptmr->OSTmrState = OS_TMR_STATE_STOPPED; /* Indicate that timer is not running yet */ + ptmr->OSTmrDly = dly; + ptmr->OSTmrPeriod = period; + ptmr->OSTmrOpt = opt; + ptmr->OSTmrCallback = callback; + ptmr->OSTmrCallbackArg = callback_arg; +#if OS_TMR_CFG_NAME_SIZE > 0 + if (pname !=(INT8U *)0) { + len = OS_StrLen(pname); /* Copy timer name */ + if (len < OS_TMR_CFG_NAME_SIZE) { + (void)OS_StrCopy(ptmr->OSTmrName, pname); + } else { +#if OS_TMR_CFG_NAME_SIZE > 1 + ptmr->OSTmrName[0] = '#'; /* Invalid size specified */ + ptmr->OSTmrName[1] = OS_ASCII_NUL; +#endif + *perr = OS_ERR_TMR_NAME_TOO_LONG; + OSTmr_Unlock(); + return (ptmr); + } + } +#endif + OSTmr_Unlock(); + *perr = OS_ERR_NONE; + return (ptmr); +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* DELETE A TIMER +* +* Description: This function is called by your application code to delete a timer. +* +* Arguments : ptmr Is a pointer to the timer to stop and delete. +* +* perr Is a pointer to an error code. '*perr' will contain one of the following: +* OS_ERR_NONE +* OS_ERR_TMR_INVALID 'ptmr' is a NULL pointer +* OS_ERR_TMR_INVALID_TYPE 'ptmr' is not pointing to an OS_TMR +* OS_ERR_TMR_ISR if the function was called from an ISR +* OS_ERR_TMR_INACTIVE if the timer was not created +* OS_ERR_TMR_INVALID_STATE the timer is in an invalid state +* +* Returns : OS_TRUE If the call was successful +* OS_FALSE If not +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +BOOLEAN OSTmrDel (OS_TMR *ptmr, + INT8U *perr) +{ +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate arguments */ + return (OS_FALSE); + } + if (ptmr == (OS_TMR *)0) { + *perr = OS_ERR_TMR_INVALID; + return (OS_FALSE); + } +#endif + if (ptmr->OSTmrType != OS_TMR_TYPE) { /* Validate timer structure */ + *perr = OS_ERR_TMR_INVALID_TYPE; + return (OS_FALSE); + } + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_TMR_ISR; + return (OS_FALSE); + } + OSTmr_Lock(); + switch (ptmr->OSTmrState) { + case OS_TMR_STATE_RUNNING: + OSTmr_Unlink(ptmr); /* Remove from current wheel spoke */ + OSTmr_Free(ptmr); /* Return timer to free list of timers */ + OSTmr_Unlock(); + *perr = OS_ERR_NONE; + return (OS_TRUE); + + case OS_TMR_STATE_STOPPED: /* Timer has not started or ... */ + case OS_TMR_STATE_COMPLETED: /* ... timer has completed the ONE-SHOT time */ + OSTmr_Free(ptmr); /* Return timer to free list of timers */ + OSTmr_Unlock(); + *perr = OS_ERR_NONE; + return (OS_TRUE); + + case OS_TMR_STATE_UNUSED: /* Already deleted */ + OSTmr_Unlock(); + *perr = OS_ERR_TMR_INACTIVE; + return (OS_FALSE); + + default: + OSTmr_Unlock(); + *perr = OS_ERR_TMR_INVALID_STATE; + return (OS_FALSE); + } +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* GET THE NAME OF A TIMER +* +* Description: This function is called to obtain the name of a timer. +* +* Arguments : ptmr Is a pointer to the timer to obtain the name for +* +* pdest Is a pointer to where the name of the timer will be placed. It is the caller's responsibility +* to ensure that he has sufficient storage in the destination, i.e. at least OS_TMR_CFG_NAME_SIZE +* +* perr Is a pointer to an error code. '*perr' will contain one of the following: +* OS_ERR_NONE The call was successful +* OS_ERR_TMR_INVALID_DEST 'pdest' is a NULL pointer +* OS_ERR_TMR_INVALID 'ptmr' is a NULL pointer +* OS_ERR_TMR_INVALID_TYPE 'ptmr' is not pointing to an OS_TMR +* OS_ERR_NAME_GET_ISR if the call was made from an ISR +* OS_ERR_TMR_INACTIVE 'ptmr' points to a timer that is not active +* OS_ERR_TMR_INVALID_STATE the timer is in an invalid state +* +* Returns : The length of the string or 0 if the timer does not exist. +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 && OS_TMR_CFG_NAME_SIZE > 0 +INT8U OSTmrNameGet (OS_TMR *ptmr, + INT8U *pdest, + INT8U *perr) +{ + INT8U len; + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { + return (0); + } + if (pdest == (INT8U *)0) { + *perr = OS_ERR_TMR_INVALID_DEST; + return (0); + } + if (ptmr == (OS_TMR *)0) { + *perr = OS_ERR_TMR_INVALID; + return (0); + } +#endif + if (ptmr->OSTmrType != OS_TMR_TYPE) { /* Validate timer structure */ + *perr = OS_ERR_TMR_INVALID_TYPE; + return (0); + } + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_NAME_GET_ISR; + return (0); + } + OSTmr_Lock(); + switch (ptmr->OSTmrState) { + case OS_TMR_STATE_RUNNING: + case OS_TMR_STATE_STOPPED: + case OS_TMR_STATE_COMPLETED: + len = OS_StrCopy(pdest, ptmr->OSTmrName); + OSTmr_Unlock(); + *perr = OS_ERR_NONE; + return (len); + + case OS_TMR_STATE_UNUSED: /* Timer is not allocated */ + OSTmr_Unlock(); + *perr = OS_ERR_TMR_INACTIVE; + return (0); + + default: + OSTmr_Unlock(); + *perr = OS_ERR_TMR_INVALID_STATE; + return (0); + } +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* GET HOW MUCH TIME IS LEFT BEFORE A TIMER EXPIRES +* +* Description: This function is called to get the number of ticks before a timer times out. +* +* Arguments : ptmr Is a pointer to the timer to obtain the remaining time from. +* +* perr Is a pointer to an error code. '*perr' will contain one of the following: +* OS_ERR_NONE +* OS_ERR_TMR_INVALID 'ptmr' is a NULL pointer +* OS_ERR_TMR_INVALID_TYPE 'ptmr' is not pointing to an OS_TMR +* OS_ERR_TMR_ISR if the call was made from an ISR +* OS_ERR_TMR_INACTIVE 'ptmr' points to a timer that is not active +* OS_ERR_TMR_INVALID_STATE the timer is in an invalid state +* +* Returns : The time remaining for the timer to expire. The time represents 'timer' increments. In other words, if +* OSTmr_Task() is signaled every 1/10 of a second then the returned value represents the number of 1/10 of +* a second remaining before the timer expires. +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +INT32U OSTmrRemainGet (OS_TMR *ptmr, + INT8U *perr) +{ + INT32U remain; + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { + return (0); + } + if (ptmr == (OS_TMR *)0) { + *perr = OS_ERR_TMR_INVALID; + return (0); + } +#endif + if (ptmr->OSTmrType != OS_TMR_TYPE) { /* Validate timer structure */ + *perr = OS_ERR_TMR_INVALID_TYPE; + return (0); + } + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_TMR_ISR; + return (0); + } + OSTmr_Lock(); + switch (ptmr->OSTmrState) { + case OS_TMR_STATE_RUNNING: + remain = ptmr->OSTmrMatch - OSTmrTime; /* Determine how much time is left to timeout */ + OSTmr_Unlock(); + *perr = OS_ERR_NONE; + return (remain); + + case OS_TMR_STATE_STOPPED: /* It's assumed that the timer has not started yet */ + switch (ptmr->OSTmrOpt) { + case OS_TMR_OPT_PERIODIC: + if (ptmr->OSTmrDly == 0) { + remain = ptmr->OSTmrPeriod; + } else { + remain = ptmr->OSTmrDly; + } + OSTmr_Unlock(); + *perr = OS_ERR_NONE; + break; + + case OS_TMR_OPT_ONE_SHOT: + default: + remain = ptmr->OSTmrDly; + OSTmr_Unlock(); + *perr = OS_ERR_NONE; + break; + } + return (remain); + + case OS_TMR_STATE_COMPLETED: /* Only ONE-SHOT that timed out can be in this state */ + OSTmr_Unlock(); + *perr = OS_ERR_NONE; + return (0); + + case OS_TMR_STATE_UNUSED: + OSTmr_Unlock(); + *perr = OS_ERR_TMR_INACTIVE; + return (0); + + default: + OSTmr_Unlock(); + *perr = OS_ERR_TMR_INVALID_STATE; + return (0); + } +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* FIND OUT WHAT STATE A TIMER IS IN +* +* Description: This function is called to determine what state the timer is in: +* +* OS_TMR_STATE_UNUSED the timer has not been created +* OS_TMR_STATE_STOPPED the timer has been created but has not been started or has been stopped +* OS_TMR_COMPLETED the timer is in ONE-SHOT mode and has completed it's timeout +* OS_TMR_RUNNING the timer is currently running +* +* Arguments : ptmr Is a pointer to the desired timer +* +* perr Is a pointer to an error code. '*perr' will contain one of the following: +* OS_ERR_NONE +* OS_ERR_TMR_INVALID 'ptmr' is a NULL pointer +* OS_ERR_TMR_INVALID_TYPE 'ptmr' is not pointing to an OS_TMR +* OS_ERR_TMR_ISR if the call was made from an ISR +* OS_ERR_TMR_INACTIVE 'ptmr' points to a timer that is not active +* OS_ERR_TMR_INVALID_STATE if the timer is not in a valid state +* +* Returns : The current state of the timer (see description). +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +INT8U OSTmrStateGet (OS_TMR *ptmr, + INT8U *perr) +{ + INT8U state; + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { + return (0); + } + if (ptmr == (OS_TMR *)0) { + *perr = OS_ERR_TMR_INVALID; + return (0); + } +#endif + if (ptmr->OSTmrType != OS_TMR_TYPE) { /* Validate timer structure */ + *perr = OS_ERR_TMR_INVALID_TYPE; + return (0); + } + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_TMR_ISR; + return (0); + } + OSTmr_Lock(); + state = ptmr->OSTmrState; + switch (state) { + case OS_TMR_STATE_UNUSED: + case OS_TMR_STATE_STOPPED: + case OS_TMR_STATE_COMPLETED: + case OS_TMR_STATE_RUNNING: + *perr = OS_ERR_NONE; + break; + + default: + *perr = OS_ERR_TMR_INVALID_STATE; + break; + } + OSTmr_Unlock(); + return (state); +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* START A TIMER +* +* Description: This function is called by your application code to start a timer. +* +* Arguments : ptmr Is a pointer to an OS_TMR +* +* perr Is a pointer to an error code. '*perr' will contain one of the following: +* OS_ERR_NONE +* OS_ERR_TMR_INVALID +* OS_ERR_TMR_INVALID_TYPE 'ptmr' is not pointing to an OS_TMR +* OS_ERR_TMR_ISR if the call was made from an ISR +* OS_ERR_TMR_INACTIVE if the timer was not created +* OS_ERR_TMR_INVALID_STATE the timer is in an invalid state +* +* Returns : OS_TRUE if the timer was started +* OS_FALSE if an error was detected +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +BOOLEAN OSTmrStart (OS_TMR *ptmr, + INT8U *perr) +{ +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate arguments */ + return (OS_FALSE); + } + if (ptmr == (OS_TMR *)0) { + *perr = OS_ERR_TMR_INVALID; + return (OS_FALSE); + } +#endif + if (ptmr->OSTmrType != OS_TMR_TYPE) { /* Validate timer structure */ + *perr = OS_ERR_TMR_INVALID_TYPE; + return (OS_FALSE); + } + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_TMR_ISR; + return (OS_FALSE); + } + OSTmr_Lock(); + switch (ptmr->OSTmrState) { + case OS_TMR_STATE_RUNNING: /* Restart the timer */ + OSTmr_Unlink(ptmr); /* ... Stop the timer */ + OSTmr_Link(ptmr, OS_TMR_LINK_DLY); /* ... Link timer to timer wheel */ + OSTmr_Unlock(); + *perr = OS_ERR_NONE; + return (OS_TRUE); + + case OS_TMR_STATE_STOPPED: /* Start the timer */ + case OS_TMR_STATE_COMPLETED: + OSTmr_Link(ptmr, OS_TMR_LINK_DLY); /* ... Link timer to timer wheel */ + OSTmr_Unlock(); + *perr = OS_ERR_NONE; + return (OS_TRUE); + + case OS_TMR_STATE_UNUSED: /* Timer not created */ + OSTmr_Unlock(); + *perr = OS_ERR_TMR_INACTIVE; + return (OS_FALSE); + + default: + OSTmr_Unlock(); + *perr = OS_ERR_TMR_INVALID_STATE; + return (OS_FALSE); + } +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* STOP A TIMER +* +* Description: This function is called by your application code to stop a timer. +* +* Arguments : ptmr Is a pointer to the timer to stop. +* +* opt Allows you to specify an option to this functions which can be: +* +* OS_TMR_OPT_NONE Do nothing special but stop the timer +* OS_TMR_OPT_CALLBACK Execute the callback function, pass it the callback argument +* specified when the timer was created. +* OS_TMR_OPT_CALLBACK_ARG Execute the callback function, pass it the callback argument +* specified in THIS function call +* +* callback_arg Is a pointer to a 'new' callback argument that can be passed to the callback function +* instead of the timer's callback argument. In other words, use 'callback_arg' passed in +* THIS function INSTEAD of ptmr->OSTmrCallbackArg +* +* perr Is a pointer to an error code. '*perr' will contain one of the following: +* OS_ERR_NONE +* OS_ERR_TMR_INVALID 'ptmr' is a NULL pointer +* OS_ERR_TMR_INVALID_TYPE 'ptmr' is not pointing to an OS_TMR +* OS_ERR_TMR_ISR if the function was called from an ISR +* OS_ERR_TMR_INACTIVE if the timer was not created +* OS_ERR_TMR_INVALID_OPT if you specified an invalid option for 'opt' +* OS_ERR_TMR_STOPPED if the timer was already stopped +* OS_ERR_TMR_INVALID_STATE the timer is in an invalid state +* OS_ERR_TMR_NO_CALLBACK if the timer does not have a callback function defined +* +* Returns : OS_TRUE If we stopped the timer (if the timer is already stopped, we also return OS_TRUE) +* OS_FALSE If not +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +BOOLEAN OSTmrStop (OS_TMR *ptmr, + INT8U opt, + void *callback_arg, + INT8U *perr) +{ + OS_TMR_CALLBACK pfnct; + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate arguments */ + return (OS_FALSE); + } + if (ptmr == (OS_TMR *)0) { + *perr = OS_ERR_TMR_INVALID; + return (OS_FALSE); + } +#endif + if (ptmr->OSTmrType != OS_TMR_TYPE) { /* Validate timer structure */ + *perr = OS_ERR_TMR_INVALID_TYPE; + return (OS_FALSE); + } + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_TMR_ISR; + return (OS_FALSE); + } + OSTmr_Lock(); + switch (ptmr->OSTmrState) { + case OS_TMR_STATE_RUNNING: + OSTmr_Unlink(ptmr); /* Remove from current wheel spoke */ + *perr = OS_ERR_NONE; + switch (opt) { + case OS_TMR_OPT_CALLBACK: + pfnct = ptmr->OSTmrCallback; /* Execute callback function if available ... */ + if (pfnct != (OS_TMR_CALLBACK)0) { + (*pfnct)((void *)ptmr, ptmr->OSTmrCallbackArg); /* Use callback arg when timer was created */ + } else { + *perr = OS_ERR_TMR_NO_CALLBACK; + } + break; + + case OS_TMR_OPT_CALLBACK_ARG: + pfnct = ptmr->OSTmrCallback; /* Execute callback function if available ... */ + if (pfnct != (OS_TMR_CALLBACK)0) { + (*pfnct)((void *)ptmr, callback_arg); /* ... using the 'callback_arg' provided in call */ + } else { + *perr = OS_ERR_TMR_NO_CALLBACK; + } + break; + + case OS_TMR_OPT_NONE: + break; + + default: + *perr = OS_ERR_TMR_INVALID_OPT; + break; + } + OSTmr_Unlock(); + return (OS_TRUE); + + case OS_TMR_STATE_COMPLETED: /* Timer has already completed the ONE-SHOT or ... */ + case OS_TMR_STATE_STOPPED: /* ... timer has not started yet. */ + OSTmr_Unlock(); + *perr = OS_ERR_TMR_STOPPED; + return (OS_TRUE); + + case OS_TMR_STATE_UNUSED: /* Timer was not created */ + OSTmr_Unlock(); + *perr = OS_ERR_TMR_INACTIVE; + return (OS_FALSE); + + default: + OSTmr_Unlock(); + *perr = OS_ERR_TMR_INVALID_STATE; + return (OS_FALSE); + } +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* SIGNAL THAT IT'S TIME TO UPDATE THE TIMERS +* +* Description: This function is typically called by the ISR that occurs at the timer tick rate and is used to signal to +* OSTmr_Task() that it's time to update the timers. +* +* Arguments : none +* +* Returns : OS_ERR_NONE The call was successful and the timer task was signaled. +* OS_ERR_SEM_OVF If OSTmrSignal() was called more often than OSTmr_Task() can handle the timers. +* This would indicate that your system is heavily loaded. +* OS_ERR_EVENT_TYPE Unlikely you would get this error because the semaphore used for signaling is created +* by uC/OS-II. +* OS_ERR_PEVENT_NULL Again, unlikely you would ever get this error because the semaphore used for signaling +* is created by uC/OS-II. +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +INT8U OSTmrSignal (void) +{ + INT8U err; + + + err = OSSemPost(OSTmrSemSignal); + return (err); +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* ALLOCATE AND FREE A TIMER +* +* Description: This function is called to allocate a timer. +* +* Arguments : none +* +* Returns : a pointer to a timer if one is available +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +static OS_TMR *OSTmr_Alloc (void) +{ + OS_TMR *ptmr; + + + if (OSTmrFreeList == (OS_TMR *)0) { + return ((OS_TMR *)0); + } + ptmr = (OS_TMR *)OSTmrFreeList; + OSTmrFreeList = (OS_TMR *)ptmr->OSTmrNext; + ptmr->OSTmrNext = (OS_TCB *)0; + ptmr->OSTmrPrev = (OS_TCB *)0; + OSTmrUsed++; + OSTmrFree--; + return (ptmr); +} +#endif + + +/* +************************************************************************************************************************ +* RETURN A TIMER TO THE FREE LIST +* +* Description: This function is called to return a timer object to the free list of timers. +* +* Arguments : ptmr is a pointer to the timer to free +* +* Returns : none +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +static void OSTmr_Free (OS_TMR *ptmr) +{ + ptmr->OSTmrState = OS_TMR_STATE_UNUSED; /* Clear timer object fields */ + ptmr->OSTmrOpt = OS_TMR_OPT_NONE; + ptmr->OSTmrPeriod = 0; + ptmr->OSTmrMatch = 0; + ptmr->OSTmrCallback = (OS_TMR_CALLBACK)0; + ptmr->OSTmrCallbackArg = (void *)0; +#if OS_TMR_CFG_NAME_SIZE > 1 + ptmr->OSTmrName[0] = '?'; /* Unknown name */ + ptmr->OSTmrName[1] = OS_ASCII_NUL; +#endif + + ptmr->OSTmrPrev = (OS_TCB *)0; /* Chain timer to free list */ + ptmr->OSTmrNext = OSTmrFreeList; + OSTmrFreeList = ptmr; + + OSTmrUsed--; /* Update timer object statistics */ + OSTmrFree++; +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* INITIALIZATION +* INITIALIZE THE FREE LIST OF TIMERS +* +* Description: This function is called by OSInit() to initialize the free list of OS_TMRs. +* +* Arguments : none +* +* Returns : none +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +void OSTmr_Init (void) +{ +#if OS_EVENT_NAME_SIZE > 10 + INT8U err; +#endif + INT16U i; + OS_TMR *ptmr1; + OS_TMR *ptmr2; + + + OS_MemClr((INT8U *)&OSTmrTbl[0], sizeof(OSTmrTbl)); /* Clear all the TMRs */ + OS_MemClr((INT8U *)&OSTmrWheelTbl[0], sizeof(OSTmrWheelTbl)); /* Clear the timer wheel */ + + ptmr1 = &OSTmrTbl[0]; + ptmr2 = &OSTmrTbl[1]; + for (i = 0; i < (OS_TMR_CFG_MAX - 1); i++) { /* Init. list of free TMRs */ + ptmr1->OSTmrType = OS_TMR_TYPE; + ptmr1->OSTmrState = OS_TMR_STATE_UNUSED; /* Indicate that timer is inactive */ + ptmr1->OSTmrNext = (void *)ptmr2; /* Link to next timer */ +#if OS_TMR_CFG_NAME_SIZE > 1 + ptmr1->OSTmrName[0] = '?'; /* Unknown name */ + ptmr1->OSTmrName[1] = OS_ASCII_NUL; +#endif + ptmr1++; + ptmr2++; + } + ptmr1->OSTmrType = OS_TMR_TYPE; + ptmr1->OSTmrState = OS_TMR_STATE_UNUSED; /* Indicate that timer is inactive */ + ptmr1->OSTmrNext = (void *)0; /* Last OS_TMR */ +#if OS_TMR_CFG_NAME_SIZE > 1 + ptmr1->OSTmrName[0] = '?'; /* Unknown name */ + ptmr1->OSTmrName[1] = OS_ASCII_NUL; +#endif + OSTmrTime = 0; + OSTmrUsed = 0; + OSTmrFree = OS_TMR_CFG_MAX; + OSTmrFreeList = &OSTmrTbl[0]; + OSTmrSem = OSSemCreate(1); + OSTmrSemSignal = OSSemCreate(0); + +#if OS_EVENT_NAME_SIZE > 18 + OSEventNameSet(OSTmrSem, (INT8U *)"uC/OS-II TmrLock", &err);/* Assign names to semaphores */ +#else +#if OS_EVENT_NAME_SIZE > 10 + OSEventNameSet(OSTmrSem, (INT8U *)"OS-TmrLock", &err); +#endif +#endif + +#if OS_EVENT_NAME_SIZE > 18 + OSEventNameSet(OSTmrSemSignal, (INT8U *)"uC/OS-II TmrSignal", &err); +#else +#if OS_EVENT_NAME_SIZE > 10 + OSEventNameSet(OSTmrSemSignal, (INT8U *)"OS-TmrSig", &err); +#endif +#endif + + OSTmr_InitTask(); +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* INITIALIZE THE TIMER MANAGEMENT TASK +* +* Description: This function is called by OSTmrInit() to create the timer management task. +* +* Arguments : none +* +* Returns : none +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +static void OSTmr_InitTask (void) +{ +#if OS_TASK_NAME_SIZE > 6 + INT8U err; +#endif + + +#if OS_TASK_CREATE_EXT_EN > 0 + #if OS_STK_GROWTH == 1 + (void)OSTaskCreateExt(OSTmr_Task, + (void *)0, /* No arguments passed to OSTmrTask() */ + &OSTmrTaskStk[OS_TASK_TMR_STK_SIZE - 1], /* Set Top-Of-Stack */ + OS_TASK_TMR_PRIO, + OS_TASK_TMR_ID, + &OSTmrTaskStk[0], /* Set Bottom-Of-Stack */ + OS_TASK_TMR_STK_SIZE, + (void *)0, /* No TCB extension */ + OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR); /* Enable stack checking + clear stack */ + #else + (void)OSTaskCreateExt(OSTmr_Task, + (void *)0, /* No arguments passed to OSTmrTask() */ + &OSTmrTaskStk[0], /* Set Top-Of-Stack */ + OS_TASK_TMR_PRIO, + OS_TASK_TMR_ID, + &OSTmrTaskStk[OS_TASK_TMR_STK_SIZE - 1], /* Set Bottom-Of-Stack */ + OS_TASK_TMR_STK_SIZE, + (void *)0, /* No TCB extension */ + OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR); /* Enable stack checking + clear stack */ + #endif +#else + #if OS_STK_GROWTH == 1 + (void)OSTaskCreate(OSTmr_Task, + (void *)0, + &OSTmrTaskStk[OS_TASK_TMR_STK_SIZE - 1], + OS_TASK_TMR_PRIO); + #else + (void)OSTaskCreate(OSTmr_Task, + (void *)0, + &OSTmrTaskStk[0], + OS_TASK_TMR_PRIO); + #endif +#endif + +#if OS_TASK_NAME_SIZE > 12 + OSTaskNameSet(OS_TASK_TMR_PRIO, (INT8U *)"uC/OS-II Tmr", &err); +#else +#if OS_TASK_NAME_SIZE > 6 + OSTaskNameSet(OS_TASK_TMR_PRIO, (INT8U *)"OS-Tmr", &err); +#endif +#endif +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* INSERT A TIMER INTO THE TIMER WHEEL +* +* Description: This function is called to insert the timer into the timer wheel. The timer is always inserted at the +* beginning of the list. +* +* Arguments : ptmr Is a pointer to the timer to insert. +* +* type Is either: +* OS_TMR_LINK_PERIODIC Means to re-insert the timer after a period expired +* OS_TMR_LINK_DLY Means to insert the timer the first time +* +* Returns : none +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +static void OSTmr_Link (OS_TMR *ptmr, INT8U type) +{ + OS_TMR *ptmr1; + OS_TMR_WHEEL *pspoke; + INT16U spoke; + + + ptmr->OSTmrState = OS_TMR_STATE_RUNNING; + if (type == OS_TMR_LINK_PERIODIC) { /* Determine when timer will expire */ + ptmr->OSTmrMatch = ptmr->OSTmrPeriod + OSTmrTime; + } else { + if (ptmr->OSTmrDly == 0) { + ptmr->OSTmrMatch = ptmr->OSTmrPeriod + OSTmrTime; + } else { + ptmr->OSTmrMatch = ptmr->OSTmrDly + OSTmrTime; + } + } + spoke = (INT16U)(ptmr->OSTmrMatch % OS_TMR_CFG_WHEEL_SIZE); + pspoke = &OSTmrWheelTbl[spoke]; + + if (pspoke->OSTmrFirst == (OS_TMR *)0) { /* Link into timer wheel */ + pspoke->OSTmrFirst = ptmr; + ptmr->OSTmrNext = (OS_TMR *)0; + pspoke->OSTmrEntries = 1; + } else { + ptmr1 = pspoke->OSTmrFirst; /* Point to first timer in the spoke */ + pspoke->OSTmrFirst = ptmr; + ptmr->OSTmrNext = (void *)ptmr1; + ptmr1->OSTmrPrev = (void *)ptmr; + pspoke->OSTmrEntries++; + } + ptmr->OSTmrPrev = (void *)0; /* Timer always inserted as first node in list */ +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* REMOVE A TIMER FROM THE TIMER WHEEL +* +* Description: This function is called to remove the timer from the timer wheel. +* +* Arguments : ptmr Is a pointer to the timer to remove. +* +* Returns : none +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +static void OSTmr_Unlink (OS_TMR *ptmr) +{ + OS_TMR *ptmr1; + OS_TMR *ptmr2; + OS_TMR_WHEEL *pspoke; + INT16U spoke; + + + spoke = (INT16U)(ptmr->OSTmrMatch % OS_TMR_CFG_WHEEL_SIZE); + pspoke = &OSTmrWheelTbl[spoke]; + + if (pspoke->OSTmrFirst == ptmr) { /* See if timer to remove is at the beginning of list */ + ptmr1 = (OS_TMR *)ptmr->OSTmrNext; + pspoke->OSTmrFirst = (OS_TMR *)ptmr1; + if (ptmr1 != (OS_TMR *)0) { + ptmr1->OSTmrPrev = (void *)0; + } + } else { + ptmr1 = (OS_TMR *)ptmr->OSTmrPrev; /* Remove timer from somewhere in the list */ + ptmr2 = (OS_TMR *)ptmr->OSTmrNext; + ptmr1->OSTmrNext = ptmr2; + if (ptmr2 != (OS_TMR *)0) { + ptmr2->OSTmrPrev = (void *)ptmr1; + } + } + ptmr->OSTmrState = OS_TMR_STATE_STOPPED; + ptmr->OSTmrNext = (void *)0; + ptmr->OSTmrPrev = (void *)0; + pspoke->OSTmrEntries--; +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* TIMER MANAGER DATA STRUCTURE LOCKING MECHANISM +* +* Description: These functions are used to gain exclusive access to timer management data structures. +* +* Arguments : none +* +* Returns : none +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +static void OSTmr_Lock (void) +{ + INT8U err; + + + OSSemPend(OSTmrSem, 0, &err); + (void)err; +} +#endif + + + +#if OS_TMR_EN > 0 +static void OSTmr_Unlock (void) +{ + (void)OSSemPost(OSTmrSem); +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* TIMER MANAGEMENT TASK +* +* Description: This task is created by OSTmrInit(). +* +* Arguments : none +* +* Returns : none +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +static void OSTmr_Task (void *p_arg) +{ + INT8U err; + OS_TMR *ptmr; + OS_TMR *ptmr_next; + OS_TMR_CALLBACK pfnct; + OS_TMR_WHEEL *pspoke; + INT16U spoke; + + + (void)p_arg; /* Not using 'p_arg', prevent compiler warning */ + for (;;) { + OSSemPend(OSTmrSemSignal, 0, &err); /* Wait for signal indicating time to update timers */ + OSTmr_Lock(); + OSTmrTime++; /* Increment the current time */ + spoke = (INT16U)(OSTmrTime % OS_TMR_CFG_WHEEL_SIZE); /* Position on current timer wheel entry */ + pspoke = &OSTmrWheelTbl[spoke]; + ptmr = pspoke->OSTmrFirst; + while (ptmr != (OS_TMR *)0) { + ptmr_next = (OS_TMR *)ptmr->OSTmrNext; /* Point to next timer to update because current ... */ + /* ... timer could get unlinked from the wheel. */ + if (OSTmrTime == ptmr->OSTmrMatch) { /* Process each timer that expires */ + pfnct = ptmr->OSTmrCallback; /* Execute callback function if available */ + if (pfnct != (OS_TMR_CALLBACK)0) { + (*pfnct)((void *)ptmr, ptmr->OSTmrCallbackArg); + } + OSTmr_Unlink(ptmr); /* Remove from current wheel spoke */ + if (ptmr->OSTmrOpt == OS_TMR_OPT_PERIODIC) { + OSTmr_Link(ptmr, OS_TMR_LINK_PERIODIC); /* Recalculate new position of timer in wheel */ + } else { + ptmr->OSTmrState = OS_TMR_STATE_COMPLETED; /* Indicate that the timer has completed */ + } + } + ptmr = ptmr_next; + } + OSTmr_Unlock(); + } +} +#endif diff --git a/FPGA_nios/hit_pat_bsp/alt_sys_init.c b/FPGA_nios/hit_pat_bsp/alt_sys_init.c new file mode 100644 index 0000000..dcedff4 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/alt_sys_init.c @@ -0,0 +1,115 @@ +/* + * alt_sys_init.c - HAL initialization source + * + * Machine generated for CPU 'cpu' in SOPC Builder design 'q_sys' + * SOPC Builder design path: D:/hit20v3/software/hit_pat/q_sys.sopcinfo + * + * Generated: Thu Jun 08 10:06:13 CEST 2023 + */ + +/* + * DO NOT MODIFY THIS FILE + * + * Changing this file will have subtle consequences + * which will almost certainly lead to a nonfunctioning + * system. If you do modify this file, be aware that your + * changes will be overwritten and lost when this file + * is generated again. + * + * DO NOT MODIFY THIS FILE + */ + +/* + * License Agreement + * + * Copyright (c) 2008 + * Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This agreement shall be governed in all respects by the laws of the State + * of California and by the laws of the United States of America. + */ + +#include "system.h" +#include "sys/alt_irq.h" +#include "sys/alt_sys_init.h" + +#include + +/* + * Device headers + */ + +#include "altera_nios2_gen2_irq.h" +#include "altera_avalon_sysid_qsys.h" +#include "altera_avalon_timer.h" +#include "altera_avalon_uart.h" +#include "altera_eth_tse.h" +#include "altera_generic_quad_spi_controller.h" +#include "altera_msgdma.h" +#include "altera_onchip_flash.h" + +/* + * Allocate the device storage + */ + +ALTERA_NIOS2_GEN2_IRQ_INSTANCE ( CPU, cpu); +ALTERA_AVALON_SYSID_QSYS_INSTANCE ( SYSID, sysid); +ALTERA_AVALON_TIMER_INSTANCE ( FRAME_TIMER, frame_timer); +ALTERA_AVALON_TIMER_INSTANCE ( SYS_CLK_TIMER, sys_clk_timer); +ALTERA_AVALON_UART_INSTANCE ( DEBUG_UART, debug_uart); +ALTERA_ETH_TSE_INSTANCE ( ETH_TSE, eth_tse); +ALTERA_GENERIC_QUAD_SPI_CONTROLLER_AVL_MEM_AVL_CSR_INSTANCE ( EXT_FLASH, EXT_FLASH_AVL_MEM, EXT_FLASH_AVL_CSR, ext_flash); +ALTERA_MSGDMA_CSR_PREFETCHER_CSR_INSTANCE ( MSGDMA_RX, MSGDMA_RX_CSR, MSGDMA_RX_PREFETCHER_CSR, msgdma_rx); +ALTERA_MSGDMA_CSR_PREFETCHER_CSR_INSTANCE ( MSGDMA_TX, MSGDMA_TX_CSR, MSGDMA_TX_PREFETCHER_CSR, msgdma_tx); +ALTERA_ONCHIP_FLASH_DATA_CSR_INSTANCE ( ONCHIP_FLASH, ONCHIP_FLASH_DATA, ONCHIP_FLASH_CSR, onchip_flash); + +/* + * Initialize the interrupt controller devices + * and then enable interrupts in the CPU. + * Called before alt_sys_init(). + * The "base" parameter is ignored and only + * present for backwards-compatibility. + */ + +void alt_irq_init ( const void* base ) +{ + ALTERA_NIOS2_GEN2_IRQ_INIT ( CPU, cpu); + alt_irq_cpu_enable_interrupts(); +} + +/* + * Initialize the non-interrupt controller devices. + * Called after alt_irq_init(). + */ + +void alt_sys_init( void ) +{ + ALTERA_AVALON_TIMER_INIT ( FRAME_TIMER, frame_timer); + ALTERA_AVALON_TIMER_INIT ( SYS_CLK_TIMER, sys_clk_timer); + ALTERA_AVALON_SYSID_QSYS_INIT ( SYSID, sysid); + ALTERA_AVALON_UART_INIT ( DEBUG_UART, debug_uart); + ALTERA_ETH_TSE_INIT ( ETH_TSE, eth_tse); + ALTERA_GENERIC_QUAD_SPI_CONTROLLER_INIT ( EXT_FLASH, ext_flash); + ALTERA_MSGDMA_INIT ( MSGDMA_RX, msgdma_rx); + ALTERA_MSGDMA_INIT ( MSGDMA_TX, msgdma_tx); + ALTERA_ONCHIP_FLASH_INIT ( ONCHIP_FLASH, onchip_flash); +} diff --git a/FPGA_nios/hit_pat_bsp/create-this-bsp b/FPGA_nios/hit_pat_bsp/create-this-bsp new file mode 100644 index 0000000..acc3e00 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/create-this-bsp @@ -0,0 +1,52 @@ +#!/bin/bash +# +# This script creates the ucosii_net_zipfs Board Support Package (BSP). + +BSP_TYPE=ucosii +BSP_DIR=. +SOPC_DIR=../../ +SOPC_FILE=../../q_sys.sopcinfo +NIOS2_BSP_ARGS="--set hal.make.bsp_cflags_defined_symbols -DTSE_MY_SYSTEM --cmd enable_sw_package altera_iniche" +CPU_NAME= + +if [ -n "$CPU_NAME" ]; then + NIOS2_BSP_ARGS="$NIOS2_BSP_ARGS --cpu-name $CPU_NAME" +fi + +# Don't run make if create-this-app script is called with --no-make arg +SKIP_MAKE= +while [ $# -gt 0 ] +do + case "$1" in + --no-make) + SKIP_MAKE=1 + ;; + *) + NIOS2_BSP_ARGS="$NIOS2_BSP_ARGS $1" + ;; + esac + shift +done + + +# Run nios2-bsp utility to create a ucosii BSP in this directory +# for the system with a .sopc file in $SOPC_FILE. +# Deprecating $SOPC_DIR in 10.1. Multiple .sopcinfo files in a directory may exist. + +if [ -z "$SOPC_FILE" ]; then + echo "WARNING: Use of a directory for locating a .sopcinfo file is deprecated in 10.1. Multiple .sopcinfo files may exist. You must specify the full .sopcinfo path." + cmd="nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_DIR $NIOS2_BSP_ARGS" +else + cmd="nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_FILE $NIOS2_BSP_ARGS" +fi + + +echo "create-this-bsp: Running \"$cmd\"" +$cmd || { + echo "$cmd failed" + exit 1 +} +if [ -z "$SKIP_MAKE" ]; then + echo "create-this-bsp: Running make" + make +fi diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_pio_regs.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_pio_regs.h new file mode 100644 index 0000000..a829ddd --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_pio_regs.h @@ -0,0 +1,67 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_PIO_REGS_H__ +#define __ALTERA_AVALON_PIO_REGS_H__ + +#include + +#define IOADDR_ALTERA_AVALON_PIO_DATA(base) __IO_CALC_ADDRESS_NATIVE(base, 0) +#define IORD_ALTERA_AVALON_PIO_DATA(base) IORD(base, 0) +#define IOWR_ALTERA_AVALON_PIO_DATA(base, data) IOWR(base, 0, data) + +#define IOADDR_ALTERA_AVALON_PIO_DIRECTION(base) __IO_CALC_ADDRESS_NATIVE(base, 1) +#define IORD_ALTERA_AVALON_PIO_DIRECTION(base) IORD(base, 1) +#define IOWR_ALTERA_AVALON_PIO_DIRECTION(base, data) IOWR(base, 1, data) + +#define IOADDR_ALTERA_AVALON_PIO_IRQ_MASK(base) __IO_CALC_ADDRESS_NATIVE(base, 2) +#define IORD_ALTERA_AVALON_PIO_IRQ_MASK(base) IORD(base, 2) +#define IOWR_ALTERA_AVALON_PIO_IRQ_MASK(base, data) IOWR(base, 2, data) + +#define IOADDR_ALTERA_AVALON_PIO_EDGE_CAP(base) __IO_CALC_ADDRESS_NATIVE(base, 3) +#define IORD_ALTERA_AVALON_PIO_EDGE_CAP(base) IORD(base, 3) +#define IOWR_ALTERA_AVALON_PIO_EDGE_CAP(base, data) IOWR(base, 3, data) + + +#define IOADDR_ALTERA_AVALON_PIO_SET_BIT(base) __IO_CALC_ADDRESS_NATIVE(base, 4) +#define IORD_ALTERA_AVALON_PIO_SET_BITS(base) IORD(base, 4) +#define IOWR_ALTERA_AVALON_PIO_SET_BITS(base, data) IOWR(base, 4, data) + +#define IOADDR_ALTERA_AVALON_PIO_CLEAR_BITS(base) __IO_CALC_ADDRESS_NATIVE(base, 5) +#define IORD_ALTERA_AVALON_PIO_CLEAR_BITS(base) IORD(base, 5) +#define IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(base, data) IOWR(base, 5, data) + + + +/* Defintions for direction-register operation with bi-directional PIOs */ +#define ALTERA_AVALON_PIO_DIRECTION_INPUT 0 +#define ALTERA_AVALON_PIO_DIRECTION_OUTPUT 1 + +#endif /* __ALTERA_AVALON_PIO_REGS_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_sysid_qsys.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_sysid_qsys.h new file mode 100644 index 0000000..f62bc22 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_sysid_qsys.h @@ -0,0 +1,60 @@ +#ifndef __ALT_AVALON_SYSID_QSYS_H__ +#define __ALT_AVALON_SYSID_QSYS_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "alt_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * ALTERA_AVALON_SYSID_QSYS_INSTANCE is the macro used by alt_sys_init() to + * allocate any per device memory that may be required. In this case no + * allocation is necessary. + */ + +#define ALTERA_AVALON_SYSID_QSYS_INSTANCE(name, dev) extern int alt_no_storage +#define ALTERA_AVALON_SYSID_QSYS_INIT(name, dev) while (0) + +#ifdef SYSID_BASE +alt_32 alt_avalon_sysid_qsys_test(void); +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_AVALON_SYSID_QSYS_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_sysid_qsys_regs.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_sysid_qsys_regs.h new file mode 100644 index 0000000..9801855 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_sysid_qsys_regs.h @@ -0,0 +1,42 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_SYSID_QSYS_REGS_H__ +#define __ALTERA_AVALON_SYSID_QSYS_REGS_H__ + +#include + +#define IOADDR_ALTERA_AVALON_SYSID_QSYS_ID(base) __IO_CALC_ADDRESS_NATIVE(base, 0) +#define IORD_ALTERA_AVALON_SYSID_QSYS_ID(base) IORD(base, 0) + +#define IOADDR_ALTERA_AVALON_SYSID_QSYS_TIMESTAMP(base) __IO_CALC_ADDRESS_NATIVE(base, 1) +#define IORD_ALTERA_AVALON_SYSID_QSYS_TIMESTAMP(base) IORD(base, 1) + +#endif /* __ALTERA_AVALON_SYSID_QSYS_REGS_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_timer.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_timer.h new file mode 100644 index 0000000..a928483 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_timer.h @@ -0,0 +1,193 @@ +#ifndef __ALT_AVALON_TIMER_H__ +#define __ALT_AVALON_TIMER_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "alt_types.h" +#include "sys/alt_dev.h" +#include "sys/alt_warning.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + + +#define __ALT_COUNTER_SIZE(name) name##_COUNTER_SIZE +#define _ALT_COUNTER_SIZE(name) __ALT_COUNTER_SIZE(name) + +#define ALT_SYS_CLK_COUNTER_SIZE _ALT_COUNTER_SIZE(ALT_SYS_CLK) +#define ALT_TIMESTAMP_COUNTER_SIZE _ALT_COUNTER_SIZE(ALT_TIMESTAMP_CLK) + +#if (ALT_SYS_CLK_COUNTER_SIZE == 64) +#define alt_sysclk_type alt_u64 +#else +#define alt_sysclk_type alt_u32 +#endif + +#if (ALT_TIMESTAMP_COUNTER_SIZE == 64) +#define alt_timestamp_type alt_u64 +#else +#define alt_timestamp_type alt_u32 +#endif + +/* + * The function alt_avalon_timer_sc_init() is the initialisation function for + * the system clock. It registers the timers interrupt handler, and then calls + * the system clock regestration function, alt_sysclk_init(). + */ + +extern void alt_avalon_timer_sc_init (void* base, alt_u32 irq_controller_id, + alt_u32 irq, alt_u32 freq); + +/* + * Variables used to store the timestamp parameters, when the device is to be + * accessed using the high resolution timestamp driver. + */ + +extern void* altera_avalon_timer_ts_base; +extern alt_u32 altera_avalon_timer_ts_freq; + +/* + * ALTERA_AVALON_TIMER_INSTANCE is the macro used by alt_sys_init() to + * allocate any per device memory that may be required. In this case no + * allocation is necessary. + */ + +#define ALTERA_AVALON_TIMER_INSTANCE(name, dev) extern int alt_no_storage + +/* + * Macro used to calculate the timer interrupt frequency. Although this is + * somewhat fearsome, when compiled with -O2 it will be resolved at compile + * time to a constant value. + */ + +#define ALTERA_AVALON_TIMER_FREQ(freq, period, units) \ + strcmp (units, "us") ? \ + (strcmp (units, "ms") ? \ + (strcmp (units, "s") ? \ + ((freq + (period - 1))/period) \ + : 1) \ + : (1000 + (period - 1))/period) \ + : ((1000000 + (period - 1))/period) + +/* + * Construct macros which contain the base address of the system clock and the + * timestamp device. These are used below to determine which driver to use for + * a given timer. + */ + +#define __ALT_CLK_BASE(name) name##_BASE +#define _ALT_CLK_BASE(name) __ALT_CLK_BASE(name) + +#define ALT_SYS_CLK_BASE _ALT_CLK_BASE(ALT_SYS_CLK) +#define ALT_TIMESTAMP_CLK_BASE _ALT_CLK_BASE(ALT_TIMESTAMP_CLK) + +/* + * If there is no system clock, then the above macro will result in + * ALT_SYS_CLK_BASE being set to none_BASE. We therefore need to provide an + * invalid value for this, so that no timer is wrongly identified as the system + * clock. + */ + +#define none_BASE 0xffffffff + +/* + * ALTERA_AVALON_TIMER_INIT is the macro used by alt_sys_init() to provide + * the run time initialisation of the device. In this case this translates to + * a call to alt_avalon_timer_sc_init() if the device is the system clock, i.e. + * if it has the name "sysclk". + * + * If the device is not the system clock, then it is used to provide the + * timestamp facility. + * + * To ensure as much as possible is evaluated at compile time, rather than + * compare the name of the device to "/dev/sysclk" using strcmp(), the base + * address of the device is compared to SYSCLK_BASE to determine whether it's + * the system clock. Since the base address of a device must be unique, these + * two aproaches are equivalent. + * + * This macro performs a sanity check to ensure that the interrupt has been + * connected for this device. If not, then an apropriate error message is + * generated at build time. + */ + + +#define ALTERA_AVALON_TIMER_INIT(name, dev) \ + if (name##_BASE == ALT_SYS_CLK_BASE) \ + { \ + if (name##_IRQ == ALT_IRQ_NOT_CONNECTED) \ + { \ + ALT_LINK_ERROR ("Error: Interrupt not connected for " #dev ". " \ + "The system clock driver requires an interrupt to be " \ + "connected. Please select an IRQ for this device in " \ + "SOPC builder."); \ + } \ + else \ + { \ + alt_avalon_timer_sc_init((void*) name##_BASE, \ + name##_IRQ_INTERRUPT_CONTROLLER_ID, \ + name##_IRQ, \ + ALTERA_AVALON_TIMER_FREQ(name##_FREQ, \ + name##_PERIOD, \ + name##_PERIOD_UNITS));\ + } \ + } \ + else if (name##_BASE == ALT_TIMESTAMP_CLK_BASE) \ + { \ + if (name##_SNAPSHOT) \ + { \ + altera_avalon_timer_ts_base = (void*) name##_BASE; \ + altera_avalon_timer_ts_freq = name##_FREQ; \ + } \ + else \ + { \ + ALT_LINK_ERROR ("Error: Snapshot register not available for " \ + #dev ". " \ + "The timestamp driver requires the snapshot register " \ + "to be readable. Please enable this register for this " \ + "device in SOPC builder."); \ + } \ + } + +/* + * + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_AVALON_TIMER_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_timer_regs.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_timer_regs.h new file mode 100644 index 0000000..d9420d5 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_timer_regs.h @@ -0,0 +1,202 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_TIMER_REGS_H__ +#define __ALTERA_AVALON_TIMER_REGS_H__ + +#include + +/* STATUS register */ +#define ALTERA_AVALON_TIMER_STATUS_REG 0 +#define IOADDR_ALTERA_AVALON_TIMER_STATUS(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_STATUS_REG) +#define IORD_ALTERA_AVALON_TIMER_STATUS(base) \ + IORD(base, ALTERA_AVALON_TIMER_STATUS_REG) +#define IOWR_ALTERA_AVALON_TIMER_STATUS(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_STATUS_REG, data) +#define ALTERA_AVALON_TIMER_STATUS_TO_MSK (0x1) +#define ALTERA_AVALON_TIMER_STATUS_TO_OFST (0) +#define ALTERA_AVALON_TIMER_STATUS_RUN_MSK (0x2) +#define ALTERA_AVALON_TIMER_STATUS_RUN_OFST (1) + +/* CONTROL register */ +#define ALTERA_AVALON_TIMER_CONTROL_REG 1 +#define IOADDR_ALTERA_AVALON_TIMER_CONTROL(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_CONTROL_REG) +#define IORD_ALTERA_AVALON_TIMER_CONTROL(base) \ + IORD(base, ALTERA_AVALON_TIMER_CONTROL_REG) +#define IOWR_ALTERA_AVALON_TIMER_CONTROL(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_CONTROL_REG, data) +#define ALTERA_AVALON_TIMER_CONTROL_ITO_MSK (0x1) +#define ALTERA_AVALON_TIMER_CONTROL_ITO_OFST (0) +#define ALTERA_AVALON_TIMER_CONTROL_CONT_MSK (0x2) +#define ALTERA_AVALON_TIMER_CONTROL_CONT_OFST (1) +#define ALTERA_AVALON_TIMER_CONTROL_START_MSK (0x4) +#define ALTERA_AVALON_TIMER_CONTROL_START_OFST (2) +#define ALTERA_AVALON_TIMER_CONTROL_STOP_MSK (0x8) +#define ALTERA_AVALON_TIMER_CONTROL_STOP_OFST (3) + +/* Period and SnapShot Register for COUNTER_SIZE = 32 */ +/*----------------------------------------------------*/ +/* PERIODL register */ +#define ALTERA_AVALON_TIMER_PERIODL_REG 2 +#define IOADDR_ALTERA_AVALON_TIMER_PERIODL(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIODL_REG) +#define IORD_ALTERA_AVALON_TIMER_PERIODL(base) \ + IORD(base, ALTERA_AVALON_TIMER_PERIODL_REG) +#define IOWR_ALTERA_AVALON_TIMER_PERIODL(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_PERIODL_REG, data) +#define ALTERA_AVALON_TIMER_PERIODL_MSK (0xFFFF) +#define ALTERA_AVALON_TIMER_PERIODL_OFST (0) + +/* PERIODH register */ +#define ALTERA_AVALON_TIMER_PERIODH_REG 3 +#define IOADDR_ALTERA_AVALON_TIMER_PERIODH(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIODH_REG) +#define IORD_ALTERA_AVALON_TIMER_PERIODH(base) \ + IORD(base, ALTERA_AVALON_TIMER_PERIODH_REG) +#define IOWR_ALTERA_AVALON_TIMER_PERIODH(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_PERIODH_REG, data) +#define ALTERA_AVALON_TIMER_PERIODH_MSK (0xFFFF) +#define ALTERA_AVALON_TIMER_PERIODH_OFST (0) + +/* SNAPL register */ +#define ALTERA_AVALON_TIMER_SNAPL_REG 4 +#define IOADDR_ALTERA_AVALON_TIMER_SNAPL(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAPL_REG) +#define IORD_ALTERA_AVALON_TIMER_SNAPL(base) \ + IORD(base, ALTERA_AVALON_TIMER_SNAPL_REG) +#define IOWR_ALTERA_AVALON_TIMER_SNAPL(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_SNAPL_REG, data) +#define ALTERA_AVALON_TIMER_SNAPL_MSK (0xFFFF) +#define ALTERA_AVALON_TIMER_SNAPL_OFST (0) + +/* SNAPH register */ +#define ALTERA_AVALON_TIMER_SNAPH_REG 5 +#define IOADDR_ALTERA_AVALON_TIMER_SNAPH(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAPH_REG) +#define IORD_ALTERA_AVALON_TIMER_SNAPH(base) \ + IORD(base, ALTERA_AVALON_TIMER_SNAPH_REG) +#define IOWR_ALTERA_AVALON_TIMER_SNAPH(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_SNAPH_REG, data) +#define ALTERA_AVALON_TIMER_SNAPH_MSK (0xFFFF) +#define ALTERA_AVALON_TIMER_SNAPH_OFST (0) + +/* Period and SnapShot Register for COUNTER_SIZE = 64 */ +/*----------------------------------------------------*/ +/* PERIOD_0 register */ +#define ALTERA_AVALON_TIMER_PERIOD_0_REG 2 +#define IOADDR_ALTERA_AVALON_TIMER_PERIOD_0(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_0_REG) +#define IORD_ALTERA_AVALON_TIMER_PERIOD_0(base) \ + IORD(base, ALTERA_AVALON_TIMER_PERIOD_0_REG) +#define IOWR_ALTERA_AVALON_TIMER_PERIOD_0(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_PERIOD_0_REG, data) +#define ALTERA_AVALON_TIMER_PERIOD_0_MSK (0xFFFF) +#define ALTERA_AVALON_TIMER_PERIOD_0_OFST (0) + +/* PERIOD_1 register */ +#define ALTERA_AVALON_TIMER_PERIOD_1_REG 3 +#define IOADDR_ALTERA_AVALON_TIMER_PERIOD_1(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_1_REG) +#define IORD_ALTERA_AVALON_TIMER_PERIOD_1(base) \ + IORD(base, ALTERA_AVALON_TIMER_PERIOD_1_REG) +#define IOWR_ALTERA_AVALON_TIMER_PERIOD_1(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_PERIOD_1_REG, data) +#define ALTERA_AVALON_TIMER_PERIOD_1_MSK (0xFFFF) +#define ALTERA_AVALON_TIMER_PERIOD_1_OFST (0) + +/* PERIOD_2 register */ +#define ALTERA_AVALON_TIMER_PERIOD_2_REG 4 +#define IOADDR_ALTERA_AVALON_TIMER_PERIOD_2(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_2_REG) +#define IORD_ALTERA_AVALON_TIMER_PERIOD_2(base) \ + IORD(base, ALTERA_AVALON_TIMER_PERIOD_2_REG) +#define IOWR_ALTERA_AVALON_TIMER_PERIOD_2(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_PERIOD_2_REG, data) +#define ALTERA_AVALON_TIMER_PERIOD_2_MSK (0xFFFF) +#define ALTERA_AVALON_TIMER_PERIOD_2_OFST (0) + +/* PERIOD_3 register */ +#define ALTERA_AVALON_TIMER_PERIOD_3_REG 5 +#define IOADDR_ALTERA_AVALON_TIMER_PERIOD_3(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_3_REG) +#define IORD_ALTERA_AVALON_TIMER_PERIOD_3(base) \ + IORD(base, ALTERA_AVALON_TIMER_PERIOD_3_REG) +#define IOWR_ALTERA_AVALON_TIMER_PERIOD_3(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_PERIOD_3_REG, data) +#define ALTERA_AVALON_TIMER_PERIOD_3_MSK (0xFFFF) +#define ALTERA_AVALON_TIMER_PERIOD_3_OFST (0) + +/* SNAP_0 register */ +#define ALTERA_AVALON_TIMER_SNAP_0_REG 6 +#define IOADDR_ALTERA_AVALON_TIMER_SNAP_0(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_0_REG) +#define IORD_ALTERA_AVALON_TIMER_SNAP_0(base) \ + IORD(base, ALTERA_AVALON_TIMER_SNAP_0_REG) +#define IOWR_ALTERA_AVALON_TIMER_SNAP_0(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_SNAP_0_REG, data) +#define ALTERA_AVALON_TIMER_SNAP_0_MSK (0xFFFF) +#define ALTERA_AVALON_TIMER_SNAP_0_OFST (0) + +/* SNAP_1 register */ +#define ALTERA_AVALON_TIMER_SNAP_1_REG 7 +#define IOADDR_ALTERA_AVALON_TIMER_SNAP_1(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_1_REG) +#define IORD_ALTERA_AVALON_TIMER_SNAP_1(base) \ + IORD(base, ALTERA_AVALON_TIMER_SNAP_1_REG) +#define IOWR_ALTERA_AVALON_TIMER_SNAP_1(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_SNAP_1_REG, data) +#define ALTERA_AVALON_TIMER_SNAP_1_MSK (0xFFFF) +#define ALTERA_AVALON_TIMER_SNAP_1_OFST (0) + +/* SNAP_2 register */ +#define ALTERA_AVALON_TIMER_SNAP_2_REG 8 +#define IOADDR_ALTERA_AVALON_TIMER_SNAP_2(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_2_REG) +#define IORD_ALTERA_AVALON_TIMER_SNAP_2(base) \ + IORD(base, ALTERA_AVALON_TIMER_SNAP_2_REG) +#define IOWR_ALTERA_AVALON_TIMER_SNAP_2(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_SNAP_2_REG, data) +#define ALTERA_AVALON_TIMER_SNAP_2_MSK (0xFFFF) +#define ALTERA_AVALON_TIMER_SNAP_2_OFST (0) + +/* SNAP_3 register */ +#define ALTERA_AVALON_TIMER_SNAP_3_REG 9 +#define IOADDR_ALTERA_AVALON_TIMER_SNAP_3(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_3_REG) +#define IORD_ALTERA_AVALON_TIMER_SNAP_3(base) \ + IORD(base, ALTERA_AVALON_TIMER_SNAP_3_REG) +#define IOWR_ALTERA_AVALON_TIMER_SNAP_3(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_SNAP_3_REG, data) +#define ALTERA_AVALON_TIMER_SNAP_3_MSK (0xFFFF) +#define ALTERA_AVALON_TIMER_SNAP_3_OFST (0) + +#endif /* __ALTERA_AVALON_TIMER_REGS_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_tse.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_tse.h new file mode 100644 index 0000000..53ab7da --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_tse.h @@ -0,0 +1,1023 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_TSE_H__ +#define __ALTERA_AVALON_TSE_H__ + +#include "altera_eth_tse_regs.h" +#include "system.h" /* check if SGDMA is used */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + + + +/* TSE DEBUG Message Level */ +/* Level 6 : Info + * Level 5 : Debug Info + * Level 4 : Warning + * Level 3 : Critical Warning + * Level 2 : Error + * Level 1 : Critical Error, eg: malloc() failed + */ + +#ifndef TSE_DEBUG_LEVEL + #define TSE_DEBUG_LEVEL 6 +#endif + +/* definition without InterNiche */ +#ifndef ALT_INICHE +#define SUCCESS 0 /* whatever the call was, it worked. */ +#define ENP_RESOURCE -22 /* ran out of other queue-able resource */ +#define ENP_PARAM -10 /* bad parameter */ + +#define MAXNETS 8 /* max ifaces to support at one time */ + +#ifdef ALT_DEBUG +#define tse_dprintf(level, fmt, rest...) \ + if(level <= TSE_DEBUG_LEVEL) { \ + printf (fmt, ## rest); \ + } \ + else { \ + no_printf (fmt, ## rest); \ + } +#else +#define tse_dprintf(level, fmt, rest...) no_printf (fmt, ## rest) +#endif /* ALT_DEBUG */ + +#else /* ALT_INICHE */ +#include "ipport.h" + +#define tse_dprintf(level, fmt, rest...) \ + if(level <= TSE_DEBUG_LEVEL) { \ + dprintf (fmt, ## rest); \ + } \ + else { \ + no_printf (fmt, ## rest); \ + } +#endif /* ALT_INICHE */ + + +void no_printf (char *fmt, ...); + + + +/* MSGDMA dependent */ +#ifdef __ALTERA_MSGDMA +#include "altera_msgdma.h" + +/* Device addressing struct for all hardware TSE MAC depends on */ +typedef struct tse_mac_trans_info_struct { + np_tse_mac *base; + alt_msgdma_dev *tx_msgdma; + alt_msgdma_dev *rx_msgdma; + alt_u32 *rx_msgdma_desc_ram; + alt_u32 cfgflags; // flags or'ed during initialization of COMMAND_CONFIG +} tse_mac_trans_info; + + +/** @Function Description - Perform initialization steps on transaction info structure to prepare it for . + * use by the library functions with two MSGDMAs and extra initialization Flags + * @API Type: Internal + * @param mi Main Device Structure. + * @param mac_base Base Address of the Control interface for the TSE MAC + * @param tx_msgdma MSGDMA device handle for TSE transmit data path + * @param rx_msgdma MSGDMA device handle for TSE receive data path + * @param cfgflags initialization flags for the device + * @return SUCCESS + */ + +alt_32 tse_mac_initTransInfo2( tse_mac_trans_info *mi, + alt_u32 mac_base, + alt_32 tx_msgdma, + alt_32 rx_msgdma, + alt_32 cfgflags); + +/** @Function Description - Synchronous MSGDMA copy from buffer memory into transmit FIFO. Waits until + * MSGDMA has completed. Raw function without any error checks. + * @API Type: Internal + * @param mi Main Device Structure. + * @param txDesc Pointer to the transmit MSGDMA descriptor + * @return actual bytes transferred if ok else ENP_RESOURCE if error + */ +alt_32 tse_mac_sTxWrite( tse_mac_trans_info *mi, + alt_msgdma_standard_descriptor *txDesc); + + + +/** @Function Description - Asynchronous MSGDMA copy from buffer memory into rxFIFO. + * Raw function without any transfer error checks. + * + * @API Type: Internal + * @param mi Main Device Structure. + * @param rxDesc Pointer to the receive MSGDMA descriptor + * @return SUCCESS if ok else -1 if error + */ +alt_32 tse_mac_aTxWrite( tse_mac_trans_info *mi, + alt_msgdma_prefetcher_standard_descriptor *txDesc); + + + +/** @Function Description - Asynchronous MSGDMA copy from rxFIFO into given buffer memory area. + * Raw function without any error checks. + * + * @API Type: Internal + * @param mi Main Device Structure. + * @param rxDesc Pointer to the receive MSGDMA descriptor + * @return SUCCESS if ok else ENP_RESOURCE if error + * + * Note: At the point of this function call return, + * the MSGDMA asynchronous operation may not have been + * completed yet, so the function does not return + * the actual bytes transferred for current descriptor + */ +alt_32 tse_mac_aRxRead(tse_mac_trans_info *mi, alt_msgdma_prefetcher_standard_descriptor *rxDesc); + +#endif /* __ALTERA_MSGDMA */ + + + + + + +/*** Debug Definition *********/ +/* change ENABLE_PHY_LOOPBACK to 1 to enable PHY loopback for debug purpose */ +#ifndef ENABLE_PHY_LOOPBACK + #define ENABLE_PHY_LOOPBACK 0 +#endif + +#ifndef pnull +#define pnull ((void *)0) +#endif + +/* Constant definition for tse_system_info.h */ +#define TSE_EXT_DESC_MEM 1 +#define TSE_INT_DESC_MEM 0 + +#define TSE_USE_SHARED_FIFO 1 +#define TSE_NO_SHARED_FIFO 0 + +#define TSE_ENABLE_MDIO_SHARING 1 + +/* Multi-channel Shared FIFO Depth Settings */ +#ifndef ALTERA_TSE_SHARED_FIFO_TX_DEPTH_DEFAULT + #define ALTERA_TSE_SHARED_FIFO_TX_DEPTH_DEFAULT 2040 +#endif + +#ifndef ALTERA_TSE_SHARED_FIFO_RX_DEPTH_DEFAULT + #define ALTERA_TSE_SHARED_FIFO_RX_DEPTH_DEFAULT 2040 +#endif + + +/* PHY Status definition */ +#define TSE_PHY_AUTO_ADDRESS -1 +#define TSE_PHY_MAP_SUCCESS 0 +#define TSE_PHY_MAP_ERROR -1 + +#define TSE_PHY_AN_NOT_COMPLETE -1 +#define TSE_PHY_AN_NOT_CAPABLE -2 +#define TSE_PHY_AN_COMPLETE 0 +#define TSE_PHY_SPEED_INVALID 3 +#define TSE_PHY_SPEED_1000 2 +#define TSE_PHY_SPEED_100 1 +#define TSE_PHY_SPEED_10 0 +#define TSE_PHY_SPEED_NO_COMMON -1 +#define TSE_PHY_DUPLEX_FULL 1 +#define TSE_PHY_DUPLEX_HALF 0 + +/* getPHYSpeed return error */ +enum { + ALT_TSE_E_NO_PMAC_FOUND = (1 << 23), + ALT_TSE_E_NO_MDIO = (1 << 22), + ALT_TSE_E_NO_PHY = (1 << 21), + ALT_TSE_E_NO_COMMON_SPEED = (1 << 20), + ALT_TSE_E_AN_NOT_COMPLETE = (1 << 19), + ALT_TSE_E_NO_PHY_PROFILE = (1 << 18), + ALT_TSE_E_PROFILE_INCORRECT_DEFINED = (1 << 17), + ALT_TSE_E_INVALID_SPEED = (1 << 16) +}; + +/* Maximum number of PHY that can be registered into PHY profile */ +#define TSE_MAX_PHY_PROFILE 8 + +/* Maximum MAC in system */ +#define TSE_MAX_MAC_IN_SYSTEM MAXNETS +#define TSE_MAX_CHANNEL MAXNETS + + +/* System Constant Definition Used in the TSE Driver Code */ + + +#define ALTERA_TSE_SW_RESET_TIME_OUT_CNT 10000 +#define ALTERA_TSE_MSGDMA_BUSY_TIME_OUT_CNT 1000000 + +//These values reflect useable chain size plus 1 for ending descriptor +#define ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE 9 +#define ALTERA_TSE_MSGDMA_TX_DESC_CHAIN_SIZE 2 /* currently only a value of 2 is supported */ + +#define ALTERA_TSE_MAC_MAX_FRAME_LENGTH 1518 + + +#define ALTERA_TSE_FULL_MAC 0 +#define ALTERA_TSE_MACLITE_10_100 1 +#define ALTERA_TSE_MACLITE_1000 2 + +#define ALTERA_TSE_NO_INDEX_FOUND -1 +#define ALTERA_TSE_SYSTEM_DEF_ERROR -1 +#define ALTERA_TSE_MALLOC_FAILED -1 + +#define ALTERA_TSE_DUPLEX_MODE_DEFAULT TSE_PHY_DUPLEX_FULL +#define ALTERA_TSE_MAC_SPEED_DEFAULT TSE_PHY_SPEED_100 +/* added as bsp public makefile settings +#define ALTERA_AUTONEG_TIMEOUT_THRESHOLD 2500 +#define ALTERA_CHECKLINK_TIMEOUT_THRESHOLD 10000 +#define ALTERA_NOMDIO_TIMEOUT_THRESHOLD 1000000 +#define ALTERA_DISGIGA_TIMEOUT_THRESHOLD 5000000 +*/ + +#define ALTERA_TSE_PCS_IF_MODE 0x14 /* 0x14th register of ALTERA PCS */ + +/* PHY ID, backward compatible */ +#define NTL848PHY_ID 0x20005c90 /* National 83848, 10/100 */ +#define MTIPPCS_ID 0x00010000 /* MTIP 1000 Base-X PCS */ +#define TDKPHY_ID 0x0300e540 /* TDK 78Q2120 10/100 */ +#define NTLPHY_ID 0x20005c7a /* National DP83865 */ +#define MVLPHY_ID 0x0141 /* Marvell 88E1111 */ + + + +/* PHY ID */ +/* Marvell PHY on PHYWORKX board */ +enum { + MV88E1111_OUI = 0x005043, + MV88E1111_MODEL = 0x0c, + MV88E1111_REV = 0x2 +}; + +/* Marvell Quad PHY on PHYWORKX board */ +enum { + MV88E1145_OUI = 0x005043, + MV88E1145_MODEL = 0x0d, + MV88E1145_REV = 0x2 +}; + +/* National PHY on PHYWORKX board */ +enum { + DP83865_OUI = 0x080017, + DP83865_MODEL = 0x07, + DP83865_REV = 0xa +}; + +/* National 10/100 PHY on PHYWORKX board */ +enum { + DP83848C_OUI = 0x080017, + DP83848C_MODEL = 0x09, + DP83848C_REV = 0x0 +}; + +/* Intel PEF7071 Phy on C10 Devkit */ +enum { + PEF7071_OUI = ((0xd565 << 6) | ((0xa401 >> 10) & 0x3f)), + PEF7071_MODEL = ((0xa401 >> 4) & 0x3f), + PEF7071_REV = (0xa401 & 0x0f) +}; + + + +/* PHY register definition */ +enum { + TSE_PHY_MDIO_CONTROL = 0, + TSE_PHY_MDIO_STATUS = 1, + TSE_PHY_MDIO_PHY_ID1 = 2, + TSE_PHY_MDIO_PHY_ID2 = 3, + TSE_PHY_MDIO_ADV = 4, + TSE_PHY_MDIO_REMADV = 5, + + TSE_PHY_MDIO_AN_EXT = 6, + TSE_PHY_MDIO_1000BASE_T_CTRL = 9, + TSE_PHY_MDIO_1000BASE_T_STATUS = 10, + TSE_PHY_MDIO_EXT_STATUS = 15 +}; + +/* MDIO CONTROL bit number */ +enum { + TSE_PHY_MDIO_CONTROL_RESET = 15, + TSE_PHY_MDIO_CONTROL_LOOPBACK = 14, + TSE_PHY_MDIO_CONTROL_SPEED_LSB = 13, + TSE_PHY_MDIO_CONTROL_AN_ENA = 12, + TSE_PHY_MDIO_CONTROL_POWER_DOWN = 11, + TSE_PHY_MDIO_CONTROL_ISOLATE = 10, + TSE_PHY_MDIO_CONTROL_RESTART_AN = 9, + TSE_PHY_MDIO_CONTROL_DUPLEX = 8, + TSE_PHY_MDIO_CONTROL_SPEED_MSB = 6 +}; + +/* MDIO STATUS bit number */ +enum { + TSE_PHY_MDIO_STATUS_100BASE_T4 = 15, + TSE_PHY_MDIO_STATUS_100BASE_X_FULL = 14, + TSE_PHY_MDIO_STATUS_100BASE_X_HALF = 13, + TSE_PHY_MDIO_STATUS_10BASE_T_FULL = 12, + TSE_PHY_MDIO_STATUS_10BASE_T_HALF = 11, + TSE_PHY_MDIO_STATUS_100BASE_T2_FULL = 10, + TSE_PHY_MDIO_STATUS_100BASE_T2_HALF = 9, + TSE_PHY_MDIO_STATUS_EXT_STATUS = 8, + TSE_PHY_MDIO_STATUS_AN_COMPLETE = 5, + TSE_PHY_MDIO_STATUS_AN_ABILITY = 3, + TSE_PHY_MDIO_STATUS_LINK_STATUS = 2 +}; + +/* AN Advertisement bit number */ +/* and also */ +/* Link Partner Ability bit number */ +enum { + TSE_PHY_MDIO_ADV_100BASE_T4 = 9, + TSE_PHY_MDIO_ADV_100BASE_TX_FULL = 8, + TSE_PHY_MDIO_ADV_100BASE_TX_HALF = 7, + TSE_PHY_MDIO_ADV_10BASE_TX_FULL = 6, + TSE_PHY_MDIO_ADV_10BASE_TX_HALF = 5 +}; + +/* AN Expansion bit number */ +enum { + TSE_PHY_MDIO_LP_AN_ABLE = 0 +}; + +/* 1000BASE-T Control bit number */ +enum { + TSE_PHY_MDIO_1000BASE_T_CTRL_FULL_ADV = 9, + TSE_PHY_MDIO_1000BASE_T_CTRL_HALF_ADV = 8 +}; + +/* 1000BASE-T Status bit number */ +enum { + TSE_PHY_MDIO_1000BASE_T_STATUS_LP_FULL_ADV = 11, + TSE_PHY_MDIO_1000BASE_T_STATUS_LP_HALF_ADV = 10 +}; + +/* Extended Status bit number */ +enum { + TSE_PHY_MDIO_EXT_STATUS_1000BASE_X_FULL = 15, + TSE_PHY_MDIO_EXT_STATUS_1000BASE_X_HALF = 14, + TSE_PHY_MDIO_EXT_STATUS_1000BASE_T_FULL = 13, + TSE_PHY_MDIO_EXT_STATUS_1000BASE_T_HALF = 12 +}; + + + + + +/* + * macros to access MSGDMA prefetcher standard Descriptors used in the TSE driver + * - use the macros to assure cache coherancy + */ +#define IORD_ALTERA_TSE_MSGDMA_DESC_READ_ADDR(base) (IORD(base, 0x0) & 0xFFFFFFFF) +#define IOWR_ALTERA_TSE_MSGDMA_DESC_READ_ADDR(base, data) IOWR(base, 0x0, data) +#define IORD_ALTERA_TSE_MSGDMA_DESC_WRITE_ADDR(base) (IORD(base, 0x1) & 0xFFFFFFFF) +#define IOWR_ALTERA_TSE_MSGDMA_DESC_WRITE_ADDR(base, data) IOWR(base, 0x1, data) +#define IORD_ALTERA_TSE_MSGDMA_DESC_NEXT(base) (IORD(base, 0x3) & 0xFFFFFFFF) +#define IOWR_ALTERA_TSE_MSGDMA_DESC_NEXT(base, data) IOWR(base, 0x3, data) + +#define IORD_ALTERA_TSE_MSGDMA_DESC_BYTES_TO_TRANSFER(base) (IORD(base, 0x2) & 0xFFFFFFFF) +#define IOWR_ALTERA_TSE_MSGDMA_DESC_BYTES_TO_TRANSFER(base, data) IOWR(base, 0x2, data)) + +#define IORD_ALTERA_TSE_MSGDMA_DESC_ACTUAL_BYTES_TRANSFERRED(base) (IORD(base, 0x4) & 0xFFFFFFFF) +#define IOWR_ALTERA_TSE_MSGDMA_DESC_ACTUAL_BYTES_TRANSFERRED(base, data) IOWR(base, 0x4, data)) +#define IORD_ALTERA_TSE_MSGDMA_DESC_STATUS(base) (((IORD(base, 0x5)) >> 16) & 0xFFFF) +#define IOWR_ALTERA_TSE_MSGDMA_DESC_STATUS(base, data) IOWR(base, 0x5, (data & 0xffff)) +#define IORD_ALTERA_TSE_MSGDMA_DESC_CONTROL(base) (((IORD(base, 0x7) >> 24) & 0xFF) +#define IOWR_ALTERA_TSE_MSGDMA_DESC_CONTROL(base, data) IOWR(base, 0x7, data) + +/* TSE System Component Structure */ +typedef struct alt_tse_system_mac_struct { + alt_u32 tse_mac_base; /* Base address of TSE MAC */ + alt_u16 tse_tx_depth; /* TX Receive FIFO depth */ + alt_u16 tse_rx_depth; /* RX Receive FIFO depth */ + alt_u8 tse_use_mdio; /* is MDIO enabled */ + alt_u8 tse_en_maclite; /* is Small MAC */ + alt_u8 tse_maclite_gige; /* is Small MAC 1000 Mbps */ + alt_u8 tse_multichannel_mac; /* MAC group together for MDIO block sharing */ + alt_u8 tse_num_of_channel; /* Number of channel for Multi-channel MAC */ + alt_u8 tse_mdio_shared; /* is MDIO block shared */ + alt_u8 tse_number_of_mac_mdio_shared; /* Number of MAC sharing the MDIO block */ + alt_u8 tse_pcs_ena; /* is MAC+PCS combination */ + alt_u8 tse_pcs_sgmii; /* is SGMII mode of PCS enabled */ +} alt_tse_system_mac; + +typedef struct alt_tse_system_msgdma_struct { + char * tse_msgdma_tx; /* MSGDMA TX name */ + char * tse_msgdma_rx; /* MSGDMA RX name */ + alt_u16 tse_msgdma_rx_irq; /* MSGDMA RX IRQ */ +} alt_tse_system_msgdma; + +typedef struct alt_tse_system_desc_mem_struct { + alt_u8 ext_desc_mem; /* is dedicated memory used for descriptor */ + alt_u32 desc_mem_base; /* Base address of Descriptor Memory if ext_desc_mem = 1 */ +} alt_tse_system_desc_mem; + +typedef struct alt_tse_system_shared_fifo_struct { + alt_u8 use_shared_fifo; /* is Shared FIFO used in the system */ + + alt_u32 tse_shared_fifo_tx_ctrl_base; /* Base address of TX Shared FIFO Ctrl */ + alt_u32 tse_shared_fifo_tx_stat_base; /* Base address of TX Shared FIFO Fill Level */ + alt_u32 tse_shared_fifo_tx_depth; /* Depth of TX Shared FIFO */ + + alt_u32 tse_shared_fifo_rx_ctrl_base; /* Base address of RX Shared FIFO Ctrl */ + alt_u32 tse_shared_fifo_rx_stat_base; /* Base address of RX Shared FIFO Fill Level */ + alt_u32 tse_shared_fifo_rx_depth; /* Depth of RX Shared FIFO */ + +} alt_tse_system_shared_fifo; + +typedef struct alt_tse_system_phy_struct { + alt_32 tse_phy_mdio_address; /* PHY's MDIO address */ + alt_32 (*tse_phy_cfg)(np_tse_mac *pmac); /* Function pointer to execute additional initialization */ +} alt_tse_system_phy; + +/* System Parameters for TSE System */ +typedef struct alt_tse_system_info_struct { + alt_u32 tse_mac_base; /* Base address of TSE MAC */ + alt_u32 tse_tx_depth; /* TX Receive FIFO depth */ + alt_u32 tse_rx_depth; /* RX Receive FIFO depth */ + alt_u8 tse_use_mdio; /* is MDIO enabled */ + alt_u8 tse_en_maclite; /* is Small MAC */ + alt_u8 tse_maclite_gige; /* is Small MAC 1000 Mbps */ + alt_u8 tse_multichannel_mac; /* MAC group together for MDIO block sharing */ + alt_u8 tse_num_of_channel; /* Number of channel for Multi-channel MAC */ + alt_u8 tse_mdio_shared; /* is MDIO block shared */ + alt_u8 tse_number_of_mac_mdio_shared; /* Number of MAC sharing the MDIO block */ + alt_u8 tse_pcs_ena; /* is MAC+PCS combination */ + alt_u8 tse_pcs_sgmii; /* is SGMII mode of PCS enabled */ + + char * tse_msgdma_tx; /* MSGDMA TX name */ + char * tse_msgdma_rx; /* MSGDMA RX name */ + alt_u16 tse_msgdma_rx_irq; /* MSGDMA TX IRQ */ + + alt_u8 ext_desc_mem; /* is dedicated memory used for descriptor */ + alt_u32 desc_mem_base; /* Base address of Descriptor Memory if ext_desc_mem = 1 */ + + alt_u8 use_shared_fifo; /* is Shared FIFO used in the system */ + alt_u32 tse_shared_fifo_tx_ctrl_base; /* Base address of TX Shared FIFO Ctrl */ + alt_u32 tse_shared_fifo_tx_stat_base; /* Base address of TX Shared FIFO Fill Level */ + alt_u32 tse_shared_fifo_tx_depth; /* Depth of TX Shared FIFO */ + + alt_u32 tse_shared_fifo_rx_ctrl_base; /* Base address of RX Shared FIFO Ctrl */ + alt_u32 tse_shared_fifo_rx_stat_base; /* Base address of RX Shared FIFO Fill Level */ + alt_u32 tse_shared_fifo_rx_depth; /* Depth of RX Shared FIFO */ + + alt_32 tse_phy_mdio_address; /* PHY's MDIO address */ + alt_32 (*tse_phy_cfg)(np_tse_mac *pmac); /* Function pointer to execute additional initialization */ + +} alt_tse_system_info; + + + + +/* PHY structure for PHY detection */ +typedef struct alt_tse_phy_profile_struct{ + + /* PHY name */ + char name[80]; + + /* PHY OUI (Organizationally Unique Identififier) */ + alt_u32 oui; + + /* PHY model number */ + alt_u8 model_number; + + /* PHY revision number */ + alt_u8 revision_number; + + /* Location of PHY Specific Status Register */ + alt_u8 status_reg_location; + + /* Location of Speed Status bit in PHY Specific Status Register */ + alt_u8 speed_lsb_location; + + /* Location of Duplex Status bit in PHY Specific Status Register */ + alt_u8 duplex_bit_location; + + /* Location of Link Status bit in PHY Specific Status Register */ + alt_u8 link_bit_location; + + /* Function pointer to execute additional initialization */ + /* Profile specific */ + alt_32 (*phy_cfg)(np_tse_mac *pmac); + + /** Function pointer to read the link status from the PHY specific status register + * Use this function pointer if the PHY is using different format to store link information in PHY specific status register + * The above _location variable will not be used if this function pointer is not NULL + * Table below show the format of the return value required by TSE driver PHY detection + * ---------------------------------------------------------------------------------- + * | BIT | Value: Description | + * ---------------------------------------------------------------------------------- + * | 31-17 | Reserved | + * | 16 | 1: Error:Invalid speed read from PHY | + * | 15- 4 | Reserved | + * | 3 | 1: 10 Mbps link | + * | 2 | 1: 100 Mbps link | + * | 1 | 1: 1000 Mbps link | + * | 0 | 1: Full Duplex 0: Half Duplex | + * ---------------------------------------------------------------------------------- + */ + alt_u32 (*link_status_read)(np_tse_mac *pmac); + +} alt_tse_phy_profile; + + +/* TSE Multi-Channel PHY detection */ +typedef struct alt_tse_phy_link_cap_struct { + /* connected PHY capabilities */ + alt_u8 cap_1000_base_x_full; + alt_u8 cap_1000_base_x_half; + alt_u8 cap_1000_base_t_full; + alt_u8 cap_1000_base_t_half; + + alt_u8 cap_100_base_t4; + alt_u8 cap_100_base_x_full; + alt_u8 cap_100_base_x_half; + alt_u8 cap_100_base_t2_full; + alt_u8 cap_100_base_t2_half; + alt_u8 cap_10_base_t_full; + alt_u8 cap_10_base_t_half; + + /* link partner capabilities */ + alt_u8 lp_1000_base_t_full; + alt_u8 lp_1000_base_t_half; + + alt_u8 lp_100_base_t4; + alt_u8 lp_100_base_tx_full; + alt_u8 lp_100_base_tx_half; + alt_u8 lp_10_base_tx_full; + alt_u8 lp_10_base_tx_half; +} alt_tse_phy_link_cap; + + +struct alt_tse_phy_info_struct; +struct alt_tse_mac_info_struct; +struct alt_tse_mac_group_struct; + +struct alt_tse_phy_info_struct { + alt_u8 mdio_address; /* Actual PHY MDIO address detected */ + alt_tse_phy_link_cap link_capability; /* structure to store link capability of PHY and link partner */ + alt_tse_phy_profile *pphy_profile; /* Pointer to type of PHY profile */ + struct alt_tse_mac_info_struct *pmac_info; /* Pointer to MAC info structure which connected to this PHY */ + +}; + +struct alt_tse_mac_info_struct { + alt_u8 mac_type; /* ALTERA_TSE_FULL_MAC, ALTERA_TSE_MACLITE_10_100, or ALTERA_TSE_MACLITE_1000 */ + struct alt_tse_phy_info_struct *pphy_info; /* Pointer to PHY info structure which connected to this MAC */ + alt_tse_system_info *psys_info; /* Pointer to alt_tse_system_info structure in alt_tse_system_info.h */ + struct alt_tse_mac_group_struct *pmac_group; /* Pointer to the MAC group this MAC belongs to, all multi-channel MAC form a group */ + +}; + +struct alt_tse_mac_group_struct { + alt_u8 channel; /* Number of channel the MAC group has */ + struct alt_tse_mac_info_struct *pmac_info[TSE_MAX_CHANNEL]; /* Pointer to hold MACs in the same group */ +}; + +typedef struct alt_tse_phy_info_struct alt_tse_phy_info; +typedef struct alt_tse_mac_info_struct alt_tse_mac_info; +typedef struct alt_tse_mac_group_struct alt_tse_mac_group; + + + +/******************************* + * + * Public API for TSE Driver + * + *******************************/ + +/* @Function Description: Perform a software Reset. Reset operation will ocur with some latency. + * COMMAND_CONFIG register is restored after reset. + * @API Type: Public + * @param pmac Pointer to the TSE MAC Control Interface Base address + * @return SUCCESS if ok, else if error return ENP_RESOURCE, ENP_LOGIC +*/ +alt_32 tse_mac_SwReset( np_tse_mac *pmac); + + + + +/* @Function Description: Perform switching of the TSE MAC into MII (10/100) mode. + * COMMAND_CONFIG register is restored after reset. + * @API Type: Public + * @param pmac Pointer to the TSE MAC Control Interface Base address + * @return SUCCESS +*/ +alt_32 tse_mac_setMIImode(np_tse_mac *pmac); + + + + +/* @Function Description: Perform switching of the TSE MAC into GMII (Gigabit) mode. + * COMMAND_CONFIG register is restored after reset. + * @API Type: Public + * @param pmac Pointer to the TSE MAC Control Interface Base address + * @return SUCCESS +*/ +alt_32 tse_mac_setGMIImode(np_tse_mac *pmac); + + +/* @Function Description - Add additional PHYs which are not supported by default into PHY profile for PHY detection and auto negotiation + * + * @API TYPE - Public + * @param phy pointer to alt_tse_phy_profile structure describing PHY registers + * @return index of PHY added in PHY profile on success, else return ALTERA_TSE_MALLOC_FAILED if memory allocation failed + * PHY which are currently supported by default : Marvell 88E1111, Marvell Quad PHY 88E1145, National DP83865, and National DP83848C + */ +alt_32 alt_tse_phy_add_profile(alt_tse_phy_profile *phy); + + +/* @Function Description - Add TSE System to tse_mac_device[] array to customize TSE System + * + * @API TYPE - Public + * @param psys_mac pointer to alt_tse_system_mac structure describing MAC of the system + * @param psys_msgdma pointer to alt_tse_system_msgdma structure describing SGDMA of the system + * @param psys_mem pointer to alt_tse_system_desc_mem structure describing Descriptor Memory of the system + * @param psys_phy pointer to alt_tse_system_phy structure describing PHY of the system + * @return SUCCESS on success + * ALTERA_TSE_MALLOC_FAILED if memory allocation failed + * ALTERA_TSE_SYSTEM_DEF_ERROR if definition of system incorrect or pointer == NULL + */ +alt_32 alt_tse_system_add_sys( + alt_tse_system_mac *psys_mac, + alt_tse_system_msgdma *psys_msgdma, + alt_tse_system_desc_mem *psys_mem, + alt_tse_system_shared_fifo *psys_shared_fifo, + alt_tse_system_phy *psys_phy ); + + +/* @Function Description - Enable MDIO sharing for multiple single channel MAC + * + * @API TYPE - Public + * @param psys_mac_list pointer to array of alt_tse_system_mac structure sharing MDIO block + * @param number_of_mac number of MAC sharing MDIO block + * @return SUCCESS on success + * ALTERA_TSE_SYSTEM_DEF_ERROR if definition of system incorrect or pointer == NULL + * Multi-channel MAC not supported + */ +alt_32 alt_tse_sys_enable_mdio_sharing(alt_tse_system_mac **psys_mac_list, alt_u8 number_of_mac); + +/* @Function Description: Get the common speed supported by all PHYs connected to the MAC within the same group + * @API Type: Public + * @param pmac Pointer to the TSE MAC Control Interface Base address + * @return common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if no common speed found + */ +alt_32 alt_tse_mac_get_common_speed(np_tse_mac *pmac); + +/* @Function Description: Set the common speed to all PHYs connected to the MAC within the same group + * @API Type: Public + * @param pmac Pointer to the TSE MAC Control Interface Base address + * common_speed common speed supported by all PHYs + * @return common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if invalid common speed specified + */ +alt_32 alt_tse_mac_set_common_speed(np_tse_mac *pmac, alt_32 common_speed); + +/******************************** + * + * Internal API for TSE Driver + * + *******************************/ + +/* @Function Description: Get the index of alt_tse_system_info structure in tse_mac_device[] + * @API Type: Internal + * @param psys_info Pointer to the alt_tse_system_info structure + * @return Index of TSE system structure in tse_mac_device[] + */ +alt_32 alt_tse_get_system_index(alt_tse_system_info *psys_info); + + +/* @Function Description: Get the index of alt_tse_mac_group structure in pmac_groups[] + * @API Type: Internal + * @param pmac_group Pointer to the alt_tse_mac_group structure + * @return Index of alt_tse_mac_group structure in pmac_groups[] + */ +alt_32 alt_tse_get_mac_group_index(alt_tse_mac_group *pmac_group); + + +/* @Function Description: Get the index of alt_tse_mac_info structure in pmac_groups[]->pmac_info[] + * @API Type: Internal + * @param pmac_group Pointer to the alt_tse_mac_info structure + * @return Index of alt_tse_mac_info structure in pmac_groups[]->pmac_info[] + */ +alt_32 alt_tse_get_mac_info_index(alt_tse_mac_info *pmac_info); + +/* @Function Description: Get the pointer of alt_tse_mac_info structure in pmac_groups[]->pmac_info[] + * @API Type: Internal + * @param pmac Pointer to the TSE MAC Control Interface Base address + * @return Pointer to alt_tse_mac_info structure in pmac_groups[]->pmac_info[] + */ +alt_tse_mac_info *alt_tse_get_mac_info(np_tse_mac *pmac); + +/* @Function Description: Perform switching of the TSE MAC speed. + * COMMAND_CONFIG register is restored after reset. + * @API Type: Internal + * @param pmac Pointer to the TSE MAC Control Interface Base address + * @param speed 2 = 1000 Mbps, 1 = 100 Mbps, 0 = 10 Mbps + */ +alt_32 alt_tse_mac_set_speed(np_tse_mac *pmac, alt_u8 speed); + + +/* @Function Description: Perform switching of the TSE MAC duplex mode. + * COMMAND_CONFIG register is restored after reset. + * @API Type: Internal + * @param pmac Pointer to the TSE MAC Control Interface Base address + * @param duplex 1 = Full Duplex, 0 = Half Duplex + */ +alt_32 alt_tse_mac_set_duplex(np_tse_mac *pmac, alt_u8 duplex); + + +/** @Function Description - Determine link speed our PHY negotiated with our link partner. + * This is fully vendor specific depending on the PHY you are using. + * + * @API TYPE - Internal + * @param tse.mi.base MAC register map. + * @return + * ---------------------------------------------------------------------------------- + * | BIT | Value: Description | + * ---------------------------------------------------------------------------------- + * | 31-23 | Reserved | + * | 23 | 1: Argument *pmac not found from the list of MAC detected during init | + * | 22 | 1: No MDIO used by the MAC | + * | 21 | 1: No PHY detected | + * | 20 | 1: No common speed found for Multi-port MAC | + * | 19 | 1: PHY auto-negotiation not completed | + * | 18 | 1: No PHY profile match the detected PHY | + * | 17 | 1: PHY Profile not defined correctly | + * | 16 | 1: Invalid speed read from PHY | + * | 4-15 | Reserved | + * | 3 | 1: 10 Mbps link | + * | 2 | 1: 100 Mbps link | + * | 1 | 1: 1000 Mbps link | + * | 0 | 1: Full Duplex 0: Half Duplex | + * ---------------------------------------------------------------------------------- + * + * If the link speed cannot be determined, it is fall back to 100 Mbps (customizable by changing ALTERA_TSE_MAC_SPEED_DEFAULT) + * Full duplex (customizable by changing ALTERA_TSE_DUPLEX_MODE_DEFAULT) + */ +alt_32 getPHYSpeed(np_tse_mac *pmac); + +/* @Function Description: Read MDIO address from the MDIO address1 register of first MAC within MAC group + * @API Type: Internal + * @param pmac Pointer to the alt_tse_phy_info structure + * @return return SUCCESS + */ +alt_32 alt_tse_phy_rd_mdio_addr(alt_tse_phy_info *pphy); + +/* @Function Description: Write MDIO address to the MDIO address1 register of first MAC within MAC group + * @API Type: Internal + * @param pmac Pointer to the alt_tse_phy_info structure + * @param mdio_address MDIO address to be written + * @return return SUCCESS + */ +alt_32 alt_tse_phy_wr_mdio_addr(alt_tse_phy_info *pphy, alt_u8 mdio_address); + +/** @Function Description - Write value of data with bit_length number of bits to mdio register based on register location reg_num + * and start from bit location lsb_num. + * + * @API TYPE - Internal + * @param pphy pointer to alt_tse_phy_info structure + * @param reg_num location of mdio register to be written. + * @param lsb_num least significant bit location of mdio register to be written. + * @param bit_length number of bits to be written to the register. + * @param data data to be written to the register at specific bit location of register. + * @return SUCCESS + */ +alt_32 alt_tse_phy_wr_mdio_reg(alt_tse_phy_info *pphy, alt_u8 reg_num, alt_u8 lsb_num, alt_u8 bit_length, alt_u16 data); + + + +/** @Function Description - Read bit_length number of bits from mdio register based on register location reg_num + * and start from bit location lsb_num. + * + * @API TYPE - Internal + * @param pphy pointer to alt_tse_phy_info structure + * @param reg_num location of mdio register to be read. + * @param lsb_num least significant bit location of mdio register to be read. + * @param bit_length number of bits to be read from the register. + * @return data read from mdio register + */ +alt_u32 alt_tse_phy_rd_mdio_reg(alt_tse_phy_info *pphy, alt_u8 reg_num, alt_u8 lsb_num, alt_u8 bit_length); + + +/* @Function Description: Add supported PHY to profile + * @API Type: Internal + * @param pmac N/A + * @return Number of PHY in profile + * + * User might add their own PHY by calling alt_tse_phy_add_profile() + */ +alt_32 alt_tse_phy_add_profile_default(); + + + +/* @Function Description: Display PHYs available in profile + * @API Type: Internal + * @param pmac N/A + * @return Number of PHY in profile + */ +alt_32 alt_tse_phy_print_profile(); + + +/* @Function Description: Store information of all the MAC available in the system + * @API Type: Internal + * @param pmac N/A + * @return return SUCCESS + * return ALTERA_TSE_SYSTEM_DEF_ERROR if alt_tse_system_info structure definition error + */ +alt_32 alt_tse_mac_group_init(); + +/* @Function Description: Store information of all the PHYs connected to MAC to phy_list + * @API Type: Internal + * @param pmac_group Pointer to the TSE MAC grouping structure + * @return Number of PHY not in profile + */ +alt_32 alt_tse_mac_get_phy(alt_tse_mac_group *pmac_group); + + +/* @Function Description: Associate the PHYs connected to the structure in alt_tse_system_info.h + * @API Type: Internal + * @param pmac_group Pointer to the TSE MAC grouping structure + * @param pphy Pointer to the TSE PHY info structure which hold information of PHY + * @return return TSE_PHY_MAP_ERROR if mapping error + * return TSE_PHY_MAP_SUCCESS otherwise + */ +alt_32 alt_tse_mac_associate_phy(alt_tse_mac_group *pmac_group, alt_tse_phy_info *pphy); + +/* @Function Description: Configure operating mode of Altera PCS if available + * @API Type: Internal + * @param pmac_info pointer to MAC info variable + * @return return SUCCESS + */ +alt_32 alt_tse_phy_cfg_pcs(alt_tse_mac_info *pmac_info); + +/* @Function Description: Detect and initialize all the PHYs connected + * @API Type: Internal + * @param pmac N/A + * @return SUCCESS + */ +alt_32 alt_tse_phy_init(); + + + +/* @Function Description: Restart Auto-Negotiation for the PHY + * @API Type: Internal + * @param pphy Pointer to the alt_tse_phy_info structure + * timeout_threshold timeout value of Auto-Negotiation + * @return return TSE_PHY_AN_COMPLETE if success + * return TSE_PHY_AN_NOT_COMPLETE if auto-negotiation not completed + * return TSE_PHY_AN_NOT_CAPABLE if the PHY not capable for AN + */ +alt_32 alt_tse_phy_restart_an(alt_tse_phy_info *pphy, alt_u32 timeout_threshold); + + +/* @Function Description: Check link status of PHY and start Auto-Negotiation if it has not yet done + * @API Type: Internal + * @param pphy Pointer to the alt_tse_phy_info structure + * timeout_threshold timeout value of Auto-Negotiation + * @return return TSE_PHY_AN_COMPLETE if success + * return TSE_PHY_AN_NOT_COMPLETE if auto-negotiation not completed + */ +alt_32 alt_tse_phy_check_link(alt_tse_phy_info *pphy, alt_u32 timeout_threshold); + + +/* @Function Description: Get link capability of PHY and link partner + * @API Type: Internal + * @param pmac Pointer to the alt_tse_phy_info structure + * @return return TSE_PHY_AN_COMPLETE if success + * return TSE_PHY_AN_NOT_COMPLETE if auto-negotiation not completed + * return TSE_PHY_AN_NOT_CAPABLE if the PHY not capable for AN + */ +alt_32 alt_tse_phy_get_cap(alt_tse_phy_info *pphy); + + +/* @Function Description: Set the advertisement of PHY for 1000 Mbps + * @API Type: Internal + * @param pmac Pointer to the alt_tse_phy_info structure + * enable set Enable = 1 to advertise this speed if the PHY capable + * set Enable = 0 to disable advertise of this speed + * @return return SUCCESS + */ +alt_32 alt_tse_phy_set_adv_1000(alt_tse_phy_info *pphy, alt_u8 enable); + + +/* @Function Description: Set the advertisement of PHY for 100 Mbps + * @API Type: Internal + * @param pmac Pointer to the alt_tse_phy_info structure + * enable set Enable = 1 to advertise this speed if the PHY capable + * set Enable = 0 to disable advertise of this speed + * @return return SUCCESS + */ +alt_32 alt_tse_phy_set_adv_100(alt_tse_phy_info *pphy, alt_u8 enable); + + +/* @Function Description: Set the advertisement of PHY for 10 Mbps + * @API Type: Internal + * @param pmac Pointer to the alt_tse_phy_info structure + * enable set Enable = 1 to advertise this speed if the PHY capable + * set Enable = 0 to disable advertise of this speed + * @return return SUCCESS + */ +alt_32 alt_tse_phy_set_adv_10(alt_tse_phy_info *pphy, alt_u8 enable); + + + +/* @Function Description: Get the common speed supported by all PHYs connected to the MAC within the same group + * @API Type: Internal + * @param pmac_group Pointer to the TSE MAC Group structure which group all the MACs that should use the same speed + * @return common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if no common speed found + */ +alt_32 alt_tse_phy_get_common_speed(alt_tse_mac_group *pmac_group); + + + +/* @Function Description: Set the common speed to all PHYs connected to the MAC within the same group + * @API Type: Internal + * @param pmac_group Pointer to the TSE MAC Group structure which group all the MACs that should use the same speed + * common_speed common speed supported by all PHYs + * @return common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if invalid common speed specified + */ +alt_32 alt_tse_phy_set_common_speed(alt_tse_mac_group *pmac_group, alt_32 common_speed); + + + +/* @Function Description: Additional configuration for Marvell PHY + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address of MAC group + */ +alt_32 marvell_phy_cfg(np_tse_mac *pmac); + +/* @Function Description: Additional configuration for PEF7071 PHY + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address of MAC group + */ +alt_32 PEF7071_config(np_tse_mac *pmac); + +/* @Function Description: Change operating mode of Marvell PHY to GMII + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group + */ +alt_32 marvell_cfg_gmii(np_tse_mac *pmac); + +/* @Function Description: Change operating mode of Marvell PHY to SGMII + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group + */ +alt_32 marvell_cfg_sgmii(np_tse_mac *pmac); + +/* @Function Description: Change operating mode of Marvell PHY to RGMII + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group + */ +alt_32 marvell_cfg_rgmii(np_tse_mac *pmac); + +/* @Function Description: Read link status from PHY specific status register of DP83848C + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group + */ +alt_u32 DP83848C_link_status_read(np_tse_mac *pmac); + +/* @Function Description: Read link status from PHY specific status register of PEF7071 + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group + */ +alt_u32 PEF7071_link_status_read(np_tse_mac *pmac); + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALTERA_AVALON_TSE_H__ */ + diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_tse_system_info.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_tse_system_info.h new file mode 100644 index 0000000..a505a71 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_tse_system_info.h @@ -0,0 +1,352 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_TSE_SYSTEM_INFO_H__ +#define __ALTERA_AVALON_TSE_SYSTEM_INFO_H__ + +#include "altera_avalon_tse.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* Define whole TSE system (dedicated descriptor memory, no shared fifo) */ +#define TSE_SYSTEM_EXT_MEM_NO_SHARED_FIFO(tse_name, offset, msgdma_tx_name, msgdma_rx_name, phy_addres, phy_cfg_fp, desc_mem_name) { \ + tse_name##_BASE + offset, \ + tse_name##_TRANSMIT_FIFO_DEPTH, \ + tse_name##_RECEIVE_FIFO_DEPTH, \ + tse_name##_USE_MDIO, \ + tse_name##_ENABLE_MACLITE, \ + tse_name##_MACLITE_GIGE, \ + tse_name##_IS_MULTICHANNEL_MAC, \ + tse_name##_NUMBER_OF_CHANNEL, \ + tse_name##_MDIO_SHARED, \ + tse_name##_NUMBER_OF_MAC_MDIO_SHARED, \ + tse_name##_PCS, \ + tse_name##_PCS_SGMII, \ + msgdma_tx_name##_CSR_NAME, \ + msgdma_rx_name##_CSR_NAME, \ + msgdma_rx_name##_CSR_IRQ, \ + TSE_EXT_DESC_MEM, \ + desc_mem_name##_BASE, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + phy_addres, \ + phy_cfg_fp \ +}, + +/* Define whole TSE system (program memory as descriptor memory, no shared fifo) */ +#define TSE_SYSTEM_INT_MEM_NO_SHARED_FIFO(tse_name, offset, msgdma_tx_name, msgdma_rx_name, phy_addres, phy_cfg_fp) { \ + tse_name##_BASE + offset, \ + tse_name##_TRANSMIT_FIFO_DEPTH, \ + tse_name##_RECEIVE_FIFO_DEPTH, \ + tse_name##_USE_MDIO, \ + tse_name##_ENABLE_MACLITE, \ + tse_name##_MACLITE_GIGE, \ + tse_name##_IS_MULTICHANNEL_MAC, \ + tse_name##_NUMBER_OF_CHANNEL, \ + tse_name##_MDIO_SHARED, \ + tse_name##_NUMBER_OF_MAC_MDIO_SHARED, \ + tse_name##_PCS, \ + tse_name##_PCS_SGMII, \ + msgdma_tx_name##_CSR_NAME, \ + msgdma_rx_name##_CSR_NAME, \ + msgdma_rx_name##_CSR_IRQ, \ + TSE_INT_DESC_MEM, \ + TSE_INT_DESC_MEM, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + phy_addres, \ + phy_cfg_fp \ +}, + +/* Define whole TSE system (dedicated descriptor memory, use shared fifo) */ +#define TSE_SYSTEM_EXT_MEM_WITH_SHARED_FIFO(tse_name, offset, msgdma_tx_name, msgdma_rx_name, phy_addres, phy_cfg_fp, desc_mem_name, shared_fifo_tx_name, shared_fifo_rx_name) { \ + tse_name##_BASE + offset, \ + tse_name##_TRANSMIT_FIFO_DEPTH, \ + tse_name##_RECEIVE_FIFO_DEPTH, \ + tse_name##_USE_MDIO, \ + tse_name##_ENABLE_MACLITE, \ + tse_name##_MACLITE_GIGE, \ + tse_name##_IS_MULTICHANNEL_MAC, \ + tse_name##_NUMBER_OF_CHANNEL, \ + tse_name##_MDIO_SHARED, \ + tse_name##_NUMBER_OF_MAC_MDIO_SHARED, \ + tse_name##_PCS, \ + tse_name##_PCS_SGMII, \ + msgdma_tx_name##_CSR_NAME, \ + msgdma_rx_name##_CSR_NAME, \ + msgdma_rx_name##_CSR_IRQ, \ + TSE_EXT_DESC_MEM, \ + desc_mem_name##_BASE, \ + TSE_USE_SHARED_FIFO, \ + shared_fifo_tx_name##_CONTROL_BASE, \ + shared_fifo_tx_name##_FILL_LEVEL_BASE, \ + ALTERA_TSE_SHARED_FIFO_TX_DEPTH_DEFAULT, \ + shared_fifo_rx_name##_CONTROL_BASE, \ + shared_fifo_rx_name##_FILL_LEVEL_BASE, \ + ALTERA_TSE_SHARED_FIFO_RX_DEPTH_DEFAULT, \ + phy_addres, \ + phy_cfg_fp \ +}, + +/* Define whole TSE system (program memory as descriptor memory, use shared fifo) */ +#define TSE_SYSTEM_INT_MEM_WITH_SHARED_FIFO(tse_name, offset, msgdma_tx_name, msgdma_rx_name, phy_addres, phy_cfg_fp, shared_fifo_tx_name, shared_fifo_rx_name) { \ + tse_name##_BASE + offset, \ + tse_name##_TRANSMIT_FIFO_DEPTH, \ + tse_name##_RECEIVE_FIFO_DEPTH, \ + tse_name##_USE_MDIO, \ + tse_name##_ENABLE_MACLITE, \ + tse_name##_MACLITE_GIGE, \ + tse_name##_IS_MULTICHANNEL_MAC, \ + tse_name##_NUMBER_OF_CHANNEL, \ + tse_name##_MDIO_SHARED, \ + tse_name##_NUMBER_OF_MAC_MDIO_SHARED, \ + tse_name##_PCS, \ + tse_name##_PCS_SGMII, \ + msgdma_tx_name##_CSR_NAME, \ + msgdma_rx_name##_CSR_NAME, \ + msgdma_rx_name##_CSR_IRQ, \ + TSE_INT_DESC_MEM, \ + TSE_INT_DESC_MEM, \ + TSE_USE_SHARED_FIFO, \ + shared_fifo_tx_name##_CONTROL_BASE, \ + shared_fifo_tx_name##_FILL_LEVEL_BASE, \ + ALTERA_TSE_SHARED_FIFO_TX_DEPTH_DEFAULT, \ + shared_fifo_rx_name##_CONTROL_BASE, \ + shared_fifo_rx_name##_FILL_LEVEL_BASE, \ + ALTERA_TSE_SHARED_FIFO_RX_DEPTH_DEFAULT, \ + phy_addres, \ + phy_cfg_fp \ +}, + + + +/* Define whole TSE system (dedicated descriptor memory, no shared fifo, enable MDIO sharing on first MAC) */ +/* MDIO sharing not supported for Multi-channel MAC */ +#define TSE_SYSTEM_EXT_MEM_NO_SHARED_FIFO_ENABLE_MDIO_SHARING(tse_name, offset, msgdma_tx_name, msgdma_rx_name, phy_addres, phy_cfg_fp, desc_mem_name, number_of_mac_mdio_sharing) { \ + tse_name##_BASE + offset, \ + tse_name##_TRANSMIT_FIFO_DEPTH, \ + tse_name##_RECEIVE_FIFO_DEPTH, \ + tse_name##_USE_MDIO, \ + tse_name##_ENABLE_MACLITE, \ + tse_name##_MACLITE_GIGE, \ + tse_name##_IS_MULTICHANNEL_MAC, \ + tse_name##_NUMBER_OF_CHANNEL, \ + TSE_ENABLE_MDIO_SHARING, \ + number_of_mac_mdio_sharing, \ + tse_name##_PCS, \ + tse_name##_PCS_SGMII, \ + msgdma_tx_name##_CSR_NAME, \ + msgdma_rx_name##_CSR_NAME, \ + msgdma_rx_name##_CSR_IRQ, \ + TSE_EXT_DESC_MEM, \ + desc_mem_name##_BASE, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + phy_addres, \ + phy_cfg_fp \ +}, + +/* Define whole TSE system (program memory as descriptor memory, no shared fifo, enable MDIO sharing on first MAC) */ +/* MDIO sharing not supported for Multi-channel MAC */ +#define TSE_SYSTEM_INT_MEM_NO_SHARED_FIFO_ENABLE_MDIO_SHARING(tse_name, offset, msgdma_tx_name, msgdma_rx_name, phy_addres, phy_cfg_fp, number_of_mac_mdio_sharing) { \ + tse_name##_BASE + offset, \ + tse_name##_TRANSMIT_FIFO_DEPTH, \ + tse_name##_RECEIVE_FIFO_DEPTH, \ + tse_name##_USE_MDIO, \ + tse_name##_ENABLE_MACLITE, \ + tse_name##_MACLITE_GIGE, \ + tse_name##_IS_MULTICHANNEL_MAC, \ + tse_name##_NUMBER_OF_CHANNEL, \ + TSE_ENABLE_MDIO_SHARING, \ + number_of_mac_mdio_sharing, \ + tse_name##_PCS, \ + tse_name##_PCS_SGMII, \ + msgdma_tx_name##_CSR_NAME, \ + msgdma_rx_name##_CSR_NAME, \ + msgdma_rx_name##_CSR_IRQ, \ + TSE_INT_DESC_MEM, \ + TSE_INT_DESC_MEM, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + phy_addres, \ + phy_cfg_fp \ +}, + +/* Define whole TSE system (dedicated descriptor memory, use shared fifo, enable MDIO sharing on first MAC) */ +/* MDIO sharing not supported for Multi-channel MAC */ +#define TSE_SYSTEM_EXT_MEM_WITH_SHARED_FIFO_ENABLE_MDIO_SHARING(tse_name, offset, msgdma_tx_name, msgdma_rx_name, phy_addres, phy_cfg_fp, desc_mem_name, shared_fifo_tx_name, shared_fifo_rx_name, number_of_mac_mdio_sharing) { \ + tse_name##_BASE + offset, \ + tse_name##_TRANSMIT_FIFO_DEPTH, \ + tse_name##_RECEIVE_FIFO_DEPTH, \ + tse_name##_USE_MDIO, \ + tse_name##_ENABLE_MACLITE, \ + tse_name##_MACLITE_GIGE, \ + tse_name##_IS_MULTICHANNEL_MAC, \ + tse_name##_NUMBER_OF_CHANNEL, \ + TSE_ENABLE_MDIO_SHARING, \ + number_of_mac_mdio_sharing, \ + tse_name##_PCS, \ + tse_name##_PCS_SGMII, \ + msgdma_tx_name##_CSR_NAME, \ + msgdma_rx_name##_CSR_NAME, \ + msgdma_rx_name##_CSR_IRQ, \ + TSE_EXT_DESC_MEM, \ + desc_mem_name##_BASE, \ + TSE_USE_SHARED_FIFO, \ + shared_fifo_tx_name##_CONTROL_BASE, \ + shared_fifo_tx_name##_FILL_LEVEL_BASE, \ + ALTERA_TSE_SHARED_FIFO_TX_DEPTH_DEFAULT, \ + shared_fifo_rx_name##_CONTROL_BASE, \ + shared_fifo_rx_name##_FILL_LEVEL_BASE, \ + ALTERA_TSE_SHARED_FIFO_RX_DEPTH_DEFAULT, \ + phy_addres, \ + phy_cfg_fp \ +}, + +/* Define whole TSE system (program memory as descriptor memory, use shared fifo, enable MDIO sharing on first MAC) */ +/* MDIO sharing not supported for Multi-channel MAC */ +#define TSE_SYSTEM_INT_MEM_WITH_SHARED_FIFO_ENABLE_MDIO_SHARING(tse_name, offset, msgdma_tx_name, msgdma_rx_name, phy_addres, phy_cfg_fp, shared_fifo_tx_name, shared_fifo_rx_name, number_of_mac_mdio_sharing) { \ + tse_name##_BASE + offset, \ + tse_name##_TRANSMIT_FIFO_DEPTH, \ + tse_name##_RECEIVE_FIFO_DEPTH, \ + tse_name##_USE_MDIO, \ + tse_name##_ENABLE_MACLITE, \ + tse_name##_MACLITE_GIGE, \ + tse_name##_IS_MULTICHANNEL_MAC, \ + tse_name##_NUMBER_OF_CHANNEL, \ + TSE_ENABLE_MDIO_SHARING, \ + number_of_mac_mdio_sharing, \ + tse_name##_PCS, \ + tse_name##_PCS_SGMII, \ + msgdma_tx_name##_CSR_NAME, \ + msgdma_rx_name##_CSR_NAME, \ + msgdma_rx_name##_CSR_IRQ, \ + TSE_INT_DESC_MEM, \ + TSE_INT_DESC_MEM, \ + TSE_USE_SHARED_FIFO, \ + shared_fifo_tx_name##_CONTROL_BASE, \ + shared_fifo_tx_name##_FILL_LEVEL_BASE, \ + ALTERA_TSE_SHARED_FIFO_TX_DEPTH_DEFAULT, \ + shared_fifo_rx_name##_CONTROL_BASE, \ + shared_fifo_rx_name##_FILL_LEVEL_BASE, \ + ALTERA_TSE_SHARED_FIFO_RX_DEPTH_DEFAULT, \ + phy_addres, \ + phy_cfg_fp \ +}, + + + + +/* Macro to define single component used by alt_tse_system_add_sys() */ +/* Define MAC of TSE system */ +#define TSE_SYSTEM_MAC(tse_name) \ + tse_name##_BASE, \ + tse_name##_TRANSMIT_FIFO_DEPTH, \ + tse_name##_RECEIVE_FIFO_DEPTH, \ + tse_name##_USE_MDIO, \ + tse_name##_ENABLE_MACLITE, \ + tse_name##_MACLITE_GIGE, \ + tse_name##_IS_MULTICHANNEL_MAC, \ + tse_name##_NUMBER_OF_CHANNEL, \ + tse_name##_MDIO_SHARED, \ + tse_name##_NUMBER_OF_MAC_MDIO_SHARED, \ + tse_name##_PCS, \ + tse_name##_PCS_SGMII + +/* Define MSGDMA of TSE system */ +#define TSE_SYSTEM_MSGDMA(msgdma_tx_name, msgdma_rx_name) \ + msgdma_tx_name##_CSR_NAME, \ + msgdma_rx_name##_CSR_NAME, \ + msgdma_rx_name##_CSR_IRQ + +/* Define descriptor memory of TSE system (dedicated descriptor memory) */ +#define TSE_SYSTEM_DESC_MEM(desc_mem_name) \ + TSE_EXT_DESC_MEM, \ + desc_mem_name##_BASE + +/* Define descriptor memory of TSE system (program memory as descriptor memory) */ +#define TSE_SYSTEM_NO_DESC_MEM() \ + TSE_INT_DESC_MEM, \ + TSE_INT_DESC_MEM + +/* Define shared fifo of TSE system (use shared fifo) */ +#define TSE_SYSTEM_SHARED_FIFO(shared_fifo_tx_name, shared_fifo_rx_name) \ + TSE_USE_SHARED_FIFO, \ + shared_fifo_tx_name##_CONTROL_BASE, \ + shared_fifo_tx_name##_FILL_LEVEL_BASE, \ + ALTERA_TSE_SHARED_FIFO_TX_DEPTH_DEFAULT, \ + shared_fifo_rx_name##_CONTROL_BASE, \ + shared_fifo_rx_name##_FILL_LEVEL_BASE, \ + ALTERA_TSE_SHARED_FIFO_RX_DEPTH_DEFAULT + +/* Define shared fifo of TSE system (no shared fifo) */ +#define TSE_SYSTEM_NO_SHARED_FIFO() \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO, \ + TSE_NO_SHARED_FIFO + +/* Define PHY of TSE system */ +#define TSE_SYSTEM_PHY(phy_addres, phy_cfg_fp) \ + phy_addres, \ + phy_cfg_fp + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALTERA_AVALON_TSE_SYSTEM_INFO_H__ */ + diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_uart.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_uart.h new file mode 100644 index 0000000..e560202 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_uart.h @@ -0,0 +1,319 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALT_AVALON_UART_H__ +#define __ALT_AVALON_UART_H__ + +#include +#include + +#include "sys/alt_warning.h" + +#include "os/alt_sem.h" +#include "os/alt_flag.h" +#include "alt_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +#if defined(ALT_USE_SMALL_DRIVERS) || defined(ALTERA_AVALON_UART_SMALL) + +/* + *********************************************************************** + *********************** SMALL DRIVER ********************************** + *********************************************************************** + */ + +/* + * State structure definition. Each instance of the driver uses one + * of these structures to hold its associated state. + */ + +typedef struct altera_avalon_uart_state_s +{ + unsigned int base; +} altera_avalon_uart_state; + +/* + * The macro ALTERA_AVALON_UART_STATE_INSTANCE is used by the + * auto-generated file alt_sys_init.c to create an instance of this + * device driver state. + */ + +#define ALTERA_AVALON_UART_STATE_INSTANCE(name, state) \ + altera_avalon_uart_state state = \ + { \ + name##_BASE \ + } + +/* + * The macro ALTERA_AVALON_UART_STATE_INIT is used by the auto-generated file + * alt_sys_init.c to initialize an instance of the device driver state. + */ + +#define ALTERA_AVALON_UART_STATE_INIT(name, state) + +#else /* fast driver */ + +/* + ********************************************************************** + *********************** FAST DRIVER ********************************** + ********************************************************************** + */ + +/* + * ALT_AVALON_UART_READ_RDY and ALT_AVALON_UART_WRITE_RDY are the bitmasks + * that define uC/OS-II event flags that are releated to this device. + * + * ALT_AVALON_UART_READY_RDY indicates that there is read data in the buffer + * ready to be processed. ALT_UART_WRITE_RDY indicates that the transmitter is + * ready for more data. + */ + +#define ALT_UART_READ_RDY 0x1 +#define ALT_UART_WRITE_RDY 0x2 + +/* + * ALT_AVALON_UART_BUF_LEN is the length of the circular buffers used to hold + * pending transmit and receive data. This value must be a power of two. + */ + +#define ALT_AVALON_UART_BUF_LEN (64) + +/* + * ALT_AVALON_UART_BUF_MSK is used as an internal convenience for detecting + * the end of the arrays used to implement the transmit and receive buffers. + */ + +#define ALT_AVALON_UART_BUF_MSK (ALT_AVALON_UART_BUF_LEN - 1) + +/* + * This is somewhat of an ugly hack, but we need some mechanism for + * representing the non-standard 9 bit mode provided by this UART. In this + * case we abscond with the 5 bit mode setting. The value CS5 is defined in + * termios.h. + */ + +#define CS9 CS5 + +/* + * The value ALT_AVALON_UART_FB is a value set in the devices flag field to + * indicate that the device has a fixed baud rate; i.e. if this flag is set + * software can not control the baud rate of the device. + */ + +#define ALT_AVALON_UART_FB 0x1 + +/* + * The value ALT_AVALON_UART_FC is a value set in the device flag field to + * indicate the the device is using flow control, i.e. the driver must + * throttle on transmit if the nCTS pin is low. + */ + +#define ALT_AVALON_UART_FC 0x2 + +/* + * The altera_avalon_uart_state structure is used to hold device specific data. + * This includes the transmit and receive buffers. + * + * An instance of this structure is created in the auto-generated + * alt_sys_init.c file for each UART listed in the systems PTF file. This is + * done using the ALTERA_AVALON_UART_STATE_INSTANCE macro given below. + */ + +typedef struct altera_avalon_uart_state_s +{ + void* base; /* The base address of the device */ + alt_u32 ctrl; /* Shadow value of the control register */ + volatile alt_u32 rx_start; /* Start of the pending receive data */ + volatile alt_u32 rx_end; /* End of the pending receive data */ + volatile alt_u32 tx_start; /* Start of the pending transmit data */ + volatile alt_u32 tx_end; /* End of the pending transmit data */ +#ifdef ALTERA_AVALON_UART_USE_IOCTL + struct termios termios; /* Current device configuration */ + alt_u32 freq; /* Current baud rate */ +#endif + alt_u32 flags; /* Configuation flags */ + ALT_FLAG_GRP (events) /* Event flags used for + * foreground/background in mult-threaded + * mode */ + ALT_SEM (read_lock) /* Semaphore used to control access to the + * read buffer in multi-threaded mode */ + ALT_SEM (write_lock) /* Semaphore used to control access to the + * write buffer in multi-threaded mode */ + volatile alt_u8 rx_buf[ALT_AVALON_UART_BUF_LEN]; /* The receive buffer */ + volatile alt_u8 tx_buf[ALT_AVALON_UART_BUF_LEN]; /* The transmit buffer */ +} altera_avalon_uart_state; + +/* + * Conditionally define the data structures used to process ioctl requests. + * The following macros are defined for use in creating a device instance: + * + * ALTERA_AVALON_UART_TERMIOS - Initialise the termios structure used to + * describe the UART configuration. + * ALTERA_AVALON_UART_FREQ - Initialise the 'freq' field of the device + * structure, if the field exists. + * ALTERA_AVALON_UART_IOCTL - Initialise the 'ioctl' field of the device + * callback structure, if ioctls are enabled. + */ + +#ifdef ALTERA_AVALON_UART_USE_IOCTL + +#define ALTERA_AVALON_UART_TERMIOS(stop_bits, \ + parity, \ + odd_parity, \ + data_bits, \ + ctsrts, \ + baud) \ +{ \ + 0, \ + 0, \ + ((stop_bits == 2) ? CSTOPB: 0) | \ + ((parity) ? PARENB: 0) | \ + ((odd_parity) ? PAODD: 0) | \ + ((data_bits == 7) ? CS7: (data_bits == 9) ? CS9: CS8) | \ + ((ctsrts) ? CRTSCTS : 0), \ + 0, \ + 0, \ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ + baud, \ + baud \ +}, +#define ALTERA_AVALON_UART_FREQ(name) name##_FREQ, + +#else /* !ALTERA_AVALON_UART_USE_IOCTL */ + +#define ALTERA_AVALON_UART_TERMIOS(stop_bits, \ + parity, \ + odd_parity, \ + data_bits, \ + ctsrts, \ + baud) +#define ALTERA_AVALON_UART_FREQ(name) + +#endif /* ALTERA_AVALON_UART_USE_IOCTL */ + +/* + * The macro ALTERA_AVALON_UART_INSTANCE is used by the auto-generated file + * alt_sys_init.c to create an instance of this device driver state. + */ + +#define ALTERA_AVALON_UART_STATE_INSTANCE(name, state) \ + altera_avalon_uart_state state = \ + { \ + (void*) name##_BASE, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + ALTERA_AVALON_UART_TERMIOS(name##_STOP_BITS, \ + (name##_PARITY == 'N'), \ + (name##_PARITY == 'O'), \ + name##_DATA_BITS, \ + name##_USE_CTS_RTS, \ + name##_BAUD) \ + ALTERA_AVALON_UART_FREQ(name) \ + (name##_FIXED_BAUD ? ALT_AVALON_UART_FB : 0) | \ + (name##_USE_CTS_RTS ? ALT_AVALON_UART_FC : 0) \ + } + +/* + * altera_avalon_uart_init() is called by the auto-generated function + * alt_sys_init() for each UART in the system. This is done using the + * ALTERA_AVALON_UART_INIT macro given below. + * + * This function is responsible for performing all the run time initilisation + * for a device instance, i.e. registering the interrupt handler, and + * regestering the device with the system. + */ +extern void altera_avalon_uart_init(altera_avalon_uart_state* sp, + alt_u32 irq_controller_id, alt_u32 irq); + +/* + * The macro ALTERA_AVALON_UART_STATE_INIT is used by the auto-generated file + * alt_sys_init.c to initialize an instance of the device driver state. + * + * This macro performs a sanity check to ensure that the interrupt has been + * connected for this device. If not, then an apropriate error message is + * generated at build time. + */ + +#define ALTERA_AVALON_UART_STATE_INIT(name, state) \ + if (name##_IRQ == ALT_IRQ_NOT_CONNECTED) \ + { \ + ALT_LINK_ERROR ("Error: Interrupt not connected for " #name ". " \ + "You have selected the interrupt driven version of " \ + "the ALTERA Avalon UART driver, but the interrupt is " \ + "not connected for this device. You can select a " \ + "polled mode driver by checking the 'small driver' " \ + "option in the HAL configuration window, or by " \ + "using the -DALTERA_AVALON_UART_SMALL preprocessor " \ + "flag."); \ + } \ + else \ + { \ + altera_avalon_uart_init(&state, name##_IRQ_INTERRUPT_CONTROLLER_ID, \ + name##_IRQ); \ + } + +#endif /* small driver */ + +/* + * Include in case non-direct version of driver required. + */ +#include "altera_avalon_uart_fd.h" + +/* + * Map alt_sys_init macros to direct or non-direct versions. + */ +#ifdef ALT_USE_DIRECT_DRIVERS + +#define ALTERA_AVALON_UART_INSTANCE(name, state) \ + ALTERA_AVALON_UART_STATE_INSTANCE(name, state) +#define ALTERA_AVALON_UART_INIT(name, state) \ + ALTERA_AVALON_UART_STATE_INIT(name, state) + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +#define ALTERA_AVALON_UART_INSTANCE(name, dev) \ + ALTERA_AVALON_UART_DEV_INSTANCE(name, dev) +#define ALTERA_AVALON_UART_INIT(name, dev) \ + ALTERA_AVALON_UART_DEV_INIT(name, dev) + +#endif /* ALT_USE_DIRECT_DRIVERS */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_AVALON_UART_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_uart_fd.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_uart_fd.h new file mode 100644 index 0000000..c5ccd0c --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_uart_fd.h @@ -0,0 +1,143 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALT_AVALON_UART_FD_H__ +#define __ALT_AVALON_UART_FD_H__ + +#include "sys/alt_dev.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Externally referenced routines + */ +extern int altera_avalon_uart_read_fd (alt_fd* fd, char* ptr, int len); +extern int altera_avalon_uart_write_fd (alt_fd* fd, const char* ptr, + int len); + +/* + * Device structure definition. This is needed by alt_sys_init in order to + * reserve memory for the device instance. + */ +typedef struct altera_avalon_uart_dev_s +{ + alt_dev dev; + altera_avalon_uart_state state; +} altera_avalon_uart_dev; + +#if defined(ALT_USE_SMALL_DRIVERS) || defined(ALTERA_AVALON_UART_SMALL) + +/* + * Macros used by alt_sys_init when the ALT file descriptor facility is used. + */ + +#define ALTERA_AVALON_UART_DEV_INSTANCE(name, d) \ + static altera_avalon_uart_dev d = \ + { \ + { \ + ALT_LLIST_ENTRY, \ + name##_NAME, \ + NULL, /* open */ \ + NULL, /* close */ \ + altera_avalon_uart_read_fd, \ + altera_avalon_uart_write_fd, \ + NULL, /* lseek */ \ + NULL, /* fstat */ \ + NULL, /* ioctl */ \ + }, \ + { \ + name##_BASE, \ + } \ + } + +#define ALTERA_AVALON_UART_DEV_INIT(name, d) alt_dev_reg (&d.dev) + +#else /* use fast version of the driver */ + +extern int altera_avalon_uart_ioctl_fd (alt_fd* fd, int req, void* arg); +extern int altera_avalon_uart_close_fd(alt_fd* fd); + +#ifdef ALTERA_AVALON_UART_USE_IOCTL +#define ALTERA_AVALON_UART_IOCTL_FD altera_avalon_uart_ioctl_fd +#else +#define ALTERA_AVALON_UART_IOCTL_FD NULL +#endif + +#define ALTERA_AVALON_UART_DEV_INSTANCE(name, d) \ + static altera_avalon_uart_dev d = \ + { \ + { \ + ALT_LLIST_ENTRY, \ + name##_NAME, \ + NULL, /* open */ \ + altera_avalon_uart_close_fd, \ + altera_avalon_uart_read_fd, \ + altera_avalon_uart_write_fd, \ + NULL, /* lseek */ \ + NULL, /* fstat */ \ + ALTERA_AVALON_UART_IOCTL_FD, \ + }, \ + { \ + (void*) name##_BASE, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + ALTERA_AVALON_UART_TERMIOS(name##_STOP_BITS, \ + (name##_PARITY == 'N'), \ + (name##_PARITY == 'O'), \ + name##_DATA_BITS, \ + name##_USE_CTS_RTS, \ + name##_BAUD) \ + ALTERA_AVALON_UART_FREQ(name) \ + (name##_FIXED_BAUD ? ALT_AVALON_UART_FB : 0) | \ + (name##_USE_CTS_RTS ? ALT_AVALON_UART_FC : 0) \ + } \ + } + +#define ALTERA_AVALON_UART_DEV_INIT(name, d) \ + { \ + ALTERA_AVALON_UART_STATE_INIT(name, d.state); \ + \ + /* make the device available to the system */ \ + alt_dev_reg(&d.dev); \ + } + +#endif /* fast driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_AVALON_UART_FD_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_uart_regs.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_uart_regs.h new file mode 100644 index 0000000..3c4c31e --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_uart_regs.h @@ -0,0 +1,137 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_UART_REGS_H__ +#define __ALTERA_AVALON_UART_REGS_H__ + +#include + +#define ALTERA_AVALON_UART_RXDATA_REG 0 +#define IOADDR_ALTERA_AVALON_UART_RXDATA(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_UART_RXDATA_REG) +#define IORD_ALTERA_AVALON_UART_RXDATA(base) \ + IORD(base, ALTERA_AVALON_UART_RXDATA_REG) +#define IOWR_ALTERA_AVALON_UART_RXDATA(base, data) \ + IOWR(base, ALTERA_AVALON_UART_RXDATA_REG, data) + +#define ALTERA_AVALON_UART_TXDATA_REG 1 +#define IOADDR_ALTERA_AVALON_UART_TXDATA(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_UART_TXDATA_REG) +#define IORD_ALTERA_AVALON_UART_TXDATA(base) \ + IORD(base, ALTERA_AVALON_UART_TXDATA_REG) +#define IOWR_ALTERA_AVALON_UART_TXDATA(base, data) \ + IOWR(base, ALTERA_AVALON_UART_TXDATA_REG, data) + +#define ALTERA_AVALON_UART_STATUS_REG 2 +#define IOADDR_ALTERA_AVALON_UART_STATUS(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_UART_STATUS_REG) +#define IORD_ALTERA_AVALON_UART_STATUS(base) \ + IORD(base, ALTERA_AVALON_UART_STATUS_REG) +#define IOWR_ALTERA_AVALON_UART_STATUS(base, data) \ + IOWR(base, ALTERA_AVALON_UART_STATUS_REG, data) + +#define ALTERA_AVALON_UART_STATUS_PE_MSK (0x1) +#define ALTERA_AVALON_UART_STATUS_PE_OFST (0) +#define ALTERA_AVALON_UART_STATUS_FE_MSK (0x2) +#define ALTERA_AVALON_UART_STATUS_FE_OFST (1) +#define ALTERA_AVALON_UART_STATUS_BRK_MSK (0x4) +#define ALTERA_AVALON_UART_STATUS_BRK_OFST (2) +#define ALTERA_AVALON_UART_STATUS_ROE_MSK (0x8) +#define ALTERA_AVALON_UART_STATUS_ROE_OFST (3) +#define ALTERA_AVALON_UART_STATUS_TOE_MSK (0x10) +#define ALTERA_AVALON_UART_STATUS_TOE_OFST (4) +#define ALTERA_AVALON_UART_STATUS_TMT_MSK (0x20) +#define ALTERA_AVALON_UART_STATUS_TMT_OFST (5) +#define ALTERA_AVALON_UART_STATUS_TRDY_MSK (0x40) +#define ALTERA_AVALON_UART_STATUS_TRDY_OFST (6) +#define ALTERA_AVALON_UART_STATUS_RRDY_MSK (0x80) +#define ALTERA_AVALON_UART_STATUS_RRDY_OFST (7) +#define ALTERA_AVALON_UART_STATUS_E_MSK (0x100) +#define ALTERA_AVALON_UART_STATUS_E_OFST (8) +#define ALTERA_AVALON_UART_STATUS_DCTS_MSK (0x400) +#define ALTERA_AVALON_UART_STATUS_DCTS_OFST (10) +#define ALTERA_AVALON_UART_STATUS_CTS_MSK (0x800) +#define ALTERA_AVALON_UART_STATUS_CTS_OFST (11) +#define ALTERA_AVALON_UART_STATUS_EOP_MSK (0x1000) +#define ALTERA_AVALON_UART_STATUS_EOP_OFST (12) + +#define ALTERA_AVALON_UART_CONTROL_REG 3 +#define IOADDR_ALTERA_AVALON_UART_CONTROL(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_UART_CONTROL_REG) +#define IORD_ALTERA_AVALON_UART_CONTROL(base) \ + IORD(base, ALTERA_AVALON_UART_CONTROL_REG) +#define IOWR_ALTERA_AVALON_UART_CONTROL(base, data) \ + IOWR(base, ALTERA_AVALON_UART_CONTROL_REG, data) + +#define ALTERA_AVALON_UART_CONTROL_PE_MSK (0x1) +#define ALTERA_AVALON_UART_CONTROL_PE_OFST (0) +#define ALTERA_AVALON_UART_CONTROL_FE_MSK (0x2) +#define ALTERA_AVALON_UART_CONTROL_FE_OFST (1) +#define ALTERA_AVALON_UART_CONTROL_BRK_MSK (0x4) +#define ALTERA_AVALON_UART_CONTROL_BRK_OFST (2) +#define ALTERA_AVALON_UART_CONTROL_ROE_MSK (0x8) +#define ALTERA_AVALON_UART_CONTROL_ROE_OFST (3) +#define ALTERA_AVALON_UART_CONTROL_TOE_MSK (0x10) +#define ALTERA_AVALON_UART_CONTROL_TOE_OFST (4) +#define ALTERA_AVALON_UART_CONTROL_TMT_MSK (0x20) +#define ALTERA_AVALON_UART_CONTROL_TMT_OFST (5) +#define ALTERA_AVALON_UART_CONTROL_TRDY_MSK (0x40) +#define ALTERA_AVALON_UART_CONTROL_TRDY_OFST (6) +#define ALTERA_AVALON_UART_CONTROL_RRDY_MSK (0x80) +#define ALTERA_AVALON_UART_CONTROL_RRDY_OFST (7) +#define ALTERA_AVALON_UART_CONTROL_E_MSK (0x100) +#define ALTERA_AVALON_UART_CONTROL_E_OFST (8) +#define ALTERA_AVALON_UART_CONTROL_DCTS_MSK (0x400) +#define ALTERA_AVALON_UART_CONTROL_DCTS_OFST (10) +#define ALTERA_AVALON_UART_CONTROL_RTS_MSK (0x800) +#define ALTERA_AVALON_UART_CONTROL_RTS_OFST (11) +#define ALTERA_AVALON_UART_CONTROL_EOP_MSK (0x1000) +#define ALTERA_AVALON_UART_CONTROL_EOP_OFST (12) + +#define ALTERA_AVALON_UART_DIVISOR_REG 4 +#define IOADDR_ALTERA_AVALON_UART_DIVISOR(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_UART_DIVISOR_REG) +#define IORD_ALTERA_AVALON_UART_DIVISOR(base) \ + IORD(base, ALTERA_AVALON_UART_DIVISOR_REG) +#define IOWR_ALTERA_AVALON_UART_DIVISOR(base, data) \ + IOWR(base, ALTERA_AVALON_UART_DIVISOR_REG, data) + +#define ALTERA_AVALON_UART_EOP_REG 5 +#define IOADDR_ALTERA_AVALON_UART_EOP(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_UART_EOP_REG) +#define IORD_ALTERA_AVALON_UART_EOP(base) \ + IORD(base, ALTERA_AVALON_UART_EOP_REG) +#define IOWR_ALTERA_AVALON_UART_EOP(base, data) \ + IOWR(base, ALTERA_AVALON_UART_EOP_REG, data) + +#define ALTERA_AVALON_UART_EOP_MSK (0xFF) +#define ALTERA_AVALON_UART_EOP_OFST (0) + +#endif /* __ALTERA_AVALON_UART_REGS_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_eth_tse.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_eth_tse.h new file mode 100644 index 0000000..d796843 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_eth_tse.h @@ -0,0 +1,45 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_ETH_TSE_H__ +#define __ALTERA_ETH_TSE_H__ + +#if defined(ALT_INICHE) + +#include "iniche/altera_eth_tse_iniche.h" + +#else + +#define ALTERA_ETH_TSE_INSTANCE(name, dev) extern int alt_no_storage +#define ALTERA_ETH_TSE_INIT(name, dev) while(0) + +#endif + +#endif /* __ALTERA_ETH_TSE_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_eth_tse_regs.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_eth_tse_regs.h new file mode 100644 index 0000000..7a2da9d --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_eth_tse_regs.h @@ -0,0 +1,735 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_ETH_TSE_REGS_H__ +#define __ALTERA_ETH_TSE_REGS_H__ + + +#include "alt_types.h" +#include "io.h" + +/* MAC Registers */ + +/* Revision register (read-only) */ +#define IOADDR_ALTERA_TSEMAC_REV(base) __IO_CALC_ADDRESS_NATIVE(base,0x0) +#define IORD_ALTERA_TSEMAC_REV(base) IORD_32DIRECT(base, 0) + +/* Scratch register */ +#define IOADDR_ALTERA_TSEMAC_SCRATCH(base) __IO_CALC_ADDRESS_NATIVE(base,0x4) +#define IORD_ALTERA_TSEMAC_SCRATCH(base) IORD_32DIRECT(base, 0x4) +#define IOWR_ALTERA_TSEMAC_SCRATCH(base,data) IOWR_32DIRECT(base, 0x4, data) + +/* Command register */ +#define IOADDR_ALTERA_TSEMAC_CMD_CONFIG(base) __IO_CALC_ADDRESS_NATIVE(base,0x8) +#define IORD_ALTERA_TSEMAC_CMD_CONFIG(base) IORD_32DIRECT(base, 0x8) +#define IOWR_ALTERA_TSEMAC_CMD_CONFIG(base,data) IOWR_32DIRECT(base, 0x8, data) + +/* Command register bit definitions */ +#define ALTERA_TSEMAC_CMD_TX_ENA_OFST (0) +#define ALTERA_TSEMAC_CMD_TX_ENA_MSK (0x1) +#define ALTERA_TSEMAC_CMD_RX_ENA_OFST (1) +#define ALTERA_TSEMAC_CMD_RX_ENA_MSK (0x2) +#define ALTERA_TSEMAC_CMD_XON_GEN_OFST (2) +#define ALTERA_TSEMAC_CMD_XON_GEN_MSK (0x4) +#define ALTERA_TSEMAC_CMD_ETH_SPEED_OFST (3) +#define ALTERA_TSEMAC_CMD_ETH_SPEED_MSK (0x8) +#define ALTERA_TSEMAC_CMD_PROMIS_EN_OFST (4) +#define ALTERA_TSEMAC_CMD_PROMIS_EN_MSK (0x10) +#define ALTERA_TSEMAC_CMD_PAD_EN_OFST (5) +#define ALTERA_TSEMAC_CMD_PAD_EN_MSK (0x20) +#define ALTERA_TSEMAC_CMD_CRC_FWD_OFST (6) +#define ALTERA_TSEMAC_CMD_CRC_FWD_MSK (0x40) +#define ALTERA_TSEMAC_CMD_PAUSE_FWD_OFST (7) +#define ALTERA_TSEMAC_CMD_PAUSE_FWD_MSK (0x80) +#define ALTERA_TSEMAC_CMD_PAUSE_IGNORE_OFST (8) +#define ALTERA_TSEMAC_CMD_PAUSE_IGNORE_MSK (0x100) +#define ALTERA_TSEMAC_CMD_TX_ADDR_INS_OFST (9) +#define ALTERA_TSEMAC_CMD_TX_ADDR_INS_MSK (0x200) +#define ALTERA_TSEMAC_CMD_HD_ENA_OFST (10) +#define ALTERA_TSEMAC_CMD_HD_ENA_MSK (0x400) +#define ALTERA_TSEMAC_CMD_EXCESS_COL_OFST (11) +#define ALTERA_TSEMAC_CMD_EXCESS_COL_MSK (0x800) +#define ALTERA_TSEMAC_CMD_LATE_COL_OFST (12) +#define ALTERA_TSEMAC_CMD_LATE_COL_MSK (0x1000) +#define ALTERA_TSEMAC_CMD_SW_RESET_OFST (13) +#define ALTERA_TSEMAC_CMD_SW_RESET_MSK (0x2000) +#define ALTERA_TSEMAC_CMD_MHASH_SEL_OFST (14) +#define ALTERA_TSEMAC_CMD_MHASH_SEL_MSK (0x4000) +#define ALTERA_TSEMAC_CMD_LOOPBACK_OFST (15) +#define ALTERA_TSEMAC_CMD_LOOPBACK_MSK (0x8000) +/* Bits (18:16) = address select */ +#define ALTERA_TSEMAC_CMD_TX_ADDR_SEL_OFST (16) +#define ALTERA_TSEMAC_CMD_TX_ADDR_SEL_MSK (0x70000) +#define ALTERA_TSEMAC_CMD_MAGIC_ENA_OFST (19) +#define ALTERA_TSEMAC_CMD_MAGIC_ENA_MSK (0x80000) +#define ALTERA_TSEMAC_CMD_SLEEP_OFST (20) +#define ALTERA_TSEMAC_CMD_SLEEP_MSK (0x100000) +#define ALTERA_TSEMAC_CMD_WAKEUP_OFST (21) +#define ALTERA_TSEMAC_CMD_WAKEUP_MSK (0x200000) +#define ALTERA_TSEMAC_CMD_XOFF_GEN_OFST (22) +#define ALTERA_TSEMAC_CMD_XOFF_GEN_MSK (0x400000) +#define ALTERA_TSEMAC_CMD_CNTL_FRM_ENA_OFST (23) +#define ALTERA_TSEMAC_CMD_CNTL_FRM_ENA_MSK (0x800000) +#define ALTERA_TSEMAC_CMD_NO_LENGTH_CHECK_OFST (24) +#define ALTERA_TSEMAC_CMD_NO_LENGTH_CHECK_MSK (0x1000000) +#define ALTERA_TSEMAC_CMD_ENA_10_OFST (25) +#define ALTERA_TSEMAC_CMD_ENA_10_MSK (0x2000000) +#define ALTERA_TSEMAC_CMD_RX_ERR_DISC_OFST (26) +#define ALTERA_TSEMAC_CMD_RX_ERR_DISC_MSK (0x4000000) +/* Bits (30..27) reserved */ +#define ALTERA_TSEMAC_CMD_CNT_RESET_OFST (31) +#define ALTERA_TSEMAC_CMD_CNT_RESET_MSK (0x80000000) + +/* Low word (bits 31:0) of MAC address */ +#define IOADDR_ALTERA_TSEMAC_MAC_0(base) __IO_CALC_ADDRESS_NATIVE(base,0xC) +#define IORD_ALTERA_TSEMAC_MAC_0(base) IORD_32DIRECT(base, 0xC) +#define IOWR_ALTERA_TSEMAC_MAC_0(base,data) IOWR_32DIRECT(base, 0xC, data) + +/* High half-word (bits 47:32) of MAC address. Upper 16 bits reserved */ +#define IOADDR_ALTERA_TSEMAC_MAC_1(base) __IO_CALC_ADDRESS_NATIVE(base,0x10) +#define IORD_ALTERA_TSEMAC_MAC_1(base) IORD_32DIRECT(base, 0x10) +#define IOWR_ALTERA_TSEMAC_MAC_1(base,data) IOWR_32DIRECT(base, 0x10, data) + +/* Maximum frame length (bits 13:0), (bits 31:14 are reserved) */ +#define IOADDR_ALTERA_TSEMAC_FRM_LENGTH(base) __IO_CALC_ADDRESS_NATIVE(base,0x14) +#define IORD_ALTERA_TSEMAC_FRM_LENGTH(base) IORD_32DIRECT(base, 0x14) +#define IOWR_ALTERA_TSEMAC_FRM_LENGTH(base,data) IOWR_32DIRECT(base, 0x14, data) + +/* Receive pause quanta. Bits 31:16 reserved */ +#define IOADDR_ALTERA_TSEMAC_PAUSE_QUANT(base) __IO_CALC_ADDRESS_NATIVE(base,0x18) +#define IORD_ALTERA_TSEMAC_PAUSE_QUANT(base) IORD_32DIRECT(base, 0x18) +#define IOWR_ALTERA_TSEMAC_PAUSE_QUANT(base,data) IOWR_32DIRECT(base, 0x18, data) + +/* Sets RX FIFO section empty threshold */ +#define IOADDR_ALTERA_TSEMAC_RX_SECTION_EMPTY(base) __IO_CALC_ADDRESS_NATIVE(base,0x1C) +#define IORD_ALTERA_TSEMAC_RX_SECTION_EMPTY(base) IORD_32DIRECT(base, 0x1C) +#define IOWR_ALTERA_TSEMAC_RX_SECTION_EMPTY(base,data) IOWR_32DIRECT(base, 0x1C, data) + +/* Set RX FIFO section full threshold */ +#define IOADDR_ALTERA_TSEMAC_RX_SECTION_FULL(base) __IO_CALC_ADDRESS_NATIVE(base,0x20) +#define IORD_ALTERA_TSEMAC_RX_SECTION_FULL(base) IORD_32DIRECT(base, 0x20) +#define IOWR_ALTERA_TSEMAC_RX_SECTION_FULL(base,data) IOWR_32DIRECT(base, 0x20, data) + +/* Set TX FIFO section empty threshold */ +#define IOADDR_ALTERA_TSEMAC_TX_SECTION_EMPTY(base) __IO_CALC_ADDRESS_NATIVE(base,0x24) +#define IORD_ALTERA_TSEMAC_TX_SECTION_EMPTY(base) IORD_32DIRECT(base, 0x24) +#define IOWR_ALTERA_TSEMAC_TX_SECTION_EMPTY(base,data) IOWR_32DIRECT(base, 0x24, data) + +/* Set TX FIFO section full threshold */ +#define IOADDR_ALTERA_TSEMAC_TX_SECTION_FULL(base) __IO_CALC_ADDRESS_NATIVE(base,0x28) +#define IORD_ALTERA_TSEMAC_TX_SECTION_FULL(base) IORD_32DIRECT(base, 0x28) +#define IOWR_ALTERA_TSEMAC_TX_SECTION_FULL(base,data) IOWR_32DIRECT(base, 0x28, data) + +/* Set RX FIFO almost empty threshold */ +#define IOADDR_ALTERA_TSEMAC_RX_ALMOST_EMPTY(base) __IO_CALC_ADDRESS_NATIVE(base,0x2c) +#define IORD_ALTERA_TSEMAC_RX_ALMOST_EMPTY(base) IORD_32DIRECT(base, 0x2c) +#define IOWR_ALTERA_TSEMAC_RX_ALMOST_EMPTY(base,data) IOWR_32DIRECT(base, 0x2c, data) + +/* Set RX FIFO almost full threshold */ +#define IOADDR_ALTERA_TSEMAC_RX_ALMOST_FULL(base) __IO_CALC_ADDRESS_NATIVE(base,0x30) +#define IORD_ALTERA_TSEMAC_RX_ALMOST_FULL(base) IORD_32DIRECT(base, 0x30) +#define IOWR_ALTERA_TSEMAC_RX_ALMOST_FULL(base,data) IOWR_32DIRECT(base, 0x30, data) + +/* Set TX FIFO almost empty threshold */ +#define IOADDR_ALTERA_TSEMAC_TX_ALMOST_EMPTY(base) __IO_CALC_ADDRESS_NATIVE(base,0x34) +#define IORD_ALTERA_TSEMAC_TX_ALMOST_EMPTY(base) IORD_32DIRECT(base, 0x34) +#define IOWR_ALTERA_TSEMAC_TX_ALMOST_EMPTY(base,data) IOWR_32DIRECT(base, 0x34, data) + +/* Set TX FIFO almost full threshold */ +#define IOADDR_ALTERA_TSEMAC_TX_ALMOST_FULL(base) __IO_CALC_ADDRESS_NATIVE(base,0x38) +#define IORD_ALTERA_TSEMAC_TX_ALMOST_FULL(base) IORD_32DIRECT(base, 0x38) +#define IOWR_ALTERA_TSEMAC_TX_ALMOST_FULL(base,data) IOWR_32DIRECT(base, 0x38, data) + +/* MDIO Address of PHY 0. Bits 31:5 reserved */ +#define IOADDR_ALTERA_TSEMAC_MDIO_ADDR0(base) __IO_CALC_ADDRESS_NATIVE(base,0x3c) +#define IORD_ALTERA_TSEMAC_MDIO_ADDR0(base) IORD_32DIRECT(base, 0x3c) +#define IOWR_ALTERA_TSEMAC_MDIO_ADDR0(base,data) IOWR_32DIRECT(base, 0x3c, data) + +/* MDIO Address of PHY 1. Bits 31:5 reserved */ +#define IOADDR_ALTERA_TSEMAC_MDIO_ADDR1(base) __IO_CALC_ADDRESS_NATIVE(base,0x40) +#define IORD_ALTERA_TSEMAC_MDIO_ADDR1(base) IORD_32DIRECT(base, 0x40) +#define IOWR_ALTERA_TSEMAC_MDIO_ADDR1(base,data) IOWR_32DIRECT(base, 0x40, data) + +/* -- Register offsets 0x44 to 0x54 reserved -- */ + +/* Register read access status */ +#define IOADDR_ALTERA_TSEMAC_REG_STAT(base) __IO_CALC_ADDRESS_NATIVE(base,0x58) +#define IORD_ALTERA_TSEMAC_REG_STAT(base) IORD_32DIRECT(base, 0x58) + + +/* Inter-packet gap. Bits 31:5 reserved/ */ +#define IOADDR_ALTERA_TSEMAC_TX_IPG_LENGTH(base) __IO_CALC_ADDRESS_NATIVE(base,0x5c) +#define IORD_ALTERA_TSEMAC_TX_IPG_LENGTH(base) IORD_32DIRECT(base, 0x5c) +#define IOWR_ALTERA_TSEMAC_TX_IPG_LENGTH(base,data) IOWR_32DIRECT(base, 0x5c, data) + + +/* IEEE802.3, RMON, and MIB-II SNMP Statistic event counters */ +#define IOADDR_ALTERA_TSEMAC_A_MACID_1(base) __IO_CALC_ADDRESS_NATIVE(base,0x60) +#define IORD_ALTERA_TSEMAC_A_MACID_1(base) IORD_32DIRECT(base, 0x60) + + +#define IOADDR_ALTERA_TSEMAC_A_MACID_2(base) __IO_CALC_ADDRESS_NATIVE(base,0x64) +#define IORD_ALTERA_TSEMAC_A_MACID_2(base) IORD_32DIRECT(base, 0x64) + + +#define IOADDR_ALTERA_TSEMAC_A_FRAMES_TX_OK(base) __IO_CALC_ADDRESS_NATIVE(base,0x68) +#define IORD_ALTERA_TSEMAC_A_FRAMES_TX_OK(base) IORD_32DIRECT(base, 0x68) + + +#define IOADDR_ALTERA_TSEMAC_A_FRAMES_RX_OK(base) __IO_CALC_ADDRESS_NATIVE(base,0x6c) +#define IORD_ALTERA_TSEMAC_A_FRAMES_RX_OK(base) IORD_32DIRECT(base, 0x6c) + + +#define IOADDR_ALTERA_TSEMAC_A_FRAME_CHECK_SEQ_ERRS(base) __IO_CALC_ADDRESS_NATIVE(base,0x70) +#define IORD_ALTERA_TSEMAC_A_FRAME_CHECK_SEQ_ERRS(base) IORD_32DIRECT(base, 0x70) + + +#define IOADDR_ALTERA_TSEMAC_A_ALIGNMENT_ERRS(base) __IO_CALC_ADDRESS_NATIVE(base,0x74) +#define IORD_ALTERA_TSEMAC_A_ALIGNMENT_ERRS(base) IORD_32DIRECT(base, 0x74) + + +#define IOADDR_ALTERA_TSEMAC_A_OCTETS_TX_OK(base) __IO_CALC_ADDRESS_NATIVE(base,0x78) +#define IORD_ALTERA_TSEMAC_A_OCTETS_TX_OK(base) IORD_32DIRECT(base, 0x78) + + +#define IOADDR_ALTERA_TSEMAC_A_OCTETS_RX_OK(base) __IO_CALC_ADDRESS_NATIVE(base,0x7c) +#define IORD_ALTERA_TSEMAC_A_OCTETS_RX_OK(base) IORD_32DIRECT(base, 0x7c) + + +#define IOADDR_ALTERA_TSEMAC_A_TX_PAUSE_MAC_CTRL_FRAMES(base) __IO_CALC_ADDRESS_NATIVE(base,0x80) +#define IORD_ALTERA_TSEMAC_A_TX_PAUSE_MAC_CTRL_FRAMES(base) IORD_32DIRECT(base, 0x80) + + +#define IOADDR_ALTERA_TSEMAC_A_RX_PAUSE_MAC_CTRL_FRAMES(base) __IO_CALC_ADDRESS_NATIVE(base,0x84) +#define IORD_ALTERA_TSEMAC_A_RX_PAUSE_MAC_CTRL_FRAMES(base) IORD_32DIRECT(base, 0x84) + + +#define IOADDR_ALTERA_TSEMAC_IF_IN_ERRORS(base) __IO_CALC_ADDRESS_NATIVE(base,0x88) +#define IORD_ALTERA_TSEMAC_IF_IN_ERRORS(base) IORD_32DIRECT(base, 0x88) + + +#define IOADDR_ALTERA_TSEMAC_IF_OUT_ERRORS(base) __IO_CALC_ADDRESS_NATIVE(base,0x8c) +#define IORD_ALTERA_TSEMAC_IF_OUT_ERRORS(base) IORD_32DIRECT(base, 0x8c) + + +#define IOADDR_ALTERA_TSEMAC_IF_IN_UCAST_PKTS(base) __IO_CALC_ADDRESS_NATIVE(base,0x90) +#define IORD_ALTERA_TSEMAC_IF_IN_UCAST_PKTS(base) IORD_32DIRECT(base, 0x90) + + +#define IOADDR_ALTERA_TSEMAC_IF_IN_MULTICAST_PKTS(base) __IO_CALC_ADDRESS_NATIVE(base,0x94) +#define IORD_ALTERA_TSEMAC_IF_IN_MULTICAST_PKTS(base) IORD_32DIRECT(base, 0x94) + + +#define IOADDR_ALTERA_TSEMAC_IF_IN_BROADCAST_PKTS(base) __IO_CALC_ADDRESS_NATIVE(base,0x98) +#define IORD_ALTERA_TSEMAC_IF_IN_BROADCAST_PKTS(base) IORD_32DIRECT(base, 0x98) + + +#define IOADDR_ALTERA_TSEMAC_IF_OUT_DISCARDS(base) __IO_CALC_ADDRESS_NATIVE(base,0x9C) +#define IORD_ALTERA_TSEMAC_IF_OUT_DISCARDS(base) IORD_32DIRECT(base, 0x9C) + + +#define IOADDR_ALTERA_TSEMAC_IF_OUT_UCAST_PKTS(base) __IO_CALC_ADDRESS_NATIVE(base,0xA0) +#define IORD_ALTERA_TSEMAC_IF_OUT_UCAST_PKTS(base) IORD_32DIRECT(base, 0xA0) + + +#define IOADDR_ALTERA_TSEMAC_IF_OUT_MULTICAST_PKTS(base) __IO_CALC_ADDRESS_NATIVE(base,0xA4) +#define IORD_ALTERA_TSEMAC_IF_OUT_MULTICAST_PKTS(base) IORD_32DIRECT(base, 0xA4) + + +#define IOADDR_ALTERA_TSEMAC_IF_OUT_BROADCAST_PKTS(base) __IO_CALC_ADDRESS_NATIVE(base,0xA8) +#define IORD_ALTERA_TSEMAC_IF_OUT_BROADCAST_PKTS(base) IORD_32DIRECT(base, 0xA8) + + +#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_DROP_EVENTS(base) __IO_CALC_ADDRESS_NATIVE(base,0xAC) +#define IORD_ALTERA_TSEMAC_ETHER_STATS_DROP_EVENTS(base) IORD_32DIRECT(base, 0xAC) + + +#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_OCTETS(base) __IO_CALC_ADDRESS_NATIVE(base,0xB0) +#define IORD_ALTERA_TSEMAC_ETHER_STATS_OCTETS(base) IORD_32DIRECT(base, 0xB0) + + +#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_PKTS(base) __IO_CALC_ADDRESS_NATIVE(base,0xB4) +#define IORD_ALTERA_TSEMAC_ETHER_STATS_PKTS(base) IORD_32DIRECT(base, 0xB4) + + +#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_UNDERSIZE_PKTS(base) __IO_CALC_ADDRESS_NATIVE(base,0xB8) +#define IORD_ALTERA_TSEMAC_ETHER_STATS_UNDERSIZE_PKTS(base) IORD_32DIRECT(base, 0xB8) + + +#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_OVERSIZE_PKTS(base) __IO_CALC_ADDRESS_NATIVE(base,0xBC) +#define IORD_ALTERA_TSEMAC_ETHER_STATS_OVERSIZE_PKTS(base) IORD_32DIRECT(base, 0xBC) + + +#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_PKTS_64_OCTETS(base) __IO_CALC_ADDRESS_NATIVE(base,0xC0) +#define IORD_ALTERA_TSEMAC_ETHER_STATS_PKTS_64_OCTETS(base) IORD_32DIRECT(base, 0xC0) + + +#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_PKTS_65_TO_127_OCTETS(base) __IO_CALC_ADDRESS_NATIVE(base,0xC4) +#define IORD_ALTERA_TSEMAC_ETHER_STATS_PKTS_65_TO_127_OCTETS(base) IORD_32DIRECT(base, 0xC4) + + +#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_PKTS_128_TO_255_OCTETS(base) __IO_CALC_ADDRESS_NATIVE(base,0xC8) +#define IORD_ALTERA_TSEMAC_ETHER_STATS_PKTS_128_TO_255_OCTETS(base) IORD_32DIRECT(base, 0xC8) + + +#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_PKTS_256_TO_511_OCTETS(base) __IO_CALC_ADDRESS_NATIVE(base,0xCC) +#define IORD_ALTERA_TSEMAC_ETHER_STATS_PKTS_256_TO_511_OCTETS(base) IORD_32DIRECT(base, 0xCC) + + +#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_PKTS_512_TO_1023_OCTETS(base) __IO_CALC_ADDRESS_NATIVE(base,0xD0) +#define IORD_ALTERA_TSEMAC_ETHER_STATS_PKTS_512_TO_1023_OCTETS(base) IORD_32DIRECT(base, 0xD0) + + +#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_PKTS_1024_TO_1518_OCTETS(base) __IO_CALC_ADDRESS_NATIVE(base,0xD4) +#define IORD_ALTERA_TSEMAC_ETHER_STATS_PKTS_1024_TO_1518_OCTETS(base) IORD_32DIRECT(base, 0xD4) + + +#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_PKTS_1519_TO_X_OCTETS(base) __IO_CALC_ADDRESS_NATIVE(base,0xD8) +#define IORD_ALTERA_TSEMAC_ETHER_STATS_PKTS_1519_TO_X_OCTETS(base) IORD_32DIRECT(base, 0xD8) + + +#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_JABBERS(base) __IO_CALC_ADDRESS_NATIVE(base,0xDC) +#define IORD_ALTERA_TSEMAC_ETHER_STATS_JABBERS(base) IORD_32DIRECT(base, 0xDC) + + +#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_FRAGMENTS(base) __IO_CALC_ADDRESS_NATIVE(base,0xE0) +#define IORD_ALTERA_TSEMAC_ETHER_STATS_FRAGMENTS(base) IORD_32DIRECT(base, 0xE0) + + + +/* Register offset 0xE4 reserved */ + +#define IOADDR_ALTERA_TSEMAC_TX_CMD_STAT(base) __IO_CALC_ADDRESS_NATIVE(base,0xE8) +#define IORD_ALTERA_TSEMAC_TX_CMD_STAT(base) IORD_32DIRECT(base, 0xE8) +#define IOWR_ALTERA_TSEMAC_TX_CMD_STAT(base,data) IOWR_32DIRECT(base, 0xE8, data) + + +#define IOADDR_ALTERA_TSEMAC_RX_CMD_STAT(base) __IO_CALC_ADDRESS_NATIVE(base,0xEC) +#define IORD_ALTERA_TSEMAC_RX_CMD_STAT(base) IORD_32DIRECT(base, 0xEC) +#define IOWR_ALTERA_TSEMAC_RX_CMD_STAT(base,data) IOWR_32DIRECT(base, 0xEC, data) + + +#define ALTERA_TSEMAC_TX_CMD_STAT_OMITCRC_OFST (17) +#define ALTERA_TSEMAC_TX_CMD_STAT_OMITCRC_MSK (0x20000) +#define ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_OFST (18) +#define ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_MSK (0x40000) + +#define ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_OFST (25) +#define ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_MSK (0x2000000) + +/* Register offset 0xF0 to 0xFC reserved */ + + +/* + * Share Multi Channel FIFO + * + * ## Threshold Register Access ## - Av-MM interface 1 + */ +#define IOADDR_ALTERA_MULTI_CHAN_FIFO_SEC_FULL_THRESHOLD(base) __IO_CALC_ADDRESS_NATIVE(base,0x00) +#define IORD_ALTERA_MULTI_CHAN_FIFO_SEC_FULL_THRESHOLD(base) IORD_32DIRECT(base, 0x00) +#define IOWR_ALTERA_MULTI_CHAN_FIFO_SEC_FULL_THRESHOLD(base,data) IOWR_32DIRECT(base, 0x00, data) + + +#define IOADDR_ALTERA_MULTI_CHAN_FIFO_SEC_EMPTY_THRESHOLD(base) __IO_CALC_ADDRESS_NATIVE(base,0x04) +#define IORD_ALTERA_MULTI_CHAN_FIFO_SEC_EMPTY_THRESHOLD(base) IORD_32DIRECT(base, 0x04) +#define IOWR_ALTERA_MULTI_CHAN_FIFO_SEC_EMPTY_THRESHOLD(base,data) IOWR_32DIRECT(base, 0x04, data) + +#define IOADDR_ALTERA_MULTI_CHAN_FIFO_ALMOST_FULL_THRESHOLD(base) __IO_CALC_ADDRESS_NATIVE(base,0x08) +#define IORD_ALTERA_MULTI_CHAN_FIFO_ALMOST_FULL_THRESHOLD(base) IORD_32DIRECT(base, 0x08) +#define IOWR_ALTERA_MULTI_CHAN_FIFO_ALMOST_FULL_THRESHOLD(base,data) IOWR_32DIRECT(base, 0x08, data) + +#define IOADDR_ALTERA_MULTI_CHAN_FIFO_ALMOST_EMPTY_THRESHOLD(base) __IO_CALC_ADDRESS_NATIVE(base,0x10) +#define IORD_ALTERA_MULTI_CHAN_FIFO_ALMOST_EMPTY_THRESHOLD(base) IORD_32DIRECT(base, 0x10) +#define IOWR_ALTERA_MULTI_CHAN_FIFO_ALMOST_EMPTY_THRESHOLD(base,data) IOWR_32DIRECT(base, 0x10, data) + +/* + * Share Multi Channel FIFO + * + * ## Fill Level Query Access ## - Av-MM interface 2 + */ +#define IOADDR_ALTERA_MULTI_CHAN_FILL_LEVEL(base, channel) __IO_CALC_ADDRESS_NATIVE(base,(channel * 0x04)) +#define IORD_ALTERA_MULTI_CHAN_FILL_LEVEL(base, channel) IORD_32DIRECT(base, (channel * 0x04)) + +/* + * Hash table occupies registers 0x100:0x1FC. Explicit register definitions + * are not provided. If programatic access to the hash table is necessary, + * define a region of uncached memory using alt_remap_uncached, or use the + * IORD/IOWR macros to access memory at the Ethernet MAC base address plus + * offsets in the range 0x100 to 0x1Fc. + * + * The hash table's purpose is to provide multicast address resolution. When + * programming the table, only bit '0' is significant. If a '1' is written, + * all multicast addresses represented by the hash code (Address bits 0 to 5) + * are accepted by the controller. If a '0' is written, matching multicast + * addresses are rejected. + */ +#define IOADDR_ALTERA_TSEMAC_HASH_TABLE(base) \ + __IO_CALC_ADDRESS_NATIVE(base,0x100) +#define IORD_ALTERA_TSEMAC_HASH_TABLE(base, offset) \ + IORD_32DIRECT(base, (0x100 + offset)) +#define IOWR_ALTERA_TSEMAC_HASH_TABLE(base, offset, data) \ + IOWR_32DIRECT(base, (0x100 + offset), data) + + /* + * PHY MDIO registers + * + * For all registers, bits 15:0 are relevant. Bits 31:16 should be written + * with 0 and ignored on read. + */ + +/* Generic access macro for either MDIO port */ +#define IOADDR_ALTERA_TSEMAC_MDIO(base, mdio) \ + __IO_CALC_ADDRESS_NATIVE(base, (0x200 + (mdio * 0x80)) ) + +#define IORD_ALTERA_TSEMAC_MDIO(base, mdio, reg_num) \ + IORD_16DIRECT(base, 0x200 + (mdio * 0x80) + (reg_num * sizeof(alt_u32)) ) + +#define IOWR_ALTERA_TSEMAC_MDIO(base, mdio, reg_num, data) \ + IOWR_16DIRECT(base, 0x200 + (mdio * 0x80) + (reg_num * sizeof(alt_u32)), data) + + + +/* Low word (bits 31:0) of supplemental MAC address 0*/ +#define IOADDR_ALTERA_TSEMAC_SMAC_0_0(base) __IO_CALC_ADDRESS_NATIVE(base,0x300) +#define IORD_ALTERA_TSEMAC_SMAC_0_0(base) IORD_32DIRECT(base, 0x300) +#define IOWR_ALTERA_TSEMAC_SMAC_0_0(base,data) IOWR_32DIRECT(base, 0x300, data) + +/* High half-word (bits 47:32) of supplemental MAC address 0. Upper 16 bits reserved */ +#define IOADDR_ALTERA_TSEMAC_SMAC_0_1(base) __IO_CALC_ADDRESS_NATIVE(base,0x304) +#define IORD_ALTERA_TSEMAC_SMAC_0_1(base) IORD_32DIRECT(base, 0x304) +#define IOWR_ALTERA_TSEMAC_SMAC_0_1(base,data) IOWR_32DIRECT(base, 0x304, data) + +/* Low word (bits 31:0) of supplemental MAC address 1 */ +#define IOADDR_ALTERA_TSEMAC_SMAC_1_0(base) __IO_CALC_ADDRESS_NATIVE(base,0x308) +#define IORD_ALTERA_TSEMAC_SMAC_1_0(base) IORD_32DIRECT(base, 0x308) +#define IOWR_ALTERA_TSEMAC_SMAC_1_0(base,data) IOWR_32DIRECT(base, 0x308, data) + +/* High half-word (bits 47:32) of supplemental MAC address 1. Upper 16 bits reserved */ +#define IOADDR_ALTERA_TSEMAC_SMAC_1_1(base) __IO_CALC_ADDRESS_NATIVE(base,0x30C) +#define IORD_ALTERA_TSEMAC_SMAC_1_1(base) IORD_32DIRECT(base, 0x30C) +#define IOWR_ALTERA_TSEMAC_SMAC_1_1(base,data) IOWR_32DIRECT(base, 0x30C, data) + +/* Low word (bits 31:0) of supplemental MAC address 2 */ +#define IOADDR_ALTERA_TSEMAC_SMAC_2_0(base) __IO_CALC_ADDRESS_NATIVE(base,0x310) +#define IORD_ALTERA_TSEMAC_SMAC_2_0(base) IORD_32DIRECT(base, 0x310) +#define IOWR_ALTERA_TSEMAC_SMAC_2_0(base,data) IOWR_32DIRECT(base, 0x310, data) + +/* High half-word (bits 47:32) of supplemental MAC address 2. Upper 16 bits reserved */ +#define IOADDR_ALTERA_TSEMAC_SMAC_2_1(base) __IO_CALC_ADDRESS_NATIVE(base,0x314) +#define IORD_ALTERA_TSEMAC_SMAC_2_1(base) IORD_32DIRECT(base, 0x314) +#define IOWR_ALTERA_TSEMAC_SMAC_2_1(base,data) IOWR_32DIRECT(base, 0x314, data) + +/* Low word (bits 31:0) of supplemental MAC address 3 */ +#define IOADDR_ALTERA_TSEMAC_SMAC_3_0(base) __IO_CALC_ADDRESS_NATIVE(base,0x318) +#define IORD_ALTERA_TSEMAC_SMAC_3_0(base) IORD_32DIRECT(base, 0x318) +#define IOWR_ALTERA_TSEMAC_SMAC_3_0(base,data) IOWR_32DIRECT(base, 0x318, data) + +/* High half-word (bits 47:32) of supplemental MAC address 3. Upper 16 bits reserved */ +#define IOADDR_ALTERA_TSEMAC_SMAC_3_1(base) __IO_CALC_ADDRESS_NATIVE(base,0x31C) +#define IORD_ALTERA_TSEMAC_SMAC_3_1(base) IORD_32DIRECT(base, 0x31C) +#define IOWR_ALTERA_TSEMAC_SMAC_3_1(base,data) IOWR_32DIRECT(base, 0x31C, data) + + + + +/* Enumeration of commonly-used PHY registers */ +#define ALTERA_TSEMAC_PHY_ADDR_CONTROL 0x0 +#define ALTERA_TSEMAC_PHY_ADDR_STATUS 0x1 +#define ALTERA_TSEMAC_PHY_ADDR_PHY_ID1 0x2 +#define ALTERA_TSEMAC_PHY_ADDR_PHY_ID2 0x3 +#define ALTERA_TSEMAC_PHY_ADDR_PHY_ADV 0x4 +#define ALTERA_TSEMAC_PHY_ADDR_PHY_REMADV 0x5 + + +/* (Original) Register bit definitions and Ethernet MAC device structure */ +// COMMAND_CONFIG Register Bits +enum +{ + mmac_cc_TX_ENA_bit = 0, + mmac_cc_RX_ENA_bit = 1, + mmac_cc_XON_GEN_bit = 2, + mmac_cc_ETH_SPEED_bit = 3, + mmac_cc_PROMIS_EN_bit = 4, + mmac_cc_PAD_EN_bit = 5, + mmac_cc_CRC_FWD_bit = 6, + mmac_cc_PAUSE_FWD_bit = 7, + mmac_cc_PAUSE_IGNORE_bit = 8, + mmac_cc_TX_ADDR__INS_bit = 9, + mmac_cc_HD_ENA_bit = 10, + mmac_cc_EXCESS_COL_bit = 11, + mmac_cc_LATE_COL_bit = 12, + mmac_cc_SW_RESET_bit = 13, + mmac_cc_MHASH_SEL_bit = 14, + mmac_cc_LOOPBACK_bit = 15, + mmac_cc_TX_ADDR_SEL_bit = 16, // bits 18:16 = address select + mmac_cc_MAGIC_ENA_bit = 19, + mmac_cc_SLEEP_ENA_bit = 20, + mmac_cc_WAKEUP_bit = 21, + mmac_cc_XOFF_GEN_bit = 22, + mmac_cc_CNTL_FRM_ENA_bit = 23, + mmac_cc_NO_LENGTH_CHECK_bit = 24, + mmac_cc_ENA_10_bit = 25, + mmac_cc_RX_ERR_DISC_bit = 26, + mmac_cc_CNT_RESET_bit = 31, + + mmac_cc_TX_ENA_mask = (1 << 0), // enable TX + mmac_cc_RX_ENA_mask = (1 << 1), // enable RX + mmac_cc_XON_GEN_mask = (1 << 2), // generate Pause frame with Quanta + mmac_cc_ETH_SPEED_mask = (1 << 3), // Select Gigabit + mmac_cc_PROMIS_EN_mask = (1 << 4), // enable Promiscuous mode + mmac_cc_PAD_EN_mask = (1 << 5), // enable padding remove on RX + mmac_cc_CRC_FWD_mask = (1 << 6), // forward CRC to application on RX (as opposed to stripping it off) + mmac_cc_PAUSE_FWD_mask = (1 << 7), // forward Pause frames to application + mmac_cc_PAUSE_IGNORE_mask = (1 << 8), // ignore Pause frames + mmac_cc_TX_ADDR_INS_mask = (1 << 9), // MAC overwrites bytes 6 to 12 of frame with address on all transmitted frames + mmac_cc_HD_ENA_mask = (1 << 10),// enable half-duplex operation + mmac_cc_EXCESS_COL_mask = (1 << 11),// indicator + mmac_cc_LATE_COL_mask = (1 << 12),// indicator + mmac_cc_SW_RESET_mask = (1 << 13),// issue register and counter reset + mmac_cc_MHASH_SEL_mask = (1 << 14),// select multicast hash method + mmac_cc_LOOPBACK_mask = (1 << 15),// enable GMII loopback + mmac_cc_TX_ADDR_SEL_mask = (1 << 16),// bits 18:16 = address select + mmac_cc_MAGIC_ENA_mask = (1 << 19),// enable magic packet detect + mmac_cc_SLEEP_ENA_mask = (1 << 20),// enter sleep mode + mmac_cc_WAKEUP_mask = (1 << 21), + mmac_cc_XOFF_GEN_mask = (1 << 22), + mmac_cc_CNTL_FRM_ENA_mask = (1 << 23), + mmac_cc_NO_LENGTH_CHECK_mask = (1 << 24), // disable payload length check + mmac_cc_ENA_10_mask = (1 << 25), + mmac_cc_RX_ERR_DISCARD_mask = (1 << 26), + mmac_cc_CNT_RESET_mask = (1 << 31) +}; + +// TX_CMD_STAT Register bits +enum{ + mmac_tcs_OMIT_CRC_mask = (1 << 17), + mmac_tcs_TX_SHIFT16_mask = (1 << 18) +}; + + +// RX_CMD_STAT Register bits +enum{ + mmac_rcs_RX_SHIFT16_mask = (1 << 25) +}; + + + +// TxConf Register Bits +enum{ + mnet_txc_TYPE_AUTO_mask = (1 << 0), + mnet_txc_H2N_IP_mask = (1 << 1), + mnet_txc_H2N_PROT_mask = (1 << 2), + mnet_txc_IPCHK_mask = (1 << 3), + mnet_txc_PROTCHK_mask = (1 << 4) +}; + +// RxConf and RxStat register bits +enum{ + mnet_rxc_PADREMOVE_mask = (1 << 0), + mnet_rxc_IPERR_DISC_mask = (1 << 1), + mnet_rxc_PROTERR_DISC_mask = (1 << 2), + mnet_rxc_TYPE_REMOVE_mask = (1 << 3), + mnet_rxc_N2H_IP_mask = (1 << 4), + mnet_rxc_N2H_PROT_mask = (1 << 5), + + mnet_rxs_HDRLEN_mask = 0x1f, // 0..4 = header length of IP+Protocol in 32-bit words + mnet_rxs_IP_CHKERR_mask = (1 << 5), + mnet_rxs_PROT_CHKERR_mask = (1 << 6), + mnet_rxs_T_REMOVED_mask = (1 << 7), + mnet_rxs_VLAN_mask = (1 << 8), + mnet_rxs_IPv6_mask = (1 << 17), + mnet_rxs_FRAGMENT_mask = (1 << 18) // IPv4 fragment + +}; + +enum { + PCS_CTL_speed1 = 1<<6, // speed select + PCS_CTL_speed0 = 1<<13, + PCS_CTL_fullduplex = 1<<8, // fullduplex mode select + PCS_CTL_an_restart = 1<<9, // Autonegotiation restart command + PCS_CTL_isolate = 1<<10, // isolate command + PCS_CTL_powerdown = 1<<11, // powerdown command + PCS_CTL_an_enable = 1<<12, // Autonegotiation enable + PCS_CTL_rx_slpbk = 1<<14, // Serial Loopback enable + PCS_CTL_sw_reset = 1<<15 // perform soft reset + +}; + +/** PCS Status Register Bits. IEEE 801.2 Clause 22.2.4.2 + */ +enum { + PCS_ST_has_extcap = 1<<0, // PHY has extended capabilities registers + PCS_ST_rx_sync = 1<<2, // RX is in sync (8B/10B codes o.k.) + PCS_ST_an_ability = 1<<3, // PHY supports autonegotiation + PCS_ST_rem_fault = 1<<4, // Autonegotiation completed + PCS_ST_an_done = 1<<5 + +}; + +/** Autonegotiation Capabilities Register Bits. IEEE 802.3 Clause 37.2.1 */ + +enum { + ANCAP_NEXTPAGE = 1 << 15, + ANCAP_ACK = 1 << 14, + ANCAP_RF2 = 1 << 13, + ANCAP_RF1 = 1 << 12, + ANCAP_PS2 = 1 << 8, + ANCAP_PS1 = 1 << 7, + ANCAP_HD = 1 << 6, + ANCAP_FD = 1 << 5 + // all others are reserved +}; + +// MDIO registers within MAC register Space +// memory mapped access +typedef volatile struct np_tse_mdio_struct +{ + unsigned int CONTROL; + unsigned int STATUS; + unsigned int PHY_ID1; + unsigned int PHY_ID2; + unsigned int ADV; + unsigned int REMADV; + + unsigned int reg6; + unsigned int reg7; + unsigned int reg8; + unsigned int reg9; + unsigned int rega; + unsigned int regb; + unsigned int regc; + unsigned int regd; + unsigned int rege; + unsigned int regf; + unsigned int reg10; + unsigned int reg11; + unsigned int reg12; + unsigned int reg13; + unsigned int reg14; + unsigned int reg15; + unsigned int reg16; + unsigned int reg17; + unsigned int reg18; + unsigned int reg19; + unsigned int reg1a; + unsigned int reg1b; + unsigned int reg1c; + unsigned int reg1d; + unsigned int reg1e; + unsigned int reg1f; + +} np_tse_mdio; + +typedef volatile struct np_tse_mac_struct +{ + unsigned int REV; + unsigned int SCRATCH; + unsigned int COMMAND_CONFIG; + unsigned int MAC_0; + unsigned int MAC_1; + unsigned int FRM_LENGTH; + unsigned int PAUSE_QUANT; + unsigned int RX_SECTION_EMPTY; + unsigned int RX_SECTION_FULL; + unsigned int TX_SECTION_EMPTY; + unsigned int TX_SECTION_FULL; + unsigned int RX_ALMOST_EMPTY; + unsigned int RX_ALMOST_FULL; + unsigned int TX_ALMOST_EMPTY; + unsigned int TX_ALMOST_FULL; + unsigned int MDIO_ADDR0; + unsigned int MDIO_ADDR1; + + unsigned int reservedx44[5]; + unsigned int REG_STAT; + unsigned int TX_IPG_LENGTH; + + unsigned int aMACID_1; + unsigned int aMACID_2; + unsigned int aFramesTransmittedOK; + unsigned int aFramesReceivedOK; + unsigned int aFramesCheckSequenceErrors; + unsigned int aAlignmentErrors; + unsigned int aOctetsTransmittedOK; + unsigned int aOctetsReceivedOK; + unsigned int aTxPAUSEMACCtrlFrames; + unsigned int aRxPAUSEMACCtrlFrames; + unsigned int ifInErrors; + unsigned int ifOutErrors; + unsigned int ifInUcastPkts; + unsigned int ifInMulticastPkts; + unsigned int ifInBroadcastPkts; + unsigned int ifOutDiscards; + unsigned int ifOutUcastPkts; + unsigned int ifOutMulticastPkts; + unsigned int ifOutBroadcastPkts; + unsigned int etherStatsDropEvent; + unsigned int etherStatsOctets; + unsigned int etherStatsPkts; + unsigned int etherStatsUndersizePkts; + unsigned int etherStatsOversizePkts; + unsigned int etherStatsPkts64Octets; + unsigned int etherStatsPkts65to127Octets; + unsigned int etherStatsPkts128to255Octets; + unsigned int etherStatsPkts256to511Octets; + unsigned int etherStatsPkts512to1023Octets; + unsigned int etherStatsPkts1024to1518Octets; + unsigned int etherStatsPkts1519toXOctets; + unsigned int etherStatsJabbers; + unsigned int etherStatsFragments; + + unsigned int reservedxE4; + unsigned int TX_CMD_STAT; + unsigned int RX_CMD_STAT; + + unsigned int msb_aOctetsTransmittedOK; + unsigned int msb_aOctetsReceivedOK; + unsigned int msb_etherStatsOctets; + unsigned int reservedxFC; // current frame's IP payload sum result + + unsigned int hashtable[64]; + + np_tse_mdio mdio0; + np_tse_mdio mdio1; + + unsigned int smac0_0; + unsigned int smac0_1; + unsigned int smac1_0; + unsigned int smac1_1; + unsigned int smac2_0; + unsigned int smac2_1; + unsigned int smac3_0; + unsigned int smac3_1; + + unsigned int reservedx320[56]; + +} np_tse_mac; + +#endif /* __ALTERA_ETH_TSE_REGS_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_generic_quad_spi_controller.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_generic_quad_spi_controller.h new file mode 100644 index 0000000..387e138 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_generic_quad_spi_controller.h @@ -0,0 +1,126 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2015 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALT_QSPI_CONTROLLER_H__ +#define __ALT_QSPI_CONTROLLER_H__ + +#include "alt_types.h" +#include "sys/alt_flash_dev.h" +#include "sys/alt_llist.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/** + * Description of the QSPI controller + */ +typedef struct alt_qspi_controller_dev +{ + alt_flash_dev dev; + + alt_u32 data_base; /** base address of data slave */ + alt_u32 data_end; /** end address of data slave (not inclusive) */ + alt_u32 csr_base; /** base address of CSR slave */ + alt_u32 size_in_bytes; /** size of memory in bytes */ + alt_u32 is_epcs; /** 1 if device is an EPCS device */ + alt_u32 number_of_sectors; /** number of flash sectors */ + alt_u32 sector_size; /** size of each flash sector */ + alt_u32 page_size; /** page size */ + alt_u32 silicon_id; /** ID of silicon used with EPCQ/QSPI IP */ +} alt_qspi_controller_dev; + +/** +* Macros used by alt_sys_init.c to create data storage for driver instance +*/ +#define ALTERA_GENERIC_QUAD_SPI_CONTROLLER_AVL_MEM_AVL_CSR_INSTANCE(qspi_name, avl_mem, avl_csr, qspi_dev) \ +static alt_qspi_controller_dev qspi_dev = \ +{ \ + .dev = { \ + .llist = ALT_LLIST_ENTRY, \ + .name = avl_mem##_NAME, \ + .write = alt_qspi_controller_write, \ + .read = alt_qspi_controller_read, \ + .get_info = alt_qspi_controller_get_info, \ + .erase_block = alt_qspi_controller_erase_block, \ + .write_block = alt_qspi_controller_write_block, \ + .base_addr = ((void*)(avl_mem##_BASE)), \ + .length = ((int)(avl_mem##_SPAN)), \ + .lock = alt_qspi_controller_lock , \ + }, \ + .data_base = ((alt_u32)(avl_mem##_BASE)), \ + .data_end = ((alt_u32)(avl_mem##_BASE) + (alt_u32)(avl_mem##_SPAN)), \ + .csr_base = ((alt_u32)(avl_csr##_BASE)), \ + .size_in_bytes = ((alt_u32)(avl_mem##_SPAN)), \ + .is_epcs = ((alt_u32)(avl_mem##_IS_EPCS)), \ + .number_of_sectors = ((alt_u32)(avl_mem##_NUMBER_OF_SECTORS)), \ + .sector_size = ((alt_u32)(avl_mem##_SECTOR_SIZE)), \ + .page_size = ((alt_u32)(avl_mem##_PAGE_SIZE)) , \ +} + +/* + Public API + + Refer to Using Flash Devices in the + Developing Programs Using the Hardware Abstraction Layer chapter + of the Nios II Software Developer's Handbook. + +*/ +int alt_qspi_controller_read(alt_flash_dev *flash_info, int offset, void *dest_addr, int length); + +int alt_qspi_controller_get_info(alt_flash_fd *fd, flash_region **info, int *number_of_regions); + +int alt_qspi_controller_erase_block(alt_flash_dev *flash_info, int block_offset); + +int alt_qspi_controller_write_block(alt_flash_dev *flash_info, int block_offset, int data_offset, const void *data, int length); + +int alt_qspi_controller_write(alt_flash_dev *flash_info, int offset, const void *src_addr, int length); + +int alt_qspi_controller_lock(alt_flash_dev *flash_info, alt_u32 sectors_to_lock); + + +/* + * Initialization function + */ +extern alt_32 altera_qspi_controller_init(alt_qspi_controller_dev *dev); + +/* + * alt_sys_init.c will call this macro automatically initialize the driver instance + */ +#define ALTERA_GENERIC_QUAD_SPI_CONTROLLER_INIT(name, dev) \ + altera_qspi_controller_init(&dev); + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_QSPI_CONTROLLER_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_generic_quad_spi_controller_regs.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_generic_quad_spi_controller_regs.h new file mode 100644 index 0000000..722cdc1 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_generic_quad_spi_controller_regs.h @@ -0,0 +1,260 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2014 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_QSPI_CONTROLLER_REGS_H__ +#define __ALTERA_QSPI_CONTROLLER_REGS_H__ + +#include + +/* + * QSPI_RD_STATUS register offset + * + * The QSPI_RD_STATUS register contains information from the read status + * register operation. A full description of the register can be found in the + * data sheet, + * + */ +#define ALTERA_QSPI_CONTROLLER_STATUS_REG (0x0) + +/* + * QSPI_RD_STATUS register access macros + */ +#define IOADDR_ALTERA_QSPI_CONTROLLER_STATUS(base) \ + __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_QSPI_CONTROLLER_STATUS_REG) + +#define IORD_ALTERA_QSPI_CONTROLLER_STATUS(base) \ + IORD_32DIRECT(base, ALTERA_QSPI_CONTROLLER_STATUS_REG) + +#define IOWR_ALTERA_QSPI_CONTROLLER_STATUS(base, data) \ + IOWR_32DIRECT(base, ALTERA_QSPI_CONTROLLER_STATUS_REG, data) + +/* + * QSPI_RD_STATUS register description macros + */ + +/** Write in progress bit */ +#define ALTERA_QSPI_CONTROLLER_STATUS_WIP_MASK (0x00000001) +#define ALTERA_QSPI_CONTROLLER_STATUS_WIP_AVAILABLE (0x00000000) +#define ALTERA_QSPI_CONTROLLER_STATUS_WIP_BUSY (0x00000001) +/** When to time out a poll of the write in progress bit */ +/* 0.7 sec time out */ +#define ALTERA_QSPI_CONTROLLER_1US_TIMEOUT_VALUE 700000 + +/* + * QSPI_RD_SID register offset + * + * The QSPI_RD_SID register contains the information from the read silicon ID + * operation and can be used to determine what type of EPCS device we have. + * Only support in EPCS16 and EPCS64. + * + * This register is valid only if the device is an EPCS. + * + */ +#define ALTERA_QSPI_CONTROLLER_SID_REG (0x4) + +/* + * QSPI_RD_SID register access macros + */ +#define IOADDR_ALTERA_QSPI_CONTROLLER_SID(base) \ + __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_QSPI_CONTROLLER_SID_REG) + +#define IORD_ALTERA_QSPI_CONTROLLER_SID(base) \ + IORD_32DIRECT(base, ALTERA_QSPI_CONTROLLER_SID_REG) + +#define IOWR_ALTERA_QSPI_CONTROLLER_SID(base, data) \ + IOWR_32DIRECT(base, ALTERA_QSPI_CONTROLLER_SID_REG, data) + +/* + * QSPI_RD_SID register description macros + * + * Specific device values obtained from Table 14 of: + * "Serial Configuration (EPCS) Devices Datasheet" + */ +#define ALTERA_QSPI_CONTROLLER_SID_MASK (0x000000FF) +#define ALTERA_QSPI_CONTROLLER_SID_EPCS16 (0x00000014) +#define ALTERA_QSPI_CONTROLLER_SID_EPCS64 (0x00000016) +#define ALTERA_QSPI_CONTROLLER_SID_EPCS128 (0x00000018) + +/* + * QSPI_RD_RDID register offset + * + * The QSPI_RD_RDID register contains the information from the read memory + * capacity operation and can be used to determine what type of EPCQ/QSPI device + * we have. + * + * This register is only valid if the device is an EPCQ/QSPI. + * + */ +#define ALTERA_QSPI_CONTROLLER_RDID_REG (0x8) + +/* + * QSPI_RD_RDID register access macros + */ +#define IOADDR_ALTERA_QSPI_CONTROLLER_RDID(base) \ + __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_QSPI_CONTROLLER_RDID_REG) + +#define IORD_ALTERA_QSPI_CONTROLLER_RDID(base) \ + IORD_32DIRECT(base, ALTERA_QSPI_CONTROLLER_RDID_REG) + +#define IOWR_ALTERA_QSPI_CONTROLLER_RDID(base, data) \ + IOWR_32DIRECT(base, ALTERA_QSPI_CONTROLLER_RDID_REG, data) + +/* + * QSPI_RD_RDID register description macros + * + * Specific device values obtained from Table 28 of: + * "Quad-Serial Configuration (EPCQ/QSPI? (www.altera.com/literature/hb/cfg/cfg_cf52012.pdf)) + * Devices Datasheet" + */ +#define ALTERA_QSPI_CONTROLLER_RDID_MASK (0x000000FF) +#define ALTERA_QSPI_CONTROLLER_RDID_QSPI16 (0x00000015) +#define ALTERA_QSPI_CONTROLLER_RDID_QSPI32 (0x00000016) +#define ALTERA_QSPI_CONTROLLER_RDID_QSPI64 (0x00000017) +#define ALTERA_QSPI_CONTROLLER_RDID_QSPI128 (0x00000018) +#define ALTERA_QSPI_CONTROLLER_RDID_QSPI256 (0x00000019) +#define ALTERA_QSPI_CONTROLLER_RDID_QSPI512 (0x00000020) +#define ALTERA_QSPI_CONTROLLER_RDID_QSPI1024 (0x00000021) + +/* + * QSPI_MEM_OP register offset + * + * The QSPI_MEM_OP register is used to do memory protect and erase operations + * + */ +#define ALTERA_QSPI_CONTROLLER_MEM_OP_REG (0xC) + +/* + * QSPI_MEM_OP register access macros + */ +#define IOADDR_ALTERA_QSPI_CONTROLLER_MEM_OP(base) \ + __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_QSPI_CONTROLLER_MEM_OP_REG) + +#define IORD_ALTERA_QSPI_CONTROLLER_MEM_OP(base) \ + IORD_32DIRECT(base, ALTERA_QSPI_CONTROLLER_MEM_OP_REG) + +#define IOWR_ALTERA_QSPI_CONTROLLER_MEM_OP(base, data) \ + IOWR_32DIRECT(base, ALTERA_QSPI_CONTROLLER_MEM_OP_REG, data) + +/* + * QSPI_MEM_OP register description macros + */ +#define ALTERA_QSPI_CONTROLLER_MEM_OP_CMD_MASK (0x00000003) +#define ALTERA_QSPI_CONTROLLER_MEM_OP_BULK_ERASE_CMD (0x00000001) +#define ALTERA_QSPI_CONTROLLER_MEM_OP_SECTOR_ERASE_CMD (0x00000002) +#define ALTERA_QSPI_CONTROLLER_MEM_OP_SECTOR_PROTECT_CMD (0x00000003) + +/** see datasheet for sector values */ +#define ALTERA_QSPI_CONTROLLER_MEM_OP_SECTOR_VALUE_MASK (0x00FFFF00) + +/* + * QSPI_ISR register offset + * + * The QSPI_ISR register is used to determine whether an invalid write or erase + * operation triggered an interrupt + * + */ +#define ALTERA_QSPI_CONTROLLER_ISR_REG (0x10) + +/* + * QSPI_ISR register access macros + */ +#define IOADDR_ALTERA_QSPI_CONTROLLER_ISR(base) \ + __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_QSPI_CONTROLLER_ISR_REG) + +#define IORD_ALTERA_QSPI_CONTROLLER_ISR(base) \ + IORD_32DIRECT(base, ALTERA_QSPI_CONTROLLER_ISR_REG) + +#define IOWR_ALTERA_QSPI_CONTROLLER_ISR(base, data) \ + IOWR_32DIRECT(base, ALTERA_QSPI_CONTROLLER_ISR_REG, data) + +/* + * QSPI_ISR register description macros + */ +#define ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_ERASE_MASK (0x00000001) +#define ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_ERASE_ACTIVE (0x00000001) + +#define ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_WRITE_MASK (0x00000002) +#define ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_WRITE_ACTIVE (0x00000002) + + +/* + * QSPI_IMR register offset + * + * The QSPI_IMR register is used to mask the invalid erase or the invalid write + * interrupts. + * + */ +#define ALTERA_QSPI_CONTROLLER_IMR_REG (0x14) + +/* + * QSPI_IMR register access macros + */ +#define IOADDR_ALTERA_QSPI_CONTROLLER_IMR(base) \ + __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_QSPI_CONTROLLER_IMR_REG) + +#define IORD_ALTERA_QSPI_CONTROLLER_IMR(base) \ + IORD_32DIRECT(base, ALTERA_QSPI_CONTROLLER_IMR_REG) + +#define IOWR_ALTERA_QSPI_CONTROLLER_IMR(base, data) \ + IOWR_32DIRECT(base, ALTERA_QSPI_CONTROLLER_IMR_REG, data) + +/* + * QSPI_IMR register description macros + */ +#define ALTERA_QSPI_CONTROLLER_IMR_ILLEGAL_ERASE_MASK (0x00000001) +#define ALTERA_QSPI_CONTROLLER_IMR_ILLEGAL_ERASE_ENABLED (0x00000001) + +#define ALTERA_QSPI_CONTROLLER_IMR_ILLEGAL_WRITE_MASK (0x00000002) +#define ALTERA_QSPI_CONTROLLER_IMR_ILLEGAL_WRITE_ENABLED (0x00000002) + +/* + * QSPI_CHIP_SELECT register offset + * + * The QSPI_CHIP_SELECT register is used to issue chip select + */ +#define ALTERA_QSPI_CHIP_SELECT_REG (0x18) + +/* + * QSPI_CHIP_SELECT register access macros + */ +#define IOADDR_ALTERA_QSPI_CHIP_SELECT(base) \ + __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_QSPI_CHIP_SELECT_REG) + +#define IOWR_ALTERA_QSPI_CHIP_SELECT(base, data) \ + IOWR_32DIRECT(base, ALTERA_QSPI_CHIP_SELECT_REG, data) + +/* + * QSPI_CHIP_SELECT register description macros + */ +#define ALTERA_QSPI_CHIP1_SELECT (0x00000001) +#define ALTERA_QSPI_CHIP2_SELECT (0x00000002) +#define ALTERA_QSPI_CHIP3_SELECT (0x00000003) + +#endif /* __ALTERA_QSPI_CONTROLLER_REGS_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma.h new file mode 100644 index 0000000..0ab231f --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma.h @@ -0,0 +1,512 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2014 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_MSGDMA_H__ +#define __ALTERA_MSGDMA_H__ + +#include +#include + +#include "sys/alt_dev.h" +#include "alt_types.h" +#include "altera_msgdma_csr_regs.h" +#include "altera_msgdma_descriptor_regs.h" +#include "altera_msgdma_response_regs.h" +#include "altera_msgdma_prefetcher_regs.h" +#include "os/alt_sem.h" +#include "os/alt_flag.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Helper struct to have easy access to hi/low values from a 64 bit value. + * Useful when having to write prefetcher/descriptor 64 bit addresses. + */ +typedef union { + alt_u64 u64; + alt_u32 u32[2]; +} msgdma_addr64; + +/* + * To ensure that a descriptor is created without spaces between the structure + * members, we call upon GCC's ability to pack to a byte-aligned boundary. + * Additionally, msgdma requires the descriptors to be aligned to a 16 byte + * boundary. + */ +#define alt_msgdma_standard_descriptor_packed \ + __attribute__ ((packed, aligned(16))) +#define alt_msgdma_extended_descriptor_packed \ + __attribute__ ((packed, aligned(32))) +#define alt_msgdma_prefetcher_standard_descriptor_packed \ + __attribute__ ((packed, aligned(32))) +#define alt_msgdma_prefetcher_extended_descriptor_packed \ + __attribute__ ((packed, aligned(64))) +#define alt_msgdma_response_packed __attribute__ ((packed, aligned(4))) + +/* + * The function alt_find_dev() is used to search the device list "list" to + * locate a device named "name". If a match is found, then a pointer to the + * device is returned, otherwise NULL is returned. + */ +extern alt_dev* alt_find_dev (const char* name, alt_llist* list); + +/* Callback routine type definition */ +typedef void (*alt_msgdma_callback)(void *context); + +/* use this structure if you haven't enabled the enhanced features */ +typedef struct { + alt_u32 *read_address; + alt_u32 *write_address; + alt_u32 transfer_length; + alt_u32 control; +} alt_msgdma_standard_descriptor_packed alt_msgdma_standard_descriptor; + +/* use this structure if you have enabled the enhanced features (only the + * elements enabled in hardware will be used) + */ +typedef struct { + alt_u32 *read_address_low; + alt_u32 *write_address_low; + alt_u32 transfer_length; + alt_u16 sequence_number; + alt_u8 read_burst_count; + alt_u8 write_burst_count; + alt_u16 read_stride; + alt_u16 write_stride; + alt_u32 *read_address_high; + alt_u32 *write_address_high; + alt_u32 control; +} alt_msgdma_extended_descriptor_packed alt_msgdma_extended_descriptor; + + +/* Prefetcher Descriptors need to be different than standard dispatcher + * descriptors use this structure if you haven't enabled the enhanced + * features + */ +typedef struct { + alt_u32 read_address; + alt_u32 write_address; + alt_u32 transfer_length; + alt_u32 next_desc_ptr; + alt_u32 bytes_transfered; + alt_u16 status; + alt_u16 _pad1_rsvd; + alt_u32 _pad2_rsvd; + alt_u32 control; +} alt_msgdma_prefetcher_standard_descriptor_packed alt_msgdma_prefetcher_standard_descriptor; + +/* use this structure if you have enabled the enhanced features (only the elements +enabled in hardware will be used) */ +typedef struct { + alt_u32 read_address_low; + alt_u32 write_address_low; + alt_u32 transfer_length; + alt_u32 next_desc_ptr_low; + alt_u32 bytes_transfered; + alt_u16 status; + alt_u16 _pad1_rsvd; + alt_u32 _pad2_rsvd; + alt_u16 sequence_number; + alt_u8 read_burst_count; + alt_u8 write_burst_count; + alt_u16 read_stride; + alt_u16 write_stride; + alt_u32 read_address_high; + alt_u32 write_address_high; + alt_u32 next_desc_ptr_high; + alt_u32 _pad3_rsvd[3]; + alt_u32 control; +} alt_msgdma_prefetcher_extended_descriptor_packed alt_msgdma_prefetcher_extended_descriptor; + + +/* msgdma device structure */ +typedef struct alt_msgdma_dev +{ + /* Device linked-list entry */ + alt_llist llist; + /* Name of msgdma in Qsys system */ + const char *name; + /* Base address of control and status register */ + alt_u32 *csr_base; + /* Base address of the descriptor slave port */ + alt_u32 *descriptor_base; + /* Base address of the response register */ + alt_u32 *response_base; + /* Base address of the prefetcher register */ + alt_u32 *prefetcher_base; + /* device IRQ controller ID */ + alt_u32 irq_controller_ID; + /* device IRQ ID */ + alt_u32 irq_ID; + /* FIFO size to store descriptor count, + { 8, 16, 32, 64,default:128, 256, 512, 1024 } */ + alt_u32 descriptor_fifo_depth; + /* FIFO size to store response count */ + alt_u32 response_fifo_depth; + /* Callback routine pointer */ + alt_msgdma_callback callback; + /* Callback context pointer */ + void *callback_context; + /* user define control setting during interrupt registering*/ + alt_u32 control; + /* Enable burst transfer */ + alt_u8 burst_enable; + /* Enable burst wrapping */ + alt_u8 burst_wrapping_support; + /* Depth of the internal data path FIFO*/ + alt_u32 data_fifo_depth; + /* Data path Width. This parameter affect both read + master and write master data width */ + alt_u32 data_width; + /* Maximum burst count*/ + alt_u32 max_burst_count; + /* Maximum transfer length*/ + alt_u32 max_byte; + /* Maximum stride count */ + alt_u64 max_stride; + /* Enable dynamic burst programming*/ + alt_u8 programmable_burst_enable; + /* Enable stride addressing */ + alt_u8 stride_enable; + /* Supported transaction type */ + const char *transfer_type; + /* Extended feature support enable "1"-enable "0"-disable */ + alt_u8 enhanced_features; + /* Enable response port "0"-memory-mapped, "1"-streaming, "2"-disable */ + alt_u8 response_port; + /* Prefetcher enabled "0"-disabled, "1"-enabled*/ + alt_u8 prefetcher_enable; + /* Semaphore used to control access registers + in multi-threaded mode */ + ALT_SEM (regs_lock) +} __attribute__ ((aligned(0x10))) alt_msgdma_dev; + + + +/******************************************************************************* + * Public API + ******************************************************************************/ +alt_msgdma_dev* alt_msgdma_open (const char* name); + +void alt_msgdma_register_callback( + alt_msgdma_dev *dev, + alt_msgdma_callback callback, + alt_u32 control, + void *context); + +int alt_msgdma_standard_descriptor_async_transfer( + alt_msgdma_dev *dev, + alt_msgdma_standard_descriptor *desc); + +int alt_msgdma_extended_descriptor_async_transfer( + alt_msgdma_dev *dev, + alt_msgdma_extended_descriptor *desc); + +int alt_msgdma_construct_standard_mm_to_mm_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_standard_descriptor *descriptor, + alt_u32 *read_address, + alt_u32 *write_address, + alt_u32 length, + alt_u32 control); + +int alt_msgdma_construct_standard_st_to_mm_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_standard_descriptor *descriptor, + alt_u32 *write_address, + alt_u32 length, + alt_u32 control); + +int alt_msgdma_construct_standard_mm_to_st_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_standard_descriptor *descriptor, + alt_u32 *read_address, + alt_u32 length, + alt_u32 control); + +int alt_msgdma_construct_extended_st_to_mm_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_extended_descriptor *descriptor, + alt_u32 *write_address, + alt_u32 length, + alt_u32 control, + alt_u16 sequence_number, + alt_u8 write_burst_count, + alt_u16 write_stride); + +int alt_msgdma_construct_extended_mm_to_st_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_extended_descriptor *descriptor, + alt_u32 *read_address, + alt_u32 length, + alt_u32 control, + alt_u16 sequence_number, + alt_u8 read_burst_count, + alt_u16 read_stride); + +int alt_msgdma_construct_extended_mm_to_mm_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_extended_descriptor *descriptor, + alt_u32 *read_address, + alt_u32 *write_address, + alt_u32 length, + alt_u32 control, + alt_u16 sequence_number, + alt_u8 read_burst_count, + alt_u8 write_burst_count, + alt_u16 read_stride, + alt_u16 write_stride); + +int alt_msgdma_standard_descriptor_sync_transfer( + alt_msgdma_dev *dev, + alt_msgdma_standard_descriptor *desc); + +int alt_msgdma_extended_descriptor_sync_transfer( + alt_msgdma_dev *dev, + alt_msgdma_extended_descriptor *desc); + +int alt_msgdma_standard_descriptor_sync_transfer( + alt_msgdma_dev *dev, + alt_msgdma_standard_descriptor *desc); + +/***************** MSGDMA PREFETCHER PUBLIC APIs ******************/ +int alt_msgdma_construct_prefetcher_standard_mm_to_mm_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_prefetcher_standard_descriptor *descriptor, + alt_u32 read_address, + alt_u32 write_address, + alt_u32 length, + alt_u32 control); + +int alt_msgdma_construct_prefetcher_standard_st_to_mm_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_prefetcher_standard_descriptor *descriptor, + alt_u32 write_address, + alt_u32 length, + alt_u32 control); + +int alt_msgdma_construct_prefetcher_standard_mm_to_st_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_prefetcher_standard_descriptor *descriptor, + alt_u32 read_address, + alt_u32 length, + alt_u32 control); + +int alt_msgdma_construct_prefetcher_extended_st_to_mm_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_prefetcher_extended_descriptor *descriptor, + alt_u32 write_address_high, + alt_u32 write_address_low, + alt_u32 length, + alt_u32 control, + alt_u16 sequence_number, + alt_u8 write_burst_count, + alt_u16 write_stride); + +int alt_msgdma_construct_prefetcher_extended_mm_to_st_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_prefetcher_extended_descriptor *descriptor, + alt_u32 read_address_high, + alt_u32 read_address_low, + alt_u32 length, + alt_u32 control, + alt_u16 sequence_number, + alt_u8 read_burst_count, + alt_u16 read_stride); + +int alt_msgdma_construct_prefetcher_extended_mm_to_mm_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_prefetcher_extended_descriptor *descriptor, + alt_u32 read_address_high, + alt_u32 read_address_low, + alt_u32 write_address_high, + alt_u32 write_address_low, + alt_u32 length, + alt_u32 control, + alt_u16 sequence_number, + alt_u8 read_burst_count, + alt_u8 write_burst_count, + alt_u16 read_stride, + alt_u16 write_stride); + +int alt_msgdma_prefetcher_add_standard_desc_to_list ( + alt_msgdma_prefetcher_standard_descriptor** list, + alt_msgdma_prefetcher_standard_descriptor* descriptor); + +int alt_msgdma_prefetcher_add_extended_desc_to_list ( + alt_msgdma_prefetcher_extended_descriptor** list, + alt_msgdma_prefetcher_extended_descriptor* descriptor); + +int alt_msgdma_start_prefetcher_with_std_desc_list ( + alt_msgdma_dev *dev, + alt_msgdma_prefetcher_standard_descriptor *list, + alt_u8 park_mode_en, + alt_u8 poll_en, + alt_u8 last_desc_owned_by_sw, + alt_u8 dcache_flush_desc_list); + +int alt_msgdma_start_prefetcher_with_extd_desc_list ( + alt_msgdma_dev *dev, + alt_msgdma_prefetcher_extended_descriptor *list, + alt_u8 park_mode_en, + alt_u8 poll_en, + alt_u8 last_desc_owned_by_sw, + alt_u8 dcache_flush_desc_list); + +int alt_msgdma_prefetcher_set_std_list_own_by_hw_bits ( + alt_msgdma_prefetcher_standard_descriptor *list, + alt_u8 last_desc_owned_by_sw, + alt_u8 dcache_flush_desc_list); + +int alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits ( + alt_msgdma_prefetcher_extended_descriptor *list, + alt_u8 last_desc_owned_by_sw, + alt_u8 dcache_flush_desc_list); + +void alt_msgdma_init (alt_msgdma_dev *dev, alt_u32 ic_id, alt_u32 irq); + +/* HAL initialization macros */ + +/*Depth of internal data path FIFO.STRIDE_ENABLE + * ALTERA_MSGDMA_INSTANCE is the macro used by alt_sys_init() to + * allocate any per device memory that may be required. + */ +#define ALTERA_MSGDMA_CSR_DESCRIPTOR_SLAVE_RESPONSE_INSTANCE(name, csr_if, desc_if, resp_if, dev) \ +static alt_msgdma_dev dev = \ +{ \ + ALT_LLIST_ENTRY, \ + name##_CSR_NAME, \ + ((alt_u32 *)(csr_if##_BASE)), \ + ((alt_u32 *)(desc_if##_BASE)), \ + ((alt_u32 *)(resp_if##_BASE)), \ + ((alt_u32 *)(0)), \ + ((alt_u32 )name##_CSR_IRQ_INTERRUPT_CONTROLLER_ID), \ + ((alt_u32 )name##_CSR_IRQ), \ + ((alt_u32 )desc_if##_DESCRIPTOR_FIFO_DEPTH), \ + ((alt_u32 )resp_if##_DESCRIPTOR_FIFO_DEPTH * 2), \ + ((void *) 0x0), \ + ((void *) 0x0), \ + ((alt_u32) 0x0), \ + ((alt_u8) csr_if##_BURST_ENABLE), \ + ((alt_u8) csr_if##_BURST_WRAPPING_SUPPORT), \ + ((alt_u32) csr_if##_DATA_FIFO_DEPTH), \ + ((alt_u32) csr_if##_DATA_WIDTH), \ + ((alt_u32) csr_if##_MAX_BURST_COUNT), \ + ((alt_u32) csr_if##_MAX_BYTE), \ + ((alt_u64) csr_if##_MAX_STRIDE), \ + ((alt_u8) csr_if##_PROGRAMMABLE_BURST_ENABLE), \ + ((alt_u8) csr_if##_STRIDE_ENABLE), \ + csr_if##_TRANSFER_TYPE, \ + ((alt_u8) csr_if##_ENHANCED_FEATURES), \ + ((alt_u8) csr_if##_RESPONSE_PORT), \ + ((alt_u8) csr_if##_PREFETCHER_ENABLE) \ +}; + +#define ALTERA_MSGDMA_CSR_DESCRIPTOR_SLAVE_INSTANCE(name, csr_if, desc_if, dev) \ +static alt_msgdma_dev dev = \ +{ \ + ALT_LLIST_ENTRY, \ + name##_CSR_NAME, \ + ((alt_u32 *)(csr_if##_BASE)), \ + ((alt_u32 *)(desc_if##_BASE)), \ + ((alt_u32 *)(0)), \ + ((alt_u32 *)(0)), \ + ((alt_u32 )name##_CSR_IRQ_INTERRUPT_CONTROLLER_ID), \ + ((alt_u32 )name##_CSR_IRQ), \ + ((alt_u32 )desc_if##_DESCRIPTOR_FIFO_DEPTH), \ + ((alt_u32) 0x0), \ + ((void *) 0x0), \ + ((void *) 0x0), \ + ((alt_u32) 0x0), \ + ((alt_u8) csr_if##_BURST_ENABLE), \ + ((alt_u8) csr_if##_BURST_WRAPPING_SUPPORT), \ + ((alt_u32) csr_if##_DATA_FIFO_DEPTH), \ + ((alt_u32) csr_if##_DATA_WIDTH), \ + ((alt_u32) csr_if##_MAX_BURST_COUNT), \ + ((alt_u32) csr_if##_MAX_BYTE), \ + ((alt_u64) csr_if##_MAX_STRIDE), \ + ((alt_u8) csr_if##_PROGRAMMABLE_BURST_ENABLE), \ + ((alt_u8) csr_if##_STRIDE_ENABLE), \ + csr_if##_TRANSFER_TYPE, \ + ((alt_u8) csr_if##_ENHANCED_FEATURES), \ + ((alt_u8) csr_if##_RESPONSE_PORT), \ + ((alt_u8) csr_if##_PREFETCHER_ENABLE) \ +}; + +/* + * New Interface for Prefetcher 15/6/2015. + */ +#define ALTERA_MSGDMA_CSR_PREFETCHER_CSR_INSTANCE(name, csr_if, pref_if, dev) \ +static alt_msgdma_dev dev = \ +{ \ + ALT_LLIST_ENTRY, \ + name##_CSR_NAME, \ + ((alt_u32 *)(csr_if##_BASE)), \ + ((alt_u32 *)(0)), \ + ((alt_u32 *)(0)), \ + ((alt_u32 *)(pref_if##_BASE)), \ + ((alt_u32 )name##_PREFETCHER_CSR_IRQ_INTERRUPT_CONTROLLER_ID), \ + ((alt_u32 )name##_PREFETCHER_CSR_IRQ), \ + ((alt_u32 )(0)), \ + ((alt_u32) 0x0), \ + ((void *) 0x0), \ + ((void *) 0x0), \ + ((alt_u32) 0x0), \ + ((alt_u8) csr_if##_BURST_ENABLE), \ + ((alt_u8) csr_if##_BURST_WRAPPING_SUPPORT), \ + ((alt_u32) csr_if##_DATA_FIFO_DEPTH), \ + ((alt_u32) csr_if##_DATA_WIDTH), \ + ((alt_u32) csr_if##_MAX_BURST_COUNT), \ + ((alt_u32) csr_if##_MAX_BYTE), \ + ((alt_u64) csr_if##_MAX_STRIDE), \ + ((alt_u8) csr_if##_PROGRAMMABLE_BURST_ENABLE), \ + ((alt_u8) csr_if##_STRIDE_ENABLE), \ + csr_if##_TRANSFER_TYPE, \ + ((alt_u8) csr_if##_ENHANCED_FEATURES), \ + ((alt_u8) csr_if##_RESPONSE_PORT), \ + ((alt_u8) csr_if##_PREFETCHER_ENABLE) \ +}; + + +/* + * The macro ALTERA_MSGDMA_INIT is called by the auto-generated function + * alt_sys_init() to initialize a given device instance. + */ +#define ALTERA_MSGDMA_INIT(name, dev) \ + alt_msgdma_init(&dev, dev.irq_controller_ID, dev.irq_ID); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALTERA_MSGDMA_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_csr_regs.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_csr_regs.h new file mode 100644 index 0000000..bd30d8b --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_csr_regs.h @@ -0,0 +1,175 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2014 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#ifndef ALTERA_MSGDMA_CSR_REGS_H_ +#define ALTERA_MSGDMA_CSR_REGS_H_ + +#include "io.h" +/* + Enhanced features off: + + Bytes Access Type Description + ----- ----------- ----------- + 0-3 R/Clr Status(1) + 4-7 R/W Control(2) + 8-12 R Descriptor Fill Level(write fill level[15:0], read + fill level[15:0]) + 13-15 R Response Fill Level[15:0] + 16-31 N/A + + + Enhanced features on: + + Bytes Access Type Description + ----- ----------- ----------- + 0-3 R/Clr Status(1) + 4-7 R/W Control(2) + 8-12 R Descriptor Fill Level (write fill level[15:0], read + fill level[15:0]) + 13-15 R Response Fill Level[15:0] + 16-20 R Sequence Number (write sequence number[15:0], read + sequence number[15:0]) + 21-31 N/A + + (1) Writing a '1' to the interrupt bit of the status register clears the + interrupt bit (when applicable), all other bits are unaffected by writes. + (2) Writing to the software reset bit will clear the entire register + (as well as all the registers for the entire msgdma). + + Status Register: + + Bits Description + ---- ----------- + 0 Busy + 1 Descriptor Buffer Empty + 2 Descriptor Buffer Full + 3 Response Buffer Empty + 4 Response Buffer Full + 5 Stop State + 6 Reset State + 7 Stopped on Error + 8 Stopped on Early Termination + 9 IRQ + 10-31 + + Control Register: + + Bits Description + ---- ----------- + 0 Stop (will also be set if a stop on error/early termination + condition occurs) + 1 Software Reset + 2 Stop on Error + 3 Stop on Early Termination + 4 Global Interrupt Enable Mask + 5 Stop dispatcher (stops the dispatcher from issuing more read/write + commands) + 6-31 +*/ + + + +#define ALTERA_MSGDMA_CSR_STATUS_REG 0x0 +#define ALTERA_MSGDMA_CSR_CONTROL_REG 0x4 +#define ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL_REG 0x8 +#define ALTERA_MSGDMA_CSR_RESPONSE_FILL_LEVEL_REG 0xC +/* this register only exists when the enhanced features are enabled */ +#define ALTERA_MSGDMA_CSR_SEQUENCE_NUMBER_REG 0x10 + + +/* masks for the status register bits */ +#define ALTERA_MSGDMA_CSR_BUSY_MASK 1 +#define ALTERA_MSGDMA_CSR_BUSY_OFFSET 0 +#define ALTERA_MSGDMA_CSR_DESCRIPTOR_BUFFER_EMPTY_MASK (1 << 1) +#define ALTERA_MSGDMA_CSR_DESCRIPTOR_BUFFER_EMPTY_OFFSET 1 +#define ALTERA_MSGDMA_CSR_DESCRIPTOR_BUFFER_FULL_MASK (1 << 2) +#define ALTERA_MSGDMA_CSR_DESCRIPTOR_BUFFER_FULL_OFFSET 2 +#define ALTERA_MSGDMA_CSR_RESPONSE_BUFFER_EMPTY_MASK (1 << 3) +#define ALTERA_MSGDMA_CSR_RESPONSE_BUFFER_EMPTY_OFFSET 3 +#define ALTERA_MSGDMA_CSR_RESPONSE_BUFFER_FULL_MASK (1 << 4) +#define ALTERA_MSGDMA_CSR_RESPONSE_BUFFER_FULL_OFFSET 4 +#define ALTERA_MSGDMA_CSR_STOP_STATE_MASK (1 << 5) +#define ALTERA_MSGDMA_CSR_STOP_STATE_OFFSET 5 +#define ALTERA_MSGDMA_CSR_RESET_STATE_MASK (1 << 6) +#define ALTERA_MSGDMA_CSR_RESET_STATE_OFFSET 6 +#define ALTERA_MSGDMA_CSR_STOPPED_ON_ERROR_MASK (1 << 7) +#define ALTERA_MSGDMA_CSR_STOPPED_ON_ERROR_OFFSET 7 +#define ALTERA_MSGDMA_CSR_STOPPED_ON_EARLY_TERMINATION_MASK (1 << 8) +#define ALTERA_MSGDMA_CSR_STOPPED_ON_EARLY_TERMINATION_OFFSET 8 +#define ALTERA_MSGDMA_CSR_IRQ_SET_MASK (1 << 9) +#define ALTERA_MSGDMA_CSR_IRQ_SET_OFFSET 9 + +/* masks for the control register bits */ +#define ALTERA_MSGDMA_CSR_STOP_MASK 1 +#define ALTERA_MSGDMA_CSR_STOP_OFFSET 0 +#define ALTERA_MSGDMA_CSR_RESET_MASK (1 << 1) +#define ALTERA_MSGDMA_CSR_RESET_OFFSET 1 +#define ALTERA_MSGDMA_CSR_STOP_ON_ERROR_MASK (1 << 2) +#define ALTERA_MSGDMA_CSR_STOP_ON_ERROR_OFFSET 2 +#define ALTERA_MSGDMA_CSR_STOP_ON_EARLY_TERMINATION_MASK (1 << 3) +#define ALTERA_MSGDMA_CSR_STOP_ON_EARLY_TERMINATION_OFFSET 3 +#define ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK (1 << 4) +#define ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_OFFSET 4 +#define ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK (1 << 5) +#define ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_OFFSET 5 + +/* masks for the FIFO fill levels and sequence number */ +#define ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_MASK 0xFFFF +#define ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_OFFSET 0 +#define ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_MASK 0xFFFF0000 +#define ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_OFFSET 16 +#define ALTERA_MSGDMA_CSR_RESPONSE_FILL_LEVEL_MASK 0xFFFF +#define ALTERA_MSGDMA_CSR_RESPONSE_FILL_LEVEL_OFFSET 0 +#define ALTERA_MSGDMA_CSR_READ_SEQUENCE_NUMBER_MASK 0xFFFF +#define ALTERA_MSGDMA_CSR_READ_SEQUENCE_NUMBER_OFFSET 0 +#define ALTERA_MSGDMA_CSR_WRITE_SEQUENCE_NUMBER_MASK 0xFFFF0000 +#define ALTERA_MSGDMA_CSR_WRITE_SEQUENCE_NUMBER_OFFSET 16 + + +/* read/write macros for each 32 bit register of the CSR port */ +#define IOWR_ALTERA_MSGDMA_CSR_STATUS(base, data) \ + IOWR_32DIRECT(base, ALTERA_MSGDMA_CSR_STATUS_REG, data) +#define IOWR_ALTERA_MSGDMA_CSR_CONTROL(base, data) \ + IOWR_32DIRECT(base, ALTERA_MSGDMA_CSR_CONTROL_REG, data) +#define IORD_ALTERA_MSGDMA_CSR_STATUS(base) \ + IORD_32DIRECT(base, ALTERA_MSGDMA_CSR_STATUS_REG) +#define IORD_ALTERA_MSGDMA_CSR_CONTROL(base) \ + IORD_32DIRECT(base, ALTERA_MSGDMA_CSR_CONTROL_REG) +#define IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(base) \ + IORD_32DIRECT(base, ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL_REG) +#define IORD_ALTERA_MSGDMA_CSR_RESPONSE_FILL_LEVEL(base) \ + IORD_32DIRECT(base, ALTERA_MSGDMA_CSR_RESPONSE_FILL_LEVEL_REG) +#define IORD_ALTERA_MSGDMA_CSR_SEQUENCE_NUMBER(base) \ + IORD_32DIRECT(base, ALTERA_MSGDMA_CSR_SEQUENCE_NUMBER_REG) + + + +#endif /*ALTERA_MSGDMA_ALTERA_MSGDMA_CSR_REGS_H_*/ diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_descriptor_regs.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_descriptor_regs.h new file mode 100644 index 0000000..21b1c31 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_descriptor_regs.h @@ -0,0 +1,163 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2014 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#ifndef ALTERA_MSGDMA_DESCRIPTOR_REGS_H_ +#define ALTERA_MSGDMA_DESCRIPTOR_REGS_H_ + +#include "io.h" + +/* + Descriptor formats: + + Standard Format: + + Offset | 3 2 1 0 + ------------------------------------------------------------------------------ + 0x0 | Read Address[31..0] + 0x4 | Write Address[31..0] + 0x8 | Length[31..0] + 0xC | Control[31..0] + + Extended Format: + +Offset| 3 2 1 0 + ------------------------------------------------------------------------------ + 0x0 | Read Address[31..0] + 0x4 | Write Address[31..0] + 0x8 | Length[31..0] + 0xC |Write Burst Count[7..0] | Read Burst Count[7..0] | Sequence Number[15..0] + 0x10 | Write Stride[15..0] | Read Stride[15..0] + 0x14 | Read Address[63..32] + 0x18 | Write Address[63..32] + 0x1C | Control[31..0] + + Note: The control register moves from offset 0xC to 0x1C depending on the + format used + +*/ + + + + +#define ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS_REG 0x0 +#define ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS_REG 0x4 +#define ALTERA_MSGDMA_DESCRIPTOR_LENGTH_REG 0x8 +#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_STANDARD_REG 0xC +#define ALTERA_MSGDMA_DESCRIPTOR_SEQUENCE_NUMBER_REG 0xC +#define ALTERA_MSGDMA_DESCRIPTOR_READ_BURST_REG 0xE +#define ALTERA_MSGDMA_DESCRIPTOR_WRITE_BURST_REG 0xF +#define ALTERA_MSGDMA_DESCRIPTOR_READ_STRIDE_REG 0x10 +#define ALTERA_MSGDMA_DESCRIPTOR_WRITE_STRIDE_REG 0x12 +#define ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS_HIGH_REG 0x14 +#define ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS_HIGH_REG 0x18 +#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_ENHANCED_REG 0x1C + + +/* masks and offsets for the sequence number and programmable burst counts */ +#define ALTERA_MSGDMA_DESCRIPTOR_SEQUENCE_NUMBER_MASK 0xFFFF +#define ALTERA_MSGDMA_DESCRIPTOR_SEQUENCE_NUMBER_OFFSET 0 +#define ALTERA_MSGDMA_DESCRIPTOR_READ_BURST_COUNT_MASK 0x00FF0000 +#define ALTERA_MSGDMA_DESCRIPTOR_READ_BURST_COUNT_OFFSET 16 +#define ALTERA_MSGDMA_DESCRIPTOR_WRITE_BURST_COUNT_MASK 0xFF000000 +#define ALTERA_MSGDMA_DESCRIPTOR_WRITE_BURST_COUNT_OFFSET 24 + + +/* masks and offsets for the read and write strides */ +#define ALTERA_MSGDMA_DESCRIPTOR_READ_STRIDE_MASK 0xFFFF +#define ALTERA_MSGDMA_DESCRIPTOR_READ_STRIDE_OFFSET 0 +#define ALTERA_MSGDMA_DESCRIPTOR_WRITE_STRIDE_MASK 0xFFFF0000 +#define ALTERA_MSGDMA_DESCRIPTOR_WRITE_STRIDE_OFFSET 16 + + +/* masks and offsets for the bits in the descriptor control field */ +#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_TRANSMIT_CHANNEL_MASK 0xFF +#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_TRANSMIT_CHANNEL_OFFSET 0 +#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GENERATE_SOP_MASK (1 << 8) +#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GENERATE_SOP_OFFSET 8 +#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MASK (1 << 9) +#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_OFFSET 9 +#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_PARK_READS_MASK (1 << 10) +#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_PARK_READS_OFFSET 10 +#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_PARK_WRITES_MASK (1 << 11) +#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_PARK_WRITES_OFFSET 11 +#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_END_ON_EOP_MASK (1 << 12) +#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_END_ON_EOP_OFFSET 12 +#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_TRANSFER_COMPLETE_IRQ_MASK (1 << 14) +#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_TRANSFER_COMPLETE_IRQ_OFFSET 14 +#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_EARLY_TERMINATION_IRQ_MASK (1 << 15) +#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_EARLY_TERMINATION_IRQ_OFFSET 15 +/* the read master will use this as the transmit error, the dispatcher will use +this to generate an interrupt if any of the error bits are asserted by the +write master */ +#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_ERROR_IRQ_MASK (0xFF << 16) +#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_ERROR_IRQ_OFFSET 16 +#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_EARLY_DONE_ENABLE_MASK (1 << 24) +#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_EARLY_DONE_ENABLE_OFFSET 24 +/* at a minimum you always have to write '1' to this bit as it commits the +descriptor to the dispatcher */ +#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK (1 << 31) +#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_OFFSET 31 + +/* Each register is byte lane accessible so the some of the values that are + * less than 32 bits wide are written to according to the field width. + */ +#define IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS(base, data) \ + IOWR_32DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS_REG, data) +#define IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS(base, data) \ + IOWR_32DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS_REG, data) +#define IOWR_ALTERA_MSGDMA_DESCRIPTOR_LENGTH(base, data) \ + IOWR_32DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_LENGTH_REG, data) +/* this pushes the descriptor into the read/write FIFOs when standard descriptors +are used */ +#define IOWR_ALTERA_MSGDMA_DESCRIPTOR_CONTROL_STANDARD(base, data) \ + IOWR_32DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_CONTROL_STANDARD_REG, data) +#define IOWR_ALTERA_MSGDMA_DESCRIPTOR_SEQUENCE_NUMBER(base, data) \ + IOWR_16DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_SEQUENCE_NUMBER_REG, data) +#define IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_BURST(base, data) \ + IOWR_8DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_READ_BURST_REG, data) +#define IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_BURST(base, data) \ + IOWR_8DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_WRITE_BURST_REG, data) +#define IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_STRIDE(base, data) \ + IOWR_16DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_READ_STRIDE_REG, data) +#define IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_STRIDE(base, data) \ + IOWR_16DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_WRITE_STRIDE_REG, data) +#define IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS_HIGH(base, data) \ + IOWR_32DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS_HIGH_REG, data) +#define IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS_HIGH(base, data) \ + IOWR_32DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS_HIGH_REG, data) +/* this pushes the descriptor into the read/write FIFOs when the extended +descriptors are used */ +#define IOWR_ALTERA_MSGDMA_DESCRIPTOR_CONTROL_ENHANCED(base, data) \ + IOWR_32DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_CONTROL_ENHANCED_REG, data) + + + +#endif /*ALTERA_MSGDMA_ALTERA_MSGDMA_DESCRIPTOR_REGS_H_*/ diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_prefetcher_regs.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_prefetcher_regs.h new file mode 100644 index 0000000..49d0815 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_prefetcher_regs.h @@ -0,0 +1,292 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2015 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#ifndef ALT_MSGDMA_PREFETCHER_REGS_H_ +#define ALT_MSGDMA_PREFETCHER_REGS_H_ + +#include "io.h" + +/* + MSGDMA Prefetcher core is an additional micro core to existing MSGDMA core which + already consists of dispatcher, read master and write master micro core. Prefetcher + core provides functionality to fetch a series of descriptors from memory that + describes the required data transfers before pass them to dispatcher core for data + transfer execution. +*/ + + +/* + * Component : MSGDMA PREFETCHER + * + */ +#define ALT_MSGDMA_PREFETCHER_CONTROL_OFST 0x00 +#define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_OFST 0x04 +#define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_OFST 0x08 +#define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ_OFST 0x0C +#define ALT_MSGDMA_PREFETCHER_STATUS_OFST 0x10 + +/* + * New MSGDMA PREFETCHER Descriptor fields. These are not prefetcher registers + * they are in the prefetcher descriptor structs + */ +/* The mask used to set the ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW value. */ +#define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET_MASK (1 << 30) +/* The mask used to clear the ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW value. */ +#define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_CLR_MASK 0xBFFFFFFF +/* The bit offset of the ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW field. */ +#define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_BIT_OFFSET 30 +/* Extracts the ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN field value from a register. */ +#define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN register field value suitable for setting the register. */ +#define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET(value) (((value) << 30) & 0x40000000) + +/* + * Register : control + * + * The control register has two defined bits. + * + * DESC_POLL_EN and RUN . + * + * Detailed description available in their individual bitfields + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [0] | R/W | 0x0 | RUN + * [1] | R/W | 0x0 | DESC_POLL_EN + * [2] | R/W1S | 0x0 | RESET_PREFETCHER + * [3] | R/W | 0x0 | GLOBAL_INTR_EN_MASK + * [4] | R/W | 0x0 | PARK_MODE + * [31:5] | R | 0x0 | RESERVED + * + */ + +/* bits making up the "control" register */ + +/* the RUN bit field in the control register */ +/* The mask used to set the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_RUN_SET_MASK 0x1 +/* The mask used to clear the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_RUN_CLR_MASK 0xFFFFFFFE +/* The bit offset of the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_RUN_BIT_OFFSET 0 +/* Extracts the ALT_MSGDMA_PREFETCHER_CTRL_RUN field value from a register. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_RUN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value suitable for setting the register. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_RUN_SET(value) (((value) << 0) & 0x00000001) + +/* the DESC_POLL_EN bit field in the control register */ +/* The mask used to set the ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN register field value. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN_MASK 0x2 +/* The mask used to clear the ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN register field value. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN_CLR_MASK 0xFFFFFFFD +/* The bit offset of the ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN register field. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN_BIT_OFFSET 1 +/* Extracts the ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN field value from a register. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN register field value suitable for setting the register. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN_SET(value) (((value) << 1) & 0x00000002) + +/* the RESET_PREFETCHER bit field in the control register */ +/* The mask used to set the ALT_MSGDMA_PREFETCHER_CTRL_RESET register field value. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_RESET_SET_MASK 0x4 +/* The mask used to clear the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_RESET_CLR_MASK 0xFFFFFFFB +/* The bit offset of the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_RESET_BIT_OFFSET 2 +/* Extracts the ALT_MSGDMA_PREFETCHER_CTRL_RUN field value from a register. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_RESET_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value suitable for setting the register. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_RESET_SET(value) (((value) << 2) & 0x00000004) + +/* the GLOBAL_INTR_EN_MASK bit field in the control register */ +/* The mask used to set the ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_MASK register field value. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_SET_MASK 0x8 +/* The mask used to clear the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_CLR_MASK 0xFFFFFFF7 +/* The bit offset of the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_BIT_OFFSET 3 +/* Extracts the ALT_MSGDMA_PREFETCHER_CTRL_RUN field value from a register. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value suitable for setting the register. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_SET(value) (((value) << 3) & 0x00000008) + +/* the PARK_MODE bit field in the control register */ +/* The mask used to set the ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE register field value. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE_SET_MASK 0x10 +/* The mask used to clear the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE_CLR_MASK 0xFFFFFFEF +/* The bit offset of the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE_BIT_OFFSET 4 +/* Extracts the ALT_MSGDMA_PREFETCHER_CTRL_RUN field value from a register. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value suitable for setting the register. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE_SET(value) (((value) << 4) & 0x00000010) + +/* + * Registers : Next Descriptor Pointer Low/High + * + * The register has no bit fields, the 64 bits represent an address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | R/W | 0x0 | NEXT_PTR_ADDR_LOW + * [63:32]| R/W | 0x0 | NEXT_PTR_ADDR_HIGH + * + */ + +/* bits making up the "Next Descriptor Pointer " register */ + +/* the NEXT_PTR_ADDR_LOW bit field in the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW register */ +/* The mask used to set the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_REG register field value. */ +#define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_SET_MASK 0xFFFFFFFF +/* The mask used to clear the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_REG register field value. */ +#define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_CLR_MASK 0x0 +/* The bit offset of the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_REG register field. */ +#define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_BIT_OFFSET 0 +/* Extracts the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_REG field value from a register. */ +#define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_GET(value) (((value) & 0xFFFFFFFF) >> 0) +/* Produces a ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_REG register field value suitable for setting the register. */ +#define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_SET(value) (((value) << 0) & 0xFFFFFFFF) + +/* the NEXT_PTR_ADDR_HIGH bit field in the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH register */ +/* The mask used to set the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_REG register field value. */ +#define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_SET_MASK 0xFFFFFFFF +/* The mask used to clear the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_REG register field value. */ +#define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_CLR_MASK 0x0 +/* The bit offset of the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_REG register field. */ +#define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_BIT_OFFSET 0 +/* Extracts the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_REG field value from a register. */ +#define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_GET(value) (((value) & 0xFFFFFFFF) >> 0) +/* Produces a ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_REG register field value suitable for setting the register. */ +#define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_SET(value) (((value) << 0) & 0xFFFFFFFF) + + +/* + * Register : Descriptor Polling Frequency + * + * The Descriptor Polling Frequency register has one defined bit field. + * + * POLL_FREQ + * + * Detailed description available in their individual bitfields + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [15:0] | R/W | 0x0 | POLL_FREQ + * [31:16] | R | 0x0 | RESERVED + * + */ + +/* bits making up the "DESC_POLL_FREQ" register */ + +/* the POLL_FREQ bit field in the ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ register */ +/* The mask used to set the ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ register field value. */ +#define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ_SET_MASK 0xFFFF +/* The mask used to clear the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value. */ +#define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ_CLR_MASK 0xFFFF0000 +/* The bit offset of the ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ register field. */ +#define ALT_MSGDMA_PREFETCHER_CTRL_RUN_BIT_OFFSET 0 +/* Extracts the ALT_MSGDMA_PREFETCHER_CTRL_RUN field value from a register. */ +#define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ_GET(value) (((value) & 0x0000FFFF) >> 0) +/* Produces a ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value suitable for setting the register. */ +#define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ_SET(value) (((value) << 0) & 0x0000FFFF) + + +/* + * Register : Status + * + * The Status register has one defined bit field. + * + * IRQ + * + * Detailed description available in their individual bitfields + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [0] | R/W1C | 0x0 | IRQ + * [31:1] | R | 0x0 | RESERVED + * + */ + +/* bits making up the "STATUS" register */ + +/* the IRQ bit field in the ALT_MSGDMA_PREFETCHER_STATUS register */ +/* The mask used to set the ALT_MSGDMA_PREFETCHER_STATUS_IRQ register field value. */ +#define ALT_MSGDMA_PREFETCHER_STATUS_IRQ_SET_MASK 0x1 +/* The mask used to clear the ALT_MSGDMA_PREFETCHER_STATUS_IRQ register field value. */ +#define ALT_MSGDMA_PREFETCHER_STATUS_IRQ_CLR_MASK 0xFFFFFFFE +/* The bit offset of the ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ register field. */ +#define ALT_MSGDMA_PREFETCHER_STATUS_IRQ_BIT_OFFSET 0 +/* Extracts the ALT_MSGDMA_PREFETCHER_CTRL_RUN field value from a register. */ +#define ALT_MSGDMA_PREFETCHER_STATUS_IRQ_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value suitable for setting the register. */ +#define ALT_MSGDMA_PREFETCHER_STATUS_IRQ_SET(value) (((value) << 0) & 0x00000001) + + + +/*****************************************************************/ +/*** READ/WRITE macros for the MSGDMA PREFETCHER registers ***/ +/*****************************************************************/ +/* ALT_MSGDMA_PREFETCHER_CONTROL_REG */ +#define IORD_ALT_MSGDMA_PREFETCHER_CONTROL(base) \ + IORD_32DIRECT(base, ALT_MSGDMA_PREFETCHER_CONTROL_OFST) +#define IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(base, data) \ + IOWR_32DIRECT(base, ALT_MSGDMA_PREFETCHER_CONTROL_OFST, data) +/* ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_REG */ +#define IORD_ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW(base) \ + IORD_32DIRECT(base, ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_OFST) +#define IOWR_ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW(base, data) \ + IOWR_32DIRECT(base, ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_OFST, data) +/* ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_REG */ +#define IORD_ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH(base) \ + IORD_32DIRECT(base, ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_OFST) +#define IOWR_ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH(base, data) \ + IOWR_32DIRECT(base, ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_OFST, data) +/* ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLLING_FREQ_REG */ +#define IORD_ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLLING_FREQ(base) \ + IORD_32DIRECT(base, ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ_OFST) +#define IOWR_ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLLING_FREQ(base, data) \ + IOWR_32DIRECT(base, ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ_OFST, data) +/* ALT_MSGDMA_PREFETCHER_STATUS_REG */ +#define IORD_ALT_MSGDMA_PREFETCHER_STATUS(base) \ + IORD_32DIRECT(base, ALT_MSGDMA_PREFETCHER_STATUS_OFST) +#define IOWR_ALT_MSGDMA_PREFETCHER_STATUS(base, data) \ + IOWR_32DIRECT(base, ALT_MSGDMA_PREFETCHER_STATUS_OFST, data) + +#endif /*ALT_MSGDMA_PREFETCHER_REGS_H_*/ diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_response_regs.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_response_regs.h new file mode 100644 index 0000000..65424d6 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_response_regs.h @@ -0,0 +1,70 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2014 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#ifndef ALTERA_MSGDMA_RESPONSE_REGS_H_ +#define ALTERA_MSGDMA_RESPONSE_REGS_H_ + +#include "io.h" + +/* + The response slave port only carries the actual bytes transferred, + error, and early termination bits. Reading from the upper most byte + of the 2nd register pops the response FIFO. For proper FIFO popping + always read the actual bytes transferred followed by the error and early + termination bits using 'little endian' accesses. If a big endian + master accesses the response slave port make sure that address 0x7 is the + last byte lane access as it's the one that pops the reponse FIFO. + + If you use a pre-fetching descriptor master in front of the dispatcher + port then you do not need to access this response slave port. +*/ + + + +#define ALTERA_MSGDMA_RESPONSE_ACTUAL_BYTES_TRANSFERRED_REG 0x0 +#define ALTERA_MSGDMA_RESPONSE_ERRORS_REG 0x4 + +/* bits making up the "errors" register */ +#define ALTERA_MSGDMA_RESPONSE_ERROR_MASK 0xFF +#define ALTERA_MSGDMA_RESPONSE_ERROR_OFFSET 0 +#define ALTERA_MSGDMA_RESPONSE_EARLY_TERMINATION_MASK (1 << 8) +#define ALTERA_MSGDMA_RESPONSE_EARLY_TERMINATION_OFFSET 8 + + +/* read macros for each 32 bit register */ +#define IORD_ALTERA_MSGDMA_RESPONSE_ACTUAL_BYTES_TRANSFERRED(base) \ + IORD_32DIRECT(base, ALTERA_MSGDMA_RESPONSE_ACTUAL_BYTES_TRANSFERRED_REG) +/* this read pops the response FIFO */ +#define IORD_ALTERA_MSGDMA_RESPONSE_ERRORS_REG(base) \ + IORD_32DIRECT(base, ALTERA_MSGDMA_RESPONSE_ERRORS_REG) + + +#endif /*ALTERA_MSGDMA_RESPONSE_REGS_H_*/ diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_onchip_flash.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_onchip_flash.h new file mode 100644 index 0000000..0d915fc --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_onchip_flash.h @@ -0,0 +1,167 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2014 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALT_ONCHIP_FLASH_H__ +#define __ALT_ONCHIP_FLASH_H__ + +#include "alt_types.h" +#include "sys/alt_flash_dev.h" +#include "sys/alt_llist.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Getting started: + * Nios II Software Developer's Handbook (URL: http://www.altera.com/literature/lit-nio2.jsp) + * -> Section II. Hardware Abstraction Layer + * -> Chapter 6. Developing Programs Using the Hardware Abstraction Layer + * -> Using Flash Devices + */ + +/* + * Description of the flash + */ +typedef struct alt_onchip_flash_dev +{ + /* Flash common declaration */ + alt_flash_dev dev; + + /* IP specific information */ + int is_read_only; + void *csr_base; + int sector1_enabled; + int sector1_start_addr; + int sector1_end_addr; + int sector2_enabled; + int sector2_start_addr; + int sector2_end_addr; + int sector3_enabled; + int sector3_start_addr; + int sector3_end_addr; + int sector4_enabled; + int sector4_start_addr; + int sector4_end_addr; + int sector5_enabled; + int sector5_start_addr; + int sector5_end_addr; + int page_size; +} alt_onchip_flash_dev; + +/* +* Macros used by alt_sys_init.c +* +*/ +#define ALTERA_ONCHIP_FLASH_DATA_CSR_INSTANCE(name, data, csr, dev) \ +static alt_onchip_flash_dev dev = \ +{ \ + { \ + ALT_LLIST_ENTRY, \ + data##_NAME, \ + NULL, \ + NULL, \ + alt_onchip_flash_write, \ + alt_onchip_flash_read, \ + alt_onchip_flash_get_info, \ + alt_onchip_flash_erase_block, \ + alt_onchip_flash_write_block, \ + ((void*)(data##_BASE)), \ + ((int)(data##_SPAN)), \ + 0 \ + }, \ + data##_READ_ONLY_MODE, \ + ((void*)(csr##_BASE)), \ + data##_SECTOR1_ENABLED, \ + data##_SECTOR1_START_ADDR, \ + data##_SECTOR1_END_ADDR, \ + data##_SECTOR2_ENABLED, \ + data##_SECTOR2_START_ADDR, \ + data##_SECTOR2_END_ADDR, \ + data##_SECTOR3_ENABLED, \ + data##_SECTOR3_START_ADDR, \ + data##_SECTOR3_END_ADDR, \ + data##_SECTOR4_ENABLED, \ + data##_SECTOR4_START_ADDR, \ + data##_SECTOR4_END_ADDR, \ + data##_SECTOR5_ENABLED, \ + data##_SECTOR5_START_ADDR, \ + data##_SECTOR5_END_ADDR, \ + data##_BYTES_PER_PAGE \ +} + +/* + Public API + + Refer to Using Flash Devices in the + Developing Programs Using the Hardware Abstraction Layer chapter + of the Nios II Software Developer's Handbook. + +*/ + +int alt_onchip_flash_read(alt_flash_dev *flash_info, int offset, void *dest_addr, int length); + +int alt_onchip_flash_get_info(alt_flash_fd *fd, flash_region **info, int *number_of_regions); + +int alt_onchip_flash_erase_block(alt_flash_dev *flash_info, int block_offset); + +int alt_onchip_flash_write_block(alt_flash_dev *flash_info, int block_offset, int data_offset, const void *data, int length); + +int alt_onchip_flash_write(alt_flash_dev *flash_info, int offset, const void *src_addr, int length); + +/* + * Initialization function + */ +extern void altera_onchip_flash_init(alt_onchip_flash_dev *dev); + +/* + * alt_sys_init.c will call this macro automatically + */ +#define ALTERA_ONCHIP_FLASH_INIT(name, dev) { altera_onchip_flash_init(&dev); } + + +/* + Private API + + Helper functions used by Public API functions. +*/ + +int alt_onchip_flash_poll_for_status_to_go_idle(alt_onchip_flash_dev *flash); + +int alt_onchip_flash_poll_for_status_erase_passed(alt_onchip_flash_dev* flash); + +int alt_onchip_flash_poll_for_status_write_passed(alt_onchip_flash_dev* flash); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_ONCHIP_FLASH_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_onchip_flash_regs.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_onchip_flash_regs.h new file mode 100644 index 0000000..6006e94 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_onchip_flash_regs.h @@ -0,0 +1,241 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2014 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_ONCHIP_FLASH_REGS_H__ +#define __ALTERA_ONCHIP_FLASH_REGS_H__ + +#include + +/* + * Status Register +*/ +#define ALTERA_ONCHIP_FLASH_STATUS_REG 0 +#define ALTERA_ONCHIP_FLASH_STATUS_MSK (0x00007FFF) + +#define ALTERA_ONCHIP_FLASH_STATUS_BUSY_MSK (0x00000003) +#define ALTERA_ONCHIP_FLASH_STATUS_BUSY_IDLE (0x00000000) +#define ALTERA_ONCHIP_FLASH_STATUS_BUSY_ERASE (0x00000001) +#define ALTERA_ONCHIP_FLASH_STATUS_BUSY_WRITE (0x00000002) +#define ALTERA_ONCHIP_FLASH_STATUS_BUSY_READ (0x00000003) + +#define ALTERA_ONCHIP_FLASH_STATUS_READ_MSK (0x00000004) +#define ALTERA_ONCHIP_FLASH_STATUS_READ_PASSED (0x00000004) +#define ALTERA_ONCHIP_FLASH_STATUS_READ_FAILED (0x00000000) + +#define ALTERA_ONCHIP_FLASH_STATUS_WRITE_MSK (0x00000008) +#define ALTERA_ONCHIP_FLASH_STATUS_WRITE_PASSED (0x00000008) +#define ALTERA_ONCHIP_FLASH_STATUS_WRITE_FAILED (0x00000000) + +#define ALTERA_ONCHIP_FLASH_STATUS_ERASE_MSK (0x00000010) +#define ALTERA_ONCHIP_FLASH_STATUS_ERASE_PASSED (0x00000010) +#define ALTERA_ONCHIP_FLASH_STATUS_ERASE_FAILED (0x00000000) + +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR1_MSK (0x00000020) +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR1_UNAVAILABLE (0x00000020) +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR1_AVAILABLE (0x00000000) + +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR2_MSK (0x00000040) +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR2_UNAVAILABLE (0x00000040) +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR2_AVAILABLE (0x00000000) + +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR3_MSK (0x00000080) +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR3_UNAVAILABLE (0x00000080) +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR3_AVAILABLE (0x00000000) + +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR4_MSK (0x00000100) +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR4_UNAVAILABLE (0x00000100) +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR4_AVAILABLE (0x00000000) + +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR5_MSK (0x00000200) +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR5_UNAVAILABLE (0x00000200) +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR5_AVAILABLE (0x00000000) + +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR1_READONLY_MSK (0x00000400) +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR1_READONLY (0x00000400) +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR1_READWRITE (0x00000000) + +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR2_READONLY_MSK (0x00000800) +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR2_READONLY (0x00000800) +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR2_READWRITE (0x00000000) + +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR3_READONLY_MSK (0x00001000) +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR3_READONLY (0x00001000) +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR3_READWRITE (0x00000000) + +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR4_READONLY_MSK (0x00002000) +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR4_READONLY (0x00002000) +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR4_READWRITE (0x00000000) + +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR5_READONLY_MSK (0x00004000) +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR5_READONLY (0x00004000) +#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR5_READWRITE (0x00000000) + +#define IOADDR_ALTERA_ONCHIP_FLASH_STATUS(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_ONCHIP_FLASH_STATUS_REG) + +#define IORD_ALTERA_ONCHIP_FLASH_STATUS(base) \ + IORD(base, ALTERA_ONCHIP_FLASH_STATUS_REG) + +#define IOWR_ALTERA_ONCHIP_FLASH_STATUS(base, data) \ + IOWR(base, ALTERA_ONCHIP_FLASH_STATUS_REG, data) + + +/* + * Control Register +*/ +#define ALTERA_ONCHIP_FLASH_CONTROL_REG 1 +#define ALTERA_ONCHIP_FLASH_CONTROL_MSK (0xCFFFFFFF) + +#define ALTERA_ONCHIP_FLASH_CONTROL_PAGE_ERASE_MSK (0x000FFFFF) +#define ALTERA_ONCHIP_FLASH_CONTROL_PAGE_ERASE_NOT_SET (0x000FFFFF) + +#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_MSK (0x00700000) +#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_SECTOR1 (0x00100000) +#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_SECTOR2 (0x00200000) +#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_SECTOR3 (0x00300000) +#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_SECTOR4 (0x00400000) +#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_SECTOR5 (0x00500000) +#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_NOT_SET (0x00700000) + +#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR1_WRITE_PROTECT_MSK (0x00800000) +#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR1_WRITE_ENABLE (0x00000000) +#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR1_WRITE_DISABLE (0x00800000) + +#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR2_WRITE_PROTECT_MSK (0x01000000) +#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR2_WRITE_ENABLE (0x00000000) +#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR2_WRITE_DISABLE (0x01000000) + +#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR3_WRITE_PROTECT_MSK (0x02000000) +#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR3_WRITE_ENABLE (0x00000000) +#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR3_WRITE_DISABLE (0x02000000) + +#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR4_WRITE_PROTECT_MSK (0x04000000) +#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR4_WRITE_ENABLE (0x00000000) +#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR4_WRITE_DISABLE (0x04000000) + +#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR5_WRITE_PROTECT_MSK (0x08000000) +#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR5_WRITE_ENABLE (0x00000000) +#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR5_WRITE_DISABLE (0x08000000) + +#define ALTERA_ONCHIP_FLASH_CONTROL_ALLSECTOR_WRITE_PROTECT_MSK (0x0F800000) +#define ALTERA_ONCHIP_FLASH_CONTROL_ALLSECTOR_WRITE_ENABLE (0x00000000) +#define ALTERA_ONCHIP_FLASH_CONTROL_ALLSECTOR_WRITE_DISABLE (0x0F800000) + +#define ALTERA_ONCHIP_FLASH_CONTROL_ERASE_STATE_MSK (0xC0000000) +#define ALTERA_ONCHIP_FLASH_CONTROL_ERASE_STATE_IDLE (0x00000000) +#define ALTERA_ONCHIP_FLASH_CONTROL_ERASE_STATE_PENDING (0x40000000) +#define ALTERA_ONCHIP_FLASH_CONTROL_ERASE_STATE_BUSY (0x80000000) +#define ALTERA_ONCHIP_FLASH_CONTROL_ERASE_STATE_RSVD (0xC0000000) + +#define IOADDR_ALTERA_ONCHIP_FLASH_CONTROL(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_ONCHIP_FLASH_CONTROL_REG) + +#define IORD_ALTERA_ONCHIP_FLASH_CONTROL(base) \ + IORD(base, ALTERA_ONCHIP_FLASH_CONTROL_REG) + +#define IOWR_ALTERA_ONCHIP_FLASH_CONTROL(base, data) \ + IOWR(base, ALTERA_ONCHIP_FLASH_CONTROL_REG, data) + + +/* + * Constant value +*/ +#define ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE (32/8) +/* 0.7 sec time out */ +#define ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE 700000 + +/* + * Functional Macros +*/ + +/* Enable Write and Erase Operation */ +#define ALTERA_ONCHIP_FLASH_ENABLE_WRITE_AND_ERASE_OPERATION(base) \ + ( \ + IOWR_ALTERA_ONCHIP_FLASH_CONTROL((base), \ + (IORD_ALTERA_ONCHIP_FLASH_CONTROL((base)) \ + & \ + ~( \ + ALTERA_ONCHIP_FLASH_CONTROL_ALLSECTOR_WRITE_PROTECT_MSK | \ + ALTERA_ONCHIP_FLASH_CONTROL_PAGE_ERASE_MSK | \ + ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_MSK \ + ) \ + ) \ + | \ + ( \ + ALTERA_ONCHIP_FLASH_CONTROL_ALLSECTOR_WRITE_ENABLE | \ + ALTERA_ONCHIP_FLASH_CONTROL_PAGE_ERASE_NOT_SET | \ + ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_NOT_SET \ + ) \ + ) \ + ) + +/* Disable Write and Erase Operation */ +#define ALTERA_ONCHIP_FLASH_DISABLE_WRITE_AND_ERASE_OPERATION(base) \ + ( \ + IOWR_ALTERA_ONCHIP_FLASH_CONTROL((base), \ + (IORD_ALTERA_ONCHIP_FLASH_CONTROL((base)) \ + & \ + ~( \ + ALTERA_ONCHIP_FLASH_CONTROL_ALLSECTOR_WRITE_PROTECT_MSK | \ + ALTERA_ONCHIP_FLASH_CONTROL_PAGE_ERASE_MSK | \ + ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_MSK \ + ) \ + ) \ + | \ + ( \ + ALTERA_ONCHIP_FLASH_CONTROL_ALLSECTOR_WRITE_DISABLE | \ + ALTERA_ONCHIP_FLASH_CONTROL_PAGE_ERASE_NOT_SET | \ + ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_NOT_SET \ + ) \ + ) \ + ) + +/* Page Erase Operation */ +#define ALTERA_ONCHIP_FLASH_PAGE_ERASE(base, page_erase_block_address) \ + ( \ + IOWR_ALTERA_ONCHIP_FLASH_CONTROL((base), \ + (IORD_ALTERA_ONCHIP_FLASH_CONTROL((base)) \ + & \ + ~( \ + ALTERA_ONCHIP_FLASH_CONTROL_ALLSECTOR_WRITE_PROTECT_MSK | \ + ALTERA_ONCHIP_FLASH_CONTROL_PAGE_ERASE_MSK | \ + ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_MSK \ + ) \ + ) \ + | \ + ( \ + ALTERA_ONCHIP_FLASH_CONTROL_ALLSECTOR_WRITE_ENABLE | \ + (page_erase_block_address) | \ + ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_NOT_SET \ + ) \ + ) \ + ) + +#endif /* __ALTERA_ONCHIP_FLASH_REGS_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/iniche/altera_eth_tse_iniche.h b/FPGA_nios/hit_pat_bsp/drivers/inc/iniche/altera_eth_tse_iniche.h new file mode 100644 index 0000000..9d0a23b --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/inc/iniche/altera_eth_tse_iniche.h @@ -0,0 +1,250 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_ETH_TSE_INICHE_H__ +#define __ALTERA_ETH_TSE_INICHE_H__ + +#include "alt_iniche_dev.h" +#include "altera_eth_tse_regs.h" +#include "ins_tse_mac.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + + +/* System Constant Definition Used in the TSE Driver Code */ +#define ALTERA_TSE_PKT_INIT_LEN 1528 + +#define ALTERA_TSE_ADMIN_STATUS_DOWN 2 +#define ALTERA_TSE_ADMIN_STATUS_UP 1 +#define ALTERA_TSE_MAX_MTU_SIZE 1514 +#define ALTERA_TSE_MIN_MTU_SIZE 14 +#define ALTERA_TSE_HAL_ADDR_LEN 6 + + + +/******************************* + * + * Public API for TSE Driver + * + *******************************/ + + + /* @Function Description: TSE MAC Driver Open/Initialization routine + * @API TYPE: Public + * @Param p_dec pointer to TSE device instance + * @Return SUCCESS + */ + +error_t altera_eth_tse_init( + alt_iniche_dev *p_dev); + + +/* @Function Description - Closing the TSE MAC Driver Interface + * + * + * @API TYPE - Public + * @param iface index of the NET interface associated with the TSE MAC. + * @return SUCCESS + */ +int tse_mac_close(int iface); + + + +/* @Function Description - TSE transmit API to send data to the MAC + * + * + * @API TYPE - Public + * @param net - NET structure associated with the TSE MAC instance + * @param data - pointer to the data payload + * @param data_bytes - number of bytes of the data payload to be sent to the MAC + * @return SUCCESS if success, else SEND_DROPPED, ENP_RESOURCE if error + * + */ +int tse_mac_raw_send(NET net, char * data, unsigned int data_bytes); + +/* @Function Description - TSE transmit API to send data to the MAC + * + * + * @API TYPE - Public + * @param pke - Packet containing data to send + * @return SUCCESS if success, else SEND_DROPPED, ENP_RESOURCE if error + * + */ +int tse_mac_pkt_send(PACKET pkt); + + +/******************************** + * + * Internal API for TSE Driver + * + *******************************/ + +/** @Function Description: TSE MAC Driver Open/Registration routine + * @API TYPE: Internal + * @Param index index of the NET structure associated with TSE instance + * @Return next index of NET + */ +int prep_tse_mac(int index, alt_tse_system_info *psys_info); + + + +/* @Function Description: TSE MAC Initialization routine. This function opens the + * device handle, configure the callback function and interrupts , + * for MSGDMA TX and MSGDMA RX block associated with the TSE MAC, + * Initialize the MAC Registers for the RX FIFO and TX FIFO + * threshold watermarks, initialize the tse device structure, + * set the MAC address of the device and enable the MAC + * + * @API TYPE: Internal + * @Param iface index of the NET structure associated with TSE instance + * @Return SUCCESS if ok, else ENP_RESOURCE, ENP_PARAM, ENP_LOGIC if error + */ +int tse_mac_init(int iface); + + + +/* @Function Description - TSE Driver MSGDMA RX ISR callback function + * + * + * @API TYPE - callback + * @param context - context of the TSE MAC instance + * @param intnum - temporary storage + * @return SUCCESS on success else ENP_LOGIC if error + */ +void tse_msgdmaRx_isr(void * context); + +/* @Function Description - TSE Driver MSGDMA TX ISR callback function + * + * + * @API TYPE - callback + * @param context - context of the TSE MAC instance + * @param intnum - temporary storage + * @return SUCCESS on success else ENP_LOGIC if error + */ +void tse_msgdmaTx_isr(void * context); + + +/* @Function Description - Init and setup MSGDMA RX Descriptor chain + * + * + * @API TYPE - Internal + * @return SUCCESS on success else ENP_NOBUFFER if error + */ +int tse_msgdma_read_init(ins_tse_info* tse_ptr); + + +/* @Function Description - Init and setup MSGDMA TX Descriptor chain + * + * + * @API TYPE - Internal + * @return SUCCESS on success else ENP_NOBUFFER if error + */ +int tse_msgdma_write_init(ins_tse_info* tse_ptr,unsigned int * ActualData,unsigned int len); + + +/* @Function Description - TSE Driver MSGDMA RX ISR callback function + * + * + * @API TYPE - callback internal function + * @return SUCCESS on success else ENP_NORESOURCE, ENP_NOBUFFER if error + */ +void tse_mac_rcv(ins_tse_info* tse_ptr); + +/* @Function Description - allocate rx descriptor chain memory + * + * + * @API TYPE - callback internal function + * @return SUCCESS on success else 1 if error + */ +int allocate_rx_descriptor_chain(ins_tse_info* tse_ptr); + + +int tse_mac_stats(void * pio, int iface); + + +/********************************** + * + * TSE Driver Structure Definition + * + **********************************/ + +typedef struct +{ + alt_iniche_dev dev; +} altera_eth_tse_if; + +typedef struct +{ + alt_iniche_dev *p_dev; + alt_u32 hw_mac_base_addr; + alt_u8 hw_channel_number; +} alt_tse_iniche_dev_driver_data; + +#define ALTERA_ETH_TSE_INSTANCE(inst_name, dev_inst) \ +altera_eth_tse_if dev_inst##_if[8]; \ +char *dev_inst##_name = inst_name##_NAME; + +#define ALTERA_ETH_TSE_INIT(inst_name, dev_inst) \ +{ \ + extern alt_u8 number_of_tse_mac; \ + extern alt_tse_iniche_dev_driver_data tse_iniche_dev_driver_data[MAXNETS]; \ + \ + int dev_inst##_loop_control = 0; \ + int dev_inst##_number_of_channel = inst_name##_NUMBER_OF_CHANNEL; \ + if(dev_inst##_number_of_channel < 1) { \ + dev_inst##_number_of_channel = 1; \ + } \ + \ + for(dev_inst##_loop_control = 0; dev_inst##_loop_control < dev_inst##_number_of_channel; dev_inst##_loop_control++) { \ + dev_inst##_if[dev_inst##_loop_control].dev.llist.next = 0; \ + dev_inst##_if[dev_inst##_loop_control].dev.llist.previous = 0; \ + dev_inst##_if[dev_inst##_loop_control].dev.name = dev_inst##_name; \ + dev_inst##_if[dev_inst##_loop_control].dev.init_func = altera_eth_tse_init; \ + \ + alt_iniche_dev_reg(&(dev_inst##_if[dev_inst##_loop_control].dev)); \ + tse_iniche_dev_driver_data[number_of_tse_mac].p_dev = &(dev_inst##_if[dev_inst##_loop_control].dev); \ + tse_iniche_dev_driver_data[number_of_tse_mac].hw_mac_base_addr = inst_name##_BASE; \ + tse_iniche_dev_driver_data[number_of_tse_mac].hw_channel_number = dev_inst##_loop_control; \ + number_of_tse_mac++; \ + } \ +} + +error_t altera_eth_tse_init( + alt_iniche_dev *p_dev); + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALTERA_ETH_TSE_INICHE_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/iniche/ins_tse_mac.h b/FPGA_nios/hit_pat_bsp/drivers/inc/iniche/ins_tse_mac.h new file mode 100644 index 0000000..4b6e01c --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/inc/iniche/ins_tse_mac.h @@ -0,0 +1,88 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef _ins_tse_regs_h_ +#define _ins_tse_regs_h_ + +#include "altera_msgdma.h" +#include "altera_msgdma_descriptor_regs.h" +#include "altera_msgdma_prefetcher_regs.h" +#include "altera_msgdma_csr_regs.h" +#include "altera_avalon_tse.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef ALT_INICHE +#include "ipport.h" +#include "tcpport.h" +#endif + +/* Base-Structure for all library functions */ +typedef struct{ + /* index number */ + int index; + + tse_mac_trans_info mi; /* MAC base driver data. */ + + /* driver specific */ + char mac_addr[8]; /* use 8 to word align */ + NET netp; /* pointer to Interniche NET struct */ + int txShift16OK; /* TX supports Shift16 */ + int rxShift16OK; /* RX supports Shift16 */ +/* Temporary variable to "protect" our transmit function - should be protected otherwise though */ + int sem; +/* Variable to store Channel number for Share Fifo System */ + int channel; + + // Location for the MSGDMA Descriptors + alt_msgdma_prefetcher_standard_descriptor *txdesc_list; + alt_msgdma_prefetcher_standard_descriptor *txdesc; + //The two lists are used to prepare one list while the other is executing + alt_msgdma_prefetcher_standard_descriptor *rxdesc_list[2]; + alt_msgdma_prefetcher_standard_descriptor *rxdesc[2]; + int rx_chain; + int rx_descriptor_index; + int tx_descriptor_index; + + // Pre-allocation of packet buffers for each RX descriptor + PACKET pkt_array_rx[2][ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE]; + + // Hardware location + void *tse; + +} ins_tse_info; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _ins_tse_regs_h_*/ diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_sysid_qsys.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_sysid_qsys.c new file mode 100644 index 0000000..3dfca88 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_sysid_qsys.c @@ -0,0 +1,82 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "altera_avalon_sysid_qsys.h" +#include "altera_avalon_sysid_qsys_regs.h" +#include "alt_types.h" +#include + +/* +* This component is special: there's only one of it. +* Therefore we can dispense with a bunch of complexity +* normally associated with components, such as specialized +* structs containing parameter info, and instead use that +* info by name directly out of system.h. A downside of this +* approach is that each time the system is regenerated, and +* system.h changes, this file must be recompiled. Fortunately +* this file is, and is likely to remain, quite small. +*/ +#include "system.h" + +#ifdef SYSID_BASE +/* +* return values: +* 0 if the hardware and software appear to be in sync +* 1 if software appears to be older than hardware +* -1 if hardware appears to be older than software +*/ + +alt_32 alt_avalon_sysid_qsys_test(void) +{ + /* Read the hardware-tag, aka value0, from the hardware. */ + alt_u32 hardware_id = IORD_ALTERA_AVALON_SYSID_QSYS_ID(SYSID_BASE); + + /* Read the time-of-generation, aka value1, from the hardware register. */ + alt_u32 hardware_timestamp = IORD_ALTERA_AVALON_SYSID_QSYS_TIMESTAMP(SYSID_BASE); + + /* Return 0 if the hardware and software appear to be in sync. */ + if ((SYSID_TIMESTAMP == hardware_timestamp) && (SYSID_ID == hardware_id)) + { + return 0; + } + + /* + * Return 1 if software appears to be older than hardware (that is, + * the value returned by the hardware is larger than that recorded by + * the generator function). + * If the hardware time happens to match the generator program's value + * (but the hardware tag, value0, doesn't match or 0 would have been + * returned above), return an arbitrary value, let's say -1. + */ + return ((alt_32)(hardware_timestamp - SYSID_TIMESTAMP)) > 0 ? 1 : -1; +} +#endif diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_timer_sc.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_timer_sc.c new file mode 100644 index 0000000..715723d --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_timer_sc.c @@ -0,0 +1,110 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/alt_alarm.h" +#include "sys/alt_irq.h" + +#include "altera_avalon_timer.h" +#include "altera_avalon_timer_regs.h" + +#include "alt_types.h" +#include "sys/alt_log_printf.h" + +/* + * alt_avalon_timer_sc_irq() is the interrupt handler used for the system + * clock. This is called periodically when a timer interrupt occurs. The + * function first clears the interrupt condition, and then calls the + * alt_tick() function to notify the system that a timer tick has occurred. + * + * alt_tick() increments the system tick count, and updates any registered + * alarms, see alt_tick.c for further details. + */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void alt_avalon_timer_sc_irq (void* base) +#else +static void alt_avalon_timer_sc_irq (void* base, alt_u32 id) +#endif +{ + alt_irq_context cpu_sr; + + /* clear the interrupt */ + IOWR_ALTERA_AVALON_TIMER_STATUS (base, 0); + + /* + * Dummy read to ensure IRQ is negated before the ISR returns. + * The control register is read because reading the status + * register has side-effects per the register map documentation. + */ + IORD_ALTERA_AVALON_TIMER_CONTROL (base); + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_SYS_CLK_HEARTBEAT(); + + /* + * Notify the system of a clock tick. disable interrupts + * during this time to safely support ISR preemption + */ + cpu_sr = alt_irq_disable_all(); + alt_tick (); + alt_irq_enable_all(cpu_sr); +} + +/* + * alt_avalon_timer_sc_init() is called to initialise the timer that will be + * used to provide the periodic system clock. This is called from the + * auto-generated alt_sys_init() function. + */ + +void alt_avalon_timer_sc_init (void* base, alt_u32 irq_controller_id, + alt_u32 irq, alt_u32 freq) +{ + /* set the system clock frequency */ + + alt_sysclk_init (freq); + + /* set to free running mode */ + + IOWR_ALTERA_AVALON_TIMER_CONTROL (base, + ALTERA_AVALON_TIMER_CONTROL_ITO_MSK | + ALTERA_AVALON_TIMER_CONTROL_CONT_MSK | + ALTERA_AVALON_TIMER_CONTROL_START_MSK); + + /* register the interrupt handler, and enable the interrupt */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_ic_isr_register(irq_controller_id, irq, alt_avalon_timer_sc_irq, + base, NULL); +#else + alt_irq_register (irq, base, alt_avalon_timer_sc_irq); +#endif +} diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_timer_ts.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_timer_ts.c new file mode 100644 index 0000000..c5df1b4 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_timer_ts.c @@ -0,0 +1,143 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "system.h" +#include "sys/alt_timestamp.h" + +#include "altera_avalon_timer.h" +#include "altera_avalon_timer_regs.h" + +#include "alt_types.h" + +/* + * These functions are only available if a timestamp device has been selected + * for this system. + */ + +#if (ALT_TIMESTAMP_CLK_BASE != none_BASE) + +/* + * The function alt_timestamp_start() can be called at application level to + * initialise the timestamp facility. In this case the period register is + * set to full scale, i.e. 0xffffffff, and then started running. Note that + * the period register may not be writable, depending on the hardware + * configuration, in which case this function does not reset the period. + * + * The timer is not run in continuous mode, so that the user can detect timer + * roll-over, i.e. alt_timestamp() returns 0. + * + * The return value of this function is 0 upon sucess and -1 if in timestamp + * device has not been registered. + */ + +int alt_timestamp_start(void) +{ + void* base = altera_avalon_timer_ts_base; + + if (!altera_avalon_timer_ts_freq) + { + return -1; + } + else + { + if(ALT_TIMESTAMP_COUNTER_SIZE == 64) { + IOWR_ALTERA_AVALON_TIMER_CONTROL (base,ALTERA_AVALON_TIMER_CONTROL_STOP_MSK); + IOWR_ALTERA_AVALON_TIMER_PERIOD_0 (base, 0xFFFF); + IOWR_ALTERA_AVALON_TIMER_PERIOD_1 (base, 0xFFFF);; + IOWR_ALTERA_AVALON_TIMER_PERIOD_2 (base, 0xFFFF); + IOWR_ALTERA_AVALON_TIMER_PERIOD_3 (base, 0xFFFF); + IOWR_ALTERA_AVALON_TIMER_CONTROL (base, ALTERA_AVALON_TIMER_CONTROL_START_MSK); + } else { + IOWR_ALTERA_AVALON_TIMER_CONTROL (base,ALTERA_AVALON_TIMER_CONTROL_STOP_MSK); + IOWR_ALTERA_AVALON_TIMER_PERIODL (base, 0xFFFF); + IOWR_ALTERA_AVALON_TIMER_PERIODH (base, 0xFFFF); + IOWR_ALTERA_AVALON_TIMER_CONTROL (base, ALTERA_AVALON_TIMER_CONTROL_START_MSK); + } + } + return 0; +} + +/* + * alt_timestamp() returns the current timestamp count. In the event that + * the timer has run full period, or there is no timestamp available, this + * function return -1. + * + * The returned timestamp counts up from the last time the period register + * was reset. + */ + +alt_timestamp_type alt_timestamp(void) +{ + + void* base = altera_avalon_timer_ts_base; + + if (!altera_avalon_timer_ts_freq) + { +#if (ALT_TIMESTAMP_COUNTER_SIZE == 64) + return 0xFFFFFFFFFFFFFFFFULL; +#else + return 0xFFFFFFFF; +#endif + } + else + { +#if (ALT_TIMESTAMP_COUNTER_SIZE == 64) + IOWR_ALTERA_AVALON_TIMER_SNAP_0 (base, 0); + alt_timestamp_type snap_0 = IORD_ALTERA_AVALON_TIMER_SNAP_0(base) & ALTERA_AVALON_TIMER_SNAP_0_MSK; + alt_timestamp_type snap_1 = IORD_ALTERA_AVALON_TIMER_SNAP_1(base) & ALTERA_AVALON_TIMER_SNAP_1_MSK; + alt_timestamp_type snap_2 = IORD_ALTERA_AVALON_TIMER_SNAP_2(base) & ALTERA_AVALON_TIMER_SNAP_2_MSK; + alt_timestamp_type snap_3 = IORD_ALTERA_AVALON_TIMER_SNAP_3(base) & ALTERA_AVALON_TIMER_SNAP_3_MSK; + + return (0xFFFFFFFFFFFFFFFFULL - ( (snap_3 << 48) | (snap_2 << 32) | (snap_1 << 16) | (snap_0) )); +#else + IOWR_ALTERA_AVALON_TIMER_SNAPL (base, 0); + alt_timestamp_type lower = IORD_ALTERA_AVALON_TIMER_SNAPL(base) & ALTERA_AVALON_TIMER_SNAPL_MSK; + alt_timestamp_type upper = IORD_ALTERA_AVALON_TIMER_SNAPH(base) & ALTERA_AVALON_TIMER_SNAPH_MSK; + + return (0xFFFFFFFF - ((upper << 16) | lower)); +#endif + } +} + +/* + * Return the number of timestamp ticks per second. This will be 0 if no + * timestamp device has been registered. + */ + +alt_u32 alt_timestamp_freq(void) +{ + return altera_avalon_timer_ts_freq; +} + +#endif /* timestamp available */ diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_timer_vars.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_timer_vars.c new file mode 100644 index 0000000..57c431d --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_timer_vars.c @@ -0,0 +1,45 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "altera_avalon_timer.h" +#include "alt_types.h" + +/* + * Variables used to store the timestamp parameters. These are initialised + * from alt_sys_init() using the ALTERA_AVALON_TIMER_INIT macro + * defined in altera_avalon_timer.h. + */ + +void* altera_avalon_timer_ts_base = (void*) 0; +alt_u32 altera_avalon_timer_ts_freq = 0; diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_tse.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_tse.c new file mode 100644 index 0000000..9c2acc1 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_tse.c @@ -0,0 +1,2339 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "altera_avalon_tse.h" +#include "sys/alt_cache.h" +#include +#include +#include +#include + +void no_printf (char *fmt, ...) {} + +#ifdef __ALTERA_MSGDMA + + +/** @Function Description - Perform initialization steps on transaction info structure to prepare it for . + * use by the library functions with two MSGDMAs and extra initialization Flags + * @API Type: Internal + * @param mi Main Device Structure. + * @param mac_base Base Address of the Control interface for the TSE MAC + * @param tx_msgdma MSGDMA device handle for TSE transmit data path + * @param rx_msgdma MSGDMA device handle for TSE receive data path + * @param cfgflags initialization flags for the device + * @return 0 + */ + +alt_32 tse_mac_initTransInfo2( tse_mac_trans_info *mi, + alt_u32 mac_base, + alt_32 tx_msgdma, + alt_32 rx_msgdma, + alt_32 cfgflags) { + + mi->base = (np_tse_mac*)mac_base; + mi->tx_msgdma = (alt_msgdma_dev *)tx_msgdma; + mi->rx_msgdma = (alt_msgdma_dev *)rx_msgdma; + mi->cfgflags = cfgflags; + return SUCCESS; +} + +/** @Function Description - Synchronous MSGDMA copy from buffer memory into transmit FIFO. Waits until + * SGDMA has completed. Raw function without any error checks. + * @API Type: Internal + * @param mi Main Device Structure. + * @param txDesc Pointer to the transmit MSGDMA descriptor + * @return actual bytes transferred if ok, else error (-1) + */ +alt_32 tse_mac_sTxWrite( tse_mac_trans_info *mi, + alt_msgdma_standard_descriptor *txDesc) +{ + + alt_32 timeout; + alt_u8 result = 0; + + // Make sure DMA controller is not busy from a former command + // and TX is able to accept data + timeout = 0; + while ( (IORD_ALTERA_MSGDMA_CSR_STATUS(mi->tx_msgdma->csr_base) & + ALTERA_MSGDMA_CSR_BUSY_MASK) ) { + if(timeout++ == ALTERA_TSE_MSGDMA_BUSY_TIME_OUT_CNT) { + tse_dprintf(4, "WARNING : TX MSGDMA Timeout\n"); + return ENP_RESOURCE; // avoid being stuck here + } + } + + // Start MSGDMA (blocking call) + alt_dcache_flush(txDesc,sizeof(alt_msgdma_standard_descriptor)); + result = alt_msgdma_standard_descriptor_sync_transfer( + mi->tx_msgdma, + txDesc); + + if (result != 0) { + tse_dprintf(4, "WARNING :alt_msgdma_standard_descriptor_sync_transfer Error code 0x%x\n",result); + return -1; + } + + return 0; +} + + +/** @Function Description - Asynchronous MSGDMA copy from rxFIFO into given buffer memory area. + * Raw function without any error checks. + * + * @API Type: Internal + * @param mi Main Device Structure. + * @param rxDesc Pointer to the receive MSGDMA descriptor list + * @return 0 if ok, else error (-1) + * + * Note: At the point of this function call return, + * the MSGDMA asynchronous operation may not have been + * completed yet, so the function does not return + * the actual bytes transferred for current descriptor + */ +alt_32 tse_mac_aRxRead( + tse_mac_trans_info *mi, + alt_msgdma_prefetcher_standard_descriptor *rxDesc) +{ + alt_u8 result; + + result = alt_msgdma_start_prefetcher_with_std_desc_list( + mi->rx_msgdma, + rxDesc,0,0,1,1); + + if (result != 0) { return -1; } + + return SUCCESS; +} + +/** @Function Description - Asynchronous MSGDMA transfer from buffer to txFIFO + * + * + * @API Type: Internal + * @param mi Main Device Structure. + * @param rxDesc Pointer to the transmit MSGDMA descriptor list + * @return 0 if ok, or (-1) if error + * + */ +alt_32 tse_mac_aTxWrite( + tse_mac_trans_info *mi, + alt_msgdma_prefetcher_standard_descriptor *txDesc) +{ + alt_u8 result; + + result = alt_msgdma_start_prefetcher_with_std_desc_list( + mi->tx_msgdma, + txDesc,0,0,1,1); + + if (result != 0) { return -1; } + + return SUCCESS; +} + + +#endif /* __ALTERA_MSGDMA */ + +/* Definition of TSE system */ +extern alt_tse_system_info tse_mac_device[MAXNETS]; + +/* PHY profile*/ +alt_tse_phy_profile *pphy_profiles[TSE_MAX_PHY_PROFILE]; +alt_u8 phy_profile_count = 0; + +/* MAC in TSE system */ +alt_tse_mac_group *pmac_groups[TSE_MAX_MAC_IN_SYSTEM]; +alt_u8 mac_group_count = 0; +alt_u8 max_mac_system = MAXNETS; + +/******************************* + * + * Public API for TSE Driver + * + *******************************/ + +/* @Function Description: Perform a software Reset. Reset operation will ocur with some latency. + * COMMAND_CONFIG register is restored after reset. + * @API Type: Public + * @param pmac Pointer to the TSE MAC Control Interface Base address +*/ +alt_32 tse_mac_SwReset(np_tse_mac *pmac) +{ + alt_32 timeout; + alt_32 cc; + + cc = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac); + + // set reset and Gig-Speed bits to make sure we have an incoming clock on + // tx side. If there is a 10/100 PHY, we will still have a valid clock on + // tx_clk no matter what setting we have here, but on a Gig phy the + // MII clock may be missing. + IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac,(ALTERA_TSEMAC_CMD_SW_RESET_MSK | ALTERA_TSEMAC_CMD_ETH_SPEED_MSK)); + + + // wait for completion with fallback in case there is no PHY or it is + // not connected and hence might not provide any clocks at all. + timeout=0; + while( (IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac) & ALTERA_TSEMAC_CMD_SW_RESET_MSK) != 0 && timeout < ALTERA_TSE_SW_RESET_TIME_OUT_CNT) timeout++; + + IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac,cc); // Restore + return SUCCESS; +} + + + +/* @Function Description: Perform switching of the TSE MAC into MII (10/100) mode. + * COMMAND_CONFIG register is restored after reset. + * @API Type: Public + * @param pmac Pointer to the TSE MAC Control Interface Base address +*/ +alt_32 tse_mac_setMIImode(np_tse_mac *pmac) +{ + alt_32 helpvar; + + helpvar = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac); + helpvar &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; + + IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac,helpvar); + return SUCCESS; +} + + +/* @Function Description: Perform switching of the TSE MAC into GMII (Gigabit) mode. + * COMMAND_CONFIG register is restored after reset. + * @API Type: Public + * @param pmac Pointer to the TSE MAC Control Interface Base address + */ +alt_32 tse_mac_setGMIImode(np_tse_mac *pmac) +{ + alt_32 helpvar; + + helpvar = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac); + helpvar |= ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; + + IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac,helpvar); + return SUCCESS; +} + + + +/* @Function Description - Add additional PHYs which are not supported by default into PHY profile for PHY detection and auto negotiation + * + * @API TYPE - Public + * @param phy pointer to alt_tse_phy_profile structure describing PHY registers + * @return index of PHY added in PHY profile on success, else return ALTERA_TSE_MALLOC_FAILED if memory allocation failed + * PHY which are currently supported by default : Marvell 88E1111, Marvell Quad PHY 88E1145, National DP83865, and National DP83848C + */ +alt_32 alt_tse_phy_add_profile(alt_tse_phy_profile *phy) +{ + alt_32 i; + + /* search PHY profile for same ID */ + for(i = 0; i < phy_profile_count; i++) + { + if(pphy_profiles[i]->oui == phy->oui && pphy_profiles[i]->model_number == phy->model_number) + { + tse_dprintf(4, "WARNING : PHY OUI 0x%06x, PHY Model Number 0x%02x already exist in PHY profile\n", (int) phy->oui, phy->model_number); + tse_dprintf(4, "In case of same PHY OUI and PHY Model Number in profile, first added PHY setting will be used\n"); + } + } + + /* Allocate memory space to store the profile */ + pphy_profiles[phy_profile_count] = (alt_tse_phy_profile *) malloc(sizeof(alt_tse_phy_profile)); + if(!pphy_profiles[phy_profile_count]) { + tse_dprintf(1, "ERROR : Unable to allocate memory for pphy_profile[%d]\n", phy_profile_count); + return ALTERA_TSE_MALLOC_FAILED; + } + + /* Store PHY information */ + *pphy_profiles[phy_profile_count] = *phy; + strcpy(pphy_profiles[phy_profile_count]->name, phy->name); + + phy_profile_count++; + + return phy_profile_count - 1; +} + +/* @Function Description - Add TSE System to tse_mac_device[] array to customize TSE System + * + * @API TYPE - Public + * @param psys_mac pointer to alt_tse_system_mac structure describing MAC of the system + * @param psys_msgdma pointer to alt_tse_system_msgdma structure describing MSGDMA of the system + * @param psys_mem pointer to alt_tse_system_desc_mem structure describing Descriptor Memory of the system + * @param psys_phy pointer to alt_tse_system_phy structure describing PHY of the system + * @return SUCCESS on success + * ALTERA_TSE_MALLOC_FAILED if memory allocation failed + * ALTERA_TSE_SYSTEM_DEF_ERROR if definition of system incorrect or pointer == NULL + */ +alt_32 alt_tse_system_add_sys( + alt_tse_system_mac *psys_mac, + alt_tse_system_msgdma *psys_msgdma, + alt_tse_system_desc_mem *psys_mem, + alt_tse_system_shared_fifo *psys_shared_fifo, + alt_tse_system_phy *psys_phy ) { + + int i; + int loop_end; + + alt_tse_system_mac *pmac = psys_mac; + alt_tse_system_msgdma *pmsgdma = psys_msgdma; + alt_tse_system_desc_mem *pmem = psys_mem; + alt_tse_system_shared_fifo *pfifo = psys_shared_fifo; + alt_tse_system_phy *pphy = psys_phy; + + static alt_8 tse_system_count = 0; + + /* Determine number of loop */ + /* Run at least one for non-multi-channel MAC */ + if(pmac->tse_num_of_channel == 0) { + loop_end = 1; + } + else if(pmac->tse_num_of_channel > 0) { + loop_end = pmac->tse_num_of_channel; + } + else { + tse_dprintf(2, "ERROR : Invalid number of channel specified!\n"); + return ALTERA_TSE_SYSTEM_DEF_ERROR; + } + + for(i = 0; i < loop_end; i++) { + + /* Make sure the boundary of array is not exceeded */ + if(tse_system_count >= MAXNETS) { + tse_dprintf(2, "ERROR : Number of TSE System added exceed the size of array!\n"); + tse_dprintf(2, "ERROR : Size of array = %d, Number of TSE System = %d\n", MAXNETS, tse_system_count); + } + + /* Add MAC info to alt_tse_system_info structure */ + if(pmac == 0) { + tse_dprintf(2, "ERROR : MAC system structure == NULL\n"); + tse_dprintf(2, "ERROR : Please pass in correct pointer to alt_tse_system_add_sys()\n"); + return ALTERA_TSE_SYSTEM_DEF_ERROR; + } + + tse_mac_device[tse_system_count].tse_mac_base = pmac->tse_mac_base + (i * 0x400); + tse_mac_device[tse_system_count].tse_tx_depth = pmac->tse_tx_depth; + tse_mac_device[tse_system_count].tse_rx_depth = pmac->tse_rx_depth; + tse_mac_device[tse_system_count].tse_use_mdio = pmac->tse_use_mdio; + tse_mac_device[tse_system_count].tse_en_maclite = pmac->tse_en_maclite; + tse_mac_device[tse_system_count].tse_maclite_gige = pmac->tse_maclite_gige; + tse_mac_device[tse_system_count].tse_multichannel_mac = pmac->tse_multichannel_mac; + tse_mac_device[tse_system_count].tse_num_of_channel = pmac->tse_num_of_channel; + tse_mac_device[tse_system_count].tse_mdio_shared = pmac->tse_mdio_shared; + tse_mac_device[tse_system_count].tse_number_of_mac_mdio_shared = pmac->tse_number_of_mac_mdio_shared; + tse_mac_device[tse_system_count].tse_pcs_ena = pmac->tse_pcs_ena; + tse_mac_device[tse_system_count].tse_pcs_sgmii = pmac->tse_pcs_sgmii; + + /* Add MSGDMA info to alt_tse_system_info structure */ + if(pmsgdma == 0) { + tse_dprintf(2, "ERROR : MSGDMA system structure == NULL\n"); + tse_dprintf(2, "ERROR : Please pass in correct pointer to alt_tse_system_add_sys() for tse_mac_device[%d]\n", tse_system_count); + return ALTERA_TSE_SYSTEM_DEF_ERROR; + } + + tse_mac_device[tse_system_count].tse_msgdma_tx = (char *) malloc(strlen(pmsgdma->tse_msgdma_tx) + 1); + if(!tse_mac_device[tse_system_count].tse_msgdma_tx) { + tse_dprintf(1, "ERROR : Unable to allocate memory for tse_mac_device[%d].tse_msgdma_tx\n", tse_system_count); + return ALTERA_TSE_MALLOC_FAILED; + } + strcpy(tse_mac_device[tse_system_count].tse_msgdma_tx, pmsgdma->tse_msgdma_tx); + + tse_mac_device[tse_system_count].tse_msgdma_rx = (char *) malloc(strlen(pmsgdma->tse_msgdma_rx) + 1); + if(!tse_mac_device[tse_system_count].tse_msgdma_rx) { + tse_dprintf(1, "ERROR : Unable to allocate memory for tse_mac_device[%d].tse_msgdma_rx\n", tse_system_count); + return ALTERA_TSE_MALLOC_FAILED; + } + strcpy(tse_mac_device[tse_system_count].tse_msgdma_rx, pmsgdma->tse_msgdma_rx); + + tse_mac_device[tse_system_count].tse_msgdma_rx_irq = pmsgdma->tse_msgdma_rx_irq; + + /* Add descriptor memory info to alt_tse_system_info structure */ + if(pmem == 0) { + tse_mac_device[tse_system_count].ext_desc_mem = TSE_INT_DESC_MEM; + tse_mac_device[tse_system_count].desc_mem_base = TSE_INT_DESC_MEM; + } + else { + tse_mac_device[tse_system_count].ext_desc_mem = pmem->ext_desc_mem; + tse_mac_device[tse_system_count].desc_mem_base = pmem->desc_mem_base; + } + + /* Add shared fifo info to alt_tse_system_info structure */ + if(pfifo == 0) { + tse_mac_device[tse_system_count].use_shared_fifo = TSE_NO_SHARED_FIFO; + tse_mac_device[tse_system_count].tse_shared_fifo_tx_ctrl_base = TSE_NO_SHARED_FIFO; + tse_mac_device[tse_system_count].tse_shared_fifo_tx_stat_base = TSE_NO_SHARED_FIFO; + tse_mac_device[tse_system_count].tse_shared_fifo_tx_depth = TSE_NO_SHARED_FIFO; + + tse_mac_device[tse_system_count].tse_shared_fifo_rx_ctrl_base = TSE_NO_SHARED_FIFO; + tse_mac_device[tse_system_count].tse_shared_fifo_rx_stat_base = TSE_NO_SHARED_FIFO; + tse_mac_device[tse_system_count].tse_shared_fifo_rx_depth = TSE_NO_SHARED_FIFO; + } + else { + tse_mac_device[tse_system_count].use_shared_fifo = pfifo->use_shared_fifo; + tse_mac_device[tse_system_count].tse_shared_fifo_tx_ctrl_base = pfifo->tse_shared_fifo_tx_ctrl_base; + tse_mac_device[tse_system_count].tse_shared_fifo_tx_stat_base = pfifo->tse_shared_fifo_tx_stat_base; + tse_mac_device[tse_system_count].tse_shared_fifo_tx_depth = pfifo->tse_shared_fifo_tx_depth; + + tse_mac_device[tse_system_count].tse_shared_fifo_rx_ctrl_base = pfifo->tse_shared_fifo_rx_ctrl_base; + tse_mac_device[tse_system_count].tse_shared_fifo_rx_stat_base = pfifo->tse_shared_fifo_rx_stat_base; + tse_mac_device[tse_system_count].tse_shared_fifo_rx_depth = pfifo->tse_shared_fifo_rx_depth; + } + + /* Add PHY info to alt_tse_system_info structure */ + if(pphy == 0) { + tse_mac_device[tse_system_count].tse_phy_mdio_address = TSE_PHY_AUTO_ADDRESS; + tse_mac_device[tse_system_count].tse_phy_cfg = 0; + } + else { + tse_mac_device[tse_system_count].tse_phy_mdio_address = pphy->tse_phy_mdio_address; + tse_mac_device[tse_system_count].tse_phy_cfg = pphy->tse_phy_cfg; + } + + /* Point to next structure */ + pmsgdma++; + if(pmem) pmem++; + if(pfifo) pfifo++; + if(pphy) pphy++; + + tse_system_count++; + max_mac_system = tse_system_count; + } + + return SUCCESS; + +} + +/* @Function Description - Enable MDIO sharing for multiple single channel MAC + * + * @API TYPE - Public + * @param psys_mac_list pointer to array of alt_tse_system_mac structure sharing MDIO block + * @param number_of_mac number of MAC sharing MDIO block + * @return SUCCESS on success + * ALTERA_TSE_SYSTEM_DEF_ERROR if definition of system incorrect or pointer == NULL + * Multi-channel MAC not supported + */ +alt_32 alt_tse_sys_enable_mdio_sharing(alt_tse_system_mac **psys_mac_list, alt_u8 number_of_mac) { + alt_32 i; + alt_32 j; + + alt_tse_system_mac *psys_mac; + + for(i = 0; i < number_of_mac; i++) { + psys_mac = psys_mac_list[i]; + + if(psys_mac == 0) { + tse_dprintf(2, "ERROR : MAC system structure == NULL\n"); + tse_dprintf(2, "ERROR : Please pass in correct pointer to alt_tse_sys_enable_mdio_sharing()\n"); + return ALTERA_TSE_SYSTEM_DEF_ERROR; + } + + for(j = 0; j < max_mac_system; j++) { + + if(psys_mac->tse_mac_base == tse_mac_device[j].tse_mac_base) { + if(tse_mac_device[j].tse_multichannel_mac) { + tse_dprintf(2, "ERROR : MDIO sharing supported by default for Multi-channel MAC\n"); + tse_dprintf(2, "ERROR : Do not include Multi-channel MAC in the MAC List\n"); + return ALTERA_TSE_SYSTEM_DEF_ERROR; + } + + tse_mac_device[j].tse_mdio_shared = 1; + tse_mac_device[j].tse_number_of_mac_mdio_shared = number_of_mac; + } + } + } + + return SUCCESS; +} + +/* @Function Description: Get the common speed supported by all PHYs connected to the MAC within the same group + * @API Type: Public + * @param pmac Pointer to the TSE MAC Control Interface Base address + * @return common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if no common speed found + */ +alt_32 alt_tse_mac_get_common_speed(np_tse_mac *pmac) { + alt_tse_mac_group *pmac_group = alt_tse_get_mac_info(pmac)->pmac_group; + return alt_tse_phy_get_common_speed(pmac_group); +} + +/* @Function Description: Set the common speed to all PHYs connected to the MAC within the same group + * @API Type: Public + * @param pmac Pointer to the TSE MAC Control Interface Base address + * common_speed common speed supported by all PHYs + * @return common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if invalid common speed specified + */ +alt_32 alt_tse_mac_set_common_speed(np_tse_mac *pmac, alt_32 common_speed) { + alt_tse_mac_group *pmac_group = alt_tse_get_mac_info(pmac)->pmac_group; + return alt_tse_phy_set_common_speed(pmac_group, common_speed); +} + + +/******************************** + * + * Internal API for TSE Driver + * + *******************************/ + +/* @Function Description: Get the index of alt_tse_system_info structure in tse_mac_device[] + * @API Type: Internal + * @param psys_info Pointer to the alt_tse_system_info structure + * @return Index of alt_tse_system_info structure in tse_mac_device[] + */ +alt_32 alt_tse_get_system_index(alt_tse_system_info *psys_info) { + alt_32 i; + + for(i = 0; i < max_mac_system; i++) { + if(psys_info == &tse_mac_device[i]) { + return i; + } + } + return ALTERA_TSE_NO_INDEX_FOUND; +} + +/* @Function Description: Get the index of alt_tse_mac_group structure in pmac_groups[] + * @API Type: Internal + * @param pmac_group Pointer to the alt_tse_mac_group structure + * @return Index of alt_tse_mac_group structure in pmac_groups[] + */ +alt_32 alt_tse_get_mac_group_index(alt_tse_mac_group *pmac_group) { + alt_32 i; + + for(i = 0; i < mac_group_count; i++) { + if(pmac_group == pmac_groups[i]) { + return i; + } + } + return ALTERA_TSE_NO_INDEX_FOUND; +} + + +/* @Function Description: Get the index of alt_tse_mac_info structure in pmac_groups[]->pmac_info[] + * @API Type: Internal + * @param pmac_group Pointer to the alt_tse_mac_info structure + * @return Index of alt_tse_mac_info structure in pmac_groups[]->pmac_info[] + */ +alt_32 alt_tse_get_mac_info_index(alt_tse_mac_info *pmac_info) { + alt_32 i; + + for(i = 0; i < pmac_info->pmac_group->channel; i++) { + if(pmac_info == pmac_info->pmac_group->pmac_info[i]) { + return i; + } + } + + return ALTERA_TSE_NO_INDEX_FOUND; +} + +/* @Function Description: Get the pointer of alt_tse_mac_info structure in pmac_groups[]->pmac_info[] + * @API Type: Internal + * @param pmac Pointer to the TSE MAC Control Interface Base address + * @return Pointer to alt_tse_mac_info structure in pmac_groups[]->pmac_info[] + */ +alt_tse_mac_info *alt_tse_get_mac_info(np_tse_mac *pmac) { + alt_32 i; + alt_32 j; + alt_tse_mac_group *pmac_group = 0; + alt_tse_mac_info *pmac_info = 0; + + for(i = 0; i < mac_group_count; i++) { + pmac_group = pmac_groups[i]; + for(j = 0; j < pmac_group->channel; j++) { + pmac_info = pmac_group->pmac_info[j]; + if(((np_tse_mac *) pmac_info->psys_info->tse_mac_base) == pmac) { + return pmac_info; + } + } + } + + return 0; +} + +/* @Function Description: Perform switching of the TSE MAC speed. + * COMMAND_CONFIG register is restored after reset. + * @API Type: Internal + * @param pmac Pointer to the TSE MAC Control Interface Base address + * @param speed 2 = 1000 Mbps, 1 = 100 Mbps, 0 = 10 Mbps + * @return ENP_PARAM if invalid speed specified, else return SUCCESS + */ +alt_32 alt_tse_mac_set_speed(np_tse_mac *pmac, alt_u8 speed) +{ + alt_32 helpvar; + + helpvar = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac); + + /* 1000 Mbps */ + if(speed == TSE_PHY_SPEED_1000) { + helpvar |= ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; + helpvar &= ~ALTERA_TSEMAC_CMD_ENA_10_MSK; + } + /* 100 Mbps */ + else if(speed == TSE_PHY_SPEED_100) { + helpvar &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; + helpvar &= ~ALTERA_TSEMAC_CMD_ENA_10_MSK; + } + /* 10 Mbps */ + else if(speed == TSE_PHY_SPEED_10) { + helpvar &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; + helpvar |= ALTERA_TSEMAC_CMD_ENA_10_MSK; + } + else { + return ENP_PARAM; + } + + IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac, helpvar); + return SUCCESS; +} + +/* @Function Description: Perform switching of the TSE MAC duplex mode. + * COMMAND_CONFIG register is restored after reset. + * @API Type: Internal + * @param pmac Pointer to the TSE MAC Control Interface Base address + * @param duplex 1 = Full Duplex, 0 = Half Duplex + * @return ENP_PARAM if invalid duplex specified, else return SUCCESS + */ +alt_32 alt_tse_mac_set_duplex(np_tse_mac *pmac, alt_u8 duplex) +{ + alt_32 helpvar; + + helpvar = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac); + + /* Half Duplex */ + if(duplex == TSE_PHY_DUPLEX_HALF) { + helpvar |= ALTERA_TSEMAC_CMD_HD_ENA_MSK; + } + /* Full Duplex */ + else if(duplex == TSE_PHY_DUPLEX_FULL) { + helpvar &= ~ALTERA_TSEMAC_CMD_HD_ENA_MSK; + } + else { + return ENP_PARAM; + } + + IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac, helpvar); + return SUCCESS; + +} + + + +/** @Function Description - Determine link speed our PHY negotiated with our link partner. + * This is fully vendor specific depending on the PHY you are using. + * + * @API TYPE - Internal + * @param tse.mi.base MAC register map. + * @return + * ---------------------------------------------------------------------------------- + * | BIT | Value: Description | + * ---------------------------------------------------------------------------------- + * | 31-23 | Reserved | + * | 23 | 1: Argument *pmac not found from the list of MAC detected during init | + * | 22 | 1: No MDIO used by the MAC | + * | 21 | 1: No PHY detected | + * | 20 | 1: No common speed found for Multi-port MAC | + * | 19 | 1: PHY auto-negotiation not completed | + * | 18 | 1: No PHY profile match the detected PHY | + * | 17 | 1: PHY Profile not defined correctly | + * | 16 | 1: Invalid speed read from PHY | + * | 4-15 | Reserved | + * | 3 | 1: 10 Mbps link | + * | 2 | 1: 100 Mbps link | + * | 1 | 1: 1000 Mbps link | + * | 0 | 1: Full Duplex 0: Half Duplex | + * ---------------------------------------------------------------------------------- + * + * If the link speed cannot be determined, it is fall back to 100 Mbps (customizable by changing ALTERA_TSE_MAC_SPEED_DEFAULT) + * Full duplex (customizable by changing ALTERA_TSE_DUPLEX_MODE_DEFAULT) + */ + +#define ALT_TSE_SPEED_DUPLEX(speed, duplex) ((duplex & 0x01) |\ + (((speed == TSE_PHY_SPEED_1000) ? 1 : 0) << 1) | \ + (((speed == TSE_PHY_SPEED_100) ? 1 : 0) << 2) | \ + (((speed == TSE_PHY_SPEED_10) ? 1 : 0) << 3) | \ + ((speed == TSE_PHY_SPEED_INVALID) ? ALT_TSE_E_INVALID_SPEED : 0)) + +alt_32 getPHYSpeed(np_tse_mac *pmac) { + + alt_u8 speed = ALTERA_TSE_MAC_SPEED_DEFAULT; + alt_u8 duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT; /* 1 = full ; 0 = half*/ + alt_32 result = ALT_TSE_SPEED_DUPLEX(speed, duplex); + + alt_tse_phy_info *pphy = 0; + alt_tse_mac_info *pmac_info = 0; + alt_tse_mac_group *pmac_group = 0; + alt_tse_system_info *psys = 0; + + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = 0; + alt_8 mac_group_index = 0; + + /* initialized PHYs only once */ + static alt_u8 is_init = 0; + if(is_init == 0) { + alt_tse_phy_init(); + is_init = 1; + } + + /* Look for pmac_group and pmac_info structure based on pmac or iface */ + pmac_info = alt_tse_get_mac_info(pmac); + + if(pmac_info == 0) { + speed = ALTERA_TSE_MAC_SPEED_DEFAULT; + duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT; + result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_NO_PMAC_FOUND; + tse_dprintf(2, "ERROR : [getPHYSpeed] pmac not found from list of pmac_info[]! Speed = %s Mbps, Duplex = %s\n", speed == TSE_PHY_SPEED_1000 ? "1000" : + speed == TSE_PHY_SPEED_100 ? "100" : + speed == TSE_PHY_SPEED_10 ? "10" : "Unknown", + duplex == 1 ? "Full" : "Half"); + tse_dprintf(2, "ERROR : [getPHYSpeed] Please define tse_mac_device[] correctly\n"); + return result; + } + + pphy = pmac_info->pphy_info; + pmac_group = pmac_info->pmac_group; + psys = pmac_info->psys_info; + + mac_info_index = alt_tse_get_mac_info_index(pmac_info); + mac_group_index = alt_tse_get_mac_group_index(pmac_group); + + /* MDIO is not used */ + if (pmac_group->pmac_info[0]->psys_info->tse_use_mdio == 0) + { + speed = ALTERA_TSE_MAC_SPEED_DEFAULT; + duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT; + result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_NO_MDIO; + usleep(ALTERA_NOMDIO_TIMEOUT_THRESHOLD); + if(psys->tse_phy_cfg) { + tse_dprintf(4, "WARNING : PHY[%d.%d] - MDIO not enabled! Running user configuration...\n", mac_group_index, mac_info_index); + result = psys->tse_phy_cfg(pmac); + } + else { + tse_dprintf(4, "WARNING : MAC Group[%d] - MDIO not enabled! Speed = %s, Duplex = %s\n", mac_group_index, speed == TSE_PHY_SPEED_1000 ? "1000" : + speed == TSE_PHY_SPEED_100 ? "100" : + speed == TSE_PHY_SPEED_10 ? "10" : "Unknown", + duplex == 1 ? "Full" : "Half"); + } + return result; + } + + /* Not running simulation */ + #ifndef ALT_SIM_OPTIMIZE + + /* These variables declaration are here to avoid "warning: unused variable" message when compile for simulation */ + np_tse_mac *pmac_group_base = (np_tse_mac *) pmac_group->pmac_info[0]->psys_info->tse_mac_base; + + /* if no PHY connected to the MAC */ + if(pphy == 0) { + speed = ALTERA_TSE_MAC_SPEED_DEFAULT; + duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT; + result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_NO_PHY; + tse_dprintf(2, "ERROR : PHY[%d.%d] - No PHY connected! Speed = %s, Duplex = %s\n", mac_group_index, mac_info_index, speed == TSE_PHY_SPEED_1000 ? "1000" : + speed == TSE_PHY_SPEED_100 ? "100" : + speed == TSE_PHY_SPEED_10 ? "10" : "Unknown", + duplex == 1 ? "Full" : "Half"); + return result; + } + + /* Small MAC */ + if(pmac_info->mac_type == ALTERA_TSE_MACLITE_10_100) { + alt_tse_phy_set_adv_1000(pphy, 0); + alt_tse_phy_restart_an(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD); + } + else if(pmac_info->mac_type == ALTERA_TSE_MACLITE_1000) { + alt_tse_phy_set_adv_100(pphy, 0); + alt_tse_phy_set_adv_10(pphy, 0); + alt_tse_phy_restart_an(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD); + } + + /* check link connection for this PHY */ + if(alt_tse_phy_check_link(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD) == TSE_PHY_AN_NOT_COMPLETE) { + speed = ALTERA_TSE_MAC_SPEED_DEFAULT; + duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT; + result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_AN_NOT_COMPLETE; + tse_dprintf(3, "WARNING : PHY[%d.%d] - Auto-Negotiation not completed! Speed = %s, Duplex = %s\n", mac_group_index, mac_info_index, speed == TSE_PHY_SPEED_1000 ? "1000" : + speed == TSE_PHY_SPEED_100 ? "100" : + speed == TSE_PHY_SPEED_10 ? "10" : "Unknown", + duplex == 1 ? "Full" : "Half"); + return result; + } + + IOWR(&pmac_group_base->MDIO_ADDR1, 0, pphy->mdio_address); + + /* To enable PHY loopback */ + #if ENABLE_PHY_LOOPBACK + tse_dprintf(5, "INFO : PHY[%d.%d] - Putting PHY in loopback\n", mac_group_index, mac_info_index); + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_LOOPBACK, 1, 1); // enable PHY loopback + #else + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_LOOPBACK, 1, 0); // disable PHY loopback + #endif + + /* if PHY not found in profile */ + if(pphy->pphy_profile == 0) { + tse_dprintf(3, "WARNING : PHY[%d.%d] - PHY not found in PHY profile\n", mac_group_index, mac_info_index); + speed = ALTERA_TSE_MAC_SPEED_DEFAULT; + duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT; + result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_NO_PHY_PROFILE; + } + // retrieve duplex information from PHY + else + { + if(pphy->pphy_profile->link_status_read) + { + result = pphy->pphy_profile->link_status_read(pmac_group_base); + speed = (result & 0x02) ? TSE_PHY_SPEED_1000 : + (result & 0x04) ? TSE_PHY_SPEED_100 : + (result & 0x08) ? TSE_PHY_SPEED_10 : TSE_PHY_SPEED_INVALID; + duplex = (result & 0x01) ? TSE_PHY_DUPLEX_FULL : TSE_PHY_DUPLEX_HALF; + + if(result & ALT_TSE_E_INVALID_SPEED) + { + tse_dprintf(3, "WARNING : PHY[%d.%d] - Invalid speed read from PHY\n", mac_group_index, mac_info_index); + } + } + else if(pphy->pphy_profile->status_reg_location == 0) + { + tse_dprintf(3, "WARNING : PHY[%d.%d] - PHY Specific Status register information not provided in profile\n", mac_group_index, mac_info_index); + speed = ALTERA_TSE_MAC_SPEED_DEFAULT; + duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT; + result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_PROFILE_INCORRECT_DEFINED; + } + else + { + /* extract connection speed and duplex information */ + speed = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->speed_lsb_location, 2); + duplex = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->duplex_bit_location, 1); + + result = ALT_TSE_SPEED_DUPLEX(speed, duplex); + } + } + + #else + /* for simulation purpose, default to gigabit mode */ + speed = 1; + duplex = 1; + #endif + + tse_dprintf(5, "INFO : PHY[%d.%d] - Speed = %s, Duplex = %s\n", mac_group_index, mac_info_index, speed == TSE_PHY_SPEED_1000 ? "1000" : + speed == TSE_PHY_SPEED_100 ? "100" : + speed == TSE_PHY_SPEED_10 ? "10" : "Unknown", + duplex == 1 ? "Full" : "Half"); + + return result; +} + + +/* @Function Description: Read MDIO address from the MDIO address1 register of first MAC within MAC group + * @API Type: Internal + * @param pmac Pointer to the alt_tse_phy_info structure + * @return return SUCCESS + */ +alt_32 alt_tse_phy_rd_mdio_addr(alt_tse_phy_info *pphy) { + np_tse_mac *pmac_group_base = (np_tse_mac *) pphy->pmac_info->pmac_group->pmac_info[0]->psys_info->tse_mac_base; + return IORD(&pmac_group_base->MDIO_ADDR1, 0); +} + + +/* @Function Description: Write MDIO address to the MDIO address1 register of first MAC within MAC group + * @API Type: Internal + * @param pmac Pointer to the alt_tse_phy_info structure + * @param mdio_address MDIO address to be written + * @return return SUCCESS + */ +alt_32 alt_tse_phy_wr_mdio_addr(alt_tse_phy_info *pphy, alt_u8 mdio_address) { + np_tse_mac *pmac_group_base = (np_tse_mac *) pphy->pmac_info->pmac_group->pmac_info[0]->psys_info->tse_mac_base; + IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdio_address); + + return SUCCESS; +} + +/** @Function Description - Write value of data with bit_length number of bits to MDIO register based on register location reg_num + * and start from bit location lsb_num. + * + * @API TYPE - Internal + * @param pphy pointer to alt_tse_phy_info structure + * @param reg_num location of MDIO register to be written. + * @param lsb_num least significant bit location of MDIO register to be written. + * @param bit_length number of bits to be written to the register. + * @param data data to be written to the register at specific bit location of register. + * @return SUCCESS + */ +alt_32 alt_tse_phy_wr_mdio_reg(alt_tse_phy_info *pphy, alt_u8 reg_num, alt_u8 lsb_num, alt_u8 bit_length, alt_u16 data) +{ + + alt_u16 temp_data; + alt_u16 bit_mask; + alt_32 i; + np_tse_mac *pmac = (np_tse_mac *) pphy->pmac_info->pmac_group->pmac_info[0]->psys_info->tse_mac_base; + + bit_mask = 0x00; + /* generate mask consist of bit_length number of 1 + * eg: bit_length = 3, bit_mask = 0b0000 0000 0000 0111 + */ + for(i = 0; i < bit_length; i++) + { + bit_mask <<= 1; + bit_mask |= 0x01; + } + + /* shifting mask to left by bit_num */ + bit_mask <<= lsb_num; + + /* read register data */ + temp_data = IORD(&pmac->mdio1, reg_num); + + /* clear bits to be written */ + temp_data &= ~bit_mask; + + /* OR-ed together corresponding bits data */ + temp_data |= ((data << lsb_num) & bit_mask); + + /* write data to MDIO register */ + IOWR(&pmac->mdio1, reg_num, temp_data); + + return SUCCESS; + +} + + + +/* @Function Description - Read bit_length number of bits from MDIO register based on register location reg_num + * and start from bit location lsb_num. + * + * @API TYPE - Internal + * @param pphy pointer to alt_tse_phy_info structure + * @param reg_num location of MDIO register to be read. + * @param lsb_num least significant bit location of MDIO register to be read. + * @param bit_length number of bits to be read from the register. + * @return data read from MDIO register + */ + +alt_u32 alt_tse_phy_rd_mdio_reg(alt_tse_phy_info *pphy, alt_u8 reg_num, alt_u8 lsb_num, alt_u8 bit_length) +{ + alt_u16 temp_data; + alt_u32 bit_mask; + alt_32 i; + np_tse_mac *pmac = (np_tse_mac *) pphy->pmac_info->pmac_group->pmac_info[0]->psys_info->tse_mac_base; + + bit_mask = 0x00; + /* generate mask consist of bit_length number of 1 + * eg: bit_length = 3, bit_mask = 0b0000 0000 0000 0111 + */ + for(i = 0; i < bit_length; i++) + { + bit_mask <<= 1; + bit_mask |= 0x01; + } + + /* read register data */ + temp_data = IORD(&pmac->mdio1, reg_num); + + /* shifting read data */ + temp_data >>= lsb_num; + + return (temp_data & bit_mask); +} + + + +/* @Function Description: Add supported PHY to profile + * @API Type: Internal + * @param pmac N/A + * @return Number of PHY in profile + * + * User might add their own PHY by calling alt_tse_phy_add_profile() + */ +alt_32 alt_tse_phy_add_profile_default() { + + /* supported PHY definition */ + + /* ------------------------------ */ + /* Marvell PHY on PHYWORKX board */ + /* ------------------------------ */ + + alt_tse_phy_profile MV88E1111 = {"Marvell 88E1111", /* Marvell 88E1111 */ + MV88E1111_OUI, /* OUI */ + MV88E1111_MODEL, /* Vender Model Number */ + MV88E1111_REV, /* Model Revision Number */ + 0x11, /* Location of Status Register */ + 14, /* Location of Speed Status */ + 13, /* Location of Duplex Status */ + 10, /* Location of Link Status */ + &marvell_phy_cfg /* Function pointer to configure Marvell PHY */ + }; + + + /* ---------------------------------- */ + /* Marvell Quad PHY on PHYWORKX board */ + /* ---------------------------------- */ + + alt_tse_phy_profile MV88E1145 = {"Marvell Quad PHY 88E1145", /* Marvell 88E1145 */ + MV88E1145_OUI, /* OUI */ + MV88E1145_MODEL, /* Vender Model Number */ + MV88E1145_REV, /* Model Revision Number */ + 0x11, /* Location of Status Register */ + 14, /* Location of Speed Status */ + 13, /* Location of Duplex Status */ + 10, /* Location of Link Status */ + &marvell_phy_cfg /* Function pointer to configure Marvell PHY */ + }; + + /* ------------------------------ */ + /* National PHY on PHYWORKX board */ + /* ------------------------------ */ + + alt_tse_phy_profile DP83865 = {"National DP83865", /* National DP83865 */ + DP83865_OUI, /* OUI */ + DP83865_MODEL, /* Vender Model Number */ + DP83865_REV, /* Model Revision Number */ + 0x11, /* Location of Status Register */ + 3, /* Location of Speed Status */ + 1, /* Location of Duplex Status */ + 2 /* Location of Link Status */ + }; + + /* -------------------------------------- */ + /* National 10/100 PHY on PHYWORKX board */ + /* -------------------------------------- */ + + alt_tse_phy_profile DP83848C = {"National DP83848C", /* National DP83848C */ + DP83848C_OUI, /* OUI */ + DP83848C_MODEL, /* Vender Model Number */ + DP83848C_REV, /* Model Revision Number */ + 0, /* Location of Status Register (ignored) */ + 0, /* Location of Speed Status (ignored) */ + 0, /* Location of Duplex Status (ignored) */ + 0, /* Location of Link Status (ignored) */ + 0, /* No function pointer configure National DP83848C */ + &DP83848C_link_status_read /* Function pointer to read from PHY specific status register */ + }; + + /* -------------------------------------- */ + /* Intel PHY on C10LP EVA board */ + /* -------------------------------------- */ + + alt_tse_phy_profile PEF7071 = {"Intel PEF7071", /* National DP83848C */ + PEF7071_OUI, /* OUI */ + PEF7071_MODEL, /* Vender Model Number */ + PEF7071_REV, /* Model Revision Number */ + 0, /* Location of Status Register */ + 0, /* Location of Speed Status */ + 0, /* Location of Duplex Status */ + 0, /* Location of Link Status */ + &PEF7071_config, /* configure PEF7071 */ + &PEF7071_link_status_read /* Function pointer to read from PHY specific status register */ + }; + + /* add supported PHY to profile */ + alt_tse_phy_add_profile(&MV88E1111); + alt_tse_phy_add_profile(&MV88E1145); + alt_tse_phy_add_profile(&DP83865); + alt_tse_phy_add_profile(&DP83848C); + alt_tse_phy_add_profile(&PEF7071); + + + return phy_profile_count; +} + +/* @Function Description: Display PHYs available in profile + * @API Type: Internal + * @param pmac N/A + * @return Number of PHY in profile + */ +alt_32 alt_tse_phy_print_profile() { + + alt_8 i; + /* display PHY in profile */ + tse_dprintf(6, "List of PHY profiles supported (Total profiles = %d)...\n", phy_profile_count); + + for(i = 0; i < phy_profile_count; i++) + { + tse_dprintf(6, "Profile No.%2d :\n", i); + tse_dprintf(6, "PHY Name : %s\n", pphy_profiles[i]->name); + + tse_dprintf(6, "PHY OUI : 0x%06x\n", (int)pphy_profiles[i]->oui); + tse_dprintf(6, "PHY Model Num. : 0x%02x\n", pphy_profiles[i]->model_number); + tse_dprintf(6, "PHY Rev. Num. : 0x%02x\n", pphy_profiles[i]->revision_number); + + tse_dprintf(6, "Status Register : 0x%02x\n", pphy_profiles[i]->status_reg_location); + + tse_dprintf(6, "Speed Bit : %d\n", pphy_profiles[i]->speed_lsb_location); + + tse_dprintf(6, "Duplex Bit : %d\n", pphy_profiles[i]->duplex_bit_location); + + tse_dprintf(6, "Link Bit : %d\n\n", pphy_profiles[i]->link_bit_location); + + } + + return phy_profile_count; +} + + + +/* @Function Description: Store information of all the MAC available in the system + * @API Type: Internal + * @param pmac N/A + * @return return SUCCESS + * return ALTERA_TSE_SYSTEM_DEF_ERROR if alt_tse_system_info structure definition error + */ +alt_32 alt_tse_mac_group_init() { + + alt_8 i; + alt_8 j; + + alt_tse_mac_group *pmac_group = 0; + alt_tse_mac_info *pmac_info = 0; + alt_tse_system_info *psys = 0; + + /* reset number of MAC group */ + mac_group_count = 0; + + /* loop through every alt_tse_system_info structure */ + for(i = 0; i < max_mac_system; i++) { + psys = &tse_mac_device[i]; + + if((psys->tse_msgdma_tx != 0) && (psys->tse_msgdma_rx != 0)) { + tse_dprintf(5, "INFO : TSE MAC %d found at address 0x%08x\n", mac_group_count, (int) psys->tse_mac_base); + + /* Allocate memory for the structure */ + pmac_group = (alt_tse_mac_group *) malloc(sizeof(alt_tse_mac_group)); + if(!pmac_group) { + tse_dprintf(1, "ERROR : Unable to allocate memory for MAC Group[%d]\n", mac_group_count); + return ALTERA_TSE_MALLOC_FAILED; + } + + /* Non-multi-channel MAC considered as 1 channel */ + if(psys->tse_multichannel_mac) { + pmac_group->channel = psys->tse_num_of_channel; + tse_dprintf(6, "INFO : Multi Channel = Yes\n"); + tse_dprintf(6, "INFO : Number of channel = %d\n", pmac_group->channel); + tse_dprintf(6, "INFO : MDIO Shared = Yes\n"); + } + else if(psys->tse_mdio_shared) { + pmac_group->channel = psys->tse_number_of_mac_mdio_shared; + tse_dprintf(6, "INFO : Multi Channel = No\n"); + tse_dprintf(6, "INFO : MDIO Shared = Yes\n"); + tse_dprintf(6, "INFO : Number of MAC Share MDIO = %d\n", pmac_group->channel); + } + else { + pmac_group->channel = 1; + tse_dprintf(6, "INFO : Multi Channel = No\n"); + tse_dprintf(6, "INFO : MDIO Shared = No\n"); + } + + for(j = 0; j < pmac_group->channel; j++) { + /* Allocate memory for the structure */ + pmac_info = (alt_tse_mac_info *) malloc(sizeof(alt_tse_mac_info)); + if(!pmac_info) { + tse_dprintf(1, "ERROR : Unable to allocate memory for MAC Group[%d]->pmac_info[%d]\n", mac_group_count, j); + return ALTERA_TSE_MALLOC_FAILED; + } + + pmac_info->pmac_group = pmac_group; + + pmac_info->pphy_info = 0; + + pmac_info->psys_info = &tse_mac_device[i + j]; + + /* check to make sure the alt_tse_system_info defined correctly or has been defined */ + if((pmac_info->psys_info->tse_msgdma_tx == 0) || (pmac_info->psys_info->tse_msgdma_rx == 0)){ + tse_dprintf(2, "ERROR : tse_mac_device[%d] does not defined correctly!\n", i + j); + return ALTERA_TSE_SYSTEM_DEF_ERROR; + } + + /* MAC type detection */ + if(pmac_info->psys_info->tse_en_maclite) { + if(pmac_info->psys_info->tse_maclite_gige) { + pmac_info->mac_type = ALTERA_TSE_MACLITE_1000; + } + else { + pmac_info->mac_type = ALTERA_TSE_MACLITE_10_100; + } + } + else { + pmac_info->mac_type = ALTERA_TSE_FULL_MAC; + } + + if((pmac_info->psys_info->tse_mdio_shared) && (!pmac_info->psys_info->tse_multichannel_mac)){ + tse_dprintf(6, "INFO : MAC %2d Address = 0x%08x\n", j, (int) pmac_info->psys_info->tse_mac_base); + tse_dprintf(6, "INFO : MAC %2d Device = tse_mac_device[%d]\n", j, i + j); + + switch(pmac_info->mac_type) { + case ALTERA_TSE_MACLITE_1000: + tse_dprintf(6, "INFO : MAC %2d Type = %s\n", j, "1000 Mbps Small MAC"); + break; + case ALTERA_TSE_MACLITE_10_100: + tse_dprintf(6, "INFO : MAC %2d Type = %s\n", j, "10/100 Mbps Small MAC"); + break; + case ALTERA_TSE_FULL_MAC: + tse_dprintf(6, "INFO : MAC %2d Type = %s\n", j, "10/100/1000 Ethernet MAC"); + break; + default : + tse_dprintf(6, "INFO : MAC %2d Type = %s\n", j, "Unknown"); + break; + } + + if(pmac_info->psys_info->tse_pcs_ena) { + tse_dprintf(6, "INFO : PCS %2d Enable = %s\n", j, pmac_info->psys_info->tse_pcs_ena ? "Yes" : "No"); + tse_dprintf(6, "INFO : PCS %2d SGMII Enable = %s\n", j, pmac_info->psys_info->tse_pcs_sgmii ? "Yes" : "No"); + } + } + else { + /* display only once for all MAC, except shared MDIO MACs */ + if(j == 0) { + switch(pmac_info->mac_type) { + case ALTERA_TSE_MACLITE_1000: + tse_dprintf(6, "INFO : MAC Type = %s\n", "1000 Mbps Small MAC"); + break; + case ALTERA_TSE_MACLITE_10_100: + tse_dprintf(6, "INFO : MAC Type = %s\n", "10/100 Mbps Small MAC"); + break; + case ALTERA_TSE_FULL_MAC: + tse_dprintf(6, "INFO : MAC Type = %s\n", "10/100/1000 Ethernet MAC"); + break; + default : + tse_dprintf(6, "INFO : MAC Type = %s\n", "Unknown"); + break; + } + + if(pmac_info->psys_info->tse_pcs_ena) { + tse_dprintf(6, "INFO : PCS Enable = %s\n", pmac_info->psys_info->tse_pcs_ena ? "Yes" : "No"); + tse_dprintf(6, "INFO : PCS SGMII Enable = %s\n", pmac_info->psys_info->tse_pcs_sgmii ? "Yes" : "No"); + } + } + + if(pmac_info->psys_info->tse_multichannel_mac) { + tse_dprintf(6, "INFO : Channel %2d Address = 0x%08x\n", j, (int) pmac_info->psys_info->tse_mac_base); + tse_dprintf(6, "INFO : Channel %2d Device = tse_mac_device[%d]\n", j, i + j); + } + else { + tse_dprintf(6, "INFO : MAC Address = 0x%08x\n", (int) pmac_info->psys_info->tse_mac_base); + tse_dprintf(6, "INFO : MAC Device = tse_mac_device[%d]\n", i + j); + } + } + + /* store the pointer in MAC group variable for the detected channel */ + pmac_group->pmac_info[j] = pmac_info; + } + + /* store the pointer in global variable */ + pmac_groups[mac_group_count] = pmac_group; + + mac_group_count++; + + /* skip for subsequent Multi-channel MAC */ + i += (pmac_group->channel - 1); + + } + } + return SUCCESS; +} + + +/* @Function Description: Store information of all the PHYs connected to MAC to phy_list + * @API Type: Internal + * @param pmac_group Pointer to the TSE MAC grouping structure + * @return Number of PHY not in profile, return ALTERA_TSE_MALLOC_FAILED if memory allocation failed + */ +alt_32 alt_tse_mac_get_phy(alt_tse_mac_group *pmac_group) { + + alt_32 phyid; + alt_32 phyid2 = 0; + alt_u8 phyadd; + + alt_u32 oui; + alt_u8 model_number; + alt_u8 revision_number; + + alt_32 i; + + alt_u8 is_phy_in_profile; + alt_32 return_value = 0; + + alt_8 phy_info_count = 0; + + alt_tse_phy_info *pphy = 0; + alt_tse_mac_info *pmac_info = 0; + alt_tse_system_info *psys = 0; + + np_tse_mac *pmac_group_base = (np_tse_mac *) pmac_group->pmac_info[0]->psys_info->tse_mac_base; + + /* Record previous MDIO address, to be restored at the end of function */ + alt_32 mdioadd_prev = IORD(&pmac_group_base->MDIO_ADDR1, 0); + + /* get index of the pointers in pointer array list */ + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + + /* loop all valid PHY address to look for connected PHY */ + for (phyadd = 0x00; phyadd < pmac_group->channel /*0x20*/; phyadd++) //M.D. 2019-08-05: don't look at unused PHYs + { + IOWR(&pmac_group_base->MDIO_ADDR1, 0, phyadd); + phyid = IORD(&pmac_group_base->mdio1.PHY_ID1,0); // read PHY ID + phyid2 = IORD(&pmac_group_base->mdio1.PHY_ID2,0); // read PHY ID + + /* PHY found */ + if (phyid != phyid2) + { + pphy = (alt_tse_phy_info *) malloc(sizeof(alt_tse_phy_info)); + if(!pphy) { + tse_dprintf(1, "ERROR : Unable to allocate memory for phy_info[%d.%d]\n", mac_group_index, phy_info_count); + return ALTERA_TSE_MALLOC_FAILED; + } + + /* store PHY address */ + pphy->mdio_address = phyadd; + + /* get oui, model number, and revision number from PHYID and PHYID2 */ + oui = (phyid << 6) | ((phyid2 >> 10) & 0x3f); + model_number = (phyid2 >> 4) & 0x3f; + revision_number = phyid2 & 0x0f; + + /* map the PHY with PHY in profile */ + is_phy_in_profile = 0; + for(i = 0; i < phy_profile_count; i++) { + + /* if PHY match with PHY in profile */ + if((pphy_profiles[i]->oui == oui) && (pphy_profiles[i]->model_number == model_number)) + { + pphy->pphy_profile = pphy_profiles[i]; + + /* PHY found, add it to phy_list */ + tse_dprintf(5, "INFO : PHY %s found at PHY address 0x%02x of MAC Group[%d]\n", pphy_profiles[i]->name, phyadd, mac_group_index); + is_phy_in_profile = 1; + break; + } + } + /* PHY not found in PHY profile */ + if(is_phy_in_profile == 0) { + pphy->pphy_profile = 0; + tse_dprintf(3, "WARNING : Unknown PHY found at PHY address 0x%02x of MAC Group[%d]\n", phyadd, mac_group_index); + tse_dprintf(3, "WARNING : Please add PHY information to PHY profile\n"); + return_value++; + } + + tse_dprintf(6, "INFO : PHY OUI = 0x%06x\n", (int) oui); + tse_dprintf(6, "INFO : PHY Model Number = 0x%02x\n", model_number); + tse_dprintf(6, "INFO : PHY Revision Number = 0x%01x\n", revision_number); + + /* map the detected PHY to connected MAC */ + if(alt_tse_mac_associate_phy(pmac_group, pphy) == TSE_PHY_MAP_SUCCESS) { + + pmac_info = pphy->pmac_info; + psys = pmac_info->psys_info; + + /* Disable PHY loopback to allow Auto-Negotiation completed */ + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_LOOPBACK, 1, 0); // disable PHY loopback + + /* Reset auto-negotiation advertisement */ + alt_tse_phy_set_adv_1000(pphy, 1); + alt_tse_phy_set_adv_100(pphy, 1); + alt_tse_phy_set_adv_10(pphy, 1); + + /* check link connection for this PHY */ + alt_tse_phy_restart_an(pphy, ALTERA_CHECKLINK_TIMEOUT_THRESHOLD); + + /* Perform additional setting if there is any */ + /* Profile specific */ + if(pphy->pphy_profile) { + if(pphy->pphy_profile->phy_cfg) { + tse_dprintf(6, "INFO : Applying additional PHY configuration of %s\n", pphy->pphy_profile->name); + pphy->pphy_profile->phy_cfg(pmac_group_base); + } + } + + /* Initialize PHY, call user's function pointer in alt_tse_system_info structure */ + /* Individual PHY specific */ + if(psys->tse_phy_cfg) { + tse_dprintf(6, "INFO : Applying additional user PHY configuration\n"); + psys->tse_phy_cfg(pmac_group_base); + } + } + + tse_dprintf(6, "\n"); + + phy_info_count++; + } + } + + TK_SLEEP(100); //Wait a little bit for PHY reset after specific configuration + + + /* check to verify the number of connected PHY match the number of channel */ + if(pmac_group->channel != phy_info_count) { + if(phy_info_count == 0) { + tse_dprintf(2, "ERROR : MAC Group[%d] - No PHY connected!\n", mac_group_index); + } + else { + tse_dprintf(3, "WARNING : MAC Group[%d] - Number of PHY connected is not equal to the number of channel, Number of PHY : %d, Channel : %d\n", mac_group_index, phy_info_count, pmac_group->channel); + } + } + + /* Restore previous MDIO address */ + IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdioadd_prev); + + return return_value; +} + + + + +/* @Function Description: Associate the PHYs connected to the structure in alt_tse_system_info.h + * @API Type: Internal + * @param pmac_group Pointer to the TSE MAC grouping structure + * @param pphy Pointer to the TSE PHY info structure which hold information of PHY + * @return return TSE_PHY_MAP_ERROR if mapping error + * return TSE_PHY_MAP_SUCCESS otherwise + */ +alt_32 alt_tse_mac_associate_phy(alt_tse_mac_group *pmac_group, alt_tse_phy_info *pphy) { + + alt_32 i; + alt_32 return_value = TSE_PHY_MAP_SUCCESS; + + alt_u8 is_mapped; + + alt_tse_system_info *psys = 0; + alt_tse_mac_info *pmac_info = 0; + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = 0; + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + alt_8 sys_info_index = 0; + + is_mapped = 0; + + for(i = 0; i < pmac_group->channel; i++) { + pmac_info = pmac_group->pmac_info[i]; + psys = pmac_info->psys_info; + + /* map according to the PHY address in alt_tse_system_info.h */ + if(psys->tse_phy_mdio_address == pphy->mdio_address) { + mac_info_index = alt_tse_get_mac_info_index(pmac_info); + sys_info_index = alt_tse_get_system_index(psys); + + pmac_info->pphy_info = pphy; + pphy->pmac_info = pmac_info; + tse_dprintf(5, "INFO : PHY[%d.%d] - Explicitly mapped to tse_mac_device[%d]\n", mac_group_index, mac_info_index, sys_info_index); + is_mapped = 1; + break; + } + } + + /* if not yet map, it will automatically mapped to the first TSE device encountered with tse_phy_mdio_address = TSE_PHY_AUTO_ADDRESS */ + if(is_mapped == 0) { + for(i = 0; i < pmac_group->channel; i++) { + pmac_info = pmac_group->pmac_info[i]; + psys = pmac_info->psys_info; + + /* alt_tse_system_info structure definition error */ + if((psys->tse_msgdma_tx == 0) || (psys->tse_msgdma_rx == 0)){ + continue; + } + + if(psys->tse_phy_mdio_address == TSE_PHY_AUTO_ADDRESS) { + mac_info_index = alt_tse_get_mac_info_index(pmac_info); + sys_info_index = alt_tse_get_system_index(psys); + + pmac_info->pphy_info = pphy; + pphy->pmac_info = pmac_info; + psys->tse_phy_mdio_address = pphy->mdio_address; + tse_dprintf(5, "INFO : PHY[%d.%d] - Automatically mapped to tse_mac_device[%d]\n", mac_group_index, mac_info_index, sys_info_index); + is_mapped = 1; + break; + } + } + } + + /* Still cannot find any matched MAC-PHY */ + if(is_mapped == 0) { + pphy->pmac_info = 0; + tse_dprintf(2, "WARNING : PHY[%d.X] - Mapping of PHY to MAC failed! Make sure the PHY address is defined correctly in tse_mac_device[] structure, and number of PHYs connected is equivalent to number of channel\n", mac_group_index); + return_value = TSE_PHY_MAP_ERROR; + } + + return return_value; +} + + + + +/* @Function Description: Configure operating mode of Altera PCS if available + * @API Type: Internal + * @param pmac_info pointer to MAC info variable + * @return return SUCCESS + */ +alt_32 alt_tse_phy_cfg_pcs(alt_tse_mac_info *pmac_info) { + + alt_tse_system_info *psys = pmac_info->psys_info; + np_tse_mac *pmac = (np_tse_mac *) psys->tse_mac_base; + alt_tse_mac_group *pmac_group = pmac_info->pmac_group; + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info); + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + + if(psys->tse_pcs_ena) { + tse_dprintf(5, "INFO : PCS[%d.%d] - Configuring PCS operating mode\n", mac_group_index, mac_info_index); + + alt_32 data = IORD(&pmac->mdio0.CONTROL, ALTERA_TSE_PCS_IF_MODE); + + if(psys->tse_pcs_sgmii) { + tse_dprintf(5, "INFO : PCS[%d.%d] - PCS SGMII mode enabled\n", mac_group_index, mac_info_index); + IOWR(&pmac->mdio0.CONTROL, ALTERA_TSE_PCS_IF_MODE, data | 0x03); + } + else { + tse_dprintf(5, "INFO : PCS[%d.%d] - PCS SGMII mode disabled\n", mac_group_index, mac_info_index); + IOWR(&pmac->mdio0.CONTROL, ALTERA_TSE_PCS_IF_MODE, data & ~0x03); + } + } + + return SUCCESS; +} + + + +/* @Function Description: Detect and initialize all the PHYs connected + * @API Type: Internal + * @param pmac N/A + * @return SUCCESS + */ +alt_32 alt_tse_phy_init() { + alt_8 i = 0; + alt_8 j = 0; + + alt_tse_mac_group *pmac_group = 0; + alt_tse_mac_info *pmac_info = 0; + + /* add supported PHYs */ + alt_tse_phy_add_profile_default(); + + /* display PHY in profile */ + alt_tse_phy_print_profile(); + + alt_tse_mac_group_init(); + + /* initialize for each TSE MAC */ + /* run once only for multi-channel MAC */ + for(i = 0; i < mac_group_count; i++) { + pmac_group = pmac_groups[i]; + + if(pmac_group->pmac_info[0]->psys_info->tse_use_mdio) { + + /* get connected PHYs */ + alt_tse_mac_get_phy(pmac_group); + } + else { + tse_dprintf(3, "WARNING : MAC Groups[%d]->pmac_info[%d] MDIO is not used, unable to run PHY detection\n", i, j); + } + + /* Configure PCS mode if MAC+PCS system is used */ + for(j = 0; j < pmac_group->channel; j++) { + pmac_info = pmac_group->pmac_info[j]; + + alt_tse_phy_cfg_pcs(pmac_info); + } + } + + return SUCCESS; +} + + +/* @Function Description: Restart Auto-Negotiation for the PHY + * @API Type: Internal + * @param pphy Pointer to the alt_tse_phy_info structure + * timeout_threshold timeout value of Auto-Negotiation + * @return return TSE_PHY_AN_COMPLETE if success + * return TSE_PHY_AN_NOT_COMPLETE if auto-negotiation not completed + * return TSE_PHY_AN_NOT_CAPABLE if the PHY not capable for AN + */ +alt_32 alt_tse_phy_restart_an(alt_tse_phy_info *pphy, alt_u32 timeout_threshold) { + + /* pointer to MAC associated and MAC group */ + alt_tse_mac_info *pmac_info = pphy->pmac_info; + alt_tse_mac_group *pmac_group = pmac_info->pmac_group; + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info); + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + + /* Record previous MDIO address, to be restored at the end of function */ + alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); + + /* write PHY address to MDIO to access the i-th PHY */ + alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address); + + if(!alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_ABILITY, 1)) { + tse_dprintf(3, "WARNING : PHY[%d.%d] - PHY not capable for Auto-Negotiation\n", mac_group_index, mac_info_index); + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + + return TSE_PHY_AN_NOT_CAPABLE; + } + + /* enable Auto-Negotiation */ + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_AN_ENA, 1, 1); + + /* send PHY reset command */ + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_RESTART_AN, 1, 1); + tse_dprintf(5, "INFO : PHY[%d.%d] - Restart Auto-Negotiation, checking PHY link...\n", mac_group_index, mac_info_index); + + alt_32 timeout = 0; + while(alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_COMPLETE, 1) == 0 ){ + if(timeout++ > timeout_threshold) { + tse_dprintf(4, "WARNING : PHY[%d.%d] - Auto-Negotiation FAILED\n", mac_group_index, mac_info_index); + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + + return TSE_PHY_AN_NOT_COMPLETE; + } + usleep(1000); + } + tse_dprintf(5, "INFO : PHY[%d.%d] - Auto-Negotiation PASSED\n", mac_group_index, mac_info_index); + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + + return TSE_PHY_AN_COMPLETE; +} + + +/* @Function Description: Check link status of PHY and start Auto-Negotiation if it has not yet done + * @API Type: Internal + * @param pphy Pointer to the alt_tse_phy_info structure + * timeout_threshold timeout value of Auto-Negotiation + * @return return TSE_PHY_AN_COMPLETE if success + * return TSE_PHY_AN_NOT_COMPLETE if auto-negotiation not completed + */ +alt_32 alt_tse_phy_check_link(alt_tse_phy_info *pphy, alt_u32 timeout_threshold) +{ + alt_32 timeout=0; + + /* pointer to MAC associated and MAC group */ + alt_tse_mac_info *pmac_info = pphy->pmac_info; + alt_tse_mac_group *pmac_group = pmac_info->pmac_group; + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info); + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + + /* Record previous MDIO address, to be restored at the end of function */ + alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); + + /* write PHY address to MDIO to access the i-th PHY */ + alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address); + + /* if Auto-Negotiation not complete yet, then restart Auto-Negotiation */ + /* Issue a PHY reset here and wait for the link + * autonegotiation complete again... this takes several SECONDS(!) + * so be very careful not to do it frequently + * perform this when PHY is configured in loopback or has no link yet. + */ + tse_dprintf(5, "INFO : PHY[%d.%d] - Checking link...\n", mac_group_index, mac_info_index); + while( ((alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_LOOPBACK, 1)) != 0) || + ((alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_COMPLETE, 1)) == 0) ) + { + if (timeout++ > timeout_threshold) + { + tse_dprintf(5, "INFO : PHY[%d.%d] - Link not yet established, restart auto-negotiation...\n", mac_group_index, mac_info_index); + /* restart Auto-Negotiation */ + /* if Auto-Negotiation still cannot complete, then go to next PHY */ + if(alt_tse_phy_restart_an(pphy, timeout_threshold) == TSE_PHY_AN_NOT_COMPLETE) + { + tse_dprintf(3, "WARNING : PHY[%d.%d] - Link could not established\n", mac_group_index, mac_info_index); + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + + return TSE_PHY_AN_NOT_COMPLETE; + } + } + usleep(1000); + } + tse_dprintf(5, "INFO : PHY[%d.%d] - Link established\n", mac_group_index, mac_info_index); + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + + return TSE_PHY_AN_COMPLETE; +} + +/* @Function Description: Get link capability of PHY and link partner + * @API Type: Internal + * @param pmac Pointer to the alt_tse_phy_info structure + * @return return TSE_PHY_AN_COMPLETE if success + * return TSE_PHY_AN_NOT_COMPLETE if auto-negotiation not completed + * return TSE_PHY_AN_NOT_CAPABLE if the PHY not capable for AN + */ +alt_32 alt_tse_phy_get_cap(alt_tse_phy_info *pphy) { + alt_32 return_value = TSE_PHY_AN_COMPLETE; + + /* pointer to MAC associated and MAC group */ + alt_tse_mac_info *pmac_info = pphy->pmac_info; + alt_tse_mac_group *pmac_group = pmac_info->pmac_group; + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info); + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + + /* Record previous MDIO address, to be restored at the end of function */ + alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); + + /* write PHY address to MDIO to access the i-th PHY */ + alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address); + + if(!alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_ABILITY, 1)) { + tse_dprintf(3, "WARNING : PHY[%d.%d] - PHY not capable for Auto-Negotiation\n", mac_group_index, mac_info_index); + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + + return TSE_PHY_AN_NOT_CAPABLE; + } + + /* check whether link has been established */ + alt_tse_phy_restart_an(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD); + + if(alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_COMPLETE, 1) == 0) { + return_value = TSE_PHY_AN_NOT_COMPLETE; + } + + /* get PHY capabilities */ + pphy->link_capability.cap_1000_base_x_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_X_FULL, 1); + pphy->link_capability.cap_1000_base_x_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_X_HALF, 1); + pphy->link_capability.cap_1000_base_t_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_T_FULL, 1); + pphy->link_capability.cap_1000_base_t_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_T_HALF, 1); + + pphy->link_capability.cap_100_base_t4 = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_T4, 1); + pphy->link_capability.cap_100_base_x_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_X_FULL, 1); + pphy->link_capability.cap_100_base_x_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_X_HALF, 1); + pphy->link_capability.cap_100_base_t2_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_T2_FULL, 1); + pphy->link_capability.cap_100_base_t2_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_T2_HALF, 1); + pphy->link_capability.cap_10_base_t_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_10BASE_T_FULL, 1); + pphy->link_capability.cap_10_base_t_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_10BASE_T_HALF, 1); + + /* get link partner capability */ + pphy->link_capability.lp_1000_base_t_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_STATUS, TSE_PHY_MDIO_1000BASE_T_STATUS_LP_FULL_ADV, 1); + pphy->link_capability.lp_1000_base_t_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_STATUS, TSE_PHY_MDIO_1000BASE_T_STATUS_LP_HALF_ADV, 1); + + pphy->link_capability.lp_100_base_t4 = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_100BASE_T4, 1); + pphy->link_capability.lp_100_base_tx_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_100BASE_TX_FULL, 1); + pphy->link_capability.lp_100_base_tx_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_100BASE_TX_HALF, 1); + pphy->link_capability.lp_10_base_tx_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_10BASE_TX_FULL, 1); + pphy->link_capability.lp_10_base_tx_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_10BASE_TX_HALF, 1); + + tse_dprintf(6, "INFO : PHY[%d.%d] - Capability of PHY :\n", mac_group_index, mac_info_index); + tse_dprintf(6, "INFO : 1000 Base-X Full Duplex = %d\n", pphy->link_capability.cap_1000_base_x_full); + tse_dprintf(6, "INFO : 1000 Base-X Half Duplex = %d\n", pphy->link_capability.cap_1000_base_x_half); + tse_dprintf(6, "INFO : 1000 Base-T Full Duplex = %d\n", pphy->link_capability.cap_1000_base_t_full); + tse_dprintf(6, "INFO : 1000 Base-T Half Duplex = %d\n", pphy->link_capability.cap_1000_base_t_half); + tse_dprintf(6, "INFO : 100 Base-T4 = %d\n", pphy->link_capability.cap_100_base_t4); + tse_dprintf(6, "INFO : 100 Base-X Full Duplex = %d\n", pphy->link_capability.cap_100_base_x_full); + tse_dprintf(6, "INFO : 100 Base-X Half Duplex = %d\n", pphy->link_capability.cap_100_base_x_half); + tse_dprintf(6, "INFO : 100 Base-T2 Full Duplex = %d\n", pphy->link_capability.cap_100_base_t2_full); + tse_dprintf(6, "INFO : 100 Base-T2 Half Duplex = %d\n", pphy->link_capability.cap_100_base_t2_half); + tse_dprintf(6, "INFO : 10 Base-T Full Duplex = %d\n", pphy->link_capability.cap_10_base_t_full); + tse_dprintf(6, "INFO : 10 Base-T Half Duplex = %d\n", pphy->link_capability.cap_10_base_t_half); + tse_dprintf(6, "\n"); + + tse_dprintf(6, "INFO : PHY[%d.%d] - Link Partner Capability :\n", mac_group_index, mac_info_index); + tse_dprintf(6, "INFO : 1000 Base-T Full Duplex = %d\n", pphy->link_capability.lp_1000_base_t_full); + tse_dprintf(6, "INFO : 1000 Base-T Half Duplex = %d\n", pphy->link_capability.lp_1000_base_t_half); + tse_dprintf(6, "INFO : 100 Base-T4 = %d\n", pphy->link_capability.lp_100_base_t4); + tse_dprintf(6, "INFO : 100 Base-TX Full Duplex = %d\n", pphy->link_capability.lp_100_base_tx_full); + tse_dprintf(6, "INFO : 100 Base-TX Half Duplex = %d\n", pphy->link_capability.lp_100_base_tx_half); + tse_dprintf(6, "INFO : 10 Base-TX Full Duplex = %d\n", pphy->link_capability.lp_10_base_tx_full); + tse_dprintf(6, "INFO : 10 Base-TX Half Duplex = %d\n", pphy->link_capability.lp_10_base_tx_half); + tse_dprintf(6, "\n"); + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + + return return_value; + +} + + +/* @Function Description: Set the advertisement of PHY for 1000 Mbps + * @API Type: Internal + * @param pmac Pointer to the alt_tse_phy_info structure + * enable set Enable = 1 to advertise this speed if the PHY capable + * set Enable = 0 to disable advertise of this speed + * @return return SUCCESS + */ +alt_32 alt_tse_phy_set_adv_1000(alt_tse_phy_info *pphy, alt_u8 enable) { + alt_u8 cap; + + /* pointer to MAC associated and MAC group */ + alt_tse_mac_info *pmac_info = pphy->pmac_info; + alt_tse_mac_group *pmac_group = pmac_info->pmac_group; + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info); + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + + /* Record previous MDIO address, to be restored at the end of function */ + alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); + + /* write PHY address to MDIO to access the i-th PHY */ + alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address); + + /* if enable = 1, set advertisement based on PHY capability */ + if(enable) { + cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_T_FULL, 1); + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_CTRL, TSE_PHY_MDIO_1000BASE_T_CTRL_FULL_ADV, 1, cap); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 1000 Base-T Full Duplex set to %d\n", mac_group_index, mac_info_index, cap); + + /* 1000 Mbps Half duplex not supported by TSE MAC */ + cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_T_HALF, 1); + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_CTRL, TSE_PHY_MDIO_1000BASE_T_CTRL_HALF_ADV, 1, cap); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 1000 Base-T Half Duplex set to %d\n", mac_group_index, mac_info_index, cap); + } + /* else disable advertisement of this speed */ + else { + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_CTRL, TSE_PHY_MDIO_1000BASE_T_CTRL_FULL_ADV, 1, 0); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 1000 Base-T Full Duplex set to %d\n", mac_group_index, mac_info_index, 0); + + /* 1000 Mbps Half duplex not supported by TSE MAC */ + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_CTRL, TSE_PHY_MDIO_1000BASE_T_CTRL_HALF_ADV, 1, 0); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement 1000 Base-T half Duplex set to %d\n", mac_group_index, mac_info_index, 0); + } + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + + return SUCCESS; +} + + +/* @Function Description: Set the advertisement of PHY for 100 Mbps + * @API Type: Internal + * @param pmac Pointer to the alt_tse_phy_info structure + * enable set Enable = 1 to advertise this speed if the PHY capable + * set Enable = 0 to disable advertise of this speed + * @return return SUCCESS + */ +alt_32 alt_tse_phy_set_adv_100(alt_tse_phy_info *pphy, alt_u8 enable) { + alt_u8 cap; + + /* pointer to MAC associated and MAC group */ + alt_tse_mac_info *pmac_info = pphy->pmac_info; + alt_tse_mac_group *pmac_group = pmac_info->pmac_group; + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info); + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + + /* Record previous MDIO address, to be restored at the end of function */ + alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); + + /* write PHY address to MDIO to access the i-th PHY */ + alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address); + + /* if enable = 1, set advertisement based on PHY capability */ + if(enable) { + cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_T4, 1); + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_T4, 1, cap); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 100 Base-T4 set to %d\n", mac_group_index, mac_info_index, cap); + + cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_X_FULL, 1); + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_TX_FULL, 1, cap); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 100 Base-TX Full Duplex set to %d\n", mac_group_index, mac_info_index, cap); + + cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_X_HALF, 1); + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_TX_HALF, 1, cap); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 100 Base-TX Half Duplex set to %d\n", mac_group_index, mac_info_index, cap); + } + /* else disable advertisement of this speed */ + else { + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_T4, 1, 0); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 100 Base-T4 set to %d\n", mac_group_index, mac_info_index, 0); + + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_TX_FULL, 1, 0); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 100 Base-TX Full Duplex set to %d\n", mac_group_index, mac_info_index, 0); + + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_TX_HALF, 1, 0); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 100 Base-TX Half Duplex set to %d\n", mac_group_index, mac_info_index, 0); + } + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + + return SUCCESS; +} + + +/* @Function Description: Set the advertisement of PHY for 10 Mbps + * @API Type: Internal + * @param pmac Pointer to the alt_tse_phy_info structure + * enable set Enable = 1 to advertise this speed if the PHY capable + * set Enable = 0 to disable advertise of this speed + * @return return SUCCESS + */ +alt_32 alt_tse_phy_set_adv_10(alt_tse_phy_info *pphy, alt_u8 enable) { + alt_u8 cap; + + /* pointer to MAC associated and MAC group */ + alt_tse_mac_info *pmac_info = pphy->pmac_info; + alt_tse_mac_group *pmac_group = pmac_info->pmac_group; + + /* get index of the pointers in pointer array list */ + int mac_info_index = alt_tse_get_mac_info_index(pmac_info); + int mac_group_index = alt_tse_get_mac_group_index(pmac_group); + + /* Record previous MDIO address, to be restored at the end of function */ + int mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); + + /* write PHY address to MDIO to access the i-th PHY */ + alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address); + + /* if enable = 1, set advertisement based on PHY capability */ + if(enable) { + cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_10BASE_T_FULL, 1); + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_10BASE_TX_FULL, 1, cap); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 10 Base-TX Full Duplex set to %d\n", mac_group_index, mac_info_index, cap); + + cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_10BASE_T_HALF, 1); + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_10BASE_TX_HALF, 1, cap); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 10 Base-TX Half Duplex set to %d\n", mac_group_index, mac_info_index, cap); + } + /* else disable advertisement of this speed */ + else { + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_10BASE_TX_FULL, 1, 0); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 10 Base-TX Full Duplex set to %d\n", mac_group_index, mac_info_index, 0); + + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_10BASE_TX_HALF, 1, 0); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 10 Base-TX Half Duplex set to %d\n", mac_group_index, mac_info_index, 0); + } + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + + return SUCCESS; +} + + + + +/* @Function Description: Get the common speed supported by all PHYs connected to the MAC within the same group + * @API Type: Internal + * @param pmac_group Pointer to the TSE MAC Group structure which group all the MACs that should use the same speed + * @return common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if no common speed found + */ +alt_32 alt_tse_phy_get_common_speed(alt_tse_mac_group *pmac_group) { + + alt_32 i; + alt_u8 common_1000 = 1; + alt_u8 common_100 = 1; + alt_u8 common_10 = 1; + + alt_32 common_speed; + + alt_u8 none_an_complete = 1; + + alt_tse_mac_info *pmac_info = 0; + alt_tse_phy_info *pphy = 0; + + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + + /* reset Auto-Negotiation advertisement */ + for(i = 0; i < pmac_group->channel; i++) { + pmac_info = pmac_group->pmac_info[i]; + pphy = pmac_info->pphy_info; + + /* run only if PHY connected */ + if(pphy) { + alt_tse_phy_set_adv_1000(pphy, 1); + alt_tse_phy_set_adv_100(pphy, 1); + alt_tse_phy_set_adv_10(pphy, 1); + } + tse_dprintf(6, "\n"); + } + + /* loop through every PHY connected */ + for(i = 0; i < pmac_group->channel; i++) { + + pmac_info = pmac_group->pmac_info[i]; + pphy = pmac_info->pphy_info; + + /* if no PHY connected */ + if(!pphy) { + continue; + } + + /* get PHY capability */ + /* skip for PHY with Auto-Negotiation not completed */ + if(alt_tse_phy_get_cap(pphy) != TSE_PHY_AN_COMPLETE) { + continue; + } + + none_an_complete = 0; + + /* Small MAC */ + if(pmac_info->mac_type == ALTERA_TSE_MACLITE_10_100) { + common_1000 = 0; + } + else if(pmac_info->mac_type == ALTERA_TSE_MACLITE_1000) { + common_100 = 0; + common_10 = 0; + } + + /* get common capabilities for all PHYs and link partners */ + common_1000 &= ((pphy->link_capability.cap_1000_base_t_full & pphy->link_capability.lp_1000_base_t_full)); + //(pphy->link_capability.cap_1000_base_t_half & pphy->link_capability.lp_1000_base_t_half)); + common_100 &= ((pphy->link_capability.cap_100_base_x_full & pphy->link_capability.lp_100_base_tx_full) | + (pphy->link_capability.cap_100_base_x_half & pphy->link_capability.lp_100_base_tx_half) | + (pphy->link_capability.cap_100_base_t4 & pphy->link_capability.lp_100_base_t4)); + common_10 &= ((pphy->link_capability.cap_10_base_t_full & pphy->link_capability.lp_10_base_tx_full) | + (pphy->link_capability.cap_10_base_t_half & pphy->link_capability.lp_10_base_tx_half)); + + } + + /* get common speed based on capabilities */ + if(none_an_complete == 1) { + common_speed = TSE_PHY_SPEED_NO_COMMON; + tse_dprintf(2, "ERROR : MAC Group[%d] - None of the PHYs Auto-Negotiation completed!\n", mac_group_index); + } + else if(common_1000) { + common_speed = TSE_PHY_SPEED_1000; + tse_dprintf(5, "INFO : MAC Group[%d] - Common Speed : %d Mbps\n", mac_group_index, 1000); + } + else if(common_100) { + common_speed = TSE_PHY_SPEED_100; + tse_dprintf(5, "INFO : MAC Group[%d] - Common Speed : %d Mbps\n", mac_group_index, 100); + } + else if(common_10) { + common_speed = TSE_PHY_SPEED_10; + tse_dprintf(5, "INFO : MAC Group[%d] - Common Speed : %d Mbps\n", mac_group_index, 10); + } + else { + common_speed = TSE_PHY_SPEED_NO_COMMON; + tse_dprintf(2, "ERROR : MAC Group[%d] - No common speed at all!\n", mac_group_index); } + + return common_speed; +} + + +/* @Function Description: Set the common speed to all PHYs connected to the MAC within the same group + * @API Type: Internal + * @param pmac_group Pointer to the TSE MAC Group structure which group all the MACs that should use the same speed + * common_speed common speed supported by all PHYs + * @return common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if invalid common speed specified + */ +alt_32 alt_tse_phy_set_common_speed(alt_tse_mac_group *pmac_group, alt_32 common_speed) { + + alt_32 i; + + alt_u8 speed; + alt_u8 duplex; + + alt_u8 gb_capable; + + alt_tse_phy_info *pphy = 0; + alt_tse_mac_info *pmac_info = 0; + alt_tse_system_info *psys = 0; + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = 0; + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + + /* Record previous MDIO address, to be restored at the end of function */ + np_tse_mac *pmac_group_base = (np_tse_mac *)pmac_group->pmac_info[0]->psys_info->tse_mac_base; + alt_32 mdioadd_prev = IORD(&pmac_group_base->MDIO_ADDR1, 0); + + if((common_speed < TSE_PHY_SPEED_10) || (common_speed > TSE_PHY_SPEED_1000)) { + tse_dprintf(2, "ERROR : MAC Group[%d] - Invalid common speed specified! common speed = %d\n", mac_group_index, (int)common_speed); + /* Restore previous MDIO address */ + IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdioadd_prev); + return TSE_PHY_SPEED_NO_COMMON; + } + + /* loop through every PHY connected */ + for(i = 0; i < pmac_group->channel; i++) { + pmac_info = pmac_group->pmac_info[i]; + mac_info_index = alt_tse_get_mac_info_index(pmac_info); + + pphy = pmac_info->pphy_info; + + /* if no PHY connected */ + if(!pphy) { + continue; + } + + psys = pmac_info->psys_info; + + /* write PHY address to MDIO to access the i-th PHY */ + alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address); + + /* capability of PHY supports 1000 Mbps */ + gb_capable = pphy->link_capability.cap_1000_base_t_full || pphy->link_capability.cap_1000_base_t_half || + pphy->link_capability.cap_1000_base_x_full || pphy->link_capability.cap_1000_base_x_half; + + /* if PHY does not supports 1000 Mbps, and common speed is 1000 Mbps */ + if((!gb_capable) && (common_speed == TSE_PHY_SPEED_1000)) { + tse_dprintf(2, "ERROR : PHY[%d.%d] - PHY does not support 1000 Mbps, please specify valid common speed\n", mac_group_index, mac_info_index); + /* Restore previous MDIO address */ + IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdioadd_prev); + return TSE_PHY_SPEED_NO_COMMON; + } + + /* if PHY is not Auto-Negotiation capable */ + if(!alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_ABILITY, 1)) { + + /* if PHY supports 1000 Mbps, write msb of speed */ + if(gb_capable) { + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_SPEED_MSB, 1, common_speed >> 1); + } + /* write lsb of speed */ + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_SPEED_LSB, 1, common_speed); + + /* continue to next PHY */ + continue; + } + + /* set Auto-Negotiation advertisement based on common speed */ + if(common_speed == TSE_PHY_SPEED_1000) { + alt_tse_phy_set_adv_1000(pphy, 1); + alt_tse_phy_set_adv_100(pphy, 1); + alt_tse_phy_set_adv_10(pphy, 1); + } + else if(common_speed == TSE_PHY_SPEED_100) { + alt_tse_phy_set_adv_1000(pphy, 0); + alt_tse_phy_set_adv_100(pphy, 1); + alt_tse_phy_set_adv_10(pphy, 1); + } + else if(common_speed == TSE_PHY_SPEED_10) { + alt_tse_phy_set_adv_1000(pphy, 0); + alt_tse_phy_set_adv_100(pphy, 0); + alt_tse_phy_set_adv_10(pphy, 1); + } + else { + alt_tse_phy_set_adv_1000(pphy, 0); + alt_tse_phy_set_adv_100(pphy, 0); + alt_tse_phy_set_adv_10(pphy, 0); + } + + /* if PHY Auto-Negotiation is completed */ + if(alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_COMPLETE, 1) == 1) { + + /* read both msb and lsb of speed bits if PHY support 1000 Mbps */ + if(gb_capable) { + + /* get speed information after Auto-Negotiation */ + speed = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->speed_lsb_location, 2); + } + + /* read lsb of speed only if PHY support only 10/100 Mbps */ + else { + /* get speed and link information after Auto-Negotiation */ + speed = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->speed_lsb_location, 1); + } + + /* if current speed != common speed, then restart Auto-Negotiation */ + if(speed != common_speed) { + alt_tse_phy_restart_an(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD); + } + + /* get speed information after Auto-Negotiation */ + duplex = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->duplex_bit_location, 1); + + /* Set MAC duplex register */ + alt_tse_mac_set_duplex((np_tse_mac *)psys->tse_mac_base, duplex); + + } + tse_dprintf(5, "INFO : PHY[%d.%d] - PHY STATUS = 0x%04x\n\n", mac_group_index, mac_info_index, (int) alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, 0, 16)); + } + tse_dprintf(5, "INFO : MAC Group[%d] - All PHYs set to common speed : %d Mbps\n", mac_group_index, (common_speed == TSE_PHY_SPEED_1000) ? 1000 : ((common_speed == TSE_PHY_SPEED_100) ? 100 : 10)); + + /* Set MAC speed register */ + alt_tse_mac_set_speed(pmac_group_base, common_speed); + + /* Restore previous MDIO address */ + IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdioadd_prev); + + return common_speed; +} + + + +/* @Function Description: Additional configuration for Marvell PHY + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address of MAC group + */ +alt_32 marvell_phy_cfg(np_tse_mac *pmac) { + + alt_u16 dat; + + /* If there is no link yet, we enable auto crossover and reset the PHY */ + if((IORD(&pmac->mdio1.STATUS, 0) & PCS_ST_an_done) == 0) { + tse_dprintf(5, "MARVELL : Enabling auto crossover\n"); + IOWR(&pmac->mdio1.CONTROL, 16, 0x0078); + tse_dprintf(5, "MARVELL : PHY reset\n"); + dat = IORD(&pmac->mdio1.CONTROL, 0); + IOWR(&pmac->mdio1.CONTROL, 0, dat | PCS_CTL_sw_reset); + } + + return 0; +} + + +/* @Function Description: Change operating mode of Marvell PHY to GMII + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group + */ +alt_32 marvell_cfg_gmii(np_tse_mac *pmac) { + + alt_u16 dat = IORD(&pmac->mdio1.reg1b, 0); + dat &= 0xfff0; + + tse_dprintf(5, "MARVELL : Mode changed to GMII to copper mode\n"); + IOWR(&pmac->mdio1.reg1b, 0, dat | 0xf); + + tse_dprintf(5, "MARVELL : Disable RGMII Timing Control\n"); + dat = IORD(&pmac->mdio1.reg14, 0); + dat &= ~0x82; + IOWR(&pmac->mdio1.reg14, 0, dat); + + tse_dprintf(5, "MARVELL : PHY reset\n"); + dat = IORD(&pmac->mdio1.CONTROL, 0); + IOWR(&pmac->mdio1.CONTROL, 0, dat | PCS_CTL_sw_reset); + + return 1; +} + +/* @Function Description: Change operating mode of Marvell PHY to SGMII + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group + */ +alt_32 marvell_cfg_sgmii(np_tse_mac *pmac) { + + alt_u16 dat = IORD(&pmac->mdio1.reg1b, 0); + dat &= 0xfff0; + + tse_dprintf(5, "MARVELL : Mode changed to SGMII without clock with SGMII Auto-Neg to copper mode\n"); + IOWR(&pmac->mdio1.reg1b, 0, dat | 0x4); + + tse_dprintf(5, "MARVELL : Disable RGMII Timing Control\n"); + dat = IORD(&pmac->mdio1.reg14, 0); + dat &= ~0x82; + IOWR(&pmac->mdio1.reg14, 0, dat); + + tse_dprintf(5, "MARVELL : PHY reset\n"); + dat = IORD(&pmac->mdio1.CONTROL, 0); + IOWR(&pmac->mdio1.CONTROL, 0, dat | PCS_CTL_sw_reset); + + return 1; +} + +/* @Function Description: Change operating mode of Marvell PHY to RGMII + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group + */ +alt_32 marvell_cfg_rgmii(np_tse_mac *pmac) { + + + alt_u16 dat = IORD(&pmac->mdio1.reg1b, 0); + dat &= 0xfff0; + + tse_dprintf(5, "MARVELL : Mode changed to RGMII/Modified MII to Copper mode\n"); + IOWR(&pmac->mdio1.reg1b, 0, dat | 0xb); + + tse_dprintf(5, "MARVELL : Enable RGMII Timing Control\n"); + dat = IORD(&pmac->mdio1.reg14, 0); + dat &= ~0x82; + dat |= 0x82; + IOWR(&pmac->mdio1.reg14, 0, dat); + + tse_dprintf(5, "MARVELL : PHY reset\n"); + dat = IORD(&pmac->mdio1.CONTROL, 0); + IOWR(&pmac->mdio1.CONTROL, 0, dat | PCS_CTL_sw_reset); + + return 1; + +} + +/* @Function Description: Read link status from PHY specific status register of DP83848C + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group + */ +alt_u32 DP83848C_link_status_read(np_tse_mac *pmac) { + alt_u32 link_status = 0; + alt_u32 reg_status = IORD(&pmac->mdio1.reg10, 0); + + /* If speed == 10 Mbps */ + if(reg_status & 0x2) { + link_status |= 0x8; + } + /* Else speed = 100 Mbps */ + else { + link_status |= 0x4; + } + + /* If duplex == Full */ + if(reg_status & 0x4) { + link_status |= 0x1; + } + + return link_status; +} + +/* @Function Description: Additional configuration for PEF7071 Phy + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group + */ +alt_32 PEF7071_config(np_tse_mac *pmac) +{ + alt_u16 dat; + + dat = IORD(&pmac->mdio1.reg14, 0); + dat &= 0x3FFF; + dat |= 0x0100; + IOWR(&pmac->mdio1.reg14, 0, dat); + + return 0; + +} + +/* @Function Description: Read link status from PHY specific status register of PEF7071 + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group + */ +alt_u32 PEF7071_link_status_read(np_tse_mac *pmac) +{ + alt_u32 link_status = 0; + alt_u32 reg18 = IORD(&pmac->mdio1.reg18, 0); + + if ((reg18 & 0x3)==0) { link_status |= 0x8; } /* If speed == 10 Mbps */ + if ((reg18 & 0x3)==1) { link_status |= 0x4; } /* Else speed = 100 Mbps */ + if ((reg18 & 0x3)==2) { link_status |= 0x2; } /* Else speed = 1000 Mbps */ + + /* If duplex == Full */ + if(reg18 & 0x8) { + link_status |= 0x1; + } + + return link_status; +} diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_tse_system_info.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_tse_system_info.c new file mode 100644 index 0000000..2fb6e8d --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_tse_system_info.c @@ -0,0 +1,61 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifdef ALT_INICHE + #include "ipport.h" +#endif + +#include "altera_avalon_tse.h" +#include "altera_avalon_tse_system_info.h" +#include "system.h" + +#ifdef TSE_MY_SYSTEM +/* define TSE_MY_SYSTEM to customize tse_mac_device[] structure using global array initialization */ + extern alt_tse_system_info tse_mac_device[MAXNETS]; +#else + +/* use tse_mac_device[] structure as defined in this file + * or + * customize tse_mac_device[] structure using API alt_tse_system_add_sys() and alt_tse_sys_enable_mdio_sharing() */ +alt_tse_system_info tse_mac_device[MAXNETS] = { + + /************************************************************************************/ + #if ( defined(TSE_0_TSE_BASE) && defined(TSE_0_DMA_TX_CSR_NAME) && defined(TSE_0_DMA_RX_CSR_NAME) ) + #ifdef DESCRIPTOR_MEMORY_BASE + TSE_SYSTEM_EXT_MEM_NO_SHARED_FIFO(TSE_0_TSE, 0, TSE_0_DMA_TX, TSE_0_DMA_RX, TSE_PHY_AUTO_ADDRESS, 0, DESCRIPTOR_MEMORY) + #else + TSE_SYSTEM_INT_MEM_NO_SHARED_FIFO(TSE_0_TSE, 0, TSE_0_DMA_TX, TSE_0_DMA_RX, TSE_PHY_AUTO_ADDRESS, 0) + #endif + #endif + /************************************************************************************/ +}; + +#endif /* TSE_MY_SYSTEM */ + diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_fd.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_fd.c new file mode 100644 index 0000000..c07024a --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_fd.c @@ -0,0 +1,100 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "alt_types.h" +#include "sys/alt_dev.h" +#include "altera_avalon_uart.h" + +extern int altera_avalon_uart_read(altera_avalon_uart_state* sp, + char* buffer, int space, int flags); +extern int altera_avalon_uart_write(altera_avalon_uart_state* sp, + const char* ptr, int count, int flags); +extern int altera_avalon_uart_ioctl(altera_avalon_uart_state* sp, + int req, void* arg); +extern int altera_avalon_uart_close(altera_avalon_uart_state* sp, int flags); + +/* ----------------------------------------------------------------------- */ +/* --------------------- WRAPPERS FOR ALT FD SUPPORT --------------------- */ +/* + * + */ + +int +altera_avalon_uart_read_fd(alt_fd* fd, char* buffer, int space) +{ + altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; + + return altera_avalon_uart_read(&dev->state, buffer, space, + fd->fd_flags); +} + +int +altera_avalon_uart_write_fd(alt_fd* fd, const char* buffer, int space) +{ + altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; + + return altera_avalon_uart_write(&dev->state, buffer, space, + fd->fd_flags); +} + +#if !defined(ALT_USE_SMALL_DRIVERS) && !defined(ALTERA_AVALON_UART_SMALL) + +/* + * Fast driver + */ + +/* + * To reduce the code footprint of this driver, the ioctl() function is not + * included by default. If you wish to use the ioctl features provided + * below, you can do so by adding the option : -DALTERA_AVALON_UART_USE_IOCTL + * to CPPFLAGS in the Makefile (or through the Eclipse IDE). + */ + +#ifdef ALTERA_AVALON_UART_USE_IOCTL + +int +altera_avalon_uart_ioctl_fd(alt_fd* fd, int req, void* arg) +{ + altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; + + return altera_avalon_uart_ioctl(&dev->state, req, arg); +} + +#endif /* ALTERA_AVALON_UART_USE_IOCTL */ + +int +altera_avalon_uart_close_fd(alt_fd* fd) +{ + altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; + + return altera_avalon_uart_close(&dev->state, fd->fd_flags); +} + +#endif /* fast driver */ diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_init.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_init.c new file mode 100644 index 0000000..92484d6 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_init.c @@ -0,0 +1,312 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include + +#include "sys/alt_dev.h" +#include "sys/alt_irq.h" +#include "sys/ioctl.h" +#include "sys/alt_errno.h" + +#include "altera_avalon_uart.h" +#include "altera_avalon_uart_regs.h" + +#if !defined(ALT_USE_SMALL_DRIVERS) && !defined(ALTERA_AVALON_UART_SMALL) + +/* ----------------------------------------------------------- */ +/* ------------------------- FAST DRIVER --------------------- */ +/* ----------------------------------------------------------- */ + +/* + * altera_avalon_uart_init() is called by the auto-generated function + * alt_sys_init() in order to initialize a particular instance of this device. + * It is responsible for configuring the device and associated software + * constructs. + */ + +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void altera_avalon_uart_irq(void* context); +#else +static void altera_avalon_uart_irq(void* context, alt_u32 id); +#endif + +static void altera_avalon_uart_rxirq(altera_avalon_uart_state* sp, + alt_u32 status); +static void altera_avalon_uart_txirq(altera_avalon_uart_state* sp, + alt_u32 status); + +void +altera_avalon_uart_init(altera_avalon_uart_state* sp, + alt_u32 irq_controller_id, alt_u32 irq) +{ + void* base = sp->base; + int error; + + /* + * Initialise the read and write flags and the semaphores used to + * protect access to the circular buffers when running in a multi-threaded + * environment. + */ + error = ALT_FLAG_CREATE (&sp->events, 0) || + ALT_SEM_CREATE (&sp->read_lock, 1) || + ALT_SEM_CREATE (&sp->write_lock, 1); + + if (!error) + { + /* enable interrupts at the device */ + sp->ctrl = ALTERA_AVALON_UART_CONTROL_RTS_MSK | + ALTERA_AVALON_UART_CONTROL_RRDY_MSK | + ALTERA_AVALON_UART_CONTROL_DCTS_MSK; + + IOWR_ALTERA_AVALON_UART_CONTROL(base, sp->ctrl); + + /* register the interrupt handler */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_ic_isr_register(irq_controller_id, irq, altera_avalon_uart_irq, sp, + 0x0); +#else + alt_irq_register (irq, sp, altera_avalon_uart_irq); +#endif + } +} + +/* + * altera_avalon_uart_irq() is the interrupt handler registered at + * configuration time for processing UART interrupts. It vectors + * interrupt requests to either altera_avalon_uart_rxirq() (for incoming + * data), or altera_avalon_uart_txirq() (for outgoing data). + */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void altera_avalon_uart_irq(void* context) +#else +static void altera_avalon_uart_irq(void* context, alt_u32 id) +#endif +{ + alt_u32 status; + + altera_avalon_uart_state* sp = (altera_avalon_uart_state*) context; + void* base = sp->base; + + /* + * Read the status register in order to determine the cause of the + * interrupt. + */ + + status = IORD_ALTERA_AVALON_UART_STATUS(base); + + /* Clear any error flags set at the device */ + IOWR_ALTERA_AVALON_UART_STATUS(base, 0); + + /* Dummy read to ensure IRQ is negated before ISR returns */ + IORD_ALTERA_AVALON_UART_STATUS(base); + + /* process a read irq */ + if (status & ALTERA_AVALON_UART_STATUS_RRDY_MSK) + { + altera_avalon_uart_rxirq(sp, status); + } + + /* process a write irq */ + if (status & (ALTERA_AVALON_UART_STATUS_TRDY_MSK | + ALTERA_AVALON_UART_STATUS_DCTS_MSK)) + { + altera_avalon_uart_txirq(sp, status); + } + + +} + +/* + * altera_avalon_uart_rxirq() is called by altera_avalon_uart_irq() to + * process a receive interrupt. It transfers the incoming character into + * the receive circular buffer, and sets the apropriate flags to indicate + * that there is data ready to be processed. + */ +static void +altera_avalon_uart_rxirq(altera_avalon_uart_state* sp, alt_u32 status) +{ + alt_u32 next; + + /* If there was an error, discard the data */ + + if (status & (ALTERA_AVALON_UART_STATUS_PE_MSK | + ALTERA_AVALON_UART_STATUS_FE_MSK)) + { + return; + } + + /* + * In a multi-threaded environment, set the read event flag to indicate + * that there is data ready. This is only done if the circular buffer was + * previously empty. + */ + + if (sp->rx_end == sp->rx_start) + { + ALT_FLAG_POST (sp->events, ALT_UART_READ_RDY, OS_FLAG_SET); + } + + /* Determine which slot to use next in the circular buffer */ + + next = (sp->rx_end + 1) & ALT_AVALON_UART_BUF_MSK; + + /* Transfer data from the device to the circular buffer */ + + sp->rx_buf[sp->rx_end] = IORD_ALTERA_AVALON_UART_RXDATA(sp->base); + + sp->rx_end = next; + + next = (sp->rx_end + 1) & ALT_AVALON_UART_BUF_MSK; + + /* + * If the cicular buffer was full, disable interrupts. Interrupts will be + * re-enabled when data is removed from the buffer. + */ + + if (next == sp->rx_start) + { + sp->ctrl &= ~ALTERA_AVALON_UART_CONTROL_RRDY_MSK; + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + } +} + +/* + * altera_avalon_uart_txirq() is called by altera_avalon_uart_irq() to + * process a transmit interrupt. It transfers data from the transmit + * buffer to the device, and sets the apropriate flags to indicate that + * there is data ready to be processed. + */ +static void +altera_avalon_uart_txirq(altera_avalon_uart_state* sp, alt_u32 status) +{ + /* Transfer data if there is some ready to be transfered */ + + if (sp->tx_start != sp->tx_end) + { + /* + * If the device is using flow control (i.e. RTS/CTS), then the + * transmitter is required to throttle if CTS is high. + */ + + if (!(sp->flags & ALT_AVALON_UART_FC) || + (status & ALTERA_AVALON_UART_STATUS_CTS_MSK)) + { + + /* + * In a multi-threaded environment, set the write event flag to indicate + * that there is space in the circular buffer. This is only done if the + * buffer was previously empty. + */ + + if (sp->tx_start == ((sp->tx_end + 1) & ALT_AVALON_UART_BUF_MSK)) + { + ALT_FLAG_POST (sp->events, + ALT_UART_WRITE_RDY, + OS_FLAG_SET); + } + + /* Write the data to the device */ + + IOWR_ALTERA_AVALON_UART_TXDATA(sp->base, sp->tx_buf[sp->tx_start]); + + sp->tx_start = (++sp->tx_start) & ALT_AVALON_UART_BUF_MSK; + + /* + * In case the tranmit interrupt had previously been disabled by + * detecting a low value on CTS, it is reenabled here. + */ + + sp->ctrl |= ALTERA_AVALON_UART_CONTROL_TRDY_MSK; + } + else + { + /* + * CTS is low and we are using flow control, so disable the transmit + * interrupt while we wait for CTS to go high again. This will be + * detected using the DCTS interrupt. + * + * There is a race condition here. "status" may indicate that + * CTS is low, but it actually went high before DCTS was cleared on + * the last write to the status register. To avoid this resulting in + * deadlock, it's necessary to re-check the status register here + * before throttling. + */ + + status = IORD_ALTERA_AVALON_UART_STATUS(sp->base); + + if (!(status & ALTERA_AVALON_UART_STATUS_CTS_MSK)) + { + sp->ctrl &= ~ALTERA_AVALON_UART_CONTROL_TRDY_MSK; + } + } + } + + /* + * If the circular buffer is empty, disable the interrupt. This will be + * re-enabled when new data is placed in the buffer. + */ + + if (sp->tx_start == sp->tx_end) + { + sp->ctrl &= ~(ALTERA_AVALON_UART_CONTROL_TRDY_MSK | + ALTERA_AVALON_UART_CONTROL_DCTS_MSK); + } + + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); +} + +/* + * The close() routine is implemented to drain the UART transmit buffer + * when not in "small" mode. This routine will wait for transimt data to be + * emptied unless the driver flags have been set to non-blocking mode. + * This routine should be called indirectly (i.e. though the C library + * close() routine) so that the file descriptor associated with the relevant + * stream (i.e. stdout) can be closed as well. This routine does not manage + * file descriptors. + * + * The close routine is not implemented for the small driver; instead it will + * map to null. This is because the small driver simply waits while characters + * are transmitted; there is no interrupt-serviced buffer to empty + */ +int altera_avalon_uart_close(altera_avalon_uart_state* sp, int flags) +{ + /* + * Wait for all transmit data to be emptied by the UART ISR. + */ + while (sp->tx_start != sp->tx_end) { + if (flags & O_NONBLOCK) { + return -EWOULDBLOCK; + } + } + + return 0; +} + +#endif /* fast driver */ diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_ioctl.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_ioctl.c new file mode 100644 index 0000000..4f281d5 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_ioctl.c @@ -0,0 +1,153 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include + +#include "sys/alt_irq.h" +#include "sys/ioctl.h" +#include "sys/alt_errno.h" + +#include "altera_avalon_uart_regs.h" +#include "altera_avalon_uart.h" + + +#if !defined(ALT_USE_SMALL_DRIVERS) && !defined(ALTERA_AVALON_UART_SMALL) + +/* ----------------------------------------------------------- */ +/* ------------------------- FAST DRIVER --------------------- */ +/* ----------------------------------------------------------- */ + +/* + * To reduce the code footprint of this driver, the ioctl() function is not + * included by default. If you wish to use the ioctl features provided + * below, you can do so by adding the option : -DALTERA_AVALON_UART_USE_IOCTL + * to CPPFLAGS in the Makefile (or through the Eclipse IDE). + */ + +#ifdef ALTERA_AVALON_UART_USE_IOCTL + +/* + * altera_avalon_uart_ioctl() is called by the system ioctl() function to handle + * ioctl requests for the UART. The only ioctl requests supported are TIOCMGET + * and TIOCMSET. + * + * TIOCMGET returns a termios structure that describes the current device + * configuration. + * + * TIOCMSET sets the device (if possible) to match the requested configuration. + * The requested configuration is described using a termios structure passed + * through the input argument "arg". + */ + +static int altera_avalon_uart_tiocmget(altera_avalon_uart_state* sp, + struct termios* term); +static int altera_avalon_uart_tiocmset(altera_avalon_uart_state* sp, + struct termios* term); + +int +altera_avalon_uart_ioctl(altera_avalon_uart_state* sp, int req, void* arg) +{ + int rc = -ENOTTY; + + switch (req) + { + case TIOCMGET: + rc = altera_avalon_uart_tiocmget(sp, (struct termios*) arg); + break; + case TIOCMSET: + rc = altera_avalon_uart_tiocmset(sp, (struct termios*) arg); + break; + default: + break; + } + return rc; +} + +/* + * altera_avalon_uart_tiocmget() is used by altera_avalon_uart_ioctl() to fill + * in the input termios structure with the current device configuration. + * + * See termios.h for further details on the contents of the termios structure. + */ + +static int +altera_avalon_uart_tiocmget(altera_avalon_uart_state* sp, + struct termios* term) +{ + memcpy (term, &sp->termios, sizeof (struct termios)); + return 0; +} + +/* + * altera_avalon_uart_tiocmset() is used by altera_avalon_uart_ioctl() to + * configure the device according to the settings in the input termios + * structure. In practice the only configuration that can be changed is the + * baud rate, and then only if the hardware is configured to have a writable + * baud register. + */ + +static int +altera_avalon_uart_tiocmset(altera_avalon_uart_state* sp, + struct termios* term) +{ + speed_t speed; + + speed = sp->termios.c_ispeed; + + /* Update the settings if the hardware supports it */ + + if (!(sp->flags & ALT_AVALON_UART_FB)) + { + sp->termios.c_ispeed = sp->termios.c_ospeed = term->c_ispeed; + } + /* + * If the request was for an unsupported setting, return an error. + */ + + if (memcmp(term, &sp->termios, sizeof (struct termios))) + { + sp->termios.c_ispeed = sp->termios.c_ospeed = speed; + return -EIO; + } + + /* + * Otherwise, update the hardware. + */ + + IOWR_ALTERA_AVALON_UART_DIVISOR(sp->base, + ((sp->freq/sp->termios.c_ispeed) - 1)); + + return 0; +} + +#endif /* ALTERA_AVALON_UART_USE_IOCTL */ + +#endif /* fast driver */ diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_read.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_read.c new file mode 100644 index 0000000..5286ba3 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_read.c @@ -0,0 +1,240 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include + +#include "sys/alt_irq.h" +#include "sys/ioctl.h" +#include "sys/alt_errno.h" + +#include "altera_avalon_uart.h" +#include "altera_avalon_uart_regs.h" + +#if defined(ALT_USE_SMALL_DRIVERS) || defined(ALTERA_AVALON_UART_SMALL) + +/* ----------------------------------------------------------- */ +/* ----------------------- SMALL DRIVER ---------------------- */ +/* ----------------------------------------------------------- */ + +/* + * altera_avalon_uart_read() is called by the system read() function in order to + * read a block of data from the UART. "len" is the maximum length of the data + * to read, and "ptr" indicates the destination address. "fd" is the file + * descriptor for the device to be read from. + * + * Permission checks are made before the call to altera_avalon_uart_read(), so + * we know that the file descriptor has been opened with the correct permissions + * for this operation. + * + * The return value is the number of bytes actually read. + * + * This implementation polls the device waiting for characters. At most it can + * only return one character, regardless of how many are requested. If the + * device is being accessed in non-blocking mode then it is possible for this + * function to return without reading any characters. In this case errno is + * set to EWOULDBLOCK. + */ + +int +altera_avalon_uart_read(altera_avalon_uart_state* sp, char* ptr, int len, + int flags) +{ + int block; + unsigned int status; + + block = !(flags & O_NONBLOCK); + + do + { + status = IORD_ALTERA_AVALON_UART_STATUS(sp->base); + + /* clear any error flags */ + + IOWR_ALTERA_AVALON_UART_STATUS(sp->base, 0); + + if (status & ALTERA_AVALON_UART_CONTROL_RRDY_MSK) + { + ptr[0] = IORD_ALTERA_AVALON_UART_RXDATA(sp->base); + + if (!(status & (ALTERA_AVALON_UART_STATUS_PE_MSK | + ALTERA_AVALON_UART_STATUS_FE_MSK))) + { + return 1; + } + } + } + while (block); + + ALT_ERRNO = EWOULDBLOCK; + + return 0; +} + +#else + +/* ----------------------------------------------------------- */ +/* ----------------------- FAST DRIVER ----------------------- */ +/* ----------------------------------------------------------- */ + +/* + * altera_avalon_uart_read() is called by the system read() function in order to + * read a block of data from the UART. "len" is the maximum length of the data + * to read, and "ptr" indicates the destination address. "sp" is the state + * pointer for the device to be read from. + * + * Permission checks are made before the call to altera_avalon_uart_read(), so + * we know that the file descriptor has been opened with the correct permissions + * for this operation. + * + * The return value is the number of bytes actually read. + * + * This function does not communicate with the device directly. Instead data is + * transfered from a circular buffer. The interrupt handler is then responsible + * for copying data from the device into this buffer. + */ + +int +altera_avalon_uart_read(altera_avalon_uart_state* sp, char* ptr, int len, + int flags) +{ + alt_irq_context context; + int block; + alt_u8 read_would_block = 0; + int count = 0; + + /* + * Construct a flag to indicate whether the device is being accessed in + * blocking or non-blocking mode. + */ + + block = !(flags & O_NONBLOCK); + + /* + * When running in a multi threaded environment, obtain the "read_lock" + * semaphore. This ensures that reading from the device is thread-safe. + */ + + ALT_SEM_PEND (sp->read_lock, 0); + + /* + * Loop, copying data from the circular buffer to the destination address + * supplied in "ptr". This loop is terminated when the required number of + * bytes have been read. If the circular buffer is empty, and no data has + * been read, then the loop will block (when in blocking mode). + * + * If the circular buffer is empty, and some data has already been + * transferred, or the device is being accessed in non-blocking mode, then + * the loop terminates without necessarily reading all the requested data. + */ + + do + { + /* + * Read the required amount of data, until the circular buffer runs + * empty + */ + + while ((count < len) && (sp->rx_start != sp->rx_end)) + { + count++; + *ptr++ = sp->rx_buf[sp->rx_start]; + + sp->rx_start = (sp->rx_start+1) & ALT_AVALON_UART_BUF_MSK; + } + + /* + * If no data has been transferred, the circular buffer is empty, and + * this is not a non-blocking access, block waiting for data to arrive. + */ + + if (!count && (sp->rx_start == sp->rx_end)) + { + if (!block) + { + /* Set errno to indicate the reason we're not returning any data */ + + ALT_ERRNO = EWOULDBLOCK; + read_would_block = 1; + break; + } + else + { + /* Block waiting for some data to arrive */ + + /* First, ensure read interrupts are enabled to avoid deadlock */ + + context = alt_irq_disable_all (); + sp->ctrl |= ALTERA_AVALON_UART_CONTROL_RRDY_MSK; + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + alt_irq_enable_all (context); + + /* + * When running in a multi-threaded mode, we pend on the read event + * flag set in the interrupt service routine. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something more + * profitable elsewhere. + */ + + ALT_FLAG_PEND (sp->events, + ALT_UART_READ_RDY, + OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, + 0); + } + } + } + while (!count && len); + + /* + * Now that access to the circular buffer is complete, release the read + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->read_lock); + + /* + * Ensure that interrupts are enabled, so that the circular buffer can + * re-fill. + */ + + context = alt_irq_disable_all (); + sp->ctrl |= ALTERA_AVALON_UART_CONTROL_RRDY_MSK; + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + alt_irq_enable_all (context); + + /* Return the number of bytes read */ + if(read_would_block) { + return -EWOULDBLOCK; + } + else { + return count; + } +} + +#endif /* fast driver */ diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_write.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_write.c new file mode 100644 index 0000000..0658e02 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_write.c @@ -0,0 +1,232 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include + +#include "sys/alt_dev.h" +#include "sys/alt_irq.h" +#include "sys/ioctl.h" +#include "sys/alt_errno.h" + +#include "altera_avalon_uart_regs.h" +#include "altera_avalon_uart.h" + +#if defined(ALT_USE_SMALL_DRIVERS) || defined(ALTERA_AVALON_UART_SMALL) + +/* ----------------------------------------------------------- */ +/* ------------------------ SMALL DRIVER --------------------- */ +/* ----------------------------------------------------------- */ + +/* + * altera_avalon_uart_write() is called by the system write() function in + * order to write a block of data to the UART. + * "len" is the length of the data to write, + * and "ptr" indicates the source address. "fd" is the file descriptor for the + * device to be read from. + * + * Permission checks are made before the call to altera_avalon_uart_write(), so + * we know that the file descriptor has been opened with the correct permissions + * for this operation. + * + * The return value is the number of bytes actually written. + * + * This function will block on the devices transmit register, until all + * characters have been transmitted. This is unless the device is being + * accessed in non-blocking mode. In this case this function will return as + * soon as the device reports that it is not ready to transmit. + * + * Since this is the small footprint version of the UART driver, the value of + * CTS is ignored. + */ + +int +altera_avalon_uart_write(altera_avalon_uart_state* sp, const char* ptr, int len, + int flags) +{ + int block; + unsigned int status; + int count; + + block = !(flags & O_NONBLOCK); + count = len; + + do + { + status = IORD_ALTERA_AVALON_UART_STATUS(sp->base); + + if (status & ALTERA_AVALON_UART_STATUS_TRDY_MSK) + { + IOWR_ALTERA_AVALON_UART_TXDATA(sp->base, *ptr++); + count--; + } + } + while (block && count); + + if (count) + { + ALT_ERRNO = EWOULDBLOCK; + } + + return (len - count); +} + +#else /* Using the "fast" version of the driver */ + +/* ----------------------------------------------------------- */ +/* ------------------------- FAST DRIVER --------------------- */ +/* ----------------------------------------------------------- */ + +/* + * altera_avalon_uart_write() is called by the system write() function in order + * to write a block of data to the UART. "len" is the length of the data to + * write, and "ptr" indicates the source address. "sp" is the state pointer + * for the device to be written to. + * + * Permission checks are made before the call to altera_avalon_uart_write(), so + * we know that the file descriptor has been opened with the correct permissions + * for this operation. + * + * The return value is the number of bytes actually written. + * + * This function does not communicate with the device directly. Instead data is + * transfered to a circular buffer. The interrupt handler is then responsible + * for copying data from this buffer into the device. + */ + +int +altera_avalon_uart_write(altera_avalon_uart_state* sp, const char* ptr, int len, + int flags) +{ + alt_irq_context context; + int no_block; + alt_u32 next; + int count = len; + + /* + * Construct a flag to indicate whether the device is being accessed in + * blocking or non-blocking mode. + */ + + no_block = (flags & O_NONBLOCK); + + /* + * When running in a multi threaded environment, obtain the "write_lock" + * semaphore. This ensures that writing to the device is thread-safe. + */ + + ALT_SEM_PEND (sp->write_lock, 0); + + /* + * Loop transferring data from the input buffer to the transmit circular + * buffer. The loop is terminated once all the data has been transferred, + * or, (if in non-blocking mode) the buffer becomes full. + */ + + while (count) + { + /* Determine the next slot in the buffer to access */ + + next = (sp->tx_end + 1) & ALT_AVALON_UART_BUF_MSK; + + /* block waiting for space if necessary */ + + if (next == sp->tx_start) + { + if (no_block) + { + /* Set errno to indicate why this function returned early */ + + ALT_ERRNO = EWOULDBLOCK; + break; + } + else + { + /* Block waiting for space in the circular buffer */ + + /* First, ensure transmit interrupts are enabled to avoid deadlock */ + + context = alt_irq_disable_all (); + sp->ctrl |= (ALTERA_AVALON_UART_CONTROL_TRDY_MSK | + ALTERA_AVALON_UART_CONTROL_DCTS_MSK); + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + alt_irq_enable_all (context); + + /* wait for space to come free */ + + do + { + /* + * When running in a multi-threaded mode, we pend on the write event + * flag set in the interrupt service routine. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something + * more profitable elsewhere. + */ + + ALT_FLAG_PEND (sp->events, + ALT_UART_WRITE_RDY, + OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, + 0); + } + while ((next == sp->tx_start)); + } + } + + count--; + + /* Add the next character to the transmit buffer */ + + sp->tx_buf[sp->tx_end] = *ptr++; + sp->tx_end = next; + } + + /* + * Now that access to the circular buffer is complete, release the write + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->write_lock); + + /* + * Ensure that interrupts are enabled, so that the circular buffer can + * drain. + */ + + context = alt_irq_disable_all (); + sp->ctrl |= ALTERA_AVALON_UART_CONTROL_TRDY_MSK | + ALTERA_AVALON_UART_CONTROL_DCTS_MSK; + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + alt_irq_enable_all (context); + + /* return the number of bytes written */ + + return (len - count); +} + +#endif /* fast driver */ diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_generic_quad_spi_controller.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_generic_quad_spi_controller.c new file mode 100644 index 0000000..ef6b9e4 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_generic_quad_spi_controller.c @@ -0,0 +1,797 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2015 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include +#include +#include +#include "sys/param.h" +#include "alt_types.h" +#include "altera_generic_quad_spi_controller_regs.h" +#include "altera_generic_quad_spi_controller.h" +#include "priv/alt_busy_sleep.h" +#include "sys/alt_debug.h" +#include "sys/alt_cache.h" + + +ALT_INLINE alt_32 static alt_qspi_validate_read_write_arguments(alt_qspi_controller_dev *flash_info,alt_u32 offset, alt_u32 length); +alt_32 static alt_qspi_poll_for_write_in_progress(alt_qspi_controller_dev* qspi_flash_info); + +/* + * Public API + * + * Refer to “Using Flash Devices†in the + * Developing Programs Using the Hardware Abstraction Layer chapter + * of the Nios II Software Developer’s Handbook. + */ + + + /** + * alt_qspi_controller_lock + * + * Locks the range of the memory sectors, which + * protected from write and erase. + * + * Arguments: + * - *flash_info: Pointer to general flash device structure. + * - sectors_to_lock: Block protection bits in EPCQ/QSPI ==> Bit4 | Bit3 | Bit2 | Bit1 | Bit0 + * TB | BP3 | BP2 | BP1 | BP0 + * For details of setting sectors protection, please refer to EPCQ/QSPI datasheet. + * + * Returns: + * 0 -> success + * -EINVAL -> Invalid arguments + * -ETIME -> Time out and skipping the looping after 0.7 sec. + * -ENOLCK -> Sectors lock failed. +**/ +int alt_qspi_controller_lock(alt_flash_dev *flash_info, alt_u32 sectors_to_lock) +{ + alt_u32 mem_op_value = 0; /* value to write to EPCQ_MEM_OP register */ + alt_qspi_controller_dev* qspi_flash_info = NULL; + alt_u32 result = 0; + alt_32 status = 0; + + /* return -EINVAL if flash_info is NULL */ + if(NULL == flash_info || 0 > sectors_to_lock) + { + return -EINVAL; + } + + qspi_flash_info = (alt_qspi_controller_dev*)flash_info; + + /* sector value should occupy bits 17:8 */ + mem_op_value = sectors_to_lock << 8; + + /* sector protect commands 0b11 occupies lower 2 bits */ + mem_op_value |= ALTERA_QSPI_CONTROLLER_MEM_OP_SECTOR_PROTECT_CMD; + + /* write sector protect command to QSPI_MEM_OP register to protect sectors */ + IOWR_ALTERA_QSPI_CONTROLLER_MEM_OP(qspi_flash_info->csr_base, mem_op_value); + + /* poll write in progress to make sure no operation is in progress */ + status = alt_qspi_poll_for_write_in_progress(qspi_flash_info); + if(status != 0) + { + return status; + } + + status = IORD_ALTERA_QSPI_CONTROLLER_STATUS(qspi_flash_info->csr_base); + result |= (status >> 2) & 0x07; /* extract out BP3 - BP0 */ + result |= (status >> 3) & 0x08; /* extract out BP4 */ + result |= (status >> 1) & 0x10; /* extract out TOP/BOTTOM bit */ + + if(result != sectors_to_lock) + { + return -ENOLCK; + } + + return 0; +} + +/** + * alt_qspi_controller_get_info + * + * Pass the table of erase blocks to the user. This flash will return a single + * flash_region that gives the number and size of sectors for the device used. + * + * Arguments: + * - *fd: Pointer to general flash device structure. + * - **info: Pointer to flash region + * - *number_of_regions: Pointer to number of regions + * + * For details of setting sectors protection, please refer to EPCQ/QSPI datasheet. + * + * Returns: + * 0 -> success + * -EINVAL -> Invalid arguments + * -EIO -> Could be hardware problem. +**/ +int alt_qspi_controller_get_info +( + alt_flash_fd *fd, /** flash device descriptor */ + flash_region **info, /** pointer to flash_region will be stored here */ + int *number_of_regions /** number of regions will be stored here */ +) +{ + alt_flash_dev* flash = NULL; + + /* return -EINVAL if fd,info and number_of_regions are NULL */ + if(NULL == fd || NULL == info || NULL == number_of_regions) + { + return -EINVAL; + } + + flash = (alt_flash_dev*)fd; + + *number_of_regions = flash->number_of_regions; + + if (!flash->number_of_regions) + { + return -EIO; + } + else + { + *info = &flash->region_info[0]; + } + + return 0; +} + +/** + * alt_qspi_controller_erase_block + * + * This function erases a single flash sector. + * + * Arguments: + * - *flash_info: Pointer to QSPI flash device structure. + * - block_offset: byte-addressed offset, from start of flash, of the sector to be erased + * + * Returns: + * 0 -> success + * -EINVAL -> Invalid arguments + * -EIO -> write failed, sector might be protected +**/ +int alt_qspi_controller_erase_block(alt_flash_dev *flash_info, int block_offset) +{ + alt_32 ret_code = 0; + alt_u32 mem_op_value = 0; /* value to write to EPCQ_MEM_OP register */ + alt_qspi_controller_dev* qspi_flash_info = NULL; + alt_u32 sector_number = 0; + + /* return -EINVAL if flash_info is NULL */ + if(NULL == flash_info) + { + return -EINVAL; + } + + qspi_flash_info = (alt_qspi_controller_dev*)flash_info; + + /* + * Sanity checks that block_offset is within the flash memory span and that the + * block offset is sector aligned. + * + */ + if((block_offset < 0) + || (block_offset >= qspi_flash_info->size_in_bytes) + || (block_offset & (qspi_flash_info->sector_size - 1)) != 0) + { + return -EINVAL; + } + + /* calculate current sector/block number */ + sector_number = (block_offset/(qspi_flash_info->sector_size)); + + /* sector value should occupy bits 23:8 */ + mem_op_value = (sector_number << 8) & ALTERA_QSPI_CONTROLLER_MEM_OP_SECTOR_VALUE_MASK; + + /* sector erase commands 0b10 occupies lower 2 bits */ + mem_op_value |= ALTERA_QSPI_CONTROLLER_MEM_OP_SECTOR_ERASE_CMD; + + /* write sector erase command to QSPI_MEM_OP register to erase sector "sector_number" */ + IOWR_ALTERA_QSPI_CONTROLLER_MEM_OP(qspi_flash_info->csr_base, mem_op_value); + + /* check whether erase triggered a illegal erase interrupt */ + if((IORD_ALTERA_QSPI_CONTROLLER_ISR(qspi_flash_info->csr_base) & + ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_ERASE_MASK) == + ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_ERASE_ACTIVE) + { + /* clear register */ + /* QSPI_ISR access is write one to clear (W1C) */ + IOWR_ALTERA_QSPI_CONTROLLER_ISR(qspi_flash_info->csr_base, + ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_ERASE_MASK ); + return -EIO; /* erase failed, sector might be protected */ + } + + return ret_code; +} + +/** + * alt_qspi_controller_write_block + * + * This function writes one block/sector of data to flash. The length of the write can NOT + * spill into the adjacent sector. + * + * It assumes that someone has already erased the appropriate sector(s). + * + * Arguments: + * - *flash_info: Pointer to QSPI flash device structure. + * - block_offset: byte-addressed offset, from the start of flash, of the sector to written to + * - data-offset: Byte offset (unaligned access) of write into flash memory. + * For best performance, word(32 bits - aligned access) offset of write is recommended. + * - *src_addr: source buffer + * - length: size of writing + * + * Returns: + * 0 -> success + * -EINVAL -> Invalid arguments + * -EIO -> write failed, sector might be protected +**/ +int alt_qspi_controller_write_block +( + alt_flash_dev *flash_info, /** flash device info */ + int block_offset, /** sector/block offset in byte addressing */ + int data_offset, /** offset of write from base address */ + const void *data, /** data to be written */ + int length /** bytes of data to be written, >0 */ +) +{ + alt_u32 buffer_offset = 0; /** offset into data buffer to get write data */ + alt_u32 remaining_length = length; /** length left to write */ + alt_u32 write_offset = data_offset; /** offset into flash to write too */ + + alt_qspi_controller_dev *qspi_flash_info = (alt_qspi_controller_dev*)flash_info; + + /* + * Sanity checks that data offset is not larger then a sector, that block offset is + * sector aligned and within the valid flash memory range and a write doesn't spill into + * the adjacent flash sector. + */ + if(block_offset < 0 + || data_offset < 0 + || NULL == flash_info + || NULL == data + || data_offset >= qspi_flash_info->size_in_bytes + || block_offset >= qspi_flash_info->size_in_bytes + || length > (qspi_flash_info->sector_size - (data_offset - block_offset)) + || length < 0 + || (block_offset & (qspi_flash_info->sector_size - 1)) != 0) + { + return -EINVAL; + } + + /* + * Do writes one 32-bit word at a time. + * We need to make sure that we pad the first few bytes so they're word aligned if they are + * not already. + */ + while (remaining_length > 0) + { + alt_u32 word_to_write = 0xFFFFFFFF; /** initialize word to write to blank word */ + alt_u32 padding = 0; /** bytes to pad the next word that is written */ + alt_u32 bytes_to_copy = sizeof(alt_u32); /** number of bytes from source to copy */ + + /* + * we need to make sure the write is word aligned + * this should only be true at most 1 time + */ + if (0 != (write_offset & (sizeof(alt_u32) - 1))) + { + /* + * data is not word aligned + * calculate padding bytes need to add before start of a data offset + */ + padding = write_offset & (sizeof(alt_u32) - 1); + + /* update variables to account for padding being added */ + bytes_to_copy -= padding; + + if(bytes_to_copy > remaining_length) + { + bytes_to_copy = remaining_length; + } + + write_offset = write_offset - padding; + if(0 != (write_offset & (sizeof(alt_u32) - 1))) + { + return -EINVAL; + } + } + else + { + if(bytes_to_copy > remaining_length) + { + bytes_to_copy = remaining_length; + } + } + + /* prepare the word to be written */ + memcpy((((void*)&word_to_write)) + padding, ((void*)data) + buffer_offset, bytes_to_copy); + + /* update offset and length variables */ + buffer_offset += bytes_to_copy; + remaining_length -= bytes_to_copy; + + /* write to flash 32 bits at a time */ + IOWR_32DIRECT(qspi_flash_info->data_base, write_offset, word_to_write); + + /* check whether write triggered a illegal write interrupt */ + if((IORD_ALTERA_QSPI_CONTROLLER_ISR(qspi_flash_info->csr_base) & + ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_WRITE_MASK) == + ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_WRITE_ACTIVE) + { + /* clear register */ + IOWR_ALTERA_QSPI_CONTROLLER_ISR(qspi_flash_info->csr_base, + ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_WRITE_MASK ); + return -EIO; /** write failed, sector might be protected */ + } + + /* update current offset */ + write_offset = write_offset + sizeof(alt_u32); + } + + return 0; +} + +/** + * alt_qspi_controller_write + * + * Program the data into the flash at the selected address. + * + * The different between this function and alt_qspi_controller_write_block function + * is that this function (alt_qspi_controller_write) will automatically erase a block as needed + * Arguments: + * - *flash_info: Pointer to QSPI flash device structure. + * - offset: Byte offset (unaligned access) of write to flash memory. For best performance, + * word(32 bits - aligned access) offset of write is recommended. + * - *src_addr: source buffer + * - length: size of writing + * + * Returns: + * 0 -> success + * -EINVAL -> Invalid arguments + * -EIO -> write failed, sector might be protected + * +**/ +int alt_qspi_controller_write( + alt_flash_dev *flash_info, /** device info */ + int offset, /** offset of write from base address */ + const void *src_addr, /** source buffer */ + int length /** size of writing */ +) +{ + alt_32 ret_code = 0; + + alt_qspi_controller_dev *qspi_flash_info = NULL; + + alt_u32 write_offset = offset; /** address of next byte to write */ + alt_u32 remaining_length = length; /** length of write data left to be written */ + alt_u32 buffer_offset = 0; /** offset into source buffer to get write data */ + alt_u32 i = 0; + + /* return -EINVAL if flash_info and src_addr are NULL */ + if(NULL == flash_info || NULL == src_addr) + { + return -EINVAL; + } + + qspi_flash_info = (alt_qspi_controller_dev*)flash_info; + + /* make sure the write parameters are within the bounds of the flash */ + ret_code = alt_qspi_validate_read_write_arguments(qspi_flash_info, offset, length); + + if(0 != ret_code) + { + return ret_code; + } + + /* + * This loop erases and writes data one sector at a time. We check for write completion + * before starting the next sector. + */ + for(i = offset/qspi_flash_info->sector_size ; i < qspi_flash_info->number_of_sectors; i++) + { + alt_u32 block_offset = 0; /** block offset in byte addressing */ + alt_u32 offset_within_current_sector = 0; /** offset into current sector to write */ + alt_u32 length_to_write = 0; /** length to write to current sector */ + + if(0 >= remaining_length) + { + break; /* out of data to write */ + } + + /* calculate current sector/block offset in byte addressing */ + block_offset = write_offset & ~(qspi_flash_info->sector_size - 1); + + /* calculate offset into sector/block if there is one */ + if(block_offset != write_offset) + { + offset_within_current_sector = write_offset - block_offset; + } + + /* erase sector */ + ret_code = alt_qspi_controller_erase_block(flash_info, block_offset); + + if(0 != ret_code) + { + return ret_code; + } + + /* calculate the byte size of data to be written in a sector */ + length_to_write = MIN(qspi_flash_info->sector_size - offset_within_current_sector, + remaining_length); + + /* write data to erased block */ + ret_code = alt_qspi_controller_write_block(flash_info, block_offset, write_offset, + src_addr + buffer_offset, length_to_write); + + + if(0 != ret_code) + { + return ret_code; + } + + /* update remaining length and buffer_offset pointer */ + remaining_length -= length_to_write; + buffer_offset += length_to_write; + write_offset += length_to_write; + } + + return ret_code; +} + +/** + * alt_qspi_controller_read + * + * There's no real need to use this function as opposed to using memcpy directly. It does + * do some sanity checks on the bounds of the read. + * + * Arguments: + * - *flash_info: Pointer to general flash device structure. + * - offset: offset read from flash memory. + * - *dest_addr: destination buffer + * - length: size of reading + * + * Returns: + * 0 -> success + * -EINVAL -> Invalid arguments +**/ +int alt_qspi_controller_read +( + alt_flash_dev *flash_info, /** device info */ + int offset, /** offset of read from base address */ + void *dest_addr, /** destination buffer */ + int length /** size of read */ +) +{ + alt_32 ret_code = 0; + alt_qspi_controller_dev *qspi_flash_info = NULL; + + /* return -EINVAL if flash_info and dest_addr are NULL */ + if(NULL == flash_info || NULL == dest_addr) + { + return -EINVAL; + } + + qspi_flash_info = (alt_qspi_controller_dev*)flash_info; + + /* validate arguments */ + ret_code = alt_qspi_validate_read_write_arguments(qspi_flash_info, offset, length); + + /* copy data from flash to destination address */ + if(0 == ret_code) + { + memcpy(dest_addr, (alt_u8*)qspi_flash_info->data_base + offset, length); + } + + return ret_code; +} + +/** + * altera_qspi_controller_init + * + * alt_sys_init.c will call this function automatically through macro + * + * Information in system.h is checked against expected values that are determined by the silicon_id. + * If the information doesn't match then this system is configured incorrectly. Most likely the wrong + * type of EPCS or EPCQ/QSPI device was selected when instantiating the soft IP. + * + * Arguments: + * - *flash: Pointer to QSPI flash device structure. + * + * Returns: + * 0 -> success + * -EINVAL -> Invalid arguments. + * -ENODEV -> System is configured incorrectly. +**/ +alt_32 altera_qspi_controller_init(alt_qspi_controller_dev *flash) +{ + alt_u32 silicon_id = 0; + alt_u32 size_in_bytes = 0; + alt_u32 number_of_sectors = 0; + + /* return -EINVAL if flash is NULL */ + if(NULL == flash) + { + return -EINVAL; + } + + /* return -ENODEV if CSR slave is not attached */ + if(NULL == (void *)flash->csr_base) + { + return -ENODEV; + } + + + /* + * If flash is an EPCQ/QSPI device, we read the QSPI_RD_RDID register for the ID + * If flash is an EPCS device, we read the QSPI_RD_SID register for the ID + * + * Whether or not the flash is a EPCQ, QSPI or EPCS is indicated in the system.h. The system.h gets + * this value from the hw.tcl of the IP. If this value is set incorrectly, then things will go + * badly. + * + * In both cases, we can determine the number of sectors, which we can use + * to calculate a size. We compare that size to the system.h value to make sure + * the QSPI soft IP was configured correctly. + */ + if(0 == flash->is_epcs) + { + /* If we're an EPCQ or QSPI, we read QSPI_RD_RDID for the silicon ID */ + silicon_id = IORD_ALTERA_QSPI_CONTROLLER_RDID(flash->csr_base); + silicon_id &= ALTERA_QSPI_CONTROLLER_RDID_MASK; + + /* Determine which EPCQ/QSPI device so we can figure out the number of sectors */ + /*EPCQ and QSPI share the same ID for the same capacity*/ + switch(silicon_id) + { + case ALTERA_QSPI_CONTROLLER_RDID_QSPI16: + { + number_of_sectors = 32; + break; + } + case ALTERA_QSPI_CONTROLLER_RDID_QSPI32: + { + number_of_sectors = 64; + break; + } + case ALTERA_QSPI_CONTROLLER_RDID_QSPI64: + { + number_of_sectors = 128; + break; + } + case ALTERA_QSPI_CONTROLLER_RDID_QSPI128: + { + number_of_sectors = 256; + break; + } + case ALTERA_QSPI_CONTROLLER_RDID_QSPI256: + { + number_of_sectors = 512; + break; + } + case ALTERA_QSPI_CONTROLLER_RDID_QSPI512: + { + number_of_sectors = 1024; + break; + } + case ALTERA_QSPI_CONTROLLER_RDID_QSPI1024: + { + number_of_sectors = 2048; + break; + } + default: + { + return -ENODEV; + } + } + } + else { + /* If we're an EPCS, we read QSPI_RD_SID for the silicon ID */ + silicon_id = IORD_ALTERA_QSPI_CONTROLLER_SID(flash->csr_base); + silicon_id &= ALTERA_QSPI_CONTROLLER_SID_MASK; + + /* Determine which EPCS device so we can figure out various properties */ + switch(silicon_id) + { + case ALTERA_QSPI_CONTROLLER_SID_EPCS16: + { + number_of_sectors = 32; + break; + } + case ALTERA_QSPI_CONTROLLER_SID_EPCS64: + { + number_of_sectors = 128; + break; + } + case ALTERA_QSPI_CONTROLLER_SID_EPCS128: + { + number_of_sectors = 256; + break; + } + default: + { + return -ENODEV; + } + } + } + + /* Calculate size of flash based on number of sectors */ + size_in_bytes = number_of_sectors * flash->sector_size; + + /* + * Make sure calculated size is the same size given in system.h + * Also check number of sectors is the same number given in system.h + * Otherwise the QSPI IP was not configured correctly + */ + if( size_in_bytes != flash->size_in_bytes || + number_of_sectors != flash->number_of_sectors) + { + flash->dev.number_of_regions = 0; + return -ENODEV; + } + else + { + flash->silicon_id = silicon_id; + flash->number_of_sectors = number_of_sectors; + + /* + * populate fields of region_info required to conform to HAL API + * create 1 region that composed of "number_of_sectors" blocks + */ + flash->dev.number_of_regions = 1; + flash->dev.region_info[0].offset = 0; + flash->dev.region_info[0].region_size = size_in_bytes; + flash->dev.region_info[0].number_of_blocks = number_of_sectors; + flash->dev.region_info[0].block_size = flash->sector_size; + } + + + /* + * Register this device as a valid flash device type + * + * Only register the device if it's configured correctly. + */ + alt_flash_device_register(&(flash->dev)); + + + return 0; +} + + +/* + * Private API + * + * Helper functions used by Public API functions. + * + * Arguments: + * - *flash_info: Pointer to QSPI flash device structure. + * - offset: Offset of read/write from base address. + * - length: Length of read/write in bytes. + * + * Returns: + * 0 -> success + * -EINVAL -> Invalid arguments + */ +/** + * Used to check that arguments to a read or write are valid + */ +ALT_INLINE alt_32 static alt_qspi_validate_read_write_arguments +( + alt_qspi_controller_dev *flash_info, /** device info */ + alt_u32 offset, /** offset of read/write */ + alt_u32 length /** length of read/write */ +) +{ + alt_qspi_controller_dev *qspi_flash_info = NULL; + alt_u32 start_address = 0; + alt_32 end_address = 0; + + /* return -EINVAL if flash_info is NULL */ + if(NULL == flash_info) + { + return -EINVAL; + } + + qspi_flash_info = (alt_qspi_controller_dev*)flash_info; + + start_address = qspi_flash_info->data_base + offset; /** first address of read or write */ + end_address = start_address + length; /** last address of read or write (not inclusive) */ + + /* make sure start and end address is less then the end address of the flash */ + if( + start_address >= qspi_flash_info->data_end || + end_address >= qspi_flash_info->data_end || + offset < 0 || + length < 0 + ) + { + return -EINVAL; + } + + return 0; +} + +/* + * Private function that polls write in progress bit QSPI_RD_STATUS. + * + * Write in progress will be set if any of the following operations are in progress: + * -WRITE STATUS REGISTER + * -WRITE NONVOLATILE CONFIGURATION REGISTER + * -PROGRAM + * -ERASE + * + * Assumes QSPI was configured correctly. + * + * If ALTERA_QSPI_CONTROLLER_1US_TIMEOUT_VALUE is set, the function will time out after + * a period of time determined by that value. + * + * Arguments: + * - *qspi_flash_info: Pointer to QSPI flash device structure. + * + * Returns: + * 0 -> success + * -EINVAL -> Invalid arguments + * -ETIME -> Time out and skipping the looping after 0.7 sec. + */ +alt_32 static alt_qspi_poll_for_write_in_progress(alt_qspi_controller_dev* qspi_flash_info) +{ + /* we'll want to implement timeout if a timeout value is specified */ +#if ALTERA_QSPI_CONTROLLER_1US_TIMEOUT_VALUE > 0 + alt_u32 timeout = ALTERA_QSPI_CONTROLLER_1US_TIMEOUT_VALUE; + alt_u16 counter = 0; +#endif + + /* return -EINVAL if qspi_flash_info is NULL */ + if(NULL == qspi_flash_info) + { + return -EINVAL; + } + + /* while Write in Progress bit is set, we wait */ + while((IORD_ALTERA_QSPI_CONTROLLER_STATUS(qspi_flash_info->csr_base) & + ALTERA_QSPI_CONTROLLER_STATUS_WIP_MASK) == + ALTERA_QSPI_CONTROLLER_STATUS_WIP_BUSY) + { + alt_busy_sleep(1); /* delay 1us */ +#if ALTERA_QSPI_CONTROLLER_1US_TIMEOUT_VALUE > 0 + if(timeout <= counter ) + { + return -ETIME; + } + + counter++; +#endif + + } + + return 0; +} + + diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_msgdma.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_msgdma.c new file mode 100644 index 0000000..db8449c --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_msgdma.c @@ -0,0 +1,1806 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2014 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include +#include +#include +#include +#include "altera_msgdma_descriptor_regs.h" +#include "altera_msgdma_csr_regs.h" +#include "altera_msgdma_response_regs.h" +#include "io.h" +#include "altera_msgdma.h" +#include "priv/alt_busy_sleep.h" +#include "sys/alt_errno.h" +#include "sys/alt_irq.h" +#include "sys/alt_stdio.h" +#include "sys/alt_cache.h" + + + + +/******************************************************************************* + * Private API + ******************************************************************************/ +static int alt_msgdma_write_standard_descriptor ( + alt_u32 *csr_base, + alt_u32 *descriptor_base, + alt_msgdma_standard_descriptor *descriptor); +static int alt_msgdma_write_extended_descriptor ( + alt_u32 *csr_base, + alt_u32 *descriptor_base, + alt_msgdma_extended_descriptor *descriptor); +static void alt_msgdma_irq(void *context); +static int alt_msgdma_construct_standard_descriptor( + alt_msgdma_dev *dev, + alt_msgdma_standard_descriptor *descriptor, + alt_u32 *read_address, + alt_u32 *write_address, + alt_u32 length, + alt_u32 control); +static int alt_msgdma_construct_extended_descriptor( + alt_msgdma_dev *dev, + alt_msgdma_extended_descriptor *descriptor, + alt_u32 *read_address, + alt_u32 *write_address, + alt_u32 length, + alt_u32 control, + alt_u16 sequence_number, + alt_u8 read_burst_count, + alt_u8 write_burst_count, + alt_u16 read_stride, + alt_u16 write_stride); +static int alt_msgdma_descriptor_async_transfer ( + alt_msgdma_dev *dev, + alt_msgdma_standard_descriptor *standard_desc, + alt_msgdma_extended_descriptor *extended_desc); +static int alt_msgdma_descriptor_sync_transfer ( + alt_msgdma_dev *dev, + alt_msgdma_standard_descriptor *standard_desc, + alt_msgdma_extended_descriptor *extended_desc); +/* The list of registered msgdma components */ +ALT_LLIST_HEAD(alt_msgdma_list); + +/* + * Functions for writing descriptor structure to the dispatcher. If you disable + * some of the extended features in the hardware then you should pass in 0 for + * that particular descriptor element. These disabled elements will not be + * buffered by the dispatcher block. + * + * This function is non-blocking and will return an error code if there is no + * room to write another descriptor to the dispatcher. It is recommended to call + * 'read_descriptor_buffer_full' and make sure it returns '0' before calling + * this function. + */ +static int alt_msgdma_write_standard_descriptor ( + alt_u32 *csr_base, + alt_u32 *descriptor_base, + alt_msgdma_standard_descriptor *descriptor) +{ + if (0 != (IORD_ALTERA_MSGDMA_CSR_STATUS(csr_base) & + ALTERA_MSGDMA_CSR_DESCRIPTOR_BUFFER_FULL_MASK)) + { + /*at least one descriptor buffer is full, returning so that this function + is non-blocking*/ + return -ENOSPC; + } + + IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS(descriptor_base, + (alt_u32)descriptor->read_address); + IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS(descriptor_base, + ( alt_u32)descriptor->write_address); + IOWR_ALTERA_MSGDMA_DESCRIPTOR_LENGTH(descriptor_base, + descriptor->transfer_length); + IOWR_ALTERA_MSGDMA_DESCRIPTOR_CONTROL_STANDARD(descriptor_base, + descriptor->control); + return 0; +} + +/* + * This function is used for writing extended descriptors to the dispatcher. + It handles only 32-bit descriptors. + */ +static int alt_msgdma_write_extended_descriptor ( + alt_u32 *csr_base, + alt_u32 *descriptor_base, + alt_msgdma_extended_descriptor *descriptor) +{ + if (0 != (IORD_ALTERA_MSGDMA_CSR_STATUS(csr_base) & + ALTERA_MSGDMA_CSR_DESCRIPTOR_BUFFER_FULL_MASK)) + { + /*at least one descriptor buffer is full, returning so that this function + is non-blocking*/ + return -ENOSPC; + } + + IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS( + descriptor_base, + (alt_u32)descriptor->read_address_low); + IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS( + descriptor_base, + (alt_u32)descriptor->write_address_low); + IOWR_ALTERA_MSGDMA_DESCRIPTOR_LENGTH( + descriptor_base, + descriptor->transfer_length); + IOWR_ALTERA_MSGDMA_DESCRIPTOR_SEQUENCE_NUMBER( + descriptor_base, + descriptor->sequence_number); + IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_BURST( + descriptor_base, + descriptor->read_burst_count); + IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_BURST( + descriptor_base, + descriptor->write_burst_count); + IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_STRIDE( + descriptor_base, + descriptor->read_stride); + IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_STRIDE( + descriptor_base, + descriptor->write_stride); + IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS_HIGH(descriptor_base, 0); + IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS_HIGH(descriptor_base, 0); + IOWR_ALTERA_MSGDMA_DESCRIPTOR_CONTROL_ENHANCED( + descriptor_base, + descriptor->control); + return 0; +} + +/* + * alt_msgdma_irq() + * + * Interrupt handler for the Modular Scatter-Gather DMA controller. + */ +static void alt_msgdma_irq(void *context) +{ + alt_msgdma_dev *dev = (alt_msgdma_dev *) context; + alt_irq_context cpu_sr; + alt_u32 temporary_control; + + + /* disable global interrupt*/ + if (dev->prefetcher_enable) + { + temporary_control = + IORD_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base) + & ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_CLR_MASK; + + IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, + temporary_control); + + /* clear the IRQ status- W1C */ + IOWR_ALT_MSGDMA_PREFETCHER_STATUS(dev->prefetcher_base, + ALT_MSGDMA_PREFETCHER_STATUS_IRQ_SET_MASK); + } + else + { + temporary_control = IORD_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base) + & (~ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK); + + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, temporary_control); + /* clear the IRQ status */ + IOWR_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base, + ALTERA_MSGDMA_CSR_IRQ_SET_MASK); + } + + /* + * Other interrupts are explicitly disabled if callbacks + * are registered because there is no guarantee that they are + * pre-emption-safe. This allows the driver to support + * interrupt pre-emption. + */ + if(dev->callback) + { + cpu_sr = alt_irq_disable_all(); + dev->callback (dev->callback_context); + alt_irq_enable_all(cpu_sr); + } + + /* enable global interrupt */ + if (dev->prefetcher_enable) + { + temporary_control = + IORD_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base) + | ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_SET_MASK; + + IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, + temporary_control); + } + else + { + temporary_control = IORD_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base) + | (ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK); + + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, temporary_control); + } + + return; +} +/* + * Helper functions for constructing mm_to_st, st_to_mm, mm_to_mm standard + * descriptors. Unnecessary elements are set to 0 for completeness and will be + * ignored by the hardware. + * Returns: + * - status: return 0 (success) + * return -EINVAL (invalid argument, could be due to argument which + * has larger value than hardware setting value) + */ +static int alt_msgdma_construct_standard_descriptor( + alt_msgdma_dev *dev, + alt_msgdma_standard_descriptor *descriptor, + alt_u32 *read_address, + alt_u32 *write_address, + alt_u32 length, + alt_u32 control) +{ + if(dev->max_byte < length || + dev->enhanced_features != 0 + ) + { + return -EINVAL; + } + descriptor->read_address = read_address; + descriptor->write_address = write_address; + descriptor->transfer_length = length; + descriptor->control = control | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK; + + return 0; +} + +/* + * Helper functions for constructing mm_to_st, st_to_mm, mm_to_mm extended + * descriptors. Unnecessary elements are set to 0 for completeness and will be + * ignored by the hardware. + * Returns: + * - status: return 0 (success) + * return -EINVAL (invalid argument, could be due to argument which + * has larger value than hardware setting value) + */ +static int alt_msgdma_construct_extended_descriptor( + alt_msgdma_dev *dev, + alt_msgdma_extended_descriptor *descriptor, + alt_u32 *read_address, + alt_u32 *write_address, + alt_u32 length, + alt_u32 control, + alt_u16 sequence_number, + alt_u8 read_burst_count, + alt_u8 write_burst_count, + alt_u16 read_stride, + alt_u16 write_stride) +{ + if(dev->max_byte < length || + dev->max_stride < read_stride || + dev->max_stride < write_stride || + dev->enhanced_features != 1 + ) + { + return -EINVAL; + } + + descriptor->read_address_low = read_address; + descriptor->write_address_low = write_address; + descriptor->transfer_length = length; + descriptor->sequence_number = sequence_number; + descriptor->read_burst_count = read_burst_count; + descriptor->write_burst_count = write_burst_count; + descriptor->read_stride = read_stride; + descriptor->write_stride = write_stride; + descriptor->read_address_high = NULL; + descriptor->write_address_high = NULL; + descriptor->control = control | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK; + + return 0 ; + +} + +/* + * Helper functions for descriptor in async transfer. + * Arguments:# This driver supports HAL types + * - *dev: Pointer to msgdma device (instance) structure. + * - *standard_desc: Pointer to single standard descriptor. + * - *extended_desc: Pointer to single extended descriptor. + * + *note: Either one of both *standard_desc and *extended_desc must + * be assigned with NULL, another with proper pointer value. + * Failing to do so can cause the function return with "-EPERM " + * + * If a callback routine has been previously registered with this + * particular msgdma controller, transfer will be set up to enable interrupt + * generation. It is the responsibility of the application developer to check + * source interruption, status completion and creating suitable interrupt + * handling. Note: "stop on error" of CSR control register is always masking + * within this function. The CSR control can be set by user through calling + * "alt_register_callback" by passing user used defined control setting. + * + * Returns: + * 0 -> success + * -ENOSPC -> FIFO descriptor buffer is full + * -EPERM -> operation not permitted due to descriptor type conflict + * -ETIME -> Time out and skipping the looping after 5 msec. + */ +static int alt_msgdma_descriptor_async_transfer ( + alt_msgdma_dev *dev, + alt_msgdma_standard_descriptor *standard_desc, + alt_msgdma_extended_descriptor *extended_desc) +{ + alt_u32 control = 0; + alt_irq_context context = 0; + alt_u16 counter = 0; + alt_u32 fifo_read_fill_level = ( + IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(dev->csr_base) & + ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_MASK) >> + ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_OFFSET; + alt_u32 fifo_write_fill_level = ( + IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(dev->csr_base) & + ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_MASK) >> + ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_OFFSET; + + /* Return with error immediately if one of read/write buffer is full */ + if((dev->descriptor_fifo_depth <= fifo_write_fill_level) || + (dev->descriptor_fifo_depth <= fifo_read_fill_level)) + { + /*at least one write or read FIFO descriptor buffer is full, + returning so that this function is non-blocking*/ + return -ENOSPC; + } + + /* + * When running in a multi threaded environment, obtain the "regs_lock" + * semaphore. This ensures that accessing registers is thread-safe. + */ + ALT_SEM_PEND (dev->regs_lock, 0); + + /* Stop the msgdma dispatcher from issuing more descriptors to the + read or write masters */ + /* stop issuing more descriptors */ + control = ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK; + /* making sure the read-modify-write below can't be pre-empted */ + context = alt_irq_disable_all(); + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, control); + /* + * Clear any (previous) status register information + * that might occlude our error checking later. + */ + IOWR_ALTERA_MSGDMA_CSR_STATUS( + dev->csr_base, + IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base)); + alt_irq_enable_all(context); + + if (NULL != standard_desc && NULL == extended_desc) + { + /*writing descriptor structure to the dispatcher, wait until descriptor + write is succeed*/ + while(0 != alt_msgdma_write_standard_descriptor ( + dev->csr_base, dev->descriptor_base, standard_desc)) + { + alt_busy_sleep(1); /* delay 1us */ + if(5000 <= counter) /* time_out if waiting longer than 5 msec */ + { + alt_printf("time out after 5 msec while waiting" + " free FIFO buffer for storing standard descriptor\n"); + + /* + * Now that access to the registers is complete, release the + * registers semaphore so that other threads can access the + * registers. + */ + ALT_SEM_POST (dev->regs_lock); + + return -ETIME; + } + counter++; + } + } + else if (NULL == standard_desc && NULL != extended_desc) + { + counter = 0; /* reset counter */ + /*writing descriptor structure to the dispatcher, wait until descriptor + write is succeed*/ + while(0 != alt_msgdma_write_extended_descriptor ( + dev->csr_base, + dev->descriptor_base, + extended_desc)) + { + alt_busy_sleep(1); /* delay 1us */ + if(5000 <= counter) /* time_out if waiting longer than 5 msec */ + { + alt_printf("time out after 5 msec while waiting free FIFO buffer" + " for storing extended descriptor\n"); + /* + * Now that access to the registers is complete, release the + * registers semaphore so that other threads can access the + * registers. + */ + ALT_SEM_POST (dev->regs_lock); + + return -ETIME; + } + counter++; + } + } + else + { + /* + * Now that access to the registers is complete, release the registers + * semaphore so that other threads can access the registers. + */ + ALT_SEM_POST (dev->regs_lock); + + /* operation not permitted due to descriptor type conflict */ + return -EPERM; + } + + /* + * If a callback routine has been previously registered which will be + * called from the msgdma ISR. Set up controller to: + * - Run + * - Stop on an error with any particular descriptor + */ + if(dev->callback) + { + + control |= (dev->control | + ALTERA_MSGDMA_CSR_STOP_ON_ERROR_MASK | + ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK ); + control &= (~ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK); + /* making sure the read-modify-write below can't be pre-empted */ + context = alt_irq_disable_all(); + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, control); + alt_irq_enable_all(context); + } + /* + * No callback has been registered. Set up controller to: + * - Run + * - Stop on an error with any particular descriptor + * - Disable interrupt generation + */ + else + { + control |= (dev->control | + ALTERA_MSGDMA_CSR_STOP_ON_ERROR_MASK ); + control &= (~ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK) & + (~ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK); + /* making sure the read-modify-write below can't be pre-empted */ + context = alt_irq_disable_all(); + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, control); + alt_irq_enable_all(context); + } + + /* + * Now that access to the registers is complete, release the registers + * semaphore so that other threads can access the registers. + */ + ALT_SEM_POST (dev->regs_lock); + + return 0; +} + +/* + * Helper functions for descriptor in sync transfer. + * Arguments: + * - *dev: Pointer to msgdma device (instance) structure. + * - *standard_desc: Pointer to single standard descriptor. + * - *extended_desc: Pointer to single extended descriptor. + * + * Note: Either one of both *standard_desc and *extended_desc must + * be assigned with NULL, another with proper pointer value. + * Failing to do so can cause the function return with "-EPERM " + * + * "stop on error" of CSR control register is always being masked and interrupt + * is always disabled within this function. + * The CSR control can be set by user through calling "alt_register_callback" + * with passing user defined control setting. + * + * Returns: + * 0 -> success + * error -> errors or conditions causing msgdma stop issuing commands to masters. + * check the bit set in the error with CSR status register. + * -EPERM -> operation not permitted due to descriptor type conflict + * -ETIME -> Time out and skipping the looping after 5 msec. + */ +static int alt_msgdma_descriptor_sync_transfer ( + alt_msgdma_dev *dev, + alt_msgdma_standard_descriptor *standard_desc, + alt_msgdma_extended_descriptor *extended_desc) +{ + alt_u32 control=0; + alt_irq_context context=0; + alt_u32 csr_status = 0; + alt_u16 counter = 0; + alt_u32 fifo_read_fill_level = ( + IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(dev->csr_base) & + ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_MASK) >> + ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_OFFSET; + alt_u32 fifo_write_fill_level = ( + IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(dev->csr_base) & + ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_MASK) >> + ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_OFFSET; + alt_u32 error = ALTERA_MSGDMA_CSR_STOPPED_ON_ERROR_MASK | + ALTERA_MSGDMA_CSR_STOPPED_ON_EARLY_TERMINATION_MASK | + ALTERA_MSGDMA_CSR_STOP_STATE_MASK | + ALTERA_MSGDMA_CSR_RESET_STATE_MASK; + + /* Wait for available FIFO buffer to store new descriptor*/ + while ((dev->descriptor_fifo_depth <= fifo_write_fill_level) || + (dev->descriptor_fifo_depth <= fifo_read_fill_level)) + { + alt_busy_sleep(1); /* delay 1us */ + if(5000 <= counter) /* time_out if waiting longer than 5 msec */ + { + alt_printf("time out after 5 msec while waiting free FIFO buffer" + " for storing descriptor\n"); + return -ETIME; + } + counter++; + fifo_read_fill_level = ( + IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(dev->csr_base) & + ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_MASK) >> + ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_OFFSET; + fifo_write_fill_level = ( + IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(dev->csr_base) & + ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_MASK) >> + ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_OFFSET; + } + + /* + * When running in a multi threaded environment, obtain the "regs_lock" + * semaphore. This ensures that accessing registers is thread-safe. + */ + ALT_SEM_PEND (dev->regs_lock, 0); + + /* Stop the msgdma dispatcher from issuing more descriptors to the + read or write masters */ + /* making sure the read-modify-write below can't be pre-empted */ + context = alt_irq_disable_all(); + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, + ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK); + /* + * Clear any (previous) status register information + * that might occlude our error checking later. + */ + IOWR_ALTERA_MSGDMA_CSR_STATUS( + dev->csr_base, + IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base)); + + if (NULL != standard_desc && NULL == extended_desc) + { + counter = 0; /* reset counter */ + /*writing descriptor structure to the dispatcher, wait until descriptor + write is succeed*/ + while(0 != alt_msgdma_write_standard_descriptor ( + dev->csr_base, dev->descriptor_base, standard_desc)) + { + alt_busy_sleep(1); /* delay 1us */ + if(5000 <= counter) /* time_out if waiting longer than 5 msec */ + { + alt_printf("time out after 5 msec while writing standard" + " descriptor to FIFO\n"); + + /* + * Now that access to the registers is complete, release the + * registers semaphore so that other threads can access the + * registers. + */ + ALT_SEM_POST (dev->regs_lock); + + return -ETIME; + } + counter++; + } + } + else if (NULL == standard_desc && NULL != extended_desc) + { + counter = 0; /* reset counter */ + /*writing descriptor structure to the dispatcher, wait until descriptor + write is succeed*/ + while(0 != alt_msgdma_write_extended_descriptor ( + dev->csr_base, dev->descriptor_base, extended_desc)) + { + alt_busy_sleep(1); /* delay 1us */ + if(5000 <= counter) /* time_out if waiting longer than 5 msec */ + { + alt_printf("time out after 5 msec while writing extended" + " descriptor to FIFO\n"); + + /* + * Now that access to the registers is complete, release the + * registers semaphore so that other threads can access the + * registers. + */ + ALT_SEM_POST (dev->regs_lock); + + return -ETIME; + } + counter++; + } + } + else + { + /* + * Now that access to the registers is complete, release the registers + * semaphore so that other threads can access the registers. + */ + ALT_SEM_POST (dev->regs_lock); + + /* operation not permitted due to descriptor type conflict */ + return -EPERM; + } + + /* + * Set up msgdma controller to: + * - Disable interrupt generation + * - Run once a valid descriptor is written to controller + * - Stop on an error with any particular descriptor + */ + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, + (dev->control | + ALTERA_MSGDMA_CSR_STOP_ON_ERROR_MASK ) & + (~ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK) & + (~ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK)) ; + + alt_irq_enable_all(context); + + counter = 0; /* reset counter */ + + csr_status = IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base); + + /* Wait for any pending transfers to complete or checking any errors or + conditions causing descriptor to stop dispatching */ + while (!(csr_status & error) && (csr_status & ALTERA_MSGDMA_CSR_BUSY_MASK)) + { + alt_busy_sleep(1); /* delay 1us */ + if(5000 <= counter) /* time_out if waiting longer than 5 msec */ + { + alt_printf("time out after 5 msec while waiting for any pending" + " transfer complete\n"); + + /* + * Now that access to the registers is complete, release the registers + * semaphore so that other threads can access the registers. + */ + ALT_SEM_POST (dev->regs_lock); + + return -ETIME; + } + counter++; + csr_status = IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base); + } + + + /*Errors or conditions causing the dispatcher stopping issuing read/write + commands to masters*/ + if(0 != (csr_status & error)) + { + /* + * Now that access to the registers is complete, release the registers + * semaphore so that other threads can access the registers. + */ + ALT_SEM_POST (dev->regs_lock); + + return error; + } + + /* Stop the msgdma dispatcher from issuing more descriptors to the + read or write masters */ + /* stop issuing more descriptors */ + control = IORD_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base) | + ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK; + /* making sure the read-modify-write below can't be pre-empted */ + context = alt_irq_disable_all(); + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, control); + /* + * Clear any (previous) status register information + * that might occlude our error checking later. + */ + IOWR_ALTERA_MSGDMA_CSR_STATUS( + dev->csr_base, + IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base)); + alt_irq_enable_all(context); + + /* + * Now that access to the registers is complete, release the registers + * semaphore so that other threads can access the registers. + */ + ALT_SEM_POST (dev->regs_lock); + + return 0; + +} + +/* + * Functions for constructing standard descriptors. Unnecessary elements are + * set to 0 for completeness and will be ignored by the hardware. + * Returns: + * - status: return 0 (success) + * return -EINVAL (invalid argument, could be due to argument which + * has larger value than hardware setting value) + */ +int alt_msgdma_construct_standard_st_to_mm_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_standard_descriptor *descriptor, + alt_u32 *write_address, alt_u32 length, alt_u32 control) +{ + return alt_msgdma_construct_standard_descriptor(dev, descriptor, NULL, + write_address, length, control); +} + +int alt_msgdma_construct_standard_mm_to_st_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_standard_descriptor *descriptor, + alt_u32 *read_address, + alt_u32 length, + alt_u32 control) +{ + return alt_msgdma_construct_standard_descriptor(dev, descriptor, read_address, + NULL, length, control); + +} + +int alt_msgdma_construct_standard_mm_to_mm_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_standard_descriptor *descriptor, + alt_u32 *read_address, + alt_u32 *write_address, + alt_u32 length, + alt_u32 control) +{ + return alt_msgdma_construct_standard_descriptor(dev, descriptor, read_address, + write_address, length, control); +} + +/* + * Functions for constructing extended descriptors. If you disable some of the + * extended features in the hardware then you should pass in 0 for that + * particular descriptor element. These disabled elements will not be buffered + * by the dispatcher block. + * Returns: + * - status: return 0 (success) + * return -EINVAL (invalid argument, could be due to argument which + * has larger value than hardware setting value) + */ +int alt_msgdma_construct_extended_st_to_mm_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_extended_descriptor *descriptor, + alt_u32 *write_address, + alt_u32 length, + alt_u32 control, + alt_u16 sequence_number, + alt_u8 write_burst_count, + alt_u16 write_stride) +{ + return alt_msgdma_construct_extended_descriptor(dev, descriptor, + NULL, write_address, length, control, sequence_number, 0, + write_burst_count, 0, write_stride); +} + +int alt_msgdma_construct_extended_mm_to_st_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_extended_descriptor *descriptor, + alt_u32 *read_address, + alt_u32 length, + alt_u32 control, + alt_u16 sequence_number, + alt_u8 read_burst_count, + alt_u16 read_stride) +{ + return alt_msgdma_construct_extended_descriptor(dev, descriptor, read_address, + NULL, length, control, sequence_number, read_burst_count, 0, + read_stride, 0); + +} + +int alt_msgdma_construct_extended_mm_to_mm_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_extended_descriptor *descriptor, + alt_u32 *read_address, + alt_u32 *write_address, + alt_u32 length, + alt_u32 control, + alt_u16 sequence_number, + alt_u8 read_burst_count, + alt_u8 write_burst_count, + alt_u16 read_stride, + alt_u16 write_stride) +{ + return alt_msgdma_construct_extended_descriptor(dev, descriptor, + read_address, write_address, length, control, sequence_number, + read_burst_count, write_burst_count, read_stride, write_stride); + +} + +/********************** MSGDMA PREFETCHER PRIVATE APIs *************************/ + +/* + * Base functions for constructing mm_to_st, st_to_mm, mm_to_mm standard + * descriptors for the prefetcher. Unnecessary elements are set to 0 for + * completeness and will be ignored by the hardware. + * The descriptor created will be suitable for park since this API will set next_ptr + * to itself as park_mode requires. Additionally OWN_BY_HW bit left as 0 (owned by sw) + * until the prefetcher is started with this descriptor in the list. + * Returns: + * - status: return 0 (success) + * return -EINVAL (invalid argument, could be due to argument which + * has larger value than hardware setting value) + */ +static int alt_msgdma_construct_prefetcher_standard_descriptor( + alt_msgdma_dev *dev, + alt_msgdma_prefetcher_standard_descriptor *descriptor, + alt_u32 read_address, + alt_u32 write_address, + alt_u32 length, + alt_u32 control) +{ + if(dev->max_byte < length || + dev->enhanced_features != 0 + ) + { + return -EINVAL; + } + descriptor->read_address = read_address; + descriptor->write_address = write_address; + descriptor->transfer_length = length; + /* have descriptor point to itself for park_mode */ + descriptor->next_desc_ptr = (alt_u32)descriptor; + + /* clear control own_by_hw bit field (SW owns this descriptor)*/ + descriptor->control = (control + & ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_CLR_MASK) + | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK; + + return 0; +} + +/* + * Base functions for constructing mm_to_st, st_to_mm, mm_to_mm extended + * descriptors. Unnecessary elements are set to 0 for completeness and will be + * ignored by the hardware. The descriptor created will be suitable for park + * mode since this API will set next_ptr to itself as park_mode requires. + * Additionally OWN_BY_HW bit left as 0 (owned by sw) until the prefetcher is + * started with this descriptor in the list. + * Returns: + * - status: return 0 (success) + * return -EINVAL (invalid argument, could be due to argument which + * has larger value than hardware setting value) + */ +static int alt_msgdma_construct_prefetcher_extended_descriptor( + alt_msgdma_dev *dev, + alt_msgdma_prefetcher_extended_descriptor *descriptor, + alt_u32 read_address_high, + alt_u32 read_address_low, + alt_u32 write_address_high, + alt_u32 write_address_low, + alt_u32 length, + alt_u32 control, + alt_u16 sequence_number, + alt_u8 read_burst_count, + alt_u8 write_burst_count, + alt_u16 read_stride, + alt_u16 write_stride) +{ + msgdma_addr64 node_addr; + + if(dev->max_byte < length || + dev->max_stride < read_stride || + dev->max_stride < write_stride || + dev->enhanced_features != 1 + ) + { + return -EINVAL; + } + + descriptor->read_address_high = read_address_high; + descriptor->read_address_low = read_address_low; + descriptor->write_address_high = write_address_high; + descriptor->write_address_low = write_address_low; + descriptor->transfer_length = length; + descriptor->sequence_number = sequence_number; + descriptor->read_burst_count = read_burst_count; + descriptor->write_burst_count = write_burst_count; + descriptor->read_stride = read_stride; + descriptor->write_stride = write_stride; + /* have descriptor point to itself */ + node_addr.u64 = (uintptr_t)descriptor; + descriptor->next_desc_ptr_low = node_addr.u32[0]; + descriptor->next_desc_ptr_high = node_addr.u32[1]; + + /* clear control own_by_hw bit field (SW still owns this descriptor). */ + descriptor->control = (control + & ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_CLR_MASK) + | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK; + + return 0 ; +} + + +/********************** MSGDMA PREFETCHER PUBLIC APIs ************************/ + +/* + * Functions for constructing standard descriptors. Unnecessary elements are + * set to 0 for completeness and will be ignored by the hardware. + * Returns: + * - status: return 0 (success) + * return -EINVAL (invalid argument, could be due to argument which + * has larger value than hardware setting value) + */ +int alt_msgdma_construct_prefetcher_standard_mm_to_mm_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_prefetcher_standard_descriptor *descriptor, + alt_u32 read_address, + alt_u32 write_address, + alt_u32 length, + alt_u32 control) +{ + return alt_msgdma_construct_prefetcher_standard_descriptor(dev, descriptor, + read_address, write_address, length, control); +} + +int alt_msgdma_construct_prefetcher_standard_st_to_mm_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_prefetcher_standard_descriptor *descriptor, + alt_u32 write_address, + alt_u32 length, + alt_u32 control) +{ + return alt_msgdma_construct_prefetcher_standard_descriptor(dev, descriptor, + 0, write_address, length, control); +} + +int alt_msgdma_construct_prefetcher_standard_mm_to_st_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_prefetcher_standard_descriptor *descriptor, + alt_u32 read_address, + alt_u32 length, + alt_u32 control) +{ + return alt_msgdma_construct_prefetcher_standard_descriptor(dev, descriptor, + read_address, 0, length, control); +} + + +/* + * Functions for constructing extended descriptors. If you disable some of the + * extended features in the hardware then you should pass in 0 for that + * particular descriptor element. These disabled elements will not be buffered + * by the dispatcher block. + * Returns: + * - status: return 0 (success) + * return -EINVAL (invalid argument, could be due to argument which + * has larger value than hardware setting value) + */ +int alt_msgdma_construct_prefetcher_extended_st_to_mm_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_prefetcher_extended_descriptor *descriptor, + alt_u32 write_address_high, + alt_u32 write_address_low, + alt_u32 length, + alt_u32 control, + alt_u16 sequence_number, + alt_u8 write_burst_count, + alt_u16 write_stride) +{ + return alt_msgdma_construct_prefetcher_extended_descriptor(dev, descriptor, + 0, 0, write_address_high, write_address_low, length, control, + sequence_number, 0, write_burst_count, 0, write_stride); +} + +int alt_msgdma_construct_prefetcher_extended_mm_to_st_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_prefetcher_extended_descriptor *descriptor, + alt_u32 read_address_high, + alt_u32 read_address_low, + alt_u32 length, + alt_u32 control, + alt_u16 sequence_number, + alt_u8 read_burst_count, + alt_u16 read_stride) +{ + return alt_msgdma_construct_prefetcher_extended_descriptor(dev, descriptor, + read_address_high, read_address_low, 0, 0, length, control, + sequence_number, read_burst_count, 0, read_stride, 0); +} + +int alt_msgdma_construct_prefetcher_extended_mm_to_mm_descriptor ( + alt_msgdma_dev *dev, + alt_msgdma_prefetcher_extended_descriptor *descriptor, + alt_u32 read_address_high, + alt_u32 read_address_low, + alt_u32 write_address_high, + alt_u32 write_address_low, + alt_u32 length, + alt_u32 control, + alt_u16 sequence_number, + alt_u8 read_burst_count, + alt_u8 write_burst_count, + alt_u16 read_stride, + alt_u16 write_stride) +{ + return alt_msgdma_construct_prefetcher_extended_descriptor(dev, descriptor, + read_address_high, read_address_low, write_address_high, + write_address_low, length, control, sequence_number, + read_burst_count, write_burst_count, read_stride, write_stride); + +} + +/* PREFETCHER linked list APIs */ +/* + * Function for adding standard descriptors to a standard descriptor list + * Returns: + * - status: return 0 (success) + * return -EINVAL (invalid argument, could be due to descriptor + * already being in the list, descriptor pointer being NULL, or + * descriptor.next_ptr not pointing back to itslef) + */ +int alt_msgdma_prefetcher_add_standard_desc_to_list ( + alt_msgdma_prefetcher_standard_descriptor** list, + alt_msgdma_prefetcher_standard_descriptor* descriptor) +{ + alt_msgdma_prefetcher_standard_descriptor *last_descr_ptr; + + if (descriptor == NULL) + { + return -EINVAL; /* this descriptor cannot be NULL */ + } + if (descriptor->next_desc_ptr != (alt_u32)descriptor) + { + return -EINVAL; /* descriptor.next_ptr must point to itself */ + } + if (*list == NULL) + { + *list = descriptor; /* make this root-node if list is empty */ + return 0; /* successfully added */ + } + if (*list == descriptor) + { + return -EINVAL; /* this descriptor cannot already be root-node */ + } + + /* get to last node in the list */ + last_descr_ptr = *list; /* start at list root-node */ + /* traverse list until you get the last node */ + while (last_descr_ptr->next_desc_ptr != (alt_u32)*list) + { + if (last_descr_ptr->next_desc_ptr == (alt_u32)descriptor) + { + return -EINVAL; /* descriptor cannot already be in the list */ + } + last_descr_ptr = + (alt_msgdma_prefetcher_standard_descriptor*)(last_descr_ptr->next_desc_ptr); + } + /* add this descriptor to end of list */ + last_descr_ptr->next_desc_ptr = (alt_u32)((uintptr_t)descriptor); + /* ensure new last pointer points the start of the list */ + descriptor->next_desc_ptr = (alt_u32)((uintptr_t)*list); + return 0; /* successfully added */ +} + +int alt_msgdma_prefetcher_add_extended_desc_to_list ( + alt_msgdma_prefetcher_extended_descriptor** list, + alt_msgdma_prefetcher_extended_descriptor* descriptor) +{ + alt_msgdma_prefetcher_extended_descriptor *last_descr_ptr; + msgdma_addr64 root_node_addr, next_node_addr; + + if (descriptor == NULL) + { + return -EINVAL; /* this descriptor cannot be NULL */ + } + + next_node_addr.u64 = (uintptr_t)descriptor; + if( (descriptor->next_desc_ptr_low != next_node_addr.u32[0]) || + (descriptor->next_desc_ptr_high != next_node_addr.u32[1])) + { + return -EINVAL; /* descriptor.next_ptr must point to itself */ + } + + if (*list == NULL) + { + *list = descriptor; /* make this the root-node if list is empty */ + return 0; + } + if (*list == descriptor) + { + return -EINVAL; /* this descriptor cannot already be root-node */ + } + + /* get to last node in the list */ + last_descr_ptr = *list; /* start at list root-node */ + /* the last nodes next ptr should point to the root node*/ + root_node_addr.u64 = (uintptr_t)*list; + + /* traverse list until you get the last node */ + while ((last_descr_ptr->next_desc_ptr_low != root_node_addr.u32[0]) + || (last_descr_ptr->next_desc_ptr_high != root_node_addr.u32[1])) + { + /* first check if descriptor already in the list */ + next_node_addr.u64 = (uintptr_t)descriptor; + if ((last_descr_ptr->next_desc_ptr_low == next_node_addr.u32[0]) + && (last_descr_ptr->next_desc_ptr_high == next_node_addr.u32[1])) + { + return -EINVAL; /* descriptor cannot already be in the list */ + } + /* go to next node in list, using 64 bit address */ + next_node_addr.u32[0] = last_descr_ptr->next_desc_ptr_low; + next_node_addr.u32[1] = last_descr_ptr->next_desc_ptr_high; + last_descr_ptr = + (alt_msgdma_prefetcher_extended_descriptor*)((uintptr_t)next_node_addr.u64); + } + /* add this descriptor to end of list */ + next_node_addr.u64 = (uintptr_t)descriptor; + last_descr_ptr->next_desc_ptr_low = next_node_addr.u32[0]; + last_descr_ptr->next_desc_ptr_high = next_node_addr.u32[1]; + /* ensure new last pointer points the beginning of the list */ + descriptor->next_desc_ptr_low = root_node_addr.u32[0]; + descriptor->next_desc_ptr_high = root_node_addr.u32[1]; + return 0; +} + +/* + * Function to set all the own-by-hw bits. This is called right before starting + * prefetcher since if the create descriptor APIs were used to create the descriptor + * list, then the set_by_hw bits are still set to SW owned. + * Note the owned bits are automatically set when using the + * alt_msgdma_start_prefetcher_with_std_desc_list function and in that case + * this function should not be used. + * This function includes options for setting the last descriptor in the + * chain to owned by software, and for flushing the descriptor list from dcache. + */ +int alt_msgdma_prefetcher_set_std_list_own_by_hw_bits ( + alt_msgdma_prefetcher_standard_descriptor *list, + alt_u8 last_desc_owned_by_sw, + alt_u8 dcache_flush_desc_list) +{ + alt_u32 descriptor_control_field = 0; + alt_msgdma_prefetcher_standard_descriptor *last_descr_ptr; + alt_u32 descriptor_count = 0; + + if (list == NULL) + { + return -EINVAL; /* this list cannot be empty */ + } + + /* update all nodes in the list */ + last_descr_ptr = list; /* start at list root-node */ + /* traverse list to update all of the nodes */ + while (last_descr_ptr->next_desc_ptr != (alt_u32)list) + { + /* get current value */ + descriptor_control_field = last_descr_ptr->control; + /* update own_by_hw bit only */ + last_descr_ptr->control = descriptor_control_field + | ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET_MASK; + /* go to next node in list */ + last_descr_ptr = + (alt_msgdma_prefetcher_standard_descriptor*)(last_descr_ptr->next_desc_ptr); + + descriptor_count++; + } + /* update the last node in the list, currently last_descr_ptr after while loop */ + descriptor_control_field = last_descr_ptr->control; /* get current value */ + /* update own_by_hw bit only */ + if (last_desc_owned_by_sw) + { + last_descr_ptr->control = descriptor_control_field + & ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_CLR_MASK; + } + else { + last_descr_ptr->control = descriptor_control_field + | ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET_MASK; + } + + descriptor_count++; + + if (dcache_flush_desc_list) + { + alt_dcache_flush(list,sizeof(alt_msgdma_prefetcher_standard_descriptor) * descriptor_count); + } + + return 0; +} + +/* + * Function to set all the own-by-hw bits. This is called right before starting + * prefetcher since if the create descriptor APIs were used to create the descriptor + * list, then the set_by_hw bits are still set to SW owned. + * Note the owned bits are automatically set when using the + * alt_msgdma_start_prefetcher_with_extd_desc_list function and in that case + * this function should not be used. + * This function includes options for setting the last descriptor in the + * chain to owned by software, and for flushing the descriptor list from dcache. + */ +int alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits ( + alt_msgdma_prefetcher_extended_descriptor *list, + alt_u8 last_desc_owned_by_sw, + alt_u8 dcache_flush_desc_list) +{ + alt_u32 descriptor_control_field = 0; + msgdma_addr64 root_node_addr, next_node_addr; + alt_msgdma_prefetcher_extended_descriptor *last_descr_ptr; + alt_u32 descriptor_count = 0; + + if (list == NULL) + { + return -EINVAL; /* this list cannot be empty */ + } + + /* update all nodes in the list */ + last_descr_ptr = list; /* start at list root-node */ + /* the last nodes next ptr should point to the root node*/ + root_node_addr.u64 = (uintptr_t)list; + + /* traverse list until you get the last node */ + while ((last_descr_ptr->next_desc_ptr_low != root_node_addr.u32[0]) + || (last_descr_ptr->next_desc_ptr_high != root_node_addr.u32[1])) + { + /* start with current value */ + descriptor_control_field = last_descr_ptr->control; + /* update own_by_hw bit only */ + last_descr_ptr->control = descriptor_control_field + | ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET_MASK; + /* go to next node in list, using 64 bit address */ + next_node_addr.u32[0] = last_descr_ptr->next_desc_ptr_low; + next_node_addr.u32[1] = last_descr_ptr->next_desc_ptr_high; + last_descr_ptr = + (alt_msgdma_prefetcher_extended_descriptor*)((uintptr_t)next_node_addr.u64); + descriptor_count++; + } + /* update the last node in the list, currently last_descr_ptr after while loop */ + descriptor_control_field = last_descr_ptr->control; /* start with current value */ + /* update own_by_hw bit only */ + if (last_desc_owned_by_sw) + { + last_descr_ptr->control = descriptor_control_field + & ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_CLR_MASK; + } + else { + last_descr_ptr->control = descriptor_control_field + | ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET_MASK; + } + + descriptor_count++; + + if (dcache_flush_desc_list) + { + alt_dcache_flush(list,sizeof(alt_msgdma_prefetcher_extended_descriptor) * descriptor_count); + } + + return 0; +} + + +/* + * Functions to start the prefetcher. Will return error if prefetcher already + * started. + * + * Arguments:# This driver supports HAL types + * - *dev: Pointer to msgdma device (instance) structure. + * - *standard_desc: Pointer to single standard descriptor OR *extended_desc: + * Pointer to single extended descriptor. + * - park_mode_en: setting for prefetcher park mode + * - poll_en: setting for poll_en (IF poll frequency still 0 this API will + * also set that to a default non-zero value) + * + *note: Must call API specific to descriptor type. Either + * alt_msgdma_start_prefetcher_with_std_desc_list OR + * alt_msgdma_start_prefetcher_with_extd_desc_list + * where the list paratmeter is the root-node of your linked list. Then those + * APIs will call the base function accordingly. + * + * If a callback routine has been previously registered with this + * particular msgdma controller, transfer will be set up to enable interrupt + * generation. It is the responsibility of the application developer to check + * source interruption, status completion and creating suitable interrupt + * handling. + * Note: "stop on error" of CSR control register is always masking within this + * function. The CSR control can be set by user through calling + * "alt_register_callback" by passing user used defined control setting. + * + * Returns: + * 0 -> success + * -EBUSY -> prefetcher busy processing list already, it is up to user to stop + * prefetcher/dispatcher correctly before calling this function. + * if already busy will always return error. + */ + +/* + * Base function to start prefetcher. + */ +int alt_msgdma_start_prefetcher_with_list_addr ( + alt_msgdma_dev *dev, + alt_u64 list_addr, + alt_u8 park_mode_en, + alt_u8 poll_en) +{ + alt_u32 prefetcher_ctl = 0; + alt_u32 dispatcher_ctl = 0; + alt_irq_context context = 0; + + /* use helper struct to get easy access to hi/low address */ + msgdma_addr64 root_node_addr; + root_node_addr.u64 = list_addr; + + /* + * When running in a multi threaded environment, obtain the "regs_lock" + * semaphore. This ensures that accessing registers is thread-safe. + */ + ALT_SEM_PEND (dev->regs_lock, 0); + + /* case where prefetcher already started, return busy error */ + prefetcher_ctl = IORD_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base); + if(ALT_MSGDMA_PREFETCHER_CTRL_RUN_GET(prefetcher_ctl)){ + /* release the registers semaphore */ + ALT_SEM_POST (dev->regs_lock); + return -EBUSY; + } + + /* Stop the msgdma dispatcher from issuing more descriptors to the + read or write masters */ + /* stop issuing more descriptors */ + dispatcher_ctl = ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK; + + /* making sure the read-modify-write below can't be pre-empted */ + context = alt_irq_disable_all(); + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, dispatcher_ctl); + /* + * Clear any (previous) status register information + * that might occlude our error checking later. + */ + IOWR_ALTERA_MSGDMA_CSR_STATUS( dev->csr_base, + IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base)); + + alt_irq_enable_all(context); + + /* + * If a callback routine has been previously registered which will be + * called from the msgdma ISR. Set up dispatcher to: + * - Run + * - Stop on an error with any particular descriptor + */ + if(dev->callback) + { + dispatcher_ctl |= (dev->control | ALTERA_MSGDMA_CSR_STOP_ON_ERROR_MASK + | ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK ); + dispatcher_ctl &= (~ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK); + + prefetcher_ctl |= ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_SET_MASK; + /* making sure the read-modify-write below can't be pre-empted */ + context = alt_irq_disable_all(); + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, dispatcher_ctl); + IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, prefetcher_ctl); + alt_irq_enable_all(context); + } + /* + * No callback has been registered. Set up dispatcher to: + * - Run + * - Stop on an error with any particular descriptor + * - Disable interrupt generation + */ + else + { + dispatcher_ctl |= (dev->control | ALTERA_MSGDMA_CSR_STOP_ON_ERROR_MASK); + dispatcher_ctl &= (~ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK) + & (~ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK); + prefetcher_ctl &= ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_CLR_MASK; + /* making sure the read-modify-write below can't be pre-empted */ + context = alt_irq_disable_all(); + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, dispatcher_ctl); + IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, prefetcher_ctl); + alt_irq_enable_all(context); + } + + /* set next descriptor registers to point to the list root-node */ + IOWR_ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW(dev->prefetcher_base, + root_node_addr.u32[0]); + IOWR_ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH(dev->prefetcher_base, + root_node_addr.u32[1]); + + /* set park-mode */ + if (park_mode_en){ + prefetcher_ctl |= ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE_SET_MASK; + } + else { + prefetcher_ctl &= ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE_CLR_MASK; + } + + /* set poll-en */ + if (poll_en){ + prefetcher_ctl |= ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN_MASK; + if(IORD_ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLLING_FREQ( + dev->prefetcher_base) == 0){ + /* set poll frequency to some non-zero default value */ + IOWR_ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLLING_FREQ( + dev->prefetcher_base, 0xFF); + } + } + else { + prefetcher_ctl &= ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN_CLR_MASK; + } + + /* set the prefetcher run bit */ + prefetcher_ctl |= ALT_MSGDMA_PREFETCHER_CTRL_RUN_SET_MASK; + /* start the dma since run bit is set */ + IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, prefetcher_ctl); + + /* + * Now that access to the registers is complete, release the registers + * semaphore so that other threads can access the registers. + */ + ALT_SEM_POST (dev->regs_lock); + + return 0; +} + +/* + * Public functions to start prefetcher. + * Note: The option last_desc_owned_by_sw has been added. + * The last descriptor in a chain usually must be set to owned by sw. + * In this case, the last descriptor does not actually transfer data. + * When set, this option will set all descriptors in a chain to hw owned + * and set the last to sw owned before starting the prefetcher. + * Note: The option dcache_flush_desc_list has been added. + * When set this will call a function to flush the + * descriptor list from dcache before starting the prefetcher. + * If park_mode_en is not set, and poll_en is not set, it is recommended to + * set both last_desc_owned_by_sw and dcache_flush_desc_list for proper + * prefetcher operation. + * Note: If options last_desc_owned_by_sw and dcache_flush_desc_list are not set + * This function will behave exactly the same as in previous revisions. + * Note: It is not necessary to call any functions to set the owned by hw bits + * before using these functions. + */ +int alt_msgdma_start_prefetcher_with_std_desc_list ( + alt_msgdma_dev *dev, + alt_msgdma_prefetcher_standard_descriptor *list, + alt_u8 park_mode_en, + alt_u8 poll_en, + alt_u8 last_desc_owned_by_sw, + alt_u8 dcache_flush_desc_list) +{ + if (alt_msgdma_prefetcher_set_std_list_own_by_hw_bits(list,last_desc_owned_by_sw,dcache_flush_desc_list) != 0) + { + return -EINVAL; + } + + return alt_msgdma_start_prefetcher_with_list_addr (dev, (uintptr_t)list, + park_mode_en, poll_en); +} + +int alt_msgdma_start_prefetcher_with_extd_desc_list ( + alt_msgdma_dev *dev, + alt_msgdma_prefetcher_extended_descriptor *list, + alt_u8 park_mode_en, + alt_u8 poll_en, + alt_u8 last_desc_owned_by_sw, + alt_u8 dcache_flush_desc_list) +{ + + if (alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits(list,last_desc_owned_by_sw,dcache_flush_desc_list) != 0) + { + return -EINVAL; + } + + return alt_msgdma_start_prefetcher_with_list_addr (dev, (uintptr_t)list, + park_mode_en, poll_en); +} + + +/* + * alt_msgdma_open - Retrieve a pointer to the msgdma + * + * Search the list of registered msgdma for one with the supplied name. + * + * The return value will be NULL on failure, and non-NULL otherwise. + * + * Arguments: + * - *name: Character pointer to name of msgdma peripheral as registered + * with the HAL. For example, an msgdma controller named "msgdma_0" + * in Qsys would be opened by asking for "/dev/msgdma_0_csr". + * + * Returns: + * - Pointer to msgdma device instance structure, or null if the device + * could not be opened. + */ +alt_msgdma_dev* alt_msgdma_open (const char* name) +{ + alt_msgdma_dev* dev = NULL; + + dev = (alt_msgdma_dev*) alt_find_dev (name, &alt_msgdma_list); + + if (NULL == dev) + { + ALT_ERRNO = ENODEV; + } + + return dev; +} + + +/* + * alt_msgdma_init() + * + * Initializes the Modular Scatter-Gather DMA controller. This routine is called + * from the ALTERA_MSGDMA_INIT macro and is called automatically + * by alt_sys_init.c + * + * This routine disables interrupts, descriptor processing, + * registers a specific instance of the device with the HAL, + * and installs an interrupt handler for the device. + */ +void alt_msgdma_init (alt_msgdma_dev *dev, alt_u32 ic_id, alt_u32 irq) +{ + extern alt_llist alt_msgdma_list; + alt_u32 temporary_control; + int error; + + if (dev->prefetcher_enable) + { + /* start prefetcher reset sequence */ + IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, + ALT_MSGDMA_PREFETCHER_CTRL_RESET_SET_MASK); + /* wait until hw clears the bit */ + while(ALT_MSGDMA_PREFETCHER_CTRL_RESET_GET( + IORD_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base))); + /* + * This reset is intended to be used along with reset dispatcher in + * dispatcher core. Once the reset sequence in prefetcher core has + * completed, software is expected to reset the dispatcher core, + * and polls for dispatcher's reset sequence to be completed. + */ + } + + /* Reset the registers and FIFOs of the dispatcher and master modules */ + /* set the reset bit, no need to read the control register first since + this write is going to clear it out */ + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, ALTERA_MSGDMA_CSR_RESET_MASK); + while(0 != (IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base) + & ALTERA_MSGDMA_CSR_RESET_STATE_MASK)); + /* + * Disable interrupts, halt descriptor processing, + * and clear status register content + */ + + /* disable global interrupt */ + temporary_control = IORD_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base) + & (~ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK); + /* stopping descriptor */ + temporary_control |= ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK; + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, temporary_control); + + /* clear the CSR status register */ + IOWR_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base, + IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base)); + + if (dev->prefetcher_enable) + { + /* clear all status bits that are set, since theyre W1C */ + IOWR_ALT_MSGDMA_PREFETCHER_STATUS(dev->prefetcher_base, + IORD_ALT_MSGDMA_PREFETCHER_STATUS(dev->prefetcher_base)); + } + + /* Register this instance of the msgdma controller with HAL */ + alt_dev_llist_insert((alt_dev_llist*) dev, &alt_msgdma_list); + + /* + * Creating semaphores used to protect access to the registers + * when running in a multi-threaded environment. + */ + error = ALT_SEM_CREATE (&dev->regs_lock, 1); + + if (!error) + { + /* Install IRQ handler */ + alt_ic_isr_register(ic_id, irq, alt_msgdma_irq, dev, 0x0); + } + else + { + alt_printf("failed to create semaphores\n"); + } + + return; + +} + + +/* + * alt_msgdma_register_callback + * + * Associate a user-specific routine with the msgdma interrupt handler. + * If a callback is registered, all non-blocking msgdma transfers will + * enable interrupts that will cause the callback to be executed. + * The callback runs as part of the interrupt service routine, and + * great care must be taken to follow the guidelines for acceptable + * interrupt service routine behaviour as described in the Nios II + * Software Developer's Handbook.However, user can change some of the CSR + * control setting in blocking transfer by calling this function. + * + * Note: To disable callbacks after registering one, this routine + * may be called passing 0x0 to the callback argument. + * + * Arguments: + * - *dev: Pointer to msgdma device (instance) structure. + * - callback: Pointer to callback routine to execute at interrupt level + * - control: For masking the source interruption and setting configuration in + * control register + */ +void alt_msgdma_register_callback( + alt_msgdma_dev *dev, + alt_msgdma_callback callback, + alt_u32 control, + void *context) +{ + dev->callback = callback; + dev->callback_context = context; + dev->control = control; + + return ; +} + +/* + * alt_msgdma_standard_descriptor_async_transfer + * + * Set up and commence a non-blocking transfer of one descriptors at a time. + * + * If the FIFO buffer for one of read/write is full at the time of this call, + * the routine will immediately return -ENOSPC, the application can then decide + * how to proceed without being blocked. + * + * Arguments: + * - *dev: Pointer to msgdma device (instance) struct. + * - *desc: Pointer to single (ready to run) descriptor. + * + * Returns: + * 0 -> success + * -ENOSPC -> FIFO descriptor buffer is full + * -EPERM -> operation not permitted due to descriptor type conflict + * -ETIME -> Time out and skipping the looping after 5 msec. + */ +int alt_msgdma_standard_descriptor_async_transfer( + alt_msgdma_dev *dev, + alt_msgdma_standard_descriptor *desc) +{ + /* + * Error detection/handling should be performed at the application + * or callback level as appropriate. + */ + return alt_msgdma_descriptor_async_transfer(dev, desc, NULL); + +} + + +/* + * alt_msgdma_extended_descriptor_async_transfer + * + * Set up and commence a non-blocking transfer of one descriptors at a time. + * + * If the FIFO buffer for one of read/write is full at the time of this call, + * the routine will immediately return -ENOSPC, the application can then + * decide how to proceed without being blocked. + * + * Arguments: + * - *dev: Pointer to msgdma device (instance) struct. + * - *desc: Pointer to single (ready to run) descriptor. + * + * Returns: + * 0 -> success + * -ENOSPC -> FIFO descriptor buffer is full + * -EPERM -> operation not permitted due to descriptor type conflict + * -ETIME -> Time out and skipping the looping after 5 msec. + */ +int alt_msgdma_extended_descriptor_async_transfer( + alt_msgdma_dev *dev, + alt_msgdma_extended_descriptor *desc) +{ + /* + * Error detection/handling should be performed at the application + * or callback level as appropriate. + */ + return alt_msgdma_descriptor_async_transfer(dev, NULL, desc); +} + + +/* + * alt_msgdma_standard_descriptor_sync_transfer + * + * This function will start commencing a blocking transfer of one standard + * descriptor at a time. If the FIFO buffer for one of read/write is full at the + * time of this call, the routine will wait until free FIFO buffer available for + * continue processing. + * + * The function will return "-1" if errors or conditions causing the dispatcher + * stop issuing the commands to both read and write masters before both read and + * write command buffers are empty. + * + * Additional error information is available in the status bits of + * each descriptor that the msgdma processed; it is the responsibility + * of the user's application to search through the descriptor + * to gather specific error information. + * + * Arguments: + * - *dev: Pointer to msgdma device (instance) structure. + * - *desc: Pointer to single (ready to run) descriptor. + * + * Returns: + * - status: return 0 (success) + * return error (errors or conditions causing msgdma stop issuing + * commands to masters) + * Suggest suggest checking the bit set in the error with CSR status + * register. + * return -EPERM (operation not permitted due to descriptor type + * conflict) + * return -ETIME (Time out and skipping the looping after 5 msec) + */ +int alt_msgdma_standard_descriptor_sync_transfer( + alt_msgdma_dev *dev, + alt_msgdma_standard_descriptor *desc) +{ + return alt_msgdma_descriptor_sync_transfer(dev, desc, NULL); +} + +/* + * alt_msgdma_extended_descriptor_sync_transfer + * + * This function will start commencing a blocking transfer of one extended + * descriptor at a time. If the FIFO buffer for one of read/write is full at the + * time of this call, the routine will wait until free FIFO buffer available for + * continue processing. + * + * The function will return "-1" if errors or conditions causing the dispatcher + * stop issuing the commands to both read and write masters before both read and + * write command buffers are empty. + * + * Additional error information is available in the status bits of + * each descriptor that the msgdma processed; it is the responsibility + * of the user's application to search through the descriptor + * to gather specific error information. + * + * + * Arguments: + * - *dev: Pointer to msgdma device (instance) structure. + * - *desc: Pointer to single (ready to run) descriptor. + * + * Returns: + * - status: return 0 (success) + * return error (errors or conditions causing msgdma stop issuing + * commands to masters) + * Suggest suggest checking the bit set in the error with CSR status + * register. + * return -EPERM (operation not permitted due to descriptor type + * conflict) + * return -ETIME (Time out and skipping the looping after 5 msec) + */ +int alt_msgdma_extended_descriptor_sync_transfer( + alt_msgdma_dev *dev, + alt_msgdma_extended_descriptor *desc) +{ + return alt_msgdma_descriptor_sync_transfer(dev, NULL, desc); +} + + + + + diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_onchip_flash.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_onchip_flash.c new file mode 100644 index 0000000..36482a4 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_onchip_flash.c @@ -0,0 +1,590 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2014 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include +#include +#include "sys/param.h" +#include "alt_types.h" +#include "sys/alt_debug.h" +#include "sys/alt_cache.h" +#include "altera_onchip_flash.h" +#include "altera_onchip_flash_regs.h" +#include "priv/alt_busy_sleep.h" + +ALT_LLIST_HEAD(altera_onchip_flash_list); + +/* + Public API + + Refer to "Using Flash Devices" in the + Developing Programs Using the Hardware Abstraction Layer chapter + of the Nios II Software Developer's Handbook. + +*/ + +/** + * alt_onchip_flash_read + * + * reads data from flash. +**/ +int alt_onchip_flash_read +( + alt_flash_dev *flash_info, + int offset, + void *dest_addr, + int length +) +{ + int ret_code = 0; + alt_onchip_flash_dev* flash = (alt_onchip_flash_dev*)flash_info; + + /* Make sure the input parameters is not outside of this device's range. */ + if ((offset >= flash->dev.length) || ((offset+length) > flash->dev.length)) { + return -EFAULT; + } + + memcpy(dest_addr, (alt_u8*)flash->dev.base_addr+offset, length); + + if (NULL != flash->csr_base) { + int read_status = IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & ALTERA_ONCHIP_FLASH_STATUS_READ_MSK; + if (read_status != ALTERA_ONCHIP_FLASH_STATUS_READ_PASSED) { + /* Read failed. Return error.*/ + ret_code = -EIO; + } + } + return ret_code; +} + +/** + * alt_onchip_flash_get_info + * + * gets the details of the erase region. +**/ +int alt_onchip_flash_get_info +( + alt_flash_fd *fd, + flash_region **info, + int *number_of_regions +) +{ + int ret_code = 0; + + alt_flash_dev* flash = (alt_flash_dev*)fd; + + if (NULL != number_of_regions) + { + /* Pass the number of region to user */ + *number_of_regions = flash->number_of_regions; + } + + if (!flash->number_of_regions) + { + ret_code = -ENOMEM; + } + else if (flash->number_of_regions > ALT_MAX_NUMBER_OF_FLASH_REGIONS) + { + ret_code = -EFAULT; + } + else + { + if (NULL != info) + { + /* Pass the table of erase blocks to user */ + *info = &flash->region_info[0]; + } + } + + return ret_code; +} + +/** + This function erases an individual flash erase block. +**/ +int alt_onchip_flash_erase_block +( + alt_flash_dev *flash_info, + int block_offset +) +{ + int ret_code = 0; + alt_onchip_flash_dev *flash = (alt_onchip_flash_dev*)flash_info; + int page_address; + + /* Make sure the input parameters is not outside of this device's range. */ + if (block_offset >= flash->dev.length) { + return -EFAULT; + } + + /* Make sure IP support write and erase operation */ + if ((flash->csr_base == NULL) || (flash->is_read_only)) { + return -ENODEV; + } + + /* The block_offset must be page size aligned */ + if ((block_offset & (flash->page_size - 1)) != 0) + { + /* The address is not aligned */ + return -EINVAL; + } + + /* Wait until flash controller idle */ + ret_code = alt_onchip_flash_poll_for_status_to_go_idle(flash); + if (ret_code != 0) + { + return ret_code; + } + + /* Enable write and erase operation */ + ALTERA_ONCHIP_FLASH_ENABLE_WRITE_AND_ERASE_OPERATION(flash->csr_base); + + /* Calculate Page erase address, it is 32bit word addressing*/ + page_address = block_offset / 4; + + /* Perform Page erase operation */ + ALTERA_ONCHIP_FLASH_PAGE_ERASE(flash->csr_base, page_address); + + /* Wait until flash controller idle */ + ret_code = alt_onchip_flash_poll_for_status_to_go_idle(flash); + + /* Wait until flash controller indicate erase passed */ + ret_code = alt_onchip_flash_poll_for_status_erase_passed(flash); + + /* Disable write and erase operation */ + ALTERA_ONCHIP_FLASH_DISABLE_WRITE_AND_ERASE_OPERATION(flash->csr_base); + + return ret_code; +} + +/** + * alt_onchip_flash_write_block + * + * This function writes one block of data to flash. + * It assume that someone has kindly erased the appropriate sector(s). + * + * Note: "block_offset" is the base of the current erase block. + * "data_offset" is the absolute address (from the 0-base of this + * device's memory) of the beginning of the write-destination. + * This device has no need for "block_offset", but it's included for + * function type compatibility. +**/ +int alt_onchip_flash_write_block +( + alt_flash_dev *flash_info, + int block_offset, + int data_offset, + const void *data, + int length +) +{ + int ret_code = 0; + alt_onchip_flash_dev *flash = (alt_onchip_flash_dev*)flash_info; + int buffer_offset = 0; + int length_of_current_write; + int current_data_offset = data_offset; + int next_data_offset; + alt_u32 chunk_of_data; + + /* Make sure the input parameters is not outside of this device's range. */ + if ( + (block_offset >= flash->dev.length) || + (data_offset >= flash->dev.length) || + (length > (flash->dev.length - data_offset)) + ) { + return -EFAULT; + } + + /* Make sure IP support support write and erase operation */ + if ((flash->csr_base == NULL) || (flash->is_read_only != 0)) { + return -ENODEV; + } + + /* Wait until flash controller idle */ + ret_code = alt_onchip_flash_poll_for_status_to_go_idle(flash); + if (ret_code != 0) + { + return ret_code; + } + + /* Enable write and erase operation */ + ALTERA_ONCHIP_FLASH_ENABLE_WRITE_AND_ERASE_OPERATION(flash->csr_base); + + /* Check data length */ + while (length) + { + /* Minimum write size to onchip flash is 32 bits of data */ + chunk_of_data = 0xFFFFFFFF; + + /* The start of data_offset must be 4 bytes (32 bits) aligned */ + if ((current_data_offset & (ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE - 1)) == 0) + { + /* The address is 4-byte aligned here */ + next_data_offset = (current_data_offset + ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE) & ~(ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE - 1); + length_of_current_write = MIN(length, next_data_offset - current_data_offset); + /* Prepare the 4 bytes chunk of data to be written */ + memcpy(&chunk_of_data, &((alt_u8*)data)[buffer_offset], length_of_current_write); + buffer_offset += length_of_current_write; + length -= length_of_current_write; + } else { + /* Calculate how many padding bytes need to be added before the start of a data offset */ + int padding = current_data_offset & (ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE - 1); + + /* Calculate new 4-byte aligned data offset */ + current_data_offset = current_data_offset - padding; + next_data_offset = (current_data_offset + ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE) & ~(ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE - 1); + length_of_current_write = MIN(length + padding, next_data_offset - current_data_offset); + /* Prepare the 4 bytes chunk of data to be written */ + memcpy((void *)(((int)&chunk_of_data) + (int)padding), &((alt_u8*)data)[buffer_offset], length_of_current_write - padding); + buffer_offset += length_of_current_write - padding; + length -= length_of_current_write - padding; + } + + /* Writing to flash via IO 32 bits at a time */ + IOWR_32DIRECT(flash->dev.base_addr, current_data_offset, chunk_of_data); + + /* Wait until flash controller idle */ + ret_code = alt_onchip_flash_poll_for_status_to_go_idle(flash); + if (ret_code != 0) + { + break; + } + + /* Wait until flash controller indicate write passed */ + ret_code = alt_onchip_flash_poll_for_status_write_passed(flash); + if (ret_code != 0) + { + break; + } + + /* Prepare to write next 4 bytes */ + current_data_offset = next_data_offset; + } + + /* Disable write and erase operation */ + ALTERA_ONCHIP_FLASH_DISABLE_WRITE_AND_ERASE_OPERATION(flash->csr_base); + + return ret_code; +} + +/** + * alt_onchip_flash_write + * + * Program the data into the flash at the selected address. + * + * The different between this function and alt_onchip_flash_write_block function + * is that this function (alt_onchip_flash_write) will automatically erase a block as needed + * +**/ +int alt_onchip_flash_write( + alt_flash_dev *flash_info, + int offset, + const void *src_addr, + int length +) +{ + int ret_code = 0; + int i,j; + int data_to_write; + int current_offset; + int full_length = length; + int start_offset = offset; + alt_onchip_flash_dev* flash = (alt_onchip_flash_dev*)flash_info; + + /* Make sure the input parameters is not outside of this device's range. */ + if ((offset >= flash->dev.length) || (length > (flash->dev.length - offset))) + { + return -EFAULT; + } + + /* + * First and foremost which sectors are affected? + */ + for(i=0;idev.number_of_regions;i++) + { + /* Is it in this erase block region?*/ + if((offset >= flash->dev.region_info[i].offset) && + (offset < (flash->dev.region_info[i].offset + + flash->dev.region_info[i].region_size))) + { + current_offset = flash->dev.region_info[i].offset; + + for(j=0;jdev.region_info[i].number_of_blocks;j++) + { + if ((offset >= current_offset ) && + (offset < (current_offset + + flash->dev.region_info[i].block_size))) + { + /* + * Check if the contents of the block are different + * from the data we wish to put there + */ + data_to_write = (current_offset + flash->dev.region_info[i].block_size - offset); + data_to_write = MIN(data_to_write, length); + if(memcmp(src_addr, (alt_u8*)flash->dev.base_addr+offset, data_to_write)) + { + ret_code = (*flash->dev.erase_block)(&flash->dev, current_offset); + + if (!ret_code) + { + ret_code = (*flash->dev.write_block)( + &flash->dev, + current_offset, + offset, + src_addr, + data_to_write); + } + } + + /* Was this the last block? */ + if ((length == data_to_write) || ret_code) + { + goto finished; + } + + length -= data_to_write; + offset = current_offset + flash->dev.region_info[i].block_size; + src_addr = (alt_u8*)src_addr + data_to_write; + } + current_offset += flash->dev.region_info[i].block_size; + } + } + } + +finished: + alt_dcache_flush((alt_u8*)flash->dev.base_addr+start_offset, full_length); + return ret_code; +} + +/** + * altera_onchip_flash_init + * + * alt_sys_init.c will call this function automatically through macro + * +**/ +void altera_onchip_flash_init +( + alt_onchip_flash_dev *flash +) +{ + /* A region is a sector of the onchip flash */ + int number_of_regions; + flash_region* region_info; + int sector1_status = ALTERA_ONCHIP_FLASH_STATUS_SECTOR1_AVAILABLE; + int sector2_status = ALTERA_ONCHIP_FLASH_STATUS_SECTOR2_AVAILABLE; + int sector3_status = ALTERA_ONCHIP_FLASH_STATUS_SECTOR3_AVAILABLE; + int sector4_status = ALTERA_ONCHIP_FLASH_STATUS_SECTOR4_AVAILABLE; + int sector5_status = ALTERA_ONCHIP_FLASH_STATUS_SECTOR5_AVAILABLE; + + /* Set up flash_region data structures. */ + number_of_regions = 0; + region_info = &flash->dev.region_info[0]; + + if (flash->csr_base != NULL) { + sector1_status = IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & ALTERA_ONCHIP_FLASH_STATUS_SECTOR1_MSK; + sector2_status = IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & ALTERA_ONCHIP_FLASH_STATUS_SECTOR2_MSK; + sector3_status = IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & ALTERA_ONCHIP_FLASH_STATUS_SECTOR3_MSK; + sector4_status = IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & ALTERA_ONCHIP_FLASH_STATUS_SECTOR4_MSK; + sector5_status = IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & ALTERA_ONCHIP_FLASH_STATUS_SECTOR5_MSK; + } + + if ((flash->sector1_enabled == 1) && (sector1_status != ALTERA_ONCHIP_FLASH_STATUS_SECTOR1_UNAVAILABLE)) { + + region_info[number_of_regions].offset = flash->sector1_start_addr; + region_info[number_of_regions].region_size = flash->sector1_end_addr - flash->sector1_start_addr + 1; + region_info[number_of_regions].number_of_blocks = flash->dev.region_info[number_of_regions].region_size / flash->page_size; + region_info[number_of_regions].block_size = flash->page_size; + + number_of_regions++; + } + + if ((flash->sector2_enabled == 1) && (sector2_status != ALTERA_ONCHIP_FLASH_STATUS_SECTOR2_UNAVAILABLE)) { + + region_info[number_of_regions].offset = flash->sector2_start_addr; + region_info[number_of_regions].region_size = flash->sector2_end_addr - flash->sector2_start_addr + 1; + region_info[number_of_regions].number_of_blocks = flash->dev.region_info[number_of_regions].region_size / flash->page_size; + region_info[number_of_regions].block_size = flash->page_size; + + number_of_regions++; + } + + if ((flash->sector3_enabled == 1) && (sector3_status != ALTERA_ONCHIP_FLASH_STATUS_SECTOR3_UNAVAILABLE)) { + + region_info[number_of_regions].offset = flash->sector3_start_addr; + region_info[number_of_regions].region_size = flash->sector3_end_addr - flash->sector3_start_addr + 1; + region_info[number_of_regions].number_of_blocks = flash->dev.region_info[number_of_regions].region_size / flash->page_size; + region_info[number_of_regions].block_size = flash->page_size; + + number_of_regions++; + } + + if ((flash->sector4_enabled == 1) && (sector4_status != ALTERA_ONCHIP_FLASH_STATUS_SECTOR4_UNAVAILABLE)) { + + region_info[number_of_regions].offset = flash->sector4_start_addr; + region_info[number_of_regions].region_size = flash->sector4_end_addr - flash->sector4_start_addr + 1; + region_info[number_of_regions].number_of_blocks = flash->dev.region_info[number_of_regions].region_size / flash->page_size; + region_info[number_of_regions].block_size = flash->page_size; + + number_of_regions++; + } + + if ((flash->sector5_enabled == 1) && (sector5_status != ALTERA_ONCHIP_FLASH_STATUS_SECTOR5_UNAVAILABLE)) { + + region_info[number_of_regions].offset = flash->sector5_start_addr; + region_info[number_of_regions].region_size = flash->sector5_end_addr - flash->sector5_start_addr + 1; + region_info[number_of_regions].number_of_blocks = flash->dev.region_info[number_of_regions].region_size / flash->page_size; + region_info[number_of_regions].block_size = flash->page_size; + + number_of_regions++; + } + + /* Update number of regions. */ + flash->dev.number_of_regions = number_of_regions; + + /* + * Register this device as a valid flash device type + */ + alt_flash_device_register(&(flash->dev)); +} + +/* + Private API + + Helper functions used by Public API functions. +*/ + + +/** + * alt_onchip_flash_poll_for_status_to_go_idle + * + * This function return non zero value when polling timeout. +**/ +int alt_onchip_flash_poll_for_status_to_go_idle +( + alt_onchip_flash_dev *flash +) +{ + int ret_code = 0; + int timeout = ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE; + int count_down = ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE; + + while ( + (IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & + ALTERA_ONCHIP_FLASH_STATUS_BUSY_MSK + ) != ALTERA_ONCHIP_FLASH_STATUS_BUSY_IDLE + ) { + + alt_busy_sleep(1); /* delay 1us */ + + /* If timeout value is zero, it will never timeout. */ + if (timeout != 0) { + count_down--; + if (count_down == 0) { + /* Timeout */ + ret_code = -ETIMEDOUT; + break; + } + } + } + + return ret_code; +} + +/** + * alt_onchip_flash_poll_for_status_erase_passed + * + * This function return non zero value when polling timeout. +**/ +int alt_onchip_flash_poll_for_status_erase_passed +( + alt_onchip_flash_dev *flash +) +{ + int ret_code = 0; + int timeout = ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE; + int count_down = ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE; + + while ( + (IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & + ALTERA_ONCHIP_FLASH_STATUS_ERASE_MSK + ) != ALTERA_ONCHIP_FLASH_STATUS_ERASE_PASSED + ) { + + alt_busy_sleep(1); /* delay 1us */ + + /* If timeout value is zero, it will never timeout. */ + if (timeout != 0) { + count_down--; + if (count_down == 0) { + /* Timeout */ + ret_code = -ETIMEDOUT; + break; + } + } + } + + return ret_code; +} + +/** + * alt_onchip_flash_poll_for_status_write_passed + * + * This function return non zero value when polling timeout. +**/ +int alt_onchip_flash_poll_for_status_write_passed +( + alt_onchip_flash_dev *flash +) +{ + int ret_code = 0; + int timeout = ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE; + int count_down = ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE; + + while ( + (IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & + ALTERA_ONCHIP_FLASH_STATUS_WRITE_MSK + ) != ALTERA_ONCHIP_FLASH_STATUS_WRITE_PASSED + ) { + + alt_busy_sleep(1); /* delay 1us */ + + /* If timeout value is zero, it will never timeout. */ + if (timeout != 0) { + count_down--; + if (count_down == 0) { + /* Timeout */ + ret_code = -ETIMEDOUT; + break; + } + } + } + + return ret_code; +} + diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/iniche/ins_tse_mac.c b/FPGA_nios/hit_pat_bsp/drivers/src/iniche/ins_tse_mac.c new file mode 100644 index 0000000..92070f0 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/drivers/src/iniche/ins_tse_mac.c @@ -0,0 +1,911 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2016 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#ifdef ALT_INICHE + +#include +#include +#include +#include +#include +#include +#include "ipport.h" + +#ifdef UCOS_II +#include +#endif + +#include "in_utils.h" +#include "netbuf.h" +#include "net.h" +#include "q.h" +#include "ether.h" +#include "system.h" +#include "alt_types.h" + +#include "altera_avalon_timer_regs.h" +#include "altera_msgdma_descriptor_regs.h" +#include "altera_avalon_tse.h" + +#include "sys/alt_irq.h" +#include "sys/alt_cache.h" + +#include "altera_eth_tse_regs.h" +#include "iniche/altera_eth_tse_iniche.h" +#include "iniche/ins_tse_mac.h" + +#include "socket.h" + +/* Task includes */ +#include "ipport.h" +#include "tcpapp.h" + +#ifndef ALT_INICHE +#include "osport.h" +#endif + +#ifdef ALT_INICHE +#include +#include "alt_iniche_dev.h" +#endif + +ins_tse_info tse[MAXNETS]; +extern alt_tse_system_info tse_mac_device[MAXNETS]; + +alt_u8 number_of_tse_mac = 0; +alt_tse_iniche_dev_driver_data tse_iniche_dev_driver_data[MAXNETS]; +extern alt_u8 max_mac_system; + +#ifdef ALT_INICHE + + +/* @Function Description: TSE MAC Driver Open/Initialization routine + * @API TYPE: Public + * @Param p_dec pointer to TSE device instance + * @Return ENP_HARDWARE on error, otherwise return SUCCESS + */ + +error_t altera_eth_tse_init( + alt_iniche_dev *p_dev) +{ + int i; + + alt_tse_iniche_dev_driver_data *p_driver_data = 0; + alt_tse_system_info *psys_info = 0; + + dprintf("altera_eth_tse_init %d\n", p_dev->if_num); + + /* Get the pointer to the alt_tse_iniche_dev_driver_data structure from the global array */ + for(i = 0; i < number_of_tse_mac; i++) { + if(tse_iniche_dev_driver_data[i].p_dev == p_dev) { + p_driver_data = &tse_iniche_dev_driver_data[i]; + } + } + /* If pointer could not found */ + if(p_driver_data == 0) { + return ENP_HARDWARE; + } + + /* Get the pointer to the alt_tse_system_info structure from the global array */ + for(i = 0; i < max_mac_system; i++) { + if(tse_mac_device[i].tse_mac_base == p_driver_data->hw_mac_base_addr) { + psys_info = &tse_mac_device[i]; + } + } + /* If pointer could not found */ + if(psys_info == 0) { + return ENP_HARDWARE; + } + + prep_tse_mac(p_dev->if_num, psys_info + p_driver_data->hw_channel_number); + + return SUCCESS; +} +#endif /* ALT_INICHE */ + + +/* @Function Description: TSE MAC Driver Open/Registration routine + * @API TYPE: Internal + * @Param index index of the NET structure associated with TSE instance + * @Param psys_info pointer to the TSE hardware info structure + * @Return next index of NET + */ +int prep_tse_mac(int index, alt_tse_system_info *psys_info) +{ + NET ifp; + dprintf("prep_tse_mac %d\n", index); + { + tse[index].sem = 0; /*Tx IDLE*/ + tse[index].tse = (void *)psys_info; + + ifp = nets[index]; + ifp->n_mib->ifAdminStatus = ALTERA_TSE_ADMIN_STATUS_DOWN; /* status = down */ + ifp->n_mib->ifOperStatus = ALTERA_TSE_ADMIN_STATUS_DOWN; + ifp->n_mib->ifLastChange = cticks * (100/TPS); + ifp->n_mib->ifPhysAddress = (u_char*)tse[index].mac_addr; + ifp->n_mib->ifDescr = "Altera TSE MAC ethernet"; + ifp->n_lnh = ETHHDR_SIZE; /* ethernet header size. was:14 */ + ifp->n_hal = ALTERA_TSE_HAL_ADDR_LEN; /* hardware address length */ + ifp->n_mib->ifType = ETHERNET; /* device type */ + ifp->n_mtu = ALTERA_TSE_MAX_MTU_SIZE; /* max frame size */ + + /* install our hardware driver routines */ + ifp->n_init = tse_mac_init; + ifp->pkt_send = NULL; + ifp->raw_send = tse_mac_raw_send; + ifp->n_close = tse_mac_close; + ifp->n_stats = (void(*)(void *, int))tse_mac_stats; + + #ifdef IP_V6 + ifp->n_flags |= (NF_NBPROT | NF_IPV6); + #else + ifp->n_flags |= NF_NBPROT; + #endif + + nets[index]->n_mib->ifPhysAddress = (u_char*)tse[index].mac_addr; /* ptr to MAC address */ + + #ifdef ALT_INICHE + /* get the MAC address. */ + get_mac_addr(ifp, (unsigned char *)tse[index].mac_addr); + #endif /* ALT_INICHE */ + + /* set cross-pointers between iface and tse structs */ + tse[index].index = index; + tse[index].netp = ifp; + ifp->n_local = (void*)(&tse[index]); + + index++; + } + + return index; +} + +//temporary code for msgdma hw workaround +void msgdma_reset(alt_msgdma_dev * dev) +{ + + /* start prefetcher reset sequence */ + IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, + ALT_MSGDMA_PREFETCHER_CTRL_RESET_SET_MASK); + /* wait until hw clears the bit */ + while(ALT_MSGDMA_PREFETCHER_CTRL_RESET_GET( + IORD_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base))); + /* + * This reset is intended to be used along with reset dispatcher in + * dispatcher core. Once the reset sequence in prefetcher core has + * completed, software is expected to reset the dispatcher core, + * and polls for dispatcher?s reset sequence to be completed. + */ + + /* Reset the registers and FIFOs of the dispatcher and master modules */ + /* set the reset bit, no need to read the control register first since + this write is going to clear it out */ + IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, ALTERA_MSGDMA_CSR_RESET_MASK); + while(0 != (IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base) + & ALTERA_MSGDMA_CSR_RESET_STATE_MASK)); + +} + +/* @Function Description: TSE MAC Initialization routine. This function opens the + * device handle, configure the callback function and interrupts , + * for MSGDMA TX and MSGDMA RX block associated with the TSE MAC, + * Initialize the MAC Registers for the RX FIFO and TX FIFO + * threshold watermarks, initialize the tse device structure, + * set the MAC address of the device and enable the MAC + * + * @API TYPE: Internal + * @Param iface index of the NET structure associated with TSE instance + * @Return 0 if ok, else -1 if error + */ +int tse_mac_init(int iface) +{ + int dat; + int speed, duplex, result, x; + int status = SUCCESS; + + alt_msgdma_dev *msgdma_tx_dev; + alt_msgdma_dev *msgdma_rx_dev; + alt_tse_system_info* tse_hw = (alt_tse_system_info *) tse[iface].tse; + + dprintf("tse_mac_init %d\n", iface); + + if (tse_hw->ext_desc_mem == 1) { + tse[iface].rxdesc[0] = (alt_msgdma_prefetcher_standard_descriptor *) tse_hw->desc_mem_base; + tse[iface].rxdesc[1] = (alt_msgdma_prefetcher_standard_descriptor *) + (tse_hw->desc_mem_base + ((1+ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE)*(sizeof(alt_msgdma_prefetcher_standard_descriptor)))); + tse[iface].txdesc = (alt_msgdma_prefetcher_standard_descriptor *) + (tse_hw->desc_mem_base + ((1+ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE+1+ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE)*(sizeof(alt_msgdma_prefetcher_standard_descriptor)))); + } + else { + tse[iface].rxdesc[0] = (alt_msgdma_prefetcher_standard_descriptor *)alt_uncached_malloc((1+ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE)*(sizeof(alt_msgdma_prefetcher_standard_descriptor))); + while ((((alt_u32)tse[iface].rxdesc[0]) % sizeof(alt_msgdma_prefetcher_standard_descriptor)) != 0) + tse[iface].rxdesc[0]++; //boundary + + tse[iface].rxdesc[1] = (alt_msgdma_prefetcher_standard_descriptor *)alt_uncached_malloc((1+ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE)*(sizeof(alt_msgdma_prefetcher_standard_descriptor))); + while ((((alt_u32)tse[iface].rxdesc[1]) % sizeof(alt_msgdma_prefetcher_standard_descriptor)) != 0) + tse[iface].rxdesc[1]++; //boundary + + tse[iface].txdesc = (alt_msgdma_prefetcher_standard_descriptor *)alt_uncached_malloc((1+ALTERA_TSE_MSGDMA_TX_DESC_CHAIN_SIZE)*(sizeof(alt_msgdma_prefetcher_standard_descriptor))); + while ((((alt_u32)tse[iface].txdesc) % sizeof(alt_msgdma_prefetcher_standard_descriptor)) != 0) + tse[iface].txdesc++; //boundary + } + + /* Get the Rx and Tx MSGDMA addresses */ + msgdma_tx_dev = alt_msgdma_open(tse_hw->tse_msgdma_tx); + + if(!msgdma_tx_dev) { + dprintf("[altera_eth_tse_init] Error opening TX MSGDMA\n"); + return ENP_RESOURCE; + } + + msgdma_rx_dev = alt_msgdma_open(tse_hw->tse_msgdma_rx); + if(!msgdma_rx_dev) { + dprintf("[altera_eth_tse_init] Error opening RX MSGDMA\n"); + return ENP_RESOURCE; + } + + /* Initialize mtip_mac_trans_info structure with values from */ + tse_mac_initTransInfo2(&tse[iface].mi, (int)tse_hw->tse_mac_base, + (unsigned int)msgdma_tx_dev, + (unsigned int)msgdma_rx_dev, + 0); + + /* reset the PHY if necessary */ + result = getPHYSpeed(tse[iface].mi.base); + speed = (result >> 1) & 0x07; + duplex = result & 0x01; + + /* reset the mac */ + IOWR_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base, + mmac_cc_SW_RESET_mask | + mmac_cc_TX_ENA_mask | + mmac_cc_RX_ENA_mask); + + x=0; + while(IORD_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base) & + ALTERA_TSEMAC_CMD_SW_RESET_MSK) { + if( x++ > 10000 ) { + break; + } + } + if(x >= 10000) { + dprintf("TSEMAC SW reset bit never cleared!\n"); + } + + dat = IORD_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base); + if( (dat & 0x03) != 0 ) { + dprintf("WARN: RX/TX not disabled after reset... missing PHY clock? CMD_CONFIG=0x%08x\n", dat); + } + else { + dprintf("OK, x=%d, CMD_CONFIG=0x%08x\n", x, dat); + } + + /* Hack code to determine the Channel number <- Someone please fix this ugly code in the future */ + extern alt_u8 mac_group_count; + extern alt_tse_mac_group *pmac_groups[TSE_MAX_MAC_IN_SYSTEM]; + + if(tse_hw->use_shared_fifo == 1) { + int channel_loop = 0; + int mac_loop = 0; + + for (channel_loop = 0; channel_loop < mac_group_count; channel_loop ++) { + for (mac_loop = 0; mac_loop < pmac_groups[channel_loop]->channel; mac_loop ++) { + if (pmac_groups[channel_loop]->pmac_info[mac_loop]->psys_info == tse_hw) { + tse[iface].channel = mac_loop; + } + } + } + } + /* End of Hack code */ + + if(tse_hw->use_shared_fifo == 1) { + IOWR_ALTERA_MULTI_CHAN_FIFO_SEC_FULL_THRESHOLD(tse_hw->tse_shared_fifo_rx_ctrl_base,tse_hw->tse_shared_fifo_rx_depth); + IOWR_ALTERA_MULTI_CHAN_FIFO_ALMOST_FULL_THRESHOLD(tse_hw->tse_shared_fifo_rx_ctrl_base,((tse_hw->tse_shared_fifo_rx_depth) - 140)); + } + else { + /* Initialize MAC registers */ + IOWR_ALTERA_TSEMAC_FRM_LENGTH(tse[iface].mi.base, ALTERA_TSE_MAC_MAX_FRAME_LENGTH); + IOWR_ALTERA_TSEMAC_RX_ALMOST_EMPTY(tse[iface].mi.base, 8); + IOWR_ALTERA_TSEMAC_RX_ALMOST_FULL(tse[iface].mi.base, 8); + IOWR_ALTERA_TSEMAC_TX_ALMOST_EMPTY(tse[iface].mi.base, 8); + IOWR_ALTERA_TSEMAC_TX_ALMOST_FULL(tse[iface].mi.base, 3); + IOWR_ALTERA_TSEMAC_TX_SECTION_EMPTY(tse[iface].mi.base, tse_hw->tse_tx_depth - 16); //1024/4; + IOWR_ALTERA_TSEMAC_TX_SECTION_FULL(tse[iface].mi.base, 0); //32/4; // start transmit when there are 48 bytes + IOWR_ALTERA_TSEMAC_RX_SECTION_EMPTY(tse[iface].mi.base, tse_hw->tse_rx_depth - 16); //4000/4); + IOWR_ALTERA_TSEMAC_RX_SECTION_FULL(tse[iface].mi.base, 0); + } + + /* Enable TX shift 16 for removing two bytes from the start of all transmitted frames */ + if((ETHHDR_BIAS !=0) && (ETHHDR_BIAS !=2)) { + dprintf("[tse_mac_init] Error: Unsupported Ethernet Header Bias Value, %d\n",ETHHDR_BIAS); + return ENP_PARAM; + } + + if(ETHHDR_BIAS == 0) { + alt_32 temp_reg; + + temp_reg = IORD_ALTERA_TSEMAC_TX_CMD_STAT(tse[iface].mi.base) & (~ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_MSK); + IOWR_ALTERA_TSEMAC_TX_CMD_STAT(tse[iface].mi.base,temp_reg); + + /* + * check if the MAC supports the 16-bit shift option allowing us + * to send BIASed frames without copying. Used by the send function later. + */ + if(IORD_ALTERA_TSEMAC_TX_CMD_STAT(tse[iface].mi.base) & + ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_MSK) { + tse[iface].txShift16OK = 1; + dprintf("[tse_mac_init] Error: Incompatible %d value with TX_CMD_STAT register return TxShift16 value. \n",ETHHDR_BIAS); + return ENP_LOGIC; + } else { + tse[iface].txShift16OK = 0; + } + + /*Enable RX shift 16 for alignment of all received frames on 16-bit start address */ + temp_reg = IORD_ALTERA_TSEMAC_RX_CMD_STAT(tse[iface].mi.base) & (~ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_MSK); + IOWR_ALTERA_TSEMAC_RX_CMD_STAT(tse[iface].mi.base,temp_reg); + + /* check if the MAC supports the 16-bit shift option at the RX CMD STATUS Register */ + if(IORD_ALTERA_TSEMAC_RX_CMD_STAT(tse[iface].mi.base) & ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_MSK) + { + tse[iface].rxShift16OK = 1; + dprintf("[tse_mac_init] Error: Incompatible %d value with RX_CMD_STAT register return RxShift16 value. \n",ETHHDR_BIAS); + return ENP_LOGIC; + } + else { + tse[iface].rxShift16OK = 0; + } + } /* if(ETHHDR_BIAS == 0) */ + + if(ETHHDR_BIAS == 2) { + IOWR_ALTERA_TSEMAC_TX_CMD_STAT(tse[iface].mi.base,ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_MSK); + + /* + * check if the MAC supports the 16-bit shift option allowing us + * to send BIASed frames without copying. Used by the send function later. + */ + if(IORD_ALTERA_TSEMAC_TX_CMD_STAT(tse[iface].mi.base) & + ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_MSK) { + tse[iface].txShift16OK = 1; + } + else { + tse[iface].txShift16OK = 0; + dprintf("[tse_mac_init] Error: Incompatible %d value with TX_CMD_STAT register return TxShift16 value. \n",ETHHDR_BIAS); + return ENP_LOGIC; + } + + /* Enable RX shift 16 for alignment of all received frames on 16-bit start address */ + IOWR_ALTERA_TSEMAC_RX_CMD_STAT(tse[iface].mi.base,ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_MSK); + + /* check if the MAC supports the 16-bit shift option at the RX CMD STATUS Register */ + if(IORD_ALTERA_TSEMAC_RX_CMD_STAT(tse[iface].mi.base) & ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_MSK) + { + tse[iface].rxShift16OK = 1; + } + else { + tse[iface].rxShift16OK = 0; + dprintf("[tse_mac_init] Error: Incompatible %d value with RX_CMD_STAT register return RxShift16 value. \n",ETHHDR_BIAS); + return ENP_LOGIC; + } + } /* if(ETHHDR_BIAS == 2) */ + + /* enable MAC */ + dat = ALTERA_TSEMAC_CMD_TX_ENA_MSK | + ALTERA_TSEMAC_CMD_RX_ENA_MSK | + mmac_cc_RX_ERR_DISCARD_mask | +#if ENABLE_PHY_LOOPBACK + ALTERA_TSEMAC_CMD_PROMIS_EN_MSK | // promiscuous mode + ALTERA_TSEMAC_CMD_LOOPBACK_MSK | // promiscuous mode +#endif + ALTERA_TSEMAC_CMD_TX_ADDR_INS_MSK | + ALTERA_TSEMAC_CMD_RX_ERR_DISC_MSK; /* automatically discard frames with CRC errors */ + + + /* 1000 Mbps */ + if(speed == 0x01) { + dat |= ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; + dat &= ~ALTERA_TSEMAC_CMD_ENA_10_MSK; + } + /* 100 Mbps */ + else if(speed == 0x02) { + dat &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; + dat &= ~ALTERA_TSEMAC_CMD_ENA_10_MSK; + } + /* 10 Mbps */ + else if(speed == 0x04) { + dat &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; + dat |= ALTERA_TSEMAC_CMD_ENA_10_MSK; + } + /* default to 100 Mbps if returned invalid speed */ + else { + dat &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; + dat &= ~ALTERA_TSEMAC_CMD_ENA_10_MSK; + } + + /* Half Duplex */ + if(duplex == TSE_PHY_DUPLEX_HALF) { + dat |= ALTERA_TSEMAC_CMD_HD_ENA_MSK; + } + /* Full Duplex */ + else { + dat &= ~ALTERA_TSEMAC_CMD_HD_ENA_MSK; + } + + IOWR_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base, dat); + dprintf("\nMAC post-initialization: CMD_CONFIG=0x%08x\n", + IORD_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base)); + + +#ifdef ALT_INICHE + /* Set the MAC address */ + IOWR_ALTERA_TSEMAC_MAC_0(tse[iface].mi.base, + ((int)((unsigned char) tse[iface].mac_addr[0]) | + (int)((unsigned char) tse[iface].mac_addr[1] << 8) | + (int)((unsigned char) tse[iface].mac_addr[2] << 16) | + (int)((unsigned char) tse[iface].mac_addr[3] << 24))); + + IOWR_ALTERA_TSEMAC_MAC_1(tse[iface].mi.base, + (((int)((unsigned char) tse[iface].mac_addr[4]) | + (int)((unsigned char) tse[iface].mac_addr[5] << 8)) & 0xFFFF)); + +#else /* not ALT_INICHE */ + + /* Set the MAC address */ + IOWR_ALTERA_TSEMAC_MAC_0(tse[iface].mi.base, + ((int)(0x00) | + (int)(0x07 << 8) | + (int)(0xAB << 16) | + (int)(0xF0 << 24))); + + IOWR_ALTERA_TSEMAC_MAC_1(tse[iface].mi.base, + (((int)(0x0D) | + (int)(0xBA << 8)) & 0xFFFF)); + + + /* Set the mac address in the tse struct */ + tse[iface].mac_addr[0] = 0x00; + tse[iface].mac_addr[1] = 0x07; + tse[iface].mac_addr[2] = 0xAB; + tse[iface].mac_addr[3] = 0xF0; + tse[iface].mac_addr[4] = 0x0D; + tse[iface].mac_addr[5] = 0xBA; + +#endif /* not ALT_INICHE */ + + /* status = UP */ + nets[iface]->n_mib->ifAdminStatus = ALTERA_TSE_ADMIN_STATUS_UP; + nets[iface]->n_mib->ifOperStatus = ALTERA_TSE_ADMIN_STATUS_UP; + + /* Install MSGDMA (RX) interrupt handler */ + alt_msgdma_register_callback( + tse[iface].mi.rx_msgdma, + (alt_msgdma_callback)&tse_msgdmaRx_isr, + 0, + (void*)(&tse[iface])); + + /* Install MSGDMA (TX) interrupt handler */ + alt_msgdma_register_callback( + tse[iface].mi.tx_msgdma, + (alt_msgdma_callback)&tse_msgdmaTx_isr, + 0, + (void*)(&tse[iface])); + + status = tse_msgdma_read_init(&tse[iface]); + if (status == 0 ) status = tse_msgdma_write_init(&tse[iface],0,0); + + if (status!=0) dprintf("TSE_MAC_INIT error\n"); + + return status; +} + +/* @Function Description - Init and setup MSGDMA TX Descriptor chain + * + * + * @API TYPE - Internal + * @return SUCCESS on success + */ +int tse_msgdma_write_init(ins_tse_info* tse_ptr,unsigned int * ActualData,unsigned int len) +{ + alt_u32 control = 0; + int desc_index; + int rc; + + tse_ptr->txdesc_list = NULL; + + for(desc_index = 0; desc_index < (ALTERA_TSE_MSGDMA_TX_DESC_CHAIN_SIZE); desc_index++) + { + + /* trigger interrupt when transfer complete */ + control = ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GENERATE_SOP_MASK | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MASK; + + if (desc_index >= ( ALTERA_TSE_MSGDMA_TX_DESC_CHAIN_SIZE - 2)) control |= ALTERA_MSGDMA_DESCRIPTOR_CONTROL_TRANSFER_COMPLETE_IRQ_MASK; + else control |= ALTERA_MSGDMA_DESCRIPTOR_CONTROL_EARLY_DONE_ENABLE_MASK; + + rc=alt_msgdma_construct_prefetcher_standard_mm_to_st_descriptor( + tse_ptr->mi.tx_msgdma, + (alt_msgdma_prefetcher_standard_descriptor *) &tse_ptr->txdesc[desc_index], + (int)ActualData, + len, + control); + if (rc!=0) return -1; + + if (desc_index==0) tse_ptr->txdesc_list = NULL; + + rc=alt_msgdma_prefetcher_add_standard_desc_to_list( + &tse_ptr->txdesc_list, + &tse_ptr->txdesc[desc_index] ); + if (rc!=0) return -1; + + } + + return 0; +} + +/* @Function Description - TSE transmit API to send data to the MAC + * + * + * @API TYPE - Public + * @param net - NET structure associated with the TSE MAC instance + * @param data - pointer to the data payload + * @param data_bytes - number of bytes of the data payload to be sent to the MAC + * @return SUCCESS if success, else a negative value + */ +int tse_mac_raw_send(NET net, char * data, unsigned int data_bytes) +{ + unsigned int len = data_bytes; + int rc; + + ins_tse_info* tse_ptr = (ins_tse_info*) net->n_local; + tse_mac_trans_info *mi; + unsigned int* ActualData; + int cpu_sr; + + OS_ENTER_CRITICAL(); + mi = &tse_ptr->mi; + + if(tse_ptr->sem!=0) /* Tx is busy*/ + { + dprintf("raw_send CALLED AGAIN!!!\n"); + OS_EXIT_CRITICAL(); + return ENP_RESOURCE; + } + + tse_ptr->sem = 1; + + // clear bit-31 before passing it to MSGDMA Driver + ActualData = (unsigned int*)alt_remap_cached ((volatile void*) data, 4); + + #if (0) + rc= tse_msgdma_write_init(tse_ptr,ActualData,len); + if (rc<0) + { + dprintf("tse_msgdma_write_init bad return\n"); + OS_EXIT_CRITICAL(); + return -1; + } + #else + tse_ptr->txdesc[0].read_address = (alt_u32)ActualData; + tse_ptr->txdesc[0].transfer_length = len; + tse_ptr->txdesc[0].control = (tse_ptr->txdesc[0].control + & ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_CLR_MASK) + | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK; + #endif + + alt_dcache_flush(ActualData,len); + rc = tse_mac_aTxWrite(mi,tse_ptr->txdesc); + if(rc < 0) /* MSGDMA not available */ + { + dprintf("raw_send() MSGDMA not available, ret=%d, len=%d\n",rc, len); + net->n_mib->ifOutDiscards++; + tse_ptr->sem = 0; + + OS_EXIT_CRITICAL(); + return SEND_DROPPED; /* ENP_RESOURCE and SEND_DROPPED have the same value! */ + } + else /* = 0, success */ + { + net->n_mib->ifOutOctets += data_bytes; + /* we dont know whether it was unicast or not, we count both in */ + net->n_mib->ifOutUcastPkts++; + tse_ptr->sem = 0; + + OS_EXIT_CRITICAL(); + return SUCCESS; /*success */ + } +} + + + +/* @Function Description - TSE Driver MSGDMA RX ISR callback function + * + * + * @API TYPE - callback + * @param context - context of the TSE MAC instance + * @param intnum - temporary storage + */ +void tse_msgdmaRx_isr(void * context) +{ + ins_tse_info* tse_ptr = (ins_tse_info *) context; + alt_u32 msgdma_status; + alt_u32 i,control; + + /* Capture current rcv queue length */ + int initial_rcvdq_len = rcvdq.q_len; + + /* reenable global interrupts so we don't miss one that occurs during the + processing of this ISR */ + IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(tse_ptr->mi.rx_msgdma->prefetcher_base, + IORD_ALT_MSGDMA_PREFETCHER_CONTROL(tse_ptr->mi.rx_msgdma->prefetcher_base) + | ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_SET_MASK); + + msgdma_status = IORD_ALTERA_MSGDMA_CSR_STATUS(tse_ptr->mi.rx_msgdma->csr_base); + + if ((msgdma_status & ALTERA_MSGDMA_CSR_STOPPED_ON_ERROR_MASK)==0) + { + /* Handle received packet */ + tse_mac_rcv(tse_ptr); + + /* read the control field of the last descriptor in the chain */ + control = IORD_32DIRECT(&tse_ptr->rxdesc[tse_ptr->rx_chain][ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE-2],0x1c); + + //if the chain is completed then start a new chain + if ((control & ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET_MASK)==0) + { + /* process any unprocessed descriptors */ + for (i=(tse_ptr->rx_descriptor_index);i<(ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE-1);i++) + { + tse_mac_rcv(tse_ptr); + } + + /* cancel any pending ints */ + /* the chain could have been completed and int generated during the processing of this ISR */ + /* But we are handling that in this ISR, so cancel any pending interrupt */ + IOWR_ALT_MSGDMA_PREFETCHER_STATUS(tse_ptr->mi.rx_msgdma->prefetcher_base,1); + + /* switch chains */ + tse_ptr->rx_descriptor_index = 0; + if (tse->rx_chain == 0) tse->rx_chain=1; else tse->rx_chain=0; + + /* start new chain */ + tse_mac_aRxRead(&tse_ptr->mi, tse_ptr->rxdesc_list[tse->rx_chain]); + + /* allocate storage for the non active chain */ + allocate_rx_descriptor_chain(tse_ptr); + } + + /* Wake up Niche stack if there are new packets are on queue */ + if ((rcvdq.q_len) > initial_rcvdq_len) { + SignalPktDemux(); + } + } /* if (no error) */ + else { dprintf("RX ERROR\n"); } + +} + +/* @Function Description - TSE Driver MSGDMA TX ISR callback function + * + * + * @API TYPE - callback + * @param context - context of the TSE MAC instance + */ +void tse_msgdmaTx_isr(void * context) +{ + ins_tse_info* tse_ptr = (ins_tse_info *) context; + int msgdma_status; + + /* + * The MSGDMA interrupt source was cleared in the MSGDMA ISR entry, + * which called this routine. New interrupt sources will cause the + * IRQ to fire again once this routine returns. + */ + + /* + * Grab MSGDMA status to validate interrupt cause. + * + * IO read to peripheral that generated the IRQ is done after IO write + * to negate the interrupt request. This ensures at the IO write reaches + * the peripheral (through any high-latency hardware in the system) + * before the ISR exits. + */ + msgdma_status = IORD_ALTERA_MSGDMA_CSR_STATUS(tse_ptr->mi.tx_msgdma->csr_base); + + if ((msgdma_status & ALTERA_MSGDMA_CSR_STOPPED_ON_ERROR_MASK)!=0) + dprintf("TX STOPPED\n"); + +} + + +/* @Function Description - Init and setup MSGDMA Descriptor chain + * + * + * @API TYPE - Internal + * @return SUCCESS on success + */ +int tse_msgdma_read_init(ins_tse_info* tse_ptr) +{ + alt_u32 *uncached_packet_payload; + alt_u32 control = 0; + int desc_index; + int chain_index; + int rc; + int max_transfer_size=0xffff; + + if (tse_ptr->mi.rx_msgdma->max_byte < max_transfer_size) { max_transfer_size = tse_ptr->mi.rx_msgdma->max_byte; } + + for (chain_index=0;chain_index<2;chain_index++) + { + tse_ptr->rxdesc_list[chain_index] = NULL; + + for(desc_index = 0; desc_index < ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE; desc_index++) + { + uncached_packet_payload = NULL; + + if ((desc_index < (ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE-1))) { + tse_ptr->pkt_array_rx[chain_index][desc_index] = pk_alloc(ALTERA_TSE_PKT_INIT_LEN); + + if (!tse_ptr->pkt_array_rx[chain_index][desc_index]) /* couldn't get a free buffer for rx */ + { + dprintf("[tse_msgdma_read_init] Fatal error: No free packet buffers for RX\n"); + tse_ptr->netp->n_mib->ifInDiscards++; + + return ENP_NOBUFFER; + } + + // ensure bit-31 of tse_ptr->pkt_array_rx[desc_index]->nb_buff is clear before passing + // to MSGDMA Driver + uncached_packet_payload = (alt_u32 *)alt_remap_cached ((volatile void*) tse_ptr->pkt_array_rx[chain_index][desc_index]->nb_buff, 4); + alt_dcache_flush((void *) uncached_packet_payload, ALTERA_TSE_PKT_INIT_LEN); + } + + /* trigger interrupt when transfer complete */ + control = ALTERA_MSGDMA_DESCRIPTOR_CONTROL_TRANSFER_COMPLETE_IRQ_MASK | + ALTERA_MSGDMA_DESCRIPTOR_CONTROL_ERROR_IRQ_MASK | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_END_ON_EOP_MASK; + + rc=alt_msgdma_construct_prefetcher_standard_st_to_mm_descriptor( + tse_ptr->mi.rx_msgdma, + (alt_msgdma_prefetcher_standard_descriptor *) &tse_ptr->rxdesc[chain_index][desc_index], + (alt_u32)uncached_packet_payload, + max_transfer_size, + control); + if (rc!=0) return -1; + + if (desc_index==0) tse_ptr->rxdesc_list[chain_index] = NULL; + + rc=alt_msgdma_prefetcher_add_standard_desc_to_list( + &tse_ptr->rxdesc_list[chain_index], + &tse_ptr->rxdesc[chain_index][desc_index] ); + if (rc!=0) return -1; + } + + } + + dprintf("[tse_msgdma_read_init] RX descriptor chain desc (%d depth) created\n", desc_index); + + tse_ptr->rx_descriptor_index=0; //for processing completed rx descriptors + tse_ptr->rx_chain=0; + tse_mac_aRxRead( &tse_ptr->mi, tse_ptr->rxdesc_list[tse_ptr->rx_chain]); + + return SUCCESS; +} + +/* allocate the storage for the non active rx descriptor chain + update the write pointers in each descriptor to point + to the allocated storage. */ +int allocate_rx_descriptor_chain(ins_tse_info* tse_ptr) +{ + PACKET replacement_pkt; + alt_u32 *uncached_packet_payload; + alt_msgdma_prefetcher_standard_descriptor *rxDesc; + int i; + + for (i=0;i<(ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE-1);i++) + { + replacement_pkt = pk_alloc(ALTERA_TSE_PKT_INIT_LEN); + if (!replacement_pkt) { /* couldn't get a free buffer for rx */ + dprintf("No free buffers for rx\n"); + return 1; + } + else + { + rxDesc = &tse_ptr->rxdesc[!tse_ptr->rx_chain][i]; + tse_ptr->pkt_array_rx[!tse_ptr->rx_chain][i] = replacement_pkt; + uncached_packet_payload = (alt_u32 *)alt_remap_cached(tse_ptr->pkt_array_rx[!tse_ptr->rx_chain][i]->nb_buff, 4); + alt_dcache_flush((void *) uncached_packet_payload, ALTERA_TSE_PKT_INIT_LEN); + rxDesc->write_address = (alt_u32)(uncached_packet_payload); + } + } + + return 0; +} + +/* @Function Description - TSE Driver MSGDMA RX ISR callback function + * + * + * @API TYPE - callback internal function + * @return SUCCESS on success + */ + +void tse_mac_rcv(ins_tse_info* tse_ptr) +{ + struct ethhdr * eth; + int pklen; + PACKET rx_packet; + + /* Correct frame length to actual (this is different from TX side) */ + pklen = IORD_32DIRECT(&tse_ptr->rxdesc[tse_ptr->rx_chain][tse_ptr->rx_descriptor_index].bytes_transfered,0) - 2; + + tse_ptr->netp->n_mib->ifInOctets += (u_long)pklen; + + rx_packet = tse_ptr->pkt_array_rx[tse_ptr->rx_chain][tse_ptr->rx_descriptor_index]; + rx_packet->nb_prot = rx_packet->nb_buff + ETHHDR_SIZE; + rx_packet->nb_plen = pklen - 14; + rx_packet->nb_tstamp = cticks; + rx_packet->net = tse_ptr->netp; + + // set packet type for demux routine + eth = (struct ethhdr *)(rx_packet->nb_buff + ETHHDR_BIAS); + rx_packet->type = eth->e_type; + + putq(&rcvdq, rx_packet); + + tse_ptr->rx_descriptor_index++; +} + +int tse_mac_stats(void * pio, int iface) +{ + ns_printf(pio, "tse_mac_stats(), stats will be added later!\n"); + return SUCCESS; +} + +/* @Function Description - Closing the TSE MAC Driver Interface + * + * + * @API TYPE - Public + * @param iface index of the NET interface associated with the TSE MAC. + * @return SUCCESS + */ +int tse_mac_close(int iface) +{ + int state; + + /* status = down */ + nets[iface]->n_mib->ifAdminStatus = ALTERA_TSE_ADMIN_STATUS_DOWN; + + /* disable the interrupt in the OS*/ + alt_msgdma_register_callback(tse[iface].mi.rx_msgdma, 0, 0, 0); + + /* Disable Receive path on the device*/ + state = IORD_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base); + IOWR_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base,state & ~ALTERA_TSEMAC_CMD_RX_ENA_MSK); + + /* status = down */ + nets[iface]->n_mib->ifOperStatus = ALTERA_TSE_ADMIN_STATUS_DOWN; + + return SUCCESS; +} +#endif /* ALT_INICHE */ diff --git a/FPGA_nios/hit_pat_bsp/iniche/inc/alt_iniche_dev.h b/FPGA_nios/hit_pat_bsp/iniche/inc/alt_iniche_dev.h new file mode 100644 index 0000000..07ac364 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/inc/alt_iniche_dev.h @@ -0,0 +1,215 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +* * +* Source for the Altera InterNiche device services. * +* * +* Author EPS * +* * +******************************************************************************/ + +#ifndef __ALT_INICHE_DEV_H__ +#define __ALT_INICHE_DEV_H__ + +/******************************************************************************* + ******************************************************************************* + * + * InterNiche device services. + * + ******************************************************************************* + ******************************************************************************/ + +/******************************************************************************* + * + * Imported services. + * + ******************************************************************************/ + +#include + +#include "ipport.h" +#include "tcpport.h" +#include "sys/alt_llist.h" + + +/******************************************************************************* + * + * Structure typedefs. + * + ******************************************************************************/ + +typedef struct alt_iniche_dev_struct alt_iniche_dev; + + +/******************************************************************************* + * + * Typedefs. + * + ******************************************************************************/ + +/* + * alt_iniche_dev_init_func + * + * --> p_dev Device to initialize. + * + * Functions of this type initialize the device specified by p_dev. + */ + +typedef error_t (*alt_iniche_dev_init_func)( + alt_iniche_dev *p_dev); + + +/******************************************************************************* + * + * Structure defs. + * + ******************************************************************************/ + +/* + * InterNiche network interface device structure + * + * llist Linked list data record. + * name Name of device. + * init_func Device initialization function. + * p_driver_data Driver data. + * if_num Device interface number. + * p_net InterNiche network interface data record. + * + * This structure contains fields used for InterNiche network interface + * device drivers. + * All device data records are maintained in a list using the field llist. + * The name of the device is maintained in name. + * The function used to initialize the device is specified by init_func. + * The device driver may maintain a pointer to its own data in p_driver_data. + * Each device has an associated interface number maintained in if_num. + * The InterNiche network interface data record is maintained in p_net. + */ + +struct alt_iniche_dev_struct +{ + alt_llist llist; + char *name; + alt_iniche_dev_init_func init_func; + void *p_driver_data; + int if_num; + NET p_net; +}; + + +/******************************************************************************* + * + * Macros. + * + ******************************************************************************/ + +/* + * alt_iniche_dev_reg + * + * --> p_dev Device to register. + * + * This macro registers the InterNiche device specified by p_dev with the + * InterNiche device services. + */ + +extern alt_llist alt_iniche_dev_list; + +#define alt_iniche_dev_reg(p_dev) \ + alt_llist_insert(&alt_iniche_dev_list, &((p_dev)->llist)) + + +/******************************************************************************* + * + * InterNiche device services prototypes. + * + ******************************************************************************/ + +int iniche_devices_init( + int ifacesFound); + + +/******************************************************************************* + ******************************************************************************* + * + * External InterNiche device services. + * + ******************************************************************************* + ******************************************************************************/ + +/******************************************************************************* + * + * External InterNiche device services prototypes. + * + * These functions are provided by the external system to the InterNiche + * device services. + * + ******************************************************************************/ + +/* + * get_mac_addr + * + * --> net Network interface for which to get MAC address. + * <-- mac_addr MAC address. + * + * This function returns in mac_addr a MAC address to be used with the network + * interface specified by net. + */ + +int get_mac_addr( + NET net, + unsigned char mac_addr[6]); + + +/* + * get_ip_addr + * + * --> p_dev Device for which to get IP address. + * <-- p_addr IP address for device. + * <-- p_netmask IP netmask for device. + * <-- p_gw_addr IP gateway address for device. + * <-- p_use_dhcp TRUE if DHCP should be used to obtain an IP + * address. + * + * This function provides IP address information for the InterNiche network + * interface device specified by p_dev. If a static IP address is to be used, + * the IP address, netmask, and default gateway address are returned in p_addr, + * p_netmask, and p_gw_addr, and FALSE is returned in p_use_dhcp. If the DHCP + * protocol is to be used to obtain an IP address, TRUE is returned in + * p_use_dhcp. + */ + +int get_ip_addr( + alt_iniche_dev *p_dev, + ip_addr *p_addr, + ip_addr *p_netmask, + ip_addr *p_gw_addr, + int *p_use_dhcp); + + +#endif /* __ALT_INICHE_DEV_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/iniche/inc/os/alt_syscall.h b/FPGA_nios/hit_pat_bsp/iniche/inc/os/alt_syscall.h new file mode 100644 index 0000000..6189afb --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/inc/os/alt_syscall.h @@ -0,0 +1,77 @@ +#ifndef __ALT_SYSCALL_H__ +#define __ALT_SYSCALL_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * The macros defined in this file are used to provide the function names used + * for the HAL 'UNIX style' interface, e.g. read(), write() etc. + * + * Operating systems which are ported to the HAL can provide their own + * version of this file, which will be used in preference. This allows + * the operating system to provide it's own implementation of the top level + * system calls, while retaining the HAL functions under a different name, + * for example, alt_read(), alt_write() etc. + */ + +#define ALT_NICHESTACK_ALT_SYSCALL_H + +#define ALT_CLOSE alt_close +#define ALT_ENVIRON environ +#define ALT_EXECVE execve +#define ALT_EXIT _exit +#define ALT_FCNTL alt_fcntl +#define ALT_FORK fork +#define ALT_FSTAT fstat +#define ALT_GETPID getpid +#define ALT_GETTIMEOFDAY gettimeofday +#define ALT_IOCTL ioctl +#define ALT_ISATTY isatty +#define ALT_KILL kill +#define ALT_LINK link +#define ALT_LSEEK lseek +#define ALT_OPEN open +#define ALT_READ alt_read +#define ALT_RENAME _rename +#define ALT_SBRK sbrk +#define ALT_SETTIMEOFDAY settimeofday +#define ALT_STAT stat +#define ALT_UNLINK unlink +#define ALT_USLEEP usleep +#define ALT_WAIT wait +#define ALT_WRITE alt_write +#define ALT_TIMES times + +/* + * + */ + +#endif /* __ALT_ALIAS_H__ */ diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/allports/allports.c b/FPGA_nios/hit_pat_bsp/iniche/src/allports/allports.c new file mode 100644 index 0000000..2f5aeb9 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/allports/allports.c @@ -0,0 +1,947 @@ +/* + * FILENAME: allports.c + * + * Copyright 1998-2008 By InterNiche Technologies Inc. All rights reserved + * + * Routines common to most targets. + * + * MODULE: MISCLIB + * + * ROUTINES: netmain_init(), icmp_port_du(), station_state(), + * ROUTINES: ftpc_callback(), sysuptime(), packet_check(), + * ROUTINES: mcastlist(), prep_modules(), + * + * The functions in this file are generic functions + * and hence used for all builds. In addition to the above functions, + * globals "name" and "prompt" are also initialized in this file. + * + * This file was previously .\misclib\cmnport.c + * + * PORTABLE: yes + * They are portable for all targets that InterNiche supports. In future + * if there is need for any of them to be made target-specific, then + * #ifndef wrappers can be provided over here. + */ + +#include "ipport.h" + +#ifdef DHCP_SERVER +#include "dhcpport.h" +#endif /* DHCP_SERVER */ + +#include "libport.h" +#include "q.h" +#include "netbuf.h" +#include "net.h" +#include "ether.h" +#include "arp.h" +#include "ip.h" +#include "icmp.h" +#include "udp.h" +#ifdef IP_V6 +#include "ip6.h" +#endif + +#ifdef INCLUDE_NVPARMS /* system uses InterNiche NV system */ +#include "nvparms.h" +#endif + +#ifdef USE_PPP +#include "ppp_port.h" +#endif /* USE_PPP */ + +#ifdef USE_MODEM +#include "mdmport.h" +#else +#ifdef USE_PPP +#include "../mppp/mppp.h" /* for pppcfg */ +#endif +#endif /* USE_MODEM */ + +#ifdef PING_APP +#include "app_ping.h" +#endif +#ifndef TIMEFOR1TICK +#define TIMEFOR1TICK (1000/TPS) +#endif + +#if defined (IP_MULTICAST) && (defined (IGMP_V1) || defined (IGMP_V2)) +#include "../ipmc/igmp_cmn.h" +#endif /* IP multicast and (IGMPv1 or IGMPv2) */ + +#include "menu.h" +#ifdef INCLUDE_INICHE_LOG +#include "iniche_log.h" +#endif +#ifdef OSPORT_H +#include OSPORT_H +#endif + +/* various network entry points */ +extern char* ip_startup(void); +extern void inet_timer(void); + +#ifdef WEBPORT +extern int http_init(void); /* start up the web server */ +extern int prep_http(void); +#endif + +#ifdef TK_STDIN_DEVICE +extern void kbdio(void); +#endif + +#if defined(TFTP_CLIENT) || defined(TFTP_SERVER) +extern int tftp_init(void); +#endif + +#ifdef TELNET_SVR +extern int tel_init(void); +extern void tel_cleanup(void); +extern int prep_telnet(void); +#endif + +#ifdef DHCP_CLIENT +extern void dhc_setup(void); +#endif + +#ifdef DHCP_SERVER +extern int dhcp_init(void); +extern int prep_dhcpsrv(void); +extern void dhcpsrv_cleanup(void); +#endif + +#ifdef DNS_CLIENT +#include "dns.h" +#endif + +#ifdef TCP_ECHOTEST +extern int tcp_echo_init(void); +extern void tcp_echo_cleanup(void); +extern void tcp_echo_recv(void); +#endif + +#ifdef TCP_CIPHERTEST +extern int tcp_cipher_init(void); +extern void tcp_cipher_cleanup(void); +extern void tcp_cipher_recv(void); +#endif + +#ifdef FTP_CLIENT +extern int fc_check(void); +extern void (*fc_callback)(void *fc,int logstate, int cmdstate); +extern void ftpc_callback(void *fc,int logstate, int cmdstate); +extern int prep_ftpc(void); +#endif + +#ifdef VFS_FILES +extern int prep_vfs(void); +#endif + +#ifdef SMTP_ALERTS +extern int smtp_init(void); +extern int prep_smtp(void); +#endif + +#ifdef NATRT +extern int prep_natrt(void); +#endif + +#ifdef IP_MULTICAST +/* Add multicast test program call and a dummy definition of mcastlist */ +extern void u_mctest_init(void); +extern int mcastlist(struct in_multi *); +#endif /* IP_MULTICAST */ + +#ifdef TESTMENU /* after menus.h */ +extern struct menu_op testmenu[10]; +#endif /* TESTMENU */ + +#ifdef CSUM_DEMO +extern int cksum_init(void); +extern void csum_init(void); +#endif + +#ifdef DNS_SERVER +extern int dns_srvr_check(void); +extern int dns_srvr_init(int ); +extern void dns_srvr_timer(void); +#endif /* DNS_SERVER */ + +#ifdef UDPSTEST +extern int udp_echo_init(void); +extern void udp_echo_cleanup(void); +#endif /* UDPSTEST */ + +#ifdef RIP_SUPPORT +extern int rip_init(void); +extern void rip_cleanup(void); +extern int prep_rip(void); +#endif /* RIP_SUPPORT */ + +#ifdef INCLUDE_SNMP +extern int snmp_init(void); +extern void snmp_cleanup(void); +extern int prep_snmp(void); +#endif /* INCLUDE_SNMP */ + +#ifdef RAWIPTEST +extern int raw_test_init(void); +#endif /* RAWIPTEST */ + +#ifdef SUPERLOOP +#define task_stats(x) ; +#else +void task_stats(void * pio); +#endif + +#ifdef FULL_ICMP +void icmp_port_du(PACKET p, struct destun * pdp); +#endif + +#ifdef FTP_SERVER +extern int ftps_init(void); +extern void ftps_cleanup(void); +#endif + +#if defined(MEMDEV_SIZE) && defined(VFS_FILES) +extern int init_memdev(void); +#endif + +#ifdef USE_AUTOIP +extern int Upnp_init(void); +#endif /* USE_AUTOIP */ + +#ifdef INICHE_SYSLOG +extern int syslog_init(void); +extern void closelog(void); +extern int prep_syslog(void); +#endif /* INICHE_SYSLOG */ + +#ifdef INCLUDE_SSLAPP +extern int sslapp_init(void); +#endif /* INCLUDE_SSLAPP */ +#ifdef SUPERLOOP +int iniche_net_ready = FALSE; +#endif + +#ifdef USE_SNTP_V4 +int sntpv4_init (void); +int sntpv4_app (void); +#endif + +/* The following global variables are used in most ports. They are used by code + * covered under a variety of ipport.h feature ifdefs. Experience has show that + * it's not practical to do a complete ifdef to omit these when they are not + * in use. It would require a huge multiple OR case, and many preprocessors + * don't handle ifdef logic that complex. + */ + +char * name = "InterNiche Portable TCP/IP, v3.1 \n"; +char * prompt = "INET> "; /* prompt for console */ +ip_addr activehost = 0L; /* common host parameter */ +u_long pingdelay = TPS; /* common delay parameter (1 second) */ +int deflength = 64; /* common length parameter */ + +/* PING_APP-related variables */ +#ifdef PING_APP +extern ip_addr ping4_activehost; /* default ping host */ +extern u_long ping4_delay; /* 1 second between pings */ +extern u_long ping4_deflength; /* default ping packet data length */ +#endif /* PING_APP */ + +#ifdef DNS_CLIENT_UPDT +extern u_long dns_update_server; +#endif /* DNS_CLIENT_UPDT */ + + +#ifdef USE_COMPORT +#include "comline.h" /* include if not yet included */ +/* Struct contaning all configuration global params for Comport */ +struct ComPortCfg comportcfg; +#endif /* USE_COMPORT */ + +/* static net structs, so we can patch in default IP address. */ +extern struct net netstatic[STATIC_NETS]; + + +/* FUNCTION: netmain_init() + * + * Initialize all the modules that are being compiled in. + * This function is generic and is required for all builds + * + * Tasks do their own initialization. Hence for modules which have + * their own tasks, we don't do the initialization in netmain_init(). + * That is done by putting then under "#ifdef SUPERLOOP" + * + * PARAM1: + * + * RETURNS: + */ + +void +netmain_init(void) +{ + int e = 0; + char * msg; +#ifdef IP_V6 + ip6_addr host; +#endif + + printf("%s\n", name); + printf("Copyright 1996-2008 by InterNiche Technologies. All rights reserved. \n"); +#ifdef IN_MENUS + install_version("allports3.1"); +#endif +#ifndef SUPERLOOP + /* call this to do pre-task setup including intialization of port_prep */ + msg = pre_task_setup(); + if (msg) + panic(msg); +#endif + +#ifdef INCLUDE_NVPARMS /* system uses InterNiche NV system */ + e = get_nv_params(); /* get flash parameters into data structs */ + if (e) + { + printf("fatal error (%d) reading NV parameters.\n", e); + panic("nv"); + } + + /* set static iface IP info up from stored parameters. These may + be overwritten from command line parms or DHCP later. */ + { + int i; + + for (i = 0; i < STATIC_NETS; i++) + { + netstatic[i].n_ipaddr = inet_nvparms.ifs[i].ipaddr; + netstatic[i].snmask = inet_nvparms.ifs[i].subnet; + netstatic[i].n_defgw = inet_nvparms.ifs[i].gateway; +#ifdef IP_MULTICAST + /* Create a dummy entry for the Ethernet interface mcastlist */ + /* If this entry is set to NULL, multicast is not supported */ + /* on this interface */ + netstatic[i].n_mcastlist = mcastlist; +#if defined (IGMP_V1) || defined (IGMP_V2) + if ((inet_nvparms.ifs[i].igmp_oper_mode != IGMP_MODE_V1) && + (inet_nvparms.ifs[i].igmp_oper_mode != IGMP_MODE_V2)) + netstatic[i].igmp_oper_mode = IGMP_MODE_DEFAULT; + else + netstatic[i].igmp_oper_mode = inet_nvparms.ifs[i].igmp_oper_mode; +#endif /* IGMPv1 or IGMPv2 */ +#endif /* IP_MULTICAST */ + } + } + +#ifdef DNS_CLIENT + /* set DNS client's server list from nvparms information */ + MEMCPY(dns_servers, inet_nvparms.dns_servers, sizeof(dns_servers)); + +#ifdef DNS_CLIENT_UPDT + MEMCPY(soa_mname, inet_nvparms.dns_zone_name, sizeof(soa_mname)); + MEMCPY(&dns_update_server, &inet_nvparms.dns_update_server, sizeof(dns_update_server)); +#endif /* DNS_CLIENT_UPDT */ + +#endif /* DNS_CLIENT */ + +#ifdef USE_COMPORT + comportcfg.comport = comport_nvparms.comport; + comportcfg.LineProtocol = comport_nvparms.LineProtocol; +#endif /* USE_COMPORT */ +#endif /* INCLUDE_NVPARMS */ + +#ifndef INCLUDE_NVPARMS +#ifdef USE_COMPORT + comportcfg.comport = 0x01; + comportcfg.LineProtocol = PPP; /* Default to PPP */ +#endif /* USE_COMPORT */ +#endif /* INCLUDE_NVPARMS */ + +#ifdef IP_V6 + ip6_init(); +#endif + +#ifdef INCLUDE_INICHE_LOG + if(global_log_create()) + { + printf("global_log_create() failed\n"); + } + glog_with_type(LOG_TYPE_INFO, "INICHE LOG initialized", 1); +#endif + + msg = ip_startup(); + if (msg) + { + printf("inet startup error: %s\n", msg); + panic("IP"); + } + +#if defined(MEMDEV_SIZE) && defined(VFS_FILES) + init_memdev(); /* init the mem and null test devices */ +#endif + +#ifdef IP_MULTICAST +#ifdef INCLUDE_TCP + /* call the IP multicast test program */ + u_mctest_init(); +#endif +#endif + + /* clear debugging flags. Port can optionally turn them + * back on in post_task_setup(); + * NDEBUG = UPCTRACE | IPTRACE | TPTRACE ; + */ + NDEBUG = 0; + + /* print IP address of the first interface - for user's benefit */ + printf("IP address of %s : %s\n" , ((NET)(netlist.q_head))->name, + print_ipad(((NET)(netlist.q_head))->n_ipaddr)); + +#ifndef SUPERLOOP + /* call this per-target routine after basic tasks & net are up */ + msg = post_task_setup(); + if (msg) + panic(msg); +#endif + +#ifdef PING_APP + ping_init(); +#endif /* PING_APP */ + +#ifdef RAWIPTEST + raw_test_init(); +#endif /* RAWIPTEST */ + +#if defined(TFTP_CLIENT) || defined(TFTP_SERVER) + tftp_init(); +#endif /* TFTP */ + +#ifdef TESTMENU + install_menu(testmenu); +#endif /* TESTMENU */ +#ifdef CSUM_DEMO + cksum_init(); +#endif + +#ifdef USE_AUTOIP + Upnp_init(); /* start Auto IP before DHCP client */ +#endif /* USE_AUTOIP */ + +#ifdef DHCP_CLIENT + dhc_setup(); /* kick off any DHCP clients */ +#endif /* DHCP_CLIENT */ + +#ifdef DHCP_SERVER +#ifdef INCLUDE_NVPARMS + if(dhserve_nvparms.ServeDHCP) +#endif + { + e = dhcp_init(); + if(e) + { + dprintf("Error %d starting DHCP server.\n",e); + } + else + { + exit_hook(dhcpsrv_cleanup); + dprintf("Started DHCP server\n"); + } + } +#endif /* DHCP_SERVER */ + +#ifdef IN_MENUS + printf(prompt); +#endif + +#ifdef UDPSTEST + e=udp_echo_init(); + if ( e == SUCCESS ) + { + exit_hook(udp_echo_cleanup); + } + else + dprintf("Error %d starting UDP Echo server.\n",e); +#endif + +#ifdef RIP_SUPPORT + e=rip_init(); + if ( e == SUCCESS ) + { + exit_hook(rip_cleanup); + } + else + dprintf("Error %d starting RIP server.\n",e); +#endif + +#ifdef INICHE_SYSLOG + e =syslog_init(); + if (e == SUCCESS) + exit_hook(closelog); + else + dprintf("Error %d initializing syslog client.\n",e); +#endif + +#ifdef FTP_CLIENT + fc_callback=ftpc_callback; +#endif + +#ifdef INCLUDE_SSLAPP + sslapp_init(); +#endif + +#ifdef USE_SNTP_V4 + sntpv4_init (); +#endif + +/* The following initializations take place when SUPERLOOP is enabled. + * Otherwise they would be done in the respective task. + */ + +#ifdef SUPERLOOP + +#ifdef INCLUDE_SNMP + e = snmp_init(); + if (e == SUCCESS) + exit_hook(snmp_cleanup); + else + dprintf("Error %d initializing SNMP agent.\n",e); +#endif /* INCLUDE_SNMP */ + +#ifdef WEBPORT + e = http_init(); /* start up http server */ + if (e) + dprintf("Error %d starting HTTP server.\n",e); +#endif /* WEBPORT */ + +#ifdef FTP_SERVER + e = ftps_init(); + if ( e == SUCCESS ) + { + exit_hook(ftps_cleanup); + } + else + dprintf("Error %d starting FTP server.\n",e); +#endif /* FTP_SERVER */ + +#ifdef TELNET_SVR + e=tel_init(); + if ( e == SUCCESS ) + { + exit_hook(tel_cleanup); + } + else + dprintf("Error %d starting TELNET server.\n",e); +#endif + +#ifdef TCP_ECHOTEST + e=tcp_echo_init(); + if ( e == SUCCESS ) + { + exit_hook(tcp_echo_cleanup); + } + else + dprintf("Error %d starting TCP Echo server.\n",e); +#endif +#ifdef TCP_CIPHERTEST + e=tcp_cipher_init(); + if ( e == SUCCESS ) + { + exit_hook(tcp_cipher_cleanup); + } + else + dprintf("Error %d starting TCP cipher server.\n",e); +#endif +#ifdef USE_CRYPTOENG + e = ce_init(); + if(e != 0) + { + dprintf("ce_init() failed\n"); + panic("prep_modules"); + } +#endif + +#ifdef SMTP_ALERTS + smtp_init (); +#endif + +#ifdef CSUM_DEMO + csum_init(); +#endif + +#ifdef USE_SNTP_V4 + e = sntpv4_app (); + if(e != 0) + { + dprintf("Failed to start time sync via SNTPv4 client\n"); + panic("prep_modules"); + } +#endif + +#endif /* SUPERLOOP */ + +#ifdef INCLUDE_SSLAPP + e = sslapp_init(); + if(e != 0) + { + dprintf("sslapp_init() failed\n"); + panic("prep_modules"); + } +#endif + USE_ARG(e); /* Avoid compiler warnings */ + +} /* end of netmain_init() */ + + +#ifdef FULL_ICMP +char * icmpdu_types[] = { + "NET", + "HOST", + "PROT", + "PORT", + "FRAG", + "SRC", +}; + +/* FUNCTION: imcp_port_du() + * + * PARAM1: void * pio + * + * RETURNS: + */ + +void +icmp_port_du(PACKET p, struct destun * pdp) +{ + dprintf("got ICMP %s UNREACHABLE from %s\n", + icmpdu_types[(int)(pdp->dtype)], print_ipad(p->fhost) ); + dprintf(prompt); +} +#endif /* FULL_ICMP */ + + + +/* FUNCTION: station_state() + * + * state() - printf some info about the current state of the user + * settable station variables. + * + * PARAM1: void * pio + * + * RETURNS: + */ + +int +station_state(void * pio) +{ + int i; + +#ifndef NO_INET_STACK + NET ifp; + + for (i = 0, ifp = (NET)netlist.q_head; ifp; ifp = ifp->n_next, i++) + { + ns_printf(pio, "iface %d-%s IP addr:%s ", + i, ifp->name, print_ipad(ifp->n_ipaddr) ); + ns_printf(pio, "subnet:%s ", print_ipad(ifp->snmask) ); + ns_printf(pio, "gateway:%s\n", print_ipad(ifp->n_defgw) ); + } +#endif /* NO_INET_STACK */ + + ns_printf(pio, "current tick count %lu\n", cticks); + + ns_printf(pio, "common delay parameter: %lu ticks (%lu ms).\n", pingdelay, (pingdelay * TIMEFOR1TICK)); + ns_printf(pio, "common host parameter: %s\n", print_ipad(activehost)); + ns_printf(pio, "common length parameter: %d\n", deflength); + +#ifdef PING_APP + ns_printf(pio, "ping delay: %lu ticks (%lu ms).\n", ping4_delay, (ping4_delay * TIMEFOR1TICK)); + ns_printf(pio, "ping host: %s\n", print_ipad(ping4_activehost)); + ns_printf(pio, "ping length: %lu\n", ping4_deflength); +#endif + +#ifdef USE_MODEM + ns_printf(pio, "current dialout number is %s\n", mdm_dial_string); +#endif /* USE_MODEM */ + +#ifdef USE_PPP + ns_printf(pio, "current dial-in user name is %s\n", pppcfg.username); + ns_printf(pio, "current dial-in password is %s\n", pppcfg.password); +#endif /* USE_PPP */ + + task_stats(pio); + + return 0; +} + +#ifdef FTP_CLIENT +/* If FC_USECALLBACK is enabled in ftpclnt.h, and if fc_callback + * is defined, then FTP Client will call fc_callback when + * its state changes. FC_USECALLBACK is enabled by default. + */ + +void ftpc_callback(void *fc,int logstate, int cmdstate) +{ + /* + dprintf("logstate=%d, cmdstate=%d\n",logstate,cmdstate); + */ + + USE_VOID(fc); + USE_ARG(logstate); + USE_ARG(cmdstate); +} + +#endif + + +#ifndef NO_INET_STACK /* these functions are pretty stack-centric */ + + +/* FUNCTION: sysuptime() + * + * sysuptime() - return MIB-2 sys group compatable "sysUptime" value + * + * PARAM1: + * + * RETURNS: + */ + +unsigned long +sysuptime() +{ + return ((cticks/TPS)*100); /* 100ths of a sec since boot time */ +} + + +/* FUNCTION: packet_check() - check for incoming packet + * Process incoming packets. + * + * inside_pktdemux is nonzero while processing a received packet. + * It is used for reentrancy protection. + * + * PARAM1: + * + * RETURNS: + */ + + +static int inside_pktdemux = 0; + +void +packet_check(void) +{ + if(inside_pktdemux != 0) /* check re-entrancy flag */ + return; /* do not re-enter pktdemux(), packet will wait... */ + inside_pktdemux++; /* set re-entrany flag */ + pktdemux(); /* process low level packet input */ + inside_pktdemux--; /* clear re-entrany flag */ +} + +#ifdef IP_MULTICAST +/* This is a dummy routine that is replaced by the porting engineer with + * a routine by the same name in the Ethernet driver. The purpose of this + * routine is to convert IP multicast addresses to their Ethernet multicast + * addresses and program the chip with the appropriate Ethernet multicast + * filters. In the case of PPP, this dummy routine can be used. + */ + + +/* FUNCTION: mcastlist() + * + * PARAM1: struct in_multi *multi_ptr + * + * RETURNS: + */ + +int +mcastlist(struct in_multi * multi_ptr) +{ + USE_ARG(multi_ptr); + + return 0; +} +#endif /* IP_MULTICAST */ + +/********* For Superloop AND Netmain builds *********************/ + +/* FUNCTION: prep_modules() + * + * Call the preparation functions for all modules. + * Each module can have a preparation function wherein it + * intializes the menu, nvparms, etc. + * + * PARAM1: + * + * RETURNS: 0 on SUCCESS. + * + */ + + +#ifdef USE_PPP +extern int ppp_setup(void); +#endif /* USE_PPP */ + +#ifdef USE_MODEM +extern int prep_modem(void); +#endif /* USE_MODEM */ + +int prep_modules(void) +{ +#ifdef IP_V6 + ip6_addr host; + int i; +#endif + +int e = 0; + + +#ifdef IP_V6 + for (i = 0; i < STATIC_NETS; i++) + { + /* zero out addresses */ + { + int ifIndx; + + for (ifIndx = 0; ifIndx < MAX_V6_ADDRS; ifIndx++) + netstatic[i].v6addrs[ifIndx] = (struct ip6_inaddr *)0; + for (ifIndx = 0; ifIndx < MAX_V6_ADDRS; ifIndx++) + netstatic[i].v6addrsExtd[ifIndx] = (struct ip6_inaddr *)0; + } + } + ip6_init(); +#endif + +#ifdef PING_APP + ping_init(); +#endif /* PING_APP */ + + +#ifdef USE_CRYPTOENG + e = ce_init(); + if(e != 0) + { + dprintf("ce_init() failed\n"); + panic("prep_modules"); + } +#endif +#ifdef USE_PPP + e = ppp_setup(); + if (e != 0) + { + dprintf("PPP Module setup failed\n"); + panic("prep_modules"); + } +#endif /* USE_PPP */ + +#ifdef USE_MODEM + e = prep_modem(); + if (e != 0) + { + dprintf("Modem Module prep failed\n"); + panic("prep_modules"); + } +#endif /* USE_MODEM */ + +#ifdef TELNET_SVR + e = prep_telnet(); + if (e != 0) + { + dprintf("Telnet Module prep failed\n"); + panic("prep_modules"); + } +#endif /* TELNET_SVR */ + +#ifdef DHCP_SERVER + e = prep_dhcpsrv(); + if (e != 0) + { + dprintf("DHCP Server Module prep failed\n"); + panic("prep_modules"); + } +#endif /* DHCP_SERVER */ + +#ifdef NATRT + e = prep_natrt(); + if (e != 0) + { + dprintf("Nat Router Module prep failed\n"); + panic("prep_modules"); + } +#endif /* NATRT */ + +#ifdef RIP_SUPPORT + e = prep_rip(); + if (e != 0) + { + dprintf("Rip Module prep failed\n"); + panic("prep_modules"); + } +#endif /* RIP_SUPPORT */ + +#ifdef INCLUDE_SNMP + e = prep_snmp(); + if (e != 0) + { + dprintf("SNMP Module prep failed\n"); + panic("prep_modules"); + } +#endif /* INCLUDE_SNMP */ + +#ifdef INICHE_SYSLOG + e = prep_syslog(); + if (e != 0) + { + dprintf("Syslog Client prep failed\n"); + panic("prep_modules"); + } +#endif /* INICHE_SYSLOG */ + +#ifdef SMTP_ALERTS + e = prep_smtp(); + if (e != 0) + { + dprintf("SMTP Module prep failed\n"); + panic("prep_modules"); + } +#endif /* SMTP_ALERTS */ + +#ifdef VFS_FILES + e = prep_vfs(); + if (e != 0) + { + dprintf("VFS Module prep failed\n"); + panic("prep_modules"); + } +#endif /* VFS_FILES */ + + +#ifdef FTP_CLIENT + e = prep_ftpc(); + if (e != 0) + { + dprintf("FTP Client Module prep failed\n"); + panic("prep_modules"); + } +#endif /* FTP_CLIENT */ + +#ifdef WEBPORT + e = prep_http(); + if (e != 0) + { + dprintf("Web Server Module prep failed\n"); + panic("prep_modules"); + } +#endif /* WEBPORT */ + +#ifdef INCLUDE_SSLAPP + e = sslapp_init(); + if(e != 0) + { + dprintf("sslapp_init() failed\n"); + panic("prep_modules"); + } +#endif + return 0; +} + +#endif /* NO_INET_STACK */ + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/allports/timeouts.c b/FPGA_nios/hit_pat_bsp/iniche/src/allports/timeouts.c new file mode 100644 index 0000000..eecfcf1 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/allports/timeouts.c @@ -0,0 +1,360 @@ +/* + * FILENAME: timeouts.c + * + * Copyright 2000 By InterNiche Technologies Inc. All rights reserved + * + * Handles InterNiche task & application interval timers. + * + * MODULE: MISCLIB + * + * ROUTINES: inet_timer(), + * + * PORTABLE: yes + */ + + +#include "ipport.h" +#include "in_utils.h" +#include "q.h" +#include "netbuf.h" +#include "net.h" +#include "arp.h" +#include "ip.h" + +#ifdef INICHE_TIMERS /* build using interval timers? */ +#include "intimers.h" +static void check_interval_timers(void); +#endif + +#ifdef INCLUDE_TCP +void tcp_tick(void); +#endif + +#if defined (IP_MULTICAST) && (defined (IGMP_V1) || defined (IGMP_V2)) +/* Call igmp timeout routine */ +extern unsigned long igmp_cticks; +extern void igmp_fasttimo(void); +#endif /* IP_MULTICAST and (IGMPv1 or IGMPv2) */ + +#ifdef USE_PPP +extern void ppp_timeisup(void); +#endif +#ifdef DHCP_CLIENT +extern int dhc_discover(int iface); +extern int dhc_second(void); +#endif +#ifdef DHCP_SERVER +extern void dhcp_timeisup(void); +#endif +#ifdef FTP_SERVER +extern void ftps_check(void); +#endif +#ifdef DNS_CLIENT +extern void dns_check(void); +#endif +#ifdef NATRT +extern void nat_timeisup(void); +#endif +#ifdef USE_MODEM +extern void dial_check(void); +#endif +#ifdef USE_COMPORT +extern void uart_check(void); +#endif +#ifdef PING_APP +void ping_check(void); +#endif +#ifdef IP_V6 +void ip6_timer(void); +static unsigned long v6timer_mod = 0L; +#endif +#ifdef TCP_ECHOTEST +void tcp_echo_poll(void); +#endif +#if defined(TFTP_CLIENT) || defined(TFTP_SERVER) +extern void tftp_tick(void); +#endif +#ifdef UDPSTEST +extern void udp_echo_poll(void); +#endif /* UDPSTEST */ +#ifdef RIP_SUPPORT +extern void rip_check(void); +#endif /* RIP_SUPPORT */ +#ifdef INCLUDE_SNMP +extern void snmp_check(void); +#endif +#ifdef BTREE_ROUTES +extern void rtbtree_tmo(void); +#endif /* BTREE_ROUTES */ +#ifdef RAWIPTEST +extern void raw_testerq_poll(void); +#endif /* RAWIPTEST */ +#ifdef WEBPORT +extern void http_check(void); +#endif +#ifdef TELNET_SVR +extern void tel_check(void); +#endif +#ifdef FTP_CLIENT +void ftpc_periodic_timer(void); +#endif +#ifdef IP_FRAGMENTS +extern u_long ire_cticks; +extern u_char ip_reasm_process_timer_tick(void); +#endif +#ifdef USE_SNTP_V4 +extern int sntpv4_timeout(void); +#endif + +/* if INICHE_TASKS is defined, this is done vxd_task() in task for Vxd */ +#ifndef INICHE_TASKS +#ifdef USE_VXD +extern void vxd_check(void); +#endif +#endif + +unsigned long nextppp = 0L; /* tick for next call to ppp timer */ + +void (*port_1s_callout)(void) = NULL; + +/* FUNCTION: inet_timer() + * + * This handles all TCP/IP related timeouts. Ideally this should be + * called about 10 times a second; and no less than twice a second + * (The minimum for TCP timeouts). Does NOT handle most + * application timeouts. + * + * + * PARAM1: void + * + * RETURNS: + */ + +void +inet_timer(void) +{ +#ifdef IP_FRAGMENTS + /* run thru' the IP reassembly queue (once every second) */ + if (ire_cticks < cticks) + ip_reasm_process_timer_tick (); +#endif + +#ifdef INCLUDE_TCP + tcp_tick(); /* run TCP timers */ +#endif + +#ifdef INICHE_TIMERS /* interval timers? */ + check_interval_timers(); +#endif + +#if defined (IP_MULTICAST) && (defined (IGMP_V1) || defined (IGMP_V2)) + /* Call igmp timeout routine */ + if (igmp_cticks < cticks) /* Call igmp timeout routine 5 times per sec */ + igmp_fasttimo(); +#endif /* IP_MULTICAST and (IGMPv1 or IGMPv2) */ + +#ifdef USE_SNTP_V4 + sntpv4_timeout (); +#endif + +#ifdef USE_MODEM + dial_check(); +#endif /* USE_MODEM */ + +#ifdef USE_COMPORT + uart_check(); +#endif + +#ifdef UDPSTEST + udp_echo_poll(); +#endif + +#ifdef PING_APP + ping_check(); /* check for ping send/receive */ +#endif + +#ifdef RAWIPTEST + raw_testerq_poll(); +#endif + + +#ifdef SUPERLOOP +#ifdef WEBPORT + http_check(); +#endif +#ifdef TELNET_SVR + tel_check(); +#endif +#ifdef INCLUDE_SNMP + snmp_check(); +#endif +#endif /* SUPERLOOP */ + + +/* if INICHE_TASKS is defined, this is done vxd_task() in task for Vxd */ +#if (defined(USE_VXD) && !defined(INICHE_TASKS)) + vxd_check(); +#endif + +/* !!!??? */ +#ifdef IP_V6 + if ((v6timer_mod < cticks) || /* next call to ip6_timer is due */ + (v6timer_mod > (cticks + (10 * TPS))) ) /* for when cticks wraps */ + { + v6timer_mod = cticks + (TPS / 5); + ip6_timer(); + } +#endif + + + + /* Some timer routines only need calling once a second: */ + if ((nextppp < cticks) || /* next call to PPP is due */ + (nextppp > (cticks+(10*TPS))) ) /* for when cticks wraps */ + { + nextppp = cticks + TPS; + + if (port_1s_callout != NULL) + (*port_1s_callout)(); + +#ifdef USE_PPP + ppp_timeisup(); +#endif +#ifdef DHCP_CLIENT + dhc_second(); +#endif +#ifdef DHCP_SERVER + dhcp_timeisup(); +#endif +#ifdef DNS_CLIENT + dns_check(); +#endif +#ifdef NATRT + nat_timeisup(); +#endif +#ifdef RIP_SUPPORT + rip_check(); +#endif +#if defined(TFTP_CLIENT) || defined(TFTP_SERVER) + tftp_tick(); +#endif + +#ifdef BTREE_ROUTES + rtbtree_tmo(); +#endif /* BTREE_ROUTES */ +#ifdef FTP_CLIENT + ftpc_periodic_timer(); +#endif +#ifdef IPSEC + IPSecTimer(); +#endif + } +} + + +#ifdef INICHE_TIMERS + +struct intimer intimers[NUM_INTIMERS]; + +/* FUNCTION: check_interval_timers() + * + * Check to see if any interval timers are ready to fire. + * + * RETURNS: NA + */ + +static int numtimers = 0; /* number of active timers */ + +static void +check_interval_timers(void) +{ + int i; + int found = 0; /* number of valid timers found */ + + /* if no timers, just return */ + if (numtimers > 0) + { + /* loop throught the timer list looking for active timers ready to fire */ + for (i = 0; i < NUM_INTIMERS; i++) + { + if (intimers[i].callback) /* is this timer active? */ + { + if ((intimers[i].tmo < cticks) && (!intimers[i].inuse)) /* timer ready fire? */ + { + intimers[i].tmo = intimers[i].interval + cticks; /* set next tmo */ + intimers[i].inuse = TRUE; + intimers[i].callback(intimers[i].parm); /* call user routine */ + intimers[i].inuse = FALSE; + } + /* If we've examined all the active timers, we're done */ + if (++found >= numtimers) + break; + } + } + } +} + +/* FUNCTION: in_timerset() + * + * Create an interval timer + * + * PARAM1: callback routine + * PARAM2: number of milliseconds between callback calls + * PARAM3: parameter to pass to callbacks + * + * RETURNS: timer ID if OK, else if table is full. + */ + +long +in_timerset(void (*callback)(long), long msecs, long parm) +{ + int i; + + for(i = 0; i < NUM_INTIMERS; i++) + { + if(intimers[i].callback == NULL) + { + /* found empty table entry, set up new timer */ + intimers[i].callback = callback; + intimers[i].parm = parm; + /* set interval, in TPS (cticks) units */ + intimers[i].interval = (msecs * TPS)/1000; + intimers[i].tmo = intimers[i].interval + cticks; /* first tmo */ + intimers[i].inuse = FALSE; + numtimers++; + return (long)&intimers[i]; + } + } + return 0; +} + +/* FUNCTION: in_timerkill() + * + * Delete a timer created previously by a call to in_timerset() + * + * PARAM1: long timer Address of the timer to delete. + * + * RETURNS: 0 if OK, ENP error if timer not in list. + */ + + +int +in_timerkill(long timer) +{ + int i; + + for(i = 0; i < NUM_INTIMERS; i++) + { + if(timer == (long)&intimers[i]) + { + intimers[i].callback = NULL; + numtimers--; + return 0; /* OK return */ + } + } + dtrap(); /* timer to kill not found */ + return ENP_PARAM; +} + +#endif /* INICHE_TIMERS */ + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/allports/tk_misc.c b/FPGA_nios/hit_pat_bsp/iniche/src/allports/tk_misc.c new file mode 100644 index 0000000..65c44bd --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/allports/tk_misc.c @@ -0,0 +1,358 @@ +/* + * FILENAME: tk_misc.c + * + * Copyright 2002 By InterNiche Technologies Inc. All rights reserved + * + * Routines to create Network Tasks for the Generic Multitasking systems ports + * of InterNiche TCP/IP NetOS package. Also contains other miscellaneous + * routines for Multitasking ports. + * + * MODULE: ALLPORTS + * + * ROUTINES: create_apptasks(), tk_keyboard() + * ROUTINES: task_stats() + * + * PORTABLE: yes + */ + +#include "ipport.h" +#include "libport.h" + +/* Multitasking systems should use this file, however superloop + *systems need to be able to ifdef it away + */ + +#ifndef SUPERLOOP /* whole file can be ifdeffed out */ + +/* include project header. Define this in ipport.h to point to a file + * in your project directory, i.e. "..\******\osport.h" + */ + +#ifndef OSPORT_H +#error Need to define OSPORT_H +#endif +#include OSPORT_H + +#ifdef WEBPORT +extern struct inet_taskinfo httptask; +extern long webport_wakes; +#endif +#ifdef FTP_SERVER +extern struct inet_taskinfo ftpstask; +extern long ftpsrv_wakes; +#endif +#ifdef FTP_CLIENT +extern struct inet_taskinfo ftpctask; +#endif +#ifdef SMTP_ALERTS +extern struct inet_taskinfo smtptask; +extern long emailer_wakes; +#endif +#ifdef TELNET_SVR +extern struct inet_taskinfo telnettask; +extern long telnetsrv_wakes; +#endif +#ifdef USE_CRYPTOENG +extern struct inet_taskinfo cuexecutetask; +extern long cuexecute_wakes; +#endif +#ifdef USE_SYSLOG_TASK +extern struct inet_taskinfo syslog_task; +extern long syslog_wakes; +#endif +#ifdef INCLUDE_SNMP +extern struct inet_taskinfo snmptask; +extern long snmp_wakes; +#endif +#ifdef DNS_SERVER +extern struct inet_taskinfo dnssrvtask; +#endif +#ifdef NICHVIEW +extern struct inet_taskinfo browtask; +extern long browtask_wakes; +#endif +#ifdef TK_STDIN_DEVICE +extern struct inet_taskinfo keyboardtask; +extern long keyboard_wakes; +extern void kbdio(void); +#endif +#ifdef USE_SNTP_V4 +extern struct inet_taskinfo sntpv4apptask; +#endif +#ifndef NO_INET_STACK +extern long netmain_wakes; +#endif /* NO_INET_STACK */ +#ifndef NO_INET_TICK +extern long nettick_wakes; +#endif /* NO_INET_TICK */ +#ifdef PING_APP +extern long pingcheck_wakes; +#endif /* #ifdef PING_APP */ +#ifdef TCP_ECHOTEST +extern long echotest_wakes; +#endif /* TCP_ECHOTEST */ +#ifdef TCP_CIPHERTEST +extern long ciphertest_wakes; +#endif /* TCP_CIPHERTEST */ +#ifdef IKE +extern struct inet_taskinfo iketask; +extern long ike_wakes; +#endif +#ifdef INCLUDE_SSLAPP +extern struct inet_taskinfo sslapp_task; +extern long sslapp_wakes; +#endif +/* per-application thread definitions */ + +int +create_apptasks(void) +{ +int e = 0; +#ifdef USE_CRYPTOENG + e = TK_NEWTASK(&cuexecutetask); + if (e != 0) + { + dprintf("cuexecutetask create error\n"); + panic("create_apptasks"); + return -1; /* compiler warnings */ + } +#endif +#ifdef WEBPORT + e = TK_NEWTASK(&httptask); + if (e != 0) + { + dprintf("httptask create error\n"); + panic("create_apptasks"); + return -1; /* compiler warnings */ + } +#endif +#ifdef FTP_SERVER + e = TK_NEWTASK(&ftpstask); + if (e != 0) + { + dprintf("ftpstask create error\n"); + panic("create_apptasks"); + return -1; /* compiler warnings */ + } +#endif +#ifdef FTP_CLIENT + e = TK_NEWTASK(&ftpctask); + if (e != 0) + { + dprintf("ftpctask create error\n"); + panic("create_apptasks"); + return -1; /* compiler warnings */ + } +#endif +#ifdef SMTP_ALERTS + e = TK_NEWTASK(&smtptask); + if (e != 0) + { + dprintf("smtptask create error\n"); + panic("create_apptasks"); + return -1; /* compiler warnings */ + } +#endif +#ifdef TELNET_SVR + e = TK_NEWTASK(&telnettask); + if (e != 0) + { + dprintf("telnettask create error\n"); + panic("create_apptasks"); + return -1; /* compiler warnings */ + } +#endif +#ifdef INCLUDE_SNMP + e = TK_NEWTASK(&snmptask); + if (e != 0) + { + dprintf("snmptask create error\n"); + panic("create_apptasks"); + return -1; /* compiler warnings */ + } +#endif +#ifdef DNS_SERVER + e = TK_NEWTASK(&dnssrvtask); + if (e != 0) + { + dprintf("dnssrvtask create error\n"); + panic("create_apptasks"); + return -1; /* compiler warnings */ + } +#endif +#ifdef NICHVIEW + e = TK_NEWTASK(&browtask); + if (e != 0) + { + dprintf("browtask create error\n"); + panic("create_apptasks"); + return -1; /* compiler warnings */ + } +#endif +#ifdef TK_STDIN_DEVICE + e = TK_NEWTASK(&keyboardtask); + if (e != 0) + { + dprintf("keyboardtask create error\n"); + panic("create_apptasks"); + return -1; /* compiler warnings */ + } +#endif +#ifdef IKE + e = TK_NEWTASK(&iketask); + if (e != 0) + { + dprintf("IKE create error\n"); + panic("create_apptasks"); + return -1; /* compiler warnings */ + } +#endif +#ifdef USE_SYSLOG_TASK + e = TK_NEWTASK(&syslog_task); + if(e != 0) + { + dprintf("syslog_task create error\n"); + panic("create_apptasks"); + return -1; /* compiler warnings */ + } +#endif +#ifdef INCLUDE_SSLAPP + e = TK_NEWTASK(&sslapp_task); + if (e != 0) + { + dprintf("sslapp_task create error\n"); + panic("create_apptasks"); + return -1; /* compiler warnings */ + } +#endif +#ifdef USE_SNTP_V4 + e = TK_NEWTASK(&sntpv4apptask); + if(e != 0) + { + dprintf("SNTPv4 application task create error\n"); + panic("create_apptasks"); + return -1; + } +#endif +/* + * Altera Niche Stack Nios port modification: + * return error code, if any + */ + return e; +} + +#ifdef TK_STDIN_DEVICE +extern void kbdio(void); +#endif + +#ifdef TK_STDIN_DEVICE +TK_OBJECT(to_keyboard); +TK_ENTRY(tk_keyboard); +long keyboard_wakes = 0; +#endif /* TK_STDIN_DEVICE */ + +#ifdef TK_STDIN_DEVICE +struct inet_taskinfo keyboardtask = { + &to_keyboard, + "console", + tk_keyboard, + TK_KEYBOARD_TPRIO, + IO_STACK_SIZE, +}; +#endif + + +/* FUNCTION: TK_ENTRY() + * + * Task to hand keystrokes to InerNiche menu system + * + * PARAM1: n/a + * + * RETURNS: n/a + */ + +#ifdef TK_STDIN_DEVICE +TK_ENTRY(tk_keyboard) +{ + for (;;) + { + TK_SLEEP(1); /* make keyboard yield some time */ + kbdio(); /* let Iniche menu routines poll for char */ + keyboard_wakes++; /* count wakeups */ + + if (net_system_exit) + break; + } + TK_RETURN_OK(); +} +#endif /* TK_STDIN_DEVICE */ + + + +/* FUNCTION: task_stats() + * + * Print the "wake" statistics of all tasks. + * + * PARAM1: void * pio + * + * RETURNS: + */ + + +void +task_stats(void * pio) +{ + ns_printf(pio, "Task wakeups:"); + +#ifndef NO_INET_STACK + ns_printf(pio, "netmain: %lu\n", netmain_wakes); +#endif +#ifndef NO_INET_TICK + ns_printf(pio, "nettick: %lu\n", nettick_wakes); +#endif +#ifdef TK_STDIN_DEVICE + ns_printf(pio, "keyboard: %lu\n", keyboard_wakes); +#endif +#ifdef WEBPORT + ns_printf(pio, "webport: %lu ", webport_wakes); +#endif +#ifdef FTP_SERVER + ns_printf(pio, "ftpsrv: %lu ", ftpsrv_wakes); +#endif +#ifdef PING_APP + ns_printf(pio, "pingcheck: %lu ", pingcheck_wakes); +#endif +#ifdef TELNET_SVR + ns_printf(pio, "telnetsrv: %lu ", telnetsrv_wakes); +#endif +#ifdef USE_CRYPTOENG + ns_printf(pio, "USE_CRYPTOENG: %lu ", cuexecute_wakes); +#endif +#ifdef USE_SYSLOG_TASK + ns_printf(pio, "USE_SYSLOG_TASK: %lu ", syslog_wakes); +#endif +#ifdef SMTP_ALERTS + ns_printf(pio, "smtpclient: %lu ", emailer_wakes); +#endif +#ifdef SNMP_SOCKETS + ns_printf(pio, "snmpsock: %lu ", snmp_wakes); +#endif +#ifdef TCP_ECHOTEST + ns_printf(pio, "echotest: %lu ", echotest_wakes); +#endif +#ifdef TCP_CIPHERTEST + ns_printf(pio, "ciphertest: %lu ", ciphertest_wakes); +#endif +#ifdef USE_BROWSER + ns_printf(pio, "browtask: %lu ", browtask_wakes); +#endif +#ifdef INCLUDE_SSLAPP + ns_printf(pio, "INCLUDE_SSLAPP: %lu ", sslapp_wakes); +#endif + ns_printf(pio, "\n"); +} + + +#endif /* SUPERLOOP - whole file can be ifdeffed out */ + + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_close.c b/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_close.c new file mode 100644 index 0000000..d989cb9 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_close.c @@ -0,0 +1,61 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT IT DIRECTLY. * +* * +* Overriding HAL Functions * +* * +* To provide your own implementation of a HAL function, include the file in * +* your Nios II IDE application project. When building the executable, the * +* Nios II IDE finds your function first, and uses it in place of the HAL * +* version. * +* * +******************************************************************************/ + +#include "system.h" +#include "sys/alt_sys_wrappers.h" +#include "ipport.h" +#include "tcpport.h" + +/* + * close() is called by an application to release a file descriptor. This + * implementation vectors requests to either the HAL alt_close() function + * (for files and device drivers) or the InterNiche soclose() function for + * sockets. + */ + +int close (int fd) +{ + return (fd < ALT_MAX_FD) ? alt_close (fd) : t_socketclose ((long) fd); +} diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_dev.c b/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_dev.c new file mode 100644 index 0000000..1414a20 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_dev.c @@ -0,0 +1,147 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +* * +* Source for the Altera InterNiche device services. * +* * +* Author EPS * +* * +******************************************************************************/ + +/******************************************************************************* + ******************************************************************************* + * + * InterNiche device services. + * + ******************************************************************************* + ******************************************************************************/ + +/******************************************************************************* + * + * Imported services. + * + ******************************************************************************/ + +#include "sys/alt_llist.h" +#include "alt_iniche_dev.h" + +#ifdef IP_MULTICAST +#include "ipmc/igmp_cmn.h" +extern int mcastlist(struct in_multi *); +#endif + + +/******************************************************************************* + * + * InterNiche device service globals. + * + ******************************************************************************/ + +/* List of InterNiche devices. */ +ALT_LLIST_HEAD(alt_iniche_dev_list); + + +/******************************************************************************* + * + * InterNiche device service functions. + * + ******************************************************************************/ + +/* + * iniche_devices_init + * + * --> if_count Number of interfaces before init. + * + * <-- Number of interfaces after init. + * + * This function initializes the InterNiche devices. The number of interfaces + * before initialization is specified by if_count. This function returns the + * total number of interfaces after initialization. + */ + +int iniche_devices_init( + int if_count) +{ + alt_iniche_dev *p_dev; + alt_iniche_dev *p_dev_list_end; + NET p_net; + ip_addr ipaddr, + netmask, + gw; + int use_dhcp; + + /* Get the InterNiche device list. */ + p_dev = (alt_iniche_dev *) (alt_iniche_dev_list.next); + p_dev_list_end = (alt_iniche_dev *) (&(alt_iniche_dev_list.next)); + + /* Initialize each InterNiche device. */ + while (p_dev != p_dev_list_end) + { + /* Initialize the InterNiche device data record. */ + p_dev->p_driver_data = p_dev; + p_dev->if_num = if_count; + p_dev->p_net = nets[p_dev->if_num]; + + /* Perform device specific initialization. */ + (*(p_dev->init_func))(p_dev); + + /* Get the interface IP address. */ + p_net = p_dev->p_net; + + if (get_ip_addr(p_dev, &ipaddr, &netmask, &gw, &use_dhcp)) + { +#ifdef DHCP_CLIENT + /* + * OR in the DHCP flag, if enabled. This will allow any + * application-specific flag setting in get_ip_addr(), such + * as enabling AUTOIP, to occur + */ + if (use_dhcp) { + p_net->n_flags |= NF_DHCPC; + } +#endif + p_net->n_ipaddr = ipaddr; + p_net->snmask = netmask; + p_net->n_defgw = gw; +#ifdef IP_MULTICAST + p_net->n_mcastlist = mcastlist; +#if defined (IGMP_V1) || defined (IGMP_V2) + p_net->igmp_oper_mode = IGMP_MODE_DEFAULT; +#endif /* IGMPv1 or IGMPv2 */ +#endif /* IP_MULTICAST */ + } + + /* Initialize next device. */ + if_count++; + p_dev = (alt_iniche_dev *) p_dev->llist.next; + } + + return (if_count); +} diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_fcntl.c b/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_fcntl.c new file mode 100644 index 0000000..fa12d36 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_fcntl.c @@ -0,0 +1,74 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT IT DIRECTLY. * +* * +* Overriding HAL Functions * +* * +******************************************************************************/ + +#include +#include +#include "system.h" +#include "sys/alt_sys_wrappers.h" +#include "ipport.h" +#include "tcpport.h" + +/* + * fcntl() is called by an application to release a file descriptor. This + * implementation duplicates the code of the HAL alt_fcntl() function + * (for files and device drivers) or calls the InterNiche bsd_ioctl for + * sockets. + */ + +int fcntl (int file, int cmd, ...) +{ + long flags; + va_list argp; + + if (file < ALT_MAX_FD) + { + va_start(argp, cmd); + flags = va_arg(argp, long); + va_end(argp); + return alt_fcntl(file, cmd, flags); + } + else + { + va_start(argp, cmd); + flags = va_arg(argp, long); + va_end(argp); + return bsd_ioctl(file, cmd, flags); + } +} diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_read.c b/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_read.c new file mode 100644 index 0000000..aa88600 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_read.c @@ -0,0 +1,64 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT IT DIRECTLY. * +* * +* Overriding HAL Functions * +* * +* To provide your own implementation of a HAL function, include the file in * +* your Nios II IDE application project. When building the executable, the * +* Nios II IDE finds your function first, and uses it in place of the HAL * +* version. * +* * +******************************************************************************/ + +#include +#include "sys/alt_sys_wrappers.h" +#include "system.h" +#include "ipport.h" +#include "tcpport.h" + +/* + * The read() system call is used to read a block of data from a file or device. + * This implementation vectors requests to either the HAL alt_read() function + * (for files and device drivers) or the InterNiche recvfrom() function for + * sockets. + */ + +int read (int fd, void *ptr, size_t len) +{ + return (fd < ALT_MAX_FD) ? alt_read (fd, ptr, len) + : recvfrom(fd, ptr, len, 0, NULL, NULL); +} + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_write.c b/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_write.c new file mode 100644 index 0000000..eed9e14 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_write.c @@ -0,0 +1,72 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT IT DIRECTLY. * +* * +* Overriding HAL Functions * +* * +* To provide your own implementation of a HAL function, include the file in * +* your Nios II IDE application project. When building the executable, the * +* Nios II IDE finds your function first, and uses it in place of the HAL * +* version. * +* * +******************************************************************************/ + +#include +#include "sys/alt_sys_wrappers.h" +#include "system.h" +#include "ipport.h" +#include "tcpport.h" + +#ifndef ALT_NICHESTACK_ALT_SYSCALL_H + #error "The NicheStack component header file 'os/alt_syscall.h' is not being used. \ +Please delete the HAL version of this file from the BSP." +#endif +/* + * The write() system call is used to write a block of data to a file or device. + * This implementation vectors requests to either the HAL alt_write() function + * (for files and device drivers) or the InterNiche send() function for sockets. + */ + +int write (int fd, const void *ptr, size_t len) +{ + if (fd < ALT_MAX_FD) + { + return alt_write (fd, ptr, len); + } + else + { + return send (fd, (void*) ptr, len, 0); + } +} diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/autoip.c b/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/autoip.c new file mode 100644 index 0000000..d32bf8b --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/autoip.c @@ -0,0 +1,383 @@ +/* + * FILENAME: autoip.c + * + * Copyright 2002 By InterNiche Technologies Inc. All rights reserved + * + * AutoIP ARPs random IP addresses in a private, non-routed range. + * range: 169.254.x.x + * If nothing replys it assigns itself the address. + * + * 9/15/2000 - Created - Stan Breitlow + * + * MODULE: AUTOIP4 + * + * ROUTINES: AutoIp_init(), AutoIp_tick(), + * ROUTINES: AutoIp_arp_response(), AutoIp_send_arp_probe(), + * ROUTINES: AutoIp_pick_address(), AutoIp_get_state(), + * ROUTINES: AutoIp_set_net_vars(), + * + * PORTABLE: yes + */ + + +#include "ipport.h" + +#ifdef USE_AUTOIP +#ifndef DHCP_CLIENT +#error DHCP_CLIENT must be defined with USE_AUTOIP +#endif + +#include "q.h" +#include "netbuf.h" +#include "net.h" +#include "ip.h" +#include "ether.h" +#include "arp.h" +#include "dhcpclnt.h" + +#include "autoip.h" +#include "upnp.h" + +/* Set defaults for Base & range on AUtoIP address pool */ +u_long dBASE_AUTO_IP_ADDRESS = 0xA9FE0100; /* 169.254.1.0 */ +u_long dMAX_AUTO_IP_ADDRESS = 0xA9FEFEFF; /* 169.254.254.255 */ + +#define dRESPONSE_TIMEOUT 2000 /* 2 seconds */ +#define dVERIFY_WAIT_TIME 1000 /* 1 second */ +#define dNUMBER_OF_VERIFIES 3 + + +/* local protos */ +static ip_addr AutoIp_pick_address(void); +static void AutoIp_set_net_vars(int iface); + +extern void fixup_subnet_mask(int netnum); /* in ipnet.c */ + +unshort rand_seed; /* pseudo-random number */ + +struct autoIP autoIPs[MAXNETS]; + +/* FUNCTION: AutoIp_init() + * + * Initialize the sub modules + * + * PARAM1: void + * + * RETURNS: 0 + */ + +int +AutoIp_init() +{ + int iface; + void * stack_garbage = &iface; /* sort of random... */ + + /* look for an ethernet to seed the random numbers */ + for(iface = 0; iface < MAXNETS; iface++) + { + if(nets[iface] == NULL) + break; + + if(nets[iface]->n_mib->ifType == ETHERNET) + { + autoIPs[iface].state = AUTOIP_START; + autoIPs[iface].response_timer = 0; + autoIPs[iface].arp_attempts = 0; + + /* seed with unique part of mac address */ + if(!rand_seed) + { + rand_seed = (unshort)(nets[iface]->mib.ifPhysAddress[3] + + (nets[iface]->mib.ifPhysAddress[4] << 4) + + (nets[iface]->mib.ifPhysAddress[5] << 8)); + } + } + else + upnp[iface].state = UPNP_DISABLED; /* Disable Non-ethernets */ + } + /* XOR the random numbers from whatever garbage is on the stack. + * This may generate a compiler warning, but it's doing the right thing. + */ + rand_seed ^= (unshort)(u_long)(stack_garbage); + + return 0; +} + +#ifndef HAL_TIMER_ALREADY +u_long HAL_TIMER_get_ms_tick() +{ + return (cticks * (1000/TPS)); +} +#endif + +/* FUNCTION: AutoIp_tick() + * + * Called from Upnp_tick() every 100ms to run finite state machine + * + * PARAM1: void + * + * RETURNS: void + */ + +void +AutoIp_tick(int iface) +{ + switch (autoIPs[iface].state) + { + case AUTOIP_START: + autoIPs[iface].state = AUTOIP_ARP_PROBE; + break; + + case AUTOIP_ARP_PROBE: + + autoIPs[iface].try_address = AutoIp_pick_address(); + AutoIp_send_arp_probe(iface); + autoIPs[iface].arp_attempts++; + autoIPs[iface].response_timer = HAL_TIMER_get_ms_tick() + dRESPONSE_TIMEOUT; + autoIPs[iface].state = AUTOIP_ARP_RESPONSE_WAIT; + break; + + case AUTOIP_ARP_RESPONSE_WAIT: + + if (HAL_TIMER_get_ms_tick() > autoIPs[iface].response_timer) + { + /* No arp response within the time so */ + /* we will verify the address */ + autoIPs[iface].state = AUTOIP_ARP_VERIFY_PROBE; + autoIPs[iface].verify_attempts = 0; + } + break; + + case AUTOIP_ARP_ADDRESS_USED: + + if (autoIPs[iface].arp_attempts < 10) + { + /* try again */ + autoIPs[iface].state = AUTOIP_ARP_PROBE; + } + else + { + autoIPs[iface].state = AUTOIP_FAILED; + } + break; + + /* The address appears to be free, */ + /* verify still not used */ + case AUTOIP_ARP_VERIFY_PROBE: + + AutoIp_send_arp_probe(iface); + autoIPs[iface].verify_attempts++; + autoIPs[iface].response_timer = HAL_TIMER_get_ms_tick() + dVERIFY_WAIT_TIME; + autoIPs[iface].state = AUTOIP_ARP_VERIFY_WAIT; + break; + + case AUTOIP_ARP_VERIFY_WAIT: + + if (HAL_TIMER_get_ms_tick() > autoIPs[iface].response_timer) + { + /* If we have verified to our satisfaction */ + /* take the address */ + if (autoIPs[iface].verify_attempts >= dNUMBER_OF_VERIFIES) + { + autoIPs[iface].state = AUTOIP_GOT_ADDRESS; + /* Lets use this address */ + AutoIp_set_net_vars(iface); + } + else + { + /* verify again */ + autoIPs[iface].state = AUTOIP_ARP_VERIFY_PROBE; + } + } + break; + + case AUTOIP_FAILED: + break; + + default: + break; + } +} + + + +/* FUNCTION: AutoIp_arp_response() + * + * If an ARP Probe gets a response, the TCP/IP Stack upcalls this function. + * We will have to try another address. + * + * PARAM1: PACKET pkt + * + * RETURNS: void + */ + +void +AutoIp_arp_response(struct arp_hdr * arphdr, NET ifp) +{ + int iface; + + iface = if_netnumber(ifp); + + /* Check that we are in a mode that cares about all this */ + if (autoIPs[iface].state == AUTOIP_ARP_RESPONSE_WAIT) + { + /* Check for someone else probing this as a target address, IE their + * target (probed) address is that same as the one we are trying + */ + if (arphdr->ar_tpa == autoIPs[iface].try_address) + { + autoIPs[iface].state = AUTOIP_ARP_ADDRESS_USED; + return; + } + + /* Also check for a response from the probed address. + * This means some already has the address. + */ + if (arphdr->ar_spa == autoIPs[iface].try_address) + { + autoIPs[iface].state = AUTOIP_ARP_ADDRESS_USED; + return; + } + } +} + + + +/* FUNCTION: AutoIp_send_arp_probe() + * + * PARAM1: interface index + * + * RETURNS: void + */ + +void +AutoIp_send_arp_probe(int iface) +{ + PACKET pkt; + + LOCK_NET_RESOURCE(FREEQ_RESID); + pkt = pk_alloc(4); /* dummy packet */ + UNLOCK_NET_RESOURCE(FREEQ_RESID); + + if (pkt == NULL) + return; + + nets[iface]->n_ipaddr = 0; /* our IP address needs to be 0 */ + pkt->net = nets[iface]; + pkt->fhost = autoIPs[iface].try_address; + send_arp(pkt, autoIPs[iface].try_address); +} + + + +/* FUNCTION: AutoIp_pick_address() + * + * Pick a random auto IP address. Returns the address in network + * endian (big), which is how the IP, ARP & DHCP modules expect them. + * + * PARAM1: void + * + * RETURNS: random IP address + */ + +ip_addr +AutoIp_pick_address(void) +{ + unshort newrand = rand_seed--; /* bump this down since cticks goes up */ + + newrand ^= (unshort)(cticks + 1); + while(newrand > dAUTO_IP_RANGE) + newrand >>= 1; + return(htonl(dBASE_AUTO_IP_ADDRESS + newrand)); +} + + +/* FUNCTION: AutoIp_get_state() + * + * PARAM1: void + * + * RETURNS: + */ + +int +AutoIp_get_state(int iface) +{ + return(autoIPs[iface].state); +} + + +/* FUNCTION: AutoIp_set_net_vars() + * + * PARAM1: int iface + * + * RETURNS: + */ + +void +AutoIp_set_net_vars(int iface) +{ + nets[iface]->n_ipaddr = autoIPs[iface].try_address; + nets[iface]->snmask = htonl(0xFFFF0000); + nets[iface]->n_defgw = 0x00000000; + + if ( nets[iface]->snmask == 0 ) + { + fixup_subnet_mask(iface); + dhc_states[iface].snmask = nets[iface]->snmask; + } + + /* fixup broadcast addresses */ + nets[iface]->n_netbr = nets[iface]->n_ipaddr | ~nets[iface]->snmask; + nets[iface]->n_netbr42 = nets[iface]->n_ipaddr & nets[iface]->snmask; + nets[iface]->n_subnetbr = nets[iface]->n_ipaddr | ~nets[iface]->snmask; + + /* print IP address acquired through AutoIP - for user's benefit */ + printf("Acquired IP address via AutoIPv4 for interface: %s\n", nets[iface]->name); + printf("IP address : %s\n", print_ipad(nets[iface]->n_ipaddr)); + printf("Subnet Mask: %s\n", print_ipad(nets[iface]->snmask)); + printf("Gateway : %s\n", print_ipad(nets[iface]->n_defgw)); +} + + + +/* FUNCTION: dhc_hostname() + * + * Called from the DHCP client to get a valid hostname for this machine. This + * is a default routine which returns a dummy name. The porting engineer is + * expected to define GETHOSTNAME_ALREADY and replace this with a system + * routine. + * + * Note - if MUST always return a string. + * + * PARAM1: none + * + * RETURNS: pointer to ascii hostname string + */ + +#ifndef DHCHOSTNAME_ALREADY + +/* globally overridable hostname */ +char * system_dhcp_hostname = "dummy"; + +u_char * +dhc_hostname() +{ + char * hostname; + +#ifdef ALWAYS_HAVE_NAME + hostname = get_device_name(); + if(strcmp(hostname,"") == 0) + { + hostname = get_device_always_name(); + } +#else + hostname = system_dhcp_hostname; +#endif + + return (u_char*)hostname; +} + +#endif /* DHCHOSTNAME_ALREADY */ + +#endif /* USE_AUTOIP */ + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/autoip.h b/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/autoip.h new file mode 100644 index 0000000..8826fc2 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/autoip.h @@ -0,0 +1,58 @@ +/* AutoIP.h + + AutoIP, determines IP address by ARPing a trial address + and waiting for responses. + + 9/15/2000 - Created - Stan Breitlow + +*/ + +#ifndef AUTOIP_H +#define AUTOIP_H + +typedef enum +{ + AUTOIP_START, + AUTOIP_GOT_ADDRESS, + AUTOIP_ARP_PROBE, + AUTOIP_ARP_RESPONSE_WAIT, + AUTOIP_ARP_ADDRESS_USED, + AUTOIP_ARP_VERIFY_WAIT, + AUTOIP_ARP_VERIFY_PROBE, + AUTOIP_FAILED +} eAUTO_IP_STATE; + +/* "methods", or vairous modes of operation for the AutoIP code */ + +typedef enum +{ + eIP_METHOD_DHCP_AUTO_FIXED, /* Try DHCP then AuoIP */ + eIP_METHOD_DHCP_FIXED, /* Try DHCP */ + eIP_METHOD_AUTO_FIXED, /* Try AutoIP */ + eIP_METHOD_FIXED /* Used fixed (NV) address */ +} eIP_METHOD; + + +extern u_long dBASE_AUTO_IP_ADDRESS; /* base of auto-address pool */ +extern u_long dMAX_AUTO_IP_ADDRESS; +#define dAUTO_IP_RANGE (dMAX_AUTO_IP_ADDRESS - dBASE_AUTO_IP_ADDRESS) + +struct autoIP +{ + eAUTO_IP_STATE state; + u_long response_timer; + ip_addr try_address; + unshort arp_attempts; + unshort verify_attempts; +}; + +extern struct autoIP autoIPs[MAXNETS]; + +int AutoIp_init(void); +void AutoIp_tick(int iface); +int AutoIp_get_state(int iface); +void AutoIp_send_arp_probe(int iface); + +#endif /* AUTOIP_H */ + + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/ds_app.h b/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/ds_app.h new file mode 100644 index 0000000..35f73dc --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/ds_app.h @@ -0,0 +1,75 @@ +/* + * FILENAME: ds_app.h + * + * Copyright 2002 By InterNiche Technologies Inc. All rights reserved + * + * Definitions for sample AutoIP database. + * +*/ + +#ifndef _DS_APP_H_ +#define _DS_APP_H_ 1 + +/* If application programmer (user) has defined his own database then + * include his files inside the file "user_ds.h"; otherwise support + * our simple default system. + */ +#ifdef USER_DS_SUPPORT +#include "user_ds.h" +#else /* use simple local system */ + + +/* AutoIP database - one for each iface entry. */ + +struct ds_struct +{ + /* tag_IP_ADDRESS_MODE is one of the eIP_METHOD enums. + * If you don't want to use the default (auto IP), then + * set this value to some other enum prior to calling + * Upnp_init() + */ + unshort tag_IP_ADDRESS_MODE; + + /* the rest of these are set during the autoIP process. */ + u_char tag_POLLING_ENABLED; /* boolean */ + u_long tag_NET_FIXED_IP; + u_long tag_NET_FIXED_SUBNET; + u_long tag_NET_FIXED_GATEWAY; + u_long tag_NET_IP_ADDRESS; + u_long tag_NET_SUBNET; + u_long tag_NET_GATEWAY; + char tag_IP_ADDRESS_STRING[50]; +}; + +/* The database: */ +extern struct ds_struct ds_structs[MAXNETS]; + + +/* Access macros */ + +/* get routines set a value form the database. If the database + * entry is zero then the value is enchanged + */ + +#define DS_get_word(tag, iface, data) \ + { *(unshort*)(data) = (unshort)ds_structs[iface].tag; } + +#define DS_get_long(tag, iface, data) \ + { *(u_long*)(data) = ds_structs[iface].tag; } + + +/* Set routines set a value in the database */ + +#define DS_set_long(tag, iface, data) \ + ds_structs[iface].tag = data; + +#define DS_set_byte(tag, iface, data) \ + ds_structs[iface].tag = data; + +#define DS_set_string(tag, iface, data) \ + { strncpy(ds_structs[iface].tag, data, sizeof(ds_structs[iface].tag));} + +#endif /* USER_DS_SUPPORT */ +#endif /* _DS_APP_H_ */ + + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/upnp.c b/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/upnp.c new file mode 100644 index 0000000..3dcd7f4 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/upnp.c @@ -0,0 +1,651 @@ +/* + * FILENAME: upnp.c + * + * Copyright 2002 By InterNiche Technologies Inc. All rights reserved + * + * Universal plug and play + * + * This file has all the top level UPnP managment routines. + * It uses: + * - DHCP client for Addressing + * - AutoIP for Addressing + * - SSDP for discovery + * + * 9/15/2000 - Created - Stan Breitlow + * + * MODULE: AUTOIP4 + * + * ROUTINES: Upnp_init(), upnp_recv_dhcp_status(), upnp_tick(), + * ROUTINES: Play (), Upnp_tick(), upnp_set_fixed_net_vars(), + * ROUTINES: Upnp_GetDnsOptionsFromDhcpOptions(), + * ROUTINES: upnp_add_net_vars_to_database(), + * + * PORTABLE: yes + */ + + + +#include "ipport.h" + +#ifdef USE_UPNP + +#include "q.h" +#include "netbuf.h" +#include "net.h" +#include "ip.h" +#include "dhcpclnt.h" +#include "dns.h" +#include "dhcpclnt.h" +#include "intimers.h" + +#include "autoip.h" +#include "upnp.h" +#include "ds_app.h" + + +#ifndef USE_AUTOIP +#error USE_AUTOIP must be defined with USE_UPNP +#endif + +#ifdef INCLUDE_NVPARMS +#include "nvparms.h" /* For nvparms struct */ +#endif /* INCLUDE_NVPARMS */ + + +/* local objects */ + +struct tUPNP upnp[MAXNETS]; +long upnp_timer; +int DHCP_WAIT_TIME = 300; /* 30 seconds default */ + +#ifndef USER_DS_SUPPORT +struct ds_struct ds_structs[MAXNETS]; /* database */ +#endif + +/* local protos */ + +int upnp_recv_dhcp_status(int iface, int state); +static void upnp_set_fixed_net_vars(int iface); +static void upnp_add_net_vars_to_database(int iface); +static void Upnp_GetDnsOptionsFromDhcpOptions(void); +static void upnp_add_Fixed_vars_to_database(int iface); + +extern void fixup_subnet_mask(int); + +#ifdef IN_MENUS +#include "menu.h" +extern struct menu_op upnpmenu[5]; +#endif /* IN_MENUS */ + +/* default method of getting IP address */ +eIP_METHOD addressing_method = eIP_METHOD_DHCP_AUTO_FIXED; + + +/* FUNCTION: Upnp_init() + * + * Initialize the sub modules + * + * PARAM1: void + * + * RETURNS: + */ + +int Upnp_init(void) +{ + int i; + int e; + struct tUPNP * up; + + e = AutoIp_init(); + if (e) + { + dtrap(); + } + + for (i = 0; i < MAXNETS; i++) + { + up = &upnp[i]; + + /* Disable Auto-IP on unset nets. If a dynamic interface wants this later, + * the creator will have to explicitly enable it. + */ + if(nets[i] == NULL) + { + up->state = UPNP_DISABLED; + continue; + } + + /* Only do this on ethernets */ + if(nets[i]->n_mib->ifType != ETHERNET) + continue; + + /* nets[] should already have info set from NV parms system or + * by other means. Save this info to the "UPnP database items now. + */ + upnp_add_Fixed_vars_to_database(i); /* set fixed info */ + upnp_add_net_vars_to_database(i); /* set tmp info */ + +#ifdef INCLUDE_NVPARMS + /* Skip interfaces which are not flagged to be DHCP clients */ + if (inet_nvparms.ifs[i].client_dhcp) /* is DHCP Client enabled ? */ + nets[i]->n_flags |= NF_AUTOIP; /* yes, then use AUTOIP too */ +#endif /* INCLUDE_NVPARMS */ + + if (!(nets[i]->n_flags & NF_AUTOIP)) + { + up->state = UPNP_DISABLED; + continue; + } + + up->state = UPNP_START; + up->idle_timer = 0 ; + up->notify_delay = 0; + up->notify_count = 0; + up->got_dhcp_address = FALSE; + + dhc_set_callback(i, upnp_recv_dhcp_status ); + + /* Check parameter database for IP setting */ + DS_get_word(tag_IP_ADDRESS_MODE, i, &addressing_method); + up->ip_method = addressing_method; + } + +#ifdef IN_MENUS + install_menu(&upnpmenu[0]); + install_version("autoip3.1"); +#endif /* IN_MENUS */ + +#ifdef USER_SMTP_ALERTS + /* If "user smtp" service is supported, do the init now. */ + UserSmtp_init(); +#endif + + /* start the AutoIP interval timer */ + upnp_timer = in_timerset(Upnp_tick, 100, 0L ); + if(upnp_timer == 0) + return -1; + + return 0; +} + + + +/* FUNCTION: upnp_recv_dhcp_status() + * + * Callback that receives status changes from the dhcp client. + * + * PARAM1: int iface + * PARAM2: int state + * + * RETURNS: + */ + +int upnp_recv_dhcp_status(int iface, int state) +{ + struct tUPNP * up; + + up = &upnp[iface]; + + switch (state) + { + case DHCS_UNUSED: /* no discovery attempted */ + case DHCS_INIT: /* Ready to send a DISCOVER packet */ + case DHCS_INITREBOOT: /* Have IP, ready to send REQUEST(skip DISCOVER) */ + case DHCS_REBOOTING: /* rebooting/reclaiming address */ + case DHCS_SELECTING: /* discovery sent, but no offer yet */ + case DHCS_REQUESTING: /* sent request; waiting for ACK|NAK */ + case DHCS_RENEWING: /* Renewing the lease */ + case DHCS_REBINDING: /* rebinding to new server */ + case DHCS_RESTARTING: + break; + + /* got a ACK we liked */ + case DHCS_BOUND: + up->got_dhcp_address = TRUE; + dhc_main_ipset(iface, state); + break; + } + + return(0); +} + + +/* FUNCTION: upnp_tick() + * + * Called every 100ms to run finite state machine. + * Manages the Address and Discover phases of AutoIP + * + * PARAM1: void + * + * RETURNS: void + */ + +u_long last_upnptick; + +void +Upnp_tick(long dummy) +{ + int iface; + struct tUPNP * up; + int timerlag; + + /* if we missed a long interval, derive a value to update the timer */ + if((cticks - last_upnptick) > (TPS/10)) + { + /* approx. number of 100ms intervals we missed. The "|10" + * on TPS is to prevent a divide by zero if TPS < 10 . + */ + timerlag = (cticks - last_upnptick)/((TPS|10)/10); + } + else + timerlag = 0; + + last_upnptick = cticks; + + for(iface = 0; iface < MAXNETS; iface++) + { + /* first blank net means we're done with loop */ + if(nets[iface] == NULL) + return; + + up = &upnp[iface]; + + if(!up) /* iface is not doing Auot IP, skip it. */ + continue; + + /* update timers if we had a long break */ + if(timerlag) + up->idle_timer += timerlag; + + switch (up->state) + { + + /*-------------------------------------------------------- */ + /* Let things settle before starting */ + /*-------------------------------------------------------- */ + + case UPNP_START: + + up->state = UPNP_INIT; + break; + + /*-------------------------------------------------------- */ + /* Determine where to start the sequence. */ + /* If the device is configured to use only fixed IP */ + /* we will skip dhcp and AutoIP */ + /*-------------------------------------------------------- */ + + case UPNP_INIT: + + /* Use configured IP addressing method */ + switch (up->ip_method) + { + default: + case eIP_METHOD_DHCP_AUTO_FIXED: + case eIP_METHOD_DHCP_FIXED: + + up->state = UPNP_DHCP_SEEK; + break; + + case eIP_METHOD_AUTO_FIXED: + + up->state = UPNP_AUTO_IP; + /* turn off dhcp, otherwise it will reset */ + dhc_halt(iface); + break; + + case eIP_METHOD_FIXED: + + up->state = UPNP_FIXED_IP; + /* turn off dhcp, otherwise it will reset */ + dhc_halt(iface); + break; + } + up->idle_timer = 0; + break; + + /*-------------------------------------------------------- */ + /* We are waiting for the dhcp server to give us an address. */ + /* We only wait so long before timing out. */ + /*-------------------------------------------------------- */ + + case UPNP_DHCP_SEEK: + + if (up->got_dhcp_address) + { + up->state = UPNP_GOT_DHCP_ADDRESS; + break; + } + + /* If dhcp dos not resolve after a while */ + /* try auto IP if it is allowed by the configuration */ + up->idle_timer++; + if (up->idle_timer >= (unsigned)DHCP_WAIT_TIME) + { + /* What is the next phase */ + if (up->ip_method == eIP_METHOD_DHCP_AUTO_FIXED) + up->state = UPNP_AUTO_IP; + else + up->state = UPNP_FIXED_IP; + /* turn off dhcp, otherwise it will reset */ + dhc_halt(iface); + } + break; + + /*-------------------------------------------------------- */ + /* We go to this state if the dhcp client gets an address */ + /* Set the active IP address to the found address */ + /*-------------------------------------------------------- */ + + case UPNP_GOT_DHCP_ADDRESS: + + /* put info in the database */ + upnp_add_net_vars_to_database(iface); + /* Start the discovery phase */ + /* up->state = UPNP_SSDP_NOTIFY; */ + Upnp_GetDnsOptionsFromDhcpOptions(); + up->state = UPNP_STARTUP_FINISHED; + break; + + /*-------------------------------------------------------- */ + /* If we did not get an address from a dhcp server */ + /* We will try to get an IP address via AutoIP, */ + /* this involve ARP probing. */ + /*-------------------------------------------------------- */ + + case UPNP_AUTO_IP: + + AutoIp_tick(iface); + switch (AutoIp_get_state(iface)) + { + case AUTOIP_GOT_ADDRESS: /* put info in the database */ + upnp_add_net_vars_to_database(iface); + /*up->state = UPNP_SSDP_NOTIFY; */ + up->state = UPNP_STARTUP_FINISHED; + break; + case AUTOIP_FAILED: + up->state = UPNP_FIXED_IP; + break; + default: + break; + } + break; + + /*-------------------------------------------------------- */ + /* Use a hardcoded IP address */ + /*-------------------------------------------------------- */ + + case UPNP_FIXED_IP: + /* Get the fix IP info back from the database */ + upnp_set_fixed_net_vars(iface); + + /* If the fixed IP address is zero, take down the iface (for now) */ + nets[iface]->n_mib->ifOperStatus = NI_DOWN; + + /* put info in the database */ + upnp_add_net_vars_to_database(iface); + DS_set_byte(tag_POLLING_ENABLED, iface, 1); + +#ifdef USER_SMTP_ALERTS + /* If "user smtp" service is supported, do the init now. */ + UserSmtp_LookupStart(); +#endif + switch (up->ip_method) + { + case eIP_METHOD_DHCP_AUTO_FIXED: + case eIP_METHOD_DHCP_FIXED: + default: + up->state = UPNP_IDLE; + break; + + /* This one will not look for a DHCP in the future */ + case eIP_METHOD_FIXED: + up->state = UPNP_IDLE_FIXED; + break; + } + break; + + /*-------------------------------------------------------- */ + /* Tell the network about ourselves. */ + /* Do this several times 1 second apart. */ + /* This is recommended by the UPNP spec */ + /*-------------------------------------------------------- */ + + case UPNP_SSDP_NOTIFY: + + /* not using ssdp currently */ + up->state = UPNP_STARTUP_FINISHED; + + /*ssdp_notify(iface); */ + up->notify_delay = 0; + up->state = UPNP_SSDP_WAIT; + break; + + /*-------------------------------------------------------- */ + /* Wait after advertising */ + /*-------------------------------------------------------- */ + + case UPNP_SSDP_WAIT: + + if (++up->notify_delay > SSDP_NOTIFY_DELAY) + { + if (++up->notify_count > SSDP_NOTIFY_COUNT) + up->state = UPNP_SSDP_DISCOVER; + else + up->state = UPNP_SSDP_NOTIFY; + } + break; + + /*-------------------------------------------------------- */ + /* Look for the other devices we need */ + /*-------------------------------------------------------- */ + + case UPNP_SSDP_DISCOVER: + + /* skip anything here for now */ + up->state = UPNP_STARTUP_FINISHED; + break; + + /*-------------------------------------------------------- */ + /* The startup phase is complete */ + /* Let the system know it can "do its thing" */ + /*-------------------------------------------------------- */ + + case UPNP_STARTUP_FINISHED: + + DS_set_byte(tag_POLLING_ENABLED, iface, 1); + up->state = UPNP_IDLE; + up->idle_timer = 0; +#ifdef USER_SMTP_ALERTS + UserSmtp_LookupStart(); +#endif + break; + + /*-------------------------------------------------------- */ + /* Spin here until its time to do monitoring and checkup stuff */ + /*-------------------------------------------------------- */ + + case UPNP_IDLE: + + up->idle_timer++; + if (up->idle_timer >= CHECKUP_TIME) + { + /* don't recheck if we have a dhcp address already */ + if (up->got_dhcp_address == FALSE) + { + up->state = UPNP_DHCP_CHECKUP; + } + /* Mark net as up so we can try again */ + nets[iface]->n_mib->ifOperStatus = NI_UP; + up->idle_timer = 0; + } + break; + + /*-------------------------------------------------------- */ + /* Here we stay as fixed IP */ + /*-------------------------------------------------------- */ + + case UPNP_IDLE_FIXED: + break; + + /*-------------------------------------------------------- */ + /* Check for a dhcp that might have come on-line */ + /*-------------------------------------------------------- */ + + case UPNP_DHCP_CHECKUP: + + /* start dhcp again */ + dhc_state_init(iface, TRUE); + dhc_set_callback(iface, upnp_recv_dhcp_status ); + up->state = UPNP_DHCP_RESEEK; + up->idle_timer = 0; + break; + + /*-------------------------------------------------------- */ + /* We are in AutoIP mode or DHCP Failed->Fixed mode */ + /* let's looking for a dhcp server again */ + /*-------------------------------------------------------- */ + + case UPNP_DHCP_RESEEK: + + if (up->got_dhcp_address) + { + up->state = UPNP_GOT_DHCP_ADDRESS; + break; + } + + /* If dhcp dos not resolve after a while return to idle */ + up->idle_timer++; + if (up->idle_timer >= (unsigned)DHCP_WAIT_TIME) + { + /* Nothing found, back to idle */ + up->state = UPNP_IDLE; + /* turn off dhcp, otherwise it will reset */ + dhc_halt(iface); + } + break; + + case UPNP_DISABLED: + break; + + default: + dtrap(); + break; + } /* switch */ + } /* for */ + +#ifdef USER_SMTP_ALERTS + UserSmtp_Tick(); +#endif + + USE_ARG(dummy); +} + + + +/* FUNCTION: upnp_set_fixed_net_vars() + * + * PARAM1: int iface + * + * RETURNS: + */ + +static void +upnp_set_fixed_net_vars(int iface) +{ + NET ifp; + + ifp = nets[iface]; + + /* Get the fixed IP address info out of database */ + DS_get_long(tag_NET_FIXED_IP, iface, &ifp->n_ipaddr); + DS_get_long(tag_NET_FIXED_SUBNET, iface, &ifp->snmask); + DS_get_long(tag_NET_FIXED_GATEWAY, iface, &ifp->n_defgw); + + if ( ifp->snmask == 0 ) + { + fixup_subnet_mask(iface); + dhc_states[iface].snmask = ifp->snmask; + } + + /* fixup broadcast addresses */ + ifp->n_netbr = ifp->n_ipaddr | ~ifp->snmask; + ifp->n_netbr42 = ifp->n_ipaddr & ifp->snmask; + ifp->n_subnetbr = ifp->n_ipaddr | ~ifp->snmask; + +} + + +/* FUNCTION: Upnp_GetDnsOptionsFromDhcpOptions() + * + * PARAM1: void + * + * RETURNS: + */ + +void +Upnp_GetDnsOptionsFromDhcpOptions(void) +{ +#ifdef DNS_CLIENT + int i; + int iface; + + iface = 0; + i=0; + while ((i < DHC_MAXDNSRVS) && (i < MAXDNSSERVERS)) + { + dns_servers[i] = dhc_states[iface].dnsrv[i]; + i++; + } +#endif /* DNS_CLIENT */ +} + + +/* FUNCTION: upnp_add_net_vars_to_database() + * + * PARAM1: int iface + * + * RETURNS: + */ + +static void +upnp_add_net_vars_to_database(int iface) +{ + char buf[32]; + NET ifp; + + ifp = nets[iface]; + + /* Put this info in the database */ + DS_set_long(tag_NET_IP_ADDRESS, iface, ifp->n_ipaddr); + DS_set_long(tag_NET_SUBNET, iface, ifp->snmask); + DS_set_long(tag_NET_GATEWAY, iface, ifp->n_defgw); + + sprintf(buf,"%u.%u.%u.%u\0", PUSH_IPADDR(ifp->n_ipaddr)); + DS_set_string(tag_IP_ADDRESS_STRING, iface, buf); +} + + +/* FUNCTION: upnp_add_net_vars_to_database() + * + * PARAM1: int iface + * + * RETURNS: + */ + +static void +upnp_add_Fixed_vars_to_database(int iface) +{ + NET ifp; + + ifp = nets[iface]; + + /* Put this info in the database */ + DS_set_long(tag_NET_FIXED_IP, iface, ifp->n_ipaddr); + DS_set_long(tag_NET_FIXED_SUBNET, iface, ifp->snmask); + DS_set_long(tag_NET_FIXED_GATEWAY, iface, ifp->n_defgw); +} + +#endif /* USE_UPNP */ + + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/upnp.h b/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/upnp.h new file mode 100644 index 0000000..b13d063 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/upnp.h @@ -0,0 +1,61 @@ +/* UPNP.h + + Universal plug and play + + 9/15/2000 - Created - Stan Breitlow + +*/ + +#ifndef UPNP_H +#define UPNP_H + +/* How long to wait for a DHCP address */ +extern int DHCP_WAIT_TIME; + + +#define SSDP_NOTIFY_DELAY 10 /* 1 second */ +#define SSDP_NOTIFY_COUNT 3 /* 3 times */ +#define SECONDS_PER_MINUTE 60 +#define TICKS_PER_SECOND 10 +#define CHECKUP_TIME 5*SECONDS_PER_MINUTE*TICKS_PER_SECOND /* 5 minutes */ + +typedef enum +{ + UPNP_START, + UPNP_INIT, + UPNP_DHCP_SEEK, + UPNP_GOT_DHCP_ADDRESS, + UPNP_AUTO_IP, + UPNP_FIXED_IP, + UPNP_SSDP_NOTIFY, + UPNP_SSDP_WAIT, + UPNP_SSDP_DISCOVER, + UPNP_STARTUP_FINISHED, + UPNP_IDLE, + UPNP_IDLE_FIXED, + UPNP_DHCP_CHECKUP, + UPNP_DHCP_RESEEK, + UPNP_DISABLED +} eUPNP_STATE; + + +struct tUPNP +{ + eUPNP_STATE state; + eIP_METHOD ip_method; + int got_dhcp_address; /* boolean */ + u_long idle_timer; + u_long notify_delay; + u_long notify_count; + int local_iface; +}; + +extern struct tUPNP upnp[MAXNETS]; + + +int Upnp_init(void); +void Upnp_tick(long); + +#endif /* UPNP_H */ + + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/upnpmenu.c b/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/upnpmenu.c new file mode 100644 index 0000000..4f023e6 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/upnpmenu.c @@ -0,0 +1,266 @@ +/* + * FILENAME: upnpmenu.c + * + * Copyright 2002 By InterNiche Technologies Inc. All rights reserved + * + * Universal plug and play menu stats & control user interface + * + * ROUTINES: upnp_stats(), upnp_disable(), upnp_restart(), + * ROUTINES: upnp_base(), + * + * + * MODULE: AUTOIP4 + * + * ROUTINES: + * + * PORTABLE: yes + */ + + + +#include "ipport.h" + +#ifdef USE_UPNP +#ifdef IN_MENUS + +#include "q.h" +#include "netbuf.h" +#include "net.h" +#include "menu.h" + +#include "autoip.h" +#include "upnp.h" +#include "ds_app.h" + +/* routine in ..\ip to get NET pointer from console text */ +extern NET if_netbytext(void * pio, char * cp); + +/* UPnP menu routines */ +int upnp_stats(void * pio); +int upnp_disable(void * pio); +int upnp_restart(void * pio); +int upnp_base(void * pio); +int upnp_db(void * pio); + +char * upnp_states[] = /* match eUPNP_STATE enums to text */ +{ + "START", + "INIT", + "DHCP_SEEK", + "GOT_DHCP_ADDRESS", + "AUTO_IP", + "FIXED_IP", + "SSDP_NOTIFY", + "SSDP_WAIT", + "SSDP_DISCOVER", + "STARTUP_FINISHED", + "IDLE", + "IDLE_FIXED", + "DHCP_CHECKUP", + "DHCP_RESEEK", + "DISABLED", +}; + + +struct menu_op upnpmenu[] = +{ + "upnp", stooges, "Upnp menu", + "upstats", upnp_stats, "status of UPnP Interfaces", + "updisable", upnp_disable, "disable UPnP on an interface", + "uprestart", upnp_restart, "restart UPnP process on interface", + "upbase", upnp_base, "Set new base for UPnP address pool", + "updbase", upnp_db, "Dump UPnP database for interface", + NULL, +}; + + + +/* FUNCTION: upnp_stats() + * + * Basic status dump menu routine + * + * PARAM1: void * pio + * + * RETURNS: 0 if OK, Else ENP_ error code + */ + +int +upnp_stats(void * pio) +{ + int i; + + ns_printf(pio, "UPnP stats:\n"); + + for(i = 0; i < MAXNETS; i++) + { + if(nets[i] == NULL) + break; + ns_printf(pio, "iface %s; state:%s; current IP:%u.%u.%u.%u\n", + nets[i]->name, upnp_states[upnp[i].state], + PUSH_IPADDR(nets[i]->n_ipaddr)); + } + + return 0; +} + + +/* FUNCTION: upnp_disable() + * + * Menu routine to disable UPnP on a specified interface + * + * PARAM1: void * pio + * + * RETURNS: 0 if OK, Else ENP_ error code + */ + +int +upnp_disable(void * pio) +{ + char * cp; + NET ifp; + int iface; + + cp = nextarg( ((GEN_IO)pio)->inbuf ); + if(!*cp) + { + ns_printf(pio, "please enter iface to disable UPnP\n"); + return -1; + } + ifp = if_netbytext(pio, cp); + if(ifp == NULL) /* error parsing iface name/number text? */ + return -1; + iface = if_netnumber(ifp); + upnp[iface].state = UPNP_DISABLED; + ns_printf(pio, "Disabled UPnP in iface %s\n", ifp->name); + return 0; +} + + +/* FUNCTION: upnp_restart() + * + * Menu routine to restart the Auto-Ip process on the specified interface + * + * PARAM1: void * pio + * + * RETURNS: 0 if OK, Else ENP_ error code + */ + +int +upnp_restart(void * pio) +{ + char * cp; + NET ifp; + int iface; + + cp = nextarg( ((GEN_IO)pio)->inbuf ); + if(!*cp) + { + ns_printf(pio, "please enter iface to restart UPnP\n"); + return -1; + } + ifp = if_netbytext(pio, cp); + if(ifp == NULL) /* error parsing iface name/number text? */ + return -1; + iface = if_netnumber(ifp); + + /* skip the DHCP step and go right to autoIP */ + upnp[iface].state = UPNP_START; + upnp[iface].ip_method = eIP_METHOD_AUTO_FIXED; + autoIPs[iface].state = AUTOIP_START; + autoIPs[iface].response_timer = 0; + autoIPs[iface].arp_attempts = 0; + + ns_printf(pio, "(re)started UPnP in iface %s\n", ifp->name); + return 0; +} + + +/* FUNCTION: upnp_base() + * + * Menu routine to change the address pool used by Auto IP + * + * PARAM1: void * pio + * + * RETURNS: 0 if OK, Else ENP_ error code + */ + +int +upnp_base(void * pio) +{ + char * cp; + u_long newbase; + u_long oldrange; + unsigned mask; + + cp = nextarg( ((GEN_IO)pio)->inbuf ); + if(!*cp) + { + ns_printf(pio, "please enter IP address for new base\n"); + return -1; + } + + cp = parse_ipad(&newbase, &mask, cp); + if(cp) + { + ns_printf(pio, "Bad IP address: %s\n", cp); + return -1; + } + + oldrange = dAUTO_IP_RANGE; + dBASE_AUTO_IP_ADDRESS = htonl(newbase); /* store in local endian */ + dMAX_AUTO_IP_ADDRESS = htonl(newbase + oldrange); + + ns_printf(pio, "Changed base of Auto-IP address pool to %u.%u.%u.%u\n", + PUSH_IPADDR(newbase) ); + + return 0; +} + +int +upnp_db(void * pio) +{ + char * cp; + NET ifp; + int iface; + ip_addr addr; + ip_addr mask; + ip_addr gateway; + + cp = nextarg( ((GEN_IO)pio)->inbuf ); + if(!*cp) + { + ns_printf(pio, "please enter iface for database dump\n"); + return -1; + } + ifp = if_netbytext(pio, cp); + if(ifp == NULL) /* error parsing iface name/number text? */ + return -1; + iface = if_netnumber(ifp); + + /* Get the fixed IP info from database into tmp vars */ + DS_get_long(tag_NET_FIXED_IP, iface, &addr); + DS_get_long(tag_NET_FIXED_SUBNET, iface, &mask); + DS_get_long(tag_NET_FIXED_GATEWAY, iface, &gateway); + + ns_printf(pio, "iface:%s; ", ifp->name); + ns_printf(pio, " Fixed IP: %u.%u.%u.%u", PUSH_IPADDR(addr) ); + ns_printf(pio, " mask: %u.%u.%u.%u", PUSH_IPADDR(mask) ); + ns_printf(pio, " gateway: %u.%u.%u.%u\n", PUSH_IPADDR(gateway) ); + + /* Get the current IP info from database into tmp vars */ + DS_get_long(tag_NET_IP_ADDRESS, iface, &addr); + DS_get_long(tag_NET_SUBNET, iface, &mask); + DS_get_long(tag_NET_GATEWAY, iface, &gateway); + + ns_printf(pio, "Current ip: %u.%u.%u.%u", PUSH_IPADDR(addr)); + ns_printf(pio, " mask: %u.%u.%u.%u", PUSH_IPADDR(mask)); + ns_printf(pio, " gateway: %u.%u.%u.%u\n", PUSH_IPADDR(gateway)); + + return 0; +} + + +#endif /* IN_MENUS */ +#endif /* USE_UPNP */ + + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpclnt.c b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpclnt.c new file mode 100644 index 0000000..f94f956 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpclnt.c @@ -0,0 +1,2424 @@ +/* + * FILENAME: ftpclnt.c + * + * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved + * + * + * MODULE: FTPCLIENT + * + * ROUTINES: fc_check(), fc_getreply(), fc_checklogin(), + * ROUTINES: fc_checkcmd(), fc_endxfer(), fc_clearf(), fc_sendmore(), + * ROUTINES: fc_getmore(), fc_dataconn(), fc_killsess(), fc_connect(), + * ROUTINES: fc_get(), fc_put(), fc_connopen(), fc_senduser(), fc_sendpass(), + * ROUTINES: fc_sendport(), fc_sendcmd(), fc_dir(), fc_pwd(), fc_chdir(), + * ROUTINES: fc_settype(), fc_quit(), fc_ready(), fc_usercmd(), + * ROUTINES: fc_hashmark(), fc_state(), fc_pasv(), + * + * PORTABLE: yes + */ + +/* ftpclnt.c Generic FTP client. This file contains the guts of the + * FTP client logic. There are several entry poins for user commands, + * include connect, send, and recv. These initiate a change in the + * connection's state machine which is should result in the + * performance of the desired task. These jobs are driven by periodic + * calls to fc_check, which can be made from a super loop, or a task + * which sleeps on ftp_clients == NULL. + * 1/12/97 - Created. John Bartas + */ + +#include "ftpport.h" /* TCP/IP, sockets, system info */ + +#ifdef FTP_CLIENT +#include "ftpsrv.h" +#include "ftpclnt.h" + +#ifdef IP_V6 +#include "socket6.h" +#endif /* IP_V6 */ + + +/* operating parmeters which may be overwritten by application code + * 1. If the FTP Client sends any FTP command, and it doesn't receive + * a reply for fc_replytmo seconds, then the FTP Client connection is + * closed. + * 2. If the FTP Client connection has remained idle ( no + * commands sent ) for fc_activity_tmo seconds, then the FTP Client + * connection is closed + */ +int fc_replytmo = 20; /* secs of inactivity for cmd timeout */ +int fc_connect_tmo = 300; /* secs of inactivity for connect timeout */ +int fc_activity_tmo = 1200; /* ftp client's inactivity timeout (secs) */ + +/* Starting port number for data transfers of ftp client */ +#define FTP_START_DATA_PORT 8000 /* Refered RFC1700 Assigned nums */ + +static unshort fc_next_port=FTP_START_DATA_PORT ; + +/* The FTP client's per-port message handler */ +extern void fc_printf(ftpc *, char *, ...); /* per-port response printer */ + +/* internal routines */ +int fc_connopen(ftpc * ftpconn); /* initiate command connection */ +int fc_getreply(ftpc * ftpconn, int * code); /* check for ftpconn reply */ +int fc_dataconn(ftpc * ftpconn); /* initiate data connection */ +int fc_checklogin(ftpc * ftpconn);/* see if user login is complete */ +int fc_checkcmd(ftpc * ftpconn); /* see if last cmd is complete */ +int fc_sendmore(ftpc * ftpconn); /* send more data on a STOR command */ +int fc_getmore(ftpc * ftpconn); /* send more data on a RETR command */ +int fc_senduser(ftpc * ftpconn); +int fc_sendpass(ftpc * ftpconn); +int fc_sendport(ftpc * ftpconn); +int fc_usercmd(ftpc * ftpconn, int cmdcode, char * cmdarg); +int fc_sendcmd(ftpc * ftpconn); +int fc_ready(ftpc * ftpconn); /* test session readiness for command */ +void fc_hashmark(ftpc * ftpconn, ulong before, unsigned added); +void fc_killsess(ftpc * ftpconn); /* clean up ftpconn resources */ +void fc_clearf(ftpc * ftpconn); /* reset ftpconn counters */ +void fc_endxfer(ftpc * ftpconn); /* end data xfer */ + +#ifdef FC_LOG +GEN_IO ftplog =NULL; /* By default log o/p would goto std output */ +int log_flag=FALSE; /* By default, logging is disabled */ +/* Text strings for logstate and cmdstate. Update this if any change + is done to the states */ +char * fc_str[]= { + "0", + "FCL_CONNECTING", /* 1 */ + "FCL_CONNECTED", /* 2 */ + "FCL_READY", /* 3 */ + "FCL_SENTUSER", /* 4 */ + "FCL_SENTPASS", /* 5 */ + "FCL_LOGGEDIN", /* 6 */ + "FCL_PENDING", /* 7 */ + "FCL_CLOSING", /* 8 */ + "9", + "FCC_RECVPORT", /* 10*/ + "FCC_RECVOK", /* 11*/ + "FCC_RECVCONN", /* 12*/ + "FCC_RECEIVING", /* 13*/ + "FCC_RECVDONE", /* 14*/ + "15", + "16", + "17", + "18", + "19", + "FCC_SENDPORT", /* 20*/ + "FCC_SENDOK", /* 21*/ + "FCC_SENDCONN", /* 22*/ + "FCC_SENDING", /* 23*/ + "FCC_SENDDONE", /* 24*/ + "25", + "26", + "27", + "28", + "29", + "FCC_NLSTPORT", /* 30*/ + "FCC_NLSTOK", /* 31*/ + "FCC_NLSTCONN", /* 32*/ + "FCC_NLSTING", /* 33*/ + "FCC_NLSTDONE", /* 34*/ + "35" +}; + +#define FC_CBLOG(fc) { \ + if (log_flag==TRUE) \ + log_printf(ftplog,"logstate=%s,cmdstate=%s\n",\ + fc_str[fc->logstate],fc_str[fc->cmdstate]); \ + } +#else /* FC_LOG */ +#define FC_CBLOG(fc) ; +#endif /* FC_LOG */ + +/* Define FC_CBACK if FC_USECALLBACK is enabled */ + +#ifdef FC_USECALLBACK +void (*fc_callback)(void * fc, int logstate, int cmdstate) = NULL ; +#define FC_CBACK(fc) {if(fc_callback) \ + (*fc_callback)((void *)fc,fc->logstate,fc->cmdstate);} +#else +#define FC_CBACK(fc) ; +#endif /* FC_USECALLBACK */ + +/* The user application can set a callback via fc_callback to receive + * information when the logstate or cmdstate changes This feature is + * available only when FC_USECALLBACK in enabled in ftpclnt.h If + * FC_LOG is enabled, then the change of state is also logged. If + * FC_USEBCALLBACK and FC_LOG are both disabled, FC_CALLBACK will + * evaluate to empty braces. + */ +#define FC_CALLBACK(fc) { \ + FC_CBACK(fc); \ + FC_CBLOG(fc); \ + } + +/* FC_SETLOGSTATE updates the logstate of ftpcon and calls + * FC_CALLBACK. Hence, if FC_CALLBACK(fc) is {}, it evaluates to a + * simple C assignment and there is no extra code. + */ +#define FC_SETLOGSTATE(fc,lstate) { fc->logstate=lstate; FC_CALLBACK(fc); } + +struct ftpc * ftp_clients = NULL ; /* support multiple client links */ + +struct queue ftpcq; /* contains messages from other tasks */ +unsigned char ftpc_msgsize [FTPC_NUM_MSGS] = {0x10, 0x0C, 0x0C, 0x0C, 0x00, 0x20, 0x0C, 0x10, 0x0C, 0x0C, 0x0C, 0x00, 0x08}; +struct ftpc_msg_stats ftpc_msg_stats; +struct ftpc_err ftpc_err; +extern struct ftpc * ftp_get_con(void * pio); + +#define FC_MENULOG() ; + + +/* FUNCTION: fc_check() + * + * fc_check() - poll ftp clients for work. This does not need to be + * called if(ftp_clients == NULL), else it should be called + * periodicly to move FTP transactions. + * + * PARAM1: void + * + * RETURNS: 0 if there are not more conenctions open, + * 1 if there are connections but no IO in progress, + * 2 if the is at least 1 file transfer going + */ + +int +fc_check(void) +{ + ftpc * ftpconn; + ftpc * ftpc_next; + int e; /* generic error holder */ + int retval = 0; + + /* loop through active client list */ + for (ftpconn = ftp_clients; ftpconn; ftpconn = ftpc_next) + { + ftpc_next = ftpconn->next; + if (ftpconn->in_use) /* make sure we're not being re-entered */ + continue; + ftpconn->in_use++; /* set re-entry flag */ + + e = 0; /* clear error before each connection */ + switch (ftpconn->logstate) + { + case FCL_CONNECTING: + case FCL_CONNECTED: + /* see if we timed out on non-blocking connect() */ + if ((ftpconn->last_cmd + ((unsigned long)fc_connect_tmo * TPS)) < ftp_ticks) + { + fc_printf(ftpconn, + "FTP Connection timed out on non-blocking connect.\n"); + e = -1; + } + else + { + e = fc_connopen(ftpconn); /* keep polling until state goes READY */ + } + break; + case FCL_SENTUSER: /* check for reply to USER or PASS cmd */ + case FCL_SENTPASS: + e = fc_checklogin(ftpconn); + if (ftpconn->logstate == FCL_LOGGEDIN) + fc_printf(ftpconn, "ftp user \"%s\" logged in.\n", ftpconn->username); + break; + case FCL_READY: /* connected & ready, but not doing login */ + if ((ftpconn->last_cmd + ((unsigned long)fc_activity_tmo*TPS)) < ftp_ticks) + { + fc_printf(ftpconn, + "FTP Connection timed out : No activity for %d secs\n", + fc_activity_tmo); + e=-1; + } + break; + case FCL_LOGGEDIN: /* nothing to do here */ + if ((ftpconn->last_cmd + ((unsigned long)fc_activity_tmo*TPS)) < ftp_ticks) + { + fc_printf(ftpconn, + "FTP Connection timed out : No activity for %d secs\n", + fc_activity_tmo); + e=-1; + } + break; + case FCL_PENDING: /* command in progress */ + e = fc_checkcmd(ftpconn); /* push command to next state */ + break; + case FCL_CLOSING: /* close FTP connection */ + e = -1; /* mark for deletion */ + break; + default: + e = -1; /* mark for deletion */ + break; + } + ftpconn->in_use--; /* clear re-entry flag */ + + if (ftpconn->logstate == FCL_PENDING) + retval = 2; /* At least 1 connection has transaction in progress */ + + /* delete any terminating connections */ + if (e) + { +#ifdef FC_LOG + if (log_flag == TRUE) + { + ftpconn->in_use++; /* set re-entry flag */ + log_printf(ftplog,"Closing FTP client connection.\n"); + ftpconn->in_use--; /* clear re-entry flag */ + } +#endif + ftpc_next = ftpconn->next; /* maintain pointer to next */ + fc_killsess(ftpconn); + } + } + if((retval == 0) && (ftp_clients)) + retval = 1; /* at least one connection open */ + return retval; +} + + + + +/* FUNCTION: fc_getreply() + * + * fc_getreply() - check for a reply to and outstanding command. + * Performs state machine actions if reply is ready. Does not handle + * timeouts. + * + * PARAM1: ftpc * ftpconn + * PARAM2: int * replycode + * + * RETURNS: Returns: 0 if we have full command, -1 if error, 1 if no + * reply yet. + */ + +int +fc_getreply(ftpc * ftpconn, int * replycode) +{ + int e; /* error holder */ + int current; /* cuurent cmd text length */ + char * beginLine; + char * endLine; + char * cp; + int rc = 1; + + current = strlen(ftpconn->cmdbuf); + e = t_recv(ftpconn->cmd_sock, ftpconn->cmdbuf + current, + CMDBUFSIZE - current, 0); + if (e < 0) /* read error ? */ + { + e = t_errno(ftpconn->cmd_sock); + if (e == EWOULDBLOCK) + { + /* If some reply info is left in buffer from a previous read, + * return code to this affect + */ + if(ftpconn->cmdbuf[0] == 0) + return 1; /* wait some more */ + } + else + { + fc_printf(ftpconn, "ftp client read error %d\n", e); + return -1; + } + } + else if (e == 0) /* socket closed by server */ + { + fc_printf(ftpconn, "ftp connection closed by server\n"); + return -1; + } + + /* add bytes read on last t_recv() to total bytes in buffer */ + current += e; + /* null terminate after length of buffer */ + ftpconn->cmdbuf[current] = 0; + beginLine = ftpconn->cmdbuf; + for (;;) + { + /* find CRLF at end of command buffer */ + endLine = strstr(beginLine, "\r\n"); + /* not a complete line yet so break and return no reply yet */ + if (!endLine) + break; + + /* scan reply code from decimal digits at beginning of line */ + cp = beginLine; + *replycode = 0; + while ((*cp >= '0') && (*cp <= '9')) + { + *replycode = (*replycode * 10) + *cp - '0'; + cp++; + } + + /* if the character following the digits is not a dash + * continuation character (see section 4.2 of RFC 959) and + * three digits were read + */ + if ((*cp != '-') && (cp == beginLine + 3)) + { + if (ftpconn->options & FCO_VERB) + fc_printf(ftpconn, "ftp reply: %s", ftpconn->cmdbuf); + if (*replycode == 421) + { + fc_printf(ftpconn, "ftp closing session per code 421\n"); + rc = -1; + } + else + rc = 0; /* command is ready */ + break; + } + /* we didn't see a complete reply so try starting at the + beginning of the next line */ + beginLine = endLine + 2; + } + return rc; +} + + + +/* FUNCTION: fc_checklogin() + * + * fc_checklogin() - Check for a reply to an outstanding USER or PASS + * command. Handle state changes if reply has arrived, do timeouts. + * + * PARAM1: ftpc * ftpconn + * + * RETURNS: Returns 0 if OK (including no reply), if error returns -1. + */ + +int +fc_checklogin(ftpc * ftpconn) +{ + int e; + int replycode; + + e = fc_getreply(ftpconn, &replycode); + if (e == 1) /* reply not ready yet */ + { + /* see if we should time out waiting for reply */ + if ((ftpconn->last_cmd + ((unsigned long)fc_replytmo*TPS)) < ftp_ticks) + { + fc_printf(ftpconn, "ftp login timed out\n"); + return -1; + } + return 0; /* else wait some more */ + } + if (e != 0) /* fatal connection error? */ + return -1; + + + if ( replycode == 220 ) + { + /* remove all 220 commands from buffer */ + /* We have remove all lines starting with 220 from cmd buf */ + char * curpos, * nextpos; + + curpos=ftpconn->cmdbuf ; + while ( (nextpos= strstr(curpos, "\r\n")) != NULL ) + { + replycode = atoi(curpos); + if ( replycode == 220 ) /* keep searching */ + curpos=nextpos+2; + else + break; + } + /* if there were any 220 commands */ + if (curpos != ftpconn->cmdbuf) + { + int reply_220_len; /* length of 220 commands */ + int remainder_len; /* length of remainder of command buffer */ + + /* compute length of 220 commands and length of remainder of + command buffer */ + reply_220_len = curpos - ftpconn->cmdbuf; + remainder_len = sizeof(ftpconn->cmdbuf) - reply_220_len; + + /* move the remainder of the command buffer to the front */ + MEMMOVE(ftpconn->cmdbuf,curpos,remainder_len); + /* zero out the number of bytes removed at the tail end of buf */ + MEMSET(ftpconn->cmdbuf + remainder_len,0,reply_220_len); + } + } + + /* we have complete reply in ftpconn->cmdbuf */ + if (replycode > 399 || replycode < 200) + { + fc_printf(ftpconn, "User login failed, error.\n"); + FC_SETLOGSTATE(ftpconn,FCL_READY); /* not logged in */ + return -1; + } + + if (replycode < 230) /* ignore 220, 226, et.al. */ + { + return 0; + } + + /* code is now in range 230 - 399 */ + switch (ftpconn->logstate) + { + case FCL_SENTUSER: /* got reply to USER cmd */ + if (replycode >= 300 && replycode < 399) /* need password */ + { + e = fc_sendpass(ftpconn); /* send password */ + if (e) + return e; + } + else + FC_SETLOGSTATE(ftpconn,FCL_LOGGEDIN); + break; + case FCL_SENTPASS: /* got reply to PASS cmd */ + FC_SETLOGSTATE(ftpconn,FCL_LOGGEDIN); + break; + } + return 0; +} + + + + +/* FUNCTION: fc_checkcmd() + * + * fc_checkcmd() - check for a reply to and outstanding command. + * Performs state machine actions if reply is ready. Also does + * timeouts. + * + * PARAM1: ftpc * ftpconn + * + * RETURNS: Returns 0 if OK, if error returns -1. + */ + +int +fc_checkcmd(ftpc * ftpconn) +{ + int e; + int replycode; + char* cp; + + /* if waiting for connect or doing data IO, just keep doing it */ + switch (ftpconn->cmdstate) + { + case FCC_SENDING: + e = fc_sendmore(ftpconn); + return e; + case FCC_RECEIVING: + case FCC_NLSTING: + e = fc_getmore(ftpconn); + return e; + case FCC_SENDCONN: /* we are trying to connect... */ + case FCC_RECVCONN: + case FCC_NLSTCONN: + e = fc_dataconn(ftpconn); /* poll data connect */ + if (e == 1) /* data port connected? */ + { + ftpconn->cmdstate++; /* go listen for result */ + FC_CALLBACK(ftpconn); + e = 0; /* definitely not an error */ + /* If cmdstate is FCC_NLSTING or FCC_RECEIVING, + * or FCC_SENDING display the message + */ + if (ftpconn->cmdstate == FCC_SENDING) + fc_printf(ftpconn, "sending file... cticks = %lu\n", cticks); + else /* FCC_NLSTING or FCC_RECEIVING */ + fc_printf(ftpconn, "receiving file...\n"); + } + else + { + /* see if we should time out waiting for connect */ + if ((ftpconn->last_cmd + ((unsigned long)fc_replytmo*TPS)) < ftp_ticks) + { + fc_printf(ftpconn, "ftp command timed out\n"); + return -1; + } + } + return e; + } + + /* fall to here if expecting a command reply */ + e = fc_getreply(ftpconn, &replycode); + if (e == 1) /* reply not ready yet */ + { + /* see if we should time out waiting for reply */ + if ((ftpconn->last_cmd + ((unsigned long)fc_replytmo*TPS)) < ftp_ticks) + { + fc_printf(ftpconn, "ftp command timed out\n"); + return -1; + } + else + { + return 0; /* else wait some more */ + } + } + else if (e != 0) /* fatal connection error? */ + { + return -1; + } + else /* e=0 */ + { + if (strstr(ftpconn->cmdbuf, "\r\n") == NULL) + return 0; + } + + + /* fall to here if we got whole reply */ + e = 0; /* clear error holder prior to case statement */ + switch (ftpconn->cmdstate) + { + case FCC_SENDPORT: + case FCC_RECVPORT: + case FCC_NLSTPORT: + if (replycode < 200 || replycode > 299) /* OK code? */ + { + fc_printf(ftpconn, "ftp port command error %s\n", ftpconn->cmdbuf); + FC_SETLOGSTATE(ftpconn,FCL_LOGGEDIN); + break; /* this is not fatal to command connection */ + } + ftpconn->cmdstate++; /* bump to actual IO command */ + FC_CALLBACK(ftpconn); + e = fc_usercmd(ftpconn, ftpconn->cmdstate, NULL); /* send cmd */ + break; + case FCC_SENDOK: + case FCC_RECVOK: + case FCC_NLSTOK: + if ((replycode == 150) || (replycode == 125)) + { + ftpconn->cmdstate++; /* next state is handle actual connect */ + FC_CALLBACK(ftpconn); + } + else /* not a 150 code, clean up data conn */ + { + fc_endxfer(ftpconn); /* kill data connection */ + FC_SETLOGSTATE(ftpconn,FCL_LOGGEDIN); /* back to base state */ + e = 0; /* don't kill command connection */ + } + break; + case FCC_RECVDONE: /* closing receive data connection */ + case FCC_NLSTDONE: + fc_endxfer(ftpconn); /* cleanup resources */ + /* fall to logstate logic */ + case FCC_SENDDONE: /* done with file send, awaiting reply */ + FC_SETLOGSTATE(ftpconn,FCL_LOGGEDIN); /* back to base state */ + break; + case FCC_TYPE: + if (replycode == 200) + ftpconn->mode = ftpconn->newmode; + else + fc_printf(ftpconn, "type cmd failed\n"); + FC_SETLOGSTATE(ftpconn,FCL_LOGGEDIN); /* go back to idle state */ + break; + case FCC_CWD: /* get reply to Change Working Directory cmd */ + case FCC_PWD: /* get reply to Print Working Directory cmd */ + if (replycode < 200 || replycode > 299) /* check reply code */ + fc_printf(ftpconn, "path error: %s", &ftpconn->cmdbuf[5]); + else /* good reply, display to user */ + fc_printf(ftpconn, "ftp: %s", &ftpconn->cmdbuf[4]); + FC_SETLOGSTATE(ftpconn,FCL_LOGGEDIN); /* go back to idle state */ + break; + case FCC_QUIT: /* get reply to QUIT command */ + if (replycode < 200 || replycode > 299) /* check reply code */ + fc_printf(ftpconn, "quit error: %s", &ftpconn->cmdbuf[5]); + else /* good reply, display to user */ + fc_printf(ftpconn, "ftp: %s", &ftpconn->cmdbuf[4]); + FC_SETLOGSTATE(ftpconn,FCL_CLOSING); /* go ahead and close conn */ + break; + default: + dtrap(); /* bad case? */ + e = -1; + } + + /* Flush current command from cmdbuf */ + cp = strstr(ftpconn->cmdbuf, "\r\n"); /* find end of command */ + if((cp == NULL) || (*(cp + 2) == 0)) + { + ftpconn->cmdbuf[0] = 0; /* invalidate whole buffer */ + } + else /* there was another command in the buffer */ + { + cp += 2; /* point to next cmd (past CR/LF) */ + MEMMOVE(ftpconn->cmdbuf, cp, strlen(cp) + 1); /* move up next cmd */ + } + return e; +} + +/* FUNCTION: fc_showspeed() + * + * show speed parameters of current transfer. + * + * PARAM1: ftpc * ftpconn + * + * RETURNS: + */ + +void +fc_showspeed(ftpc * ftpconn) +{ + unsigned secs; + u_long ticks; + char * oper; + + switch (ftpconn->cmdstate) /* set operation string */ + { + case FCC_SENDING: + case FCC_SENDDONE: + oper = "Sent"; + break; + case FCC_RECEIVING: + case FCC_RECVDONE: + oper = "Received"; + break; + case FCC_NLSTING: + case FCC_NLSTDONE: + oper = "Listed"; + break; + default: + return; + } + + ticks = ftp_ticks - ftpconn->last_data; + secs = (unsigned)(ticks/TPS); + fc_printf(ftpconn, "%s %lu bytes in %d seconds (cticks = %lu)\n", + oper, ftpconn->datadone, secs, cticks); + /* show speed if samples are big enough */ + if (secs > 0 && ftpconn->datadone > 1024) + { + fc_printf(ftpconn, "speed: %ld.%ld KB/s\n", + (ftpconn->datadone/secs)/1024L, + (ftpconn->datadone/secs)%1024L ); + } +} + +/* FUNCTION: fc_endxfer() + * + * fc_endxfer(ftpconn) - housekepping routine to clean up after a + * data transfer. + * + * PARAM1: ftpc * ftpconn + * + * RETURNS: + */ + +void +fc_endxfer(ftpc * ftpconn) +{ + /* close file if open */ + if (ftpconn->fp) + vfclose(ftpconn->fp); + ftpconn->fp = NULL; + + /* close data socket if open */ + if (ftpconn->data_sock && ftpconn->data_sock != SYS_SOCKETNULL) + t_socketclose(ftpconn->data_sock); + ftpconn->data_sock = SYS_SOCKETNULL; + + /* printf messages as required */ + if (ftpconn->options & FCO_VERB) + { + fc_showspeed(ftpconn); + } + + FC_SETLOGSTATE(ftpconn,FCL_LOGGEDIN); + /* reset data transfer state variables */ + fc_clearf(ftpconn); +} + + + +/* FUNCTION: fc_clearf() + * + * fc_clearf(ftpconn) - housekepping routine to set all file transfer + * counters to zero. + * + * PARAM1: ftpc * ftpconn + * + * RETURNS: + */ + +void +fc_clearf(ftpc * ftpconn) +{ + /* clean up ftpconn counters, etc. */ + ftpconn->datact = 0; /* clear count */ + ftpconn->offset = 0; /* clear offset */ + ftpconn->datadone = 0L; + ftpconn->filesize = 0L; + ftpconn->last_cmd = ftp_ticks; /* update last_cmd */ +} + + + +/* FUNCTION: fc_sendmore() + * + * fc_XXXXmore() - called to drive file transfers. + * + * PARAM1: ftpc * ftpconn + * + * RETURNS: Both return 0 if OK, if error returns -1. + */ + +int +fc_sendmore(ftpc * ftpconn) +{ + int e; + + /* see if we need to read in buffer */ + if (ftpconn->datact == 0) + { + ftpconn->offset = 0; /* reset databuf index */ + ftpconn->datact = vfread(ftpconn->databuf, 1, FILEBUFSIZE, ftpconn->fp); + if (ftpconn->datact <= 0) /* end of file? */ + { + ftpconn->cmdstate = FCC_SENDDONE; /* move to await reply? */ + FC_CALLBACK(ftpconn); + fc_endxfer(ftpconn); /* close data connection , etc. */ + /* At this point we expect to receive the cmd "226 Transfer + * complete at connection for " from the peer. + * Hence the logstate should be FCL_PENDING. + */ + FC_SETLOGSTATE(ftpconn,FCL_PENDING); + return 0; + } + } + e = t_send(ftpconn->data_sock, &ftpconn->databuf[ftpconn->offset], + ftpconn->datact, 0); + if (e <= 0) + { + e = t_errno(ftpconn->data_sock); + if((e == EWOULDBLOCK) || + (e == ENOBUFS)) + { + return 0; /* Transient error, try again later */ + } + else + { + fc_printf(ftpconn, "ftp data send error %d\n", e); + return -1; + } + } + + /* fall to here if we sent data. Consider this command activity */ + ftpconn->last_cmd = ftp_ticks; + + /* do hash mark printfing */ + if (ftpconn->options & FCO_HASH) + fc_hashmark(ftpconn, ftpconn->datadone, (unsigned)e); + + ftpconn->offset += e; + ftpconn->datadone += (long)e; + ftpconn->datact -= e; + return 0; +} + +#define FTPC_MAX_PRINTF_LEN 80 + + + +/* FUNCTION: fc_getmore() + * + * PARAM1: ftpc * ftpconn + * + * RETURNS: + */ + +int +fc_getmore(ftpc * ftpconn) +{ + int e; + int read_size; + + /* we will usually try to read a whole buffer full */ + read_size = FILEBUFSIZE; + /* but if its for a list command, we read 1 byte less so that we + * got room to null terminate what we've read so we can pass it to + * fc_printf() + */ + if (ftpconn->cmdstate == FCC_NLSTING) + read_size--; + + e = t_recv(ftpconn->data_sock, ftpconn->databuf, read_size, 0); + if (e < 0) /* socket error */ + { + e = t_errno(ftpconn->data_sock); + if (e == EWOULDBLOCK) + return 0; /* no data ready try again later */ + fc_printf(ftpconn, "ftp data socket error %d\n", e); + return -1; + } + else if (e == 0) /* server closed connection */ + { + /* this is a normal transfer termination */ + if (ftpconn->options & FCO_VERB) + fc_printf(ftpconn, "ftp server closed data connection\n"); + +#if 0 + /* close data socket if open */ + if (ftpconn->data_sock && ftpconn->data_sock != SYS_SOCKETNULL) + t_socketclose(ftpconn->data_sock); + ftpconn->data_sock = SYS_SOCKETNULL; +#endif + + ftpconn->cmdstate++; /* move to shutdown state */ + FC_CALLBACK(ftpconn); + return 0; + } + else /* e is positive byte count */ + { + /* got data - consider this a command activity */ + ftpconn->last_cmd = ftp_ticks; + ftpconn->offset = 0; /* update data pointer & count */ + ftpconn->datact = e; + } + + if (ftpconn->cmdstate == FCC_NLSTING) + { + /* our homegrown version of printf() limits field sizes to + * something like 132 bytes. this loop feeds the LIST output + * to printf() 80 chars at a time so as not to exceed this limit + */ + char * cp; + char c; + int len; + + /* null terminate the string so printf will handle it right */ + ftpconn->databuf[e] = 0; + cp = ftpconn->databuf; + len = e; + + /* while there's more than 80 chars left to printf */ + while (len > FTPC_MAX_PRINTF_LEN) + { + /* save the 80th char in so we can restore it below */ + c = *(cp + FTPC_MAX_PRINTF_LEN); + /* overwrite the 80th char with a null so printf will do + the right thing */ + *(cp + FTPC_MAX_PRINTF_LEN) = 0; + + /* print the 80 bytes */ + fc_printf(ftpconn, "%s", cp); + + /* put the overwritten byte back */ + *(cp + FTPC_MAX_PRINTF_LEN) = c; + len -= FTPC_MAX_PRINTF_LEN; + cp += FTPC_MAX_PRINTF_LEN; + } + + fc_printf(ftpconn, "%s", cp); + ftpconn->datadone += ftpconn->datact; + return 0; + } + + e = vfwrite(ftpconn->databuf, 1, ftpconn->datact, ftpconn->fp); + if (e != (int)ftpconn->datact) + { + fc_printf(ftpconn, "ftp file write error\n"); + return -1; + } + /* do hash mark printfing */ + if (ftpconn->options & FCO_HASH) + fc_hashmark(ftpconn, ftpconn->datadone, ftpconn->datact); + ftpconn->datadone += (long)ftpconn->datact; + ftpconn->datact = 0;; + return 0; +} + + + + +/* FUNCTION: fc_dataconn() + * + * fc_dataconn() - Initiate or check open of a data connection. If + * ftpconn->data_sock is nonzero, this creates a socket and starts + * the non-blocking connect, else it calls connect to see if + * connection has completed. If connection completes + * ftpconn->cmdstate is incremented. This handles both active and + * passive opens, based on the FCP_PASV bit int ftpconn->options. + * + * PARAM1: ftpc * ftpconn + * + * RETURNS: Returns -1 if error detected, 1 if we're now connected, + * 0 if still * waiting. + */ + +int +fc_dataconn(ftpc * ftpconn) +{ + int e; + SOCKTYPE sock = SYS_SOCKETNULL; + struct sockaddr ftpsin; /* generic, will be cast to v4 or v6 format */ + int sinsize; /* size of ftpsin after domain selection */ + + switch (ftpconn->domain) + { +#ifdef IP_V4 + case AF_INET: + { + struct sockaddr_in * ftpsin4; + /* fill in connect parameters for v4 connection */ + sinsize = sizeof(struct sockaddr_in); + ftpsin4 = (struct sockaddr_in *)&ftpsin; + ftpsin4->sin_family = AF_INET; + ftpsin4->sin_addr.s_addr = ftpconn->fhost; + break; + } +#endif /* IP_V4 */ +#ifdef IP_V6 + case AF_INET6: + { + struct sockaddr_in6 * ftpsin6; + /* fill in connect parameters for v6 connection */ + sinsize = sizeof(struct sockaddr_in6); + ftpsin6 = (struct sockaddr_in6 *)&ftpsin; + ftpsin6->sin6_family = AF_INET; + IP6CPY(&ftpsin6->sin6_addr, &ftpconn->ip6_fhost); + break; + } +#endif /* IP_V4 */ + default: + dtrap(); /* no domain setting */ + return -1; + } + + /* see if there is already a connection in progress */ + if (ftpconn->data_sock && ftpconn->data_sock != SYS_SOCKETNULL) + { + /* see if we are listening (passive) or connecting (active) */ + if ((ftpconn->options & FCO_PASV)==0) /* server not passive, try accept */ + { + sock = t_accept(ftpconn->data_sock, &ftpsin, &sinsize); + if (sock == SYS_SOCKETNULL) + { + e = t_errno(ftpconn->data_sock); + if (e == EWOULDBLOCK) + return 0; /* normal return for waiting opens */ + fc_printf(ftpconn, "ftp: error %d on listening socket\n", e); + return -1; + } + else /* accept worked, we are connected */ + { + t_socketclose(ftpconn->data_sock); /* close listen socket */ + ftpconn->data_sock = sock; /* install accepted data socket */ + + return 1; /* return "connected" code */ + } + } + else /* server passive, we must poll active connect */ + { + e = t_connect(sock, &ftpsin, sinsize); + if (e == 0) /* connection completed OK */ + { + ftpconn->cmdstate++; /* bump command to next state */ + FC_CALLBACK(ftpconn); +#ifdef IP_V4 + if(ftpconn->domain == AF_INET) + ftpconn->dport = htons(((struct sockaddr_in *)(&ftpsin))->sin_port); +#endif /* IP_V4 */ +#ifdef IP_V6 + if(ftpconn->domain == AF_INET6) + ftpconn->dport = htons(((struct sockaddr_in6*)(&ftpsin))->sin6_port); +#endif /* IP_V6 */ + return 1; + } + e = t_errno(sock); /* get socket error */ + if (e == EINPROGRESS) /* still connecting */ + return 0; /* normal return for PASV SENDCONN & RECVCONN */ + fc_printf(ftpconn, "ftp: error %d open data connection\n", e); + return -1; + } + } + + /* see if we should be listening or connecting */ + if ((ftpconn->options & FCO_PASV)==0) /* server not passive, do listen */ + { + /* start TCP listen on data port, passing parms in local endian */ + + ftpconn->dport= fc_next_port; /* Use a unique data port */ + + fc_next_port++; + if ( fc_next_port < FTP_START_DATA_PORT ) /* wraparound occurd ? */ + fc_next_port = FTP_START_DATA_PORT ; + + sock = t_tcplisten((u_short*)&ftpconn->dport, ftpconn->domain); + + if (sock == SYS_SOCKETNULL) + { + e = t_errno(ftpconn->data_sock); + fc_printf(ftpconn, "ftp client data port list failed, error %d\n", e); + return -1; + } + } + else /* server is passive, initiate connection */ + { + sock = t_socket(ftpconn->domain, SOCK_STREAM, 0); + if (sock == SYS_SOCKETNULL) + return -1; /* fatal, kill command connection */ + + /* make non-blocking connect call */ + t_setsockopt(sock, SOL_SOCKET, SO_NBIO, NULL, 0); + e = t_connect(sock, &ftpsin, sinsize); + if (e != 0) + { + e = t_errno(sock); /* get socket error */ + if (e != EINPROGRESS) /* still connecting */ + { + fc_printf(ftpconn, "ftp: error %d open data connection\n", e); + return -1; + } + } + } + /* update state variables */ + ftpconn->last_cmd = ftp_ticks; + ftpconn->last_data = ftp_ticks; + ftpconn->data_sock = sock; + ftpconn->cmdstate++; + FC_CALLBACK(ftpconn); + return 0; +} + + + + +/* FUNCTION: fc_killsess() + * + * fc_killsess() - the "destructor" for an ftp client session struct + * + * PARAM1: ftpc * ftpconn + * + * RETURNS: + */ + +void +fc_killsess(ftpc * ftpconn) +{ + ftpc * ftpnext; + ftpc * ftplast; + + if (ftpconn->cmd_sock && ftpconn->cmd_sock != INVALID_SOCKET) + t_socketclose(ftpconn->cmd_sock); + ftpconn->cmd_sock = INVALID_SOCKET; + if (ftpconn->data_sock && ftpconn->data_sock != INVALID_SOCKET) + t_socketclose(ftpconn->data_sock); + ftpconn->data_sock = INVALID_SOCKET; + if (ftpconn->fp) + vfclose(ftpconn->fp); + + /* search ftp client list for ftpconn so we can unlink it */ + ftpnext = ftp_clients; + ftplast = NULL; + while (ftpnext) + { + if (ftpnext == ftpconn) /* found connection to delete */ + { + if (ftplast) /* not at head of queue */ + ftplast->next = ftpconn->next; /* unlink */ + else /* it's head of queue */ + ftp_clients = ftpconn->next; + break; + } + ftplast = ftpnext; + ftpnext = ftpnext->next; + } +#ifdef NPDEBUG + if (!ftpnext) /* not found in list ? */ + { dtrap(); } +#endif + FTPC_FREE(ftpconn); /* free structure memory */ +} + + + +/* FUNCTION: fc_connect() + * + * fc_connect() - initiate connect to an FTP server. If user name is + * not passed, connection will be made, but no login will occur. If + * username in given, password must be passed also if the server will + * require it. Note that many BSD derived servers ask for the + * password even if the UNIX user does not have one in his passwd + * file. + * + * this first parameter is a pointer to a binary IP address. This + * is 4 bytes long if the domain parameter is AF_INET, and 16 bytes + * long if AF_INET6. + * + * PARAM1: ip_addr fhost - ftp server to contact + * PARAM2: char * user - user & passwd to log in with + * PARAM3: char * passwd + * PARAM4: void * pio + * PARAM5: int domain - AF_INET or AF_INET6 + * + * RETURNS: Returns NULL if error, else an ftpc structure. + */ + +ftpc * +fc_connect(void * ipaddr, + char * user, /* user name */ + char * passwd, /* optional password, may be NULL or "" */ + void * pio, /* Handle to output device (for messages) */ + int domain) /* AF_INET or AF_INET6 */ +{ + ftpc * ftpconn; + int e; + + /* create connection structure */ + ftpconn = FTPC_ALLOC(sizeof(ftpc)); + if (ftpconn == NULL) + { + fc_printf(NULL, "alloc failed\n"); + return NULL; + } + + /* fill in connection structure */ + FC_SETLOGSTATE(ftpconn,0); + ftpconn->mode = FTPTYPE_ASCII; + ftpconn->domain = domain; + + /* make a copy of the passed FTP server IP address */ + switch(domain) + { +#ifdef IP_V4 + case AF_INET: + /* IPv4 Host is passed in net endian */ + ftpconn->fhost = *(ip_addr *)ipaddr; + break; +#endif /* IP_V4 */ +#ifdef IP_V6 + case AF_INET6: + IP6CPY(&ftpconn->ip6_fhost, (ip6_addr *)ipaddr); + break; +#endif /* IP_V6 */ + default: + dtrap(); + return NULL; + } + + /* if user & pw passed, copy them; else leave as 0s */ + if (user) + MEMCPY(ftpconn->username, user, FTPMAXUSERNAME); + if (passwd) + MEMCPY(ftpconn->password, passwd, FTPMAXUSERPASS); + ftpconn->next = ftp_clients; /* link at front of list */ + ftp_clients = ftpconn; + +#ifdef NPDEBUG + ftpconn->options |= FCO_VERB; /* turn on verbose for debug builds */ +#endif + + ftpconn->pio = pio; + + /* start the connection request */ + e = fc_connopen(ftpconn); + if (e) + { + fc_printf(NULL, "connect error %d\n", e); + fc_killsess(ftpconn); + return NULL; + } + SignalFtpClient(); /* wake client maintainance task */ + return ftpconn; +} + + + +/* FUNCTION: fc_get() + * + * fc_get() - Start the RETR of a file from the ftp server to the + * local file system. + * + * PARAM1: ftpc * fc + * PARAM2: char * sname + * PARAM3: char * dname + * + * RETURNS: Returns 0 if OK, else negtive error code + */ + +int +fc_get(ftpc * fc, char * sname, char * dname) +{ + int e; + char * mode; + + /* make sure session is conencted and ready */ + if (fc->logstate != FCL_LOGGEDIN) + return -1; + + if (fc->mode == FTPTYPE_ASCII) + mode = "wt"; /* ANSI translated mode */ + else + mode = "wb"; /* ANSI binary mode */ + + /* open emtpy file for receive */ + fc->fp = vfopen(dname, mode); /* check mode later */ + if (fc->fp == NULL) + { + fc_printf(fc, "Unable to open local file %s\n", dname); + return -1; + } + + MEMCPY(fc->ffilename, sname, sizeof(fc->ffilename)); + FC_SETLOGSTATE(fc,FCL_PENDING); + + if ((fc->options & FCO_PASV)==0) /* server not passive */ + { + e = fc_dataconn(fc); /* this will start our listen */ + if (e) return e; + } + + fc->cmdstate = FCC_RECVPORT; + FC_SETLOGSTATE(fc,FCL_PENDING); /* Maybe this is redundant */ + e = fc_sendport(fc); + return e; +} + + + +/* FUNCTION: fc_put() + * + * fc_put() - Start the STOR of a local file to the ftp server. + * + * PARAM1: ftpc * fc + * PARAM2: char * sname + * PARAM3: char * dname + * + * RETURNS: Returns 0 if OK, else negtive error code + */ + +int +fc_put(ftpc * fc, char * sname, char * dname) +{ + int e; + char * mode; + + /* make sure session is connected and ready */ + if (fc->logstate != FCL_LOGGEDIN) + return -1; + + /* open local file for send */ + if (fc->mode == FTPTYPE_ASCII) + mode = "rt"; /* ANSI translated mode */ + else + mode = "rb"; /* ANSI binary mode */ + + fc->fp = vfopen(sname, mode); + if (fc->fp == NULL) + { + fc_printf(fc, "Unable to open local file %s\n", sname); + return -1; + } + + MEMCPY(fc->ffilename, dname, sizeof(fc->ffilename)); + FC_SETLOGSTATE(fc,FCL_PENDING); + + if ((fc->options & FCO_PASV)==0) /* server not passive */ + { + e = fc_dataconn(fc); /* this will start our listen */ + if (e) return e; + } + + fc->cmdstate = FCC_SENDPORT; + FC_SETLOGSTATE(fc,FCL_PENDING); + e = fc_sendport(fc); + return e; +} + + + + +/* FUNCTION: fc_connopen() + * + * fc_connopen() - TCP active open routine. Provided so FTP client + * et.al. can open an active TCP connection without blocking in TCP. + * All parameters are passed in network endian. When calling for the + * first time, ftpconn->fhost and ftpconn->dport should be set and + * ftpconn->cmdstate should be 0. To poll for connection ready, + * ftpconn->cmdstate is set to the value returned from the first call + * and all other settings are ignored. + * + * PARAM1: ftpc * ftpconn + * + * RETURNS: Returns 0 if OK, -1 if error detected. + */ + +int +fc_connopen(ftpc * ftpconn) +{ + int e; + SOCKTYPE sock; + struct sockaddr ftpsin; /* cast as sockaddr_in or sockaddr_in6 */ + int sinsize; /* size of ftpsin cast */ + int replycode; + + if (ftpconn->logstate == FCL_CONNECTED) /* connected but not ready */ + { + e = fc_getreply(ftpconn, &replycode); + if (e == -1) return -1; /* return if error */ + if (e == 1) return 0; /* return if not ready yet */ + /* fall to here if we have an FTP message after socket open */ + if (replycode == 220) /* got "ready" code? */ + { + FC_SETLOGSTATE(ftpconn,FCL_READY); /* ready to send USER cmd */ + if (ftpconn->username[0]) + return(fc_senduser(ftpconn)); + else + return 0; + } + else /* got code other than "ready" - this is bad. */ + { + fc_printf(ftpconn, "connect failed; %s\n", ftpconn->cmdbuf); + return -1; /* kill off client session */ + } + } + + switch (ftpconn->domain) + { +#ifdef IP_V4 + case AF_INET: + { + struct sockaddr_in * ftpsin4; + /* fill in connect parameters for v4 connection */ + sinsize = sizeof(struct sockaddr_in); + ftpsin4 = (struct sockaddr_in *)&ftpsin; + ftpsin4->sin_family = AF_INET; + ftpsin4->sin_addr.s_addr = ftpconn->fhost; + ftpsin4->sin_port = htons(FTP_PORT); + break; + } +#endif /* IP_V4 */ +#ifdef IP_V6 + case AF_INET6: + { + struct sockaddr_in6 * ftpsin6; + /* fill in connect parameters for v6 connection */ + sinsize = sizeof(struct sockaddr_in6); + ftpsin6 = (struct sockaddr_in6 *)&ftpsin; + ftpsin6->sin6_family = AF_INET6; + ftpsin6->sin6_port = htons(FTP_PORT); + IP6CPY(&ftpsin6->sin6_addr, &ftpconn->ip6_fhost); + break; + } +#endif /* IP_V6 */ + default: + dtrap(); /* no domain setting */ + return -1; + } + + + /* if this client session already has a socket, see if it's connected */ + if (ftpconn->logstate == FCL_CONNECTING) + { + /* poll t_connect() for complete */ + e = t_connect(ftpconn->cmd_sock, &ftpsin, sinsize); + if (e) + e = t_errno(ftpconn->cmd_sock); + if (e == 0 || e == EISCONN) /* socket connected to server OK */ + { + FC_SETLOGSTATE(ftpconn,FCL_CONNECTED); + return 0; + } + /* else handle connect error */ + if (e == EINPROGRESS) /* connect still in progress? */ + return 0; /* wait some more */ + fc_printf(ftpconn, "ftp connect error %d\n", e); + return -1; + } + + /* fall to here on first connect. Get a new socket: */ + sock = t_socket(ftpconn->domain, SOCK_STREAM, 0); + if (sock == SYS_SOCKETNULL) + return -1; + + ftpconn->cmd_sock = sock; + + t_setsockopt(sock, SOL_SOCKET, SO_NBIO, NULL, 0); + + /* make initial non-blocking connect call */ + e = t_connect(sock, &ftpsin, sinsize); + if (e != 0) + { + e = t_errno(sock); + if (e != EINPROGRESS) /* still connecting */ + { + return -1; + } + } + ftpconn->last_cmd = ftp_ticks; + FC_SETLOGSTATE(ftpconn,FCL_CONNECTING); + return 0; +} + + + +/* FUNCTION: fc_senduser() + * + * state drivers - each of these is called from the state machine + * switch table to push the connection from one state to another. + * + * + * PARAM1: ftpc * ftpconn + * + * RETURNS: All return 0 if OK, else non-zero error code + */ + +int +fc_senduser(ftpc * ftpconn) +{ + /* try to log in with username */ + sprintf(ftpconn->cmdbuf, "USER %s\r\n", ftpconn->username); + FC_SETLOGSTATE(ftpconn,FCL_SENTUSER); + return (fc_sendcmd(ftpconn)); +} + + + +/* FUNCTION: fc_sendpass() + * + * PARAM1: ftpc * ftpconn + * + * RETURNS: + */ + +int +fc_sendpass(ftpc * ftpconn) +{ + sprintf(ftpconn->cmdbuf, "PASS %s\r\n", ftpconn->password); + FC_SETLOGSTATE(ftpconn,FCL_SENTPASS); + return (fc_sendcmd(ftpconn)); +} + + + +/* FUNCTION: fc_sendport() + * + * PARAM1: ftpc * ftpconn + * + * RETURNS: + */ + +int +fc_sendport(ftpc * ftpconn) +{ + +#ifdef IP_V4 + if(ftpconn->domain == AF_INET) + { + ulong lp; + unshort sp; + + /* get my IP addr for this connection, set to local endian */ + lp = htonl(ip_mymach(ftpconn->fhost)); + sp = (unshort)ftpconn->dport; + + /* format the port command from the fhost and dport info */ + sprintf(ftpconn->cmdbuf, "PORT %u,%u,%u,%u,%u,%u\r\n", + (unsigned)(lp >> 24), (unsigned)(lp >> 16)&0xff, + (unsigned)(lp >> 8)&0xff, (unsigned)(lp&0xff), + (unsigned)(sp >> 8), (unsigned)(sp & 0xff)); + } +#endif /* IPV4 */ +#ifdef IP_V6 + if(ftpconn->domain == AF_INET6) + { + struct ip6_inaddr * myaddr; + char addrbuf[46]; + + /* get my IP addr for this connection & format into text */ + myaddr = ip6_myaddr(&ftpconn->ip6_fhost, NULL); + if(myaddr == NULL) + { + dtrap(); + return ENP_LOGIC; + } + inet_ntop(AF_INET6, &myaddr->addr, addrbuf, sizeof(addrbuf) ); + + /* format the port command from the fhost and dport info */ + sprintf(ftpconn->cmdbuf, "EPRT |2|%s|%u|\r\n", addrbuf, ftpconn->dport); + } +#endif /* IP_V6 */ + + fc_clearf(ftpconn); /* clear file xfer counters */ + return (fc_sendcmd(ftpconn)); +} + + + + +/* FUNCTION: fc_sendcmd() + * + * fc_sendcmd(ftpc ftpconn) - send the command in the + * ftpconn->cmdbuf. This is suitable for calling from the state + * driver switch statement in fc_check() + * + * PARAM1: ftpc * ftpconn + * + * RETURNS: Returns 0 if OK, else non-zero error code + */ + +int +fc_sendcmd(ftpc * ftpconn) +{ + int e; + int send_len; + + /* + * Altera Niche Stack Nios port modification: + * print cmdstate as %d rather than %s to remove build warning. + */ + if(ftpconn->cmd_sock == INVALID_SOCKET) + { + dprintf("fc_sendcmd: bad socket; logstate: %d, cmdstate:%d \n", + ftpconn->logstate, ftpconn->cmdstate); + dtrap(); + return -1; + } + + /* do the printf first, else we run into state machine problems + on speedy systems if command finishes while we're printfing */ + if (ftpconn->options & FCO_VERB) + fc_printf(ftpconn, "ftp send: %s", ftpconn->cmdbuf); + + send_len = strlen(ftpconn->cmdbuf); + /* these are short commands and should send all at once: */ + e = t_send(ftpconn->cmd_sock, ftpconn->cmdbuf, send_len, 0); + if (e < 0) + { + e = t_errno(ftpconn->cmd_sock); + fc_printf(ftpconn, "send error %d on cmd %s", e, ftpconn->cmdbuf); + return -1; + } + /* verify that the whole buffer was sent */ + if (e != send_len) + { + fc_printf(ftpconn,"partial send %d bytes on cmd %s",e,ftpconn->cmdbuf); + return -1; + } + ftpconn->last_cmd = ftp_ticks; + ftpconn->cmdbuf[0] = 0; /* clear command buffer for reply */ + return 0; +} + + + +/* FUNCTION: fc_dir() + * + * fc_dir() - start the ftp command to do a DIR ("ls" for you UNIX + * folks) of the current directory of the server. Problems or results + * are reported via fc_printf(). + * + * PARAM1: ftpc * ftpconn + * + * RETURNS: Returns 0 if OK, else ENP_ error code. + */ + +int +fc_dir(ftpc * ftpconn) +{ + int e; + + if ((e = fc_ready(ftpconn)) != 0) + return e; + if ((ftpconn->options & FCO_PASV)==0) /* server not passive */ + { + e = fc_dataconn(ftpconn); /* this will start our listen */ + if (e) /* if error, kill session and exit */ + { + fc_killsess(ftpconn); + return e; + } + } + ftpconn->cmdstate = FCC_NLSTPORT; /* command state: sending list port */ + FC_SETLOGSTATE(ftpconn,FCL_PENDING); /* login state: cmd in progress */ + e = fc_sendport(ftpconn); /* kick off the port command */ + return e; +} + + + +/* FUNCTION: fc_pwd() + * + * fc_pwd() - start the ftp command to return the Current Working + * Directory. Problems or results are reported via fc_printf(). + * + * PARAM1: ftpc * ftpconn + * + * RETURNS: Returns 0 if OK, else ENP_ error code. + */ + +int +fc_pwd(ftpc * ftpconn) +{ + int e; + + if ((e = fc_ready(ftpconn)) != 0) + return e; + return(fc_usercmd(ftpconn, FCC_PWD, NULL)); +} + + + +/* FUNCTION: fc_chdir() + * + * fc_chdir() - start the ftp command to return the Current Working + * Directory. Problems or results are reported via fc_printf(). + * + * PARAM1: ftpc * ftpconn + * PARAM2: char * dirparm + * + * RETURNS: Returns 0 if OK, else ENP_ error code. + */ + +int +fc_chdir(ftpc * ftpconn, char * dirparm) +{ + int e; + + if ((e = fc_ready(ftpconn)) != 0) + return e; + return(fc_usercmd(ftpconn, FCC_CWD, dirparm)); +} + + + +/* FUNCTION: fc_settype() + * + * fc_chdir() - start the ftp command to set the data type Problems + * or results are reported via fc_printf(). + * + * PARAM1: ftpc * ftpconn + * PARAM2: int typecode + * + * RETURNS: Returns 0 if OK, else ENP_ error code. + */ + +int +fc_settype(ftpc * ftpconn, int typecode) +{ + char * typestring; + int e; + + if ((e = fc_ready(ftpconn)) != 0) + return e; + + if (typecode == FTPTYPE_ASCII) + typestring = "A"; + else if(typecode == FTPTYPE_IMAGE) + typestring = "I"; + else + return ENP_PARAM; /* unsupported typecode */ + + ftpconn->newmode = typecode; /* save type in case command works */ + return(fc_usercmd(ftpconn, FCC_TYPE, typestring)); /* roll the bones */ +} + + + +/* FUNCTION: fc_quit() + * + * fc_quit() - start the ftp command to end the ftp connection. + * Problems or results are reported via fc_printf(). + * + * PARAM1: ftpc * ftpconn + * + * RETURNS: Returns 0 if OK, else ENP_ error code. + */ + +int +fc_quit(ftpc * ftpconn) +{ + int e; + + if(ftpconn == NULL) + { + fc_printf(ftpconn, "ftp client not open\n"); + return ENP_PARAM; + } + + if(ftpconn->logstate != FCL_LOGGEDIN) + { + /* not logged in yet, just close the cmd socket */ + if (ftpconn->cmd_sock && ftpconn->cmd_sock != INVALID_SOCKET) + t_socketclose(ftpconn->cmd_sock); + ftpconn->cmd_sock = INVALID_SOCKET; + } + if ((e = fc_ready(ftpconn)) != 0) + return e; + return(fc_usercmd(ftpconn, FCC_QUIT, NULL)); +} + + + +/* FUNCTION: fc_ready() + * + * fc_ready() - Check to see if the passed session is ready to + * initiate a new command. + * + * PARAM1: ftpc * ftpconn + * + * RETURNS: Returns 0 if ready, else ENP_ error code. + */ + +int +fc_ready(ftpc * ftpconn) +{ + if(ftpconn == NULL) + { + fc_printf(ftpconn, "ftp client not open\n"); + return ENP_PARAM; + } + + if (ftpconn->logstate != FCL_LOGGEDIN) + { + if (ftpconn->logstate == FCL_PENDING) + fc_printf(ftpconn, "ftp client is busy, state %d\n", ftpconn->logstate); + else + fc_printf(ftpconn, "ftp client not logged in\n"); + return ENP_BAD_STATE; + } + return 0; /* ready for new command */ +} + + + +/* FUNCTION: fc_usercmd() + * + * fc_usertcmd() - The guts of several simple ftp client commands. + * Formats & send a command based on the passed code and an optional + * text parameter. Problems or results are reported via fc_printf(). + * + * PARAM1: ftpc * ftpconn + * PARAM2: int cmdcode + * PARAM3: char * cmdarg + * + * RETURNS: Returns 0 if OK, else ENP_ error code. + */ + +int +fc_usercmd(ftpc * ftpconn, int cmdcode, char * cmdarg) +{ + + ftpconn->cmdstate = cmdcode; /* set command state */ + FC_SETLOGSTATE(ftpconn,FCL_PENDING); /* mark login state as busy */ + switch (cmdcode) + { + case FCC_PWD: + strcpy(ftpconn->cmdbuf, "XPWD\r\n"); + break; + case FCC_CWD: + sprintf(ftpconn->cmdbuf, "CWD %s\r\n", cmdarg); + break; + case FCC_TYPE: + sprintf(ftpconn->cmdbuf, "TYPE %s\r\n", cmdarg); + break; + case FCC_NLSTOK: + sprintf(ftpconn->cmdbuf, "NLST\r\n"); + break; + case FCC_RECVOK: + sprintf(ftpconn->cmdbuf, "RETR %s\r\n", ftpconn->ffilename); + break; + case FCC_SENDOK: + sprintf(ftpconn->cmdbuf, "STOR %s\r\n", ftpconn->ffilename); + break; + case FCC_QUIT: + sprintf(ftpconn->cmdbuf, "QUIT\r\n"); + break; + default: /* bad parameter */ + dtrap(); + return ENP_PARAM; + } + return(fc_sendcmd(ftpconn)); /* send to server */ +} + +unsigned marksize = 4096; /* units for hash marking */ + + +/* FUNCTION: fc_hashmark() + * + * fc_hashmark() - called after each sucessfull network data block + * transfer to handle the printing of hashmarks. + * + * PARAM1: ftpc * ftpconn + * PARAM2: ulong before + * PARAM3: unsigned added + * + * RETURNS: + */ + +void +fc_hashmark(ftpc * ftpconn, + ulong before, /* data already moved before this transfer */ + unsigned added) /* additional data moved in this transfer */ +{ + /* print a hash mark for each "marksize" boundary */ + while (before/marksize < (before+added)/marksize) + { + fc_printf(ftpconn, "#"); /* call per-port printf */ + if (added > marksize) /* don't let "added" wrap */ + added -= marksize; + else + added = 0; + } +} + + + +/* fc_state() - display state info for passed connection */ + +#ifdef NET_STATS + +char * fc_statestr[]={ + "started connect", + "connected but no \"220 ready\" msg", + "ready, but not logged in", + "sent user, waiting reply", + "user OK, sent password", + "cmd port open, no activity", + "command in progress", + "closing command connection", +}; + + + +/* FUNCTION: fc_state() + * + * PARAM1: ftpc * fc + * + * RETURNS: + */ + +int +fc_state(ftpc * fc) +{ + ns_printf(fc->pio,"state: %s, cmdstate: %d, mode:%s idle:%ld\n", + fc_statestr[fc->logstate-1], + fc->cmdstate, + fc->mode == FTPTYPE_ASCII?"ascii":"binary", + (ftp_ticks - fc->last_cmd)/TPS); + ns_printf(fc->pio,"server: %u.%u.%u.%u, data port:%d\n", + PUSH_IPADDR(fc->fhost), fc->dport ); + ns_printf(fc->pio,"Hashing: %s, passive: %s\n", + (fc->options & FCO_HASH)?"ON":"OFF", + (fc->options & FCO_PASV)?"enabled":"off"); + + /* printf what's left of the last command. We do this by starting + * with the second char, sice we may have nulled-out the first to + * invalidate the buffer. + */ + if(fc->cmdbuf[1]) /* don't bother if no text is set */ + ns_printf(fc->pio, "last msg: %s", &fc->cmdbuf[3]); + /* if command in progess, show speed */ + if(fc->logstate == 7) + fc_showspeed(fc); + return 0; +} +#endif /* NET_STATS */ + + + +/* FUNCTION: fc_pasv() + * + * fc_pasv(ftpc ftpconn) - Start attempt to set FTP command session + * to passive mode. This will cause the server to wait for client + * (that's us) to initiate data transfers. This is usefull if we are + * behind a firewall. Problems or results are reported via + * fc_printf(). + * + * PARAM1: ftpc * ftpconn + * + * RETURNS: Returns 0 if OK, else ENP_ error code. + */ + +int +fc_pasv(ftpc * ftpconn) +{ + int e; + + if ((e = fc_ready(ftpconn)) != 0) + return e; + + if (ftpconn->options & FCO_PASV) /* already passive? */ + return ENP_LOGIC; + + /* send PASV command to server */ + ftpconn->cmdstate = FCC_PASV; /* command state: sending pasv */ + FC_SETLOGSTATE(ftpconn,FCL_LOGGEDIN); /* login state: cmd in progress */ + +#ifdef INWORKS + !!!!!!!!! + + /* post-pasv operations */ + + ftpconn->options |= FCO_PASV; /* set connection bit */ + +#endif + + + return 0; +} + + +#ifdef OS_PREEMPTIVE +/* FUNCTION: ftpc_process_rcvd_msgs () + * + * It processes messages received from other tasks (such as console + * task, Telnet server task, and timer task). These messages provide + * configuration parameters, initiate (or terminate) FTP transfer + * requests, and provide periodic timeout notification. This function + * is invoked after the FTP client task returns from its wait for the + * FTP client semaphore. + * + * This function is only used in multitasking environments. + * + * INPUT: None. + * + * OUTPUT: None. + */ + +void ftpc_process_rcvd_msgs (void) +{ + struct ftpctask_msg * msgp; + + while (ftpcq.q_len > 0) + { + LOCK_NET_RESOURCE (FTPCQ_RESID); + msgp = getq (&ftpcq); + UNLOCK_NET_RESOURCE (FTPCQ_RESID); + + if (!msgp) + { + ++ftpc_err.empty_q; + return; + } + + switch (msgp->type) + { + case FTPC_CNTRL_TRANSFER_MODE: + { + u_long transfer_mode; + + ++ftpc_msg_stats.transfer_mode; + /* extract new transfer mode from rcvd message */ + transfer_mode = *((u_long *)(&(msgp->parms [0]))); + if (transfer_mode == FTPTYPE_ASCII) + ftpc_process_asc_mode ((void *) (msgp->pio)); + else + ftpc_process_bin_mode ((void *) (msgp->pio)); + break; + } + case FTPC_CNTRL_CD: + ++ftpc_msg_stats.cd; + ftpc_process_chdir (((void *) (msgp->pio)), (char *) &(msgp->parms [0])); + break; + case FTPC_CNTRL_QUIT_FTP_SESS: + ++ftpc_msg_stats.quit_sess; + ftpc_process_quit_sess ((void *) (msgp->pio)); + break; + case FTPC_CNTRL_VERBOSE: + ++ftpc_msg_stats.verbose; + ftpc_process_verbose ((void *) (msgp->pio)); + break; + case FTPC_CNTRL_PASV: + ++ftpc_err.not_implemented; + break; + case FTPC_CNTRL_START_SESS: + { + u_long domain; + char * userp; + char * passwdp; + + ++ftpc_msg_stats.start_sess; + domain = *((u_long *)((&(msgp->parms [0])) + 16)); + userp = (char *) (((&(msgp->parms [0])) + 16) + sizeof (domain)); + passwdp = userp + strlen (userp) + 1; + ftpc_process_open (((void *) (msgp->pio)), (&(msgp->parms [0])), domain, userp, passwdp); + break; + } + case FTPC_CNTRL_HASH_PRINT: + ++ftpc_msg_stats.hash_print; + ftpc_process_hash ((void *) (msgp->pio)); + break; + case FTPC_CNTRL_MOVE_FILE: + { + u_long transfer_type; + char * sfilep; + char * dfilep; + + ++ftpc_msg_stats.move_file; + transfer_type = *((u_long *)(&(msgp->parms [0]))); + sfilep = (char *) (&(msgp->parms [0]) + sizeof (transfer_type)); + dfilep = sfilep + strlen (sfilep) + 1; + ftpc_process_move (((void *) (msgp->pio)), transfer_type, sfilep, dfilep); + break; + } + case FTPC_CNTRL_PWD: + ++ftpc_msg_stats.pwd; + ftpc_process_pwd ((void *) (msgp->pio)); + break; + case FTPC_CNTRL_LIST: + ++ftpc_msg_stats.list; + ftpc_process_list ((void *) (msgp->pio)); + break; + case FPTC_CNTRL_PRINT_STATE: + ++ftpc_msg_stats.print_state; + ftpc_process_print_state ((void *) (msgp->pio)); + break; + case FTPC_CNTRL_LOG: + ++ftpc_err.not_implemented; + break; + case FTPC_CNTRL_PERIODIC_TIMER: + ++ftpc_msg_stats.periodic_timer; + fc_check (); + break; + default: + /* increment error counter */ + ++ftpc_err.bad_msgtype; + break; + } + + /* free the message structure */ + FTPC_FREE (msgp); + } +} +#endif /* OS_PREEMPTIVE */ + + +/* FUNCTION: ftpc_process_asc_mode () + * + * This function sets the file transfer type for an ongoing FTP session + * to ASCII. it is either invoked directly from the FTP menu functions + * that process user input (for SUPERLOOP-type systems), or from the + * message handler (ftpc_process_rcvd_msgs () (for multitasking + * environments)). + * + * INPUT: Pointer to generic IO structure where request originated. + * + * OUTPUT: -1, if an FTP session doesn't exist for the originating console; + * or return code from fc_settype (). + */ + +int +ftpc_process_asc_mode(void * pio) +{ + struct ftpc * tmpcon; + int e; + + FC_MENULOG(); + if ((tmpcon = ftp_get_con (pio)) == NULL) + { + ns_printf(pio,"Open FTP session first\n"); + return -1; + } + + e = fc_settype (tmpcon, FTPTYPE_ASCII); + if (e) + ns_printf (pio,"ftp error %d setting type.\n", e); + + return e; +} + + +/* FUNCTION: ftpc_process_bin_mode () + * + * This function sets the file transfer type for an ongoing FTP session + * to image (binary). + * + * INPUT: Pointer to generic IO structure where request originated. + * + * OUTPUT: -1, if an FTP session doesn't exist for the originating console; + * or return code from fc_settype (). + */ + +int +ftpc_process_bin_mode(void * pio) +{ + struct ftpc * tmpcon; + int e; + + FC_MENULOG(); + if ((tmpcon = ftp_get_con (pio)) == NULL) + { + ns_printf (pio,"Open FTP session first\n"); + return -1; + } + + e = fc_settype (tmpcon, FTPTYPE_IMAGE); + if (e) + ns_printf (pio,"ftp error %d setting type.\n", e); + + return e; +} + + +/* FUNCTION: ftpc_process_chdir () + * + * This function requests a change to a new working directory. + * + * INPUT: (1) Pointer to generic IO structure where request originated. + * (2) Name of new working directory + * + * OUTPUT: -1, if an FTP session doesn't exist for the originating console; + * or return code from fc_chdir (). + */ + +int +ftpc_process_chdir(void * pio, char * dirstr) +{ + struct ftpc * tmpcon; + + if ((tmpcon = ftp_get_con (pio)) == NULL) + { + ns_printf (pio,"Open FTP session first\n"); + return -1; + } + + return (fc_chdir (tmpcon, dirstr)); +} + + +/* FUNCTION: ftpc_process_quit_sess () + * + * This function requests a termination of the FTP session. + * + * INPUT: Pointer to generic IO structure where request originated. + * + * OUTPUT: -1, if an FTP session doesn't exist for the originating console; + * or return code from fc_quit (). + */ + +int +ftpc_process_quit_sess (void * pio) +{ + struct ftpc * tmpcon; + + FC_MENULOG(); + if ((tmpcon = ftp_get_con (pio)) == NULL) + { + ns_printf(pio,"Open FTP session first\n"); + return -1; + } + + return (fc_quit (tmpcon)); +} + + +/* FUNCTION: ftpc_process_verbose () + * + * This function sets the verbose flag for the FTP session. + * + * INPUT: Pointer to generic IO structure where request originated. + * + * OUTPUT: -1, if an FTP session doesn't exist for the originating console; + * 0, otherwise. + */ + +int +ftpc_process_verbose(void * pio) +{ + struct ftpc * tmpcon; + + FC_MENULOG(); + if ((tmpcon = ftp_get_con (pio)) == NULL) + { + ns_printf(pio,"Open FTP session first\n"); + return -1; + } + + if (tmpcon->options & FCO_VERB) + tmpcon->options &= ~FCO_VERB; + else + tmpcon->options |= FCO_VERB; + + ns_printf(pio,"ftp verbose mode %s\n", + (tmpcon->options & FCO_VERB) ? "on":"off"); + + return 0; +} + + +/* FUNCTION: ftpc_process_open () + * + * This function opens a new session to the specified FTP server. + * + * INPUT: (1) Pointer to generic IO structure where request originated. + * (2) IP address (IPv4 or IPv6 address) + * (3) domain (AF_INET or AF_INET6) + * (4) username + * (5) password + * + * OUTPUT: -1, if fc_connect () returns 0; otherwise, 0. + */ + +int +ftpc_process_open(void * pio, u_char * srvp, u_long domain, char * user, char * passwd) +{ + /* make the connection; this will add a connection to the list + * starting from "ftp_clients" + */ + if (fc_connect (srvp, user, passwd, pio, domain) == NULL) + return -1; + else + return 0; +} + + +/* FUNCTION: ftpc_process_hash () + * + * This function sets the hash print flag for the FTP session. + * + * INPUT: Pointer to generic IO structure where request originated. + * + * OUTPUT: -1, if an FTP session doesn't exist for the originating console; + * 0, otherwise. + */ + +int +ftpc_process_hash(void * pio) +{ + struct ftpc * tmpcon; + + FC_MENULOG(); + if ((tmpcon = ftp_get_con (pio)) == NULL) + { + ns_printf(pio,"Open FTP session first\n"); + return -1; + } + + if (tmpcon->options & FCO_HASH) + tmpcon->options &= ~FCO_HASH; + else + tmpcon->options |= FCO_HASH; + + ns_printf(pio,"FTP hash mark printing turned %s\n", + tmpcon->options & FCO_HASH?"on":"off"); + + return 0; +} + + +/* FUNCTION: ftpc_process_move () + * + * This function gets (or puts) a file from (or to) the FTP server. + * + * INPUT: (1) Pointer to generic IO structure where request originated. + * (2) Direction of transfer (e.g., FTPC_GET_TRANSFER, etc.) + * (3) source filename + * (4) destination filename + * + * OUTPUT: -1, if an FTP session doesn't exist for the originating console; + * or, the return code from fc_get () or fc_put (). + */ + +int +ftpc_process_move(void * pio, int direction, char * sfile, char * dfile) +{ + struct ftpc * tmpcon; + + if ((tmpcon = ftp_get_con (pio)) == NULL) + { + ns_printf (pio,"Open FTP session first\n"); + return -1; + } + + if (direction == FTPC_GET_TRANSFER) + return (fc_get (tmpcon, sfile, dfile)); + else + return (fc_put (tmpcon, sfile, dfile)); +} + + +/* FUNCTION: ftpc_process_pwd () + * + * This function sends a request to obtain the current working directory. + * + * INPUT: Pointer to generic IO structure where request originated. + * + * OUTPUT: -1, if an FTP session doesn't exist for the originating console; + * or, the return code from fc_pwd (). + */ + +int +ftpc_process_pwd (void * pio) +{ + struct ftpc * tmpcon; + + FC_MENULOG(); + if ((tmpcon = ftp_get_con (pio)) == NULL) + { + ns_printf(pio,"Open FTP session first\n"); + return -1; + } + + return (fc_pwd (ftp_get_con(pio))); +} + + +/* FUNCTION: ftpc_process_list () + * + * This function sends a request to obtain a listing of the current working + * directory. + * + * INPUT: Pointer to generic IO structure where request originated. + * + * OUTPUT: -1, if an FTP session doesn't exist for the originating console; + * or, the return code from fc_dir (). + */ + +int +ftpc_process_list (void * pio) +{ + struct ftpc * tmpcon; + + FC_MENULOG(); + if ((tmpcon = ftp_get_con (pio)) == NULL) + { + ns_printf(pio,"ftp command connection not open\n"); + return 1; + } + + return (fc_dir (tmpcon)); +} + + +/* FUNCTION: ftpc_process_print_state () + * + * This function prints state information associated with the current FTP + * session. + * + * INPUT: Pointer to generic IO structure where request originated. + * + * OUTPUT: 0. + */ + +int +ftpc_process_print_state (void * pio) +{ + struct ftpc * tmpcon ; + + if ((tmpcon = ftp_get_con(pio)) == NULL) + { + ns_printf(pio,"FTP client not open\n"); + } +/* + * Altera Niche Stack Nios port modification + * conditionally call fc_state; it may not be available + */ +#ifdef NET_STATS + else + { + fc_state(tmpcon); + } +#endif + +#ifdef FC_LOG + if (log_flag==TRUE) + { +#ifdef FC_LOGFILE + if (ftplog) + { + ns_printf(pio,"Logging to file is enabled\n"); + } + else +#endif /*FC_LOGFILE */ + ns_printf(pio,"Logging to STDIO is enabled\n"); + } + else + ns_printf(pio,"Logging is disabled\n"); + +#endif /* FC_LOG */ + + return 0; +} + +#endif /* FTP_CLIENT */ diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpclnt.h b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpclnt.h new file mode 100644 index 0000000..3cd4353 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpclnt.h @@ -0,0 +1,244 @@ +/* + * FILENAME: FTPCLNT.H + * + * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved + * + * + * MODULE: FTP + * + * ROUTINES: + * + * PORTABLE: yes + */ + +/* ftpclnt.h Definitions for generic FTP client. + * 1/12/97 - Created. John Bartas + */ +#ifndef FTPCLNT_H +#define FTPCLNT_H + +/* Define the options enabled for FTP Client */ +#define FC_USECALLBACK 1 /* Call callbacks when FTPClient changes state */ +#define FC_LOG 1 /* Log FTP output to stdio/file */ + +#ifdef NOTDEF /* List of options disabled */ +#endif /* NOTDEF */ + +#ifdef SUPERLOOP +#define SignalFtpClient() /* define to nothing */ +#endif + +/* Define the structure used for each FTP connection */ +typedef struct ftpc +{ + struct ftpc * next; /* list link */ + int logstate; /* loggin (FCL_) state */ + int cmdstate; /* command (FCC_) state */ + int mode; /* FTPTYPE_ASCII or FTPTYPE_IMAGE */ + int newmode; /* mode to set if TYPE cmd succeeds */ + int in_use; /* reentry flag */ + int domain; /* AF_INET or AF_INET6 */ + ip_addr fhost; /* host, if connected (in net endian) */ +#ifdef IP_V6 + ip6_addr ip6_fhost; /* V6 host, if connected */ +#endif /* IP_V4 */ + unsigned options; /* hash, pasv, etc */ + unshort dport; /* data port */ + SOCKTYPE cmd_sock; /* command socket descriptor */ + SOCKTYPE data_sock; /* data socket descriptor */ + char username[FTPMAXUSERNAME]; /* name of connection user for login */ + char password[FTPMAXUSERPASS]; /* password for login */ + char ffilename[FTPMAXPATH+FTPMAXFILE]; /* name for foriegn file */ + char cmdbuf[CMDBUFSIZE]; /* command buffer */ + char databuf[FILEBUFSIZE]; /* buffer for FTP data */ + VFILE * fp; /* file in progress */ + unsigned datact; /* unprocessed data in databuf */ + unsigned offset; /* offset to data in databuf */ + ulong datadone; /* data already moved in current transfer */ + ulong filesize; /* file size of send/receive file */ + ulong last_cmd; /* time of last cmdstate change */ + ulong last_data; /* time of last data transfer activity */ + void * pio; /* To support Generic I/O for client */ +} ftpc; + +extern ftpc * ftp_clients; /* support multiple client links */ + +extern unsigned marksize; /* units for hash marking */ + +/* bits for ftpc options field: */ +#define FCO_HASH 0x0001 /* hash mark printing */ +#define FCO_PASV 0x0002 /* in passive mode */ +#define FCO_VERB 0x0004 /* verbose mode */ + +/* ftp client loggin states; If any change is done, also update fc_str[]. */ +#define FCL_CONNECTING 1 /* started connect */ +#define FCL_CONNECTED 2 /* connected but no "220 ready" msg */ +#define FCL_READY 3 /* ready, but not logged in */ +#define FCL_SENTUSER 4 /* sent user, waiting reply */ +#define FCL_SENTPASS 5 /* user OK, sent password */ +#define FCL_LOGGEDIN 6 /* cmd port open, no activity */ +#define FCL_PENDING 7 /* command in progress (see FCC_* codes) */ +#define FCL_CLOSING 8 /* closing command connection */ + +/* ftp client command states; grouped by command type + If any change is done, also update fc_str[]. */ +#define FCC_RECVPORT 10 /* sent port command, awaiting reply */ +#define FCC_RECVOK 11 /* sent RETR command, awaiting reply */ +#define FCC_RECVCONN 12 /* connecting for file receive */ +#define FCC_RECEIVING 13 /* file receive in progress */ +#define FCC_RECVDONE 14 /* done with RETR, awaiting final msg */ + +#define FCC_SENDPORT 20 /* sent port command, awaiting reply */ +#define FCC_SENDOK 21 /* sent STOR command, awaiting reply */ +#define FCC_SENDCONN 22 /* connecting for file send */ +#define FCC_SENDING 23 /* data file send in progress */ +#define FCC_SENDDONE 24 /* done with STOR, awaiting final msg */ + +#define FCC_NLSTPORT 30 /* sent port for NLST command */ +#define FCC_NLSTOK 31 /* sent NLST for NLST command */ +#define FCC_NLSTCONN 32 /* waiting for connect on data port */ +#define FCC_NLSTING 33 /* waiting for connect on data port */ +#define FCC_NLSTDONE 34 /* done with NLST, awaiting final msg */ + + +/* the non-data port commands: */ + +#define FCC_CWD 70 /* sent cwd command, awaiting reply */ +#define FCC_PWD 80 /* sent pwd command, awaiting reply */ +#define FCC_TYPE 90 /* sent TYPE command, awaiting reply */ +#define FCC_PASV 100 /* sent PASV, awaiting reply */ +#define FCC_QUIT 110 /* sent QUIT, awaiting reply (before closing) */ + +/* Map ftp memory alloc/free routines */ +#define FTPC_ALLOC(size) (ftpc*)npalloc(size) +#define FTPC_FREE(buf) npfree(buf) + + +/* ftp client extern entry points. The commands (all but fc_check) + * initiate the transactions and return without blocking. The system + * or caller must regularly call fc_check() to drive the transaction. + * Completion is detected by checking fc_logstate. + */ +ftpc * fc_connect(void * fhost, char * user, char * passwd,void * pio, int domain); +int fc_put(ftpc * fc, char * fname, char * lname); +int fc_get(ftpc * fc, char * fname, char * lname); +int fc_chdir(ftpc * ftpconn, char * dirparm); +int fc_pwd(ftpc * ftpconn); +int fc_dir(ftpc * ftpconn); +int fc_settype(ftpc * ftpconn, int type); +int fc_state(ftpc * ftpconn); +int fc_pasv(ftpc * ftpconn); +int fc_quit(ftpc * ftpconn); + +int fc_check(void); /* ftp client "task" entry point */ + +/* log_printf is used in ftpclnt.c and ftpcprn.c */ +#ifdef FC_LOG +#include "in_utils.h" /* for GEN_IO */ +extern GEN_IO ftplog; /* ftplog is "ptr to IO device" */ +#define log_printf ns_printf /* Use genericIO to send log to stdio/file */ +extern int log_flag; /* to dynamically enable/disable logging */ +#define FC_LOGFILE 1 /* log to file */ + +#else +#define log_printf ; /* Do nothing */ +#endif /* FC_LOG */ + +/* The user application can set a callback via fc_callback to receive + * information when the logstate or cmdstate changes. Sometimes, the + * callback might just be interested in the states, if it is using + * only one FTP connection. In that case, it need not know about + * ftpc. Hence the first argument is a "void instead of "ftpc If the + * callback needs information about ftp connection, it can cast fc to + * "ftpc *" + */ +#ifdef FC_USECALLBACK +extern void (*fc_callback)(void * fc, int logstate, int cmdstate); +#endif + +/* types of messages sent to FTP client task from the console task, + * Telnet server task, or timer tick task. These messages are + * deposited into the 'ftpcq' queue, and provide configuration + * parameters, initiate (or terminate) FTP transfer requests, and + * provide periodic timeout notification. + */ +#define FTPC_CNTRL_TRANSFER_MODE 0x0 /* ascii or binary */ +#define FTPC_CNTRL_CD 0x1 +#define FTPC_CNTRL_QUIT_FTP_SESS 0x2 +#define FTPC_CNTRL_VERBOSE 0x3 +#define FTPC_CNTRL_PASV 0x4 +#define FTPC_CNTRL_START_SESS 0x5 +#define FTPC_CNTRL_HASH_PRINT 0x6 +#define FTPC_CNTRL_MOVE_FILE 0x7 /* get or put */ +#define FTPC_CNTRL_PWD 0x8 +#define FTPC_CNTRL_LIST 0x9 +#define FPTC_CNTRL_PRINT_STATE 0xA +#define FTPC_CNTRL_LOG 0xB +#define FTPC_CNTRL_PERIODIC_TIMER 0xC + +#define FTPC_NUM_MSGS 0xD + +/* type of FTP transfer requested from client: GET or PUT */ +#define FTPC_GET_TRANSFER 0x1 +#define FTPC_PUT_TRANSFER 0x2 + +/* base structure for all messages sent to FTP client task */ +struct ftpctask_msg +{ + struct ftpctask_msg * next; + u_long type; + u_long pio; + u_char parms [1]; +}; + +/* statistics on errors encountered by the FTP client task */ +struct ftpc_err +{ + u_long alloc_fail; + u_long empty_q; + u_long not_implemented; + u_long bad_msgtype; +}; + +/* statistics on the types of messages received by the FTP client task */ +struct ftpc_msg_stats +{ + u_long transfer_mode; + u_long cd; + u_long quit_sess; + u_long verbose; + u_long start_sess; + u_long hash_print; + u_long move_file; + u_long pwd; + u_long list; + u_long print_state; + u_long periodic_timer; +}; + +/* FTP client task message queue (contains messages from other tasks) */ +extern struct queue ftpcq; +/* data structure to keep track of number of various types of messages + * received by the FTP client task. + */ +extern struct ftpc_msg_stats ftpc_msg_stats; +/* data structure to keep track of errors encountered by the FTP client + * task during its operation. + */ +extern struct ftpc_err ftpc_err; + +void ftpc_process_rcvd_msgs (void); +int ftpc_process_asc_mode(void * pio); +int ftpc_process_bin_mode(void * pio); +int ftpc_process_chdir(void * pio, char * dirstr); +int ftpc_process_quit_sess (void * pio); +int ftpc_process_verbose(void * pio); +int ftpc_process_open(void * pio, u_char * srvp, u_long domain, char * user, char * passwd); +int ftpc_process_hash (void * pio); +int ftpc_process_move (void * pio, int direction, char * sfile, char * dfile); +int ftpc_process_pwd (void * pio); +int ftpc_process_list (void * pio); +int ftpc_process_print_state (void * pio); + +#endif /* FTPCLNT_H */ + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpcport.c b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpcport.c new file mode 100644 index 0000000..1d069f0 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpcport.c @@ -0,0 +1,205 @@ +/* + * FILENAME: ftpcport.c + * + * Copyright 2002 By InterNiche Technologies Inc. All rights reserved + * + * + * MODULE: FTP Client + * + * ROUTINES: ftpc_nvset(), prep_ftpc(), tk_ftpclnt() + * + * PORTABLE: NO + */ + +#include "ftpport.h" /* TCP/IP, sockets, system info */ + +#ifdef FTP_CLIENT + +#include "ftpsrv.h" +#include "ftpclnt.h" + +#ifndef SUPERLOOP +#ifndef OSPORT_H +#error Need to define OSPORT_H +#endif +#include OSPORT_H +#endif /* SUPERLOOP */ + +#ifdef INCLUDE_NVPARMS +#include "nvparms.h" +#endif /* INCLUDE_NVPARMS */ + +#ifdef IN_MENUS +#include "menu.h" +#endif /* IN_MENUS */ + +#ifdef IN_MENUS +extern struct menu_op ftpmenu[]; +#endif /* IN_MENUS */ + +#ifdef INCLUDE_NVPARMS +/* Please see nvparms.h and nvparms.c regarding the usage of + * the following datatypes and functions. + */ + +int ftpc_nvset(NV_FILE * fp); + +struct ftpc_nvparam ftpc_nvparms; + +struct nvparm_info ftpc_nvformats[] = +{ + {"ftpc reply timout: %u\n" , NVINT, NVBND_NOOP, \ + &ftpc_nvparms.fc_replytmo , NULL, }, + {"ftpc activity timout: %u\n", NVINT, NVBND_NOOP, \ + &ftpc_nvparms.fc_activity_tmo, NULL, }, +}; + +#define NUMFTPC_FORMATS \ + (sizeof(ftpc_nvformats)/sizeof(struct nvparm_info)) + +#endif /* INCLUDE_NVPARMS */ + +#ifdef INCLUDE_NVPARMS + +/* FUNCTION: ftpc_nvset() + * + * PARAM1: NV_FILE * fp + * + * RETURNS: Silent return of 0 for OK + */ +int ftpc_nvset(NV_FILE * fp) +{ +int i = 0; + + nv_fprintf(fp, ftpc_nvformats[i++].pattern, ftpc_nvparms.fc_replytmo); + nv_fprintf(fp, ftpc_nvformats[i++].pattern, ftpc_nvparms.fc_activity_tmo); + return 0; +} + +struct nvparm_format ftpc_format = +{ + NUMFTPC_FORMATS, + &ftpc_nvformats[0], + ftpc_nvset, + NULL +}; + +#endif /* INCLUDE_NVPARMS */ + + +/* FUNCTION: prep_ftpc() + * + * PARAMS: NONE + * + * RETURNS: Error Code or 0 for OK + */ +int prep_ftpc(void) +{ +int e = 0; +#ifdef IN_MENUS + /* install the FTP Client commands */ + e = install_menu(&ftpmenu[0]); +#endif /* IN_MENUS */ + +#ifdef INCLUDE_NVPARMS + e = install_nvformat(&ftpc_format, nv_formats); + if(e) + { + dprintf("unable to install FTPClient NVPARMS reconfigure nv_formats[]\n"); + dtrap(); + } +#endif /* INCLUDE_NVPARMS */ + return e; +} + + +#ifndef SUPERLOOP + +#ifdef FTP_CLIENT +TK_OBJECT(to_ftpclnt); +TK_ENTRY(tk_ftpclnt); +long ftpclnt_wakes = 0; +#endif + +/* + * Altera Niche Stack Nios port modification: + * Use task priority and stack size values from ipport.h + */ +#ifdef FTP_CLIENT +struct inet_taskinfo ftpctask = { + &to_ftpclnt, + "FTP client", + tk_ftpclnt, + TK_FTPCLNT_TPRIO, + TK_FTPCLNT_SSIZE, +}; +#endif + +/* The FTP client task waits for the FTP semaphore to be signaled. + * The semaphore is signaled by other tasks such as console task, Telnet + * server task, and timer task after they have deposited a message into + * the FTP client task's message queue. These messages provide + * configuration parameters, initiate (or terminate) FTP transfer requests, + * and provide periodic timeout notification. The latter is currently + * where the bulk of the work (wrt transfers) is done. + */ + +/* FUNCTION: tk_ftpclnt() + * + * PARAM1: n/a + * + * RETURNS: n/a + */ + +#ifdef FTP_CLIENT + +TK_ENTRY(tk_ftpclnt) +{ + while (!iniche_net_ready) + TK_SLEEP(1); + +#ifndef OS_PREEMPTIVE + for (;;) + { + int work; + + work = fc_check(); /* Let client spin, get level of load */ + switch(work) /* base task action on work level */ + { + case 2: + tk_yield(); /* quick give up of CPU in case it didn't block */ + break; + case 1: + TK_SLEEP(1); /* pass a time tick before checking again */ + break; + case 0: + TK_BLOCK(); /* all done, go back to sleep */ + break; + default: + dtrap(); /* bad return value */ + break; + } + ftpclnt_wakes++; /* count wakeups */ + if (net_system_exit) + break; + } +#else + for (;;) + { + wait_app_sem (FTPC_SEMID); + ftpclnt_wakes++; /* count wakeups */ + ftpc_process_rcvd_msgs (); /* process messages received from other tasks */ + if (net_system_exit) + break; + } +#endif + + TK_RETURN_OK(); +} + +#endif /* FTP_CLIENT */ + +#endif /* SUPERLOOP */ + +#endif /* FTP_CLIENT */ + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpcprn.c b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpcprn.c new file mode 100644 index 0000000..7109294 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpcprn.c @@ -0,0 +1,137 @@ +/* + * FILENAME: ftpcprn.c + * + * Copyright 2000 By InterNiche Technologies Inc. All rights reserved + * + * + * MODULE: FTP + * + * ROUTINES: fc_printf(), + * + * PORTABLE: yes + */ + +/* The FTP client's message handler for this port. This is off by + * itself without it's prototype included to please the incredibly + * fussy Borland compiler again.... + */ +#include "ftpport.h" /* TCP/IP, sockets, system info */ + +#ifdef FTP_CLIENT + +#include "ftpsrv.h" +#include "ftpclnt.h" + +struct ftpc; +extern struct ftpc * ftp_clients; /* support multiple client links */ +extern char * prompt; + + +/* The member in_use of a FTP connection is turned ON when fc_printf() is + * being done. FTP Client, unlike FTP Server has different entry points. + * For example, + * - When the user enters FTP commands from the command line, the FTP client + * code gets executed. + * - fc_check() is called periodically to process FTP client connections. + * Consider the following scenario. + * 1. The user executes PUT command, and the FTP client code + * initiating the PUT uses fc_printf() immediately after sending the + * PORT command using fc->cmdbuf. It would then check whether the command + * was properly sent or not. + * 2. Now before this check can be done, fc_printf() calls tk_yield(), which + * would call fc_check(). fc_check() would execute and do network I/O for + * this connection and update the fc->cmdbuf based on the response for + * PORT command. + * 3. Now after fc_printf() is done, the check for PORT command would fail + * because the fc->cmdbuf is modified. + * + * On a multitasking system, FTP client would be more susceptible to + * these kind of problems. Hence a provision is provided wherein fc_check() + * doesn't execute when fc_printf() is being done. +*/ + + + +/* FUNCTION: fc_printf() + * + * fc_printf() - per-port function to handle messages from the FTP + * client library. The messages may be sent to a console if your + * system has one, logged, or just punted. For DOS demo .exe, we + * print to screen and restore the user prompt. + * + * PARAM1: struct ftpc * fc + * PARAM2: char * format + * PARAM3: long p1 + * PARAM4: long p2 + * PARAM5: long p3 + * PARAM6: long p4 + * PARAM7: long p5 + * + * RETURNS: + */ + +#ifdef PRINTF_STDARG +/* different fc_printf() functions depending on VA support */ + +void +fc_printf(struct ftpc * fc, char * format, ...) +{ + va_list a; + char linebuf[FTPMAXPATH]; + +#else /* the non-STDARG version */ + +void +fc_printf(struct ftpc * fc, char * format, + long p1, long p2, long p3, long p4, long p5) +{ +#endif /* PRINTF_STDARG */ + + char * cp; + void * pio=NULL; + + /* make sure caller passed our sole supported fc. note: fc may be NULL + * during fc_connect() call - this is OK. + */ + if (fc != NULL ) + { + pio=(void *)fc->pio; + /* set re-entry flag. So that fc_check() doesn't process this + * connection. If fc_check()->...->fc_printf() is called, then + * in_use is already set, and the increment/decrement + * below is harmless. + */ + fc->in_use++; + } + + +#ifdef PRINTF_STDARG + va_start(a,format); + vsprintf(linebuf,format,a); + va_end(a); + ns_printf(pio,linebuf); +#else /* the non-STDARG version */ + ns_printf(pio,format, p1, p2, p3, p4, p5); +#endif /* PRINTF_STDARG */ + +#ifdef FC_LOG + /* If logging is enabled, log it. Don't log to stdio. + */ + if ((log_flag == TRUE) && (ftplog!=NULL) ) +#ifdef PRINTF_STDARG + log_printf(ftplog,linebuf); +#else /* the non-STDARG version */ + log_printf(ftplog,format, p1, p2, p3, p4, p5); +#endif /* PRINTF_STDARG */ +#endif + + /* see if we should regenerate prompt */ + cp = (format + (strlen(format)-1)); + if (*cp == '\n' || *cp == '\r') /* look for newline */ + ns_printf(pio,prompt); + + if(fc) + fc->in_use--; /* clear re-entry flag */ +} + +#endif /* FTP_CLIENT */ diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpmenu.c b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpmenu.c new file mode 100644 index 0000000..df8a25d --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpmenu.c @@ -0,0 +1,971 @@ +/* + * FILENAME: ftpmenu.c + * + * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved + * + * + * MODULE: FTPCLIENT + * + * ROUTINES: ftp_get_con(), ftp_open(), ftp_get(), ftp_put(), + * ROUTINES: ftp_move(), ftp_asc_mode(), ftp_bin_mode(), ftp_hash(), + * ROUTINES: ftp_pwd(), ftp_chdir(), ftp_verbose(), ftp_quit(), + * ROUTINES: ftp_list(), ftp_state(), ftp_pasv(), fc_file_out(), ftp_log(), + * + * PORTABLE: yes + */ + +/* ftpmenu.c DOS demo menu hooks for FTP client. This is the + * non-portable portion of the FTP client for the DOS demo package. + * 1/12/97 - Created. John Bartas + * 1/4/99 - Edited menu text -MPG- + */ + +#include "ftpport.h" /* TCP/IP, sockets, system info */ + +#ifdef FTP_CLIENT + +#include "ftpsrv.h" +#include "ftpclnt.h" + +#include "menu.h" + +/* The FTP client's per-port message handler */ +extern void fc_printf(ftpc *, char *, ...); /* per-port response printer */ + +int ftp_open (void * pio); +int ftp_move (void * pio, int direction); +int ftp_get (void * pio); +int ftp_put (void * pio); +int ftp_asc_mode(void * pio); +int ftp_bin_mode(void * pio); +int ftp_hash (void * pio); +int ftp_pwd (void * pio); +int ftp_list (void * pio); +int ftp_chdir (void * pio); +int ftp_verbose (void * pio); +int ftp_state (void * pio); +int ftp_pasv (void * pio); +int ftp_quit (void * pio); +int ftp_log (void * pio); + +/* + * Altera Niche Stack Nios port modification: + * Add braces to remove build warning + */ +struct menu_op ftpmenu[] = { + { "ftpc", stooges, "FTP client menu" }, + { "ascii", ftp_asc_mode,"use ASCII transfer mode" }, + { "binary",ftp_bin_mode,"use Binary transfer mode" }, + { "cd", ftp_chdir, "change server's directory" }, + { "fquit", ftp_quit, "quit FTP session" }, + { "fverb", ftp_verbose, "toggle verbose mode" }, + { "fpasv", ftp_pasv, "set server to passive mode" }, + { "ftp", ftp_open, "open an FTP connection" }, + { "hash", ftp_hash, "toggle hash mark printing" }, + { "get", ftp_get, "GET a file" }, + { "put", ftp_put, "PUT a file" }, + { "pwd", ftp_pwd, "print working directory" }, + { "ls", ftp_list, "list files in server directory" }, +#ifdef NET_STATS + { "fstate",ftp_state, "display FTP client state" }, +#endif +#ifdef FC_LOG + { "flog", ftp_log, "enable/disable logging" }, +#endif + { NULL }, +}; + +#ifdef FC_LOG +#define FC_MENULOG() { \ + if ((log_flag==TRUE) && (ftplog!=NULL)) \ + log_printf(ftplog,"%s%s\n", \ + prompt,((GEN_IO)pio)->inbuf); \ + } +#else +#define FC_MENULOG() ; +#endif /* FC_LOG */ + +static char * ousage = "usage: ftp host username [password]\n"; +extern char * prompt; /* system menu prompt */ + +/* functions that are used to send messages to the FTP client task */ +int ftpc_send_msg1 (u_long type, u_long pio); + +int ftpc_send_msg2 (u_long type, u_long pio, u_char * argp, u_long arglen); + +int ftpc_send_msg4 (u_long type, + u_long pio, + u_char * arg1p, + u_long arg1len, + u_char * arg2p, + u_long arg2len, + u_char * arg3p, + u_long arg3len); + +int ftpc_send_msg5 (u_long type, + u_long pio, + u_char * arg1p, /* address */ + u_long arg1len, + u_char * arg2p, /* domain */ + u_long arg2len, + u_char * arg3p, /* username */ + u_long arg3len, + u_char * arg4p, /* password */ + u_long arg4len); + + +/* FUNCTION: ftp_get_con() + * + * ftp_get_con() - Get the FTP connection for the particular pio + * + * PARAM1: void * pio + * + * RETURNS: Return NULL if a corresponding connection is not found. + */ + +struct ftpc * +ftp_get_con(void * pio) +{ + struct ftpc * tmpcon = NULL ; + + tmpcon = ftp_clients ; + while ( tmpcon ) + { + if (tmpcon->pio == pio ) + { + return tmpcon; + } + else + tmpcon=tmpcon->next ; + } + + /* We couldn't find a connection which uses pio */ + + return NULL ; +} + + +/* FUNCTION: ftp_open() + * + * ftp_open() - Menu system function to open a new connection for FTP + * commands. If a connection is already open, this function returns an + * error to its caller. get host, user, password info from menu system's + * command buffer. + * + * In multitasking environments, this function sends a message (with the + * various parameters from the user's request) to the FTP client task. + * In SUPERLOOP mode, it just directly invokes the function that uses + * the parameters provided to initiate a connection. + * + * PARAM1: void * pio + * + * RETURNS: -1 if an error occured; 0, if it initiated the opening of + * a session. + */ + +int +ftp_open(void * pio) +{ + char * hostname=NULL; + char * user; + char * passwd; + char * msg; + u_long domain; /* AF_INET or AF_INET6 */ + u_char server[16]; /* dual mode IP address */ + u_long x; + + GEN_IO io= (GEN_IO) pio ; + + FC_MENULOG(); + /* extract args from command buffer */ + if ( io != NULL ) + hostname = nextarg(io->inbuf); + if (*hostname == 0) + { + ns_printf(pio,ousage); + return -1; + } + user = nextarg(hostname); + *(user-1) = 0; /* null terminate hostname */ + if (*user == 0) + { + ns_printf(pio,ousage); + return -1; + } + passwd = nextarg(user); + if (*passwd != 0) /* if passwrod was specd... */ + *(passwd-1) = 0; /* ...null terminate user */ + + + +#ifdef IP_V6 + /* Code for both dual-mode and IP_V6 only: + * If there are colons in the host name, then assume + * it's IPv6, else set domain for IP_V4 + */ + if(strchr(hostname, ':')) + domain = AF_INET6; + else + domain = AF_INET; + + if(inet_pton(domain, hostname, &server) !=0) + msg = pton_error; + else + msg = NULL; +#else /* IP_V4 only */ + { + unsigned int my_bits; /* tmp, for subnet bits */ + msg = parse_ipad((ip_addr*)&server, &my_bits, hostname); + domain = AF_INET; + } +#endif /* IP_V4 */ + + if (msg) + { + ns_printf(pio,"FTP host address error: %s\n", msg); + return -1; + } + + /* Supports only one client connection for each PIO */ + if ( ftp_get_con(pio) != NULL ) + { + ns_printf(pio,"ftp session already open\n"); + return -1; + } + + x = strlen (passwd) + 1; + +#ifdef OS_PREEMPTIVE + ftpc_send_msg5 (FTPC_CNTRL_START_SESS, + (u_long) pio, + server, + sizeof (server), + (u_char *) &domain, + sizeof (domain), + (u_char *) user, + (strlen (user) + 1), + (u_char *) passwd, + (strlen (passwd) + 1)); +#else + ftpc_process_open (pio, server, domain, user, passwd); +#endif + + return 0; +} + + +/* FUNCTION: ftp_get() + * + * PARAM1: void * pio + * + * RETURNS: + */ + +int +ftp_get(void * pio) +{ + FC_MENULOG(); + return ftp_move(pio,1); +} + + +/* FUNCTION: ftp_put() + * + * PARAM1: void * pio + * + * RETURNS: + */ + +int +ftp_put(void * pio) +{ + FC_MENULOG(); + return ftp_move(pio,0); +} + + +/* FUNCTION: ftp_move() + * + * ftp_move() - menu routine to start a file mvoe operation. Passed + * flag tells us put(0) or get(1). + * + * In multitasking environments, this function sends a message (with the + * various parameters from the user's request) to the FTP client task. + * In SUPERLOOP mode, it just directly invokes the function that uses + * the parameters provided to start the move. + * + * PARAM1: void * pio + * PARAM2: int direction + * + * RETURNS: -1 if an error occured; 0, if it initiated the move request. + */ + +int +ftp_move(void * pio, int direction) +{ + char * sfile=NULL; /* name of source file to put/get */ + char * dfile; /* optional name */ + GEN_IO io= (GEN_IO) pio ; + unsigned long int transfer_type; + + if ( ftp_get_con(pio) == NULL ) + { + ns_printf(pio,"Open FTP session first\n"); + return -1; + } + + /* extract args from command buffer */ + if ( io != NULL ) + sfile = nextarg(io->inbuf); /* name of source file */ + if (!sfile || !*sfile) + { + ns_printf(pio,"usage: ftp put|get filename [destname]\n"); + return -1; + } + dfile = nextarg(sfile); + if (dfile && *dfile) /* optional dest name given? */ + *(dfile-1) = 0; /* null terminate source file name */ + else + dfile = sfile; /* use foreign name for both */ + + if (direction) transfer_type = FTPC_GET_TRANSFER; + else transfer_type = FTPC_PUT_TRANSFER; + +#ifdef OS_PREEMPTIVE + ftpc_send_msg4 (FTPC_CNTRL_MOVE_FILE, + (u_long) pio, + (u_char *) &transfer_type, + sizeof (transfer_type), + (u_char *) sfile, + (strlen (sfile) + 1), + (u_char *) dfile, + (strlen (dfile) + 1)); +#else + ftpc_process_move (pio, transfer_type, sfile, dfile); +#endif + + return 0; +} + + +/* FUNCTION: ftp_asc_mode() + * + * In multitasking environments, this function sends a message (with the + * filetype configuration (ASCII) from the user's request) to the FTP + * client task. In SUPERLOOP mode, it just directly invokes the function + * that sets up the type of the transfer. + * + * PARAM1: void * pio + * + * RETURNS: Return code from ftpc_send_msg2 () for non-SUPERLOOP environments, + * or the return code from ftpc_process_asc_mode () for SUPERLOOP + * environments. + */ + +int +ftp_asc_mode(void * pio) +{ +#ifdef OS_PREEMPTIVE + unsigned long int transfer_mode = FTPTYPE_ASCII; + + return (ftpc_send_msg2 (FTPC_CNTRL_TRANSFER_MODE, (u_long) pio, + (u_char *) &transfer_mode, sizeof (transfer_mode))); +#else + return (ftpc_process_asc_mode (pio)); +#endif +} + + +/* FUNCTION: ftp_bin_mode() + * + * In multitasking environments, this function sends a message (with the + * filetype configuration (image) from the user's request) to the FTP + * client task. In SUPERLOOP mode, it just directly invokes the function + * that sets up the type of the transfer. + * + * PARAM1: void * pio + * + * RETURNS: Return code from ftpc_send_msg2 () for non-SUPERLOOP environments, + * or the return code from ftpc_process_asc_mode () for SUPERLOOP + * environments. + */ + +int +ftp_bin_mode(void * pio) +{ +#ifdef OS_PREEMPTIVE + unsigned long int transfer_mode = FTPTYPE_IMAGE; + + return (ftpc_send_msg2 (FTPC_CNTRL_TRANSFER_MODE, (u_long) pio, + (u_char *) &transfer_mode, sizeof (transfer_mode))); +#else + return (ftpc_process_bin_mode (pio)); +#endif +} + + +/* FUNCTION: ftp_hash() + * + * In multitasking environments, this function sends a message (requesting + * that hashes be printed to display the progress of an ongoing file transfer) + * to the FTP client task. In SUPERLOOP mode, it just directly invokes the + * function that provides the same request to the FTP client. + * + * PARAM1: void * pio + * + * RETURNS: Return code from ftpc_send_msg1 () for non-SUPERLOOP environments, + * or the return code from ftpc_process_hash () for SUPERLOOP + * environments. + */ + +int +ftp_hash(void * pio) +{ +#ifdef OS_PREEMPTIVE + return (ftpc_send_msg1 (FTPC_CNTRL_HASH_PRINT, (u_long) pio)); +#else + return (ftpc_process_hash (pio)); +#endif +} + + +/* FUNCTION: ftp_pwd() + * + * In multitasking environments, this function sends a message (requesting + * the name of the current working directory at the server where the client + * is logged in) to the FTP client task. In SUPERLOOP mode, it just directly + * invokes the function that provides the same request to the FTP client. + * + * PARAM1: void * pio + * + * RETURNS: Return code from ftpc_send_msg1 () for non-SUPERLOOP environments, + * or the return code from ftpc_process_pwd () for SUPERLOOP + * environments. + */ + +int +ftp_pwd(void * pio) +{ +#ifdef OS_PREEMPTIVE + return (ftpc_send_msg1 (FTPC_CNTRL_PWD, (u_long) pio)); +#else + return (ftpc_process_pwd (pio)); +#endif +} + + +/* FUNCTION: ftp_chdir() + * + * In multitasking environments, this function sends a message (requesting + * a change of the current working directory at the server where the client + * is logged in) to the FTP client task. In SUPERLOOP mode, it just directly + * invokes the function that provides the same request to the FTP client. + * + * PARAM1: void * pio + * + * RETURNS: -1 if a path to 'cd' to is not provided; otherwise, the return + * code from ftpc_send_msg2 () for non-SUPERLOOP environments, + * or the return code from ftpc_process_chdir () for SUPERLOOP + * environments. + */ + +int +ftp_chdir(void * pio) +{ + char * cparm=NULL; + GEN_IO io= (GEN_IO) pio ; + + FC_MENULOG(); + if ( io != NULL ) + cparm = nextarg(io->inbuf); + if (!cparm || !*cparm) + { + ns_printf(pio,"please specify path arg\n"); + return -1; + } + +#ifdef OS_PREEMPTIVE + return (ftpc_send_msg2 (FTPC_CNTRL_CD, (u_long) pio, (u_char *) cparm, strlen (cparm) + 1)); +#else + return (ftpc_process_chdir (pio, cparm)); +#endif +} + + +/* FUNCTION: ftp_verbose() + * + * In multitasking environments, this function sends a message (requesting + * that the client be verbose when displaying the state of an ongoing + * transaction) to the FTP client task. In SUPERLOOP mode, it just directly + * invokes the function that provides the same request to the FTP client. + * + * PARAM1: void * pio + * + * RETURNS: Return code from ftpc_send_msg1 () for non-SUPERLOOP environments, + * or the return code from ftpc_process_verbose () for SUPERLOOP + * environments. + */ + +int +ftp_verbose(void * pio) +{ +#ifdef OS_PREEMPTIVE + return (ftpc_send_msg1 (FTPC_CNTRL_VERBOSE, (u_long) pio)); +#else + return (ftpc_process_verbose (pio)); +#endif +} + + +/* FUNCTION: ftp_quit() + * + * In multitasking environments, this function sends a message (requesting + * the termination of an ongoing FTP session) to the FTP client task. In + * SUPERLOOP mode, it just directly invokes the function that provides the + * same request to the FTP client. + * + * PARAM1: void * pio + * + * RETURNS: Return code from ftpc_send_msg1 () for non-SUPERLOOP environments, + * or the return code from ftpc_process_quit_sess () for SUPERLOOP + * environments. + */ + +int +ftp_quit(void * pio) +{ +#ifdef OS_PREEMPTIVE + return (ftpc_send_msg1 (FTPC_CNTRL_QUIT_FTP_SESS, (u_long) pio)); +#else + return (ftpc_process_quit_sess (pio)); +#endif +} + + +/* FUNCTION: ftp_list() + * + * In multitasking environments, this function sends a message (requesting + * a listing of the files in the current working directory at the server + * where the client is logged in) to the FTP client task. In SUPERLOOP + * mode, it just directly invokes the function that provides the same + * request to the FTP client. + * + * PARAM1: void * pio + * + * RETURNS: Return code from ftpc_send_msg1 () for non-SUPERLOOP environments, + * or the return code from ftpc_process_list () for SUPERLOOP + * environments. + */ + +int +ftp_list(void * pio) +{ +#ifdef OS_PREEMPTIVE + return (ftpc_send_msg1 (FTPC_CNTRL_LIST, (u_long) pio)); +#else + return (ftpc_process_list (pio)); +#endif +} + +#ifdef NET_STATS + + +/* FUNCTION: ftp_state() + * + * In multitasking environments, this function sends a message (requesting + * a display of the latest status of the currently open FTP session (if any)) + * to the FTP client task. In SUPERLOOP mode, it just directly invokes the + * function that provides the same request to the FTP client. + * + * PARAM1: void * pio + * + * RETURNS: Return code from ftpc_send_msg1 () for non-SUPERLOOP environments, + * or the return code from ftpc_process_print_state () for SUPERLOOP + * environments. + */ + +int +ftp_state(void * pio) +{ +#ifdef OS_PREEMPTIVE + return (ftpc_send_msg1 (FPTC_CNTRL_PRINT_STATE, (u_long) pio)); +#else + return (ftpc_process_print_state (pio)); +#endif +} +#endif /* NET_STATS */ + + + +/* FUNCTION: ftp_pasv() + * + * PARAM1: void * pio + * + * RETURNS: + */ + +int +ftp_pasv(void * pio) +{ + int e; + struct ftpc * tmpcon ; + + FC_MENULOG(); + if ( (tmpcon=ftp_get_con(pio)) == NULL ) + { + ns_printf(pio,"FTP client not open\n"); + return 0; + } + + e = fc_pasv(tmpcon); + return e; +} + +#ifdef FC_LOG +/* Use of ftp_log needs some explanation. + * Each call to ftp_log toggles logging. That is, + * If logging is enabled, it is disabled. + * If logging is disabled, it is enabled. + * If logging is disabled, and ftp_log is called, then + * If no arguments are passed, logging to stdio is enabled. + * Else the argument is treated as filename and logging to file is enabled. + * If logging is enabled, and ftp_log is called, then the argument are not used. + * + * If FC_LOGFILE is disabled, then "logging to FILE" feature is disabled. + * + * EXAMPLE + * The flog command from menu prompt will invoke ftp_log(). + * Assume that logging is disabled and FC_LOGFILE is enabled. + * + * flog - enables logging to stdio + * flog - disables logging + * flog ftp.log - enables logging to file ftp.log + * flog - disables logging + * + */ +#ifdef FC_LOGFILE +char fc_buf[FTPMAXFILE]; + + +/* FUNCTION: fc_file_out() + * + * PARAM1: long s + * PARAM2: char *buf + * PARAM3: int len + * + * RETURNS: + */ + +int fc_file_out(long s, char * buf, int len) +{ + VFILE *fp = (VFILE *)s; + + vfwrite(buf,len,1,fp); + return len; +} + +struct GenericIO fc_file_io = { fc_buf, fc_file_out, 0, NULL } ; +#endif /*FC_LOGFILE */ + + + +/* FUNCTION: ftp_log() + * + * PARAM1: void * pio + * + * RETURNS: + */ + +int +ftp_log(void * pio) +{ + + FC_MENULOG(); + if (log_flag==TRUE) + { + /* Logging is enabled. Disable it */ + log_flag=FALSE; +#ifdef FC_LOGFILE + if (ftplog) + { + ns_printf(pio, "Logging to file disabled\n"); + vfclose((VFILE *)fc_file_io.id); + } + else +#endif /*FC_LOGFILE */ + ns_printf(pio, "Logging to STDIO disabled\n"); + } + else + { + /* Logging is disabled. Enable it. If an argument is passed, + * then it is name of logfile. Hence enable logging to file. If + * no argument is passed, then enable logging to stdio. + */ +#ifdef FC_LOGFILE + char * filename=NULL; + GEN_IO io= (GEN_IO) pio ; + VFILE * fp; +#endif /*FC_LOGFILE */ + + log_flag=TRUE; + ftplog =NULL; /* By default log to stdio */ + +#ifdef FC_LOGFILE + /* extract args from command buffer */ + if ( io != NULL ) + { + filename = nextarg(io->inbuf); + if(*filename != 0) /* user passed file name */ + { + fp=vfopen(filename, "w"); + if (fp==NULL) + { + ns_printf(pio, "Can't open file %s.", filename); + } + else + { + fc_file_io.id = (long)fp; + ftplog = &fc_file_io; + } + } + } + + if (ftplog) + ns_printf(pio, "Logging to file %s enabled\n", filename); + else +#endif /*FC_LOGFILE */ + ns_printf(pio, "Logging to STDIO enabled\n"); + } + + return 0; +} +#endif /* FC_LOG */ + + + +#ifdef OS_PREEMPTIVE +/* utility functions to send messages with zero or more parameters to the FTP client task */ + +/* FUNCTION: ftpc_send_msg1 () + * + * This function sends a zero- or one-parameter message to the FTP client task. + * The list of messages that use this function include: + * + * FTPC_CNTRL_QUIT_FTP_SESS + * FTPC_CNTRL_VERBOSE + * FTPC_CNTRL_HASH_PRINT + * FTPC_CNTRL_PWD + * FTPC_CNTRL_LIST + * FPTC_CNTRL_PRINT_STATE + * FTPC_CNTRL_PERIODIC_TIMER (zero parameters; 'pio' arg is ignored) + * + * INPUT: (1) Type of message to be sent (FTPC_CNTRL_QUIT_FTP_SESS, etc.) + * (2) Pointer to generic IO structure from where request originated + * + * OUTPUT: -1, if storage for the message could not be allocated; 0, otherwise. + */ + +int ftpc_send_msg1 (u_long type, u_long pio) +{ + struct ftpctask_msg * msgp; + + msgp = (struct ftpctask_msg *) FTPC_ALLOC (sizeof (struct ftpctask_msg)); + if (!msgp) + { + ++ftpc_err.alloc_fail; + return -1; + } + + msgp->type = type; + msgp->pio = pio; + + /* send message to FTP client task */ + LOCK_NET_RESOURCE (FTPCQ_RESID); + putq(&ftpcq, (q_elt)msgp); + UNLOCK_NET_RESOURCE (FTPCQ_RESID); + + post_app_sem (FTPC_SEMID); + + return 0; +} + + +/* FUNCTION: ftpc_send_msg2 () + * + * This function sends a two-parameter message to the FTP client task. + * The list of messages that use this function include: + * + * FTPC_CNTRL_TRANSFER_MODE + * FTPC_CNTRL_CD + * + * INPUT: (1) Type of message to be sent (FTPC_CNTRL_TRANSFER_MODE, etc.) + * (2) Pointer to generic IO structure from where request originated + * (3) Pointer to second parameter (in the message for the FTP client task) + * (4) Length of second parameter (starting at 'argp') + * + * OUTPUT: -1, if storage for the message could not be allocated; 0, otherwise. + */ + +int ftpc_send_msg2 (u_long type, u_long pio, u_char * argp, u_long arglen) +{ + struct ftpctask_msg * msgp; + + msgp = (struct ftpctask_msg *) FTPC_ALLOC (sizeof (struct ftpctask_msg) + arglen); + if (!msgp) + { + ++ftpc_err.alloc_fail; + return -1; + } + + msgp->type = type; + msgp->pio = pio; + memcpy (msgp->parms, argp, arglen); + + /* send message to FTP client task */ + LOCK_NET_RESOURCE (FTPCQ_RESID); + putq(&ftpcq, (q_elt)msgp); + UNLOCK_NET_RESOURCE (FTPCQ_RESID); + + post_app_sem (FTPC_SEMID); + + return 0; +} + + +/* FUNCTION: ftpc_send_msg4 () + * + * This function sends a four-parameter message to the FTP client task. + * The list of messages that use this function include: + * + * FTPC_CNTRL_MOVE_FILE + * + * INPUT: (1) Type of message to be sent (FTPC_CNTRL_MOVE_FILE) + * (2) Pointer to generic IO structure from where request originated + * (3) Pointer to second parameter (in the message for the FTP client task) + * (4) Length of second parameter (starting at 'arg1p') + * (5) Pointer to third parameter (in the message for the FTP client task) + * (6) Length of third parameter (starting at 'arg2p') + * (7) Pointer to fourth parameter (in the message for the FTP client task) + * (8) Length of fourth parameter (starting at 'arg3p') + * + * OUTPUT: -1, if storage for the message could not be allocated; 0, otherwise. + */ + +int ftpc_send_msg4 (u_long type, + u_long pio, + u_char * arg1p, + u_long arg1len, + u_char * arg2p, + u_long arg2len, + u_char * arg3p, + u_long arg3len) +{ + struct ftpctask_msg * msgp; + unsigned char * startp; + + msgp = (struct ftpctask_msg *) FTPC_ALLOC (sizeof (struct ftpctask_msg) + arg1len + arg2len + arg3len); + if (!msgp) + { + ++ftpc_err.alloc_fail; + return -1; + } + + msgp->type = type; + msgp->pio = pio; + startp = &(msgp->parms[0]); + memcpy (startp, arg1p, arg1len); + memcpy (startp + arg1len, arg2p, arg2len); + memcpy (startp + arg1len + arg2len, arg3p, arg3len); + + /* send message to FTP client task */ + LOCK_NET_RESOURCE (FTPCQ_RESID); + putq(&ftpcq, (q_elt)msgp); + UNLOCK_NET_RESOURCE (FTPCQ_RESID); + + post_app_sem (FTPC_SEMID); + + return 0; +} + + +/* FUNCTION: ftpc_send_msg5 () + * + * This function is used to send a five-parameter message to the FTP client task. + * + * FTPC_CNTRL_START_SESS + * + * INPUT: (1) Type of message to be sent (FTPC_CNTRL_MOVE_FILE) + * (2) Pointer to generic IO structure from where request originated + * (3) Pointer to second parameter (in the message for the FTP client task) + * (4) Length of second parameter (starting at 'arg1p') + * (5) Pointer to third parameter (in the message for the FTP client task) + * (6) Length of third parameter (starting at 'arg2p') + * (7) Pointer to fourth parameter (in the message for the FTP client task) + * (8) Length of fourth parameter (starting at 'arg3p') + * (9) Pointer to fifth parameter (in the message for the FTP client task) + * (A) Length of fifth parameter (starting at 'arg4p') + * + * OUTPUT: -1, if storage for the message could not be allocated; 0, otherwise. + */ + +int ftpc_send_msg5 (u_long type, + u_long pio, + u_char * arg1p, /* address */ + u_long arg1len, + u_char * arg2p, /* domain */ + u_long arg2len, + u_char * arg3p, /* username */ + u_long arg3len, + u_char * arg4p, /* password */ + u_long arg4len) +{ + struct ftpctask_msg * msgp; + unsigned char * startp; + + msgp = (struct ftpctask_msg *) FTPC_ALLOC (sizeof (struct ftpctask_msg) + arg1len + arg2len + arg3len + arg4len); + if (!msgp) + { + ++ftpc_err.alloc_fail; + return -1; + } + + msgp->type = type; + msgp->pio = pio; + startp = &(msgp->parms[0]); + memcpy (startp, arg1p, arg1len); + memcpy (startp + arg1len, arg2p, arg2len); + memcpy (startp + arg1len + arg2len, arg3p, arg3len); + memcpy (startp + arg1len + arg2len + arg3len, arg4p, arg4len); + + /* send message to FTP client task */ + LOCK_NET_RESOURCE (FTPCQ_RESID); + putq(&ftpcq, (q_elt)msgp); + UNLOCK_NET_RESOURCE (FTPCQ_RESID); + + post_app_sem (FTPC_SEMID); + + return 0; +} +#endif /* OS_PREEMPTIVE */ + + +/* FUNCTION: ftpc_periodic_timer () + * + * This function is invoked from timer task (tk_nettick), and is responsible for + * moving the file transfer to completion. + * + * INPUT: None. + * OUTPUT: None. + */ + +void ftpc_periodic_timer (void) +{ +#ifdef OS_PREEMPTIVE + /* the second ('pio') parameter is irrelevant */ + ftpc_send_msg1(FTPC_CNTRL_PERIODIC_TIMER, 0); +#else + fc_check(); +#endif +} + +#endif /* FTP_CLIENT */ diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpport.h b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpport.h new file mode 100644 index 0000000..039e955 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpport.h @@ -0,0 +1,128 @@ +/* + * FILENAME: FTPPORT.H + * + * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved + * + * + * MODULE: FTP + * + * ROUTINES: + * + * PORTABLE: yes + */ + +/* ftpport.h FTP server's per-port definitions. + * 1/12/97 - Created as part of cleanup. John Bartas + */ + +#ifndef _FTPPORT_H_ +#define _FTPPORT_H_ 1 + +#include "ipport.h" +#include "libport.h" +#include "tcpapp.h" +#include "userpass.h" + +/* Implementation defines: */ +#define FTPMAXPATH 168 /* max path length, excluding file name */ +#define FTPMAXFILE 16 /* max file name length w/o path */ +#define CMDBUFSIZE 256 +/* #define CMDBUFSIZE 1024 // Texas Imperial Sw's WFTD sends a BIG welcome str */ + + +#ifndef FILEBUFSIZE /* Allow override from ipport.h */ +#define FILEBUFSIZE (6*1024) +#endif /* FILEBUFSIZE */ + + +#ifdef MAX_USERLENGTH +#define FTPMAXUSERNAME MAX_USERLENGTH +#define FTPMAXUSERPASS MAX_USERLENGTH +#else +#define FTPMAXUSERNAME 32 +#define FTPMAXUSERPASS 24 +#endif + +/* default port for FTP data transfers. This can default to 20 (as + * some interpret the RFC as recommending) or default to 0 to let the + * sockets layer pick a port randomly. It could even point to a user + * provided routine which determines a port number alogrithmically. + */ +#define FTP_DATAPORT 20 + + +/* set up file system options for target system */ + +#ifdef UNIX_VFS +#define FTP_SLASH '/' /* use UNIX style slash */ +#else +#if ((!defined(AMD_NET186)) && (!defined(ACE_360)) && (!defined(ARM_PID))) +#define DRIVE_LETTERS 1 /* track drive as well as directory */ +#endif +#define DEFAULT_DRIVE "c:" +#define FTP_SLASH '\\' /* use DOS style slash */ +#endif + +/* define clock tick info for DOS */ +#define FTPTPS TPS /* number of ftps_loop calls per second */ +#define ftpticks cticks + + +#ifdef MINI_TCP /* mini-sockets */ +/* Set the type of indentifier sockets will have */ +#define SO_GET_FPORT(so) (((M_SOCK)so)->fport) +#define SO_GET_LPORT(so) (((M_SOCK)so)->lport) +#else /* not MINI_TCP, use BSDish sockets */ +unshort SO_GET_FPORT(WP_SOCKTYPE so); +unshort SO_GET_LPORT(WP_SOCKTYPE so); +#endif + + +/* Added sys_ routines for FTP support */ +SOCKTYPE t_tcplisten(u_short * lport, int doamin); +SOCKTYPE t_tcpopen(ip_addr host, u_short lport, u_short fport); + + +/* define number of read-sends to do per ftp_check(). For best + * performance, this times the FILEBUFSIZE should be about equal + * to anicipated TCP window. + */ +#ifndef MAXSENDLOOPS /* allow tuning from ipport.h */ +#ifdef TCP_ZEROCOPY +#define MAXSENDLOOPS 12 /* MAX number of loops */ +#else +#define MAXSENDLOOPS 1 /* MAX number of loops */ +#endif /* not TCP_ZEROCOPY */ +#endif /* no MAXSENDLOOPS */ + +/* Configurable limit on max number of ftp sessions. Setting this value to 0 or + * -1 results in no limitation on number of sessions. The default value is 32. + */ +#ifndef MAX_FTPS_SESS /* allow tuning from ipport.h */ +#define MAX_FTPS_SESS 32 +#endif /* MAX_FTPS_SESS */ + +/* map ftp's timer tick count to system's */ +#define ftp_ticks cticks + +/* map FTP server's alloc and free to local mem library */ +#define FTPSALLOC(size) npalloc(size) +#define FTPSFREE(ptr) npfree(ptr) + +/* FTP Client related non-volatile parameters. Please see nvparms.h + * and nvparms.c regarding the usage of the following structure. + */ +#ifdef INCLUDE_NVPARMS +#ifdef FTP_CLIENT +struct ftpc_nvparam +{ + int fc_replytmo ; /* secs of inactivity (for a cmd) for timeout*/ + int fc_activity_tmo; /* ftp client's inactivity timeout (secs) */ +}; + +extern struct ftpc_nvparam ftpc_nvparms; +#endif /* FTP_CLIENT */ +#endif /* INCLUDE_NVPARMS */ + +#endif /* _FTPPORT_H_ */ + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsport.c b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsport.c new file mode 100644 index 0000000..abfc932 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsport.c @@ -0,0 +1,535 @@ +/* + * FILENAME: ftpsport.c + * + * Copyright 2000-2008 By InterNiche Technologies Inc. All rights reserved + * + * + * MODULE: FTPSERVER + * + * ROUTINES: ftps_init(), ftps_check(), fs_lookupuser(), + * ROUTINES: ftps_cleanup(), + * + * PORTABLE: no + */ + +/* Additional Copyrights: */ + +/* ftpsport.c + * Portions Copyright 1996 by NetPort Software. All rights reserved. + * The Port-dependant portion of the FTP Server code. 11/24/96 - + * Created by John Bartas + */ + +#include "ftpport.h" /* TCP/IP, sockets, system info */ +#include "ftpsrv.h" + +#ifndef SUPERLOOP +#ifndef OSPORT_H +#error Need to define OSPORT_H +#endif +#include OSPORT_H +#endif /* SUPERLOOP */ + +struct sockaddr_in ftpssin; + +#ifdef IP_V4 +SOCKTYPE ftps_sock = SYS_SOCKETNULL; +#endif /* IP_V4 */ + +#ifdef IP_V6 +SOCKTYPE ftps_sock6 = SYS_SOCKETNULL; +#endif /* IP_V6 */ + + +#ifdef MINI_TCP +#include "msring.h" +#ifndef FTPS_NEWQLEN +#define FTPS_NEWQLEN 4 /* max # buffered new connections */ +#endif /* ndef FTPS_NEWQLEN */ +struct msring ftps_msring; +static M_SOCK ftps_msring_buf[FTPS_NEWQLEN + 1]; +#endif /* MINI_TCP */ + + +#if (defined(FTP_CLIENT) && defined(INCLUDE_NVPARMS)) +#include "nvparms.h" +extern int fc_replytmo ; /* secs of inactivity (for a cmd) for timeout*/ +extern int fc_activity_tmo; /* ftp client's inactivity timeout (secs) */ +#endif + +#ifdef FTP_SERVER +extern int ftps_init(void); +extern void ftps_cleanup(void); +extern void ftps_check(void); +#endif + + + +/* FUNCTION: ftps_init() + * + * ftps_init() - this is called by the ftp server demo package once + * at startup time. It initializes the vfs and opens a tcp socket to + * listen sfor web connections + * + * If FTP_CLIENT and INCLUDE_NVPARMS are both enabled, then we need to + * change a couple of FTP_CLIENT parameters to that in the NV file. + * + * PARAM1: + * + * RETURNS: Returns 0 if OK, non-zero if error. + */ + +int +ftps_init() +{ + unshort port; + int opens = 0; + + /* add default users for this port */ + /* anonymous makes you enter a password, we just don't care what it is */ + add_user("anonymous", "*", NULL); + add_user("guest", "guest", NULL); + + port = FTP_PORT; + +#ifdef IP_V4 + ftps_sock = t_tcplisten(&port, AF_INET); + if (ftps_sock == SYS_SOCKETNULL) + dprintf("FTP server: unable to start listen\n"); + else + opens++; +#endif /* IP_V4 */ + +#ifdef IP_V6 + ftps_sock6 = t_tcplisten(&port, AF_INET6); + if (ftps_sock6 == SYS_SOCKETNULL) + dprintf("FTP server: unable to start IPv6 listen\n"); + else + opens++; +#endif /* IP_V6 */ + + if (opens == 0) + return -1; + +#ifdef MINI_TCP + msring_init(&ftps_msring, ftps_msring_buf, + sizeof(ftps_msring_buf) / sizeof(ftps_msring_buf[0])); +#endif /* MINI_TCP */ + +#if (defined(FTP_CLIENT) && defined(INCLUDE_NVPARMS)) + /* So the following code is included only when an NVFS exists. */ + + if (ftpc_nvparms.fc_replytmo > 0) + fc_replytmo = ftpc_nvparms.fc_replytmo ; + + if (ftpc_nvparms.fc_activity_tmo > 0) + fc_activity_tmo = ftpc_nvparms.fc_activity_tmo ; + +#endif /* FTP_CLIENT & INCLUDE_NVPARMS */ + + return 0; +} + +#ifndef MINI_TCP + +/* Accept a new FTP command connection + * + * Returns 0 if OK, or ENP error code + */ + +int +ftp_accept(int domain, SOCKTYPE ftps_sock, int clientlen) +{ + SOCKTYPE socktmp; + struct sockaddr client; + int err; + ftpsvr * ftps; + + socktmp = t_accept(ftps_sock, &client, &clientlen); + if (socktmp != SYS_SOCKETNULL) + { + ftps = ftps_connection(socktmp); + if (ftps == NULL) + return ENP_NOMEM; /* most likely problem */ + ftps->domain = domain; + } + else + { + err = t_errno(ftps_sock); + if (err != EWOULDBLOCK) + { + return err; + } + } + return 0; +} +#endif /* ndef MINI_TCP */ + + +/* FUNCTION: ftps_check() + * + * ftp server task loop. For the PC DOS demo, this is called once + * every main task loop. + * + * PARAM1: + * + * RETURNS: + */ + +static int in_ftps_check = 0; /* reentry guard */ + +void +ftps_check() +{ +#ifdef MINI_TCP + SOCKTYPE socktmp; +#endif + + in_ftps_check++; + if (in_ftps_check != 1) + { + in_ftps_check--; + return; + } + +#ifdef MINI_TCP + + while (msring_del(&ftps_msring, &socktmp) == 0) + { + ftpsvr *e; + + e = ftps_connection(socktmp); + if (e == (ftpsvr *)NULL) + { + dprintf("ftp connection error\n"); + continue; + } + m_ioctl(socktmp, SO_NONBLOCK, NULL); /* make socket non-blocking */ + } + +#ifndef SUPERLOOP + { + struct sockaddr_in client; + int block = TRUE; /* flag to block FTP server task */ + ftpsvr * ftp; + + /* loop through ftp structs to see if it's OK to block task */ + for (ftp = ftplist; ftp; ftp = ftp->next) + { + /* The ftp data sending and receiving states can hang if we + * block the thread. If any session is in this state then + * clear the block flag to avoid this. + */ + if ((ftp->state == FTPS_SENDING) || + (ftp->state == FTPS_RECEIVING)) + { + block = FALSE; /* don't block server task */ + break; /* no need to check any more sessions */ + } + } + if (block) /* flag should now be set */ + TK_BLOCK(); /* sleep until a callback wakes us */ + } +#endif /* SUPERLOOP */ + /* nothing to do in the MINI_TCP & SUPERLOOP case since connects + * are callback driven and the superloop will poll us anyway. + */ +#elif defined(BLOCKING_APPS) /* use blocking select to drive server app */ + { + fd_set ftp_fdrecv; + fd_set ftp_fdsend; + ftpsvr *ftp; + int events; /* return from select() */ +#ifndef USE_FDS + int recvs = 0; /* number of entries in recv FD_SET array */ + int sends = 0; +#endif +#ifdef FTP_IDLECONN_TMO + extern int ftps_iotmo; /* idle time in BLOCKING_APPS mode */ +#endif /* FTP_IDLECONN_TMO */ + +#ifdef USE_FDS + FD_ZERO(&ftp_fdrecv); + FD_ZERO(&ftp_fdsend); +#else + MEMSET(&ftp_fdrecv, 0, sizeof(fd_set)); + MEMSET(&ftp_fdsend, 0, sizeof(fd_set)); +#endif /* USE_FDS */ + + /* use the recv array to detect new connections */ + +#ifdef IP_V4 + if (ftps_sock != SYS_SOCKETNULL) + { + FD_SET(ftps_sock, &ftp_fdrecv); +#ifndef USE_FDS + recvs++; +#endif + } +#endif +#ifdef IP_V6 + if (ftps_sock6 != SYS_SOCKETNULL) + { + FD_SET(ftps_sock6, &ftp_fdrecv); +#ifndef USE_FDS + recvs++; +#endif + } +#endif + + /* If no listening sockets, don't bother */ +#ifdef USE_FDS + if (FD_COUNT(&ftp_fdrecv) == 0) + return; +#else + if (recvs == 0) + return; +#endif /* USE_FDS */ + + /* loop through ftp structs building read/write arrays for select */ + for (ftp = ftplist; ftp; ftp = ftp->next) + { + /* add ftp server's open sockets to the FD lists based on + * their state. The server thread will block until one of + * these has activity. + */ +#ifdef USE_FDS + /* error checking is done in FD_SET */ +#else + if ((recvs > FD_SETSIZE) || (sends > FD_SETSIZE)) + { + dtrap(); /* port needs bigger FD_SETSIZE */ + break; /* no point in looping any more */ + } +#endif /* USE_FDS */ + + FD_SET(ftp->sock, &ftp_fdrecv); +#ifndef USE_FDS + recvs++; +#endif + if (ftp->datasock && (ftp->datasock != SYS_SOCKETNULL)) + { + /* always add the data socket to the receive FD_SET */ + FD_SET(ftp->datasock, &ftp_fdrecv); +#ifndef USE_FDS + recvs++; +#endif + /* only add the send socket if we are actively sending */ + if (ftp->state == FTPS_SENDING) + { + FD_SET(ftp->datasock, &ftp_fdsend); +#ifndef USE_FDS + sends++; +#endif + } + } + } /* end of for(ftplist) loop */ + + /* block until one of the sockets has activity */ +#ifndef FTP_IDLECONN_TMO + events = t_select(&ftp_fdrecv, &ftp_fdsend, (fd_set *)NULL, -1); +#else /* do not block idle time, enable inactivity timeout */ + events = t_select(&ftp_fdrecv, &ftp_fdsend, (fd_set *)NULL, + (unsigned long)ftps_iotmo * FTPTPS); +#endif /* FTP_IDLECONN_TMO */ + +#ifdef IP_V4 + if (FD_ISSET(ftps_sock, &ftp_fdrecv)) /* got a connect to server listen? */ + { + ftp_accept(AF_INET, ftps_sock, sizeof(struct sockaddr_in)); + events--; + } +#endif /* IP_V4 */ + +#ifdef IP_V6 + if (FD_ISSET(ftps_sock6, &ftp_fdrecv)) /* got a connect v6 listen? */ + { + ftp_accept(AF_INET6, ftps_sock6, sizeof(struct sockaddr_in6)); + events--; + } +#endif /* IP_V6 */ + + if (events <= 0) /* connect was only socket */ + { + in_ftps_check--; + return; + } + } +#else /* not BLOCKING_APPS, poll non-blocking sockets */ + +#ifdef IP_V4 + if (ftps_sock != SYS_SOCKETNULL) + ftp_accept(AF_INET, ftps_sock, sizeof(struct sockaddr_in)); +#endif /* IP_V4 */ + +#ifdef IP_V6 + if (ftps_sock6 != SYS_SOCKETNULL) + ftp_accept(AF_INET6, ftps_sock6, sizeof(struct sockaddr_in6)); +#endif /* IP_V6 */ + +#endif /* BLOCKING_APPS */ + + /* work on existing conections - data or command */ + ftps_loop(); + + in_ftps_check--; + return; +} + + + + +/* FUNCTION: fs_lookupuser() + * + * fs_lookupuser() lookup a user based on the name. Fill in user + * struct in ftp, including password. If no password required, fill + * in null string. Filled in data is in unencrypted form. This + * particular port is for the user database in ..\misclib\userpass.c + * + * PARAM1: ftpsvr * ftp + * PARAM2: char * username + * + * RETURNS: Returns 0 if user found, else -1 if user invalid. + */ + +int +fs_lookupuser(ftpsvr * ftp, char * username) +{ + int i; + + for (i = 0; i < NUM_NETUSERS; i++) + { + if (users[i].username[0] == 0) + continue; + if (strcmp(users[i].username, username) == 0) + break; + } + + if (i >= NUM_NETUSERS) /* username not found? */ + return -1; + + /* extract username from command */ + strncpy(ftp->user.username, username, FTPMAXUSERNAME); + strncpy(ftp->user.password, users[i].password, FTPMAXUSERPASS); + strcpy(ftp->user.home, "c:\\"); /* default for DOS port */ + return 0; +} + +void delftp(ftpsvr * ftp); + + +/* FUNCTION: ftps_cleanup() + * + * Close down all the connections to FTP Server. Then close the + * socket used for FTP Server listen + * + * PARAM1: void + * + * RETURNS: + */ + +void +ftps_cleanup(void) +{ + ftpsvr * ftp; + ftpsvr * ftpnext; + + ftpnext = ftplist; /* will be set to ftp at top of loop */ + + /* loop throught connection list */ + while (ftpnext) + { + ftp = ftpnext; + ftpnext = ftp->next; + delftp(ftp); /* kill the connection */ + } + +#ifdef IP_V4 + if ( ftps_sock != INVALID_SOCKET ) + { + sys_closesocket(ftps_sock); + ftps_sock = INVALID_SOCKET ; + } +#endif + +#ifdef IP_V6 + if ( ftps_sock6 != INVALID_SOCKET ) + { + sys_closesocket(ftps_sock6); + ftps_sock6 = INVALID_SOCKET ; + } +#endif +} + + +#ifndef SUPERLOOP + +#ifdef FTP_SERVER + +TK_OBJECT(to_ftpsrv); +TK_ENTRY(tk_ftpsrv); +long ftpsrv_wakes = 0; + +/* + * Altera Niche Stack Nios port modification: + * Use task priority and stack size values from ipport.h + */ +struct inet_taskinfo ftpstask = { + &to_ftpsrv, + "FTP server", + tk_ftpsrv, + TK_FTPSRVR_TPRIO, + TK_FTPSRVR_SSIZE, +}; + + +/* The application thread works on a "controlled polling" basis: + * it wakes up periodically and polls for work. If there is outstanding + * work, the next wake is accellerated to give better performance under + * heavy loads. + * + * The FTP task could aternativly be set up to use blocking sockets, + * in which case the loops below would only call the "xxx_check()" + * routines - suspending would be handled by the TCP code. + */ + +/* FUNCTION: tk_ftpsrv() + * + * PARAM1: n/a + * + * RETURNS: n/a + */ + +TK_ENTRY(tk_ftpsrv) +{ + int e; + + while (!iniche_net_ready) + TK_SLEEP(1); + + e = ftps_init(); + if (e) + TK_RETURN_ERROR(); + exit_hook(ftps_cleanup); + + for (;;) + { + ftps_check(); /* may block on select */ +#ifndef BLOCKING_APPS + tk_yield(); /* give up CPU if it didn't block */ +#else +#ifdef MINI_TCP + tk_yield(); /* give up CPU, MINI_TCP doesn't select() */ +#endif /* MINI_TCP */ +#endif /* BLOCKING_APPS */ + ftpsrv_wakes++; /* count wakeups */ + if (net_system_exit) + break; + } + TK_RETURN_OK(); +} + +#endif /* FTP_SERVER */ + +#endif /* SUPERLOOP */ + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsrv.c b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsrv.c new file mode 100644 index 0000000..969b47d --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsrv.c @@ -0,0 +1,2061 @@ +/* + * FILENAME: ftpsrv.c + * + * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved + * + * + * MODULE: FTPSERVER + * + * ROUTINES: ftps_connection(), ftpputs(), ftp_getcmd(), + * ROUTINES: ftp_flushcmd(), ftps_loop(), newftp(), delftp(), ftps_user(), + * ROUTINES: ftps_password(), ftp_cmdpath(), ftp_make_filename() + * ROUTINES: ftp_leave_passive_state(), ftps_do_pasv(), ftps_cmd(), + * + * PORTABLE: yes + */ + + +#include "ftpport.h" /* TCP/IP, sockets, system info */ +#include "ftpsrv.h" /* FTP server includes */ + +static u_long max_ftps_conn = MAX_FTPS_SESS; + +u_long ftps_connects = 0; /* TCP connections tocmd port */ +u_long ftps_sessions = 0; /* user & password OK */ +u_long ftps_badauth = 0; /* user or password badK */ +u_long ftps_txfiles = 0; /* total data files sent */ +u_long ftps_rxfiles = 0; /* total data files received */ +u_long ftps_txbytes = 0; /* total data bytes received */ +u_long ftps_rxbytes = 0; /* total data bytes sent */ +u_long ftps_dirs = 0; /* total directory operations done */ + +/* ftp server internal routines: */ +static int ftp_getcmd(ftpsvr * ftp); +static void ftp_flushcmd(ftpsvr * ftp); + +ftpsvr * newftp(void); +void delftp(ftpsvr * ftp); +int ftps_user(ftpsvr * ftp); +int ftps_password(ftpsvr * ftp); +int ftps_cmd(ftpsvr * ftp); +int ftp_sendfile(ftpsvr * ftp); +int ftp_getfile(ftpsvr * ftp); +void ftp_xfercleanup(ftpsvr * ftp); + +/* common FTP server reply tokens */ +char * ftp_cmdok = "200 Command OK\r\n"; +char * ftp_ready = "220 Service ready\r\n"; +char * ftp_needpass= "331 User name ok, need password\r\n"; +char * ftp_loggedin= "230 User logged in\r\n"; +char * ftp_fileok = "150 File status okay; about to open data connection\r\n"; +char * ftp_closing = "226 Closing data connection, file transfer successful\r\n"; +char * ftp_badcmd = "500 Unsupported command\r\n"; +char * ftp_noaccess= "550 Access denied\r\n"; + +ftpsvr * ftplist = NULL; /* master list of FTP connections */ + +int notfatal = 0; /* unfatal error handling */ + +/* ftp server timeouts, left as globals for app overrides: */ +int ftps_iotmo = 120; /* Idle timeout during IO activity */ +int ftps_lotmo = 60; /* Idle timeout during logins */ + +#ifdef FTP_IDLECONN_TMO +int ftps_conntmo = 0; /* connection idle timeout, 0==no timeout */ +#endif + + +/* if x is an upper case letter, this evaluates to x, + * if x is a lower case letter, this evaluates to the upper case. + */ +#define upper_case(x) ((x) & ~0x20) + +u_short listcmds = 0; /* number of LIST or DIR commands */ + +#ifndef SUPERLOOP +extern TK_OBJECT(to_ftpsrv); +#endif + + +/* FUNCTION: ftps_connection() + * + * ftps_connection() - Called whenever we have accepted a connection + * on the FTP server listener socket. The socket passed will stay + * open until we close it. + * + * PARAM1: WP_SOCKTYPE sock + * + * RETURNS: Returns ftpsvr pointer if OK, else NULL + */ + +ftpsvr * +ftps_connection(SOCKTYPE sock) +{ + ftpsvr * ftp; + int e; + + ftps_connects++; /* count connections */ + + /* check if we have exceeded the maximum number of connections */ + if ((max_ftps_conn > 0) && (ftps_connects > max_ftps_conn)) + { + ftps_connects--; + t_socketclose(sock); + return NULL; + } + + /* create new FTP connection */ + if ((ftp = newftp()) == (ftpsvr *)NULL) + { + ftps_connects--; + t_socketclose(sock); + return NULL; + } + + /* set the default data port we will connect to for data transfers + * to be the same as the port that the client connected with just + * in case we connect to a client that doesn't send PORT commands. + * see section 3.2 ESTABLISHING DATA CONNECTIONS in RFC 959 for a + * description of this, keeping in mind that what we are doing + * here is setting the default "user-process data port". + * + * note that t_getpeername() can in theory fail, but its not clear + * what we could do at this point to recover if it did and it only + * makes a difference if we connect to clients that don't send + * PORT commands anyway, so just use whatever port that we get back + */ + ftp->dataport = SO_GET_FPORT(sock); + + ftp->sock = sock; /* remember client socket */ + ftp->state = FTPS_CONNECTING; + e = t_send(ftp->sock, ftp_ready, strlen(ftp_ready), 0); + if (e == -1) /* did connection die already? */ + { + dtrap(); + delftp(ftp); + return NULL; + } + + return ftp; +} + + + +/* FUNCTION: ftpputs() + * + * ftpputs() - put a string to an ftp command socket. + * + * PARAM1: ftpsvr * ftp + * PARAM2: char * text + * + * RETURNS: Retuns 0 if OK -1 if error. ftpsvr is deleted on error. + */ + +int +ftpputs(ftpsvr * ftp, char * text) +{ + int bytes_to_send; + int bytes_sent; + int rc; + + bytes_to_send = strlen(text); + for (bytes_sent = 0; bytes_to_send > 0; ) + { + rc = t_send(ftp->sock, text + bytes_sent, bytes_to_send, 0); + if (rc < 0) + { + rc = t_errno(ftp->sock); + dtrap(); /* show errors to programmer */ + ftp->state = FTPS_CLOSING; + return -1; + } + bytes_to_send -= rc; + bytes_sent += rc; + if (bytes_to_send > 0) + tk_yield(); + } + /* bytes_to_send should end up 0 */ + if (bytes_to_send < 0) + { + dtrap(); + } + return 0; +} + +#define FTP_HASCMD 1 +#define FTP_NOCMD 2 +#define FTP_ERROR 3 + + + +/* FUNCTION: ftp_getcmd() + * + * ftp_getcmd() - Get a command from the ftp command stream. Trys to + * read more data from a ftp client sock until a command is buffered. + * + * PARAM1: ftpsvr * ftp + * + * RETURNS: FTP_HASCMD if a command is ready at ftp->cmdbuf, else + * FTP_NOCMD if a command is not ready, or FTP_ERROR if there's a + * serious data problem. If FTP_HASCMD is returned and the caller + * processes the command, he should call ftp_flushcmd() so the + * command doen't get processed again. + */ + +static int +ftp_getcmd(ftpsvr * ftp) +{ + int readval; + int e; + char * cp; + + /* if we filled up the input buffer on the last pass and there was + no CRLF terminating a command in any of it */ + if (ftp->cmdbuflen >= (CMDBUFSIZE - 1)) + { + /* the input is bogus so discard it */ + ftp->cmdbuflen = 0; + } + + /* read as much data as will fit into the command buffer, leaving + * room for the NULL that we are going to insert following the + * first CRLF, below + */ + + readval = t_recv(ftp->sock, (ftp->cmdbuf + ftp->cmdbuflen), + (CMDBUFSIZE - ftp->cmdbuflen - 1), 0); + + if (readval == 0) + ftp->state = FTPS_CLOSING; + + if (readval < 0) /* error on socket? */ + { + e = t_errno(ftp->sock); + if (e != EWOULDBLOCK) + { + /* let programmer see errors */ + dprintf("ftpsvr cmd socket error %d\n", e); + delftp(ftp); /* thats the end of this connection... */ + return FTP_ERROR; /* error return */ + } + else /* no command ready */ + return FTP_NOCMD; + } + ftp->cmdbuflen += readval; /* add read data to hp */ + + if (ftp->cmdbuflen == 0) /* nothing in buffer? */ + return FTP_NOCMD; + + ftp->lasttime = ftpticks; /* this is activity; rest timeout */ + + cp = strstr(ftp->cmdbuf, "\r\n"); /* look for trailing CRLF */ + if (cp) /* look for trailing CRLF */ + { + char * src; + char * dst; + + /* point to first byte following the CRLF */ + cp += 2; + /* if there's not already a null there */ + if (*cp) + { + /* move all the characters following the CRLF up one so we got + room to insert a null to terminate the command after the CRLF */ + /* note we do this here because some of the later code paths + treat the command like an ASCIIZ string */ + dst = ftp->cmdbuf + ftp->cmdbuflen; + src = dst - 1; + while (src >= cp) + *dst-- = *src--; + /* increment the number of characters in the command buffer to + account for the NULL */ + ftp->cmdbuflen++; + /* NULL terminate the command */ + *cp = 0; + } + + /* now, flip the characters at the beginning of the buffer that + * could be an FTP command from lower to upper case since + * the protocol's supposed to be case insensitive * + * + * we look at at most the first 4 bytes since no commands + * are more than 4 bytes long + */ + + for (dst = ftp->cmdbuf; dst < (ftp->cmdbuf + 4); ++dst) + { + /* upper case, leave as is */ + if ((*dst >= 'A') && (*dst <= 'Z')) + continue; + /* lower case gets flipped to upper */ + if ((*dst >= 'a') && (*dst <= 'z')) + { + *dst = (char) (*dst + (char) ('A' - 'a')); + continue; + } + /* anthing else means we got to end of command so break */ + break; + } + return FTP_HASCMD; /* Got command */ + } + else + return FTP_NOCMD; /* NO command */ +} + + + +/* FUNCTION: ftp_flushcmd() + * + * PARAM1: ftpsvr * ftp + * + * RETURNS: + */ + +static void +ftp_flushcmd(ftpsvr * ftp) +{ + char * cp; + int old_cmd_len; + int rest_of_cmds_len; + + /* find command terminating CRLF */ +ff_again: + cp = strstr(ftp->cmdbuf, "\r\n"); + if (!cp) + { + /* might be clobbered CR at end of path (see CWD code) */ + if ( (unsigned)strlen(ftp->cmdbuf) < ftp->cmdbuflen) + { + ftp->cmdbuf[strlen(ftp->cmdbuf)] = '\r'; /* put back CR */ + goto ff_again; + } + dtrap(); /* prog error */ + return; + } + + /* cp now points to a CRLF followed by the NULL we inserted in + * ftp_getcmd(), so if theres data in the buffer following the + * NULL, then its the beginning of the next command + */ + /* point to where next comamnd will be if its there */ + cp += 3; + /* compute the length of the old command */ + old_cmd_len = cp - ftp->cmdbuf - 1; + + /* compute the length of the rest of the commands in the buffer */ + /* that's the number of bytes that had been read into the buffer, + * less the length of the old command less 1 for the NULL that + * we inserted to null terminate the old command + */ + rest_of_cmds_len = ftp->cmdbuflen - old_cmd_len - 1; + + /* this will happen if we didn't insert a null after the command + * because there was one there already, which will be the case + * when the old command is the only data that's been read so far, + * in which case the length of the rest of the commands is 0 + */ + + if (rest_of_cmds_len < 0) + rest_of_cmds_len = 0; + + /* if there are any other commands left in the buffer */ + if (rest_of_cmds_len) + { + /* move them to the front of the buffer */ + MEMCPY(ftp->cmdbuf,cp,rest_of_cmds_len); + } + + /* zero the data following rest of the commands for the length of + * the old command or else you risk finding command termination + * sequences when none have been received + */ + /* if there are no other commands, this zeroes the old command + from the buffer */ + MEMSET(ftp->cmdbuf + rest_of_cmds_len,0,old_cmd_len + 1); + + ftp->cmdbuflen = rest_of_cmds_len; +} + + + + +/* FUNCTION: ftps_loop() + * + * PARAM1: + * + * RETURNS: + */ + +void +ftps_loop() +{ + ftpsvr * ftp; + ftpsvr * ftpnext; + int cmdready; + int e; /* error holder */ + +#ifndef MINI_TCP + struct sockaddr client; /* for BSDish accept() call */ + int clientsize; + SOCKTYPE data_sock; /* socket for passive accept */ +#endif + + ftpnext = ftplist; /* will be set to ftp at top of loop */ + + /* loop throught connection list */ + while (ftpnext) + { + ftp = ftpnext; + ftpnext = ftp->next; /* remember next in case ftp is deleted */ + if (ftp->inuse) /* if we are blocked in guts, quit */ + continue; + ftp->inuse++; /* set reentry flag */ + e = 0; /* clear error holder */ + /* see if a command is ready */ + cmdready = ftp_getcmd(ftp); + if (cmdready == FTP_ERROR) + continue; + + switch (ftp->state) + { + case FTPS_CONNECTING: + case FTPS_NEEDPASS: + /* check for shorter session timeout in these states */ + if (ftp->lasttime + ((unsigned long)ftps_lotmo * FTPTPS) < ftpticks) + { + e = -1; /* set flag to force deletion of ftps */ + break; + } + if (cmdready != FTP_HASCMD) + break; + if (ftp->state == FTPS_CONNECTING) + e = ftps_user(ftp); + else + e = ftps_password(ftp); + break; + case FTPS_LOGGEDIN: + /* connection timeouts like this are really obnoxious and should + * be disabled usless there is some compling reason your target + * should do otherwise (like dialup charges). + */ +#ifdef FTP_IDLECONN_TMO + /* see if session has been idle for too long */ + if((ftps_conntmo > 0) && + (ftp->lasttime + ((unsigned long)ftps_conntmo * FTPTPS) < ftpticks)) + { + dprintf("ftpsrv: timout of idle FTP session\n"); + delftp(ftp); + break; + } +#endif /* FTP_IDLECONN_TMO */ + + if (cmdready == FTP_HASCMD) + e = ftps_cmd(ftp); + /* if we are in passive mode and the client hasn't connected yet */ + if (ftp->passive_state == FTPS_PASSIVE_MODE) + { + /* check to see if the client connected */ +#ifndef MINI_TCP + + /* Accept for either V4 or V6 + */ + data_sock = SYS_SOCKETNULL; +#ifdef IP_V6 + if (LONG2SO(ftp->datasock)->so_domain == AF_INET6) + { + struct sockaddr_in6 cli6; + char ipv6WrkBuffer[60]; + + clientsize = sizeof(struct sockaddr_in6); + data_sock = t_accept(ftp->datasock, &cli6, &clientsize); + } +#endif /* IP_V6 */ + +#ifdef IP_V4 + if (LONG2SO(ftp->datasock)->so_domain == AF_INET) + { + clientsize = sizeof(struct sockaddr_in); + data_sock = t_accept(ftp->datasock, &client, &clientsize); + } +#endif /* IP_V4 */ + + /* if client didn't connect, break to continue */ + if (data_sock == SYS_SOCKETNULL) + break; + /* client connected, so close listening socket so we wont take + * any more connections to it. + */ + t_socketclose(ftp->datasock); + + /* the data socket we care about is now the actual connection + * to the client. + */ + ftp->datasock = data_sock; + +#else /* mini sockets */ + /* mini-sockets sets data_sock in a callback. If client + * didn't connect yet, break to continue. + */ + if(ftp->datasock->state & SS_ISCONNECTED == 0) + break; +#endif + /* change our passive state so that we know we are connected + to the client on the data socket */ + ftp->passive_state |= FTPS_PASSIVE_CONNECTED; + /* if we have already received our data transfer command */ + if (ftp->passive_cmd) + { + /* then do the command */ + IN_PROFILER(PF_FTP, PF_ENTRY); + switch (ftp->passive_cmd) + { + case 0x4c495354: /* "LIST" */ + case 0x4e4c5354: /* "NLST" */ + if (fs_dodir(ftp, ftp->passive_cmd)) + ftpputs(ftp, "451 exec error\r\n"); + break; + case 0x52455452: /* "RETR" */ + ftp_sendfile(ftp); + break; + case 0x53544f52: /* "STOR" */ + ftp_getfile(ftp); + break; + /* there is a serious logic error someplace */ + default : + dprintf("invalid passive_cmd\n"); + dtrap(); + } + IN_PROFILER(PF_FTP, PF_EXIT); + } + } + break; + case FTPS_RECEIVING: /* task suspended while doing IO */ + case FTPS_SENDING: + /* check for shorter session timeout in these states */ + if (ftp->lasttime + ((unsigned long)ftps_iotmo * FTPTPS) < ftpticks) + { + e = -1; /* set flag to force deletion of ftps */ + break; + } + IN_PROFILER(PF_FTP, PF_ENTRY); + if (ftp->state == FTPS_SENDING) + e = ftp_sendfile(ftp); + else /* must be receiving */ + e = ftp_getfile(ftp); + IN_PROFILER(PF_FTP, PF_EXIT); + +#ifndef SUPERLOOP + /* If not superloop and there is still more data to move, + * then make sure ftp server will wake up to finish the + * send/receive later. The the transfer finished, the ftps + * state will have returned to LOGGEDIN. + */ + if(ftp->state != FTPS_LOGGEDIN) + TK_WAKE(&to_ftpsrv); /* make sure we come back later */ +#endif + break; + case FTPS_CLOSING: + break; + default: /* bad state? */ + dtrap(); + break; + } + /* if fatal error or connection closed */ + /* if (e == 452) + { + ftp->state = FTPS_LOGGEDIN; + ftp_flushcmd(ftp); + ftp->inuse--; + } */ + if (e || (ftp->state == FTPS_CLOSING)) + delftp(ftp); + else + ftp->inuse--; /* set reentry flag */ + } +} + + + +/* FUNCTION: newftp() + * + * newftp() - create a new ftpsvr structure. Put in master queue. + * + * PARAM1: + * + * RETURNS: + */ + +ftpsvr * +newftp() +{ + ftpsvr * ftp; + + ftp = (ftpsvr *)FTPSALLOC(sizeof(ftpsvr)); + if (!ftp) + return NULL; + ftp->next = ftplist; + ftp->lasttime = ftpticks; + ftplist = ftp; + + /* make sure we have a valid domain */ +#if defined(IP_V4) || defined(MINI_IP) + ftp->domain = AF_INET; /* default to IPv4 */ +#else + ftp->domain = AF_INET6; +#endif + return(ftp); +} + + + +/* FUNCTION: delftp() + * + * PARAM1: ftpsvr * ftp + * + * RETURNS: + */ + +void +delftp(ftpsvr *ftp) +{ + ftpsvr *list; + ftpsvr *last; + + last = NULL; + for (list = ftplist; list; list = list->next) + { + if (list == ftp) + { + /* found server to kill, unlink: */ + if (last) + last->next = list->next; + else + ftplist = list->next; + + if (ftp->sock) + { + t_socketclose(ftp->sock); + ftp->sock = 0; + } + if (ftp->datasock) + { + t_socketclose(ftp->datasock); + ftp->datasock = 0; + } + +#ifdef TCP_ZEROCOPY + /* don't orphan any packets we may have stored in ftpsq */ + while (ftp->ftpsq.q_len > 0) + tcp_pktfree ((PACKET)getq(&ftp->ftpsq) ); +#endif /* TCP_ZEROCOPY or not */ + + FTPSFREE(ftp); + ftps_connects--; /* decrement connection count */ + break; + } + last = list; + } +} + + + +/* the ftps_ server command handler routines. These are called when a + * command is received in the ftp->cmdbuf. Which one is called + * depends in the session state. These all process a command, maybe + * change the state, (or kill the session) and flush the command. All + * return 0 if OK (which may mean pending work) or negative error + * code if a fatal error was detected. + */ + + + +/* FUNCTION: ftps_user() + * + * ftps_user() - called when we get a command in the initial state + * + * PARAM1: ftpsvr * ftp + * + * RETURNS: + */ + +int +ftps_user(ftpsvr * ftp) +{ + char * cp; + int e; + + /* make sure client's telling me about a user */ + if (MEMCMP(ftp->cmdbuf, "USER", 4) != 0) + { + ftpputs(ftp, ftp_badcmd); + return -1; /* signal main loop to kill session */ + } + cp = strstr(ftp->cmdbuf, "\r\n"); + if (!cp) + { + dtrap(); + return -1; /* signal main loop to kill session */ + } + *cp = 0; /* NULL terminate user name */ + + /* search user list */ + e = fs_lookupuser(ftp, &ftp->cmdbuf[5]); + *cp = '\r'; /* put back buffer char we clobbered */ + if (e) + { + ftp->state = FTPS_CONNECTING; + ftpputs(ftp, "530 Invalid user\r\n"); + ftp_flushcmd(ftp); + return 0; /* user not valid */ + } + + ftp->cwd[0] = FTP_SLASH; + ftp->cwd[1] = 0; +#ifdef DRIVE_LETTERS + strcpy(ftp->drive, DEFAULT_DRIVE); +#endif /* DRIVE_LETTERS */ + ftp->type = FTPTYPE_ASCII; /* RFC says make text the defaul type */ + + + if (ftp->user.password[0] == '\0') /* no password required? */ + { + ftpputs(ftp, ftp_loggedin); + ftp->state = FTPS_LOGGEDIN; + ftps_sessions++; + } + else /* require a password */ + { + ftpputs(ftp, ftp_needpass); /* message to client */ + ftp->state = FTPS_NEEDPASS; /* set proper state */ + } + ftp_flushcmd(ftp); + return 0; +} + + + +/* FUNCTION: ftps_password() + * + * ftps_password() - called when we get a command in the + * FTPS_NEEDPASS state. + * + * PARAM1: ftpsvr * ftp + * + * RETURNS: Returns 0 if OK (which may mean pending work) + * or negative error code if a fatal error was detected. + */ + +int +ftps_password(ftpsvr * ftp) +{ + char * password; + char * cp; + + if (MEMCMP(ftp->cmdbuf, "PASS", 4) != 0) + { + ftpputs(ftp, ftp_badcmd); + return -1; /* signal main loop to kill session */ + } + password = &ftp->cmdbuf[5]; + cp = strstr(password, "\r\n"); /* find end of command */ + if (!cp) /* require whole command to be in buffer */ + return -1; /* signal main loop to kill session */ + + *cp = 0; /* NULL terminate */ + /* password '*' means we accept any password, so don't even compare */ + if (ftp->user.password[0] != '*') + { + if (strcmp(password, ftp->user.password) != 0) + { + ftp->state = FTPS_CONNECTING; + ftpputs(ftp, "530 Invalid password\r\n"); + + if (ftp->logtries++ > 2) + return -1; /* too many failed logins, kill session */ + else + { + ftp_flushcmd(ftp); + return 0; /* wait for another user/pass try */ + } + } + } + ftpputs(ftp, ftp_loggedin); /* login OK, set up session */ + ftp->state = FTPS_LOGGEDIN; + ftps_sessions++; + ftp_flushcmd(ftp); + return 0; +} + + + +/* FUNCTION: ftp_cmdpath() + * + * ftp_getpath() - extract path from an FTP command in C string form. + * The returned pointer is to the ftp->cmdbuf area. + * + * PARAM1: ftpsvr * ftp + * + * RETURNS: Returns NULL on any error after sending complain + * string to client. + */ + +char * +ftp_cmdpath(ftpsvr * ftp) +{ + char * cp; + + cp = strchr(&ftp->cmdbuf[4], '\r'); + if (!cp) + { + ftpputs(ftp, "501 garbled path\r\n"); + return NULL; + } + *cp = 0; /* null terminate path in buffer */ + cp = &ftp->cmdbuf[4]; + while (*cp == ' ') cp++; /* bump past spaces */ + if (strlen(cp) > FTPMAXPATH) + { + ftpputs(ftp, "553 path too long\r\n"); + return NULL; + } + return cp; +} + + + +/* FUNCTION: ftp_make_filename() + * + * create a complete file name and path from the file specification + * in the command buffer and the cwd associated with the current ftp + * session. allow_empty_filespec specifies whether a file + * specification is required (as is the case with RETR and STOR) or + * whether it is optional (as is the case with NLST and LIST). + * + * PARAM1: ftpsvr *ftp + * PARAM2: int allow_empty_filespec + * + * RETURNS: TRUE if success, FALSE if some error occurred + */ + +int ftp_make_filename(ftpsvr *ftp,int allow_empty_filespec) +{ + char *cp; + char *cp1; + int relative_path; + + cp = ftp_cmdpath(ftp); + if(!cp) return FALSE; /* ftp_cmdpath() already sent error */ + + /* if there is no file spec in the command buffer and one is + required, xmit error response and fail function */ + if(!(*cp) && !allow_empty_filespec) + { + ftpputs(ftp, "501 bad path\r\n"); + return FALSE; + } + + /* if the file spec is too long, xmit error response and fail */ + if(strlen(cp) > FTPMAXPATH) + { + ftpputs(ftp, "552 Path/name too long\r\n"); + return FALSE; + } + lslash(cp); + + /* assume the path specified is not a relative path */ + relative_path = FALSE; + + /* working pointer to file name */ + cp1 = ftp->filename; + +/* if this target system deals with DOS drive letters */ +#ifdef DRIVE_LETTERS + /* if the client specified path contains a colon in the right place */ + if (*cp && (*(cp + 1) == ':')) + { + /* copy the drive: to the beginning of the filename */ + *cp1++ = (char) upper_case(*cp); + *cp1++ = ':'; + + /* if the specified drive is the same as the current drive + and the client specified path does not start at the root */ + if ((upper_case(*cp) == upper_case(ftp->drive[0])) && + (*(cp + 2) != FTP_SLASH)) + { + /* then its a relative path */ + relative_path = TRUE; + } + + /* bump past drive and colon in client path */ + cp += 2; + } + /* client path does not contain a drive spec */ + else + { + /* so use the current drive */ + *cp1++ = ftp->drive[0]; + *cp1++ = ':'; + /* if client path does not start at the root */ + if (*cp != FTP_SLASH) + { + /* its a relative path */ + relative_path = TRUE; + } + } +#else /* DRIVE_LETTERS */ + /* target system is fortunate enough to not have to deal + with DOS drive letters */ + + /* if client path does not start at root */ + if (*cp != FTP_SLASH) + { + /* else its a relative path */ + relative_path = TRUE; + } +#endif /* DRIVE_LETTERS */ + + /* if the client specified path is not relative */ + if (!relative_path) + { + /* in this case, cp now points to past any drive info in + the path provided by the client and cp1 now points to past + any drive info in the constructed file name */ + /* if the path provided by the client isn't absolute, append + a slash to the constructed file name. note this can happen + if the client specified a drive other than the default */ + if (*cp != FTP_SLASH) + *cp1++ = FTP_SLASH; + /* append client path to our constructed file name */ + strcpy(cp1,cp); + } + /* the client specified path was relative */ + else + { + /* copy current working directory to file name (following + any drive letter stuff that might have been added above) */ + strcpy(cp1, ftp->cwd); + cp1 = &ftp->filename[strlen(ftp->filename)-1]; /* point to end */ + + /* if ftp->cwd is not terminated with a slash and the file spec + is not empty, append a slash */ + if ((*cp1 != FTP_SLASH) && *cp) + { + ++cp1; /* increment ptr past last character to NULL */ + *cp1++ = FTP_SLASH; + *cp1 = 0; + } + + /* make sure the concatenation of the specified file name to + the current working directory wont be too big for the + file name field */ + if ((strlen(ftp->filename) + strlen(cp)) >= sizeof(ftp->filename)) + { + ftpputs(ftp,"501 file name too long\r\n"); + return FALSE; + } + + /* concatenate the file spec from the command line to the + current working directory */ + strcat(ftp->filename, cp); + } + + return TRUE; /* function succeeded */ +} + + +/* FUNCTION: ftp_leave_passive_state() + * + * this function is called to make the session leave passive state + * + * PARAM1: ftpsvr *ftp + * + * RETURNS: + */ + +void ftp_leave_passive_state(ftpsvr * ftp) +{ + /* there's a little confusion about whether this field is 0 or + * -1 when the socket is unactive, so check for both + */ + if ((ftp->datasock != SYS_SOCKETNULL) && (ftp->datasock != 0)) + t_socketclose(ftp->datasock); + ftp->datasock = 0; + /* we aren't in passive mode anymore */ + ftp->passive_state = 0; + /* no data transfer command received while in passive state */ + ftp->passive_cmd = 0; + ftp->server_dataport = 0; +} + + + +/* FUNCTION: ftps_do_pasv() + * + * handle IPv4 PASV command + * + * Called when the client requests a transfer in "passive" mode. + * + * PARAM1: ftpsvr *ftp + * + * RETURNS: + */ + +#ifdef IP_V4 +void ftps_do_pasv(ftpsvr * ftp) +{ + /* do_pasv() may re-enter if the client sends us a PASV while we + * are transfering a file. This is an error on the client's part. + * Its not clear that this can happen given the way the + * main state machine works, but check for it just in case + */ + if (ftp->passive_state & FTPS_PASSIVE_CONNECTED) + { + ftpputs(ftp,"425 Data transfer already in progress\r\n"); + return; + } + + /* This will happen if the client had sent us a PASV and then sent + * us another one without an intervening data transfer command. + */ + if (ftp->passive_state & FTPS_PASSIVE_MODE) + { + ftp_leave_passive_state(ftp); + } + + /* call sockets routine to do passive open */ + ftps_v4pasv(ftp); + + /* we are now in passive mode, but the client hasn't connected yet */ + ftp->passive_state = FTPS_PASSIVE_MODE; + + /* we haven't received a data transfer command from the client yet */ + ftp->passive_cmd = 0; +} +#endif /* IP_V4 */ + + + +/* FUNCTION: ftps_cmd() + * + * called when we get a command in the FTPS_LOGGEDIN state + * + * PARAM1: ftpsvr * ftp + * + * RETURNS: Returns 0 if OK, else ftp error. + */ + +int +ftps_cmd(ftpsvr * ftp) +{ + int i; /* scratch for command processing */ + char * cp; + char * cp1; + u_long lparm; /* scratch, for parameter extraction */ + u_short sparm; /* "" */ + u_long ftpcmd; /* 4 char command as number for fast switching */ + int relative_path; + + ftpcmd = 0L; + /* copy 4 bytes of ftp cmd text into local long value, replacing + unprintable chars with blanks */ + for (i = 0; i < 4; i++) + { + if (ftp->cmdbuf[i] >= ' ') + ftpcmd = (ftpcmd << 8) | ftp->cmdbuf[i]; + else /* space over unprintable characters */ + ftpcmd = (ftpcmd << 8) | ' '; + } + + /* switch on command */ + switch (ftpcmd) + { + case 0x53595354: /* "SYST" */ + /* see what Netscape does with this */ + ftpputs(ftp, "215 UNIX system type\r\n"); + break; + case 0x54595045: /* "TYPE" */ + if ((ftp->cmdbuf[5] == 'A') || (ftp->cmdbuf[5] == 'a')) + ftp->type = FTPTYPE_ASCII; + else /* we default all other types to binary */ + ftp->type = FTPTYPE_IMAGE; + ftpputs(ftp, ftp_cmdok); + break; + case 0x50574420: /* "PWD " */ + sprintf(ftp->filebuf, "257 \"%s\"\r\n", uslash(ftp->cwd)); + lslash(ftp->cwd); + ftpputs(ftp, ftp->filebuf); + break; + case 0x58505744: /* "XPWD" */ + sprintf(ftp->filebuf, "257 \"%s%s\"\r\n", DRIVE_PTR(ftp), ftp->cwd); + ftpputs(ftp, ftp->filebuf); + break; + case 0x55534552: /* "USER" */ + return(ftps_user(ftp)); + case 0x504f5254: /* PORT */ + cp = &ftp->cmdbuf[5]; /* point to IP address text */ + lparm = 0L; + for (i = 3; i >= 0; i--) /* extract 4 digit IP address */ + { + lparm |= (((u_long)atoi(cp)) << (i*8)); + cp = strchr(cp, ','); /* bump through number to comma */ + if (!cp) /* must be comma delimited */ + { + ftpputs(ftp,"501 invalid PORT command\r\n"); + break; + } + cp++; /* point to next digit */ + } + /* the C break key word really needs a parameter so constructs + * like this aren't necessary, anyway, if this is true, its + * because we broke out of the above for on an error and we + */ + if (!cp) + break; + sparm = (u_short)atoi(cp) << 8; + while (*cp >= '0')cp++; /* bump through number */ + if (*cp != ',') /* must be comma delimited */ + { + ftpputs(ftp,"501 invalid PORT command\r\n"); + break; + } + cp++; /* point to next digit */ + sparm |= atoi(cp); + + /* this will happen if the client sends us a PORT while we are + * transfering a file. this is an error on the client's part, + */ + /* actually, its not clear that this can happen given the way the + main state machine works, but check for it just in case */ + if (ftp->passive_state & FTPS_PASSIVE_CONNECTED) + { + ftpputs(ftp,"425 Data transfer already in progress\r\n"); + break; + } + /* this will happen if the client had sent us a PASV and then + * sent us a PORT without an intervening data transfer command. + */ + if (ftp->passive_state & FTPS_PASSIVE_MODE) + { + ftp_leave_passive_state(ftp); + } + + ftp->host = lparm; + ftp->dataport = sparm; + ftpputs(ftp, ftp_cmdok); + break; + case 0x51554954: /* QUIT" */ + /* if we don't have a file transfer going, kill sess now */ + if ((ftp->state != FTPS_SENDING) && (ftp->state != FTPS_RECEIVING)) + { + ftpputs(ftp, "221 Bye\r\n"); /* session terminating */ + ftp->state = FTPS_CLOSING; + /* delftp(ftp); */ + return -1; /* signal main loop to kill session */ + } + else + return 0; /* return without flushing QUIT */ + case 0x43574420: /* "CWD " */ + /* note the intent here is to end up with the client supplied + * drive string (as in "c:") in the drive field, and the client + * supplied current working directory, without any drive spec, + * in the cwd field. to this end we construct the fully + * qualified path, including the drive in the filename field + * which will + */ + cp = ftp_cmdpath(ftp); + if (!cp) break; + lslash(cp); /* convert slashes to local */ + + /* assume the path specified is not a relative path */ + relative_path = FALSE; + + /* point to beginning of file name */ + cp1 = ftp->filename; + + /* if this target system deals with DOS drive letters */ +#ifdef DRIVE_LETTERS + /* if the client specified path contains a colon in the right place */ + if (*cp && (*(cp + 1) == ':')) + { + /* copy the drive: to the beginning of the filename */ + *cp1++ = (char) upper_case(*cp); + *cp1++ = ':'; + + /* if the specified drive is the same as the current drive + and the client specified path does not start at the root */ + if ((upper_case(*cp) == upper_case(ftp->drive[0])) && + (*(cp + 2) != FTP_SLASH)) + { + /* then its a relative path */ + relative_path = TRUE; + } + + /* bump past drive and colon in client path */ + cp += 2; + } + /* client path does not contain a drive spec */ + else + { + /* so use the current drive */ + *cp1++ = ftp->drive[0]; + *cp1++ = ':'; + /* if client path does not start at the root */ + if (*cp != FTP_SLASH) + { + /* its a relative path */ + relative_path = TRUE; + } + } +#else /* DRIVE_LETTERS */ + /* target system is fortunate enough to not have to deal + with DOS drive letters */ + /* if client path does not start at root */ + if (*cp != FTP_SLASH) + { + /* else its a relative path */ + relative_path = TRUE; + } +#endif /* DRIVE_LETTERS */ + + /* if the client specified path is not relative */ + if (!relative_path) + { + /* in this case, cp now points to past any drive info in the + * path provided by the client and cp1 now points to past + * + * if the path provided by the client isn't absolute, append + * a slash to the constructed file name. note this can + * happen + */ + if (*cp != FTP_SLASH) + *cp1++ = FTP_SLASH; + strcpy(cp1,cp); + } + /* the client specified path was relative */ + else + { + /* copy current working directory to file name (following + any drive letter stuff that might have been added above) */ + strcpy(cp1, ftp->cwd); /* copy cwd for change */ + cp1 = ftp->filename + strlen(ftp->filename); /* start at end */ + while (*cp) + { + if (*cp == '.' && *(cp+1) == '.') /* double dot? */ + { /* back up 1 level */ + if (strlen(ftp->cwd) < 2) /* make sure we have room */ + { + ftpputs(ftp, "550 Bad path\r\n"); + ftp_flushcmd(ftp); + return 0; /* not a fatal error */ + } + /* null out last directory level */ + while (*cp1 != FTP_SLASH && cp1 > ftp->filename) + *cp1-- = 0; +#ifdef DRIVE_LETTERS + if (cp1 > (ftp->filename + 2)) +#else /* DRIVE_LETTERS */ + if(cp1 > ftp->filename) /* if not at root... */ +#endif /* DRIVE_LETTERS */ + *cp1 = 0; /* null over trailing slash */ + cp += 2; /* bump past double dot */ + } + else if(*cp == FTP_SLASH) /* embedded slash */ + cp++; /* just skip past it */ + else /* got a dir name, append to new path */ + { + if(*(cp1-1) != FTP_SLASH) /* if not at top... */ + *cp1++ = FTP_SLASH; /* add the slash to new path */ + while(*cp && *cp != FTP_SLASH) /* copy directory name */ + { + *cp1++ = *cp++; + if(cp1 >= &ftp->filename[FTPMAXPATH+2]) /* check length */ + { + ftpputs(ftp, "550 Path too long\r\n"); + ftp_flushcmd(ftp); + return 0; /* not a fatal error */ + } + } + } + } /* end of 'while(*cp)' loop */ +#ifdef DRIVE_LETTERS + if(cp1 == ftp->filename + 2) /* if at root... */ +#else /* DRIVE_LETTERS */ + if(cp1 == ftp->filename) /* if at root... */ +#endif /* DRIVE_LETTERS */ + cp1++; /* bump past slash */ + *cp1 = 0; /* null terminate new path */ + } + + /* new drive and/or directory is now in ftp->filename */ + /* verify path exists */ + if (!fs_dir(ftp)) + { + sprintf(ftp->filebuf, "550 Unable to find %s\r\n",ftp->filename); + ftpputs(ftp, ftp->filebuf); + break; + } + +#ifdef DRIVE_LETTERS + + /* store the drive into the filename in the drive field */ + ftp->drive[0] = ftp->filename[0]; + ftp->drive[1] = ':'; + ftp->drive[2] = 0; + /* store the file name sans drive info in the cwd field */ + strcpy(ftp->cwd,ftp->filename + 2); + +#else /* DRIVE_LETTERS */ + + /* store the file name in the cwd field */ + strcpy(ftp->cwd, ftp->filename); + +#endif /* DRIVE_LETTERS */ + + sprintf(ftp->filebuf, + "200 directory changed to %s%s\r\n", DRIVE_PTR(ftp), ftp->cwd); + ftpputs(ftp, ftp->filebuf); /* send reply to client */ + break; + case 0x4c495354: /* "LIST" */ + case 0x4e4c5354: /* "NLST" */ + listcmds++; + /* attempt to create a complete path from the current working + directory and the file spec in the command buffer. */ + if (!ftp_make_filename(ftp,TRUE)) + break; + + /* if we are in passive mode but the client hasn't connected to + data socket yet, just store the command so it will get executed + when the client connects */ + if (ftp->passive_state == FTPS_PASSIVE_MODE) + { + ftp->passive_cmd = ftpcmd; + break; + } + + + /* generate the listing, if the function fails, + send an error message back to the client */ + if (fs_dodir(ftp, ftpcmd)) + ftpputs(ftp, "451 exec error\r\n"); + break; + +#ifdef IP_V4 + case 0x50415356: /* "PASV" */ + ftps_do_pasv(ftp); + break; +#endif /* IP_V4 */ + +#ifdef IP_V6 + case 0x45505356: /* "EPSV" - IPv6 extended PASV */ + ftps_epsv(ftp); + break; + case 0x45505254: /* "EPRT" - IPv6 extended PORT */ + ftps_eprt(ftp); + break; +#endif /* IP_V6 */ + + /* some commands we know about and just don't do: */ + case 0x4d414342: /* "MACB" - ??? Netscape 3.0 for Win95 sends this */ + case 0x53495a45: /* "SIZE" - Netscape again. */ + case 0x4f505453: /* "OPTS" - IE 5.50 */ + ftpputs(ftp, ftp_badcmd); + break; + case 0x52455452: /* "RETR" */ + case 0x53544f52: /* "STOR" */ + /* attempt to create a complete path from the current working + directory and the file spec in the command buffer. */ + if (!ftp_make_filename(ftp,FALSE)) + break; + + /* ftp->filename now has drive:path/name of file to try for */ + + /* check for user permission */ + if(fs_permit(ftp) == FALSE) + { + ftpputs(ftp, ftp_noaccess); + ftp_xfercleanup(ftp); + break; + } + + /* verify that the name of the file we are trying to put or + get does not exist as a directory */ + if(fs_dir(ftp)) + { + ftpputs(ftp, "501 bad path\r\n"); + ftp_xfercleanup(ftp); + break; + } + + /* if we are in passive mode but the client hasn't connected to + data socket yet, just store the command so it will get executed + when the client connects */ + if (ftp->passive_state == FTPS_PASSIVE_MODE) + { + ftp->passive_cmd = ftpcmd; + break; + } + + IN_PROFILER(PF_FTP, PF_ENTRY); + if(ftpcmd == 0x52455452) /* RETR */ + ftp_sendfile(ftp); + else /* must be STOR */ + ftp_getfile(ftp); + IN_PROFILER(PF_FTP, PF_EXIT); + + break; + case 0x44454c45: /* "DELE" */ + /* attempt to create a complete path from the current working + directory and the file spec in the command buffer. */ + if (!ftp_make_filename(ftp,FALSE)) + { + sprintf(ftp->filebuf, "550 Unable to parse filename %s\r\n", \ + ftp->filename); + + ftpputs(ftp, ftp->filebuf); + break; + } + + lslash(ftp->filename); + + /* ftp->filename now has drive:path/name of file to try for */ + + /* check if the file that the client wants to delete exists */ + if (ftp->type == FTPTYPE_ASCII) + ftp->filep = vfopen(ftp->filename, "r"); /* ANSI translated mode */ + else + ftp->filep = vfopen(ftp->filename, "rb"); /* ANSI binary mode */ + + if (ftp->filep == NULL) + { + /* if we appended VFS path to our constructed file name dont say so */ + if (*(ftp->filename) == FTP_SLASH) + cp = ftp->filename + 1; + else + cp = ftp->filename; + + sprintf(ftp->filebuf, "550 No such file %s\r\n", cp); + ftpputs(ftp, ftp->filebuf); + break; + } + else + { + vfclose(ftp->filep); + } + + /* check for user permission */ + if(fs_permit(ftp) == FALSE) + { + ftpputs(ftp, ftp_noaccess); + break; + } + + if (vunlink(ftp->filename) != 0) + { + /* if we appended VFS path to our constructed file name dont say so */ + if (*(ftp->filename) == FTP_SLASH) + cp = ftp->filename + 1; + else + cp = ftp->filename; + + sprintf(ftp->filebuf, "550 Unable to delete file %s\r\n", cp); + ftpputs(ftp, ftp->filebuf); + break; + } + else + { + ftpputs(ftp, "250 DELE command successful\r\n"); + break; + } + case 0x4e4f4f50: /* "NOOP" */ + ftpputs(ftp, ftp_cmdok); + break; + default: + sprintf(ftp->filebuf, "500 Unknown cmd %s", ftp->cmdbuf); + ftpputs(ftp, ftp->filebuf); + } + ftp_flushcmd(ftp); + return 0; +} + + +/* FUNCTION: ftp_xfercleanup() + * + * Called after a file transfer to clean up session structure and + * handle replys. + * + * PARAM1: ftpsvr * ftp + * + * RETURNS: void + */ + +void +ftp_xfercleanup(ftpsvr * ftp) +{ + /* close any open file */ + if(ftp->filep) + { + vfclose(ftp->filep); + ftp->filep = NULL; + } + /* close any open socket */ + if (ftp->datasock != SYS_SOCKETNULL) + { + t_socketclose(ftp->datasock); + ftp->datasock = SYS_SOCKETNULL; + } + ftp->state = FTPS_LOGGEDIN; + +#ifdef TCP_ZEROCOPY + /* don't orphan any packets we may have stored in ftpsq */ + while (ftp->ftpsq.q_len > 0) + tcp_pktfree ((PACKET)getq(&ftp->ftpsq) ); +#endif /* TCP_ZEROCOPY or not */ + + /* we aren't in passive mode anymore */ + ftp_leave_passive_state(ftp); +} + + + +#ifdef TCP_ZEROCOPY /* use InterNiche Zero-copy TCP socket extensions */ +extern PACKET tcp_pktalloc(int); +extern void tcp_pktfree(PACKET); +int ftps_rxupcall(struct socket * so, PACKET pkt, int code); +#endif /* TCP_ZEROCOPY */ + + +/* FUNCTION: ftp_sendfile() + * + * Send a file. Filename, Port, type, and IP address are all + * set in ftp structure. Returns 0 if OK, else ftp error. + * + * + * PARAM1: ftpsvr * ftp + * + * RETURNS: Returns 0 if OK, else ftp error. + */ + +int +ftp_sendfile(ftpsvr * ftp) +{ + int e; + int reterr = 0; + u_long put_timer; /* timer for max time to loop in this routine */ + +#ifndef TCP_ZEROCOPY + int bytes = 0; +#endif + + /* See if this is start of send */ + if (ftp->state != FTPS_SENDING) + { + lslash(ftp->filename); + if (ftp->type == FTPTYPE_ASCII) + ftp->filep = vfopen(ftp->filename, "r"); + else + ftp->filep = vfopen(ftp->filename, "rb"); + if (!ftp->filep) + { + ftpputs(ftp, "451 aborted, can't open file\r\n"); + + /* if we are already connected to the client because we were + * in passive mode, close the connection to client and exit + */ + if (ftp->passive_state & FTPS_PASSIVE_MODE) + ftp_leave_passive_state(ftp); + return 451; + } + ftpputs(ftp, "150 Here it comes...\r\n"); + /* if we are not already connected from a previous PASV */ + if (!(ftp->passive_state & FTPS_PASSIVE_CONNECTED)) + { + /* connect to client */ + ftp->datasock = FTP_TCPOPEN(ftp); + if (ftp->datasock == SYS_SOCKETNULL) + { + ftpputs(ftp, "425 Can't open data connection\r\n"); + reterr = 425; + goto ftsnd_exit; + } + } + +#ifdef TCP_ZEROCOPY + ftp->iosize = tcp_mss(LONG2SO(ftp->datasock)); +#endif /* TCP_ZEROCOPY */ + + ftp->state = FTPS_SENDING; + ftp->filebuflen = 0; + } + + /* + * loop below while sending, quit when we reach MAX number of + * ftpticks we're allowed. The ftps_loop() routine will call us + * again later + */ + put_timer = (ftpticks + FTPTPS); /* set timeout tick */ + +#ifdef TCP_ZEROCOPY + /* different loops for ZEROCOPY and plain sockets */ + for (;;) + { + PACKET pkt; + if (ftp->pkt == NULL) /* need to read more file data */ + { + pkt = tcp_pktalloc(ftp->iosize); + if (!pkt) /* if no buffer, try again later */ + return 0; + e = vfread(pkt->nb_prot, 1, ftp->iosize, ftp->filep); + if (e < 0) + { + ftpputs(ftp, "451 aborted, file read error\r\n"); + reterr = 451; + break; + } + pkt->nb_plen = (unsigned)e; + } + else /* retry old packet saved in session structure */ + { + pkt = ftp->pkt; + } + + if (pkt->nb_plen) + { + e = tcp_xout(ftp->datasock, pkt); + if (e == ENP_RESOURCE) /* blocked */ + { + ftp->pkt = pkt; /* save pkt for later */ + tk_yield(); /* spin system */ + return 0; /* wait for socket to clear */ + } + else if(e < 0) + { + ftpputs(ftp, "426 aborted, data send error\r\n"); + reterr = 426; + if (pkt) + { + tcp_pktfree(pkt); + } + break; + } + else /* sent without error */ + { + /* tcp layer will free pkt when data is acked, just + clear to ftps pointer for now */ + ftp->pkt = NULL; + } + ftp->lasttime = ftpticks; /* reset timeout */ + /* + * force return to let other FTP sessions run if we have had CPU + * continuously for a longish while + */ + if (ftpticks > put_timer) + return 0; + } + else /* end of file & all bytes sent */ + { + tcp_pktfree(pkt); + ftp->pkt = NULL; + break; /* fall to send termination logic */ + } + } +#else /* not TCP_ZEROCOPY */ + for (;;) + { + if (ftp->filebuflen == 0) /* need to read more file data */ + { + /* if its an ASCII type transfer */ + if (ftp->type == FTPTYPE_ASCII) + { + /* then we need to insert a CR before any LF that is not + * already preceeded by an LF. + * Since the last character we read before filling up the + * file transfer buffer could be a lonely LF and in that + * case we'd have no room to insert the CR before it and + * it would be a righteous pain to keep track of this one + * boundary condition in the state machine, we will + * terminate the loop when there is still 1 byte left + */ + while (ftp->filebuflen < FILEBUFSIZE - 1) + { + int next_char; + int prev_char = 0; + + /* read next character from file */ + next_char = vgetc(ftp->filep); + /* break on end of file */ + if (next_char < 0) + break; + /* if we read an LF */ + if (next_char == '\n') + { + /* and the previous char wasn't a CR */ + if (prev_char != '\r') + { + /* insert a CR ahead of the LF */ + ftp->filebuf[ftp->filebuflen] = '\r'; + ftp->filebuflen++; + } + } + ftp->filebuf[ftp->filebuflen] = (char) next_char; + ftp->filebuflen++; + /* if we just read a LF, break. why? you ask. well + * what happens if the last byte we read before + * filling up the transfer buffer is a CR. when we + * come back in here again and read the LF, that LF + * looks like a lonely LF, so we'd end up inserting + * another CR, which wouldn't be right. so to protect + * against that and allow us to avoid storing the last + * character read in the ftpsrv structure in order to + * support this archaic feature, we just terminate the + * read when we get to the end of a line on the + * assumption that theres not going to be too many + * people moving text + */ + if (next_char == '\n') + break; + prev_char = next_char; + } + } + else /* its a binary transfer so just read the data */ + { + e = vfread(ftp->filebuf, 1, FILEBUFSIZE, ftp->filep); + if (e < 0) + { + ftpputs(ftp, "451 aborted, file read error\r\n"); + reterr = 451; + break; + } + ftp->filebuflen = (unsigned)e; + } + } + bytes = (int)ftp->filebuflen; + if (bytes) + { + e = t_send(ftp->datasock, ftp->filebuf, bytes, 0); + if (e < 0) + { + /* See what kind of error it is. If we're out of sockbuf + * space or buffers then + * return 0 to try again later. If its anything else then + * it's serious and we should abort with an error + */ + e = t_errno(ftp->datasock); + if((e == EWOULDBLOCK) || (e == ENOBUFS)) + { + return 0; /* out of socket space, try layer */ + } + ftpputs(ftp, "426 aborted, data send error\r\n"); + reterr = 426; + break; + } + else /* no send error */ + { +#ifdef NPDEBUG /* sanity test socket return values */ + if (e > FILEBUFSIZE) + { dtrap(); /* serious logic problem here */ + return 0; + } +#endif /* NPDEBUG */ + ftp->filebuflen -= e; +#ifdef NPDEBUG + if ((int)ftp->filebuflen < 0) + { dtrap(); + return 0; + } +#endif + if (e != bytes) /* partial send on NBIO socket */ + { + if (e != 0) /* sent some data, but not all - move buffer */ + { + MEMMOVE(ftp->filebuf, ftp->filebuf+e, ftp->filebuflen); + } + return 0; /* try again later */ + } + } + + ftp->lasttime = ftpticks; /* reset timeout */ + + /* + * force return to let other FTP sessions run if we have had CPU + * continuously for a longish while + */ + if (ftpticks > put_timer) + { + return 0; + } + } + else /* end of file & all bytes sent */ + break; /* fall to send termination logic */ + } +#endif /* TCP_ZEROCOPY */ + +ftsnd_exit: + + /* get here if EOF or fatal error */ + +#ifdef NPDEBUG + if (reterr == 0 && ftp->filebuflen != 0) /* buffer should be empty */ + { dtrap(); } +#endif + + /* first reply to user if xfer was OK */ + if (!reterr) + ftpputs(ftp, "226 Transfer OK, Closing connection\r\n"); + + ftp_xfercleanup(ftp); + return reterr; +} + + +/* FUNCTION: ftp_getfile() + * + * Get a file from client. We open a connection to the client + * and he will send it to us. Filename, Port, type, and IP + * address are all set in ftp structure. + * + * PARAM1: ftpsvr * ftp + * + * RETURNS: Returns 0 if OK, else ftp error. + */ + +int +ftp_getfile(ftpsvr * ftp) +{ + int bytes; + int e; + int reterr = 0; + u_long get_timer; /* ctick to force a return */ + + /* See if this is start of receive operation */ + if (ftp->state != FTPS_RECEIVING) + { + lslash(ftp->filename); + + if (ftp->type == FTPTYPE_ASCII) + ftp->filep = vfopen(ftp->filename, "w"); + else + ftp->filep = vfopen(ftp->filename, "wb"); + if (!ftp->filep) + { + ftpputs(ftp, "451 aborted, can't open file\r\n"); + + /* if we are already connected to the client because we were + * in passive mode, close the connection to client and exit + */ + if (ftp->passive_state & FTPS_PASSIVE_MODE) + ftp_leave_passive_state(ftp); + + return 550; + } + /* if we are not already connected from a previous PASV */ + if (!(ftp->passive_state & FTPS_PASSIVE_CONNECTED)) + { + ftp->datasock = FTP_TCPOPEN(ftp); + if (ftp->datasock == SYS_SOCKETNULL) + { + ftpputs(ftp, "425 Can't open data connection\r\n"); + reterr = 425; + goto ftget_exit; + } + } + ftpputs(ftp, "150 Connecting for STOR\r\n"); + ftp->state = FTPS_RECEIVING; +#ifdef TCP_ZEROCOPY + ftp->rxcode = 0; + t_setsockopt(ftp->datasock, 0, SO_CALLBACK, (void*)ftps_rxupcall, 0); +#endif /* TCP_ZEROCOPY */ + } + + get_timer = ftpticks + FTPTPS; /* set tick to timeout this loop */ + +#ifdef TCP_ZEROCOPY + /* different data transfer loops for zerocopy option */ + for (;;) + { + PACKET pkt; + + /* handle any packets the upcall has queued for us */ + while (ftp->ftpsq.q_len > 0) + { + LOCK_NET_RESOURCE(NET_RESID); /* syncronize ftpsq with upcall */ + pkt = (PACKET)getq(&(ftp->ftpsq)); + UNLOCK_NET_RESOURCE(NET_RESID); + if (ftp->rxcode && ftp->rxcode != ESHUTDOWN) /* network error? */ + { + tcp_pktfree(pkt); + continue; + } + bytes = pkt->nb_plen; + e = vfwrite(pkt->nb_prot, 1, bytes, ftp->filep); + tcp_pktfree(pkt); + + if (e == 0) /* memory allocation failed, not enough space to write a file on the server */ + { + ftpputs(ftp, "452 Insufficient storage space, file write error\r\n"); + reterr = 0; /* not a fatal error to abort */ + notfatal = 1; + goto ftget_exit; + } + if (e != bytes) + { + dtrap(); + ftpputs(ftp, "450 File unavailable, file write error\r\n"); + reterr = 0; /* not a fatal error to abort */ + notfatal = 1; + goto ftget_exit; + } + /* force return to let other FTP sessions run if we have had CPU + * continuously for a while. + */ + if (ftpticks > get_timer) + break; + +#if !defined(CHRONOS) && !defined(SUPERLOOP) + /* the yield here not only lets other tasks run, but if we have + * incoming data in the rcvdq it gives pktdemux a chance to get it + * into our queue via the upcall. This is not an Issue on Chronos + * since it runs the Net task at a higher priority, and it's + * dangerous on superloops. + */ + tk_yield(); /* let other tasks run */ +#endif /* neither CHRONOS nor SUPERLOOP */ + + } + if (ftp->rxcode) /* network error? */ + { + if (ftp->rxcode == ESHUTDOWN) /* file receive done */ + reterr = 0; /* no error */ + else + { + reterr = 426; + ftpputs(ftp, "426 aborted, data recv error\r\n"); + } + break; /* break out of for loop */ + } + return 0; /* done for now, let other things run */ + } +#else /* not TCP_ZEROCOPY */ + for (;;) + { + bytes = t_recv(ftp->datasock, ftp->filebuf, 1024, 0); + if (bytes > 0) + { + e = vfwrite(ftp->filebuf, 1, bytes, ftp->filep); + if (e == 0) /* memory allocation failed, not enough space to write a file on the server */ + { + ftpputs(ftp, "452 Insufficient storage space, file write error\r\n"); + reterr = 0; /* not a fatal error to abort */ + notfatal = 1; + break; + } + if (e != bytes) + { + dtrap(); + ftpputs(ftp, "450 File unavailable, file write error\r\n"); + reterr = 0; /* not a fatal error to abort */ + notfatal = 1; + break; + } + ftp->lasttime = ftpticks; /* reset timeout */ + } + if (bytes < 0) /* error, no data (EWOULDBLOCK) or finished */ + { + e = t_errno(ftp->datasock); + if (e == EWOULDBLOCK) + return 0; /* no work right now, let other things run */ + else /* probably socket cloesed due to end of file */ + { + bytes = 0; + break; /* break our of read loop to exit code */ + } + } + else if(bytes == 0) /* another form of broken? */ + { + /* bytes = -1; */ + ftp->state = FTPS_CLOSING; + break; + } + /* + * force return to let other FTP sessions run if we have had CPU + * continuously for a longish while. + */ + if (ftpticks > get_timer) + return 0; + } /* end of forever loop */ + + if (bytes < 0) + { + ftpputs(ftp, "426 aborted, data recv error\r\n"); + reterr = 426; + } +#endif /* TCP_ZEROCOPY or not */ + +ftget_exit: + + /* first reply to user if xfer was OK */ + if (!reterr && !notfatal) + ftpputs(ftp, "226 Transfer OK, Closing connection\r\n"); + + ftp_xfercleanup(ftp); + return reterr; +} + + +#ifdef TCP_ZEROCOPY + +/* FUNCTION: ftps_rxupcall() + * + * Upcall handler for TCP_ZEROCOPY data processing. This is passed + * packets directly from the sockets layer for fast, copyless processing + * + * PARAM1: struct socket * so + * PARAM2: PACKET pkt + * PARAM3: int code + * + * RETURNS: 0 if packet accepted, -1 if not. + */ + +int +ftps_rxupcall(struct socket * so, PACKET pkt, int code) +{ + ftpsvr * ftps; + + for (ftps = ftplist; ftps; ftps = ftps->next) + if ((long)ftps->datasock == SO2LONG(so)) + break; + + if (!ftps) /* can't find socket? */ + { + /* if no pkt and code is set, this may be a reset (or + * other cleanup) of a stale socket for which we have + * already cleared out the ftps. In this case just return, + * else dtrap & return error code. + */ + if (pkt || (code == 0)) + { + dtrap(); /* If pkt or no code, tel programmer */ + return -1; /* return error code */ + } + return 0; /* not an error */ + } + ftps->rxcode = code; /* save code */ + + if (pkt) /* save pkt, if any */ + putq( &(ftps->ftpsq), pkt ); + +#ifndef SUPERLOOP + /* If the queue is filling, spin server task */ + if(ftps->ftpsq.q_len > 10) + { + TK_WAKE(&to_ftpsrv); /* make sure it's awake */ + tk_yield(); /* let FTP server task spin */ + } +#endif /* SUPERLOOP */ + + ftps->lasttime = ftpticks; /* reset timeout */ + + return 0; +} +#endif /* TCP_ZEROCOPY or not */ + + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsrv.h b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsrv.h new file mode 100644 index 0000000..d2a5d61 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsrv.h @@ -0,0 +1,159 @@ +/* + * FILENAME: FTPSRV.H + * + * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved + * + * + * MODULE: FTP + * + * ROUTINES: + * + * PORTABLE: yes + */ + +/* ftpsrv.h FTP server for WebPort HTTP server. + * 1/12/97 - Created. John Bartas + */ +#ifndef FTPSVR_H +#define FTPSVR_H 1 + + +#ifdef VFS_FILES /* from inet\ipport.h */ +#include "vfsfiles.h" +#else /* map "vf" vcalls to native file system */ +#ifndef vfopen /* allow override in ftpport.h */ +#define vfopen(file, mode) fopen(file, mode) +#define vfread(buf, ct, size, fp) fread(buf, ct, size, fp) +#define vfwrite(buf, ct, size, fp) fwrite(buf, ct, size, fp) +#define vgetc(fp) fgetc(fp) +#define vfclose(fp) fclose(fp) +#define vunlink(fp) remove(fp) +#define VFILE FILE +#endif /* vfsopen */ +#endif /* VFS_FILES */ + +#define FTP_PORT 21 /* standard FTP command port */ + +struct userstruct { + char username[FTPMAXUSERNAME]; + char password[FTPMAXUSERPASS]; + char home[FTPMAXPATH+2]; /* user's "home" directory */ + void * group; /* for use by port */ +}; +typedef struct userstruct userinfo; + +#ifndef ip_addr +#define ip_addr u_long +#endif + +struct ftpsvrs { + struct ftpsvrs * next; /* list link */ + int inuse; /* re-entry semaphore */ + SOCKTYPE sock; /* client command socket */ + SOCKTYPE datasock;/* client data socket */ + int state; /* one of FTPS_ defines below */ + u_long lasttime; /* ftptick when last action occured */ + userinfo user; + int logtries; /* retry count of logins */ + int type; /* ASCII or BINARY */ + VFILE * filep; /* pointer to open file during IO */ +#ifdef IP_V6 + ip6_addr ip6_host; /* host if domain == AF_INET6 */ +#endif /* IP_V6 */ + ip_addr host; /* FTP client */ + u_short dataport; /* client data TCP port */ + char * lastreply; /* last reply string sent, for debugging */ + unsigned int passive_state; /* state info for PASV command */ + u_long passive_cmd; /* file XFER command in passive state */ + u_short server_dataport; /* data port we listen on in passive mode */ +#ifdef DRIVE_LETTERS + char drive[4]; /* usually "c:\0" */ +#endif /* DRIVE_LETTERS */ + char cwd[FTPMAXPATH+1]; /* current directory, e.g. "/" or "/tmp/foo/" */ + char filename[FTPMAXPATH+FTPMAXFILE]; + char cmdbuf[CMDBUFSIZE]; /* buffer for comamnds from client */ + unsigned cmdbuflen; /* number of bytes currently receieved in cmdbuf */ + char filebuf[FILEBUFSIZE]; /* file buffer for data socket & file IO */ + unsigned filebuflen; /* amount of data actually in filebuf */ +#ifdef TCP_ZEROCOPY + PACKET pkt; /* packet currently queued for send */ + queue ftpsq; /* queue of received PACKETs */ + int rxcode; /* last receive code */ + int iosize; /* optimal IO size (TCP MSS) */ +#endif /* TCP_ZEROCOPY */ + int wFlag; /* flags for write blocked, et. al. */ + int domain; /* AF_INET or AF_INET6 */ +}; +typedef struct ftpsvrs ftpsvr; + +extern ftpsvr * ftplist; /* master list of FTP connections */ + +extern u_long ftps_connects; +extern u_long ftps_txfiles; +extern u_long ftps_rxfiles; +extern u_long ftps_txbytes; +extern u_long ftps_rxbytes; +extern u_long ftps_dirs; + + +/* ftpsvr.states: */ +#define FTPS_CONNECTING 1 /* connected, no USER info yet */ +#define FTPS_NEEDPASS 2 /* user OK, need password */ +#define FTPS_LOGGEDIN 3 /* ready to rock */ +#define FTPS_SENDING 4 /* sending a data file in progress */ +#define FTPS_RECEIVING 5 /* receiveing a data file in progress */ +#define FTPS_CLOSING 9 /* closing */ + +#define FTPTYPE_ASCII 1 +#define FTPTYPE_IMAGE 2 + +/* ftpsvr.passive_state bits */ +#define FTPS_PASSIVE_MODE 0x01 /* session is in passive mode */ +#define FTPS_PASSIVE_CONNECTED 0x02 /* client has connected to data port */ + +/* FTP server internal commands */ +char * ftp_cmdpath(ftpsvr * ftp); /* extract path from cmd text */ +char * uslash(char * path); /* make path into UNIX slashes */ + +/* required OS dependant routines */ +int fs_dodir(ftpsvr * ftp, u_long ftpcmd); +void lslash(char * path); /* make path into local slashes */ +int fs_dir(ftpsvr * ftp); /* verify drive:/path exists */ +int fs_permit(ftpsvr * ftp); /* verify user permission */ +int fs_lookupuser(ftpsvr * ftp, char * username); + +/* macro to insert optional drive letter in sprintfs */ +#ifdef DRIVE_LETTERS +#define DRIVE_PTR(ftp) ftp->drive +#else /* drive not supported, insert pointer to null */ +#define DRIVE_PTR(ftp) "" +#endif + +/* prototype server exported routines */ +ftpsvr * ftps_connection(SOCKTYPE); /* new connection */ +void ftp_leave_passive_state(ftpsvr * ftp); +void ftps_loop(void); /* periodic loop (tick) */ +int ftps_v4pasv(ftpsvr * ftp); +int ftps_v6pasv(ftpsvr * ftp); +void ftps_eprt(ftpsvr * ftp); +void ftps_epsv(ftpsvr * ftp); + +/* define the macro/routine FTP_TCPOPEN() based on version ifdefs */ + +#ifdef IP_V4 /* begin version mess */ +#ifndef IP_V6 /* IP_V4 only */ +SOCKTYPE ftp4open(ftpsvr * ftp); +#define FTP_TCPOPEN(ftp) ftp4open(ftp) +#else /* IP_V4 and IP_V6 */ +SOCKTYPE FTP_TCPOPEN(ftpsvr * ftp); /* dual mode uses routine */ +#endif /* IP_V4 */ +#else /* IP_V6 only */ +SOCKTYPE ftp6open(ftpsvr * ftp); +#define FTP_TCPOPEN(ftp) ftp6open(ftp) +#endif /* IP_V6 only */ + +#endif /* FTPSVR_H */ + +/* end of file ftpsrv.h */ + + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpssock.c b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpssock.c new file mode 100644 index 0000000..f8e05ff --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpssock.c @@ -0,0 +1,759 @@ +/* + * FILENAME: ftpssock.c + * + * Copyright 2000 - 2002 By InterNiche Technologies Inc. All rights reserved + * + * Sockets specific code for FTP. FTP Implementations on APIs + * other than sockets need to replace these. + * + * MODULE: FTP + * + * ROUTINES: ftp_cmdcb(), ftp_datacb(), t_tcplisten(), + * ROUTINES: FTP_TCPOPEN(), ftp4open(), ftp6open(), SO_GET_FPORT(), + * ROUTINES: SO_GET_LPORT(), ftps_v4pasv(), ftps_eprt(), ftps_epsv(), + * + * PORTABLE: yes + */ + +/* Additional Copyrights: */ + +/* ftpssock.c + * Portions Copyright 1996 by NetPort Software. All rights reserved. + * The Sockets-dependant portion of the FTP Server code. + * 11/24/96 - Created by John Bartas + */ + +#include "ftpport.h" /* TCP/IP, sockets, system info */ +#include "ftpsrv.h" + +#ifdef IP_V6 +#include "socket6.h" +#endif + + +#ifdef MINI_TCP + +#include "msring.h" +extern struct msring ftps_msring; + +#ifndef SUPERLOOP +extern TK_OBJECT(to_ftpsrv); +#endif + + +/* ftp_cmcb() - ftp command connection callback */ +int +ftp_cmdcb(int code, M_SOCK so, void * data) +{ + int e = 0; + + switch(code) + { + case M_OPENOK: /* new socket is connected */ + msring_add(&ftps_msring, so); + break; + case M_CLOSED: /* TCP lost socket connection */ + break; /* let stale conn timer catch these */ + case M_RXDATA: /* received data packet, let recv() handle it */ + case M_TXDATA: /* ready to send more, http_loop will do it */ + e = -1; /* return nonzero code to indicate we don't want it */ + break; + default: + dtrap(); /* not a legal case */ + return 0; + } + +#ifdef SUPERLOOP + ftps_loop(); /* give loop a spin */ +#else /* multitasking */ + TK_WAKE(&to_ftpsrv); /* wake webserver task */ +#endif + + USE_VOID(data); + return e; + +} + +/* ftp_datacb() - ftp data socket connection callback */ + +int +ftp_datacb(int code, M_SOCK so, void * data) +{ + int e = 0; + + switch(code) + { + case M_OPENOK: /* new socket is connected */ + /* if this FTP was listening for a data connection, + * switch its listening socket for the data socket + * and close the listening socket + */ + if (so->app_data) + { + ftpsvr * ftp; + M_SOCK old_so; + + ftp = (ftpsvr *)(so->app_data); + old_so = ftp->datasock; + ftp->datasock = so; + if (old_so != SYS_SOCKETNULL) + { + UNLOCK_NET_RESOURCE(NET_RESID); + m_close(old_so); + LOCK_NET_RESOURCE(NET_RESID); + } + } + UNLOCK_NET_RESOURCE(NET_RESID); + m_ioctl(so, SO_NONBLOCK, NULL); /* make socket non-blocking */ + LOCK_NET_RESOURCE(NET_RESID); + break; + case M_RXDATA: + e = -1; /* return nonzero code to indicate we don't want it */ + break; + case M_TXDATA: + case M_CLOSED: /* lost ftp data socket connection */ + break; + default: + dtrap(); /* not a legal case */ + return 0; + } + +#ifdef SUPERLOOP + ftps_loop(); /* give loop a spin */ +#else /* multitasking */ + TK_WAKE(&to_ftpsrv); /* wake webserver task */ +#endif + + USE_VOID(data); + return e; +} + + +#endif /* MINI_TCP */ + + +/* FUNCTION: t_tcplisten() + * + * t_tcplisten() implementation for NetPort sockets. Local port + * (lport) is passed in local endian. If lport is 0 (wildcard), then + * selected value is filled in to caller's variable. + * + * PARAM1: u_short * lport + * + * RETURNS: returns a listening socket, or SYS_SOCKETNULL if error. + */ + + +#ifdef MINI_TCP +SOCKTYPE +t_tcplisten(u_short * lport, int domain) +{ + int e; + SOCKTYPE sock; + struct sockaddr_in ftpsin; + + ftpsin.sin_addr.s_addr = INADDR_ANY; + ftpsin.sin_port = htons(*lport); + + if (*lport == FTP_PORT) + sock = m_listen(&ftpsin, ftp_cmdcb, &e); + else + sock = m_listen(&ftpsin, ftp_datacb, &e); + + if (sock == INVALID_SOCKET) + { +listenerr: + dprintf("error %d starting listen on ftp server\n", e); + return SYS_SOCKETNULL; + } + + /* put socket in non-blocking mode */ + e = m_ioctl(sock, SO_NBIO, NULL); + if (e != 0) + { + m_close(sock); + goto listenerr; + } + + /* if wildcard port requested, return assigned port */ + if (*lport == 0) + *lport = htons(sock->lport); + + return sock; +} + +#else /* full-sockets TCP */ + +SOCKTYPE +t_tcplisten(u_short * lport, int domain) +{ + int e; + SOCKTYPE sock; + + sock = t_socket(domain, SOCK_STREAM, 0); + if (sock == SYS_SOCKETNULL) + return sock; + + switch(domain) + { +#ifdef IP_V4 + case AF_INET: + { + struct sockaddr_in ftpsin; + int addrlen = sizeof(ftpsin); + + ftpsin.sin_family = AF_INET; + ftpsin.sin_addr.s_addr = INADDR_ANY; + ftpsin.sin_port = htons(*lport); + e = t_bind(sock, (struct sockaddr*)&ftpsin, addrlen); + if (e != 0) + { + e = t_errno(sock); + dtrap(); + dprintf("error %d binding tcp listen on port %d\n", + e, htons(*lport)); + return SYS_SOCKETNULL; + } + if(*lport == 0) /* was it wildcard port? */ + *lport = htons(ftpsin.sin_port); /* return it to caller */ + } + break; +#endif /* IP_V4 */ +#ifdef IP_V6 + case AF_INET6: + { + struct sockaddr_in6 ftpsin6; + int addrlen = sizeof(ftpsin6); + + IP6CPY(&ftpsin6.sin6_addr, &in6addr_any); + ftpsin6.sin6_port = htons(*lport); + ftpsin6.sin6_family = AF_INET6; + e = t_bind(sock, (struct sockaddr *)&ftpsin6, addrlen); + if (e != 0) + { + e = t_errno(sock); + dtrap(); + dprintf("error %d binding ftp6 listen on port %d\n", + e, htons(*lport)); + return SYS_SOCKETNULL; + } + if (*lport == 0) /* was it wildcard port? */ + *lport = htons(ftpsin6.sin6_port); /* return it to caller */ + } + break; +#endif /* IP_V6 */ + default: + dtrap(); /* bad domain parameter */ + return SYS_SOCKETNULL; + } /* end switch(domain) */ + + /* For FTP, put socket in non-block mode */ + t_setsockopt(sock, SOL_SOCKET, SO_NBIO, NULL, 0); + + e = t_listen(sock, 5); + if (e != 0) + { + e = t_errno(sock); + dprintf("error %d starting listen on ftp server\n", e); + return SYS_SOCKETNULL; + } + + return sock; /* return listen sock to caller */ +} +#endif /* notdef MINI_TCP */ + + + + +/* FUNCTION: ftp4open() + * FUNCTION: ftp6open() + * FUNCTION: FTP_TCPOPEN() (may be macro) + * + * FTP's TCP active open routine(s). Provided for FTP server to + * can open an active TCP connection, such as FTP data. Versions + * are provided for IPv4 and IPv6. The routine is intended to + * be mapped to the macro FTP_TCPOPEN(), which is also provided + * as a dual-mode function below. + * + * PARAM1: ftpsrv * ftp + * + * RETURNS: Returns conencted socket if OK, + * SYS_SOCKETNULL on error + */ + +#ifndef FTP_TCPOPEN /* see if it's defined */ + +/* dual-mode version */ +SOCKTYPE +FTP_TCPOPEN(ftpsvr * ftp) +{ +#ifdef IP_V4 + if(ftp->domain == AF_INET) + return(ftp4open(ftp)); +#endif /* IP_V4 */ +#ifdef IP_V6 + if(ftp->domain == AF_INET6) + return(ftp6open(ftp)); +#endif /* IP_V6 */ + + dtrap(); /* bad domain setting */ + return SYS_SOCKETNULL; +} +#endif /* FTP_TCPOPEN */ + + +#ifdef IP_V4 +SOCKTYPE +ftp4open(ftpsvr * ftp) +{ + int e; /* error holder */ + SOCKTYPE sock; + struct sockaddr_in ftpsin; + + sock = t_socket(AF_INET, SOCK_STREAM, 0); + if (sock == SYS_SOCKETNULL) + return sock; + + /* Change the socket options to allow address re-use. A customer + * requested this to ease implementing an FTP client with multiple + * connections. + */ + if (ftp->server_dataport) + { +#ifndef MINI_TCP + int opt = 1; /* boolean option value holder */ + + e = t_setsockopt(sock, 0, SO_REUSEADDR, &opt, sizeof(opt)); + if (e != 0) + { + e = t_errno(sock); + dtrap(); + dprintf("error %d setting SO_REUSEADDR on port %d\n", + e, ftp->server_dataport); + return SYS_SOCKETNULL; + } + + /* Bind local port to the socket we just created */ + ftpsin.sin_family = AF_INET; + ftpsin.sin_addr.s_addr = INADDR_ANY; + ftpsin.sin_port = htons(ftp->server_dataport); + + e = t_bind(sock, (struct sockaddr*)&ftpsin, sizeof(ftpsin)); + if (e != 0) + { + e = t_errno(sock); + dtrap(); + dprintf("error %d binding tcp listen on port %d\n", + e, ftp->server_dataport); + return SYS_SOCKETNULL; + } +#else + sock->lport = htons(ftp->server_dataport); +#endif /* MINI_TCP */ + } + + ftpsin.sin_addr.s_addr = htonl(ftp->host); + ftpsin.sin_port = htons(ftp->dataport); + +#ifdef MINI_TCP + sock->app_data = NULL; + e = m_connect(sock, &ftpsin, ftp_datacb); +#else + ftpsin.sin_family = AF_INET; + e = t_connect(sock, (struct sockaddr*)&ftpsin, sizeof(ftpsin)); +#endif + if (e != 0) + { + dtrap(); +#ifndef MINI_TCP + t_errno(sock); /* so debugger can see error */ +#endif + return SYS_SOCKETNULL; + } + + /* FTP data socket can be in blocking or non-blocking mode */ +#ifdef MINI_TCP + m_ioctl(sock, SO_NBIO, NULL); +#else + t_setsockopt(sock, 0, SO_NBIO, NULL, 0); +#endif + + return sock; +} +#endif /* IP_V4 */ + +/* FUNCTION: ftp6open() + * + * v6 version of FTP4open() + * + * PARAM1: ftpsvr * ftp + * + * RETURNS: Returns conencted socket if OK, SYS_SOCKETNULL on error + */ + +#ifdef IP_V6 +SOCKTYPE +ftp6open(ftpsvr * ftp) +{ + int e; /* error holder */ + SOCKTYPE sock; + struct sockaddr_in6 ftpsin; + unshort lport; + + lport = ftp->server_dataport; + + sock = t_socket(AF_INET6, SOCK_STREAM, 0); + if (sock == SYS_SOCKETNULL) + return sock; + + /* Change the socket options to allow address re-use. A customer + * requested this to ease implementing an FTP client with multiple + * connections. + */ + if (lport) + { + int opt = 1; + + e = t_setsockopt(sock, 0, SO_REUSEADDR, &opt, sizeof(opt)); + if (e != 0) + { + e = t_errno(sock); + dtrap(); + dprintf("error %d setting SO_REUSEADDR on port %d\n", e, lport); + return SYS_SOCKETNULL; + } + + /* Bind local port to the socket we just created */ + ftpsin.sin6_family = AF_INET6; + IP6CPY(&ftpsin.sin6_addr, &ip6unspecified); + ftpsin.sin6_port = htons(lport); + + e = t_bind(sock, (struct sockaddr*)&ftpsin, sizeof(ftpsin)); + if (e != 0) + { + e = t_errno(sock); + dtrap(); + dprintf("error %d binding tcp listen on port %d\n", e, lport); + return SYS_SOCKETNULL; + } + } + + IP6CPY(&ftpsin.sin6_addr, &ftp->ip6_host); + ftpsin.sin6_port = htons(ftp->dataport); + + ftpsin.sin6_family = AF_INET6; + e = t_connect(sock, (struct sockaddr*)&ftpsin, sizeof(ftpsin)); + if (e != 0) + { + dtrap(); + t_errno(sock); /* so debugger can see error */ + return SYS_SOCKETNULL; + } + + /* FTP data socket can be in blocking or non-blocking mode */ + t_setsockopt(sock, SOL_SOCKET, SO_NBIO, NULL, 0); + + return sock; +} +#endif /* IP_V6 */ + + +#ifndef MINI_TCP + +/* FUNCTION: SO_GET_FPORT() + * + * Return the foreign port of a socket. No error checking is done. It's + * up to the caller to make sure this socket is connected before calling. + * + * PARAM1: the socket + * + * RETURNS: Returns the foreign port of the passed socket. + */ + +unshort +SO_GET_FPORT(SOCKTYPE sock) +{ + struct sockaddr client; + int clientsize; + unshort port; + + clientsize = sizeof(client); + t_getpeername(sock, &client, &clientsize); + +#ifdef IP_V4 +#ifndef IP_V6 /* v4 only case: */ + port = ((struct sockaddr_in *)(&client))->sin_port; +#else /* dual mode */ + if(clientsize == sizeof(struct sockaddr_in)) + port = ((struct sockaddr_in *)(&client))->sin_port; + else + port = ((struct sockaddr_in6 *)(&client))->sin6_port; +#endif /* end dual mode code */ +#else /* no v4, v6 only */ + port = ((struct sockaddr_in6 *)(&client))->sin6_port; +#endif /* v6 only */ + + return (ntohs(port)); +} + +/* FUNCTION: SO_GET_LPORT() + * + * Return the foreign port of a socket. No error checking is done. It's + * up to the caller to make sure this socket is connected before calling. + * + * PARAM1: the socket + * + * RETURNS: Returns the foreign port of the passed socket. + */ + +unshort +SO_GET_LPORT(WP_SOCKTYPE sock) +{ + struct sockaddr_in client; + int clientsize; + unshort port; + + clientsize = sizeof(client); + t_getsockname(sock, (struct sockaddr *) &client, &clientsize); + +#ifdef IP_V4 +#ifndef IP_V6 /* v4 only case: */ + port = ((struct sockaddr_in *)(&client))->sin_port; +#else /* dual mode */ + if(clientsize == sizeof(struct sockaddr_in)) + port = ((struct sockaddr_in *)(&client))->sin_port; + else + port = ((struct sockaddr_in6 *)(&client))->sin6_port; +#endif /* end dual mode code */ +#else /* no v4, v6 only */ + port = ((struct sockaddr_in6 *)(&client))->sin6_port; +#endif /* v6 only */ + + return (ntohs(port)); +} + +#endif /* MINI_TCP */ + + +/* error reporting mechanism for open sessions. "text" should start + * with an FTP code (e.g. "425 " since it will be sent to client + * on the command connection. + */ +extern int ftpputs(ftpsvr * ftp, char * text); + +static char * err = "425 Can't open data connection\r\n"; + +#ifdef IP_V4 +int +ftps_v4pasv(ftpsvr * ftp) +{ + SOCKTYPE sock; + u_short port; + unsigned long addr; + char responseBuf[80]; + + /* create a TCP socket to listen on, it will be the data socket. + * First set port to 0 so sockets will pick one for us + */ + port = 0; + sock = t_tcplisten(&port, AF_INET); /* call API to start listen */ + if (sock == SYS_SOCKETNULL) /* if socket creation failed */ + { + ftpputs(ftp, err); + return EIEIO; + } + + /* get our address and data port so we can tell the client + * what address to connect to. + */ + +#ifdef MINI_TCP + sock->app_data = (void *)ftp; /* ptr back to FTP server state */ + addr = ntohl(ftp->sock->lhost); /* address from connected cmd sock */ + port = ntohs(sock->lport); /* port from listening data sock */ +#else /* BSDish sockets */ +{ + struct sockaddr_in our_addr; + int sa_len = sizeof(our_addr); + + if (t_getsockname(ftp->sock,(struct sockaddr *) &our_addr, &sa_len)) + { + /* tell client pasv failed */ + ftpputs(ftp,err); + return t_errno(sock); + } + + /* extract and convert to local endian our command socket address */ + addr = ntohl(our_addr.sin_addr.s_addr); + + /* get our port on the data socket */ + if (t_getsockname(sock,(struct sockaddr *) &our_addr, &sa_len)) + { + /* close the socket we just opened */ + t_socketclose(sock); + /* tell client pasv failed */ + ftpputs(ftp,err); + return t_errno(sock); + } + + /* extract and convert to local endian our data socket port */ + port = ntohs(our_addr.sin_port); +} +#endif /* MINI_TCP or BSD sockets */ + + /* create our response which tells the client what address and + * port to connect to + */ + sprintf(responseBuf, + "227 Entering Passive Mode (%d,%d,%d,%d,%d,%d)\r\n", + (int) (addr >> 24), (int) ((addr >> 16) & 0xff), + (int) ((addr >> 8) & 0xff), (int) (addr & 0xff), + (int) (port >> 8),(int) (port & 0xff)); + ftpputs(ftp,responseBuf); + + ftp->server_dataport = port; + ftp->datasock = sock; + + return 0; +} +#endif /* IP_V4 */ + +#ifdef IP_V6 + +void +ftps_eprt(ftpsvr * ftp) +{ + char * cp; /* scratch command buffer pointer */ + char delimit; /* delimiter, from string */ + int domain; /* domain from command */ + unshort port; /* port number form command */ + char addr[16]; /* local address buffer (binary) */ + char responseBuf[80]; + + /* point into command buffer after "EPSV " string */ + cp = &ftp->cmdbuf[5]; + delimit = *cp++; /* read delimiter */ + + if(*cp == '1') + domain = AF_INET; + else if(*cp == '2') + domain = AF_INET6; + else + { + ftpputs(ftp,"501 Unsupported EPRT domain\r\n"); + return; + } + if(domain != ftp->domain) + { + dtrap(); /* in theory this is possible.... */ + ftpputs(ftp,"501 Mismatched EPRT domain\r\n"); + return; + } + + cp = strchr(cp, delimit); /* advance to address */ + if(!cp) + goto eprt_error; + cp++; + if(inet_pton(domain, cp, &addr[0])) + { + /* Send detailed parse error message to console. */ + dprintf("FTP EPRT addr error: %s\n", pton_error); + goto eprt_error; + } + + cp = strchr(cp, delimit); /* advance to port */ + if(!cp) + goto eprt_error; + cp++; + + port = (unshort)atoi(cp); + if(port == 0) + goto eprt_error; + + /* got everything, fill in the ftps and ack the command */ + ftp->dataport = port; + + if(domain == AF_INET6) + IP6CPY(&ftp->ip6_host, (ip6_addr*)(&addr)); + else + ftp->host = *(ip_addr*)(&addr[0]); + + sprintf(responseBuf, "229 EPRT OK on port %u\r\n", port); + ftpputs(ftp,responseBuf); + return; + +eprt_error: + ftpputs(ftp,"501 Bad EPRT command\r\n"); + return; +} + +void +ftps_epsv(ftpsvr * ftp) +{ + SOCKTYPE sock; + u_short port; + char responseBuf[80]; + struct sockaddr_in6 our_addr; /* v6 type socket */ + int sa_len; + + /* Run the same tests as the v4 ftps_do_pasv() */ + if (ftp->passive_state & FTPS_PASSIVE_CONNECTED) + { + ftpputs(ftp,"425 Data transfer already in progress\r\n"); + return; + } + + /* This will happen if the client had sent us a PASV and then sent + * us another one without an intervening data transfer command. + */ + if (ftp->passive_state & FTPS_PASSIVE_MODE) + { + ftp_leave_passive_state(ftp); + } + + /* create a TCP socket to listen on, it will be the data socket. + * First set port to 0 so sockets will pick one for us + */ + port = 0; + sock = t_tcplisten(&port, ftp->domain); /* call API to start listen */ + if (sock == SYS_SOCKETNULL) /* if socket creation failed */ + { + ftpputs(ftp, err); + return; + } + + /* get our address and data port so we can tell the client + * what address to connect to. + */ + sa_len = sizeof(our_addr); + if (t_getsockname(sock, (struct sockaddr *)&our_addr, &sa_len)) + { + /* close the socket we just opened */ + t_socketclose(sock); + /* tell client pasv failed */ + ftpputs(ftp,err); + return; + } + + /* extract and convert to local endian our data socket port */ + port = ntohs(our_addr.sin6_port); + + /* respons to the EPSV command. */ + sprintf(responseBuf, + "229 Entering Extended Passive Mode (|||%d|)\r\n", port ); + ftpputs(ftp,responseBuf); + + /* we are now in passive mode, but the client hasn't connected yet */ + ftp->passive_state = FTPS_PASSIVE_MODE; + + /* we haven't received a data transfer command from the client yet */ + ftp->passive_cmd = 0; + + ftp->server_dataport = port; + ftp->datasock = sock; + + return; +} +#endif /* IP_V6 */ + + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsvfs.c b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsvfs.c new file mode 100644 index 0000000..96a3739 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsvfs.c @@ -0,0 +1,233 @@ +/* + * FILENAME: ftpsvfs.c + * + * Copyright 2000 By InterNiche Technologies Inc. All rights reserved + * + * + * MODULE: FTP + * + * ROUTINES: fs_dodir(), lslash(), fs_dir(), fs_permit(), + * + * PORTABLE: no + */ + +/* Additional Copyrights: */ + +/* ftpsvfs.c + * Portions Copyright 1996 by NetPort Software. All rights reserved. + * FS dependent portions of FTP serer. This version for InteNiche + * VFS. + * 7/21/96 - Taken out of ftpsrv.c - John Bartas + */ + +#include "ftpport.h" /* TCP/IP, sockets, system info */ +#include "ftpsrv.h" + +#include "vfsfiles.h" +#include "in_utils.h" + +int ftpputs(ftpsvr * ftp, char * text); +void ftp_leave_passive_state(ftpsvr * ftp); + + + +/* FUNCTION: fs_dodir() + * + * fs_dodir() - do a "dir" (or "ls" for UNIX weenies) on the current + * ftp directory, write the resulting text out ftps->datasock, which + * is open before this is called. How you do the DIR and buffer is + * local to this function. Any tmp files or buffers should be cleaned + * up before you return. This is the VFS-only version. + * + * PARAM1: ftpsvr * ftp + * PARAM2: u_long ftpcmd + * + * RETURNS: Returns 0 if OK, else -1 if error. + */ + +int +fs_dodir(ftpsvr * ftp, u_long ftpcmd) +{ + char * cp; + int bytes_to_send; + int bytes_sent; + int rc; + int blocked; + struct vfs_file * vfp; + + ftpputs(ftp, "150 Here it comes...\r\n"); + + /* if we are already connected to the client because we are in + passive mode, don't create connection to client */ + if (!(ftp->passive_state & FTPS_PASSIVE_CONNECTED)) + { + /* create a data connection back to the client */ + ftp->datasock = FTP_TCPOPEN(ftp); + if (ftp->datasock == SYS_SOCKETNULL) + { + ftpputs(ftp, "425 Can't open data connection\r\n"); + return 0; /* not actually OK, but we handled error */ + } + } + + /* lock the VFS */ + vfs_lock(); + + /* for each file in the file list */ + for (vfp = vfsfiles; vfp; vfp = vfp->next) + { + /* if client asked for long version of file listing */ + if (ftpcmd == 0x4c495354) /* "LIST" */ + { + /* print month, day, hour and minute, as in : + -rw-r--r-- 1 jharan jharan 11772 Jan 19 13:31 install.log */ + /* since we don't have time stamps in the VFS, we lie about + * the date and time. if the VF_WRITE bit is set, the file + * is read/write so we display the roughly analogous + * Unix file mask corresponding to 666 else 444 + */ + sprintf(ftp->filebuf, + "%s 0 root root %11ld %s %2d %02d:%02d %s", + ((vfp->flags & VF_WRITE) ? "-rw-rw-rw-" : "-r--r--r--"), + vfp->real_size,"Jan",1,1,1,vfp->name); + } + else + /* else just give the client the file name */ + strcpy(ftp->filebuf,vfp->name); + + /* append a newline sequence to the end of the file listing */ + cp = ftp->filebuf + strlen(ftp->filebuf); + *cp++ = '\r'; + *cp++ = '\n'; + *cp = 0; + + /* get number of bytes to transmit */ + bytes_to_send = cp - ftp->filebuf; + + blocked = 0; + /* while there are bytes left to transmit */ + for (bytes_sent = 0; bytes_to_send > 0; ) + { + /* try to send as much as is left to transmit */ + rc = t_send(ftp->datasock,ftp->filebuf + bytes_sent,bytes_to_send,0); + + /* this means some sort of error occurred */ + if (rc < 0) + { + /* get socket error. If it's s (hopefully) transient buffer shortage + * then just wait a bit and try again, up to a limit: + */ + rc = t_errno(ftp->datasock); + if((rc == EWOULDBLOCK) || (rc == ENOBUFS)) + { + if(blocked++ < 100) /* don't loop here forever... */ + { + tk_yield(); /* let system spin a bit */ + continue; + } + } + ftpputs(ftp, "426 aborted, data send error\r\n"); + break; + } + + /* socket could be non-blocking, which means t_send() might have + sent something less than what was requested */ + bytes_to_send -= rc; + bytes_sent += rc; + +#ifndef BLOCKING_APP + /* if the whole thing wasn't sent, it wont get any better + * if you don't yield to receive side + */ + if (bytes_to_send > 0) + tk_yield(); +#endif + } + + /* if this happens, we broke in the loop above because of a + socket error */ + if (bytes_to_send > 0) + break; + } + + /* unlock the VFS */ + vfs_unlock(); + + /* if vfp is now NULL, then we exited the above loop without an + error, so we can report that the transfer went ok */ + if (!vfp) + ftpputs(ftp, "226 Transfer OK, Closing connection\r\n"); + + /* close the data connection and leave passive state if we in it */ + ftp_leave_passive_state(ftp); + + return 0; /* good return */ +} + + + + +/* FUNCTION: lslash() + * + * lslash() - format universal (UNIX) slashes '/' into local type. + * PC-DOS version. + * + * PARAM1: char * path + * + * RETURNS: + */ + +void +lslash(char * path) +{ + char * cp; + + for (cp = path; *cp; cp++) + if (*cp == '\\') /* DOS slash? */ + *cp = '/'; /* convert to normal slash */ +} + +/* fs_dir() - verify drive/directory exists. */ + + + +/* FUNCTION: fs_dir() + * + * PARAM1: ftpsvr * ftp + * + * RETURNS: + */ + +int +fs_dir(ftpsvr * ftp) +{ + /* for the sake of web browsers that start off with a cd /, we + will allow that the directory "/" exists */ + if (!strcmp(ftp->filename,"/")) + return TRUE; + /* otherwise the VFS is flat, so there are no directories */ + return FALSE; /* path/name not found */ +} + + + + +/* FUNCTION: fs_permit() + * + * fs_permit() - check if the logged in user has permision for this + * file operation. Returns TRUE or FALSE. + * + * PARAM1: ftpsvr * ftp + * + * RETURNS: + */ + +int +fs_permit(ftpsvr * ftp) /* verify user permission */ +{ + USE_ARG(ftp); + + return TRUE; +} + + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/app_ping.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/app_ping.h new file mode 100644 index 0000000..f62438f --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/app_ping.h @@ -0,0 +1,145 @@ +/* + * FILENAME: app_ping.h + * + * Copyright 2000 By InterNiche Technologies Inc. All rights reserved + * + * Header file for app_ping.c + * NOTE - this file may by included even if PING_APP is not defined in the + * system build, since UDP_ECHO and others use some of these values. + * + * MODULE: TCP + * + * PORTABLE: yes + */ + +#ifndef APP_PING_H +#define APP_PING_H 1 + +#include "in_utils.h" + +struct PingInfo +{ + u_long delay; /* delay between successive pings */ + u_long length; /* ping packet length */ + ip_addr ipadd; + u_long nextping; /* cticks value to do next ping */ + long times; /* number of times to ping */ + int out; + int in; + GEN_IO pio; /* To communicate with invocator of ping */ + struct PingInfo * next; /* Next ping packet */ +}; + +typedef struct PingInfo * PING_INFO ; + +extern ip_addr activehost; /* default ping host */ + +#define TIMEFOR1TICK (1000/TPS) /* Time between each tick in millisecs */ + + +int ping_init(void); +PING_INFO ping_new (void); +int ping_delete(PING_INFO p); +int ping_addq(PING_INFO p); +int ping_delq(PING_INFO p); +PING_INFO ping_search(GEN_IO pio); +int ping_start(void * pio); +int ping_send(PING_INFO p); +int ping_end(void * pio); +int ping_setdelay(void * pio); +int ping_setlength(void * pio); /* menu routine to set default ping size*/ +int ping_sethost(void * pio); /* set default host for pings, et.al. */ +int pingUpcall(PACKET p); +void ping_check(void); +PING_INFO ping_demux(ip_addr fhost); +int ping_stats(void * pio); + +#define PING_ALLOC(size) npalloc(size) +#define PING_FREE(ptr) npfree(ptr) + +/* Note that some of the error codes listed below have been + * reused by other functions in this module. + */ +#define PINGERRBASE 200 + +/* List of error codes returned by ping_delq() */ +#define PING_DELQ_BAD_OBJECT (PINGERRBASE+11) +#define PING_DELQ_Q_EMPTY (PINGERRBASE+12) +#define PING_DELQ_OBJ_NOT_FOUND (PINGERRBASE+13) + +/* List of error codes returned by ping_delete() */ +#define PING_DEL_NULL_ARGUMENT (PINGERRBASE+21) + +/* List of error codes returned by ping_start() */ +#define PING_ST_NOIP (PINGERRBASE+31) +#define PING_ST_BAD_ARG2 (PINGERRBASE+32) +#define PING_ST_ALLOC_ERR (PINGERRBASE+33) + +/* List of error codes returned by ping_end() */ +#define PING_END_NO_SESSION (PINGERRBASE+41) + +/* List of error codes returned by ping_setdelay() */ +#define PING_DELAY_BAD_ARG (PINGERRBASE+51) + +/* List of error codes returned by ping_setlength() */ +#define PING_LEN_BAD_ARG (PINGERRBASE+61) + +/* types of messages sent to PING client task from the console task, + * Telnet server task, or timer tick task. These messages provide + * configuration parameters, initiate (or terminate) ping requests, + * and provide periodic timeout notification. + */ +#define PING_CNTRL_START_PING 0x1 +#define PING_CNTRL_END_PING 0x2 +#define PING_CNTRL_SET_PARM 0x3 +#define PING_CNTRL_PERIODIC_TIMER 0x4 +#define PING_CNTRL_LIST_STATS 0x5 +#define PING_DATA_ECHO_REPLY 0x6 + +/* type of parameter sent in PING_CNTRL_SET_PARM message */ +#define PARM_TYPE_HOST 0x1 +#define PARM_TYPE_DELAY 0x2 +#define PARM_TYPE_LENGTH 0x3 + +/* structure of message sent to PING client task. Note that not all + * parameters are used in all of the messages. + */ +struct pingtask_msg +{ + struct pingtask_msg * next; + u_char type; + u_long parm1; + u_long parm2; + u_long parm3; + u_long parm4; + u_long parm5; +}; + +/* Counters used by PING client code to keep track of error conditions + * encountered during processing + */ +struct ping_err +{ + u_long alloc_fail; + u_long bad_msgtype; + u_long bad_parmtype; + u_long empty_q; +}; + +/* counters for the number of messages of various types received by + * the PING client task + */ +struct ping_msg_stats +{ + u_long start_ping; + u_long end_ping; + u_long set_parm; + u_long periodic_timer; + u_long list_stats; + u_long echo_reply; +}; + +extern struct queue pingRcvq; /* contains messages from other tasks */ + +#endif /* APP_PING_H */ + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/arp.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/arp.h new file mode 100644 index 0000000..8904e42 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/arp.h @@ -0,0 +1,127 @@ +/* + * FILENAME: arp.h + * + * Copyright 2000 By InterNiche Technologies Inc. All rights reserved + * + * ARP related constats and definitions. + * + * MODULE: INET + * + * + * PORTABLE: yes + */ + +/* Additional Copyrights: */ +/* Portions Copyright 1990 by NetPort Software. */ + + +#ifndef _ARP_H +#define _ARP_H 1 + +#define ET_ARP htons(0x0806) /* net endian 0x0806 */ +#define MACADDSIZ 6 /* biggest mac address we use */ + + +/* The ARP table entry structure. It is empty (unused) if t_pro_addr + * == 0L. The first three entrys match those specified by the MIB in + * rfc 1156 for the Address Translation Tables. + */ + +struct arptabent { + unsigned long t_pro_addr; /* protocol address */ + unsigned char t_phy_addr[6]; /* physical addr */ + struct net * net; /* interface for which this entry is valid */ + PACKET pending; /* packets waiting for resolution of this arp */ + u_long createtime; /* time entry was created (cticks) */ + u_long lasttime; /* time entry was last referenced */ + unshort flags; /* mask of the ET flags */ +}; + +#define MAXARPS 8 /* maximum mumber of arp table entries */ +extern struct arptabent arp_table[MAXARPS]; /* the actual table */ + +/* arp function prototypes */ +int etainit (void); /* init arp package */ +int arprcv (PACKET); /* arp received packet upcall */ +void at_entry (ip_addr, char*, int); /* make an entry in the arp table */ +void arpReply (PACKET ); +int et_send (PACKET pkt, struct arptabent * tp); +int send_arp (PACKET pkt, ip_addr dest_ip); +int send_via_arp (PACKET pkt, ip_addr dest_ip); + +struct arptabent * find_oldest_arp(ip_addr dest_ip); +struct arptabent * make_arp_entry(ip_addr dest_ip, NET net); + +#ifdef DYNAMIC_IFACES +int clear_arp_entries(ip_addr dest_ip, NET ifp); +#endif + +/* arp stats - In addition to MIB */ +extern unsigned arpReqsIn; /* requests received */ +extern unsigned arpReqsOut; /* requests sent */ +extern unsigned arpRepsIn; /* replys received */ +extern unsigned arpRepsOut; /* replys sent */ + + +/* Plummer's internals. All constants are already byte-swapped. */ +#define ARETH htons(1) /* ethernet hardware type */ +#define ARREQ htons(1) /* byte swapped request opcode */ +#define ARREP htons(2) /* byte swapped reply opcode */ +#define ARPIP htons(0x0800) /* IP type in net endian */ +#define ARPHW htons(1) /* arp hardware type for ethernet, in net endian */ +#define ARP8023HW htons(6) /* arp hardware type for IEEE 802.3 in net endian */ + +/* have two arp headers because of problems with some hardware insisting + * 32 bit fields must be on 32 bit boundaries. + */ + +#ifdef NO_CC_PACKING +/* the ARP header as it appears on the wire: */ +struct arp_wire { + unshort ar_hd; /* hardware type */ + unshort ar_pro; /* protcol type */ + char ar_hln; /* hardware addr length */ + char ar_pln; /* protocol header length */ + unshort ar_op; /* opcode */ + char data[20]; /* send IP, send eth, target IP, target eth */ +}; + +/* offsets to fields in arp_wire->data[] */ +#define AR_SHA 0 +#define AR_SPA 6 +#define AR_THA 10 +#define AR_TPA 16 +#endif /* NO_CC_PACKING */ + +/* THE ARP header structure, with special macros around it to help + * with declaring it "packed". Also se NO_CC_PACKING #define. + */ + +START_PACKED_STRUCT(arp_hdr) /* macro to optionally pack struct */ + unshort ar_hd; /* hardware type */ + unshort ar_pro; /* protcol type */ + char ar_hln; /* hardware addr length */ + char ar_pln; /* protocol header length */ + unshort ar_op; /* opcode */ + char ar_sha[6]; /* sender hardware address */ + ip_addr ar_spa; /* sender protocol address */ + char ar_tha[6]; /* target hardware address */ + ip_addr ar_tpa; /* target protocol address */ +END_PACKED_STRUCT(arp_hdr) + +/* bits for tp->flags */ +#define ET_ETH2 1 /* this IP address uses Ethernet II */ +#define ET_SNAP 2 /* this IP address uses snap headers */ + + +#ifdef IEEE_802_3 +/* 8 bytes of useless filler, required for IEEE 802.3 support */ +struct snap_hdr +{ + u_char llc_etc[6]; + unshort type; /* the pkt protocol, 0x0800 for IP, etc. */ +}; +#endif /* IEEE_802_3 */ + +#endif /* _ARP_H 1 */ + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/bsdsock.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/bsdsock.h new file mode 100644 index 0000000..91a259c --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/bsdsock.h @@ -0,0 +1,154 @@ +/* FILENAME: bsdsock.h + * + * Copyright 2000 InterNiche Technologies Inc. All rights reserved. + * + * BSD sockets porting aid + * + * #define BSD_SOCKETS in your ipport.h_h, and #include this in your + * application source to get the BSD-flavored sockets API. + * + * Then you get: + * BSD_SOCKET as a retargetable "socket" type + * BSD_SIZE_T as a retargetable "size" type + * BSD_TIMEVAL_T as a retargetable "struct timeval" type + * bsd_...() retargetable functions and macros for the BSD sockets API + * + * ...so you can write your code using these, and then re-target + * them to various sockets-like platforms (we supply the InterNiche + * target, but these should be straightforward for modern Un*x + * and mostly so for Winsock). + * + * MODULE: misclib + * ROUTINES: bsd_bind(), bsd_close(), bsd_connect(), bsd_errno(), + * bsd_listen(), bsd_recv(), bsd_send(), bsd_sendto(), + * bsd_shutdown(), bsd_socket() + * PORTABLE: yes + * + */ + +#ifndef BSDSOCK_H +#define BSDSOCK_H + +#include "tcpport.h" +#include "socket.h" +#include "sockcall.h" +#include "nptcp.h" + +/* + * BSD_SOCKET - the type of a socket. For InterNiche Release 1.x (x + * <= 7) sockets this is "long", so that is the default. For BSD it + * would be "int". For Winsock it would be "SOCKET". Don't change + * this, override this default with your own macro prior to including + * this file. + */ +#ifndef BSD_SOCKET +#define BSD_SOCKET long +#endif + +/* + * BSD_SIZE_T - the "size" type. For InterNiche Release 1.x (x <= 7) + * this is "int". + */ +#ifndef BSD_SIZE_T +#define BSD_SIZE_T int +#endif + +/* + * BSD_IN_ADDR_T - the "Internet Address" type. Must be able to + * hold a 32-bit IPv4 address. + */ +#ifndef BSD_IN_ADDR_T +#define BSD_IN_ADDR_T unsigned long +#endif + +/* + * BSD_TIMEVAL_T - the "struct timeval" type. bsd_select() needs a + * structure with these fields for its timeout parameter. + */ +#ifndef BSD_TIMEVAL_T +struct timeval +{ + long tv_sec; /* seconds */ + long tv_usec; /* and microseconds */ +}; +#define BSD_TIMEVAL_T struct timeval +#endif + +/* + * ioctl() request definitions + * + * The only ioctl() request presently supported is FIONBIO, so + * rather than define the whole _IOC macro family we just + * define FIONBIO. + */ +#define FIONBIO SO_NONBLOCK + +/* + * Some BSD sockets calls can be mapped to InterNiche sockets calls + * with straightforward macro definitions, so we do. + */ +#define bsd_bind(s, addr, addrlen) t_bind((s), (addr), addrlen) +#define bsd_close(s) t_socketclose((s)) +#define bsd_connect(s, addr, addrlen) t_connect((s), (addr), addrlen) +#define bsd_listen(s, backlog) t_listen((s), (backlog)) +#define bsd_recv(s, buf, len, flags) t_recv((s), (buf), (len), (flags)) +#define bsd_send(s, buf, len, flags) t_send((s), (buf), (len), (flags)) +#define bsd_sendto(s, msg, len, flags, to, tolen) \ + t_sendto((s), (msg), (len), (flags), (to), tolen) +#define bsd_shutdown(s, how) t_shutdown((s), (how)) +/* + * Altera Niche Stack Nios port modification: + * fix build warning + */ +#ifdef ALT_INICHE +#define bsd_socket(dom, type, proto) t_socket((dom), (type), (proto)) +#else +#define bsd_socket(dom, type, proto) t_socket((dom), (type), 0) +#endif +/* + * BSD errno isn't the best choice for a multithreaded environment. + * The InterNiche sockets API provides a per-socket error which can be + * read via t_errno(s). We suppose this could be re-targeted to errno + * for a Unix-like environment (or perhaps better, the SO_ERROR socket + * option), or WSAGetLastError() for a Winsock environment. + */ +#define bsd_errno(s) t_errno((s)) + +/* + * Some other BSD sockets calls require functions to do the mapping + * to InterNiche sockets calls; we provide the prototypes for those + * functions here, and the implementations in misclib/bsdsock.c. + */ +BSD_SOCKET bsd_accept(BSD_SOCKET s, + struct sockaddr * addr, int * addrlen); +int bsd_getpeername(BSD_SOCKET s, + struct sockaddr * addr, int * addrlen); +int bsd_getsockname(BSD_SOCKET s, + struct sockaddr * addr, int * addrlen); +int bsd_getsockopt(BSD_SOCKET s, + int level, + int name, + void * opt, int * optlen); +BSD_IN_ADDR_T bsd_inet_addr(char * cp); +int bsd_inet_aton(char * cp, struct in_addr * pin); +char * bsd_inet_ntoa(struct in_addr in); +int bsd_ioctl(BSD_SOCKET s, unsigned long request, ...); +int bsd_recvfrom(BSD_SOCKET s, + void * buf, + BSD_SIZE_T len, + int flags, + struct sockaddr * from, int * fromlen); +#ifdef SO_SELECT +int bsd_select(int nfds, + fd_set * readfds, + fd_set * writefds, + fd_set * exceptfds, + struct timeval * timeout); +#endif /* SO_SELECT */ +int bsd_setsockopt(BSD_SOCKET s, + int level, + int name, + void * opt, int optlen); + +#endif /* BSDSOCK_H */ + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/comline.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/comline.h new file mode 100644 index 0000000..3bdcd8b --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/comline.h @@ -0,0 +1,116 @@ +/* + * FILENAME: comline.h + * + * Copyright 2000 By InterNiche Technologies Inc. All rights reserved + * + * Definitions for comm lines to be used under PPP and SLIP. + * + * MODULE: INET + * + * PORTABLE: yes + */ + +/* Additional Copyrights: */ +/* Portions Copyright 1994, 1995 by NetPort Software. */ + + +#ifndef _COMLINE_H_ +#define _COMLINE_H_ + +#include "netbuf.h" + +/* Values for Line State ln_state. */ + +typedef enum { + LN_INITIAL, /* not set up yet */ + LN_DISCONNECTED, /* line not connected (idle) */ + LN_AUTOANS, /* line ready (e.g. mode in autoanswer mode) */ + LN_CONNECTING, /* line is connecting (e.g. modem dialing) */ + LN_CONNECTED, + LN_DISCONNECTING, /* e.g. modem in the process of hanging up */ + LN_BROKEN, /* hardware is missing, misconfigured, or broken */ + LN_RESETTING /* line is being reset - ignore incoming chars */ +} ln_states; + + +/* API structure for PPP and SLIP line IO. One of these structures is + * created for each instance where a line layer, (UART, modem, slip, PPP, + * etc.) interfaces with another line layer. Example: PPP over AT modem + * over RS232 would have two of these, one between PPP and modem and + * another between modem and RS232 UART. + */ + +struct com_line +{ + /* bring/check line up */ + int (*ln_connect)(struct com_line * lineptr); + + /* disconnect the line */ + int (*ln_disconnect)(struct com_line *); + + /* one of the send routines (the next two) may be NULL */ + int (*ln_putc)(struct com_line *, int byte); /* send single char */ + int (*ln_write)(struct com_line *, PACKET pkt); + + /* speed and state of the lower module */ + long ln_speed; /* most recent detected speed */ + ln_states ln_state; + + int (*ln_getc)(struct com_line *, int byte); /* receive single char */ + + /* types for the layers above and below this interface */ + int upper_type; + int lower_type; + + void * upper_unit; /* depends on upper_type, usually M_PPP */ + int lower_unit; /* legacy ID for lower (UART level) drivers */ +}; + +typedef struct com_line * LINEP; + +/* Values for upper_type and lower_type. Note that a modem could + * be both the lower layer to PPP code and upper layer to a + * UART driver. + */ + +#define LN_PPP 1 /* upper layer is PPP */ +#define LN_SLIP 2 /* upper layer is SLIP */ +#define LN_UART 3 /* lower layer is a UART */ +#define LN_ATMODEM 4 /* upper/lower layer is a modem */ +#define LN_PPPOE 5 /* lower layer is PPPOE */ +#define LN_LBXOVER 6 /* lower is loopback crossover (for test) */ +#define LN_PORTSET 7 /* (init) lower will be set by callback */ + + +/* UARTs under this line struct should support this API: */ + +/* logical line operations on UARTs: */ +extern int ln_uinit(LINEP line); /* assigned unit, sets up structs */ +extern int ln_uconnect(LINEP line); /* move to connected state */ +extern int ln_udisconnect(LINEP line); /* move to disconnected state */ +extern int ln_uputc(LINEP line, int byte); /* send a single byte */ + + +/* lowest level UART API */ +extern int uart_init(int unit); /* sets up hardware */ +extern int uart_putc(int unit, u_char); /* send character to comm port */ +extern int uart_getc(int unit); /* read next buffered char from com port */ +extern int uart_ready(int unit); /* returns TRUE if uart is ready to send a char */ +extern void uart_close(int unit); /* undoes uart_init */ +extern int uart_stats(void * pio, int unit); + +/* Struct contaning all configuration global params for Comport */ + +#ifdef USE_COMPORT +struct ComPortCfg +{ + int comport; /* PC comm port to default to */ + int LineProtocol; /* 1=PPP, 2=SLIP */ +}; + +extern struct ComPortCfg comportcfg; +#endif /* USE_COMPORT */ + +#endif /* _COMLINE_H_ */ + + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/crypt_api.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/crypt_api.h new file mode 100644 index 0000000..d5ff81f --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/crypt_api.h @@ -0,0 +1,245 @@ +/* + * FILENAME: crypt_api.c + * + * Copyright 1999-2004 by InterNiche Technologies Inc. All rights reserved. + * + * + * ROUTINES: + * ROUTINES: + * + */ +#ifndef _CRYPT_API_H_ +#define _CRYPT_API_H_ + +#define PRINT_BUFFER + +#define AES128_KEY_SIZE 16 +#define AES128_IV_SIZE 16 +#define DES64_KEY_SIZE 8 +#define DES64_IV_SIZE 8 +#define TDES192_KEY_SIZE 24 +#define TDES192_IV_SIZE 8 + + +#define MD5_DIGEST_LENGTH 16 +#define SHA1_DIGEST_LENGTH 20 +#define MAX_IV_SIZE 16 /* Max size of encryption IV */ +#define MAX_BLOCK_SIZE 16 /* Max size of encryption block */ +#define MAX_AUTH_DATA_SIZE 12 /* Bytes (96-bits) */ +#define MAX_DIGEST_SIZE 64 /* SHA-512 digest size in bytes */ +#define MAX_AUTH_KEY_SIZE 64 /* Max size of authentication key */ +#define MAX_ENCR_KEY_SIZE 64 /* Max size of encryption key */ +#define HMAC_MAX_CBLOCK 64 +#define ENTROPY_NEEDED 20 /* require 160 bits = 20 bytes of randomness */ + +/* + * IPSEC Algorithms + */ +/* ESP Transforms from RFC 2407 (IPSEC-DOI) */ +#define ALG_ESP_DES_IV4 1 +#define ALG_ESP_DES 2 +#define ALG_ESP_3DES 3 +#define ALG_ESP_RC5 4 +#define ALG_ESP_IDEA 5 +#define ALG_ESP_CAST 6 +#define ALG_ESP_BLOWFISH 7 +#define ALG_ESP_3IDEA 8 +#define ALG_ESP_DES_IV32 9 +#define ALG_ESP_RC4 10 +#define ALG_ESP_NULL 11 +#define ALG_ESP_AES 12 + +/* Private values used only at the API level. Not used internally */ +#define ALG_ESP_AES_128 201 +#define ALG_ESP_AES_192 202 +#define ALG_ESP_AES_256 203 + +/* ESP Authentication Algorithms */ +#define ALG_ESP_HMAC_NULL 0 /* private value, not defined by spec */ +#define ALG_ESP_HMAC_MD5 1 +#define ALG_ESP_HMAC_SHA 2 +#define ALG_ESP_HMAC_SHA_256 5 +#define ALG_ESP_HMAC_SHA_384 6 +#define ALG_ESP_HMAC_SHA_512 7 + +/* AH Transforms from RFC 2407 (IPSEC-DOI) */ +#define ALG_AH_NULL 0 +#define ALG_AH_MD5 2 +#define ALG_AH_SHA 3 +#define ALG_AH_DES 4 +#define ALG_AH_SHA_256 5 +#define ALG_AH_SHA_384 6 +#define ALG_AH_SHA_512 7 + +/* Compression Algorithms from RFC 2407 (IPSEC-DOI) */ +#define ALG_IPCOMP_OUI 1 +#define ALG_IPCOMP_DEFLATE 2 +#define ALG_IPCOMP_LZS 3 + +typedef struct DigestAlgs_s +{ + int alg; + int digest_len; + int ctx_len; + void (*init)(void *ctx); + void (*update)(void *ctx, unsigned char *data, int len); + void (*final)(unsigned char *digest, void *ctx); +} DigestAlgs; + +typedef struct HmacContext_s +{ + unsigned char ipad[64]; + unsigned char opad[64]; + const DigestAlgs *digest_alg; + void *digest_ctx; +} HmacContext; + +typedef struct KeyedContext_s +{ + int keylen; + DigestAlgs *digest_alg; + void *key; + void *digest_ctx; +} KeyedContext; + +typedef struct EncrAlgs_s +{ + int alg; + int blocksize; /* Algorithm block length (bytes) */ + int (*crypt)(unsigned char *in, unsigned int in_len, unsigned char *out, + unsigned int out_len, unsigned char *key, unsigned char *iv, int enc); +} EncrAlgs; + +EncrAlgs *enc_alg_lookup(int alg); +/* + * Generic HMAC authentication APIs + */ +HmacContext *hmac_init(int alg, unsigned char *key, int keylen); +void hmac_update(HmacContext *hctx, unsigned char *data, int len); +void hmac_final(HmacContext *hctx, unsigned char *digest, int len); +int hmac_digest_len(HmacContext *hctx); + +/* + * Generic Keyed authentication APIs + */ +KeyedContext *keyed_init(int alg, unsigned char *key, int keylen); +void keyed_update(KeyedContext *kctx, unsigned char *data, int len); +void keyed_final(KeyedContext *kctx, unsigned char *digest, int len); +int keyed_digest_len(KeyedContext *kctx); + +int aes_do(unsigned char *in, unsigned int in_len, unsigned char *out, + unsigned int out_len, unsigned char *key, unsigned char *iv, int enc); +int bf_do(unsigned char *in, unsigned int in_len, unsigned char *out, + unsigned int out_len, unsigned char *key, unsigned char *iv, int enc); + +int null_do(unsigned char *in, unsigned int in_len, unsigned char *out, + unsigned int out_len, unsigned char *key, unsigned char *iv, int enc); + +int des_do_ncbc(unsigned char *in, unsigned int in_len, unsigned char *out, + unsigned int out_len, unsigned char *key, unsigned char *iv, int enc); + +int des_do(unsigned char *in, unsigned int in_len, unsigned char *out, + unsigned int out_len, unsigned char *key, unsigned char *iv, int enc); + +int tdes_do(unsigned char *in, unsigned int in_len, unsigned char *out, + unsigned int out_len, unsigned char *key, unsigned char *iv, int enc); + +int hmac_ipsec_do(int alg_id, unsigned char *alg_key, int alg_keylen, void *in, + unsigned int in_offset, unsigned char *digest, unsigned int digest_len); + +int keyed_do_ipsec(int alg_id, unsigned char *alg_key, int alg_keylen, void *in, + unsigned int in_offset, unsigned char *digest, unsigned int digest_len); + +void md4_do(unsigned char *in, unsigned int in_len, unsigned char *digest); +char bits2hex(unsigned int num); +void convert2hex(char *out, char *msg, int size); +int sha1_do(unsigned char *digest, unsigned char *text, unsigned int text_len); +unsigned char *SHA1(const unsigned char *d, unsigned long n, unsigned char *md); +int sha1_do2(unsigned char *s1, int s1_len, unsigned char *s2, int s2_len, char *digest); +int sha1_do3(unsigned char *s1, int s1_len, unsigned char *s2, int s2_len, + unsigned char *s3, int s3_len, char *digest); +int sha1_do4(unsigned char *s1, int s1_len, unsigned char *s2, int s2_len, + unsigned char *s3, int s3_len, unsigned char *s4, int s4_len, char *digest); +int sha1_do5(unsigned char *s1, int s1_len, unsigned char *s2, int s2_len, + unsigned char *s3, int s3_len, unsigned char *s4, int s4_len, + unsigned char *s5, int s5_len, char *digest); +int sha1_do6(unsigned char *s1, int s1_len, unsigned char *s2, int s2_len, + unsigned char *s3, int s3_len, unsigned char *s4, int s4_len, + unsigned char *s5, int s5_len, unsigned char *s6, int s6_len, char *digest); + +int md5_do(unsigned char *digest, unsigned char *text, unsigned int text_len); +unsigned char *MD5(const unsigned char *d, unsigned long n, unsigned char *md); +int md5_do2(unsigned char *s1, int s1_len, unsigned char *s2, int s2_len, char *digest); +int md5_do3(unsigned char *s1, int s1_len, unsigned char *s2, int s2_len, + unsigned char *s3, int s3_len, char *digest); +int md5_do4(unsigned char *s1, int s1_len, unsigned char *s2, int s2_len, + unsigned char *s3, int s3_len, unsigned char *s4, int s4_len, char *digest); +int md5_do5(unsigned char *s1, int s1_len, unsigned char *s2, int s2_len, + unsigned char *s3, int s3_len, unsigned char *s4, int s4_len, + unsigned char *s5, int s5_len, char *digest); +int md5_do6(unsigned char *s1, int s1_len, unsigned char *s2, int s2_len, + unsigned char *s3, int s3_len, unsigned char *s4, int s4_len, + unsigned char *s5, int s5_len, unsigned char *s6, int s6_len, char *digest); +int des_do_ecb(unsigned char *in, unsigned char *out, unsigned char *key, int enc); + +int sha256_do(unsigned char *digest, unsigned char *text, unsigned int text_len); +int sha256_do2(unsigned char *s1, int s1_len, unsigned char *s2, int s2_len, char *digest); +int sha384_do(unsigned char *digest, unsigned char *text, unsigned int text_len); +int sha512_do(unsigned char *digest, unsigned char *text, unsigned int text_len); + +int p2k_md5(unsigned char *digest, unsigned char *text, unsigned int text_len); + +#ifdef PRINT_BUFFER +void print_buffer(unsigned char *buf, int len); +#endif + +void *alloc_md5_ctx(void); +void x_md5_init(void *ctx); +void x_md5_update(void *ctx, unsigned char *data, int len); +void x_md5_final(unsigned char *digest, void *ctx); + +void *alloc_sha1_ctx(void); +void x_sha1_init(void *ctx); +void x_sha1_update(void *ctx, unsigned char *data, int len); +void x_sha1_final(unsigned char *digest, void *ctx); + +void *alloc_sha256_ctx(void); +void x_sha256_init(void *ctx); +void x_sha256_update(void *ctx, unsigned char *data, int len); +void x_sha256_final(unsigned char *digest, void *ctx); + +void *alloc_sha384_ctx(void); +void x_sha384_init(void *ctx); +void x_sha384_update(void *ctx, unsigned char *data, int len); +void x_sha384_final(unsigned char *digest, void *ctx); + +void *alloc_sha512_ctx(void); +void x_sha512_init(void *ctx); +void x_sha512_update(void *ctx, unsigned char *data, int len); +void x_sha512_final(unsigned char *digest, void *ctx); + +void hmac_md5(unsigned char* auth_key, int key_len, unsigned char* text, + int text_len, unsigned char* digest); +void hmac_sha(unsigned char *k, int lk, unsigned char *d, int ld, + unsigned char *out, int t); + +int hmac_do(int alg_id, unsigned char *alg_key, int alg_keylen, unsigned char *in, + unsigned int in_len, unsigned char *digest, unsigned int digest_len); + +int hmac_do2(int alg_id, unsigned char *alg_key, int alg_keylen, unsigned char *s1, + unsigned int s1_len, unsigned char *s2, unsigned int s2_len, + unsigned char *digest, unsigned int digest_len); + +int hmac_do3(int alg_id, unsigned char *alg_key, int alg_keylen, unsigned char *s1, + unsigned int s1_len, unsigned char *s2, unsigned int s2_len, + unsigned char *s3, unsigned int s3_len, + unsigned char *digest, unsigned int digest_len); + +int rc4_do(unsigned char *in, unsigned int in_len, unsigned char *out, + unsigned char *key, unsigned key_len); + +int concat_buffer(void *in, unsigned char **out, unsigned int in_offset, unsigned int *out_len); + +void crypt_test(void); + +#endif /* _CRYPT_API_H_ */ diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/crypt_port.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/crypt_port.h new file mode 100644 index 0000000..df9a5c7 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/crypt_port.h @@ -0,0 +1,241 @@ +/* + * FILENAME: crypt_port.h + * + * Copyright 2002-2003 InterNiche Technologies Inc. All rights reserved. + * + * Crypt library configuration. + * + * MODULE: IPSECCRYPTO + * + * PORTABLE: yes + */ +#ifndef _CRYPT_PORT_H_ +#define _CRYPT_PORT_H_ + +/* You enable the defines that you need in your particular application +and undef the rest of the algorithms to reduce code space. */ +/* These are the highest level defines */ + +#define USE_MD5 1 +#define USE_SHA1 1 +#define USE_MD4 1 +#define USE_3DES 1 +#define USE_DES 1 +#define USE_RC4 1 +#define USE_BF 1 +#define USE_AES 1 +#define USE_SHA2 1 + +#define USE_HMAC 1 + +#ifdef NOT_USED +Make sure "NOT_USED" is really undefined + +/* Note SSL must be enables for this because it resides in SSL directory */ +#define USE_SSL_DSA 1 + +#endif + +/* This define is used in CryptoEngine. It might help the performance. But +this is totally platform dependent */ + +#define KICK_CRYPTO_ENGINE 1 + +/* This define compiles in the CryptoEngine demo. When you have IPSEC defined +and USE_SEC_HARDWARE make sure this is undefed because with this macro defined +different IDs are passed to hardware accelerator and therefore IPSEC would not +work properly. In real applications there is no need for INCLUDE_CE_DEMO anyway +and it should be undefed */ + +#define INCLUDE_CE_DEMO 1 + +/* This macro compiles in the hardware Security engine driver and links it +to the application code. For example it should be turned on in MCF5235 and MCF5485 +platforms */ + +/*#define USE_SEC_HARDWARE 1*/ + +/* Note that most of the time +either _HW or _SW macros for algorithms are enabled. But in some cases +depending on product configuration both macros might be enabled */ + +/* AES is isolated pretty good in current applicatiion code and +probably it is safe to either enable software or hardware support (assuming it is +available) for AES */ + +#ifdef USE_AES +#ifdef USE_SEC_HARDWARE +#define USE_AES_HW 1 +#else +#define USE_AES_SW 1 +#endif +#endif + +#ifdef USE_DES + +#ifdef USE_SEC_HARDWARE +#define USE_DES_HW 1 +#endif + +#define USE_DES_3DES 1 + +#endif /* USE_DES */ + +/* In the current code base 3DES is also pretty clean and +perhaps it is safe to define either _HW or _SW for 3DES +algorithm */ +#ifdef USE_3DES +#define USE_DES_3DES 1 + +#ifdef USE_SEC_HARDWARE +#define USE_3DES_HW 1 +#else +#define USE_3DES_SW 1 +#endif + +#endif /* USE_3DES */ + +#ifdef USE_DES_3DES +/* Here you can breakdown what you want to include even further */ +#define USE_DES_CBC_CKSM 1 /* only used in SSL */ +#define USE_DES_CFB64_EDE 1 /* only used in SSL */ +#define USE_DES_OFB64_EDE 1 /* only used in SSL */ +#define USE_DES_CFB64_ENC 1 /* only used in SSL */ +#define USE_DES_OFB64_ENC 1 /* only used in SSL */ +#define USE_DES_ECB3_ENC 1 /* only used in SSL */ +#define USE_DES_ECB_ENC 1 /* used in SSL and MSCHAP */ +#define USE_DES_XCBC_ENC 1 /* only used in SSL */ + +/*#define USE_DES_CFB_ENC 1*/ /* might be used in SSL */ +/*#define USE_DES_STR2KEY 1*/ /* might be used in SSL */ + +#endif + +#ifdef USE_MD5 + +#ifdef USE_SEC_HARDWARE +#define USE_MD5_HW 1 +#else +#define USE_MD5_SW 1 +#endif + +#ifdef INCLUDE_SNMPV3 /* P2K algorithm is only used in SNMPV3 */ +#ifdef USE_SEC_HARDWARE +#define USE_P2K_MD5_HW 1 /* This feature is not complete yet*/ +#else +#define USE_P2K_MD5_SW 1 +#endif +#endif + +#endif /* USE_MD5 */ + +#ifdef USE_SHA1 + +#ifdef USE_SEC_HARDWARE +#define USE_SHA1_HW 1 +#else +#define USE_SHA1_SW 1 +#endif + +#endif /* USE_SHA1 */ + + +#ifdef USE_HMAC + +#ifdef USE_SEC_HARDWARE +#define USE_HMAC_HW 1 +#define USE_HMAC_MD5_HW 1 +#define USE_HMAC_SHA_HW 1 +#else +#define USE_HMAC_SW 1 +#define USE_HMAC_MD5_SW 1 +#define USE_HMAC_SHA_SW 1 +#endif + +/* This macro could yield to hardware or software + computation based on definition of USE_HMAC_MD5_HW */ +#define USE_IPSEC_MD5 1 + +/* This macro could yield to hardware or software + computation based on definition of USE_HMAC_SHA_HW */ +#define USE_IPSEC_SHA 1 + +#ifdef USE_SHA2 +#define USE_HMAC_SHA_256 1 +#define USE_HMAC_SHA_384 1 +#define USE_HMAC_SHA_512 1 +#define USE_IPSEC_SHA_256 1 +#define USE_IPSEC_SHA_384 1 +#define USE_IPSEC_SHA_512 1 +#endif + +#endif /* USE_HMAC */ + +/* a lot of code from the asyrmmetric libraries still reside in SSL directory +and is not moved to crypt directory yet. Therefore compiling RSA require +SSL to be enabled. */ + +#ifdef ENABLE_SSL +#define USE_RSA 1 +#endif + +/* Only one for the following should be defined */ +/* The prime number generation stuff may not work when + * EIGHT_BIT but I don't care since I've only used this mode + * for debuging the bignum libraries */ +#undef SIXTY_FOUR_BIT_LONG +#undef SIXTY_FOUR_BIT +#define THIRTY_TWO_BIT +#undef SIXTEEN_BIT +#undef EIGHT_BIT + +#ifndef EIGHT_BIT +#define NUMPRIMES 2048 +#else +#define NUMPRIMES 54 +#endif + +#define CRYPT_MALLOC(size) npalloc(size) +#define CRYPT_FREE(p) npfree(p) +#define CRYPT_FREE_FUNC npfree +#define CRYPT_REALLOC(a,n) nprealloc(a,n) +#define CRYPT_ASSERT(x) + +#ifdef USE_PROFILER +#define CRYPT_TICKS() get_ptick() +#else +#define CRYPT_TICKS CTICKS +#endif /* USE_PROFILER */ + +/* This is just a CE demo macro. Is has no other significance. */ +#define CU_MAX_BUF_SIZE (64*40) + +/* port specific defines */ +#define CU_ACQUIRE_RESOURCE(x) ENTER_CRIT_SECTION(x) +#define CU_RELEASE_RESOURCE(x) EXIT_CRIT_SECTION(x) +#define CU_TK_YIELD tk_yield + +/* BIO library is only part of SSL code currently */ +#ifndef ENABLE_SSL +#define NO_BIO +#endif + +#define NO_FP_API +/*#define NO_STDIO*/ +#define NO_LHASH + +#if defined(ENABLE_SSL) || defined(IKE) || defined(IPSEC) + +#define MD_RAND 1 +#define CRYPT_LIB 1 +#define USE_BN 1 +#define USE_DH 1 +#define USE_CRYPT_RAND 1 +#define USE_RAND_WIN 1 +#define USE_CRYPT_STACK 1 +#define USE_CRYPT_ERR 1 +#define USE_CRYPT_LHASH 1 + +#endif + +#endif /* _CRYPT_PORT_H_ */ diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/dhcpclnt.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/dhcpclnt.h new file mode 100644 index 0000000..6b20426 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/dhcpclnt.h @@ -0,0 +1,266 @@ +/* + * FILENAME: dhcpclnt.h + * + * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved + * + * dhcpclnt.h - was bootp.h, and then dhcp.h, and the IETF commitees aren't + * through with this poor protocol yet... + * + * MODULE: INET + * + * PORTABLE: yes + */ + +/* Additional Copyrights: */ +/* Portions Copyright 1995-1996 by NetPort Software. */ + + +#ifndef _DHCPCLNT_H +#define _DHCPCLNT_H 1 + +/* List of enabled DHCP CLIENT options */ +#define DHCP_REQLIST 1 + +/* List of disabled DHCP CLIENT options */ +#ifdef NOTDEF +#define DHC_MAXDNSRVS 2 +#endif + +#ifdef USE_AUTOIP /* AutoIP requires DNS option */ +#define DHC_MAXDNSRVS 2 +#endif /* USE_AUTOIP */ + +#define BOOTP_SERVER_PORT 67 +#define BOOTP_CLIENT_PORT 68 + +/* DHCP packet types; from options field of bootp header */ +#define DHCP_INVALIDOP 99 +#define DHCP_DISCOVER 1 +#define DHCP_OFFER 2 +#define DHCP_REQUEST 3 +#define DHCP_DECLINE 4 +#define DHCP_ACK 5 +#define DHCP_NAK 6 +#define DHCP_RELEASE 7 + +/* DHCP options we support: */ + +#define DHOP_PAD 0 /* single char of padding, always 0 */ +#define DHOP_SNMASK 1 /* client's subnet mask */ +#define DHOP_ROUTER 3 /* set default router */ +#define DHOP_DNSRV 6 /* IP address of domain name server */ +#define DHOP_NAME 12 /* name (maybe DNS-ish) of host */ +#define DHOP_DOMAIN 15 /* name of host's domain */ + +#define DHOP_CADDR 50 /* client requested IP address */ +#define DHOP_LEASE 51 /* lease time */ +#define DHOP_OVLD 52 /* options are in sname and file fields too */ +#define DHOP_TYPE 53 /* DHCP type of pkt; 1-7 above */ +#define DHOP_SERVER 54 /* server ID (IP address) */ +#define DHOP_REQLIST 55 /* client's parameter request list */ +#define DHOP_MSG 56 /* message text explaining NAK or DECLINE */ +#define DHOP_MAXSIZE 57 /* maximum DHCP message size */ +#define DHOP_RENEWAL 58 /* renewal (T1) time */ +#define DHOP_REBINDING 59 /* rebinding (T2) time */ +#define DHOP_CLIENT 61 /* client ID (i.e. hardware address) */ +#define DHOP_END 255 /* marks end of valid options */ + +/* DHCP Client per-net states (for dhc_state). The states are as per + * the description in RFC2131. DHCS_RESTARTING is a transient state. + * It is just used to inform the application layer(user) that DHCP + * Client is restarting the negotiation. Following is an example + * + * 1. Client sends a REQUEST (it might be in DHCS_REBOOTING or + * DHCS_REQUESTING state). + * 2. Client doesn't receive a ACK/NAK. It retransmits + * 3. After few retransmits (as per RFC2131), the client needs to move back + * to DHCS_INIT state. At this time, the user needs to be informed + * that the client is restarting. + * 4. The Client calls the callback with state as DHCS_RESTARTING. + * 5. The Client moves to DHCS_INIT state. + * + * There is another example where DHCS_RESTARTING is used. + * 1. Client is in DHCS_BOUND state. At the required time (when lease timer + * t1 expires), it will move to DHCS_RENEWING state. It sends a REQUEST + * to renew the lease + * 2. No ACK/NAK is received in DHCS_RENEWING state. When lease timer t2 + * expires, the Client moves to DHCS_REBINDING state, and sends a + * REQUEST to rebind the current IP address. + * 3. If no ACK/NAK comes and the lease expires, then the client should + * stop all network processing and request network reinitialization. + * That is, the IP address of the interface should be cleared and + * Client should move to DHCS_INIT state. At this time, the user needs + * to be informed that the client is restarting. + * 4. The Client calls the callback with state as DHCS_RESTARTING. + * 5. The Client moves to DHCS_INIT state. + * + */ + +#define DHCS_UNUSED 0 /* no discovery attempted */ +#define DHCS_INIT 1 /* Ready to send a DISCOVER packet */ +#define DHCS_INITREBOOT 2 /* Have IP, ready to send REQUEST(skip DISCOVER)*/ +#define DHCS_REBOOTING 3 /* rebooting/reclaiming address */ +#define DHCS_SELECTING 4 /* discovery sent, but no offer yet */ +#define DHCS_REQUESTING 5 /* sent request; waiting for ACK|NAK */ +#define DHCS_BOUND 6 /* got a ACK we liked */ +#define DHCS_RENEWING 7 /* Renewing the lease */ +#define DHCS_REBINDING 8 /* rebinding to new server */ +#define DHCS_RESTARTING 9 /* Temp. state. Only to inform callback() */ + +/* macro for writing IP address options to the options buffer. +Assumes the IP address is in local endian. */ +#if(BYTE_ORDER == BIG_ENDIAN) +#define PUT_IP_OPT(ptr, code, ip) { \ + *ptr++ = code; \ + *ptr++ = 4; \ + *(ptr++) = *(char*)(&ip); \ + *(ptr++) = *(((char*)(&ip))+1); \ + *(ptr++) = *(((char*)(&ip))+2); \ + *(ptr++) = *(((char*)(&ip))+3); \ + } +#else +#define PUT_IP_OPT(ptr, code, ip) { \ + *ptr++ = code; \ + *ptr++ = 4; \ + *(ptr+3) = *(char*)(&ip); \ + *(ptr+2) = *(((char*)(&ip))+1); \ + *(ptr+1) = *(((char*)(&ip))+2); \ + *(ptr) = *(((char*)(&ip))+3); \ + ptr += 4; \ + } +#endif + +/* macro for writing string options to the options buffer */ +#define PUT_STRING_OPT(ptr, code, string) { int len;\ + *ptr++ = code; \ + len = strlen(string); \ + *ptr++ = (u_char)len; \ + strncpy((char*)ptr, (char*)string, len); \ + ptr += len; \ + } + +/* macro to extract IP option. extracted address is in NET endian */ +#define EXTRACT_IP_OPT(ptr, ip) { \ + ptr++; \ + (ip) = *(long*)(ptr); \ + } + +#define BOOTREQUEST 1 /* packet op codes */ +#define BOOTREPLY 2 + +/* DHCP hardware typres, from ARP section of RFC1700 */ +#define ETHHWTYPE 1 /* ethernet hardware type */ +#define LINEHWTYPE 20 /* Serial line hardware type */ + +#define RFC1084_MAGIC_COOKIE htonl(0x63825363) +#define RFC1084_PAD ((unsigned char) 0) +#define RFC1084_SUBNET_MASK ((unsigned char) 1) +#define RFC1084_GATEWAY ((unsigned char) 3) +#define RFC1084_END ((unsigned char) 255) + +#define WHITESPACE "\n\t " + +#define ADDR_ERR_STRING "Invalid ethernet address" + +#define xtoi(x) ((x>='a')&&(x<='f')?(x-'a'+10):((x>='A')&&(x<= 'F')?(x-'A'+10):(x-'0'))) + +#define OP 0 +#define HTYPE 1 +#define HLEN 2 +#define HOPS 3 +#define CIADDR 12 +#define YIADDR 16 +#define SIADDR 20 +#define CHADDR 28 + +#define BOOTP_OPTSIZE 64 /* older value */ +#define DHCP_OPTSIZE 312 /* newer value */ + +/* bit we mask into the op field of received packets internally. + * This is set if the packet is DHCP (as opposed to plain bootp) + */ +#define ISDHCP 0x04 +#define isdhcp(bp) (bp->op & ISDHCP) + + +/* The structure of a bootp/dhcp packet. This is the + * UDP data area of a bootp or dhcp packet. + */ + +struct bootp { + unsigned char op; + unsigned char htype; + unsigned char hlen; + unsigned char hops; + unsigned long xid; + unsigned short secs; + unsigned short flags; + unsigned long ciaddr; + unsigned long yiaddr; + unsigned long siaddr; + unsigned long giaddr; + unsigned char chaddr[16]; + unsigned char sname[64]; + unsigned char file[128]; + unsigned char options[BOOTP_OPTSIZE]; /* was "vend" for bootp */ +}; + +/* define sizes for both old bootppackets and newer dhcop packets. + * Need to be aware the Windows95 and other broken systems send DHCP + * packets in the bootp size, so you need to check both size and + * options to + */ +#define BOOTPSIZE (sizeof(struct bootp)) +#define DHCPSIZE (BOOTPSIZE + (DHCP_OPTSIZE-BOOTP_OPTSIZE)) + +/* dhcp utility routines */ +u_char * find_opt(u_char opcode, u_char * opts); + +/* DHCP client per-interface state: */ +struct dhc_state { + unsigned state; /* one of the "DHCS" states below */ + int tries; /* retry count of current state */ + u_long xid; /* last xid sent */ + u_short secs; /* seconds since client came up */ + u_long last_tick; /* time of last DHCP packet */ + u_long lease; /* lease; only valid if state == DHCS_BOUND */ + u_long t1 ; /* lease related - renew timer */ + u_long t2 ; /* lease related - rebind timer */ + u_long lease_start; /* time in cticks of when lease started */ + + /* Configuration options of outstanding request */ + ip_addr ipaddr; /* IP address */ + ip_addr snmask; /* subnet mask */ + ip_addr defgw; /* default gateway (router) */ + + ip_addr rly_ipaddr; /* IP addr of our RELAY agent (if any) */ + + /* IP Address of the DHCP Server. + * Needed to send unicast when renewing IP Addr + */ + ip_addr srv_ipaddr; + +#if defined(DHC_MAXDNSRVS) && (DHC_MAXDNSRVS > 0) + ip_addr dnsrv[DHC_MAXDNSRVS]; /* domain name server addresses */ +#endif /* DHC_MAXDNSRVS */ + + int (*callback)(int iface, int state); /* callback when IPaddress set */ +}; + +extern struct dhc_state dhc_states[MAXNETS]; /* DHCP client state of each net*/ + +/* DHCP client entry points */ +int dhc_init (void); +int dhc_second (void); +int dhc_alldone (void); +int dhc_ifacedone (int iface); +void dhc_state_init (int iface, int init_flag); +void dhc_halt (int iface); +void dhc_set_callback(int iface, int (*routine)(int,int) ); +int dhc_stats (void *pio); + + +#endif /* _DHCPCLNT_H */ + + + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/dns.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/dns.h new file mode 100644 index 0000000..345634f --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/dns.h @@ -0,0 +1,216 @@ +/* + * FILENAME: dns.h + * + * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved + * + * DNS defines for NetPort IP stack. + * + * MODULE: INET + * + * + * PORTABLE: yes + */ + + +#ifndef _DNS_H_ +#define _DNS_H_ 1 + +/* set defaults of DNS variables, may override in ipport.h */ + +#ifndef MAXDNSNAME +#define MAXDNSNAME 256 /* max length of name including domain */ +#endif + +#ifndef MAXDNSUDP +#define MAXDNSUDP 512 /* MAX allowable UDP size */ +#endif + +#ifndef MAXDNSSERVERS +#define MAXDNSSERVERS 3 /* MAX number of servers to try */ +#endif + +#ifndef MAXDNSADDRS +#define MAXDNSADDRS 10 /* MAX IP addresses to return via gethostbyname() */ +#endif + +#ifndef MAXDNSALIAS +#define MAXDNSALIAS 2 /* MAX number of alias names */ +#endif + +#define DNS_QUERY 0 /* Op code for query */ +#define DNS_UPDT 5 /* Op code for UPDATE request */ + +/* DNS Record types */ +#define DNS_TYPE_QUERY 0 /* Type value for question record */ +#define DNS_TYPE_IPADDR 1 /* Type value for IPv4 address */ +#define DNS_TYPE_AUTHNS 2 /* Authoritative name server */ +#define DNS_TYPE_ALIAS 5 /* Alias for queried name */ +#define DNS_TYPE_PTR 12 /* Domain Name pointer */ +#define DNS_TYPE_AAAA 0x1c /* IPv6 address ("AAAA" record) */ + +/* Description of data base entry for a single host. */ +struct hostent +{ + char * h_name; /* Official name of host. */ + char **h_aliases; /* Alias list. */ + int h_addrtype; /* Host address type. */ + int h_length; /* Length of address. */ + char **h_addr_list; /* List of addresses from name server. */ +#define h_addr h_addr_list[0] /* Address, for backward compatibility. */ + +#ifdef DNS_CLIENT_UPDT + /* Extra variables passed in to Dynamic DNS updates. */ + char * h_z_name; /* IN- zone name for UPDATE packet */ + ip_addr h_add_ipaddr; /* IN- add this ip address for host name in zone */ + u_long h_ttl; /* IN- time-to-live field for UPDATE packet */ +#endif /* DNS_CLIENT_UPDT */ +}; + + +/* basic internal structure of a client DNS entry. This one structure does double + * duty as a request manager and database entry. + */ + +struct dns_querys +{ + struct dns_querys * next; + u_long send_time; /* ctick when last request was sent/received */ + u_long expire_time; /* second (local) when this data expires */ + unshort tries; /* retry count */ + unshort lport; /* local (client) UDP port, for verification */ + unshort id; /* ID of request, 0 == unused entry. */ + int replies; /* number of replys to current request */ + int ipaddrs; /* count of entries in ipaddr_list[] */ + ip_addr ipaddr_list[MAXDNSADDRS]; /* IP addresses (net endian) */ + char * addrptrs[MAXDNSADDRS]; /* pointers, for hostent.h_addr_list */ + int err; /* last ENP_ error if, if any */ + int rcode; /* last response code if replys > 1 */ + char dns_names[MAXDNSNAME]; /* buffer of names (usually w/domain) */ + char ptr_name[MAXDNSNAME]; /* The result of PTR query is stored here (just one for now) */ + ip_addr auths_ip; /* IPv4 addresses of 1st auth server */ + char * alist[MAXDNSALIAS+1]; /* alias list, points into dns_names */ + + /* Most DNS queries need a hostent structure to return the data to + * the calling application; so we embed the hostent structure inside + * the query structure - one less alloced buffer to keep track of. + */ + struct hostent he; /* for return from gethostbyname() */ + char type; /* type of original query */ + +#ifdef IP_V6 + int ip6addrs; /* count of entries in ip6_list */ + char ip6_list[MAXDNSADDRS][16]; /* IPv6 address from answers */ + char auths_ip6[16]; /* IPv6 addresses of 1st auth server */ +#endif /* IP_V6 */ +}; + + +/* List of DNS objects */ +extern struct dns_querys * dns_qs; + +/* Macros to allocate & free DNS objects */ +#ifndef DNC_ALLOC +#define DNC_ALLOC(size) (struct dns_querys *)npalloc(size) +#define DNC_FREE(ptr) npfree((void *)ptr) +#endif + +/* pending requests, can be used as a flag to spin dnsc_check() task */ +extern unsigned dnsc_active; + +/* DNS client statistics: */ +extern ulong dnsc_errors; /* protocol/implementation runtime errors */ +extern ulong dnsc_requests; /* requests sent */ +extern ulong dnsc_OK; /* OK replys received */ +extern ulong dnsc_unks; /* error (unknown) replys received */ +extern ulong dnsc_tmos; /* timeouts */ + + +/* DNS operational parameters which can be set at run time */ +extern ip_addr dns_servers[MAXDNSSERVERS]; + +#ifdef DNS_CLIENT_UPDT +extern char soa_mname[MAXDNSNAME]; +#endif /* DNS_CLIENT_UPDT */ + +extern unsigned dns_firsttry; /* time to first retry, in seconds */ +extern unsigned dns_trys; /* max number of retrys */ + + + +/* header format of a DNS packet over UDP */ +START_PACKED_STRUCT(dns_hdr) + unshort id; /* 16 bit unique query ID */ + unshort flags; /* various bit fields, see below */ + unshort qdcount; /* entries in the question field */ + unshort ancount; /* resource records in the answer field */ + unshort nscount; /* name server resource records */ + unshort arcount; /* resource records in the additional records */ +END_PACKED_STRUCT(dns_hdr) + +#define DNS_PORT 53 /* DNS reserved port on UDP */ + +/* DNS header flags field defines */ +#define DNSF_QR 0x8000 /* query (0), or response (1) */ +#define DNSF_OPMASK 0x7800 /* 4 bit opcode kinds of query, 0==standard */ +#define DNSF_AUTHOR 0x0400 /* authoritative */ +#define DNSF_RECUR 0x0100 /* recursion */ +#define DNSF_NONAME 0x0003 /* No such name. */ +#define DNSF_AA 0x0400 /* set if Authoritive Answers */ +#define DNSF_TC 0x0200 /* set if truncated message */ +#define DNSF_RD 0x0100 /* Recursion Desired bit */ +#define DNSF_RA 0x0080 /* Recursion Allowed bit */ +#define DNSF_Z 0x0070 /* 3 reserved bits, must be zero */ +#define DNSF_RCMASK 0x000F /* Response Code mask */ + +/* Reponse Code values: */ +#define DNSRC_OK 0 /* good response */ +#define DNSRC_EFORMAT 1 /* Format error */ +#define DNSRC_ESERVER 2 /* Server Error */ +#define DNSRC_ENAME 3 /* Name error */ +#define DNSRC_EIMP 4 /* Not Implemented on server */ +#define DNSRC_EREFUSE 5 /* Server refused operation */ +#define DNSRC_UNSET 0xFF /* No reponse yet (used only in dns_querys struct) */ + +#ifdef DNS_CLIENT_UPDT + +/* Error codes used within Dynamic DNS Update operation */ +#define DNSRC_EDOMAIN 6 /* Some name that ought not to exist, exists */ +#define DNSRC_ERRSET 7 /* Some RRset that ought not to exist, exists*/ +#define DNSRC_ENRRSET 8 /* Some RRset that ought to exist, does not */ +#define DNSRC_NOTAUTH 9 /* Server is not authoritative for the zone */ + /* named in the zone section */ +#define DNSRC_NOTZONE 10 /* A name used within the Update section */ + /* is not within the zone denoted */ +#define DNS_CLASS_NONE 254 /* CLASS NONE */ + +#endif /* DNS_CLIENT_UPDT */ + +/* DNS client external entry points: */ +int dns_query(char * name, ip_addr * ip); /* start a DNS query */ +int dns_lookup(ip_addr * ip, char * name); /* check query status */ +void dnsc_check(void); /* spin once a second to drive retrys & timeouts */ + +/* New (for v2.0) version of dns_query(), which takes a record type + * argument and fills in a pointer to the dns_query structure. + */ +int dns_query_type(char * name, char type, ip_addr ipaddr, + unsigned long ttl, struct dns_querys ** dns_ptr); + +/* flags for in_reshost(); */ +#define RH_VERBOSE 0x01 /* do informational printfs */ +#define RH_BLOCK 0x02 /* block with call to tk_yield() */ +int in_reshost(char * host, ip_addr * address, int flags); + + +/* Return entry from host data base for host with NAME. This could be + * in sockcall.h but is here because a non-TCP used may want DNS. + */ +struct hostent * gethostbyname(char * name); +int nslookup(char * name, char type, struct dns_querys **dns_entry); + +/* ....And the crufty v6 version (RFC2133).... */ +struct hostent * gethostbyname2(char * name, int af); + +#endif /* _DNS_H_ */ + + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/dnsport.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/dnsport.h new file mode 100644 index 0000000..3f17096 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/dnsport.h @@ -0,0 +1,40 @@ +/* + * FILENAME: dnsport.h + * + * Copyright 2000 By InterNiche Technologies Inc. All rights reserved + * + * + * MODULE: DNS + * + * + * PORTABLE: no + */ + +/* dnsport.h + * + * Per-port DNS definition. Most of these are pretty much the same on all + * systems, but may require tuning for weird cases + */ + +#ifndef _DNSPORT_H_ +#define _DNSPORT_H_ 1 + +#define UDPPORT_DNS 53 /* UDP port to use */ + +typedef short int16_t; +typedef unsigned short u_int16_t; +typedef unsigned long u_int32_t; + + +#ifndef NO_TIME_T +typedef unsigned long time_t; + +/* a unix-y timeval structure */ +struct timeval { + unsigned long tv_sec; + unsigned long tv_usec; +}; +#endif + +#endif /* _DNSPORT_H_ */ + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/ether.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/ether.h new file mode 100644 index 0000000..62d88f7 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/ether.h @@ -0,0 +1,94 @@ +/* + * FILENAME: ether.h + * + * Copyright 2000 By InterNiche Technologies Inc. All rights reserved + * + * information common to all ethernet drivers + * + * MODULE: INET + * + * + * PORTABLE: yes + */ + +/* Additional Copyrights: */ +/* Portions Copyright 1990, 1993 by NetPort Software. */ +/* Portions Copyright 1986 by Carnegie Mellon */ +/* Portions Copyright 1983, 1985 by the Massachusetts Institute of Technology */ + +#ifndef _ETHER_H_ +#define _ETHER_H_ 1 + + +/* initialization modes: 0 = rcv normal + broadcast packets */ +#define LOOPBACK 0x01 /* send packets in loopback mode */ +#define ALLPACK 0x02 /* receive all packets: promiscuous */ +#define MULTI 0x04 /* receive multicast packets */ + +/* ethernet packet header */ + +START_PACKED_STRUCT(ethhdr) +u_char e_dst[6]; +u_char e_src[6]; +unshort e_type; +END_PACKED_STRUCT(ethhdr) + +/* ETHHDR_SIZE - size of packet header structure for allocation + * purposes Note this is a default -- it should be overridden in + * ipport.h if the need arises. + */ + +#ifndef ETHHDR_SIZE +#define ETHHDR_SIZE (sizeof(struct ethhdr)) +#endif /* ETHHDR_SIZE */ + +/* ETHHDR_BIAS - where to locate the struct ethhdr within the + * allocated space, as an offset from the start in bytes Note this is + * a default -- it should be overridden in ipport.h if the need + * arises. + */ + +#ifndef ETHHDR_BIAS +#define ETHHDR_BIAS 0 +#endif /* ETHHDR_BIAS */ + +/* ET_DSTOFF - offset of destination address within Ethernet header + */ +#define ET_DSTOFF (0) + +/* ET_SRCOFF - offset of source address within Ethernet header + */ +#define ET_SRCOFF (6) + +/* ET_TYPEOFF - offset of Ethernet type within Ethernet header + */ +#define ET_TYPEOFF (12) + +/* ET_TYPE_GET(e) - get Ethernet type from Ethernet header pointed to + * by char * e + * Note returned Ethernet type is in host order! + */ +#define ET_TYPE_GET(e) \ + (((unsigned)(*((e) + ET_TYPEOFF)) << 8) + \ + (*((e) + ET_TYPEOFF + 1) & 0xff)) + +/* ET_TYPE_SET(e, type) - set Ethernet type in Ethernet header pointed to + * by char * e to value (type) + * Note Ethernet type is value is expected to be in host order! + */ +#define ET_TYPE_SET(e, type) \ + *((e) + ET_TYPEOFF) = (unsigned char)(((type) >> 8) & 0xff); \ + *((e) + ET_TYPEOFF + 1) = (unsigned char)((type) & 0xff); + +/* minimum & maximun length legal ethernet packet sizes */ +#define ET_MINLEN 60 +#define ET_MAXLEN 1514 +#define MINTU 60 +#define MTU 1514 + +extern unsigned char ETBROADCAST[]; + +#endif /* _ETHER_H_ */ + + + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/genlist.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/genlist.h new file mode 100644 index 0000000..45c9d87 --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/genlist.h @@ -0,0 +1,142 @@ +/* + * FILENAME: GENLIST.H + * + * Copyright 1999-2002 By InterNiche Technologies Inc. All rights reserved + * + * MODULE: MISCLIB + * + * ROUTINES: + * + * PORTABLE: yes + */ + +/* Additional Copyrights: */ + +/* + * GENERIC Implementation of a list. + * + * 1999 - Implemented for use with SNMPv3 tables -AT- + * 2/21/2002 - Added niche_add_sorted() and moved from snmpv3 to h -AT- + */ + + +#ifndef GENLIST_H /* Make sure the header file is included only once */ +#define GENLIST_H 1 + +#include "ipport.h" + +/* Generic list is used by SNMPv3 code and IPFILTER code. */ +#if (defined(INCLUDE_SNMPV3) || defined(USE_IPFILTER) || defined(INICHE_SYSLOG)) +#define USE_GENLIST 1 +#endif + +#define GEN_MAX_ARRAY 10 + +#ifndef GEN_ALLOC +#define GEN_ALLOC(size) npalloc(size) +#endif +#ifndef GEN_FREE +#define GEN_FREE(ptr) npfree(ptr) +#endif + +#ifndef MEMCMP +#define MEMCMP memcmp +#endif +#ifndef MEMCPY +#define MEMCPY memcpy +#endif + +#ifndef SUCCESS +#define SUCCESS 0 +#endif +#ifndef FAILURE +#define FAILURE 1 +#endif + + +#ifndef MAX_NAME_LEN /* usually defined in snmpport.h */ +#define MAX_NAME_LEN 64 /* max number of subid's in a objid */ +#endif + +/* NicheElement had two members. One is a pointer to the DATA and the + * other is a pointer to the next element. If there is no next + * element, the pointer is NULL. GEN_STRUCT can be anything. + * Following are some thoughts on the way things are declared and + * intended. + * 1. If there is only one list, GEN_STRUCT can be + * explicitly named to the STRUCT/CLASS + * 2. If there are multiple lists, then GEN_STRUCT can be "void*" + * and casting can be done whenever we are using it + * 3. If we need a CLASS implementation, all the functions can be + * made as interfaces of the CLASS. So we just + * need a class wrapper. Further, it is assumed that GEN_STRUCT has + * two members defined as follows + * "long id;" + * "char name[MAX_NAME_LEN];" + * The list can be a singly indexed list (that + * is all elements can be uniquely identified by their IDs). Or it + * can be doubly indexed list (all elements can be uniquely + * identified by their ID and name combined). Lookup and deletion + * from the list has been provided for this use. + */ +struct TemplateStruct +{ + long id; + char name[MAX_NAME_LEN]; +}; + +typedef struct TemplateStruct * GEN_STRUCT ; + +struct NicheElement +{ + GEN_STRUCT p_data; /* Pointer to element/data */ + struct NicheElement * next; /* Pointer to next data element */ +}; + +typedef struct NicheElement * NICHE_ELE; + + +struct NicheList +{ + NICHE_ELE head ; /* First element of the list */ + int len_of_element;/* Len of the struct representing element/data*/ +}; + +typedef struct NicheList * NICHELIST; + + +int niche_list_constructor (NICHELIST list, int len_of_ele); +int niche_list_destructor (NICHELIST list); +int niche_add (NICHELIST list, GEN_STRUCT ptr_data); +int niche_add_sorted (NICHELIST list, GEN_STRUCT ptr_data); +int niche_add_id_and_name (NICHELIST list, long id, char * name); +int niche_del (NICHELIST list, GEN_STRUCT ptr_data); +int niche_del_id (NICHELIST list, long id); +int niche_del_name (NICHELIST list, char * name); +int niche_del_id_and_name (NICHELIST list, long id, char * name); +GEN_STRUCT niche_lookup_id (NICHELIST list, long id); +GEN_STRUCT niche_lookup_name (NICHELIST list, char *name); +GEN_STRUCT niche_lookup_id_and_name(NICHELIST list, long id, char *name); +int niche_lookup_multi_match(NICHELIST list, long id, char * name, + GEN_STRUCT matches[]); +int niche_list_show (NICHELIST list); +int niche_list_len (NICHELIST list); +GEN_STRUCT niche_list_getat (NICHELIST list,int index); +int niche_element_show (GEN_STRUCT ptr_data); + + + +#define NICHE_ERRBASE 2000 + +#define NICHE_NO_MEM (NICHE_ERRBASE+1) +#define NICHE_NO_MEM_FOR_DATA (NICHE_ERRBASE+2) +#define NICHE_ADD_NOT_ENOUGH_MEMORY (NICHE_ERRBASE+3) +#define NICHE_DEL_LIST_EMPTY (NICHE_ERRBASE+4) +#define NICHE_DEL_NOT_FOUND (NICHE_ERRBASE+5) +#define NICHE_DEL_NOT_ENOUGH_MEMORY (NICHE_ERRBASE+6) +#define NICHE_LISTPTR_INVALID (NICHE_ERRBASE+7) +#define NICHE_DUP_ENTRY (NICHE_ERRBASE+8) + + +#endif /* GENLIST_H */ + diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/htcmptab.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/htcmptab.h new file mode 100644 index 0000000..cd22b3e --- /dev/null +++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/htcmptab.h @@ -0,0 +1,123 @@ +/* htcmptab.h + * + * Copyright 1996 2001 by NetPort software. All rights reserved. + * + * Compression table for HTML compression. This files contains + * static data & thus should be included in only ONE source file per + * executable. + * +!!!!!!!!!!!!!!!!!! W A R N I N G !!!!!!!!!!!!!!!!!!!! + * If you change this table, be sure to recompile BOTH the VFS tables + * AND your application. If you don't do this you will get lots of + * subtle, hard to find errors. + */ + +#ifndef _HTCMPTAB_H_ +#define _HTCMPTAB_H_ + +/* A one byte insertion value is derived for each of the + * following common HTML strings by the following: + * + * low 7 bits is offset into array + * high bit always on + */ + +char * htmltags[] = { +" ", +" ", +"", +"", +" ", +"\r\n", +"