diff --git a/Documentation/Flussdichteschätzung.xlsx b/Documentation/Flussdichteschätzung.xlsx new file mode 100644 index 0000000..329ebe6 Binary files /dev/null and b/Documentation/Flussdichteschätzung.xlsx differ diff --git a/Documentation/HIT_v2_technical_description-flat-compressed.pdf b/Documentation/HIT_v2_technical_description-flat-compressed.pdf new file mode 100644 index 0000000..33bbf64 Binary files /dev/null and b/Documentation/HIT_v2_technical_description-flat-compressed.pdf differ diff --git a/Documentation/LIBC HIT Version 1.5 C12 V8.xlsx b/Documentation/LIBC HIT Version 1.5 C12 V8.xlsx new file mode 100644 index 0000000..6e1ecd5 Binary files /dev/null and b/Documentation/LIBC HIT Version 1.5 C12 V8.xlsx differ diff --git a/Documentation/LIBC HIT Version 1.5 He4 V1.xlsx b/Documentation/LIBC HIT Version 1.5 He4 V1.xlsx new file mode 100644 index 0000000..a1d1fa5 Binary files /dev/null and b/Documentation/LIBC HIT Version 1.5 He4 V1.xlsx differ diff --git a/Documentation/LIBC HIT Version 1.5 O16 V2.xlsx b/Documentation/LIBC HIT Version 1.5 O16 V2.xlsx new file mode 100644 index 0000000..168976a Binary files /dev/null and b/Documentation/LIBC HIT Version 1.5 O16 V2.xlsx differ diff --git a/Documentation/LIBC HIT Version 1.5 p V11.xlsx b/Documentation/LIBC HIT Version 1.5 p V11.xlsx new file mode 100644 index 0000000..f6b12ed Binary files /dev/null and b/Documentation/LIBC HIT Version 1.5 p V11.xlsx differ diff --git a/Documentation/README.md b/Documentation/README.md new file mode 100644 index 0000000..5e08a9e --- /dev/null +++ b/Documentation/README.md @@ -0,0 +1 @@ +Documentation goes here. \ No newline at end of file diff --git a/Documentation/arXiv_sub_20180228.pdf b/Documentation/arXiv_sub_20180228.pdf new file mode 100644 index 0000000..e994005 Binary files /dev/null and b/Documentation/arXiv_sub_20180228.pdf differ diff --git a/FPGA_firmware/.gitignore b/FPGA_firmware/.gitignore new file mode 100644 index 0000000..cccd4c7 --- /dev/null +++ b/FPGA_firmware/.gitignore @@ -0,0 +1,63 @@ +# Ignore everything +* + + +!debouncer.v + +!.gitignore +!README.txt +!clkctrl.qsys +!debouncer.v +!hit20v3.qsf +!m10_rgmii.out.sdc +!m10_rgmii.v +!q_sys.qsys +!udp_generator.v +!udp_generator_hw.tcl + +!sensor_algo_qsys +!sensor_algo_qsys/calibration.v +!sensor_algo_qsys/rms.sv +!sensor_algo_qsys/algo_top_cl_cali_rms.v +!sensor_algo_qsys/bkg_subtraction_pipe.v +!sensor_algo_qsys/calibration.v +!sensor_algo_qsys/cluster_locate.sv +!sensor_algo_qsys/data_caled_ram.v +!sensor_algo_qsys/div.v +!sensor_algo_qsys/frame_counter.v +!sensor_algo_qsys/ram4bkg.v +!sensor_algo_qsys/rms.sv +!sensor_algo_qsys/sensor_algo.v +!sensor_algo_qsys/sensor_interface.v +!sensor_algo_qsys/sensor_recon_hw.tcl +!sensor_algo_qsys/serial_rx.v +!sensor_algo_qsys/serial_tx.v +!sensor_algo_qsys/sqrt.v +!sensor_algo_qsys/sqrt_bb.v +!sensor_algo_qsys/sqrt_inst.v +!sensor_algo_qsys/st2mm.v +!sensor_algo_qsys/st2mm_l2s.v +!sensor_algo_qsys/stl2sts.v +!sensor_algo_qsys/sts2stl.v + +!sensor_algo_qsys/q_sys +!sensor_algo_qsys/q_sys/synthesis +!sensor_algo_qsys/q_sys/synthesis/altera_avalon_st_splitter.sv +!sensor_algo_qsys/q_sys/synthesis/st_splitter16.v + +!sensor_algo_qsys/testbench +!sensor_algo_qsys/testbench/algo_top_cl_cali_rms_tb.v +!sensor_algo_qsys/testbench/algo_top_cl_cali_tb.v +!sensor_algo_qsys/testbench/algo_top_cl_tb.v +!sensor_algo_qsys/testbench/algo_top_tb.v +!sensor_algo_qsys/testbench/bkg_subtraction_pipe_tb.v +!sensor_algo_qsys/testbench/bkg_subtraction_tb.v +!sensor_algo_qsys/testbench/calibration_tb.v +!sensor_algo_qsys/testbench/cluster_locate_tb.v +!sensor_algo_qsys/testbench/sensor_algo_tb.v +!sensor_algo_qsys/testbench/st2mm_tb.v +!sensor_algo_qsys/testbench/stl2sts_tb.v +!sensor_algo_qsys/testbench/sts2stl_tb.v + + + diff --git a/FPGA_firmware/README.txt b/FPGA_firmware/README.txt new file mode 100644 index 0000000..165ca80 --- /dev/null +++ b/FPGA_firmware/README.txt @@ -0,0 +1,5 @@ +This firmware is generted from Simple Socket Server Example. + +M.Dziewiecki created sensor_interface.v in 2019, which controls, collects, and sends ADC data to ethernet. + +L.Qin created algo_top_cl_cali_rms.v in 2024, which reconstructs the position and sigma from the ADC data. diff --git a/FPGA_firmware/clkctrl.qsys b/FPGA_firmware/clkctrl.qsys new file mode 100644 index 0000000..aaf67e1 --- /dev/null +++ b/FPGA_firmware/clkctrl.qsys @@ -0,0 +1,71 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FPGA_firmware/debouncer.v b/FPGA_firmware/debouncer.v new file mode 100644 index 0000000..dca59e6 --- /dev/null +++ b/FPGA_firmware/debouncer.v @@ -0,0 +1,57 @@ +// Signal debouncer + +`timescale 100 ps / 100 ps +module debouncer ( + input wire rst, //reset + input wire clk, //clock + input wire in, //signal input + output wire out //signal output + ); + + parameter LENGTH=8; + + integer i; + + reg [LENGTH-1:0] queue; //State of the state machine + reg reg_out; + wire all_low; + wire all_high; + + //Little helpers + assign all_low = ~(|queue); + assign all_high = &queue; + + + always @(posedge clk or posedge rst) + begin + if (rst) + begin + queue[LENGTH-1:0] <= 0; + reg_out <= 0; + end + else + begin + queue[LENGTH-2:0] <= queue[LENGTH-1:1]; + queue[LENGTH-1] <= in; + + //change the output state only if all the queue has a correct state + case (reg_out) + 0: + begin + if (all_high) + reg_out <= 1; + end + 1: + begin + if (all_low) + reg_out <= 0; + end + endcase + end + end + + //Assign output + assign out = reg_out; + + +endmodule \ No newline at end of file diff --git a/FPGA_firmware/hit20v3.qsf b/FPGA_firmware/hit20v3.qsf new file mode 100644 index 0000000..d4d9150 --- /dev/null +++ b/FPGA_firmware/hit20v3.qsf @@ -0,0 +1,668 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition +# Date created = 13:50:14 June 05, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# hit20v3_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name TOP_LEVEL_ENTITY m10_rgmii +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:52:12 JUNE 15, 2015" +set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_location_assignment PIN_M9 -to clk_50_max10 +set_location_assignment PIN_D9 -to fpga_resetn +set_location_assignment PIN_T20 -to user_led[0] +set_location_assignment PIN_U22 -to user_led[1] +set_location_assignment PIN_U21 -to user_led[2] +set_location_assignment PIN_AA21 -to user_led[3] +set_location_assignment PIN_AA22 -to user_led[4] +set_location_assignment PIN_L22 -to user_pb[0] +set_location_assignment PIN_M21 -to user_pb[1] +set_location_assignment PIN_M22 -to user_pb[2] +set_location_assignment PIN_N21 -to user_pb[3] +set_location_assignment PIN_H21 -to user_dipsw[0] +set_location_assignment PIN_H22 -to user_dipsw[1] +set_location_assignment PIN_J21 -to user_dipsw[2] +set_location_assignment PIN_J22 -to user_dipsw[3] +set_location_assignment PIN_G19 -to user_dipsw[4] +set_location_assignment PIN_B2 -to qspi_clk +set_location_assignment PIN_C6 -to qspi_io[0] +set_location_assignment PIN_C3 -to qspi_io[1] +set_location_assignment PIN_C5 -to qspi_io[2] +set_location_assignment PIN_B1 -to qspi_io[3] +set_location_assignment PIN_C2 -to qspi_csn +set_location_assignment PIN_Y6 -to enet_mdc +set_location_assignment PIN_Y5 -to enet_mdio +set_location_assignment PIN_T5 -to enet_gtx_clk +set_location_assignment PIN_V8 -to enet_resetn +set_location_assignment PIN_P3 -to enet_rx_clk +set_location_assignment PIN_N9 -to enet_rx_d[0] +set_location_assignment PIN_T1 -to enet_rx_d[1] +set_location_assignment PIN_N1 -to enet_rx_d[2] +set_location_assignment PIN_T3 -to enet_rx_d[3] +set_location_assignment PIN_T2 -to enet_rx_dv +set_location_assignment PIN_E10 -to enet_tx_clk +set_location_assignment PIN_R5 -to enet_tx_d[0] +set_location_assignment PIN_P5 -to enet_tx_d[1] +set_location_assignment PIN_W1 -to enet_tx_d[2] +set_location_assignment PIN_W2 -to enet_tx_d[3] +set_location_assignment PIN_R4 -to enet_tx_en +set_location_assignment PIN_R9 -to enet_led_link100 +set_location_assignment PIN_C22 -to mem_a[13] +set_location_assignment PIN_J14 -to mem_a[12] +set_location_assignment PIN_E20 -to mem_a[11] +set_location_assignment PIN_Y20 -to mem_a[10] +set_location_assignment PIN_E22 -to mem_a[9] +set_location_assignment PIN_D22 -to mem_a[8] +set_location_assignment PIN_B20 -to mem_a[7] +set_location_assignment PIN_E21 -to mem_a[6] +set_location_assignment PIN_F19 -to mem_a[5] +set_location_assignment PIN_C20 -to mem_a[4] +set_location_assignment PIN_U20 -to mem_a[3] +set_location_assignment PIN_A21 -to mem_a[2] +set_location_assignment PIN_D19 -to mem_a[1] +set_location_assignment PIN_V20 -to mem_a[0] +set_location_assignment PIN_W22 -to mem_ba[2] +set_location_assignment PIN_N18 -to mem_ba[1] +set_location_assignment PIN_V22 -to mem_ba[0] +set_location_assignment PIN_U19 -to mem_cas_n[0] +set_location_assignment PIN_D18 -to mem_ck[0] +set_location_assignment PIN_E18 -to mem_ck_n[0] +set_location_assignment PIN_W20 -to mem_cke[0] +set_location_assignment PIN_Y22 -to mem_cs_n[0] +set_location_assignment PIN_J15 -to mem_dm[0] +set_location_assignment PIN_K19 -to mem_dq[7] +set_location_assignment PIN_H20 -to mem_dq[6] +set_location_assignment PIN_J20 -to mem_dq[5] +set_location_assignment PIN_H19 -to mem_dq[4] +set_location_assignment PIN_K18 -to mem_dq[3] +set_location_assignment PIN_H18 -to mem_dq[2] +set_location_assignment PIN_K20 -to mem_dq[1] +set_location_assignment PIN_J18 -to mem_dq[0] +set_location_assignment PIN_K14 -to mem_dqs[0] +set_location_assignment PIN_W19 -to mem_odt[0] +set_location_assignment PIN_V18 -to mem_ras_n[0] +set_location_assignment PIN_B22 -to mem_reset_n +set_location_assignment PIN_Y21 -to mem_we_n[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_50_max10 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to fpga_resetn +set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[0] +set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[1] +set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[2] +set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[3] +set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[4] +set_instance_assignment -name IO_STANDARD "1.5 V" -to user_pb[0] +set_instance_assignment -name IO_STANDARD "1.5 V" -to user_pb[1] +set_instance_assignment -name IO_STANDARD "1.5 V" -to user_pb[2] +set_instance_assignment -name IO_STANDARD "1.5 V" -to user_pb[3] +set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[0] +set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[1] +set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[2] +set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[3] +set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_csn +set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_gtx_clk +set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_resetn +set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_clk +set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_d[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_d[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_d[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_d[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_dv +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to enet_tx_clk +set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_d[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_d[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_d[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_d[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_en +set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_led_link100 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_dq[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[1] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_dq[1] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[2] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_dq[2] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[3] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_dq[3] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[4] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_dq[4] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[5] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_dq[5] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[6] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_dq[6] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[7] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_dq[7] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_dqs[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_dqs[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_dqs_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_dqs_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_ck[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_ck[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_ck_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_ck_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[10] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[11] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[12] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[1] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[2] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[3] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[4] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[5] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[6] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[7] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[8] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[9] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_ba[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_ba[1] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_ba[2] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_cs_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_we_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_ras_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_cas_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_cke[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_odt[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD 1.5V -to mem_reset_n -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dm[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_dm[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name CKN_CK_PAIR ON -from mem_ck_n[0] -to mem_ck[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[1] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[2] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[3] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[4] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[5] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[6] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[7] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dm[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name DM_PIN ON -to mem_dm[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[1] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[2] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[3] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[4] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[5] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[6] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[7] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dm[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[10] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[11] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[12] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[1] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[2] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[3] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[4] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[5] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[6] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[7] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[8] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[9] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ba[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ba[1] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ba[2] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_cs_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_we_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ras_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_cas_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_cke[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_odt[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_reset_n -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ck[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ck_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to q_sys_inst|mem_if_ddr3_emif_0 -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[13] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[13] -tag __q_sys_mem_if_ddr3_emif_0_p0 +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name UNIPHY_TEMP_VER_CODE 2133383589 +set_global_assignment -name ECO_REGENERATE_REPORT ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name ENABLE_SIGNALTAP ON +set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp2.stp +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM +set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL +set_global_assignment -name MUX_RESTRUCTURE OFF +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON +set_global_assignment -name SMART_RECOMPILE OFF +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE" +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[4] +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[1] +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[7] +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[2] +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_led[0] +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_led[2] +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_pb[1] +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000 +set_location_assignment PIN_E9 -to pmoda[7] +set_location_assignment PIN_A5 -to pmoda[6] +set_location_assignment PIN_A4 -to pmoda[5] +set_location_assignment PIN_D8 -to pmoda[4] +set_location_assignment PIN_B7 -to pmoda[3] +set_location_assignment PIN_A6 -to pmoda[2] +set_location_assignment PIN_C8 -to pmoda[1] +set_location_assignment PIN_C7 -to pmoda[0] +set_location_assignment PIN_B3 -to pmodb[7] +set_location_assignment PIN_B4 -to pmodb[6] +set_location_assignment PIN_A3 -to pmodb[5] +set_location_assignment PIN_A2 -to pmodb[4] +set_location_assignment PIN_C4 -to pmodb[3] +set_location_assignment PIN_B5 -to pmodb[2] +set_location_assignment PIN_D5 -to pmodb[1] +set_location_assignment PIN_E8 -to pmodb[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmoda[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmoda[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmoda[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmoda[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmodb[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmodb[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmodb[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmodb[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmodb[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmoda[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmoda[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmoda[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmoda[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmoda +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmodb[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmodb[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmodb[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmodb +set_location_assignment PIN_Y19 -to debug_rxd +set_location_assignment PIN_W18 -to debug_txd +set_location_assignment PIN_P12 -to adc_cnv[1] +set_instance_assignment -name IO_STANDARD LVDS -to adc_cnv[1] +set_location_assignment PIN_R12 -to "adc_cnv[1](n)" +set_location_assignment PIN_V16 -to adc_cnv[0] +set_instance_assignment -name IO_STANDARD LVDS -to adc_sck[1] +set_instance_assignment -name IO_STANDARD LVDS -to adc_cnv[0] +set_location_assignment PIN_U15 -to "adc_cnv[0](n)" +set_instance_assignment -name IO_STANDARD LVDS -to adc_cnv +set_location_assignment PIN_V12 -to adc_sck[1] +set_location_assignment PIN_V11 -to "adc_sck[1](n)" +set_location_assignment PIN_Y14 -to adc_sck[0] +set_instance_assignment -name IO_STANDARD LVDS -to adc_sck[0] +set_location_assignment PIN_Y13 -to "adc_sck[0](n)" +set_instance_assignment -name IO_STANDARD LVDS -to adc_sck +set_location_assignment PIN_AB20 -to adc_sdo[4] +set_instance_assignment -name IO_STANDARD LVDS -to adc_sdo[4] +set_location_assignment PIN_AB19 -to "adc_sdo[4](n)" +set_location_assignment PIN_AB11 -to adc_sdo[3] +set_instance_assignment -name IO_STANDARD LVDS -to adc_sdo[3] +set_location_assignment PIN_AB10 -to "adc_sdo[3](n)" +set_location_assignment PIN_AB18 -to adc_sdo[2] +set_instance_assignment -name IO_STANDARD LVDS -to adc_sdo[2] +set_location_assignment PIN_AB17 -to "adc_sdo[2](n)" +set_location_assignment PIN_Y16 -to adc_sdo[1] +set_instance_assignment -name IO_STANDARD LVDS -to adc_sdo[1] +set_location_assignment PIN_AA15 -to "adc_sdo[1](n)" +set_location_assignment PIN_W13 -to adc_sdo[0] +set_instance_assignment -name IO_STANDARD LVDS -to adc_sdo[0] +set_location_assignment PIN_W12 -to "adc_sdo[0](n)" +set_instance_assignment -name IO_STANDARD LVDS -to adc_sdo +set_location_assignment PIN_U7 -to link_dir[3] +set_instance_assignment -name IO_STANDARD LVDS -to link_dir[3] +set_location_assignment PIN_U6 -to "link_dir[3](n)" +set_location_assignment PIN_W8 -to link_dir[2] +set_instance_assignment -name IO_STANDARD LVDS -to link_dir[2] +set_location_assignment PIN_W7 -to "link_dir[2](n)" +set_location_assignment PIN_AA7 -to link_dir[1] +set_instance_assignment -name IO_STANDARD LVDS -to link_dir[1] +set_location_assignment PIN_AA6 -to "link_dir[1](n)" +set_location_assignment PIN_W10 -to link_dir[0] +set_instance_assignment -name IO_STANDARD LVDS -to link_dir[0] +set_location_assignment PIN_W9 -to "link_dir[0](n)" +set_instance_assignment -name IO_STANDARD LVDS -to link_dir +set_location_assignment PIN_AB8 -to link_rx[3] +set_instance_assignment -name IO_STANDARD LVDS -to link_rx[3] +set_location_assignment PIN_AA8 -to "link_rx[3](n)" +set_location_assignment PIN_AB9 -to link_rx[2] +set_instance_assignment -name IO_STANDARD LVDS -to link_rx[2] +set_location_assignment PIN_AA9 -to "link_rx[2](n)" +set_location_assignment PIN_AB7 -to link_rx[1] +set_instance_assignment -name IO_STANDARD LVDS -to link_rx[1] +set_location_assignment PIN_AB6 -to "link_rx[1](n)" +set_location_assignment PIN_Y4 -to link_rx[0] +set_instance_assignment -name IO_STANDARD LVDS -to link_rx[0] +set_location_assignment PIN_Y3 -to "link_rx[0](n)" +set_instance_assignment -name IO_STANDARD LVDS -to link_rx +set_location_assignment PIN_W3 -to link_tx[3] +set_instance_assignment -name IO_STANDARD LVDS -to link_tx[3] +set_location_assignment PIN_W4 -to "link_tx[3](n)" +set_location_assignment PIN_W6 -to link_tx[2] +set_instance_assignment -name IO_STANDARD LVDS -to link_tx[2] +set_location_assignment PIN_W5 -to "link_tx[2](n)" +set_location_assignment PIN_AA10 -to link_tx[1] +set_instance_assignment -name IO_STANDARD LVDS -to link_tx[1] +set_location_assignment PIN_Y10 -to "link_tx[1](n)" +set_location_assignment PIN_P10 -to link_tx[0] +set_instance_assignment -name IO_STANDARD LVDS -to link_tx[0] +set_location_assignment PIN_R10 -to "link_tx[0](n)" +set_instance_assignment -name IO_STANDARD LVDS -to link_tx +set_location_assignment PIN_AA12 -to sensor_clk[1] +set_instance_assignment -name IO_STANDARD LVDS -to sensor_clk[1] +set_location_assignment PIN_AA11 -to "sensor_clk[1](n)" +set_location_assignment PIN_W16 -to sensor_clk[0] +set_instance_assignment -name IO_STANDARD LVDS -to sensor_clk[0] +set_location_assignment PIN_V15 -to "sensor_clk[0](n)" +set_instance_assignment -name IO_STANDARD LVDS -to sensor_clk +set_location_assignment PIN_Y17 -to sensor_reset[1] +set_instance_assignment -name IO_STANDARD LVDS -to sensor_reset[1] +set_location_assignment PIN_AA17 -to "sensor_reset[1](n)" +set_location_assignment PIN_V17 -to sensor_reset[0] +set_instance_assignment -name IO_STANDARD LVDS -to sensor_reset[0] +set_location_assignment PIN_W17 -to "sensor_reset[0](n)" +set_instance_assignment -name IO_STANDARD LVDS -to sensor_reset +set_location_assignment PIN_AB13 -to sensor_trig[4] +set_instance_assignment -name IO_STANDARD LVDS -to sensor_trig[4] +set_location_assignment PIN_AB12 -to "sensor_trig[4](n)" +set_location_assignment PIN_Y11 -to sensor_trig[3] +set_instance_assignment -name IO_STANDARD LVDS -to sensor_trig[3] +set_location_assignment PIN_W11 -to "sensor_trig[3](n)" +set_location_assignment PIN_AA16 -to sensor_trig[2] +set_instance_assignment -name IO_STANDARD LVDS -to sensor_trig[2] +set_location_assignment PIN_AB16 -to "sensor_trig[2](n)" +set_location_assignment PIN_AB15 -to sensor_trig[1] +set_instance_assignment -name IO_STANDARD LVDS -to sensor_trig[1] +set_location_assignment PIN_AA14 -to "sensor_trig[1](n)" +set_location_assignment PIN_AB5 -to sensor_trig[0] +set_instance_assignment -name IO_STANDARD LVDS -to sensor_trig[0] +set_location_assignment PIN_AA5 -to "sensor_trig[0](n)" +set_instance_assignment -name IO_STANDARD LVDS -to sensor_trig +set_location_assignment PIN_AA1 -to sensor_gainn +set_location_assignment PIN_AA2 -to sensor_gainp +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH sensor_algo_tb -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_NAME sensor_algo_tb -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id sensor_algo_tb +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME sensor_algo_tb -section_id sensor_algo_tb +set_global_assignment -name EDA_TEST_BENCH_FILE ../dev_room_qlq/algo_dev/testbeanch/sensor_algo_tb.sv -section_id sensor_algo_tb +set_global_assignment -name ALLOW_REGISTER_RETIMING OFF +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES ON +set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE" +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL" -to ddr3_ram_pll_ref_clk_clk +set_location_assignment PIN_N15 -to "ddr3_ram_pll_ref_clk_clk(n)" +set_location_assignment PIN_N14 -to ddr3_ram_pll_ref_clk_clk +set_global_assignment -name VERILOG_FILE debouncer.v +set_global_assignment -name QIP_FILE software/hit20_v3/mem_init/meminit.qip +set_global_assignment -name SDC_FILE m10_rgmii.out.sdc +set_global_assignment -name QIP_FILE enet_gtx_clk_ddio/enet_gtx_clk_ddio.qip +set_global_assignment -name QIP_FILE clkctrl/synthesis/clkctrl.qip +set_global_assignment -name QIP_FILE q_sys/synthesis/q_sys.qip +set_global_assignment -name VERILOG_FILE m10_rgmii.v +set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to ddr3_ram_pll_ref_clk_clk -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=1" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=2" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_MGR_ENTITY=sld_reserved_hit20v3_auto_signaltap_0_flow_mgr_c90c" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=0" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=0" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INCREMENTAL_ROUTING=1" -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[4] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[7] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[8] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[10] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[12] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[19] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[20] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[23] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_PIPELINE=0" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_PIPELINE=0" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE=0" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[0] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[1] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[5] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[13] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[14] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[18] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[22] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[26] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[28] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[30] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_startofpacket" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_endofpacket" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=2" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_BITS=141" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=21" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=2048" -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[2] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[3] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[15] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[16] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[17] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[24] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[27] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[29] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=2048" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[22]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[23]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[24]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[25]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[26]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[27]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[28]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[29]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[30]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[31]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[22]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[23]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[24]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[25]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[26]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[27]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[28]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[29]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[30]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[31]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_wren_a" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[119] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[120] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[121] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[122] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[123] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[124] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_ready" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[125] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_startofpacket" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[126] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_valid" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[127] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[128] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[129] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[130] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[131] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[132] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[133] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[134] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[135] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[136] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_endofpacket" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[137] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_ready" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[138] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_startofpacket" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[139] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_valid" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[140] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|waitrequest" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=141" -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[6] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[9] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[11] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[21] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[25] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[31] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 +set_global_assignment -name SLD_FILE db/stp2_auto_stripped.stp +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_firmware/m10_rgmii.out.sdc b/FPGA_firmware/m10_rgmii.out.sdc new file mode 100644 index 0000000..2ff30dd --- /dev/null +++ b/FPGA_firmware/m10_rgmii.out.sdc @@ -0,0 +1,88 @@ +#************************************************************** +# Create Clock +# modified by LQ.Qin for DDR3 clock +#************************************************************** + +# RX clock, 125 MHz - M.D. 2019.10.07 +#create_clock -name enet_rx_clk -period 8.000 [get_ports {enet_rx_clk}] + +derive_pll_clocks + +# JTAG Signal Constraints constrain the TCK port, assuming a 10MHz JTAG clock and 3ns delays +create_clock -name {altera_reserved_tck} -period 41.667 [get_ports { altera_reserved_tck }] +set_input_delay -clock altera_reserved_tck -clock_fall -max 5 [get_ports altera_reserved_tdi] +set_input_delay -clock altera_reserved_tck -clock_fall -max 5 [get_ports altera_reserved_tms] +set_output_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tdo] + +create_clock -name {clk_50_max10} -period 20.000 {clk_50_max10} + +#for DDR3 from CLK_DDR3_100_P +create_clock -name {ddr3_ram_pll_ref_clk_clk} -period 10.000 {ddr3_ram_pll_ref_clk_clk} + +################################ SDC for RGMII interface ################################################# +#set enet_pll_125 { q_sys_inst|enet_pll|sd1|pll7|clk[0] }; +#set enet_pll_25 { q_sys_inst|enet_pll|sd1|pll7|clk[1] }; +#set enet_pll_2p5 { q_sys_inst|enet_pll|sd1|pll7|clk[2] }; + +set enet_pll_125 { q_sys_inst|enet_pll|sd1|pll7|clk[3] }; +set enet_pll_25 { q_sys_inst|enet_pll|sd1|pll7|clk[4] }; +set enet_pll_2p5 { q_sys_inst|enet_pll|sd1|pll7|clk[2] }; + +#call sdc files for rgmii interface +source rgmii_sdc/rgmii_clocks.sdc +source rgmii_sdc/rgmii_input.sdc +source rgmii_sdc/rgmii_output.sdc + +# +# Create false paths between clock domains that are not fully constrained by the IP that makes these paths. +# Ideally we should not have to do this, however, these paths must be cut to meet timing and in most cases +# the IP should be accounting for synchronization between these paths. +# The risk of a global cut like these is that if the IP is not synchronizing properly between the two domains +# then you have significant problems with the design. Ideally the IP should synchronize it's clock crossing +# paths and create constraints to cut those paths so we don't have to perform a global cut like this. +# + +set_clock_groups \ + -exclusive \ + -group [get_clocks {tx_clk_125 tx_clk_25 tx_clk_2p5}] \ + -group [get_clocks enet_rx_clk] \ + -group [get_clocks clk_50_max10] + +## +## These are the constraints out of the TSE MAC SDC file that are relevant to us. +## The TSE MAC SDC file should be commented out by this script. +## +#set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *] +#set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *] +#set_multicycle_path -setup 5 -from [ get_registers *] -to [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] +#set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *] +#set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *] +#set_multicycle_path -hold 5 -from [ get_registers *] -to [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] +#set_max_delay 7 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|dout_reg_sft*] -to [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*] +#set_max_delay 7 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|eop_sft*] -to [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*] +#set_max_delay 7 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|sop_reg*] -to [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*] + +# +#some clock uncertainty is required +# +derive_clock_uncertainty + +# QSPI interface +set_output_delay -clock { clk_50_max10 } -rise -min 11 [get_ports {qspi_io[*]}] +set_output_delay -clock { clk_50_max10 } -rise -min 11 [get_ports {qspi_clk}] +set_output_delay -clock { clk_50_max10 } -rise -min 11 [get_ports {qspi_csn}] +set_input_delay -clock { clk_50_max10 } -rise -min 10 [get_ports {qspi_io[*]}] + +# Ethernet MDIO interface +set_output_delay -clock [ get_clocks clk_50_max10 ] 2 [ get_ports {enet_mdc} ] +set_input_delay -clock [ get_clocks clk_50_max10 ] 2 [ get_ports {enet_mdio} ] +set_output_delay -clock [ get_clocks clk_50_max10 ] 2 [ get_ports {enet_mdio} ] + +set_false_path -from [get_ports {fpga_resetn}] +set_false_path -from [get_ports {user_dipsw[*]}] +set_false_path -from [get_ports {user_pb[*]}] +set_false_path -to [get_ports {user_led[*]}] +set_false_path -to [get_ports {enet_resetn}] + +#set_false_path -from * -to {sld_signaltap:auto_signaltap_0|*} +#set_false_path -from {sld_signaltap:auto_signaltap_0|*} -to * diff --git a/FPGA_firmware/m10_rgmii.v b/FPGA_firmware/m10_rgmii.v new file mode 100644 index 0000000..c79bec4 --- /dev/null +++ b/FPGA_firmware/m10_rgmii.v @@ -0,0 +1,357 @@ +/****************************************************************************** +* Copyright * +* Scintillating Fibre Beam Profile Monitor Software by Michal Dziewiecki, * +* Blake Leverington and Liqing Qin is licensed under CC BY 4.0 * +* https://creativecommons.org/licenses/by/4.0/ * +* funded by the Deutsche Forschungsgemeinschaft * +* (DFG, German Research Foundation) Projektnummer 419255448 * +* Project Leader: B.Leverington * +******************************************************************************* +* Create Date - 2019 * +* Author: M.Dziewiecki * +* Module - m10_rgmii.v * +* Edited by L.Qin on Oct 15. 2024 for reconstruction * +******************************************************************************/ + +module m10_rgmii ( + //Clock and Reset + input wire clk_50_max10, + input wire fpga_resetn, + + + //LED PB DIPSW + output wire [4:0] user_led, + input wire [3:0] user_pb, + input wire [4:0] user_dipsw, + + //Dual Ethernet + output wire enet_mdc, + inout wire enet_mdio, + output wire enet_resetn, + input wire enet_rx_clk, + input wire enet_tx_clk, + output wire enet_gtx_clk, + input wire [3:0] enet_rx_d, + output wire [3:0] enet_tx_d, + output wire enet_tx_en, + input wire enet_rx_dv, + input wire enet_led_link100, + + input wire ddr3_ram_pll_ref_clk_clk, // ddr3_ram_pll_ref_clk.clk + + output wire [13:0] mem_a, + output wire [2:0] mem_ba, + inout wire [0:0] mem_ck, + inout wire [0:0] mem_ck_n, + output wire [0:0] mem_cke, + output wire [0:0] mem_cs_n, + output wire [0:0] mem_dm, + output wire [0:0] mem_ras_n, + output wire [0:0] mem_cas_n, + output wire [0:0] mem_we_n, + output wire mem_reset_n, + inout wire [7:0] mem_dq, + inout wire [0:0] mem_dqs, + inout wire [0:0] mem_dqs_n, + output wire [0:0] mem_odt, + + //QSPI + output qspi_clk, + inout [3:0] qspi_io, + output qspi_csn, + + //Sensors + output wire [1:0] sensor_reset, + output wire [1:0] sensor_clk, + input wire [4:0] sensor_trig, + output wire [1:0] adc_cnv, + output wire [1:0] adc_sck, + input wire [4:0] adc_sdo, + output wire sensor_gainp, + output wire sensor_gainn, + + //Synchro + input wire [3:0] link_rx, + output wire [3:0] link_tx, + output wire [3:0] link_dir, + + + //PMOD + input wire [7:0] pmoda, //used for 8-fold SMA input;) + output wire [7:0] pmodb, + + //USB UART + output wire debug_txd, + input wire debug_rxd + + ); + +//*********************************** Signals ************************************* + +//Heart-beat counter +reg [25:0] heart_beat_cnt; + +//DDR3 interface assignments +wire local_init_done; +wire local_cal_success; +wire local_cal_fail; + +//Ethernet interface assignments +wire phy_resetn; +wire system_resetn; + +wire mdio_oen_from_the_tse_mac; +wire mdio_out_from_the_tse_mac; +wire eth_mode_from_the_tse_mac; +wire ena_10_from_the_tse_mac; +wire enet_tx_125; +wire enet_tx_25; +wire enet_tx_2p5; +wire locked_from_the_enet_pll; +wire tx_clk_to_the_tse_mac; +wire tx_clk_to_the_tse_mac_g; + +wire enet_tx_125_shift; +wire enet_tx_25_shift; +wire enet_tx_2p5_shift; +wire enet_tx_250_shift; // signaltap sample clock +wire locked_from_the_shift_pll; +wire tx_clk_to_the_tse_mac_shift; +wire tx_clk_to_the_tse_mac_shift_g; + +//User interface ;) +wire [8:0] user_input; +wire [7:0] int_output; + +//Sensor interface +wire int_sensor_in_trg; +wire int_sensor_out_adc_clk; +wire int_sensor_out_adc_cnv; +wire [4:0] int_sensor_in_adc_data; +wire int_sensor_out_sensor_rst; +wire int_sensor_out_sensor_clk; +wire int_sensor_out_sensor_gain; +wire [7:0] int_sensor_status; + + +//Trigger stuff +wire int_frame_timer; +reg sym_frame_timer; + +//*********************************** Sensor connections ************************************* + +assign sensor_reset[0] = int_sensor_out_sensor_rst; +assign sensor_reset[1] = int_sensor_out_sensor_rst; +assign sensor_clk[0] = ~int_sensor_out_sensor_clk; +assign sensor_clk[1] = ~int_sensor_out_sensor_clk; +assign sensor_gainp = int_sensor_out_sensor_gain; +assign sensor_gainn = ~int_sensor_out_sensor_gain; +assign adc_cnv[0] = int_sensor_out_adc_cnv; +assign adc_cnv[1] = int_sensor_out_adc_cnv; +assign adc_sck[0] = ~int_sensor_out_adc_clk; +assign adc_sck[1] = ~int_sensor_out_adc_clk; +assign int_sensor_in_adc_data = adc_sdo; //all of them are not-inverted :) + + +//*********************************** Frame trigger & synchro routing (master/slave) ************************************* + +//Synchro pulse is LINK3 (inverted) +//Global counter transmission is LINK2 (inverted) + +wire trig_mode; +assign trig_mode = int_output[7]; +wire int_synchro_rx; +wire int_synchro_tx; +wire int_trig_debouncer_in; +wire int_ser_debouncer_in; + + //Pulse flip-flop +always @(posedge int_frame_timer or negedge fpga_resetn) +begin + if (!fpga_resetn) + sym_frame_timer <= 0; + else if (trig_mode == 0) + sym_frame_timer <= 0; + else + sym_frame_timer <= ~sym_frame_timer; +end + //Trigger Assignments +assign link_dir[3] = trig_mode; //set link direction according to M/S setting (LED PIO 7) +assign link_tx[3] = ~sym_frame_timer; //connect internal frame trigger to TX +assign int_trig_debouncer_in = trig_mode ? sym_frame_timer : link_rx[3]; //connect either internal or external frame trigger + + //Debouncer for trigger signals - limit trigger bandwidth to 2.5 MHz +debouncer #( + .LENGTH (10) +) trig_debouncer ( + .rst (!system_resetn), + .clk (clk_50_max10), + .in (int_trig_debouncer_in), + .out (int_sensor_in_trg) +); + + //Serial assignments +assign link_dir[2] = trig_mode; +assign int_ser_debouncer_in = trig_mode ? int_synchro_tx : link_rx[2]; +assign link_tx[2] = ~int_synchro_tx; + + //Debouncer for serial RX - limit bandwidth to 2.5 MHz +debouncer #( + .LENGTH (10) +) ser_debouncer ( + .rst (!system_resetn), + .clk (clk_50_max10), + .in (int_ser_debouncer_in), + .out (int_synchro_rx) +); + + +//*********************************** Various logic ************************************* + +assign system_resetn = fpga_resetn & local_init_done; + + //PMOD debug lines +assign pmodb[0] = int_trig_debouncer_in; +assign pmodb[1] = int_sensor_in_trg; +assign pmodb[7:2] = int_sensor_status[5:0]; + + //Buttons/switches +assign user_input[3:0] = user_pb[3:0]; +assign user_input[8:4] = user_dipsw[4:0]; + +//LED forwarding +assign user_led[3:0] = ~int_output[3:0]; + //disable user_led[4] blink with int_output[5]; force user_led[4] with int_output[4] +assign user_led[4] = ~int_output[4] & (heart_beat_cnt[25] | int_output[5]); + //int_output[6] is used for PHY hard reset + //int_output[7] is used for master/slave frame trigger routing + + +//Heart beat by 50MHz clock +always @(posedge clk_50_max10 or negedge fpga_resetn) + if (!fpga_resetn) + heart_beat_cnt <= 26'h0; //0x3FFFFFF + else + heart_beat_cnt <= heart_beat_cnt + 1'b1; + + + +//*********************************** Ethernet ************************************* + + //PHY power-on reset control +parameter MSB = 20; // PHY interface: need minimum 10ms delay for POR +reg [MSB:0] epcount; + +always @(posedge clk_50_max10 or negedge fpga_resetn) + if (!fpga_resetn) + epcount <= MSB + 1'b0; + else if (epcount[MSB] == 1'b0) + epcount <= epcount + 1; + else + epcount <= epcount; + +assign phy_resetn = user_pb[0] & !(int_output[6] & epcount[MSB]) & !epcount[MSB-1]; //PHY hard reset by counter, user button or software +assign enet_resetn = phy_resetn; + +//MDIO output control +assign enet_mdio = ( !mdio_oen_from_the_tse_mac ) ? ( mdio_out_from_the_tse_mac ) : ( 1'bz ); + +assign enet_tx_2p5_shift = !enet_tx_2p5; + +//RGMII clock solution +assign tx_clk_to_the_tse_mac = ( eth_mode_from_the_tse_mac ) ? ( enet_tx_125 ) : // GbE Mode = 125MHz clock + ( ena_10_from_the_tse_mac ) ? ( enet_tx_2p5 ) : // 10Mb Mode = 2.5MHz clock + ( enet_tx_25 ); // 100Mb Mode = 25MHz clock + +assign tx_clk_to_the_tse_mac_shift = ( eth_mode_from_the_tse_mac ) ? ( enet_tx_125_shift ) : // GbE Mode = 125MHz clock + ( ena_10_from_the_tse_mac ) ? ( enet_tx_2p5_shift ) : // 10Mb Mode = 2.5MHz clock + ( enet_tx_25_shift); // 100Mb Mode = 25MHz clock + +clkctrl clkctrl_inst0 ( + .inclk (tx_clk_to_the_tse_mac ), + .outclk (tx_clk_to_the_tse_mac_g) + ); + +clkctrl clkctrl_inst1 ( + .inclk (tx_clk_to_the_tse_mac_shift ), + .outclk (tx_clk_to_the_tse_mac_shift_g) + ); + +enet_gtx_clk_ddio enet_gtx_clk_ddio_inst ( + .outclock (tx_clk_to_the_tse_mac_shift_g), // tx_clk_to_the_tse_mac_g ), + .din (2'b10 ), + .pad_out (enet_gtx_clk ), + .aclr (!phy_resetn ) + ); + + +//*********************************** Main QSYS ************************************* + +q_sys q_sys_inst ( + .sys_clk_clk (clk_50_max10 ), // sys_clk.clk + .reset_reset_n (system_resetn ), // reset.reset_n + .mem_resetn_in_reset_reset_n (fpga_resetn ), // mem_resetn_in_reset.reset_n + .altpll_shift_c0_clk (enet_tx_250_shift ), // altpll_shift_c0.clk + .altpll_shift_locked_conduit_export (locked_from_the_shift_pll ), // altpll_shift_locked_conduit.export + .clock_bridge_0_in_clk_clk (enet_tx_25 ), // clock_bridge_0_in_clk.clk + .enet_pll_c0_clk (enet_tx_125 ), // enet_pll_c0.clk + .enet_pll_c1_clk (enet_tx_25 ), // enet_pll_c1.clk + .enet_pll_c2_clk (enet_tx_2p5 ), // enet_pll_c2.clk + .enet_pll_c3_clk (enet_tx_125_shift ), // enet_pll_c3.clk + .enet_pll_c4_clk (enet_tx_25_shift ), // enet_pll_c4.clk + .enet_pll_locked_conduit_export (locked_from_the_enet_pll ), // enet_pll_locked_conduit.export + .eth_tse_mac_mdio_connection_mdc (enet_mdc ), // eth_tse_mac_mdio_connection.mdc + .eth_tse_mac_mdio_connection_mdio_in (enet_mdio ), // .mdio_in + .eth_tse_mac_mdio_connection_mdio_out (mdio_out_from_the_tse_mac ), // .mdio_out + .eth_tse_mac_mdio_connection_mdio_oen (mdio_oen_from_the_tse_mac ), // .mdio_oen + .eth_tse_mac_rgmii_connection_rgmii_in (enet_rx_d ), // eth_tse_mac_rgmii_connection.rgmii_in + .eth_tse_mac_rgmii_connection_rgmii_out (enet_tx_d ), // .rgmii_out + .eth_tse_mac_rgmii_connection_rx_control (enet_rx_dv ), // .rx_control + .eth_tse_mac_rgmii_connection_tx_control (enet_tx_en ), // .tx_control + .eth_tse_mac_status_connection_set_10 ( ), // eth_tse_mac_status_connection.set_10 + .eth_tse_mac_status_connection_set_1000 ( ), // .set_1000 + .eth_tse_mac_status_connection_eth_mode (eth_mode_from_the_tse_mac ), // .eth_mode + .eth_tse_mac_status_connection_ena_10 (ena_10_from_the_tse_mac ), // .ena_10 + .eth_tse_pcs_mac_rx_clock_connection_clk (enet_rx_clk ), // eth_tse_pcs_mac_rx_clock_connection.clk + .eth_tse_pcs_mac_tx_clock_connection_clk (tx_clk_to_the_tse_mac_g ), // eth_tse_pcs_mac_tx_clock_connection.clk + .ext_flash_flash_dataout_conduit_dataout (qspi_io ), // ext_flash_flash_dataout.conduit_dataout + .ext_flash_flash_dclk_out_conduit_dclk_out (qspi_clk ), // ext_flash_flash_dclk_out.conduit_dclk_out + .ext_flash_flash_ncs_conduit_ncs (qspi_csn ), // ext_flash_flash_ncs.conduit_ncs + .ddr3_ram_pll_ref_clk_clk (ddr3_ram_pll_ref_clk_clk ), + .memory_mem_a (mem_a ), // memory.mem_a + .memory_mem_ba (mem_ba ), // .mem_ba + .memory_mem_ck (mem_ck ), // .mem_ck + .memory_mem_ck_n (mem_ck_n ), // .mem_ck_n + .memory_mem_cke (mem_cke ), // .mem_cke + .memory_mem_cs_n (mem_cs_n ), // .mem_cs_n + .memory_mem_dm (mem_dm ), // .mem_dm + .memory_mem_ras_n (mem_ras_n ), // .mem_ras_n + .memory_mem_cas_n (mem_cas_n ), // .mem_cas_n + .memory_mem_we_n (mem_we_n ), // .mem_we_n + .memory_mem_reset_n (mem_reset_n ), // .mem_reset_n + .memory_mem_dq (mem_dq ), // .mem_dq + .memory_mem_dqs (mem_dqs ), // .mem_dqs + .memory_mem_dqs_n (mem_dqs_n ), // .mem_dqs_n + .memory_mem_odt (mem_odt ), // .mem_odt + .led_pio_external_connection_export (int_output[7:0] ), // led_pio_external_connection.export + .mem_if_ddr3_emif_0_status_local_init_done (local_init_done ), // mem_if_ddr3_emif_0_status.local_init_done + .mem_if_ddr3_emif_0_status_local_cal_success (local_cal_success ), // .local_cal_success + .mem_if_ddr3_emif_0_status_local_cal_fail (local_cal_fail ), // .local_cal_fail + .button_pio_external_connection_export (user_input ), // + .debug_uart_external_connection_rxd (debug_rxd ), // + .debug_uart_external_connection_txd (debug_txd ), // + .sensor_in_trg (int_sensor_in_trg ), + .sensor_out_adc_clk (int_sensor_out_adc_clk ), + .sensor_out_adc_cnv (int_sensor_out_adc_cnv ), + .sensor_in_adc_data (int_sensor_in_adc_data ), + .sensor_out_sensor_rst (int_sensor_out_sensor_rst ), + .sensor_out_sensor_clk (int_sensor_out_sensor_clk ), + .sensor_out_sensor_gain (int_sensor_out_sensor_gain), + .frame_timer_export (int_frame_timer), + .sensor_synchro_serial_rx (int_synchro_rx),// sensor_synchro.serial_rx + .sensor_synchro_serial_tx (int_synchro_tx),// .serial_tx + .sensor_synchro_ext_input (pmoda), + .sensor_status_status_out (int_sensor_status) + ); + +endmodule diff --git a/FPGA_firmware/q_sys.qsys b/FPGA_firmware/q_sys.qsys new file mode 100644 index 0000000..a99ccc7 --- /dev/null +++ b/FPGA_firmware/q_sys.qsys @@ -0,0 +1,2812 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 15000 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 2 CT#PORT_LOCKED PORT_USED + altpll_avalon_elaboration + altpll_avalon_post_edit + IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} + + IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1 + MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1 + PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 0 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 0 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ2 100.00000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 6 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT2 0.00000000 PT#PHASE_SHIFT1 135.00000000 PT#DIV_FACTOR2 20 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 2 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 250.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 5 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1423823783608952.mif PT#ACTIVECLK_CHECK 0 + UP#locked used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $${FILENAME}_calibration_ram + + + + + + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + cpu.jtag_debug_module + + + + + + + + + + + + + ]]> + + + + + + + + + + + + + + + + + + + + + + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + + + + + + + + + + + + + + + + + ]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 0x000000000000000000 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $${FILENAME}_descriptor_memory + + + + + + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + + + + + + /data/acastill/simple_socket_10M50/software/niosII_simple_socket_server/mem_init/q_sys_descriptor_memory.hex + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_USED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 2 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT -3000 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 2 CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 1 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NO_COMPENSATION CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT -10000 CT#INCLK0_INPUT_FREQUENCY 20000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 2 CT#CLK1_DIVIDE_BY 2 CT#CLK3_MULTIPLY_BY 5 CT#PORT_LOCKED PORT_USED + altpll_avalon_elaboration + altpll_avalon_post_edit + IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} + + IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#CLK4_DIVIDE_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1 + MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1 + PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 0 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 0 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 0 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 100.00000000 PT#OUTPUT_FREQ3 100.00000000 PT#OUTPUT_FREQ2 2.50000000 PT#OUTPUT_FREQ1 25.00000000 PT#OUTPUT_FREQ0 125.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 -90.00000000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 -135.00000000 PT#DIV_FACTOR4 2 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 2 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR1 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 1 PT#USE_CLKENA4 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 25.000000 PT#EFF_OUTPUT_FREQ_VALUE3 125.000000 PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 125.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK4 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 5 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1418882816093282.mif PT#ACTIVECLK_CHECK 0 + UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $${FILENAME}_ext_flash + + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 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-0,0 +1,367 @@ +/****************************************************************************** +* Copyright * +* Scintillating Fibre Beam Profile Monitor Software by Michal Dziewiecki, * +* Blake Leverington and Liqing Qin is licensed under CC BY 4.0 * +* https://creativecommons.org/licenses/by/4.0/ * +* funded by the Deutsche Forschungsgemeinschaft * +* (DFG, German Research Foundation) Projektnummer 419255448 * +* Project Leader: B.Leverington * +******************************************************************************* +* Create Date - Oct 15th. 2024 * +* Author: L.Qin * +* Module - algo_top_cl_cali_rms.v * +******************************************************************************/ +/*Created by Lq.Qin on Oct 15th. 2024*/ + +//module algo_top_cl_cali_rms +//combine bkg_subtraction, cluster_locate, and calibration, and rms + +//tested with algo_top_cl_cali_rms_tb.v +module algo_top_cl_cali_rms( + + //clock and reset + input wire clk, + input wire rst, // connect to rst_run + + //avalon ST(Streaming) sink: 0 readlatency and 0 readallowence // 163 word = 3 header + 160 data + input wire [31:0] data_in_data, // st.data + output wire data_in_ready, // .ready + input wire data_in_valid, // .valid + input wire [1:0] data_in_empty, // .empty + input wire data_in_endofpacket, // .endofpacket + input wire data_in_startofpacket, // .startofpacket + + + //avalon ST(Streaming) source: 0 readlatency and 0 readallowence // 3 + 160 + 4 = 167 words * 32bit + output wire [31:0] to_udp_data, // st.data + input wire to_udp_ready, // .ready + output wire to_udp_valid, // .valid + output wire [1:0] to_udp_empty, // .empty + output wire to_udp_endofpacket, // .endofpacket + output wire to_udp_startofpacket , // .startofpacket + + + //Avalon MM slave + input wire [1:0] csr_address, // avalon_slave.address + input wire csr_read, // .read + output wire [31:0] csr_readdata, // .readdata + input wire csr_write, // .write + input wire [31:0] csr_writedata, // .writedata + input wire [3:0] csr_byteenable, // .byteenable + + //for cluster => will be in register map + input wire [7:0] CL_THRESHOLD, + input wire [7:0] CL_SIZE, + input wire [7:0] IN_ALGO_THRESHOLD, + + //the interface with cali_ram (storing cali factor) Avalon-MM: read califac from this ram; output is not registered + output wire [8:0] address, + output wire clken, + input wire [15:0] cali_fac, + input wire waitrequest + +); + //avalon source for header + wire [31:0] header_data; + wire header_ready; + wire [1:0] header_empty; + wire header_endofpacket; + wire header_startofpacket; + wire header_valid; + + //avalon source for channel data + wire [31:0] channel_data; + wire channel_ready; + wire [1:0] channel_empty; + wire channel_endofpacket; + wire channel_startofpacket; + wire channel_valid; + + //avalon source for result + wire [31:0] recon_data; + wire recon_ready; + wire [1:0] recon_empty; + wire recon_endofpacket; + wire recon_startofpacket; + wire recon_valid; + + /******************** merge three data source together *****************************************/ + reg [1:0] avalon_sender_state; + localparam STATE_IDLE = 2'd0; + localparam STATE_HEADER = 2'd1; + localparam STATE_CHANNEL = 2'd3; + localparam STATE_RECON = 2'd2; + + + always @ (posedge clk or posedge rst) + begin + if (rst) + begin + avalon_sender_state <= STATE_IDLE; + end + else case(avalon_sender_state) + STATE_IDLE: + begin + if (header_startofpacket) + avalon_sender_state <= STATE_HEADER; + end + STATE_HEADER: + begin + if (channel_startofpacket) + avalon_sender_state <= STATE_CHANNEL; + end + STATE_CHANNEL: + begin + if (recon_startofpacket) + avalon_sender_state <= STATE_RECON; + end + STATE_RECON: + begin + if (recon_endofpacket && to_udp_ready) + avalon_sender_state <= STATE_IDLE; + end + default: + avalon_sender_state <= STATE_IDLE; + endcase + end + + + assign to_udp_data = (avalon_sender_state == STATE_HEADER)? header_data: (avalon_sender_state == STATE_CHANNEL)? channel_data: (avalon_sender_state == STATE_RECON)? recon_data: 32'd0; + assign header_ready = (avalon_sender_state == STATE_HEADER)? to_udp_ready: 1'b0; + assign channel_ready = (avalon_sender_state == STATE_CHANNEL)? to_udp_ready: 1'b0; + assign recon_ready = (avalon_sender_state == STATE_RECON)? to_udp_ready: 1'b0; + + assign to_udp_empty = 2'b0; + assign to_udp_startofpacket = (avalon_sender_state == STATE_HEADER)? header_startofpacket: 1'b0; + assign to_udp_endofpacket = (avalon_sender_state == STATE_RECON)? recon_endofpacket: 1'b0; + assign to_udp_valid = (avalon_sender_state == STATE_HEADER)? header_valid: (avalon_sender_state == STATE_CHANNEL)? channel_valid: (avalon_sender_state == STATE_RECON)? recon_valid: 1'b0; + + + + + + + + + + + + wire [31:0] wire_data0; + wire wire_ready0; + wire wire_valid0; + wire [1:0] wire_empty0; + wire wire_endofpacket0; + wire wire_startofpacket0; + wire bkg_sub_on; + + bkg_subtraction_pipe #(.BKG_FRAME(8192)) bkg_subtraction0( //4 for simulation, 8192 for real firmware setup + + .clk (clk), + .rst (rst), + + .data_in_data (data_in_data), + .data_in_ready (data_in_ready), + .data_in_valid (data_in_valid), + .data_in_empty (data_in_empty), + .data_in_startofpacket (data_in_startofpacket), + .data_in_endofpacket (data_in_endofpacket), + + .data_out_data (wire_data0), + .data_out_empty (wire_empty0), + .data_out_endofpacket (wire_endofpacket0), + .data_out_startofpacket (wire_startofpacket0), + .data_out_ready (wire_ready0), + .data_out_valid (wire_valid0), + .bkg_sub_on (bkg_sub_on), + + + //3 header + .to_udp_data (header_data), + .to_udp_ready(header_ready), + .to_udp_valid (header_valid), + .to_udp_empty (header_empty), + .to_udp_endofpacket (header_endofpacket), + .to_udp_startofpacket (header_startofpacket) + + + + ); + + + wire [15:0] wire_data1; + wire wire_ready1; + wire wire_valid1; + wire wire_empty1; + wire wire_endofpacket1; + wire wire_startofpacket1; + + stl2sts stl2sts0( + + .clk (clk), + .rst (rst), + + .data_in_data (wire_data0), + .data_in_ready (wire_ready0), + .data_in_valid (wire_valid0), + .data_in_empty (wire_empty0), + .data_in_startofpacket (wire_startofpacket0), + .data_in_endofpacket (wire_endofpacket0), + + .data_out_data (wire_data1), + .data_out_empty (wire_empty1), + .data_out_endofpacket (wire_endofpacket1), + .data_out_startofpacket (wire_startofpacket1), + .data_out_ready (wire_ready1), + .data_out_valid (wire_valid1) + + ); + + //from st_splitter0 to cluster_locate + wire [15:0] wire_data2; + wire wire_ready2; + wire wire_valid2; + wire wire_empty2; + wire wire_endofpacket2; + wire wire_startofpacket2; + + //from st_splitter0 to calibration + wire [15:0] wire_data3; + wire wire_ready3; + wire wire_valid3; + wire wire_empty3; + wire wire_endofpacket3; + wire wire_startofpacket3; + + st_splitter16 st_splitter0 ( + .st_splitter16_clk_clk (clk), // st_splitter16_clk.clk + .st_splitter16_reset_reset (rst), // st_splitter16_reset.reset + + + .st_splitter16_in_ready (wire_ready1), // st_splitter16_in.ready + .st_splitter16_in_valid (wire_valid1), // .valid + .st_splitter16_in_startofpacket (wire_startofpacket1), // .startofpacket + .st_splitter16_in_endofpacket (wire_endofpacket1), // .endofpacket + .st_splitter16_in_empty (wire_empty1), // .empty + .st_splitter16_in_data (wire_data1), // .data + + + .st_splitter16_out0_ready (wire_ready2), // st_splitter16_out0.ready + .st_splitter16_out0_valid (wire_valid2), // .valid + .st_splitter16_out0_startofpacket (wire_startofpacket2), // .startofpacket + .st_splitter16_out0_endofpacket (wire_endofpacket2), // .endofpacket + .st_splitter16_out0_empty (wire_empty2), // .empty + .st_splitter16_out0_data (wire_data2), // .data + + + .st_splitter16_out1_ready (wire_ready3), // st_splitter16_out1.ready + .st_splitter16_out1_valid (wire_valid3), // .valid + .st_splitter16_out1_startofpacket (wire_startofpacket3), // .startofpacket + .st_splitter16_out1_endofpacket (wire_endofpacket3), // .endofpacket + .st_splitter16_out1_empty (wire_empty3), // .empty + .st_splitter16_out1_data (wire_data3) // .data + ); + + + wire[8:0] sig_ch_left; + wire[8:0] sig_ch_right; + wire has_cluster; + wire no_cluster; + + wire cl_last_channel; + cluster_locate cluster_locate0( + + .clk (clk), + .rst (rst), + + .data_in_data (wire_data2), + .data_in_ready (wire_ready2), + .data_in_valid (wire_valid2), + .data_in_empty (wire_empty2), + .data_in_startofpacket (wire_startofpacket2), + .data_in_endofpacket (wire_endofpacket2), + + .THRESHOLD ({8'b0,CL_THRESHOLD}), + .SIZE ({1'b0,CL_SIZE}), + + .sig_ch_left (sig_ch_left), + .sig_ch_right (sig_ch_right), + .has_cluster (has_cluster), + .no_cluster (no_cluster), + + .data_in_last (cl_last_channel) + + ); + + + wire[8:0] data_caled_address; + wire [15:0] data_caled; + wire data_caled_rd_enable; + + //when bkg_sub_on is off, it equals to 8192.... the scaled 1 for calibration factor + wire [15:0] cali_fac_masked = bkg_sub_on? cali_fac:16'd8192; + calibration calibration0( + + .clk(clk), + .rst(rst), + + .data_in_data (wire_data3), + .data_in_ready (wire_ready3), + .data_in_valid (wire_valid3), + .data_in_empty (wire_empty3), + .data_in_startofpacket (wire_startofpacket3), + .data_in_endofpacket (wire_endofpacket3), + + .address (address), + .clken (clken), + .cali_fac (cali_fac_masked), + .waitrequest(waitrequest), + + .data_caled_address(data_caled_address), + .data_caled(data_caled), + .data_caled_rd_enable(data_caled_rd_enable), + + .to_udp_data (channel_data), + .to_udp_ready(channel_ready), + .to_udp_valid (channel_valid), + .to_udp_empty (channel_empty), + .to_udp_endofpacket (channel_endofpacket), + .to_udp_startofpacket (channel_startofpacket) + + ); + + + rms rms0( + + + .clk(clk), + .rst(rst), + + .bkg_sub_on (bkg_sub_on), + .sig_ram_last (cl_last_channel), + + .sig_rdaddress(data_caled_address), + .sig(data_caled), + .sig_rd_eable(data_caled_rd_enable), + + .sig_ch_left (sig_ch_left), + .sig_ch_right (sig_ch_right), + .has_cluster (has_cluster), + .no_cluster (no_cluster), + + .to_udp_data (recon_data), + .to_udp_ready(recon_ready), + .to_udp_valid (recon_valid), + .to_udp_empty (recon_empty), + .to_udp_endofpacket (recon_endofpacket), + .to_udp_startofpacket (recon_startofpacket) + + + ); + + +endmodule + + + + + \ No newline at end of file diff --git a/FPGA_firmware/sensor_algo_qsys/bkg_subtraction_pipe.v b/FPGA_firmware/sensor_algo_qsys/bkg_subtraction_pipe.v new file mode 100644 index 0000000..11d9ad8 --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/bkg_subtraction_pipe.v @@ -0,0 +1,327 @@ +/****************************************************************************** +* Copyright * +* Scintillating Fibre Beam Profile Monitor Software by Michal Dziewiecki, * +* Blake Leverington and Liqing Qin is licensed under CC BY 4.0 * +* https://creativecommons.org/licenses/by/4.0/ * +* funded by the Deutsche Forschungsgemeinschaft * +* (DFG, German Research Foundation) Projektnummer 419255448 * +* Project Leader: B.Leverington * +******************************************************************************* +* Create Date - Oct 15th. 2024 * +* Author: L.Qin * +* Module - bkg_subtraction_pipe.v * +******************************************************************************/ +/*Created by Lq.Qin on Oct 15th. 2024*/ + +//background subtraction module + +//tested with algo_top_cl_cali_tb.v with bkg_subtraction_pipe +//tested with bkg_subtraction_pipe_tb + +//okay... it is not really pipe.... has to read a ram after use the previous output of this ram + +module bkg_subtraction_pipe #(parameter BKG_FRAME = 4)( + + //clock and reset + input wire clk, + input wire rst, // connect to rst_run + + //avalon ST(Streaming) sink: 0 readlatency and 0 readallowence // 163 word = 3 header + 160 data + input wire [31:0] data_in_data, // st.data + output wire data_in_ready, // .ready + input wire data_in_valid, // .valid + input wire [1:0] data_in_empty, // .empty + input wire data_in_endofpacket, // .endofpacket + input wire data_in_startofpacket, // .startofpacket + + //avalon ST(Streaming) source: 0 readlatency and 0 readallowence //160 word only with data + output wire [31:0] data_out_data, // st.data + input wire data_out_ready, // .ready + output wire data_out_valid, // .valid + output wire [1:0] data_out_empty, // .empty + output wire data_out_endofpacket, // .endofpacket + output wire data_out_startofpacket, // .startofpacket + + output wire bkg_sub_on, + + //avalon ST(Streaming) source: 0 readlatency and 0 readallowence //3 headers + output wire [31:0] to_udp_data, // st.data + input wire to_udp_ready, // .ready + output wire to_udp_valid, // .valid + output wire [1:0] to_udp_empty, // .empty + output wire to_udp_endofpacket, // .endofpacket + output wire to_udp_startofpacket // .startofpacket + + //output rst_frame // I have to think about this rst_frame when is a good timing! or do I need it? 26.June. 2024 +); + localparam SHIFT_BIT = $clog2(BKG_FRAME); + + wire rst_frame = data_in_startofpacket; + + wire data_out_ready_for3header = to_udp_ready; + + /************************* Frame Counter***********************************/ + /* + This is a frame counter; + frameID +1 at the rising edge of data_in_startofpacket + if frame increase at 10kHz, the 27-bit frameID can count 3.72 hour frame + */ + reg [26:0] frameID; + reg data_in_startofpacket_last; + + always @(posedge clk or posedge rst) + begin + if (rst) + begin + data_in_startofpacket_last <= 1'b0; + frameID<= 27'b0; + end + else + begin + data_in_startofpacket_last <= data_in_startofpacket; + if (~data_in_startofpacket_last && data_in_startofpacket) + frameID<= frameID + 1'b1; + end + end + + //**********************bkg_subtraction or not ***************** + + reg[1:0] state_bkg; + localparam STATE_BKG_IDLE = 0; + localparam STATE_RAM_RST = 1; + localparam STATE_BKG_ADD = 3; + localparam STATE_BKG_OUT = 2; + + assign bkg_sub_on = (state_bkg == STATE_BKG_OUT)? 1'b1:1'b0; + + always @(posedge clk or posedge rst) + begin + if (rst) + state_bkg <= STATE_BKG_IDLE; + else if (frameID <=27'd1) + state_bkg <= STATE_RAM_RST; + else if (frameID >BKG_FRAME+1) + state_bkg <= STATE_BKG_OUT; + else + state_bkg <= STATE_BKG_ADD; + end + + + + /************** bkg RAM ****************************/ + /* + for prepare the bkg signal by two RAM; + one for data_in_data[31:16]; the other for data_in_data[15:0] + the signal after bkg subtraction is 16 bit signed; the LSM bit is dropped out; (it's not important with current noise level) + */ + + reg[8:0] rdaddress; //for read ram + reg[8:0] wraddress; + wire wren; + + //data_in_data + ram0_q + reg[31:0] ram0_data; + reg[31:0] ram1_data; + + wire[31:0] ram0_q; + wire[31:0] ram1_q; + + + + ram4bkg ram4bkg0 ( + .data(ram0_data), //32 bits + .rdaddress(rdaddress), + .clock(clk), + .wraddress(wraddress), + .wren(wren), + .q(ram0_q) //32 bits + ); + + ram4bkg ram4bkg1 ( + .data(ram1_data), //32 bits + .rdaddress(rdaddress), + .clock(clk), + .wraddress(wraddress), + .wren(wren), + .q(ram1_q) //32 bits + ); + + wire[15:0] bkg0; + wire[15:0] bkg1; + + assign bkg0 = bkg_sub_on?ram0_q[SHIFT_BIT+15:SHIFT_BIT]:16'b0; + assign bkg1 = bkg_sub_on?ram1_q[SHIFT_BIT+15:SHIFT_BIT]:16'b0; + + + + //data_in_data - bkg0 + reg[16:0] data0_sub; + reg[16:0] data1_sub; + + //data_in_data + wire[15:0] data0_in_data; + wire[15:0] data1_in_data; + + //reverse the polarity of ADC signal for calculation => no for simulation + assign data0_in_data = ~data_in_data[31:16]; + assign data1_in_data = ~data_in_data[15:0]; + + + // *********************** ST interface *********************** + + reg [3:0] state; //State of the state machine + localparam STATE_IDLE = 4'd0; //waiting for SOP + localparam STATE_WORD0 = 4'd1; //sending first word : + localparam STATE_WORD1 = 4'd2; //sending second word: + localparam STATE_WORD2 = 4'd3; //sending third word : + localparam STATE_RDRAM0 = 4'd4; //wait to read the first channel of ram + localparam STATE_INPUT0 = 4'd5; //data_in_ready do sub and sum + localparam STATE_RDRAM1 = 4'd6; //data_in_data is ready to output, data_out_startofpacket is high; read next ram + localparam STATE_INPUT = 4'd7; //data_in_ready do sub and sum for next + localparam STATE_RDRAM = 4'd8; + localparam STATE_OUTPUT_LAST = 4'd9; //output last, data_out_endofpacket is high + localparam STATE_LOC = 4'd10; // + + + wire state_bkg_valid; + wire state_data_valid; + // Check if state_bkg is either STATE_RAM_RST or STATE_BKG_ADD for write + assign state_bkg_valid = (state_bkg == STATE_RAM_RST) || (state_bkg == STATE_BKG_ADD); + // Check if state is STATE_DATA and both data_in_valid and data_out_ready are true + assign state_data_valid = (state == STATE_RDRAM1 || state == STATE_RDRAM || state == STATE_OUTPUT_LAST); + + // Final wren assignment combining the conditions + assign wren = (state_bkg_valid && state_data_valid)? 1'b1 : 1'b0; + + + + //The state machine + always @(posedge clk or posedge rst) + begin + if (rst) + begin + state <= STATE_IDLE; + end + else + case(state) + STATE_IDLE: + begin + rdaddress <= 0; + wraddress <= 0; + if (data_in_startofpacket) + begin + state <= STATE_WORD0; + end + end + STATE_WORD0: + begin + if (data_in_valid && data_out_ready_for3header) + begin + state <= STATE_WORD1; + end + end + STATE_WORD1: + begin + if (data_in_valid && data_out_ready_for3header) + begin + state <= STATE_WORD2; + end + end + STATE_WORD2: + begin + if (data_in_valid && data_out_ready_for3header) + begin + state <= STATE_RDRAM0; + rdaddress <= 0; + end + end + STATE_RDRAM0: + begin + state <= STATE_INPUT0; + end + STATE_INPUT0: + begin + if (data_in_valid) + begin + state <= STATE_RDRAM1; + rdaddress <= rdaddress + 1'b1; + data0_sub <= data0_in_data - bkg0; + data1_sub <= data1_in_data - bkg1; + if (state_bkg == STATE_BKG_ADD) + begin + ram0_data <= data0_in_data + ram0_q; + ram1_data <= data1_in_data + ram1_q; + end else + begin + ram0_data <= 0; + ram1_data <= 0; + end + end + end + STATE_RDRAM1: + begin + if (data_out_ready) + state <= STATE_INPUT; + end + STATE_INPUT: + begin + if (data_in_valid) + begin + if (data_in_endofpacket) + state <= STATE_OUTPUT_LAST; + else + state <= STATE_RDRAM; + rdaddress <= rdaddress + 1'b1; + wraddress <= wraddress + 1'b1; + data0_sub <= data0_in_data - bkg0; + data1_sub <= data1_in_data - bkg1; + if (state_bkg == STATE_BKG_ADD) + begin + ram0_data <= data0_in_data + ram0_q; + ram1_data <= data1_in_data + ram1_q; + end else + begin + ram0_data <= 0; + ram1_data <= 0; + end + end + end + STATE_RDRAM: + begin + if (data_out_ready) + state <= STATE_INPUT; + end + STATE_OUTPUT_LAST: + begin + if (data_out_ready) + state <= STATE_LOC; + end + STATE_LOC: + begin + state <= STATE_IDLE; + end + default: + begin + state <= STATE_IDLE; + end + endcase + end + + + + //output 160 words + assign data_in_ready = ((state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2) && data_out_ready_for3header) || (state == STATE_INPUT) ||(state == STATE_INPUT0); + assign data_out_valid = (state == STATE_RDRAM1 || state == STATE_RDRAM || state == STATE_OUTPUT_LAST) ? 1'b1 : 1'b0; + assign data_out_data = (state == STATE_RDRAM1 || state == STATE_RDRAM || state == STATE_OUTPUT_LAST)? (bkg_sub_on? {data0_sub[16:1],data1_sub[16:1]}: {data0_sub[15:0],data1_sub[15:0]}):0; + assign data_out_startofpacket = (state == STATE_RDRAM1)? 1'b1: 1'b0; + assign data_out_endofpacket = (state == STATE_OUTPUT_LAST) ? 1'b1 : 1'b0; + assign data_out_empty = 0; + + //output the 3 header to upd + assign to_udp_data = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2)? data_in_data:0; + assign to_udp_valid = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2)? data_in_valid: 1'b0; + assign to_udp_empty = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2)? data_in_empty: 2'b0; + assign to_udp_startofpacket = data_in_startofpacket; + assign to_udp_endofpacket = (state == STATE_WORD2)?data_in_valid: 1'b0; + +endmodule diff --git a/FPGA_firmware/sensor_algo_qsys/calibration.v b/FPGA_firmware/sensor_algo_qsys/calibration.v new file mode 100644 index 0000000..8af1539 --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/calibration.v @@ -0,0 +1,248 @@ +/****************************************************************************** +* Copyright * +* Scintillating Fibre Beam Profile Monitor Software by Michal Dziewiecki, * +* Blake Leverington and Liqing Qin is licensed under CC BY 4.0 * +* https://creativecommons.org/licenses/by/4.0/ * +* funded by the Deutsche Forschungsgemeinschaft * +* (DFG, German Research Foundation) Projektnummer 419255448 * +* Project Leader: B.Leverington * +******************************************************************************* +* Create Date - Oct 15th. 2024 * +* Author: L.Qin * +* Module - calibration.v * +******************************************************************************/ +/*Created by Lq.Qin on Oct 15th. 2024*/ + +//module calibration has two functions: calibration and merge 16-bit stream to 32-bit stream and then output +//calibration output 16-bit data_caled +//a better design is a design seperate these two functions +//tested by calibration_tb 25.07.2024 + +module calibration +( + + input wire clk, + input wire rst, // connect to the data_in_startofpacket; to reset for everyframe + + //avalon ST(Streaming) sink: 0 readlatency and 0 readallowence 320 channel + input wire signed[15:0] data_in_data, // st.data + output wire data_in_ready, // .ready + input wire data_in_valid, // .valid + input wire data_in_empty, // .empty + input wire data_in_endofpacket, // .endofpacket + input wire data_in_startofpacket, // .startofpacket + + //the interface with cali_ram (storing cali factor) Avalon-MM: read califac from this ram + output wire [8:0] address, + output wire clken, //read + input wire [15:0] cali_fac, + input wire waitrequest, + + //the interface for provide the calibrated data in a ram // one clock latency + input wire [8:0] data_caled_address, + output wire [15:0] data_caled, + input wire data_caled_rd_enable, // to enable read + + output wire data_in_last, //.... + + //avalon ST(Streaming) source: 0 readlatency and 0 readallowence //160 * 32 bits data + // channel 0 [31:16] channel 1 [15:0] + output wire [31:0] to_udp_data, // st.data + input wire to_udp_ready, // .ready + output wire to_udp_valid, // .valid + output wire [1:0] to_udp_empty, // .empty + output wire to_udp_endofpacket, // .endofpacket + output wire to_udp_startofpacket // .startofpacket +); + + assign data_in_last = data_in_endofpacket; + + localparam SHIFT_BIT = 13; //2^13 = 8192, the calibration factor 1 is represented by 8192 + + //for to_udp_data + reg [15:0] first_data_buffer; + + //for read calibration ram + reg [8:0] read_cali_address; + reg signed[16:0] cali_fac_buffer; + wire read; + assign clken = read; + assign address = read_cali_address; + + //for write and read the calibrated data + reg signed[31:0] data_caled_data_32bit; + wire data_caled_wren_a; + reg [8:0] data_caled_address_a; + wire [8:0] address_b; + assign address_b = (data_caled_rd_enable)? data_caled_address: 9'd0; + wire[15:0] data_caled_data_a; + assign data_caled_data_a = {data_caled_data_32bit[31],data_caled_data_32bit[14+SHIFT_BIT:SHIFT_BIT]}; + + + data_caled_ram data_caled_ram0 ( + + .clock ( clk ), + + .address_a (data_caled_address_a), + .data_a (data_caled_data_a), + .wren_a (data_caled_wren_a), + .q_a ( ), + + .address_b ( address_b ), + .data_b ( ), + .wren_b (1'b0), + .q_b ( data_caled) + ); + + //the state machine for read calibration factor from ram + reg[3:0] state; + localparam STATE_IDLE = 4'd0; //waiting for startofpacket + localparam STATE_CAL0 = 4'd1; //get califactor for channel0 + localparam STATE_INPUT0 = 4'd2; // stream in data for channel0; + localparam STATE_CAL1 = 4'd3; // get califactor for channel1 + localparam STATE_INPUT1 = 4'd4; // stream in data for channel1; + localparam STATE_CAL2 = 4'd5; //get califactor for channel1; output the first 32-bit udp data [channel0, channel1] + localparam STATE_INPUT_EVEN = 4'd6; // stream in data for channel 2,4,6..... + localparam STATE_CAL_ODD = 4'd7; + localparam STATE_INPUT_ODD = 4'd8; + localparam STATE_CAL_EVEN = 4'd9; + localparam STATE_OUTPUT_LAST = 4'd10; //outout the last 32-bit udp data + + + assign data_in_ready = (state == STATE_INPUT0 || state == STATE_INPUT1 || state == STATE_INPUT_EVEN || state == STATE_INPUT_ODD)?1'b1:1'b0; + assign data_caled_wren_a = (state == STATE_CAL1 || state == STATE_CAL2 || state == STATE_CAL_EVEN || state == STATE_CAL_ODD || state == STATE_OUTPUT_LAST)?1'b1:1'b0; + assign read = (state == STATE_CAL0 ||state == STATE_CAL1 || state == STATE_CAL2 || state == STATE_CAL_EVEN || state == STATE_CAL_ODD)?1'b1:1'b0; + + + + always @ (posedge clk or posedge rst) + begin + if (rst) + begin + state <= STATE_IDLE; + data_caled_address_a <= 0; + read_cali_address <= 0; + end + else case(state) + STATE_IDLE: + begin + data_caled_address_a <= 0; + read_cali_address <= 0; + if (data_in_startofpacket) + begin + state <= STATE_CAL0; + end + end + STATE_CAL0: + begin + if (~waitrequest) begin + cali_fac_buffer <= {1'b0,cali_fac}; + state <= STATE_INPUT0; + end + end + STATE_INPUT0: + begin + if (data_in_valid) + begin + first_data_buffer <= 16'd0; + data_caled_data_32bit <= data_in_data*cali_fac_buffer; + //data_caled_data_32bit <= cali_fac_buffer;// test! cali + read_cali_address <= read_cali_address + 1'b1; + state <= STATE_CAL1; + end + end + STATE_CAL1: + begin + if (~waitrequest) begin + cali_fac_buffer <= {1'b0,cali_fac}; + state <= STATE_INPUT1; + end + end + STATE_INPUT1: + begin + if (data_in_valid) + begin + first_data_buffer <= data_caled_data_a; + data_caled_data_32bit <= data_in_data*cali_fac_buffer; + //data_caled_data_32bit <= cali_fac_buffer;// test! cali + read_cali_address <= read_cali_address + 1'b1; + data_caled_address_a <= data_caled_address_a + 1'b1; + state <= STATE_CAL2; + end + end + STATE_CAL2: + begin + if (~waitrequest & to_udp_ready) begin + cali_fac_buffer <= {1'b0,cali_fac}; + state <= STATE_INPUT_EVEN; + end + end + STATE_INPUT_EVEN: + begin + if (data_in_valid) + begin + data_caled_data_32bit <= data_in_data*cali_fac_buffer; + //data_caled_data_32bit <= cali_fac_buffer;// test! cali + first_data_buffer <= 16'd0; + read_cali_address <= read_cali_address + 1'b1; + data_caled_address_a <= data_caled_address_a + 1'b1; + if (data_in_endofpacket) + state <= STATE_OUTPUT_LAST; + else + state <= STATE_CAL_ODD; + end + end + STATE_CAL_ODD: + begin + if (~waitrequest) begin + cali_fac_buffer <= {1'b0,cali_fac}; + state <= STATE_INPUT_ODD; + end + end + STATE_INPUT_ODD: + begin + if (data_in_valid) + begin + first_data_buffer <= data_caled_data_a; + data_caled_data_32bit <= data_in_data*cali_fac_buffer; + //data_caled_data_32bit <= cali_fac_buffer;// test! cali + read_cali_address <= read_cali_address + 1'b1; + data_caled_address_a <= data_caled_address_a + 1'b1; + if (data_in_endofpacket) + state <= STATE_OUTPUT_LAST; + else + state <= STATE_CAL_EVEN; + end + end + STATE_CAL_EVEN: + begin + if (~waitrequest & to_udp_ready) begin + cali_fac_buffer <= {1'b0,cali_fac}; + state <= STATE_INPUT_EVEN; + end + end + STATE_OUTPUT_LAST: + begin + if (to_udp_ready) + state <= STATE_IDLE; + end + default: + state <= STATE_IDLE; + endcase + end + + + //output the 160 32bit words to upd, first channel [31:16] , second channel [15:16] + //output wire [31:0] to_udp_data, // st.data + assign to_udp_valid = (((state == STATE_CAL2 || state == STATE_CAL_EVEN) && (~waitrequest))|| state == STATE_OUTPUT_LAST)? 1'b1: 1'b0; + assign to_udp_empty = 2'b0; + assign to_udp_startofpacket = (state == STATE_CAL2 && (~waitrequest))? 1'b1:1'b0; + assign to_udp_endofpacket = (state == STATE_OUTPUT_LAST)? 1'b1: 1'b0; + //reverse the polarity for output => no for simulation + assign to_udp_data = (((state == STATE_CAL2 || state == STATE_CAL_EVEN) && (~waitrequest))|| state == STATE_OUTPUT_LAST) ? {~first_data_buffer,~data_caled_data_a}: 32'b0; + + + + + +endmodule diff --git a/FPGA_firmware/sensor_algo_qsys/cluster_locate.sv b/FPGA_firmware/sensor_algo_qsys/cluster_locate.sv new file mode 100644 index 0000000..b1a1a99 --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/cluster_locate.sv @@ -0,0 +1,200 @@ +/****************************************************************************** +* Copyright * +* Scintillating Fibre Beam Profile Monitor Software by Michal Dziewiecki, * +* Blake Leverington and Liqing Qin is licensed under CC BY 4.0 * +* https://creativecommons.org/licenses/by/4.0/ * +* funded by the Deutsche Forschungsgemeinschaft * +* (DFG, German Research Foundation) Projektnummer 419255448 * +* Project Leader: B.Leverington * +******************************************************************************* +* Create Date - Oct 15th. 2024 * +* Author: L.Qin * +* Module - cluster_locate.sv * +******************************************************************************/ +/* +Created by Lq.Qin on Oct 15th. 2024 +CLUSTER LOCATE: +if there is continuous [equal or more than SIZE]signals above THRESHOLD, there is cluster; +The STATE_FIRST_CLUSTER find the left position of the Cluster; sig_ch_left +if there is more than one cluster, the STATE_LAST_CLUSTER determine the right position of the Cluster; sig_ch_right +When the address is 319, it goes to output state: +the has_cluster, no_cluster, sig_ch_left and sig_ch_right keep for two clocks +*/ + +//the interface tested by algo_top_cl_tb.v +//the detailed math precise tested by cluster_locate_tb.v + +module cluster_locate // #(parameter THRESHOLD=54, SIZE=4) +( + + input wire clk, + input wire rst, // connect to the data_in_startofpacket; to reset for everyframe + + //avalon ST(Streaming) sink: 0 readlatency and 0 readallowence 320 channel + input logic signed [15:0] data_in_data, // st.data + output wire data_in_ready, // .ready + input wire data_in_valid, // .valid + input wire data_in_empty, // .empty + input wire data_in_endofpacket, // .endofpacket + input wire data_in_startofpacket, // .startofpacket + + input wire[15:0] THRESHOLD, //range 0~255 + input wire[8:0] SIZE, //range 0~255 + + output wire[8:0] sig_ch_left, + output wire[8:0] sig_ch_right, + output wire has_cluster, + output wire no_cluster, + + output wire data_in_last //.... after this, there is has_cluster of no_cluster signal +); + + assign data_in_last = data_in_endofpacket; + + localparam CHANNEL_NUM = 320; + reg signed[15:0] REG_THRESHOLD; + reg unsigned[8:0] REG_SIZE; + + reg[2:0] states; + localparam STATE_IDLE = 3'b000; + localparam STATE_REC = 3'b001; + localparam STATE_FIRST_CLUSTER = 3'b011; + localparam STATE_LAST_CLUSTER = 3'b010; + localparam STATE_HAS_CLUSTER = 3'b110; + localparam STATE_NO_CLUSTER = 3'b111; + localparam STATE_HAS_CLUSTER_KEEP = 3'b101; + localparam STATE_NO_CLUSTER_KEEP = 3'b100; + + reg unsigned[8:0] size_ctr; //the same as the channel + reg[8:0] ch_left; + reg[8:0] ch_right; + reg[8:0] address; + + + assign sig_ch_left = (states == STATE_HAS_CLUSTER || states == STATE_HAS_CLUSTER_KEEP)? ch_left: 9'd0; + assign sig_ch_right = (states == STATE_HAS_CLUSTER || states == STATE_HAS_CLUSTER_KEEP)? ch_right: 9'd0; + assign has_cluster = (states==STATE_HAS_CLUSTER || states == STATE_HAS_CLUSTER_KEEP)? 1'b1: 1'b0; + assign no_cluster = (states==STATE_NO_CLUSTER || states == STATE_NO_CLUSTER_KEEP)? 1'b1 : 1'b0; + + assign data_in_ready = (states == STATE_REC || states == STATE_FIRST_CLUSTER || states == STATE_LAST_CLUSTER)? 1'b1: 1'b0; + + wire data_over_th; /* synthesis keep */ + assign data_over_th = (data_in_data > REG_THRESHOLD)? 1'b1: 1'b0; + + + always @ (posedge clk or posedge rst) + begin + if (rst) + begin + ch_left <= 0; + ch_right <= 0; + address <= 0; + size_ctr <= 0; + states <= STATE_IDLE; + REG_THRESHOLD <= THRESHOLD; + REG_SIZE <= SIZE; + end + else + case(states) + STATE_IDLE: + begin + ch_left <= 0; + ch_right <= 0; + address <= 0; + size_ctr <= 0; + REG_THRESHOLD <= THRESHOLD; + REG_SIZE <= SIZE; + if (data_in_startofpacket) + states <= STATE_REC; + end + STATE_REC: + begin + if (data_in_valid) + begin + address <= address + 1'b1; + if (data_in_endofpacket) + states <= STATE_NO_CLUSTER; + else if (data_over_th) + begin + size_ctr <= size_ctr + 1'b1; + states <= STATE_FIRST_CLUSTER; + ch_left <= address; + end + end + end + STATE_FIRST_CLUSTER: + begin + if (data_in_valid) + begin + address <= address + 1'b1; + if (data_in_endofpacket) + begin + if ((size_ctr + data_over_th) > REG_SIZE) + begin + states <= STATE_HAS_CLUSTER; + ch_right <= address; + end else + states <= STATE_NO_CLUSTER; + end + else if (data_over_th) + size_ctr <= size_ctr + 1'b1; + else + begin + size_ctr <= 0; + if (size_ctr > REG_SIZE) + begin + states <= STATE_LAST_CLUSTER; + ch_right <= address -1'b1; + end else + begin + states <= STATE_REC; + ch_left <= 0; + end + end + end + end + STATE_LAST_CLUSTER: + begin + if (data_in_valid) + begin + address <= address + 1'b1; + if (data_in_endofpacket) + begin + states <= STATE_HAS_CLUSTER; + if ((size_ctr + data_over_th) > REG_SIZE) + ch_right <= address - ~data_over_th; //2024.09.30 ch_right <= address - ~data_over_th; + end + else if (data_over_th) + size_ctr<= size_ctr + 1'b1; + else + begin + if (size_ctr > REG_SIZE) + ch_right <= address-1'b1; + size_ctr <= 0; + end + end + end + STATE_HAS_CLUSTER: + begin + states <= STATE_HAS_CLUSTER_KEEP; + end + STATE_NO_CLUSTER: + begin + states <= STATE_NO_CLUSTER_KEEP; + end + STATE_HAS_CLUSTER_KEEP: + begin + states <= STATE_IDLE; + end + STATE_NO_CLUSTER_KEEP: + begin + states <= STATE_IDLE; + end + default: + states <= STATE_IDLE; + endcase + end + +endmodule + + diff --git a/FPGA_firmware/sensor_algo_qsys/data_caled_ram.v b/FPGA_firmware/sensor_algo_qsys/data_caled_ram.v new file mode 100644 index 0000000..dc286ee --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/data_caled_ram.v @@ -0,0 +1,243 @@ +// megafunction wizard: %RAM: 2-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: data_caled_ram.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 19.1.0 Build 670 09/22/2019 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2019 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module data_caled_ram ( + address_a, + address_b, + clock, + data_a, + data_b, + wren_a, + wren_b, + q_a, + q_b); + + input [8:0] address_a; + input [8:0] address_b; + input clock; + input [15:0] data_a; + input [15:0] data_b; + input wren_a; + input wren_b; + output [15:0] q_a; + output [15:0] q_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; + tri0 wren_a; + tri0 wren_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [15:0] sub_wire0; + wire [15:0] sub_wire1; + wire [15:0] q_a = sub_wire0[15:0]; + wire [15:0] q_b = sub_wire1[15:0]; + + altsyncram altsyncram_component ( + .address_a (address_a), + .address_b (address_b), + .clock0 (clock), + .data_a (data_a), + .data_b (data_b), + .wren_a (wren_a), + .wren_b (wren_b), + .q_a (sub_wire0), + .q_b (sub_wire1), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .eccstatus (), + .rden_a (1'b1), + .rden_b (1'b1)); + defparam + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.indata_reg_b = "CLOCK0", + altsyncram_component.intended_device_family = "MAX 10", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 512, + altsyncram_component.numwords_b = 512, + altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 9, + altsyncram_component.widthad_b = 9, + altsyncram_component.width_a = 16, + altsyncram_component.width_b = 16, + altsyncram_component.width_byteena_a = 1, + altsyncram_component.width_byteena_b = 1, + altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRq NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren NUMERIC "0" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRwren NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Clock_A NUMERIC "0" +// Retrieval info: PRIVATE: Clock_B NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192" +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGq NUMERIC "0" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: REGrren NUMERIC "0" +// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +// Retrieval info: PRIVATE: REGwren NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +// Retrieval info: PRIVATE: VarWidth NUMERIC "0" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]" +// Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL "address_b[8..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL "data_a[15..0]" +// Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL "data_b[15..0]" +// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]" +// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]" +// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" +// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" +// Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0 +// Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0 +// Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0 +// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_firmware/sensor_algo_qsys/div.v b/FPGA_firmware/sensor_algo_qsys/div.v new file mode 100644 index 0000000..5d50d2d --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/div.v @@ -0,0 +1,116 @@ +// megafunction wizard: %LPM_DIVIDE% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: LPM_DIVIDE + +// ============================================================ +// File Name: div.v +// Megafunction Name(s): +// LPM_DIVIDE +// +// Simulation Library Files(s): +// lpm +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 19.1.0 Build 670 09/22/2019 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2019 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module div ( + clken, + clock, + denom, + numer, + quotient, + remain); + + input clken; + input clock; + input [29:0] denom; + input [39:0] numer; + output [39:0] quotient; + output [29:0] remain; + + wire [39:0] sub_wire0; + wire [29:0] sub_wire1; + wire [39:0] quotient = sub_wire0[39:0]; + wire [29:0] remain = sub_wire1[29:0]; + + lpm_divide LPM_DIVIDE_component ( + .clken (clken), + .clock (clock), + .denom (denom), + .numer (numer), + .quotient (sub_wire0), + .remain (sub_wire1), + .aclr (1'b0)); + defparam + LPM_DIVIDE_component.lpm_drepresentation = "UNSIGNED", + LPM_DIVIDE_component.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE", + LPM_DIVIDE_component.lpm_nrepresentation = "UNSIGNED", + LPM_DIVIDE_component.lpm_pipeline = 26, + LPM_DIVIDE_component.lpm_type = "LPM_DIVIDE", + LPM_DIVIDE_component.lpm_widthd = 30, + LPM_DIVIDE_component.lpm_widthn = 40; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE" +// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1" +// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2" +// Retrieval info: PRIVATE: new_diagram STRING "1" +// Retrieval info: LIBRARY: lpm lpm.lpm_components.all +// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED" +// Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE" +// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED" +// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "26" +// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE" +// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "30" +// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "40" +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL "clken" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +// Retrieval info: USED_PORT: denom 0 0 30 0 INPUT NODEFVAL "denom[29..0]" +// Retrieval info: USED_PORT: numer 0 0 40 0 INPUT NODEFVAL "numer[39..0]" +// Retrieval info: USED_PORT: quotient 0 0 40 0 OUTPUT NODEFVAL "quotient[39..0]" +// Retrieval info: USED_PORT: remain 0 0 30 0 OUTPUT NODEFVAL "remain[29..0]" +// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0 +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @denom 0 0 30 0 denom 0 0 30 0 +// Retrieval info: CONNECT: @numer 0 0 40 0 numer 0 0 40 0 +// Retrieval info: CONNECT: quotient 0 0 40 0 @quotient 0 0 40 0 +// Retrieval info: CONNECT: remain 0 0 30 0 @remain 0 0 30 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL div.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL div.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL div.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL div.bsf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL div_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL div_bb.v FALSE +// Retrieval info: LIB_FILE: lpm diff --git a/FPGA_firmware/sensor_algo_qsys/frame_counter.v b/FPGA_firmware/sensor_algo_qsys/frame_counter.v new file mode 100644 index 0000000..2df7a6d --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/frame_counter.v @@ -0,0 +1,36 @@ +//the frame counter +//count the frame number by the sensor_interface status_out[0] rising edge + + + +module frame_counter( + + input wire clk_clk, + input wire rst_reset, //this reset should connect to sensor_interface int_rst + + input wire sig, + input wire [31:0] data_in, //for connect in qsys only + input wire data_in_endofpacket, // for connect in qsys only + + output reg [26:0] frame_Num +); + + + reg sig_last; + + always @(posedge clk_clk or posedge rst_reset) + begin + if (rst_reset) + begin + sig_last <= 1'b0; + frame_Num <= 27'b0; + end + else + begin + sig_last <= sig; + if (~sig_last&&sig) + frame_Num <= frame_Num + 1'b1; + end + end + +endmodule \ No newline at end of file diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/altera_avalon_st_splitter.sv b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/altera_avalon_st_splitter.sv new file mode 100644 index 0000000..c244a3f --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/altera_avalon_st_splitter.sv @@ -0,0 +1,422 @@ +// (C) 2001-2019 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $File: //acds/main/ip/avalon_st/altera_avalon_st_splitter/altera_avalon_st_splitter.sv $ +// $Revision: #3 $ +// $Date: 2012/01/18 $ +// $Author: pscheidt $ +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ns + +module altera_avalon_st_splitter #( + parameter + NUMBER_OF_OUTPUTS = 2, + QUALIFY_VALID_OUT = 1, + DATA_WIDTH = 8, + BITS_PER_SYMBOL = 8, + USE_PACKETS = 0, + CHANNEL_WIDTH = 1, + ERROR_WIDTH = 1, + EMPTY_WIDTH = 1 + ) +( + output wire in0_ready, + input wire in0_valid, + input wire [DATA_WIDTH-1 :0] in0_data, + input wire [CHANNEL_WIDTH-1 :0] in0_channel, + input wire [ERROR_WIDTH-1 :0] in0_error, + input wire in0_startofpacket, + input wire in0_endofpacket, + input wire [EMPTY_WIDTH-1 :0] in0_empty, + + input wire out0_ready, + output wire out0_valid, + output wire [DATA_WIDTH-1 :0] out0_data, + output wire [CHANNEL_WIDTH-1 :0] out0_channel, + output wire [ERROR_WIDTH-1 :0] out0_error, + output wire out0_startofpacket, + output wire out0_endofpacket, + output wire [EMPTY_WIDTH-1 :0] out0_empty, + + input wire out1_ready, + output wire out1_valid, + output wire [DATA_WIDTH-1 :0] out1_data, + output wire [CHANNEL_WIDTH-1 :0] out1_channel, + output wire [ERROR_WIDTH-1 :0] out1_error, + output wire out1_startofpacket, + output wire out1_endofpacket, + output wire [EMPTY_WIDTH-1 :0] out1_empty, + + input wire out2_ready, + output wire out2_valid, + output wire [DATA_WIDTH-1 :0] out2_data, + output wire [CHANNEL_WIDTH-1 :0] out2_channel, + output wire [ERROR_WIDTH-1 :0] out2_error, + output wire out2_startofpacket, + output wire out2_endofpacket, + output wire [EMPTY_WIDTH-1 :0] out2_empty, + + input wire out3_ready, + output wire out3_valid, + output wire [DATA_WIDTH-1 :0] out3_data, + output wire [CHANNEL_WIDTH-1 :0] out3_channel, + output wire [ERROR_WIDTH-1 :0] out3_error, + output wire out3_startofpacket, + output wire out3_endofpacket, + output wire [EMPTY_WIDTH-1 :0] out3_empty, + + input wire out4_ready, + output wire out4_valid, + output wire [DATA_WIDTH-1 :0] out4_data, + output wire [CHANNEL_WIDTH-1 :0] out4_channel, + output wire [ERROR_WIDTH-1 :0] out4_error, + output wire out4_startofpacket, + output wire out4_endofpacket, + output wire [EMPTY_WIDTH-1 :0] out4_empty, + + input wire out5_ready, + output wire out5_valid, + output wire [DATA_WIDTH-1 :0] out5_data, + output wire [CHANNEL_WIDTH-1 :0] out5_channel, + output wire [ERROR_WIDTH-1 :0] out5_error, + output wire out5_startofpacket, + output wire out5_endofpacket, + output wire [EMPTY_WIDTH-1 :0] out5_empty, + + input wire out6_ready, + output wire out6_valid, + output wire [DATA_WIDTH-1 :0] out6_data, + output wire [CHANNEL_WIDTH-1 :0] out6_channel, + output wire [ERROR_WIDTH-1 :0] out6_error, + output wire out6_startofpacket, + output wire out6_endofpacket, + output wire [EMPTY_WIDTH-1 :0] out6_empty, + + input wire out7_ready, + output wire out7_valid, + output wire [DATA_WIDTH-1 :0] out7_data, + output wire [CHANNEL_WIDTH-1 :0] out7_channel, + output wire [ERROR_WIDTH-1 :0] out7_error, + output wire out7_startofpacket, + output wire out7_endofpacket, + output wire [EMPTY_WIDTH-1 :0] out7_empty, + + input wire out8_ready, + output wire out8_valid, + output wire [DATA_WIDTH-1 :0] out8_data, + output wire [CHANNEL_WIDTH-1 :0] out8_channel, + output wire [ERROR_WIDTH-1 :0] out8_error, + output wire out8_startofpacket, + output wire out8_endofpacket, + output wire [EMPTY_WIDTH-1 :0] out8_empty, + + input wire out9_ready, + output wire out9_valid, + output wire [DATA_WIDTH-1 :0] out9_data, + output wire [CHANNEL_WIDTH-1 :0] out9_channel, + output wire [ERROR_WIDTH-1 :0] out9_error, + output wire out9_startofpacket, + output wire out9_endofpacket, + output wire [EMPTY_WIDTH-1 :0] out9_empty, + + input wire out10_ready, + output wire out10_valid, + output wire [DATA_WIDTH-1 :0] out10_data, + output wire [CHANNEL_WIDTH-1 :0] out10_channel, + output wire [ERROR_WIDTH-1 :0] out10_error, + output wire out10_startofpacket, + output wire out10_endofpacket, + output wire [EMPTY_WIDTH-1 :0] out10_empty, + + input wire out11_ready, + output wire out11_valid, + output wire [DATA_WIDTH-1 :0] out11_data, + output wire [CHANNEL_WIDTH-1 :0] out11_channel, + output wire [ERROR_WIDTH-1 :0] out11_error, + output wire out11_startofpacket, + output wire out11_endofpacket, + output wire [EMPTY_WIDTH-1 :0] out11_empty, + + input wire out12_ready, + output wire out12_valid, + output wire [DATA_WIDTH-1 :0] out12_data, + output wire [CHANNEL_WIDTH-1 :0] out12_channel, + output wire [ERROR_WIDTH-1 :0] out12_error, + output wire out12_startofpacket, + output wire out12_endofpacket, + output wire [EMPTY_WIDTH-1 :0] out12_empty, + + input wire out13_ready, + output wire out13_valid, + output wire [DATA_WIDTH-1 :0] out13_data, + output wire [CHANNEL_WIDTH-1 :0] out13_channel, + output wire [ERROR_WIDTH-1 :0] out13_error, + output wire out13_startofpacket, + output wire out13_endofpacket, + output wire [EMPTY_WIDTH-1 :0] out13_empty, + + input wire out14_ready, + output wire out14_valid, + output wire [DATA_WIDTH-1 :0] out14_data, + output wire [CHANNEL_WIDTH-1 :0] out14_channel, + output wire [ERROR_WIDTH-1 :0] out14_error, + output wire out14_startofpacket, + output wire out14_endofpacket, + output wire [EMPTY_WIDTH-1 :0] out14_empty, + + input wire out15_ready, + output wire out15_valid, + output wire [DATA_WIDTH-1 :0] out15_data, + output wire [CHANNEL_WIDTH-1 :0] out15_channel, + output wire [ERROR_WIDTH-1 :0] out15_error, + output wire out15_startofpacket, + output wire out15_endofpacket, + output wire [EMPTY_WIDTH-1 :0] out15_empty, + + input wire clk, + input wire reset +); + + +// ******************************************************************** +// Module Wiring + +wire [15:0] OutReady; +wire [15:0] OutValid; +wire [DATA_WIDTH-1 :0] OutData [15:0]; +wire [CHANNEL_WIDTH-1 :0] OutChannel [15:0]; +wire [ERROR_WIDTH-1 :0] OutError [15:0]; +wire [15:0] OutSOP; +wire [15:0] OutEOP; +wire [EMPTY_WIDTH-1 :0] OutEmpty [15:0]; + +genvar i, j; + + +// ******************************************************************** +// Module Logic + +assign in0_ready = &(OutReady[NUMBER_OF_OUTPUTS-1:0]); + + +generate + for (i=0; i < NUMBER_OF_OUTPUTS; i=i+1) begin : SPLIT_PORT + assign OutData[i] = in0_data; + assign OutChannel[i] = in0_channel; + assign OutError[i] = in0_error; + assign OutSOP[i] = in0_startofpacket; + assign OutEOP[i] = in0_endofpacket; + assign OutEmpty[i] = in0_empty; + end +endgenerate + + +generate + for (j=NUMBER_OF_OUTPUTS; j <16; j=j+1) begin : NULL_PORT + assign OutData[j] = {DATA_WIDTH{1'b0}}; + assign OutChannel[j] = {CHANNEL_WIDTH{1'b0}}; + assign OutError[j] = {ERROR_WIDTH{1'b0}}; + assign OutSOP[j] = 1'b0; + assign OutEOP[j] = 1'b0; + assign OutEmpty[j] = {EMPTY_WIDTH{1'b0}}; + end +endgenerate + + +generate + if (QUALIFY_VALID_OUT) begin + assign OutValid[0] = &{in0_valid, OutReady[15:1]}; + assign OutValid[1] = &{in0_valid, OutReady[15:2], OutReady[0]}; + assign OutValid[2] = &{in0_valid, OutReady[15:3], OutReady[1:0]}; + assign OutValid[3] = &{in0_valid, OutReady[15:4], OutReady[2:0]}; + assign OutValid[4] = &{in0_valid, OutReady[15:5], OutReady[3:0]}; + assign OutValid[5] = &{in0_valid, OutReady[15:6], OutReady[4:0]}; + assign OutValid[6] = &{in0_valid, OutReady[15:7], OutReady[5:0]}; + assign OutValid[7] = &{in0_valid, OutReady[15:8], OutReady[6:0]}; + assign OutValid[8] = &{in0_valid, OutReady[15:9], OutReady[7:0]}; + assign OutValid[9] = &{in0_valid, OutReady[15:10], OutReady[8:0]}; + assign OutValid[10] = &{in0_valid, OutReady[15:11], OutReady[9:0]}; + assign OutValid[11] = &{in0_valid, OutReady[15:12], OutReady[10:0]}; + assign OutValid[12] = &{in0_valid, OutReady[15:13], OutReady[11:0]}; + assign OutValid[13] = &{in0_valid, OutReady[15:14], OutReady[12:0]}; + assign OutValid[14] = &{in0_valid, OutReady[15], OutReady[13:0]}; + assign OutValid[15] = &{in0_valid, OutReady[14:0]}; + end + else begin + assign OutValid[0] = in0_valid; + assign OutValid[1] = in0_valid; + assign OutValid[2] = in0_valid; + assign OutValid[3] = in0_valid; + assign OutValid[4] = in0_valid; + assign OutValid[5] = in0_valid; + assign OutValid[6] = in0_valid; + assign OutValid[7] = in0_valid; + assign OutValid[8] = in0_valid; + assign OutValid[9] = in0_valid; + assign OutValid[10] = in0_valid; + assign OutValid[11] = in0_valid; + assign OutValid[12] = in0_valid; + assign OutValid[13] = in0_valid; + assign OutValid[14] = in0_valid; + assign OutValid[15] = in0_valid; + end +endgenerate + + +assign OutReady[0] = out0_ready; +assign out0_valid = OutValid[0]; +assign out0_data = OutData[0]; +assign out0_channel = OutChannel[0]; +assign out0_error = OutError[0]; +assign out0_startofpacket = OutSOP[0]; +assign out0_endofpacket = OutEOP[0]; +assign out0_empty = OutEmpty[0]; + +assign OutReady[1] = out1_ready; +assign out1_valid = OutValid[1]; +assign out1_data = OutData[1]; +assign out1_channel = OutChannel[1]; +assign out1_error = OutError[1]; +assign out1_startofpacket = OutSOP[1]; +assign out1_endofpacket = OutEOP[1]; +assign out1_empty = OutEmpty[1]; + +assign OutReady[2] = out2_ready; +assign out2_valid = OutValid[2]; +assign out2_data = OutData[2]; +assign out2_channel = OutChannel[2]; +assign out2_error = OutError[2]; +assign out2_startofpacket = OutSOP[2]; +assign out2_endofpacket = OutEOP[2]; +assign out2_empty = OutEmpty[2]; + +assign OutReady[3] = out3_ready; +assign out3_valid = OutValid[3]; +assign out3_data = OutData[3]; +assign out3_channel = OutChannel[3]; +assign out3_error = OutError[3]; +assign out3_startofpacket = OutSOP[3]; +assign out3_endofpacket = OutEOP[3]; +assign out3_empty = OutEmpty[3]; + +assign OutReady[4] = out4_ready; +assign out4_valid = OutValid[4]; +assign out4_data = OutData[4]; +assign out4_channel = OutChannel[4]; +assign out4_error = OutError[4]; +assign out4_startofpacket = OutSOP[4]; +assign out4_endofpacket = OutEOP[4]; +assign out4_empty = OutEmpty[4]; + +assign OutReady[5] = out5_ready; +assign out5_valid = OutValid[5]; +assign out5_data = OutData[5]; +assign out5_channel = OutChannel[5]; +assign out5_error = OutError[5]; +assign out5_startofpacket = OutSOP[5]; +assign out5_endofpacket = OutEOP[5]; +assign out5_empty = OutEmpty[5]; + +assign OutReady[6] = out6_ready; +assign out6_valid = OutValid[6]; +assign out6_data = OutData[6]; +assign out6_channel = OutChannel[6]; +assign out6_error = OutError[6]; +assign out6_startofpacket = OutSOP[6]; +assign out6_endofpacket = OutEOP[6]; +assign out6_empty = OutEmpty[6]; + +assign OutReady[7] = out7_ready; +assign out7_valid = OutValid[7]; +assign out7_data = OutData[7]; +assign out7_channel = OutChannel[7]; +assign out7_error = OutError[7]; +assign out7_startofpacket = OutSOP[7]; +assign out7_endofpacket = OutEOP[7]; +assign out7_empty = OutEmpty[7]; + +assign OutReady[8] = out8_ready; +assign out8_valid = OutValid[8]; +assign out8_data = OutData[8]; +assign out8_channel = OutChannel[8]; +assign out8_error = OutError[8]; +assign out8_startofpacket = OutSOP[8]; +assign out8_endofpacket = OutEOP[8]; +assign out8_empty = OutEmpty[8]; + +assign OutReady[9] = out9_ready; +assign out9_valid = OutValid[9]; +assign out9_data = OutData[9]; +assign out9_channel = OutChannel[9]; +assign out9_error = OutError[9]; +assign out9_startofpacket = OutSOP[9]; +assign out9_endofpacket = OutEOP[9]; +assign out9_empty = OutEmpty[9]; + +assign OutReady[10] = out10_ready; +assign out10_valid = OutValid[10]; +assign out10_data = OutData[10]; +assign out10_channel = OutChannel[10]; +assign out10_error = OutError[10]; +assign out10_startofpacket = OutSOP[10]; +assign out10_endofpacket = OutEOP[10]; +assign out10_empty = OutEmpty[10]; + +assign OutReady[11] = out11_ready; +assign out11_valid = OutValid[11]; +assign out11_data = OutData[11]; +assign out11_channel = OutChannel[11]; +assign out11_error = OutError[11]; +assign out11_startofpacket = OutSOP[11]; +assign out11_endofpacket = OutEOP[11]; +assign out11_empty = OutEmpty[11]; + +assign OutReady[12] = out12_ready; +assign out12_valid = OutValid[12]; +assign out12_data = OutData[12]; +assign out12_channel = OutChannel[12]; +assign out12_error = OutError[12]; +assign out12_startofpacket = OutSOP[12]; +assign out12_endofpacket = OutEOP[12]; +assign out12_empty = OutEmpty[12]; + +assign OutReady[13] = out13_ready; +assign out13_valid = OutValid[13]; +assign out13_data = OutData[13]; +assign out13_channel = OutChannel[13]; +assign out13_error = OutError[13]; +assign out13_startofpacket = OutSOP[13]; +assign out13_endofpacket = OutEOP[13]; +assign out13_empty = OutEmpty[13]; + +assign OutReady[14] = out14_ready; +assign out14_valid = OutValid[14]; +assign out14_data = OutData[14]; +assign out14_channel = OutChannel[14]; +assign out14_error = OutError[14]; +assign out14_startofpacket = OutSOP[14]; +assign out14_endofpacket = OutEOP[14]; +assign out14_empty = OutEmpty[14]; + +assign OutReady[15] = out15_ready; +assign out15_valid = OutValid[15]; +assign out15_data = OutData[15]; +assign out15_channel = OutChannel[15]; +assign out15_error = OutError[15]; +assign out15_startofpacket = OutSOP[15]; +assign out15_endofpacket = OutEOP[15]; +assign out15_empty = OutEmpty[15]; + + +endmodule diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/st_splitter16.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/st_splitter16.v new file mode 100644 index 0000000..823c35f --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/st_splitter16.v @@ -0,0 +1,179 @@ +// st_splitter16.v + +// Generated using ACDS version 19.1 670 + +`timescale 1 ps / 1 ps +module st_splitter16 ( + input wire st_splitter16_clk_clk, // st_splitter16_clk.clk + output wire st_splitter16_in_ready, // st_splitter16_in.ready + input wire st_splitter16_in_valid, // .valid + input wire st_splitter16_in_startofpacket, // .startofpacket + input wire st_splitter16_in_endofpacket, // .endofpacket + input wire [0:0] st_splitter16_in_empty, // .empty + input wire [15:0] st_splitter16_in_data, // .data + input wire st_splitter16_out0_ready, // st_splitter16_out0.ready + output wire st_splitter16_out0_valid, // .valid + output wire st_splitter16_out0_startofpacket, // .startofpacket + output wire st_splitter16_out0_endofpacket, // .endofpacket + output wire [0:0] st_splitter16_out0_empty, // .empty + output wire [15:0] st_splitter16_out0_data, // .data + input wire st_splitter16_out1_ready, // st_splitter16_out1.ready + output wire st_splitter16_out1_valid, // .valid + output wire st_splitter16_out1_startofpacket, // .startofpacket + output wire st_splitter16_out1_endofpacket, // .endofpacket + output wire [0:0] st_splitter16_out1_empty, // .empty + output wire [15:0] st_splitter16_out1_data, // .data + input wire st_splitter16_reset_reset // st_splitter16_reset.reset + ); + + altera_avalon_st_splitter #( + .NUMBER_OF_OUTPUTS (2), + .QUALIFY_VALID_OUT (1), + .USE_PACKETS (1), + .DATA_WIDTH (16), + .CHANNEL_WIDTH (1), + .ERROR_WIDTH (1), + .BITS_PER_SYMBOL (8), + .EMPTY_WIDTH (1) + ) st_splitter16 ( + .clk (st_splitter16_clk_clk), // clk.clk + .reset (st_splitter16_reset_reset), // reset.reset + .in0_ready (st_splitter16_in_ready), // in.ready + .in0_valid (st_splitter16_in_valid), // .valid + .in0_startofpacket (st_splitter16_in_startofpacket), // .startofpacket + .in0_endofpacket (st_splitter16_in_endofpacket), // .endofpacket + .in0_empty (st_splitter16_in_empty), // .empty + .in0_data (st_splitter16_in_data), // .data + .out0_ready (st_splitter16_out0_ready), // out0.ready + .out0_valid (st_splitter16_out0_valid), // .valid + .out0_startofpacket (st_splitter16_out0_startofpacket), // .startofpacket + .out0_endofpacket (st_splitter16_out0_endofpacket), // .endofpacket + .out0_empty (st_splitter16_out0_empty), // .empty + .out0_data (st_splitter16_out0_data), // .data + .out1_ready (st_splitter16_out1_ready), // out1.ready + .out1_valid (st_splitter16_out1_valid), // .valid + .out1_startofpacket (st_splitter16_out1_startofpacket), // .startofpacket + .out1_endofpacket (st_splitter16_out1_endofpacket), // .endofpacket + .out1_empty (st_splitter16_out1_empty), // .empty + .out1_data (st_splitter16_out1_data), // .data + .in0_channel (1'b0), // (terminated) + .in0_error (1'b0), // (terminated) + .out0_channel (), // (terminated) + .out0_error (), // (terminated) + .out1_channel (), // (terminated) + .out1_error (), // (terminated) + .out2_ready (1'b1), // (terminated) + .out2_valid (), // (terminated) + .out2_startofpacket (), // (terminated) + .out2_endofpacket (), // (terminated) + .out2_empty (), // (terminated) + .out2_channel (), // (terminated) + .out2_error (), // (terminated) + .out2_data (), // (terminated) + .out3_ready (1'b1), // (terminated) + .out3_valid (), // (terminated) + .out3_startofpacket (), // (terminated) + .out3_endofpacket (), // (terminated) + .out3_empty (), // (terminated) + .out3_channel (), // (terminated) + .out3_error (), // (terminated) + .out3_data (), // (terminated) + .out4_ready (1'b1), // (terminated) + .out4_valid (), // (terminated) + .out4_startofpacket (), // (terminated) + .out4_endofpacket (), // (terminated) + .out4_empty (), // (terminated) + .out4_channel (), // (terminated) + .out4_error (), // (terminated) + .out4_data (), // (terminated) + .out5_ready (1'b1), // (terminated) + .out5_valid (), // (terminated) + .out5_startofpacket (), // (terminated) + .out5_endofpacket (), // (terminated) + .out5_empty (), // (terminated) + .out5_channel (), // (terminated) + .out5_error (), // (terminated) + .out5_data (), // (terminated) + .out6_ready (1'b1), // (terminated) + .out6_valid (), // (terminated) + .out6_startofpacket (), // (terminated) + .out6_endofpacket (), // (terminated) + .out6_empty (), // (terminated) + .out6_channel (), // (terminated) + .out6_error (), // (terminated) + .out6_data (), // (terminated) + .out7_ready (1'b1), // (terminated) + .out7_valid (), // (terminated) + .out7_startofpacket (), // (terminated) + .out7_endofpacket (), // (terminated) + .out7_empty (), // (terminated) + .out7_channel (), // (terminated) + .out7_error (), // (terminated) + .out7_data (), // (terminated) + .out8_ready (1'b1), // (terminated) + .out8_valid (), // (terminated) + .out8_startofpacket (), // (terminated) + .out8_endofpacket (), // (terminated) + .out8_empty (), // (terminated) + .out8_channel (), // (terminated) + .out8_error (), // (terminated) + .out8_data (), // (terminated) + .out9_ready (1'b1), // (terminated) + .out9_valid (), // (terminated) + .out9_startofpacket (), // (terminated) + .out9_endofpacket (), // (terminated) + .out9_empty (), // (terminated) + .out9_channel (), // (terminated) + .out9_error (), // (terminated) + .out9_data (), // (terminated) + .out10_ready (1'b1), // (terminated) + .out10_valid (), // (terminated) + .out10_startofpacket (), // (terminated) + .out10_endofpacket (), // (terminated) + .out10_empty (), // (terminated) + .out10_channel (), // (terminated) + .out10_error (), // (terminated) + .out10_data (), // (terminated) + .out11_ready (1'b1), // (terminated) + .out11_valid (), // (terminated) + .out11_startofpacket (), // (terminated) + .out11_endofpacket (), // (terminated) + .out11_empty (), // (terminated) + .out11_channel (), // (terminated) + .out11_error (), // (terminated) + .out11_data (), // (terminated) + .out12_ready (1'b1), // (terminated) + .out12_valid (), // (terminated) + .out12_startofpacket (), // (terminated) + .out12_endofpacket (), // (terminated) + .out12_empty (), // (terminated) + .out12_channel (), // (terminated) + .out12_error (), // (terminated) + .out12_data (), // (terminated) + .out13_ready (1'b1), // (terminated) + .out13_valid (), // (terminated) + .out13_startofpacket (), // (terminated) + .out13_endofpacket (), // (terminated) + .out13_empty (), // (terminated) + .out13_channel (), // (terminated) + .out13_error (), // (terminated) + .out13_data (), // (terminated) + .out14_ready (1'b1), // (terminated) + .out14_valid (), // (terminated) + .out14_startofpacket (), // (terminated) + .out14_endofpacket (), // (terminated) + .out14_empty (), // (terminated) + .out14_channel (), // (terminated) + .out14_error (), // (terminated) + .out14_data (), // (terminated) + .out15_ready (1'b1), // (terminated) + .out15_valid (), // (terminated) + .out15_startofpacket (), // (terminated) + .out15_endofpacket (), // (terminated) + .out15_empty (), // (terminated) + .out15_channel (), // (terminated) + .out15_error (), // (terminated) + .out15_data () // (terminated) + ); + +endmodule diff --git a/FPGA_firmware/sensor_algo_qsys/ram4bkg.v b/FPGA_firmware/sensor_algo_qsys/ram4bkg.v new file mode 100644 index 0000000..d4e9c5b --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/ram4bkg.v @@ -0,0 +1,214 @@ +// megafunction wizard: %RAM: 2-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: ram4bkg.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 19.1.0 Build 670 09/22/2019 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2019 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module ram4bkg ( + clock, + data, + rdaddress, + wraddress, + wren, + q); + + input clock; + input [31:0] data; + input [7:0] rdaddress; + input [7:0] wraddress; + input wren; + output [31:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; + tri0 wren; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [31:0] sub_wire0; + wire [31:0] q = sub_wire0[31:0]; + + altsyncram altsyncram_component ( + .address_a (wraddress), + .address_b (rdaddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .q_b (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({32{1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "MAX 10", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 256, + altsyncram_component.numwords_b = 256, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = 8, + altsyncram_component.widthad_b = 8, + altsyncram_component.width_a = 32, + altsyncram_component.width_b = 32, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRq NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren NUMERIC "0" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRwren NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Clock_A NUMERIC "0" +// Retrieval info: PRIVATE: Clock_B NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192" +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGq NUMERIC "1" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" +// Retrieval info: PRIVATE: REGrren NUMERIC "1" +// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +// Retrieval info: PRIVATE: REGwren NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +// Retrieval info: PRIVATE: VarWidth NUMERIC "0" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" +// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" +// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]" +// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" +// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0 +// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_firmware/sensor_algo_qsys/rms.sv b/FPGA_firmware/sensor_algo_qsys/rms.sv new file mode 100644 index 0000000..63bf4cd --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/rms.sv @@ -0,0 +1,410 @@ +/****************************************************************************** +* Copyright * +* Scintillating Fibre Beam Profile Monitor Software by Michal Dziewiecki, * +* Blake Leverington and Liqing Qin is licensed under CC BY 4.0 * +* https://creativecommons.org/licenses/by/4.0/ * +* funded by the Deutsche Forschungsgemeinschaft * +* (DFG, German Research Foundation) Projektnummer 419255448 * +* Project Leader: B.Leverington * +******************************************************************************* +* Create Date - Oct 15th. 2024 * +* Author: L.Qin * +* Module - rms.sv * +******************************************************************************/ +//the module for rms +/* + +if there is cluster: +go through the data three times: +first time, calc Xmean; +second time calc Sigma; + +if there is no cluster: +directly send it. + +*/ + +// + +//tested with algo_top_cl_cali_rms_tb.v + +module rms( + + input wire clk, // clk.clk + input wire rst, // the reset should connect to the int_rst from sensor + + //data for sig after bkg subtraction + input wire bkg_sub_on, //indicate that bkg_sub is on + input wire sig_ram_last, //the last channel is being wroten when sig_ram_last=1'b1 + + output wire[8:0] sig_rdaddress, //0~319 for data. 500~502 for the 3 words head + input wire [15:0] sig, + output wire sig_rd_eable, //eable read, get sig next clock + + //the output of cluster_locate + input wire[8:0] sig_ch_left, //after sig_ram_last, if has_cluster, catch the sig_ch_left and right signal, and calc + input wire[8:0] sig_ch_right, + input wire has_cluster, + input wire no_cluster, // this is not used + + //the result + output wire overflow, + + //avalon ST(Streaming) source: 0 readlatency and 0 readallowence //4 * 32 bits data + output wire [31:0] to_udp_data, // st.data + input wire to_udp_ready, // .ready + output wire to_udp_valid, // .valid + output wire [1:0] to_udp_empty, // .empty + output wire to_udp_endofpacket, // .endofpacket + output wire to_udp_startofpacket // .startofpacket + + ); + + + + + /* reg results has 32*4 bits + WORDS 163 [31:16]MeanXleftshift [15:0] Sigma0; + 164 [31:16]MaxY; [15:0] STATUS; + 165 for debug; + 166 for debug; + for status register: + STATUS_BKG_SUB_ON 0x0001 + STATUS_HAS_CLUSTER 0x0002 + STATUS_NO_CLUSTER 0x0004 + */ + + + reg[31:0] results[4]; + + localparam WORDS_TO_SEND = 4; //results[4] + localparam SHIFT_BITS = 2; + + + reg[3:0] state; + localparam STATE_IDLE = 0; //when sig_ram_last, move to STATE_JUDGE + localparam STATE_JUDGE = 1; + /*reset registers; If has_cluster to STATE_CAL1 => WAIT_4_CLK => DIV1 => CAL2 => WAIT_6CLK => DIV2 => SQRT => LOCK => SEND=>, + if not to =>SEND*/ + localparam STATE_SEND = 2; // give a start_transmission signal and start the other statemachine for sending + localparam STATE_CAL1 = 4; + localparam STATE_WAIT_4CLK = 5; + localparam STATE_DIV1 = 6; + localparam STATE_CAL2 = 7; + localparam STATE_WAIT_6CLK = 8; + localparam STATE_DIV2 = 9; + localparam STATE_SQRT = 10; + localparam STATE_LOCK = 11; //lock the MaxY, Sigma0, and MeanXleftshift + + + + // channel_ctr is address from sig_ram + // arrayID depends on the channel_ctr one clock ago + reg[8:0] channel_ctr; + localparam CH_NUM = 320; //channel number, 5 array, 320 channel + reg[8:0] ch_right; + reg[8:0] ch_left; + reg signed[3:0] arrayID; + + assign sig_rdaddress = channel_ctr; + assign sig_rd_eable = (state == STATE_CAL1 || state == STATE_CAL2)? 1'b1: 1'b0; + + // registers for CAL1 + reg signed[13:0] X[2]; + reg signed[15:0] Y[3]; //only Y[0] for cal1 //Y[2], Y[1], Y[0] for cal2, pipe + reg signed[15:0] MaxY; + reg signed[31:0] SumY; + reg signed[31:0] XY; + reg signed[34:0] SumXY; + wire signed[36:0] SumXYleftshift; + reg signed[13:0] MeanXleftshift; + + assign SumXYleftshift = SumXY << SHIFT_BITS; + + + //the registers for CAL2 + reg signed[31:0] SumYm1; //SumY - 1 + reg signed[14:0] DiffxMeanX; + reg signed[28:0] DiffxMeanX2; + reg signed[43:0] DiffxMeanX2Yi; + reg signed[43:0] SumDiffxMeanX2Yi; + reg unsigned[25:0] Sigma2; + reg unsigned[12:0] Sigma0; + + + + + //the wait_ctr for different steps in each states + reg unsigned[8:0] wait_ctr; + + wire div_clken; + wire[29:0] denom; + wire[39:0] numer; + wire[31:0] quotient; + assign div_clken = (state == STATE_DIV1 || state == STATE_DIV2)? 1'b1: 1'b0; + assign denom = (state == STATE_DIV1)? SumY[29:0]: + (state == STATE_DIV2)? (SumYm1[29:0]): 30'b1; + assign numer = (state == STATE_DIV1)? (SumXYleftshift[35:0]) : + (state == STATE_DIV2)? SumDiffxMeanX2Yi[39:0]: 0; + localparam DIV_LATENCY = 26; + //division with 26 clocks latency + div div1 ( + .clken ( div_clken ), + .clock ( clk), + .denom ( denom ), + .numer ( numer ), + .quotient ( quotient ) + ); + + wire sqrt_clken; + wire[25:0] radical_sig; + wire[12:0] q_sqrt; + assign sqrt_clken = (state == STATE_SQRT)? 1'b1: 1'b0; + assign radical_sig = (state == STATE_SQRT)? Sigma2: 26'b0; + localparam SQRT_LATENCY = 13; + //sqrt with 13 clocks latency + sqrt sqrt_inst ( + .clk ( clk), + .ena ( sqrt_clken ), + .radical ( radical_sig ), + .q ( q_sqrt ) + ); + + + // 12 July 2024 I should change arrayID to wires + //the sequential logic for arrayID + always @ (posedge clk or posedge rst) + begin + if (rst) + arrayID <= 4'd0; + else if (channel_ctr>=9'h0 && channel_ctr<9'h40) + arrayID <= 4'd0; + else if (channel_ctr<9'h80) + arrayID <= 4'd1; + else if (channel_ctr<9'hC0) + arrayID <= 4'd2; + else if (channel_ctr<9'h100) + arrayID <= 4'd3; + else if (channel_ctr<9'h140) + arrayID <= 4'd4; + else + arrayID <= 4'd0; + end + + + always @ (posedge clk or posedge rst) + begin + if (rst) + begin + state <= STATE_IDLE; + end + else case(state) + STATE_IDLE: + begin + X[0] <= 0; //For cal1 + X[1] <= 0; + Y[0] <= 0; + MaxY <= 0; + XY <= 0; + SumXY <= 0; + SumY <= 0; + SumDiffxMeanX2Yi <= 0; + wait_ctr <= 0; + MeanXleftshift <= 0; + Y[1] <= 0; //For cal2 + Y[2] <= 0; + SumYm1 <= 0; + DiffxMeanX <= 0; + DiffxMeanX2 <= 0; + DiffxMeanX2Yi <= 0; + SumDiffxMeanX2Yi <= 0; + Sigma2 <= 0; + Sigma0 <= 0; + results[0] <= 0; //Collect Results + results[1] <= 0; + results[2] <= 0; + results[3] <= 0; + ch_right <= 0; + ch_left <= 0; + if (sig_ram_last) begin + state <= STATE_JUDGE; + end + end + STATE_JUDGE: + begin + if (~sig_ram_last) begin + if (bkg_sub_on && has_cluster) + state <= STATE_CAL1; + else + state <= STATE_SEND; + results[1][0] <= bkg_sub_on; + results[1][1] <= has_cluster; + results[1][2] <= no_cluster; + results[2][31:16] <= {7'b0,sig_ch_left}; + results[2][15:0] <= {7'b0,sig_ch_right}; + ch_right <= sig_ch_right; + ch_left <= sig_ch_left; + channel_ctr <= sig_ch_left; + end + end + STATE_CAL1: + begin + wait_ctr <= wait_ctr + 1'b1; + channel_ctr <= channel_ctr + 1'b1; + X[1][12:0]<= channel_ctr << 2; //here, the position is quantized in 1 per 0.2mm + if (wait_ctr >= 1) begin + X[0] <= X[1] + arrayID; + Y[0] <= sig; + end + if (wait_ctr>=2) begin + XY <= X[0]*Y[0]; + SumY <= SumY + Y[0]; + if (MaxY=3) begin + SumXY <= SumXY + XY; + end + if (channel_ctr ==ch_right) begin + state <= STATE_WAIT_4CLK; + channel_ctr <= ch_left; + wait_ctr <= 0; + end + end + STATE_WAIT_4CLK: + begin + wait_ctr <= wait_ctr + 1'b1; + if (wait_ctr < 1) begin + X[0] <= X[1] + arrayID; + Y[0] <= sig; + end + if (wait_ctr < 2) begin + XY <= X[0]*Y[0]; + SumY <= SumY + Y[0]; + if (MaxY= 1) begin + X[0] <= (X[1] + arrayID) << SHIFT_BITS; // here the position is quantized in 1 per 0.05 mm when SHIFT_BITS = 2 + Y[2] <= sig; + end + if (wait_ctr >= 2) begin + Y[1] <= Y[2]; + DiffxMeanX <= X[0] - MeanXleftshift; + end + if (wait_ctr >= 3) begin + Y[0] <= Y[1]; + DiffxMeanX2 <= DiffxMeanX * DiffxMeanX; + end + if (wait_ctr >= 4) begin + DiffxMeanX2Yi <= DiffxMeanX2*Y[0]; + end + if (wait_ctr >= 5) begin + SumDiffxMeanX2Yi <= SumDiffxMeanX2Yi + DiffxMeanX2Yi; + end + if (channel_ctr ==ch_right) begin + state <= STATE_WAIT_6CLK; + wait_ctr <= 0; + channel_ctr <= ch_left; + end + end + STATE_WAIT_6CLK: + begin + wait_ctr <= wait_ctr + 1'b1; + if (wait_ctr < 1) begin + X[0] <= (X[1] + arrayID) << SHIFT_BITS; // here the position is quantized in 1 per 0.05 mm when SHIFT_BITS = 2 + Y[2] <= sig; + end + if (wait_ctr < 2) begin + Y[1] <= Y[2]; + DiffxMeanX <= X[0] - MeanXleftshift; + end + if (wait_ctr < 3) begin + Y[0] <= Y[1]; + DiffxMeanX2 <= DiffxMeanX * DiffxMeanX; + end + if (wait_ctr < 4) begin + DiffxMeanX2Yi <= DiffxMeanX2*Y[0]; + end + if (wait_ctr < 5) begin + SumDiffxMeanX2Yi <= SumDiffxMeanX2Yi + DiffxMeanX2Yi; + end + if (wait_ctr == 5) begin + wait_ctr <= 0; + state <= STATE_DIV2; + end + end + STATE_DIV2: + begin + wait_ctr <= wait_ctr + 1'b1; + if (wait_ctr == DIV_LATENCY) + begin + Sigma2 <= quotient[25:0]; + wait_ctr <= 0; + state <= STATE_SQRT; + end + end + STATE_SQRT: + begin + wait_ctr <= wait_ctr + 1'b1; + if (wait_ctr == SQRT_LATENCY) + begin + state <= STATE_LOCK; + wait_ctr <= 0; + Sigma0 <= q_sqrt; + end + end + STATE_LOCK: + begin + results[0][31:16] <= MeanXleftshift; + results[0][15:0] <= Sigma0; + results[1][31:16] <= MaxY; + state <= STATE_SEND; + end + STATE_SEND: + begin + if (to_udp_ready) + begin + wait_ctr <= wait_ctr + 1'b1; + if (wait_ctr == WORDS_TO_SEND-1) + state <= STATE_IDLE; + end + end + default: + state <= STATE_IDLE; + endcase + end + + assign to_udp_data = (state == STATE_SEND)? results[wait_ctr]:32'b0; + assign to_udp_empty = 2'b0; + assign to_udp_startofpacket = (state == STATE_SEND && wait_ctr == 9'b0)? 1'b1: 1'b0; + assign to_udp_valid = (state == STATE_SEND)? 1'b1: 1'b0; + assign to_udp_endofpacket = (state == STATE_SEND && wait_ctr == (WORDS_TO_SEND-1))? 1'b1: 1'b0; + + + + endmodule \ No newline at end of file diff --git a/FPGA_firmware/sensor_algo_qsys/sensor_algo.v b/FPGA_firmware/sensor_algo_qsys/sensor_algo.v new file mode 100644 index 0000000..6b224e6 --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/sensor_algo.v @@ -0,0 +1,153 @@ +/****************************************************************************** +* Copyright * +* Scintillating Fibre Beam Profile Monitor Software by Michal Dziewiecki, * +* Blake Leverington and Liqing Qin is licensed under CC BY 4.0 * +* https://creativecommons.org/licenses/by/4.0/ * +* funded by the Deutsche Forschungsgemeinschaft * +* (DFG, German Research Foundation) Projektnummer 419255448 * +* Project Leader: B.Leverington * +******************************************************************************* +* Create Date - Oct 15th. 2024 * +* Author: L.Qin * +* Module - sensor_algo.v * +******************************************************************************/ +/*Created by Lq.Qin on Oct 15th. 2024*/ +//module sensor_algo +//combine sensor_interface bkg_subtraction, cluster_locate, and calibration, and rms + + +module sensor_algo( + + //Clock/reset + input wire clk_clk, // clk.clk + input wire rst_reset, // rst.reset + //Avalon MM slave + input wire [1:0] csr_address, // avalon_slave.address + input wire csr_read, // .read + output wire [31:0] csr_readdata, // .readdata + input wire csr_write, // .write + input wire [31:0] csr_writedata, // .writedata + input wire [3:0] csr_byteenable, // .byteenable + //Avalon ST transmitter + output wire [31:0] data_out_data, // avalon_streaming_source.data + output wire data_out_endofpacket, // .endofpacket + output wire data_out_startofpacket, // .startofpacket + input wire data_out_ready, // .ready + output wire data_out_valid, // .valid + output wire [1:0] data_out_empty, // .empty + //Sensor interface + input wire in_trg, // sensor.in_trg // This is the frame timer + output wire out_adc_clk, // .out_dac_clk + output wire out_adc_cnv, // .out_dac_cnv + input wire [4:0] in_adc_data, // .in_dac_data + output wire out_sensor_rst, // .out_sensor_rst + output wire out_sensor_clk, // .out_sensor_clk + output wire out_sensor_gain, // .out_sensor_gain + //Serial synchro interface + input wire serial_rx, //receive data + output wire serial_tx, //send data + input wire [7:0] ext_input, //SMA etc. + //Debug information + output wire [7:0] status_out, //status bits - same as in reg0_read[15:8] + + + //the interface with cali_ram (storing cali factor) Avalon-MM: read califac from this ram; output is not registered + output wire [8:0] address, + output wire clken, + input wire [15:0] cali_fac, + input wire waitrequest + +); + + + wire [31:0] data_out_data1; // Output data + wire data_out_endofpacket1; // Output end-of-packet signal + wire data_out_startofpacket1; // Output start-of-packet signal + wire data_out_ready1; // Output ready signal + wire data_out_valid1; // Output valid signal + wire [1:0] data_out_empty1; // Output empty signal + + wire int_rst; + wire [7:0] cluster_threshold; + wire [7:0] cluster_size; + wire [7:0] in_algo_threshold; + + + + sensor_interface the_sensor_interface ( + .clk_clk (clk_clk), // clk.clk + .rst_reset (rst_reset), // rst.reset + + .csr_address (csr_address), // csr.address + .csr_write (csr_write), // .write + .csr_writedata (csr_writedata), // .writedata + .csr_byteenable (csr_byteenable), // .byteenable + .csr_read (csr_read), // .read + .csr_readdata (csr_readdata), // .readdata + + .data_out_data (data_out_data1), // data_out.data + .data_out_empty (data_out_empty1), // .empty + .data_out_endofpacket (data_out_endofpacket1), // .endofpacket + .data_out_startofpacket (data_out_startofpacket1),// .startofpacket + .data_out_ready (data_out_ready1), // .ready + .data_out_valid (data_out_valid1), // .valid + + .in_trg (in_trg), // sensor.in_trg + .out_adc_clk (out_adc_clk), // .out_dac_clk + .out_adc_cnv (out_adc_cnv), // .out_dac_cnv + .in_adc_data (in_adc_data), // .in_dac_data + .out_sensor_rst (out_sensor_rst), // .out_sensor_rst + .out_sensor_clk (out_sensor_clk), // .out_sensor_clk + .out_sensor_gain (out_sensor_gain), // .out_sensor_gain + .serial_rx (serial_rx), //receive data + .serial_tx (serial_tx), //send data + .ext_input (ext_input), //SMA etc. + + .int_rst (int_rst), + .cluster_threshold (cluster_threshold), + .cluster_size (cluster_size), + .in_algo_threshold (in_algo_threshold) + + ); + + + algo_top_cl_cali_rms recon( + + .clk (clk_clk), + .rst (int_rst), + + .data_in_data (data_out_data1), + .data_in_ready (data_out_ready1), + .data_in_valid (data_out_valid1), + .data_in_empty (data_out_empty1), + .data_in_startofpacket (data_out_startofpacket1), + .data_in_endofpacket (data_out_endofpacket1), + + + .CL_THRESHOLD (cluster_threshold), + .CL_SIZE (cluster_size), + .IN_ALGO_THRESHOLD (in_algo_threshold), + + .address (address), + .clken (clken), + .cali_fac (cali_fac), + .waitrequest(waitrequest), + + .to_udp_data (data_out_data), + .to_udp_ready(data_out_ready), + .to_udp_valid (data_out_valid), + .to_udp_empty (data_out_empty), + .to_udp_endofpacket (data_out_endofpacket), + .to_udp_startofpacket (data_out_startofpacket) + ); + + + + + +endmodule + + + + + \ No newline at end of file diff --git a/FPGA_firmware/sensor_algo_qsys/sensor_interface.v b/FPGA_firmware/sensor_algo_qsys/sensor_interface.v new file mode 100644 index 0000000..2b45fa3 --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/sensor_interface.v @@ -0,0 +1,796 @@ +/****************************************************************************** +* Copyright * +* Scintillating Fibre Beam Profile Monitor Software by Michal Dziewiecki, * +* Blake Leverington and Liqing Qin is licensed under CC BY 4.0 * +* https://creativecommons.org/licenses/by/4.0/ * +* funded by the Deutsche Forschungsgemeinschaft * +* (DFG, German Research Foundation) Projektnummer 419255448 * +* Project Leader: B.Leverington * +******************************************************************************* +* Create Date - 2019 * +* Author: M.Dziewiecki * +* Module - sensor_interface.v * +* Edited by L.Qin on Oct 15. 2024 * +******************************************************************************/ + + +`timescale 1 ps / 1 ps +module sensor_interface ( + //Clock/reset + input wire clk_clk, // clk.clk + input wire rst_reset, // rst.reset + //Avalon MM slave + input wire [1:0] csr_address, // avalon_slave.address + input wire csr_read, // .read + output wire [31:0] csr_readdata, // .readdata + input wire csr_write, // .write + input wire [31:0] csr_writedata, // .writedata + input wire [3:0] csr_byteenable, // .byteenable + //Avalon ST transmitter + output wire [31:0] data_out_data, // avalon_streaming_source.data + output wire data_out_endofpacket, // .endofpacket + output wire data_out_startofpacket, // .startofpacket + input wire data_out_ready, // .ready + output wire data_out_valid, // .valid + output wire [1:0] data_out_empty, // .empty + //Sensor interface + input wire in_trg, // sensor.in_trg // This is the frame timer + output wire out_adc_clk, // .out_dac_clk + output wire out_adc_cnv, // .out_dac_cnv + input wire [4:0] in_adc_data, // .in_dac_data + output wire out_sensor_rst, // .out_sensor_rst + output wire out_sensor_clk, // .out_sensor_clk + output wire out_sensor_gain, // .out_sensor_gain + //Serial synchro interface + input wire serial_rx, //receive data + output wire serial_tx, //send data + input wire [7:0] ext_input, //SMA etc. + //Debug information + output wire [7:0] status_out, //status bits - same as in reg0_read[15:8] + + output reg int_rst, //the reset for each new run + output reg [7:0] cluster_threshold, //from registers[3][7:0] + output reg [7:0] cluster_size, //from registers[3][15:8] + output reg [7:0] in_algo_threshold //from registers[3][23:16] + ); + + + //Very important globals + reg[31:0] transmit_buffer[162:0]; //Data to send: 3 words header plus sensor data + wire readout_ready; //pulsing this signal causes copying data from frame buffer to transmit buffer and initiating transmission + wire start_transmission; //pulsing this signal causes the Avalon ST link to start transmission + reg[15:0] local_sync_ctr; //local synchronization counter, it increments by one at each frame + wire[8:0] global_sync_ctr; //global synchronization counter, it's simply the received value from serial RX. + wire global_sync_error; //RX error in the global synchronization counter + + //Common generate variables + genvar i; //for generate loops + genvar j; + integer xi; //for normal loops + integer xj; + + // *********************** CSR stuff ************************ + /* + There are 4 32-bit R/W-able registers. They are used for setting up the module and checking its state + Reg0 is a bit different: when read, bits 15-8 (the status byte) are taken directly from device internals, not from register contents. + The bus can be accessed 32-, 16- or 8-bit-wise. + + Register definition + //reg0 + #define SENSOR_REG_COMMAND 0 //8 bits + #define SENSOR_REG_STATUS 1 //8 bits + #define SENSOR_REG_SENSORCLK 2 //8 bits, 6 used divider for producing sensor clock ('4' MHz) + #define SESNOR_REG_ADCCNV 3 //8 bits, 6 used time of conversion pulse in ADC clocks, should be > 500 ns + //reg1 + #define SENSOR_REG_DELAY 4 //16 bits, 12 used reset signal delay in 50 MHz clocks + #define SENSOR_REG_SHUTTER 6 //16 bits, 12 used sensor reset ('shutter') time in sensor clocks + //reg2 + #define SENSOR_REG_SERSPEED 8 //8 bits synchro baudrate, 50 for 1 Mbps + #define SENSOR_REG_HEADER_ANYDATA 9 //8 bits any data transmitted with SMA state (8 bits SMA + 8 bits anydata) + #define SENSOR_REG_HEADER_CMD 10 //16 bits command field of the command header transmitted in packet + //reg3 //configure reg3 17.July.2024 Qin,L + #define SENSOR_REG_CLUSTER_THRESHOLD 12 //8 bits the threshold for cluster locate, range 0~255 + #define SENSOR_REG_CLUSTER_SIZE 13 //8 bits the size for clluster locate, range 0~255 + #define SENSOR_REG_IN_ALGO_THRESHOLD 14 //8 bits the threshold inside Linear Regression, range 0~255 + #define SENSOR_REG_RESERVED 15 //8 bits not used + + Command bitmasks + #define SENSOR_CSR_EN_BITMASK 0x01 //enable operation + #define SENSOR_CSR_GAIN_BITMASK 0x02 //gain selection + #define SENSOR_CSR_ADCK_BITMASK 0x04 //ADC clock divider on/off + #define SENSOR_CSR_RESET_BITMASK 0x08 //Reset all logic //registers[0][3] + + Status bitmasks + #define SENSOR_STATUS_SEND 0x01 //Sending over Avalon-ST + #define SENSOR_STATUS_TRG_WAITING 0x02 //The trigger came and is being delayed now + #define SENSOR_STATUS_RESET_ACTIVE 0x04 //The RESET signal for the sensor is active now + #define SENSOR_STATUS_ADC_ACTIVE 0x08 //The ADC is converting data (signal high over all 64 channels) or just finished and waits for reset high + #define SESNOR_STATUS_ADC_FINISHED 0x10 //The ADC waits for reset high + #define SESNOR_STATUS_TX_ACTIVE 0x20 //Sync port is sending + #define SESNOR_STATUS_RX_ACTIVE 0x40 //Sync port is receiving + + */ + + reg [31:0] registers[3:0]; //main register space + wire [31:0] reg0_read; //reg[0] is read indirectly to include status byt(bits 15-8) + + //read logic + assign reg0_read[7:0] = registers[0][7:0]; // Readback of control bits + assign reg0_read[31:16] = registers[0][31:16]; // Readback of payload size + assign reg0_read[15] = 0; // Unused bits of the status byte + assign csr_readdata = (csr_address==0) ? reg0_read : registers[csr_address]; + + //write logic + generate + for (i = 0; i < 4; i = i+1) + begin : write_registers //Quartus wants labels for 'for' blocks + for (j = 0; j < 4; j = j+1) + begin : write_bytes + always @(posedge clk_clk or posedge rst_reset) + begin + if (rst_reset) + registers[i][8*j+7:8*j] <= 8'd0; + else + if (csr_byteenable[j] && (csr_address == i) && (csr_write)) + registers[i][8*j+7:8*j] <= csr_writedata[8*j+7:8*j]; + end + end + end + endgenerate + + // *********************** Internal reset logic ************************ + /* + The internal reset signal derives from the reset input and reset bit (reg0.3). + It drives all subcomponents but registers (which use simpy the reset input). + This signal is registered to be sure that no glitches from register bank pass. + */ + + //reg int_rst; + + always @(posedge clk_clk) + begin + int_rst <= rst_reset | registers[0][3]; + end + + // *********************** Avalon transmitter ************************ + /* + The transmitter is used to transmit collected sensor data together with sync frame. + It can be later packed into UDP by UDP generator and sent over Ethernet. Or whatever. + The transmitter has 8-bit symbol, 4 symbols per beat. It's backpressurizable and includes packet signals. + The Empty signal is dummy (always zero), as the data is always aligned to 32-bit size. + The transmission starts when the 'start_transmission' signal gets pulsed + */ + + assign data_out_empty = 2'b00; + + reg [1:0] data_out_state; //State of the state machine + localparam DATA_OUT_STATE_IDLE = 0; //waiting for high + localparam DATA_OUT_STATE_SEND = 1; //sending data + localparam DATA_OUT_STATE_LOCK = 2; //waiting for trigger low + + //localparam DATA_OUT_STATE_PEND = 3; //the pending when sending data + + localparam WORDS_TO_SEND = 163; + + //registers to drive output pins of ST interfaces +// reg reg_valid; +// reg [31:0] reg_data; +// reg reg_startofpacket; +// reg reg_endofpacket; + + //Helper stuff + reg [15:0] tx_ctr; //counter of sent data words + + //The state machine + always @(posedge clk_clk or posedge int_rst) + begin + if (int_rst) + begin + data_out_state <= DATA_OUT_STATE_IDLE; + cluster_threshold <= registers[3][7:0]; + cluster_size <= registers[3][15:8]; + in_algo_threshold <= registers[3][23:16]; + end + else + case(data_out_state) + DATA_OUT_STATE_IDLE: + begin + if (start_transmission) + begin + data_out_state <= DATA_OUT_STATE_SEND; + tx_ctr <= 0; + cluster_threshold <= registers[3][7:0]; + cluster_size <= registers[3][15:8]; + in_algo_threshold <= registers[3][23:16]; + end + end + DATA_OUT_STATE_SEND: + begin + if (data_out_ready) + begin + tx_ctr <= tx_ctr + 1'b1; + if (tx_ctr == (WORDS_TO_SEND-1)) + data_out_state <= DATA_OUT_STATE_LOCK; + end + end + DATA_OUT_STATE_LOCK: + begin + if (~start_transmission) + data_out_state <= DATA_OUT_STATE_IDLE; + end + + default: + data_out_state <= DATA_OUT_STATE_IDLE; + endcase + end + + assign data_out_valid = (data_out_state == DATA_OUT_STATE_SEND)? 1'b1: 1'b0; + assign data_out_data = (data_out_state == DATA_OUT_STATE_SEND)? transmit_buffer[tx_ctr]: 32'b0; + assign data_out_startofpacket = (data_out_state == DATA_OUT_STATE_SEND && tx_ctr == 0) ? 1'b1: 1'b0; + assign data_out_endofpacket = (data_out_state == DATA_OUT_STATE_SEND && tx_ctr == (WORDS_TO_SEND-1)) ? 1'b1: 1'b0; + + assign reg0_read[8] = ~(data_out_state == DATA_OUT_STATE_IDLE); //to status register + + // *********************** Detector gain logic ************************ + /* + The gain signal is simply derived from reg0. + */ + + assign out_sensor_gain = registers[0][1]; + + // *********************** Trigger delay logic ************************ + /* + Individual trigger delay settings are needed to synchronize multiple boards. + A 12-bit downcounter allows for delaying incoming trigger's rising edge by up to 4095 50MHz clock cycles, i.e. 81.9 us. + Note: A further delay of one sensor clock will be added in the sensor clock generation logic. + */ + + reg [11:0] trg_delay_ctr; + wire int_trg; + reg [1:0] trg_state; + localparam TRG_STATE_IDLE = 0; //waiting for external trigger + localparam TRG_STATE_DELAY = 1; //downcounting + localparam TRG_STATE_ACTIVE = 2; //internal trigger active + localparam TRG_STATE_LOCK = 3; //waiting for external trigger inactive + + //localparam TRG_DURATION = 4; //duration of the trigger signal + + assign int_trg = (trg_state == TRG_STATE_ACTIVE) ? 1'b1 : 1'b0; + + always @(posedge clk_clk or posedge int_rst) + begin + if (int_rst) + begin + trg_state <= TRG_STATE_LOCK; + end + else + begin + case(trg_state) + TRG_STATE_IDLE: + begin + if (in_trg && registers[0][0]) //react on trigger only if enabled + begin + trg_delay_ctr <= registers[1][11:0]; + trg_state <= TRG_STATE_DELAY; + end + end + TRG_STATE_DELAY: + begin + trg_delay_ctr <= trg_delay_ctr - 1'b1; + if (trg_delay_ctr == 0) + begin + //trg_delay_ctr <= TRG_DURATION-1; + trg_state <= TRG_STATE_ACTIVE; + end + end + TRG_STATE_ACTIVE: + begin + //trg_delay_ctr <= trg_delay_ctr - 1; + //if (trg_delay_ctr == 0) + //begin + trg_state <= TRG_STATE_LOCK; //only one cycle of active int_trg + //end + end + TRG_STATE_LOCK: + begin + if (~in_trg) + trg_state <= TRG_STATE_IDLE; + end + endcase + end + end + + assign reg0_read[9] = ~(trg_state == TRG_STATE_IDLE); //to status register + + // *********************** Sensor clock logic ************************ + /* + The sensor needs a clock of max. 4 MHz, which is generated by this module. + The actual clock speed is configurable by a register with a formula: Fs = Fi/2/(div+1), + where Fs is the sensor clock, Fi is input clock (50 MHz nom.) and div is a divider taken from the register. + A 5-bit downcounter allows for frequencies from 0.39 MHz (div=63) to 12.5 MHz (div=1). + The nominal setting is 6, giving 3.5714285 MHz. + + Important: The sensor clock is synchronized to the rising edge of the (delayed) trigger input, + so that there is a positive slope at exactly one sensor clock period after the trigger. + This positive slope is then used to synchronize integration start signal (sensor reset or shutter). + The synchronization is done so that one of clock states (0 or 1) gets extended, but never shortened. + + Note: 4 MHz is also the top speed accepted by the ADC module. + */ + + reg [5:0] sensor_clk_ctr; + reg [1:0] sensor_clk_state; + + localparam SENSOR_CLK_STATE_LOW = 2'd0; + localparam SENSOR_CLK_STATE_HIGH = 2'd1; + localparam SENSOR_CLK_STATE_LOWAIT = 2'd2; + localparam SENSOR_CLK_STATE_HIWAIT = 2'd3; + + assign out_sensor_clk = sensor_clk_state[0]; + + always @(posedge clk_clk or posedge int_rst) + begin + if (int_rst) + begin + sensor_clk_state <= SENSOR_CLK_STATE_LOW; + sensor_clk_ctr <= registers[0][21:16]; + end + else + begin + case(sensor_clk_state) + SENSOR_CLK_STATE_LOW: + begin + sensor_clk_ctr <= sensor_clk_ctr-1'b1; + if (int_trg) + begin + sensor_clk_ctr <= registers[0][21:16]; + sensor_clk_state <= SENSOR_CLK_STATE_LOWAIT; + end + else if (sensor_clk_ctr == 0) + begin + sensor_clk_ctr <= registers[0][21:16]; + sensor_clk_state <= SENSOR_CLK_STATE_HIGH; + end + end + SENSOR_CLK_STATE_HIGH: + begin + sensor_clk_ctr <= sensor_clk_ctr-1'b1; + if (int_trg) + begin + sensor_clk_ctr <= registers[0][21:16]; + sensor_clk_state <= SENSOR_CLK_STATE_HIWAIT; + end + else if (sensor_clk_ctr == 0) + begin + sensor_clk_ctr <= registers[0][21:16]; + sensor_clk_state <= SENSOR_CLK_STATE_LOW; + end + end + SENSOR_CLK_STATE_LOWAIT: + begin + sensor_clk_ctr <= sensor_clk_ctr-1'b1; + if (sensor_clk_ctr == 0) + begin + sensor_clk_ctr <= registers[0][21:16]; + sensor_clk_state <= SENSOR_CLK_STATE_LOW; + end + end + SENSOR_CLK_STATE_HIWAIT: + begin + sensor_clk_ctr <= sensor_clk_ctr-1'b1; + if (sensor_clk_ctr == 0) + begin + sensor_clk_ctr <= registers[0][21:16]; + sensor_clk_state <= SENSOR_CLK_STATE_LOW; + end + end + endcase + end + end + + // *********************** Sensor reset (shutter) logic ************************ + /* + This block generates a 'reset' (shutter) signal for the sensor. + It defines the integration time and is programmable by means of a register in sensor clock units. + The leading (positive) slope of this signal is synchronized with the first positive slope of the sensor clock after the trigger. + An internal 12-bit downcounter allows for a max. integration time of ca 1.15 ms. It can be further extended by slowing down the sensor clock. + It's user's responsibility to check if the integration period fits into the trigger period. If this requirement is not fulfilled, some triggers will be skipped. + Sorry for this ugly code, but since it works... + + Important remark from sensor's specification: Rise of a RESET pulse must be set outside the video output period. + This must by guaranteed by user by means of proper timing. First video comes 18 cycles after negative slope of sensor reset and is 2 cycles long. + Then 2 cycles pause (here we can come with the positive reset slope), then next video and so on, every 4 cycles. + The minimum duration of reset low is 21 clocks, and 20 clocks for reset high. + Our logic requires that new reset low comes only after all channels are read. + */ + + reg [11:0] sensor_rst_ctr; + reg sensor_rst_state; + + assign out_sensor_rst = sensor_rst_state; + + always @(posedge int_trg or posedge out_sensor_clk or posedge int_rst) + begin + if (int_rst) + begin + sensor_rst_state <= 0; + sensor_rst_ctr <= 0; + end + else if (int_trg) + begin + sensor_rst_ctr <= registers[1][27:16]; + end + else + begin + if (sensor_rst_ctr == 0) + begin + sensor_rst_state <= 0; + end + else + begin + sensor_rst_ctr <= sensor_rst_ctr - 1'b1; + sensor_rst_state <= 1'b1; + end + end + end + + assign reg0_read[10] = sensor_rst_state; //to status register + + // *********************** ADC trigger logic ************************ + /* + This piece produces triggering signals for ADC framework and cares about counting ADC samples. + It doesn't rely on incoming Trig signals, just generates them internally by counting clocks. + + */ + + reg [5:0] adc_current_channel; + reg [2:0] adc_trg_state; + reg [4:0] adc_trg_downctr; + wire int_adc_trg; + wire adc_trg_frame_ready; + + localparam ADC_TRG_STATE_IDLE = 0; //nothing happens, RESET is high or initial state + localparam ADC_TRG_STATE_WAIT = 1; //waiting for the first video + localparam ADC_TRG_STATE_VIDEO1 = 2; //capturing video + localparam ADC_TRG_STATE_VIDEO2 = 3; //second cycle + localparam ADC_TRG_STATE_VIDEO3 = 4; //third cycle + localparam ADC_TRG_STATE_VIDEO4 = 5; //fourth cycle + localparam ADC_TRG_STATE_FINISH = 6; //finished readout, waiting for RESET high to enter idle + localparam ADC_TRG_STATE_INIT = 7; //used only for reset procedure + + localparam ADC_TRG_INITIALWAIT = 5'd17; //initial wait for the first video + localparam ADC_TRG_VIDEOPERIOD = 4; //video output period + + always @(posedge out_sensor_clk or posedge int_rst) + begin + if (int_rst) + begin + adc_current_channel <= 63; + adc_trg_downctr <= 0; + adc_trg_state <= ADC_TRG_STATE_INIT; //will go to IDLE when adc_trg_reset is high + end + else + case(adc_trg_state) + ADC_TRG_STATE_IDLE: + begin + if (~out_sensor_rst) + begin + adc_trg_downctr <= ADC_TRG_INITIALWAIT; + adc_current_channel <= 63; + adc_trg_state <= ADC_TRG_STATE_WAIT; + end + end + ADC_TRG_STATE_WAIT: + begin + adc_trg_downctr <= adc_trg_downctr - 1'b1; + if (adc_trg_downctr == 0) + begin + adc_trg_state <= ADC_TRG_STATE_VIDEO1; + end + end + ADC_TRG_STATE_VIDEO1: + begin + adc_current_channel <= adc_current_channel + 1'b1; + adc_trg_state = ADC_TRG_STATE_VIDEO2; + end + ADC_TRG_STATE_VIDEO2: + begin + adc_trg_state = ADC_TRG_STATE_VIDEO3; + end + ADC_TRG_STATE_VIDEO3: + begin + adc_trg_state = ADC_TRG_STATE_VIDEO4; + end + ADC_TRG_STATE_VIDEO4: + begin + if (adc_current_channel == 63) + adc_trg_state <= ADC_TRG_STATE_FINISH; + else + adc_trg_state = ADC_TRG_STATE_VIDEO1; + end + ADC_TRG_STATE_FINISH, ADC_TRG_STATE_INIT: + begin + if (out_sensor_rst) + adc_trg_state <= ADC_TRG_STATE_IDLE; + end + endcase + end + + //Producing internal trigger for ADC framework (see below) + assign int_adc_trg = (adc_trg_state == ADC_TRG_STATE_VIDEO1) ? 1'b1 : 1'b0; + + assign adc_trg_frame_ready = (adc_trg_state == ADC_TRG_STATE_FINISH) ? 1'b1 : 1'b0; //trigger data collection machine when the frame is ready + + assign reg0_read[11] = ~(adc_trg_state == ADC_TRG_STATE_IDLE); //to status register + assign reg0_read[12] = (adc_trg_state == ADC_TRG_STATE_FINISH); //to status register + + // *********************** ADC logic ************************ + /* + SPI interface for ADCs. Triggers conversion and reads out the data on each incoming int_adc_trg. + The ADC framework and SPI runs with full clock frequency or with half of it, depending on register setting. + The ADC works in the 'CS Mode, 3-Wire Without Busy Indicator Serial Interface'. + The CNV signal length is defined by register and expressed in ADC clocks. + It's user's responsibility to ensure that the CNV pulse is longer than 500 ns (required by ADC spec). + The ADC clock can be selected to be either full or half system clock. + */ + + //Clock divider and selection + reg adc_halfclock; + wire int_adc_clk; + always @(posedge clk_clk or posedge int_rst) + begin + if (int_rst) + adc_halfclock <= 0; + else + adc_halfclock <= ~adc_halfclock; + end + assign int_adc_clk = registers[0][2] ? adc_halfclock : clk_clk; + + //The main state machine + reg [2:0] adc_state; + reg [5:0] adc_downctr; + + localparam ADC_STATE_IDLE = 0; //waiting for conversion + localparam ADC_STATE_CNV = 1; //conversion on-going + localparam ADC_STATE_STARTREAD = 2; //prepare to read, conversion finished + localparam ADC_STATE_READ = 3; //reading data + localparam ADC_STATE_FINISH = 4; //copy data to global buffer + localparam ADC_STATE_FINISHED = 5; //wait until trigger low, then go to idle + + always @(posedge int_adc_clk or posedge int_rst) + begin + if (int_rst) + begin + adc_downctr <= 0; + adc_state <= ADC_STATE_IDLE; + end + else + begin + case(adc_state) + ADC_STATE_IDLE: + begin + adc_downctr <= registers[0][29:24]; + if (int_adc_trg) + adc_state <= ADC_STATE_CNV; + end + ADC_STATE_CNV: + begin + adc_downctr <= adc_downctr - 1'b1; + if (adc_downctr == 0) + adc_state <= ADC_STATE_STARTREAD; + end + ADC_STATE_STARTREAD: + begin + adc_downctr <= 15; + adc_state <= ADC_STATE_READ; + end + ADC_STATE_READ: + begin + adc_downctr <= adc_downctr - 1'b1; + if (adc_downctr == 0) + adc_state <= ADC_STATE_FINISH; + end + ADC_STATE_FINISH: + begin + adc_state <= ADC_STATE_FINISHED; + end + ADC_STATE_FINISHED: + begin + if (!int_adc_trg) + adc_state <= ADC_STATE_IDLE; + end + default + begin + adc_state <= ADC_STATE_IDLE; + end + endcase + end + end + + //Reading data - this happens on the negative slope of clock! + reg [15:0] adc_buffer[4:0]; //A shift register for SPI acquisition + reg [15:0] frame_buffer[319:0]; //The 'big buffer' for whole frame + + always @(negedge int_adc_clk or posedge int_rst) + begin + if (int_rst) + begin + for (xi = 0; xi < 5; xi = xi+1) + adc_buffer[xi] <= 0; + end + else + begin + case(adc_state) + ADC_STATE_STARTREAD: + begin + for (xi = 0; xi < 5; xi = xi+1) + adc_buffer[xi] <= 0; + end + ADC_STATE_READ: + begin + for (xi = 0; xi < 5; xi = xi+1) + begin + adc_buffer[xi][15:1] <= adc_buffer[xi][14:0]; + adc_buffer[xi][0] <= in_adc_data[xi]; + end + end + ADC_STATE_FINISH: + begin + for (xi = 0; xi < 5; xi = xi+1) + frame_buffer[64*xi + adc_current_channel] <= adc_buffer[xi]; + end + endcase + end + end + + + assign out_adc_cnv = (adc_state == ADC_STATE_CNV) ? 1'b1 : 1'b0; + assign out_adc_clk = (adc_state == ADC_STATE_READ) ? int_adc_clk : 1'b1; + + + // *********************** Putting data together and letting transmit it ************************ + /* + The data is sent together with a 3-word header (6 16-bit numbers), + which is compatible with v.1 head structures: + typedef struct + { + unsigned short marker; //must be 0x5555 + unsigned short command; + unsigned short length; + } command_header; + typedef struct + { + //unsigned short channel_id; + unsigned short local_ctr; + unsigned short global_ctr; + unsigned short sma_state; + } sync_frame; + + */ + + reg [2:0] merger_state; + + localparam MERGER_STATE_IDLE = 0; //waiting for ADC + localparam MERGER_STATE_COLLECT = 1; //collect frame information + localparam MERGER_STATE_SEND = 2; //run Avalon sender + localparam MERGER_STATE_FINISH = 3; //roll to idle + + always @(posedge clk_clk or posedge int_rst) + begin + if (int_rst) + begin + merger_state <= ADC_STATE_IDLE; + for (xi= 0; xi < 163; xi = xi+1) + transmit_buffer[xi] <= 0; + end + else + begin + case(merger_state) + MERGER_STATE_IDLE: + begin + if (adc_trg_frame_ready) + merger_state <= MERGER_STATE_COLLECT; + end + MERGER_STATE_COLLECT: + begin + transmit_buffer[0][31:16] <= 16'h5555; //command_header.marker = 0x5555 + transmit_buffer[0][15:0] <= registers[2][31:16]; //command_header.command = reg2.31-16 + transmit_buffer[1][31:16] <= 16'd323; //16'd652; //command_header.length = 320 samples + 6 sync bytes = 323 * 16bit //16'h143 + transmit_buffer[1][15:0] <= local_sync_ctr[15:0]; //sync_frame.local_ctr + transmit_buffer[2][24:16] <= global_sync_ctr; //sync_frame.global_ctr + transmit_buffer[2][25] <= global_sync_error; + transmit_buffer[2][31:26] <= 0; + transmit_buffer[2][7:0] <= ext_input; //sync_frame.sma_state[7:0] = ext_input + transmit_buffer[2][15:8] <= registers[2][15:8]; //sync_frame.sma_state[15:8] = reg2.15-8 + for (xi = 0; xi < 160; xi = xi+1) + begin + //transmit_buffer[xi+3][15:0] <= frame_buffer[2*xi][15:0]; //ADC data + //transmit_buffer[xi+3][31:16] <= frame_buffer[2*xi+1][15:0]; + transmit_buffer[xi+3][31:16] <= frame_buffer[2*xi][15:0]; //ADC data //CHANGED 26.11.2019 + transmit_buffer[xi+3][15:0] <= frame_buffer[2*xi+1][15:0]; + end + merger_state <= MERGER_STATE_SEND; + + end + MERGER_STATE_SEND: + begin + merger_state <= MERGER_STATE_FINISH; + end + MERGER_STATE_FINISH: + begin + if (~adc_trg_frame_ready) + merger_state <= MERGER_STATE_IDLE; + end + endcase + end + end + + //Generate Avalon trigger signal + assign start_transmission = (merger_state == MERGER_STATE_SEND) ? 1'b1 : 1'b0; + + // *********************** Synchro counter update ************************ + /* + Just increment sunchronization counter at every trigger. + The counter is reset by int_reset. + */ + + always @(posedge clk_clk or posedge int_rst) + begin + if (int_rst) + begin + local_sync_ctr <= 0; + end + else + begin + if (int_trg) + local_sync_ctr <= local_sync_ctr + 1'b1; + end + end + + + + // *********************** Synchronization serial ports ************************ + /* + There is one TX and one RX module. + The TX is getting triggered by int_trg (same as for the main readout framework). + It sends 9 LSBs of the local synchro counter with programmed baudrate. + The default baudrate is 1 Mbps, which needs a setting of 50 for fclk=50MHz. + The RX puts freshly received data into global_sync_ctr. It does not need any triggering. + */ + + wire tx_idle; + wire rx_idle; + assign reg0_read[13] = ~tx_idle; + assign reg0_read[14] = ~rx_idle; + + serial_tx synchro_tx ( + .clk (clk_clk), // full-speed clock + .rst (int_rst), // reset + .data (local_sync_ctr[8:0]), // data to send + .clk_divisor (registers[2][7:0]), // defines baudrate + .trigger (start_transmission), // pulse to start transmission - just AFTER collecting data from sensors + .tx (serial_tx), // tx serial connection + .idle (tx_idle) // 1 if sender in idle state + ); + + serial_rx synchro_rx( + .clk (clk_clk), // full-speed clock + .rst (int_rst), // reset + .clk_divisor (registers[2][7:0]), // defines baudrate + .rx (serial_rx), // rx serial connection + .newdata (), // pulses for new data received + .data (global_sync_ctr), // data received + .error (global_sync_error), // bad start or stop bit + .idle (rx_idle) // 1 if receiver in idle state + ); + + // *********************** Status output ************************ + /* + The status of the module (== reg0_read[15:8]) is available at the output status bus. + It can be then routed to a scope or whatever for debugging + */ + + assign status_out[7:0] = reg0_read[15:8]; + + +endmodule diff --git a/FPGA_firmware/sensor_algo_qsys/sensor_recon_hw.tcl b/FPGA_firmware/sensor_algo_qsys/sensor_recon_hw.tcl new file mode 100644 index 0000000..9f75448 --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/sensor_recon_hw.tcl @@ -0,0 +1,246 @@ +# TCL File Generated by Component Editor 19.1 +# Mon Jul 29 16:45:07 CEST 2024 +# DO NOT MODIFY + + +# +# sensor_recon "sensor_recon_rms_cali" v1 +# Qin,Liqing 17.July,2024 2024.07.29.16:45:07 +# +# + +# +# request TCL package from ACDS 16.1 +# +package require -exact qsys 16.1 + + +# +# module sensor_recon +# +set_module_property DESCRIPTION "" +set_module_property NAME sensor_recon +set_module_property VERSION 1 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property AUTHOR "Qin,Liqing 17.July,2024" +set_module_property DISPLAY_NAME sensor_recon_rms_cali +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL sensor_algo +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file rms.sv SYSTEM_VERILOG PATH rms.sv +add_fileset_file stl2sts.v VERILOG PATH stl2sts.v +add_fileset_file calibration.v VERILOG PATH calibration.v +add_fileset_file algo_top_cl_cali_rms.v VERILOG PATH algo_top_cl_cali_rms.v +add_fileset_file sensor_interface.v VERILOG PATH sensor_interface.v +add_fileset_file serial_rx.v VERILOG PATH serial_rx.v +add_fileset_file serial_tx.v VERILOG PATH serial_tx.v +add_fileset_file sensor_algo.v VERILOG PATH sensor_algo.v TOP_LEVEL_FILE +add_fileset_file bkg_subtraction_pipe.v VERILOG PATH bkg_subtraction_pipe.v +add_fileset_file cluster_locate.sv SYSTEM_VERILOG PATH cluster_locate.sv +add_fileset_file data_caled_ram.v VERILOG PATH data_caled_ram.v +add_fileset_file st_splitter16.v VERILOG PATH q_sys/synthesis/st_splitter16.v +add_fileset_file altera_avalon_st_splitter.sv SYSTEM_VERILOG PATH q_sys/synthesis/altera_avalon_st_splitter.sv +add_fileset_file div.v VERILOG PATH div.v +add_fileset_file sqrt.v VERILOG PATH sqrt.v +add_fileset_file ram4bkg.v VERILOG PATH ram4bkg.v + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point csr +# +add_interface csr avalon end +set_interface_property csr addressUnits WORDS +set_interface_property csr associatedClock clk +set_interface_property csr associatedReset rst +set_interface_property csr bitsPerSymbol 8 +set_interface_property csr burstOnBurstBoundariesOnly false +set_interface_property csr burstcountUnits WORDS +set_interface_property csr explicitAddressSpan 0 +set_interface_property csr holdTime 0 +set_interface_property csr linewrapBursts false +set_interface_property csr maximumPendingReadTransactions 0 +set_interface_property csr maximumPendingWriteTransactions 0 +set_interface_property csr readLatency 0 +set_interface_property csr readWaitTime 1 +set_interface_property csr setupTime 0 +set_interface_property csr timingUnits Cycles +set_interface_property csr writeWaitTime 0 +set_interface_property csr ENABLED true +set_interface_property csr EXPORT_OF "" +set_interface_property csr PORT_NAME_MAP "" +set_interface_property csr CMSIS_SVD_VARIABLES "" +set_interface_property csr SVD_ADDRESS_GROUP "" + +add_interface_port csr csr_address address Input 2 +add_interface_port csr csr_read read Input 1 +add_interface_port csr csr_readdata readdata Output 32 +add_interface_port csr csr_write write Input 1 +add_interface_port csr csr_writedata writedata Input 32 +add_interface_port csr csr_byteenable byteenable Input 4 +set_interface_assignment csr embeddedsw.configuration.isFlash 0 +set_interface_assignment csr embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment csr embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment csr embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point data_out +# +add_interface data_out avalon_streaming start +set_interface_property data_out associatedClock clk +set_interface_property data_out associatedReset rst +set_interface_property data_out dataBitsPerSymbol 8 +set_interface_property data_out errorDescriptor "" +set_interface_property data_out firstSymbolInHighOrderBits true +set_interface_property data_out maxChannel 0 +set_interface_property data_out readyLatency 0 +set_interface_property data_out ENABLED true +set_interface_property data_out EXPORT_OF "" +set_interface_property data_out PORT_NAME_MAP "" +set_interface_property data_out CMSIS_SVD_VARIABLES "" +set_interface_property data_out SVD_ADDRESS_GROUP "" + +add_interface_port data_out data_out_endofpacket endofpacket Output 1 +add_interface_port data_out data_out_data data Output 32 +add_interface_port data_out data_out_empty empty Output 2 +add_interface_port data_out data_out_ready ready Input 1 +add_interface_port data_out data_out_startofpacket startofpacket Output 1 +add_interface_port data_out data_out_valid valid Output 1 + + +# +# connection point clk +# +add_interface clk clock end +set_interface_property clk clockRate 0 +set_interface_property clk ENABLED true +set_interface_property clk EXPORT_OF "" +set_interface_property clk PORT_NAME_MAP "" +set_interface_property clk CMSIS_SVD_VARIABLES "" +set_interface_property clk SVD_ADDRESS_GROUP "" + +add_interface_port clk clk_clk clk Input 1 + + +# +# connection point rst +# +add_interface rst reset end +set_interface_property rst associatedClock clk +set_interface_property rst synchronousEdges DEASSERT +set_interface_property rst ENABLED true +set_interface_property rst EXPORT_OF "" +set_interface_property rst PORT_NAME_MAP "" +set_interface_property rst CMSIS_SVD_VARIABLES "" +set_interface_property rst SVD_ADDRESS_GROUP "" + +add_interface_port rst rst_reset reset Input 1 + + +# +# connection point sensor +# +add_interface sensor conduit end +set_interface_property sensor associatedClock clk +set_interface_property sensor associatedReset "" +set_interface_property sensor ENABLED true +set_interface_property sensor EXPORT_OF "" +set_interface_property sensor PORT_NAME_MAP "" +set_interface_property sensor CMSIS_SVD_VARIABLES "" +set_interface_property sensor SVD_ADDRESS_GROUP "" + +add_interface_port sensor in_adc_data in_adc_data Input 5 +add_interface_port sensor in_trg in_trg Input 1 +add_interface_port sensor out_adc_clk out_adc_clk Output 1 +add_interface_port sensor out_adc_cnv out_adc_cnv Output 1 +add_interface_port sensor out_sensor_clk out_sensor_clk Output 1 +add_interface_port sensor out_sensor_gain out_sensor_gain Output 1 +add_interface_port sensor out_sensor_rst out_sensor_rst Output 1 + + +# +# connection point status_out +# +add_interface status_out conduit end +set_interface_property status_out associatedClock clk +set_interface_property status_out associatedReset "" +set_interface_property status_out ENABLED true +set_interface_property status_out EXPORT_OF "" +set_interface_property status_out PORT_NAME_MAP "" +set_interface_property status_out CMSIS_SVD_VARIABLES "" +set_interface_property status_out SVD_ADDRESS_GROUP "" + +add_interface_port status_out status_out status_out Output 8 + + +# +# connection point synchro +# +add_interface synchro conduit end +set_interface_property synchro associatedClock clk +set_interface_property synchro associatedReset "" +set_interface_property synchro ENABLED true +set_interface_property synchro EXPORT_OF "" +set_interface_property synchro PORT_NAME_MAP "" +set_interface_property synchro CMSIS_SVD_VARIABLES "" +set_interface_property synchro SVD_ADDRESS_GROUP "" + +add_interface_port synchro ext_input ext_input Input 8 +add_interface_port synchro serial_rx serial_rx Input 1 +add_interface_port synchro serial_tx serial_tx Output 1 + + +# +# connection point calibration_ram_interface +# +add_interface calibration_ram_interface avalon start +set_interface_property calibration_ram_interface addressUnits WORDS +set_interface_property calibration_ram_interface associatedClock clk +set_interface_property calibration_ram_interface associatedReset rst +set_interface_property calibration_ram_interface bitsPerSymbol 8 +set_interface_property calibration_ram_interface burstOnBurstBoundariesOnly false +set_interface_property calibration_ram_interface burstcountUnits WORDS +set_interface_property calibration_ram_interface doStreamReads false +set_interface_property calibration_ram_interface doStreamWrites false +set_interface_property calibration_ram_interface holdTime 0 +set_interface_property calibration_ram_interface linewrapBursts false +set_interface_property calibration_ram_interface maximumPendingReadTransactions 0 +set_interface_property calibration_ram_interface maximumPendingWriteTransactions 0 +set_interface_property calibration_ram_interface readLatency 0 +set_interface_property calibration_ram_interface readWaitTime 1 +set_interface_property calibration_ram_interface setupTime 0 +set_interface_property calibration_ram_interface timingUnits Cycles +set_interface_property calibration_ram_interface writeWaitTime 0 +set_interface_property calibration_ram_interface ENABLED true +set_interface_property calibration_ram_interface EXPORT_OF "" +set_interface_property calibration_ram_interface PORT_NAME_MAP "" +set_interface_property calibration_ram_interface CMSIS_SVD_VARIABLES "" +set_interface_property calibration_ram_interface SVD_ADDRESS_GROUP "" + +add_interface_port calibration_ram_interface address address Output 9 +add_interface_port calibration_ram_interface clken read Output 1 +add_interface_port calibration_ram_interface cali_fac readdata Input 16 +add_interface_port calibration_ram_interface waitrequest waitrequest Input 1 + diff --git a/FPGA_firmware/sensor_algo_qsys/serial_rx.v b/FPGA_firmware/sensor_algo_qsys/serial_rx.v new file mode 100644 index 0000000..cc1f14d --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/serial_rx.v @@ -0,0 +1,84 @@ +// 9-bit Serial port receiver +// It's very simple, just single sample halfway of each bit. +// If start bit is not zero or stop bit is not one, an error will be signaled. +// In general, this module is prone to glitches in signal. First of all, any glitch > Tclk will trigger the reception process. +// RX is high on idle. +// Baud rate is programmable via clk_divisor +// clk_divisor ids internally divided by 2 to get in the middle of bit, so need to be at least 2. + +`timescale 100 ps / 100 ps +module serial_rx ( + input wire clk, // full-speed clock + input wire rst, // reset + input wire [7:0] clk_divisor, // defines baudrate + input wire rx, // rx serial connection + output wire newdata, // pulses for new data received + output wire [8:0] data, // data to send + output wire error, // bad start or stop bit + output wire idle // 1 if receiver in idle state + ); + + reg [1:0] state; //State of the state machine + localparam STATE_IDLE = 0; //waiting for enable + localparam STATE_DATA = 1; //sending data + localparam STATE_FINISH = 2; //finished + + reg [4:0] rx_ctr; //counter of received data words + reg [7:0] downctr; //counter to generate baudrate + reg [10:0] buffer; //internal latch/shift register with start and stop bit + reg [8:0] reg_data; //latched received data + reg reg_error; //latched error + + //The state machine + always @(posedge clk or posedge rst) + begin + if (rst) + begin + state <= STATE_IDLE; + reg_data <= 0; + reg_error <= 0; + end + else + case(state) + STATE_IDLE: + begin + if (~rx) + begin + state <= STATE_DATA; + rx_ctr <= 10; + downctr[6:0]<= clk_divisor[7:1]; //wait half a bit + downctr[7] <= 0; + buffer <= 0; + end + end + STATE_DATA: + begin + downctr = downctr - 1; + if (downctr == 0) + begin + downctr <= clk_divisor; + rx_ctr <= rx_ctr - 1; + buffer[9:0] <= buffer[10:1]; + buffer[10] <= rx; + if (rx_ctr == 0) + state <= STATE_FINISH; + end + end + STATE_FINISH: + begin + reg_data[8:0] <= buffer[9:1]; + reg_error <= buffer[0] | ~buffer[10]; //high start or low stop bit + state <= STATE_IDLE; + end + default: + state <= STATE_IDLE; + endcase + end + + //assignments + assign idle = (state == STATE_IDLE) ? 1 : 0; + assign data = reg_data; + assign error = reg_error; + + +endmodule diff --git a/FPGA_firmware/sensor_algo_qsys/serial_tx.v b/FPGA_firmware/sensor_algo_qsys/serial_tx.v new file mode 100644 index 0000000..ab1b607 --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/serial_tx.v @@ -0,0 +1,115 @@ +// 9-bit Serial port transmitter +// TX is high on idle. +// Baud rate is programmable via clk_divisor + +`timescale 100 ps / 100 ps +module serial_tx ( + input wire clk, // full-speed clock + input wire rst, // reset + input wire [8:0] data, // data to send + input wire [7:0] clk_divisor, // defines baudrate + input wire trigger, // pulse to start transmission + output wire tx, // tx serial connection + output wire idle // 1 if sender in idle state + + ); + + reg [2:0] state; //State of the state machine + localparam STATE_IDLE = 0; //waiting for enable + localparam STATE_STARTBIT = 1; //sending start bit + localparam STATE_DATA = 2; //sending data + localparam STATE_STOPBIT = 3; //sending stop bit + localparam STATE_FINISH = 4; //finished + + reg [4:0] tx_ctr; //counter of sent data words + reg [7:0] downctr; //counter to generate baudrate + reg [8:0] buffer; //internal latch/shift register + reg reg_tx; + + //The state machine + always @(posedge clk or posedge rst) + begin + if (rst) + state <= STATE_FINISH; + else + case(state) + STATE_IDLE: + begin + if (trigger) + begin + state <= STATE_STARTBIT; + tx_ctr <= 8; + buffer <= data; + downctr <= clk_divisor; + end + end + STATE_STARTBIT: + begin + downctr = downctr - 1; + if (downctr == 0) + begin + downctr <= clk_divisor; + state <= STATE_DATA; + end + + end + STATE_DATA: + begin + downctr = downctr - 1; + if (downctr == 0) + begin + downctr <= clk_divisor; + tx_ctr <= tx_ctr - 1; + buffer[7:0] <= buffer[8:1]; + buffer[8] <= 0; + if (tx_ctr == 0) + state <= STATE_STOPBIT; + end + end + STATE_STOPBIT: + begin + downctr = downctr - 1; + if (downctr == 0) + begin + downctr <= clk_divisor; + state <= STATE_FINISH; + end + + end + STATE_FINISH: + begin + if (~trigger) + state <= STATE_IDLE; + end + default: + state <= STATE_FINISH; + endcase + end + + //tx assignment + always @( * ) + begin + if (rst) + reg_tx = 1; + else + case(state) + STATE_IDLE: + reg_tx = 1; + STATE_STARTBIT: + reg_tx = 0; + STATE_DATA: + reg_tx = buffer[0]; + STATE_STOPBIT: + reg_tx = 1; + STATE_FINISH: + reg_tx = 1; + default: + reg_tx = 1; + endcase + end + assign tx = reg_tx; + + //idle assignment + assign idle = (state == STATE_IDLE) ? 1 : 0; + +endmodule diff --git a/FPGA_firmware/sensor_algo_qsys/sqrt.v b/FPGA_firmware/sensor_algo_qsys/sqrt.v new file mode 100644 index 0000000..a3a89bc --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/sqrt.v @@ -0,0 +1,104 @@ +// megafunction wizard: %ALTSQRT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTSQRT + +// ============================================================ +// File Name: sqrt.v +// Megafunction Name(s): +// ALTSQRT +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 19.1.0 Build 670 09/22/2019 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2019 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module sqrt ( + clk, + ena, + radical, + q, + remainder); + + input clk; + input ena; + input [25:0] radical; + output [12:0] q; + output [13:0] remainder; + + wire [12:0] sub_wire0; + wire [13:0] sub_wire1; + wire [12:0] q = sub_wire0[12:0]; + wire [13:0] remainder = sub_wire1[13:0]; + + altsqrt ALTSQRT_component ( + .clk (clk), + .ena (ena), + .radical (radical), + .q (sub_wire0), + .remainder (sub_wire1) + // synopsys translate_off + , + .aclr () + // synopsys translate_on + ); + defparam + ALTSQRT_component.pipeline = 13, + ALTSQRT_component.q_port_width = 13, + ALTSQRT_component.r_port_width = 14, + ALTSQRT_component.width = 26; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: PIPELINE NUMERIC "13" +// Retrieval info: CONSTANT: Q_PORT_WIDTH NUMERIC "13" +// Retrieval info: CONSTANT: R_PORT_WIDTH NUMERIC "14" +// Retrieval info: CONSTANT: WIDTH NUMERIC "26" +// Retrieval info: USED_PORT: clk 0 0 0 0 INPUT NODEFVAL "clk" +// Retrieval info: USED_PORT: ena 0 0 0 0 INPUT NODEFVAL "ena" +// Retrieval info: USED_PORT: q 0 0 13 0 OUTPUT NODEFVAL "q[12..0]" +// Retrieval info: USED_PORT: radical 0 0 26 0 INPUT NODEFVAL "radical[25..0]" +// Retrieval info: USED_PORT: remainder 0 0 14 0 OUTPUT NODEFVAL "remainder[13..0]" +// Retrieval info: CONNECT: @clk 0 0 0 0 clk 0 0 0 0 +// Retrieval info: CONNECT: @ena 0 0 0 0 ena 0 0 0 0 +// Retrieval info: CONNECT: @radical 0 0 26 0 radical 0 0 26 0 +// Retrieval info: CONNECT: q 0 0 13 0 @q 0 0 13 0 +// Retrieval info: CONNECT: remainder 0 0 14 0 @remainder 0 0 14 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_firmware/sensor_algo_qsys/sqrt_bb.v b/FPGA_firmware/sensor_algo_qsys/sqrt_bb.v new file mode 100644 index 0000000..8ef6720 --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/sqrt_bb.v @@ -0,0 +1,76 @@ +// megafunction wizard: %ALTSQRT%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTSQRT + +// ============================================================ +// File Name: sqrt.v +// Megafunction Name(s): +// ALTSQRT +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 19.1.0 Build 670 09/22/2019 SJ Lite Edition +// ************************************************************ + +//Copyright (C) 2019 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. + +module sqrt ( + clk, + ena, + radical, + q, + remainder); + + input clk; + input ena; + input [25:0] radical; + output [12:0] q; + output [13:0] remainder; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: PIPELINE NUMERIC "13" +// Retrieval info: CONSTANT: Q_PORT_WIDTH NUMERIC "13" +// Retrieval info: CONSTANT: R_PORT_WIDTH NUMERIC "14" +// Retrieval info: CONSTANT: WIDTH NUMERIC "26" +// Retrieval info: USED_PORT: clk 0 0 0 0 INPUT NODEFVAL "clk" +// Retrieval info: USED_PORT: ena 0 0 0 0 INPUT NODEFVAL "ena" +// Retrieval info: USED_PORT: q 0 0 13 0 OUTPUT NODEFVAL "q[12..0]" +// Retrieval info: USED_PORT: radical 0 0 26 0 INPUT NODEFVAL "radical[25..0]" +// Retrieval info: USED_PORT: remainder 0 0 14 0 OUTPUT NODEFVAL "remainder[13..0]" +// Retrieval info: CONNECT: @clk 0 0 0 0 clk 0 0 0 0 +// Retrieval info: CONNECT: @ena 0 0 0 0 ena 0 0 0 0 +// Retrieval info: CONNECT: @radical 0 0 26 0 radical 0 0 26 0 +// Retrieval info: CONNECT: q 0 0 13 0 @q 0 0 13 0 +// Retrieval info: CONNECT: remainder 0 0 14 0 @remainder 0 0 14 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_firmware/sensor_algo_qsys/sqrt_inst.v b/FPGA_firmware/sensor_algo_qsys/sqrt_inst.v new file mode 100644 index 0000000..f88c492 --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/sqrt_inst.v @@ -0,0 +1,7 @@ +sqrt sqrt_inst ( + .clk ( clk_sig ), + .ena ( ena_sig ), + .radical ( radical_sig ), + .q ( q_sig ), + .remainder ( remainder_sig ) + ); diff --git a/FPGA_firmware/sensor_algo_qsys/st2mm.v b/FPGA_firmware/sensor_algo_qsys/st2mm.v new file mode 100644 index 0000000..ff5ff6f --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/st2mm.v @@ -0,0 +1,86 @@ +//a module bridge the avalon streaming interface and avalon memory map interface +//collect data from interface and write to RAM + +//32 2; OR 16 1 + +//tested by st2mm_tb.v +module st2mm #(parameter BITSIZE = 32, EMPTY_SIZE = 2)( + + //clock and reset + input wire clk, + input wire rst, + + //avalon ST(Streaming) sink: 0 readlatency and 0 readallowence + input wire [BITSIZE-1:0] data_in_data, // st.data + output wire data_in_ready, // .ready + input wire data_in_valid, // .valid + input wire [EMPTY_SIZE-1:0] data_in_empty, // .empty + input wire data_in_endofpacket, // .endofpacket + input wire data_in_startofpacket, // .startofpacket + + //avalon MM(Memory Mapped) source writelatency 0; readlatency 1 but no read logic here + output wire [8:0] mm_address, + output wire mm_chipselect, // only for write + output wire mm_write, + output wire [BITSIZE-1:0] mm_writedata, + input wire mm_waitrequest_n //it equals to mm_ready.. + + //output wire mm_clken, //only for write write enable + input wire [BITSIZE-1:0]mm_readdate, //do not read + +); + + reg[1:0] state; + localparam STATE_IDLE = 2'd0; //waiting for startofpacket + localparam STATE_WRITE = 2'd1; //write to mm + localparam STATE_LOCK = 2'd3; //Finish writing + + reg[8:0] ctr; // count data and the address for MM + localparam CTR_ZERO = 9'd0; + assign mm_address = ctr; + assign mm_writedata = data_in_data; + assign mm_write = (state == STATE_WRITE)? 1'b1: 1'b0; + + assign mm_chipselect = (state == STATE_WRITE && data_in_valid)? 1'b1: 1'b0; + //assign mm_clken = (state == STATE_WRITE && data_in_valid)? 1'b1: 1'b0; + assign data_in_ready = (state == STATE_WRITE)? mm_waitrequest_n: 1'b0; + + + always @ (posedge clk or posedge rst) + begin + if (rst) + begin + state <= STATE_IDLE; + ctr <= CTR_ZERO; + end + else case(state) + STATE_IDLE: + begin + ctr <= CTR_ZERO; + if (data_in_startofpacket) + state <= STATE_WRITE; + end + STATE_WRITE: + begin + if (data_in_valid && mm_waitrequest_n) + begin + ctr <= ctr + 1'b1; + if (data_in_endofpacket) + state <= STATE_LOCK; + ctr <= CTR_ZERO; + end + end + STATE_LOCK: + begin + state <= STATE_IDLE; + ctr <= CTR_ZERO; + end + default: + state <= STATE_IDLE; + endcase + end + + + +endmodule + diff --git a/FPGA_firmware/sensor_algo_qsys/st2mm_l2s.v b/FPGA_firmware/sensor_algo_qsys/st2mm_l2s.v new file mode 100644 index 0000000..0e2264b --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/st2mm_l2s.v @@ -0,0 +1,80 @@ +//a module bridge the avalon streaming interface and avalon memory map interface +//collect data from interface and write to RAM +//long to short +//32 bits to 16 bits + + +module st2mm_l2s( + + //clock and reset + input wire clk, + input wire rst, + + //avalon ST(Streaming) sink: 0 readlatency and 0 readallowence + input wire [31:0] st_data, // st.data + output wire st_ready, // .ready + input wire st_valid, // .valid + input wire [1:0] st_empty, // .empty + input wire st_endofpacket, // .endofpacket + input wire st_startofpacket, // .startofpacket + + //avalon MM(Memory Mapped) source + output wire [8:0] mm_address, + output wire mm_chipselect, // only for write + output wire mm_clken, //only for write; write enable + input wire [31:0]mm_readdate, //do not read + output wire mm_write, + output wire [8:0] mm_writedata + +); + + reg[1:0] state; + localparam STATE_IDLE = 2'd0; //waiting for startofpacket + localparam STATE_WRITE = 2'd1; //write to mm + localparam STATE_LOCK = 2'd3; //Finish writing + + reg[8:0] ctr; // count data and the address for MM + localparam CTR_ZERO = 9'd0; + assign mm_address = ctr; + assign mm_writedata = st_data; + + assign mm_chipselect = (state == STATE_WRITE && st_valid)? 1'b1: 1'b0; + assign mm_clken = (state == STATE_WRITE && st_valid)? 1'b1: 1'b0; + assign st_ready = (state == STATE_WRITE)? 1'b1: 1'b0; + + + always @ (posedge clk or posedge rst) + begin + if (rst) + begin + state <= STATE_IDLE; + ctr <= CTR_ZERO; + end + else case(state) + STATE_IDLE: + begin + ctr <= CTR_ZERO; + if (st_startofpacket) + state <= STATE_WRITE; + end + STATE_WRITE: + begin + if (st_valid) + ctr <= ctr + 1'b1; + if (st_endofpacket) + state <= STATE_LOCK; + end + STATE_LOCK: + begin + state <= STATE_IDLE; + ctr <= CTR_ZERO; + end + default: + state <= STATE_IDLE; + endcase + end + + + +endmodule + diff --git a/FPGA_firmware/sensor_algo_qsys/stl2sts.v b/FPGA_firmware/sensor_algo_qsys/stl2sts.v new file mode 100644 index 0000000..dd286d7 --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/stl2sts.v @@ -0,0 +1,100 @@ +/****************************************************************************** +* Copyright * +* Scintillating Fibre Beam Profile Monitor Software by Michal Dziewiecki, * +* Blake Leverington and Liqing Qin is licensed under CC BY 4.0 * +* https://creativecommons.org/licenses/by/4.0/ * +* funded by the Deutsche Forschungsgemeinschaft * +* (DFG, German Research Foundation) Projektnummer 419255448 * +* Project Leader: B.Leverington * +******************************************************************************* +* Create Date - Oct 15th. 2024 * +* Author: L.Qin * +* Module - stl2sts.v * +******************************************************************************/ +/* +Created by Lq.Qin on Oct 15th. 2024 +*/ +//a module bridge the avalon streaming interfaces with data length from 32 bit to 16 bit +//long to short +//32 bits to 16 bits [31:16] streaming out first and then [15:0] +//ST long to ST short + + + +//tested by stl2sts_tb.v +module stl2sts( + + //clock and reset + input wire clk, + input wire rst, + + //avalon ST(Streaming) sink: 0 readlatency and 0 readallowence + input wire [31:0] data_in_data, // st.data + output wire data_in_ready, // .ready + input wire data_in_valid, // .valid + input wire [1:0] data_in_empty, // .empty + input wire data_in_endofpacket, // .endofpacket + input wire data_in_startofpacket, // .startofpacket + + //avalon ST(Streaming) source: 0 readlatency and 0 readallowence + output wire [15:0] data_out_data, // st.data + input wire data_out_ready, // .ready + output wire data_out_valid, // .valid + output wire data_out_empty, // .empty + output wire data_out_endofpacket, // .endofpacket + output wire data_out_startofpacket // .startofpacket +); + + reg[1:0] state; + localparam STATE_IDLE = 2'd0; //waiting for startofpacket + localparam STATE1 = 2'd1; //streaming [31:16] + localparam STATE2 = 2'd3; //streaming [15:0] + localparam STATE_LOCK = 2'd2; //Finishing streaming + + assign data_in_ready = (state == STATE2 && data_out_ready)? 1'b1:1'b0; + + assign data_out_data = (state == STATE1)? data_in_data[31:16]:(state== STATE2)? data_in_data[15:0]: 16'b0; + assign data_out_valid = (state == STATE1 || state == STATE2)?data_in_valid:1'b0; + assign data_out_empty = 1'b0; + assign data_out_startofpacket = (state == STATE1)? data_in_startofpacket: 1'b0; + assign data_out_endofpacket = (state == STATE2)? data_in_endofpacket: 1'b0; + + always @ (posedge clk or posedge rst) + begin + if (rst) + state <= STATE_IDLE; + else case(state) + STATE_IDLE: + begin + if (data_in_startofpacket) + state <= STATE1; + end + STATE1: + begin + if (data_in_valid && data_out_ready) + state <= STATE2; + end + STATE2: + begin + if (data_in_valid && data_out_ready) + begin + if (data_in_endofpacket) + state <= STATE_LOCK; + else + state <= STATE1; + end + end + STATE_LOCK: + state <= STATE_IDLE; + default: + state <= STATE_IDLE; + endcase + end + + + + + + +endmodule + diff --git a/FPGA_firmware/sensor_algo_qsys/sts2stl.v b/FPGA_firmware/sensor_algo_qsys/sts2stl.v new file mode 100644 index 0000000..f0f9739 --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/sts2stl.v @@ -0,0 +1,108 @@ +//a module bridge the avalon streaming interfaces with data length from 16 bit to 32bit +//short to long +//First fill [31:16] and then fill [15:0] +//ST short to ST long + +//the number of ST short data_in_data has to be even +//tested by sts2stl_tb.v +module sts2stl( + + //clock and reset + input wire clk, + input wire rst, + + //avalon ST(Streaming) sink: 0 readlatency and 0 readallowence + input wire [15:0] data_in_data, // st.data + output wire data_in_ready, // .ready + input wire data_in_valid, // .valid + input wire data_in_empty, // .empty + input wire data_in_endofpacket, // .endofpacket + input wire data_in_startofpacket, // .startofpacket + + //avalon ST(Streaming) source: 0 readlatency and 0 readallowence + output wire [31:0] data_out_data, // st.data + input wire data_out_ready, // .ready + output wire data_out_valid, // .valid + output wire [1:0] data_out_empty, // .empty + output wire data_out_endofpacket, // .endofpacket + output wire data_out_startofpacket // .startofpacket +); + + reg[2:0] state; + localparam STATE_IDLE = 3'd0; //waiting for startofpacket + localparam STATE10 = 3'd1; // collecting [31:16] + localparam STATE20 = 3'd3; // collecting [15:0] + localparam STATE1 = 3'd7; + localparam STATE2 = 3'd6; + localparam STATE_LOCK = 3'd5; //Finishing streaming + + reg[15:0] data_buffer; //buffer for the first and then fill [31:16] + + assign data_in_ready = ((state == STATE20 || state == STATE2) && data_out_ready)? 1'b1:(state == STATE1 || state == STATE10)? 1'b1: 1'b0; + + assign data_out_data = (state == STATE2 || state == STATE20)? {data_buffer, data_in_data}: 32'b0; + assign data_out_valid = (state == STATE2 || state == STATE20)? data_in_valid: 1'b0; + assign data_out_empty = 2'b0; + assign data_out_startofpacket = (state == STATE20)? 1'b1: 1'b0; + assign data_out_endofpacket = (state == STATE2)? data_in_endofpacket: 1'b0; + + always @ (posedge clk or posedge rst) + begin + if (rst) + state <= STATE_IDLE; + else case(state) + STATE_IDLE: + begin + if (data_in_startofpacket) + state <= STATE10; + end + STATE10: + begin + if (data_in_valid) + begin + state <= STATE20; + data_buffer <= data_in_data; + end + end + STATE20: + begin + if (data_in_valid && data_out_ready) + begin + if (data_in_endofpacket) + state <= STATE_LOCK; + else + state <= STATE1; + end + end + STATE1: + begin + if (data_in_valid) + begin + state <= STATE2; + data_buffer <= data_in_data; + end + end + STATE2: + begin + if (data_in_valid && data_out_ready) + begin + if (data_in_endofpacket) + state <= STATE_LOCK; + else + state <= STATE1; + end + end + STATE_LOCK: + state <= STATE_IDLE; + default: + state <= STATE_IDLE; + endcase + end + + + + + + +endmodule + diff --git a/FPGA_firmware/sensor_algo_qsys/testbench/algo_top_cl_cali_rms_tb.v b/FPGA_firmware/sensor_algo_qsys/testbench/algo_top_cl_cali_rms_tb.v new file mode 100644 index 0000000..d6a7923 --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/testbench/algo_top_cl_cali_rms_tb.v @@ -0,0 +1,177 @@ +//module algo_top_cl_cali_tb + + +`timescale 1 ns / 1 ns + +module algo_top_cl_cali_rms_tb(); + + localparam CLK_PERIOD = 20; + + reg clk; + reg rst; + + //avalon ST(Streaming) sink: 0 readlatency and 0 readallowence + reg [31:0] data_in_data; + wire[31:0] data_in_data_n; + assign data_in_data_n = ~data_in_data; + wire data_in_ready; + wire data_in_valid; + reg [1:0] data_in_empty; + reg data_in_startofpacket; + wire data_in_endofpacket; + + + reg [1:0] state; + localparam STATE_IDLE = 2'd0; + localparam STATE_SEND = 2'd1; + localparam STATE_LOC = 2'd3; + + reg [7:0] tx_ctr; //counter for how many data has been sent + localparam WORDS_TO_SEND = 163; + + + //for cluster + reg[15:0] CL_THRESHOLD; + reg[15:0] CL_SIZE; + + + //the interface with cali_ram (storing cali factor) Avalon-MM: read califac from this ram + wire [8:0] address; + reg [15:0] cali_fac; + wire clken; + + // + reg waitrequest; + always @(posedge clk) begin + if (clken) + waitrequest<=1'b0; + else + waitrequest <= 1'b1; + end + + + algo_top_cl_cali_rms algo_top_cl_cali_rms_dut( + + .clk (clk), + .rst (rst), + + .data_in_data (data_in_data_n), + .data_in_ready (data_in_ready), + .data_in_valid (data_in_valid), + .data_in_empty (data_in_empty), + .data_in_startofpacket (data_in_startofpacket), + .data_in_endofpacket (data_in_endofpacket), + + + .CL_THRESHOLD (CL_THRESHOLD), + .CL_SIZE (CL_SIZE), + .address (address), + .clken (clken), + .cali_fac (cali_fac), + .waitrequest (waitrequest), + + .to_udp_data (to_udp_data), + .to_udp_ready(1'b1), + .to_udp_valid (to_udp_valid), + .to_udp_empty (to_udp_empty), + .to_udp_endofpacket (to_udp_endofpacket), + .to_udp_startofpacket (to_udp_startofpacket) + ); + + initial begin + + CL_SIZE = 5; + CL_THRESHOLD = 2; + + clk = 1'b1; + rst = 1'b1; + cali_fac = 16'd10003; + + data_in_data = 0; + data_in_empty = 2'b0; + data_in_startofpacket = 1'b0; + //data_in_endofpacket = 1'b0; + + + + state = STATE_IDLE; + + + #(CLK_PERIOD*2); + rst = 1'b0; + + //the next sink is ready.. + #(CLK_PERIOD*20); + + + #1; //make sure startofpacket and endofpacket start after clk rising edge + + repeat(8) begin + /******one packet*******/ + //start packet + data_in_data = 'hF0; + #(CLK_PERIOD*2); + data_in_startofpacket = 1'b1; + //end packet +// #(CLK_PERIOD*163*4); +// data_in_endofpacket = 1'b1; + #(CLK_PERIOD*5000); + + end + + repeat(8) begin + /******one packet*******/ + //start packet + data_in_data = 'h600F7; //output data should be 9,9,9,9,9, SumY=2880; SumXY=1843200; MeanXleftshift=2560 + #(CLK_PERIOD*2); + data_in_startofpacket = 1'b1; + //end packet +// #(CLK_PERIOD*163*4); +// data_in_endofpacket = 1'b1; + #(CLK_PERIOD*5000); + end + + + #(CLK_PERIOD*200); $stop; + + end + + + //clk + always #(CLK_PERIOD/2) clk = ~ clk; + + assign data_in_valid = (state == STATE_SEND || data_in_startofpacket || data_in_endofpacket)? 1'b1 : 1'b0; + assign data_in_endofpacket = (state == STATE_SEND && tx_ctr == WORDS_TO_SEND -1)? 1'b1: 1'b0; + always @(posedge clk) begin + case(state) + STATE_IDLE: + begin + tx_ctr <= 8'd0; + if (data_in_startofpacket) + begin + state <= STATE_SEND; + end + end + STATE_SEND: + begin + if (data_in_ready) + begin + data_in_startofpacket <= 1'b0; + tx_ctr <= tx_ctr + 1'b1; + if (tx_ctr == WORDS_TO_SEND-1) begin + state <= STATE_LOC; + //data_in_data <= 600000; + end else begin + data_in_data <= data_in_data + 1; + end + end + end + STATE_LOC: + begin + state <= STATE_IDLE; + tx_ctr <= 8'd0; + end + endcase + end + +endmodule \ No newline at end of file diff --git a/FPGA_firmware/sensor_algo_qsys/testbench/algo_top_cl_cali_tb.v b/FPGA_firmware/sensor_algo_qsys/testbench/algo_top_cl_cali_tb.v new file mode 100644 index 0000000..52ed3bb --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/testbench/algo_top_cl_cali_tb.v @@ -0,0 +1,158 @@ +//module algo_top_cl_cali_tb + + +`timescale 1 ns / 1 ns + +module algo_top_cl_cali_tb(); + + localparam CLK_PERIOD = 20; + + reg clk; + reg rst; + + //avalon ST(Streaming) sink: 0 readlatency and 0 readallowence + reg [31:0] data_in_data; + wire data_in_ready; + wire data_in_valid; + reg [1:0] data_in_empty; + reg data_in_startofpacket; + wire data_in_endofpacket; + + + reg [1:0] state; + localparam STATE_IDLE = 2'd0; + localparam STATE_SEND = 2'd1; + localparam STATE_LOC = 2'd3; + + reg [7:0] tx_ctr; //counter for how many data has been sent + localparam WORDS_TO_SEND = 163; + + + //for cluster + reg[15:0] CL_THRESHOLD; + reg[15:0] CL_SIZE; + + + //the interface with cali_ram (storing cali factor) Avalon-MM: read califac from this ram + wire [8:0] address; + reg [15:0] cali_fac; + wire clken; + + algo_top_cl_cali algo_top_cl_cali_dut( + + .clk (clk), + .rst (rst), + + .data_in_data (data_in_data), + .data_in_ready (data_in_ready), + .data_in_valid (data_in_valid), + .data_in_empty (data_in_empty), + .data_in_startofpacket (data_in_startofpacket), + .data_in_endofpacket (data_in_endofpacket), + + + .CL_THRESHOLD (CL_THRESHOLD), + .CL_SIZE (CL_SIZE), + .address (address), + .clken (clken), + .cali_fac (cali_fac) + + ); + + initial begin + + CL_SIZE = 5; + CL_THRESHOLD = 2; + + clk = 1'b1; + rst = 1'b1; + cali_fac = 'h3; + + data_in_data = 0; + data_in_empty = 2'b0; + data_in_startofpacket = 1'b0; + //data_in_endofpacket = 1'b0; + + + + state = STATE_IDLE; + + + #(CLK_PERIOD*2); + rst = 1'b0; + + //the next sink is ready.. + #(CLK_PERIOD*20); + + + #1; //make sure startofpacket and endofpacket start after clk rising edge + + repeat(8) begin + /******one packet*******/ + //start packet + data_in_data = 'hF0; + #(CLK_PERIOD*2); + data_in_startofpacket = 1'b1; + //end packet +// #(CLK_PERIOD*163*4); +// data_in_endofpacket = 1'b1; + #(CLK_PERIOD*5000); + + end + + repeat(8) begin + /******one packet*******/ + //start packet + data_in_data = 'hF3; //output data should be 0,3,0,3... + #(CLK_PERIOD*2); + data_in_startofpacket = 1'b1; + //end packet +// #(CLK_PERIOD*163*4); +// data_in_endofpacket = 1'b1; + #(CLK_PERIOD*5000); + end + + + #(CLK_PERIOD*200); $stop; + + end + + + //clk + always #(CLK_PERIOD/2) clk = ~ clk; + + assign data_in_valid = (state == STATE_SEND || data_in_startofpacket || data_in_endofpacket)? 1'b1 : 1'b0; + assign data_in_endofpacket = (state == STATE_SEND && tx_ctr == WORDS_TO_SEND -1)? 1'b1: 1'b0; + always @(posedge clk) begin + case(state) + STATE_IDLE: + begin + tx_ctr <= 8'd0; + if (data_in_startofpacket) + begin + state <= STATE_SEND; + end + end + STATE_SEND: + begin + if (data_in_ready) + begin + data_in_startofpacket <= 1'b0; + tx_ctr <= tx_ctr + 1'b1; + if (tx_ctr == WORDS_TO_SEND-1) begin + state <= STATE_LOC; + //data_in_data <= 600000; + end else begin + data_in_data <= data_in_data + 1; + end + end + end + STATE_LOC: + begin + state <= STATE_IDLE; + tx_ctr <= 8'd0; + end + endcase + end + +endmodule \ No newline at end of file diff --git a/FPGA_firmware/sensor_algo_qsys/testbench/algo_top_cl_tb.v b/FPGA_firmware/sensor_algo_qsys/testbench/algo_top_cl_tb.v new file mode 100644 index 0000000..92f8ffd --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/testbench/algo_top_cl_tb.v @@ -0,0 +1,160 @@ +//algo_top_cl testbench + +//testbench for algo_top + +`timescale 1 ns / 1 ns +module algo_top_cl_tb(); + + localparam CLK_PERIOD = 20; + + reg clk; + reg rst; + + //avalon ST(Streaming) sink: 0 readlatency and 0 readallowence + reg [31:0] data_in_data; + wire data_in_ready; + wire data_in_valid; + reg [1:0] data_in_empty; + reg data_in_startofpacket; + wire data_in_endofpacket; + + //avalon ST(Streaming) source: 0 readlatency and 0 readallowence + wire [15:0] data_out_data; // data_out.data + wire data_out_empty; // .empty + wire data_out_endofpacket; // .endofpacket + wire data_out_startofpacket; // .startofpacket + reg data_out_ready; // .ready + wire data_out_valid; // .valid + + reg [1:0] state; + localparam STATE_IDLE = 2'd0; + localparam STATE_SEND = 2'd1; + localparam STATE_LOC = 2'd3; + + reg [7:0] tx_ctr; //counter for how many data has been sent + localparam WORDS_TO_SEND = 163; + + //for cluster + reg[15:0] CL_THRESHOLD; + reg[15:0] CL_SIZE; + + algo_top_cl algo_top_cl_dut( + + .clk (clk), + .rst (rst), + + .data_in_data (data_in_data), + .data_in_ready (data_in_ready), + .data_in_valid (data_in_valid), + .data_in_empty (data_in_empty), + .data_in_startofpacket (data_in_startofpacket), + .data_in_endofpacket (data_in_endofpacket), + + .data_out_data (data_out_data), + .data_out_empty (data_out_empty), + .data_out_endofpacket (data_out_endofpacket), + .data_out_startofpacket (data_out_startofpacket), + //.data_out_ready (data_out_ready), + .data_out_valid (data_out_valid), + + .CL_THRESHOLD (CL_THRESHOLD), + .CL_SIZE (CL_SIZE) + + ); + + initial begin + + CL_SIZE = 5; + CL_THRESHOLD = 2; + + clk = 1'b1; + rst = 1'b1; + + data_in_data = 600000; + data_in_empty = 2'b0; + data_in_startofpacket = 1'b0; + //data_in_endofpacket = 1'b0; + + data_out_ready = 1'b0; + + state = STATE_IDLE; + + + #(CLK_PERIOD*2); + rst = 1'b0; + + //the next sink is ready.. + #(CLK_PERIOD*20); + data_out_ready = 1'b1; + + #1; //make sure startofpacket and endofpacket start after clk rising edge + + repeat(8) begin + /******one packet*******/ + //start packet + data_in_data = 600000; + #(CLK_PERIOD*2); + data_in_startofpacket = 1'b1; + //end packet +// #(CLK_PERIOD*163*4); +// data_in_endofpacket = 1'b1; + #(CLK_PERIOD*5000); + + end + + repeat(8) begin + /******one packet*******/ + //start packet + data_in_data = 7000000; + #(CLK_PERIOD*2); + data_in_startofpacket = 1'b1; + //end packet +// #(CLK_PERIOD*163*4); +// data_in_endofpacket = 1'b1; + #(CLK_PERIOD*5000); + end + + + #(CLK_PERIOD*200); $stop; + + end + + + //clk + always #(CLK_PERIOD/2) clk = ~ clk; + + assign data_in_valid = (state == STATE_SEND || data_in_startofpacket || data_in_endofpacket)? 1'b1 : 1'b0; + assign data_in_endofpacket = (state == STATE_SEND && tx_ctr == WORDS_TO_SEND -1)? 1'b1: 1'b0; + always @(posedge clk) begin + case(state) + STATE_IDLE: + begin + tx_ctr <= 8'd0; + if (data_in_startofpacket) + begin + state <= STATE_SEND; + end + end + STATE_SEND: + begin + if (data_in_ready) + begin + data_in_startofpacket <= 1'b0; + tx_ctr <= tx_ctr + 1'b1; + if (tx_ctr == WORDS_TO_SEND-1) begin + state <= STATE_LOC; + //data_in_data <= 600000; + end else begin + data_in_data <= data_in_data + 1; + end + end + end + STATE_LOC: + begin + state <= STATE_IDLE; + tx_ctr <= 8'd0; + end + endcase + end + +endmodule \ No newline at end of file diff --git a/FPGA_firmware/sensor_algo_qsys/testbench/algo_top_tb.v b/FPGA_firmware/sensor_algo_qsys/testbench/algo_top_tb.v new file mode 100644 index 0000000..b919314 --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/testbench/algo_top_tb.v @@ -0,0 +1,136 @@ +//testbench for algo_top + +`timescale 1 ns / 1 ns +module algo_top_tb(); + + localparam CLK_PERIOD = 20; + + reg clk; + reg rst; + + //avalon ST(Streaming) sink: 0 readlatency and 0 readallowence + reg [31:0] data_in_data; + wire data_in_ready; + wire data_in_valid; + reg [1:0] data_in_empty; + reg data_in_startofpacket; + wire data_in_endofpacket; + + //avalon ST(Streaming) source: 0 readlatency and 0 readallowence + wire [15:0] data_out_data; // data_out.data + wire data_out_empty; // .empty + wire data_out_endofpacket; // .endofpacket + wire data_out_startofpacket; // .startofpacket + reg data_out_ready; // .ready + wire data_out_valid; // .valid + + reg [1:0] state; + localparam STATE_IDLE = 2'd0; + localparam STATE_SEND = 2'd1; + localparam STATE_LOC = 2'd3; + + reg [7:0] tx_ctr; //counter for how many data has been sent + localparam WORDS_TO_SEND = 163; + + algo_top algo_top_dut( + + .clk (clk), + .rst (rst), + + .data_in_data (data_in_data), + .data_in_ready (data_in_ready), + .data_in_valid (data_in_valid), + .data_in_empty (data_in_empty), + .data_in_startofpacket (data_in_startofpacket), + .data_in_endofpacket (data_in_endofpacket), + + .data_out_data (data_out_data), + .data_out_empty (data_out_empty), + .data_out_endofpacket (data_out_endofpacket), + .data_out_startofpacket (data_out_startofpacket), + .data_out_ready (data_out_ready), + .data_out_valid (data_out_valid) + + ); + + initial begin + + clk = 1'b1; + rst = 1'b1; + + data_in_data = 600000; + data_in_empty = 2'b0; + data_in_startofpacket = 1'b0; + //data_in_endofpacket = 1'b0; + + data_out_ready = 1'b0; + + state = STATE_IDLE; + + + #(CLK_PERIOD*2); + rst = 1'b0; + + //the next sink is ready.. + #(CLK_PERIOD*20); + data_out_ready = 1'b1; + + #1; //make sure startofpacket and endofpacket start after clk rising edge + + repeat(8) begin + /******one packet*******/ + //start packet + #(CLK_PERIOD*2); + data_in_startofpacket = 1'b1; + //end packet +// #(CLK_PERIOD*163*4); +// data_in_endofpacket = 1'b1; + #(CLK_PERIOD*5000); + end + + + #(CLK_PERIOD*200); $stop; + + end + + + //clk + always #(CLK_PERIOD/2) clk = ~ clk; + + assign data_in_valid = (state == STATE_SEND || data_in_startofpacket || data_in_endofpacket)? 1'b1 : 1'b0; + assign data_in_endofpacket = (state == STATE_SEND && tx_ctr == WORDS_TO_SEND -1)? 1'b1: 1'b0; + always @(posedge clk) begin + case(state) + STATE_IDLE: + begin + tx_ctr <= 8'd0; + if (data_in_startofpacket) + begin + state <= STATE_SEND; + data_in_data <= data_in_data + 1; + end + end + STATE_SEND: + begin + if (data_in_ready) + begin + data_in_startofpacket <= 1'b0; + tx_ctr <= tx_ctr + 1'b1; + if (tx_ctr == WORDS_TO_SEND-1) begin + state <= STATE_LOC; + data_in_data <= 600000; + //data_in_endofpacket <= 1'b0; + end else begin + data_in_data <= data_in_data + 1; + end + end + end + STATE_LOC: + begin + state <= STATE_IDLE; + tx_ctr <= 8'd0; + end + endcase + end + +endmodule \ No newline at end of file diff --git a/FPGA_firmware/sensor_algo_qsys/testbench/bkg_subtraction_pipe_tb.v b/FPGA_firmware/sensor_algo_qsys/testbench/bkg_subtraction_pipe_tb.v new file mode 100644 index 0000000..5fbb7c2 --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/testbench/bkg_subtraction_pipe_tb.v @@ -0,0 +1,143 @@ +//bkg_subtraction_pipe_tb.v + +//testbench for bkg_subtraction_pipe + +`timescale 1 ns / 1 ns +module bkg_subtraction_pipe_tb(); + + localparam CLK_PERIOD = 20; + + reg clk; + reg rst; + + //avalon ST(Streaming) sink: 0 readlatency and 0 readallowence + reg [31:0] data_in_data; + wire data_in_ready; + wire data_in_valid; + reg [1:0] data_in_empty; + reg data_in_startofpacket; + wire data_in_endofpacket; + + //avalon ST(Streaming) source: 0 readlatency and 0 readallowence + wire [31:0] data_out_data; // data_out.data + wire data_out_empty; // .empty + wire data_out_endofpacket; // .endofpacket + wire data_out_startofpacket; // .startofpacket + reg data_out_ready; // .ready + wire data_out_valid; // .valid + + reg [1:0] state; + localparam STATE_IDLE = 2'd0; + localparam STATE_SEND = 2'd1; + localparam STATE_LOC = 2'd3; + + reg [7:0] tx_ctr; //counter for how many data has been sent + localparam WORDS_TO_SEND = 163; + + bkg_subtraction_pipe #(.BKG_FRAME(4)) bkg_subtraction_dut( + + .clk (clk), + .rst (rst), + + .data_in_data (data_in_data), + .data_in_ready (data_in_ready), + .data_in_valid (data_in_valid), + .data_in_empty (data_in_empty), + .data_in_startofpacket (data_in_startofpacket), + .data_in_endofpacket (data_in_endofpacket), + + .data_out_data (data_out_data), + .data_out_empty (data_out_empty), + .data_out_endofpacket (data_out_endofpacket), + .data_out_startofpacket (data_out_startofpacket), + .data_out_ready (data_out_ready), + .data_out_valid (data_out_valid), + + .to_udp_ready(1'b1) + + ); + + initial begin + + clk = 1'b1; + rst = 1'b1; + + //data_in_data = 32'hFFFFFFFF; + data_in_data = 0; + data_in_empty = 2'b0; + data_in_startofpacket = 1'b0; + //data_in_endofpacket = 1'b0; + + data_out_ready = 1'b0; + + state = STATE_IDLE; + + + #(CLK_PERIOD*2); + rst = 1'b0; + + //the next sink is ready.. + #(CLK_PERIOD*20); + data_out_ready = 1'b1; + + #1; //make sure startofpacket and endofpacket start after clk rising edge + + repeat(8) begin + /******one packet*******/ + //start packet + #(CLK_PERIOD*2); + data_in_startofpacket = 1'b1; + //end packet +// #(CLK_PERIOD*163*4); +// data_in_endofpacket = 1'b1; + #(CLK_PERIOD*500); + end + + + #(CLK_PERIOD*200); $stop; + + end + + + //clk + always #(CLK_PERIOD/2) clk = ~ clk; + + assign data_in_valid = (state == STATE_SEND || data_in_startofpacket || data_in_endofpacket)? 1'b1 : 1'b0; + assign data_in_endofpacket = (state == STATE_SEND && tx_ctr == WORDS_TO_SEND -1)? 1'b1: 1'b0; + always @(posedge clk) begin + case(state) + STATE_IDLE: + begin + tx_ctr <= 8'd0; + if (data_in_startofpacket) + begin + state <= STATE_SEND; + data_in_data <= data_in_data +1'b1; + end + end + STATE_SEND: + begin + if (data_in_ready) + begin + data_in_startofpacket <= 1'b0; + tx_ctr <= tx_ctr + 1'b1; + if (tx_ctr == WORDS_TO_SEND-1) begin + state <= STATE_LOC; + data_in_data = 0; + + //data_in_data <= 32'hFFFFFFFF; + //data_in_endofpacket <= 1'b0; + end else begin + data_in_data <= data_in_data +1'b1; + end + end + end + STATE_LOC: + begin + state <= STATE_IDLE; + tx_ctr <= 8'd0; + end + endcase + end + +endmodule \ No newline at end of file diff --git a/FPGA_firmware/sensor_algo_qsys/testbench/bkg_subtraction_tb.v b/FPGA_firmware/sensor_algo_qsys/testbench/bkg_subtraction_tb.v new file mode 100644 index 0000000..45db278 --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/testbench/bkg_subtraction_tb.v @@ -0,0 +1,136 @@ +//testbench for bkg_subtraction + +`timescale 1 ns / 1 ns +module bkg_subtraction_tb(); + + localparam CLK_PERIOD = 20; + + reg clk; + reg rst; + + //avalon ST(Streaming) sink: 0 readlatency and 0 readallowence + reg [31:0] data_in_data; + wire data_in_ready; + wire data_in_valid; + reg [1:0] data_in_empty; + reg data_in_startofpacket; + wire data_in_endofpacket; + + //avalon ST(Streaming) source: 0 readlatency and 0 readallowence + wire [31:0] data_out_data; // data_out.data + wire data_out_empty; // .empty + wire data_out_endofpacket; // .endofpacket + wire data_out_startofpacket; // .startofpacket + reg data_out_ready; // .ready + wire data_out_valid; // .valid + + reg [1:0] state; + localparam STATE_IDLE = 2'd0; + localparam STATE_SEND = 2'd1; + localparam STATE_LOC = 2'd3; + + reg [7:0] tx_ctr; //counter for how many data has been sent + localparam WORDS_TO_SEND = 163; + + bkg_subtraction #(.BKG_FRAME(4)) bkg_subtraction_dut( + + .clk (clk), + .rst (rst), + + .data_in_data (data_in_data), + .data_in_ready (data_in_ready), + .data_in_valid (data_in_valid), + .data_in_empty (data_in_empty), + .data_in_startofpacket (data_in_startofpacket), + .data_in_endofpacket (data_in_endofpacket), + + .data_out_data (data_out_data), + .data_out_empty (data_out_empty), + .data_out_endofpacket (data_out_endofpacket), + .data_out_startofpacket (data_out_startofpacket), + .data_out_ready (data_out_ready), + .data_out_valid (data_out_valid) + + ); + + initial begin + + clk = 1'b1; + rst = 1'b1; + + data_in_data = 0; + data_in_empty = 2'b0; + data_in_startofpacket = 1'b0; + //data_in_endofpacket = 1'b0; + + data_out_ready = 1'b0; + + state = STATE_IDLE; + + + #(CLK_PERIOD*2); + rst = 1'b0; + + //the next sink is ready.. + #(CLK_PERIOD*20); + data_out_ready = 1'b1; + + #1; //make sure startofpacket and endofpacket start after clk rising edge + + repeat(8) begin + /******one packet*******/ + //start packet + #(CLK_PERIOD*2); + data_in_startofpacket = 1'b1; + //end packet +// #(CLK_PERIOD*163*4); +// data_in_endofpacket = 1'b1; + #(CLK_PERIOD*500); + end + + + #(CLK_PERIOD*200); $stop; + + end + + + //clk + always #(CLK_PERIOD/2) clk = ~ clk; + + assign data_in_valid = (state == STATE_SEND || data_in_startofpacket || data_in_endofpacket)? 1'b1 : 1'b0; + assign data_in_endofpacket = (state == STATE_SEND && tx_ctr == WORDS_TO_SEND -1)? 1'b1: 1'b0; + always @(posedge clk) begin + case(state) + STATE_IDLE: + begin + tx_ctr <= 8'd0; + if (data_in_startofpacket) + begin + state <= STATE_SEND; + data_in_data <= data_in_data + 1; + end + end + STATE_SEND: + begin + if (data_in_ready) + begin + data_in_startofpacket <= 1'b0; + tx_ctr <= tx_ctr + 1'b1; + if (tx_ctr == WORDS_TO_SEND-1) begin + state <= STATE_LOC; + data_in_data <= 0; + //data_in_endofpacket <= 1'b0; + end else begin + data_in_data <= data_in_data + 1; + end + end + end + STATE_LOC: + begin + state <= STATE_IDLE; + tx_ctr <= 8'd0; + end + endcase + end + +endmodule \ No newline at end of file diff --git a/FPGA_firmware/sensor_algo_qsys/testbench/calibration_tb.v b/FPGA_firmware/sensor_algo_qsys/testbench/calibration_tb.v new file mode 100644 index 0000000..609cdde --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/testbench/calibration_tb.v @@ -0,0 +1,217 @@ +//module calibration testbench +//data_caled calculate: address's square +`timescale 1 ns / 1 ns +module calibration_tb(); + + localparam CLK_PERIOD = 20; + + reg clk; + reg rst; + + //avalon ST(Streaming) sink: 0 readlatency and 0 readallowence + reg [15:0] data_in_data; + wire data_in_ready; + wire data_in_valid; + reg data_in_empty; + reg data_in_startofpacket; + reg data_in_endofpacket; + + reg to_udp_ready; + + //the interface with cali_ram (storing cali factor) Avalon-MM: read califac from this ram + wire [8:0] address; + wire [15:0] cali_fac; + wire clken; + + reg [8:0] data_caled_address; + wire [15:0] data_caled; + wire data_caled_rd_enable; + + reg [15:0] data_a; + wire wren_a; + reg [8:0] wr_address; + reg start_wr; + + + + reg [2:0] state; + localparam STATE_IDLE = 3'd0; + localparam STATE_WR = 3'd1; + localparam STATE_LOC0 = 3'd2; + localparam STATE_SEND = 3'd3; + localparam STATE_LOC1 = 3'd4; + localparam STATE_RD = 3'd5; + localparam STATE_LOC2 = 3'd6; + + assign data_caled_rd_enable = (state == STATE_RD)? 1'b1: 1'b0; + + + // + reg waitrequest; + always @(posedge clk) begin + if (clken) + waitrequest<=1'b0; + else + waitrequest <= 1'b1; + end + + + + //the ram for store the cali_fac in testbench + ram_sim cal_fac_simulation_ram ( + .clock ( clk ), + .address_a (wr_address), + .data_a (data_a), + .wren_a (wren_a), + .rden_a (1'b0), + .q_a (), + + .address_b ( address ), + .data_b ( ), + .rden_b (clken), + .wren_b (1'b0), + .q_b ( cali_fac) + ); + + calibration calibration_dut( + + .clk(clk), + .rst(rst), + + .data_in_data (data_in_data), + .data_in_ready (data_in_ready), + .data_in_valid (data_in_valid), + .data_in_empty (data_in_empty), + .data_in_startofpacket (data_in_startofpacket), + .data_in_endofpacket (data_in_endofpacket), + + .address (address), + .clken (clken), + .cali_fac (cali_fac), + .waitrequest(waitrequest), + + .data_caled_address(data_caled_address), + .data_caled(data_caled), + .data_caled_rd_enable(data_caled_rd_enable), + + .to_udp_ready(to_udp_ready) + + ); + + + initial begin + + clk = 1'b1; + rst = 1'b1; + + data_in_data = 0; + data_in_empty = 2'b0; + data_in_startofpacket = 1'b0; + data_in_endofpacket = 1'b0; + start_wr = 1'b0; + to_udp_ready = 1'b0; + + state = STATE_IDLE; + + + #(CLK_PERIOD*2 + 1); + rst = 1'b0; + start_wr = 1'b1; + + #(CLK_PERIOD*2); + start_wr = 1'b0; + + #(CLK_PERIOD*400); + + + //start packet + #(CLK_PERIOD*2+1); + data_in_startofpacket = 1'b1; + #(CLK_PERIOD*2); + to_udp_ready = 1'b1; + + #(CLK_PERIOD*10); + to_udp_ready = 1'b0; + #(CLK_PERIOD*10); + to_udp_ready = 1'b1; + #(CLK_PERIOD*309); + //end packet + data_in_endofpacket = 1'b1; + + + #(CLK_PERIOD*500); $stop; + + end + + + //clk + always #(CLK_PERIOD/2) clk = ~ clk; + + assign data_in_valid = (state == STATE_SEND || data_in_startofpacket || data_in_endofpacket)? 1'b1 : 1'b0; + assign wren_a = (state == STATE_WR)? 1'b1: 1'b0; + always @(posedge clk) begin + case(state) + STATE_IDLE: + begin + wr_address <= 0; + data_a <= 0; + data_caled_address <= 0; + if (start_wr) + begin + state <= STATE_WR; + end + end + STATE_WR: + begin + wr_address <= wr_address + 1; + data_a <= data_a + 1; + if (wr_address == 319) + begin + state <= STATE_LOC0; + end + end + STATE_LOC0: + begin + if (data_in_startofpacket && data_in_ready) + begin + state <= STATE_SEND; + data_in_data <= data_in_data + 1; + data_in_startofpacket <= 1'b0; + end + end + STATE_SEND: + begin + if (data_in_ready) + begin + if (data_in_endofpacket) begin + state <= STATE_LOC1; + data_in_data <= 0; + data_in_endofpacket <= 1'b0; + end else begin + data_in_data <= data_in_data + 1; + end + end + end + STATE_LOC1: + begin + state <= STATE_RD; + end + STATE_RD: + begin + data_caled_address <= data_caled_address + 1; + if (data_caled_address == 319) + state <= STATE_LOC2; + end + STATE_LOC2: + state <= STATE_IDLE; + endcase + end + + + + + + + + +endmodule diff --git a/FPGA_firmware/sensor_algo_qsys/testbench/cluster_locate_tb.v b/FPGA_firmware/sensor_algo_qsys/testbench/cluster_locate_tb.v new file mode 100644 index 0000000..1d92e5f --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/testbench/cluster_locate_tb.v @@ -0,0 +1,172 @@ +//module cluster_locate testbench + +//algo_top_cl testbench + +//testbench for algo_top + +`timescale 1 ns / 1 ns +module cluster_locate_tb(); + + localparam CLK_PERIOD = 20; + + reg clk; + reg rst; + + //avalon ST(Streaming) sink: 0 readlatency and 0 readallowence + reg [15:0] data_in_data; + wire data_in_ready; + wire data_in_valid; + reg data_in_empty; + reg data_in_startofpacket; + wire data_in_endofpacket; + + //for cluster + reg[15:0] CL_THRESHOLD; + reg[15:0] CL_SIZE; + + wire[8:0] sig_ch_left; + wire[8:0] sig_ch_right; + wire has_cluster; + wire no_cluster; + + + + reg [1:0] state; + localparam STATE_IDLE = 2'd0; + localparam STATE_SEND = 2'd1; + localparam STATE_LOC = 2'd3; + + reg [8:0] tx_ctr; //counter for how many data has been sent + localparam WORDS_TO_SEND = 320; + + + + cluster_locate cluster_locate_dut( + + .clk (clk), + .rst (rst), + + .data_in_data (data_in_data), + .data_in_ready (data_in_ready), + .data_in_valid (data_in_valid), + .data_in_empty (data_in_empty), + .data_in_startofpacket (data_in_startofpacket), + .data_in_endofpacket (data_in_endofpacket), + + .THRESHOLD (CL_THRESHOLD), + .SIZE (CL_SIZE), + + .sig_ch_left (sig_ch_left), + .sig_ch_right (sig_ch_right), + .has_cluster (has_cluster), + .no_cluster (no_cluster) + + ); + + localparam HEIGHT = 2000; + reg[31:0] WIDTH; + localparam POS = 100; + + + initial begin + + CL_SIZE = 5; + CL_THRESHOLD = 200; + + clk = 1'b1; + rst = 1'b1; + + + data_in_empty = 2'b0; + data_in_startofpacket = 1'b0; + //data_in_endofpacket = 1'b0; + + + state = STATE_IDLE; + + + #(CLK_PERIOD*2); + rst = 1'b0; + + + #1; //make sure startofpacket and endofpacket start after clk rising edge + + repeat(4) begin + WIDTH = 20; + /******one packet*******/ + //start packet + #(CLK_PERIOD*2); + data_in_startofpacket = 1'b1; + + #(CLK_PERIOD*5000); + + end + + repeat(4) begin + WIDTH = 3; + /******one packet*******/ + //start packet + #(CLK_PERIOD*2); + data_in_startofpacket = 1'b1; + + #(CLK_PERIOD*5000); + + end + + + #(CLK_PERIOD*200); $stop; + + end + + + //clk + always #(CLK_PERIOD/2) clk = ~ clk; + + assign data_in_valid = (state == STATE_SEND || data_in_startofpacket || data_in_endofpacket)? 1'b1 : 1'b0; + assign data_in_endofpacket = (state == STATE_SEND && tx_ctr == WORDS_TO_SEND -1)? 1'b1: 1'b0; + always @(posedge clk) begin + case(state) + STATE_IDLE: + begin + tx_ctr <= 8'd0; + if (data_in_startofpacket) + begin + state <= STATE_SEND; + end + end + STATE_SEND: + begin + if (data_in_ready) + begin + data_in_startofpacket <= 1'b0; + tx_ctr <= tx_ctr + 1'b1; + if (tx_ctr < 60) + data_in_data<=0; + else if (tx_ctr < 60+WIDTH-1) + data_in_data <= HEIGHT/WIDTH + data_in_data; + else if (tx_ctr < 60+2*WIDTH-1) + data_in_data <= data_in_data-HEIGHT/WIDTH; + else if (tx_ctr < 60+3*WIDTH-1) + data_in_data <= HEIGHT/WIDTH + data_in_data; + else if (tx_ctr < 60+4*WIDTH-1) + data_in_data <= data_in_data-HEIGHT/WIDTH; + else if (tx_ctr < 60+5*WIDTH-1) + data_in_data <= HEIGHT/WIDTH + data_in_data; + else if (tx_ctr < 60+6*WIDTH-1) + data_in_data <= data_in_data-HEIGHT/WIDTH; + else + data_in_data <= 0; + if (tx_ctr == WORDS_TO_SEND-1) begin + state <= STATE_LOC; + end + end + end + STATE_LOC: + begin + state <= STATE_IDLE; + tx_ctr <= 8'd0; + end + endcase + end + +endmodule \ No newline at end of file diff --git a/FPGA_firmware/sensor_algo_qsys/testbench/sensor_algo_tb.v b/FPGA_firmware/sensor_algo_qsys/testbench/sensor_algo_tb.v new file mode 100644 index 0000000..f85b5db --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/testbench/sensor_algo_tb.v @@ -0,0 +1,171 @@ +//This is a testbench from Sensorinterface to algo output +//This is a testbench from the UDP generator + + +`timescale 1 ns / 1 ns +module sensor_algo_tb(); + + +//Signals + + reg clk_clk; // clk.clk + reg rst_reset; // rst.reset + reg [2:0] csr_address; // csr.address + reg csr_write; // .write + reg [31:0] csr_writedata; // .writedata + reg [3:0] csr_byteenable; // .byteenable + reg csr_read; // .read + wire [31:0] csr_readdata; // .readdata + + + wire [31:0] data_out_data; // data_out.data + wire [1:0] data_out_empty; // .empty + wire data_out_endofpacket; // .endofpacket + wire data_out_startofpacket; // .startofpacket + reg data_out_ready; // .ready + wire data_out_valid; // .valid + + reg in_trg; // sensor.in_trg + wire out_adc_clk; // .out_dac_clk + wire out_adc_cnv; // .out_dac_cnv + reg [4:0] in_adc_data; // .in_dac_data + wire out_sensor_rst; // .out_sensor_rst + wire out_sensor_clk; // .out_sensor_clk + wire out_sensor_gain; // .out_sensor_gain + + wire serial; + reg [7:0] ext; + + reg[26:0] frameID; + + +initial +begin + clk_clk = 0; + rst_reset = 1; + csr_address = 3'd0; + csr_write = 0; + csr_writedata = 32'd0; + csr_byteenable = 4'b1111; + csr_read = 0; + data_out_ready = 1; + + in_trg = 0; + in_adc_data = 5'b11011; //11111 with out any signal + + ext = 0; + + #50 + rst_reset = 0; + + //write 0xAAAA0032 to register 2 + #20 + csr_write = 1; + csr_byteenable = 4'b1111; + csr_address = 3'd2; + csr_writedata = 32'hAAAA0032; + #20 + csr_write = 0; + + //write 0x00040004 to register 1 + #20 + csr_write = 1; + csr_byteenable = 4'b1111; + csr_address = 3'd1; + csr_writedata = 32'h01200004; + //csr_writedata = 32'h00040004; + #20 + csr_write = 0; + + //write 0x00060001 to register 0 + #20 + csr_write = 1; + csr_byteenable = 4'b1111; + csr_address = 3'd0; + csr_writedata = 32'h00060001; + #20 + csr_write = 0; + + //write 0x20040032 to register 3 + #20 + csr_write = 1; + csr_byteenable = 4'b1111; + csr_address = 3'd3; + csr_writedata = 32'h20040032; + #20 + csr_write = 0; + + + + //#500000 + #1200000 + $stop; + +end + +always #10 clk_clk = ~clk_clk; + +always @(posedge clk_clk) begin + if (data_out_startofpacket) + data_out_ready<=1; + if (data_out_endofpacket) + data_out_ready<=0; + end +always #50010 in_trg = ~in_trg; + + +//always #20 begin +// if (out_sensor_rst) +// in_adc_data = in_adc_data + 1; //dummy hay to ADCs +// else +// in_adc_data = 0; +//end + + + +//always @(posedge out_adc_clk ) +// begin +// if (frameID<8) +// in_adc_data[2] = ~in_adc_data[2]; //add some signal on the third sensor array +// else +// in_adc_data[2] = 0; +// end + +sensor_algo sensor_algo_dut( + .clk_clk (clk_clk), // clk.clk + .rst_reset (rst_reset), // rst.reset + + .csr_address (csr_address), // csr.address + .csr_write (csr_write), // .write + .csr_writedata (csr_writedata), // .writedata + .csr_byteenable (csr_byteenable), // .byteenable + .csr_read (csr_read), // .read + .csr_readdata (csr_readdata), // .readdata + + .data_out_data (data_out_data), // data_out.data + .data_out_empty (data_out_empty), // .empty + .data_out_endofpacket (data_out_endofpacket), // .endofpacket + .data_out_startofpacket (data_out_startofpacket),// .startofpacket + .data_out_ready (data_out_ready), // .ready + .data_out_valid (data_out_valid), // .valid + + .in_trg (in_trg), // sensor.in_trg + .out_adc_clk (out_adc_clk), // .out_dac_clk + .out_adc_cnv (out_adc_cnv), // .out_dac_cnv + .in_adc_data (in_adc_data), // .in_dac_data + .out_sensor_rst (out_sensor_rst), // .out_sensor_rst + .out_sensor_clk (out_sensor_clk), // .out_sensor_clk + .out_sensor_gain (out_sensor_gain), // .out_sensor_gain + .serial_rx (serial), //receive data + .serial_tx (serial), //send data + .ext_input (ext), //SMA etc. + + .status_out (status_out), + + .address (), + .cali_fac (16'd3), + .clken (), + .waitrequest (1'b0) + ); + +endmodule \ No newline at end of file diff --git a/FPGA_firmware/sensor_algo_qsys/testbench/st2mm_tb.v b/FPGA_firmware/sensor_algo_qsys/testbench/st2mm_tb.v new file mode 100644 index 0000000..6db2781 --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/testbench/st2mm_tb.v @@ -0,0 +1,135 @@ +//testbench for stl2sts: ST long 32-bit to ST short 16-bit + +`timescale 1 ns / 1 ns +module st2mm_tb(); + + localparam CLK_PERIOD = 20; + + reg clk; + reg rst; + + //avalon ST(Streaming) sink: 0 readlatency and 0 readallowence + reg [31:0] data_in_data; + wire data_in_ready; + wire data_in_valid; + reg [1:0] data_in_empty; + reg data_in_startofpacket; + reg data_in_endofpacket; + + + + //avalon MM(Memory Mapped) source writelatency 0; readlatency 1 but no read logic here + wire [8:0] mm_address; + wire mm_chipselect; // only for write + wire [31:0] mm_readdate; //do not read + wire mm_write; + wire [31:0] mm_writedata; + reg mm_waitrequest_n; + + + reg [1:0] state; + localparam STATE_IDLE = 2'd0; + localparam STATE_SEND = 2'd1; + localparam STATE_LOC = 2'd3; + + st2mm #(.BITSIZE(32), .EMPTY_SIZE(2)) st2mm_dut( + + .clk (clk), + .rst (rst), + + .data_in_data (data_in_data), + .data_in_ready (data_in_ready), + .data_in_valid (data_in_valid), + .data_in_empty (data_in_empty), + .data_in_startofpacket (data_in_startofpacket), + .data_in_endofpacket (data_in_endofpacket), + + .mm_address (mm_address), + .mm_chipselect (mm_chipselect), + .mm_readdate (mm_readdate), + .mm_write (mm_write), + .mm_writedata (mm_writedata), + .mm_waitrequest_n (mm_waitrequest_n) + + ); + + initial begin + + clk = 1'b1; + rst = 1'b1; + + data_in_data = 0; + data_in_empty = 2'b0; + data_in_startofpacket = 1'b0; + data_in_endofpacket = 1'b0; + + mm_waitrequest_n = 1'b0; + + state = STATE_IDLE; + + + #(CLK_PERIOD*2); + rst = 1'b0; + + //the next sink is ready.. + #(CLK_PERIOD*20); + mm_waitrequest_n = 1'b1; + + //start packet + #(CLK_PERIOD*2+1); + data_in_startofpacket = 1'b1; + + #(CLK_PERIOD*2); + mm_waitrequest_n = 1'b0; + + #(CLK_PERIOD*2); + mm_waitrequest_n = 1'b1; + + + + //end packet + #(CLK_PERIOD*5); + data_in_endofpacket = 1'b1; + + + #(CLK_PERIOD*200); $stop; + + end + + + //clk + always #(CLK_PERIOD/2) clk = ~ clk; + + assign data_in_valid = (state == STATE_SEND || data_in_startofpacket || data_in_endofpacket)? 1'b1 : 1'b0; + always @(posedge clk) begin + case(state) + STATE_IDLE: + begin + if (data_in_startofpacket && data_in_ready) + begin + state <= STATE_SEND; + data_in_data <= data_in_data + 1; + data_in_startofpacket <= 1'b0; + end + end + STATE_SEND: + begin + if (data_in_ready) + begin + if (data_in_endofpacket) begin + state <= STATE_LOC; + data_in_data <= 0; + data_in_endofpacket <= 1'b0; + end else begin + data_in_data <= data_in_data + 1; + end + end + end + STATE_LOC: + begin + state <= STATE_IDLE; + end + endcase + end + +endmodule \ No newline at end of file diff --git a/FPGA_firmware/sensor_algo_qsys/testbench/stl2sts_tb.v b/FPGA_firmware/sensor_algo_qsys/testbench/stl2sts_tb.v new file mode 100644 index 0000000..122b395 --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/testbench/stl2sts_tb.v @@ -0,0 +1,126 @@ +//testbench for stl2sts: ST long 32-bit to ST short 16-bit + +`timescale 1 ns / 1 ns +module stl2sts_tb(); + + localparam CLK_PERIOD = 20; + + reg clk; + reg rst; + + //avalon ST(Streaming) sink: 0 readlatency and 0 readallowence + reg [31:0] data_in_data; + wire data_in_ready; + wire data_in_valid; + reg [1:0] data_in_empty; + reg data_in_startofpacket; + reg data_in_endofpacket; + + //avalon ST(Streaming) source: 0 readlatency and 0 readallowence + wire [15:0] data_out_data; // data_out.data + wire data_out_empty; // .empty + wire data_out_endofpacket; // .endofpacket + wire data_out_startofpacket; // .startofpacket + reg data_out_ready; // .ready + wire data_out_valid; // .valid + + reg [1:0] state; + localparam STATE_IDLE = 2'd0; + localparam STATE_SEND = 2'd1; + localparam STATE_LOC = 2'd3; + + stl2sts stl2sts_dut( + + .clk (clk), + .rst (rst), + + .data_in_data (data_in_data), + .data_in_ready (data_in_ready), + .data_in_valid (data_in_valid), + .data_in_empty (data_in_empty), + .data_in_startofpacket (data_in_startofpacket), + .data_in_endofpacket (data_in_endofpacket), + + .data_out_data (data_out_data), + .data_out_empty (data_out_empty), + .data_out_endofpacket (data_out_endofpacket), + .data_out_startofpacket (data_out_startofpacket), + .data_out_ready (data_out_ready), + .data_out_valid (data_out_valid) + + ); + + initial begin + + clk = 1'b1; + rst = 1'b1; + + data_in_data = 0; + data_in_empty = 2'b0; + data_in_startofpacket = 1'b0; + data_in_endofpacket = 1'b0; + + data_out_ready = 1'b0; + + state = STATE_IDLE; + + + #(CLK_PERIOD*2); + rst = 1'b0; + + //the next sink is ready.. + #(CLK_PERIOD*20); + data_out_ready = 1'b1; + + //start packet + #(CLK_PERIOD*2+1); + data_in_startofpacket = 1'b1; + + + + //end packet + #(CLK_PERIOD*5); + data_in_endofpacket = 1'b1; + + + #(CLK_PERIOD*200); $stop; + + end + + + //clk + always #(CLK_PERIOD/2) clk = ~ clk; + + assign data_in_valid = (state == STATE_SEND || data_in_startofpacket || data_in_endofpacket)? 1'b1 : 1'b0; + always @(posedge clk) begin + case(state) + STATE_IDLE: + begin + if (data_in_startofpacket && data_in_ready) + begin + state <= STATE_SEND; + data_in_data <= data_in_data + 1; + data_in_startofpacket <= 1'b0; + end + end + STATE_SEND: + begin + if (data_in_ready) + begin + if (data_in_endofpacket) begin + state <= STATE_LOC; + data_in_data <= 0; + data_in_endofpacket <= 1'b0; + end else begin + data_in_data <= data_in_data + 1; + end + end + end + STATE_LOC: + begin + state <= STATE_IDLE; + end + endcase + end + +endmodule \ No newline at end of file diff --git a/FPGA_firmware/sensor_algo_qsys/testbench/sts2stl_tb.v b/FPGA_firmware/sensor_algo_qsys/testbench/sts2stl_tb.v new file mode 100644 index 0000000..6b24611 --- /dev/null +++ b/FPGA_firmware/sensor_algo_qsys/testbench/sts2stl_tb.v @@ -0,0 +1,126 @@ +//testbench for sts2stl: ST short 16-bit to ST long 32-bit + +`timescale 1 ns / 1 ns +module sts2stl_tb(); + + localparam CLK_PERIOD = 20; + + reg clk; + reg rst; + + //avalon ST(Streaming) sink: 0 readlatency and 0 readallowence + reg [15:0] data_in_data; + wire data_in_ready; + wire data_in_valid; + reg [1:0] data_in_empty; + reg data_in_startofpacket; + reg data_in_endofpacket; + + //avalon ST(Streaming) source: 0 readlatency and 0 readallowence + wire [31:0] data_out_data; // data_out.data + wire [1:0] data_out_empty; // .empty + wire data_out_endofpacket; // .endofpacket + wire data_out_startofpacket; // .startofpacket + reg data_out_ready; // .ready + wire data_out_valid; // .valid + + reg [1:0] state; + localparam STATE_IDLE = 2'd0; + localparam STATE_SEND = 2'd1; + localparam STATE_LOC = 2'd3; + + sts2stl sts2stl_dut( + + .clk (clk), + .rst (rst), + + .data_in_data (data_in_data), + .data_in_ready (data_in_ready), + .data_in_valid (data_in_valid), + .data_in_empty (data_in_empty), + .data_in_startofpacket (data_in_startofpacket), + .data_in_endofpacket (data_in_endofpacket), + + .data_out_data (data_out_data), + .data_out_empty (data_out_empty), + .data_out_endofpacket (data_out_endofpacket), + .data_out_startofpacket (data_out_startofpacket), + .data_out_ready (data_out_ready), + .data_out_valid (data_out_valid) + + ); + + initial begin + + clk = 1'b1; + rst = 1'b1; + + data_in_data = 0; + data_in_empty = 2'b0; + data_in_startofpacket = 1'b0; + data_in_endofpacket = 1'b0; + + data_out_ready = 1'b0; + + state = STATE_IDLE; + + + #(CLK_PERIOD*2); + rst = 1'b0; + + //the next sink is ready.. + #(CLK_PERIOD*20); + data_out_ready = 1'b1; + + //start packet + #(CLK_PERIOD*2+1); + data_in_startofpacket = 1'b1; + + + + //end packet + #(CLK_PERIOD*6); + data_in_endofpacket = 1'b1; + + + #(CLK_PERIOD*200); $stop; + + end + + + //clk + always #(CLK_PERIOD/2) clk = ~ clk; + + assign data_in_valid = (state == STATE_SEND || data_in_startofpacket || data_in_endofpacket)? 1'b1 : 1'b0; + always @(posedge clk) begin + case(state) + STATE_IDLE: + begin + if (data_in_startofpacket && data_in_ready) + begin + state <= STATE_SEND; + data_in_data <= data_in_data + 1; + data_in_startofpacket <= 1'b0; + end + end + STATE_SEND: + begin + if (data_in_ready) + begin + if (data_in_endofpacket) begin + state <= STATE_LOC; + data_in_data <= 0; + data_in_endofpacket <= 1'b0; + end else begin + data_in_data <= data_in_data + 1; + end + end + end + STATE_LOC: + begin + state <= STATE_IDLE; + end + endcase + end + +endmodule \ No newline at end of file diff --git a/FPGA_firmware/udp_generator.v b/FPGA_firmware/udp_generator.v new file mode 100644 index 0000000..c3b1535 --- /dev/null +++ b/FPGA_firmware/udp_generator.v @@ -0,0 +1,396 @@ +// UDP generator +/* +Takes an input stream and generates a valid UDP/IPv4 packet, then outputs it as a stream which can be directly connected to TSE. + +Remarks: +- Both input and output are Avalon ST ports, 8-bit symbol, 4 symbols per beat +- Start/end of packet signals are REQUIRED. +- Empty signals are discarded. An incoming packet should have a length of 4N. If not, it will be padded with what's on the bus. +- Backpressure is supported and actively used during transfer. Data source must be backpressurizable. +- The transfer is performed on the fly, without buffering. Input gets backpressed for the time of sending headers. +- Size of payload must be known in advance and programmed over Avalon MM interface. +- Longer packets will be cut. Shorter packets will be padded with zeros. +- UDP checksum is not calculated (the price of realtime approach) and filled with zeros. IP header checksum is calculated. +- The Programming interface is an Avalon MM. It's 32-bit wide and allows byte, halfword and word operations. Block transfers are not supported. +- Source MAC is not programmable; it must be filled by TSE. +- Two leading zero bytes are added on front of the packet for 32-bit alignment. TSE settings must comply wit this. +- If transfer is disabled (see control bits), the input will be backpressed all the time. +- Maximum transfer size is about 64K, but limitations of the Ethernet must be taken into account. +- The IPv4 header has the 'Don't fragment' flag set. + +Register map: (byte offsets are given) +UDPGEN_REG_CSR 0 //16 bits 8 bits control(LSB) + 8 bits status(MSB) +UDPGEN_REG_SIZE 2 //16 bits payload size in words +UDPGEN_REG_SRCIP 4 //32 bits source IP, last octet first +UDPGEN_REG_DSTIP 8 //32 bits destination IP. last octet first +UDPGEN_REG_DSTPORT 12 //16 bits destination port +UDPGEN_REG_SRCPORT 14 //16 bits source port +UDPGEN_REG_DSTMAC 16 //2*32 bits destination MAC, last octet first +UDPGEN_REG_RES1 24 //32 bits reserved +UDPGEN_REG_RES2 28 //32 bits reserved + +Control bits: +0: transfer enable +1-7: unused + +Status bits: +0-3: state of the machine +7-4: unused + +*/ + + +`timescale 100 ps / 100 ps +module udp_generator ( + input wire clk_clk, // clk.clk + input wire rst_reset, // rst.reset + input wire [2:0] csr_address, // csr.address + input wire csr_write, // .write + input wire [31:0] csr_writedata, // .writedata + input wire [3:0] csr_byteenable, // .byteenable + input wire csr_read, // .read + output wire [31:0] csr_readdata, // .readdata + input wire [31:0] data_in_data, // data_in.data + output wire data_in_ready, // .ready + input wire data_in_valid, // .valid + input wire [1:0] data_in_empty, // .empty + input wire data_in_endofpacket, // .endofpacket + input wire data_in_startofpacket, // .startofpacket + output wire [31:0] data_out_data, // data_out.data + output wire [1:0] data_out_empty, // .empty + output wire data_out_endofpacket, // .endofpacket + output wire data_out_startofpacket, // .startofpacket + input wire data_out_ready, // .ready + output wire data_out_valid // .valid + ); + + + // *********************** CSR stuff ************************ + + reg [31:0] registers[7:0]; //main register space + wire [31:0] reg0_read; //reg[0] is read indirectly to include status byt(bits 15-8) + + //read logic + assign reg0_read[7:0] = registers[0][7:0]; // Readback of control bits + assign reg0_read[31:16] = registers[0][31:16]; // Readback of payload size + assign reg0_read[15:12] = 0; // Unused bits of the status byte + assign csr_readdata = (csr_address==0) ? reg0_read : registers[csr_address]; + + //write logic + genvar i; + genvar j; + generate + for (i = 0; i < 8; i = i+1) + begin : write_registers //Quartus wants labels for 'for' blocks + for (j = 0; j < 4; j = j+1) + begin : write_bytes + always @(posedge clk_clk or posedge rst_reset) + begin + if (rst_reset) + registers[i][8*j+7:8*j] <= 8'd0; + else + if (csr_byteenable[j] && (csr_address == i) && (csr_write)) + registers[i][8*j+7:8*j] <= csr_writedata[8*j+7:8*j]; + end + end + end + endgenerate + + + // *********************** ST interface *********************** + + reg [4:0] state; //State of the state machine + localparam STATE_IDLE = 0; //waiting for SOP + localparam STATE_MAC1 = 1; //sending first word of MAC header: 00 00 dest_mac[5:4] + localparam STATE_MAC2 = 2; //sending second word of MAC header: dest_mac[3:0] + localparam STATE_MAC3 = 3; //sending zeroes as source MAC msbs: 00 00 00 00 + localparam STATE_MAC4 = 4; //sending zeroes as source MAC lsbs & packet type: 00 00 08 00 + localparam STATE_IP1 = 5; //sending IP ver & header size, DSF, total length 45 00 length[1:0] + localparam STATE_IP2 = 6; //sending IP id, flags (don't fragment), fragm. offset=0 ip_id[1:0] 40 00 + localparam STATE_IP3 = 7; //sending TTL, protocol, header checksum 80 11 checksum[1:0] + localparam STATE_IP4 = 8; //sending source IP src_ip[4:0] + localparam STATE_IP5 = 9; //sending destination IP dst_ip[4:0] + localparam STATE_UDP1 = 10; //sending src & dest port src_port[1:0] dst_port[1:0] + localparam STATE_UDP2 = 11; //sending UDP frame length and (unused) checksum udp_length[1:0] 00 00 + localparam STATE_DATA = 12; //sending packet data but the last word + localparam STATE_PAD = 13; //padding packet with zeros if incoming packet was too short + localparam STATE_DUMP = 14; //dumping tail of incoming packet if it was too long + localparam STATE_END = 15; //transfer finished, just wait one cycle + + reg reg_ready; //registers to drive output pins of ST interfaces + reg reg_valid; + reg [31:0] reg_data; + reg reg_startofpacket; + reg reg_endofpacket; + reg reg_empty; + + //Helper stuff + wire [15:0] udp_length; + wire [15:0] total_length; + wire [19:0] int_checksum; + wire [16:0] int_checksum2; + wire [15:0] header_checksum; + reg [15:0] ip_id; //unique identifier of a packet + reg [15:0] tx_ctr; //counter of sent data words + + assign reg0_read[11:8] = state; //state forwarded to status register + + assign udp_length = 4*registers[0][31:16] + 16'd8; + assign total_length = 4*registers[0][31:16] + 16'd28; + + assign int_checksum = 20'h10511 + total_length + ip_id + registers[1][31:16] + registers[1][15:0] + registers[2][31:16] + registers[2][15:0]; + assign int_checksum2 = int_checksum[15:0] + int_checksum[19:16]; + assign header_checksum = ~(int_checksum2[15:0] + int_checksum2[16]); + + //The state machine + always @(posedge clk_clk or posedge rst_reset) + begin + if (rst_reset) + begin + state <= STATE_IDLE; + ip_id<= 0; + end + else + case(state) + STATE_IDLE: + begin + if (data_in_startofpacket && registers[0][0]) + begin + state <= STATE_MAC1; + ip_id <= ip_id+1; + tx_ctr <= 1; + end + end + STATE_MAC1, STATE_MAC2, STATE_MAC3, STATE_MAC4, STATE_IP1, STATE_IP2, STATE_IP3, STATE_IP4, STATE_IP5, STATE_UDP1, STATE_UDP2: + begin + if (data_out_ready) + state <= state + 1; + end + STATE_DATA: + begin + if (data_out_ready && data_in_valid) + begin + tx_ctr <= tx_ctr+1; + if ((tx_ctr == registers[0][31:16]) && data_in_endofpacket) //last word, size matches + state <= STATE_END; + else if (data_in_endofpacket) //packet too short + state <= STATE_PAD; + else if (tx_ctr == registers[0][31:16]) //packet too long + state <= STATE_DUMP; + end + end + STATE_PAD: + begin + if (data_out_ready) + begin + tx_ctr <= tx_ctr+1; + if (tx_ctr == registers[0][31:16]) + state <= STATE_END; + end + end + STATE_DUMP: + begin + if (data_out_ready && data_in_valid) + begin + if (data_in_endofpacket) + state <= STATE_END; + end + end + + default: + begin + state <= STATE_IDLE; + end + endcase + end + + //Driving bus signals + always @( * ) + begin + if (rst_reset) + begin + reg_ready = 0; + reg_valid = 0; + reg_data = 0; + reg_startofpacket = 0; + reg_endofpacket = 0; + reg_empty = 0; + end + else + case(state) + STATE_IDLE: + begin + reg_ready = 0; + reg_valid = 0; + reg_data = 0; + reg_startofpacket = 0; + reg_endofpacket = 0; + reg_empty = 0; + end + STATE_MAC1: + begin + reg_ready = 0; + reg_valid = 1; + reg_data[31:16] = 0; + reg_data[15:0] = registers[5][15:0]; + reg_startofpacket = 1; + reg_endofpacket = 0; + reg_empty = 0; + end + STATE_MAC2: + begin + reg_ready = 0; + reg_valid = 1; + reg_data = registers[4]; + reg_startofpacket = 0; + reg_endofpacket = 0; + reg_empty = 0; + end + STATE_MAC3: + begin + reg_ready = 0; + reg_valid = 1; + reg_data = 32'h00000000; + reg_startofpacket = 0; + reg_endofpacket = 0; + reg_empty = 0; + end + STATE_MAC4: + begin + reg_ready = 0; + reg_valid = 1; + reg_data = 32'h00000800; + reg_startofpacket = 0; + reg_endofpacket = 0; + reg_empty = 0; + end + STATE_IP1: + begin + reg_ready = 0; + reg_valid = 1; + reg_data[31:16] = 16'h4500; + reg_data[15:0] = total_length; + reg_startofpacket = 0; + reg_endofpacket = 0; + reg_empty = 0; + end + STATE_IP2: + begin + reg_ready = 0; + reg_valid = 1; + reg_data[31:16] = ip_id; + reg_data[15:0] = 16'h4000; + reg_startofpacket = 0; + reg_endofpacket = 0; + reg_empty = 0; + end + STATE_IP3: + begin + reg_ready = 0; + reg_valid = 1; + reg_data[31:16] = 16'h8011; + reg_data[15:0] = header_checksum; + reg_startofpacket = 0; + reg_endofpacket = 0; + reg_empty = 0; + end + STATE_IP4: + begin + reg_ready = 0; + reg_valid = 1; + reg_data = registers[1]; + reg_startofpacket = 0; + reg_endofpacket = 0; + reg_empty = 0; + end + STATE_IP5: + begin + reg_ready = 0; + reg_valid = 1; + reg_data = registers[2]; + reg_startofpacket = 0; + reg_endofpacket = 0; + reg_empty = 0; + end + STATE_UDP1: + begin + reg_ready = 0; + reg_valid = 1; + reg_data = registers[3]; + reg_startofpacket = 0; + reg_endofpacket = 0; + reg_empty = 0; + end + STATE_UDP2: + begin + reg_ready = 0; + reg_valid = 1; + reg_data[31:16] = udp_length; + reg_data[15:0] = 16'h0000; + reg_startofpacket = 0; + reg_endofpacket = 0; + reg_empty = 0; + end + STATE_DATA: + begin + reg_ready = data_out_ready; + reg_valid = data_in_valid; + reg_data = data_in_data; + reg_startofpacket = 0; + if (tx_ctr == registers[0][31:16]) + reg_endofpacket = 1; + else + reg_endofpacket = 0; + reg_empty = 0; + end + STATE_PAD: + begin + reg_ready = 0; + reg_valid = 1; + reg_data = 32'h0; + reg_startofpacket = 0; + if (tx_ctr == registers[0][31:16]) + reg_endofpacket = 1; + else + reg_endofpacket = 0; + reg_empty = 0; + end + STATE_DUMP: + begin + reg_ready = 1; + reg_valid = 0; + reg_data = 0; + reg_startofpacket = 0; + reg_endofpacket = 0; + reg_empty = 0; + end + STATE_END: + begin + reg_ready = 0; + reg_valid = 0; + reg_data = 0; + reg_startofpacket = 0; + reg_endofpacket = 0; + reg_empty = 0; + end + default: + begin + reg_ready = 0; + reg_valid = 0; + reg_data = 0; + reg_startofpacket = 0; + reg_endofpacket = 0; + reg_empty = 0; + end + endcase + end + + + assign data_in_ready = reg_ready; + assign data_out_valid = reg_valid; + assign data_out_data = reg_data; + assign data_out_startofpacket = reg_startofpacket; + assign data_out_endofpacket = reg_endofpacket; + assign data_out_empty = reg_empty; + +endmodule diff --git a/FPGA_firmware/udp_generator_hw.tcl b/FPGA_firmware/udp_generator_hw.tcl new file mode 100644 index 0000000..83a4c89 --- /dev/null +++ b/FPGA_firmware/udp_generator_hw.tcl @@ -0,0 +1,184 @@ +# TCL File Generated by Component Editor 18.0 +# Thu Aug 08 17:47:55 CEST 2019 +# DO NOT MODIFY + + +# +# udp_generator "UDP generator" v1.0 +# M. Dziewiecki 2019.08.08.17:47:55 +# A block for making UDP/IP shell over received data +# + +# +# request TCL package from ACDS 16.1 +# +package require -exact qsys 16.1 + + +# +# module udp_generator +# +set_module_property DESCRIPTION "A block for making UDP/IP shell over received data" +set_module_property NAME udp_generator +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property AUTHOR "M. Dziewiecki" +set_module_property DISPLAY_NAME "UDP generator" +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL udp_generator +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file udp_generator.v VERILOG PATH udp_generator.v TOP_LEVEL_FILE + +add_fileset SIM_VERILOG SIM_VERILOG "" "" +set_fileset_property SIM_VERILOG TOP_LEVEL udp_generator +set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file udp_generator.v VERILOG PATH udp_generator.v + +add_fileset SIM_VHDL SIM_VHDL "" "" +set_fileset_property SIM_VHDL TOP_LEVEL udp_generator +set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property SIM_VHDL ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file udp_generator.v VERILOG PATH udp_generator.v + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clk +# +add_interface clk clock end +set_interface_property clk clockRate 0 +set_interface_property clk ENABLED true +set_interface_property clk EXPORT_OF "" +set_interface_property clk PORT_NAME_MAP "" +set_interface_property clk CMSIS_SVD_VARIABLES "" +set_interface_property clk SVD_ADDRESS_GROUP "" + +add_interface_port clk clk_clk clk Input 1 + + +# +# connection point rst +# +add_interface rst reset end +set_interface_property rst associatedClock clk +set_interface_property rst synchronousEdges DEASSERT +set_interface_property rst ENABLED true +set_interface_property rst EXPORT_OF "" +set_interface_property rst PORT_NAME_MAP "" +set_interface_property rst CMSIS_SVD_VARIABLES "" +set_interface_property rst SVD_ADDRESS_GROUP "" + +add_interface_port rst rst_reset reset Input 1 + + +# +# connection point csr +# +add_interface csr avalon end +set_interface_property csr addressUnits WORDS +set_interface_property csr associatedClock clk +set_interface_property csr associatedReset rst +set_interface_property csr bitsPerSymbol 8 +set_interface_property csr burstOnBurstBoundariesOnly false +set_interface_property csr burstcountUnits WORDS +set_interface_property csr explicitAddressSpan 0 +set_interface_property csr holdTime 0 +set_interface_property csr linewrapBursts false +set_interface_property csr maximumPendingReadTransactions 0 +set_interface_property csr maximumPendingWriteTransactions 0 +set_interface_property csr readLatency 0 +set_interface_property csr readWaitTime 1 +set_interface_property csr setupTime 0 +set_interface_property csr timingUnits Cycles +set_interface_property csr writeWaitTime 0 +set_interface_property csr ENABLED true +set_interface_property csr EXPORT_OF "" +set_interface_property csr PORT_NAME_MAP "" +set_interface_property csr CMSIS_SVD_VARIABLES "" +set_interface_property csr SVD_ADDRESS_GROUP "" + +add_interface_port csr csr_address address Input 3 +add_interface_port csr csr_write write Input 1 +add_interface_port csr csr_writedata writedata Input 32 +add_interface_port csr csr_byteenable byteenable Input 4 +add_interface_port csr csr_read read Input 1 +add_interface_port csr csr_readdata readdata Output 32 +set_interface_assignment csr embeddedsw.configuration.isFlash 0 +set_interface_assignment csr embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment csr embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment csr embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point data_in +# +add_interface data_in avalon_streaming end +set_interface_property data_in associatedClock clk +set_interface_property data_in associatedReset rst +set_interface_property data_in dataBitsPerSymbol 8 +set_interface_property data_in errorDescriptor "" +set_interface_property data_in firstSymbolInHighOrderBits true +set_interface_property data_in maxChannel 0 +set_interface_property data_in readyLatency 0 +set_interface_property data_in symbolsPerBeat 4 +set_interface_property data_in ENABLED true +set_interface_property data_in EXPORT_OF "" +set_interface_property data_in PORT_NAME_MAP "" +set_interface_property data_in CMSIS_SVD_VARIABLES "" +set_interface_property data_in SVD_ADDRESS_GROUP "" + +add_interface_port data_in data_in_data data Input 32 +add_interface_port data_in data_in_ready ready Output 1 +add_interface_port data_in data_in_valid valid Input 1 +add_interface_port data_in data_in_empty empty Input 2 +add_interface_port data_in data_in_endofpacket endofpacket Input 1 +add_interface_port data_in data_in_startofpacket startofpacket Input 1 + + +# +# connection point data_out +# +add_interface data_out avalon_streaming start +set_interface_property data_out associatedClock clk +set_interface_property data_out associatedReset rst +set_interface_property data_out dataBitsPerSymbol 8 +set_interface_property data_out errorDescriptor "" +set_interface_property data_out firstSymbolInHighOrderBits true +set_interface_property data_out maxChannel 0 +set_interface_property data_out readyLatency 0 +set_interface_property data_out symbolsPerBeat 4 +set_interface_property data_out ENABLED true +set_interface_property data_out EXPORT_OF "" +set_interface_property data_out PORT_NAME_MAP "" +set_interface_property data_out CMSIS_SVD_VARIABLES "" +set_interface_property data_out SVD_ADDRESS_GROUP "" + +add_interface_port data_out data_out_data data Output 32 +add_interface_port data_out data_out_empty empty Output 2 +add_interface_port data_out data_out_endofpacket endofpacket Output 1 +add_interface_port data_out data_out_startofpacket startofpacket Output 1 +add_interface_port data_out data_out_ready ready Input 1 +add_interface_port data_out data_out_valid valid Output 1 + diff --git a/FPGA_nios/.gitignore b/FPGA_nios/.gitignore new file mode 100644 index 0000000..afda2b2 --- /dev/null +++ b/FPGA_nios/.gitignore @@ -0,0 +1,77 @@ +#ignore not ours'code +hit_pat_bsp +hit_pat_software.zip +hit_pat/mem_init +hit_pat/obj +hit_pat/create-this-app +hit_pat/.force_relink +hit_pat/.project +#do not ignore this one +!hit_pat_bsp/drivers/src/altera_avalon_tse.c + +*.elf +*.objdump +*.flash +*.map + + +.metadata +bin/ +tmp/ +*.tmp +*.bak +*.swp +*~.nib +local.properties +.settings/ +.loadpath +.recommenders + +# External tool builders +.externalToolBuilders/ + +# Locally stored "Eclipse launch configurations" +*.launch + +# PyDev specific (Python IDE for Eclipse) +*.pydevproject + +# CDT-specific (C/C++ Development Tooling) +.cproject + +# CDT- autotools +.autotools + +# Java annotation processor (APT) +.factorypath + +# PDT-specific (PHP Development Tools) +.buildpath + +# sbteclipse plugin +.target + +# Tern plugin +.tern-project + +# TeXlipse plugin +.texlipse + +# STS (Spring Tool Suite) +.springBeans + +# Code Recommenders +.recommenders/ + +# Annotation Processing +.apt_generated/ +.apt_generated_test/ + +# Scala IDE specific (Scala & Java development for Eclipse) +.cache-main +.scala_dependencies +.worksheet + +# Uncomment this line if you wish to ignore the project description file. +# Typically, this file would be tracked if it contains build/dependency configurations: +#.project \ No newline at end of file diff --git a/FPGA_nios/hit_pat/inc/control.h b/FPGA_nios/hit_pat/inc/control.h new file mode 100644 index 0000000..9342fe9 --- /dev/null +++ b/FPGA_nios/hit_pat/inc/control.h @@ -0,0 +1,46 @@ +/****************************************************************************** +* Copyright * +* Scintillating Fibre Beam Profile Monitor Software by Michal Dziewiecki, * +* Blake Leverington and Liqing Qin is licensed under CC BY 4.0 * +* https://creativecommons.org/licenses/by/4.0/ * +* funded by the Deutsche Forschungsgemeinschaft * +* (DFG, German Research Foundation) Projektnummer 419255448 * +* Project Leader: B.Leverington * +******************************************************************************* +* Create Date - Aug 14, 2017 * +* Author: M.Dziewiecki * +* Module - control.h * +******************************************************************************/ + +#ifndef CONTROL_H_ +#define CONTROL_H_ + +//************************** + +#include "dev_commands.h" + +//************************** + +#define CONTROL_TASK_PRIORITY 10 +#define CONTROL_STACK_SIZE (6144+8192) + +#define CONTROL_MAX_DATA_LENGTH 16 //maximum command data length in WORDS (16-bit) +#define CONTROL_TIMEOUT 1000 //timeout to get command data in unknown time units + +#define CONTROL_PORT 4000 +#define DATA_PORT 4001 + +#define CONTROL_SWAP_BYTES 1 //playing around endianness in PC communication + +typedef struct +{ + unsigned short marker; //must be 0x5555 + unsigned short command; + unsigned short length; +} command_header; + + //Initialize control task +void control_init(); + + +#endif /* CONTROL_H_ */ diff --git a/FPGA_nios/hit_pat/inc/dev_commands.h b/FPGA_nios/hit_pat/inc/dev_commands.h new file mode 100644 index 0000000..ff0f324 --- /dev/null +++ b/FPGA_nios/hit_pat/inc/dev_commands.h @@ -0,0 +1,151 @@ +/****************************************************************************** +* Copyright * +* Scintillating Fibre Beam Profile Monitor Software by Michal Dziewiecki, * +* Blake Leverington and Liqing Qin is licensed under CC BY 4.0 * +* https://creativecommons.org/licenses/by/4.0/ * +* funded by the Deutsche Forschungsgemeinschaft * +* (DFG, German Research Foundation) Projektnummer 419255448 * +* Project Leader: B.Leverington * +******************************************************************************* +* Create Date - Aug 14, 2017 * +* Author: M.Dziewiecki * +* Module - dev_commands.h * +* Edited by L.Qin on Oct 15. 2024 * +******************************************************************************/ + +#ifndef DEV_COMMANDS_H +#define DEV_COMMANDS_H + +//This file is derived from v.1 version and it's great if it's kept compatible +//All sizes are in HALF-WORDS (16-bit)! + +#define COMMAND_PING 0x0001 + //L: 0 + //D: [] + //Return the same + +#define COMMAND_DEBUG_LED_OFF 0x0010 + //L: 0 + //D: []; + //Turn off LED 0 + +#define COMMAND_DEBUG_LED_ON 0x0011 + //L: 0 + //D: []; + //Turn on LED 0 + +// ***DEVICE CONTROL*** + +#define COMMAND_LEDS_DISABLE 0x0110 + //L: 0 + //D: []; + //Disable LED4 blinking. Other LEDs must be explicitly switched off + +#define COMMAND_LEDS_ENABLE 0x0111 + //L: 0 + //D: []; + //Enable LED4 blinking + +// ***TRIGGER SETTING*** + +#define COMMAND_TRIGGER_DISABLE 0x0210 + //L: 0 + //D: []; + //Disable trigger generation in master mode + +#define COMMAND_TRIGGER_ENABLE 0x0211 + //L: 0 + //D: []; + //Enable trigger generation in master mode + +#define COMMAND_TRIGGER_SET_SLAVE 0x0220 + //L: 0 + //D: []; + //Set trigger to slave mode + +#define COMMAND_TRIGGER_SET_MASTER 0x0221 + //L: 0 + //D: []; + //Set trigger to master mode + +#define COMMAND_TRIGGER_SET_PERIOD 0x0230 + //L: 1 L: 0 + //D: [Period_ticks] D: [] + //Set trigger period for master mode in timer ticks + +#define COMMAND_TRIGGER_SET_TINT 0x0240 + //L: 1 L: 0 + //D: [Tint_ticks] D: [] + //Set integration time in timer ticks + +#define COMMAND_SET_GAIN 0x0250 + //L: 1 L:0 + //D: [gain] D: [] + +#define COMMAND_TRIGGER_SET_MASTER_DELAY 0x0260 + //L: 1 L: 0 + //D: [Tdelay_ticks] D: [] + //Set trigger delay time in timer ticks for master mode. + +#define COMMAND_TRIGGER_SET_SLAVE_DELAY 0x0270 + //L: 1 L: 0 + //D: [Tdelay_ticks] D: [] + //Set trigger delay time in timer ticks for slave mode. + + +// ***DAQ CONTROL*** + +#define COMMAND_DAQ_DISABLE 0x0310 + //L: 0 + //D: []; + //Disable sending data + +#define COMMAND_DAQ_ENABLE 0x0311 + //L: 0 + //D: []; + //Enable sending data + +#define COMMAND_DAQ_RESET_COUNTERS 0x0321 + //L: 0 + //D: [] + //Reset synchronization counters + +#define COMMAND_DAQ_FLUSH_DATA 0x0322 + //L: 0 + //D: [] + //Send all remaining data over data socket + +#define COMMAND_DAQ_CONFIG_PEER 0x0331 + //L: 5 L: 0 + //D: [ip ip ip ip port] D: [] + //Set connection settings (peer IP and port) for data transfer + //Warning: IP is sent as 4 shorts with MSB=0! + +// ***SLOW CONTROL*** + +#define COMMAND_SLOWCTRL_SNAPSHOT 0x0410 + //L: 0 L: 10 + //D:[] D: [(Readout of 5 ADC channels as 32-bit integers)] + //Slow control snapshot - read all channels of ADC + + +// ***DATA TRANSFER - SOCKET 1!!!!*** + +#define COMMAND_DATA_TRANSFER 0x8000 + //(no incoming packet) L: 64*5*2 + 6 + //(no incoming packet) D: [Read out single frame] + + +// *** SET_CLUSTER_THRESHOLD *** // +#define COMMAND_SET_CLUSTER_THRESHOLD 0x4001 + //L: 1 +#define COMMAND_SET_CLUSTER_SIZE 0x4002 + //L: 1 +#define COMMAND_SET_CALIBRATION_FACTOR 0x4003 + //L: 2* 16bit + + + + + +#endif // DEV_COMMANDS_H diff --git a/FPGA_nios/hit_pat/inc/network_utilities.h b/FPGA_nios/hit_pat/inc/network_utilities.h new file mode 100644 index 0000000..635bc05 --- /dev/null +++ b/FPGA_nios/hit_pat/inc/network_utilities.h @@ -0,0 +1,49 @@ +/****************************************************************************** +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. All use of this software and documentation is * +* subject to the License Agreement located at the end of this file below. * +****************************************************************************** +* Date - October 24, 2006 * +* Module - network_utilities.h * +* * +******************************************************************************/ + +#ifndef __NETWORK_UTILITIES_H__ +#define __NETWORK_UTILITIES_H__ + +#include + +error_t get_board_mac_addr(unsigned char mac_addr[6]); + +#endif /*__NETWORK_UTILITIES_H__ */ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ diff --git a/FPGA_nios/hit_pat/inc/sensor.h b/FPGA_nios/hit_pat/inc/sensor.h new file mode 100644 index 0000000..dd737e5 --- /dev/null +++ b/FPGA_nios/hit_pat/inc/sensor.h @@ -0,0 +1,76 @@ +/****************************************************************************** +* Copyright * +* Scintillating Fibre Beam Profile Monitor Software by Michal Dziewiecki, * +* Blake Leverington and Liqing Qin is licensed under CC BY 4.0 * +* https://creativecommons.org/licenses/by/4.0/ * +* funded by the Deutsche Forschungsgemeinschaft * +* (DFG, German Research Foundation) Projektnummer 419255448 * +* Project Leader: B.Leverington * +******************************************************************************* +* Create Date - Aug 19, 2019 * +* Author: M.Dziewiecki * +* Module - sensor.h * +* Edited by L.Qin on Oct 15. 2024 * +******************************************************************************/ + + +#ifndef SENSOR_H_ +#define SENSOR_H_ + +//SENSOR_INTERFACE_BASE - this is the base address of the interface + + //byte offsets for registers + #define SENSOR_REG_COMMAND 0 //8 bits + #define SENSOR_REG_STATUS 1 //8 bits + #define SENSOR_REG_SENSORCLK 2 //16 bits, 6 used divider for producing sensor clock ('4' MHz) + #define SESNOR_REG_ADCCNV 3 //8 bits, 6 used time of conversion pulse in ADC clocks, should be > 500 ns + #define SENSOR_REG_DELAY 4 //16 bits, 12 used reset signal delay in 50 MHz clocks + #define SENSOR_REG_SHUTTER 6 //16 bits, 12 used sensor reset ('shutter') time in sensor clocks + #define SENSOR_REG_SERSPEED 8 //8 bits synchro baudrate, 50 for 1 Mbps + #define SENSOR_REG_HEADER_ANYDATA 9 //8 bits any data transmitted with SMA state (8 bits SMA + 8 bits anydata) + #define SENSOR_REG_HEADER_CMD 10 //16 bits command field of the command header transmitted in packet + #define SENSOR_REG_CLUSTER_THRESHOLD 12 //8 bits the threshold for cluster locate, range 0~255 + #define SENSOR_REG_CLUSTER_SIZE 13 //8 bits the size for clluster locate, range 0~255 + #define SENSOR_REG_IN_ALGO_THRESHOLD 14 //8 bits the threshold inside Linear Regression, range 0~255 + #define SENSOR_REG_RESERVED 15 //8 bits not used + + //CSR bitmasks + #define SENSOR_CSR_EN_BITMASK 0x01 //enable operation + #define SENSOR_CSR_GAIN_BITMASK 0x02 //gain selection + #define SENSOR_CSR_ADCK_BITMASK 0x04 //ADC clock divider on/off + #define SENSOR_CSR_RESET_BITMASK 0x08 //Reset all logic + + //Status bitmasks + #define SENSOR_STATUS_SEND 0x01 //Sending over Avalon-ST + #define SENSOR_STATUS_TRG_WAITING 0x02 //The trigger came and is being delayed now + #define SENSOR_STATUS_RESET_ACTIVE 0x04 //The RESET signal for the sensor is active now + #define SENSOR_STATUS_ADC_ACTIVE 0x08 //The ADC is converting data (signal high over all 64 channels) or just finished and waits for reset high + #define SESNOR_STATUS_ADC_FINISHED 0x10 //The ADC waits for reset high + #define SESNOR_STATUS_TX_ACTIVE 0x20 //Sync port is sending + #define SESNOR_STATUS_RX_ACTIVE 0x40 //Sync port is receiving + + + //Register access functions/macros +void sensor_command_bit(alt_u32 base, alt_u8 bitmask, alt_u8 state); +#define sensor_command(base, val) IOWR_8DIRECT(base, SENSOR_REG_COMMAND, val) +#define sensor_set_enable(base, val) sensor_command_bit(base, SENSOR_CSR_EN_BITMASK, val); +#define sensor_set_gain(base, val) sensor_command_bit(base, SENSOR_CSR_GAIN_BITMASK, val); +#define sensor_set_adck(base, val) sensor_command_bit(base, SENSOR_CSR_ADCK_BITMASK, val); +#define sensor_reset(base) { sensor_command_bit(base,SENSOR_CSR_RESET_BITMASK,1); sensor_command_bit(base,SENSOR_CSR_RESET_BITMASK,0); } +#define sensor_set_sensorclk(base, val) IOWR_8DIRECT(base, SENSOR_REG_SENSORCLK, val) +#define sensor_set_adccnv(base, val) IOWR_8DIRECT(base, SESNOR_REG_ADCCNV, val) +#define sensor_set_delay(base, val) IOWR_16DIRECT(base, SENSOR_REG_DELAY, val) +#define sensor_set_shutter(base, val) IOWR_16DIRECT(base, SENSOR_REG_SHUTTER, val) +#define sensor_set_serspeed(base, val) IOWR_8DIRECT(base, SENSOR_REG_SERSPEED, val) +#define sensor_set_header_anydata(base, val) IOWR_8DIRECT(base, SENSOR_REG_HEADER_ANYDATA, val) +#define sensor_set_header_cmd(base, val) IOWR_16DIRECT(base, SENSOR_REG_HEADER_CMD, val) +#define sensor_set_cluster_threshold(base, val) IOWR_8DIRECT(base, SENSOR_REG_CLUSTER_THRESHOLD, val) +#define sensor_set_cluster_size(base, val) IOWR_8DIRECT(base, SENSOR_REG_CLUSTER_SIZE, val) +#define sensor_set_in_algo_threshold(base, val) IOWR_8DIRECT(base, SENSOR_REG_IN_ALGO_THRESHOLD, val) + +//write calibration factor: CALIBRATION_RAM_BASE +#define calibration_ram_set_factor(base, channelID, val) IOWR_16DIRECT(base, channelID*2, val) + +void sensor_preconfigure(alt_u32 base); + +#endif /* SENSOR_H_ */ diff --git a/FPGA_nios/hit_pat/inc/socket_server.h b/FPGA_nios/hit_pat/inc/socket_server.h new file mode 100644 index 0000000..73db3ac --- /dev/null +++ b/FPGA_nios/hit_pat/inc/socket_server.h @@ -0,0 +1,144 @@ +/****************************************************************************** +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. All use of this software and documentation is * +* subject to the License Agreement located at the end of this file below. * +******************************************************************************* * +* Date - October 24, 2006 * +* Module - simple_socket_server.h * +* EXTENSIVELY REWRITTEN by M.Dziewiecki 2019 * * +******************************************************************************/ + +/* + SO THIS IS HOW IT WORKS: + + User can use up to NR_CHANNELS sockets. + First, ethernet_init() must be called from any task. + It will start a special 'listener' thread which is responsible for serving connection requests. + Then: + For each 'channel' (a placeholder for one socket), user may call ethernet_listen() to start listening on a specified port. + After that, ethernet_read() and ethernet_write() can be used. These functions are non-blocking and return 0 if no client is connected. + User can explicitly close connection to a client by calling ethernet_close(); + If another connection request comes when a client is already connected, the old client will be disconnected in favor of the new one. + It means, that only one client can be connected to one channel at a given time. + This weird behaviour is implemented to enable easy killing 'hanging' connections. + Channel re-configuration (i.e. repeated calls of ethernet_listen() for the same channel) is not allowed. + VERY IMPORTANT: + All the above functions (excluding ethernet_init()) must be called from a socket-compatible thread (created with TK_NEWTASK). + All ethernet_* calls are served directly in user's task. Ethernet_init() can be called from any thread after hardware configuration. + */ + + /* Validate supported Software components specified on system library properties page. + */ +#ifndef __SOCKET_SERVER_H__ +#define __SOCKET_SERVER_H__ + +#if !defined (ALT_INICHE) + #error The Simple Socket Server example requires the + #error NicheStack TCP/IP Stack Software Component. Please see the Nichestack + #error Tutorial for details on Nichestack TCP/IP Stack - Nios II Edition, + #error including notes on migrating applications from lwIP to NicheStack. +#endif + +#ifndef __ucosii__ + #error This Simple Socket Server example requires + #error the MicroC/OS-II Intellectual Property Software Component. +#endif + +#if defined (ALT_LWIP) + #error The Simple Socket Server example requires the + #error NicheStack TCP/IP Stack Software Component, and no longer works + #error with the lwIP networking stack. Please see the Altera Nichstack + #error Tutorial for details on Nichestack TCP/IP Stack - Nios II Edition, + #error including notes on migrating applications from lwIP to NicheStack. +#endif + + + + +/* + * Task Priorities: + * MicroC/OS-II only allows one task (thread) per priority number. + */ +#define SS_LISTENER_TASK_PRIORITY 9 //Also, another priority just below this one will be reserved for mutex +#define SS_LISTENER_STACK_SIZE (6144+8192) + +#define NR_CHANNELS 1 //number of listening sockets - as in Wiznet + //Each socket listens on its own port and is able to open one "talking" connection at a time + //If a new connection request comes, the old one gets preempted. This allows us killing dead connections. + + +/* + * If DHCP will not be used, select valid static _BASE_ IP addresses here: + * The contents of DIPSW[3:0] will be added to the last byte of the IP. + * DIPSW[4] is used to enable/disable DHCP. + */ +#define IPADDR0 10 +#define IPADDR1 0 +#define IPADDR2 7 +#define IPADDR3 16 + +#define GWADDR0 10 +#define GWADDR1 0 +#define GWADDR2 7 +#define GWADDR3 1 + +#define MSKADDR0 255 +#define MSKADDR1 255 +#define MSKADDR2 255 +#define MSKADDR3 0 + + +/* + * Here we structure to manage sss communication for a single connection + */ +typedef struct SS_SOCKET +{ + enum { FREE, LISTENING, CONNECTED} state; + int fd_listen; + int fd_conn; + int listenport; +} SSConn; + +// *** User's interface *** + +int ethernet_init(); +/*REMARK: All the below functions can be used ONLY: + 1: After ethernet_init(); + 2: From a task created by TK_NEWTASK. */ +int ethernet_listen(int channel, int port); //Remark: Once we listen on a port, we can not change it +int ethernet_write(int channel, int size, unsigned char* data); +int ethernet_read(int channel, int size, unsigned char* data); //Non-blocking. Returns the number of characters read. +int ethernet_close(int channel); + +#endif /* __SOCKET_SERVER_H__ */ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ diff --git a/FPGA_nios/hit_pat/inc/udpgen.h b/FPGA_nios/hit_pat/inc/udpgen.h new file mode 100644 index 0000000..21bd1c7 --- /dev/null +++ b/FPGA_nios/hit_pat/inc/udpgen.h @@ -0,0 +1,61 @@ +/****************************************************************************** +* Copyright * +* Scintillating Fibre Beam Profile Monitor Software by Michal Dziewiecki, * +* Blake Leverington and Liqing Qin is licensed under CC BY 4.0 * +* https://creativecommons.org/licenses/by/4.0/ * +* funded by the Deutsche Forschungsgemeinschaft * +* (DFG, German Research Foundation) Projektnummer 419255448 * +* Project Leader: B.Leverington * +******************************************************************************* +* Create Date - Aug 7, 2019 * +* Author: M.Dziewiecki * +* Module - udpgen.h * +******************************************************************************/ + +#ifndef UDPGEN_H_ +#define UDPGEN_H_ + +//UDP_GENERATOR_0_BASE + + //byte offsets for registers +#define UDPGEN_REG_CSR 0 //16 bits 8 bits command + 8 bits status +#define UDPGEN_REG_SIZE 2 //16 bits payload size in words +#define UDPGEN_REG_SRCIP 4 //32 bits source IP, last octet first +#define UDPGEN_REG_DSTIP 8 //32 bits destination IP. last octet first +#define UDPGEN_REG_DSTPORT 12 //16 bits destination port +#define UDPGEN_REG_SRCPORT 14 //16 bits source port +#define UDPGEN_REG_DSTMAC 16 //2*32 bits destination MAC, last octet first +#define UDPGEN_REG_RES1 24 //32 bits reserved +#define UDPGEN_REG_RES2 28 //32 bits reserved + + //csr bitmasks +#define UDPGEN_CSR_EN_BITMASK 0x0001 + + + //Register access macros +void udpgen_command_bit(alt_u32 base, alt_u8 bitmask, alt_u8 state); +#define udpgen_command(base, val) IOWR_8DIRECT(base, UDPGEN_REG_CSR, val) +#define udpgen_set_size(base, val) IOWR_16DIRECT(base, UDPGEN_REG_SIZE, val) +#define udpgen_set_srcip(base, val) IOWR_32DIRECT(base, UDPGEN_REG_SRCIP, val) +#define udpgen_set_dstip(base, val) IOWR_32DIRECT(base, UDPGEN_REG_DSTIP, val) +#define udpgen_set_srcip_a(base, val) { for(int i = 0; i < 4; i++) IOWR_8DIRECT(base, UDPGEN_REG_SRCIP+i, val[3-i]); } +#define udpgen_set_dstip_a(base, val) { for(int i = 0; i < 4; i++) IOWR_8DIRECT(base, UDPGEN_REG_DSTIP+i, val[3-i]); } +#define udpgen_set_srcport(base, val) IOWR_16DIRECT(base, UDPGEN_REG_SRCPORT, val) +#define udpgen_set_dstport(base, val) IOWR_16DIRECT(base, UDPGEN_REG_DSTPORT, val) +#define udpgen_set_dstmac_a(base, val) { for(int i = 0; i < 6; i++) IOWR_8DIRECT(base, UDPGEN_REG_DSTMAC+i, val[5-i]); } + +#define udpgen_status(base) IORD_16DIRECT(base, UDPGEN_REG_CSR) +#define udpgen_get_size(base, val) IORD_16DIRECT(base, UDPGEN_REG_SIZE) +#define udpgen_get_srcip(base, val) IORD_32DIRECT(base, UDPGEN_REG_SRCIP) +#define udpgen_get_dstip(base, val) IORD_32DIRECT(base, UDPGEN_REG_DSTIP) +#define udpgen_get_srcport(base, val) IORD_16DIRECT(base, UDPGEN_REG_SRCPORT) +#define udpgen_get_dstport(base, val) IORD_16DIRECT(base, UDPGEN_REG_DSTPORT) +#define udpgen_get_dstmac(base, val) { for(int i = 0; i < 6; i++) val[i] = IORD_8DIRECT(base, UDPGEN_REG_DSTMAC+i); } + + +//****************************************************** + +void udpgen_test(alt_u32 base); + + +#endif /* UDPGEN_H_ */ diff --git a/FPGA_nios/hit_pat/inc/utils.h b/FPGA_nios/hit_pat/inc/utils.h new file mode 100644 index 0000000..c104bf7 --- /dev/null +++ b/FPGA_nios/hit_pat/inc/utils.h @@ -0,0 +1,41 @@ +/****************************************************************************** +* Copyright * +* Scintillating Fibre Beam Profile Monitor Software by Michal Dziewiecki, * +* Blake Leverington and Liqing Qin is licensed under CC BY 4.0 * +* https://creativecommons.org/licenses/by/4.0/ * +* funded by the Deutsche Forschungsgemeinschaft * +* (DFG, German Research Foundation) Projektnummer 419255448 * +* Project Leader: B.Leverington * +******************************************************************************* +* Create Date - Jul 31, 2019 * +* Author: M.Dziewiecki * +* Module - utils.h * +******************************************************************************/ +//Various utils for various purposes +//Mainly wrappers on hardware + + + +#ifndef UTILS_H_ +#define UTILS_H_ + +//Swap opdd/even bytes in a bunch of data to align endianness of shorts +void swap_bytes(unsigned char* array, int size_bytes); +void swap_quad(unsigned char* array, int size_bytes); + +void reload_fpga(); //trigger FPGA reload + +#define TRIGGER_MASTER 1 +#define TRIGGER_SLAVE 0 +void masterslave(alt_u8 master); //set trigger system to master or slave operation +void master_clock_period(alt_u32 period); //set period of the master frame timer +void master_clock_enable(alt_u8 en); //enable/disable pulse generation + +void led_set(alt_u8 led_nr); +void led_clear(alt_u8 led_nr); +void led_toggle(alt_u8 led_nr); +void led4_blink_enable(alt_u8 en); + +void set_delay(alt_u8 master, alt_u16 value); + +#endif /* UTILS_H_ */ diff --git a/FPGA_nios/hit_pat/readme.txt b/FPGA_nios/hit_pat/readme.txt new file mode 100644 index 0000000..27a7415 --- /dev/null +++ b/FPGA_nios/hit_pat/readme.txt @@ -0,0 +1,4 @@ +This software is generated from Simple Socket Server Software Example. +The original Simple Socket Server Software Example is deeply modified. +For BSP generation, the altera_avalon_tse.c is disabled. This file is modifed by M.D in 2019. + diff --git a/FPGA_nios/hit_pat/src/control.c b/FPGA_nios/hit_pat/src/control.c new file mode 100644 index 0000000..bafeddc --- /dev/null +++ b/FPGA_nios/hit_pat/src/control.c @@ -0,0 +1,398 @@ +/****************************************************************************** +* Copyright * +* Scintillating Fibre Beam Profile Monitor Software by Michal Dziewiecki, * +* Blake Leverington and Liqing Qin is licensed under CC BY 4.0 * +* https://creativecommons.org/licenses/by/4.0/ * +* funded by the Deutsche Forschungsgemeinschaft * +* (DFG, German Research Foundation) Projektnummer 419255448 * +* Project Leader: B.Leverington * +******************************************************************************* +* Create Date - Aug 14, 2017 * +* Author: M.Dziewiecki * +* Module - control.c * +* Edited by L.Qin on Oct 15. 2024 * +******************************************************************************/ + + +#include +#include +#include + +/* MicroC/OS-II definitions */ +#include "includes.h" + +#include +#include + +/* Nichestack definitions */ +#include "ipport.h" +#include "tcpport.h" +#include "libport.h" +#include "osport.h" + +#include "socket_server.h" +#include "control.h" +#include "sensor.h" +#include "udpgen.h" +#include "utils.h" + +// **************************** + +extern NET nets[MAXNETS]; /* pointers to the static network structs */ + +// **************************** + +void control_delay() +{ + TK_SLEEP(1); +} + + +// **************************** + + //simple reply +void control_pong(command_header* header) +{ + command_header tmp; + tmp = *header; + swap_bytes((char*)(void*)(&tmp), sizeof(tmp)); + ethernet_write(0, sizeof(command_header), (unsigned char*)(header)); +} + +void control_process_snapshot() +{ + command_header header = {.marker = 0x5555, .command = COMMAND_SLOWCTRL_SNAPSHOT, + .length = 0}; //SLOWCTRL_ADC_CHANNEL_COUNT * sizeof(SLOWCTRL_ADC_DATA_TYPE) / sizeof(unsigned short)}; + swap_bytes((char*)(void*)(&header), sizeof(header)); + ethernet_write(0, sizeof(command_header), (unsigned char*)(&header)); + //ethernet_write(0, SLOWCTRL_ADC_CHANNEL_COUNT*sizeof(SLOWCTRL_ADC_DATA_TYPE), (unsigned char*)slowctrl_adc_buffer); +} + + //helper for the one below +int check_arp(struct arptabent * arp_entry, ip_addr ip) +{ + if (arp_entry->t_pro_addr != ip) + return 0; //bad IP + + for (int i = 0; i < 6; i++) + if (arp_entry->t_phy_addr[i] != 0) + return 1; //non-zero MAC + + return 0; +} + +void control_process_config_peer(unsigned short* data) +{ + ip_addr ip = 0; + ip_addr srcip = 0; + int i; + command_header header = {.marker = 0x5555, .command = COMMAND_DAQ_CONFIG_PEER, .length = 0}; + + for (i = 0; i < 4; i++) + ip = (ip << 8) | (unsigned char)(data[3-i] & 0x00FF); + + //daq_configure_peer_addr(ip, data[4]); + + printf("Querying ARP for %d.%d.%d.%d ...\n",data[0],data[1],data[2],data[3]); + + struct arptabent * arp_entry = find_oldest_arp(ip); + + int pingseq = 0; + while (!check_arp(arp_entry, ip)) //big loop for pinging 10 times + { + printf("ARP entry could not be found, pinging!\n"); + //ping the peer to ARP it. + icmpEcho(ip, NULL, 8, pingseq++); + + for (int i = 0; (i < 5) && (!check_arp(arp_entry, ip)); i++) //small loop for waiting 5 times after each ping + { + TK_SLEEP(10); + arp_entry = find_oldest_arp(ip); + } + + if (pingseq > 10) + { + printf("Could not resolve MAC! The result below is random!\n"); + break; + } + } + + printf("Peer MAC is %02x %02x %02x %02x %02x %02x\n", + arp_entry->t_phy_addr[0], arp_entry->t_phy_addr[1], arp_entry->t_phy_addr[2], + arp_entry->t_phy_addr[3], arp_entry->t_phy_addr[4], arp_entry->t_phy_addr[5]); + + srcip = nets[0]->n_ipaddr; + swap_quad((unsigned char*)(void*)(&srcip), 4); //UDP generator needs such a format + swap_quad((unsigned char*)(void*)(&ip), 4); + + //set up udpgen with correct values + udpgen_set_size(UDP_GENERATOR_BASE, 167); //sensor_interface.v:39 + udpgen_set_srcip(UDP_GENERATOR_BASE, srcip); + udpgen_set_dstip(UDP_GENERATOR_BASE, ip); + udpgen_set_srcport(UDP_GENERATOR_BASE, DATA_PORT); + udpgen_set_dstport(UDP_GENERATOR_BASE, data[4]); + udpgen_set_dstmac_a(UDP_GENERATOR_BASE, arp_entry->t_phy_addr); + + swap_bytes((unsigned char*)(void*)(&header), sizeof(header)); + ethernet_write(0, sizeof(command_header), (unsigned char*)(&header)); +} + + + +// **************************** + + //Receive command header. Return (without loosing data!) if number of received bytes is insufficient. +unsigned char control_get_header(command_header** result) +{ + static command_header header; + static unsigned int bytes_received = 0; + + bytes_received += ethernet_read(0, sizeof(command_header)-bytes_received, (unsigned char*)(&header) + bytes_received); + + if (bytes_received < sizeof(command_header)) + return 0; + + swap_bytes((unsigned char*)(void*)(&header),sizeof(header)); //if the header is complete, swap bytes and return it + *result = &header; + bytes_received = 0; + return 1; +} + + //Receive command data. Return (without loosing data!) if number of received bytes is insufficient. + //Expected data length is given in words! +unsigned char control_get_data(unsigned short expected_length, unsigned short** data) +{ + static unsigned short packet_data[CONTROL_MAX_DATA_LENGTH]; + static unsigned int bytes_received = 0; + + bytes_received += ethernet_read(0, 2*expected_length - bytes_received, (unsigned char*)(&packet_data) + bytes_received); + + if (bytes_received < (2*expected_length)) + return 0; + + *data = packet_data; + bytes_received = 0; + return 1; +} + +// **************************** + +void control_step() +{ + command_header* header; + unsigned short* data; + unsigned int loop_ctr = 0; + + + //get header - at this moment this is blocking! + while (!control_get_header(&header)) + { + control_delay(); + + if (++loop_ctr > CONTROL_TIMEOUT) + { + return; + } + } + + //check start marker + if (header->marker != 0x5555) + return; + + + //get packet data - at this moment this is blocking! + while (!control_get_data(header->length, &data)) + { + control_delay(); + + if (++loop_ctr > CONTROL_TIMEOUT) + { + return; + } + } + //swap data bytes + swap_bytes((unsigned char*)(void*)data, header->length*2); + + switch(header->command) + { + case COMMAND_PING: + printf("COMMAND_PING\n"); + control_pong(header); + break; + case COMMAND_DEBUG_LED_OFF: + printf("COMMAND_DEBUG_LED_OFF\n"); + led_clear(0); + control_pong(header); + break; + case COMMAND_DEBUG_LED_ON: + printf("COMMAND_DEBUG_LED_ON\n"); + led_set(0); + control_pong(header); + break; + + case COMMAND_LEDS_DISABLE: + printf("COMMAND_LEDS_DISABLE\n"); + led4_blink_enable(0); + control_pong(header); + break; + case COMMAND_LEDS_ENABLE: + printf("COMMAND_LEDS_ENABLE\n"); + led4_blink_enable(1); + control_pong(header); + break; + + case COMMAND_TRIGGER_DISABLE: + printf("COMMAND_TRIGGER_DISABLE\n"); + master_clock_enable(0); + control_pong(header); + break; + case COMMAND_TRIGGER_ENABLE: + printf("COMMAND_TRIGGER_ENABLE\n"); + master_clock_enable(1); + control_pong(header); + break; + case COMMAND_TRIGGER_SET_SLAVE: + printf("COMMAND_TRIGGER_SET_SLAVE\n"); + masterslave(TRIGGER_SLAVE); + control_pong(header); + break; + case COMMAND_TRIGGER_SET_MASTER: + printf("COMMAND_TRIGGER_SET_MASTER\n"); + masterslave(TRIGGER_MASTER); + control_pong(header); + break; + case COMMAND_TRIGGER_SET_PERIOD: + printf("COMMAND_TRIGGER_SET_PERIOD: %d\n", data[0]); + master_clock_period((alt_u32)data[0]); //we set only 16 lsbs! + header->length = 0; + control_pong(header); + break; + case COMMAND_TRIGGER_SET_TINT: + printf("COMMAND_TRIGGER_SET_TINT: %d\n", data[0]); + sensor_set_shutter(SENSOR_INTERFACE_BASE, data[0]); + header->length = 0; + control_pong(header); + break; + case COMMAND_SET_GAIN: + printf("COMMAND_SET_GAIN: %d\n", data[0]); + sensor_set_gain(SENSOR_INTERFACE_BASE, data[0]); + header->length = 0; + control_pong(header); + break; + case COMMAND_TRIGGER_SET_MASTER_DELAY: + printf("COMMAND_TRIGGER_SET_MASTER_DELAY: %d\n", data[0]); + set_delay(TRIGGER_MASTER, data[0]); + header->length = 0; + control_pong(header); + break; + case COMMAND_TRIGGER_SET_SLAVE_DELAY: + printf("COMMAND_TRIGGER_SET_SLAVE_DELAY: %d\n", data[0]); + set_delay(TRIGGER_SLAVE, data[0]); + header->length = 0; + control_pong(header); + break; + + case COMMAND_DAQ_DISABLE: + printf("COMMAND_DAQ_DISABLE\n"); + sensor_set_enable(SENSOR_INTERFACE_BASE, 0); + udpgen_command_bit(UDP_GENERATOR_BASE, UDPGEN_CSR_EN_BITMASK,0); + control_pong(header); + break; + case COMMAND_DAQ_ENABLE: + printf("COMMAND_DAQ_ENABLE\n"); + udpgen_command_bit(UDP_GENERATOR_BASE, UDPGEN_CSR_EN_BITMASK,1); + sensor_set_enable(SENSOR_INTERFACE_BASE, 1); + control_pong(header); + break; + case COMMAND_DAQ_RESET_COUNTERS: + printf("COMMAND_DAQ_RESET_COUNTERS\n"); + sensor_reset(SENSOR_INTERFACE_BASE); + control_pong(header); + break; + case COMMAND_DAQ_FLUSH_DATA: + printf("COMMAND_DAQ_FLUSH_DATA\n"); + //nothing + control_pong(header); + break; + case COMMAND_DAQ_CONFIG_PEER: + printf("COMMAND_DAQ_CONFIG_PEER\n"); + control_process_config_peer(data); + break; + + case COMMAND_SLOWCTRL_SNAPSHOT: + printf("COMMAND_SLOWCTRL_SNAPSHOT\n"); + control_process_snapshot(); + break; + + case COMMAND_SET_CLUSTER_THRESHOLD: + printf("COMMAND_SET_CLUSTER_THRESHOLD: %d\n", data[0]); + sensor_set_cluster_threshold(SENSOR_INTERFACE_BASE,data[0]); + header->length = 0; + control_pong(header); + break; + + case COMMAND_SET_CLUSTER_SIZE: + printf("COMMAND_SET_CLUSTER_SIZE: %d\n", data[0]); + sensor_set_cluster_size(SENSOR_INTERFACE_BASE,data[0]); + header->length = 0; + control_pong(header); + break; + + case COMMAND_SET_CALIBRATION_FACTOR: //data[i] is 16 bit unsigned short; calibration factor is 16 bit + if (header->length>=2){ + calibration_ram_set_factor(CALIBRATION_RAM_BASE,data[0],data[1]); //i is channelID + printf("COMMAND_SET_CALIBRATION_FACTOR ChannelIP%d : %d\n", data[0],data[1]); + }else{ + printf("COMMAND_SET_CALIBRATION_FACTOR length: %d\n", header->length); + } + header->length = 0; + control_pong(header); + break; + + + default: + break; + } + +} + +// ******************** The task ***************** + +TK_OBJECT(to_controltask); +TK_ENTRY(ControlTask); + +struct inet_taskinfo controltask = +{ + &to_controltask, + "Control thread", + ControlTask, + CONTROL_TASK_PRIORITY, + CONTROL_STACK_SIZE, +}; + + +void ControlTask(void* param) +{ + printf ("::: Control task started ::: \n"); + ethernet_listen(0, CONTROL_PORT); + + sensor_preconfigure(SENSOR_INTERFACE_BASE); + + //initial calibration factor here + printf("Initiate Calibration Factor 1 to 320 from channel1 to channel320 \n"); + + + for (alt_u32 i = 0; i < 320; i++) { + //pow(2,13)=8192. represent calibration factor 1; range[0.00012,8) + //default calibration factor is 1. + calibration_ram_set_factor(CALIBRATION_RAM_BASE,i,8192); //i is channelID + } + + while(1) + control_step(); +} + +void control_init() +{ + TK_NEWTASK(&controltask); +} diff --git a/FPGA_nios/hit_pat/src/main.c b/FPGA_nios/hit_pat/src/main.c new file mode 100644 index 0000000..e41efc4 --- /dev/null +++ b/FPGA_nios/hit_pat/src/main.c @@ -0,0 +1,161 @@ +/****************************************************************************** +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. All use of this software and documentation is * +* subject to the License Agreement located at the end of this file below. * +******************************************************************************* * +* Date - October 24, 2006 * +* Module - iniche_init.c * +* * * +******************************************************************************/ + +/****************************************************************************** + * NicheStack TCP/IP stack initialization and Operating System Start in main() + * for Simple Socket Server (SSS) example. + * + * This example demonstrates the use of MicroC/OS-II running on NIOS II. + * In addition it is to serve as a good starting point for designs using + * MicroC/OS-II and Altera NicheStack TCP/IP Stack - NIOS II Edition. + * + * Please refer to the Altera NicheStack Tutorial documentation for details on + * this software example, as well as details on how to configure the NicheStack + * TCP/IP networking stack and MicroC/OS-II Real-Time Operating System. + */ + + +#include + +/* MicroC/OS-II definitions */ +#include "includes.h" + +/* Simple Socket Server definitions */ +#include "socket_server.h" +#include "control.h" +//#include "alt_error_handler.h" + + +/* Nichestack definitions */ +#include "ipport.h" +#include "libport.h" +#include "osport.h" + +#define SS_INITIAL_TASK_PRIORITY 5 +/* Definition of task stack for the initial task which will initialize the NicheStack + * TCP/IP Stack and then initialize the rest of the Simple Socket Server example tasks. + */ +OS_STK InitialTaskStk[APP_STACK_SIZE]; + +/* InitialTask will initialize the NicheStack + * TCP/IP Stack and then initialize the rest of the Simple Socket Server example + * RTOS structures and tasks. + */ +void InitialTask(void *task_data) +{ + INT8U error_code; + + /* + * Initialize Altera NicheStack TCP/IP Stack - Nios II Edition specific code. + * NicheStack is initialized from a task, so that RTOS will have started, and + * I/O drivers are available. Two tasks are created: + * "Inet main" task with priority 2 + * "clock tick" task with priority 3 + */ + + alt_iniche_init(); + netmain(); + + /* Wait for the network stack to be ready before proceeding. + * iniche_net_ready indicates that TCP/IP stack is ready, and IP address is obtained. + */ + while (!iniche_net_ready){ + TK_SLEEP(1); + } + + /* Now that the stack is running, perform the application initialization steps */ + + /* Application Specific Task Launching Code Block Begin */ + + printf("\nSocket Server starting up\n"); + + /* Create tasks */ + ethernet_init(); + control_init(); + //TK_NEWTASK(&ssconntask); + + /* Application Specific Task Launching Code Block End */ + + /*This task is deleted because there is no need for it to run again */ + error_code = OSTaskDel(OS_PRIO_SELF); + //alt_uCOSIIErrorHandler(error_code, 0); + + while (1); /* Correct Program Flow should never get here */ +} + +/* Main creates a single task, SSSInitialTask, and starts task scheduler. + */ + +int main (int argc, char* argv[], char* envp[]) +{ + + INT8U error_code; + + /* Clear the RTOS timer */ + OSTimeSet(0); + + /* SSSInitialTask will initialize the NicheStack + * TCP/IP Stack and then initialize the rest of the Simple Socket Server example + * RTOS structures and tasks. + */ + error_code = OSTaskCreateExt(InitialTask, + NULL, + (void *)&InitialTaskStk[APP_STACK_SIZE], + SS_INITIAL_TASK_PRIORITY, + SS_INITIAL_TASK_PRIORITY, + InitialTaskStk, + APP_STACK_SIZE, + NULL, + 0); + //alt_uCOSIIErrorHandler(error_code, 0); + + /* + * As with all MicroC/OS-II designs, once the initial thread(s) and + * associated RTOS resources are declared, we start the RTOS. That's it! + */ + OSStart(); + + + + while(1); /* Correct Program Flow never gets here. */ + + return -1; +} + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ diff --git a/FPGA_nios/hit_pat/src/network_utilities.c b/FPGA_nios/hit_pat/src/network_utilities.c new file mode 100644 index 0000000..1b54881 --- /dev/null +++ b/FPGA_nios/hit_pat/src/network_utilities.c @@ -0,0 +1,456 @@ +/****************************************************************************** +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. All use of this software and documentation is * +* subject to the License Agreement located at the end of this file below. * +****************************************************************************** +* Date - October 24, 2006 * +* Module - network_utilities.c * +* * +******************************************************************************/ + +#include +#include +#include +#include +#include +#include "includes.h" +#include "io.h" +#include + +#include "ipport.h" +#include "tcpport.h" +#include "network_utilities.h" + +#include +#include + +#define IP4_ADDR(ipaddr, a,b,c,d) ipaddr = \ + htonl((((alt_u32)(a & 0xff) << 24) | ((alt_u32)(b & 0xff) << 16) | \ + ((alt_u32)(c & 0xff) << 8) | (alt_u32)(d & 0xff))) + +error_t generate_mac_addr(unsigned char mac_addr[6]); + +/* +* get_mac_addr +* +* Read the MAC address in a board specific way. Prompt user to enter serial +* number to generate MAC address if failed to read from flash. +* +*/ +int get_mac_addr(NET net, unsigned char mac_addr[6]) +{ + error_t error = 0; + + error = get_board_mac_addr(mac_addr); + + if(error) + { + /* Failed read MAC address from flash, prompt user to enter serial + number to generate MAC address. */ + error = generate_mac_addr(mac_addr); + } + return error; +} + +/* + * get_ip_addr() + * + * This routine is called by InterNiche to obtain an IP address for the + * specified network adapter. Like the MAC address, obtaining an IP address is + * very system-dependant and therefore this function is exported for the + * developer to control. + * + * In our system, we are either attempting DHCP auto-negotiation of IP address, + * or we are setting our own static IP, Gateway, and Subnet Mask addresses our + * self. This routine is where that happens. + */ +int get_ip_addr(alt_iniche_dev *p_dev, + ip_addr* ipaddr, + ip_addr* netmask, + ip_addr* gw, + int* use_dhcp) +{ + + alt_u32 sw_state = ~(IORD_ALTERA_AVALON_PIO_DATA(BUTTON_PIO_BASE)); + + printf("Input state: 0x%08lx\n", sw_state); + + /*if (sw_state & 0x100) + { + *use_dhcp = 1; + IP4_ADDR(*ipaddr, 0, 0, 0, 0); + IP4_ADDR(*gw, 0, 0, 0, 0); + IP4_ADDR(*netmask, 0, 0, 0, 0); + printf("DHCP enabled.\n"); + } + else + {*/ + *use_dhcp = 0; + IP4_ADDR(*ipaddr, IPADDR0, IPADDR1, IPADDR2, IPADDR3+((sw_state>>4)&0x0F)); + IP4_ADDR(*gw, GWADDR0, GWADDR1, GWADDR2, GWADDR3); + IP4_ADDR(*netmask, MSKADDR0, MSKADDR1, MSKADDR2, MSKADDR3); + printf("DHCP disabled.\n"); + printf("Static IP Address is %d.%d.%d.%d\n", + ip4_addr1(*ipaddr), + ip4_addr2(*ipaddr), + ip4_addr3(*ipaddr), + ip4_addr4(*ipaddr)); + //} + + + /* Non-standard API: return 1 for success */ + return 1; +} + +int FindLastFlashSectorOffset( + alt_u32 *pLastFlashSectorOffset); + +alt_u32 last_flash_sector_offset; +alt_u32 last_flash_sector; + +/* +* get_serial_number +* +* Prompt user to enter 9-digit serial number. +* +*/ +alt_u32 get_serial_number (void) +{ + alt_u32 ser_num = 0; + char serial_number[9]; + int i = 0; + + while(!ser_num) + { + printf("Please enter your 9-digit serial number. This is printed on a \n"); + printf("label under your Nios dev. board. The first 3 digits of the \n"); + printf("label are ASJ and the serial number follows this.\n -->"); + + for(i=0; i<9; i++) + { + serial_number[i] = getchar(); + putchar(serial_number[i]); + + /* Handle backspaces. How civilized. */ + if ((serial_number[i] == 0x08) && (i >= 0)) + { + i--; + } + } + printf("\n"); + + for(i=0; i<9; i++) + { + if (isdigit(serial_number[i])) + { + ser_num *= 10; + ser_num += serial_number[i] - '0'; + } + else + { + ser_num = 0; + printf("Serial number only contains decimal digits and is non-zero\n"); + break; + } + } + } + + return ser_num; +} + +/* + * generate_and_store_mac_addr() + * + * This routine is called when, upon program initialization, we discover + * that there is no valid network settings (including MAC address) programmed + * into flash memory at the last flash sector. If it is not safe to use the + * contents of this last sector of flash, the user is prompted to + * enter the serial number at the console. A MAC address is then + * generated using 0xFF followed by the last 2 bytes of the serial number + * appended to Altera's Vendor ID, an assigned MAC address range with the first + * 3 bytes of 00:07:ED. For example, if the Nios Development Board serial + * number is 040800017, the corresponding ethernet number generated will be + * 00:07:ED:FF:8F:11. + * + * It should be noted that this number, while unique, will likely differ from + * the also unique (but now lost forever) MAC address programmed into the + * development board on the production line. + * + * As we are erasing the entire flash sector, we'll re-program it with not + * only the MAC address, but static IP, subnet, gateway, and "Use DHCP" + * sections. These fail-safe static settings are compatible with previous + * Nios Ethernet designs, and allow the "factory-safe" design to behave + * as expected if the last flash sector is erased. + */ +error_t generate_and_store_mac_addr() +{ + error_t error = -1; + alt_u32 ser_num = 0; + char flash_content[32]; + alt_flash_fd* flash_handle; + + printf("Can't read the MAC address from your board (this probably means\n"); + printf("that your flash was erased). We will assign you a MAC address and\n"); + printf("static network settings\n\n"); + + ser_num = get_serial_number(); + + if (ser_num) + { + /* This says the image is safe */ + flash_content[0] = 0xfe; + flash_content[1] = 0x5a; + flash_content[2] = 0x0; + flash_content[3] = 0x0; + + /* This is the Altera Vendor ID */ + flash_content[4] = 0x0; + flash_content[5] = 0x7; + flash_content[6] = 0xed; + + /* Reserverd Board identifier for erase boards */ + flash_content[7] = 0xFF; + flash_content[8] = (ser_num & 0xff00) >> 8; + flash_content[9] = ser_num & 0xff; + + /* Then comes a 16-bit "flags" field */ + flash_content[10] = 0xFF; + flash_content[11] = 0xFF; + + /* Then comes the static IP address */ + flash_content[12] = IPADDR0; + flash_content[13] = IPADDR1; + flash_content[14] = IPADDR2; + flash_content[15] = IPADDR3; + + /* Then comes the static nameserver address */ + flash_content[16] = 0xFF; + flash_content[17] = 0xFF; + flash_content[18] = 0xFF; + flash_content[19] = 0xFF; + + /* Then comes the static subnet mask */ + flash_content[20] = MSKADDR0; + flash_content[21] = MSKADDR1; + flash_content[22] = MSKADDR2; + flash_content[23] = MSKADDR3; + + /* Then comes the static gateway address */ + flash_content[24] = GWADDR0; + flash_content[25] = GWADDR1; + flash_content[26] = GWADDR2; + flash_content[27] = GWADDR3; + + /* And finally whether to use DHCP - set all bits to be safe */ + flash_content[28] = 0xFF; + flash_content[29] = 0xFF; + flash_content[30] = 0xFF; + flash_content[31] = 0xFF; + + /* Write the MAC address to flash */ + flash_handle = alt_flash_open_dev(EXT_FLASH_AVL_MEM_NAME); + if (flash_handle) + { + alt_write_flash(flash_handle, + last_flash_sector_offset, + flash_content, + 32); + alt_flash_close_dev(flash_handle); + error = 0; + } + } + + return error; +} + +/* + * generate_mac_addr() + * + * This routine is called when failed to read MAC address from flash (i.e: no + * flash on the board). The user is prompted to enter the serial number at the + * console. A MAC address is then generated using 0xFF followed by the last 2 + * bytes of the serial number appended to Altera's Vendor ID, an assigned MAC + * address range with the first 3 bytes of 00:07:ED. For example, if the Nios + * Development Board serial number is 040800017, the corresponding ethernet + * number generated will be 00:07:ED:FF:8F:11. + * + */ +error_t generate_mac_addr(unsigned char mac_addr[6]) +{ + error_t error = -1; + alt_u32 ser_num = 0; + + printf("\nCan't read the MAC address from your board. We will assign you\n"); + printf("a MAC address.\n\n"); + + ser_num = get_serial_number(); + + if (ser_num) + { + /* This is the Altera Vendor ID */ + mac_addr[0] = 0x0; + mac_addr[1] = 0x7; + mac_addr[2] = 0xed; + + /* Reserverd Board identifier */ + mac_addr[3] = 0xFF; + mac_addr[4] = (ser_num & 0xff00) >> 8; + mac_addr[5] = ser_num & 0xff; + + printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", + mac_addr[0], + mac_addr[1], + mac_addr[2], + mac_addr[3], + mac_addr[4], + mac_addr[5]); + + error = 0; + } + + return error; +} + +/* +* get_board_mac_addr +* +* Read the MAC address in a board specific way +* +*/ +error_t get_board_mac_addr(unsigned char mac_addr[6]) +{ + error_t error = 0; + alt_u32 signature; + + /* Get the flash sector with the MAC address. */ + error = FindLastFlashSectorOffset(&last_flash_sector_offset); + if (!error) + last_flash_sector = EXT_FLASH_AVL_MEM_BASE + last_flash_sector_offset; + + /* This last_flash_sector region of flash is examined to see if + * valid network settings are present, indicated by a signature of 0x00005afe at + * the first address of the last flash sector. This hex value is chosen as the + * signature since it looks like the english word "SAFE", meaning that it is + * safe to use these network address values. + */ + if (!error) + { + signature = IORD_32DIRECT(last_flash_sector, 0); + if (signature != 0x00005afe) + { + error = generate_and_store_mac_addr(); + } + } + + if (!error) + { + mac_addr[0] = IORD_8DIRECT(last_flash_sector, 4); + mac_addr[1] = IORD_8DIRECT(last_flash_sector, 5); + mac_addr[2] = IORD_8DIRECT(last_flash_sector, 6); + mac_addr[3] = IORD_8DIRECT(last_flash_sector, 7); + mac_addr[4] = IORD_8DIRECT(last_flash_sector, 8); + mac_addr[5] = IORD_8DIRECT(last_flash_sector, 9); + + printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", + mac_addr[0], + mac_addr[1], + mac_addr[2], + mac_addr[3], + mac_addr[4], + mac_addr[5]); + + } + + return error; +} + +/******************************************************************************* + * + * Flash service functions. + * + ******************************************************************************/ + +#include "sys/alt_flash.h" +#include "sys/alt_flash_dev.h" + +/* + * FindLastFlashSectorOffset + * + * <-- pLastFlashSectorOffset Offset of last sector in flash. + * + * This function finds the offset to the last sector in flash and returns it + * in pLastFlashSectorOffset. + */ + +int FindLastFlashSectorOffset( + alt_u32 *pLastFlashSectorOffset) +{ + alt_flash_fd *fd; + flash_region *regions; + int numRegions; + flash_region *pLastRegion; + int lastFlashSectorOffset; + int n; + int error = 0; + + /* Open the flash device. */ + fd = alt_flash_open_dev(EXT_FLASH_AVL_MEM_NAME); + if (fd <= 0) + error = -1; + + /* Get the flash info. */ + if (!error) + error = alt_get_flash_info(fd, ®ions, &numRegions); + + /* Find the last flash sector. */ + if (!error) + { + pLastRegion = &(regions[0]); + for (n = 1; n < numRegions; n++) + { + if (regions[n].offset > pLastRegion->offset) + pLastRegion = &(regions[n]); + } + lastFlashSectorOffset = pLastRegion->offset + + pLastRegion->region_size + - pLastRegion->block_size; + } + + /* Return results. */ + if (!error) + *pLastFlashSectorOffset = lastFlashSectorOffset; + + return (error); +} + + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ diff --git a/FPGA_nios/hit_pat/src/sensor.c b/FPGA_nios/hit_pat/src/sensor.c new file mode 100644 index 0000000..762f6aa --- /dev/null +++ b/FPGA_nios/hit_pat/src/sensor.c @@ -0,0 +1,62 @@ +/****************************************************************************** +* Copyright * +* Scintillating Fibre Beam Profile Monitor Software by Michal Dziewiecki, * +* Blake Leverington and Liqing Qin is licensed under CC BY 4.0 * +* https://creativecommons.org/licenses/by/4.0/ * +* funded by the Deutsche Forschungsgemeinschaft * +* (DFG, German Research Foundation) Projektnummer 419255448 * +* Project Leader: B.Leverington * +******************************************************************************* +* Create Date - Aug 19, 2019 * +* Author: M.Dziewiecki * +* Module - sensor.c * +* Edited by L.Qin on Oct 15. 2024 * +******************************************************************************/ + + +#include +#include "includes.h" +#include +#include +#include + +/* Nichestack definitions */ +#include "ipport.h" +#include "libport.h" +#include "osport.h" + +#include "utils.h" +#include "dev_commands.h" +#include "sensor.h" + + +void sensor_command_bit(alt_u32 base, alt_u8 bitmask, alt_u8 state) +{ + alt_u8 tmp = IORD_8DIRECT(base, SENSOR_REG_COMMAND); + if (state) + tmp |= bitmask; + else + tmp &= ~bitmask; + IOWR_8DIRECT(base, SENSOR_REG_COMMAND, tmp); +} + + +void sensor_preconfigure(alt_u32 base) +{ + printf(" *** Preconfiguring sensor module... \n"); + + sensor_command(base, 0); //disable + sensor_set_sensorclk(base, 6); //sensor clock - 3.57 MHz + sensor_set_adccnv(base, 31); //conversion delay - default + sensor_set_delay(base, 1); //trigger delay - default + sensor_set_shutter(base, 100); //integration time - dummy default + sensor_set_serspeed(base, 50); //synchro serial port - 1 Mbps + sensor_set_header_anydata(base, 0x00); //should be 0 + sensor_set_header_cmd(base, COMMAND_DATA_TRANSFER); //command header, must be this one + sensor_command(base, 1); //enable, gain low, SCLK full + + sensor_set_cluster_threshold(base, 10); //default cluster threshold 10 + sensor_set_cluster_size(base, 4); //default cluster size 4 + sensor_set_in_algo_threshold(base, 4); //default algo threshold 4 + +} diff --git a/FPGA_nios/hit_pat/src/socket_server.c b/FPGA_nios/hit_pat/src/socket_server.c new file mode 100644 index 0000000..ba4f205 --- /dev/null +++ b/FPGA_nios/hit_pat/src/socket_server.c @@ -0,0 +1,332 @@ +/****************************************************************************** +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. All use of this software and documentation is * +* subject to the License Agreement located at the end of this file below. * +******************************************************************************* +* Date - October 24, 2006 * +* Module - simple_socket_server.c * +* * +******************************************************************************/ + +/****************************************************************************** + * Simple Socket Server (SSS) example. + * + * This example demonstrates the use of MicroC/OS-II running on NIOS II. + * In addition it is to serve as a good starting point for designs using + * MicroC/OS-II and Altera NicheStack TCP/IP Stack - NIOS II Edition. + * + * -Known Issues + * None. + * + * Please refer to the Altera NicheStack Tutorial documentation for details on this + * software example, as well as details on how to configure the NicheStack TCP/IP + * networking stack and MicroC/OS-II Real-Time Operating System. + */ + +#include +#include +#include + +/* MicroC/OS-II definitions */ +#include "includes.h" + +/* Simple Socket Server definitions */ +#include "socket_server.h" +//#include "alt_error_handler.h" + +/* Nichestack definitions */ +#include "ipport.h" +#include "tcpport.h" +#include "libport.h" +#include "osport.h" + + +static OS_EVENT *mutex; + +static SSConn connections[NR_CHANNELS]; + +TK_OBJECT(to_sslistenertask); +TK_ENTRY(SSListenerTask); + +struct inet_taskinfo sslistenertask = +{ + &to_sslistenertask, + "socket server listener", + SSListenerTask, + SS_LISTENER_TASK_PRIORITY, + SS_LISTENER_STACK_SIZE, +}; + +// ******************************************************** + + + +void ss_reset_connection(SSConn* conn) //called e.g. after closing a socket +{ + conn->fd_conn = -1; + conn->state = LISTENING; + return; +} + +void ss_initialize_connection(SSConn* conn) //called only at initialization +{ + conn->fd_conn = -1; + conn->fd_listen = -1; + conn->listenport = -1; + conn->state = FREE; + return; +} + +void ss_handle_accept(SSConn* conn) +{ + int socket; + int len; + struct sockaddr_in incoming_addr; + + INT8U err; + OSMutexPend(mutex, 0, &err); + + len = sizeof(incoming_addr); + + //Close old connection if needed + if ((conn)->fd_conn != -1) + { + printf("[ss_handle_accept] closing old connection\n"); + close(conn->fd_conn); + ss_reset_connection(conn); + } + + if((socket=accept(conn->fd_listen,(struct sockaddr*)&incoming_addr,&len))<0) + { + //alt_NetworkErrorHandler(EXPANDED_DIAGNOSIS_CODE, + // "[ss_handle_accept] accept failed"); + } + else + { + (conn)->fd_conn = socket; + (conn)->state = CONNECTED; + printf("[ss_handle_accept] accepted connection request from %s\n", + inet_ntoa(incoming_addr.sin_addr)); + } + + OSMutexPost(mutex); + return; +} + +/* + * Listener Task() + */ +void SSListenerTask(void* param) +{ + + int max_socket = 0; + BSD_TIMEVAL_T timeout; + + INT8U err; + OSMutexPend(mutex, 0, &err); //wrap initialization in a mutex - just in case... + + timeout.tv_sec = 0; + timeout.tv_usec = 100000; + + fd_set readfds; //set of descriptors + + for (int ch = 0; ch < NR_CHANNELS; ch++) + if ((connections[ch].fd_listen = socket(AF_INET, SOCK_STREAM, 0)) < 0) + { + //printf("Errot initializing socket #%d!\n", ch); + //alt_NetworkErrorHandler(EXPANDED_DIAGNOSIS_CODE,"[sss_task] Socket creation failed"); + } + + //Binding etc. is done by ethernet_listen() + + OSMutexPost(mutex); + + //Now run in loop to handle incoming requests on all listening ports + while(1) + { + FD_ZERO(&readfds); + + for (int ch = 0; ch < NR_CHANNELS; ch++) + if (connections[ch].listenport >= 0) + { + FD_SET(connections[ch].fd_listen, &readfds); + if (connections[ch].fd_listen >= max_socket) + max_socket = connections[ch].fd_listen+1; + } + + if (max_socket == 0) + TK_SLEEP(10); //just sleep a bit if nothing to do + else + { + select(max_socket, &readfds, NULL, NULL, &timeout); //we must timeout from time to time to find newly set-up channels + + for (int ch = 0; ch < NR_CHANNELS; ch++) + if (FD_ISSET(connections[ch].fd_listen, &readfds)) + ss_handle_accept(&(connections[ch])); + } + } /* while(1) */ + + //never come here +} + + +// ****************** User interface ******************** + +int ethernet_init() +{ + INT8U err; + mutex = OSMutexCreate(SS_LISTENER_TASK_PRIORITY-1, &err); + + + for (int ch = 0; ch < NR_CHANNELS; ch++) + ss_initialize_connection(&(connections[ch])); + + TK_NEWTASK(&sslistenertask); + return 0; +} + +int ethernet_listen(int channel, int port) +{ + struct sockaddr_in addr; + + INT8U err; + OSMutexPend(mutex, 0, &err); + + addr.sin_family = AF_INET; + addr.sin_port = htons(port); + addr.sin_addr.s_addr = INADDR_ANY; + + if (bind(connections[channel].fd_listen,(struct sockaddr *)&addr,sizeof(addr)) < 0) + { + //alt_NetworkErrorHandler(EXPANDED_DIAGNOSIS_CODE,"[sss_task] Bind failed"); + OSMutexPost(mutex); + return -1; + } + + if (listen(connections[channel].fd_listen,1) < 0) + { + //alt_NetworkErrorHandler(EXPANDED_DIAGNOSIS_CODE,"[sss_task] Listen failed"); + OSMutexPost(mutex); + return -2; + } + + ss_reset_connection(&(connections[channel])); + connections[channel].listenport = port; + printf("[sss_task] Simple Socket Server listening on port %d\n", port); + + OSMutexPost(mutex); + return 0; +} + +int ethernet_write(int channel, int size, unsigned char* data) +{ + int result; + + INT8U err; + OSMutexPend(mutex, 0, &err); + + if (connections[channel].fd_conn == -1) //socket is closed or channel unconfigured + { + OSMutexPost(mutex); + return 0; + } + + result = (int)send(connections[channel].fd_conn, data, size, 0); + if (result == -1) + { + printf("[ethernet_write] closing connection due to error\n"); + close(connections[channel].fd_conn); //close connection on error + ss_reset_connection(&(connections[channel])); + result = 0; + } + + OSMutexPost(mutex); + return result; +} + +int ethernet_read(int channel, int size, unsigned char* data) +{ + fd_set readfds; //set of descriptors + int max_socket; + BSD_TIMEVAL_T timeout; + int result; + + INT8U err; + OSMutexPend(mutex, 0, &err); + + if (connections[channel].fd_conn == -1) //socket is closed or channel unconfigured + { + OSMutexPost(mutex); + return 0; + } + + //prepare call parameters + FD_ZERO(&readfds); + FD_SET(connections[channel].fd_conn, &readfds); + max_socket = connections[channel].fd_conn+1; + timeout.tv_sec = 0; + timeout.tv_usec = 0; + + //check for data + if (select(max_socket, &readfds, NULL, NULL, &timeout)) + if (FD_ISSET(connections[channel].fd_conn, &readfds)) + { + result = (int)recv(connections[channel].fd_conn, data, size, 0); + if (result == -1) + { + printf("[ethernet_read] closing connection due to error\n"); + close(connections[channel].fd_conn); //close connection on error + ss_reset_connection(&(connections[channel])); + result = 0; + } + OSMutexPost(mutex); + return result; + } + + OSMutexPost(mutex); + return 0; +} + +int ethernet_close(int channel) +{ + INT8U err; + OSMutexPend(mutex, 0, &err); + + close(connections[channel].fd_conn); + ss_reset_connection(&(connections[channel])); + + OSMutexPost(mutex); + return 0; +} + + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ diff --git a/FPGA_nios/hit_pat/src/tse_my_system.c b/FPGA_nios/hit_pat/src/tse_my_system.c new file mode 100644 index 0000000..a6cbb18 --- /dev/null +++ b/FPGA_nios/hit_pat/src/tse_my_system.c @@ -0,0 +1,12 @@ +#ifdef ALT_INICHE + #include "ipport.h" +#endif + +#include "system.h" +#include "altera_avalon_tse.h" +#include "altera_avalon_tse_system_info.h" + +alt_tse_system_info tse_mac_device[MAXNETS] = { + TSE_SYSTEM_EXT_MEM_NO_SHARED_FIFO(ETH_TSE, 0, MSGDMA_TX, MSGDMA_RX, TSE_PHY_AUTO_ADDRESS, &marvell_cfg_rgmii, DESCRIPTOR_MEMORY) + +}; diff --git a/FPGA_nios/hit_pat/src/udpgen.c b/FPGA_nios/hit_pat/src/udpgen.c new file mode 100644 index 0000000..fea3e45 --- /dev/null +++ b/FPGA_nios/hit_pat/src/udpgen.c @@ -0,0 +1,59 @@ +/****************************************************************************** +* Copyright * +* Scintillating Fibre Beam Profile Monitor Software by Michal Dziewiecki, * +* Blake Leverington and Liqing Qin is licensed under CC BY 4.0 * +* https://creativecommons.org/licenses/by/4.0/ * +* funded by the Deutsche Forschungsgemeinschaft * +* (DFG, German Research Foundation) Projektnummer 419255448 * +* Project Leader: B.Leverington * +******************************************************************************* +* Create Date - Aug 19, 2019 * +* Author: M.Dziewiecki * +* Module - udpgen.c * +******************************************************************************/ + + +#include +#include "includes.h" +#include +#include +#include + +/* Nichestack definitions */ +#include "ipport.h" +#include "libport.h" +#include "osport.h" + +#include "utils.h" + +#include "udpgen.h" + +//******************************************************************* + + +void udpgen_command_bit(alt_u32 base, alt_u8 bitmask, alt_u8 state) +{ + alt_u8 tmp = IORD_8DIRECT(base, UDPGEN_REG_CSR); + if (state) + tmp |= bitmask; + else + tmp &= ~bitmask; + IOWR_8DIRECT(base, UDPGEN_REG_CSR, tmp); +} + +void udpgen_test(alt_u32 base) +{ + printf (" *** Setting up UDP generator... \n"); + + unsigned char dstmac[] = {0x18, 0xd6, 0xc7, 0x05, 0xaa, 0x63}; + unsigned char srcip[] = {10,0,7,17}; + unsigned char dstip[] = {10,0,7,1}; + + udpgen_command(UDP_GENERATOR_BASE, 0x01); + udpgen_set_size(UDP_GENERATOR_BASE, 16); + udpgen_set_srcip_a(UDP_GENERATOR_BASE, srcip); + udpgen_set_dstip_a(UDP_GENERATOR_BASE, dstip); + udpgen_set_srcport(UDP_GENERATOR_BASE, 4096); + udpgen_set_dstport(UDP_GENERATOR_BASE, 4097); + udpgen_set_dstmac_a(UDP_GENERATOR_BASE, dstmac); +} diff --git a/FPGA_nios/hit_pat/src/utils.c b/FPGA_nios/hit_pat/src/utils.c new file mode 100644 index 0000000..24557cd --- /dev/null +++ b/FPGA_nios/hit_pat/src/utils.c @@ -0,0 +1,138 @@ +/****************************************************************************** +* Copyright * +* Scintillating Fibre Beam Profile Monitor Software by Michal Dziewiecki, * +* Blake Leverington and Liqing Qin is licensed under CC BY 4.0 * +* https://creativecommons.org/licenses/by/4.0/ * +* funded by the Deutsche Forschungsgemeinschaft * +* (DFG, German Research Foundation) Projektnummer 419255448 * +* Project Leader: B.Leverington * +******************************************************************************* +* Create Date - Jul 31, 2019 * +* Author: M.Dziewiecki * +* Module - utils.c * +******************************************************************************/ + + +#include +#include "includes.h" +#include +#include + +/* Nichestack definitions */ +#include "ipport.h" +#include "libport.h" +#include "osport.h" + +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_timer_regs.h" +#include "utils.h" + +#include "sensor.h" + +alt_u16 delays[2]; +alt_u8 mastermode; + +//****************************************************** + +//Swap odd/even bytes in a bunch of data to align endianness of shorts +void swap_bytes(unsigned char* array, int size_bytes) +{ + for (int i = 0; i < size_bytes; i+= 2) + { + unsigned char tmp = array[i]; + array[i] = array[i+1]; + array[i+1] = tmp; + } +} +//The same, but four-byte-wise +void swap_quad(unsigned char* array, int size_bytes) +{ + unsigned char buf[4]; + + for (int i = 0; i < size_bytes; i+= 4) + { + memcpy(buf, array+i, 4); + for (int j = 0; j < 4; j++) + array[i+j] = buf[3-j]; + } +} + + //trigger FPGA reload +void reload_fpga() +{ + printf("$$$$ RECONFIGURING FPGA!!! $$$$\n"); + //TK_SLEEP(100); //let it print the message before dying + //IOWR(DUAL_BOOT_BASE, 0, 0x1); + printf("*** DISABLED! ***\n"); +} + +void masterslave(alt_u8 master) +{ + if (master) + IOWR_ALTERA_AVALON_PIO_SET_BITS(OUTPUT_PIO_BASE, 0x80); + else + IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(OUTPUT_PIO_BASE, 0x80); + mastermode = master; + set_delay(mastermode, delays[mastermode]); //update sensor delay setting +} + +void master_clock_period(alt_u32 period) +{ + //set period + IOWR_ALTERA_AVALON_TIMER_PERIODL(FRAME_TIMER_BASE, (alt_u16)(period & 0xFFFF)); + IOWR_ALTERA_AVALON_TIMER_PERIODH(FRAME_TIMER_BASE, (alt_u16)((period>>16) & 0xFFFF)); + //start timer in continuous mode + //IOWR_ALTERA_AVALON_TIMER_CONTROL(FRAME_TIMER_BASE, + // ALTERA_AVALON_TIMER_CONTROL_CONT_MSK); +} + +void master_clock_enable(alt_u8 en) +{ + alt_u16 tmp = 0; // = IORD_ALTERA_AVALON_TIMER_CONTROL(FRAME_TIMER_BASE); + + if (en) + tmp |= ALTERA_AVALON_TIMER_CONTROL_START_MSK | ALTERA_AVALON_TIMER_CONTROL_CONT_MSK; + else + tmp |= ALTERA_AVALON_TIMER_CONTROL_STOP_MSK; + + IOWR_ALTERA_AVALON_TIMER_CONTROL(FRAME_TIMER_BASE,tmp); +} + +void led_set(alt_u8 led_nr) +{ + if (led_nr > 4) + return; + IOWR_ALTERA_AVALON_PIO_SET_BITS(OUTPUT_PIO_BASE, 1< 4) + return; + IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(OUTPUT_PIO_BASE, 1< 4) + return; + alt_u32 tmp = IORD_ALTERA_AVALON_PIO_DATA(OUTPUT_PIO_BASE); + tmp ^= (1< +#include +#include +#include + +void no_printf (char *fmt, ...) {} + +#ifdef __ALTERA_MSGDMA + + +/** @Function Description - Perform initialization steps on transaction info structure to prepare it for . + * use by the library functions with two MSGDMAs and extra initialization Flags + * @API Type: Internal + * @param mi Main Device Structure. + * @param mac_base Base Address of the Control interface for the TSE MAC + * @param tx_msgdma MSGDMA device handle for TSE transmit data path + * @param rx_msgdma MSGDMA device handle for TSE receive data path + * @param cfgflags initialization flags for the device + * @return 0 + */ + +alt_32 tse_mac_initTransInfo2( tse_mac_trans_info *mi, + alt_u32 mac_base, + alt_32 tx_msgdma, + alt_32 rx_msgdma, + alt_32 cfgflags) { + + mi->base = (np_tse_mac*)mac_base; + mi->tx_msgdma = (alt_msgdma_dev *)tx_msgdma; + mi->rx_msgdma = (alt_msgdma_dev *)rx_msgdma; + mi->cfgflags = cfgflags; + return SUCCESS; +} + +/** @Function Description - Synchronous MSGDMA copy from buffer memory into transmit FIFO. Waits until + * SGDMA has completed. Raw function without any error checks. + * @API Type: Internal + * @param mi Main Device Structure. + * @param txDesc Pointer to the transmit MSGDMA descriptor + * @return actual bytes transferred if ok, else error (-1) + */ +alt_32 tse_mac_sTxWrite( tse_mac_trans_info *mi, + alt_msgdma_standard_descriptor *txDesc) +{ + + alt_32 timeout; + alt_u8 result = 0; + + // Make sure DMA controller is not busy from a former command + // and TX is able to accept data + timeout = 0; + while ( (IORD_ALTERA_MSGDMA_CSR_STATUS(mi->tx_msgdma->csr_base) & + ALTERA_MSGDMA_CSR_BUSY_MASK) ) { + if(timeout++ == ALTERA_TSE_MSGDMA_BUSY_TIME_OUT_CNT) { + tse_dprintf(4, "WARNING : TX MSGDMA Timeout\n"); + return ENP_RESOURCE; // avoid being stuck here + } + } + + // Start MSGDMA (blocking call) + alt_dcache_flush(txDesc,sizeof(alt_msgdma_standard_descriptor)); + result = alt_msgdma_standard_descriptor_sync_transfer( + mi->tx_msgdma, + txDesc); + + if (result != 0) { + tse_dprintf(4, "WARNING :alt_msgdma_standard_descriptor_sync_transfer Error code 0x%x\n",result); + return -1; + } + + return 0; +} + + +/** @Function Description - Asynchronous MSGDMA copy from rxFIFO into given buffer memory area. + * Raw function without any error checks. + * + * @API Type: Internal + * @param mi Main Device Structure. + * @param rxDesc Pointer to the receive MSGDMA descriptor list + * @return 0 if ok, else error (-1) + * + * Note: At the point of this function call return, + * the MSGDMA asynchronous operation may not have been + * completed yet, so the function does not return + * the actual bytes transferred for current descriptor + */ +alt_32 tse_mac_aRxRead( + tse_mac_trans_info *mi, + alt_msgdma_prefetcher_standard_descriptor *rxDesc) +{ + alt_u8 result; + + result = alt_msgdma_start_prefetcher_with_std_desc_list( + mi->rx_msgdma, + rxDesc,0,0,1,1); + + if (result != 0) { return -1; } + + return SUCCESS; +} + +/** @Function Description - Asynchronous MSGDMA transfer from buffer to txFIFO + * + * + * @API Type: Internal + * @param mi Main Device Structure. + * @param rxDesc Pointer to the transmit MSGDMA descriptor list + * @return 0 if ok, or (-1) if error + * + */ +alt_32 tse_mac_aTxWrite( + tse_mac_trans_info *mi, + alt_msgdma_prefetcher_standard_descriptor *txDesc) +{ + alt_u8 result; + + result = alt_msgdma_start_prefetcher_with_std_desc_list( + mi->tx_msgdma, + txDesc,0,0,1,1); + + if (result != 0) { return -1; } + + return SUCCESS; +} + + +#endif /* __ALTERA_MSGDMA */ + +/* Definition of TSE system */ +extern alt_tse_system_info tse_mac_device[MAXNETS]; + +/* PHY profile*/ +alt_tse_phy_profile *pphy_profiles[TSE_MAX_PHY_PROFILE]; +alt_u8 phy_profile_count = 0; + +/* MAC in TSE system */ +alt_tse_mac_group *pmac_groups[TSE_MAX_MAC_IN_SYSTEM]; +alt_u8 mac_group_count = 0; +alt_u8 max_mac_system = MAXNETS; + +/******************************* + * + * Public API for TSE Driver + * + *******************************/ + +/* @Function Description: Perform a software Reset. Reset operation will ocur with some latency. + * COMMAND_CONFIG register is restored after reset. + * @API Type: Public + * @param pmac Pointer to the TSE MAC Control Interface Base address +*/ +alt_32 tse_mac_SwReset(np_tse_mac *pmac) +{ + alt_32 timeout; + alt_32 cc; + + cc = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac); + + // set reset and Gig-Speed bits to make sure we have an incoming clock on + // tx side. If there is a 10/100 PHY, we will still have a valid clock on + // tx_clk no matter what setting we have here, but on a Gig phy the + // MII clock may be missing. + IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac,(ALTERA_TSEMAC_CMD_SW_RESET_MSK | ALTERA_TSEMAC_CMD_ETH_SPEED_MSK)); + + + // wait for completion with fallback in case there is no PHY or it is + // not connected and hence might not provide any clocks at all. + timeout=0; + while( (IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac) & ALTERA_TSEMAC_CMD_SW_RESET_MSK) != 0 && timeout < ALTERA_TSE_SW_RESET_TIME_OUT_CNT) timeout++; + + IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac,cc); // Restore + return SUCCESS; +} + + + +/* @Function Description: Perform switching of the TSE MAC into MII (10/100) mode. + * COMMAND_CONFIG register is restored after reset. + * @API Type: Public + * @param pmac Pointer to the TSE MAC Control Interface Base address +*/ +alt_32 tse_mac_setMIImode(np_tse_mac *pmac) +{ + alt_32 helpvar; + + helpvar = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac); + helpvar &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; + + IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac,helpvar); + return SUCCESS; +} + + +/* @Function Description: Perform switching of the TSE MAC into GMII (Gigabit) mode. + * COMMAND_CONFIG register is restored after reset. + * @API Type: Public + * @param pmac Pointer to the TSE MAC Control Interface Base address + */ +alt_32 tse_mac_setGMIImode(np_tse_mac *pmac) +{ + alt_32 helpvar; + + helpvar = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac); + helpvar |= ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; + + IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac,helpvar); + return SUCCESS; +} + + + +/* @Function Description - Add additional PHYs which are not supported by default into PHY profile for PHY detection and auto negotiation + * + * @API TYPE - Public + * @param phy pointer to alt_tse_phy_profile structure describing PHY registers + * @return index of PHY added in PHY profile on success, else return ALTERA_TSE_MALLOC_FAILED if memory allocation failed + * PHY which are currently supported by default : Marvell 88E1111, Marvell Quad PHY 88E1145, National DP83865, and National DP83848C + */ +alt_32 alt_tse_phy_add_profile(alt_tse_phy_profile *phy) +{ + alt_32 i; + + /* search PHY profile for same ID */ + for(i = 0; i < phy_profile_count; i++) + { + if(pphy_profiles[i]->oui == phy->oui && pphy_profiles[i]->model_number == phy->model_number) + { + tse_dprintf(4, "WARNING : PHY OUI 0x%06x, PHY Model Number 0x%02x already exist in PHY profile\n", (int) phy->oui, phy->model_number); + tse_dprintf(4, "In case of same PHY OUI and PHY Model Number in profile, first added PHY setting will be used\n"); + } + } + + /* Allocate memory space to store the profile */ + pphy_profiles[phy_profile_count] = (alt_tse_phy_profile *) malloc(sizeof(alt_tse_phy_profile)); + if(!pphy_profiles[phy_profile_count]) { + tse_dprintf(1, "ERROR : Unable to allocate memory for pphy_profile[%d]\n", phy_profile_count); + return ALTERA_TSE_MALLOC_FAILED; + } + + /* Store PHY information */ + *pphy_profiles[phy_profile_count] = *phy; + strcpy(pphy_profiles[phy_profile_count]->name, phy->name); + + phy_profile_count++; + + return phy_profile_count - 1; +} + +/* @Function Description - Add TSE System to tse_mac_device[] array to customize TSE System + * + * @API TYPE - Public + * @param psys_mac pointer to alt_tse_system_mac structure describing MAC of the system + * @param psys_msgdma pointer to alt_tse_system_msgdma structure describing MSGDMA of the system + * @param psys_mem pointer to alt_tse_system_desc_mem structure describing Descriptor Memory of the system + * @param psys_phy pointer to alt_tse_system_phy structure describing PHY of the system + * @return SUCCESS on success + * ALTERA_TSE_MALLOC_FAILED if memory allocation failed + * ALTERA_TSE_SYSTEM_DEF_ERROR if definition of system incorrect or pointer == NULL + */ +alt_32 alt_tse_system_add_sys( + alt_tse_system_mac *psys_mac, + alt_tse_system_msgdma *psys_msgdma, + alt_tse_system_desc_mem *psys_mem, + alt_tse_system_shared_fifo *psys_shared_fifo, + alt_tse_system_phy *psys_phy ) { + + int i; + int loop_end; + + alt_tse_system_mac *pmac = psys_mac; + alt_tse_system_msgdma *pmsgdma = psys_msgdma; + alt_tse_system_desc_mem *pmem = psys_mem; + alt_tse_system_shared_fifo *pfifo = psys_shared_fifo; + alt_tse_system_phy *pphy = psys_phy; + + static alt_8 tse_system_count = 0; + + /* Determine number of loop */ + /* Run at least one for non-multi-channel MAC */ + if(pmac->tse_num_of_channel == 0) { + loop_end = 1; + } + else if(pmac->tse_num_of_channel > 0) { + loop_end = pmac->tse_num_of_channel; + } + else { + tse_dprintf(2, "ERROR : Invalid number of channel specified!\n"); + return ALTERA_TSE_SYSTEM_DEF_ERROR; + } + + for(i = 0; i < loop_end; i++) { + + /* Make sure the boundary of array is not exceeded */ + if(tse_system_count >= MAXNETS) { + tse_dprintf(2, "ERROR : Number of TSE System added exceed the size of array!\n"); + tse_dprintf(2, "ERROR : Size of array = %d, Number of TSE System = %d\n", MAXNETS, tse_system_count); + } + + /* Add MAC info to alt_tse_system_info structure */ + if(pmac == 0) { + tse_dprintf(2, "ERROR : MAC system structure == NULL\n"); + tse_dprintf(2, "ERROR : Please pass in correct pointer to alt_tse_system_add_sys()\n"); + return ALTERA_TSE_SYSTEM_DEF_ERROR; + } + + tse_mac_device[tse_system_count].tse_mac_base = pmac->tse_mac_base + (i * 0x400); + tse_mac_device[tse_system_count].tse_tx_depth = pmac->tse_tx_depth; + tse_mac_device[tse_system_count].tse_rx_depth = pmac->tse_rx_depth; + tse_mac_device[tse_system_count].tse_use_mdio = pmac->tse_use_mdio; + tse_mac_device[tse_system_count].tse_en_maclite = pmac->tse_en_maclite; + tse_mac_device[tse_system_count].tse_maclite_gige = pmac->tse_maclite_gige; + tse_mac_device[tse_system_count].tse_multichannel_mac = pmac->tse_multichannel_mac; + tse_mac_device[tse_system_count].tse_num_of_channel = pmac->tse_num_of_channel; + tse_mac_device[tse_system_count].tse_mdio_shared = pmac->tse_mdio_shared; + tse_mac_device[tse_system_count].tse_number_of_mac_mdio_shared = pmac->tse_number_of_mac_mdio_shared; + tse_mac_device[tse_system_count].tse_pcs_ena = pmac->tse_pcs_ena; + tse_mac_device[tse_system_count].tse_pcs_sgmii = pmac->tse_pcs_sgmii; + + /* Add MSGDMA info to alt_tse_system_info structure */ + if(pmsgdma == 0) { + tse_dprintf(2, "ERROR : MSGDMA system structure == NULL\n"); + tse_dprintf(2, "ERROR : Please pass in correct pointer to alt_tse_system_add_sys() for tse_mac_device[%d]\n", tse_system_count); + return ALTERA_TSE_SYSTEM_DEF_ERROR; + } + + tse_mac_device[tse_system_count].tse_msgdma_tx = (char *) malloc(strlen(pmsgdma->tse_msgdma_tx) + 1); + if(!tse_mac_device[tse_system_count].tse_msgdma_tx) { + tse_dprintf(1, "ERROR : Unable to allocate memory for tse_mac_device[%d].tse_msgdma_tx\n", tse_system_count); + return ALTERA_TSE_MALLOC_FAILED; + } + strcpy(tse_mac_device[tse_system_count].tse_msgdma_tx, pmsgdma->tse_msgdma_tx); + + tse_mac_device[tse_system_count].tse_msgdma_rx = (char *) malloc(strlen(pmsgdma->tse_msgdma_rx) + 1); + if(!tse_mac_device[tse_system_count].tse_msgdma_rx) { + tse_dprintf(1, "ERROR : Unable to allocate memory for tse_mac_device[%d].tse_msgdma_rx\n", tse_system_count); + return ALTERA_TSE_MALLOC_FAILED; + } + strcpy(tse_mac_device[tse_system_count].tse_msgdma_rx, pmsgdma->tse_msgdma_rx); + + tse_mac_device[tse_system_count].tse_msgdma_rx_irq = pmsgdma->tse_msgdma_rx_irq; + + /* Add descriptor memory info to alt_tse_system_info structure */ + if(pmem == 0) { + tse_mac_device[tse_system_count].ext_desc_mem = TSE_INT_DESC_MEM; + tse_mac_device[tse_system_count].desc_mem_base = TSE_INT_DESC_MEM; + } + else { + tse_mac_device[tse_system_count].ext_desc_mem = pmem->ext_desc_mem; + tse_mac_device[tse_system_count].desc_mem_base = pmem->desc_mem_base; + } + + /* Add shared fifo info to alt_tse_system_info structure */ + if(pfifo == 0) { + tse_mac_device[tse_system_count].use_shared_fifo = TSE_NO_SHARED_FIFO; + tse_mac_device[tse_system_count].tse_shared_fifo_tx_ctrl_base = TSE_NO_SHARED_FIFO; + tse_mac_device[tse_system_count].tse_shared_fifo_tx_stat_base = TSE_NO_SHARED_FIFO; + tse_mac_device[tse_system_count].tse_shared_fifo_tx_depth = TSE_NO_SHARED_FIFO; + + tse_mac_device[tse_system_count].tse_shared_fifo_rx_ctrl_base = TSE_NO_SHARED_FIFO; + tse_mac_device[tse_system_count].tse_shared_fifo_rx_stat_base = TSE_NO_SHARED_FIFO; + tse_mac_device[tse_system_count].tse_shared_fifo_rx_depth = TSE_NO_SHARED_FIFO; + } + else { + tse_mac_device[tse_system_count].use_shared_fifo = pfifo->use_shared_fifo; + tse_mac_device[tse_system_count].tse_shared_fifo_tx_ctrl_base = pfifo->tse_shared_fifo_tx_ctrl_base; + tse_mac_device[tse_system_count].tse_shared_fifo_tx_stat_base = pfifo->tse_shared_fifo_tx_stat_base; + tse_mac_device[tse_system_count].tse_shared_fifo_tx_depth = pfifo->tse_shared_fifo_tx_depth; + + tse_mac_device[tse_system_count].tse_shared_fifo_rx_ctrl_base = pfifo->tse_shared_fifo_rx_ctrl_base; + tse_mac_device[tse_system_count].tse_shared_fifo_rx_stat_base = pfifo->tse_shared_fifo_rx_stat_base; + tse_mac_device[tse_system_count].tse_shared_fifo_rx_depth = pfifo->tse_shared_fifo_rx_depth; + } + + /* Add PHY info to alt_tse_system_info structure */ + if(pphy == 0) { + tse_mac_device[tse_system_count].tse_phy_mdio_address = TSE_PHY_AUTO_ADDRESS; + tse_mac_device[tse_system_count].tse_phy_cfg = 0; + } + else { + tse_mac_device[tse_system_count].tse_phy_mdio_address = pphy->tse_phy_mdio_address; + tse_mac_device[tse_system_count].tse_phy_cfg = pphy->tse_phy_cfg; + } + + /* Point to next structure */ + pmsgdma++; + if(pmem) pmem++; + if(pfifo) pfifo++; + if(pphy) pphy++; + + tse_system_count++; + max_mac_system = tse_system_count; + } + + return SUCCESS; + +} + +/* @Function Description - Enable MDIO sharing for multiple single channel MAC + * + * @API TYPE - Public + * @param psys_mac_list pointer to array of alt_tse_system_mac structure sharing MDIO block + * @param number_of_mac number of MAC sharing MDIO block + * @return SUCCESS on success + * ALTERA_TSE_SYSTEM_DEF_ERROR if definition of system incorrect or pointer == NULL + * Multi-channel MAC not supported + */ +alt_32 alt_tse_sys_enable_mdio_sharing(alt_tse_system_mac **psys_mac_list, alt_u8 number_of_mac) { + alt_32 i; + alt_32 j; + + alt_tse_system_mac *psys_mac; + + for(i = 0; i < number_of_mac; i++) { + psys_mac = psys_mac_list[i]; + + if(psys_mac == 0) { + tse_dprintf(2, "ERROR : MAC system structure == NULL\n"); + tse_dprintf(2, "ERROR : Please pass in correct pointer to alt_tse_sys_enable_mdio_sharing()\n"); + return ALTERA_TSE_SYSTEM_DEF_ERROR; + } + + for(j = 0; j < max_mac_system; j++) { + + if(psys_mac->tse_mac_base == tse_mac_device[j].tse_mac_base) { + if(tse_mac_device[j].tse_multichannel_mac) { + tse_dprintf(2, "ERROR : MDIO sharing supported by default for Multi-channel MAC\n"); + tse_dprintf(2, "ERROR : Do not include Multi-channel MAC in the MAC List\n"); + return ALTERA_TSE_SYSTEM_DEF_ERROR; + } + + tse_mac_device[j].tse_mdio_shared = 1; + tse_mac_device[j].tse_number_of_mac_mdio_shared = number_of_mac; + } + } + } + + return SUCCESS; +} + +/* @Function Description: Get the common speed supported by all PHYs connected to the MAC within the same group + * @API Type: Public + * @param pmac Pointer to the TSE MAC Control Interface Base address + * @return common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if no common speed found + */ +alt_32 alt_tse_mac_get_common_speed(np_tse_mac *pmac) { + alt_tse_mac_group *pmac_group = alt_tse_get_mac_info(pmac)->pmac_group; + return alt_tse_phy_get_common_speed(pmac_group); +} + +/* @Function Description: Set the common speed to all PHYs connected to the MAC within the same group + * @API Type: Public + * @param pmac Pointer to the TSE MAC Control Interface Base address + * common_speed common speed supported by all PHYs + * @return common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if invalid common speed specified + */ +alt_32 alt_tse_mac_set_common_speed(np_tse_mac *pmac, alt_32 common_speed) { + alt_tse_mac_group *pmac_group = alt_tse_get_mac_info(pmac)->pmac_group; + return alt_tse_phy_set_common_speed(pmac_group, common_speed); +} + + +/******************************** + * + * Internal API for TSE Driver + * + *******************************/ + +/* @Function Description: Get the index of alt_tse_system_info structure in tse_mac_device[] + * @API Type: Internal + * @param psys_info Pointer to the alt_tse_system_info structure + * @return Index of alt_tse_system_info structure in tse_mac_device[] + */ +alt_32 alt_tse_get_system_index(alt_tse_system_info *psys_info) { + alt_32 i; + + for(i = 0; i < max_mac_system; i++) { + if(psys_info == &tse_mac_device[i]) { + return i; + } + } + return ALTERA_TSE_NO_INDEX_FOUND; +} + +/* @Function Description: Get the index of alt_tse_mac_group structure in pmac_groups[] + * @API Type: Internal + * @param pmac_group Pointer to the alt_tse_mac_group structure + * @return Index of alt_tse_mac_group structure in pmac_groups[] + */ +alt_32 alt_tse_get_mac_group_index(alt_tse_mac_group *pmac_group) { + alt_32 i; + + for(i = 0; i < mac_group_count; i++) { + if(pmac_group == pmac_groups[i]) { + return i; + } + } + return ALTERA_TSE_NO_INDEX_FOUND; +} + + +/* @Function Description: Get the index of alt_tse_mac_info structure in pmac_groups[]->pmac_info[] + * @API Type: Internal + * @param pmac_group Pointer to the alt_tse_mac_info structure + * @return Index of alt_tse_mac_info structure in pmac_groups[]->pmac_info[] + */ +alt_32 alt_tse_get_mac_info_index(alt_tse_mac_info *pmac_info) { + alt_32 i; + + for(i = 0; i < pmac_info->pmac_group->channel; i++) { + if(pmac_info == pmac_info->pmac_group->pmac_info[i]) { + return i; + } + } + + return ALTERA_TSE_NO_INDEX_FOUND; +} + +/* @Function Description: Get the pointer of alt_tse_mac_info structure in pmac_groups[]->pmac_info[] + * @API Type: Internal + * @param pmac Pointer to the TSE MAC Control Interface Base address + * @return Pointer to alt_tse_mac_info structure in pmac_groups[]->pmac_info[] + */ +alt_tse_mac_info *alt_tse_get_mac_info(np_tse_mac *pmac) { + alt_32 i; + alt_32 j; + alt_tse_mac_group *pmac_group = 0; + alt_tse_mac_info *pmac_info = 0; + + for(i = 0; i < mac_group_count; i++) { + pmac_group = pmac_groups[i]; + for(j = 0; j < pmac_group->channel; j++) { + pmac_info = pmac_group->pmac_info[j]; + if(((np_tse_mac *) pmac_info->psys_info->tse_mac_base) == pmac) { + return pmac_info; + } + } + } + + return 0; +} + +/* @Function Description: Perform switching of the TSE MAC speed. + * COMMAND_CONFIG register is restored after reset. + * @API Type: Internal + * @param pmac Pointer to the TSE MAC Control Interface Base address + * @param speed 2 = 1000 Mbps, 1 = 100 Mbps, 0 = 10 Mbps + * @return ENP_PARAM if invalid speed specified, else return SUCCESS + */ +alt_32 alt_tse_mac_set_speed(np_tse_mac *pmac, alt_u8 speed) +{ + alt_32 helpvar; + + helpvar = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac); + + /* 1000 Mbps */ + if(speed == TSE_PHY_SPEED_1000) { + helpvar |= ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; + helpvar &= ~ALTERA_TSEMAC_CMD_ENA_10_MSK; + } + /* 100 Mbps */ + else if(speed == TSE_PHY_SPEED_100) { + helpvar &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; + helpvar &= ~ALTERA_TSEMAC_CMD_ENA_10_MSK; + } + /* 10 Mbps */ + else if(speed == TSE_PHY_SPEED_10) { + helpvar &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; + helpvar |= ALTERA_TSEMAC_CMD_ENA_10_MSK; + } + else { + return ENP_PARAM; + } + + IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac, helpvar); + return SUCCESS; +} + +/* @Function Description: Perform switching of the TSE MAC duplex mode. + * COMMAND_CONFIG register is restored after reset. + * @API Type: Internal + * @param pmac Pointer to the TSE MAC Control Interface Base address + * @param duplex 1 = Full Duplex, 0 = Half Duplex + * @return ENP_PARAM if invalid duplex specified, else return SUCCESS + */ +alt_32 alt_tse_mac_set_duplex(np_tse_mac *pmac, alt_u8 duplex) +{ + alt_32 helpvar; + + helpvar = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac); + + /* Half Duplex */ + if(duplex == TSE_PHY_DUPLEX_HALF) { + helpvar |= ALTERA_TSEMAC_CMD_HD_ENA_MSK; + } + /* Full Duplex */ + else if(duplex == TSE_PHY_DUPLEX_FULL) { + helpvar &= ~ALTERA_TSEMAC_CMD_HD_ENA_MSK; + } + else { + return ENP_PARAM; + } + + IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac, helpvar); + return SUCCESS; + +} + + + +/** @Function Description - Determine link speed our PHY negotiated with our link partner. + * This is fully vendor specific depending on the PHY you are using. + * + * @API TYPE - Internal + * @param tse.mi.base MAC register map. + * @return + * ---------------------------------------------------------------------------------- + * | BIT | Value: Description | + * ---------------------------------------------------------------------------------- + * | 31-23 | Reserved | + * | 23 | 1: Argument *pmac not found from the list of MAC detected during init | + * | 22 | 1: No MDIO used by the MAC | + * | 21 | 1: No PHY detected | + * | 20 | 1: No common speed found for Multi-port MAC | + * | 19 | 1: PHY auto-negotiation not completed | + * | 18 | 1: No PHY profile match the detected PHY | + * | 17 | 1: PHY Profile not defined correctly | + * | 16 | 1: Invalid speed read from PHY | + * | 4-15 | Reserved | + * | 3 | 1: 10 Mbps link | + * | 2 | 1: 100 Mbps link | + * | 1 | 1: 1000 Mbps link | + * | 0 | 1: Full Duplex 0: Half Duplex | + * ---------------------------------------------------------------------------------- + * + * If the link speed cannot be determined, it is fall back to 100 Mbps (customizable by changing ALTERA_TSE_MAC_SPEED_DEFAULT) + * Full duplex (customizable by changing ALTERA_TSE_DUPLEX_MODE_DEFAULT) + */ + +#define ALT_TSE_SPEED_DUPLEX(speed, duplex) ((duplex & 0x01) |\ + (((speed == TSE_PHY_SPEED_1000) ? 1 : 0) << 1) | \ + (((speed == TSE_PHY_SPEED_100) ? 1 : 0) << 2) | \ + (((speed == TSE_PHY_SPEED_10) ? 1 : 0) << 3) | \ + ((speed == TSE_PHY_SPEED_INVALID) ? ALT_TSE_E_INVALID_SPEED : 0)) + +alt_32 getPHYSpeed(np_tse_mac *pmac) { + + alt_u8 speed = ALTERA_TSE_MAC_SPEED_DEFAULT; + alt_u8 duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT; /* 1 = full ; 0 = half*/ + alt_32 result = ALT_TSE_SPEED_DUPLEX(speed, duplex); + + alt_tse_phy_info *pphy = 0; + alt_tse_mac_info *pmac_info = 0; + alt_tse_mac_group *pmac_group = 0; + alt_tse_system_info *psys = 0; + + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = 0; + alt_8 mac_group_index = 0; + + /* initialized PHYs only once */ + static alt_u8 is_init = 0; + if(is_init == 0) { + alt_tse_phy_init(); + is_init = 1; + } + + /* Look for pmac_group and pmac_info structure based on pmac or iface */ + pmac_info = alt_tse_get_mac_info(pmac); + + if(pmac_info == 0) { + speed = ALTERA_TSE_MAC_SPEED_DEFAULT; + duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT; + result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_NO_PMAC_FOUND; + tse_dprintf(2, "ERROR : [getPHYSpeed] pmac not found from list of pmac_info[]! Speed = %s Mbps, Duplex = %s\n", speed == TSE_PHY_SPEED_1000 ? "1000" : + speed == TSE_PHY_SPEED_100 ? "100" : + speed == TSE_PHY_SPEED_10 ? "10" : "Unknown", + duplex == 1 ? "Full" : "Half"); + tse_dprintf(2, "ERROR : [getPHYSpeed] Please define tse_mac_device[] correctly\n"); + return result; + } + + pphy = pmac_info->pphy_info; + pmac_group = pmac_info->pmac_group; + psys = pmac_info->psys_info; + + mac_info_index = alt_tse_get_mac_info_index(pmac_info); + mac_group_index = alt_tse_get_mac_group_index(pmac_group); + + /* MDIO is not used */ + if (pmac_group->pmac_info[0]->psys_info->tse_use_mdio == 0) + { + speed = ALTERA_TSE_MAC_SPEED_DEFAULT; + duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT; + result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_NO_MDIO; + usleep(ALTERA_NOMDIO_TIMEOUT_THRESHOLD); + if(psys->tse_phy_cfg) { + tse_dprintf(4, "WARNING : PHY[%d.%d] - MDIO not enabled! Running user configuration...\n", mac_group_index, mac_info_index); + result = psys->tse_phy_cfg(pmac); + } + else { + tse_dprintf(4, "WARNING : MAC Group[%d] - MDIO not enabled! Speed = %s, Duplex = %s\n", mac_group_index, speed == TSE_PHY_SPEED_1000 ? "1000" : + speed == TSE_PHY_SPEED_100 ? "100" : + speed == TSE_PHY_SPEED_10 ? "10" : "Unknown", + duplex == 1 ? "Full" : "Half"); + } + return result; + } + + /* Not running simulation */ + #ifndef ALT_SIM_OPTIMIZE + + /* These variables declaration are here to avoid "warning: unused variable" message when compile for simulation */ + np_tse_mac *pmac_group_base = (np_tse_mac *) pmac_group->pmac_info[0]->psys_info->tse_mac_base; + + /* if no PHY connected to the MAC */ + if(pphy == 0) { + speed = ALTERA_TSE_MAC_SPEED_DEFAULT; + duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT; + result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_NO_PHY; + tse_dprintf(2, "ERROR : PHY[%d.%d] - No PHY connected! Speed = %s, Duplex = %s\n", mac_group_index, mac_info_index, speed == TSE_PHY_SPEED_1000 ? "1000" : + speed == TSE_PHY_SPEED_100 ? "100" : + speed == TSE_PHY_SPEED_10 ? "10" : "Unknown", + duplex == 1 ? "Full" : "Half"); + return result; + } + + /* Small MAC */ + if(pmac_info->mac_type == ALTERA_TSE_MACLITE_10_100) { + alt_tse_phy_set_adv_1000(pphy, 0); + alt_tse_phy_restart_an(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD); + } + else if(pmac_info->mac_type == ALTERA_TSE_MACLITE_1000) { + alt_tse_phy_set_adv_100(pphy, 0); + alt_tse_phy_set_adv_10(pphy, 0); + alt_tse_phy_restart_an(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD); + } + + /* check link connection for this PHY */ + if(alt_tse_phy_check_link(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD) == TSE_PHY_AN_NOT_COMPLETE) { + speed = ALTERA_TSE_MAC_SPEED_DEFAULT; + duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT; + result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_AN_NOT_COMPLETE; + tse_dprintf(3, "WARNING : PHY[%d.%d] - Auto-Negotiation not completed! Speed = %s, Duplex = %s\n", mac_group_index, mac_info_index, speed == TSE_PHY_SPEED_1000 ? "1000" : + speed == TSE_PHY_SPEED_100 ? "100" : + speed == TSE_PHY_SPEED_10 ? "10" : "Unknown", + duplex == 1 ? "Full" : "Half"); + return result; + } + + IOWR(&pmac_group_base->MDIO_ADDR1, 0, pphy->mdio_address); + + /* To enable PHY loopback */ + #if ENABLE_PHY_LOOPBACK + tse_dprintf(5, "INFO : PHY[%d.%d] - Putting PHY in loopback\n", mac_group_index, mac_info_index); + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_LOOPBACK, 1, 1); // enable PHY loopback + #else + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_LOOPBACK, 1, 0); // disable PHY loopback + #endif + + /* if PHY not found in profile */ + if(pphy->pphy_profile == 0) { + tse_dprintf(3, "WARNING : PHY[%d.%d] - PHY not found in PHY profile\n", mac_group_index, mac_info_index); + speed = ALTERA_TSE_MAC_SPEED_DEFAULT; + duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT; + result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_NO_PHY_PROFILE; + } + // retrieve duplex information from PHY + else + { + if(pphy->pphy_profile->link_status_read) + { + result = pphy->pphy_profile->link_status_read(pmac_group_base); + speed = (result & 0x02) ? TSE_PHY_SPEED_1000 : + (result & 0x04) ? TSE_PHY_SPEED_100 : + (result & 0x08) ? TSE_PHY_SPEED_10 : TSE_PHY_SPEED_INVALID; + duplex = (result & 0x01) ? TSE_PHY_DUPLEX_FULL : TSE_PHY_DUPLEX_HALF; + + if(result & ALT_TSE_E_INVALID_SPEED) + { + tse_dprintf(3, "WARNING : PHY[%d.%d] - Invalid speed read from PHY\n", mac_group_index, mac_info_index); + } + } + else if(pphy->pphy_profile->status_reg_location == 0) + { + tse_dprintf(3, "WARNING : PHY[%d.%d] - PHY Specific Status register information not provided in profile\n", mac_group_index, mac_info_index); + speed = ALTERA_TSE_MAC_SPEED_DEFAULT; + duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT; + result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_PROFILE_INCORRECT_DEFINED; + } + else + { + /* extract connection speed and duplex information */ + speed = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->speed_lsb_location, 2); + duplex = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->duplex_bit_location, 1); + + result = ALT_TSE_SPEED_DUPLEX(speed, duplex); + } + } + + #else + /* for simulation purpose, default to gigabit mode */ + speed = 1; + duplex = 1; + #endif + + tse_dprintf(5, "INFO : PHY[%d.%d] - Speed = %s, Duplex = %s\n", mac_group_index, mac_info_index, speed == TSE_PHY_SPEED_1000 ? "1000" : + speed == TSE_PHY_SPEED_100 ? "100" : + speed == TSE_PHY_SPEED_10 ? "10" : "Unknown", + duplex == 1 ? "Full" : "Half"); + + return result; +} + + +/* @Function Description: Read MDIO address from the MDIO address1 register of first MAC within MAC group + * @API Type: Internal + * @param pmac Pointer to the alt_tse_phy_info structure + * @return return SUCCESS + */ +alt_32 alt_tse_phy_rd_mdio_addr(alt_tse_phy_info *pphy) { + np_tse_mac *pmac_group_base = (np_tse_mac *) pphy->pmac_info->pmac_group->pmac_info[0]->psys_info->tse_mac_base; + return IORD(&pmac_group_base->MDIO_ADDR1, 0); +} + + +/* @Function Description: Write MDIO address to the MDIO address1 register of first MAC within MAC group + * @API Type: Internal + * @param pmac Pointer to the alt_tse_phy_info structure + * @param mdio_address MDIO address to be written + * @return return SUCCESS + */ +alt_32 alt_tse_phy_wr_mdio_addr(alt_tse_phy_info *pphy, alt_u8 mdio_address) { + np_tse_mac *pmac_group_base = (np_tse_mac *) pphy->pmac_info->pmac_group->pmac_info[0]->psys_info->tse_mac_base; + IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdio_address); + + return SUCCESS; +} + +/** @Function Description - Write value of data with bit_length number of bits to MDIO register based on register location reg_num + * and start from bit location lsb_num. + * + * @API TYPE - Internal + * @param pphy pointer to alt_tse_phy_info structure + * @param reg_num location of MDIO register to be written. + * @param lsb_num least significant bit location of MDIO register to be written. + * @param bit_length number of bits to be written to the register. + * @param data data to be written to the register at specific bit location of register. + * @return SUCCESS + */ +alt_32 alt_tse_phy_wr_mdio_reg(alt_tse_phy_info *pphy, alt_u8 reg_num, alt_u8 lsb_num, alt_u8 bit_length, alt_u16 data) +{ + + alt_u16 temp_data; + alt_u16 bit_mask; + alt_32 i; + np_tse_mac *pmac = (np_tse_mac *) pphy->pmac_info->pmac_group->pmac_info[0]->psys_info->tse_mac_base; + + bit_mask = 0x00; + /* generate mask consist of bit_length number of 1 + * eg: bit_length = 3, bit_mask = 0b0000 0000 0000 0111 + */ + for(i = 0; i < bit_length; i++) + { + bit_mask <<= 1; + bit_mask |= 0x01; + } + + /* shifting mask to left by bit_num */ + bit_mask <<= lsb_num; + + /* read register data */ + temp_data = IORD(&pmac->mdio1, reg_num); + + /* clear bits to be written */ + temp_data &= ~bit_mask; + + /* OR-ed together corresponding bits data */ + temp_data |= ((data << lsb_num) & bit_mask); + + /* write data to MDIO register */ + IOWR(&pmac->mdio1, reg_num, temp_data); + + return SUCCESS; + +} + + + +/* @Function Description - Read bit_length number of bits from MDIO register based on register location reg_num + * and start from bit location lsb_num. + * + * @API TYPE - Internal + * @param pphy pointer to alt_tse_phy_info structure + * @param reg_num location of MDIO register to be read. + * @param lsb_num least significant bit location of MDIO register to be read. + * @param bit_length number of bits to be read from the register. + * @return data read from MDIO register + */ + +alt_u32 alt_tse_phy_rd_mdio_reg(alt_tse_phy_info *pphy, alt_u8 reg_num, alt_u8 lsb_num, alt_u8 bit_length) +{ + alt_u16 temp_data; + alt_u32 bit_mask; + alt_32 i; + np_tse_mac *pmac = (np_tse_mac *) pphy->pmac_info->pmac_group->pmac_info[0]->psys_info->tse_mac_base; + + bit_mask = 0x00; + /* generate mask consist of bit_length number of 1 + * eg: bit_length = 3, bit_mask = 0b0000 0000 0000 0111 + */ + for(i = 0; i < bit_length; i++) + { + bit_mask <<= 1; + bit_mask |= 0x01; + } + + /* read register data */ + temp_data = IORD(&pmac->mdio1, reg_num); + + /* shifting read data */ + temp_data >>= lsb_num; + + return (temp_data & bit_mask); +} + + + +/* @Function Description: Add supported PHY to profile + * @API Type: Internal + * @param pmac N/A + * @return Number of PHY in profile + * + * User might add their own PHY by calling alt_tse_phy_add_profile() + */ +alt_32 alt_tse_phy_add_profile_default() { + + /* supported PHY definition */ + + /* ------------------------------ */ + /* Marvell PHY on PHYWORKX board */ + /* ------------------------------ */ + + alt_tse_phy_profile MV88E1111 = {"Marvell 88E1111", /* Marvell 88E1111 */ + MV88E1111_OUI, /* OUI */ + MV88E1111_MODEL, /* Vender Model Number */ + MV88E1111_REV, /* Model Revision Number */ + 0x11, /* Location of Status Register */ + 14, /* Location of Speed Status */ + 13, /* Location of Duplex Status */ + 10, /* Location of Link Status */ + &marvell_phy_cfg /* Function pointer to configure Marvell PHY */ + }; + + + /* ---------------------------------- */ + /* Marvell Quad PHY on PHYWORKX board */ + /* ---------------------------------- */ + + alt_tse_phy_profile MV88E1145 = {"Marvell Quad PHY 88E1145", /* Marvell 88E1145 */ + MV88E1145_OUI, /* OUI */ + MV88E1145_MODEL, /* Vender Model Number */ + MV88E1145_REV, /* Model Revision Number */ + 0x11, /* Location of Status Register */ + 14, /* Location of Speed Status */ + 13, /* Location of Duplex Status */ + 10, /* Location of Link Status */ + &marvell_phy_cfg /* Function pointer to configure Marvell PHY */ + }; + + /* ------------------------------ */ + /* National PHY on PHYWORKX board */ + /* ------------------------------ */ + + alt_tse_phy_profile DP83865 = {"National DP83865", /* National DP83865 */ + DP83865_OUI, /* OUI */ + DP83865_MODEL, /* Vender Model Number */ + DP83865_REV, /* Model Revision Number */ + 0x11, /* Location of Status Register */ + 3, /* Location of Speed Status */ + 1, /* Location of Duplex Status */ + 2 /* Location of Link Status */ + }; + + /* -------------------------------------- */ + /* National 10/100 PHY on PHYWORKX board */ + /* -------------------------------------- */ + + alt_tse_phy_profile DP83848C = {"National DP83848C", /* National DP83848C */ + DP83848C_OUI, /* OUI */ + DP83848C_MODEL, /* Vender Model Number */ + DP83848C_REV, /* Model Revision Number */ + 0, /* Location of Status Register (ignored) */ + 0, /* Location of Speed Status (ignored) */ + 0, /* Location of Duplex Status (ignored) */ + 0, /* Location of Link Status (ignored) */ + 0, /* No function pointer configure National DP83848C */ + &DP83848C_link_status_read /* Function pointer to read from PHY specific status register */ + }; + + /* -------------------------------------- */ + /* Intel PHY on C10LP EVA board */ + /* -------------------------------------- */ + + alt_tse_phy_profile PEF7071 = {"Intel PEF7071", /* National DP83848C */ + PEF7071_OUI, /* OUI */ + PEF7071_MODEL, /* Vender Model Number */ + PEF7071_REV, /* Model Revision Number */ + 0, /* Location of Status Register */ + 0, /* Location of Speed Status */ + 0, /* Location of Duplex Status */ + 0, /* Location of Link Status */ + &PEF7071_config, /* configure PEF7071 */ + &PEF7071_link_status_read /* Function pointer to read from PHY specific status register */ + }; + + /* add supported PHY to profile */ + alt_tse_phy_add_profile(&MV88E1111); + alt_tse_phy_add_profile(&MV88E1145); + alt_tse_phy_add_profile(&DP83865); + alt_tse_phy_add_profile(&DP83848C); + alt_tse_phy_add_profile(&PEF7071); + + + return phy_profile_count; +} + +/* @Function Description: Display PHYs available in profile + * @API Type: Internal + * @param pmac N/A + * @return Number of PHY in profile + */ +alt_32 alt_tse_phy_print_profile() { + + alt_8 i; + /* display PHY in profile */ + tse_dprintf(6, "List of PHY profiles supported (Total profiles = %d)...\n", phy_profile_count); + + for(i = 0; i < phy_profile_count; i++) + { + tse_dprintf(6, "Profile No.%2d :\n", i); + tse_dprintf(6, "PHY Name : %s\n", pphy_profiles[i]->name); + + tse_dprintf(6, "PHY OUI : 0x%06x\n", (int)pphy_profiles[i]->oui); + tse_dprintf(6, "PHY Model Num. : 0x%02x\n", pphy_profiles[i]->model_number); + tse_dprintf(6, "PHY Rev. Num. : 0x%02x\n", pphy_profiles[i]->revision_number); + + tse_dprintf(6, "Status Register : 0x%02x\n", pphy_profiles[i]->status_reg_location); + + tse_dprintf(6, "Speed Bit : %d\n", pphy_profiles[i]->speed_lsb_location); + + tse_dprintf(6, "Duplex Bit : %d\n", pphy_profiles[i]->duplex_bit_location); + + tse_dprintf(6, "Link Bit : %d\n\n", pphy_profiles[i]->link_bit_location); + + } + + return phy_profile_count; +} + + + +/* @Function Description: Store information of all the MAC available in the system + * @API Type: Internal + * @param pmac N/A + * @return return SUCCESS + * return ALTERA_TSE_SYSTEM_DEF_ERROR if alt_tse_system_info structure definition error + */ +alt_32 alt_tse_mac_group_init() { + + alt_8 i; + alt_8 j; + + alt_tse_mac_group *pmac_group = 0; + alt_tse_mac_info *pmac_info = 0; + alt_tse_system_info *psys = 0; + + /* reset number of MAC group */ + mac_group_count = 0; + + /* loop through every alt_tse_system_info structure */ + for(i = 0; i < max_mac_system; i++) { + psys = &tse_mac_device[i]; + + if((psys->tse_msgdma_tx != 0) && (psys->tse_msgdma_rx != 0)) { + tse_dprintf(5, "INFO : TSE MAC %d found at address 0x%08x\n", mac_group_count, (int) psys->tse_mac_base); + + /* Allocate memory for the structure */ + pmac_group = (alt_tse_mac_group *) malloc(sizeof(alt_tse_mac_group)); + if(!pmac_group) { + tse_dprintf(1, "ERROR : Unable to allocate memory for MAC Group[%d]\n", mac_group_count); + return ALTERA_TSE_MALLOC_FAILED; + } + + /* Non-multi-channel MAC considered as 1 channel */ + if(psys->tse_multichannel_mac) { + pmac_group->channel = psys->tse_num_of_channel; + tse_dprintf(6, "INFO : Multi Channel = Yes\n"); + tse_dprintf(6, "INFO : Number of channel = %d\n", pmac_group->channel); + tse_dprintf(6, "INFO : MDIO Shared = Yes\n"); + } + else if(psys->tse_mdio_shared) { + pmac_group->channel = psys->tse_number_of_mac_mdio_shared; + tse_dprintf(6, "INFO : Multi Channel = No\n"); + tse_dprintf(6, "INFO : MDIO Shared = Yes\n"); + tse_dprintf(6, "INFO : Number of MAC Share MDIO = %d\n", pmac_group->channel); + } + else { + pmac_group->channel = 1; + tse_dprintf(6, "INFO : Multi Channel = No\n"); + tse_dprintf(6, "INFO : MDIO Shared = No\n"); + } + + for(j = 0; j < pmac_group->channel; j++) { + /* Allocate memory for the structure */ + pmac_info = (alt_tse_mac_info *) malloc(sizeof(alt_tse_mac_info)); + if(!pmac_info) { + tse_dprintf(1, "ERROR : Unable to allocate memory for MAC Group[%d]->pmac_info[%d]\n", mac_group_count, j); + return ALTERA_TSE_MALLOC_FAILED; + } + + pmac_info->pmac_group = pmac_group; + + pmac_info->pphy_info = 0; + + pmac_info->psys_info = &tse_mac_device[i + j]; + + /* check to make sure the alt_tse_system_info defined correctly or has been defined */ + if((pmac_info->psys_info->tse_msgdma_tx == 0) || (pmac_info->psys_info->tse_msgdma_rx == 0)){ + tse_dprintf(2, "ERROR : tse_mac_device[%d] does not defined correctly!\n", i + j); + return ALTERA_TSE_SYSTEM_DEF_ERROR; + } + + /* MAC type detection */ + if(pmac_info->psys_info->tse_en_maclite) { + if(pmac_info->psys_info->tse_maclite_gige) { + pmac_info->mac_type = ALTERA_TSE_MACLITE_1000; + } + else { + pmac_info->mac_type = ALTERA_TSE_MACLITE_10_100; + } + } + else { + pmac_info->mac_type = ALTERA_TSE_FULL_MAC; + } + + if((pmac_info->psys_info->tse_mdio_shared) && (!pmac_info->psys_info->tse_multichannel_mac)){ + tse_dprintf(6, "INFO : MAC %2d Address = 0x%08x\n", j, (int) pmac_info->psys_info->tse_mac_base); + tse_dprintf(6, "INFO : MAC %2d Device = tse_mac_device[%d]\n", j, i + j); + + switch(pmac_info->mac_type) { + case ALTERA_TSE_MACLITE_1000: + tse_dprintf(6, "INFO : MAC %2d Type = %s\n", j, "1000 Mbps Small MAC"); + break; + case ALTERA_TSE_MACLITE_10_100: + tse_dprintf(6, "INFO : MAC %2d Type = %s\n", j, "10/100 Mbps Small MAC"); + break; + case ALTERA_TSE_FULL_MAC: + tse_dprintf(6, "INFO : MAC %2d Type = %s\n", j, "10/100/1000 Ethernet MAC"); + break; + default : + tse_dprintf(6, "INFO : MAC %2d Type = %s\n", j, "Unknown"); + break; + } + + if(pmac_info->psys_info->tse_pcs_ena) { + tse_dprintf(6, "INFO : PCS %2d Enable = %s\n", j, pmac_info->psys_info->tse_pcs_ena ? "Yes" : "No"); + tse_dprintf(6, "INFO : PCS %2d SGMII Enable = %s\n", j, pmac_info->psys_info->tse_pcs_sgmii ? "Yes" : "No"); + } + } + else { + /* display only once for all MAC, except shared MDIO MACs */ + if(j == 0) { + switch(pmac_info->mac_type) { + case ALTERA_TSE_MACLITE_1000: + tse_dprintf(6, "INFO : MAC Type = %s\n", "1000 Mbps Small MAC"); + break; + case ALTERA_TSE_MACLITE_10_100: + tse_dprintf(6, "INFO : MAC Type = %s\n", "10/100 Mbps Small MAC"); + break; + case ALTERA_TSE_FULL_MAC: + tse_dprintf(6, "INFO : MAC Type = %s\n", "10/100/1000 Ethernet MAC"); + break; + default : + tse_dprintf(6, "INFO : MAC Type = %s\n", "Unknown"); + break; + } + + if(pmac_info->psys_info->tse_pcs_ena) { + tse_dprintf(6, "INFO : PCS Enable = %s\n", pmac_info->psys_info->tse_pcs_ena ? "Yes" : "No"); + tse_dprintf(6, "INFO : PCS SGMII Enable = %s\n", pmac_info->psys_info->tse_pcs_sgmii ? "Yes" : "No"); + } + } + + if(pmac_info->psys_info->tse_multichannel_mac) { + tse_dprintf(6, "INFO : Channel %2d Address = 0x%08x\n", j, (int) pmac_info->psys_info->tse_mac_base); + tse_dprintf(6, "INFO : Channel %2d Device = tse_mac_device[%d]\n", j, i + j); + } + else { + tse_dprintf(6, "INFO : MAC Address = 0x%08x\n", (int) pmac_info->psys_info->tse_mac_base); + tse_dprintf(6, "INFO : MAC Device = tse_mac_device[%d]\n", i + j); + } + } + + /* store the pointer in MAC group variable for the detected channel */ + pmac_group->pmac_info[j] = pmac_info; + } + + /* store the pointer in global variable */ + pmac_groups[mac_group_count] = pmac_group; + + mac_group_count++; + + /* skip for subsequent Multi-channel MAC */ + i += (pmac_group->channel - 1); + + } + } + return SUCCESS; +} + + +/* @Function Description: Store information of all the PHYs connected to MAC to phy_list + * @API Type: Internal + * @param pmac_group Pointer to the TSE MAC grouping structure + * @return Number of PHY not in profile, return ALTERA_TSE_MALLOC_FAILED if memory allocation failed + */ +alt_32 alt_tse_mac_get_phy(alt_tse_mac_group *pmac_group) { + + alt_32 phyid; + alt_32 phyid2 = 0; + alt_u8 phyadd; + + alt_u32 oui; + alt_u8 model_number; + alt_u8 revision_number; + + alt_32 i; + + alt_u8 is_phy_in_profile; + alt_32 return_value = 0; + + alt_8 phy_info_count = 0; + + alt_tse_phy_info *pphy = 0; + alt_tse_mac_info *pmac_info = 0; + alt_tse_system_info *psys = 0; + + np_tse_mac *pmac_group_base = (np_tse_mac *) pmac_group->pmac_info[0]->psys_info->tse_mac_base; + + /* Record previous MDIO address, to be restored at the end of function */ + alt_32 mdioadd_prev = IORD(&pmac_group_base->MDIO_ADDR1, 0); + + /* get index of the pointers in pointer array list */ + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + + /* loop all valid PHY address to look for connected PHY */ + for (phyadd = 0x00; phyadd < pmac_group->channel /*0x20*/; phyadd++) //M.D. 2019-08-05: don't look at unused PHYs + { + IOWR(&pmac_group_base->MDIO_ADDR1, 0, phyadd); + phyid = IORD(&pmac_group_base->mdio1.PHY_ID1,0); // read PHY ID + phyid2 = IORD(&pmac_group_base->mdio1.PHY_ID2,0); // read PHY ID + + /* PHY found */ + if (phyid != phyid2) + { + pphy = (alt_tse_phy_info *) malloc(sizeof(alt_tse_phy_info)); + if(!pphy) { + tse_dprintf(1, "ERROR : Unable to allocate memory for phy_info[%d.%d]\n", mac_group_index, phy_info_count); + return ALTERA_TSE_MALLOC_FAILED; + } + + /* store PHY address */ + pphy->mdio_address = phyadd; + + /* get oui, model number, and revision number from PHYID and PHYID2 */ + oui = (phyid << 6) | ((phyid2 >> 10) & 0x3f); + model_number = (phyid2 >> 4) & 0x3f; + revision_number = phyid2 & 0x0f; + + /* map the PHY with PHY in profile */ + is_phy_in_profile = 0; + for(i = 0; i < phy_profile_count; i++) { + + /* if PHY match with PHY in profile */ + if((pphy_profiles[i]->oui == oui) && (pphy_profiles[i]->model_number == model_number)) + { + pphy->pphy_profile = pphy_profiles[i]; + + /* PHY found, add it to phy_list */ + tse_dprintf(5, "INFO : PHY %s found at PHY address 0x%02x of MAC Group[%d]\n", pphy_profiles[i]->name, phyadd, mac_group_index); + is_phy_in_profile = 1; + break; + } + } + /* PHY not found in PHY profile */ + if(is_phy_in_profile == 0) { + pphy->pphy_profile = 0; + tse_dprintf(3, "WARNING : Unknown PHY found at PHY address 0x%02x of MAC Group[%d]\n", phyadd, mac_group_index); + tse_dprintf(3, "WARNING : Please add PHY information to PHY profile\n"); + return_value++; + } + + tse_dprintf(6, "INFO : PHY OUI = 0x%06x\n", (int) oui); + tse_dprintf(6, "INFO : PHY Model Number = 0x%02x\n", model_number); + tse_dprintf(6, "INFO : PHY Revision Number = 0x%01x\n", revision_number); + + /* map the detected PHY to connected MAC */ + if(alt_tse_mac_associate_phy(pmac_group, pphy) == TSE_PHY_MAP_SUCCESS) { + + pmac_info = pphy->pmac_info; + psys = pmac_info->psys_info; + + /* Disable PHY loopback to allow Auto-Negotiation completed */ + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_LOOPBACK, 1, 0); // disable PHY loopback + + /* Reset auto-negotiation advertisement */ + alt_tse_phy_set_adv_1000(pphy, 1); + alt_tse_phy_set_adv_100(pphy, 1); + alt_tse_phy_set_adv_10(pphy, 1); + + /* check link connection for this PHY */ + alt_tse_phy_restart_an(pphy, ALTERA_CHECKLINK_TIMEOUT_THRESHOLD); + + /* Perform additional setting if there is any */ + /* Profile specific */ + if(pphy->pphy_profile) { + if(pphy->pphy_profile->phy_cfg) { + tse_dprintf(6, "INFO : Applying additional PHY configuration of %s\n", pphy->pphy_profile->name); + pphy->pphy_profile->phy_cfg(pmac_group_base); + } + } + + /* Initialize PHY, call user's function pointer in alt_tse_system_info structure */ + /* Individual PHY specific */ + if(psys->tse_phy_cfg) { + tse_dprintf(6, "INFO : Applying additional user PHY configuration\n"); + psys->tse_phy_cfg(pmac_group_base); + } + } + + tse_dprintf(6, "\n"); + + phy_info_count++; + } + } + + TK_SLEEP(100); //Wait a little bit for PHY reset after specific configuration + + + /* check to verify the number of connected PHY match the number of channel */ + if(pmac_group->channel != phy_info_count) { + if(phy_info_count == 0) { + tse_dprintf(2, "ERROR : MAC Group[%d] - No PHY connected!\n", mac_group_index); + } + else { + tse_dprintf(3, "WARNING : MAC Group[%d] - Number of PHY connected is not equal to the number of channel, Number of PHY : %d, Channel : %d\n", mac_group_index, phy_info_count, pmac_group->channel); + } + } + + /* Restore previous MDIO address */ + IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdioadd_prev); + + return return_value; +} + + + + +/* @Function Description: Associate the PHYs connected to the structure in alt_tse_system_info.h + * @API Type: Internal + * @param pmac_group Pointer to the TSE MAC grouping structure + * @param pphy Pointer to the TSE PHY info structure which hold information of PHY + * @return return TSE_PHY_MAP_ERROR if mapping error + * return TSE_PHY_MAP_SUCCESS otherwise + */ +alt_32 alt_tse_mac_associate_phy(alt_tse_mac_group *pmac_group, alt_tse_phy_info *pphy) { + + alt_32 i; + alt_32 return_value = TSE_PHY_MAP_SUCCESS; + + alt_u8 is_mapped; + + alt_tse_system_info *psys = 0; + alt_tse_mac_info *pmac_info = 0; + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = 0; + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + alt_8 sys_info_index = 0; + + is_mapped = 0; + + for(i = 0; i < pmac_group->channel; i++) { + pmac_info = pmac_group->pmac_info[i]; + psys = pmac_info->psys_info; + + /* map according to the PHY address in alt_tse_system_info.h */ + if(psys->tse_phy_mdio_address == pphy->mdio_address) { + mac_info_index = alt_tse_get_mac_info_index(pmac_info); + sys_info_index = alt_tse_get_system_index(psys); + + pmac_info->pphy_info = pphy; + pphy->pmac_info = pmac_info; + tse_dprintf(5, "INFO : PHY[%d.%d] - Explicitly mapped to tse_mac_device[%d]\n", mac_group_index, mac_info_index, sys_info_index); + is_mapped = 1; + break; + } + } + + /* if not yet map, it will automatically mapped to the first TSE device encountered with tse_phy_mdio_address = TSE_PHY_AUTO_ADDRESS */ + if(is_mapped == 0) { + for(i = 0; i < pmac_group->channel; i++) { + pmac_info = pmac_group->pmac_info[i]; + psys = pmac_info->psys_info; + + /* alt_tse_system_info structure definition error */ + if((psys->tse_msgdma_tx == 0) || (psys->tse_msgdma_rx == 0)){ + continue; + } + + if(psys->tse_phy_mdio_address == TSE_PHY_AUTO_ADDRESS) { + mac_info_index = alt_tse_get_mac_info_index(pmac_info); + sys_info_index = alt_tse_get_system_index(psys); + + pmac_info->pphy_info = pphy; + pphy->pmac_info = pmac_info; + psys->tse_phy_mdio_address = pphy->mdio_address; + tse_dprintf(5, "INFO : PHY[%d.%d] - Automatically mapped to tse_mac_device[%d]\n", mac_group_index, mac_info_index, sys_info_index); + is_mapped = 1; + break; + } + } + } + + /* Still cannot find any matched MAC-PHY */ + if(is_mapped == 0) { + pphy->pmac_info = 0; + tse_dprintf(2, "WARNING : PHY[%d.X] - Mapping of PHY to MAC failed! Make sure the PHY address is defined correctly in tse_mac_device[] structure, and number of PHYs connected is equivalent to number of channel\n", mac_group_index); + return_value = TSE_PHY_MAP_ERROR; + } + + return return_value; +} + + + + +/* @Function Description: Configure operating mode of Altera PCS if available + * @API Type: Internal + * @param pmac_info pointer to MAC info variable + * @return return SUCCESS + */ +alt_32 alt_tse_phy_cfg_pcs(alt_tse_mac_info *pmac_info) { + + alt_tse_system_info *psys = pmac_info->psys_info; + np_tse_mac *pmac = (np_tse_mac *) psys->tse_mac_base; + alt_tse_mac_group *pmac_group = pmac_info->pmac_group; + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info); + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + + if(psys->tse_pcs_ena) { + tse_dprintf(5, "INFO : PCS[%d.%d] - Configuring PCS operating mode\n", mac_group_index, mac_info_index); + + alt_32 data = IORD(&pmac->mdio0.CONTROL, ALTERA_TSE_PCS_IF_MODE); + + if(psys->tse_pcs_sgmii) { + tse_dprintf(5, "INFO : PCS[%d.%d] - PCS SGMII mode enabled\n", mac_group_index, mac_info_index); + IOWR(&pmac->mdio0.CONTROL, ALTERA_TSE_PCS_IF_MODE, data | 0x03); + } + else { + tse_dprintf(5, "INFO : PCS[%d.%d] - PCS SGMII mode disabled\n", mac_group_index, mac_info_index); + IOWR(&pmac->mdio0.CONTROL, ALTERA_TSE_PCS_IF_MODE, data & ~0x03); + } + } + + return SUCCESS; +} + + + +/* @Function Description: Detect and initialize all the PHYs connected + * @API Type: Internal + * @param pmac N/A + * @return SUCCESS + */ +alt_32 alt_tse_phy_init() { + alt_8 i = 0; + alt_8 j = 0; + + alt_tse_mac_group *pmac_group = 0; + alt_tse_mac_info *pmac_info = 0; + + /* add supported PHYs */ + alt_tse_phy_add_profile_default(); + + /* display PHY in profile */ + alt_tse_phy_print_profile(); + + alt_tse_mac_group_init(); + + /* initialize for each TSE MAC */ + /* run once only for multi-channel MAC */ + for(i = 0; i < mac_group_count; i++) { + pmac_group = pmac_groups[i]; + + if(pmac_group->pmac_info[0]->psys_info->tse_use_mdio) { + + /* get connected PHYs */ + alt_tse_mac_get_phy(pmac_group); + } + else { + tse_dprintf(3, "WARNING : MAC Groups[%d]->pmac_info[%d] MDIO is not used, unable to run PHY detection\n", i, j); + } + + /* Configure PCS mode if MAC+PCS system is used */ + for(j = 0; j < pmac_group->channel; j++) { + pmac_info = pmac_group->pmac_info[j]; + + alt_tse_phy_cfg_pcs(pmac_info); + } + } + + return SUCCESS; +} + + +/* @Function Description: Restart Auto-Negotiation for the PHY + * @API Type: Internal + * @param pphy Pointer to the alt_tse_phy_info structure + * timeout_threshold timeout value of Auto-Negotiation + * @return return TSE_PHY_AN_COMPLETE if success + * return TSE_PHY_AN_NOT_COMPLETE if auto-negotiation not completed + * return TSE_PHY_AN_NOT_CAPABLE if the PHY not capable for AN + */ +alt_32 alt_tse_phy_restart_an(alt_tse_phy_info *pphy, alt_u32 timeout_threshold) { + + /* pointer to MAC associated and MAC group */ + alt_tse_mac_info *pmac_info = pphy->pmac_info; + alt_tse_mac_group *pmac_group = pmac_info->pmac_group; + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info); + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + + /* Record previous MDIO address, to be restored at the end of function */ + alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); + + /* write PHY address to MDIO to access the i-th PHY */ + alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address); + + if(!alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_ABILITY, 1)) { + tse_dprintf(3, "WARNING : PHY[%d.%d] - PHY not capable for Auto-Negotiation\n", mac_group_index, mac_info_index); + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + + return TSE_PHY_AN_NOT_CAPABLE; + } + + /* enable Auto-Negotiation */ + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_AN_ENA, 1, 1); + + /* send PHY reset command */ + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_RESTART_AN, 1, 1); + tse_dprintf(5, "INFO : PHY[%d.%d] - Restart Auto-Negotiation, checking PHY link...\n", mac_group_index, mac_info_index); + + alt_32 timeout = 0; + while(alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_COMPLETE, 1) == 0 ){ + if(timeout++ > timeout_threshold) { + tse_dprintf(4, "WARNING : PHY[%d.%d] - Auto-Negotiation FAILED\n", mac_group_index, mac_info_index); + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + + return TSE_PHY_AN_NOT_COMPLETE; + } + usleep(1000); + } + tse_dprintf(5, "INFO : PHY[%d.%d] - Auto-Negotiation PASSED\n", mac_group_index, mac_info_index); + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + + return TSE_PHY_AN_COMPLETE; +} + + +/* @Function Description: Check link status of PHY and start Auto-Negotiation if it has not yet done + * @API Type: Internal + * @param pphy Pointer to the alt_tse_phy_info structure + * timeout_threshold timeout value of Auto-Negotiation + * @return return TSE_PHY_AN_COMPLETE if success + * return TSE_PHY_AN_NOT_COMPLETE if auto-negotiation not completed + */ +alt_32 alt_tse_phy_check_link(alt_tse_phy_info *pphy, alt_u32 timeout_threshold) +{ + alt_32 timeout=0; + + /* pointer to MAC associated and MAC group */ + alt_tse_mac_info *pmac_info = pphy->pmac_info; + alt_tse_mac_group *pmac_group = pmac_info->pmac_group; + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info); + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + + /* Record previous MDIO address, to be restored at the end of function */ + alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); + + /* write PHY address to MDIO to access the i-th PHY */ + alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address); + + /* if Auto-Negotiation not complete yet, then restart Auto-Negotiation */ + /* Issue a PHY reset here and wait for the link + * autonegotiation complete again... this takes several SECONDS(!) + * so be very careful not to do it frequently + * perform this when PHY is configured in loopback or has no link yet. + */ + tse_dprintf(5, "INFO : PHY[%d.%d] - Checking link...\n", mac_group_index, mac_info_index); + while( ((alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_LOOPBACK, 1)) != 0) || + ((alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_COMPLETE, 1)) == 0) ) + { + if (timeout++ > timeout_threshold) + { + tse_dprintf(5, "INFO : PHY[%d.%d] - Link not yet established, restart auto-negotiation...\n", mac_group_index, mac_info_index); + /* restart Auto-Negotiation */ + /* if Auto-Negotiation still cannot complete, then go to next PHY */ + if(alt_tse_phy_restart_an(pphy, timeout_threshold) == TSE_PHY_AN_NOT_COMPLETE) + { + tse_dprintf(3, "WARNING : PHY[%d.%d] - Link could not established\n", mac_group_index, mac_info_index); + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + + return TSE_PHY_AN_NOT_COMPLETE; + } + } + usleep(1000); + } + tse_dprintf(5, "INFO : PHY[%d.%d] - Link established\n", mac_group_index, mac_info_index); + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + + return TSE_PHY_AN_COMPLETE; +} + +/* @Function Description: Get link capability of PHY and link partner + * @API Type: Internal + * @param pmac Pointer to the alt_tse_phy_info structure + * @return return TSE_PHY_AN_COMPLETE if success + * return TSE_PHY_AN_NOT_COMPLETE if auto-negotiation not completed + * return TSE_PHY_AN_NOT_CAPABLE if the PHY not capable for AN + */ +alt_32 alt_tse_phy_get_cap(alt_tse_phy_info *pphy) { + alt_32 return_value = TSE_PHY_AN_COMPLETE; + + /* pointer to MAC associated and MAC group */ + alt_tse_mac_info *pmac_info = pphy->pmac_info; + alt_tse_mac_group *pmac_group = pmac_info->pmac_group; + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info); + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + + /* Record previous MDIO address, to be restored at the end of function */ + alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); + + /* write PHY address to MDIO to access the i-th PHY */ + alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address); + + if(!alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_ABILITY, 1)) { + tse_dprintf(3, "WARNING : PHY[%d.%d] - PHY not capable for Auto-Negotiation\n", mac_group_index, mac_info_index); + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + + return TSE_PHY_AN_NOT_CAPABLE; + } + + /* check whether link has been established */ + alt_tse_phy_restart_an(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD); + + if(alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_COMPLETE, 1) == 0) { + return_value = TSE_PHY_AN_NOT_COMPLETE; + } + + /* get PHY capabilities */ + pphy->link_capability.cap_1000_base_x_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_X_FULL, 1); + pphy->link_capability.cap_1000_base_x_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_X_HALF, 1); + pphy->link_capability.cap_1000_base_t_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_T_FULL, 1); + pphy->link_capability.cap_1000_base_t_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_T_HALF, 1); + + pphy->link_capability.cap_100_base_t4 = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_T4, 1); + pphy->link_capability.cap_100_base_x_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_X_FULL, 1); + pphy->link_capability.cap_100_base_x_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_X_HALF, 1); + pphy->link_capability.cap_100_base_t2_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_T2_FULL, 1); + pphy->link_capability.cap_100_base_t2_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_T2_HALF, 1); + pphy->link_capability.cap_10_base_t_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_10BASE_T_FULL, 1); + pphy->link_capability.cap_10_base_t_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_10BASE_T_HALF, 1); + + /* get link partner capability */ + pphy->link_capability.lp_1000_base_t_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_STATUS, TSE_PHY_MDIO_1000BASE_T_STATUS_LP_FULL_ADV, 1); + pphy->link_capability.lp_1000_base_t_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_STATUS, TSE_PHY_MDIO_1000BASE_T_STATUS_LP_HALF_ADV, 1); + + pphy->link_capability.lp_100_base_t4 = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_100BASE_T4, 1); + pphy->link_capability.lp_100_base_tx_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_100BASE_TX_FULL, 1); + pphy->link_capability.lp_100_base_tx_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_100BASE_TX_HALF, 1); + pphy->link_capability.lp_10_base_tx_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_10BASE_TX_FULL, 1); + pphy->link_capability.lp_10_base_tx_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_10BASE_TX_HALF, 1); + + tse_dprintf(6, "INFO : PHY[%d.%d] - Capability of PHY :\n", mac_group_index, mac_info_index); + tse_dprintf(6, "INFO : 1000 Base-X Full Duplex = %d\n", pphy->link_capability.cap_1000_base_x_full); + tse_dprintf(6, "INFO : 1000 Base-X Half Duplex = %d\n", pphy->link_capability.cap_1000_base_x_half); + tse_dprintf(6, "INFO : 1000 Base-T Full Duplex = %d\n", pphy->link_capability.cap_1000_base_t_full); + tse_dprintf(6, "INFO : 1000 Base-T Half Duplex = %d\n", pphy->link_capability.cap_1000_base_t_half); + tse_dprintf(6, "INFO : 100 Base-T4 = %d\n", pphy->link_capability.cap_100_base_t4); + tse_dprintf(6, "INFO : 100 Base-X Full Duplex = %d\n", pphy->link_capability.cap_100_base_x_full); + tse_dprintf(6, "INFO : 100 Base-X Half Duplex = %d\n", pphy->link_capability.cap_100_base_x_half); + tse_dprintf(6, "INFO : 100 Base-T2 Full Duplex = %d\n", pphy->link_capability.cap_100_base_t2_full); + tse_dprintf(6, "INFO : 100 Base-T2 Half Duplex = %d\n", pphy->link_capability.cap_100_base_t2_half); + tse_dprintf(6, "INFO : 10 Base-T Full Duplex = %d\n", pphy->link_capability.cap_10_base_t_full); + tse_dprintf(6, "INFO : 10 Base-T Half Duplex = %d\n", pphy->link_capability.cap_10_base_t_half); + tse_dprintf(6, "\n"); + + tse_dprintf(6, "INFO : PHY[%d.%d] - Link Partner Capability :\n", mac_group_index, mac_info_index); + tse_dprintf(6, "INFO : 1000 Base-T Full Duplex = %d\n", pphy->link_capability.lp_1000_base_t_full); + tse_dprintf(6, "INFO : 1000 Base-T Half Duplex = %d\n", pphy->link_capability.lp_1000_base_t_half); + tse_dprintf(6, "INFO : 100 Base-T4 = %d\n", pphy->link_capability.lp_100_base_t4); + tse_dprintf(6, "INFO : 100 Base-TX Full Duplex = %d\n", pphy->link_capability.lp_100_base_tx_full); + tse_dprintf(6, "INFO : 100 Base-TX Half Duplex = %d\n", pphy->link_capability.lp_100_base_tx_half); + tse_dprintf(6, "INFO : 10 Base-TX Full Duplex = %d\n", pphy->link_capability.lp_10_base_tx_full); + tse_dprintf(6, "INFO : 10 Base-TX Half Duplex = %d\n", pphy->link_capability.lp_10_base_tx_half); + tse_dprintf(6, "\n"); + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + + return return_value; + +} + + +/* @Function Description: Set the advertisement of PHY for 1000 Mbps + * @API Type: Internal + * @param pmac Pointer to the alt_tse_phy_info structure + * enable set Enable = 1 to advertise this speed if the PHY capable + * set Enable = 0 to disable advertise of this speed + * @return return SUCCESS + */ +alt_32 alt_tse_phy_set_adv_1000(alt_tse_phy_info *pphy, alt_u8 enable) { + alt_u8 cap; + + /* pointer to MAC associated and MAC group */ + alt_tse_mac_info *pmac_info = pphy->pmac_info; + alt_tse_mac_group *pmac_group = pmac_info->pmac_group; + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info); + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + + /* Record previous MDIO address, to be restored at the end of function */ + alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); + + /* write PHY address to MDIO to access the i-th PHY */ + alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address); + + /* if enable = 1, set advertisement based on PHY capability */ + if(enable) { + cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_T_FULL, 1); + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_CTRL, TSE_PHY_MDIO_1000BASE_T_CTRL_FULL_ADV, 1, cap); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 1000 Base-T Full Duplex set to %d\n", mac_group_index, mac_info_index, cap); + + /* 1000 Mbps Half duplex not supported by TSE MAC */ + cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_T_HALF, 1); + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_CTRL, TSE_PHY_MDIO_1000BASE_T_CTRL_HALF_ADV, 1, cap); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 1000 Base-T Half Duplex set to %d\n", mac_group_index, mac_info_index, cap); + } + /* else disable advertisement of this speed */ + else { + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_CTRL, TSE_PHY_MDIO_1000BASE_T_CTRL_FULL_ADV, 1, 0); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 1000 Base-T Full Duplex set to %d\n", mac_group_index, mac_info_index, 0); + + /* 1000 Mbps Half duplex not supported by TSE MAC */ + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_CTRL, TSE_PHY_MDIO_1000BASE_T_CTRL_HALF_ADV, 1, 0); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement 1000 Base-T half Duplex set to %d\n", mac_group_index, mac_info_index, 0); + } + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + + return SUCCESS; +} + + +/* @Function Description: Set the advertisement of PHY for 100 Mbps + * @API Type: Internal + * @param pmac Pointer to the alt_tse_phy_info structure + * enable set Enable = 1 to advertise this speed if the PHY capable + * set Enable = 0 to disable advertise of this speed + * @return return SUCCESS + */ +alt_32 alt_tse_phy_set_adv_100(alt_tse_phy_info *pphy, alt_u8 enable) { + alt_u8 cap; + + /* pointer to MAC associated and MAC group */ + alt_tse_mac_info *pmac_info = pphy->pmac_info; + alt_tse_mac_group *pmac_group = pmac_info->pmac_group; + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info); + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + + /* Record previous MDIO address, to be restored at the end of function */ + alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); + + /* write PHY address to MDIO to access the i-th PHY */ + alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address); + + /* if enable = 1, set advertisement based on PHY capability */ + if(enable) { + cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_T4, 1); + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_T4, 1, cap); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 100 Base-T4 set to %d\n", mac_group_index, mac_info_index, cap); + + cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_X_FULL, 1); + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_TX_FULL, 1, cap); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 100 Base-TX Full Duplex set to %d\n", mac_group_index, mac_info_index, cap); + + cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_X_HALF, 1); + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_TX_HALF, 1, cap); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 100 Base-TX Half Duplex set to %d\n", mac_group_index, mac_info_index, cap); + } + /* else disable advertisement of this speed */ + else { + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_T4, 1, 0); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 100 Base-T4 set to %d\n", mac_group_index, mac_info_index, 0); + + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_TX_FULL, 1, 0); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 100 Base-TX Full Duplex set to %d\n", mac_group_index, mac_info_index, 0); + + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_TX_HALF, 1, 0); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 100 Base-TX Half Duplex set to %d\n", mac_group_index, mac_info_index, 0); + } + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + + return SUCCESS; +} + + +/* @Function Description: Set the advertisement of PHY for 10 Mbps + * @API Type: Internal + * @param pmac Pointer to the alt_tse_phy_info structure + * enable set Enable = 1 to advertise this speed if the PHY capable + * set Enable = 0 to disable advertise of this speed + * @return return SUCCESS + */ +alt_32 alt_tse_phy_set_adv_10(alt_tse_phy_info *pphy, alt_u8 enable) { + alt_u8 cap; + + /* pointer to MAC associated and MAC group */ + alt_tse_mac_info *pmac_info = pphy->pmac_info; + alt_tse_mac_group *pmac_group = pmac_info->pmac_group; + + /* get index of the pointers in pointer array list */ + int mac_info_index = alt_tse_get_mac_info_index(pmac_info); + int mac_group_index = alt_tse_get_mac_group_index(pmac_group); + + /* Record previous MDIO address, to be restored at the end of function */ + int mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); + + /* write PHY address to MDIO to access the i-th PHY */ + alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address); + + /* if enable = 1, set advertisement based on PHY capability */ + if(enable) { + cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_10BASE_T_FULL, 1); + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_10BASE_TX_FULL, 1, cap); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 10 Base-TX Full Duplex set to %d\n", mac_group_index, mac_info_index, cap); + + cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_10BASE_T_HALF, 1); + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_10BASE_TX_HALF, 1, cap); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 10 Base-TX Half Duplex set to %d\n", mac_group_index, mac_info_index, cap); + } + /* else disable advertisement of this speed */ + else { + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_10BASE_TX_FULL, 1, 0); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 10 Base-TX Full Duplex set to %d\n", mac_group_index, mac_info_index, 0); + + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_10BASE_TX_HALF, 1, 0); + tse_dprintf(6, "INFO : PHY[%d.%d] - Advertisement of 10 Base-TX Half Duplex set to %d\n", mac_group_index, mac_info_index, 0); + } + + /* Restore previous MDIO address */ + alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev); + + return SUCCESS; +} + + + + +/* @Function Description: Get the common speed supported by all PHYs connected to the MAC within the same group + * @API Type: Internal + * @param pmac_group Pointer to the TSE MAC Group structure which group all the MACs that should use the same speed + * @return common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if no common speed found + */ +alt_32 alt_tse_phy_get_common_speed(alt_tse_mac_group *pmac_group) { + + alt_32 i; + alt_u8 common_1000 = 1; + alt_u8 common_100 = 1; + alt_u8 common_10 = 1; + + alt_32 common_speed; + + alt_u8 none_an_complete = 1; + + alt_tse_mac_info *pmac_info = 0; + alt_tse_phy_info *pphy = 0; + + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + + /* reset Auto-Negotiation advertisement */ + for(i = 0; i < pmac_group->channel; i++) { + pmac_info = pmac_group->pmac_info[i]; + pphy = pmac_info->pphy_info; + + /* run only if PHY connected */ + if(pphy) { + alt_tse_phy_set_adv_1000(pphy, 1); + alt_tse_phy_set_adv_100(pphy, 1); + alt_tse_phy_set_adv_10(pphy, 1); + } + tse_dprintf(6, "\n"); + } + + /* loop through every PHY connected */ + for(i = 0; i < pmac_group->channel; i++) { + + pmac_info = pmac_group->pmac_info[i]; + pphy = pmac_info->pphy_info; + + /* if no PHY connected */ + if(!pphy) { + continue; + } + + /* get PHY capability */ + /* skip for PHY with Auto-Negotiation not completed */ + if(alt_tse_phy_get_cap(pphy) != TSE_PHY_AN_COMPLETE) { + continue; + } + + none_an_complete = 0; + + /* Small MAC */ + if(pmac_info->mac_type == ALTERA_TSE_MACLITE_10_100) { + common_1000 = 0; + } + else if(pmac_info->mac_type == ALTERA_TSE_MACLITE_1000) { + common_100 = 0; + common_10 = 0; + } + + /* get common capabilities for all PHYs and link partners */ + common_1000 &= ((pphy->link_capability.cap_1000_base_t_full & pphy->link_capability.lp_1000_base_t_full)); + //(pphy->link_capability.cap_1000_base_t_half & pphy->link_capability.lp_1000_base_t_half)); + common_100 &= ((pphy->link_capability.cap_100_base_x_full & pphy->link_capability.lp_100_base_tx_full) | + (pphy->link_capability.cap_100_base_x_half & pphy->link_capability.lp_100_base_tx_half) | + (pphy->link_capability.cap_100_base_t4 & pphy->link_capability.lp_100_base_t4)); + common_10 &= ((pphy->link_capability.cap_10_base_t_full & pphy->link_capability.lp_10_base_tx_full) | + (pphy->link_capability.cap_10_base_t_half & pphy->link_capability.lp_10_base_tx_half)); + + } + + /* get common speed based on capabilities */ + if(none_an_complete == 1) { + common_speed = TSE_PHY_SPEED_NO_COMMON; + tse_dprintf(2, "ERROR : MAC Group[%d] - None of the PHYs Auto-Negotiation completed!\n", mac_group_index); + } + else if(common_1000) { + common_speed = TSE_PHY_SPEED_1000; + tse_dprintf(5, "INFO : MAC Group[%d] - Common Speed : %d Mbps\n", mac_group_index, 1000); + } + else if(common_100) { + common_speed = TSE_PHY_SPEED_100; + tse_dprintf(5, "INFO : MAC Group[%d] - Common Speed : %d Mbps\n", mac_group_index, 100); + } + else if(common_10) { + common_speed = TSE_PHY_SPEED_10; + tse_dprintf(5, "INFO : MAC Group[%d] - Common Speed : %d Mbps\n", mac_group_index, 10); + } + else { + common_speed = TSE_PHY_SPEED_NO_COMMON; + tse_dprintf(2, "ERROR : MAC Group[%d] - No common speed at all!\n", mac_group_index); } + + return common_speed; +} + + +/* @Function Description: Set the common speed to all PHYs connected to the MAC within the same group + * @API Type: Internal + * @param pmac_group Pointer to the TSE MAC Group structure which group all the MACs that should use the same speed + * common_speed common speed supported by all PHYs + * @return common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if invalid common speed specified + */ +alt_32 alt_tse_phy_set_common_speed(alt_tse_mac_group *pmac_group, alt_32 common_speed) { + + alt_32 i; + + alt_u8 speed; + alt_u8 duplex; + + alt_u8 gb_capable; + + alt_tse_phy_info *pphy = 0; + alt_tse_mac_info *pmac_info = 0; + alt_tse_system_info *psys = 0; + + /* get index of the pointers in pointer array list */ + alt_8 mac_info_index = 0; + alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); + + /* Record previous MDIO address, to be restored at the end of function */ + np_tse_mac *pmac_group_base = (np_tse_mac *)pmac_group->pmac_info[0]->psys_info->tse_mac_base; + alt_32 mdioadd_prev = IORD(&pmac_group_base->MDIO_ADDR1, 0); + + if((common_speed < TSE_PHY_SPEED_10) || (common_speed > TSE_PHY_SPEED_1000)) { + tse_dprintf(2, "ERROR : MAC Group[%d] - Invalid common speed specified! common speed = %d\n", mac_group_index, (int)common_speed); + /* Restore previous MDIO address */ + IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdioadd_prev); + return TSE_PHY_SPEED_NO_COMMON; + } + + /* loop through every PHY connected */ + for(i = 0; i < pmac_group->channel; i++) { + pmac_info = pmac_group->pmac_info[i]; + mac_info_index = alt_tse_get_mac_info_index(pmac_info); + + pphy = pmac_info->pphy_info; + + /* if no PHY connected */ + if(!pphy) { + continue; + } + + psys = pmac_info->psys_info; + + /* write PHY address to MDIO to access the i-th PHY */ + alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address); + + /* capability of PHY supports 1000 Mbps */ + gb_capable = pphy->link_capability.cap_1000_base_t_full || pphy->link_capability.cap_1000_base_t_half || + pphy->link_capability.cap_1000_base_x_full || pphy->link_capability.cap_1000_base_x_half; + + /* if PHY does not supports 1000 Mbps, and common speed is 1000 Mbps */ + if((!gb_capable) && (common_speed == TSE_PHY_SPEED_1000)) { + tse_dprintf(2, "ERROR : PHY[%d.%d] - PHY does not support 1000 Mbps, please specify valid common speed\n", mac_group_index, mac_info_index); + /* Restore previous MDIO address */ + IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdioadd_prev); + return TSE_PHY_SPEED_NO_COMMON; + } + + /* if PHY is not Auto-Negotiation capable */ + if(!alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_ABILITY, 1)) { + + /* if PHY supports 1000 Mbps, write msb of speed */ + if(gb_capable) { + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_SPEED_MSB, 1, common_speed >> 1); + } + /* write lsb of speed */ + alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_SPEED_LSB, 1, common_speed); + + /* continue to next PHY */ + continue; + } + + /* set Auto-Negotiation advertisement based on common speed */ + if(common_speed == TSE_PHY_SPEED_1000) { + alt_tse_phy_set_adv_1000(pphy, 1); + alt_tse_phy_set_adv_100(pphy, 1); + alt_tse_phy_set_adv_10(pphy, 1); + } + else if(common_speed == TSE_PHY_SPEED_100) { + alt_tse_phy_set_adv_1000(pphy, 0); + alt_tse_phy_set_adv_100(pphy, 1); + alt_tse_phy_set_adv_10(pphy, 1); + } + else if(common_speed == TSE_PHY_SPEED_10) { + alt_tse_phy_set_adv_1000(pphy, 0); + alt_tse_phy_set_adv_100(pphy, 0); + alt_tse_phy_set_adv_10(pphy, 1); + } + else { + alt_tse_phy_set_adv_1000(pphy, 0); + alt_tse_phy_set_adv_100(pphy, 0); + alt_tse_phy_set_adv_10(pphy, 0); + } + + /* if PHY Auto-Negotiation is completed */ + if(alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_COMPLETE, 1) == 1) { + + /* read both msb and lsb of speed bits if PHY support 1000 Mbps */ + if(gb_capable) { + + /* get speed information after Auto-Negotiation */ + speed = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->speed_lsb_location, 2); + } + + /* read lsb of speed only if PHY support only 10/100 Mbps */ + else { + /* get speed and link information after Auto-Negotiation */ + speed = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->speed_lsb_location, 1); + } + + /* if current speed != common speed, then restart Auto-Negotiation */ + if(speed != common_speed) { + alt_tse_phy_restart_an(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD); + } + + /* get speed information after Auto-Negotiation */ + duplex = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->duplex_bit_location, 1); + + /* Set MAC duplex register */ + alt_tse_mac_set_duplex((np_tse_mac *)psys->tse_mac_base, duplex); + + } + tse_dprintf(5, "INFO : PHY[%d.%d] - PHY STATUS = 0x%04x\n\n", mac_group_index, mac_info_index, (int) alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, 0, 16)); + } + tse_dprintf(5, "INFO : MAC Group[%d] - All PHYs set to common speed : %d Mbps\n", mac_group_index, (common_speed == TSE_PHY_SPEED_1000) ? 1000 : ((common_speed == TSE_PHY_SPEED_100) ? 100 : 10)); + + /* Set MAC speed register */ + alt_tse_mac_set_speed(pmac_group_base, common_speed); + + /* Restore previous MDIO address */ + IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdioadd_prev); + + return common_speed; +} + + + +/* @Function Description: Additional configuration for Marvell PHY + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address of MAC group + */ +alt_32 marvell_phy_cfg(np_tse_mac *pmac) { + + alt_u16 dat; + + /* If there is no link yet, we enable auto crossover and reset the PHY */ + if((IORD(&pmac->mdio1.STATUS, 0) & PCS_ST_an_done) == 0) { + tse_dprintf(5, "MARVELL : Enabling auto crossover\n"); + IOWR(&pmac->mdio1.CONTROL, 16, 0x0078); + tse_dprintf(5, "MARVELL : PHY reset\n"); + dat = IORD(&pmac->mdio1.CONTROL, 0); + IOWR(&pmac->mdio1.CONTROL, 0, dat | PCS_CTL_sw_reset); + } + + return 0; +} + + +/* @Function Description: Change operating mode of Marvell PHY to GMII + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group + */ +alt_32 marvell_cfg_gmii(np_tse_mac *pmac) { + + alt_u16 dat = IORD(&pmac->mdio1.reg1b, 0); + dat &= 0xfff0; + + tse_dprintf(5, "MARVELL : Mode changed to GMII to copper mode\n"); + IOWR(&pmac->mdio1.reg1b, 0, dat | 0xf); + + tse_dprintf(5, "MARVELL : Disable RGMII Timing Control\n"); + dat = IORD(&pmac->mdio1.reg14, 0); + dat &= ~0x82; + IOWR(&pmac->mdio1.reg14, 0, dat); + + tse_dprintf(5, "MARVELL : PHY reset\n"); + dat = IORD(&pmac->mdio1.CONTROL, 0); + IOWR(&pmac->mdio1.CONTROL, 0, dat | PCS_CTL_sw_reset); + + return 1; +} + +/* @Function Description: Change operating mode of Marvell PHY to SGMII + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group + */ +alt_32 marvell_cfg_sgmii(np_tse_mac *pmac) { + + alt_u16 dat = IORD(&pmac->mdio1.reg1b, 0); + dat &= 0xfff0; + + tse_dprintf(5, "MARVELL : Mode changed to SGMII without clock with SGMII Auto-Neg to copper mode\n"); + IOWR(&pmac->mdio1.reg1b, 0, dat | 0x4); + + tse_dprintf(5, "MARVELL : Disable RGMII Timing Control\n"); + dat = IORD(&pmac->mdio1.reg14, 0); + dat &= ~0x82; + IOWR(&pmac->mdio1.reg14, 0, dat); + + tse_dprintf(5, "MARVELL : PHY reset\n"); + dat = IORD(&pmac->mdio1.CONTROL, 0); + IOWR(&pmac->mdio1.CONTROL, 0, dat | PCS_CTL_sw_reset); + + return 1; +} + +/* @Function Description: Change operating mode of Marvell PHY to RGMII + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group + */ +alt_32 marvell_cfg_rgmii(np_tse_mac *pmac) { + + + alt_u16 dat = IORD(&pmac->mdio1.reg1b, 0); + dat &= 0xfff0; + + tse_dprintf(5, "MARVELL : Mode changed to RGMII/Modified MII to Copper mode\n"); + IOWR(&pmac->mdio1.reg1b, 0, dat | 0xb); + + tse_dprintf(5, "MARVELL : Enable RGMII Timing Control\n"); + dat = IORD(&pmac->mdio1.reg14, 0); + dat &= ~0x82; + dat |= 0x82; + IOWR(&pmac->mdio1.reg14, 0, dat); + + tse_dprintf(5, "MARVELL : PHY reset\n"); + dat = IORD(&pmac->mdio1.CONTROL, 0); + IOWR(&pmac->mdio1.CONTROL, 0, dat | PCS_CTL_sw_reset); + + return 1; + +} + +/* @Function Description: Read link status from PHY specific status register of DP83848C + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group + */ +alt_u32 DP83848C_link_status_read(np_tse_mac *pmac) { + alt_u32 link_status = 0; + alt_u32 reg_status = IORD(&pmac->mdio1.reg10, 0); + + /* If speed == 10 Mbps */ + if(reg_status & 0x2) { + link_status |= 0x8; + } + /* Else speed = 100 Mbps */ + else { + link_status |= 0x4; + } + + /* If duplex == Full */ + if(reg_status & 0x4) { + link_status |= 0x1; + } + + return link_status; +} + +/* @Function Description: Additional configuration for PEF7071 Phy + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group + */ +alt_32 PEF7071_config(np_tse_mac *pmac) +{ + alt_u16 dat; + + dat = IORD(&pmac->mdio1.reg14, 0); + dat &= 0x3FFF; + dat |= 0x0100; + IOWR(&pmac->mdio1.reg14, 0, dat); + + return 0; + +} + +/* @Function Description: Read link status from PHY specific status register of PEF7071 + * @API Type: Internal + * @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group + */ +alt_u32 PEF7071_link_status_read(np_tse_mac *pmac) +{ + alt_u32 link_status = 0; + alt_u32 reg18 = IORD(&pmac->mdio1.reg18, 0); + + if ((reg18 & 0x3)==0) { link_status |= 0x8; } /* If speed == 10 Mbps */ + if ((reg18 & 0x3)==1) { link_status |= 0x4; } /* Else speed = 100 Mbps */ + if ((reg18 & 0x3)==2) { link_status |= 0x2; } /* Else speed = 1000 Mbps */ + + /* If duplex == Full */ + if(reg18 & 0x8) { + link_status |= 0x1; + } + + return link_status; +} diff --git a/FPGA_nios/q_sys.sopcinfo b/FPGA_nios/q_sys.sopcinfo new file mode 100644 index 0000000..bcbaa52 --- /dev/null +++ b/FPGA_nios/q_sys.sopcinfo @@ -0,0 +1,45271 @@ + + + + + + + java.lang.Integer + 1729065917 + false + true + false + true + GENERATION_ID + + + java.lang.String + + false + true + false + true + UNIQUE_ID + + + java.lang.String + MAX10FPGA + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + 10M50DAF484C6GES + false + true + false + true + DEVICE + + + java.lang.String + 6 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.Long + -1 + false + true + false + true + CLOCK_RATE + clock_bridge_0_in_clk + + + java.lang.Integer + -1 + false + true + false + true + CLOCK_DOMAIN + clock_bridge_0_in_clk + + + java.lang.Integer + -1 + false + true + false + true + RESET_DOMAIN + clock_bridge_0_in_clk + + + java.lang.Long + -1 + false + true + false + true + CLOCK_RATE + ddr3_ram_pll_ref_clk + + + java.lang.Integer + -1 + false + true + false + true + CLOCK_DOMAIN + ddr3_ram_pll_ref_clk + + + java.lang.Integer + -1 + false + true + false + true + RESET_DOMAIN + ddr3_ram_pll_ref_clk + + + java.lang.Long + -1 + false + true + false + true + CLOCK_RATE + eth_tse_pcs_mac_rx_clock_connection + + + java.lang.Integer + -1 + false + true + false + true + CLOCK_DOMAIN + eth_tse_pcs_mac_rx_clock_connection + + + java.lang.Integer + -1 + false + true + false + true + RESET_DOMAIN + eth_tse_pcs_mac_rx_clock_connection + + + java.lang.Long + -1 + false + true + false + true + CLOCK_RATE + eth_tse_pcs_mac_tx_clock_connection + + + java.lang.Integer + -1 + false + true + false + true + CLOCK_DOMAIN + eth_tse_pcs_mac_tx_clock_connection + + + java.lang.Integer + -1 + false + true + false + true + RESET_DOMAIN + eth_tse_pcs_mac_tx_clock_connection + + + java.lang.Long + -1 + false + true + false + true + CLOCK_RATE + sys_clk + + + java.lang.Integer + -1 + false + true + false + true + CLOCK_DOMAIN + sys_clk + + + java.lang.Integer + -1 + false + true + false + true + RESET_DOMAIN + sys_clk + + + java.lang.String + MAX 10 + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + java.lang.String + altpll_avalon_elaboration + false + true + false + true + + + java.lang.String + altpll_avalon_post_edit + false + true + false + true + + + java.lang.String + MAX 10 + false + true + true + true + + + java.lang.String + 5 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + 20000 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + NORMAL + false + true + true + true + + + java.lang.String + AUTO + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + CLK0 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + AUTO + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + 5 + false + true + true + true + + + java.lang.String + 1 + false + true + true + true + + + java.lang.String + 1 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + 1 + false + true + true + true + + + java.lang.String + 2 + false + true + true + true + + + java.lang.String + 20 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + 0 + false + true + true + true + + + java.lang.String + 15000 + false + true + true + true + + + java.lang.String + 0 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + 50 + false + true + true + true + + + java.lang.String + 50 + false + true + true + true + + + java.lang.String + 50 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_USED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_USED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_USED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + PORT_USED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + NO + false + true + true + true + + + java.lang.String + CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 15000 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 2 CT#PORT_LOCKED PORT_USED + false + true + false + true + + + java.lang.String + PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 0 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 0 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ2 100.00000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 6 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT2 0.00000000 PT#PHASE_SHIFT1 135.00000000 PT#DIV_FACTOR2 20 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 2 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 250.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 5 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1423823783608952.mif PT#ACTIVECLK_CHECK 0 + false + true + false + true + + + java.lang.String + UP#locked used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used + false + true + false + true + + + java.lang.String + IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1 + false + true + false + true + + + java.lang.String + MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1 + false + true + false + true + + + java.lang.String + IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} + false + true + false + true + + + java.lang.String + 0 + false + true + false + true + + + java.lang.String + MAX10FPGA + false + true + false + true + DEVICE_FAMILY + + + java.lang.Long + 50000000 + false + true + false + true + CLOCK_RATE + inclk_interface + + + java.lang.String + MAX 10 + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + inclk_interface + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset + Input + 1 + reset + + + + + + embeddedsw.configuration.isMemoryDevice + false + + + embeddedsw.configuration.isNonVolatileStorage + false + + + embeddedsw.configuration.isPrintableDevice + false + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 16 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + inclk_interface + false + true + true + true + + + java.lang.String + inclk_interface_reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + read + Input + 1 + read + + + write + Input + 1 + write + + + address + Input + 2 + address + + + readdata + Output + 32 + readdata + + + writedata + Input + 32 + writedata + + + + + + java.lang.String + + false + true + true + true + + + long + 250000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + c0 + Output + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + areset + Input + 1 + export + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + locked + Output + 1 + export + + + + + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 9 + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0 + + + embeddedsw.CMacro.EDGE_TYPE + NONE + + + embeddedsw.CMacro.FREQ + 50000000 + + + embeddedsw.CMacro.HAS_IN + 1 + + + embeddedsw.CMacro.HAS_OUT + 0 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.IRQ_TYPE + NONE + + + embeddedsw.CMacro.RESET_VALUE + 0 + + + embeddedsw.dts.compatible + altr,pio-1.0 + + + embeddedsw.dts.group + gpio + + + embeddedsw.dts.name + pio + + + embeddedsw.dts.params.altr,gpio-bank-width + 9 + + + embeddedsw.dts.params.resetvalue + 0 + + + embeddedsw.dts.vendor + altr + + + boolean + false + false + false + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + Input + false + true + true + true + + + java.lang.String + RISING + false + false + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + LEVEL + false + false + true + true + + + long + 0 + false + false + true + true + + + boolean + false + false + true + true + true + + + long + 0 + false + false + true + true + + + int + 9 + false + true + true + true + + + long + 50000000 + false + true + false + true + CLOCK_RATE + clk + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 4 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + readdata + Output + 32 + readdata + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + in_port + Input + 9 + export + + + + + + + embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR + 0 + + + embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE + 0 + + + embeddedsw.CMacro.CONTENTS_INFO + "" + + + embeddedsw.CMacro.DUAL_PORT + 1 + + + embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE + AUTO + + + embeddedsw.CMacro.INIT_CONTENTS_FILE + q_sys_calibration_ram + + + embeddedsw.CMacro.INIT_MEM_CONTENT + 0 + + + embeddedsw.CMacro.INSTANCE_ID + NONE + + + embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED + 0 + + + embeddedsw.CMacro.RAM_BLOCK_TYPE + AUTO + + + embeddedsw.CMacro.READ_DURING_WRITE_MODE + DONT_CARE + + + embeddedsw.CMacro.SINGLE_CLOCK_OP + 0 + + + embeddedsw.CMacro.SIZE_MULTIPLE + 1 + + + embeddedsw.CMacro.SIZE_VALUE + 640 + + + embeddedsw.CMacro.WRITABLE + 1 + + + embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR + SIM_DIR + + + embeddedsw.memoryInfo.GENERATE_DAT_SYM + 1 + + + embeddedsw.memoryInfo.GENERATE_HEX + 1 + + + embeddedsw.memoryInfo.HAS_BYTE_LANE + 0 + + + embeddedsw.memoryInfo.HEX_INSTALL_DIR + QPF_DIR + + + embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH + 16 + + + embeddedsw.memoryInfo.MEM_INIT_FILENAME + q_sys_calibration_ram + + + postgeneration.simulation.init_file.param_name + INIT_FILE + + + postgeneration.simulation.init_file.type + MEM_INIT + + + boolean + false + false + true + true + true + + + java.lang.String + AUTO + false + true + true + true + + + int + 16 + false + true + true + true + + + int + 16 + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + true + true + + + java.lang.String + onchip_mem.hex + false + false + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + NONE + false + false + true + true + + + long + 640 + false + true + true + true + + + java.lang.String + DONT_CARE + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + true + true + false + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + false + false + true + + + boolean + false + false + false + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + q_sys_calibration_ram + false + true + false + true + UNIQUE_ID + + + java.lang.String + MAX10FPGA + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + false + true + false + true + DEVICE_FEATURES + + + int + 9 + true + true + false + true + + + int + 9 + true + true + false + true + + + int + 16 + true + true + false + true + + + int + 16 + true + true + false + true + + + java.lang.String + Automatic + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + q_sys_calibration_ram.hex + true + true + false + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 1 + false + true + false + true + + + java.math.BigInteger + 640 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk1 + false + true + true + true + + + java.lang.String + reset1 + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 640 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 9 + address + + + clken + Input + 1 + clken + + + chipselect + Input + 1 + chipselect + + + write + Input + 1 + write + + + readdata + Output + 16 + readdata + + + writedata + Input + 16 + writedata + + + byteenable + Input + 2 + byteenable + + + + + + java.lang.String + clk1 + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset + Input + 1 + reset + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 1 + false + true + false + true + + + java.math.BigInteger + 640 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk2 + false + true + true + true + + + java.lang.String + reset2 + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 640 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address2 + Input + 9 + address + + + chipselect2 + Input + 1 + chipselect + + + clken2 + Input + 1 + clken + + + write2 + Input + 1 + write + + + readdata2 + Output + 16 + readdata + + + writedata2 + Input + 16 + writedata + + + byteenable2 + Input + 2 + byteenable + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk2 + Input + 1 + clk + + + + + + java.lang.String + clk2 + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset2 + Input + 1 + reset + + + + + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + true + false + true + true + true + + + java.lang.String + YES + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 4 + false + true + true + true + + + boolean + true + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + [Ljava.lang.String; + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 4 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + false + + in_data + Input + 32 + data + + + in_valid + Input + 1 + valid + + + in_ready + Output + 1 + ready + + + in_startofpacket + Input + 1 + startofpacket + + + in_endofpacket + Input + 1 + endofpacket + + + in_empty + Input + 2 + empty + + + in_error + Input + 1 + error + + + in_channel + Input + 1 + channel + + + + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 4 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + true + + out_data + Output + 32 + data + + + out_valid + Output + 1 + valid + + + out_ready + Input + 1 + ready + + + out_startofpacket + Output + 1 + startofpacket + + + out_endofpacket + Output + 1 + endofpacket + + + out_empty + Output + 2 + empty + + + out_error + Output + 1 + error + + + + + + + debug.hostConnection + type jtag id 70:34|110:135 + + + embeddedsw.CMacro.BIG_ENDIAN + 0 + + + embeddedsw.CMacro.BREAK_ADDR + 0x18402820 + + + embeddedsw.CMacro.CPU_ARCH_NIOS2_R1 + + + + embeddedsw.CMacro.CPU_FREQ + 50000000u + + + embeddedsw.CMacro.CPU_ID_SIZE + 1 + + + embeddedsw.CMacro.CPU_ID_VALUE + 0x00000000 + + + embeddedsw.CMacro.CPU_IMPLEMENTATION + "fast" + + + embeddedsw.CMacro.DATA_ADDR_WIDTH + 29 + + + embeddedsw.CMacro.DCACHE_BYPASS_MASK + 0x80000000 + + + embeddedsw.CMacro.DCACHE_LINE_SIZE + 32 + + + embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2 + 5 + + + embeddedsw.CMacro.DCACHE_SIZE + 2048 + + + embeddedsw.CMacro.EXCEPTION_ADDR + 0x08000120 + + + embeddedsw.CMacro.FLASH_ACCELERATOR_LINES + 0 + + + embeddedsw.CMacro.FLASH_ACCELERATOR_LINE_SIZE + 0 + + + embeddedsw.CMacro.FLUSHDA_SUPPORTED + + + + embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT + 0 + + + embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT + 1 + + + embeddedsw.CMacro.HARDWARE_MULX_PRESENT + 0 + + + embeddedsw.CMacro.HAS_DEBUG_CORE + 1 + + + embeddedsw.CMacro.HAS_DEBUG_STUB + + + + embeddedsw.CMacro.HAS_EXTRA_EXCEPTION_INFO + + + + embeddedsw.CMacro.HAS_ILLEGAL_INSTRUCTION_EXCEPTION + + + + embeddedsw.CMacro.HAS_JMPI_INSTRUCTION + + + + embeddedsw.CMacro.ICACHE_LINE_SIZE + 32 + + + embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2 + 5 + + + embeddedsw.CMacro.ICACHE_SIZE + 2048 + + + embeddedsw.CMacro.INITDA_SUPPORTED + + + + embeddedsw.CMacro.INST_ADDR_WIDTH + 29 + + + embeddedsw.CMacro.NUM_OF_SHADOW_REG_SETS + 0 + + + embeddedsw.CMacro.OCI_VERSION + 1 + + + embeddedsw.CMacro.RESET_ADDR + 0x14000000 + + + embeddedsw.configuration.DataCacheVictimBufImpl + ram + + + embeddedsw.configuration.HDLSimCachesCleared + 1 + + + embeddedsw.configuration.breakOffset + 32 + + + embeddedsw.configuration.breakSlave + cpu.debug_mem_slave + + + embeddedsw.configuration.cpuArchitecture + Nios II + + + embeddedsw.configuration.exceptionOffset + 288 + + + embeddedsw.configuration.exceptionSlave + ddr3_ram.avl + + + embeddedsw.configuration.resetOffset + 0 + + + embeddedsw.configuration.resetSlave + ext_flash.avl_mem + + + embeddedsw.dts.compatible + altr,nios2-1.1 + + + embeddedsw.dts.group + cpu + + + embeddedsw.dts.name + nios2 + + + embeddedsw.dts.params.altr,exception-addr + 0x08000120 + + + embeddedsw.dts.params.altr,has-initda + 1 + + + embeddedsw.dts.params.altr,has-mul + 1 + + + embeddedsw.dts.params.altr,implementation + "fast" + + + embeddedsw.dts.params.altr,reset-addr + 0x14000000 + + + embeddedsw.dts.params.clock-frequency + 50000000u + + + embeddedsw.dts.params.dcache-line-size + 32 + + + embeddedsw.dts.params.dcache-size + 2048 + + + embeddedsw.dts.params.icache-line-size + 32 + + + embeddedsw.dts.params.icache-size + 2048 + + + embeddedsw.dts.vendor + altr + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + false + true + true + + + int + 0 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 8 + false + false + true + true + + + int + 8 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + true + true + true + + + int + 288 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 32 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + ext_flash.avl_mem + false + true + true + true + + + java.lang.String + + false + false + true + true + + + java.lang.String + ddr3_ram.avl + false + true + true + true + + + java.lang.String + cpu.jtag_debug_module + false + true + false + true + + + java.lang.String + Internal + false + true + true + true + + + java.lang.String + Dynamic + false + true + true + true + + + int + 8 + false + true + true + true + + + int + 1 + false + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + fast_le_shift + true + true + false + true + + + java.lang.String + mul_fast32 + true + true + false + true + + + int + 0 + false + true + true + true + + + int + 3 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + java.lang.String + no_div + false + true + true + true + + + int + 12 + false + false + true + true + + + int + 12 + false + false + true + true + + + int + 4 + false + false + true + true + + + int + 6 + false + false + true + true + + + int + 7 + false + false + true + true + + + int + 16 + false + false + true + true + + + int + 8 + false + false + true + true + + + java.lang.String + Fast + false + true + true + true + + + int + 2048 + false + true + true + true + + + int + 2 + false + false + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + Automatic + false + true + false + true + + + java.lang.String + Automatic + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + None + false + true + true + true + + + java.lang.String + false + false + true + true + true + + + java.lang.String + ram + false + true + true + true + + + int + 2048 + false + true + true + true + + + java.lang.String + Automatic + false + true + false + true + + + java.lang.String + Automatic + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + Automatic + false + true + false + true + + + java.lang.String + Automatic + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + Automatic + false + true + false + true + + + java.lang.String + Automatic + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + _128 + false + false + true + true + + + int + 2 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + none + false + true + true + true + + + java.lang.String + onchip_trace + false + false + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 335544320 + true + true + true + true + + + int + 134218016 + true + true + true + true + + + int + 406857760 + true + true + false + true + + + int + 0 + true + true + true + true + + + java.lang.String + false + true + true + false + true + + + int + 2048 + true + true + false + true + + + java.lang.String + cpu.debug_mem_slave + true + true + false + true + + + int + 32 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + java.lang.String + "synthesis translate_on" + true + true + false + true + + + java.lang.String + "synthesis translate_off" + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 29 + false + true + false + true + ADDRESS_WIDTH + instruction_master + + + int + 1 + false + true + false + true + ADDRESS_WIDTH + flash_instruction_master + + + int + 29 + false + true + false + true + ADDRESS_WIDTH + data_master + + + int + 1 + false + true + false + true + ADDRESS_WIDTH + tightly_coupled_data_master_0 + + + int + 1 + false + true + false + true + ADDRESS_WIDTH + tightly_coupled_data_master_1 + + + int + 1 + false + true + false + true + ADDRESS_WIDTH + tightly_coupled_data_master_2 + + + int + 1 + false + true + false + true + ADDRESS_WIDTH + tightly_coupled_data_master_3 + + + int + 1 + false + true + false + true + ADDRESS_WIDTH + tightly_coupled_instruction_master_0 + + + int + 1 + false + true + false + true + ADDRESS_WIDTH + tightly_coupled_instruction_master_1 + + + int + 1 + false + true + false + true + ADDRESS_WIDTH + tightly_coupled_instruction_master_2 + + + int + 1 + false + true + false + true + ADDRESS_WIDTH + tightly_coupled_instruction_master_3 + + + int + 1 + false + true + false + true + ADDRESS_WIDTH + data_master_high_performance + + + int + 1 + false + true + false + true + ADDRESS_WIDTH + instruction_master_high_performance + + + java.lang.String + ]]> + false + true + false + true + ADDRESS_MAP + instruction_master + + + java.lang.String + + false + true + false + true + ADDRESS_MAP + flash_instruction_master + + + java.lang.String + ]]> + false + true + false + true + ADDRESS_MAP + data_master + + + java.lang.String + + false + true + false + true + ADDRESS_MAP + tightly_coupled_data_master_0 + + + java.lang.String + + false + true + false + true + ADDRESS_MAP + tightly_coupled_data_master_1 + + + java.lang.String + + false + true + false + true + ADDRESS_MAP + tightly_coupled_data_master_2 + + + java.lang.String + + false + true + false + true + ADDRESS_MAP + tightly_coupled_data_master_3 + + + java.lang.String + + false + true + false + true + ADDRESS_MAP + tightly_coupled_instruction_master_0 + + + java.lang.String + + false + true + false + true + ADDRESS_MAP + tightly_coupled_instruction_master_1 + + + java.lang.String + + false + true + false + true + ADDRESS_MAP + tightly_coupled_instruction_master_2 + + + java.lang.String + + false + true + false + true + ADDRESS_MAP + tightly_coupled_instruction_master_3 + + + java.lang.String + + false + true + false + true + ADDRESS_MAP + data_master_high_performance + + + java.lang.String + + false + true + false + true + ADDRESS_MAP + instruction_master_high_performance + + + long + 50000000 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.String + MAX10FPGA + false + true + false + true + DEVICE_FAMILY + + + long + 61 + false + true + false + true + INTERRUPTS_USED + irq + + + java.lang.String + ]]> + false + true + false + true + CUSTOM_INSTRUCTION_SLAVES + custom_instruction_master + + + java.lang.String + ]]> + false + true + false + true + CUSTOM_INSTRUCTION_SLAVES + custom_instruction_master_a + + + java.lang.String + ]]> + false + true + false + true + CUSTOM_INSTRUCTION_SLAVES + custom_instruction_master_b + + + java.lang.String + ]]> + false + true + false + true + CUSTOM_INSTRUCTION_SLAVES + custom_instruction_master_c + + + java.lang.String + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + false + true + false + true + DEVICE_FEATURES + + + java.lang.String + 10M50DAF484C6GES + false + true + false + true + DEVICE + + + java.lang.String + 6 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.Integer + 14 + false + true + false + true + CLOCK_DOMAIN + clk + + + java.lang.Integer + 14 + false + true + false + true + RESET_DOMAIN + clk + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + reset_req + Input + 1 + reset_req + + + + + + debug.providesServices + master + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 1 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + true + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 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+ + + d_byteenable + Output + 4 + byteenable + + + d_read + Output + 1 + read + + + d_readdata + Input + 32 + readdata + + + d_waitrequest + Input + 1 + waitrequest + + + d_write + Output + 1 + write + + + d_writedata + Output + 32 + writedata + + + d_readdatavalid + Input + 1 + readdatavalid + + + debug_mem_slave_debugaccess_to_roms + Output + 1 + debugaccess + + + false + ddr3_ram + avl + ddr3_ram.avl + 134217728 + 134217728 + + + false + ext_flash + avl_csr + ext_flash.avl_csr + 406863136 + 32 + + + false + ext_flash + avl_mem + ext_flash.avl_mem + 335544320 + 67108864 + + + false + eth_tse + control_port + eth_tse.control_port + 406859776 + 1024 + + + false + sysid + control_slave + sysid.control_slave + 406863208 + 8 + + + false + msgdma_tx + csr + msgdma_tx.csr + 406863104 + 32 + + + false + msgdma_rx + csr + msgdma_rx.csr + 406863072 + 32 + + + false + onchip_flash + csr + onchip_flash.csr + 406863200 + 8 + + + false + udp_generator + csr + udp_generator.csr + 406863040 + 32 + + + false + sensor_interface + csr + sensor_interface.csr + 406863184 + 16 + + + false + onchip_flash + data + onchip_flash.data + 404750336 + 1441792 + + + false + cpu + debug_mem_slave + cpu.debug_mem_slave + 406857728 + 2048 + + + false + msgdma_tx + prefetcher_csr + msgdma_tx.prefetcher_csr + 406863008 + 32 + + + false + msgdma_rx + prefetcher_csr + msgdma_rx.prefetcher_csr + 406862976 + 32 + + + false + descriptor_memory + s1 + descriptor_memory.s1 + 406847488 + 8192 + + + false + sys_clk_timer + s1 + sys_clk_timer.s1 + 406862944 + 32 + + + false + output_pio + s1 + output_pio.s1 + 406862912 + 32 + + + false + button_pio + s1 + button_pio.s1 + 406863168 + 16 + + + false + debug_uart + s1 + debug_uart.s1 + 406862880 + 32 + + + false + frame_timer + s1 + frame_timer.s1 + 406862848 + 32 + + + false + calibration_ram + s1 + calibration_ram.s1 + 406860800 + 640 + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 1 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + true + 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onchip_flash + data + onchip_flash.data + 404750336 + 1441792 + + + false + cpu + debug_mem_slave + cpu.debug_mem_slave + 406857728 + 2048 + + + + + + com.altera.entityinterfaces.IConnectionPoint + cpu.data_master + false + true + true + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + java.lang.String + + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + INDIVIDUAL_REQUESTS + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + true + + irq + Input + 32 + irq + + + false + msgdma_tx + csr_irq + msgdma_tx.csr_irq + 2 + + + false + msgdma_rx + csr_irq + msgdma_rx.csr_irq + 3 + + + false + ext_flash + interrupt_sender + ext_flash.interrupt_sender + 5 + + + false + sys_clk_timer + irq + sys_clk_timer.irq + 0 + + + false + debug_uart + irq + debug_uart.irq + 4 + + + + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + + false + true + true + true + + + [Ljava.lang.String; + none + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + debug_reset_request + Output + 1 + reset + + + + + + embeddedsw.configuration.hideDevice + 1 + + + qsys.ui.connect + instruction_master,data_master + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 2048 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + 0 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + debug_mem_slave_address + Input + 9 + address + + + debug_mem_slave_byteenable + Input + 4 + byteenable + + + debug_mem_slave_debugaccess + Input + 1 + debugaccess + + + debug_mem_slave_read + Input + 1 + read + + + debug_mem_slave_readdata + Output + 32 + readdata + + + debug_mem_slave_waitrequest + Output + 1 + waitrequest + + + debug_mem_slave_write + Input + 1 + write + + + debug_mem_slave_writedata + Input + 32 + writedata + + + + + + java.lang.String + + true + true + false + true + + + int + 8 + false + true + false + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios_custom_instruction + true + + dummy_ci_port + Output + 1 + readra + + + + + + + embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH + 32 + + + postgeneration.simulation.init_file.param_name + ABS_RAM_MEM_INIT_FILENAME + + + postgeneration.simulation.init_file.type + MEM_INIT + + + testbench.partner.map.memory + mem_model.memory + + + testbench.partner.mem_model.class + altera_mem_if_ddr3_mem_model + + + testbench.partner.mem_model.parameter.AC_PARITY + false + + + testbench.partner.mem_model.parameter.AC_ROM_MR0 + 0001000010001 + + + testbench.partner.mem_model.parameter.AC_ROM_MR0_CALIB + + + + testbench.partner.mem_model.parameter.AC_ROM_MR0_DLL_RESET + 0001100010000 + + + testbench.partner.mem_model.parameter.AC_ROM_MR0_DLL_RESET_MIRR + 0001010001000 + + + testbench.partner.mem_model.parameter.AC_ROM_MR0_MIRR + 0001000001001 + + + testbench.partner.mem_model.parameter.AC_ROM_MR1 + 0000000000000 + + + testbench.partner.mem_model.parameter.AC_ROM_MR1_CALIB + + + + testbench.partner.mem_model.parameter.AC_ROM_MR1_MIRR + 0000000000000 + + + testbench.partner.mem_model.parameter.AC_ROM_MR1_OCD_ENABLE + + + + testbench.partner.mem_model.parameter.AC_ROM_MR2 + 0000000000000 + + + testbench.partner.mem_model.parameter.AC_ROM_MR2_MIRR + 0000000000000 + + + testbench.partner.mem_model.parameter.AC_ROM_MR3 + 0000000000000 + + + testbench.partner.mem_model.parameter.AC_ROM_MR3_MIRR + 0000000000000 + + + testbench.partner.mem_model.parameter.ADDR_CMD_DDR + 0 + + + testbench.partner.mem_model.parameter.ADDR_RATE_RATIO + 1 + + + testbench.partner.mem_model.parameter.AFI_ADDR_WIDTH + 28 + + + testbench.partner.mem_model.parameter.AFI_BANKADDR_WIDTH + 6 + + + testbench.partner.mem_model.parameter.AFI_CLK_EN_WIDTH + 2 + + + testbench.partner.mem_model.parameter.AFI_CLK_PAIR_COUNT + 1 + + + testbench.partner.mem_model.parameter.AFI_CONTROL_WIDTH + 2 + + + testbench.partner.mem_model.parameter.AFI_CS_WIDTH + 2 + + + testbench.partner.mem_model.parameter.AFI_DM_WIDTH + 4 + + + testbench.partner.mem_model.parameter.AFI_DQ_WIDTH + 32 + + + testbench.partner.mem_model.parameter.AFI_ODT_WIDTH + 2 + + + testbench.partner.mem_model.parameter.AFI_RATE_RATIO + 2 + + + testbench.partner.mem_model.parameter.AFI_RLAT_WIDTH + 6 + + + testbench.partner.mem_model.parameter.AFI_RRANK_WIDTH + 2 + + + testbench.partner.mem_model.parameter.AFI_WLAT_WIDTH + 6 + + + testbench.partner.mem_model.parameter.AFI_WRANK_WIDTH + 2 + + + testbench.partner.mem_model.parameter.AFI_WRITE_DQS_WIDTH + 2 + + + testbench.partner.mem_model.parameter.ALTMEMPHY_COMPATIBLE_MODE + false + + + testbench.partner.mem_model.parameter.AP_MODE + false + + + testbench.partner.mem_model.parameter.AP_MODE_EN + 0 + + + testbench.partner.mem_model.parameter.CFG_TCCD + 1 + + + testbench.partner.mem_model.parameter.CFG_TCCD_NS + 2.5 + + + testbench.partner.mem_model.parameter.CTL_RD_TO_PCH_EXTRA_CLK + 0 + + + testbench.partner.mem_model.parameter.CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK + 1 + + + testbench.partner.mem_model.parameter.CTL_RD_TO_RD_EXTRA_CLK + 0 + + + testbench.partner.mem_model.parameter.CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK + 1 + + + testbench.partner.mem_model.parameter.CTL_WR_TO_WR_EXTRA_CLK + 0 + + + testbench.partner.mem_model.parameter.CUT_NEW_FAMILY_TIMING + true + + + testbench.partner.mem_model.parameter.DATA_RATE_RATIO + 2 + + + testbench.partner.mem_model.parameter.DAT_DATA_WIDTH + 32 + + + testbench.partner.mem_model.parameter.DEVICE_DEPTH + 1 + + + testbench.partner.mem_model.parameter.DEVICE_FAMILY + MAX 10 + + + testbench.partner.mem_model.parameter.DEVICE_FAMILY_PARAM + + + + testbench.partner.mem_model.parameter.DEVICE_WIDTH + 1 + + + testbench.partner.mem_model.parameter.DISABLE_CHILD_MESSAGING + false + + + testbench.partner.mem_model.parameter.DISCRETE_FLY_BY + true + + + testbench.partner.mem_model.parameter.DQ_DDR + 1 + + + testbench.partner.mem_model.parameter.DUPLICATE_AC + false + + + testbench.partner.mem_model.parameter.FLY_BY + false + + + testbench.partner.mem_model.parameter.FORCE_DQS_TRACKING + AUTO + + + testbench.partner.mem_model.parameter.FORCE_SHADOW_REGS + AUTO + + + testbench.partner.mem_model.parameter.HARD_EMIF + false + + + testbench.partner.mem_model.parameter.HARD_PHY + false + + + testbench.partner.mem_model.parameter.HHP_HPS + false + + + testbench.partner.mem_model.parameter.HHP_HPS_SIMULATION + false + + + testbench.partner.mem_model.parameter.HHP_HPS_VERIFICATION + false + + + testbench.partner.mem_model.parameter.HPS_PROTOCOL + DEFAULT + + + testbench.partner.mem_model.parameter.IS_ES_DEVICE + false + + + testbench.partner.mem_model.parameter.LRDIMM + false + + + testbench.partner.mem_model.parameter.LRDIMM_EXTENDED_CONFIG + 0x000000000000000000 + + + testbench.partner.mem_model.parameter.LRDIMM_INT + 0 + + + testbench.partner.mem_model.parameter.MEM_ASR + Manual + + + testbench.partner.mem_model.parameter.MEM_ATCL + Disabled + + + testbench.partner.mem_model.parameter.MEM_ATCL_INT + 0 + + + testbench.partner.mem_model.parameter.MEM_AUTO_LEVELING_MODE + true + + + testbench.partner.mem_model.parameter.MEM_BANKADDR_WIDTH + 3 + + + testbench.partner.mem_model.parameter.MEM_BL + OTF + + + testbench.partner.mem_model.parameter.MEM_BT + Sequential + + + testbench.partner.mem_model.parameter.MEM_BURST_LENGTH + 8 + + + testbench.partner.mem_model.parameter.MEM_CK_WIDTH + 1 + + + testbench.partner.mem_model.parameter.MEM_CLK_EN_WIDTH + 1 + + + testbench.partner.mem_model.parameter.MEM_CLK_FREQ + 300.0 + + + testbench.partner.mem_model.parameter.MEM_CLK_FREQ_MAX + 800.0 + + + testbench.partner.mem_model.parameter.MEM_CLK_MAX_NS + 1.25 + + + testbench.partner.mem_model.parameter.MEM_CLK_MAX_PS + 1250.0 + + + testbench.partner.mem_model.parameter.MEM_CLK_TO_DQS_CAPTURE_DELAY + 100000 + + + testbench.partner.mem_model.parameter.MEM_COL_ADDR_WIDTH + 10 + + + testbench.partner.mem_model.parameter.MEM_CS_WIDTH + 1 + + + testbench.partner.mem_model.parameter.MEM_DLL_EN + true + + + testbench.partner.mem_model.parameter.MEM_DQS_TO_CLK_CAPTURE_DELAY + 100 + + + testbench.partner.mem_model.parameter.MEM_DQ_PER_DQS + 8 + + + testbench.partner.mem_model.parameter.MEM_DQ_WIDTH + 8 + + + testbench.partner.mem_model.parameter.MEM_DRV_STR + RZQ/6 + + + testbench.partner.mem_model.parameter.MEM_FORMAT + DISCRETE + + + testbench.partner.mem_model.parameter.MEM_GUARANTEED_WRITE_INIT + false + + + testbench.partner.mem_model.parameter.MEM_IF_ADDR_WIDTH + 14 + + + testbench.partner.mem_model.parameter.MEM_IF_ADDR_WIDTH_MIN + 13 + + + testbench.partner.mem_model.parameter.MEM_IF_BANKADDR_WIDTH + 3 + + + testbench.partner.mem_model.parameter.MEM_IF_BOARD_BASE_DELAY + 10 + + + testbench.partner.mem_model.parameter.MEM_IF_CHIP_BITS + 1 + + + testbench.partner.mem_model.parameter.MEM_IF_CK_WIDTH + 1 + + + testbench.partner.mem_model.parameter.MEM_IF_CLK_EN_WIDTH + 1 + + + testbench.partner.mem_model.parameter.MEM_IF_CLK_PAIR_COUNT + 1 + + + testbench.partner.mem_model.parameter.MEM_IF_COL_ADDR_WIDTH + 10 + + + testbench.partner.mem_model.parameter.MEM_IF_CONTROL_WIDTH + 1 + + + testbench.partner.mem_model.parameter.MEM_IF_CS_PER_DIMM + 1 + + + testbench.partner.mem_model.parameter.MEM_IF_CS_PER_RANK + 1 + + + testbench.partner.mem_model.parameter.MEM_IF_CS_WIDTH + 1 + + + testbench.partner.mem_model.parameter.MEM_IF_DM_PINS_EN + true + + + testbench.partner.mem_model.parameter.MEM_IF_DM_WIDTH + 1 + + + testbench.partner.mem_model.parameter.MEM_IF_DQSN_EN + true + + + testbench.partner.mem_model.parameter.MEM_IF_DQS_WIDTH + 1 + + + testbench.partner.mem_model.parameter.MEM_IF_DQ_WIDTH + 8 + + + testbench.partner.mem_model.parameter.MEM_IF_LRDIMM_RM + 0 + + + testbench.partner.mem_model.parameter.MEM_IF_NUMBER_OF_RANKS + 1 + + + testbench.partner.mem_model.parameter.MEM_IF_ODT_WIDTH + 1 + + + testbench.partner.mem_model.parameter.MEM_IF_RD_TO_WR_TURNAROUND_OCT + 2 + + + testbench.partner.mem_model.parameter.MEM_IF_READ_DQS_WIDTH + 1 + + + testbench.partner.mem_model.parameter.MEM_IF_ROW_ADDR_WIDTH + 14 + + + testbench.partner.mem_model.parameter.MEM_IF_SIM_VALID_WINDOW + 0 + + + testbench.partner.mem_model.parameter.MEM_IF_WRITE_DQS_WIDTH + 1 + + + testbench.partner.mem_model.parameter.MEM_IF_WR_TO_RD_TURNAROUND_OCT + 3 + + + testbench.partner.mem_model.parameter.MEM_INIT_EN + false + + + testbench.partner.mem_model.parameter.MEM_INIT_FILE + + + + testbench.partner.mem_model.parameter.MEM_LEVELING + true + + + testbench.partner.mem_model.parameter.MEM_LRDIMM_ENABLED + false + + + testbench.partner.mem_model.parameter.MEM_MIRROR_ADDRESSING + 0 + + + testbench.partner.mem_model.parameter.MEM_MIRROR_ADDRESSING_DEC + 0 + + + testbench.partner.mem_model.parameter.MEM_NUMBER_OF_DIMMS + 1 + + + testbench.partner.mem_model.parameter.MEM_NUMBER_OF_RANKS_PER_DEVICE + 1 + + + testbench.partner.mem_model.parameter.MEM_NUMBER_OF_RANKS_PER_DIMM + 1 + + + testbench.partner.mem_model.parameter.MEM_PD + DLL off + + + testbench.partner.mem_model.parameter.MEM_RANK_MULTIPLICATION_FACTOR + 1 + + + testbench.partner.mem_model.parameter.MEM_REGDIMM_ENABLED + false + + + testbench.partner.mem_model.parameter.MEM_ROW_ADDR_WIDTH + 14 + + + testbench.partner.mem_model.parameter.MEM_RTT_NOM + ODT Disabled + + + testbench.partner.mem_model.parameter.MEM_RTT_WR + Dynamic ODT off + + + testbench.partner.mem_model.parameter.MEM_SRT + Normal + + + testbench.partner.mem_model.parameter.MEM_TCL + 5 + + + testbench.partner.mem_model.parameter.MEM_TDQSCK + 1 + + + testbench.partner.mem_model.parameter.MEM_TFAW + 10 + + + testbench.partner.mem_model.parameter.MEM_TFAW_NS + 30.0 + + + testbench.partner.mem_model.parameter.MEM_TINIT_CK + 150000 + + + testbench.partner.mem_model.parameter.MEM_TINIT_US + 500 + + + testbench.partner.mem_model.parameter.MEM_TMRD_CK + 4 + + + testbench.partner.mem_model.parameter.MEM_TRAS + 11 + + + testbench.partner.mem_model.parameter.MEM_TRAS_NS + 35.0 + + + testbench.partner.mem_model.parameter.MEM_TRC + 15 + + + testbench.partner.mem_model.parameter.MEM_TRCD + 5 + + + testbench.partner.mem_model.parameter.MEM_TRCD_NS + 13.75 + + + testbench.partner.mem_model.parameter.MEM_TREFI + 2341 + + + testbench.partner.mem_model.parameter.MEM_TREFI_US + 7.8 + + + testbench.partner.mem_model.parameter.MEM_TRFC + 34 + + + testbench.partner.mem_model.parameter.MEM_TRFC_NS + 110.0 + + + testbench.partner.mem_model.parameter.MEM_TRP + 5 + + + testbench.partner.mem_model.parameter.MEM_TRP_NS + 13.75 + + + testbench.partner.mem_model.parameter.MEM_TRRD + 2 + + + testbench.partner.mem_model.parameter.MEM_TRRD_NS + 6.0 + + + testbench.partner.mem_model.parameter.MEM_TRTP + 3 + + + testbench.partner.mem_model.parameter.MEM_TRTP_NS + 7.5 + + + testbench.partner.mem_model.parameter.MEM_TWR + 5 + + + testbench.partner.mem_model.parameter.MEM_TWR_NS + 15.0 + + + testbench.partner.mem_model.parameter.MEM_TWTR + 6 + + + testbench.partner.mem_model.parameter.MEM_TYPE + DDR3 + + + testbench.partner.mem_model.parameter.MEM_USER_LEVELING_MODE + Leveling + + + testbench.partner.mem_model.parameter.MEM_VENDOR + JEDEC + + + testbench.partner.mem_model.parameter.MEM_VERBOSE + true + + + testbench.partner.mem_model.parameter.MEM_WTCL + 5 + + + testbench.partner.mem_model.parameter.MEM_WTCL_INT + 5 + + + testbench.partner.mem_model.parameter.MR0_BL + 1 + + + testbench.partner.mem_model.parameter.MR0_BT + 0 + + + testbench.partner.mem_model.parameter.MR0_CAS_LATENCY + 1 + + + testbench.partner.mem_model.parameter.MR0_DLL + 1 + + + testbench.partner.mem_model.parameter.MR0_PD + 0 + + + testbench.partner.mem_model.parameter.MR0_WR + 1 + + + testbench.partner.mem_model.parameter.MR1_AL + 0 + + + testbench.partner.mem_model.parameter.MR1_DLL + 0 + + + testbench.partner.mem_model.parameter.MR1_DQS + 0 + + + testbench.partner.mem_model.parameter.MR1_ODS + 0 + + + testbench.partner.mem_model.parameter.MR1_QOFF + 0 + + + testbench.partner.mem_model.parameter.MR1_RDQS + 0 + + + testbench.partner.mem_model.parameter.MR1_RTT + 0 + + + testbench.partner.mem_model.parameter.MR1_TDQS + 0 + + + testbench.partner.mem_model.parameter.MR1_WL + 0 + + + testbench.partner.mem_model.parameter.MR2_ASR + 0 + + + testbench.partner.mem_model.parameter.MR2_CWL + 0 + + + testbench.partner.mem_model.parameter.MR2_RTT_WR + 0 + + + testbench.partner.mem_model.parameter.MR2_SRF + 0 + + + testbench.partner.mem_model.parameter.MR2_SRT + 0 + + + testbench.partner.mem_model.parameter.MR3_MPR + 0 + + + testbench.partner.mem_model.parameter.MR3_MPR_AA + 0 + + + testbench.partner.mem_model.parameter.MR3_MPR_RF + 0 + + + testbench.partner.mem_model.parameter.MRS_MIRROR_PING_PONG_ATSO + false + + + testbench.partner.mem_model.parameter.NEXTGEN + true + + + testbench.partner.mem_model.parameter.PARSE_FRIENDLY_DEVICE_FAMILY + MAX10 + + + testbench.partner.mem_model.parameter.PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID + true + + + testbench.partner.mem_model.parameter.PARSE_FRIENDLY_DEVICE_FAMILY_PARAM + + + + testbench.partner.mem_model.parameter.PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID + false + + + testbench.partner.mem_model.parameter.PINGPONGPHY_EN + false + + + testbench.partner.mem_model.parameter.PRE_V_SERIES_FAMILY + true + + + testbench.partner.mem_model.parameter.RATE + Half + + + testbench.partner.mem_model.parameter.RDIMM + false + + + testbench.partner.mem_model.parameter.RDIMM_CONFIG + 0000000000000000 + + + testbench.partner.mem_model.parameter.RDIMM_INT + 0 + + + testbench.partner.mem_model.parameter.REFRESH_BURST_VALIDATION + false + + + testbench.partner.mem_model.parameter.SCC_DATA_WIDTH + 1 + + + testbench.partner.mem_model.parameter.SPEED_GRADE + 6 + + + testbench.partner.mem_model.parameter.SYS_INFO_DEVICE_FAMILY + MAX 10 + + + testbench.partner.mem_model.parameter.TIMING_TDH + 45 + + + testbench.partner.mem_model.parameter.TIMING_TDQSCK + 225 + + + testbench.partner.mem_model.parameter.TIMING_TDQSCKDL + 1200 + + + testbench.partner.mem_model.parameter.TIMING_TDQSCKDM + 900 + + + testbench.partner.mem_model.parameter.TIMING_TDQSCKDS + 450 + + + testbench.partner.mem_model.parameter.TIMING_TDQSQ + 100 + + + testbench.partner.mem_model.parameter.TIMING_TDQSS + 0.27 + + + testbench.partner.mem_model.parameter.TIMING_TDS + 10 + + + testbench.partner.mem_model.parameter.TIMING_TDSH + 0.18 + + + testbench.partner.mem_model.parameter.TIMING_TDSS + 0.18 + + + testbench.partner.mem_model.parameter.TIMING_TIH + 120 + + + testbench.partner.mem_model.parameter.TIMING_TIS + 170 + + + testbench.partner.mem_model.parameter.TIMING_TQH + 0.38 + + + testbench.partner.mem_model.parameter.TIMING_TQSH + 0.4 + + + testbench.partner.mem_model.parameter.TRK_PARALLEL_SCC_LOAD + false + + + testbench.partner.mem_model.parameter.USE_DQS_TRACKING + false + + + testbench.partner.mem_model.parameter.USE_HPS_DQS_TRACKING + false + + + testbench.partner.mem_model.parameter.USE_MEM_CLK_FREQ + false + + + testbench.partner.mem_model.parameter.USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY + false + + + testbench.partner.mem_model.parameter.USE_SHADOW_REGS + false + + + java.lang.String + 0001000010001 + true + true + false + true + + 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true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + [Ljava.lang.String; + 0,None,None,None,None,None + true + true + false + true + + + [Ljava.lang.String; + 0,None,None,None,None,None + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + BL_8 + true + true + false + true + + + java.lang.String + DWIDTH_32 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + STARVE_LIMIT_32 + true + true + false + true + + + java.lang.String + DDR3 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + NO_CLR_INTR + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + CHIP_BANK_ROW_COL + true + true + false + true + + + java.lang.String + CTL_ECC_DISABLED + true + true + false + true + + + java.lang.String + CTL_ECC_RMW_DISABLED + true + true + false + true + + + java.lang.String + REGDIMM_DISABLED + true + true + false + true + + + java.lang.String + CTL_USR_REFRESH_DISABLED + true + true + false + true + + + java.lang.String + DATA_WIDTH_64_BIT + true + true + false + true + + + java.lang.String + BONDING_LATENCY_0 + true + true + false + true + + + java.lang.String + DFX_BYPASS_DISABLED + true + true + false + true + + + java.lang.String + MERGING_ENABLED + true + true + false + true + + + java.lang.String + ECC_DQ_WIDTH_0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + GEN_DBE_DISABLED + true + true + false + true + + + java.lang.String + GEN_SBE_DISABLED + true + true + false + true + + + java.lang.String + FIFO_SET_2 + true + true + false + true + + + java.lang.String + ADDR_WIDTH_2 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + AL_0 + true + true + false + true + + + java.lang.String + ADDR_WIDTH_3 + true + true + false + true + + + java.lang.String + MEM_IF_BURSTLENGTH_8 + true + true + false + true + + + java.lang.String + ADDR_WIDTH_12 + true + true + false + true + + + java.lang.String + MEM_IF_CS_PER_RANK_1 + true + true + false + true + + + java.lang.String + MEM_IF_CS_WIDTH_1 + true + true + false + true + + + java.lang.String + MEM_IF_DQ_PER_CHIP_8 + true + true + false + true + + + java.lang.String + DQS_WIDTH_4 + true + true + false + true + + + java.lang.String + MEM_IF_DWIDTH_32 + true + true + false + true + + + java.lang.String + DDR3_SDRAM + true + true + false + true + + + java.lang.String + ADDR_WIDTH_16 + true + true + false + true + + + java.lang.String + DDR3_1066_6_6_6 + true + true + false + true + + + java.lang.String + TCCD_4 + true + true + false + true + + + java.lang.String + TCL_6 + true + true + false + true + + + java.lang.String + TCWL_5 + true + true + false + true + + + java.lang.String + TFAW_16 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + TRAS_16 + true + true + false + true + + + java.lang.String + TRC_22 + true + true + false + true + + + java.lang.String + TRCD_6 + true + true + false + true + + + java.lang.String + TRP_6 + true + true + false + true + + + java.lang.String + TRRD_4 + true + true + false + true + + + java.lang.String + TRTP_4 + true + true + false + true + + + java.lang.String + TWR_6 + true + true + false + true + + + java.lang.String + TWTR_4 + true + true + false + true + + + java.lang.String + MP_BL_8 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + SLOW_EXIT + true + true + false + true + + + java.lang.String + PORT_64_BIT + true + true + false + true + + + java.lang.String + PORT_64_BIT + true + true + false + true + + + java.lang.String + PORT_64_BIT + true + true + false + true + + + java.lang.String + PORT_64_BIT + true + true + false + true + + + java.lang.String + PORT_64_BIT + true + true + false + true + + + java.lang.String + PORT_64_BIT + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_0 + true + true + false + true + + + java.lang.String + PRIORITY_0 + true + true + false + true + + + java.lang.String + PRIORITY_0 + true + true + false + true + + + java.lang.String + PRIORITY_0 + true + true + false + true + + + java.lang.String + PRIORITY_0 + true + true + false + true + + + java.lang.String + PRIORITY_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + ODT_DISABLED + true + true + false + true + + + java.lang.String + DATA_REORDERING + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CONCATENATE_RDY + true + true + false + true + + + java.lang.String + CONCATENATE_RDY + true + true + false + true + + + java.lang.String + CONCATENATE_RDY + true + true + false + true + + + java.lang.String + CONCATENATE_RDY + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + ASYNCHRONOUS + true + true + false + true + + + java.lang.String + ASYNCHRONOUS + true + true + false + true + + + java.lang.String + ASYNCHRONOUS + true + true + false + true + + + java.lang.String + ASYNCHRONOUS + true + true + false + true + + + java.lang.String + ASYNCHRONOUS + true + true + false + true + + + java.lang.String + ASYNCHRONOUS + true + true + false + true + + + java.lang.String + NORMAL_MODE + true + true + false + true + + + java.lang.String + THRESHOLD_32 + true + true + false + true + + + java.lang.String + THRESHOLD_32 + true + true + false + true + + + java.lang.String + THRESHOLD_32 + true + true + false + true + + + java.lang.String + THRESHOLD_32 + true + true + false + true + + + java.lang.String + THRESHOLD_32 + true + true + false + true + + + java.lang.String + THRESHOLD_32 + true + true + false + true + + + java.lang.String + THRESHOLD_16 + true + true + false + true + + + java.lang.String + THRESHOLD_16 + true + true + false + true + + + java.lang.String + THRESHOLD_16 + true + true + false + true + + + java.lang.String + THRESHOLD_16 + true + true + false + true + + + java.lang.String + THRESHOLD_16 + true + true + false + true + + + java.lang.String + THRESHOLD_16 + true + true + false + true + + + java.lang.String + EMPTY + true + true + false + true + + + java.lang.String + EMPTY + true + true + false + true + + + java.lang.String + EMPTY + true + true + false + true + + + java.lang.String + EMPTY + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + PRIORITY_0 + true + true + false + true + + + java.lang.String + PRIORITY_0 + true + true + false + true + + + java.lang.String + PRIORITY_0 + true + true + false + true + + + java.lang.String + PRIORITY_0 + true + true + false + true + + + java.lang.String + PRIORITY_0 + true + true + false + true + + + java.lang.String + PRIORITY_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + NOT_FULL + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + ODT_DISABLED + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 3120 + true + true + false + true + + + int + 34 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.math.BigInteger + 0 + true + true + false + true + + + java.math.BigInteger + 0 + true + true + false + true + + + java.math.BigInteger + 0 + true + true + false + true + + + java.math.BigInteger + 0 + true + true + false + true + + + java.math.BigInteger + 0 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 10 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + PORT_64_BIT + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + PORT_64_BIT + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + PORT_64_BIT + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + PORT_64_BIT + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + PORT_64_BIT + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + FALSE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLE + true + true + false + true + + + java.lang.String + FIFO_0 + true + true + false + true + + + java.lang.String + DISABLED + true + true + false + true + + + java.lang.String + PORT_64_BIT + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + java.lang.String + WEIGHT_0 + true + true + false + true + + + java.lang.String + PRIORITY_0 + true + true + false + true + + + java.lang.String + DWIDTH_0 + true + true + false + true + + + java.lang.String + USE_NO + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + java.lang.String + CMD_PORT_0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + 4 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 4 + false + true + true + true + + + java.lang.String + 5 + false + true + false + true + + + boolean + true + false + true + true + true + + + int + 10 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + INTERNAL_JTAG + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 4 + false + false + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 7 + true + true + false + true + + + int + 6 + false + true + false + true + + + int + 16 + false + true + false + true + + + int + 32 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + false + false + true + + + int + 8 + false + true + false + true + + + int + 1 + false + true + false + true + + + java.lang.String + INTER_BANK + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.Integer; + 32,32,32,32,32,32 + false + true + false + true + + + [Ljava.lang.Integer; + 1,1,1,1,1,1 + false + true + false + true + + + [Ljava.lang.Integer; + 0,0,0,0,0,0 + false + true + false + true + + + [Ljava.lang.String; + Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 191 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 16 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + HALF + true + true + false + true + + + int + 8 + true + true + false + true + + + int + 1 + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + double + 100.0 + false + true + true + true + + + java.lang.String + 100.0 MHz + true + true + false + true + + + double + 10.0 + true + true + false + true + + + double + 10000.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 300.0 + true + true + true + true + + + java.lang.String + 300.0 MHz + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + double + 150.0 + true + true + true + true + + + java.lang.String + 150.0 MHz + true + true + false + true + + + java.lang.String + 6668 ps + true + true + false + true + + + int + 0 + true + true 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java.lang.String + 300.0 MHz + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 300.0 MHz + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + double + 270.0 + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + double + 270.0 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + double + 0.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 10.0 + true + true + false + true + + + double + 500.0 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 150.0 + true + true + false + true + + + java.lang.String + 6668 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 2 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 300.0 + true + true + false + true + + + java.lang.String + 3334 ps + true + true + false + true + + + int + 2500 + true + true + false + true + + + java.lang.String + 2500 ps + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + 6 + true + true + false + true + + + boolean + false + true + true + false + true + + + double + 300.0 + true + true + false + true + + + double + 100.0 + true + true + false + true + + + java.lang.String + Half + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + MAX10 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + NIOS + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 10 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + None + false + true + false + true + + + int + 1 + false + false + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + 0_0000_0000_0000 + false + true + false + true + + + java.lang.String + 0_0000_0000_1000 + false + true + false + true + + + int + 35100 + false + true + false + true + + + int + 15000 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 350 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + MISSING_MODEL + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 9000 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 7 + true + true + false + true + + + int + 14 + true + true + false + true + + + boolean + false + true + true + false + true + + + double + 3.333 + true + true + false + true + + + double + 3333.0 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 12 + true + true + false + true + + + int + 416 + true + true + false + true + + + int + 50 + true + true + false + true + + + int + 50 + true + true + false + true + + + int + 7 + true + true + false + true + + + int + 15 + true + true + false + true + + + int + 15 + true + true + false + true + + + int + 15 + true + true + false + true + + + int + 7 + true + true + false + true + + + java.lang.String + SSTL-15 + true + true + true + true + + + boolean + true + true + true + false + true + + + java.lang.String + NIOS + false + true + false + true + + + java.lang.String + ../ + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.0 + false + false + false + true + + + double + 0.0 + false + false + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + 1.5V DDR3 + false + true + true + true + + + java.lang.String + Top_Bottom + false + false + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + INVERTED_DQS_BUS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DIFFERENTIAL + false + true + false + true + + + int + 32 + false + true + false + true + + + java.lang.String + Skip + false + true + false + true + + + int + 32 + false + true + false + true + + + int + 13 + true + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + INTERNAL_JTAG + false + true + false + true + + + java.lang.String + 1 + false + true + false + true + + + java.lang.String + AUTO + false + true + true + true + + + double + 2.0 + false + true + false + true + + + double + 1.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 1.0 + false + true + false + true + + + double + 2.0 + true + true + true + true + + + double + 1.0 + true + true + true + true + + + double + 2.0 + true + true + true + true + + + double + 1.0 + true + true + true + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.32 + true + true + true + true + + + double + 0.22 + true + true + true + true + + + double + 0.16 + true + true + true + true + + + double + 0.145 + true + true + true + true + + + java.lang.String + AUTO + false + true + true + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.2443 + false + true + true + true + + + double + 0.21929 + false + true + true + true + + + double + 0.02286 + false + true + true + true + + + double + 0.02286 + true + true + false + true + + + double + 0.04429 + false + true + true + true + + + double + 0.04429 + true + true + false + true + + + double + 0.05 + false + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.01806 + false + true + true + true + + + double + 0.04246 + false + true + true + true + + + double + -0.01152 + false + true + true + true + + + double + 0.07801 + false + true + true + true + + + double + -0.04709 + false + true + true + true + + + boolean + false + false + false + false + true + + + java.lang.String + EXPORT + false + false + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + meminit + false + true + false + true + + + int + 6 + true + true + false + true + + + int + 6 + true + true + false + true + + + java.lang.String + HIGH + true + true + false + true + + + int + 8 + true + true + false + true + + + java.lang.String + None + false + true + false + true + + + int + 1 + false + false + false + true + + + int + 14 + true + true + false + true + + + java.lang.String + None + false + true + false + true + + + int + 1 + false + false + false + true + + + java.lang.String + 10M50DAF484C6GES + false + true + false + true + DEVICE + + + java.lang.String + 6 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + pll_ref_clk + Input + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + global_reset_n + Input + 1 + reset_n + + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + soft_reset_n + Input + 1 + reset_n + + + + + + java.lang.String + + false + true + true + true + + + long + 150000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + afi_clk + Output + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + long + 300000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + afi_half_clk + Output + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + soft_reset + false + true + true + true + + + [Ljava.lang.String; + soft_reset,global_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + afi_reset_n + Output + 1 + reset_n + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + soft_reset + false + true + true + true + + + [Ljava.lang.String; + soft_reset,global_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + afi_reset_export_n + Output + 1 + reset_n + + + + + + qsys.ui.export_name + memory + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + mem_a + Output + 14 + mem_a + + + mem_ba + Output + 3 + mem_ba + + + mem_ck + Bidir + 1 + mem_ck + + + mem_ck_n + Bidir + 1 + mem_ck_n + + + mem_cke + Output + 1 + mem_cke + + + mem_cs_n + Output + 1 + mem_cs_n + + + mem_dm + Output + 1 + mem_dm + + + mem_ras_n + Output + 1 + mem_ras_n + + + mem_cas_n + Output + 1 + mem_cas_n + + + mem_we_n + Output + 1 + mem_we_n + + + mem_reset_n + Output + 1 + mem_reset_n + + + mem_dq + Bidir + 8 + mem_dq + + + mem_dqs + Bidir + 1 + mem_dqs + + + mem_dqs_n + Bidir + 1 + mem_dqs_n + + + mem_odt + Output + 1 + mem_odt + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 134217728 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + afi_clk + false + true + true + true + + + java.lang.String + soft_reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + 0 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + avl_ready + Output + 1 + waitrequest_n + + + avl_burstbegin + Input + 1 + beginbursttransfer + + + avl_addr + Input + 25 + address + + + avl_rdata_valid + Output + 1 + readdatavalid + + + avl_rdata + Output + 32 + readdata + + + avl_wdata + Input + 32 + writedata + + + avl_be + Input + 4 + byteenable + + + avl_read_req + Input + 1 + read + + + avl_write_req + Input + 1 + write + + + avl_size + Input + 3 + burstcount + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + local_init_done + Output + 1 + local_init_done + + + local_cal_success + Output + 1 + local_cal_success + + + local_cal_fail + Output + 1 + local_cal_fail + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + pll_mem_clk + Output + 1 + pll_mem_clk + + + pll_write_clk + Output + 1 + pll_write_clk + + + pll_locked + Output + 1 + pll_locked + + + pll_capture0_clk + Output + 1 + pll_capture0_clk + + + pll_capture1_clk + Output + 1 + pll_capture1_clk + + + + + + + int + 1 + false + true + true + true + + + java.lang.String + none + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.Long + -1 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + in_reset_n + Input + 1 + reset_n + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + in_reset + false + true + true + true + + + [Ljava.lang.String; + in_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + out_reset_n + Output + 1 + reset_n + + + + + + + embeddedsw.CMacro.BAUD + 115200 + + + embeddedsw.CMacro.DATA_BITS + 8 + + + embeddedsw.CMacro.FIXED_BAUD + 1 + + + embeddedsw.CMacro.FREQ + 50000000 + + + embeddedsw.CMacro.PARITY + 'N' + + + embeddedsw.CMacro.SIM_CHAR_STREAM + "" + + + embeddedsw.CMacro.SIM_TRUE_BAUD + 0 + + + embeddedsw.CMacro.STOP_BITS + 1 + + + embeddedsw.CMacro.SYNC_REG_DEPTH + 2 + + + embeddedsw.CMacro.USE_CTS_RTS + 0 + + + embeddedsw.CMacro.USE_EOP_REGISTER + 0 + + + embeddedsw.dts.compatible + altr,uart-1.0 + + + embeddedsw.dts.group + serial + + + embeddedsw.dts.name + uart + + + embeddedsw.dts.params.clock-frequency + 50000000 + + + embeddedsw.dts.params.current-speed + 115200 + + + embeddedsw.dts.vendor + altr + + + int + 115200 + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + true + false + true + true + true + + + java.lang.String + NONE + false + true + true + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 2 + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + long + 50000000 + false + true + false + true + CLOCK_RATE + clk + + + double + 0.01 + true + true + true + true + + + java.lang.String + N + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 8 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 3 + address + + + begintransfer + Input + 1 + begintransfer + + + chipselect + Input + 1 + chipselect + + + read_n + Input + 1 + read_n + + + write_n + Input + 1 + write_n + + + writedata + Input + 16 + writedata + + + readdata + Output + 16 + readdata + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + rxd + Input + 1 + export + + + txd + Output + 1 + export + + + + + + com.altera.entityinterfaces.IConnectionPoint + debug_uart.s1 + false + true + true + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + java.lang.Integer + + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + true + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + irq + Output + 1 + irq + + + + + + + embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR + 0 + + + embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE + 0 + + + embeddedsw.CMacro.CONTENTS_INFO + "" + + + embeddedsw.CMacro.DUAL_PORT + 0 + + + embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE + AUTO + + + embeddedsw.CMacro.INIT_CONTENTS_FILE + q_sys_descriptor_memory + + + embeddedsw.CMacro.INIT_MEM_CONTENT + 0 + + + embeddedsw.CMacro.INSTANCE_ID + NONE + + + embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED + 0 + + + embeddedsw.CMacro.RAM_BLOCK_TYPE + AUTO + + + embeddedsw.CMacro.READ_DURING_WRITE_MODE + DONT_CARE + + + embeddedsw.CMacro.SINGLE_CLOCK_OP + 0 + + + embeddedsw.CMacro.SIZE_MULTIPLE + 1 + + + embeddedsw.CMacro.SIZE_VALUE + 8192 + + + embeddedsw.CMacro.WRITABLE + 1 + + + embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR + SIM_DIR + + + embeddedsw.memoryInfo.GENERATE_DAT_SYM + 1 + + + embeddedsw.memoryInfo.GENERATE_HEX + 1 + + + embeddedsw.memoryInfo.HAS_BYTE_LANE + 0 + + + embeddedsw.memoryInfo.HEX_INSTALL_DIR + QPF_DIR + + + embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH + 32 + + + embeddedsw.memoryInfo.MEM_INIT_FILENAME + q_sys_descriptor_memory + + + postgeneration.simulation.init_file.param_name + INIT_FILE + + + postgeneration.simulation.init_file.type + MEM_INIT + + + boolean + false + false + true + true + true + + + java.lang.String + AUTO + false + true + true + true + + + int + 32 + false + true + true + true + + + int + 32 + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + true + true + + + java.lang.String + /data/acastill/simple_socket_10M50/software/niosII_simple_socket_server/mem_init/q_sys_descriptor_memory.hex + false + false + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + NONE + false + false + true + true + + + long + 8192 + false + true + true + true + + + java.lang.String + DONT_CARE + false + false + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + false + true + true + + + boolean + false + true + true + false + true + + + int + 1 + false + true + true + true + + + int + 1 + false + false + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + false + false + true + + + boolean + false + false + false + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + java.lang.String + q_sys_descriptor_memory + false + true + false + true + UNIQUE_ID + + + java.lang.String + MAX10FPGA + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + false + true + false + true + DEVICE_FEATURES + + + int + 11 + true + true + false + true + + + int + 11 + true + true + false + true + + + int + 32 + true + true + false + true + + + int + 32 + true + true + false + true + + + java.lang.String + Automatic + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + q_sys_descriptor_memory.hex + true + true + false + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 8192 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk1 + false + true + true + true + + + java.lang.String + reset1 + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 8192 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 11 + address + + + clken + Input + 1 + clken + + + chipselect + Input + 1 + chipselect + + + write + Input + 1 + write + + + readdata + Output + 32 + readdata + + + writedata + Input + 32 + writedata + + + byteenable + Input + 4 + byteenable + + + + + + java.lang.String + clk1 + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset + Input + 1 + reset + + + reset_req + Input + 1 + reset_req + + + + + + + java.lang.String + altpll_avalon_elaboration + false + true + false + true + + + java.lang.String + altpll_avalon_post_edit + false + true + false + true + + + java.lang.String + MAX 10 + false + true + true + true + + + java.lang.String + 5 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + 20000 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + NO_COMPENSATION + false + true + true + true + + + java.lang.String + AUTO + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + CLK0 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + AUTO + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + 5 + false + true + true + true + + + java.lang.String + 1 + false + true + true + true + + + java.lang.String + 1 + false + true + true + true + + + java.lang.String + 5 + false + true + true + true + + + java.lang.String + 1 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + 2 + false + true + true + true + + + java.lang.String + 2 + false + true + true + true + + + java.lang.String + 20 + false + true + true + true + + + java.lang.String + 2 + false + true + true + true + + + java.lang.String + 2 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + 0 + false + true + true + true + + + java.lang.String + 0 + false + true + true + true + + + java.lang.String + 0 + false + true + true + true + + + java.lang.String + -3000 + false + true + true + true + + + java.lang.String + -10000 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + 50 + false + true + true + true + + + java.lang.String + 50 + false + true + true + true + + + java.lang.String + 50 + false + true + true + true + + + java.lang.String + 50 + false + true + true + true + + + java.lang.String + 50 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_USED + false + true + true + true + + + java.lang.String + PORT_USED + false + true + true + true + + + java.lang.String + PORT_USED + false + true + true + true + + + java.lang.String + PORT_USED + false + true + true + true + + + java.lang.String + PORT_USED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_USED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + PORT_USED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + NO + false + true + true + true + + + java.lang.String + CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_USED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 2 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT -3000 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 2 CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 1 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NO_COMPENSATION CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT -10000 CT#INCLK0_INPUT_FREQUENCY 20000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 2 CT#CLK1_DIVIDE_BY 2 CT#CLK3_MULTIPLY_BY 5 CT#PORT_LOCKED PORT_USED + false + true + false + true + + + java.lang.String + PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 0 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 0 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 0 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 100.00000000 PT#OUTPUT_FREQ3 100.00000000 PT#OUTPUT_FREQ2 2.50000000 PT#OUTPUT_FREQ1 25.00000000 PT#OUTPUT_FREQ0 125.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 -90.00000000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 -135.00000000 PT#DIV_FACTOR4 2 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 2 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR1 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 1 PT#USE_CLKENA4 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 25.000000 PT#EFF_OUTPUT_FREQ_VALUE3 125.000000 PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 125.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK4 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 5 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1418882816093282.mif PT#ACTIVECLK_CHECK 0 + false + true + false + true + + + java.lang.String + UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used + false + true + false + true + + + java.lang.String + IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#CLK4_DIVIDE_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1 + false + true + false + true + + + java.lang.String + MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1 + false + true + false + true + + + java.lang.String + IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} + false + true + false + true + + + java.lang.String + 0 + false + true + false + true + + + java.lang.String + MAX10FPGA + false + true + false + true + DEVICE_FAMILY + + + java.lang.Long + 50000000 + false + true + false + true + CLOCK_RATE + inclk_interface + + + java.lang.String + MAX 10 + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + inclk_interface + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset + Input + 1 + reset + + + + + + embeddedsw.configuration.isMemoryDevice + false + + + embeddedsw.configuration.isNonVolatileStorage + false + + + embeddedsw.configuration.isPrintableDevice + false + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 16 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + inclk_interface + false + true + true + true + + + java.lang.String + inclk_interface_reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + read + Input + 1 + read + + + write + Input + 1 + write + + + address + Input + 2 + address + + + readdata + Output + 32 + readdata + + + writedata + Input + 32 + writedata + + + + + + java.lang.String + + false + true + true + true + + + long + 125000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + c0 + Output + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + long + 25000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + c1 + Output + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + long + 2500000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + c2 + Output + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + long + 125000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + c3 + Output + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + long + 25000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + c4 + Output + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + locked + Output + 1 + export + + + + + + + embeddedsw.CMacro.ENABLE_MACLITE + 0 + + + embeddedsw.CMacro.FIFO_WIDTH + 32 + + + embeddedsw.CMacro.IS_MULTICHANNEL_MAC + 0 + + + embeddedsw.CMacro.MACLITE_GIGE + 0 + + + embeddedsw.CMacro.MDIO_SHARED + 0 + + + embeddedsw.CMacro.NUMBER_OF_CHANNEL + 1 + + + embeddedsw.CMacro.NUMBER_OF_MAC_MDIO_SHARED + 1 + + + embeddedsw.CMacro.PCS + 0 + + + embeddedsw.CMacro.PCS_ID + 0 + + + embeddedsw.CMacro.PCS_SGMII + 1 + + + embeddedsw.CMacro.RECEIVE_FIFO_DEPTH + 2048 + + + embeddedsw.CMacro.REGISTER_SHARED + 0 + + + embeddedsw.CMacro.RGMII + 1 + + + embeddedsw.CMacro.TRANSMIT_FIFO_DEPTH + 2048 + + + embeddedsw.CMacro.USE_MDIO + 1 + + + embeddedsw.dts.compatible + altr,tse-1.0 + + + embeddedsw.dts.group + ethernet + + + embeddedsw.dts.name + tse + + + embeddedsw.dts.params.ALTR,rx-fifo-depth + 2048 + + + embeddedsw.dts.params.ALTR,tx-fifo-depth + 2048 + + + embeddedsw.dts.vendor + altr + + + java.lang.String + MAX10FPGA + false + true + false + true + DEVICE_FAMILY + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 4865 + true + true + false + true + + + int + 4865 + true + true + false + true + + + int + 2048 + true + true + false + true + + + int + 2048 + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 3 + true + true + false + true + + + java.lang.String + MAX10 + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + MAC_ONLY + false + true + true + true + + + java.lang.String + RGMII + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 1 + false + false + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + NONE + false + false + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + true + true + + + int + 40 + false + true + true + true + + + int + 32 + false + true + true + true + + + int + 11 + false + true + true + true + + + int + 11 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + true + false + false + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + false + true + true + + + int + 0 + false + false + true + true + + + java.lang.String + CMU + false + false + true + true + + + java.lang.String + 1250 Mbps + false + false + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + x1 + false + false + true + true + + + boolean + true + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 4 + true + false + false + true + + + boolean + false + false + false + true + true + + + boolean + false + false + false + true + true + + + int + 4 + false + false + true + true + + + java.lang.String + 10M50DAF484C6GES + false + true + false + true + DEVICE + + + java.lang.String + 6 + false + true + false + true + DEVICE_SPEEDGRADE + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + control_port_clock_connection + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset + Input + 1 + reset + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 1024 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + control_port_clock_connection + false + true + true + true + + + java.lang.String + reset_connection + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + 0 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + reg_addr + Input + 8 + address + + + reg_data_out + Output + 32 + readdata + + + reg_rd + Input + 1 + read + + + reg_data_in + Input + 32 + writedata + + + reg_wr + Input + 1 + write + + + reg_busy + Output + 1 + waitrequest + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + tx_clk + Input + 1 + clk + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + rx_clk + Input + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + set_10 + Input + 1 + set_10 + + + set_1000 + Input + 1 + set_1000 + + + eth_mode + Output + 1 + eth_mode + + + ena_10 + Output + 1 + ena_10 + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + rgmii_in + Input + 4 + rgmii_in + + + rgmii_out + Output + 4 + rgmii_out + + + rx_control + Input + 1 + rx_control + + + tx_control + Output + 1 + tx_control + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + ff_rx_clk + Input + 1 + clk + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + ff_tx_clk + Input + 1 + clk + + + + + + java.lang.String + receive_clock_connection + false + true + false + true + + + java.lang.String + reset_connection + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 2 + false + true + true + true + + + int + 4 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + true + + ff_rx_data + Output + 32 + data + + + ff_rx_eop + Output + 1 + endofpacket + + + rx_err + Output + 6 + error + + + ff_rx_mod + Output + 2 + empty + + + ff_rx_rdy + Input + 1 + ready + + + ff_rx_sop + Output + 1 + startofpacket + + + ff_rx_dval + Output + 1 + valid + + + + + + java.lang.String + transmit_clock_connection + false + true + false + true + + + java.lang.String + reset_connection + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 4 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + false + + ff_tx_data + Input + 32 + data + + + ff_tx_eop + Input + 1 + endofpacket + + + ff_tx_err + Input + 1 + error + + + ff_tx_mod + Input + 2 + empty + + + ff_tx_rdy + Output + 1 + ready + + + ff_tx_sop + Input + 1 + startofpacket + + + ff_tx_wren + Input + 1 + valid + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + mdc + Output + 1 + mdc + + + mdio_in + Input + 1 + mdio_in + + + mdio_out + Output + 1 + mdio_out + + + mdio_oen + Output + 1 + mdio_oen + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + magic_wakeup + Output + 1 + magic_wakeup + + + magic_sleep_n + Input + 1 + magic_sleep_n + + + ff_tx_crc_fwd + Input + 1 + ff_tx_crc_fwd + + + ff_tx_septy + Output + 1 + ff_tx_septy + + + tx_ff_uflow + Output + 1 + tx_ff_uflow + + + ff_tx_a_full + Output + 1 + ff_tx_a_full + + + ff_tx_a_empty + Output + 1 + ff_tx_a_empty + + + rx_err_stat + Output + 18 + rx_err_stat + + + rx_frm_type + Output + 4 + rx_frm_type + + + ff_rx_dsav + Output + 1 + ff_rx_dsav + + + ff_rx_a_full + Output + 1 + ff_rx_a_full + + + ff_rx_a_empty + Output + 1 + ff_rx_a_empty + + + + + + + embeddedsw.CMacro.FLASH_TYPE + Micron512 + + + embeddedsw.CMacro.IS_EPCS + 0 + + + embeddedsw.CMacro.NUMBER_OF_SECTORS + 1024 + + + embeddedsw.CMacro.PAGE_SIZE + 256 + + + embeddedsw.CMacro.SECTOR_SIZE + 65536 + + + embeddedsw.CMacro.SUBSECTOR_SIZE + 4096 + + + embeddedsw.dts.compatible + altr,quadspi-1.0 + + + embeddedsw.dts.group + quadspi + + + embeddedsw.dts.name + quadspi + + + embeddedsw.dts.vendor + altr + + + embeddedsw.memoryInfo.GENERATE_DAT_SYM + 0 + + + embeddedsw.memoryInfo.GENERATE_FLASH + 0 + + + embeddedsw.memoryInfo.GENERATE_HEX + 1 + + + embeddedsw.memoryInfo.HEX_INSTALL_DIR + QPF_DIR + + + embeddedsw.memoryInfo.IS_FLASH + 1 + + + embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH + 32 + + + embeddedsw.memoryInfo.USE_BYTE_ADDRESSING_FOR_HEX + 1 + + + java.lang.String + MAX10FPGA + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + q_sys_ext_flash + false + true + false + true + UNIQUE_ID + + + long + 0 + false + true + false + true + CLOCK_RATE + clock_sink + + + int + 1 + true + true + false + true + + + int + 24 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 32 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + java.lang.String + Micron512 + false + true + true + true + + + java.lang.String + QUAD + false + true + true + true + + + int + 1 + false + false + true + true + + + java.lang.String + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + false + true + false + true + DEVICE_FEATURES + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + false + true + true + false + true + + + java.lang.Long + 0 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clock_sink + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 32 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clock_sink + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + avl_csr_read + Input + 1 + read + + + avl_csr_waitrequest + Output + 1 + waitrequest + + + avl_csr_write + Input + 1 + write + + + avl_csr_addr + Input + 3 + address + + + avl_csr_wrdata + Input + 32 + writedata + + + avl_csr_rddata + Output + 32 + readdata + + + avl_csr_rddata_valid + Output + 1 + readdatavalid + + + + + + embeddedsw.configuration.isFlash + 1 + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.isNonVolatileStorage + 1 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 67108864 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clock_sink + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + true + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + avl_mem_write + Input + 1 + write + + + avl_mem_burstcount + Input + 7 + burstcount + + + avl_mem_waitrequest + Output + 1 + waitrequest + + + avl_mem_read + Input + 1 + read + + + avl_mem_addr + Input + 24 + address + + + avl_mem_wrdata + Input + 32 + writedata + + + avl_mem_rddata + Output + 32 + readdata + + + avl_mem_rddata_valid + Output + 1 + readdatavalid + + + avl_mem_byteenable + Input + 4 + byteenable + + + + + + com.altera.entityinterfaces.IConnectionPoint + ext_flash.avl_csr + false + true + true + true + + + java.lang.String + clock_sink + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + java.lang.Integer + + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + true + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + irq + Output + 1 + irq + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + flash_dataout + Bidir + 4 + conduit_dataout + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + flash_dclk_out + Output + 1 + conduit_dclk_out + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + flash_ncs + Output + 1 + conduit_ncs + + + + + + + long + 0 + false + true + true + true + CLOCK_RATE + in_clk + + + long + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + false + true + true + false + true + + + java.lang.Long + 0 + true + true + false + true + + clock + false + + in_clk + Input + 1 + clk + + + + + + java.lang.String + in_clk + false + true + true + true + + + long + 0 + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + out_clk + Output + 1 + clk + + + false + ext_flash + clock_sink + ext_flash.clock_sink + + + + + + + embeddedsw.CMacro.ALWAYS_RUN + 0 + + + embeddedsw.CMacro.COUNTER_SIZE + 32 + + + embeddedsw.CMacro.FIXED_PERIOD + 0 + + + embeddedsw.CMacro.FREQ + 50000000 + + + embeddedsw.CMacro.LOAD_VALUE + 4999 + + + embeddedsw.CMacro.MULT + 2e-8 + + + embeddedsw.CMacro.PERIOD + 5000 + + + embeddedsw.CMacro.PERIOD_UNITS + clocks + + + embeddedsw.CMacro.RESET_OUTPUT + 0 + + + embeddedsw.CMacro.SNAPSHOT + 0 + + + embeddedsw.CMacro.TICKS_PER_SEC + 10000 + + + embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT + 1 + + + embeddedsw.dts.vendor + altr + + + boolean + false + false + true + true + true + + + int + 32 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + 5000 + false + true + true + true + + + java.lang.String + CLOCKS + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + long + 50000000 + false + true + false + true + CLOCK_RATE + clk + + + int + 2 + false + true + false + true + + + java.lang.String + CUSTOM + true + true + false + true + + + java.lang.String + clocks + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + 4999 + true + true + false + true + + + double + 2.0E-8 + true + true + false + true + + + double + 10000.0 + true + true + false + true + + + int + 3 + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + embeddedsw.configuration.isTimerDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 8 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 3 + address + + + writedata + Input + 16 + writedata + + + readdata + Output + 16 + readdata + + + chipselect + Input + 1 + chipselect + + + write_n + Input + 1 + write_n + + + + + + com.altera.entityinterfaces.IConnectionPoint + frame_timer.s1 + false + true + true + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + java.lang.Integer + + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + true + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + irq + Output + 1 + irq + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + timeout_pulse + Output + 1 + export + + + + + + + embeddedsw.CMacro.BURST_ENABLE + 0 + + + embeddedsw.CMacro.BURST_WRAPPING_SUPPORT + 0 + + + embeddedsw.CMacro.CHANNEL_ENABLE + 0 + + + embeddedsw.CMacro.CHANNEL_ENABLE_DERIVED + 0 + + + embeddedsw.CMacro.CHANNEL_WIDTH + 8 + + + embeddedsw.CMacro.DATA_FIFO_DEPTH + 32 + + + embeddedsw.CMacro.DATA_WIDTH + 32 + + + embeddedsw.CMacro.DESCRIPTOR_FIFO_DEPTH + 8 + + + embeddedsw.CMacro.DMA_MODE + 2 + + + embeddedsw.CMacro.ENHANCED_FEATURES + 0 + + + embeddedsw.CMacro.ERROR_ENABLE + 1 + + + embeddedsw.CMacro.ERROR_ENABLE_DERIVED + 1 + + + embeddedsw.CMacro.ERROR_WIDTH + 6 + + + embeddedsw.CMacro.MAX_BURST_COUNT + 2 + + + embeddedsw.CMacro.MAX_BYTE + 2048 + + + embeddedsw.CMacro.MAX_STRIDE + 1 + + + embeddedsw.CMacro.PACKET_ENABLE + 1 + + + embeddedsw.CMacro.PACKET_ENABLE_DERIVED + 1 + + + embeddedsw.CMacro.PREFETCHER_ENABLE + 1 + + + embeddedsw.CMacro.PROGRAMMABLE_BURST_ENABLE + 0 + + + embeddedsw.CMacro.RESPONSE_PORT + 2 + + + embeddedsw.CMacro.STRIDE_ENABLE + 0 + + + embeddedsw.CMacro.STRIDE_ENABLE_DERIVED + 0 + + + embeddedsw.CMacro.TRANSFER_TYPE + Aligned Accesses + + + embeddedsw.dts.compatible + altr,msgdma-1.0 + + + embeddedsw.dts.group + msgdma + + + embeddedsw.dts.name + msgdma + + + embeddedsw.dts.vendor + altr + + + int + 2 + false + true + true + true + + + int + 32 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 32 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 32 + false + true + true + true + + + int + 8 + false + true + true + true + + + int + 2 + false + false + true + true + + + int + 2048 + false + true + true + true + + + java.lang.String + Aligned Accesses + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 2 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 0 + true + true + false + true + + + int + 1 + false + true + true + true + + + int + 1 + true + true + false + true + + + int + 1 + false + true + true + true + + + int + 1 + true + true + false + true + + + int + 6 + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + true + true + false + true + + + int + 8 + false + false + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 32 + false + true + true + true + + + int + 2 + false + false + true + true + + + java.lang.String + MAX10FPGA + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + 10M50DAF484C6GES + false + true + false + true + DEVICE + + + java.lang.String + 6 + false + true + false + true + DEVICE_SPEEDGRADE + + + com.altera.entityinterfaces.moduleext.AddressMap + + false + true + false + true + ADDRESS_MAP + mm_read + + + com.altera.entityinterfaces.moduleext.AddressWidthType + AddressWidth = -1 + false + true + false + true + ADDRESS_WIDTH + mm_read + + + com.altera.entityinterfaces.moduleext.AddressMap + ]]> + false + true + false + true + ADDRESS_MAP + mm_write + + + com.altera.entityinterfaces.moduleext.AddressWidthType + AddressWidth = 28 + false + true + false + true + ADDRESS_WIDTH + mm_write + + + com.altera.entityinterfaces.moduleext.AddressMap + ]]> + false + true + false + true + ADDRESS_MAP + descriptor_read_master + + + com.altera.entityinterfaces.moduleext.AddressWidthType + AddressWidth = 29 + false + true + false + true + ADDRESS_WIDTH + descriptor_read_master + + + com.altera.entityinterfaces.moduleext.AddressMap + ]]> + false + true + false + true + ADDRESS_MAP + descriptor_write_master + + + com.altera.entityinterfaces.moduleext.AddressWidthType + AddressWidth = 29 + false + true + false + true + ADDRESS_WIDTH + descriptor_write_master + + + java.lang.String + MAX 10 + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clock + false + true + true + true + + + java.lang.String + reset_n + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + mm_write_address + Output + 28 + address + + + mm_write_write + Output + 1 + write + + + mm_write_byteenable + Output + 4 + byteenable + + + mm_write_writedata + Output + 32 + writedata + + + mm_write_waitrequest + Input + 1 + waitrequest + + + false + ddr3_ram + avl + ddr3_ram.avl + 134217728 + 134217728 + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clock + false + true + true + true + + + java.lang.String + reset_n + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + descriptor_read_master_address + Output + 29 + address + + + descriptor_read_master_read + Output + 1 + read + + + descriptor_read_master_readdata + Input + 32 + readdata + + + descriptor_read_master_waitrequest + Input + 1 + waitrequest + + + descriptor_read_master_readdatavalid + Input + 1 + readdatavalid + + + false + descriptor_memory + s1 + descriptor_memory.s1 + 406847488 + 8192 + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clock + false + true + true + true + + + java.lang.String + reset_n + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 3 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + descriptor_write_master_address + Output + 29 + address + + + descriptor_write_master_write + Output + 1 + write + + + descriptor_write_master_byteenable + Output + 4 + byteenable + + + descriptor_write_master_writedata + Output + 32 + writedata + + + descriptor_write_master_waitrequest + Input + 1 + waitrequest + + + descriptor_write_master_response + Input + 2 + response + + + descriptor_write_master_writeresponsevalid + Input + 1 + writeresponsevalid + + + false + descriptor_memory + s1 + descriptor_memory.s1 + 406847488 + 8192 + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clock_clk + Input + 1 + clk + + + + + + java.lang.String + clock + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n_reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 32 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clock + false + true + true + true + + + java.lang.String + reset_n + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + 0 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + csr_writedata + Input + 32 + writedata + + + csr_write + Input + 1 + write + + + csr_byteenable + Input + 4 + byteenable + + + csr_readdata + Output + 32 + readdata + + + csr_read + Input + 1 + read + + + csr_address + Input + 3 + address + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 32 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clock + false + true + true + true + + + java.lang.String + reset_n + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + 0 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + prefetcher_csr_address + Input + 3 + address + + + prefetcher_csr_read + Input + 1 + read + + + prefetcher_csr_write + Input + 1 + write + + + prefetcher_csr_writedata + Input + 32 + writedata + + + prefetcher_csr_readdata + Output + 32 + readdata + + + + + + com.altera.entityinterfaces.IConnectionPoint + msgdma_rx.prefetcher_csr + false + true + true + true + + + java.lang.String + clock + false + true + false + true + + + java.lang.String + reset_n + false + true + false + true + + + java.lang.Integer + 0 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + true + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + csr_irq_irq + Output + 1 + irq + + + + + + java.lang.String + clock + false + true + false + true + + + java.lang.String + reset_n + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 4 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + false + + st_sink_data + Input + 32 + data + + + st_sink_valid + Input + 1 + valid + + + st_sink_ready + Output + 1 + ready + + + st_sink_startofpacket + Input + 1 + startofpacket + + + st_sink_endofpacket + Input + 1 + endofpacket + + + st_sink_empty + Input + 2 + empty + + + st_sink_error + Input + 6 + error + + + + + + + embeddedsw.CMacro.BURST_ENABLE + 0 + + + embeddedsw.CMacro.BURST_WRAPPING_SUPPORT + 0 + + + embeddedsw.CMacro.CHANNEL_ENABLE + 0 + + + embeddedsw.CMacro.CHANNEL_ENABLE_DERIVED + 0 + + + embeddedsw.CMacro.CHANNEL_WIDTH + 8 + + + embeddedsw.CMacro.DATA_FIFO_DEPTH + 32 + + + embeddedsw.CMacro.DATA_WIDTH + 32 + + + embeddedsw.CMacro.DESCRIPTOR_FIFO_DEPTH + 8 + + + embeddedsw.CMacro.DMA_MODE + 1 + + + embeddedsw.CMacro.ENHANCED_FEATURES + 0 + + + embeddedsw.CMacro.ERROR_ENABLE + 1 + + + embeddedsw.CMacro.ERROR_ENABLE_DERIVED + 1 + + + embeddedsw.CMacro.ERROR_WIDTH + 1 + + + embeddedsw.CMacro.MAX_BURST_COUNT + 2 + + + embeddedsw.CMacro.MAX_BYTE + 2048 + + + embeddedsw.CMacro.MAX_STRIDE + 1 + + + embeddedsw.CMacro.PACKET_ENABLE + 1 + + + embeddedsw.CMacro.PACKET_ENABLE_DERIVED + 1 + + + embeddedsw.CMacro.PREFETCHER_ENABLE + 1 + + + embeddedsw.CMacro.PROGRAMMABLE_BURST_ENABLE + 0 + + + embeddedsw.CMacro.RESPONSE_PORT + 2 + + + embeddedsw.CMacro.STRIDE_ENABLE + 0 + + + embeddedsw.CMacro.STRIDE_ENABLE_DERIVED + 0 + + + embeddedsw.CMacro.TRANSFER_TYPE + Aligned Accesses + + + embeddedsw.dts.compatible + altr,msgdma-1.0 + + + embeddedsw.dts.group + msgdma + + + embeddedsw.dts.name + msgdma + + + embeddedsw.dts.vendor + altr + + + int + 1 + false + true + true + true + + + int + 32 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 32 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 32 + false + true + true + true + + + int + 8 + false + true + true + true + + + int + 2 + false + false + true + true + + + int + 2048 + false + true + true + true + + + java.lang.String + Aligned Accesses + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 2 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 0 + true + true + false + true + + + int + 1 + false + true + true + true + + + int + 1 + true + true + false + true + + + int + 1 + false + true + true + true + + + int + 1 + true + true + false + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + true + true + false + true + + + int + 8 + false + false + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 32 + false + true + true + true + + + int + 2 + false + false + true + true + + + java.lang.String + MAX10FPGA + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + 10M50DAF484C6GES + false + true + false + true + DEVICE + + + java.lang.String + 6 + false + true + false + true + DEVICE_SPEEDGRADE + + + com.altera.entityinterfaces.moduleext.AddressMap + ]]> + false + true + false + true + ADDRESS_MAP + mm_read + + + com.altera.entityinterfaces.moduleext.AddressWidthType + AddressWidth = 28 + false + true + false + true + ADDRESS_WIDTH + mm_read + + + com.altera.entityinterfaces.moduleext.AddressMap + + false + true + false + true + ADDRESS_MAP + mm_write + + + com.altera.entityinterfaces.moduleext.AddressWidthType + AddressWidth = -1 + false + true + false + true + ADDRESS_WIDTH + mm_write + + + com.altera.entityinterfaces.moduleext.AddressMap + ]]> + false + true + false + true + ADDRESS_MAP + descriptor_read_master + + + com.altera.entityinterfaces.moduleext.AddressWidthType + AddressWidth = 29 + false + true + false + true + ADDRESS_WIDTH + descriptor_read_master + + + com.altera.entityinterfaces.moduleext.AddressMap + ]]> + false + true + false + true + ADDRESS_MAP + descriptor_write_master + + + com.altera.entityinterfaces.moduleext.AddressWidthType + AddressWidth = 29 + false + true + false + true + ADDRESS_WIDTH + descriptor_write_master + + + java.lang.String + MAX 10 + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clock + false + true + true + true + + + java.lang.String + reset_n + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + mm_read_address + Output + 28 + address + + + mm_read_read + Output + 1 + read + + + mm_read_byteenable + Output + 4 + byteenable + + + mm_read_readdata + Input + 32 + readdata + + + mm_read_waitrequest + Input + 1 + waitrequest + + + mm_read_readdatavalid + Input + 1 + readdatavalid + + + false + ddr3_ram + avl + ddr3_ram.avl + 134217728 + 134217728 + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clock + false + true + true + true + + + java.lang.String + reset_n + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + descriptor_read_master_address + Output + 29 + address + + + descriptor_read_master_read + Output + 1 + read + + + descriptor_read_master_readdata + Input + 32 + readdata + + + descriptor_read_master_waitrequest + Input + 1 + waitrequest + + + descriptor_read_master_readdatavalid + Input + 1 + readdatavalid + + + false + descriptor_memory + s1 + descriptor_memory.s1 + 406847488 + 8192 + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clock + false + true + true + true + + + java.lang.String + reset_n + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 3 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + descriptor_write_master_address + Output + 29 + address + + + descriptor_write_master_write + Output + 1 + write + + + descriptor_write_master_byteenable + Output + 4 + byteenable + + + descriptor_write_master_writedata + Output + 32 + writedata + + + descriptor_write_master_waitrequest + Input + 1 + waitrequest + + + descriptor_write_master_response + Input + 2 + response + + + descriptor_write_master_writeresponsevalid + Input + 1 + writeresponsevalid + + + false + descriptor_memory + s1 + descriptor_memory.s1 + 406847488 + 8192 + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clock_clk + Input + 1 + clk + + + + + + java.lang.String + clock + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n_reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 32 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clock + false + true + true + true + + + java.lang.String + reset_n + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + 0 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + csr_writedata + Input + 32 + writedata + + + csr_write + Input + 1 + write + + + csr_byteenable + Input + 4 + byteenable + + + csr_readdata + Output + 32 + readdata + + + csr_read + Input + 1 + read + + + csr_address + Input + 3 + address + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 32 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clock + false + true + true + true + + + java.lang.String + reset_n + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + 0 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + prefetcher_csr_address + Input + 3 + address + + + prefetcher_csr_read + Input + 1 + read + + + prefetcher_csr_write + Input + 1 + write + + + prefetcher_csr_writedata + Input + 32 + writedata + + + prefetcher_csr_readdata + Output + 32 + readdata + + + + + + com.altera.entityinterfaces.IConnectionPoint + msgdma_tx.prefetcher_csr + false + true + true + true + + + java.lang.String + clock + false + true + false + true + + + java.lang.String + reset_n + false + true + false + true + + + java.lang.Integer + 0 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + true + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + csr_irq_irq + Output + 1 + irq + + + + + + java.lang.String + clock + false + true + false + true + + + java.lang.String + reset_n + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 4 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + true + + st_source_data + Output + 32 + data + + + st_source_valid + Output + 1 + valid + + + st_source_ready + Input + 1 + ready + + + st_source_startofpacket + Output + 1 + startofpacket + + + st_source_endofpacket + Output + 1 + endofpacket + + + st_source_empty + Output + 2 + empty + + + st_source_error + Output + 1 + error + + + + + + + embeddedsw.CMacro.BYTES_PER_PAGE + 8192 + + + embeddedsw.CMacro.READ_ONLY_MODE + 0 + + + embeddedsw.CMacro.SECTOR1_ENABLED + 1 + + + embeddedsw.CMacro.SECTOR1_END_ADDR + 32767 + + + embeddedsw.CMacro.SECTOR1_START_ADDR + 0 + + + embeddedsw.CMacro.SECTOR2_ENABLED + 1 + + + embeddedsw.CMacro.SECTOR2_END_ADDR + 65535 + + + embeddedsw.CMacro.SECTOR2_START_ADDR + 32768 + + + embeddedsw.CMacro.SECTOR3_ENABLED + 1 + + + embeddedsw.CMacro.SECTOR3_END_ADDR + 458751 + + + embeddedsw.CMacro.SECTOR3_START_ADDR + 65536 + + + embeddedsw.CMacro.SECTOR4_ENABLED + 1 + + + embeddedsw.CMacro.SECTOR4_END_ADDR + 753663 + + + embeddedsw.CMacro.SECTOR4_START_ADDR + 458752 + + + embeddedsw.CMacro.SECTOR5_ENABLED + 1 + + + embeddedsw.CMacro.SECTOR5_END_ADDR + 1441791 + + + embeddedsw.CMacro.SECTOR5_START_ADDR + 753664 + + + embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR + SIM_DIR + + + embeddedsw.memoryInfo.FLASH_INSTALL_DIR + APP_DIR + + + embeddedsw.memoryInfo.GENERATE_DAT_SYM + 1 + + + embeddedsw.memoryInfo.GENERATE_FLASH + 1 + + + embeddedsw.memoryInfo.GENERATE_HEX + 1 + + + embeddedsw.memoryInfo.HAS_BYTE_LANE + 0 + + + embeddedsw.memoryInfo.HEX_INSTALL_DIR + QPF_DIR + + + embeddedsw.memoryInfo.IS_FLASH + 1 + + + embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH + 32 + + + embeddedsw.memoryInfo.USE_BYTE_ADDRESSING_FOR_HEX + 1 + + + postgeneration.simulation.init_file.param_name + INIT_FILENAME + + + postgeneration.simulation.init_file.type + MEM_INIT + + + java.lang.String + Parallel + false + true + true + true + + + java.lang.String + Incrementing + false + true + true + true + + + int + 8 + false + true + true + true + + + double + 50.0 + false + false + true + true + + + java.lang.String + Internal Configuration + false + false + true + true + + + java.lang.String + Single Uncompressed Image + false + true + true + true + + + [Ljava.lang.String; + 1,2,3,4,5 + true + false + true + true + + + [Ljava.lang.String; + Read and write,Read and write,Read and write,Read and write,Read and write + false + true + true + true + + + [Ljava.lang.String; + 0x00000 - 0x07fff,0x08000 - 0x0ffff,0x10000 - 0x6ffff,0x70000 - 0xb7fff,0xb8000 - 0x15ffff + true + false + true + true + + + [Ljava.lang.String; + UFM,UFM,UFM,CFM,CFM + true + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + D:/projekty/HIT/v2.0/fpga/software/hit20_v3/mem_init/q_sys_onchip_flash.hex + false + false + true + true + + + java.lang.String + altera_onchip_flash.dat + false + false + true + true + + + java.lang.String + q_sys_onchip_flash + false + true + false + true + UNIQUE_ID + + + java.lang.String + + true + false + false + true + + + java.lang.String + + true + false + false + true + + + java.lang.String + MAX10FPGA + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + 10M50DAF484C6GES + false + true + false + true + DEVICE + + + long + 50000000 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.String + 50 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 8191 + true + true + false + true + + + int + 8192 + true + true + false + true + + + int + 16383 + true + true + false + true + + + int + 16384 + true + true + false + true + + + int + 114687 + true + true + false + true + + + int + 114688 + true + true + false + true + + + int + 188415 + true + true + false + true + + + int + 188416 + true + true + false + true + + + int + 360447 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 360447 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 114687 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 360447 + true + true + false + true + + + int + 360447 + true + true + false + true + + + int + 2048 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 19 + true + true + false + true + + + int + 32 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 12 + true + true + false + true + + + int + 60 + true + true + false + true + + + int + 17500000 + true + true + false + true + + + int + 15250 + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + False + true + true + false + true + + + java.lang.String + True + true + true + false + true + + + java.lang.String + False + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clock + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 1 + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.isNonVolatileStorage + 1 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 1441792 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + nreset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 1441792 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + avmm_data_addr + Input + 19 + address + + + avmm_data_read + Input + 1 + read + + + avmm_data_writedata + Input + 32 + writedata + + + avmm_data_write + Input + 1 + write + + + avmm_data_readdata + Output + 32 + readdata + + + avmm_data_waitrequest + Output + 1 + waitrequest + + + avmm_data_readdatavalid + Output + 1 + readdatavalid + + + avmm_data_burstcount + Input + 4 + burstcount + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 8 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + nreset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + avmm_csr_addr + Input + 1 + address + + + avmm_csr_read + Input + 1 + read + + + avmm_csr_writedata + Input + 32 + writedata + + + avmm_csr_write + Input + 1 + write + + + avmm_csr_readdata + Output + 32 + readdata + + + + + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 1 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 8 + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0 + + + embeddedsw.CMacro.EDGE_TYPE + NONE + + + embeddedsw.CMacro.FREQ + 50000000 + + + embeddedsw.CMacro.HAS_IN + 0 + + + embeddedsw.CMacro.HAS_OUT + 1 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.IRQ_TYPE + NONE + + + embeddedsw.CMacro.RESET_VALUE + 0 + + + embeddedsw.dts.compatible + altr,pio-1.0 + + + embeddedsw.dts.group + gpio + + + embeddedsw.dts.name + pio + + + embeddedsw.dts.params.altr,gpio-bank-width + 8 + + + embeddedsw.dts.params.resetvalue + 0 + + + embeddedsw.dts.vendor + altr + + + boolean + false + false + false + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + Output + false + true + true + true + + + java.lang.String + RISING + false + false + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + LEVEL + false + false + true + true + + + long + 0 + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 0 + false + false + true + true + + + int + 8 + false + true + true + true + + + long + 50000000 + false + true + false + true + CLOCK_RATE + clk + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 8 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 3 + address + + + write_n + Input + 1 + write_n + + + writedata + Input + 32 + writedata + + + chipselect + Input + 1 + chipselect + + + readdata + Output + 32 + readdata + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + out_port + Output + 8 + export + + + + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 16 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + rst + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + csr_address + Input + 2 + address + + + csr_read + Input + 1 + read + + + csr_readdata + Output + 32 + readdata + + + csr_write + Input + 1 + write + + + csr_writedata + Input + 32 + writedata + + + csr_byteenable + Input + 4 + byteenable + + + + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + rst + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + true + + data_out_endofpacket + Output + 1 + endofpacket + + + data_out_data + Output + 32 + data + + + data_out_empty + Output + 2 + empty + + + data_out_ready + Input + 1 + ready + + + data_out_startofpacket + Output + 1 + startofpacket + + + data_out_valid + Output + 1 + valid + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk_clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + rst_reset + Input + 1 + reset + + + + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + in_adc_data + Input + 5 + in_adc_data + + + in_trg + Input + 1 + in_trg + + + out_adc_clk + Output + 1 + out_adc_clk + + + out_adc_cnv + Output + 1 + out_adc_cnv + + + out_sensor_clk + Output + 1 + out_sensor_clk + + + out_sensor_gain + Output + 1 + out_sensor_gain + + + out_sensor_rst + Output + 1 + out_sensor_rst + + + + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + status_out + Output + 8 + status_out + + + + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + ext_input + Input + 8 + ext_input + + + serial_rx + Input + 1 + serial_rx + + + serial_tx + Output + 1 + serial_tx + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + rst + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + address + Output + 9 + address + + + clken + Output + 1 + read + + + cali_fac + Input + 16 + readdata + + + waitrequest + Input + 1 + waitrequest + + + false + calibration_ram + s2 + calibration_ram.s2 + 0 + 640 + + + + + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + long + 0 + false + true + false + true + CLOCK_RATE + clk_in + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + qsys.ui.export_name + clk + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + in_clk + Input + 1 + clk + + + + + + qsys.ui.export_name + reset + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + java.lang.String + clk_in + false + true + true + true + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + clk_out + Output + 1 + clk + + + false + sysid + clk + sysid.clk + + + false + sys_clk_timer + clk + sys_clk_timer.clk + + + false + cpu + clk + cpu.clk + + + false + output_pio + clk + output_pio.clk + + + false + button_pio + clk + button_pio.clk + + + false + debug_uart + clk + debug_uart.clk + + + false + onchip_flash + clk + onchip_flash.clk + + + false + tx_multiplexer + clk + tx_multiplexer.clk + + + false + channel_adapter_0 + clk + channel_adapter_0.clk + + + false + udp_generator + clk + udp_generator.clk + + + false + frame_timer + clk + frame_timer.clk + + + false + sensor_interface + clk + sensor_interface.clk + + + false + descriptor_memory + clk1 + descriptor_memory.clk1 + + + false + calibration_ram + clk1 + calibration_ram.clk1 + + + false + calibration_ram + clk2 + calibration_ram.clk2 + + + false + msgdma_tx + clock + msgdma_tx.clock + + + false + msgdma_rx + clock + msgdma_rx.clock + + + false + eth_tse + control_port_clock_connection + eth_tse.control_port_clock_connection + + + false + enet_pll + inclk_interface + enet_pll.inclk_interface + + + false + altpll_shift + inclk_interface + altpll_shift.inclk_interface + + + false + eth_tse + receive_clock_connection + eth_tse.receive_clock_connection + + + false + eth_tse + transmit_clock_connection + eth_tse.transmit_clock_connection + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + clk_in_reset + false + true + true + true + + + [Ljava.lang.String; + clk_in_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + reset_n_out + Output + 1 + reset_n + + + + + + + embeddedsw.CMacro.ALWAYS_RUN + 0 + + + embeddedsw.CMacro.COUNTER_SIZE + 32 + + + embeddedsw.CMacro.FIXED_PERIOD + 0 + + + embeddedsw.CMacro.FREQ + 50000000 + + + embeddedsw.CMacro.LOAD_VALUE + 499999 + + + embeddedsw.CMacro.MULT + 0.001 + + + embeddedsw.CMacro.PERIOD + 10 + + + embeddedsw.CMacro.PERIOD_UNITS + ms + + + embeddedsw.CMacro.RESET_OUTPUT + 0 + + + embeddedsw.CMacro.SNAPSHOT + 1 + + + embeddedsw.CMacro.TICKS_PER_SEC + 100 + + + embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT + 0 + + + embeddedsw.dts.compatible + altr,timer-1.0 + + + embeddedsw.dts.group + timer + + + embeddedsw.dts.name + timer + + + embeddedsw.dts.params.clock-frequency + 50000000 + + + embeddedsw.dts.vendor + altr + + + boolean + false + false + true + true + true + + + int + 32 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + 10 + false + true + true + true + + + java.lang.String + MSEC + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + long + 50000000 + false + true + false + true + CLOCK_RATE + clk + + + int + 2 + false + true + false + true + + + java.lang.String + FULL_FEATURED + true + true + false + true + + + java.lang.String + ms + true + true + false + true + + + double + 0.001 + true + true + false + true + + + java.lang.String + 499999 + true + true + false + true + + + double + 0.001 + true + true + false + true + + + double + 100.0 + true + true + false + true + + + int + 3 + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + embeddedsw.configuration.isTimerDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 8 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 3 + address + + + writedata + Input + 16 + writedata + + + readdata + Output + 16 + readdata + + + chipselect + Input + 1 + chipselect + + + write_n + Input + 1 + write_n + + + + + + com.altera.entityinterfaces.IConnectionPoint + sys_clk_timer.s1 + false + true + true + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + java.lang.Integer + + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + true + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + irq + Output + 1 + irq + + + + + + + embeddedsw.CMacro.ID + 4207856382 + + + embeddedsw.CMacro.TIMESTAMP + 1729065917 + + + embeddedsw.dts.compatible + altr,sysid-1.0 + + + embeddedsw.dts.group + sysid + + + embeddedsw.dts.name + sysid + + + embeddedsw.dts.params.id + 4207856382 + + + embeddedsw.dts.params.timestamp + 1729065917 + + + embeddedsw.dts.vendor + altr + + + int + -87110914 + false + true + true + true + + + int + 1729065917 + true + false + false + true + GENERATION_ID + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clock + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isMemoryDevice + false + + + embeddedsw.configuration.isNonVolatileStorage + false + + + embeddedsw.configuration.isPrintableDevice + false + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 8 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + readdata + Output + 32 + readdata + + + address + Input + 1 + address + + + + + + + int + 1 + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + true + true + false + true + + + java.lang.String + AUTO + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 2 + false + true + true + true + + + int + 512 + false + false + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + true + true + + + int + 4 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 4 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + true + + out_data + Output + 32 + data + + + out_valid + Output + 1 + valid + + + out_ready + Input + 1 + ready + + + out_startofpacket + Output + 1 + startofpacket + + + out_endofpacket + Output + 1 + endofpacket + + + out_empty + Output + 2 + empty + + + out_error + Output + 1 + error + + + out_channel + Output + 1 + channel + + + + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 4 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + false + + in0_data + Input + 32 + data + + + in0_valid + Input + 1 + valid + + + in0_ready + Output + 1 + ready + + + in0_startofpacket + Input + 1 + startofpacket + + + in0_endofpacket + Input + 1 + endofpacket + + + in0_empty + Input + 2 + empty + + + in0_error + Input + 1 + error + + + + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 4 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + false + + in1_data + Input + 32 + data + + + in1_valid + Input + 1 + valid + + + in1_ready + Output + 1 + ready + + + in1_startofpacket + Input + 1 + startofpacket + + + in1_endofpacket + Input + 1 + endofpacket + + + in1_empty + Input + 2 + empty + + + in1_error + Input + 1 + error + + + + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk_clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + rst_reset + Input + 1 + reset + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 32 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + rst + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + csr_address + Input + 3 + address + + + csr_write + Input + 1 + write + + + csr_writedata + Input + 32 + writedata + + + csr_byteenable + Input + 4 + byteenable + + + csr_read + Input + 1 + read + + + csr_readdata + Output + 32 + readdata + + + + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + rst + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 4 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + false + + data_in_data + Input + 32 + data + + + data_in_ready + Output + 1 + ready + + + data_in_valid + Input + 1 + valid + + + data_in_empty + Input + 2 + empty + + + data_in_endofpacket + Input + 1 + endofpacket + + + data_in_startofpacket + Input + 1 + startofpacket + + + + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + rst + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 4 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + true + + data_out_data + Output + 32 + data + + + data_out_empty + Output + 2 + empty + + + data_out_endofpacket + Output + 1 + endofpacket + + + data_out_startofpacket + Output + 1 + startofpacket + + + data_out_ready + Input + 1 + ready + + + data_out_valid + Output + 1 + valid + + + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x0000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sensor_interface + calibration_ram_interface + calibration_ram + s2 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x08000000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + ddr3_ram + avl + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18403d20 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + ext_flash + avl_csr + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x14000000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + ext_flash + avl_mem + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18403000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + eth_tse + control_port + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18403d68 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + sysid + control_slave + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18403d00 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + msgdma_tx + csr + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18403ce0 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + msgdma_rx + csr + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18403d60 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + onchip_flash + csr + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18403cc0 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + udp_generator + csr + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18403d50 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + sensor_interface + csr + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18200000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + onchip_flash + data + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18402800 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + cpu + debug_mem_slave + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18403ca0 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + msgdma_tx + prefetcher_csr + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18403c80 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + msgdma_rx + prefetcher_csr + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18400000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + descriptor_memory + s1 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18403c60 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + sys_clk_timer + s1 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18403c40 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + output_pio + s1 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18403d40 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + button_pio + s1 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18403c20 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + debug_uart + s1 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18403c00 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + frame_timer + s1 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18403400 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + calibration_ram + s1 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18400000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + msgdma_tx + descriptor_read_master + descriptor_memory + s1 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18400000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + msgdma_rx + descriptor_read_master + descriptor_memory + s1 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18400000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + msgdma_tx + descriptor_write_master + descriptor_memory + s1 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18400000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + msgdma_rx + descriptor_write_master + descriptor_memory + s1 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x08000000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + instruction_master + ddr3_ram + avl + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x14000000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + instruction_master + ext_flash + avl_mem + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18200000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + instruction_master + onchip_flash + data + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x18402800 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + instruction_master + cpu + debug_mem_slave + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x08000000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + msgdma_tx + mm_read + ddr3_ram + avl + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x08000000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + msgdma_rx + mm_write + ddr3_ram + avl + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sensor_interface + data_out + udp_generator + data_in + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + udp_generator + data_out + tx_multiplexer + in1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + tx_multiplexer + out + channel_adapter_0 + in + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + channel_adapter_0 + out + eth_tse + transmit + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + eth_tse + receive + msgdma_rx + st_sink + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + msgdma_tx + st_source + tx_multiplexer + in0 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk + sysid + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk + sys_clk_timer + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk + cpu + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk + output_pio + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk + button_pio + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk + debug_uart + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk + onchip_flash + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk + tx_multiplexer + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk + channel_adapter_0 + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk + udp_generator + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk + frame_timer + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk + sensor_interface + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk + descriptor_memory + clk1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk + calibration_ram + clk1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk + calibration_ram + clk2 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk + msgdma_tx + clock + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk + msgdma_rx + clock + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk + eth_tse + control_port_clock_connection + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk + enet_pll + inclk_interface + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk + altpll_shift + inclk_interface + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk + eth_tse + receive_clock_connection + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk + eth_tse + transmit_clock_connection + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + ext_flash_clock_bridge + out_clk + ext_flash + clock_sink + + + + int + 2 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + irq + msgdma_tx + csr_irq + + + + int + 3 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + irq + msgdma_rx + csr_irq + + + + int + 5 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + irq + ext_flash + interrupt_sender + + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + irq + sys_clk_timer + irq + + + + int + 4 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + irq + debug_uart + irq + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk_reset + onchip_flash + nreset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk_reset + sys_clk_timer + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk_reset + sysid + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk_reset + cpu + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk_reset + output_pio + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk_reset + ext_flash + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk_reset + button_pio + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk_reset + debug_uart + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk_reset + tx_multiplexer + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk_reset + channel_adapter_0 + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk_reset + frame_timer + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk_reset + descriptor_memory + reset1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk_reset + calibration_ram + reset1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk_reset + calibration_ram + reset2 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk_reset + eth_tse + reset_connection + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk_reset + msgdma_tx + reset_n + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk_reset + msgdma_rx + reset_n + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk_reset + udp_generator + rst + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sys_clk + clk_reset + sensor_interface + rst + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + debug_reset_request + ddr3_ram + global_reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + debug_reset_request + ext_flash + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + debug_reset_request + sys_clk_timer + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + debug_reset_request + sysid + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + debug_reset_request + output_pio + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + debug_reset_request + descriptor_memory + reset1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + debug_reset_request + eth_tse + reset_connection + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + debug_reset_request + ddr3_ram + soft_reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + ddr3_ram_resetn + out_reset + ddr3_ram + global_reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + ddr3_ram_resetn + out_reset + altpll_shift + inclk_interface_reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + ddr3_ram_resetn + out_reset + enet_pll + inclk_interface_reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + ddr3_ram_resetn + out_reset + ddr3_ram + soft_reset + + + 2 + altpll + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + ALTPLL Intel FPGA IP + 19.1 + + + 27 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 19.1 + + + 24 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 19.1 + + + 24 + avalon_slave + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Slave + 19.1 + + + 9 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output + 19.1 + + + 20 + conduit_end + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Conduit + 19.1 + + + 2 + altera_avalon_pio + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + PIO (Parallel I/O) Intel FPGA IP + 19.1 + + + 2 + altera_avalon_onchip_memory2 + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + On-Chip Memory (RAM or ROM) Intel FPGA IP + 19.1 + + + 1 + channel_adapter + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Avalon-ST Channel Adapter + 19.1 + + + 6 + avalon_streaming_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Streaming Sink + 19.1 + + + 6 + avalon_streaming_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Streaming Source + 19.1 + + + 1 + altera_nios2_gen2 + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Nios II Processor + 19.1 + + + 9 + avalon_master + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Master + 19.1 + + + 1 + interrupt_receiver + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Receiver + 19.1 + + + 4 + reset_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Output + 19.1 + + + 1 + nios_custom_instruction_master + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Custom Instruction Master + 19.1 + + + 1 + altera_mem_if_ddr3_emif + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + DDR3 SDRAM Controller with UniPHY Intel FPGA IP + 19.1 + + + 1 + altera_reset_bridge + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Reset Bridge + 19.1 + + + 1 + altera_avalon_uart + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + UART (RS-232 Serial Port) Intel FPGA IP + 19.1 + + + 6 + interrupt_sender + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Sender + 19.1 + + + 1 + altera_eth_tse + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Triple-Speed Ethernet Intel FPGA IP + 19.1 + + + 1 + altera_generic_quad_spi_controller + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Generic QUAD SPI Controller Intel FPGA IP + 19.1 + + + 1 + altera_clock_bridge + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Clock Bridge + 19.1 + + + 2 + altera_avalon_timer + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Interval Timer Intel FPGA IP + 19.1 + + + 2 + altera_msgdma + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Modular Scatter-Gather DMA Intel FPGA IP + 19.1 + + + 1 + altera_onchip_flash + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + On-Chip Flash Intel FPGA IP + 19.1 + + + 1 + sensor_recon + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + sensor_recon_rms_cali + 1 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Clock Source + 19.1 + + + 1 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 19.1 + + + 1 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 19.1 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output + 19.1 + + + 1 + reset_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Output + 19.1 + + + 1 + altera_avalon_sysid_qsys + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + System ID Peripheral Intel FPGA IP + 19.1 + + + 1 + multiplexer + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Avalon-ST Multiplexer + 19.1 + + + 1 + udp_generator + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + UDP generator + 1.0 + + + 32 + avalon + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Avalon Memory Mapped Connection + 19.1 + + + 6 + avalon_streaming + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Avalon Streaming Connection + 19.1 + + + 23 + clock + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Clock Connection + 19.1 + + + 5 + interrupt + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Interrupt Connection + 19.1 + + + 31 + reset + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Reset Connection + 19.1 + + 19.1 670 + + diff --git a/LICENSE b/LICENSE index d5075a3..d5445e6 100644 --- a/LICENSE +++ b/LICENSE @@ -1,8 +1,23 @@ -Permission is hereby granted, without written agreement and without -license or royalty fees, to use, copy, modify, and distribute this -software and its documentation for any purpose, provided that the -above copyright notice and the following two paragraphs appear in -all copies of this software. +Scintillating Fibre Beam Profile Monitor Software by Michal Dziewiecki, Blake Leverington and Liqing Qin is licensed under CC BY 4.0 + +https://creativecommons.org/licenses/by/4.0/ + + +You are free to: + Share — copy and redistribute the material in any medium or format for any purpose, even commercially. + Adapt — remix, transform, and build upon the material for any purpose, even commercially. + The licensor cannot revoke these freedoms as long as you follow the license terms. + +Under the following terms: + + Attribution — You must give appropriate credit , provide a link to the license, and indicate if changes were made . You may do so in any reasonable manner, but not in any way that suggests the licensor endorses you or your use. + No additional restrictions — You may not apply legal terms or technological measures that legally restrict others from doing anything the license permits. + +Notices: + +You do not have to comply with the license for elements of the material in the public domain or where your use is permitted by an applicable exception or limitation . + +No warranties are given. The license may not give you all of the permissions necessary for your intended use. For example, other rights such as publicity, privacy, or moral rights may limit how you use the material. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES diff --git a/README.md b/README.md index 23dfab5..ea7f4fc 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,15 @@ +DFG reference number: LE 4256/1-1 +Project number: 419255448 +Project title: A scintillating fibre based beam profile monitor for ion therapy beams +Name(s) of the applicant(s): Dr. Blake Dean Leverington, Ph.D. +Official address(es): Physikalisches Institut, Im Neuenheimer Feld 226, 69120 Heidelberg + +This repository contains the code and documentation for the project. It contains the DAQ software, as well as the electronics design files, and documention. This project was developed by Blake Leverington, Michal Dziewiecki, and Liqing Qin. The project was supported by the Deutsche Forschungsgemeinschaft (DFG), Heidelberg Universitaet, and the Heidelberg Ion-beam Therapy Clinic (HIT). + + # HITDAQ +Recomended stable version is in */hit2023v2_RMS* + The data acquisition software currently compiled with QtCreator on Windows 11, Qt6.5.2, MinGW-11.2.0 64-bit. Needs QtSerialPort. Also uses QCustomPlot from https://www.qcustomplot.com/release/2.1.1/QCustomPlot-source.tar.gz \ No newline at end of file diff --git a/data_analyser/hitreader.h b/data_analyser/hitreader.h new file mode 100644 index 0000000..af72780 --- /dev/null +++ b/data_analyser/hitreader.h @@ -0,0 +1,601 @@ +/****************************************************************************** +* Copyright * +* Scintillating Fibre Beam Profile Monitor Software by Michal Dziewiecki, * +* Blake Leverington and Liqing Qin is licensed under CC BY 4.0 * +* https://creativecommons.org/licenses/by/4.0/ * +* funded by the Deutsche Forschungsgemeinschaft * +* (DFG, German Research Foundation) Projektnummer 419255448 * +* Project Leader: B.Leverington * +******************************************************************************* +* Create Date - 2019 * +* Author: M.Dziewiecki * +* Module - hitreader.h * +* Edited by L.Qin on 01. Feb. 2024 * +******************************************************************************/ + +// This is an object interface for reading HIT data files for testbeam 2024Feb/Aug with the new FPGA firmware. +// See HIT documentation for details and examples. +/* + .L hitreader.c + + Hitdata data; + data.readFile(“my_file.da2”); //to load whole file at once – forget it! See below. + data.readFile(“my_file.da2”,1000,100,10) //to read 100 frames starting from frame 1000 and incrementing by 10 (i.e. frame 1000, 1010, 1020, ... 1990 will be read) + //Reading 10 000 frames is reasonable. Reading 100 000 frames made my VM beg for memory. + + data.nrFrames //to see how many frames you have + data.frames[0].nrBoards //to see how many boards you had in the system + data.frames[0].boards[0].nrChannels //to see how many channels you have in board 0 + data.frames[10].boards[0].data[100] //get signal value for frame 10, board 0, channel 100 + data.frames[10].boards[0].syncframe.local_ctr //get the local synchro counter for frame 10, board 0 + //same for .global_ctr, .sma_state, .dummy, .device_nr, .data_ok + + */ + +//*********************** Helper ************************* + +#include +#include +#define DATASOURCE string("2024_08_08") + + +using namespace std; + +// #define debug(str) std::cout << "HIT DEBUG: " << str << endl; +#define debug(str) + +//*********************** Fpgasframe ************************* + /* reg results has 32*4 bits + WORDS 163 [31:16]MeanXleftshift [15:0] Sigma0; + 164 [31:16]MaxY; [15:0] STATUS; + 165 for debug; + 166 for debut; + + results[1][0] <= bkg_sub_on; + results[1][1] <= has_cluster; + results[1][2] <= no_cluster; + results[2][31:16] <= {7'b0,Windowleft}; + results[2][15:0] <= {7'b0,Windowright}; + for status register: + STATUS_BKG_SUB_ON 0x0001 + STATUS_HAS_CLUSTER 0x0002 + STATUS_NO_CLUSTER 0x0004 + */ + +class Fpgasframe +{ +public: + Fpgasframe() + { + debug("Fpgasframe()"); + + Position = Sigma = Peak = Status = 0; + Dummy0 = Dummy1 = 0; + BKG_SUB_ON = Status & 0x0001; + HAS_CLUSTER = Status & 0x0002; + NO_CLUSTER = Status & 0x0004; + Windowleft = (Dummy0 & 0xFFFF0000)>>16; + Windowright = (Dummy0 & 0x0000FFFF); + }; + + ~Fpgasframe() + { + debug("~Fpgasframe()"); + }; + + int sizeInFile() + { + return 16; + }; + + int read(std::ifstream *file) + { + char buffer[16]; + file->read(buffer, 16); + if (file->fail()) + return 1; + Position = *(unsigned short *)(buffer + 0)*0.05; + Sigma = *(unsigned short *)(buffer + 2)*0.05; + Peak = *(unsigned short *)(buffer + 4); + Status = *(unsigned short *)(buffer + 6); + Dummy0 = *(int *)(buffer + 8); + Dummy1 = *(int *)(buffer + 12); + BKG_SUB_ON = (Status & 0x0001)>>0; + HAS_CLUSTER = (Status & 0x0002)>>1; + NO_CLUSTER = (Status & 0x0004)>>2; + Windowright = (Dummy0 & 0xFFFF0000)>>16; + Windowleft = (Dummy0 & 0x0000FFFF); + //std::cout << "Fpgasframe:" << Position << " " << Sigma << " " << Peak << " " << Status << " " << Dummy0 << " " << Dummy1 << std::endl; + return 0; + }; + + int write(std::ofstream *file) + { + char buffer[16]; + *(unsigned short *)(buffer + 0) = Position/0.05; + *(unsigned short *)(buffer + 2) = Sigma/0.05; + *(unsigned short *)(buffer + 4) = Peak; + *(unsigned short *)(buffer + 6) = Status; + *(int *)(buffer + 8) = Dummy0; + *(int *)(buffer + 12) = Dummy1; + + file->write(buffer, 16); + + if (file->fail()) + return 1; + + return 0; + } + + double Position; + double Sigma; + unsigned short Peak; + unsigned short Status; + unsigned short Windowleft; + unsigned short Windowright; + unsigned short BKG_SUB_ON; + unsigned short HAS_CLUSTER; + unsigned short NO_CLUSTER; + int Dummy0; + int Dummy1; +}; + +//*********************** Syncframe ************************* +class Syncframe +{ +public: + Syncframe() + { + debug("Syncframe()"); + + local_ctr = global_ctr = 0; + sma_state = dummy = 0; + device_nr = -1; + data_ok = 0; + }; + + ~Syncframe() + { + debug("~Syncframe()"); + }; + + int sizeInFile() + { + return 16; + }; + + int read(std::ifstream *file) + { + char buffer[16]; + file->read(buffer, 16); + if (file->fail()) + return 1; + local_ctr = *(unsigned short *)(buffer + 0); + global_ctr = *(unsigned short *)(buffer + 2); + sma_state = *(unsigned short *)(buffer + 4); + dummy = *(unsigned short *)(buffer + 6); + device_nr = *(int *)(buffer + 8); + data_ok = *(int *)(buffer + 12); + // std::cout << "Syncframe:" << local_ctr << " " << global_ctr << " " << sma_state << " " << dummy << " " << device_nr << " " << data_ok << std::endl; + + return 0; + }; + + int write(std::ofstream *file) + { + char buffer[16]; + *(unsigned short *)(buffer + 0) = local_ctr; + *(unsigned short *)(buffer + 2) = global_ctr; + *(unsigned short *)(buffer + 4) = sma_state; + *(unsigned short *)(buffer + 6) = dummy; + *(int *)(buffer + 8) = device_nr; + *(int *)(buffer + 12) = data_ok; + + file->write(buffer, 16); + + if (file->fail()) + return 1; + + return 0; + } + + unsigned short local_ctr; + unsigned short global_ctr; + unsigned short sma_state; + unsigned short dummy; + int device_nr; + unsigned int data_ok; +}; + +//*********************** Sensorframe ************************* +class Boardframe +{ +public: + Boardframe(int nr_channels = 0) + { + debug("Boardframe()"); + + data = NULL; + resize(nr_channels); + }; + + Boardframe(const Boardframe &in) + { + debug("Boardframe(Boardframe&)"); + + data = NULL; + resize(in.nrChannels); + for (int i = 0; i < nrChannels; i++) + data[i] = in.data[i]; + syncframe = in.syncframe; + fpgas = in.fpgas; + }; + + Boardframe &operator=(const Boardframe &in) + { + debug("Boardframe::operator=="); + + resize(in.nrChannels); // creates an array called data of length nrChannels + for (int i = 0; i < nrChannels; i++) + data[i] = in.data[i]; + syncframe = in.syncframe; + fpgas = in.fpgas; + return *this; + }; + + ~Boardframe() + { + debug("~Boardframe()"); + + if (data) + delete[] data; + }; + + void resize(int nr_channels) + { + if (data) + delete[] data; + nrChannels = nr_channels; + if (nrChannels) + data = new signed short[nrChannels]; + else + data = NULL; + }; + + int sizeInFile() + { + return syncframe.sizeInFile() + nrChannels * 2 + fpgas.sizeInFile(); + }; + + int read(std::ifstream *file) + { + if (syncframe.read(file) == 1) // get the syncframe before the board data + return 1; + // I must be already resized at this point! + file->read((char *)data, 2 * nrChannels); + if (file->fail()) + return 1; + if (fpgas.read(file) == 1) // get the fpgasframe after the board data + return 1; + // for print data out + /* std::cout<< "data[" << nrChannels << "]: "; + for (int i = 0;iwrite(reinterpret_cast(data), 2 * nrChannels); + + if (file->fail()) + return 1; + + if (!fpgas.write(file)) + return 1; + + return 0; + } + + signed short &operator[](int index) + { + return data[index]; + }; + + Syncframe syncframe; + int nrChannels; + signed short *data; + Fpgasframe fpgas; +}; + +//*********************** Fullframe ************************* +class Fullframe +{ +public: + Fullframe(int nr_boards = 0) + { + debug("Fullframe()"); + boards = NULL; + resize(nr_boards); + }; + + Fullframe(const Fullframe &in) + { + debug("Fullframe(Fullframe&)"); + boards = NULL; + resize(in.nrBoards); + for (int i = 0; i < nrBoards; i++) + boards[i] = in.boards[i]; + }; + + Fullframe &operator=(const Fullframe &in) + { + debug("Fullframe::operator=="); + resize(in.nrBoards); + for (int i = 0; i < nrBoards; i++) + boards[i] = in.boards[i]; + + return *this; + }; + + ~Fullframe() + { + debug("~Fullframe()"); + if (boards) + delete[] boards; + }; + + void resize(int nr_boards) + { + if (boards) + delete[] boards; + nrBoards = nr_boards; + if (nrBoards) + boards = new Boardframe[nrBoards]; + else + boards = NULL; + } + + int sizeInFile() + { + int sum_size = 0; + if (boards) + { + for (int i = 0; i < nrBoards; i++) + sum_size += boards[i].sizeInFile(); + return 2 + nrBoards * 2 + sum_size; + } + // return 2 + 4*2 + (16 +320*2)+(16+128*2)*3; + // return 2 + nrBoards*2 + nrBoards * boards[0].sizeInFile(); + else + return 1; // no boards, makes no sense... + }; + + int read(std::ifstream *file) + { + // Read number of boards + unsigned short nr_boards; + file->read((char *)&nr_boards, 2); + if (file->fail() || nr_boards > 6) + { + std::cerr << "Unrealistic number of board to be read:" << nr_boards << std::endl; + return 1; + } + // std::cout << " nr_boards: " << nr_boards << std::endl; + // Read channel counts + unsigned short *channel_counts = new unsigned short[nr_boards]; + file->read((char *)channel_counts, nr_boards * 2); + if (file->fail()) + { + delete[] channel_counts; + return 1; + } + + // Read board frames + resize(nr_boards); + for (int board_nr = 0; board_nr < nr_boards; board_nr++) + { + // std::cout << " channel_counts[" << board_nr << "]: "<< channel_counts[board_nr] << std::endl; + + boards[board_nr].resize(channel_counts[board_nr]); + if (boards[board_nr].read(file) == 1) // read the board + { + delete[] channel_counts; + return 1; + } + } + + delete[] channel_counts; + return 0; + }; + + int write(std::ofstream *file) + { + // write nrboards + file->write((char *)&nrBoards, 2); + unsigned short *channel_counts = new unsigned short[nrBoards]; + for (int board_nr = 0; board_nr < nrBoards; board_nr++) + { + channel_counts[board_nr] = boards[board_nr].nrChannels; + } + file->write((char *)channel_counts, nrBoards * 2); + for (int board_nr = 0; board_nr < nrBoards; board_nr++) + { + if (boards[board_nr].write(file) == 1) // write the board + { + delete[] channel_counts; + return 1; + } + } + delete[] channel_counts; + return 0; + }; + + TGraph *plot(int board_nr) + { + + auto g = new TGraph(); + for (int i = 0; i < boards[board_nr].nrChannels; ++i) + { + g->SetPoint(i, i, boards[board_nr].data[i]); + } + g->Draw(); + + return g; + } + + int nrChannels() + { + int result = 0; + for (int board_nr = 0; board_nr < nrBoards; board_nr++) + result += boards[board_nr].nrChannels; + return result; + }; + + signed short &operator[](int index) + { + for (int board_nr = 0; board_nr < nrBoards; board_nr++) + { + if (index >= boards[board_nr].nrChannels) + index -= boards[board_nr].nrChannels; + else + return boards[board_nr][index]; + } + + std::cerr << " ### Fullframe::operator[]: index out of range!" << std::endl; + // return (*NULL); //this will cause crash (intended). + return boards[nrBoards][index]; + }; + + int nrBoards; + Boardframe *boards; +}; + +//*********************** Hitdata ************************* + +class Hitdata +{ +public: + Hitdata(int nr_frames = 0) + { + frames = NULL; + resize(nr_frames); + }; + + Hitdata(const Hitdata &in) + { + frames = NULL; + resize(in.nrFrames); + for (int i = 0; i < nrFrames; i++) + frames[i] = in.frames[i]; + }; + + Hitdata &operator=(const Hitdata &in) + { + resize(in.nrFrames); + for (int i = 0; i < nrFrames; i++) + frames[i] = in.frames[i]; + + return *this; + }; + + ~Hitdata() + { + if (nrFrames) + delete[] frames; + }; + + void resize(int nr_frames) + { + if (nrFrames) + delete[] frames; + nrFrames = nr_frames; + if (nrFrames) + frames = new Fullframe[nrFrames]; + else + frames = NULL; + }; + + // Read data from a given file. + // first_frame is the number of first frame to be read + // nr_frames is the maximum number of frames to be read + //-1 to read all of them + // increment allows you reading once every nth sample + // Return number of frames read or 0 in case of failure + int readFile(char *filename, int first_frame = 0, int nr_frames = -1, int increment = 1) + { + std::ifstream file; + // Open the file + file.open(filename, ios_base::in | ios_base::binary); + if (!file.is_open()) + { + std::cerr << " ### Hitdata: File could not be open!" << std::endl; + return 1; // file could not be opened + } + + // Read first record to find board configuration + Fullframe sampleframe; + if (sampleframe.read(&file) == 1) + { + std::cerr << " ### Hitdata: First frame could not be read!" << std::endl; + file.close(); + return 1; + } + + // Check file size + file.seekg(0, std::ios::beg); + std::streamsize fsize = file.tellg(); + file.seekg(0, std::ios::end); + fsize = file.tellg() - fsize; + + // Determine real frames to read + unsigned int max_frames = (fsize / sampleframe.sizeInFile() - first_frame) / increment; + if ((nr_frames == -1) || (max_frames < nr_frames)) + nr_frames = max_frames; + + std::cout << " Hitdata: Nr frames to be read: " << nr_frames << std::endl; + + // Read! + resize(nr_frames); // make an array called frames of size nr_frames #####!!!! + file.seekg(first_frame * sampleframe.sizeInFile(), std::ios::beg); + for (long int frame_nr = 0; frame_nr < nr_frames; frame_nr++) + { + /* if ((frame_nr%100) == 0) + std::cout << " Frame " << frame_nr << std::endl;*/ + + file.seekg((first_frame + frame_nr * increment) * sampleframe.sizeInFile(), std::ios::beg); + if (frames[frame_nr].read(&file) == 1) // read the next frame + { + std::cerr << " ### Hitdata: Frame " << frame_nr << " could not be read!" << std::endl; + file.close(); // read error, finish! + // frames = frame_nr; //Kinky! We decrease nr_frames, but the actual array size remains unchanged! + ///???? I don't know what the above line does. + return frame_nr; + } + // std::cout << frames[frame_nr].nrBoards << std::endl; + } + + // Finished + file.close(); + return nr_frames; + }; + + Fullframe &operator[](int index) + { + if (index < nrFrames) + return frames[index]; + else + { + std::cerr << " ### Hitdata::operator[]: index out of range!" << std::endl; + // return (*NULL); //this will cause crash (intended). + return frames[index]; + } + }; + + int nrFrames; + Fullframe *frames; +};