77 lines
3.1 KiB
Coq
77 lines
3.1 KiB
Coq
|
// megafunction wizard: %ALTSQRT%VBB%
|
||
|
|
// GENERATION: STANDARD
|
||
|
|
// VERSION: WM1.0
|
||
|
|
// MODULE: ALTSQRT
|
||
|
|
|
||
|
|
// ============================================================
|
||
|
|
// File Name: sqrt.v
|
||
|
|
// Megafunction Name(s):
|
||
|
|
// ALTSQRT
|
||
|
|
//
|
||
|
|
// Simulation Library Files(s):
|
||
|
|
// altera_mf
|
||
|
|
// ============================================================
|
||
|
|
// ************************************************************
|
||
|
|
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||
|
|
//
|
||
|
|
// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||
|
|
// ************************************************************
|
||
|
|
|
||
|
|
//Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||
|
|
//Your use of Intel Corporation's design tools, logic functions
|
||
|
|
//and other software and tools, and any partner logic
|
||
|
|
//functions, and any output files from any of the foregoing
|
||
|
|
//(including device programming or simulation files), and any
|
||
|
|
//associated documentation or information are expressly subject
|
||
|
|
//to the terms and conditions of the Intel Program License
|
||
|
|
//Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||
|
|
//the Intel FPGA IP License Agreement, or other applicable license
|
||
|
|
//agreement, including, without limitation, that your use is for
|
||
|
|
//the sole purpose of programming logic devices manufactured by
|
||
|
|
//Intel and sold by Intel or its authorized distributors. Please
|
||
|
|
//refer to the applicable agreement for further details, at
|
||
|
|
//https://fpgasoftware.intel.com/eula.
|
||
|
|
|
||
|
|
module sqrt (
|
||
|
|
clk,
|
||
|
|
ena,
|
||
|
|
radical,
|
||
|
|
q,
|
||
|
|
remainder);
|
||
|
|
|
||
|
|
input clk;
|
||
|
|
input ena;
|
||
|
|
input [25:0] radical;
|
||
|
|
output [12:0] q;
|
||
|
|
output [13:0] remainder;
|
||
|
|
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
// ============================================================
|
||
|
|
// CNX file retrieval info
|
||
|
|
// ============================================================
|
||
|
|
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
|
||
|
|
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||
|
|
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||
|
|
// Retrieval info: CONSTANT: PIPELINE NUMERIC "13"
|
||
|
|
// Retrieval info: CONSTANT: Q_PORT_WIDTH NUMERIC "13"
|
||
|
|
// Retrieval info: CONSTANT: R_PORT_WIDTH NUMERIC "14"
|
||
|
|
// Retrieval info: CONSTANT: WIDTH NUMERIC "26"
|
||
|
|
// Retrieval info: USED_PORT: clk 0 0 0 0 INPUT NODEFVAL "clk"
|
||
|
|
// Retrieval info: USED_PORT: ena 0 0 0 0 INPUT NODEFVAL "ena"
|
||
|
|
// Retrieval info: USED_PORT: q 0 0 13 0 OUTPUT NODEFVAL "q[12..0]"
|
||
|
|
// Retrieval info: USED_PORT: radical 0 0 26 0 INPUT NODEFVAL "radical[25..0]"
|
||
|
|
// Retrieval info: USED_PORT: remainder 0 0 14 0 OUTPUT NODEFVAL "remainder[13..0]"
|
||
|
|
// Retrieval info: CONNECT: @clk 0 0 0 0 clk 0 0 0 0
|
||
|
|
// Retrieval info: CONNECT: @ena 0 0 0 0 ena 0 0 0 0
|
||
|
|
// Retrieval info: CONNECT: @radical 0 0 26 0 radical 0 0 26 0
|
||
|
|
// Retrieval info: CONNECT: q 0 0 13 0 @q 0 0 13 0
|
||
|
|
// Retrieval info: CONNECT: remainder 0 0 14 0 @remainder 0 0 14 0
|
||
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.v TRUE
|
||
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.inc FALSE
|
||
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.cmp FALSE
|
||
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.bsf FALSE
|
||
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_inst.v TRUE
|
||
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_bb.v TRUE
|
||
|
|
// Retrieval info: LIB_FILE: altera_mf
|