139 lines
5.6 KiB
Coq
139 lines
5.6 KiB
Coq
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//module sensor_algo
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//combine sensor_interface bkg_subtraction, cluster_locate, and calibration, and rms
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module sensor_algo(
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//Clock/reset
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input wire clk_clk, // clk.clk
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input wire rst_reset, // rst.reset
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//Avalon MM slave
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input wire [1:0] csr_address, // avalon_slave.address
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input wire csr_read, // .read
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output wire [31:0] csr_readdata, // .readdata
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input wire csr_write, // .write
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input wire [31:0] csr_writedata, // .writedata
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input wire [3:0] csr_byteenable, // .byteenable
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//Avalon ST transmitter
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output wire [31:0] data_out_data, // avalon_streaming_source.data
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output wire data_out_endofpacket, // .endofpacket
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output wire data_out_startofpacket, // .startofpacket
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input wire data_out_ready, // .ready
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output wire data_out_valid, // .valid
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output wire [1:0] data_out_empty, // .empty
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//Sensor interface
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input wire in_trg, // sensor.in_trg // This is the frame timer
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output wire out_adc_clk, // .out_dac_clk
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output wire out_adc_cnv, // .out_dac_cnv
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input wire [4:0] in_adc_data, // .in_dac_data
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output wire out_sensor_rst, // .out_sensor_rst
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output wire out_sensor_clk, // .out_sensor_clk
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output wire out_sensor_gain, // .out_sensor_gain
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//Serial synchro interface
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input wire serial_rx, //receive data
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output wire serial_tx, //send data
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input wire [7:0] ext_input, //SMA etc.
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//Debug information
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output wire [7:0] status_out, //status bits - same as in reg0_read[15:8]
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//the interface with cali_ram (storing cali factor) Avalon-MM: read califac from this ram; output is not registered
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output wire [8:0] address,
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output wire clken,
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input wire [15:0] cali_fac,
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input wire waitrequest
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);
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wire [31:0] data_out_data1; // Output data
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wire data_out_endofpacket1; // Output end-of-packet signal
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wire data_out_startofpacket1; // Output start-of-packet signal
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wire data_out_ready1; // Output ready signal
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wire data_out_valid1; // Output valid signal
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wire [1:0] data_out_empty1; // Output empty signal
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wire int_rst;
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wire [7:0] cluster_threshold;
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wire [7:0] cluster_size;
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wire [7:0] in_algo_threshold;
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sensor_interface the_sensor_interface (
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.clk_clk (clk_clk), // clk.clk
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.rst_reset (rst_reset), // rst.reset
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.csr_address (csr_address), // csr.address
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.csr_write (csr_write), // .write
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.csr_writedata (csr_writedata), // .writedata
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.csr_byteenable (csr_byteenable), // .byteenable
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.csr_read (csr_read), // .read
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.csr_readdata (csr_readdata), // .readdata
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.data_out_data (data_out_data1), // data_out.data
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.data_out_empty (data_out_empty1), // .empty
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.data_out_endofpacket (data_out_endofpacket1), // .endofpacket
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.data_out_startofpacket (data_out_startofpacket1),// .startofpacket
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.data_out_ready (data_out_ready1), // .ready
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.data_out_valid (data_out_valid1), // .valid
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.in_trg (in_trg), // sensor.in_trg
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.out_adc_clk (out_adc_clk), // .out_dac_clk
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.out_adc_cnv (out_adc_cnv), // .out_dac_cnv
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.in_adc_data (in_adc_data), // .in_dac_data
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.out_sensor_rst (out_sensor_rst), // .out_sensor_rst
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.out_sensor_clk (out_sensor_clk), // .out_sensor_clk
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.out_sensor_gain (out_sensor_gain), // .out_sensor_gain
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.serial_rx (serial_rx), //receive data
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.serial_tx (serial_tx), //send data
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.ext_input (ext_input), //SMA etc.
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.int_rst (int_rst),
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.cluster_threshold (cluster_threshold),
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.cluster_size (cluster_size),
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.in_algo_threshold (in_algo_threshold)
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);
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algo_top_cl_cali_rms recon(
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.clk (clk_clk),
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.rst (int_rst),
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.data_in_data (data_out_data1),
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.data_in_ready (data_out_ready1),
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.data_in_valid (data_out_valid1),
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.data_in_empty (data_out_empty1),
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.data_in_startofpacket (data_out_startofpacket1),
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.data_in_endofpacket (data_out_endofpacket1),
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.CL_THRESHOLD (cluster_threshold),
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.CL_SIZE (cluster_size),
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.IN_ALGO_THRESHOLD (in_algo_threshold),
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.address (address),
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.clken (clken),
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.cali_fac (cali_fac),
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.waitrequest(waitrequest),
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.to_udp_data (data_out_data),
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.to_udp_ready(data_out_ready),
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.to_udp_valid (data_out_valid),
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.to_udp_empty (data_out_empty),
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.to_udp_endofpacket (data_out_endofpacket),
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.to_udp_startofpacket (data_out_startofpacket)
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);
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endmodule
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