39 lines
1.6 KiB
Plaintext
39 lines
1.6 KiB
Plaintext
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2019 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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*/
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(header "symbol" (version "1.1"))
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(symbol
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(rect 0 0 96 64)
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(text "sensor_algo" (rect 13 -1 61 11)(font "Arial" (font_size 10)))
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(text "inst" (rect 8 48 20 60)(font "Arial" ))
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(drawing
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(text " system " (rect 45 48 138 106)(font "Arial" ))
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(line (pt 16 32)(pt 80 32)(line_width 1))
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(line (pt 80 32)(pt 80 48)(line_width 1))
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(line (pt 16 48)(pt 80 48)(line_width 1))
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(line (pt 16 32)(pt 16 48)(line_width 1))
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(line (pt 0 0)(pt 97 0)(line_width 1))
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(line (pt 97 0)(pt 97 64)(line_width 1))
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(line (pt 0 64)(pt 97 64)(line_width 1))
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(line (pt 0 0)(pt 0 64)(line_width 1))
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)
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)
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