57 lines
1000 B
Coq
57 lines
1000 B
Coq
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// Signal debouncer
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`timescale 100 ps / 100 ps
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module debouncer (
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input wire rst, //reset
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input wire clk, //clock
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input wire in, //signal input
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output wire out //signal output
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);
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parameter LENGTH=8;
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integer i;
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reg [LENGTH-1:0] queue; //State of the state machine
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reg reg_out;
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wire all_low;
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wire all_high;
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//Little helpers
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assign all_low = ~(|queue);
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assign all_high = &queue;
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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begin
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queue[LENGTH-1:0] <= 0;
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reg_out <= 0;
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end
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else
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begin
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queue[LENGTH-2:0] <= queue[LENGTH-1:1];
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queue[LENGTH-1] <= in;
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//change the output state only if all the queue has a correct state
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case (reg_out)
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0:
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begin
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if (all_high)
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reg_out <= 1;
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end
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1:
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begin
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if (all_low)
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reg_out <= 0;
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end
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endcase
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end
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end
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//Assign output
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assign out = reg_out;
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endmodule
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