81 lines
1.9 KiB
Coq
81 lines
1.9 KiB
Coq
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//a module bridge the avalon streaming interface and avalon memory map interface
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//collect data from interface and write to RAM
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//long to short
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//32 bits to 16 bits
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module st2mm_l2s(
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//clock and reset
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input wire clk,
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input wire rst,
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//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence
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input wire [31:0] st_data, // st.data
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output wire st_ready, // .ready
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input wire st_valid, // .valid
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input wire [1:0] st_empty, // .empty
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input wire st_endofpacket, // .endofpacket
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input wire st_startofpacket, // .startofpacket
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//avalon MM(Memory Mapped) source
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output wire [8:0] mm_address,
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output wire mm_chipselect, // only for write
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output wire mm_clken, //only for write; write enable
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input wire [31:0]mm_readdate, //do not read
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output wire mm_write,
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output wire [8:0] mm_writedata
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);
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reg[1:0] state;
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localparam STATE_IDLE = 2'd0; //waiting for startofpacket
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localparam STATE_WRITE = 2'd1; //write to mm
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localparam STATE_LOCK = 2'd3; //Finish writing
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reg[8:0] ctr; // count data and the address for MM
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localparam CTR_ZERO = 9'd0;
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assign mm_address = ctr;
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assign mm_writedata = st_data;
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assign mm_chipselect = (state == STATE_WRITE && st_valid)? 1'b1: 1'b0;
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assign mm_clken = (state == STATE_WRITE && st_valid)? 1'b1: 1'b0;
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assign st_ready = (state == STATE_WRITE)? 1'b1: 1'b0;
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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begin
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state <= STATE_IDLE;
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ctr <= CTR_ZERO;
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end
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else case(state)
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STATE_IDLE:
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begin
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ctr <= CTR_ZERO;
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if (st_startofpacket)
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state <= STATE_WRITE;
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end
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STATE_WRITE:
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begin
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if (st_valid)
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ctr <= ctr + 1'b1;
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if (st_endofpacket)
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state <= STATE_LOCK;
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end
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STATE_LOCK:
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begin
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state <= STATE_IDLE;
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ctr <= CTR_ZERO;
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end
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default:
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state <= STATE_IDLE;
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endcase
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end
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endmodule
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