397 lines
12 KiB
Coq
397 lines
12 KiB
Coq
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// UDP generator
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/*
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Takes an input stream and generates a valid UDP/IPv4 packet, then outputs it as a stream which can be directly connected to TSE.
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Remarks:
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- Both input and output are Avalon ST ports, 8-bit symbol, 4 symbols per beat
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- Start/end of packet signals are REQUIRED.
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- Empty signals are discarded. An incoming packet should have a length of 4N. If not, it will be padded with what's on the bus.
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- Backpressure is supported and actively used during transfer. Data source must be backpressurizable.
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- The transfer is performed on the fly, without buffering. Input gets backpressed for the time of sending headers.
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- Size of payload must be known in advance and programmed over Avalon MM interface.
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- Longer packets will be cut. Shorter packets will be padded with zeros.
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- UDP checksum is not calculated (the price of realtime approach) and filled with zeros. IP header checksum is calculated.
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- The Programming interface is an Avalon MM. It's 32-bit wide and allows byte, halfword and word operations. Block transfers are not supported.
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- Source MAC is not programmable; it must be filled by TSE.
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- Two leading zero bytes are added on front of the packet for 32-bit alignment. TSE settings must comply wit this.
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- If transfer is disabled (see control bits), the input will be backpressed all the time.
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- Maximum transfer size is about 64K, but limitations of the Ethernet must be taken into account.
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- The IPv4 header has the 'Don't fragment' flag set.
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Register map: (byte offsets are given)
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UDPGEN_REG_CSR 0 //16 bits 8 bits control(LSB) + 8 bits status(MSB)
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UDPGEN_REG_SIZE 2 //16 bits payload size in words
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UDPGEN_REG_SRCIP 4 //32 bits source IP, last octet first
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UDPGEN_REG_DSTIP 8 //32 bits destination IP. last octet first
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UDPGEN_REG_DSTPORT 12 //16 bits destination port
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UDPGEN_REG_SRCPORT 14 //16 bits source port
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UDPGEN_REG_DSTMAC 16 //2*32 bits destination MAC, last octet first
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UDPGEN_REG_RES1 24 //32 bits reserved
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UDPGEN_REG_RES2 28 //32 bits reserved
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Control bits:
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0: transfer enable
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1-7: unused
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Status bits:
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0-3: state of the machine
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7-4: unused
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*/
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`timescale 100 ps / 100 ps
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module udp_generator (
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input wire clk_clk, // clk.clk
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input wire rst_reset, // rst.reset
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input wire [2:0] csr_address, // csr.address
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input wire csr_write, // .write
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input wire [31:0] csr_writedata, // .writedata
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input wire [3:0] csr_byteenable, // .byteenable
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input wire csr_read, // .read
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output wire [31:0] csr_readdata, // .readdata
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input wire [31:0] data_in_data, // data_in.data
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output wire data_in_ready, // .ready
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input wire data_in_valid, // .valid
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input wire [1:0] data_in_empty, // .empty
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input wire data_in_endofpacket, // .endofpacket
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input wire data_in_startofpacket, // .startofpacket
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output wire [31:0] data_out_data, // data_out.data
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output wire [1:0] data_out_empty, // .empty
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output wire data_out_endofpacket, // .endofpacket
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output wire data_out_startofpacket, // .startofpacket
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input wire data_out_ready, // .ready
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output wire data_out_valid // .valid
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);
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// *********************** CSR stuff ************************
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reg [31:0] registers[7:0]; //main register space
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wire [31:0] reg0_read; //reg[0] is read indirectly to include status byt(bits 15-8)
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//read logic
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assign reg0_read[7:0] = registers[0][7:0]; // Readback of control bits
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assign reg0_read[31:16] = registers[0][31:16]; // Readback of payload size
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assign reg0_read[15:12] = 0; // Unused bits of the status byte
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assign csr_readdata = (csr_address==0) ? reg0_read : registers[csr_address];
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//write logic
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genvar i;
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genvar j;
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generate
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for (i = 0; i < 8; i = i+1)
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begin : write_registers //Quartus wants labels for 'for' blocks
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for (j = 0; j < 4; j = j+1)
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begin : write_bytes
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always @(posedge clk_clk or posedge rst_reset)
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begin
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if (rst_reset)
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registers[i][8*j+7:8*j] <= 8'd0;
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else
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if (csr_byteenable[j] && (csr_address == i) && (csr_write))
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registers[i][8*j+7:8*j] <= csr_writedata[8*j+7:8*j];
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end
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end
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end
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endgenerate
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// *********************** ST interface ***********************
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reg [4:0] state; //State of the state machine
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localparam STATE_IDLE = 0; //waiting for SOP
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localparam STATE_MAC1 = 1; //sending first word of MAC header: 00 00 dest_mac[5:4]
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localparam STATE_MAC2 = 2; //sending second word of MAC header: dest_mac[3:0]
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localparam STATE_MAC3 = 3; //sending zeroes as source MAC msbs: 00 00 00 00
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localparam STATE_MAC4 = 4; //sending zeroes as source MAC lsbs & packet type: 00 00 08 00
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localparam STATE_IP1 = 5; //sending IP ver & header size, DSF, total length 45 00 length[1:0]
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localparam STATE_IP2 = 6; //sending IP id, flags (don't fragment), fragm. offset=0 ip_id[1:0] 40 00
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localparam STATE_IP3 = 7; //sending TTL, protocol, header checksum 80 11 checksum[1:0]
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localparam STATE_IP4 = 8; //sending source IP src_ip[4:0]
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localparam STATE_IP5 = 9; //sending destination IP dst_ip[4:0]
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localparam STATE_UDP1 = 10; //sending src & dest port src_port[1:0] dst_port[1:0]
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localparam STATE_UDP2 = 11; //sending UDP frame length and (unused) checksum udp_length[1:0] 00 00
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localparam STATE_DATA = 12; //sending packet data but the last word
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localparam STATE_PAD = 13; //padding packet with zeros if incoming packet was too short
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localparam STATE_DUMP = 14; //dumping tail of incoming packet if it was too long
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localparam STATE_END = 15; //transfer finished, just wait one cycle
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reg reg_ready; //registers to drive output pins of ST interfaces
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reg reg_valid;
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reg [31:0] reg_data;
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reg reg_startofpacket;
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reg reg_endofpacket;
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reg reg_empty;
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//Helper stuff
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wire [15:0] udp_length;
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wire [15:0] total_length;
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wire [19:0] int_checksum;
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wire [16:0] int_checksum2;
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wire [15:0] header_checksum;
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reg [15:0] ip_id; //unique identifier of a packet
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reg [15:0] tx_ctr; //counter of sent data words
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assign reg0_read[11:8] = state; //state forwarded to status register
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assign udp_length = 4*registers[0][31:16] + 16'd8;
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assign total_length = 4*registers[0][31:16] + 16'd28;
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assign int_checksum = 20'h10511 + total_length + ip_id + registers[1][31:16] + registers[1][15:0] + registers[2][31:16] + registers[2][15:0];
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assign int_checksum2 = int_checksum[15:0] + int_checksum[19:16];
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assign header_checksum = ~(int_checksum2[15:0] + int_checksum2[16]);
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//The state machine
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always @(posedge clk_clk or posedge rst_reset)
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begin
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if (rst_reset)
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begin
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state <= STATE_IDLE;
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ip_id<= 0;
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end
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else
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case(state)
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STATE_IDLE:
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begin
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if (data_in_startofpacket && registers[0][0])
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begin
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state <= STATE_MAC1;
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ip_id <= ip_id+1;
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tx_ctr <= 1;
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end
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end
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STATE_MAC1, STATE_MAC2, STATE_MAC3, STATE_MAC4, STATE_IP1, STATE_IP2, STATE_IP3, STATE_IP4, STATE_IP5, STATE_UDP1, STATE_UDP2:
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begin
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if (data_out_ready)
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state <= state + 1;
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end
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STATE_DATA:
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begin
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if (data_out_ready && data_in_valid)
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begin
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tx_ctr <= tx_ctr+1;
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if ((tx_ctr == registers[0][31:16]) && data_in_endofpacket) //last word, size matches
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state <= STATE_END;
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else if (data_in_endofpacket) //packet too short
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state <= STATE_PAD;
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else if (tx_ctr == registers[0][31:16]) //packet too long
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state <= STATE_DUMP;
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end
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end
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STATE_PAD:
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begin
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if (data_out_ready)
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begin
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tx_ctr <= tx_ctr+1;
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if (tx_ctr == registers[0][31:16])
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state <= STATE_END;
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end
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end
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STATE_DUMP:
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begin
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if (data_out_ready && data_in_valid)
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begin
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if (data_in_endofpacket)
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state <= STATE_END;
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end
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end
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default:
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begin
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state <= STATE_IDLE;
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end
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endcase
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end
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//Driving bus signals
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always @( * )
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begin
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if (rst_reset)
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begin
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reg_ready = 0;
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reg_valid = 0;
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reg_data = 0;
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reg_startofpacket = 0;
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reg_endofpacket = 0;
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reg_empty = 0;
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end
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else
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case(state)
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STATE_IDLE:
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begin
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reg_ready = 0;
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reg_valid = 0;
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reg_data = 0;
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reg_startofpacket = 0;
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reg_endofpacket = 0;
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reg_empty = 0;
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end
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STATE_MAC1:
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begin
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reg_ready = 0;
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reg_valid = 1;
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reg_data[31:16] = 0;
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reg_data[15:0] = registers[5][15:0];
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reg_startofpacket = 1;
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reg_endofpacket = 0;
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reg_empty = 0;
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end
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STATE_MAC2:
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begin
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reg_ready = 0;
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reg_valid = 1;
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reg_data = registers[4];
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reg_startofpacket = 0;
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reg_endofpacket = 0;
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reg_empty = 0;
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end
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STATE_MAC3:
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begin
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reg_ready = 0;
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reg_valid = 1;
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reg_data = 32'h00000000;
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reg_startofpacket = 0;
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reg_endofpacket = 0;
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reg_empty = 0;
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end
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STATE_MAC4:
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begin
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reg_ready = 0;
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reg_valid = 1;
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reg_data = 32'h00000800;
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reg_startofpacket = 0;
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reg_endofpacket = 0;
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reg_empty = 0;
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end
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STATE_IP1:
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begin
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reg_ready = 0;
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reg_valid = 1;
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reg_data[31:16] = 16'h4500;
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reg_data[15:0] = total_length;
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reg_startofpacket = 0;
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reg_endofpacket = 0;
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reg_empty = 0;
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end
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STATE_IP2:
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begin
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reg_ready = 0;
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reg_valid = 1;
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reg_data[31:16] = ip_id;
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reg_data[15:0] = 16'h4000;
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reg_startofpacket = 0;
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reg_endofpacket = 0;
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reg_empty = 0;
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end
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STATE_IP3:
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begin
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reg_ready = 0;
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reg_valid = 1;
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reg_data[31:16] = 16'h8011;
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reg_data[15:0] = header_checksum;
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reg_startofpacket = 0;
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reg_endofpacket = 0;
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reg_empty = 0;
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end
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STATE_IP4:
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begin
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reg_ready = 0;
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reg_valid = 1;
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reg_data = registers[1];
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reg_startofpacket = 0;
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reg_endofpacket = 0;
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reg_empty = 0;
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end
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STATE_IP5:
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begin
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reg_ready = 0;
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reg_valid = 1;
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reg_data = registers[2];
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reg_startofpacket = 0;
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reg_endofpacket = 0;
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reg_empty = 0;
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end
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STATE_UDP1:
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begin
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reg_ready = 0;
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reg_valid = 1;
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reg_data = registers[3];
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reg_startofpacket = 0;
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reg_endofpacket = 0;
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reg_empty = 0;
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end
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STATE_UDP2:
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begin
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reg_ready = 0;
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reg_valid = 1;
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reg_data[31:16] = udp_length;
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reg_data[15:0] = 16'h0000;
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reg_startofpacket = 0;
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reg_endofpacket = 0;
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reg_empty = 0;
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end
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STATE_DATA:
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begin
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reg_ready = data_out_ready;
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reg_valid = data_in_valid;
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reg_data = data_in_data;
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reg_startofpacket = 0;
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if (tx_ctr == registers[0][31:16])
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reg_endofpacket = 1;
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else
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reg_endofpacket = 0;
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reg_empty = 0;
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end
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STATE_PAD:
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begin
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reg_ready = 0;
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reg_valid = 1;
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reg_data = 32'h0;
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reg_startofpacket = 0;
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if (tx_ctr == registers[0][31:16])
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reg_endofpacket = 1;
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else
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reg_endofpacket = 0;
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reg_empty = 0;
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end
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STATE_DUMP:
|
||
|
|
begin
|
||
|
|
reg_ready = 1;
|
||
|
|
reg_valid = 0;
|
||
|
|
reg_data = 0;
|
||
|
|
reg_startofpacket = 0;
|
||
|
|
reg_endofpacket = 0;
|
||
|
|
reg_empty = 0;
|
||
|
|
end
|
||
|
|
STATE_END:
|
||
|
|
begin
|
||
|
|
reg_ready = 0;
|
||
|
|
reg_valid = 0;
|
||
|
|
reg_data = 0;
|
||
|
|
reg_startofpacket = 0;
|
||
|
|
reg_endofpacket = 0;
|
||
|
|
reg_empty = 0;
|
||
|
|
end
|
||
|
|
default:
|
||
|
|
begin
|
||
|
|
reg_ready = 0;
|
||
|
|
reg_valid = 0;
|
||
|
|
reg_data = 0;
|
||
|
|
reg_startofpacket = 0;
|
||
|
|
reg_endofpacket = 0;
|
||
|
|
reg_empty = 0;
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
|
||
|
|
assign data_in_ready = reg_ready;
|
||
|
|
assign data_out_valid = reg_valid;
|
||
|
|
assign data_out_data = reg_data;
|
||
|
|
assign data_out_startofpacket = reg_startofpacket;
|
||
|
|
assign data_out_endofpacket = reg_endofpacket;
|
||
|
|
assign data_out_empty = reg_empty;
|
||
|
|
|
||
|
|
endmodule
|