2024-10-15 16:39:23 +02:00
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/******************************************************************************
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* Copyright *
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* Scintillating Fibre Beam Profile Monitor Software by Michal Dziewiecki, *
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* Blake Leverington and Liqing Qin is licensed under CC BY 4.0 *
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* https://creativecommons.org/licenses/by/4.0/ *
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* funded by the Deutsche Forschungsgemeinschaft *
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* (DFG, German Research Foundation) Projektnummer 419255448 *
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* Project Leader: B.Leverington *
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*******************************************************************************
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* Create Date - 2019 *
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* Author: M.Dziewiecki *
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* Module - m10_rgmii.v *
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* Edited by L.Qin on Oct 15. 2024 for reconstruction *
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******************************************************************************/
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2024-10-15 11:25:38 +02:00
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2024-10-11 14:42:06 +02:00
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module m10_rgmii (
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//Clock and Reset
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input wire clk_50_max10,
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input wire fpga_resetn,
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//LED PB DIPSW
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output wire [4:0] user_led,
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input wire [3:0] user_pb,
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input wire [4:0] user_dipsw,
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//Dual Ethernet
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output wire enet_mdc,
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inout wire enet_mdio,
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output wire enet_resetn,
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input wire enet_rx_clk,
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input wire enet_tx_clk,
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output wire enet_gtx_clk,
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input wire [3:0] enet_rx_d,
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output wire [3:0] enet_tx_d,
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output wire enet_tx_en,
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input wire enet_rx_dv,
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input wire enet_led_link100,
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input wire ddr3_ram_pll_ref_clk_clk, // ddr3_ram_pll_ref_clk.clk
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output wire [13:0] mem_a,
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output wire [2:0] mem_ba,
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inout wire [0:0] mem_ck,
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inout wire [0:0] mem_ck_n,
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output wire [0:0] mem_cke,
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output wire [0:0] mem_cs_n,
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output wire [0:0] mem_dm,
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output wire [0:0] mem_ras_n,
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output wire [0:0] mem_cas_n,
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output wire [0:0] mem_we_n,
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output wire mem_reset_n,
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inout wire [7:0] mem_dq,
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inout wire [0:0] mem_dqs,
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inout wire [0:0] mem_dqs_n,
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output wire [0:0] mem_odt,
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//QSPI
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output qspi_clk,
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inout [3:0] qspi_io,
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output qspi_csn,
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//Sensors
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output wire [1:0] sensor_reset,
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output wire [1:0] sensor_clk,
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input wire [4:0] sensor_trig,
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output wire [1:0] adc_cnv,
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output wire [1:0] adc_sck,
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input wire [4:0] adc_sdo,
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output wire sensor_gainp,
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output wire sensor_gainn,
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//Synchro
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input wire [3:0] link_rx,
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output wire [3:0] link_tx,
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output wire [3:0] link_dir,
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//PMOD
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input wire [7:0] pmoda, //used for 8-fold SMA input;)
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output wire [7:0] pmodb,
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//USB UART
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output wire debug_txd,
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input wire debug_rxd
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);
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//*********************************** Signals *************************************
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//Heart-beat counter
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reg [25:0] heart_beat_cnt;
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//DDR3 interface assignments
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wire local_init_done;
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wire local_cal_success;
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wire local_cal_fail;
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//Ethernet interface assignments
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wire phy_resetn;
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wire system_resetn;
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wire mdio_oen_from_the_tse_mac;
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wire mdio_out_from_the_tse_mac;
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wire eth_mode_from_the_tse_mac;
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wire ena_10_from_the_tse_mac;
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wire enet_tx_125;
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wire enet_tx_25;
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wire enet_tx_2p5;
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wire locked_from_the_enet_pll;
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wire tx_clk_to_the_tse_mac;
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wire tx_clk_to_the_tse_mac_g;
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wire enet_tx_125_shift;
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wire enet_tx_25_shift;
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wire enet_tx_2p5_shift;
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wire enet_tx_250_shift; // signaltap sample clock
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wire locked_from_the_shift_pll;
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wire tx_clk_to_the_tse_mac_shift;
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wire tx_clk_to_the_tse_mac_shift_g;
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//User interface ;)
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wire [8:0] user_input;
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wire [7:0] int_output;
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//Sensor interface
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wire int_sensor_in_trg;
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wire int_sensor_out_adc_clk;
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wire int_sensor_out_adc_cnv;
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wire [4:0] int_sensor_in_adc_data;
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wire int_sensor_out_sensor_rst;
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wire int_sensor_out_sensor_clk;
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wire int_sensor_out_sensor_gain;
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wire [7:0] int_sensor_status;
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//Trigger stuff
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wire int_frame_timer;
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reg sym_frame_timer;
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//*********************************** Sensor connections *************************************
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assign sensor_reset[0] = int_sensor_out_sensor_rst;
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assign sensor_reset[1] = int_sensor_out_sensor_rst;
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assign sensor_clk[0] = ~int_sensor_out_sensor_clk;
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assign sensor_clk[1] = ~int_sensor_out_sensor_clk;
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assign sensor_gainp = int_sensor_out_sensor_gain;
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assign sensor_gainn = ~int_sensor_out_sensor_gain;
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assign adc_cnv[0] = int_sensor_out_adc_cnv;
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assign adc_cnv[1] = int_sensor_out_adc_cnv;
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assign adc_sck[0] = ~int_sensor_out_adc_clk;
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assign adc_sck[1] = ~int_sensor_out_adc_clk;
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assign int_sensor_in_adc_data = adc_sdo; //all of them are not-inverted :)
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//*********************************** Frame trigger & synchro routing (master/slave) *************************************
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//Synchro pulse is LINK3 (inverted)
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//Global counter transmission is LINK2 (inverted)
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wire trig_mode;
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assign trig_mode = int_output[7];
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wire int_synchro_rx;
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wire int_synchro_tx;
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wire int_trig_debouncer_in;
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wire int_ser_debouncer_in;
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//Pulse flip-flop
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always @(posedge int_frame_timer or negedge fpga_resetn)
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begin
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if (!fpga_resetn)
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sym_frame_timer <= 0;
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else if (trig_mode == 0)
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sym_frame_timer <= 0;
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else
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sym_frame_timer <= ~sym_frame_timer;
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end
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//Trigger Assignments
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assign link_dir[3] = trig_mode; //set link direction according to M/S setting (LED PIO 7)
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assign link_tx[3] = ~sym_frame_timer; //connect internal frame trigger to TX
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assign int_trig_debouncer_in = trig_mode ? sym_frame_timer : link_rx[3]; //connect either internal or external frame trigger
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//Debouncer for trigger signals - limit trigger bandwidth to 2.5 MHz
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debouncer #(
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.LENGTH (10)
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) trig_debouncer (
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.rst (!system_resetn),
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.clk (clk_50_max10),
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.in (int_trig_debouncer_in),
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.out (int_sensor_in_trg)
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);
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//Serial assignments
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assign link_dir[2] = trig_mode;
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assign int_ser_debouncer_in = trig_mode ? int_synchro_tx : link_rx[2];
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assign link_tx[2] = ~int_synchro_tx;
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//Debouncer for serial RX - limit bandwidth to 2.5 MHz
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debouncer #(
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.LENGTH (10)
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) ser_debouncer (
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.rst (!system_resetn),
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.clk (clk_50_max10),
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.in (int_ser_debouncer_in),
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.out (int_synchro_rx)
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);
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//*********************************** Various logic *************************************
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assign system_resetn = fpga_resetn & local_init_done;
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//PMOD debug lines
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assign pmodb[0] = int_trig_debouncer_in;
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assign pmodb[1] = int_sensor_in_trg;
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assign pmodb[7:2] = int_sensor_status[5:0];
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//Buttons/switches
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assign user_input[3:0] = user_pb[3:0];
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assign user_input[8:4] = user_dipsw[4:0];
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//LED forwarding
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assign user_led[3:0] = ~int_output[3:0];
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//disable user_led[4] blink with int_output[5]; force user_led[4] with int_output[4]
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assign user_led[4] = ~int_output[4] & (heart_beat_cnt[25] | int_output[5]);
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//int_output[6] is used for PHY hard reset
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//int_output[7] is used for master/slave frame trigger routing
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//Heart beat by 50MHz clock
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always @(posedge clk_50_max10 or negedge fpga_resetn)
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if (!fpga_resetn)
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heart_beat_cnt <= 26'h0; //0x3FFFFFF
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else
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heart_beat_cnt <= heart_beat_cnt + 1'b1;
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//*********************************** Ethernet *************************************
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//PHY power-on reset control
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parameter MSB = 20; // PHY interface: need minimum 10ms delay for POR
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reg [MSB:0] epcount;
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always @(posedge clk_50_max10 or negedge fpga_resetn)
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if (!fpga_resetn)
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epcount <= MSB + 1'b0;
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else if (epcount[MSB] == 1'b0)
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epcount <= epcount + 1;
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else
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epcount <= epcount;
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assign phy_resetn = user_pb[0] & !(int_output[6] & epcount[MSB]) & !epcount[MSB-1]; //PHY hard reset by counter, user button or software
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assign enet_resetn = phy_resetn;
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//MDIO output control
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assign enet_mdio = ( !mdio_oen_from_the_tse_mac ) ? ( mdio_out_from_the_tse_mac ) : ( 1'bz );
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assign enet_tx_2p5_shift = !enet_tx_2p5;
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//RGMII clock solution
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assign tx_clk_to_the_tse_mac = ( eth_mode_from_the_tse_mac ) ? ( enet_tx_125 ) : // GbE Mode = 125MHz clock
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( ena_10_from_the_tse_mac ) ? ( enet_tx_2p5 ) : // 10Mb Mode = 2.5MHz clock
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( enet_tx_25 ); // 100Mb Mode = 25MHz clock
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assign tx_clk_to_the_tse_mac_shift = ( eth_mode_from_the_tse_mac ) ? ( enet_tx_125_shift ) : // GbE Mode = 125MHz clock
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( ena_10_from_the_tse_mac ) ? ( enet_tx_2p5_shift ) : // 10Mb Mode = 2.5MHz clock
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( enet_tx_25_shift); // 100Mb Mode = 25MHz clock
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clkctrl clkctrl_inst0 (
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.inclk (tx_clk_to_the_tse_mac ),
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.outclk (tx_clk_to_the_tse_mac_g)
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);
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clkctrl clkctrl_inst1 (
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.inclk (tx_clk_to_the_tse_mac_shift ),
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.outclk (tx_clk_to_the_tse_mac_shift_g)
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);
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enet_gtx_clk_ddio enet_gtx_clk_ddio_inst (
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.outclock (tx_clk_to_the_tse_mac_shift_g), // tx_clk_to_the_tse_mac_g ),
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.din (2'b10 ),
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.pad_out (enet_gtx_clk ),
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.aclr (!phy_resetn )
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);
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//*********************************** Main QSYS *************************************
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q_sys q_sys_inst (
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.sys_clk_clk (clk_50_max10 ), // sys_clk.clk
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.reset_reset_n (system_resetn ), // reset.reset_n
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.mem_resetn_in_reset_reset_n (fpga_resetn ), // mem_resetn_in_reset.reset_n
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.altpll_shift_c0_clk (enet_tx_250_shift ), // altpll_shift_c0.clk
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.altpll_shift_locked_conduit_export (locked_from_the_shift_pll ), // altpll_shift_locked_conduit.export
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.clock_bridge_0_in_clk_clk (enet_tx_25 ), // clock_bridge_0_in_clk.clk
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.enet_pll_c0_clk (enet_tx_125 ), // enet_pll_c0.clk
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.enet_pll_c1_clk (enet_tx_25 ), // enet_pll_c1.clk
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.enet_pll_c2_clk (enet_tx_2p5 ), // enet_pll_c2.clk
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.enet_pll_c3_clk (enet_tx_125_shift ), // enet_pll_c3.clk
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.enet_pll_c4_clk (enet_tx_25_shift ), // enet_pll_c4.clk
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.enet_pll_locked_conduit_export (locked_from_the_enet_pll ), // enet_pll_locked_conduit.export
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.eth_tse_mac_mdio_connection_mdc (enet_mdc ), // eth_tse_mac_mdio_connection.mdc
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.eth_tse_mac_mdio_connection_mdio_in (enet_mdio ), // .mdio_in
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.eth_tse_mac_mdio_connection_mdio_out (mdio_out_from_the_tse_mac ), // .mdio_out
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.eth_tse_mac_mdio_connection_mdio_oen (mdio_oen_from_the_tse_mac ), // .mdio_oen
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.eth_tse_mac_rgmii_connection_rgmii_in (enet_rx_d ), // eth_tse_mac_rgmii_connection.rgmii_in
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.eth_tse_mac_rgmii_connection_rgmii_out (enet_tx_d ), // .rgmii_out
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.eth_tse_mac_rgmii_connection_rx_control (enet_rx_dv ), // .rx_control
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.eth_tse_mac_rgmii_connection_tx_control (enet_tx_en ), // .tx_control
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.eth_tse_mac_status_connection_set_10 ( ), // eth_tse_mac_status_connection.set_10
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.eth_tse_mac_status_connection_set_1000 ( ), // .set_1000
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.eth_tse_mac_status_connection_eth_mode (eth_mode_from_the_tse_mac ), // .eth_mode
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.eth_tse_mac_status_connection_ena_10 (ena_10_from_the_tse_mac ), // .ena_10
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.eth_tse_pcs_mac_rx_clock_connection_clk (enet_rx_clk ), // eth_tse_pcs_mac_rx_clock_connection.clk
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.eth_tse_pcs_mac_tx_clock_connection_clk (tx_clk_to_the_tse_mac_g ), // eth_tse_pcs_mac_tx_clock_connection.clk
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.ext_flash_flash_dataout_conduit_dataout (qspi_io ), // ext_flash_flash_dataout.conduit_dataout
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.ext_flash_flash_dclk_out_conduit_dclk_out (qspi_clk ), // ext_flash_flash_dclk_out.conduit_dclk_out
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.ext_flash_flash_ncs_conduit_ncs (qspi_csn ), // ext_flash_flash_ncs.conduit_ncs
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.ddr3_ram_pll_ref_clk_clk (ddr3_ram_pll_ref_clk_clk ),
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.memory_mem_a (mem_a ), // memory.mem_a
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.memory_mem_ba (mem_ba ), // .mem_ba
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.memory_mem_ck (mem_ck ), // .mem_ck
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.memory_mem_ck_n (mem_ck_n ), // .mem_ck_n
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.memory_mem_cke (mem_cke ), // .mem_cke
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.memory_mem_cs_n (mem_cs_n ), // .mem_cs_n
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.memory_mem_dm (mem_dm ), // .mem_dm
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.memory_mem_ras_n (mem_ras_n ), // .mem_ras_n
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.memory_mem_cas_n (mem_cas_n ), // .mem_cas_n
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.memory_mem_we_n (mem_we_n ), // .mem_we_n
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.memory_mem_reset_n (mem_reset_n ), // .mem_reset_n
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.memory_mem_dq (mem_dq ), // .mem_dq
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.memory_mem_dqs (mem_dqs ), // .mem_dqs
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.memory_mem_dqs_n (mem_dqs_n ), // .mem_dqs_n
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.memory_mem_odt (mem_odt ), // .mem_odt
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.led_pio_external_connection_export (int_output[7:0] ), // led_pio_external_connection.export
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.mem_if_ddr3_emif_0_status_local_init_done (local_init_done ), // mem_if_ddr3_emif_0_status.local_init_done
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.mem_if_ddr3_emif_0_status_local_cal_success (local_cal_success ), // .local_cal_success
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.mem_if_ddr3_emif_0_status_local_cal_fail (local_cal_fail ), // .local_cal_fail
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.button_pio_external_connection_export (user_input ), //
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.debug_uart_external_connection_rxd (debug_rxd ), //
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.debug_uart_external_connection_txd (debug_txd ), //
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.sensor_in_trg (int_sensor_in_trg ),
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.sensor_out_adc_clk (int_sensor_out_adc_clk ),
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.sensor_out_adc_cnv (int_sensor_out_adc_cnv ),
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.sensor_in_adc_data (int_sensor_in_adc_data ),
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.sensor_out_sensor_rst (int_sensor_out_sensor_rst ),
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.sensor_out_sensor_clk (int_sensor_out_sensor_clk ),
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.sensor_out_sensor_gain (int_sensor_out_sensor_gain),
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.frame_timer_export (int_frame_timer),
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.sensor_synchro_serial_rx (int_synchro_rx),// sensor_synchro.serial_rx
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.sensor_synchro_serial_tx (int_synchro_tx),// .serial_tx
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.sensor_synchro_ext_input (pmoda),
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.sensor_status_status_out (int_sensor_status)
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);
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endmodule
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