131 lines
2.8 KiB
Systemverilog
131 lines
2.8 KiB
Systemverilog
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/*
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The ram provides the background signal.
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when frameID is 1, reset ram content to 0
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frameID is 2~1+TOTAL_FRAME, sum the signal store in the ram
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when rameID is TOTAL_FRAME+2, output the background signal
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The TOTAL_FRAME has to be the power of 2, and it belongs to [2,65536]
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In general, TOTAL_FRAME = 8192
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*/
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module bkg_ram #(parameter TOTAL_FRAME = 4)
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(
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input wire clk_clk,
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input wire rst_reset,
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input wire enable,
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input wire[26:0] frameID,
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input wire [7:0] address,
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input wire [31:0] data_in_data,
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input wire data_in_valid,
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output wire [31:0] bkg_signal,
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output wire bkg_sub_status
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);
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wire wren;
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reg[7:0] wraddress_buffer; //delay address 3 clocks
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//reg[31:0] reg_data_in; //delay data_in_data 1 clocks
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wire[31:0] q_sig1; //output from ram
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wire[31:0] data_sig1; //write in the ram
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reg[31:0] reg_sum1;
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wire[31:0] q_sig2;
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wire[31:0] data_sig2;
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reg[31:0] reg_sum2;
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// localparam TOTAL_FRAME = 8192; //2^13= 8192
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// localparam SHIFG_BIT = 13;
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//for fast simulation
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//localparam TOTAL_FRAME = 4; //2^2= 4
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localparam SHIFT_BIT = $clog2(TOTAL_FRAME);
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ram4bkg ram4bkg1 (
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.data(data_sig1),
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.rdaddress(address),
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.clock(clk_clk),
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.wraddress(wraddress_buffer),
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.wren(wren),
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.q(q_sig1)
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);
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ram4bkg ram4bkg2 (
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.data(data_sig2),
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.rdaddress(address),
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.clock(clk_clk),
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.wraddress(wraddress_buffer),
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.wren(wren),
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.q(q_sig2)
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);
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reg[1:0] states;
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localparam STATE_IDLE = 0;
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localparam STATE_RAM_RST = 1;
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localparam STATE_BKG_ADD = 3;
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localparam STATE_BKG_OUT = 2;
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assign bkg_sub_status = (states==STATE_BKG_OUT)? 1'b1:1'b0;
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always @(posedge clk_clk or posedge rst_reset)
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begin
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if (rst_reset)
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states <= STATE_IDLE;
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else if (frameID <=27'd1)
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states <= STATE_RAM_RST;
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else if (frameID >TOTAL_FRAME+1)
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states <= STATE_BKG_OUT;
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else
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states <= STATE_BKG_ADD;
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end
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assign bkg_signal[31:16] = (states==STATE_BKG_OUT)?q_sig1[SHIFT_BIT+15:SHIFT_BIT]:16'b0;
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assign bkg_signal[15:0] = (states==STATE_BKG_OUT)?q_sig2[SHIFT_BIT+15:SHIFT_BIT]:16'b0;
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assign wren = (states==STATE_RAM_RST || states==STATE_BKG_ADD)? 1'b1: 1'b0;
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assign data_sig1 = (states==STATE_BKG_ADD)? reg_sum1: 0;
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assign data_sig2 = (states==STATE_BKG_ADD)? reg_sum2: 0;
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always @(posedge clk_clk or posedge rst_reset)
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begin
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if (rst_reset)
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begin
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reg_sum1 <= 0;
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//reg_data_in[1] <= 0;
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wraddress_buffer <= 0;
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reg_sum2 <= 0;
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end
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else
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case(states)
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STATE_IDLE:
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begin
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reg_sum1 <= 0;
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//reg_data_in[1] <= 0;
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reg_sum2 <= 0;
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end
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STATE_BKG_ADD:
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begin
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if (data_in_valid)
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begin
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//reg_data_in <= data_in_data;
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reg_sum1 <= q_sig1 + data_in_data[31:16];
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reg_sum2 <= q_sig2 + data_in_data[15:0];
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wraddress_buffer <= address;
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end
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end
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STATE_RAM_RST:
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wraddress_buffer[0] <= address;
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endcase
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end
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endmodule
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