HITDAQ/FPGA_firmware/clkctrl/synthesis/clkctrl.v

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2024-10-11 14:42:06 +02:00
// clkctrl.v
// Generated using ACDS version 19.1 670
`timescale 1 ps / 1 ps
module clkctrl (
input wire inclk, // altclkctrl_input.inclk
output wire outclk // altclkctrl_output.outclk
);
clkctrl_altclkctrl_0 altclkctrl_0 (
.inclk (inclk), // altclkctrl_input.inclk
.outclk (outclk) // altclkctrl_output.outclk
);
endmodule