11 lines
288 B
Plaintext
11 lines
288 B
Plaintext
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<?xml version="1.0" encoding="UTF-8"?>
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<simPackage>
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<file
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path="simulation/submodules/clkctrl_altclkctrl_0.v"
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type="VERILOG"
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library="altclkctrl_0" />
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<file path="simulation/clkctrl.v" type="VERILOG" />
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<topLevel name="clkctrl" />
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<deviceFamily name="max10" />
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</simPackage>
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