HITDAQ/FPGA_firmware/udp_generator_hw.tcl

# TCL File Generated by Component Editor 18.0
# Thu Aug 08 17:47:55 CEST 2019
# DO NOT MODIFY


# 
# udp_generator "UDP generator" v1.0
# M. Dziewiecki 2019.08.08.17:47:55
# A block for making UDP/IP shell over received data
# 

# 
# request TCL package from ACDS 16.1
# 
package require -exact qsys 16.1


# 
# module udp_generator
# 
set_module_property DESCRIPTION "A block for making UDP/IP shell over received data"
set_module_property NAME udp_generator
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR "M. Dziewiecki"
set_module_property DISPLAY_NAME "UDP generator"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false


# 
# file sets
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL udp_generator
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file udp_generator.v VERILOG PATH udp_generator.v TOP_LEVEL_FILE

add_fileset SIM_VERILOG SIM_VERILOG "" ""
set_fileset_property SIM_VERILOG TOP_LEVEL udp_generator
set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file udp_generator.v VERILOG PATH udp_generator.v

add_fileset SIM_VHDL SIM_VHDL "" ""
set_fileset_property SIM_VHDL TOP_LEVEL udp_generator
set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property SIM_VHDL ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file udp_generator.v VERILOG PATH udp_generator.v


# 
# parameters
# 


# 
# display items
# 


# 
# connection point clk
# 
add_interface clk clock end
set_interface_property clk clockRate 0
set_interface_property clk ENABLED true
set_interface_property clk EXPORT_OF ""
set_interface_property clk PORT_NAME_MAP ""
set_interface_property clk CMSIS_SVD_VARIABLES ""
set_interface_property clk SVD_ADDRESS_GROUP ""

add_interface_port clk clk_clk clk Input 1


# 
# connection point rst
# 
add_interface rst reset end
set_interface_property rst associatedClock clk
set_interface_property rst synchronousEdges DEASSERT
set_interface_property rst ENABLED true
set_interface_property rst EXPORT_OF ""
set_interface_property rst PORT_NAME_MAP ""
set_interface_property rst CMSIS_SVD_VARIABLES ""
set_interface_property rst SVD_ADDRESS_GROUP ""

add_interface_port rst rst_reset reset Input 1


# 
# connection point csr
# 
add_interface csr avalon end
set_interface_property csr addressUnits WORDS
set_interface_property csr associatedClock clk
set_interface_property csr associatedReset rst
set_interface_property csr bitsPerSymbol 8
set_interface_property csr burstOnBurstBoundariesOnly false
set_interface_property csr burstcountUnits WORDS
set_interface_property csr explicitAddressSpan 0
set_interface_property csr holdTime 0
set_interface_property csr linewrapBursts false
set_interface_property csr maximumPendingReadTransactions 0
set_interface_property csr maximumPendingWriteTransactions 0
set_interface_property csr readLatency 0
set_interface_property csr readWaitTime 1
set_interface_property csr setupTime 0
set_interface_property csr timingUnits Cycles
set_interface_property csr writeWaitTime 0
set_interface_property csr ENABLED true
set_interface_property csr EXPORT_OF ""
set_interface_property csr PORT_NAME_MAP ""
set_interface_property csr CMSIS_SVD_VARIABLES ""
set_interface_property csr SVD_ADDRESS_GROUP ""

add_interface_port csr csr_address address Input 3
add_interface_port csr csr_write write Input 1
add_interface_port csr csr_writedata writedata Input 32
add_interface_port csr csr_byteenable byteenable Input 4
add_interface_port csr csr_read read Input 1
add_interface_port csr csr_readdata readdata Output 32
set_interface_assignment csr embeddedsw.configuration.isFlash 0
set_interface_assignment csr embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment csr embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment csr embeddedsw.configuration.isPrintableDevice 0


# 
# connection point data_in
# 
add_interface data_in avalon_streaming end
set_interface_property data_in associatedClock clk
set_interface_property data_in associatedReset rst
set_interface_property data_in dataBitsPerSymbol 8
set_interface_property data_in errorDescriptor ""
set_interface_property data_in firstSymbolInHighOrderBits true
set_interface_property data_in maxChannel 0
set_interface_property data_in readyLatency 0
set_interface_property data_in symbolsPerBeat 4
set_interface_property data_in ENABLED true
set_interface_property data_in EXPORT_OF ""
set_interface_property data_in PORT_NAME_MAP ""
set_interface_property data_in CMSIS_SVD_VARIABLES ""
set_interface_property data_in SVD_ADDRESS_GROUP ""

add_interface_port data_in data_in_data data Input 32
add_interface_port data_in data_in_ready ready Output 1
add_interface_port data_in data_in_valid valid Input 1
add_interface_port data_in data_in_empty empty Input 2
add_interface_port data_in data_in_endofpacket endofpacket Input 1
add_interface_port data_in data_in_startofpacket startofpacket Input 1


# 
# connection point data_out
# 
add_interface data_out avalon_streaming start
set_interface_property data_out associatedClock clk
set_interface_property data_out associatedReset rst
set_interface_property data_out dataBitsPerSymbol 8
set_interface_property data_out errorDescriptor ""
set_interface_property data_out firstSymbolInHighOrderBits true
set_interface_property data_out maxChannel 0
set_interface_property data_out readyLatency 0
set_interface_property data_out symbolsPerBeat 4
set_interface_property data_out ENABLED true
set_interface_property data_out EXPORT_OF ""
set_interface_property data_out PORT_NAME_MAP ""
set_interface_property data_out CMSIS_SVD_VARIABLES ""
set_interface_property data_out SVD_ADDRESS_GROUP ""

add_interface_port data_out data_out_data data Output 32
add_interface_port data_out data_out_empty empty Output 2
add_interface_port data_out data_out_endofpacket endofpacket Output 1
add_interface_port data_out data_out_startofpacket startofpacket Output 1
add_interface_port data_out data_out_ready ready Input 1
add_interface_port data_out data_out_valid valid Output 1