# TCL File Generated by Component Editor 19.1
# Mon Jul 29 16:45:07 CEST 2024
# DO NOT MODIFY


# 
# sensor_recon "sensor_recon_rms_cali" v1
# Qin,Liqing 17.July,2024 2024.07.29.16:45:07
# 
# 

# 
# request TCL package from ACDS 16.1
# 
package require -exact qsys 16.1


# 
# module sensor_recon
# 
set_module_property DESCRIPTION ""
set_module_property NAME sensor_recon
set_module_property VERSION 1
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR "Qin,Liqing 17.July,2024"
set_module_property DISPLAY_NAME sensor_recon_rms_cali
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false


# 
# file sets
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL sensor_algo
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file rms.sv SYSTEM_VERILOG PATH rms.sv
add_fileset_file stl2sts.v VERILOG PATH stl2sts.v
add_fileset_file calibration.v VERILOG PATH calibration.v
add_fileset_file algo_top_cl_cali_rms.v VERILOG PATH algo_top_cl_cali_rms.v
add_fileset_file sensor_interface.v VERILOG PATH sensor_interface.v
add_fileset_file serial_rx.v VERILOG PATH serial_rx.v
add_fileset_file serial_tx.v VERILOG PATH serial_tx.v
add_fileset_file sensor_algo.v VERILOG PATH sensor_algo.v TOP_LEVEL_FILE
add_fileset_file bkg_subtraction_pipe.v VERILOG PATH bkg_subtraction_pipe.v
add_fileset_file cluster_locate.sv SYSTEM_VERILOG PATH cluster_locate.sv
add_fileset_file data_caled_ram.v VERILOG PATH data_caled_ram.v
add_fileset_file st_splitter16.v VERILOG PATH q_sys/synthesis/st_splitter16.v
add_fileset_file altera_avalon_st_splitter.sv SYSTEM_VERILOG PATH q_sys/synthesis/altera_avalon_st_splitter.sv
add_fileset_file div.v VERILOG PATH div.v
add_fileset_file sqrt.v VERILOG PATH sqrt.v
add_fileset_file ram4bkg.v VERILOG PATH ram4bkg.v


# 
# parameters
# 


# 
# display items
# 


# 
# connection point csr
# 
add_interface csr avalon end
set_interface_property csr addressUnits WORDS
set_interface_property csr associatedClock clk
set_interface_property csr associatedReset rst
set_interface_property csr bitsPerSymbol 8
set_interface_property csr burstOnBurstBoundariesOnly false
set_interface_property csr burstcountUnits WORDS
set_interface_property csr explicitAddressSpan 0
set_interface_property csr holdTime 0
set_interface_property csr linewrapBursts false
set_interface_property csr maximumPendingReadTransactions 0
set_interface_property csr maximumPendingWriteTransactions 0
set_interface_property csr readLatency 0
set_interface_property csr readWaitTime 1
set_interface_property csr setupTime 0
set_interface_property csr timingUnits Cycles
set_interface_property csr writeWaitTime 0
set_interface_property csr ENABLED true
set_interface_property csr EXPORT_OF ""
set_interface_property csr PORT_NAME_MAP ""
set_interface_property csr CMSIS_SVD_VARIABLES ""
set_interface_property csr SVD_ADDRESS_GROUP ""

add_interface_port csr csr_address address Input 2
add_interface_port csr csr_read read Input 1
add_interface_port csr csr_readdata readdata Output 32
add_interface_port csr csr_write write Input 1
add_interface_port csr csr_writedata writedata Input 32
add_interface_port csr csr_byteenable byteenable Input 4
set_interface_assignment csr embeddedsw.configuration.isFlash 0
set_interface_assignment csr embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment csr embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment csr embeddedsw.configuration.isPrintableDevice 0


# 
# connection point data_out
# 
add_interface data_out avalon_streaming start
set_interface_property data_out associatedClock clk
set_interface_property data_out associatedReset rst
set_interface_property data_out dataBitsPerSymbol 8
set_interface_property data_out errorDescriptor ""
set_interface_property data_out firstSymbolInHighOrderBits true
set_interface_property data_out maxChannel 0
set_interface_property data_out readyLatency 0
set_interface_property data_out ENABLED true
set_interface_property data_out EXPORT_OF ""
set_interface_property data_out PORT_NAME_MAP ""
set_interface_property data_out CMSIS_SVD_VARIABLES ""
set_interface_property data_out SVD_ADDRESS_GROUP ""

add_interface_port data_out data_out_endofpacket endofpacket Output 1
add_interface_port data_out data_out_data data Output 32
add_interface_port data_out data_out_empty empty Output 2
add_interface_port data_out data_out_ready ready Input 1
add_interface_port data_out data_out_startofpacket startofpacket Output 1
add_interface_port data_out data_out_valid valid Output 1


# 
# connection point clk
# 
add_interface clk clock end
set_interface_property clk clockRate 0
set_interface_property clk ENABLED true
set_interface_property clk EXPORT_OF ""
set_interface_property clk PORT_NAME_MAP ""
set_interface_property clk CMSIS_SVD_VARIABLES ""
set_interface_property clk SVD_ADDRESS_GROUP ""

add_interface_port clk clk_clk clk Input 1


# 
# connection point rst
# 
add_interface rst reset end
set_interface_property rst associatedClock clk
set_interface_property rst synchronousEdges DEASSERT
set_interface_property rst ENABLED true
set_interface_property rst EXPORT_OF ""
set_interface_property rst PORT_NAME_MAP ""
set_interface_property rst CMSIS_SVD_VARIABLES ""
set_interface_property rst SVD_ADDRESS_GROUP ""

add_interface_port rst rst_reset reset Input 1


# 
# connection point sensor
# 
add_interface sensor conduit end
set_interface_property sensor associatedClock clk
set_interface_property sensor associatedReset ""
set_interface_property sensor ENABLED true
set_interface_property sensor EXPORT_OF ""
set_interface_property sensor PORT_NAME_MAP ""
set_interface_property sensor CMSIS_SVD_VARIABLES ""
set_interface_property sensor SVD_ADDRESS_GROUP ""

add_interface_port sensor in_adc_data in_adc_data Input 5
add_interface_port sensor in_trg in_trg Input 1
add_interface_port sensor out_adc_clk out_adc_clk Output 1
add_interface_port sensor out_adc_cnv out_adc_cnv Output 1
add_interface_port sensor out_sensor_clk out_sensor_clk Output 1
add_interface_port sensor out_sensor_gain out_sensor_gain Output 1
add_interface_port sensor out_sensor_rst out_sensor_rst Output 1


# 
# connection point status_out
# 
add_interface status_out conduit end
set_interface_property status_out associatedClock clk
set_interface_property status_out associatedReset ""
set_interface_property status_out ENABLED true
set_interface_property status_out EXPORT_OF ""
set_interface_property status_out PORT_NAME_MAP ""
set_interface_property status_out CMSIS_SVD_VARIABLES ""
set_interface_property status_out SVD_ADDRESS_GROUP ""

add_interface_port status_out status_out status_out Output 8


# 
# connection point synchro
# 
add_interface synchro conduit end
set_interface_property synchro associatedClock clk
set_interface_property synchro associatedReset ""
set_interface_property synchro ENABLED true
set_interface_property synchro EXPORT_OF ""
set_interface_property synchro PORT_NAME_MAP ""
set_interface_property synchro CMSIS_SVD_VARIABLES ""
set_interface_property synchro SVD_ADDRESS_GROUP ""

add_interface_port synchro ext_input ext_input Input 8
add_interface_port synchro serial_rx serial_rx Input 1
add_interface_port synchro serial_tx serial_tx Output 1


# 
# connection point calibration_ram_interface
# 
add_interface calibration_ram_interface avalon start
set_interface_property calibration_ram_interface addressUnits WORDS
set_interface_property calibration_ram_interface associatedClock clk
set_interface_property calibration_ram_interface associatedReset rst
set_interface_property calibration_ram_interface bitsPerSymbol 8
set_interface_property calibration_ram_interface burstOnBurstBoundariesOnly false
set_interface_property calibration_ram_interface burstcountUnits WORDS
set_interface_property calibration_ram_interface doStreamReads false
set_interface_property calibration_ram_interface doStreamWrites false
set_interface_property calibration_ram_interface holdTime 0
set_interface_property calibration_ram_interface linewrapBursts false
set_interface_property calibration_ram_interface maximumPendingReadTransactions 0
set_interface_property calibration_ram_interface maximumPendingWriteTransactions 0
set_interface_property calibration_ram_interface readLatency 0
set_interface_property calibration_ram_interface readWaitTime 1
set_interface_property calibration_ram_interface setupTime 0
set_interface_property calibration_ram_interface timingUnits Cycles
set_interface_property calibration_ram_interface writeWaitTime 0
set_interface_property calibration_ram_interface ENABLED true
set_interface_property calibration_ram_interface EXPORT_OF ""
set_interface_property calibration_ram_interface PORT_NAME_MAP ""
set_interface_property calibration_ram_interface CMSIS_SVD_VARIABLES ""
set_interface_property calibration_ram_interface SVD_ADDRESS_GROUP ""

add_interface_port calibration_ram_interface address address Output 9
add_interface_port calibration_ram_interface clken read Output 1
add_interface_port calibration_ram_interface cali_fac readdata Input 16
add_interface_port calibration_ram_interface waitrequest waitrequest Input 1

