<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
 <component
   name="$${FILENAME}"
   displayName="$${FILENAME}"
   version="1.0"
   description=""
   tags=""
   categories="System" />
 <parameter name="bonusData"><![CDATA[bonusData 
{
   element altpll_shift
   {
      datum _sortIndex
      {
         value = "23";
         type = "int";
      }
   }
   element button_pio
   {
      datum _sortIndex
      {
         value = "13";
         type = "int";
      }
   }
   element button_pio.s1
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "406863168";
         type = "String";
      }
   }
   element calibration_ram
   {
      datum _sortIndex
      {
         value = "5";
         type = "int";
      }
   }
   element calibration_ram.s1
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "406860800";
         type = "String";
      }
   }
   element calibration_ram.s2
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "0";
         type = "String";
      }
   }
   element channel_adapter_0
   {
      datum _sortIndex
      {
         value = "20";
         type = "int";
      }
   }
   element cpu
   {
      datum _sortIndex
      {
         value = "1";
         type = "int";
      }
      datum sopceditor_expanded
      {
         value = "1";
         type = "boolean";
      }
   }
   element cpu.debug_mem_slave
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "406857728";
         type = "String";
      }
   }
   element ddr3_ram
   {
      datum _sortIndex
      {
         value = "7";
         type = "int";
      }
   }
   element ddr3_ram.avl
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "134217728";
         type = "String";
      }
   }
   element ddr3_ram_resetn
   {
      datum _sortIndex
      {
         value = "6";
         type = "int";
      }
   }
   element debug_uart
   {
      datum _sortIndex
      {
         value = "11";
         type = "int";
      }
   }
   element debug_uart.s1
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "406862880";
         type = "String";
      }
   }
   element descriptor_memory
   {
      datum _sortIndex
      {
         value = "14";
         type = "int";
      }
      datum sopceditor_expanded
      {
         value = "1";
         type = "boolean";
      }
   }
   element descriptor_memory.s1
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "406847488";
         type = "String";
      }
   }
   element enet_pll
   {
      datum _sortIndex
      {
         value = "22";
         type = "int";
      }
   }
   element eth_tse
   {
      datum _sortIndex
      {
         value = "21";
         type = "int";
      }
      datum sopceditor_expanded
      {
         value = "1";
         type = "boolean";
      }
   }
   element eth_tse.control_port
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "406859776";
         type = "String";
      }
   }
   element ext_flash
   {
      datum _sortIndex
      {
         value = "3";
         type = "int";
      }
   }
   element ext_flash.avl_csr
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "406863136";
         type = "String";
      }
   }
   element ext_flash.avl_mem
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "335544320";
         type = "String";
      }
   }
   element ext_flash_clock_bridge
   {
      datum _sortIndex
      {
         value = "2";
         type = "int";
      }
   }
   element frame_timer
   {
      datum _sortIndex
      {
         value = "24";
         type = "int";
      }
   }
   element frame_timer.s1
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "406862848";
         type = "String";
      }
   }
   element glad
   {
      datum _sortIndex
      {
         value = "25";
         type = "int";
      }
   }
   element glad.s1
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "406861824";
         type = "String";
      }
   }
   element msgdma_rx
   {
      datum _sortIndex
      {
         value = "15";
         type = "int";
      }
   }
   element msgdma_rx.csr
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "406863072";
         type = "String";
      }
   }
   element msgdma_rx.prefetcher_csr
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "406862976";
         type = "String";
      }
   }
   element msgdma_tx
   {
      datum _sortIndex
      {
         value = "16";
         type = "int";
      }
   }
   element msgdma_tx.csr
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "406863104";
         type = "String";
      }
   }
   element msgdma_tx.prefetcher_csr
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "406863008";
         type = "String";
      }
   }
   element onchip_flash
   {
      datum _sortIndex
      {
         value = "4";
         type = "int";
      }
   }
   element onchip_flash.csr
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "406863200";
         type = "String";
      }
   }
   element onchip_flash.data
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "404750336";
         type = "String";
      }
   }
   element onchip_ram
   {
      datum _sortIndex
      {
         value = "8";
         type = "int";
      }
   }
   element onchip_ram.s1
   {
      datum baseAddress
      {
         value = "403767296";
         type = "String";
      }
   }
   element output_pio
   {
      datum _sortIndex
      {
         value = "12";
         type = "int";
      }
   }
   element output_pio.s1
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "406862912";
         type = "String";
      }
   }
   element q_sys
   {
      datum _originalDeviceFamily
      {
         value = "MAX 10";
         type = "String";
      }
   }
   element q_sys
   {
      datum _originalDeviceFamily
      {
         value = "MAX 10";
         type = "String";
      }
   }
   element q_sys
   {
      datum _originalDeviceFamily
      {
         value = "MAX 10";
         type = "String";
      }
   }
   element q_sys
   {
      datum _originalDeviceFamily
      {
         value = "MAX 10";
         type = "String";
      }
   }
   element q_sys
   {
      datum _originalDeviceFamily
      {
         value = "MAX 10";
         type = "String";
      }
   }
   element q_sys
   {
      datum _originalDeviceFamily
      {
         value = "MAX 10";
         type = "String";
      }
   }
   element q_sys
   {
      datum _originalDeviceFamily
      {
         value = "MAX 10";
         type = "String";
      }
   }
   element q_sys
   {
      datum _originalDeviceFamily
      {
         value = "MAX 10";
         type = "String";
      }
   }
   element q_sys
   {
      datum _originalDeviceFamily
      {
         value = "MAX 10";
         type = "String";
      }
   }
   element q_sys
   {
      datum _originalDeviceFamily
      {
         value = "MAX 10";
         type = "String";
      }
   }
   element q_sys
   {
      datum _originalDeviceFamily
      {
         value = "MAX 10";
         type = "String";
      }
   }
   element q_sys
   {
      datum _originalDeviceFamily
      {
         value = "MAX 10";
         type = "String";
      }
   }
   element q_sys
   {
      datum _originalDeviceFamily
      {
         value = "MAX 10";
         type = "String";
      }
   }
   element q_sys
   {
      datum _originalDeviceFamily
      {
         value = "MAX 10";
         type = "String";
      }
   }
   element q_sys
   {
      datum _originalDeviceFamily
      {
         value = "MAX 10";
         type = "String";
      }
   }
   element q_sys
   {
      datum _originalDeviceFamily
      {
         value = "MAX 10";
         type = "String";
      }
   }
   element q_sys
   {
      datum _originalDeviceFamily
      {
         value = "MAX 10";
         type = "String";
      }
   }
   element q_sys
   {
      datum _originalDeviceFamily
      {
         value = "MAX 10";
         type = "String";
      }
   }
   element q_sys
   {
      datum _originalDeviceFamily
      {
         value = "MAX 10";
         type = "String";
      }
   }
   element q_sys
   {
      datum _originalDeviceFamily
      {
         value = "MAX 10";
         type = "String";
      }
   }
   element q_sys
   {
      datum _originalDeviceFamily
      {
         value = "MAX 10";
         type = "String";
      }
   }
   element q_sys
   {
      datum _originalDeviceFamily
      {
         value = "MAX 10";
         type = "String";
      }
   }
   element q_sys
   {
      datum _originalDeviceFamily
      {
         value = "MAX 10";
         type = "String";
      }
   }
   element sensor_interface
   {
      datum _sortIndex
      {
         value = "17";
         type = "int";
      }
   }
   element sensor_interface.csr
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "406863184";
         type = "String";
      }
   }
   element sys_clk
   {
      datum _sortIndex
      {
         value = "0";
         type = "int";
      }
      datum sopceditor_expanded
      {
         value = "1";
         type = "boolean";
      }
   }
   element sys_clk_timer
   {
      datum _sortIndex
      {
         value = "9";
         type = "int";
      }
      datum sopceditor_expanded
      {
         value = "1";
         type = "boolean";
      }
   }
   element sys_clk_timer.s1
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "406862944";
         type = "String";
      }
   }
   element sysid
   {
      datum _sortIndex
      {
         value = "10";
         type = "int";
      }
      datum sopceditor_expanded
      {
         value = "1";
         type = "boolean";
      }
   }
   element sysid.clk
   {
      datum _tags
      {
         value = "";
         type = "String";
      }
   }
   element sysid.control_slave
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "406863208";
         type = "String";
      }
   }
   element tx_multiplexer
   {
      datum _sortIndex
      {
         value = "19";
         type = "int";
      }
   }
   element udp_generator
   {
      datum _sortIndex
      {
         value = "18";
         type = "int";
      }
   }
   element udp_generator.csr
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "406863040";
         type = "String";
      }
   }
}
]]></parameter>
 <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
 <parameter name="device" value="10M50DAF484C6GES" />
 <parameter name="deviceFamily" value="MAX 10" />
 <parameter name="deviceSpeedGrade" value="6" />
 <parameter name="fabricMode" value="QSYS" />
 <parameter name="generateLegacySim" value="false" />
 <parameter name="generationId" value="0" />
 <parameter name="globalResetBus" value="false" />
 <parameter name="hdlLanguage" value="VERILOG" />
 <parameter name="hideFromIPCatalog" value="false" />
 <parameter name="lockedInterfaceDefinition" value="" />
 <parameter name="maxAdditionalLatency" value="0" />
 <parameter name="projectName" value="hit20v3.qpf" />
 <parameter name="sopcBorderPoints" value="false" />
 <parameter name="systemHash" value="0" />
 <parameter name="testBenchDutName" value="" />
 <parameter name="timeStamp" value="0" />
 <parameter name="useTestBenchNamingPattern" value="false" />
 <instanceScript></instanceScript>
 <interface
   name="altpll_shift_c0"
   internal="altpll_shift.c0"
   type="clock"
   dir="start" />
 <interface name="altpll_shift_c1" internal="altpll_shift.c1" />
 <interface name="altpll_shift_c2" internal="altpll_shift.c2" />
 <interface
   name="altpll_shift_locked_conduit"
   internal="altpll_shift.locked_conduit"
   type="conduit"
   dir="end" />
 <interface
   name="button_pio_external_connection"
   internal="button_pio.external_connection"
   type="conduit"
   dir="end" />
 <interface
   name="clock_bridge_0_in_clk"
   internal="ext_flash_clock_bridge.in_clk"
   type="clock"
   dir="end" />
 <interface name="ddr2_lo_latency_128m_auxfull" internal=".auxfull" />
 <interface name="ddr2_lo_latency_128m_global_reset_n" internal=".global_reset_n" />
 <interface name="ddr2_lo_latency_128m_memory" internal=".memory" />
 <interface
   name="ddr3_ram_pll_ref_clk"
   internal="ddr3_ram.pll_ref_clk"
   type="clock"
   dir="end" />
 <interface
   name="debug_uart_external_connection"
   internal="debug_uart.external_connection"
   type="conduit"
   dir="end" />
 <interface name="dipsw_pio_out" internal=".external_connection" />
 <interface name="enet_pll_c0" internal="enet_pll.c0" type="clock" dir="start" />
 <interface name="enet_pll_c1" internal="enet_pll.c1" type="clock" dir="start" />
 <interface name="enet_pll_c2" internal="enet_pll.c2" type="clock" dir="start" />
 <interface name="enet_pll_c3" internal="enet_pll.c3" type="clock" dir="start" />
 <interface name="enet_pll_c4" internal="enet_pll.c4" type="clock" dir="start" />
 <interface
   name="enet_pll_locked_conduit"
   internal="enet_pll.locked_conduit"
   type="conduit"
   dir="end" />
 <interface
   name="eth_tse_mac_mdio_connection"
   internal="eth_tse.mac_mdio_connection"
   type="conduit"
   dir="end" />
 <interface
   name="eth_tse_mac_rgmii_connection"
   internal="eth_tse.mac_rgmii_connection"
   type="conduit"
   dir="end" />
 <interface
   name="eth_tse_mac_status_connection"
   internal="eth_tse.mac_status_connection"
   type="conduit"
   dir="end" />
 <interface
   name="eth_tse_pcs_mac_rx_clock_connection"
   internal="eth_tse.pcs_mac_rx_clock_connection"
   type="clock"
   dir="end" />
 <interface
   name="eth_tse_pcs_mac_tx_clock_connection"
   internal="eth_tse.pcs_mac_tx_clock_connection"
   type="clock"
   dir="end" />
 <interface name="eth_tse_serial_connection" internal="eth_tse.serial_connection" />
 <interface
   name="eth_tse_status_led_connection"
   internal="eth_tse.status_led_connection" />
 <interface
   name="ext_flash_flash_dataout"
   internal="ext_flash.flash_dataout"
   type="conduit"
   dir="end" />
 <interface
   name="ext_flash_flash_dclk_out"
   internal="ext_flash.flash_dclk_out"
   type="conduit"
   dir="end" />
 <interface
   name="ext_flash_flash_ncs"
   internal="ext_flash.flash_ncs"
   type="conduit"
   dir="end" />
 <interface
   name="frame_timer"
   internal="frame_timer.external_port"
   type="conduit"
   dir="end" />
 <interface name="jtag_avalon_master_clk_reset" internal=".clk_reset" />
 <interface
   name="led_pio_external_connection"
   internal="output_pio.external_connection"
   type="conduit"
   dir="end" />
 <interface
   name="mem_if_ddr3_emif_0_status"
   internal="ddr3_ram.status"
   type="conduit"
   dir="end" />
 <interface
   name="mem_resetn_in_reset"
   internal="ddr3_ram_resetn.in_reset"
   type="reset"
   dir="end" />
 <interface name="memory" internal="ddr3_ram.memory" type="conduit" dir="end" />
 <interface name="ref_clk_clk_in" internal=".clk_in" />
 <interface name="reset" internal="sys_clk.clk_in_reset" type="reset" dir="end" />
 <interface
   name="sensor"
   internal="sensor_interface.sensor"
   type="conduit"
   dir="end" />
 <interface
   name="sensor_status"
   internal="sensor_interface.status_out"
   type="conduit"
   dir="end" />
 <interface
   name="sensor_synchro"
   internal="sensor_interface.synchro"
   type="conduit"
   dir="end" />
 <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
 <module name="altpll_shift" kind="altpll" version="19.1" enabled="1">
  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
  <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
  <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
  <parameter name="BANDWIDTH" value="" />
  <parameter name="BANDWIDTH_TYPE" value="AUTO" />
  <parameter name="CLK0_DIVIDE_BY" value="1" />
  <parameter name="CLK0_DUTY_CYCLE" value="50" />
  <parameter name="CLK0_MULTIPLY_BY" value="5" />
  <parameter name="CLK0_PHASE_SHIFT" value="0" />
  <parameter name="CLK1_DIVIDE_BY" value="2" />
  <parameter name="CLK1_DUTY_CYCLE" value="50" />
  <parameter name="CLK1_MULTIPLY_BY" value="1" />
  <parameter name="CLK1_PHASE_SHIFT" value="15000" />
  <parameter name="CLK2_DIVIDE_BY" value="20" />
  <parameter name="CLK2_DUTY_CYCLE" value="50" />
  <parameter name="CLK2_MULTIPLY_BY" value="1" />
  <parameter name="CLK2_PHASE_SHIFT" value="0" />
  <parameter name="CLK3_DIVIDE_BY" value="" />
  <parameter name="CLK3_DUTY_CYCLE" value="" />
  <parameter name="CLK3_MULTIPLY_BY" value="" />
  <parameter name="CLK3_PHASE_SHIFT" value="" />
  <parameter name="CLK4_DIVIDE_BY" value="" />
  <parameter name="CLK4_DUTY_CYCLE" value="" />
  <parameter name="CLK4_MULTIPLY_BY" value="" />
  <parameter name="CLK4_PHASE_SHIFT" value="" />
  <parameter name="CLK5_DIVIDE_BY" value="" />
  <parameter name="CLK5_DUTY_CYCLE" value="" />
  <parameter name="CLK5_MULTIPLY_BY" value="" />
  <parameter name="CLK5_PHASE_SHIFT" value="" />
  <parameter name="CLK6_DIVIDE_BY" value="" />
  <parameter name="CLK6_DUTY_CYCLE" value="" />
  <parameter name="CLK6_MULTIPLY_BY" value="" />
  <parameter name="CLK6_PHASE_SHIFT" value="" />
  <parameter name="CLK7_DIVIDE_BY" value="" />
  <parameter name="CLK7_DUTY_CYCLE" value="" />
  <parameter name="CLK7_MULTIPLY_BY" value="" />
  <parameter name="CLK7_PHASE_SHIFT" value="" />
  <parameter name="CLK8_DIVIDE_BY" value="" />
  <parameter name="CLK8_DUTY_CYCLE" value="" />
  <parameter name="CLK8_MULTIPLY_BY" value="" />
  <parameter name="CLK8_PHASE_SHIFT" value="" />
  <parameter name="CLK9_DIVIDE_BY" value="" />
  <parameter name="CLK9_DUTY_CYCLE" value="" />
  <parameter name="CLK9_MULTIPLY_BY" value="" />
  <parameter name="CLK9_PHASE_SHIFT" value="" />
  <parameter name="COMPENSATE_CLOCK" value="CLK0" />
  <parameter name="DOWN_SPREAD" value="" />
  <parameter name="DPA_DIVIDER" value="" />
  <parameter name="DPA_DIVIDE_BY" value="" />
  <parameter name="DPA_MULTIPLY_BY" value="" />
  <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
  <parameter name="EXTCLK0_DIVIDE_BY" value="" />
  <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
  <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
  <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
  <parameter name="EXTCLK1_DIVIDE_BY" value="" />
  <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
  <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
  <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
  <parameter name="EXTCLK2_DIVIDE_BY" value="" />
  <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
  <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
  <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
  <parameter name="EXTCLK3_DIVIDE_BY" value="" />
  <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
  <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
  <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
  <parameter name="FEEDBACK_SOURCE" value="" />
  <parameter name="GATE_LOCK_COUNTER" value="" />
  <parameter name="GATE_LOCK_SIGNAL" value="" />
  <parameter name="HIDDEN_CONSTANTS">CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 15000 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 2 CT#PORT_LOCKED PORT_USED</parameter>
  <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
  <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
  <parameter name="HIDDEN_IF_PORTS">IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}</parameter>
  <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
  <parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
  <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
  <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 0 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 0 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ2 100.00000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 6 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT2 0.00000000 PT#PHASE_SHIFT1 135.00000000 PT#DIV_FACTOR2 20 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 2 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 250.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 5 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1423823783608952.mif PT#ACTIVECLK_CHECK 0</parameter>
  <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
  <parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
  <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
  <parameter name="INTENDED_DEVICE_FAMILY" value="MAX 10" />
  <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
  <parameter name="LOCK_HIGH" value="" />
  <parameter name="LOCK_LOW" value="" />
  <parameter name="OPERATION_MODE" value="NORMAL" />
  <parameter name="PLL_TYPE" value="AUTO" />
  <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
  <parameter name="PORT_ARESET" value="PORT_USED" />
  <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
  <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
  <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
  <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
  <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
  <parameter name="PORT_ENABLE0" value="" />
  <parameter name="PORT_ENABLE1" value="" />
  <parameter name="PORT_FBIN" value="PORT_UNUSED" />
  <parameter name="PORT_FBOUT" value="" />
  <parameter name="PORT_INCLK0" value="PORT_USED" />
  <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
  <parameter name="PORT_LOCKED" value="PORT_USED" />
  <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
  <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
  <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
  <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
  <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
  <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
  <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
  <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
  <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
  <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
  <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
  <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
  <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
  <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
  <parameter name="PORT_SCLKOUT0" value="" />
  <parameter name="PORT_SCLKOUT1" value="" />
  <parameter name="PORT_VCOOVERRANGE" value="" />
  <parameter name="PORT_VCOUNDERRANGE" value="" />
  <parameter name="PORT_clk0" value="PORT_USED" />
  <parameter name="PORT_clk1" value="PORT_UNUSED" />
  <parameter name="PORT_clk2" value="PORT_UNUSED" />
  <parameter name="PORT_clk3" value="PORT_UNUSED" />
  <parameter name="PORT_clk4" value="PORT_UNUSED" />
  <parameter name="PORT_clk5" value="PORT_UNUSED" />
  <parameter name="PORT_clk6" value="" />
  <parameter name="PORT_clk7" value="" />
  <parameter name="PORT_clk8" value="" />
  <parameter name="PORT_clk9" value="" />
  <parameter name="PORT_clkena0" value="PORT_UNUSED" />
  <parameter name="PORT_clkena1" value="PORT_UNUSED" />
  <parameter name="PORT_clkena2" value="PORT_UNUSED" />
  <parameter name="PORT_clkena3" value="PORT_UNUSED" />
  <parameter name="PORT_clkena4" value="PORT_UNUSED" />
  <parameter name="PORT_clkena5" value="PORT_UNUSED" />
  <parameter name="PORT_extclk0" value="PORT_UNUSED" />
  <parameter name="PORT_extclk1" value="PORT_UNUSED" />
  <parameter name="PORT_extclk2" value="PORT_UNUSED" />
  <parameter name="PORT_extclk3" value="PORT_UNUSED" />
  <parameter name="PORT_extclkena0" value="" />
  <parameter name="PORT_extclkena1" value="" />
  <parameter name="PORT_extclkena2" value="" />
  <parameter name="PORT_extclkena3" value="" />
  <parameter name="PRIMARY_CLOCK" value="" />
  <parameter name="QUALIFY_CONF_DONE" value="" />
  <parameter name="SCAN_CHAIN" value="" />
  <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
  <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
  <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
  <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
  <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
  <parameter name="SKIP_VCO" value="" />
  <parameter name="SPREAD_FREQUENCY" value="" />
  <parameter name="SWITCH_OVER_COUNTER" value="" />
  <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
  <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
  <parameter name="SWITCH_OVER_TYPE" value="" />
  <parameter name="USING_FBMIMICBIDIR_PORT" value="" />
  <parameter name="VALID_LOCK_MULTIPLIER" value="" />
  <parameter name="VCO_DIVIDE_BY" value="" />
  <parameter name="VCO_FREQUENCY_CONTROL" value="" />
  <parameter name="VCO_MULTIPLY_BY" value="" />
  <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
  <parameter name="WIDTH_CLOCK" value="5" />
  <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
 </module>
 <module name="button_pio" kind="altera_avalon_pio" version="19.1" enabled="1">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="false" />
  <parameter name="clockRate" value="50000000" />
  <parameter name="direction" value="Input" />
  <parameter name="edgeType" value="RISING" />
  <parameter name="generateIRQ" value="false" />
  <parameter name="irqType" value="LEVEL" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="9" />
 </module>
 <module
   name="calibration_ram"
   kind="altera_avalon_onchip_memory2"
   version="19.1"
   enabled="1">
  <parameter name="allowInSystemMemoryContentEditor" value="false" />
  <parameter name="autoInitializationFileName">$${FILENAME}_calibration_ram</parameter>
  <parameter name="blockType" value="AUTO" />
  <parameter name="copyInitFile" value="false" />
  <parameter name="dataWidth" value="16" />
  <parameter name="dataWidth2" value="16" />
  <parameter name="deviceFamily" value="MAX 10" />
  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
  <parameter name="dualPort" value="true" />
  <parameter name="ecc_enabled" value="false" />
  <parameter name="enPRInitMode" value="false" />
  <parameter name="enableDiffWidth" value="false" />
  <parameter name="initMemContent" value="false" />
  <parameter name="initializationFileName" value="onchip_mem.hex" />
  <parameter name="instanceID" value="NONE" />
  <parameter name="memorySize" value="640" />
  <parameter name="readDuringWriteMode" value="DONT_CARE" />
  <parameter name="resetrequest_enabled" value="false" />
  <parameter name="simAllowMRAMContentsFile" value="false" />
  <parameter name="simMemInitOnlyFilename" value="0" />
  <parameter name="singleClockOperation" value="false" />
  <parameter name="slave1Latency" value="1" />
  <parameter name="slave2Latency" value="1" />
  <parameter name="useNonDefaultInitFile" value="false" />
  <parameter name="useShallowMemBlocks" value="false" />
  <parameter name="writable" value="true" />
 </module>
 <module
   name="channel_adapter_0"
   kind="channel_adapter"
   version="19.1"
   enabled="1">
  <parameter name="inBitsPerSymbol" value="8" />
  <parameter name="inChannelWidth" value="1" />
  <parameter name="inErrorDescriptor" value="" />
  <parameter name="inErrorWidth" value="1" />
  <parameter name="inMaxChannel" value="1" />
  <parameter name="inReadyLatency" value="0" />
  <parameter name="inSymbolsPerBeat" value="4" />
  <parameter name="inUseEmpty" value="false" />
  <parameter name="inUseEmptyPort" value="YES" />
  <parameter name="inUsePackets" value="true" />
  <parameter name="inUseReady" value="true" />
  <parameter name="outChannelWidth" value="0" />
  <parameter name="outMaxChannel" value="1" />
 </module>
 <module name="cpu" kind="altera_nios2_gen2" version="19.1" enabled="1">
  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="13" />
  <parameter name="AUTO_CLK_RESET_DOMAIN" value="13" />
  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
  <parameter name="bht_ramBlockType" value="Automatic" />
  <parameter name="breakOffset" value="32" />
  <parameter name="breakSlave">cpu.jtag_debug_module</parameter>
  <parameter name="cdx_enabled" value="false" />
  <parameter name="clockFrequency" value="50000000" />
  <parameter name="cpuArchRev" value="1" />
  <parameter name="cpuID" value="0" />
  <parameter name="cpuReset" value="false" />
  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
  <parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
  <parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
  <parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
  <parameter name="dataAddrWidth" value="29" />
  <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
  <parameter name="dataMasterHighPerformanceMapParam" value="" />
  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18200000' end='0x18360000' type='altera_onchip_flash.data' /><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' type='altera_avalon_onchip_memory2.s1' /><slave name='cpu.debug_mem_slave' start='0x18402800' end='0x18403000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='eth_tse.control_port' start='0x18403000' end='0x18403400' type='altera_eth_tse.control_port' /><slave name='calibration_ram.s1' start='0x18403400' end='0x18403680' type='altera_avalon_onchip_memory2.s1' /><slave name='frame_timer.s1' start='0x18403C00' end='0x18403C20' type='altera_avalon_timer.s1' /><slave name='debug_uart.s1' start='0x18403C20' end='0x18403C40' type='altera_avalon_uart.s1' /><slave name='output_pio.s1' start='0x18403C40' end='0x18403C60' type='altera_avalon_pio.s1' /><slave name='sys_clk_timer.s1' start='0x18403C60' end='0x18403C80' type='altera_avalon_timer.s1' /><slave name='msgdma_rx.prefetcher_csr' start='0x18403C80' end='0x18403CA0' type='altera_msgdma.prefetcher_csr' /><slave name='msgdma_tx.prefetcher_csr' start='0x18403CA0' end='0x18403CC0' type='altera_msgdma.prefetcher_csr' /><slave name='udp_generator.csr' start='0x18403CC0' end='0x18403CE0' type='udp_generator.csr' /><slave name='msgdma_rx.csr' start='0x18403CE0' end='0x18403D00' type='altera_msgdma.csr' /><slave name='msgdma_tx.csr' start='0x18403D00' end='0x18403D20' type='altera_msgdma.csr' /><slave name='ext_flash.avl_csr' start='0x18403D20' end='0x18403D40' type='altera_generic_quad_spi_controller.avl_csr' /><slave name='button_pio.s1' start='0x18403D40' end='0x18403D50' type='altera_avalon_pio.s1' /><slave name='sensor_interface.csr' start='0x18403D50' end='0x18403D60' type='sensor_recon.csr' /><slave name='onchip_flash.csr' start='0x18403D60' end='0x18403D68' type='altera_onchip_flash.csr' /><slave name='sysid.control_slave' start='0x18403D68' end='0x18403D70' type='altera_avalon_sysid_qsys.control_slave' /></address-map>]]></parameter>
  <parameter name="data_master_high_performance_paddr_base" value="0" />
  <parameter name="data_master_high_performance_paddr_size" value="0" />
  <parameter name="data_master_paddr_base" value="0" />
  <parameter name="data_master_paddr_size" value="0" />
  <parameter name="dcache_bursts" value="false" />
  <parameter name="dcache_numTCDM" value="0" />
  <parameter name="dcache_ramBlockType" value="Automatic" />
  <parameter name="dcache_size" value="2048" />
  <parameter name="dcache_tagramBlockType" value="Automatic" />
  <parameter name="dcache_victim_buf_impl" value="ram" />
  <parameter name="debug_OCIOnchipTrace" value="_128" />
  <parameter name="debug_assignJtagInstanceID" value="false" />
  <parameter name="debug_datatrigger" value="0" />
  <parameter name="debug_debugReqSignals" value="false" />
  <parameter name="debug_enabled" value="true" />
  <parameter name="debug_hwbreakpoint" value="2" />
  <parameter name="debug_jtagInstanceID" value="0" />
  <parameter name="debug_traceStorage" value="onchip_trace" />
  <parameter name="debug_traceType" value="none" />
  <parameter name="debug_triggerArming" value="true" />
  <parameter name="deviceFamilyName" value="MAX 10" />
  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
  <parameter name="dividerType" value="no_div" />
  <parameter name="exceptionOffset" value="288" />
  <parameter name="exceptionSlave" value="ddr3_ram.avl" />
  <parameter name="faAddrWidth" value="1" />
  <parameter name="faSlaveMapParam" value="" />
  <parameter name="fa_cache_line" value="2" />
  <parameter name="fa_cache_linesize" value="0" />
  <parameter name="flash_instruction_master_paddr_base" value="0" />
  <parameter name="flash_instruction_master_paddr_size" value="0" />
  <parameter name="icache_burstType" value="None" />
  <parameter name="icache_numTCIM" value="0" />
  <parameter name="icache_ramBlockType" value="Automatic" />
  <parameter name="icache_size" value="2048" />
  <parameter name="icache_tagramBlockType" value="Automatic" />
  <parameter name="impl" value="Fast" />
  <parameter name="instAddrWidth" value="29" />
  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18200000' end='0x18360000' type='altera_onchip_flash.data' /><slave name='cpu.debug_mem_slave' start='0x18402800' end='0x18403000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
  <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
  <parameter name="instructionMasterHighPerformanceMapParam" value="" />
  <parameter name="instruction_master_high_performance_paddr_base" value="0" />
  <parameter name="instruction_master_high_performance_paddr_size" value="0" />
  <parameter name="instruction_master_paddr_base" value="0" />
  <parameter name="instruction_master_paddr_size" value="0" />
  <parameter name="internalIrqMaskSystemInfo" value="61" />
  <parameter name="io_regionbase" value="0" />
  <parameter name="io_regionsize" value="0" />
  <parameter name="master_addr_map" value="false" />
  <parameter name="mmu_TLBMissExcOffset" value="0" />
  <parameter name="mmu_TLBMissExcSlave" value="" />
  <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
  <parameter name="mmu_enabled" value="false" />
  <parameter name="mmu_processIDNumBits" value="8" />
  <parameter name="mmu_ramBlockType" value="Automatic" />
  <parameter name="mmu_tlbNumWays" value="16" />
  <parameter name="mmu_tlbPtrSz" value="7" />
  <parameter name="mmu_udtlbNumEntries" value="6" />
  <parameter name="mmu_uitlbNumEntries" value="4" />
  <parameter name="mpu_enabled" value="false" />
  <parameter name="mpu_minDataRegionSize" value="12" />
  <parameter name="mpu_minInstRegionSize" value="12" />
  <parameter name="mpu_numOfDataRegion" value="8" />
  <parameter name="mpu_numOfInstRegion" value="8" />
  <parameter name="mpu_useLimit" value="false" />
  <parameter name="mpx_enabled" value="false" />
  <parameter name="mul_32_impl" value="3" />
  <parameter name="mul_64_impl" value="0" />
  <parameter name="mul_shift_choice" value="0" />
  <parameter name="ocimem_ramBlockType" value="Automatic" />
  <parameter name="ocimem_ramInit" value="false" />
  <parameter name="regfile_ramBlockType" value="Automatic" />
  <parameter name="register_file_por" value="false" />
  <parameter name="resetOffset" value="0" />
  <parameter name="resetSlave" value="ext_flash.avl_mem" />
  <parameter name="resetrequest_enabled" value="true" />
  <parameter name="setting_HBreakTest" value="false" />
  <parameter name="setting_HDLSimCachesCleared" value="true" />
  <parameter name="setting_activateMonitors" value="true" />
  <parameter name="setting_activateTestEndChecker" value="false" />
  <parameter name="setting_activateTrace" value="true" />
  <parameter name="setting_allow_break_inst" value="false" />
  <parameter name="setting_alwaysEncrypt" value="true" />
  <parameter name="setting_asic_add_scan_mode_input" value="false" />
  <parameter name="setting_asic_enabled" value="false" />
  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
  <parameter name="setting_asic_third_party_synthesis" value="false" />
  <parameter name="setting_avalonDebugPortPresent" value="false" />
  <parameter name="setting_bhtPtrSz" value="8" />
  <parameter name="setting_bigEndian" value="false" />
  <parameter name="setting_branchpredictiontype" value="Dynamic" />
  <parameter name="setting_breakslaveoveride" value="false" />
  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
  <parameter name="setting_dc_ecc_present" value="false" />
  <parameter name="setting_disable_tmr_inj" value="false" />
  <parameter name="setting_disableocitrace" value="false" />
  <parameter name="setting_dtcm_ecc_present" value="false" />
  <parameter name="setting_ecc_present" value="false" />
  <parameter name="setting_ecc_sim_test_ports" value="false" />
  <parameter name="setting_exportHostDebugPort" value="false" />
  <parameter name="setting_exportPCB" value="false" />
  <parameter name="setting_export_large_RAMs" value="false" />
  <parameter name="setting_exportdebuginfo" value="false" />
  <parameter name="setting_exportvectors" value="false" />
  <parameter name="setting_fast_register_read" value="false" />
  <parameter name="setting_ic_ecc_present" value="true" />
  <parameter name="setting_interruptControllerType" value="Internal" />
  <parameter name="setting_itcm_ecc_present" value="false" />
  <parameter name="setting_mmu_ecc_present" value="true" />
  <parameter name="setting_oci_export_jtag_signals" value="false" />
  <parameter name="setting_oci_version" value="1" />
  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
  <parameter name="setting_removeRAMinit" value="false" />
  <parameter name="setting_rf_ecc_present" value="true" />
  <parameter name="setting_shadowRegisterSets" value="0" />
  <parameter name="setting_showInternalSettings" value="false" />
  <parameter name="setting_showUnpublishedSettings" value="false" />
  <parameter name="setting_support31bitdcachebypass" value="true" />
  <parameter name="setting_tmr_output_disable" value="false" />
  <parameter name="setting_usedesignware" value="false" />
  <parameter name="shift_rot_impl" value="0" />
  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
  <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
  <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
  <parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
  <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
  <parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
  <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
  <parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
  <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
  <parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
  <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
  <parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
  <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
  <parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
  <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
  <parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
  <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
  <parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
  <parameter name="tmr_enabled" value="false" />
  <parameter name="tracefilename" value="" />
  <parameter name="userDefinedSettings" value="" />
 </module>
 <module
   name="ddr3_ram"
   kind="altera_mem_if_ddr3_emif"
   version="19.1"
   enabled="1">
  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
  <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
  <parameter name="AC_PACKAGE_DESKEW" value="false" />
  <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
  <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
  <parameter name="ADDR_ORDER" value="0" />
  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
  <parameter name="ADVANCED_CK_PHASES" value="false" />
  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
  <parameter name="AP_MODE" value="false" />
  <parameter name="AP_MODE_EN" value="0" />
  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
  <parameter name="AUTO_PD_CYCLES" value="0" />
  <parameter name="AUTO_POWERDN_EN" value="false" />
  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
  <parameter name="AVL_MAX_SIZE" value="4" />
  <parameter name="BYTE_ENABLE" value="true" />
  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
  <parameter name="CALIBRATION_MODE" value="Skip" />
  <parameter name="CALIB_REG_WIDTH" value="8" />
  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
  <parameter name="CFG_REORDER_DATA" value="true" />
  <parameter name="CFG_TCCD_NS" value="2.5" />
  <parameter name="COMMAND_PHASE" value="0.0" />
  <parameter name="CONTROLLER_LATENCY" value="5" />
  <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
  <parameter name="CPORT_TYPE_PORT">Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional</parameter>
  <parameter name="CTL_AUTOPCH_EN" value="false" />
  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
  <parameter name="CTL_CSR_ENABLED" value="false" />
  <parameter name="CTL_CSR_READ_ONLY" value="1" />
  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
  <parameter name="CTL_ECC_ENABLED" value="false" />
  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" />
  <parameter name="CTL_HRB_ENABLED" value="false" />
  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
  <parameter name="CTL_USR_REFRESH_EN" value="false" />
  <parameter name="CTL_ZQCAL_EN" value="false" />
  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
  <parameter name="DAT_DATA_WIDTH" value="32" />
  <parameter name="DEBUG_MODE" value="false" />
  <parameter name="DEVICE_DEPTH" value="1" />
  <parameter name="DEVICE_FAMILY_PARAM" value="" />
  <parameter name="DISABLE_CHILD_MESSAGING" value="false" />
  <parameter name="DISCRETE_FLY_BY" value="true" />
  <parameter name="DLL_SHARING_MODE" value="None" />
  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
  <parameter name="DUPLICATE_AC" value="false" />
  <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
  <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
  <parameter name="ENABLE_BONDING" value="false" />
  <parameter name="ENABLE_BURST_MERGE" value="false" />
  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
  <parameter name="ENABLE_ISS_PROBES" value="false" />
  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
  <parameter name="ENABLE_NON_DES_CAL" value="false" />
  <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
  <parameter name="ENABLE_USER_ECC" value="false" />
  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
  <parameter name="EXTRA_SETTINGS" value="" />
  <parameter name="FIX_READ_LATENCY" value="8" />
  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
  <parameter name="HARD_EMIF" value="false" />
  <parameter name="HCX_COMPAT_MODE" value="false" />
  <parameter name="HHP_HPS" value="false" />
  <parameter name="HHP_HPS_SIMULATION" value="false" />
  <parameter name="HHP_HPS_VERIFICATION" value="false" />
  <parameter name="HPS_PROTOCOL" value="DEFAULT" />
  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
  <parameter name="IS_ES_DEVICE" value="false" />
  <parameter name="LOCAL_ID_WIDTH" value="8" />
  <parameter name="LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
  <parameter name="MARGIN_VARIATION_TEST" value="false" />
  <parameter name="MAX_PENDING_RD_CMD" value="32" />
  <parameter name="MAX_PENDING_WR_CMD" value="16" />
  <parameter name="MEM_ASR" value="Manual" />
  <parameter name="MEM_ATCL" value="Disabled" />
  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
  <parameter name="MEM_BL" value="OTF" />
  <parameter name="MEM_BT" value="Sequential" />
  <parameter name="MEM_CK_PHASE" value="0.0" />
  <parameter name="MEM_CK_WIDTH" value="1" />
  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
  <parameter name="MEM_CLK_FREQ" value="300.0" />
  <parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
  <parameter name="MEM_CS_WIDTH" value="1" />
  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
  <parameter name="MEM_DLL_EN" value="true" />
  <parameter name="MEM_DQ_PER_DQS" value="8" />
  <parameter name="MEM_DQ_WIDTH" value="8" />
  <parameter name="MEM_DRV_STR" value="RZQ/6" />
  <parameter name="MEM_FORMAT" value="DISCRETE" />
  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
  <parameter name="MEM_IF_DQSN_EN" value="true" />
  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
  <parameter name="MEM_INIT_EN" value="false" />
  <parameter name="MEM_INIT_FILE" value="" />
  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
  <parameter name="MEM_PD" value="DLL off" />
  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
  <parameter name="MEM_ROW_ADDR_WIDTH" value="14" />
  <parameter name="MEM_RTT_NOM" value="ODT Disabled" />
  <parameter name="MEM_RTT_WR" value="Dynamic ODT off" />
  <parameter name="MEM_SRT" value="Normal" />
  <parameter name="MEM_TCL" value="5" />
  <parameter name="MEM_TFAW_NS" value="30.0" />
  <parameter name="MEM_TINIT_US" value="500" />
  <parameter name="MEM_TMRD_CK" value="4" />
  <parameter name="MEM_TRAS_NS" value="35.0" />
  <parameter name="MEM_TRCD_NS" value="13.75" />
  <parameter name="MEM_TREFI_US" value="7.8" />
  <parameter name="MEM_TRFC_NS" value="110.0" />
  <parameter name="MEM_TRP_NS" value="13.75" />
  <parameter name="MEM_TRRD_NS" value="6.0" />
  <parameter name="MEM_TRTP_NS" value="7.5" />
  <parameter name="MEM_TWR_NS" value="15.0" />
  <parameter name="MEM_TWTR" value="6" />
  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
  <parameter name="MEM_VENDOR" value="JEDEC" />
  <parameter name="MEM_VERBOSE" value="true" />
  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
  <parameter name="MEM_WTCL" value="5" />
  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
  <parameter name="MULTICAST_EN" value="false" />
  <parameter name="NEXTGEN" value="true" />
  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
  <parameter name="NUM_OF_PORTS" value="1" />
  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
  <parameter name="OCT_SHARING_MODE" value="None" />
  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
  <parameter name="PACKAGE_DESKEW" value="false" />
  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
  <parameter name="PHY_CSR_ENABLED" value="false" />
  <parameter name="PHY_ONLY" value="false" />
  <parameter name="PINGPONGPHY_EN" value="false" />
  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="PLL_CLK_PARAM_VALID" value="false" />
  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="PLL_LOCATION" value="Top_Bottom" />
  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="PLL_SHARING_MODE" value="None" />
  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="POWER_OF_TWO_BUS" value="false" />
  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
  <parameter name="RATE" value="Half" />
  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
  <parameter name="READ_FIFO_SIZE" value="8" />
  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
  <parameter name="REFRESH_INTERVAL" value="15000" />
  <parameter name="REF_CLK_FREQ" value="100.0" />
  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
  <parameter name="SEQUENCER_TYPE" value="NIOS" />
  <parameter name="SEQ_MODE" value="0" />
  <parameter name="SKIP_MEM_INIT" value="true" />
  <parameter name="SOPC_COMPAT_RESET" value="false" />
  <parameter name="SPEED_GRADE" value="6" />
  <parameter name="STARVE_LIMIT" value="10" />
  <parameter name="SYS_INFO_DEVICE_FAMILY" value="MAX 10" />
  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
  <parameter name="TIMING_BOARD_AC_SKEW" value="0.07801" />
  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="-0.04709" />
  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="-0.01152" />
  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.2443" />
  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.21929" />
  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.04246" />
  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.04429" />
  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="0.02286" />
  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.01806" />
  <parameter name="TIMING_BOARD_TDH" value="0.0" />
  <parameter name="TIMING_BOARD_TDS" value="0.0" />
  <parameter name="TIMING_BOARD_TIH" value="0.0" />
  <parameter name="TIMING_BOARD_TIS" value="0.0" />
  <parameter name="TIMING_TDH" value="45" />
  <parameter name="TIMING_TDQSCK" value="225" />
  <parameter name="TIMING_TDQSCKDL" value="1200" />
  <parameter name="TIMING_TDQSCKDM" value="900" />
  <parameter name="TIMING_TDQSCKDS" value="450" />
  <parameter name="TIMING_TDQSQ" value="100" />
  <parameter name="TIMING_TDQSS" value="0.27" />
  <parameter name="TIMING_TDS" value="10" />
  <parameter name="TIMING_TDSH" value="0.18" />
  <parameter name="TIMING_TDSS" value="0.18" />
  <parameter name="TIMING_TIH" value="120" />
  <parameter name="TIMING_TIS" value="170" />
  <parameter name="TIMING_TQH" value="0.38" />
  <parameter name="TIMING_TQSH" value="0.4" />
  <parameter name="TRACKING_ERROR_TEST" value="false" />
  <parameter name="TRACKING_WATCH_TEST" value="false" />
  <parameter name="TREFI" value="35100" />
  <parameter name="TRFC" value="350" />
  <parameter name="USER_DEBUG_LEVEL" value="1" />
  <parameter name="USE_AXI_ADAPTOR" value="false" />
  <parameter name="USE_FAKE_PHY" value="false" />
  <parameter name="USE_MEM_CLK_FREQ" value="false" />
  <parameter name="USE_MM_ADAPTOR" value="true" />
  <parameter name="USE_SEQUENCER_BFM" value="false" />
  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
 </module>
 <module
   name="ddr3_ram_resetn"
   kind="altera_reset_bridge"
   version="19.1"
   enabled="1">
  <parameter name="ACTIVE_LOW_RESET" value="1" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
  <parameter name="NUM_RESET_OUTPUTS" value="1" />
  <parameter name="SYNCHRONOUS_EDGES" value="none" />
  <parameter name="USE_RESET_REQUEST" value="0" />
 </module>
 <module
   name="debug_uart"
   kind="altera_avalon_uart"
   version="19.1"
   enabled="1">
  <parameter name="baud" value="115200" />
  <parameter name="clockRate" value="50000000" />
  <parameter name="dataBits" value="8" />
  <parameter name="fixedBaud" value="true" />
  <parameter name="parity" value="NONE" />
  <parameter name="simCharStream" value="" />
  <parameter name="simInteractiveInputEnable" value="false" />
  <parameter name="simInteractiveOutputEnable" value="false" />
  <parameter name="simTrueBaud" value="false" />
  <parameter name="stopBits" value="1" />
  <parameter name="syncRegDepth" value="2" />
  <parameter name="useCtsRts" value="false" />
  <parameter name="useEopRegister" value="false" />
  <parameter name="useRelativePathForSimFile" value="false" />
 </module>
 <module
   name="descriptor_memory"
   kind="altera_avalon_onchip_memory2"
   version="19.1"
   enabled="1">
  <parameter name="allowInSystemMemoryContentEditor" value="false" />
  <parameter name="autoInitializationFileName">$${FILENAME}_descriptor_memory</parameter>
  <parameter name="blockType" value="AUTO" />
  <parameter name="copyInitFile" value="false" />
  <parameter name="dataWidth" value="32" />
  <parameter name="dataWidth2" value="32" />
  <parameter name="deviceFamily" value="MAX 10" />
  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
  <parameter name="dualPort" value="false" />
  <parameter name="ecc_enabled" value="false" />
  <parameter name="enPRInitMode" value="false" />
  <parameter name="enableDiffWidth" value="false" />
  <parameter name="initMemContent" value="false" />
  <parameter name="initializationFileName">/data/acastill/simple_socket_10M50/software/niosII_simple_socket_server/mem_init/q_sys_descriptor_memory.hex</parameter>
  <parameter name="instanceID" value="NONE" />
  <parameter name="memorySize" value="8192" />
  <parameter name="readDuringWriteMode" value="DONT_CARE" />
  <parameter name="resetrequest_enabled" value="true" />
  <parameter name="simAllowMRAMContentsFile" value="false" />
  <parameter name="simMemInitOnlyFilename" value="0" />
  <parameter name="singleClockOperation" value="false" />
  <parameter name="slave1Latency" value="1" />
  <parameter name="slave2Latency" value="1" />
  <parameter name="useNonDefaultInitFile" value="false" />
  <parameter name="useShallowMemBlocks" value="false" />
  <parameter name="writable" value="true" />
 </module>
 <module name="enet_pll" kind="altpll" version="19.1" enabled="1">
  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
  <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
  <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
  <parameter name="BANDWIDTH" value="" />
  <parameter name="BANDWIDTH_TYPE" value="AUTO" />
  <parameter name="CLK0_DIVIDE_BY" value="2" />
  <parameter name="CLK0_DUTY_CYCLE" value="50" />
  <parameter name="CLK0_MULTIPLY_BY" value="5" />
  <parameter name="CLK0_PHASE_SHIFT" value="0" />
  <parameter name="CLK1_DIVIDE_BY" value="2" />
  <parameter name="CLK1_DUTY_CYCLE" value="50" />
  <parameter name="CLK1_MULTIPLY_BY" value="1" />
  <parameter name="CLK1_PHASE_SHIFT" value="0" />
  <parameter name="CLK2_DIVIDE_BY" value="20" />
  <parameter name="CLK2_DUTY_CYCLE" value="50" />
  <parameter name="CLK2_MULTIPLY_BY" value="1" />
  <parameter name="CLK2_PHASE_SHIFT" value="0" />
  <parameter name="CLK3_DIVIDE_BY" value="2" />
  <parameter name="CLK3_DUTY_CYCLE" value="50" />
  <parameter name="CLK3_MULTIPLY_BY" value="5" />
  <parameter name="CLK3_PHASE_SHIFT" value="-3000" />
  <parameter name="CLK4_DIVIDE_BY" value="2" />
  <parameter name="CLK4_DUTY_CYCLE" value="50" />
  <parameter name="CLK4_MULTIPLY_BY" value="1" />
  <parameter name="CLK4_PHASE_SHIFT" value="-10000" />
  <parameter name="CLK5_DIVIDE_BY" value="" />
  <parameter name="CLK5_DUTY_CYCLE" value="" />
  <parameter name="CLK5_MULTIPLY_BY" value="" />
  <parameter name="CLK5_PHASE_SHIFT" value="" />
  <parameter name="CLK6_DIVIDE_BY" value="" />
  <parameter name="CLK6_DUTY_CYCLE" value="" />
  <parameter name="CLK6_MULTIPLY_BY" value="" />
  <parameter name="CLK6_PHASE_SHIFT" value="" />
  <parameter name="CLK7_DIVIDE_BY" value="" />
  <parameter name="CLK7_DUTY_CYCLE" value="" />
  <parameter name="CLK7_MULTIPLY_BY" value="" />
  <parameter name="CLK7_PHASE_SHIFT" value="" />
  <parameter name="CLK8_DIVIDE_BY" value="" />
  <parameter name="CLK8_DUTY_CYCLE" value="" />
  <parameter name="CLK8_MULTIPLY_BY" value="" />
  <parameter name="CLK8_PHASE_SHIFT" value="" />
  <parameter name="CLK9_DIVIDE_BY" value="" />
  <parameter name="CLK9_DUTY_CYCLE" value="" />
  <parameter name="CLK9_MULTIPLY_BY" value="" />
  <parameter name="CLK9_PHASE_SHIFT" value="" />
  <parameter name="COMPENSATE_CLOCK" value="CLK0" />
  <parameter name="DOWN_SPREAD" value="" />
  <parameter name="DPA_DIVIDER" value="" />
  <parameter name="DPA_DIVIDE_BY" value="" />
  <parameter name="DPA_MULTIPLY_BY" value="" />
  <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
  <parameter name="EXTCLK0_DIVIDE_BY" value="" />
  <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
  <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
  <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
  <parameter name="EXTCLK1_DIVIDE_BY" value="" />
  <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
  <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
  <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
  <parameter name="EXTCLK2_DIVIDE_BY" value="" />
  <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
  <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
  <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
  <parameter name="EXTCLK3_DIVIDE_BY" value="" />
  <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
  <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
  <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
  <parameter name="FEEDBACK_SOURCE" value="" />
  <parameter name="GATE_LOCK_COUNTER" value="" />
  <parameter name="GATE_LOCK_SIGNAL" value="" />
  <parameter name="HIDDEN_CONSTANTS">CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_USED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 2 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT -3000 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 2 CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 1 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NO_COMPENSATION CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT -10000 CT#INCLK0_INPUT_FREQUENCY 20000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 2 CT#CLK1_DIVIDE_BY 2 CT#CLK3_MULTIPLY_BY 5 CT#PORT_LOCKED PORT_USED</parameter>
  <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
  <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
  <parameter name="HIDDEN_IF_PORTS">IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}</parameter>
  <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
  <parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#CLK4_DIVIDE_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
  <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
  <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 0 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 0 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 0 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 100.00000000 PT#OUTPUT_FREQ3 100.00000000 PT#OUTPUT_FREQ2 2.50000000 PT#OUTPUT_FREQ1 25.00000000 PT#OUTPUT_FREQ0 125.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 -90.00000000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 -135.00000000 PT#DIV_FACTOR4 2 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 2 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR1 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 1 PT#USE_CLKENA4 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 25.000000 PT#EFF_OUTPUT_FREQ_VALUE3 125.000000 PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 125.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK4 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 5 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1418882816093282.mif PT#ACTIVECLK_CHECK 0</parameter>
  <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
  <parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
  <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
  <parameter name="INTENDED_DEVICE_FAMILY" value="MAX 10" />
  <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
  <parameter name="LOCK_HIGH" value="" />
  <parameter name="LOCK_LOW" value="" />
  <parameter name="OPERATION_MODE" value="NO_COMPENSATION" />
  <parameter name="PLL_TYPE" value="AUTO" />
  <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
  <parameter name="PORT_ARESET" value="PORT_UNUSED" />
  <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
  <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
  <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
  <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
  <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
  <parameter name="PORT_ENABLE0" value="" />
  <parameter name="PORT_ENABLE1" value="" />
  <parameter name="PORT_FBIN" value="PORT_UNUSED" />
  <parameter name="PORT_FBOUT" value="" />
  <parameter name="PORT_INCLK0" value="PORT_USED" />
  <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
  <parameter name="PORT_LOCKED" value="PORT_USED" />
  <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
  <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
  <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
  <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
  <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
  <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
  <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
  <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
  <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
  <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
  <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
  <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
  <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
  <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
  <parameter name="PORT_SCLKOUT0" value="" />
  <parameter name="PORT_SCLKOUT1" value="" />
  <parameter name="PORT_VCOOVERRANGE" value="" />
  <parameter name="PORT_VCOUNDERRANGE" value="" />
  <parameter name="PORT_clk0" value="PORT_USED" />
  <parameter name="PORT_clk1" value="PORT_USED" />
  <parameter name="PORT_clk2" value="PORT_USED" />
  <parameter name="PORT_clk3" value="PORT_USED" />
  <parameter name="PORT_clk4" value="PORT_USED" />
  <parameter name="PORT_clk5" value="PORT_UNUSED" />
  <parameter name="PORT_clk6" value="" />
  <parameter name="PORT_clk7" value="" />
  <parameter name="PORT_clk8" value="" />
  <parameter name="PORT_clk9" value="" />
  <parameter name="PORT_clkena0" value="PORT_UNUSED" />
  <parameter name="PORT_clkena1" value="PORT_UNUSED" />
  <parameter name="PORT_clkena2" value="PORT_UNUSED" />
  <parameter name="PORT_clkena3" value="PORT_UNUSED" />
  <parameter name="PORT_clkena4" value="PORT_UNUSED" />
  <parameter name="PORT_clkena5" value="PORT_UNUSED" />
  <parameter name="PORT_extclk0" value="PORT_UNUSED" />
  <parameter name="PORT_extclk1" value="PORT_UNUSED" />
  <parameter name="PORT_extclk2" value="PORT_UNUSED" />
  <parameter name="PORT_extclk3" value="PORT_UNUSED" />
  <parameter name="PORT_extclkena0" value="" />
  <parameter name="PORT_extclkena1" value="" />
  <parameter name="PORT_extclkena2" value="" />
  <parameter name="PORT_extclkena3" value="" />
  <parameter name="PRIMARY_CLOCK" value="" />
  <parameter name="QUALIFY_CONF_DONE" value="" />
  <parameter name="SCAN_CHAIN" value="" />
  <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
  <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
  <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
  <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
  <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
  <parameter name="SKIP_VCO" value="" />
  <parameter name="SPREAD_FREQUENCY" value="" />
  <parameter name="SWITCH_OVER_COUNTER" value="" />
  <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
  <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
  <parameter name="SWITCH_OVER_TYPE" value="" />
  <parameter name="USING_FBMIMICBIDIR_PORT" value="" />
  <parameter name="VALID_LOCK_MULTIPLIER" value="" />
  <parameter name="VCO_DIVIDE_BY" value="" />
  <parameter name="VCO_FREQUENCY_CONTROL" value="" />
  <parameter name="VCO_MULTIPLY_BY" value="" />
  <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
  <parameter name="WIDTH_CLOCK" value="5" />
  <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
 </module>
 <module name="eth_tse" kind="altera_eth_tse" version="19.1" enabled="1">
  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
  <parameter name="XCVR_RCFG_JTAG_ENABLE" value="0" />
  <parameter name="XCVR_SET_CAPABILITY_REG_ENABLE" value="0" />
  <parameter name="XCVR_SET_CSR_SOFT_LOGIC_ENABLE" value="0" />
  <parameter name="XCVR_SET_PRBS_SOFT_LOGIC_ENABLE" value="0" />
  <parameter name="XCVR_SET_USER_IDENTIFIER" value="0" />
  <parameter name="core_variation" value="MAC_ONLY" />
  <parameter name="deviceFamilyName" value="MAX 10" />
  <parameter name="eg_addr" value="11" />
  <parameter name="ena_hash" value="false" />
  <parameter name="enable_alt_reconfig" value="false" />
  <parameter name="enable_ecc" value="false" />
  <parameter name="enable_ena" value="32" />
  <parameter name="enable_gmii_loopback" value="true" />
  <parameter name="enable_hd_logic" value="true" />
  <parameter name="enable_mac_flow_ctrl" value="false" />
  <parameter name="enable_mac_vlan" value="false" />
  <parameter name="enable_magic_detect" value="true" />
  <parameter name="enable_ptp_1step" value="false" />
  <parameter name="enable_sgmii" value="true" />
  <parameter name="enable_shift16" value="true" />
  <parameter name="enable_sup_addr" value="false" />
  <parameter name="enable_timestamping" value="false" />
  <parameter name="enable_use_internal_fifo" value="true" />
  <parameter name="export_pwrdn" value="false" />
  <parameter name="ext_stat_cnt_ena" value="false" />
  <parameter name="ifGMII" value="RGMII" />
  <parameter name="ing_addr" value="11" />
  <parameter name="max_channels" value="1" />
  <parameter name="mdio_clk_div" value="40" />
  <parameter name="nf_phyip_rcfg_enable" value="true" />
  <parameter name="phy_identifier" value="0" />
  <parameter name="phyip_en_synce_support" value="false" />
  <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
  <parameter name="phyip_pll_type" value="CMU" />
  <parameter name="phyip_pma_bonding_mode" value="x1" />
  <parameter name="starting_channel_number" value="0" />
  <parameter name="stat_cnt_ena" value="true" />
  <parameter name="transceiver_type" value="NONE" />
  <parameter name="tstamp_fp_width" value="4" />
  <parameter name="useMDIO" value="true" />
  <parameter name="use_mac_clken" value="false" />
  <parameter name="use_misc_ports" value="true" />
 </module>
 <module
   name="ext_flash"
   kind="altera_generic_quad_spi_controller"
   version="19.1"
   enabled="1">
  <parameter name="CHIP_SELS" value="1" />
  <parameter name="DEVICE_FAMILY" value="MAX 10" />
  <parameter name="FLASH_TYPE" value="Micron512" />
  <parameter name="IO_MODE" value="QUAD" />
  <parameter name="UNIQUE_ID">$${FILENAME}_ext_flash</parameter>
  <parameter name="clkFreq" value="0" />
  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
 </module>
 <module
   name="ext_flash_clock_bridge"
   kind="altera_clock_bridge"
   version="19.1"
   enabled="1">
  <parameter name="DERIVED_CLOCK_RATE" value="0" />
  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
 </module>
 <module
   name="frame_timer"
   kind="altera_avalon_timer"
   version="19.1"
   enabled="1">
  <parameter name="alwaysRun" value="false" />
  <parameter name="counterSize" value="32" />
  <parameter name="fixedPeriod" value="false" />
  <parameter name="period" value="5000" />
  <parameter name="periodUnits" value="CLOCKS" />
  <parameter name="resetOutput" value="false" />
  <parameter name="snapshot" value="false" />
  <parameter name="systemFrequency" value="50000000" />
  <parameter name="timeoutPulseOutput" value="true" />
  <parameter name="watchdogPulse" value="2" />
 </module>
 <module
   name="glad"
   kind="altera_avalon_onchip_memory2"
   version="19.1"
   enabled="0">
  <parameter name="allowInSystemMemoryContentEditor" value="true" />
  <parameter name="autoInitializationFileName" value="q_sys_glad" />
  <parameter name="blockType" value="AUTO" />
  <parameter name="copyInitFile" value="false" />
  <parameter name="dataWidth" value="16" />
  <parameter name="dataWidth2" value="32" />
  <parameter name="deviceFamily" value="MAX 10" />
  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
  <parameter name="dualPort" value="false" />
  <parameter name="ecc_enabled" value="false" />
  <parameter name="enPRInitMode" value="false" />
  <parameter name="enableDiffWidth" value="false" />
  <parameter name="initMemContent" value="false" />
  <parameter name="initializationFileName" value="onchip_mem.hex" />
  <parameter name="instanceID" value="glad" />
  <parameter name="memorySize" value="640" />
  <parameter name="readDuringWriteMode" value="DONT_CARE" />
  <parameter name="resetrequest_enabled" value="false" />
  <parameter name="simAllowMRAMContentsFile" value="false" />
  <parameter name="simMemInitOnlyFilename" value="0" />
  <parameter name="singleClockOperation" value="false" />
  <parameter name="slave1Latency" value="1" />
  <parameter name="slave2Latency" value="1" />
  <parameter name="useNonDefaultInitFile" value="false" />
  <parameter name="useShallowMemBlocks" value="false" />
  <parameter name="writable" value="true" />
 </module>
 <module name="msgdma_rx" kind="altera_msgdma" version="19.1" enabled="1">
  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP"><![CDATA[<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>]]></parameter>
  <parameter
     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
     value="AddressWidth = 29" />
  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP"><![CDATA[<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>]]></parameter>
  <parameter
     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
     value="AddressWidth = 29" />
  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
  <parameter name="AUTO_MM_READ_ADDRESS_MAP" value="" />
  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = -1" />
  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP"><![CDATA[<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' /></address-map>]]></parameter>
  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = 28" />
  <parameter name="BURST_ENABLE" value="0" />
  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
  <parameter name="CHANNEL_ENABLE" value="0" />
  <parameter name="CHANNEL_WIDTH" value="8" />
  <parameter name="DATA_FIFO_DEPTH" value="32" />
  <parameter name="DATA_WIDTH" value="32" />
  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="8" />
  <parameter name="ENHANCED_FEATURES" value="0" />
  <parameter name="ERROR_ENABLE" value="1" />
  <parameter name="ERROR_WIDTH" value="6" />
  <parameter name="EXPOSE_ST_PORT" value="0" />
  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
  <parameter name="MAX_BURST_COUNT" value="2" />
  <parameter name="MAX_BYTE" value="2048" />
  <parameter name="MAX_STRIDE" value="1" />
  <parameter name="MODE" value="2" />
  <parameter name="PACKET_ENABLE" value="1" />
  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
  <parameter name="PREFETCHER_ENABLE" value="1" />
  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
  <parameter name="RESPONSE_PORT" value="2" />
  <parameter name="STRIDE_ENABLE" value="0" />
  <parameter name="TRANSFER_TYPE" value="Aligned Accesses" />
  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
 </module>
 <module name="msgdma_tx" kind="altera_msgdma" version="19.1" enabled="1">
  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP"><![CDATA[<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>]]></parameter>
  <parameter
     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
     value="AddressWidth = 29" />
  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP"><![CDATA[<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>]]></parameter>
  <parameter
     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
     value="AddressWidth = 29" />
  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
  <parameter name="AUTO_MM_READ_ADDRESS_MAP"><![CDATA[<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' /></address-map>]]></parameter>
  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = 28" />
  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP" value="" />
  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = -1" />
  <parameter name="BURST_ENABLE" value="0" />
  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
  <parameter name="CHANNEL_ENABLE" value="0" />
  <parameter name="CHANNEL_WIDTH" value="8" />
  <parameter name="DATA_FIFO_DEPTH" value="32" />
  <parameter name="DATA_WIDTH" value="32" />
  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="8" />
  <parameter name="ENHANCED_FEATURES" value="0" />
  <parameter name="ERROR_ENABLE" value="1" />
  <parameter name="ERROR_WIDTH" value="1" />
  <parameter name="EXPOSE_ST_PORT" value="0" />
  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
  <parameter name="MAX_BURST_COUNT" value="2" />
  <parameter name="MAX_BYTE" value="2048" />
  <parameter name="MAX_STRIDE" value="1" />
  <parameter name="MODE" value="1" />
  <parameter name="PACKET_ENABLE" value="1" />
  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
  <parameter name="PREFETCHER_ENABLE" value="1" />
  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
  <parameter name="RESPONSE_PORT" value="2" />
  <parameter name="STRIDE_ENABLE" value="0" />
  <parameter name="TRANSFER_TYPE" value="Aligned Accesses" />
  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
 </module>
 <module
   name="onchip_flash"
   kind="altera_onchip_flash"
   version="19.1"
   enabled="1">
  <parameter name="AUTO_CLOCK_RATE" value="50000000" />
  <parameter name="CLOCK_FREQUENCY" value="50.0" />
  <parameter name="CONFIGURATION_MODE">Single Uncompressed Image</parameter>
  <parameter name="CONFIGURATION_SCHEME">Internal Configuration</parameter>
  <parameter name="DATA_INTERFACE" value="Parallel" />
  <parameter name="DEVICE_FAMILY" value="MAX 10" />
  <parameter name="PART_NAME" value="10M50DAF484C6GES" />
  <parameter name="READ_BURST_COUNT" value="8" />
  <parameter name="READ_BURST_MODE" value="Incrementing" />
  <parameter name="SECTOR_ACCESS_MODE">Read and write,Read and write,Read and write,Read and write,Read and write</parameter>
  <parameter name="autoInitializationFileName">$${FILENAME}_onchip_flash</parameter>
  <parameter name="initFlashContent" value="false" />
  <parameter name="initializationFileName">D:/projekty/HIT/v2.0/fpga/software/hit20_v3/mem_init/q_sys_onchip_flash.hex</parameter>
  <parameter name="initializationFileNameForSim">altera_onchip_flash.dat</parameter>
  <parameter name="useNonDefaultInitFile" value="false" />
 </module>
 <module
   name="onchip_ram"
   kind="altera_avalon_onchip_memory2"
   version="19.1"
   enabled="0">
  <parameter name="allowInSystemMemoryContentEditor" value="false" />
  <parameter name="autoInitializationFileName" value="q_sys_onchip_ram" />
  <parameter name="blockType" value="AUTO" />
  <parameter name="copyInitFile" value="false" />
  <parameter name="dataWidth" value="32" />
  <parameter name="dataWidth2" value="32" />
  <parameter name="deviceFamily" value="MAX 10" />
  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
  <parameter name="dualPort" value="false" />
  <parameter name="ecc_enabled" value="false" />
  <parameter name="enPRInitMode" value="false" />
  <parameter name="enableDiffWidth" value="false" />
  <parameter name="initMemContent" value="false" />
  <parameter name="initializationFileName" value="onchip_mem.hex" />
  <parameter name="instanceID" value="NONE" />
  <parameter name="memorySize" value="65536" />
  <parameter name="readDuringWriteMode" value="DONT_CARE" />
  <parameter name="resetrequest_enabled" value="true" />
  <parameter name="simAllowMRAMContentsFile" value="false" />
  <parameter name="simMemInitOnlyFilename" value="0" />
  <parameter name="singleClockOperation" value="false" />
  <parameter name="slave1Latency" value="1" />
  <parameter name="slave2Latency" value="1" />
  <parameter name="useNonDefaultInitFile" value="false" />
  <parameter name="useShallowMemBlocks" value="false" />
  <parameter name="writable" value="true" />
 </module>
 <module name="output_pio" kind="altera_avalon_pio" version="19.1" enabled="1">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="true" />
  <parameter name="captureEdge" value="false" />
  <parameter name="clockRate" value="50000000" />
  <parameter name="direction" value="Output" />
  <parameter name="edgeType" value="RISING" />
  <parameter name="generateIRQ" value="false" />
  <parameter name="irqType" value="LEVEL" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="8" />
 </module>
 <module name="sensor_interface" kind="sensor_recon" version="1" enabled="1" />
 <module name="sys_clk" kind="clock_source" version="19.1" enabled="1">
  <parameter name="clockFrequency" value="50000000" />
  <parameter name="clockFrequencyKnown" value="true" />
  <parameter name="inputClockFrequency" value="0" />
  <parameter name="resetSynchronousEdges" value="NONE" />
 </module>
 <module
   name="sys_clk_timer"
   kind="altera_avalon_timer"
   version="19.1"
   enabled="1">
  <parameter name="alwaysRun" value="false" />
  <parameter name="counterSize" value="32" />
  <parameter name="fixedPeriod" value="false" />
  <parameter name="period" value="10" />
  <parameter name="periodUnits" value="MSEC" />
  <parameter name="resetOutput" value="false" />
  <parameter name="snapshot" value="true" />
  <parameter name="systemFrequency" value="50000000" />
  <parameter name="timeoutPulseOutput" value="false" />
  <parameter name="watchdogPulse" value="2" />
 </module>
 <module
   name="sysid"
   kind="altera_avalon_sysid_qsys"
   version="19.1"
   enabled="1">
  <parameter name="id" value="-87110914" />
 </module>
 <module name="tx_multiplexer" kind="multiplexer" version="19.1" enabled="1">
  <parameter name="bitsPerSymbol" value="8" />
  <parameter name="errorWidth" value="1" />
  <parameter name="numInputInterfaces" value="2" />
  <parameter name="outChannelWidth" value="1" />
  <parameter name="packetScheduling" value="true" />
  <parameter name="schedulingSize" value="512" />
  <parameter name="symbolsPerBeat" value="4" />
  <parameter name="useHighBitsOfChannel" value="true" />
  <parameter name="usePackets" value="true" />
 </module>
 <module name="udp_generator" kind="udp_generator" version="1.0" enabled="1" />
 <connection
   kind="avalon"
   version="19.1"
   start="sensor_interface.calibration_ram_interface"
   end="calibration_ram.s2">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0000" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.data_master"
   end="ddr3_ram.avl">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x08000000" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.data_master"
   end="ext_flash.avl_csr">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18403d20" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.data_master"
   end="ext_flash.avl_mem">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x14000000" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.data_master"
   end="eth_tse.control_port">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18403000" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.data_master"
   end="sysid.control_slave">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18403d68" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.data_master"
   end="msgdma_tx.csr">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18403d00" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.data_master"
   end="msgdma_rx.csr">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18403ce0" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.data_master"
   end="onchip_flash.csr">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18403d60" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.data_master"
   end="udp_generator.csr">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18403cc0" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.data_master"
   end="sensor_interface.csr">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18403d50" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.data_master"
   end="onchip_flash.data">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18200000" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.data_master"
   end="cpu.debug_mem_slave">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18402800" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.data_master"
   end="msgdma_tx.prefetcher_csr">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18403ca0" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.data_master"
   end="msgdma_rx.prefetcher_csr">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18403c80" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.data_master"
   end="descriptor_memory.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18400000" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.data_master"
   end="sys_clk_timer.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18403c60" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.data_master"
   end="output_pio.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18403c40" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.data_master"
   end="button_pio.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18403d40" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.data_master"
   end="debug_uart.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18403c20" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.data_master"
   end="frame_timer.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18403c00" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.data_master"
   end="onchip_ram.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18110000" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.data_master"
   end="calibration_ram.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18403400" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection kind="avalon" version="19.1" start="cpu.data_master" end="glad.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18403800" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="msgdma_tx.descriptor_read_master"
   end="descriptor_memory.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18400000" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="msgdma_rx.descriptor_read_master"
   end="descriptor_memory.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18400000" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="msgdma_tx.descriptor_write_master"
   end="descriptor_memory.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18400000" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="msgdma_rx.descriptor_write_master"
   end="descriptor_memory.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18400000" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.instruction_master"
   end="ddr3_ram.avl">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x08000000" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.instruction_master"
   end="ext_flash.avl_mem">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x14000000" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.instruction_master"
   end="onchip_flash.data">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18200000" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.instruction_master"
   end="cpu.debug_mem_slave">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18402800" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="cpu.instruction_master"
   end="onchip_ram.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18110000" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="msgdma_tx.mm_read"
   end="ddr3_ram.avl">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x08000000" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="msgdma_tx.mm_read"
   end="onchip_ram.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18110000" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="msgdma_rx.mm_write"
   end="ddr3_ram.avl">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x08000000" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon"
   version="19.1"
   start="msgdma_rx.mm_write"
   end="onchip_ram.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x18110000" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection
   kind="avalon_streaming"
   version="19.1"
   start="sensor_interface.data_out"
   end="udp_generator.data_in" />
 <connection
   kind="avalon_streaming"
   version="19.1"
   start="udp_generator.data_out"
   end="tx_multiplexer.in1" />
 <connection
   kind="avalon_streaming"
   version="19.1"
   start="tx_multiplexer.out"
   end="channel_adapter_0.in" />
 <connection
   kind="avalon_streaming"
   version="19.1"
   start="channel_adapter_0.out"
   end="eth_tse.transmit" />
 <connection
   kind="avalon_streaming"
   version="19.1"
   start="eth_tse.receive"
   end="msgdma_rx.st_sink" />
 <connection
   kind="avalon_streaming"
   version="19.1"
   start="msgdma_tx.st_source"
   end="tx_multiplexer.in0" />
 <connection kind="clock" version="19.1" start="sys_clk.clk" end="sysid.clk" />
 <connection
   kind="clock"
   version="19.1"
   start="sys_clk.clk"
   end="sys_clk_timer.clk" />
 <connection kind="clock" version="19.1" start="sys_clk.clk" end="cpu.clk" />
 <connection kind="clock" version="19.1" start="sys_clk.clk" end="output_pio.clk" />
 <connection kind="clock" version="19.1" start="sys_clk.clk" end="button_pio.clk" />
 <connection kind="clock" version="19.1" start="sys_clk.clk" end="debug_uart.clk" />
 <connection
   kind="clock"
   version="19.1"
   start="sys_clk.clk"
   end="onchip_flash.clk" />
 <connection
   kind="clock"
   version="19.1"
   start="sys_clk.clk"
   end="tx_multiplexer.clk" />
 <connection
   kind="clock"
   version="19.1"
   start="sys_clk.clk"
   end="channel_adapter_0.clk" />
 <connection
   kind="clock"
   version="19.1"
   start="sys_clk.clk"
   end="udp_generator.clk" />
 <connection kind="clock" version="19.1" start="sys_clk.clk" end="frame_timer.clk" />
 <connection
   kind="clock"
   version="19.1"
   start="sys_clk.clk"
   end="sensor_interface.clk" />
 <connection
   kind="clock"
   version="19.1"
   start="sys_clk.clk"
   end="descriptor_memory.clk1" />
 <connection kind="clock" version="19.1" start="sys_clk.clk" end="onchip_ram.clk1" />
 <connection
   kind="clock"
   version="19.1"
   start="sys_clk.clk"
   end="calibration_ram.clk1" />
 <connection kind="clock" version="19.1" start="sys_clk.clk" end="glad.clk1" />
 <connection
   kind="clock"
   version="19.1"
   start="sys_clk.clk"
   end="calibration_ram.clk2" />
 <connection kind="clock" version="19.1" start="sys_clk.clk" end="msgdma_tx.clock" />
 <connection kind="clock" version="19.1" start="sys_clk.clk" end="msgdma_rx.clock" />
 <connection
   kind="clock"
   version="19.1"
   start="sys_clk.clk"
   end="eth_tse.control_port_clock_connection" />
 <connection
   kind="clock"
   version="19.1"
   start="sys_clk.clk"
   end="enet_pll.inclk_interface" />
 <connection
   kind="clock"
   version="19.1"
   start="sys_clk.clk"
   end="altpll_shift.inclk_interface" />
 <connection
   kind="clock"
   version="19.1"
   start="sys_clk.clk"
   end="eth_tse.receive_clock_connection" />
 <connection
   kind="clock"
   version="19.1"
   start="sys_clk.clk"
   end="eth_tse.transmit_clock_connection" />
 <connection
   kind="clock"
   version="19.1"
   start="ext_flash_clock_bridge.out_clk"
   end="ext_flash.clock_sink" />
 <connection
   kind="interrupt"
   version="19.1"
   start="cpu.irq"
   end="msgdma_tx.csr_irq">
  <parameter name="irqNumber" value="2" />
 </connection>
 <connection
   kind="interrupt"
   version="19.1"
   start="cpu.irq"
   end="msgdma_rx.csr_irq">
  <parameter name="irqNumber" value="3" />
 </connection>
 <connection
   kind="interrupt"
   version="19.1"
   start="cpu.irq"
   end="ext_flash.interrupt_sender">
  <parameter name="irqNumber" value="5" />
 </connection>
 <connection
   kind="interrupt"
   version="19.1"
   start="cpu.irq"
   end="sys_clk_timer.irq">
  <parameter name="irqNumber" value="0" />
 </connection>
 <connection kind="interrupt" version="19.1" start="cpu.irq" end="debug_uart.irq">
  <parameter name="irqNumber" value="4" />
 </connection>
 <connection
   kind="reset"
   version="19.1"
   start="sys_clk.clk_reset"
   end="onchip_flash.nreset" />
 <connection
   kind="reset"
   version="19.1"
   start="sys_clk.clk_reset"
   end="sys_clk_timer.reset" />
 <connection
   kind="reset"
   version="19.1"
   start="sys_clk.clk_reset"
   end="sysid.reset" />
 <connection kind="reset" version="19.1" start="sys_clk.clk_reset" end="cpu.reset" />
 <connection
   kind="reset"
   version="19.1"
   start="sys_clk.clk_reset"
   end="output_pio.reset" />
 <connection
   kind="reset"
   version="19.1"
   start="sys_clk.clk_reset"
   end="ext_flash.reset" />
 <connection
   kind="reset"
   version="19.1"
   start="sys_clk.clk_reset"
   end="button_pio.reset" />
 <connection
   kind="reset"
   version="19.1"
   start="sys_clk.clk_reset"
   end="debug_uart.reset" />
 <connection
   kind="reset"
   version="19.1"
   start="sys_clk.clk_reset"
   end="tx_multiplexer.reset" />
 <connection
   kind="reset"
   version="19.1"
   start="sys_clk.clk_reset"
   end="channel_adapter_0.reset" />
 <connection
   kind="reset"
   version="19.1"
   start="sys_clk.clk_reset"
   end="frame_timer.reset" />
 <connection
   kind="reset"
   version="19.1"
   start="sys_clk.clk_reset"
   end="descriptor_memory.reset1" />
 <connection
   kind="reset"
   version="19.1"
   start="sys_clk.clk_reset"
   end="onchip_ram.reset1" />
 <connection
   kind="reset"
   version="19.1"
   start="sys_clk.clk_reset"
   end="calibration_ram.reset1" />
 <connection
   kind="reset"
   version="19.1"
   start="sys_clk.clk_reset"
   end="glad.reset1" />
 <connection
   kind="reset"
   version="19.1"
   start="sys_clk.clk_reset"
   end="calibration_ram.reset2" />
 <connection
   kind="reset"
   version="19.1"
   start="sys_clk.clk_reset"
   end="eth_tse.reset_connection" />
 <connection
   kind="reset"
   version="19.1"
   start="sys_clk.clk_reset"
   end="msgdma_tx.reset_n" />
 <connection
   kind="reset"
   version="19.1"
   start="sys_clk.clk_reset"
   end="msgdma_rx.reset_n" />
 <connection
   kind="reset"
   version="19.1"
   start="sys_clk.clk_reset"
   end="udp_generator.rst" />
 <connection
   kind="reset"
   version="19.1"
   start="sys_clk.clk_reset"
   end="sensor_interface.rst" />
 <connection
   kind="reset"
   version="19.1"
   start="cpu.debug_reset_request"
   end="ddr3_ram.global_reset" />
 <connection
   kind="reset"
   version="19.1"
   start="cpu.debug_reset_request"
   end="ext_flash.reset" />
 <connection
   kind="reset"
   version="19.1"
   start="cpu.debug_reset_request"
   end="sys_clk_timer.reset" />
 <connection
   kind="reset"
   version="19.1"
   start="cpu.debug_reset_request"
   end="sysid.reset" />
 <connection
   kind="reset"
   version="19.1"
   start="cpu.debug_reset_request"
   end="output_pio.reset" />
 <connection
   kind="reset"
   version="19.1"
   start="cpu.debug_reset_request"
   end="descriptor_memory.reset1" />
 <connection
   kind="reset"
   version="19.1"
   start="cpu.debug_reset_request"
   end="eth_tse.reset_connection" />
 <connection
   kind="reset"
   version="19.1"
   start="cpu.debug_reset_request"
   end="ddr3_ram.soft_reset" />
 <connection
   kind="reset"
   version="19.1"
   start="ddr3_ram_resetn.out_reset"
   end="ddr3_ram.global_reset" />
 <connection
   kind="reset"
   version="19.1"
   start="ddr3_ram_resetn.out_reset"
   end="altpll_shift.inclk_interface_reset" />
 <connection
   kind="reset"
   version="19.1"
   start="ddr3_ram_resetn.out_reset"
   end="enet_pll.inclk_interface_reset" />
 <connection
   kind="reset"
   version="19.1"
   start="ddr3_ram_resetn.out_reset"
   end="ddr3_ram.soft_reset" />
 <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
 <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="0" />
</system>
